wangxinze/Verilog_data · Datasets at Hugging Face

module_content stringlengths 18 1.05M
module fifo_4k_a_gray2bin_9m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [11:0] bin; input [11:0] gray; wire xor0; wire xor1; wire xor10; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor10 = (gray[11] ^ gray[10]), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[9] ^ xor10); endmodule
module fifo_4k_a_graycounter_826 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_a_graycounter_3r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_altsyncram_8pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [11:0] address_a; input [11:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [11:0] address_a_wire; wire [11:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 12, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 4095, ram_block3a_0.port_a_logical_ram_depth = 4096, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 12, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 4095, ram_block3a_0.port_b_logical_ram_depth = 4096, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 12, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 4095, ram_block3a_1.port_a_logical_ram_depth = 4096, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 12, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 4095, ram_block3a_1.port_b_logical_ram_depth = 4096, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 12, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 4095, ram_block3a_2.port_a_logical_ram_depth = 4096, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 12, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 4095, ram_block3a_2.port_b_logical_ram_depth = 4096, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 12, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 4095, ram_block3a_3.port_a_logical_ram_depth = 4096, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 12, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 4095, ram_block3a_3.port_b_logical_ram_depth = 4096, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 12, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 4095, ram_block3a_4.port_a_logical_ram_depth = 4096, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 12, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 4095, ram_block3a_4.port_b_logical_ram_depth = 4096, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 12, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 4095, ram_block3a_5.port_a_logical_ram_depth = 4096, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 12, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 4095, ram_block3a_5.port_b_logical_ram_depth = 4096, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 12, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 4095, ram_block3a_6.port_a_logical_ram_depth = 4096, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 12, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 4095, ram_block3a_6.port_b_logical_ram_depth = 4096, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 12, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 4095, ram_block3a_7.port_a_logical_ram_depth = 4096, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 12, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 4095, ram_block3a_7.port_b_logical_ram_depth = 4096, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 12, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 4095, ram_block3a_8.port_a_logical_ram_depth = 4096, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 12, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 4095, ram_block3a_8.port_b_logical_ram_depth = 4096, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 12, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 4095, ram_block3a_9.port_a_logical_ram_depth = 4096, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 12, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 4095, ram_block3a_9.port_b_logical_ram_depth = 4096, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 12, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 4095, ram_block3a_10.port_a_logical_ram_depth = 4096, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 12, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 4095, ram_block3a_10.port_b_logical_ram_depth = 4096, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 12, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 4095, ram_block3a_11.port_a_logical_ram_depth = 4096, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 12, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 4095, ram_block3a_11.port_b_logical_ram_depth = 4096, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 12, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 4095, ram_block3a_12.port_a_logical_ram_depth = 4096, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 12, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 4095, ram_block3a_12.port_b_logical_ram_depth = 4096, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 12, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 4095, ram_block3a_13.port_a_logical_ram_depth = 4096, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 12, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 4095, ram_block3a_13.port_b_logical_ram_depth = 4096, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 12, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 4095, ram_block3a_14.port_a_logical_ram_depth = 4096, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 12, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 4095, ram_block3a_14.port_b_logical_ram_depth = 4096, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 12, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 4095, ram_block3a_15.port_a_logical_ram_depth = 4096, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 12, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 4095, ram_block3a_15.port_b_logical_ram_depth = 4096, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule
module fifo_4k_dffpipe_bb3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe4a_D; reg [11:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; // synopsys translate_off initial dffe4a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; assign wire_dffe4a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule
module fifo_4k_dffpipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe6a_D; reg [11:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; // synopsys translate_off initial dffe6a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; assign wire_dffe6a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule
module fifo_4k_alt_synch_pipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffpipe5_q; fifo_4k_dffpipe_em2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule
module fifo_4k_add_sub_b18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [11:0] dataa; input [11:0] datab; output [11:0] result; wire [11:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [0:0] wire_add_sub_cella_10cout; wire [11:0] wire_add_sub_cella_dataa; wire [11:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(wire_add_sub_cella_10cout[0:0]), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "69b2", add_sub_cella_10.operation_mode = "arithmetic", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_11 ( .cin(wire_add_sub_cella_10cout[0:0]), .combout(wire_add_sub_cella_combout[11:11]), .cout(), .dataa(wire_add_sub_cella_dataa[11:11]), .datab(wire_add_sub_cella_datab[11:11]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_11.cin_used = "true", add_sub_cella_11.lut_mask = "6969", add_sub_cella_11.operation_mode = "normal", add_sub_cella_11.sum_lutc_input = "cin", add_sub_cella_11.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule
module fifo_4k_dcfifo_6cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g\|power_modified_counter_values\" -to \"ws_dgrp\|dffpipe5\|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp\|dffpipe5\|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [11:0] rdusedw; input wrclk; output wrfull; input wrreq; output [11:0] wrusedw; wire [11:0] wire_rdptr_g_gray2bin_bin; wire [11:0] wire_rs_dgwp_gray2bin_bin; wire [11:0] wire_wrptr_g_gray2bin_bin; wire [11:0] wire_ws_dgrp_gray2bin_bin; wire [11:0] wire_rdptr_g_q; wire [11:0] wire_rdptr_g1p_q; wire [11:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [11:0] delayed_wrptr_g; reg [11:0] wrptr_g; wire [11:0] wire_rs_brp_q; wire [11:0] wire_rs_bwp_q; wire [11:0] wire_rs_dgwp_q; wire [11:0] wire_ws_brp_q; wire [11:0] wire_ws_bwp_q; wire [11:0] wire_ws_dgrp_q; wire [11:0] wire_rdusedw_sub_result; wire [11:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [11:0] wire_rdempty_eq_comp_dataa; wire [11:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [11:0] wire_wrfull_eq_comp_dataa; wire [11:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_4k_a_graycounter_826 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_4k_a_graycounter_3r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_4k_a_graycounter_3r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_4k_altsyncram_8pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) \| (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq \| int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 12'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_4k_dffpipe_bb3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_4k_dffpipe_bb3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_4k_alt_synch_pipe_em2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_4k_dffpipe_bb3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_4k_dffpipe_bb3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_4k_alt_synch_pipe_em2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_4k_add_sub_b18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_4k_add_sub_b18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule
module fifo_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [11:0] rdusedw; output wrfull; output [11:0] wrusedw; wire sub_wire0; wire [11:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [11:0] sub_wire4; wire rdempty = sub_wire0; wire [11:0] wrusedw = sub_wire1[11:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [11:0] rdusedw = sub_wire4[11:0]; fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule
module fifo_4k_a_gray2bin_9m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [11:0] bin; input [11:0] gray; wire xor0; wire xor1; wire xor10; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor10 = (gray[11] ^ gray[10]), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[9] ^ xor10); endmodule
module fifo_4k_a_graycounter_826 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_a_graycounter_3r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_altsyncram_8pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [11:0] address_a; input [11:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [11:0] address_a_wire; wire [11:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 12, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 4095, ram_block3a_0.port_a_logical_ram_depth = 4096, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 12, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 4095, ram_block3a_0.port_b_logical_ram_depth = 4096, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 12, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 4095, ram_block3a_1.port_a_logical_ram_depth = 4096, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 12, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 4095, ram_block3a_1.port_b_logical_ram_depth = 4096, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 12, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 4095, ram_block3a_2.port_a_logical_ram_depth = 4096, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 12, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 4095, ram_block3a_2.port_b_logical_ram_depth = 4096, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 12, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 4095, ram_block3a_3.port_a_logical_ram_depth = 4096, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 12, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 4095, ram_block3a_3.port_b_logical_ram_depth = 4096, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 12, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 4095, ram_block3a_4.port_a_logical_ram_depth = 4096, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 12, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 4095, ram_block3a_4.port_b_logical_ram_depth = 4096, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 12, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 4095, ram_block3a_5.port_a_logical_ram_depth = 4096, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 12, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 4095, ram_block3a_5.port_b_logical_ram_depth = 4096, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 12, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 4095, ram_block3a_6.port_a_logical_ram_depth = 4096, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 12, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 4095, ram_block3a_6.port_b_logical_ram_depth = 4096, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 12, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 4095, ram_block3a_7.port_a_logical_ram_depth = 4096, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 12, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 4095, ram_block3a_7.port_b_logical_ram_depth = 4096, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 12, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 4095, ram_block3a_8.port_a_logical_ram_depth = 4096, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 12, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 4095, ram_block3a_8.port_b_logical_ram_depth = 4096, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 12, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 4095, ram_block3a_9.port_a_logical_ram_depth = 4096, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 12, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 4095, ram_block3a_9.port_b_logical_ram_depth = 4096, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 12, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 4095, ram_block3a_10.port_a_logical_ram_depth = 4096, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 12, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 4095, ram_block3a_10.port_b_logical_ram_depth = 4096, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 12, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 4095, ram_block3a_11.port_a_logical_ram_depth = 4096, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 12, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 4095, ram_block3a_11.port_b_logical_ram_depth = 4096, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 12, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 4095, ram_block3a_12.port_a_logical_ram_depth = 4096, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 12, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 4095, ram_block3a_12.port_b_logical_ram_depth = 4096, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 12, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 4095, ram_block3a_13.port_a_logical_ram_depth = 4096, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 12, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 4095, ram_block3a_13.port_b_logical_ram_depth = 4096, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 12, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 4095, ram_block3a_14.port_a_logical_ram_depth = 4096, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 12, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 4095, ram_block3a_14.port_b_logical_ram_depth = 4096, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 12, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 4095, ram_block3a_15.port_a_logical_ram_depth = 4096, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 12, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 4095, ram_block3a_15.port_b_logical_ram_depth = 4096, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule
module fifo_4k_dffpipe_bb3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe4a_D; reg [11:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; // synopsys translate_off initial dffe4a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; assign wire_dffe4a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule
module fifo_4k_dffpipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe6a_D; reg [11:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; // synopsys translate_off initial dffe6a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; assign wire_dffe6a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule
module fifo_4k_alt_synch_pipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffpipe5_q; fifo_4k_dffpipe_em2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule
module fifo_4k_add_sub_b18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [11:0] dataa; input [11:0] datab; output [11:0] result; wire [11:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [0:0] wire_add_sub_cella_10cout; wire [11:0] wire_add_sub_cella_dataa; wire [11:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(wire_add_sub_cella_10cout[0:0]), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "69b2", add_sub_cella_10.operation_mode = "arithmetic", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_11 ( .cin(wire_add_sub_cella_10cout[0:0]), .combout(wire_add_sub_cella_combout[11:11]), .cout(), .dataa(wire_add_sub_cella_dataa[11:11]), .datab(wire_add_sub_cella_datab[11:11]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_11.cin_used = "true", add_sub_cella_11.lut_mask = "6969", add_sub_cella_11.operation_mode = "normal", add_sub_cella_11.sum_lutc_input = "cin", add_sub_cella_11.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule
module fifo_4k_dcfifo_6cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g\|power_modified_counter_values\" -to \"ws_dgrp\|dffpipe5\|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp\|dffpipe5\|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [11:0] rdusedw; input wrclk; output wrfull; input wrreq; output [11:0] wrusedw; wire [11:0] wire_rdptr_g_gray2bin_bin; wire [11:0] wire_rs_dgwp_gray2bin_bin; wire [11:0] wire_wrptr_g_gray2bin_bin; wire [11:0] wire_ws_dgrp_gray2bin_bin; wire [11:0] wire_rdptr_g_q; wire [11:0] wire_rdptr_g1p_q; wire [11:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [11:0] delayed_wrptr_g; reg [11:0] wrptr_g; wire [11:0] wire_rs_brp_q; wire [11:0] wire_rs_bwp_q; wire [11:0] wire_rs_dgwp_q; wire [11:0] wire_ws_brp_q; wire [11:0] wire_ws_bwp_q; wire [11:0] wire_ws_dgrp_q; wire [11:0] wire_rdusedw_sub_result; wire [11:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [11:0] wire_rdempty_eq_comp_dataa; wire [11:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [11:0] wire_wrfull_eq_comp_dataa; wire [11:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_4k_a_graycounter_826 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_4k_a_graycounter_3r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_4k_a_graycounter_3r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_4k_altsyncram_8pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) \| (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq \| int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 12'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_4k_dffpipe_bb3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_4k_dffpipe_bb3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_4k_alt_synch_pipe_em2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_4k_dffpipe_bb3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_4k_dffpipe_bb3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_4k_alt_synch_pipe_em2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_4k_add_sub_b18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_4k_add_sub_b18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule
module fifo_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [11:0] rdusedw; output wrfull; output [11:0] wrusedw; wire sub_wire0; wire [11:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [11:0] sub_wire4; wire rdempty = sub_wire0; wire [11:0] wrusedw = sub_wire1[11:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [11:0] rdusedw = sub_wire4[11:0]; fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule
module fifo_4k_a_gray2bin_9m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [11:0] bin; input [11:0] gray; wire xor0; wire xor1; wire xor10; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor10 = (gray[11] ^ gray[10]), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[9] ^ xor10); endmodule
module fifo_4k_a_graycounter_826 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_a_graycounter_3r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_altsyncram_8pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [11:0] address_a; input [11:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [11:0] address_a_wire; wire [11:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 12, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 4095, ram_block3a_0.port_a_logical_ram_depth = 4096, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 12, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 4095, ram_block3a_0.port_b_logical_ram_depth = 4096, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 12, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 4095, ram_block3a_1.port_a_logical_ram_depth = 4096, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 12, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 4095, ram_block3a_1.port_b_logical_ram_depth = 4096, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 12, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 4095, ram_block3a_2.port_a_logical_ram_depth = 4096, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 12, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 4095, ram_block3a_2.port_b_logical_ram_depth = 4096, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 12, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 4095, ram_block3a_3.port_a_logical_ram_depth = 4096, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 12, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 4095, ram_block3a_3.port_b_logical_ram_depth = 4096, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 12, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 4095, ram_block3a_4.port_a_logical_ram_depth = 4096, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 12, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 4095, ram_block3a_4.port_b_logical_ram_depth = 4096, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 12, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 4095, ram_block3a_5.port_a_logical_ram_depth = 4096, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 12, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 4095, ram_block3a_5.port_b_logical_ram_depth = 4096, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 12, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 4095, ram_block3a_6.port_a_logical_ram_depth = 4096, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 12, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 4095, ram_block3a_6.port_b_logical_ram_depth = 4096, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 12, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 4095, ram_block3a_7.port_a_logical_ram_depth = 4096, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 12, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 4095, ram_block3a_7.port_b_logical_ram_depth = 4096, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 12, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 4095, ram_block3a_8.port_a_logical_ram_depth = 4096, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 12, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 4095, ram_block3a_8.port_b_logical_ram_depth = 4096, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 12, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 4095, ram_block3a_9.port_a_logical_ram_depth = 4096, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 12, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 4095, ram_block3a_9.port_b_logical_ram_depth = 4096, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 12, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 4095, ram_block3a_10.port_a_logical_ram_depth = 4096, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 12, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 4095, ram_block3a_10.port_b_logical_ram_depth = 4096, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 12, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 4095, ram_block3a_11.port_a_logical_ram_depth = 4096, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 12, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 4095, ram_block3a_11.port_b_logical_ram_depth = 4096, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 12, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 4095, ram_block3a_12.port_a_logical_ram_depth = 4096, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 12, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 4095, ram_block3a_12.port_b_logical_ram_depth = 4096, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 12, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 4095, ram_block3a_13.port_a_logical_ram_depth = 4096, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 12, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 4095, ram_block3a_13.port_b_logical_ram_depth = 4096, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 12, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 4095, ram_block3a_14.port_a_logical_ram_depth = 4096, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 12, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 4095, ram_block3a_14.port_b_logical_ram_depth = 4096, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 12, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 4095, ram_block3a_15.port_a_logical_ram_depth = 4096, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 12, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 4095, ram_block3a_15.port_b_logical_ram_depth = 4096, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule
module fifo_4k_dffpipe_bb3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe4a_D; reg [11:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; // synopsys translate_off initial dffe4a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; assign wire_dffe4a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule
module fifo_4k_dffpipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe6a_D; reg [11:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; // synopsys translate_off initial dffe6a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; assign wire_dffe6a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule
module fifo_4k_alt_synch_pipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffpipe5_q; fifo_4k_dffpipe_em2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule
module fifo_4k_add_sub_b18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [11:0] dataa; input [11:0] datab; output [11:0] result; wire [11:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [0:0] wire_add_sub_cella_10cout; wire [11:0] wire_add_sub_cella_dataa; wire [11:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(wire_add_sub_cella_10cout[0:0]), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "69b2", add_sub_cella_10.operation_mode = "arithmetic", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_11 ( .cin(wire_add_sub_cella_10cout[0:0]), .combout(wire_add_sub_cella_combout[11:11]), .cout(), .dataa(wire_add_sub_cella_dataa[11:11]), .datab(wire_add_sub_cella_datab[11:11]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_11.cin_used = "true", add_sub_cella_11.lut_mask = "6969", add_sub_cella_11.operation_mode = "normal", add_sub_cella_11.sum_lutc_input = "cin", add_sub_cella_11.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule
module fifo_4k_dcfifo_6cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g\|power_modified_counter_values\" -to \"ws_dgrp\|dffpipe5\|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp\|dffpipe5\|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [11:0] rdusedw; input wrclk; output wrfull; input wrreq; output [11:0] wrusedw; wire [11:0] wire_rdptr_g_gray2bin_bin; wire [11:0] wire_rs_dgwp_gray2bin_bin; wire [11:0] wire_wrptr_g_gray2bin_bin; wire [11:0] wire_ws_dgrp_gray2bin_bin; wire [11:0] wire_rdptr_g_q; wire [11:0] wire_rdptr_g1p_q; wire [11:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [11:0] delayed_wrptr_g; reg [11:0] wrptr_g; wire [11:0] wire_rs_brp_q; wire [11:0] wire_rs_bwp_q; wire [11:0] wire_rs_dgwp_q; wire [11:0] wire_ws_brp_q; wire [11:0] wire_ws_bwp_q; wire [11:0] wire_ws_dgrp_q; wire [11:0] wire_rdusedw_sub_result; wire [11:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [11:0] wire_rdempty_eq_comp_dataa; wire [11:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [11:0] wire_wrfull_eq_comp_dataa; wire [11:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_4k_a_graycounter_826 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_4k_a_graycounter_3r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_4k_a_graycounter_3r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_4k_altsyncram_8pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) \| (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq \| int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 12'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_4k_dffpipe_bb3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_4k_dffpipe_bb3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_4k_alt_synch_pipe_em2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_4k_dffpipe_bb3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_4k_dffpipe_bb3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_4k_alt_synch_pipe_em2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_4k_add_sub_b18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_4k_add_sub_b18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule
module fifo_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [11:0] rdusedw; output wrfull; output [11:0] wrusedw; wire sub_wire0; wire [11:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [11:0] sub_wire4; wire rdempty = sub_wire0; wire [11:0] wrusedw = sub_wire1[11:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [11:0] rdusedw = sub_wire4[11:0]; fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule
module fifo_4k_a_gray2bin_9m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [11:0] bin; input [11:0] gray; wire xor0; wire xor1; wire xor10; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor10 = (gray[11] ^ gray[10]), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[9] ^ xor10); endmodule
module fifo_4k_a_graycounter_826 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_a_graycounter_3r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule
module fifo_4k_altsyncram_8pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [11:0] address_a; input [11:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [11:0] address_a_wire; wire [11:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 12, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 4095, ram_block3a_0.port_a_logical_ram_depth = 4096, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 12, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 4095, ram_block3a_0.port_b_logical_ram_depth = 4096, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 12, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 4095, ram_block3a_1.port_a_logical_ram_depth = 4096, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 12, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 4095, ram_block3a_1.port_b_logical_ram_depth = 4096, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 12, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 4095, ram_block3a_2.port_a_logical_ram_depth = 4096, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 12, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 4095, ram_block3a_2.port_b_logical_ram_depth = 4096, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 12, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 4095, ram_block3a_3.port_a_logical_ram_depth = 4096, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 12, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 4095, ram_block3a_3.port_b_logical_ram_depth = 4096, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 12, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 4095, ram_block3a_4.port_a_logical_ram_depth = 4096, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 12, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 4095, ram_block3a_4.port_b_logical_ram_depth = 4096, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 12, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 4095, ram_block3a_5.port_a_logical_ram_depth = 4096, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 12, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 4095, ram_block3a_5.port_b_logical_ram_depth = 4096, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 12, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 4095, ram_block3a_6.port_a_logical_ram_depth = 4096, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 12, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 4095, ram_block3a_6.port_b_logical_ram_depth = 4096, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 12, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 4095, ram_block3a_7.port_a_logical_ram_depth = 4096, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 12, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 4095, ram_block3a_7.port_b_logical_ram_depth = 4096, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 12, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 4095, ram_block3a_8.port_a_logical_ram_depth = 4096, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 12, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 4095, ram_block3a_8.port_b_logical_ram_depth = 4096, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 12, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 4095, ram_block3a_9.port_a_logical_ram_depth = 4096, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 12, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 4095, ram_block3a_9.port_b_logical_ram_depth = 4096, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 12, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 4095, ram_block3a_10.port_a_logical_ram_depth = 4096, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 12, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 4095, ram_block3a_10.port_b_logical_ram_depth = 4096, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 12, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 4095, ram_block3a_11.port_a_logical_ram_depth = 4096, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 12, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 4095, ram_block3a_11.port_b_logical_ram_depth = 4096, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 12, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 4095, ram_block3a_12.port_a_logical_ram_depth = 4096, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 12, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 4095, ram_block3a_12.port_b_logical_ram_depth = 4096, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 12, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 4095, ram_block3a_13.port_a_logical_ram_depth = 4096, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 12, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 4095, ram_block3a_13.port_b_logical_ram_depth = 4096, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 12, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 4095, ram_block3a_14.port_a_logical_ram_depth = 4096, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 12, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 4095, ram_block3a_14.port_b_logical_ram_depth = 4096, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 12, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 4095, ram_block3a_15.port_a_logical_ram_depth = 4096, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 12, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 4095, ram_block3a_15.port_b_logical_ram_depth = 4096, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule
module fifo_4k_dffpipe_bb3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe4a_D; reg [11:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; // synopsys translate_off initial dffe4a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; assign wire_dffe4a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule
module fifo_4k_dffpipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe6a_D; reg [11:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; // synopsys translate_off initial dffe6a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; assign wire_dffe6a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule
module fifo_4k_alt_synch_pipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffpipe5_q; fifo_4k_dffpipe_em2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule
module fifo_4k_add_sub_b18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [11:0] dataa; input [11:0] datab; output [11:0] result; wire [11:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [0:0] wire_add_sub_cella_10cout; wire [11:0] wire_add_sub_cella_dataa; wire [11:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(wire_add_sub_cella_10cout[0:0]), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "69b2", add_sub_cella_10.operation_mode = "arithmetic", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_11 ( .cin(wire_add_sub_cella_10cout[0:0]), .combout(wire_add_sub_cella_combout[11:11]), .cout(), .dataa(wire_add_sub_cella_dataa[11:11]), .datab(wire_add_sub_cella_datab[11:11]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_11.cin_used = "true", add_sub_cella_11.lut_mask = "6969", add_sub_cella_11.operation_mode = "normal", add_sub_cella_11.sum_lutc_input = "cin", add_sub_cella_11.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule
module fifo_4k_dcfifo_6cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 / / synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g\|power_modified_counter_values\" -to \"ws_dgrp\|dffpipe5\|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp\|dffpipe5\|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [11:0] rdusedw; input wrclk; output wrfull; input wrreq; output [11:0] wrusedw; wire [11:0] wire_rdptr_g_gray2bin_bin; wire [11:0] wire_rs_dgwp_gray2bin_bin; wire [11:0] wire_wrptr_g_gray2bin_bin; wire [11:0] wire_ws_dgrp_gray2bin_bin; wire [11:0] wire_rdptr_g_q; wire [11:0] wire_rdptr_g1p_q; wire [11:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [11:0] delayed_wrptr_g; reg [11:0] wrptr_g; wire [11:0] wire_rs_brp_q; wire [11:0] wire_rs_bwp_q; wire [11:0] wire_rs_dgwp_q; wire [11:0] wire_ws_brp_q; wire [11:0] wire_ws_bwp_q; wire [11:0] wire_ws_dgrp_q; wire [11:0] wire_rdusedw_sub_result; wire [11:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [11:0] wire_rdempty_eq_comp_dataa; wire [11:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [11:0] wire_wrfull_eq_comp_dataa; wire [11:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_4k_a_graycounter_826 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_4k_a_graycounter_3r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_4k_a_graycounter_3r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_4k_altsyncram_8pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) \| (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq \| int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 12'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_4k_dffpipe_bb3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_4k_dffpipe_bb3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_4k_alt_synch_pipe_em2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_4k_dffpipe_bb3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_4k_dffpipe_bb3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_4k_alt_synch_pipe_em2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_4k_add_sub_b18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_4k_add_sub_b18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule
module fifo_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [11:0] rdusedw; output wrfull; output [11:0] wrusedw; wire sub_wire0; wire [11:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [11:0] sub_wire4; wire rdempty = sub_wire0; wire [11:0] wrusedw = sub_wire1[11:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [11:0] rdusedw = sub_wire4[11:0]; fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule
module axi_crossbar_v2_1_wdata_mux # ( parameter C_FAMILY = "none", // FPGA Family. parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports. parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT. parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2*C_FIFO_DEPTH_LOG. ) ( // System Signals input wire ACLK, input wire ARESET, // Slave Data Ports input wire [C_NUM_SLAVE_SLOTSC_WMESG_WIDTH-1:0] S_WMESG, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY, // Master Data Ports output wire [C_WMESG_WIDTH-1:0] M_WMESG, output wire M_WLAST, output wire M_WVALID, input wire M_WREADY, // Write Command Ports input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter input wire S_AVALID, output wire S_AREADY ); localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32 // Decode select input to 1-hot function [C_NUM_SLAVE_SLOTS-1:0] f_decoder ( input [C_SELECT_WIDTH-1:0] sel ); integer i; begin for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin f_decoder[i] = (sel == i); end end endfunction wire m_valid_i; wire m_last_i; wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot; wire [C_SELECT_WIDTH-1:0] m_select_enc; wire m_avalid; wire m_aready; generate if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI-side write command queue axi_data_fifo_v2_1_axic_reg_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (C_SELECT_WIDTH), .C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG), .C_USE_FULL (0) ) wmux_aw_fifo ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (S_ASELECT), .S_VALID (S_AVALID), .S_READY (S_AREADY), .M_MESG (m_select_enc), .M_VALID (m_avalid), .M_READY (m_aready) ); assign m_select_hot = f_decoder(m_select_enc); // Instantiate MUX generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (C_SELECT_WIDTH), .C_DATA_WIDTH (C_WMESG_WIDTH) ) mux_w ( .S (m_select_enc), .A (S_WMESG), .O (M_WMESG), .OE (1'b1) ); assign m_last_i = \|(S_WLAST & m_select_hot); assign m_valid_i = \|(S_WVALID & m_select_hot); assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY; assign M_WLAST = m_last_i; assign M_WVALID = m_valid_i & m_avalid; assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}}; end else begin : gen_no_wmux assign S_AREADY = 1'b1; assign M_WVALID = S_WVALID; assign S_WREADY = M_WREADY; assign M_WLAST = S_WLAST; assign M_WMESG = S_WMESG; end endgenerate endmodule
module axi_crossbar_v2_1_wdata_mux # ( parameter C_FAMILY = "none", // FPGA Family. parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports. parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT. parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2*C_FIFO_DEPTH_LOG. ) ( // System Signals input wire ACLK, input wire ARESET, // Slave Data Ports input wire [C_NUM_SLAVE_SLOTSC_WMESG_WIDTH-1:0] S_WMESG, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY, // Master Data Ports output wire [C_WMESG_WIDTH-1:0] M_WMESG, output wire M_WLAST, output wire M_WVALID, input wire M_WREADY, // Write Command Ports input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter input wire S_AVALID, output wire S_AREADY ); localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32 // Decode select input to 1-hot function [C_NUM_SLAVE_SLOTS-1:0] f_decoder ( input [C_SELECT_WIDTH-1:0] sel ); integer i; begin for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin f_decoder[i] = (sel == i); end end endfunction wire m_valid_i; wire m_last_i; wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot; wire [C_SELECT_WIDTH-1:0] m_select_enc; wire m_avalid; wire m_aready; generate if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI-side write command queue axi_data_fifo_v2_1_axic_reg_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (C_SELECT_WIDTH), .C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG), .C_USE_FULL (0) ) wmux_aw_fifo ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (S_ASELECT), .S_VALID (S_AVALID), .S_READY (S_AREADY), .M_MESG (m_select_enc), .M_VALID (m_avalid), .M_READY (m_aready) ); assign m_select_hot = f_decoder(m_select_enc); // Instantiate MUX generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (C_SELECT_WIDTH), .C_DATA_WIDTH (C_WMESG_WIDTH) ) mux_w ( .S (m_select_enc), .A (S_WMESG), .O (M_WMESG), .OE (1'b1) ); assign m_last_i = \|(S_WLAST & m_select_hot); assign m_valid_i = \|(S_WVALID & m_select_hot); assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY; assign M_WLAST = m_last_i; assign M_WVALID = m_valid_i & m_avalid; assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}}; end else begin : gen_no_wmux assign S_AREADY = 1'b1; assign M_WVALID = S_WVALID; assign S_WREADY = M_WREADY; assign M_WLAST = S_WLAST; assign M_WMESG = S_WMESG; end endgenerate endmodule
module axi_crossbar_v2_1_wdata_mux # ( parameter C_FAMILY = "none", // FPGA Family. parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports. parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT. parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2*C_FIFO_DEPTH_LOG. ) ( // System Signals input wire ACLK, input wire ARESET, // Slave Data Ports input wire [C_NUM_SLAVE_SLOTSC_WMESG_WIDTH-1:0] S_WMESG, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST, input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID, output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY, // Master Data Ports output wire [C_WMESG_WIDTH-1:0] M_WMESG, output wire M_WLAST, output wire M_WVALID, input wire M_WREADY, // Write Command Ports input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter input wire S_AVALID, output wire S_AREADY ); localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32 // Decode select input to 1-hot function [C_NUM_SLAVE_SLOTS-1:0] f_decoder ( input [C_SELECT_WIDTH-1:0] sel ); integer i; begin for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin f_decoder[i] = (sel == i); end end endfunction wire m_valid_i; wire m_last_i; wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot; wire [C_SELECT_WIDTH-1:0] m_select_enc; wire m_avalid; wire m_aready; generate if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux // SI-side write command queue axi_data_fifo_v2_1_axic_reg_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (C_SELECT_WIDTH), .C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG), .C_USE_FULL (0) ) wmux_aw_fifo ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (S_ASELECT), .S_VALID (S_AVALID), .S_READY (S_AREADY), .M_MESG (m_select_enc), .M_VALID (m_avalid), .M_READY (m_aready) ); assign m_select_hot = f_decoder(m_select_enc); // Instantiate MUX generic_baseblocks_v2_1_mux_enc # ( .C_FAMILY ("rtl"), .C_RATIO (C_NUM_SLAVE_SLOTS), .C_SEL_WIDTH (C_SELECT_WIDTH), .C_DATA_WIDTH (C_WMESG_WIDTH) ) mux_w ( .S (m_select_enc), .A (S_WMESG), .O (M_WMESG), .OE (1'b1) ); assign m_last_i = \|(S_WLAST & m_select_hot); assign m_valid_i = \|(S_WVALID & m_select_hot); assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY; assign M_WLAST = m_last_i; assign M_WVALID = m_valid_i & m_avalid; assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}}; end else begin : gen_no_wmux assign S_AREADY = 1'b1; assign M_WVALID = S_WVALID; assign S_WREADY = M_WREADY; assign M_WLAST = S_WLAST; assign M_WMESG = S_WMESG; end endgenerate endmodule
module axi_crossbar_v2_1_axi_crossbar # ( parameter C_FAMILY = "rtl", // FPGA Base Family. Current version: virtex6 or spartan6. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of Slave Interface (SI) slots for connecting // to master IP. Range: 1-16. parameter integer C_NUM_MASTER_SLOTS = 2, // Number of Master Interface (MI) slots for connecting // to slave IP. Range: 1-16. parameter integer C_AXI_ID_WIDTH = 1, // Width of ID signals propagated by the Interconnect. // Width of ID signals produced on all MI slots. // Range: 1-32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and // m_axi_araddr for all SI/MI slots. // Range: 1-64. parameter integer C_AXI_DATA_WIDTH = 32, // Data width of the internal interconnect write and read // data paths. // Range: 32, 64, 128, 256, 512, 1024. parameter integer C_AXI_PROTOCOL = 0, // 0 = "AXI4", // 1 = "AXI3", // 2 = "AXI4LITE" // Propagate WID only when C_AXI_PROTOCOL = 1. parameter integer C_NUM_ADDR_RANGES = 1, // Number of BASE/HIGH_ADDR pairs per MI slot. // Range: 1-16. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000, // Base address of each range of each MI slot. // For unused ranges, set C_M_AXI_BASE_ADDR[mmaa64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. // (Bit positions above C_AXI_ADDR_WIDTH are ignored.) // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, // Number of low-order address bits that are used to select locations within each address range of each MI slot. // The High address of each range is derived as BASE_ADDR + 2*C_M_AXI_ADDR_WIDTH -1. // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0. // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000. // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}. // Range: 0 - C_AXI_ADDR_WIDTH. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_BASE_ID = 32'h00000000, // Base ID of each SI slot. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 to 2*C_AXI_ID_WIDTH-1. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000, // Number of low-order ID bits a connected master may vary to select a transaction thread. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 - C_AXI_ID_WIDTH. parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway write connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway read connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter integer C_R_REGISTER = 0, // Insert register slice on R channel in the crossbar. (Valid only for SASD) // Range: Reg-slice type (0-8). parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000, // 0 = Implement separate command queues per ID thread. // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0, 1 parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002, // Maximum number of active write transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002, // Maximum number of active read transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004, // Maximum number of data-active write transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004, // Maximum number of active read transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000, // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0-15. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_SECURE = 32'h00000000, // Indicates whether each MI slot connects to a secure slave // (allows only TrustZone secure access). // Format: C_NUM_MASTER_SLOTS{Bit32}. // Range: 0, 1 parameter integer C_CONNECTIVITY_MODE = 1 // 0 = Shared-Address Shared-Data (SASD). // 1 = Shared-Address Multi-Data (SAMD). // Default 1 (on) for simulation; default 0 (off) for implementation. ) ( // Global Signals input wire aclk, input wire aresetn, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_awburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast, input wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_bresp, output wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] s_axi_buser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_arburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_rresp, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast, output wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_awburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awqos, output wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast, output wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_bresp, input wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] m_axi_buser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_arburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arqos, output wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_rresp, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast, input wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready ); localparam [64:0] P_ONES = {65{1'b1}}; localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_BASE_ID = f_base_id(0); localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_HIGH_ID = f_high_id(0); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam [2:0] P_AXILITE_SIZE = 3'b010; localparam [1:0] P_INCR = 2'b01; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0); localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0); localparam integer C_DEBUG = 1; localparam integer P_RANGE_CHECK = 1; // 1 (non-zero) = Detect and issue DECERR on the following conditions: // a. address range mismatch (no valid MI slot) // b. Burst or >32-bit transfer to AxiLite slave // c. TrustZone access violation // d. R/W direction unsupported by target // 0 = Pass all transactions (no DECERR): // a. Omit DECERR detection and response logic // b. Omit address decoder and propagate s_axi_aREGION to m_axi_aREGION // when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1. // c. Unpredictable target MI-slot if address mismatch and >1 MI-slot // d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0. localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) \|\| (C_NUM_MASTER_SLOTS > 1) \|\| (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1 localparam [C_NUM_MASTER_SLOTS32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}; // Transaction error detection (per MI-slot) // 0 = None; 1 = AXI4Lite burst violation // Format: C_NUM_MASTER_SLOTS{Bit32}; localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8; localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1; localparam P_FAMILY = ((C_FAMILY == "virtex7") \|\| (C_FAMILY == "kintex7") \|\| (C_FAMILY == "artix7") \|\| (C_FAMILY == "zynq")) ? C_FAMILY : "rtl"; function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2*acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_write_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_write_issue_width_vec = result; end endfunction // Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_read_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_read_issue_width_vec = result; end endfunction // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_write_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si32+:32]); end f_write_accept_width_vec = result; end endfunction // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_read_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si32+:32]); end f_read_accept_width_vec = result; end endfunction // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format function [C_NUM_SLAVE_SLOTS64-1:0] f_base_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH]; end f_base_id = result; end endfunction // Construct P_S_HIGH_ID vector function [C_NUM_SLAVE_SLOTS64-1:0] f_high_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end f_high_id = result; end endfunction // Construct P_M_HIGH_ADDR vector function [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] f_high_addr (input null_arg); integer ar; reg [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] result; begin result = {C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64{1'b0}}; for (ar=0; ar<C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES; ar=ar+1) begin result[ar64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar32+:32] == 0) ? 64'h00000000_00000000 : ({1'b0, C_M_AXI_ADDR_WIDTH[ar32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} : (C_M_AXI_BASE_ADDR[ar64+:C_AXI_ADDR_WIDTH] \| ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar32+:7]})); end f_high_addr = result; end endfunction // Generate a mask of valid ID bits for a given SI slot. function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask (input integer si); begin f_thread_id_mask = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : ({C_AXI_ID_WIDTH{1'b0}} \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end endfunction // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer si ); begin f_extend_ID = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? s_id : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]}))); end endfunction // Bit vector of SI slots with at least one write connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_write = result; end endfunction // Bit vector of SI slots with at least one read connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_read = result; end endfunction // Bit vector of MI slots with at least one write connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_write[mi] = (\|C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction // Bit vector of MI slots with at least one read connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_read[mi] = (\|C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_awid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_awlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_wid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_wdata ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] si_cb_wuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_bid ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_bresp ; wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] si_cb_buser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_arid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_araddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_arlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_rid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_rdata ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_rresp ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] si_cb_ruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_awid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_awlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awqos ; wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_wid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_wdata ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ; wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_bid ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_bresp ; wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] cb_mi_buser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_arid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_arlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arqos ; wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_rid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_rdata ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_rresp ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ; wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ; genvar slot; generate for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff assign si_cb_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_awlen[slot8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_awsize[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_awburst[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot2+:2] : P_INCR ; assign si_cb_awlock[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slotP_LOCK+:1]} : 0 ; assign si_cb_awcache[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot4+:4] : 0 ; assign si_cb_awprot[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot3+:3] : 0 ; assign si_cb_awqos[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot4+:4] : 0 ; // assign si_cb_awregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot4+:4] : 0 ; assign si_cb_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign si_cb_awvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot1+:1] : 0 ; assign si_cb_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign si_cb_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign si_cb_wlast[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot1+:1] : 1'b1 ; assign si_cb_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign si_cb_wvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot1+:1] : 0 ; assign si_cb_bready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot1+:1] : 0 ; assign si_cb_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_arlen[slot8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_arsize[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_arburst[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot2+:2] : P_INCR ; assign si_cb_arlock[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slotP_LOCK+:1]} : 0 ; assign si_cb_arcache[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot4+:4] : 0 ; assign si_cb_arprot[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot3+:3] : 0 ; assign si_cb_arqos[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot4+:4] : 0 ; // assign si_cb_arregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot4+:4] : 0 ; assign si_cb_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign si_cb_arvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot1+:1] : 0 ; assign si_cb_rready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot1+:1] : 0 ; assign s_axi_awready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot1+:1] : 0 ; assign s_axi_wready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot1+:1] : 0 ; assign s_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_bresp[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot2+:2] : 0 ; assign s_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign s_axi_bvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot1+:1] : 0 ; assign s_axi_arready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot1+:1] : 0 ; assign s_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign s_axi_rresp[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot2+:2] : 0 ; assign s_axi_rlast[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot1+:1] : 0 ; assign s_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign s_axi_rvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot1+:1] : 0 ; end // gen_si_tieoff for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff assign m_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_awlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot8+:4] : 0 ; assign m_axi_awsize[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot3+:3] : 0 ; assign m_axi_awburst[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot2+:2] : 0 ; assign m_axi_awlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot2+:1] : 0 ; assign m_axi_awcache[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot4+:4] : 0 ; assign m_axi_awprot[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot3+:3] : 0 ; assign m_axi_awregion[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot4+:4] : 0 ; assign m_axi_awqos[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot4+:4] : 0 ; assign m_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign m_axi_awvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot1+:1] : 0 ; assign m_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign m_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign m_axi_wlast[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot1+:1] : 0 ; assign m_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign m_axi_wvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot1+:1] : 0 ; assign m_axi_bready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot1+:1] : 0 ; assign m_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_arlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot8+:4] : 0 ; assign m_axi_arsize[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot3+:3] : 0 ; assign m_axi_arburst[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot2+:2] : 0 ; assign m_axi_arlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot2+:1] : 0 ; assign m_axi_arcache[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot4+:4] : 0 ; assign m_axi_arprot[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot3+:3] : 0 ; assign m_axi_arregion[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot4+:4] : 0 ; assign m_axi_arqos[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot4+:4] : 0 ; assign m_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign m_axi_arvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot1+:1] : 0 ; assign m_axi_rready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot1+:1] : 0 ; assign cb_mi_awready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot1+:1] : 0 ; assign cb_mi_wready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot1+:1] : 0 ; assign cb_mi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_bresp[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot2+:2] : 0 ; assign cb_mi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign cb_mi_bvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot1+:1] : 0 ; assign cb_mi_arready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot1+:1] : 0 ; assign cb_mi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign cb_mi_rresp[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot2+:2] : 0 ; assign cb_mi_rlast[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot1+:1] : 1'b1 ; assign cb_mi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign cb_mi_rvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ; end // gen_mi_tieoff if ((C_CONNECTIVITY_MODE==0) \|\| (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd axi_crossbar_v2_1_crossbar_sasd # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_R_REGISTER (C_R_REGISTER), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_sasd_0 ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end else begin : gen_samd axi_crossbar_v2_1_crossbar # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY), .C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY), .C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD), .C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE), .C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE), .C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING), .C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ), .C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ), .C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)), .C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_samd ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end // gen_samd // end // gen_crossbar endgenerate endmodule
module axi_crossbar_v2_1_axi_crossbar # ( parameter C_FAMILY = "rtl", // FPGA Base Family. Current version: virtex6 or spartan6. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of Slave Interface (SI) slots for connecting // to master IP. Range: 1-16. parameter integer C_NUM_MASTER_SLOTS = 2, // Number of Master Interface (MI) slots for connecting // to slave IP. Range: 1-16. parameter integer C_AXI_ID_WIDTH = 1, // Width of ID signals propagated by the Interconnect. // Width of ID signals produced on all MI slots. // Range: 1-32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and // m_axi_araddr for all SI/MI slots. // Range: 1-64. parameter integer C_AXI_DATA_WIDTH = 32, // Data width of the internal interconnect write and read // data paths. // Range: 32, 64, 128, 256, 512, 1024. parameter integer C_AXI_PROTOCOL = 0, // 0 = "AXI4", // 1 = "AXI3", // 2 = "AXI4LITE" // Propagate WID only when C_AXI_PROTOCOL = 1. parameter integer C_NUM_ADDR_RANGES = 1, // Number of BASE/HIGH_ADDR pairs per MI slot. // Range: 1-16. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000, // Base address of each range of each MI slot. // For unused ranges, set C_M_AXI_BASE_ADDR[mmaa64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. // (Bit positions above C_AXI_ADDR_WIDTH are ignored.) // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, // Number of low-order address bits that are used to select locations within each address range of each MI slot. // The High address of each range is derived as BASE_ADDR + 2*C_M_AXI_ADDR_WIDTH -1. // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0. // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000. // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}. // Range: 0 - C_AXI_ADDR_WIDTH. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_BASE_ID = 32'h00000000, // Base ID of each SI slot. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 to 2*C_AXI_ID_WIDTH-1. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000, // Number of low-order ID bits a connected master may vary to select a transaction thread. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 - C_AXI_ID_WIDTH. parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway write connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway read connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter integer C_R_REGISTER = 0, // Insert register slice on R channel in the crossbar. (Valid only for SASD) // Range: Reg-slice type (0-8). parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000, // 0 = Implement separate command queues per ID thread. // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0, 1 parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002, // Maximum number of active write transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002, // Maximum number of active read transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004, // Maximum number of data-active write transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004, // Maximum number of active read transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000, // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0-15. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_SECURE = 32'h00000000, // Indicates whether each MI slot connects to a secure slave // (allows only TrustZone secure access). // Format: C_NUM_MASTER_SLOTS{Bit32}. // Range: 0, 1 parameter integer C_CONNECTIVITY_MODE = 1 // 0 = Shared-Address Shared-Data (SASD). // 1 = Shared-Address Multi-Data (SAMD). // Default 1 (on) for simulation; default 0 (off) for implementation. ) ( // Global Signals input wire aclk, input wire aresetn, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_awburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast, input wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_bresp, output wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] s_axi_buser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_arburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_rresp, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast, output wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_awburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awqos, output wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast, output wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_bresp, input wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] m_axi_buser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_arburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arqos, output wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_rresp, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast, input wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready ); localparam [64:0] P_ONES = {65{1'b1}}; localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_BASE_ID = f_base_id(0); localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_HIGH_ID = f_high_id(0); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam [2:0] P_AXILITE_SIZE = 3'b010; localparam [1:0] P_INCR = 2'b01; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0); localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0); localparam integer C_DEBUG = 1; localparam integer P_RANGE_CHECK = 1; // 1 (non-zero) = Detect and issue DECERR on the following conditions: // a. address range mismatch (no valid MI slot) // b. Burst or >32-bit transfer to AxiLite slave // c. TrustZone access violation // d. R/W direction unsupported by target // 0 = Pass all transactions (no DECERR): // a. Omit DECERR detection and response logic // b. Omit address decoder and propagate s_axi_aREGION to m_axi_aREGION // when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1. // c. Unpredictable target MI-slot if address mismatch and >1 MI-slot // d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0. localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) \|\| (C_NUM_MASTER_SLOTS > 1) \|\| (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1 localparam [C_NUM_MASTER_SLOTS32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}; // Transaction error detection (per MI-slot) // 0 = None; 1 = AXI4Lite burst violation // Format: C_NUM_MASTER_SLOTS{Bit32}; localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8; localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1; localparam P_FAMILY = ((C_FAMILY == "virtex7") \|\| (C_FAMILY == "kintex7") \|\| (C_FAMILY == "artix7") \|\| (C_FAMILY == "zynq")) ? C_FAMILY : "rtl"; function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2*acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_write_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_write_issue_width_vec = result; end endfunction // Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_read_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_read_issue_width_vec = result; end endfunction // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_write_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si32+:32]); end f_write_accept_width_vec = result; end endfunction // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_read_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si32+:32]); end f_read_accept_width_vec = result; end endfunction // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format function [C_NUM_SLAVE_SLOTS64-1:0] f_base_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH]; end f_base_id = result; end endfunction // Construct P_S_HIGH_ID vector function [C_NUM_SLAVE_SLOTS64-1:0] f_high_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end f_high_id = result; end endfunction // Construct P_M_HIGH_ADDR vector function [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] f_high_addr (input null_arg); integer ar; reg [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] result; begin result = {C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64{1'b0}}; for (ar=0; ar<C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES; ar=ar+1) begin result[ar64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar32+:32] == 0) ? 64'h00000000_00000000 : ({1'b0, C_M_AXI_ADDR_WIDTH[ar32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} : (C_M_AXI_BASE_ADDR[ar64+:C_AXI_ADDR_WIDTH] \| ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar32+:7]})); end f_high_addr = result; end endfunction // Generate a mask of valid ID bits for a given SI slot. function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask (input integer si); begin f_thread_id_mask = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : ({C_AXI_ID_WIDTH{1'b0}} \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end endfunction // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer si ); begin f_extend_ID = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? s_id : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]}))); end endfunction // Bit vector of SI slots with at least one write connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_write = result; end endfunction // Bit vector of SI slots with at least one read connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_read = result; end endfunction // Bit vector of MI slots with at least one write connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_write[mi] = (\|C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction // Bit vector of MI slots with at least one read connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_read[mi] = (\|C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_awid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_awlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_wid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_wdata ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] si_cb_wuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_bid ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_bresp ; wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] si_cb_buser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_arid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_araddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_arlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_rid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_rdata ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_rresp ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] si_cb_ruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_awid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_awlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awqos ; wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_wid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_wdata ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ; wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_bid ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_bresp ; wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] cb_mi_buser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_arid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_arlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arqos ; wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_rid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_rdata ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_rresp ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ; wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ; genvar slot; generate for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff assign si_cb_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_awlen[slot8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_awsize[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_awburst[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot2+:2] : P_INCR ; assign si_cb_awlock[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slotP_LOCK+:1]} : 0 ; assign si_cb_awcache[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot4+:4] : 0 ; assign si_cb_awprot[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot3+:3] : 0 ; assign si_cb_awqos[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot4+:4] : 0 ; // assign si_cb_awregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot4+:4] : 0 ; assign si_cb_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign si_cb_awvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot1+:1] : 0 ; assign si_cb_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign si_cb_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign si_cb_wlast[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot1+:1] : 1'b1 ; assign si_cb_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign si_cb_wvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot1+:1] : 0 ; assign si_cb_bready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot1+:1] : 0 ; assign si_cb_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_arlen[slot8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_arsize[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_arburst[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot2+:2] : P_INCR ; assign si_cb_arlock[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slotP_LOCK+:1]} : 0 ; assign si_cb_arcache[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot4+:4] : 0 ; assign si_cb_arprot[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot3+:3] : 0 ; assign si_cb_arqos[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot4+:4] : 0 ; // assign si_cb_arregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot4+:4] : 0 ; assign si_cb_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign si_cb_arvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot1+:1] : 0 ; assign si_cb_rready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot1+:1] : 0 ; assign s_axi_awready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot1+:1] : 0 ; assign s_axi_wready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot1+:1] : 0 ; assign s_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_bresp[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot2+:2] : 0 ; assign s_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign s_axi_bvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot1+:1] : 0 ; assign s_axi_arready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot1+:1] : 0 ; assign s_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign s_axi_rresp[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot2+:2] : 0 ; assign s_axi_rlast[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot1+:1] : 0 ; assign s_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign s_axi_rvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot1+:1] : 0 ; end // gen_si_tieoff for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff assign m_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_awlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot8+:4] : 0 ; assign m_axi_awsize[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot3+:3] : 0 ; assign m_axi_awburst[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot2+:2] : 0 ; assign m_axi_awlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot2+:1] : 0 ; assign m_axi_awcache[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot4+:4] : 0 ; assign m_axi_awprot[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot3+:3] : 0 ; assign m_axi_awregion[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot4+:4] : 0 ; assign m_axi_awqos[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot4+:4] : 0 ; assign m_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign m_axi_awvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot1+:1] : 0 ; assign m_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign m_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign m_axi_wlast[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot1+:1] : 0 ; assign m_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign m_axi_wvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot1+:1] : 0 ; assign m_axi_bready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot1+:1] : 0 ; assign m_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_arlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot8+:4] : 0 ; assign m_axi_arsize[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot3+:3] : 0 ; assign m_axi_arburst[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot2+:2] : 0 ; assign m_axi_arlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot2+:1] : 0 ; assign m_axi_arcache[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot4+:4] : 0 ; assign m_axi_arprot[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot3+:3] : 0 ; assign m_axi_arregion[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot4+:4] : 0 ; assign m_axi_arqos[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot4+:4] : 0 ; assign m_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign m_axi_arvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot1+:1] : 0 ; assign m_axi_rready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot1+:1] : 0 ; assign cb_mi_awready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot1+:1] : 0 ; assign cb_mi_wready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot1+:1] : 0 ; assign cb_mi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_bresp[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot2+:2] : 0 ; assign cb_mi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign cb_mi_bvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot1+:1] : 0 ; assign cb_mi_arready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot1+:1] : 0 ; assign cb_mi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign cb_mi_rresp[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot2+:2] : 0 ; assign cb_mi_rlast[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot1+:1] : 1'b1 ; assign cb_mi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign cb_mi_rvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ; end // gen_mi_tieoff if ((C_CONNECTIVITY_MODE==0) \|\| (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd axi_crossbar_v2_1_crossbar_sasd # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_R_REGISTER (C_R_REGISTER), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_sasd_0 ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end else begin : gen_samd axi_crossbar_v2_1_crossbar # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY), .C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY), .C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD), .C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE), .C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE), .C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING), .C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ), .C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ), .C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)), .C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_samd ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end // gen_samd // end // gen_crossbar endgenerate endmodule
module axi_crossbar_v2_1_axi_crossbar # ( parameter C_FAMILY = "rtl", // FPGA Base Family. Current version: virtex6 or spartan6. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of Slave Interface (SI) slots for connecting // to master IP. Range: 1-16. parameter integer C_NUM_MASTER_SLOTS = 2, // Number of Master Interface (MI) slots for connecting // to slave IP. Range: 1-16. parameter integer C_AXI_ID_WIDTH = 1, // Width of ID signals propagated by the Interconnect. // Width of ID signals produced on all MI slots. // Range: 1-32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and // m_axi_araddr for all SI/MI slots. // Range: 1-64. parameter integer C_AXI_DATA_WIDTH = 32, // Data width of the internal interconnect write and read // data paths. // Range: 32, 64, 128, 256, 512, 1024. parameter integer C_AXI_PROTOCOL = 0, // 0 = "AXI4", // 1 = "AXI3", // 2 = "AXI4LITE" // Propagate WID only when C_AXI_PROTOCOL = 1. parameter integer C_NUM_ADDR_RANGES = 1, // Number of BASE/HIGH_ADDR pairs per MI slot. // Range: 1-16. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000, // Base address of each range of each MI slot. // For unused ranges, set C_M_AXI_BASE_ADDR[mmaa64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. // (Bit positions above C_AXI_ADDR_WIDTH are ignored.) // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, // Number of low-order address bits that are used to select locations within each address range of each MI slot. // The High address of each range is derived as BASE_ADDR + 2*C_M_AXI_ADDR_WIDTH -1. // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0. // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000. // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}. // Range: 0 - C_AXI_ADDR_WIDTH. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_BASE_ID = 32'h00000000, // Base ID of each SI slot. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 to 2*C_AXI_ID_WIDTH-1. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000, // Number of low-order ID bits a connected master may vary to select a transaction thread. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 - C_AXI_ID_WIDTH. parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway write connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway read connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter integer C_R_REGISTER = 0, // Insert register slice on R channel in the crossbar. (Valid only for SASD) // Range: Reg-slice type (0-8). parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000, // 0 = Implement separate command queues per ID thread. // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0, 1 parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002, // Maximum number of active write transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002, // Maximum number of active read transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004, // Maximum number of data-active write transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004, // Maximum number of active read transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000, // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0-15. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_SECURE = 32'h00000000, // Indicates whether each MI slot connects to a secure slave // (allows only TrustZone secure access). // Format: C_NUM_MASTER_SLOTS{Bit32}. // Range: 0, 1 parameter integer C_CONNECTIVITY_MODE = 1 // 0 = Shared-Address Shared-Data (SASD). // 1 = Shared-Address Multi-Data (SAMD). // Default 1 (on) for simulation; default 0 (off) for implementation. ) ( // Global Signals input wire aclk, input wire aresetn, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_awburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast, input wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_bresp, output wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] s_axi_buser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_arburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_rresp, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast, output wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_awburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awqos, output wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast, output wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_bresp, input wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] m_axi_buser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_arburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arqos, output wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_rresp, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast, input wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready ); localparam [64:0] P_ONES = {65{1'b1}}; localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_BASE_ID = f_base_id(0); localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_HIGH_ID = f_high_id(0); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam [2:0] P_AXILITE_SIZE = 3'b010; localparam [1:0] P_INCR = 2'b01; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0); localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0); localparam integer C_DEBUG = 1; localparam integer P_RANGE_CHECK = 1; // 1 (non-zero) = Detect and issue DECERR on the following conditions: // a. address range mismatch (no valid MI slot) // b. Burst or >32-bit transfer to AxiLite slave // c. TrustZone access violation // d. R/W direction unsupported by target // 0 = Pass all transactions (no DECERR): // a. Omit DECERR detection and response logic // b. Omit address decoder and propagate s_axi_aREGION to m_axi_aREGION // when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1. // c. Unpredictable target MI-slot if address mismatch and >1 MI-slot // d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0. localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) \|\| (C_NUM_MASTER_SLOTS > 1) \|\| (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1 localparam [C_NUM_MASTER_SLOTS32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}; // Transaction error detection (per MI-slot) // 0 = None; 1 = AXI4Lite burst violation // Format: C_NUM_MASTER_SLOTS{Bit32}; localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8; localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1; localparam P_FAMILY = ((C_FAMILY == "virtex7") \|\| (C_FAMILY == "kintex7") \|\| (C_FAMILY == "artix7") \|\| (C_FAMILY == "zynq")) ? C_FAMILY : "rtl"; function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2*acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_write_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_write_issue_width_vec = result; end endfunction // Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_read_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_read_issue_width_vec = result; end endfunction // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_write_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si32+:32]); end f_write_accept_width_vec = result; end endfunction // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_read_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si32+:32]); end f_read_accept_width_vec = result; end endfunction // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format function [C_NUM_SLAVE_SLOTS64-1:0] f_base_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH]; end f_base_id = result; end endfunction // Construct P_S_HIGH_ID vector function [C_NUM_SLAVE_SLOTS64-1:0] f_high_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end f_high_id = result; end endfunction // Construct P_M_HIGH_ADDR vector function [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] f_high_addr (input null_arg); integer ar; reg [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] result; begin result = {C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64{1'b0}}; for (ar=0; ar<C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES; ar=ar+1) begin result[ar64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar32+:32] == 0) ? 64'h00000000_00000000 : ({1'b0, C_M_AXI_ADDR_WIDTH[ar32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} : (C_M_AXI_BASE_ADDR[ar64+:C_AXI_ADDR_WIDTH] \| ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar32+:7]})); end f_high_addr = result; end endfunction // Generate a mask of valid ID bits for a given SI slot. function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask (input integer si); begin f_thread_id_mask = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : ({C_AXI_ID_WIDTH{1'b0}} \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end endfunction // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer si ); begin f_extend_ID = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? s_id : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]}))); end endfunction // Bit vector of SI slots with at least one write connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_write = result; end endfunction // Bit vector of SI slots with at least one read connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_read = result; end endfunction // Bit vector of MI slots with at least one write connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_write[mi] = (\|C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction // Bit vector of MI slots with at least one read connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_read[mi] = (\|C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_awid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_awlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_wid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_wdata ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] si_cb_wuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_bid ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_bresp ; wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] si_cb_buser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_arid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_araddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_arlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_rid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_rdata ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_rresp ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] si_cb_ruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_awid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_awlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awqos ; wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_wid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_wdata ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ; wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_bid ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_bresp ; wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] cb_mi_buser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_arid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_arlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arqos ; wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_rid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_rdata ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_rresp ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ; wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ; genvar slot; generate for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff assign si_cb_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_awlen[slot8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_awsize[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_awburst[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot2+:2] : P_INCR ; assign si_cb_awlock[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slotP_LOCK+:1]} : 0 ; assign si_cb_awcache[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot4+:4] : 0 ; assign si_cb_awprot[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot3+:3] : 0 ; assign si_cb_awqos[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot4+:4] : 0 ; // assign si_cb_awregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot4+:4] : 0 ; assign si_cb_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign si_cb_awvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot1+:1] : 0 ; assign si_cb_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign si_cb_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign si_cb_wlast[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot1+:1] : 1'b1 ; assign si_cb_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign si_cb_wvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot1+:1] : 0 ; assign si_cb_bready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot1+:1] : 0 ; assign si_cb_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_arlen[slot8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_arsize[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_arburst[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot2+:2] : P_INCR ; assign si_cb_arlock[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slotP_LOCK+:1]} : 0 ; assign si_cb_arcache[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot4+:4] : 0 ; assign si_cb_arprot[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot3+:3] : 0 ; assign si_cb_arqos[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot4+:4] : 0 ; // assign si_cb_arregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot4+:4] : 0 ; assign si_cb_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign si_cb_arvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot1+:1] : 0 ; assign si_cb_rready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot1+:1] : 0 ; assign s_axi_awready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot1+:1] : 0 ; assign s_axi_wready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot1+:1] : 0 ; assign s_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_bresp[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot2+:2] : 0 ; assign s_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign s_axi_bvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot1+:1] : 0 ; assign s_axi_arready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot1+:1] : 0 ; assign s_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign s_axi_rresp[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot2+:2] : 0 ; assign s_axi_rlast[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot1+:1] : 0 ; assign s_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign s_axi_rvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot1+:1] : 0 ; end // gen_si_tieoff for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff assign m_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_awlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot8+:4] : 0 ; assign m_axi_awsize[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot3+:3] : 0 ; assign m_axi_awburst[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot2+:2] : 0 ; assign m_axi_awlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot2+:1] : 0 ; assign m_axi_awcache[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot4+:4] : 0 ; assign m_axi_awprot[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot3+:3] : 0 ; assign m_axi_awregion[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot4+:4] : 0 ; assign m_axi_awqos[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot4+:4] : 0 ; assign m_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign m_axi_awvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot1+:1] : 0 ; assign m_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign m_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign m_axi_wlast[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot1+:1] : 0 ; assign m_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign m_axi_wvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot1+:1] : 0 ; assign m_axi_bready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot1+:1] : 0 ; assign m_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_arlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot8+:4] : 0 ; assign m_axi_arsize[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot3+:3] : 0 ; assign m_axi_arburst[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot2+:2] : 0 ; assign m_axi_arlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot2+:1] : 0 ; assign m_axi_arcache[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot4+:4] : 0 ; assign m_axi_arprot[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot3+:3] : 0 ; assign m_axi_arregion[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot4+:4] : 0 ; assign m_axi_arqos[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot4+:4] : 0 ; assign m_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign m_axi_arvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot1+:1] : 0 ; assign m_axi_rready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot1+:1] : 0 ; assign cb_mi_awready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot1+:1] : 0 ; assign cb_mi_wready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot1+:1] : 0 ; assign cb_mi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_bresp[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot2+:2] : 0 ; assign cb_mi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign cb_mi_bvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot1+:1] : 0 ; assign cb_mi_arready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot1+:1] : 0 ; assign cb_mi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign cb_mi_rresp[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot2+:2] : 0 ; assign cb_mi_rlast[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot1+:1] : 1'b1 ; assign cb_mi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign cb_mi_rvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ; end // gen_mi_tieoff if ((C_CONNECTIVITY_MODE==0) \|\| (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd axi_crossbar_v2_1_crossbar_sasd # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_R_REGISTER (C_R_REGISTER), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_sasd_0 ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end else begin : gen_samd axi_crossbar_v2_1_crossbar # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY), .C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY), .C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD), .C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE), .C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE), .C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING), .C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ), .C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ), .C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)), .C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_samd ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end // gen_samd // end // gen_crossbar endgenerate endmodule
module axi_crossbar_v2_1_axi_crossbar # ( parameter C_FAMILY = "rtl", // FPGA Base Family. Current version: virtex6 or spartan6. parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of Slave Interface (SI) slots for connecting // to master IP. Range: 1-16. parameter integer C_NUM_MASTER_SLOTS = 2, // Number of Master Interface (MI) slots for connecting // to slave IP. Range: 1-16. parameter integer C_AXI_ID_WIDTH = 1, // Width of ID signals propagated by the Interconnect. // Width of ID signals produced on all MI slots. // Range: 1-32. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and // m_axi_araddr for all SI/MI slots. // Range: 1-64. parameter integer C_AXI_DATA_WIDTH = 32, // Data width of the internal interconnect write and read // data paths. // Range: 32, 64, 128, 256, 512, 1024. parameter integer C_AXI_PROTOCOL = 0, // 0 = "AXI4", // 1 = "AXI3", // 2 = "AXI4LITE" // Propagate WID only when C_AXI_PROTOCOL = 1. parameter integer C_NUM_ADDR_RANGES = 1, // Number of BASE/HIGH_ADDR pairs per MI slot. // Range: 1-16. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000, // Base address of each range of each MI slot. // For unused ranges, set C_M_AXI_BASE_ADDR[mmaa64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}. // (Bit positions above C_AXI_ADDR_WIDTH are ignored.) // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}. parameter [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c, // Number of low-order address bits that are used to select locations within each address range of each MI slot. // The High address of each range is derived as BASE_ADDR + 2*C_M_AXI_ADDR_WIDTH -1. // For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0. // For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000. // Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}. // Range: 0 - C_AXI_ADDR_WIDTH. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_BASE_ID = 32'h00000000, // Base ID of each SI slot. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 to 2*C_AXI_ID_WIDTH-1. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000, // Number of low-order ID bits a connected master may vary to select a transaction thread. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0 - C_AXI_ID_WIDTH. parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, // 1 = Propagate all USER signals, 0 = Dont propagate. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals for all SI slots and MI slots. // Range: 1-1024. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway write connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF, // Multi-pathway read connectivity from each SI slot (N) to each // MI slot (M): // 0 = no pathway required; 1 = pathway required. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; parameter integer C_R_REGISTER = 0, // Insert register slice on R channel in the crossbar. (Valid only for SASD) // Range: Reg-slice type (0-8). parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000, // 0 = Implement separate command queues per ID thread. // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0, 1 parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002, // Maximum number of active write transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002, // Maximum number of active read transactions that each SI // slot can accept. (Valid only for SAMD) // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004, // Maximum number of data-active write transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004, // Maximum number of active read transactions that // each MI slot can generate at any one time. (Valid only for SAMD) // Format: C_NUM_MASTER_SLOTS{Bit32}; // Range: 1-32. parameter [C_NUM_SLAVE_SLOTS32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000, // Arbitration priority among each SI slot. // Higher values indicate higher priority. // Format: C_NUM_SLAVE_SLOTS{Bit32}; // Range: 0-15. parameter [C_NUM_MASTER_SLOTS32-1:0] C_M_AXI_SECURE = 32'h00000000, // Indicates whether each MI slot connects to a secure slave // (allows only TrustZone secure access). // Format: C_NUM_MASTER_SLOTS{Bit32}. // Range: 0, 1 parameter integer C_CONNECTIVITY_MODE = 1 // 0 = Shared-Address Shared-Data (SASD). // 1 = Shared-Address Multi-Data (SAMD). // Default 1 (on) for simulation; default 0 (off) for implementation. ) ( // Global Signals input wire aclk, input wire aresetn, // Slave Interface Write Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_awid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_awburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_awprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_awqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready, // Slave Interface Write Data Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_wid, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_wdata, input wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast, input wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready, // Slave Interface Write Response Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_bid, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_bresp, output wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] s_axi_buser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready, // Slave Interface Read Address Ports input wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_arid, input wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arsize, input wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_arburst, input wire [C_NUM_SLAVE_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arcache, input wire [C_NUM_SLAVE_SLOTS3-1:0] s_axi_arprot, // input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arregion, input wire [C_NUM_SLAVE_SLOTS4-1:0] s_axi_arqos, input wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready, // Slave Interface Read Data Ports output wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] s_axi_rid, output wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] s_axi_rdata, output wire [C_NUM_SLAVE_SLOTS2-1:0] s_axi_rresp, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast, output wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid, input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready, // Master Interface Write Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_awburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_awprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_awqos, output wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready, // Master Interface Write Data Ports output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast, output wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready, // Master Interface Write Response Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_bresp, input wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] m_axi_buser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready, // Master Interface Read Address Port output wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arsize, output wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_arburst, output wire [C_NUM_MASTER_SLOTS((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arcache, output wire [C_NUM_MASTER_SLOTS3-1:0] m_axi_arprot, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arregion, output wire [C_NUM_MASTER_SLOTS4-1:0] m_axi_arqos, output wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready, // Master Interface Read Data Ports input wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [C_NUM_MASTER_SLOTS2-1:0] m_axi_rresp, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast, input wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid, output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready ); localparam [64:0] P_ONES = {65{1'b1}}; localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_BASE_ID = f_base_id(0); localparam [C_NUM_SLAVE_SLOTS64-1:0] P_S_AXI_HIGH_ID = f_high_id(0); localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; localparam [2:0] P_AXILITE_SIZE = 3'b010; localparam [1:0] P_INCR = 2'b01; localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0); localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0); localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0); localparam integer C_DEBUG = 1; localparam integer P_RANGE_CHECK = 1; // 1 (non-zero) = Detect and issue DECERR on the following conditions: // a. address range mismatch (no valid MI slot) // b. Burst or >32-bit transfer to AxiLite slave // c. TrustZone access violation // d. R/W direction unsupported by target // 0 = Pass all transactions (no DECERR): // a. Omit DECERR detection and response logic // b. Omit address decoder and propagate s_axi_aREGION to m_axi_aREGION // when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1. // c. Unpredictable target MI-slot if address mismatch and >1 MI-slot // d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave // Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0. localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) \|\| (C_NUM_MASTER_SLOTS > 1) \|\| (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1 localparam [C_NUM_MASTER_SLOTS32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}}; // Transaction error detection (per MI-slot) // 0 = None; 1 = AXI4Lite burst violation // Format: C_NUM_MASTER_SLOTS{Bit32}; localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8; localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1; localparam P_FAMILY = ((C_FAMILY == "virtex7") \|\| (C_FAMILY == "kintex7") \|\| (C_FAMILY == "artix7") \|\| (C_FAMILY == "zynq")) ? C_FAMILY : "rtl"; function integer f_ceil_log2 ( input integer x ); integer acc; begin acc=0; while ((2*acc) < x) acc = acc + 1; f_ceil_log2 = acc; end endfunction // Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_write_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_write_issue_width_vec = result; end endfunction // Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [(C_NUM_MASTER_SLOTS+1)32-1:0] f_read_issue_width_vec (input null_arg); integer mi; reg [(C_NUM_MASTER_SLOTS+1)32-1:0] result; begin result = 0; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result[mi32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi32+:32]); end result[C_NUM_MASTER_SLOTS32+:32] = 32'h0; f_read_issue_width_vec = result; end endfunction // Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_write_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si32+:32]); end f_write_accept_width_vec = result; end endfunction // Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit) function [C_NUM_SLAVE_SLOTS32-1:0] f_read_accept_width_vec (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS32-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si32+:32]); end f_read_accept_width_vec = result; end endfunction // Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format function [C_NUM_SLAVE_SLOTS64-1:0] f_base_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH]; end f_base_id = result; end endfunction // Construct P_S_HIGH_ID vector function [C_NUM_SLAVE_SLOTS64-1:0] f_high_id (input null_arg); integer si; reg [C_NUM_SLAVE_SLOTS64-1:0] result; begin result = 0; for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin result[si64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end f_high_id = result; end endfunction // Construct P_M_HIGH_ADDR vector function [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] f_high_addr (input null_arg); integer ar; reg [C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64-1:0] result; begin result = {C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES64{1'b0}}; for (ar=0; ar<C_NUM_MASTER_SLOTSC_NUM_ADDR_RANGES; ar=ar+1) begin result[ar64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar32+:32] == 0) ? 64'h00000000_00000000 : ({1'b0, C_M_AXI_ADDR_WIDTH[ar32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} : (C_M_AXI_BASE_ADDR[ar64+:C_AXI_ADDR_WIDTH] \| ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar32+:7]})); end f_high_addr = result; end endfunction // Generate a mask of valid ID bits for a given SI slot. function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask (input integer si); begin f_thread_id_mask = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} : ({C_AXI_ID_WIDTH{1'b0}} \| ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]})); end endfunction // Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value // only for end-point SI-slots function [C_AXI_ID_WIDTH-1:0] f_extend_ID ( input [C_AXI_ID_WIDTH-1:0] s_id, input integer si ); begin f_extend_ID = (C_S_AXI_THREAD_ID_WIDTH[si32+:32] == 0) ? C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] : ({1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:31]} >= C_AXI_ID_WIDTH) ? s_id : (C_S_AXI_BASE_ID[si32+:C_AXI_ID_WIDTH] \| (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si32+:6]}))); end endfunction // Bit vector of SI slots with at least one write connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_write = result; end endfunction // Bit vector of SI slots with at least one read connection. function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read (input null_arg); integer mi; reg [C_NUM_SLAVE_SLOTS-1:0] result; begin result = {C_NUM_SLAVE_SLOTS{1'b0}}; for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin result = result \| C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]; end f_s_supports_read = result; end endfunction // Bit vector of MI slots with at least one write connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_write[mi] = (\|C_M_AXI_WRITE_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction // Bit vector of MI slots with at least one read connection. function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read (input null_arg); integer mi; begin for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin f_m_supports_read[mi] = (\|C_M_AXI_READ_CONNECTIVITY[mi32+:C_NUM_SLAVE_SLOTS]); end end endfunction wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_awid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_awlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_awlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_awprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_awqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_wid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_wdata ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_WUSER_WIDTH-1:0] si_cb_wuser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_bid ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_bresp ; wire [C_NUM_SLAVE_SLOTSC_AXI_BUSER_WIDTH-1:0] si_cb_buser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_arid ; wire [C_NUM_SLAVE_SLOTSC_AXI_ADDR_WIDTH-1:0] si_cb_araddr ; wire [C_NUM_SLAVE_SLOTS8-1:0] si_cb_arlen ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arsize ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arburst ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_arlock ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arcache ; wire [C_NUM_SLAVE_SLOTS3-1:0] si_cb_arprot ; // wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arregion ; wire [C_NUM_SLAVE_SLOTS4-1:0] si_cb_arqos ; wire [C_NUM_SLAVE_SLOTSC_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ; wire [C_NUM_SLAVE_SLOTSC_AXI_ID_WIDTH-1:0] si_cb_rid ; wire [C_NUM_SLAVE_SLOTSC_AXI_DATA_WIDTH-1:0] si_cb_rdata ; wire [C_NUM_SLAVE_SLOTS2-1:0] si_cb_rresp ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ; wire [C_NUM_SLAVE_SLOTSC_AXI_RUSER_WIDTH-1:0] si_cb_ruser ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ; wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_awid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_awlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_awlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_awprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_awqos ; wire [C_NUM_MASTER_SLOTSC_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_wid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_wdata ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ; wire [C_NUM_MASTER_SLOTSC_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_bid ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_bresp ; wire [C_NUM_MASTER_SLOTSC_AXI_BUSER_WIDTH-1:0] cb_mi_buser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_arid ; wire [C_NUM_MASTER_SLOTSC_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ; wire [C_NUM_MASTER_SLOTS8-1:0] cb_mi_arlen ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arsize ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arburst ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_arlock ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arcache ; wire [C_NUM_MASTER_SLOTS3-1:0] cb_mi_arprot ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arregion ; wire [C_NUM_MASTER_SLOTS4-1:0] cb_mi_arqos ; wire [C_NUM_MASTER_SLOTSC_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ; wire [C_NUM_MASTER_SLOTSC_AXI_ID_WIDTH-1:0] cb_mi_rid ; wire [C_NUM_MASTER_SLOTSC_AXI_DATA_WIDTH-1:0] cb_mi_rdata ; wire [C_NUM_MASTER_SLOTS2-1:0] cb_mi_rresp ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ; wire [C_NUM_MASTER_SLOTSC_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ; wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ; genvar slot; generate for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff assign si_cb_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_awlen[slot8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_awsize[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_awburst[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot2+:2] : P_INCR ; assign si_cb_awlock[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slotP_LOCK+:1]} : 0 ; assign si_cb_awcache[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot4+:4] : 0 ; assign si_cb_awprot[slot3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot3+:3] : 0 ; assign si_cb_awqos[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot4+:4] : 0 ; // assign si_cb_awregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot4+:4] : 0 ; assign si_cb_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign si_cb_awvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot1+:1] : 0 ; assign si_cb_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign si_cb_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign si_cb_wlast[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot1+:1] : 1'b1 ; assign si_cb_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign si_cb_wvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot1+:1] : 0 ; assign si_cb_bready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot1+:1] : 0 ; assign si_cb_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign si_cb_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign si_cb_arlen[slot8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slotP_LEN+:P_LEN] : 0 ; assign si_cb_arsize[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot3+:3] : P_AXILITE_SIZE ; assign si_cb_arburst[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot2+:2] : P_INCR ; assign si_cb_arlock[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slotP_LOCK+:1]} : 0 ; assign si_cb_arcache[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot4+:4] : 0 ; assign si_cb_arprot[slot3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot3+:3] : 0 ; assign si_cb_arqos[slot4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot4+:4] : 0 ; // assign si_cb_arregion[slot4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot4+:4] : 0 ; assign si_cb_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign si_cb_arvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot1+:1] : 0 ; assign si_cb_rready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot1+:1] : 0 ; assign s_axi_awready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot1+:1] : 0 ; assign s_axi_wready[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot1+:1] : 0 ; assign s_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_bresp[slot2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot2+:2] : 0 ; assign s_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign s_axi_bvalid[slot1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot1+:1] : 0 ; assign s_axi_arready[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot1+:1] : 0 ; assign s_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ; assign s_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign s_axi_rresp[slot2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot2+:2] : 0 ; assign s_axi_rlast[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot1+:1] : 0 ; assign s_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign s_axi_rvalid[slot1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot1+:1] : 0 ; end // gen_si_tieoff for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff assign m_axi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_awlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot8+:4] : 0 ; assign m_axi_awsize[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot3+:3] : 0 ; assign m_axi_awburst[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot2+:2] : 0 ; assign m_axi_awlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot2+:1] : 0 ; assign m_axi_awcache[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot4+:4] : 0 ; assign m_axi_awprot[slot3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot3+:3] : 0 ; assign m_axi_awregion[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot4+:4] : 0 ; assign m_axi_awqos[slot4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot4+:4] : 0 ; assign m_axi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slotC_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ; assign m_axi_awvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot1+:1] : 0 ; assign m_axi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign m_axi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slotC_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ; assign m_axi_wlast[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot1+:1] : 0 ; assign m_axi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slotC_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ; assign m_axi_wvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot1+:1] : 0 ; assign m_axi_bready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot1+:1] : 0 ; assign m_axi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign m_axi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slotC_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ; assign m_axi_arlen[slotP_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot8+:4] : 0 ; assign m_axi_arsize[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot3+:3] : 0 ; assign m_axi_arburst[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot2+:2] : 0 ; assign m_axi_arlock[slotP_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot2+:1] : 0 ; assign m_axi_arcache[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot4+:4] : 0 ; assign m_axi_arprot[slot3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot3+:3] : 0 ; assign m_axi_arregion[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot4+:4] : 0 ; assign m_axi_arqos[slot4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot4+:4] : 0 ; assign m_axi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slotC_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ; assign m_axi_arvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot1+:1] : 0 ; assign m_axi_rready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot1+:1] : 0 ; assign cb_mi_awready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot1+:1] : 0 ; assign cb_mi_wready[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot1+:1] : 0 ; assign cb_mi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_bresp[slot2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot2+:2] : 0 ; assign cb_mi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slotC_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ; assign cb_mi_bvalid[slot1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot1+:1] : 0 ; assign cb_mi_arready[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot1+:1] : 0 ; assign cb_mi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slotC_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ; assign cb_mi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slotC_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ; assign cb_mi_rresp[slot2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot2+:2] : 0 ; assign cb_mi_rlast[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot1+:1] : 1'b1 ; assign cb_mi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slotC_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ; assign cb_mi_rvalid[slot1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ; end // gen_mi_tieoff if ((C_CONNECTIVITY_MODE==0) \|\| (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd axi_crossbar_v2_1_crossbar_sasd # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_R_REGISTER (C_R_REGISTER), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_sasd_0 ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end else begin : gen_samd axi_crossbar_v2_1_crossbar # ( .C_FAMILY (P_FAMILY), .C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS), .C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS), .C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_PROTOCOL (C_AXI_PROTOCOL), .C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR), .C_M_AXI_HIGH_ADDR (f_high_addr(0)), .C_S_AXI_BASE_ID (P_S_AXI_BASE_ID), .C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), .C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE), .C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ), .C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE), .C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ), .C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY), .C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY), .C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD), .C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE), .C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE), .C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING), .C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING), .C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY), .C_M_AXI_SECURE (C_M_AXI_SECURE), .C_RANGE_CHECK (P_RANGE_CHECK), .C_ADDR_DECODE (P_ADDR_DECODE), .C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ), .C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ), .C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)), .C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)), .C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE), .C_DEBUG (C_DEBUG) ) crossbar_samd ( .ACLK (aclk), .ARESETN (aresetn), .S_AXI_AWID (si_cb_awid ), .S_AXI_AWADDR (si_cb_awaddr ), .S_AXI_AWLEN (si_cb_awlen ), .S_AXI_AWSIZE (si_cb_awsize ), .S_AXI_AWBURST (si_cb_awburst ), .S_AXI_AWLOCK (si_cb_awlock ), .S_AXI_AWCACHE (si_cb_awcache ), .S_AXI_AWPROT (si_cb_awprot ), // .S_AXI_AWREGION (si_cb_awregion ), .S_AXI_AWQOS (si_cb_awqos ), .S_AXI_AWUSER (si_cb_awuser ), .S_AXI_AWVALID (si_cb_awvalid ), .S_AXI_AWREADY (si_cb_awready ), .S_AXI_WID (si_cb_wid ), .S_AXI_WDATA (si_cb_wdata ), .S_AXI_WSTRB (si_cb_wstrb ), .S_AXI_WLAST (si_cb_wlast ), .S_AXI_WUSER (si_cb_wuser ), .S_AXI_WVALID (si_cb_wvalid ), .S_AXI_WREADY (si_cb_wready ), .S_AXI_BID (si_cb_bid ), .S_AXI_BRESP (si_cb_bresp ), .S_AXI_BUSER (si_cb_buser ), .S_AXI_BVALID (si_cb_bvalid ), .S_AXI_BREADY (si_cb_bready ), .S_AXI_ARID (si_cb_arid ), .S_AXI_ARADDR (si_cb_araddr ), .S_AXI_ARLEN (si_cb_arlen ), .S_AXI_ARSIZE (si_cb_arsize ), .S_AXI_ARBURST (si_cb_arburst ), .S_AXI_ARLOCK (si_cb_arlock ), .S_AXI_ARCACHE (si_cb_arcache ), .S_AXI_ARPROT (si_cb_arprot ), // .S_AXI_ARREGION (si_cb_arregion ), .S_AXI_ARQOS (si_cb_arqos ), .S_AXI_ARUSER (si_cb_aruser ), .S_AXI_ARVALID (si_cb_arvalid ), .S_AXI_ARREADY (si_cb_arready ), .S_AXI_RID (si_cb_rid ), .S_AXI_RDATA (si_cb_rdata ), .S_AXI_RRESP (si_cb_rresp ), .S_AXI_RLAST (si_cb_rlast ), .S_AXI_RUSER (si_cb_ruser ), .S_AXI_RVALID (si_cb_rvalid ), .S_AXI_RREADY (si_cb_rready ), .M_AXI_AWID (cb_mi_awid ), .M_AXI_AWADDR (cb_mi_awaddr ), .M_AXI_AWLEN (cb_mi_awlen ), .M_AXI_AWSIZE (cb_mi_awsize ), .M_AXI_AWBURST (cb_mi_awburst ), .M_AXI_AWLOCK (cb_mi_awlock ), .M_AXI_AWCACHE (cb_mi_awcache ), .M_AXI_AWPROT (cb_mi_awprot ), .M_AXI_AWREGION (cb_mi_awregion ), .M_AXI_AWQOS (cb_mi_awqos ), .M_AXI_AWUSER (cb_mi_awuser ), .M_AXI_AWVALID (cb_mi_awvalid ), .M_AXI_AWREADY (cb_mi_awready ), .M_AXI_WID (cb_mi_wid ), .M_AXI_WDATA (cb_mi_wdata ), .M_AXI_WSTRB (cb_mi_wstrb ), .M_AXI_WLAST (cb_mi_wlast ), .M_AXI_WUSER (cb_mi_wuser ), .M_AXI_WVALID (cb_mi_wvalid ), .M_AXI_WREADY (cb_mi_wready ), .M_AXI_BID (cb_mi_bid ), .M_AXI_BRESP (cb_mi_bresp ), .M_AXI_BUSER (cb_mi_buser ), .M_AXI_BVALID (cb_mi_bvalid ), .M_AXI_BREADY (cb_mi_bready ), .M_AXI_ARID (cb_mi_arid ), .M_AXI_ARADDR (cb_mi_araddr ), .M_AXI_ARLEN (cb_mi_arlen ), .M_AXI_ARSIZE (cb_mi_arsize ), .M_AXI_ARBURST (cb_mi_arburst ), .M_AXI_ARLOCK (cb_mi_arlock ), .M_AXI_ARCACHE (cb_mi_arcache ), .M_AXI_ARPROT (cb_mi_arprot ), .M_AXI_ARREGION (cb_mi_arregion ), .M_AXI_ARQOS (cb_mi_arqos ), .M_AXI_ARUSER (cb_mi_aruser ), .M_AXI_ARVALID (cb_mi_arvalid ), .M_AXI_ARREADY (cb_mi_arready ), .M_AXI_RID (cb_mi_rid ), .M_AXI_RDATA (cb_mi_rdata ), .M_AXI_RRESP (cb_mi_rresp ), .M_AXI_RLAST (cb_mi_rlast ), .M_AXI_RUSER (cb_mi_ruser ), .M_AXI_RVALID (cb_mi_rvalid ), .M_AXI_RREADY (cb_mi_rready ) ); end // gen_samd // end // gen_crossbar endgenerate endmodule
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); parameter bitwidth = 16; parameter zwidth = 16; parameter shift = 1; input clock; input reset; input enable; input [bitwidth-1:0] xi,yi; input [zwidth-1:0] zi; input [zwidth-1:0] constant; output [bitwidth-1:0] xo,yo; output [zwidth-1:0] zo; wire z_is_pos = ~zi[zwidth-1]; reg [bitwidth-1:0] xo,yo; reg [zwidth-1:0] zo; always @(posedge clock) if(reset) begin xo <= #1 0; yo <= #1 0; zo <= #1 0; end else if(enable) begin xo <= #1 z_is_pos ? xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} : xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]}; yo <= #1 z_is_pos ? yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} : yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]}; zo <= #1 z_is_pos ? zi - constant : zi + constant; end endmodule
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); parameter bitwidth = 16; parameter zwidth = 16; parameter shift = 1; input clock; input reset; input enable; input [bitwidth-1:0] xi,yi; input [zwidth-1:0] zi; input [zwidth-1:0] constant; output [bitwidth-1:0] xo,yo; output [zwidth-1:0] zo; wire z_is_pos = ~zi[zwidth-1]; reg [bitwidth-1:0] xo,yo; reg [zwidth-1:0] zo; always @(posedge clock) if(reset) begin xo <= #1 0; yo <= #1 0; zo <= #1 0; end else if(enable) begin xo <= #1 z_is_pos ? xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} : xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]}; yo <= #1 z_is_pos ? yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} : yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]}; zo <= #1 z_is_pos ? zi - constant : zi + constant; end endmodule
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); parameter bitwidth = 16; parameter zwidth = 16; parameter shift = 1; input clock; input reset; input enable; input [bitwidth-1:0] xi,yi; input [zwidth-1:0] zi; input [zwidth-1:0] constant; output [bitwidth-1:0] xo,yo; output [zwidth-1:0] zo; wire z_is_pos = ~zi[zwidth-1]; reg [bitwidth-1:0] xo,yo; reg [zwidth-1:0] zo; always @(posedge clock) if(reset) begin xo <= #1 0; yo <= #1 0; zo <= #1 0; end else if(enable) begin xo <= #1 z_is_pos ? xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} : xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]}; yo <= #1 z_is_pos ? yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} : yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]}; zo <= #1 z_is_pos ? zi - constant : zi + constant; end endmodule
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); parameter bitwidth = 16; parameter zwidth = 16; parameter shift = 1; input clock; input reset; input enable; input [bitwidth-1:0] xi,yi; input [zwidth-1:0] zi; input [zwidth-1:0] constant; output [bitwidth-1:0] xo,yo; output [zwidth-1:0] zo; wire z_is_pos = ~zi[zwidth-1]; reg [bitwidth-1:0] xo,yo; reg [zwidth-1:0] zo; always @(posedge clock) if(reset) begin xo <= #1 0; yo <= #1 0; zo <= #1 0; end else if(enable) begin xo <= #1 z_is_pos ? xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} : xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]}; yo <= #1 z_is_pos ? yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} : yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]}; zo <= #1 z_is_pos ? zi - constant : zi + constant; end endmodule
module axi_crossbar_v2_1_wdata_router # ( parameter C_FAMILY = "none", // FPGA Family. parameter integer C_WMESG_WIDTH = 1, // Width of all data signals parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports. parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT. parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG. ) ( // System Signals input wire ACLK, input wire ARESET, // Slave Data Ports input wire [C_WMESG_WIDTH-1:0] S_WMESG, input wire S_WLAST, input wire S_WVALID, output wire S_WREADY, // Master Data Ports output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots output wire M_WLAST, // Broadcast to all MI-slots output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot // Address Arbiter Ports input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command input wire S_AVALID, output wire S_AREADY ); localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32 // Decode select input to 1-hot function [C_NUM_MASTER_SLOTS-1:0] f_decoder ( input [C_SELECT_WIDTH-1:0] sel ); integer i; begin for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin f_decoder[i] = (sel == i); end end endfunction //--------------------------------------------------------------------------- // Internal signal declarations //--------------------------------------------------------------------------- wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot; wire [C_SELECT_WIDTH-1:0] m_select_enc; wire m_avalid; wire m_aready; //--------------------------------------------------------------------------- // Router //--------------------------------------------------------------------------- // SI-side write command queue axi_data_fifo_v2_1_axic_reg_srl_fifo # ( .C_FAMILY (C_FAMILY), .C_FIFO_WIDTH (C_SELECT_WIDTH), .C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG), .C_USE_FULL (1) ) wrouter_aw_fifo ( .ACLK (ACLK), .ARESET (ARESET), .S_MESG (S_ASELECT), .S_VALID (S_AVALID), .S_READY (S_AREADY), .M_MESG (m_select_enc), .M_VALID (m_avalid), .M_READY (m_aready) ); assign m_select_hot = f_decoder(m_select_enc); // W-channel payload and LAST are broadcast to all MI-slot's W-mux assign M_WMESG = S_WMESG; assign M_WLAST = S_WLAST; // Assert m_aready when last beat acknowledged by slave assign m_aready = m_avalid & S_WVALID & S_WLAST & (\|(M_WREADY & m_select_hot)); // M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS). // The slot selected by the head of the queue (m_select_enc) is enabled. assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot; // S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc). assign S_WREADY = m_avalid & (\|(M_WREADY & m_select_hot)); endmodule
module cic_dec_shifter(rate,signal_in,signal_out); parameter bw = 16; parameter maxbitgain = 28; input [7:0] rate; input wire [bw+maxbitgain-1:0] signal_in; output reg [bw-1:0] signal_out; function [4:0] bitgain; input [7:0] rate; case(rate) // Exact Cases -- Nlog2(rate) 8'd4 : bitgain = 8; 8'd8 : bitgain = 12; 8'd16 : bitgain = 16; 8'd32 : bitgain = 20; 8'd64 : bitgain = 24; 8'd128 : bitgain = 28; // Nearest without overflow -- ceil(Nlog2(rate)) 8'd5 : bitgain = 10; 8'd6 : bitgain = 11; 8'd7 : bitgain = 12; 8'd9 : bitgain = 13; 8'd10,8'd11 : bitgain = 14; 8'd12,8'd13 : bitgain = 15; 8'd14,8'd15 : bitgain = 16; 8'd17,8'd18,8'd19 : bitgain = 17; 8'd20,8'd21,8'd22 : bitgain = 18; 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; default : bitgain = 28; endcase // case(rate) endfunction // bitgain wire [4:0] shift = bitgain(rate+1); // We should be able to do this, but can't .... // assign signal_out = signal_in[shift+bw-1:shift]; always @* case(shift) 5'd8 : signal_out = signal_in[8+bw-1:8]; 5'd10 : signal_out = signal_in[10+bw-1:10]; 5'd11 : signal_out = signal_in[11+bw-1:11]; 5'd12 : signal_out = signal_in[12+bw-1:12]; 5'd13 : signal_out = signal_in[13+bw-1:13]; 5'd14 : signal_out = signal_in[14+bw-1:14]; 5'd15 : signal_out = signal_in[15+bw-1:15]; 5'd16 : signal_out = signal_in[16+bw-1:16]; 5'd17 : signal_out = signal_in[17+bw-1:17]; 5'd18 : signal_out = signal_in[18+bw-1:18]; 5'd19 : signal_out = signal_in[19+bw-1:19]; 5'd20 : signal_out = signal_in[20+bw-1:20]; 5'd21 : signal_out = signal_in[21+bw-1:21]; 5'd22 : signal_out = signal_in[22+bw-1:22]; 5'd23 : signal_out = signal_in[23+bw-1:23]; 5'd24 : signal_out = signal_in[24+bw-1:24]; 5'd25 : signal_out = signal_in[25+bw-1:25]; 5'd26 : signal_out = signal_in[26+bw-1:26]; 5'd27 : signal_out = signal_in[27+bw-1:27]; 5'd28 : signal_out = signal_in[28+bw-1:28]; default : signal_out = signal_in[28+bw-1:28]; endcase // case(shift) endmodule
module cic_dec_shifter(rate,signal_in,signal_out); parameter bw = 16; parameter maxbitgain = 28; input [7:0] rate; input wire [bw+maxbitgain-1:0] signal_in; output reg [bw-1:0] signal_out; function [4:0] bitgain; input [7:0] rate; case(rate) // Exact Cases -- Nlog2(rate) 8'd4 : bitgain = 8; 8'd8 : bitgain = 12; 8'd16 : bitgain = 16; 8'd32 : bitgain = 20; 8'd64 : bitgain = 24; 8'd128 : bitgain = 28; // Nearest without overflow -- ceil(Nlog2(rate)) 8'd5 : bitgain = 10; 8'd6 : bitgain = 11; 8'd7 : bitgain = 12; 8'd9 : bitgain = 13; 8'd10,8'd11 : bitgain = 14; 8'd12,8'd13 : bitgain = 15; 8'd14,8'd15 : bitgain = 16; 8'd17,8'd18,8'd19 : bitgain = 17; 8'd20,8'd21,8'd22 : bitgain = 18; 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; default : bitgain = 28; endcase // case(rate) endfunction // bitgain wire [4:0] shift = bitgain(rate+1); // We should be able to do this, but can't .... // assign signal_out = signal_in[shift+bw-1:shift]; always @* case(shift) 5'd8 : signal_out = signal_in[8+bw-1:8]; 5'd10 : signal_out = signal_in[10+bw-1:10]; 5'd11 : signal_out = signal_in[11+bw-1:11]; 5'd12 : signal_out = signal_in[12+bw-1:12]; 5'd13 : signal_out = signal_in[13+bw-1:13]; 5'd14 : signal_out = signal_in[14+bw-1:14]; 5'd15 : signal_out = signal_in[15+bw-1:15]; 5'd16 : signal_out = signal_in[16+bw-1:16]; 5'd17 : signal_out = signal_in[17+bw-1:17]; 5'd18 : signal_out = signal_in[18+bw-1:18]; 5'd19 : signal_out = signal_in[19+bw-1:19]; 5'd20 : signal_out = signal_in[20+bw-1:20]; 5'd21 : signal_out = signal_in[21+bw-1:21]; 5'd22 : signal_out = signal_in[22+bw-1:22]; 5'd23 : signal_out = signal_in[23+bw-1:23]; 5'd24 : signal_out = signal_in[24+bw-1:24]; 5'd25 : signal_out = signal_in[25+bw-1:25]; 5'd26 : signal_out = signal_in[26+bw-1:26]; 5'd27 : signal_out = signal_in[27+bw-1:27]; 5'd28 : signal_out = signal_in[28+bw-1:28]; default : signal_out = signal_in[28+bw-1:28]; endcase // case(shift) endmodule
module cic_dec_shifter(rate,signal_in,signal_out); parameter bw = 16; parameter maxbitgain = 28; input [7:0] rate; input wire [bw+maxbitgain-1:0] signal_in; output reg [bw-1:0] signal_out; function [4:0] bitgain; input [7:0] rate; case(rate) // Exact Cases -- Nlog2(rate) 8'd4 : bitgain = 8; 8'd8 : bitgain = 12; 8'd16 : bitgain = 16; 8'd32 : bitgain = 20; 8'd64 : bitgain = 24; 8'd128 : bitgain = 28; // Nearest without overflow -- ceil(Nlog2(rate)) 8'd5 : bitgain = 10; 8'd6 : bitgain = 11; 8'd7 : bitgain = 12; 8'd9 : bitgain = 13; 8'd10,8'd11 : bitgain = 14; 8'd12,8'd13 : bitgain = 15; 8'd14,8'd15 : bitgain = 16; 8'd17,8'd18,8'd19 : bitgain = 17; 8'd20,8'd21,8'd22 : bitgain = 18; 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; default : bitgain = 28; endcase // case(rate) endfunction // bitgain wire [4:0] shift = bitgain(rate+1); // We should be able to do this, but can't .... // assign signal_out = signal_in[shift+bw-1:shift]; always @* case(shift) 5'd8 : signal_out = signal_in[8+bw-1:8]; 5'd10 : signal_out = signal_in[10+bw-1:10]; 5'd11 : signal_out = signal_in[11+bw-1:11]; 5'd12 : signal_out = signal_in[12+bw-1:12]; 5'd13 : signal_out = signal_in[13+bw-1:13]; 5'd14 : signal_out = signal_in[14+bw-1:14]; 5'd15 : signal_out = signal_in[15+bw-1:15]; 5'd16 : signal_out = signal_in[16+bw-1:16]; 5'd17 : signal_out = signal_in[17+bw-1:17]; 5'd18 : signal_out = signal_in[18+bw-1:18]; 5'd19 : signal_out = signal_in[19+bw-1:19]; 5'd20 : signal_out = signal_in[20+bw-1:20]; 5'd21 : signal_out = signal_in[21+bw-1:21]; 5'd22 : signal_out = signal_in[22+bw-1:22]; 5'd23 : signal_out = signal_in[23+bw-1:23]; 5'd24 : signal_out = signal_in[24+bw-1:24]; 5'd25 : signal_out = signal_in[25+bw-1:25]; 5'd26 : signal_out = signal_in[26+bw-1:26]; 5'd27 : signal_out = signal_in[27+bw-1:27]; 5'd28 : signal_out = signal_in[28+bw-1:28]; default : signal_out = signal_in[28+bw-1:28]; endcase // case(shift) endmodule
module cic_dec_shifter(rate,signal_in,signal_out); parameter bw = 16; parameter maxbitgain = 28; input [7:0] rate; input wire [bw+maxbitgain-1:0] signal_in; output reg [bw-1:0] signal_out; function [4:0] bitgain; input [7:0] rate; case(rate) // Exact Cases -- Nlog2(rate) 8'd4 : bitgain = 8; 8'd8 : bitgain = 12; 8'd16 : bitgain = 16; 8'd32 : bitgain = 20; 8'd64 : bitgain = 24; 8'd128 : bitgain = 28; // Nearest without overflow -- ceil(Nlog2(rate)) 8'd5 : bitgain = 10; 8'd6 : bitgain = 11; 8'd7 : bitgain = 12; 8'd9 : bitgain = 13; 8'd10,8'd11 : bitgain = 14; 8'd12,8'd13 : bitgain = 15; 8'd14,8'd15 : bitgain = 16; 8'd17,8'd18,8'd19 : bitgain = 17; 8'd20,8'd21,8'd22 : bitgain = 18; 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; default : bitgain = 28; endcase // case(rate) endfunction // bitgain wire [4:0] shift = bitgain(rate+1); // We should be able to do this, but can't .... // assign signal_out = signal_in[shift+bw-1:shift]; always @* case(shift) 5'd8 : signal_out = signal_in[8+bw-1:8]; 5'd10 : signal_out = signal_in[10+bw-1:10]; 5'd11 : signal_out = signal_in[11+bw-1:11]; 5'd12 : signal_out = signal_in[12+bw-1:12]; 5'd13 : signal_out = signal_in[13+bw-1:13]; 5'd14 : signal_out = signal_in[14+bw-1:14]; 5'd15 : signal_out = signal_in[15+bw-1:15]; 5'd16 : signal_out = signal_in[16+bw-1:16]; 5'd17 : signal_out = signal_in[17+bw-1:17]; 5'd18 : signal_out = signal_in[18+bw-1:18]; 5'd19 : signal_out = signal_in[19+bw-1:19]; 5'd20 : signal_out = signal_in[20+bw-1:20]; 5'd21 : signal_out = signal_in[21+bw-1:21]; 5'd22 : signal_out = signal_in[22+bw-1:22]; 5'd23 : signal_out = signal_in[23+bw-1:23]; 5'd24 : signal_out = signal_in[24+bw-1:24]; 5'd25 : signal_out = signal_in[25+bw-1:25]; 5'd26 : signal_out = signal_in[26+bw-1:26]; 5'd27 : signal_out = signal_in[27+bw-1:27]; 5'd28 : signal_out = signal_in[28+bw-1:28]; default : signal_out = signal_in[28+bw-1:28]; endcase // case(shift) endmodule
module mac (input clock, input reset, input enable, input clear, input signed [15:0] x, input signed [15:0] y, input [7:0] shift, output [15:0] z ); reg signed [30:0] product; reg signed [39:0] z_int; reg signed [15:0] z_shift; reg enable_d1; always @(posedge clock) enable_d1 <= #1 enable; always @(posedge clock) if(reset \| clear) z_int <= #1 40'd0; else if(enable_d1) z_int <= #1 z_int + {{9{product[30]}},product}; always @(posedge clock) product <= #1 xy; always @ // FIXME full case? parallel case? case(shift) //8'd0 : z_shift <= z_int[39:24]; //8'd1 : z_shift <= z_int[38:23]; //8'd2 : z_shift <= z_int[37:22]; //8'd3 : z_shift <= z_int[36:21]; //8'd4 : z_shift <= z_int[35:20]; //8'd5 : z_shift <= z_int[34:19]; 8'd6 : z_shift <= z_int[33:18]; 8'd7 : z_shift <= z_int[32:17]; 8'd8 : z_shift <= z_int[31:16]; 8'd9 : z_shift <= z_int[30:15]; 8'd10 : z_shift <= z_int[29:14]; 8'd11 : z_shift <= z_int[28:13]; //8'd12 : z_shift <= z_int[27:12]; //8'd13 : z_shift <= z_int[26:11]; //8'd14 : z_shift <= z_int[25:10]; //8'd15 : z_shift <= z_int[24:9]; //8'd16 : z_shift <= z_int[23:8]; //8'd17 : z_shift <= z_int[22:7]; //8'd18 : z_shift <= z_int[21:6]; //8'd19 : z_shift <= z_int[20:5]; //8'd20 : z_shift <= z_int[19:4]; //8'd21 : z_shift <= z_int[18:3]; //8'd22 : z_shift <= z_int[17:2]; //8'd23 : z_shift <= z_int[16:1]; //8'd24 : z_shift <= z_int[15:0]; default : z_shift <= z_int[15:0]; endcase // case(shift) // FIXME do we need to saturate? //assign z = z_shift; assign z = z_int[15:0]; endmodule
module mac (input clock, input reset, input enable, input clear, input signed [15:0] x, input signed [15:0] y, input [7:0] shift, output [15:0] z ); reg signed [30:0] product; reg signed [39:0] z_int; reg signed [15:0] z_shift; reg enable_d1; always @(posedge clock) enable_d1 <= #1 enable; always @(posedge clock) if(reset \| clear) z_int <= #1 40'd0; else if(enable_d1) z_int <= #1 z_int + {{9{product[30]}},product}; always @(posedge clock) product <= #1 xy; always @ // FIXME full case? parallel case? case(shift) //8'd0 : z_shift <= z_int[39:24]; //8'd1 : z_shift <= z_int[38:23]; //8'd2 : z_shift <= z_int[37:22]; //8'd3 : z_shift <= z_int[36:21]; //8'd4 : z_shift <= z_int[35:20]; //8'd5 : z_shift <= z_int[34:19]; 8'd6 : z_shift <= z_int[33:18]; 8'd7 : z_shift <= z_int[32:17]; 8'd8 : z_shift <= z_int[31:16]; 8'd9 : z_shift <= z_int[30:15]; 8'd10 : z_shift <= z_int[29:14]; 8'd11 : z_shift <= z_int[28:13]; //8'd12 : z_shift <= z_int[27:12]; //8'd13 : z_shift <= z_int[26:11]; //8'd14 : z_shift <= z_int[25:10]; //8'd15 : z_shift <= z_int[24:9]; //8'd16 : z_shift <= z_int[23:8]; //8'd17 : z_shift <= z_int[22:7]; //8'd18 : z_shift <= z_int[21:6]; //8'd19 : z_shift <= z_int[20:5]; //8'd20 : z_shift <= z_int[19:4]; //8'd21 : z_shift <= z_int[18:3]; //8'd22 : z_shift <= z_int[17:2]; //8'd23 : z_shift <= z_int[16:1]; //8'd24 : z_shift <= z_int[15:0]; default : z_shift <= z_int[15:0]; endcase // case(shift) // FIXME do we need to saturate? //assign z = z_shift; assign z = z_int[15:0]; endmodule
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr); parameter depth = 4; parameter width = 16; parameter size = 16; input wclk; input [width-1:0] wdata; input [depth-1:0] waddr; input wen; input rclk; output reg [width-1:0] rdata; input [depth-1:0] raddr; reg [width-1:0] ram [0:size-1]; always @(posedge wclk) if(wen) ram[waddr] <= #1 wdata; always @(posedge rclk) rdata <= #1 ram[raddr]; endmodule
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr); parameter depth = 4; parameter width = 16; parameter size = 16; input wclk; input [width-1:0] wdata; input [depth-1:0] waddr; input wen; input rclk; output reg [width-1:0] rdata; input [depth-1:0] raddr; reg [width-1:0] ram [0:size-1]; always @(posedge wclk) if(wen) ram[waddr] <= #1 wdata; always @(posedge rclk) rdata <= #1 ram[raddr]; endmodule
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr); parameter depth = 4; parameter width = 16; parameter size = 16; input wclk; input [width-1:0] wdata; input [depth-1:0] waddr; input wen; input rclk; output reg [width-1:0] rdata; input [depth-1:0] raddr; reg [width-1:0] ram [0:size-1]; always @(posedge wclk) if(wen) ram[waddr] <= #1 wdata; always @(posedge rclk) rdata <= #1 ram[raddr]; endmodule
module mylpm_addsub ( add_sub, dataa, datab, clock, result); input add_sub; input [15:0] dataa; input [15:0] datab; input clock; output [15:0] result; endmodule
module mylpm_addsub ( add_sub, dataa, datab, clock, result); input add_sub; input [15:0] dataa; input [15:0] datab; input clock; output [15:0] result; endmodule
module clk_doubler ( inclk0, c0); input inclk0; output c0; wire [5:0] sub_wire0; wire [0:0] sub_wire4 = 1'h0; wire [0:0] sub_wire1 = sub_wire0[0:0]; wire c0 = sub_wire1; wire sub_wire2 = inclk0; wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; altpll altpll_component ( .inclk (sub_wire3), .clk (sub_wire0) // synopsys translate_off , .activeclock (), .areset (), .clkbad (), .clkena (), .clkloss (), .clkswitch (), .enable0 (), .enable1 (), .extclk (), .extclkena (), .fbin (), .locked (), .pfdena (), .pllena (), .scanaclr (), .scanclk (), .scandata (), .scandataout (), .scandone (), .scanread (), .scanwrite (), .sclkout0 (), .sclkout1 () // synopsys translate_on ); defparam altpll_component.clk0_duty_cycle = 50, altpll_component.lpm_type = "altpll", altpll_component.clk0_multiply_by = 2, altpll_component.inclk0_input_frequency = 15625, altpll_component.clk0_divide_by = 1, altpll_component.pll_type = "AUTO", altpll_component.intended_device_family = "Cyclone", altpll_component.operation_mode = "NORMAL", altpll_component.compensate_clock = "CLK0", altpll_component.clk0_phase_shift = "0"; endmodule
module clk_doubler ( inclk0, c0); input inclk0; output c0; wire [5:0] sub_wire0; wire [0:0] sub_wire4 = 1'h0; wire [0:0] sub_wire1 = sub_wire0[0:0]; wire c0 = sub_wire1; wire sub_wire2 = inclk0; wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; altpll altpll_component ( .inclk (sub_wire3), .clk (sub_wire0) // synopsys translate_off , .activeclock (), .areset (), .clkbad (), .clkena (), .clkloss (), .clkswitch (), .enable0 (), .enable1 (), .extclk (), .extclkena (), .fbin (), .locked (), .pfdena (), .pllena (), .scanaclr (), .scanclk (), .scandata (), .scandataout (), .scandone (), .scanread (), .scanwrite (), .sclkout0 (), .sclkout1 () // synopsys translate_on ); defparam altpll_component.clk0_duty_cycle = 50, altpll_component.lpm_type = "altpll", altpll_component.clk0_multiply_by = 2, altpll_component.inclk0_input_frequency = 15625, altpll_component.clk0_divide_by = 1, altpll_component.pll_type = "AUTO", altpll_component.intended_device_family = "Cyclone", altpll_component.operation_mode = "NORMAL", altpll_component.compensate_clock = "CLK0", altpll_component.clk0_phase_shift = "0"; endmodule
module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; endmodule
module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; endmodule
module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; endmodule
module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; endmodule
module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; endmodule
module tx_chain_hb (input clock, input reset, input enable, input wire [7:0] interp_rate, input sample_strobe, input interpolator_strobe, input hb_strobe, input wire [31:0] freq, input wire [15:0] i_in, input wire [15:0] q_in, output wire [15:0] i_out, output wire [15:0] q_out, output wire [15:0] debug, output [15:0] hb_i_out ); assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe}; wire [15:0] bb_i, bb_q; wire [15:0] hb_i_out, hb_q_out; halfband_interp hb (.clock(clock),.reset(reset),.enable(enable), .strobe_in(interpolator_strobe),.strobe_out(hb_strobe), .signal_in_i(i_in),.signal_in_q(q_in), .signal_out_i(hb_i_out),.signal_out_q(hb_q_out), .debug(debug[12:0])); cic_interp cic_interp_i ( .clock(clock),.reset(reset),.enable(enable), .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), .signal_in(hb_i_out),.signal_out(bb_i) ); cic_interp cic_interp_q ( .clock(clock),.reset(reset),.enable(enable), .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), .signal_in(hb_q_out),.signal_out(bb_q) ); `define NOCORDIC_TX `ifdef NOCORDIC_TX assign i_out = bb_i; assign q_out = bb_q; `else wire [31:0] phase; phase_acc phase_acc_tx (.clk(clock),.reset(reset),.enable(enable), .strobe(sample_strobe),.freq(freq),.phase(phase) ); cordic tx_cordic_0 ( .clock(clock),.reset(reset),.enable(sample_strobe), .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), .xo(i_out),.yo(q_out),.zo() ); `endif endmodule
module tx_chain_hb (input clock, input reset, input enable, input wire [7:0] interp_rate, input sample_strobe, input interpolator_strobe, input hb_strobe, input wire [31:0] freq, input wire [15:0] i_in, input wire [15:0] q_in, output wire [15:0] i_out, output wire [15:0] q_out, output wire [15:0] debug, output [15:0] hb_i_out ); assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe}; wire [15:0] bb_i, bb_q; wire [15:0] hb_i_out, hb_q_out; halfband_interp hb (.clock(clock),.reset(reset),.enable(enable), .strobe_in(interpolator_strobe),.strobe_out(hb_strobe), .signal_in_i(i_in),.signal_in_q(q_in), .signal_out_i(hb_i_out),.signal_out_q(hb_q_out), .debug(debug[12:0])); cic_interp cic_interp_i ( .clock(clock),.reset(reset),.enable(enable), .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), .signal_in(hb_i_out),.signal_out(bb_i) ); cic_interp cic_interp_q ( .clock(clock),.reset(reset),.enable(enable), .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), .signal_in(hb_q_out),.signal_out(bb_q) ); `define NOCORDIC_TX `ifdef NOCORDIC_TX assign i_out = bb_i; assign q_out = bb_q; `else wire [31:0] phase; phase_acc phase_acc_tx (.clk(clock),.reset(reset),.enable(enable), .strobe(sample_strobe),.freq(freq),.phase(phase) ); cordic tx_cordic_0 ( .clock(clock),.reset(reset),.enable(sample_strobe), .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), .xo(i_out),.yo(q_out),.zo() ); `endif endmodule
module tx_chain_hb (input clock, input reset, input enable, input wire [7:0] interp_rate, input sample_strobe, input interpolator_strobe, input hb_strobe, input wire [31:0] freq, input wire [15:0] i_in, input wire [15:0] q_in, output wire [15:0] i_out, output wire [15:0] q_out, output wire [15:0] debug, output [15:0] hb_i_out ); assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe}; wire [15:0] bb_i, bb_q; wire [15:0] hb_i_out, hb_q_out; halfband_interp hb (.clock(clock),.reset(reset),.enable(enable), .strobe_in(interpolator_strobe),.strobe_out(hb_strobe), .signal_in_i(i_in),.signal_in_q(q_in), .signal_out_i(hb_i_out),.signal_out_q(hb_q_out), .debug(debug[12:0])); cic_interp cic_interp_i ( .clock(clock),.reset(reset),.enable(enable), .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), .signal_in(hb_i_out),.signal_out(bb_i) ); cic_interp cic_interp_q ( .clock(clock),.reset(reset),.enable(enable), .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe), .signal_in(hb_q_out),.signal_out(bb_q) ); `define NOCORDIC_TX `ifdef NOCORDIC_TX assign i_out = bb_i; assign q_out = bb_q; `else wire [31:0] phase; phase_acc phase_acc_tx (.clk(clock),.reset(reset),.enable(enable), .strobe(sample_strobe),.freq(freq),.phase(phase) ); cordic tx_cordic_0 ( .clock(clock),.reset(reset),.enable(sample_strobe), .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), .xo(i_out),.yo(q_out),.zo() ); `endif endmodule
module ddr3_int_example_top ( // inputs: clock_source, global_reset_n, // outputs: mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, mem_dm, mem_dq, mem_dqs, mem_dqsn, mem_odt, mem_ras_n, mem_reset_n, mem_we_n, pnf, pnf_per_byte, test_complete, test_status ) ; output [ 12: 0] mem_addr; output [ 2: 0] mem_ba; output mem_cas_n; output [ 0: 0] mem_cke; inout [ 0: 0] mem_clk; inout [ 0: 0] mem_clk_n; output [ 0: 0] mem_cs_n; output [ 3: 0] mem_dm; inout [ 31: 0] mem_dq; inout [ 3: 0] mem_dqs; inout [ 3: 0] mem_dqsn; output [ 0: 0] mem_odt; output mem_ras_n; output mem_reset_n; output mem_we_n; output pnf; output [ 15: 0] pnf_per_byte; output test_complete; output [ 7: 0] test_status; input clock_source; input global_reset_n; wire [ 0: 0] cs_n; wire dll_reference_clk_sig; wire [ 5: 0] dqs_delay_ctrl_export_sig; wire local_burstbegin_sig; wire [ 12: 0] mem_addr; wire mem_aux_full_rate_clk; wire mem_aux_half_rate_clk; wire [ 2: 0] mem_ba; wire mem_cas_n; wire [ 0: 0] mem_cke; wire [ 0: 0] mem_clk; wire [ 0: 0] mem_clk_n; wire [ 0: 0] mem_cs_n; wire [ 3: 0] mem_dm; wire [ 31: 0] mem_dq; wire [ 3: 0] mem_dqs; wire [ 3: 0] mem_dqsn; wire [ 23: 0] mem_local_addr; wire [ 15: 0] mem_local_be; wire [ 9: 0] mem_local_col_addr; wire mem_local_cs_addr; wire [127: 0] mem_local_rdata; wire mem_local_rdata_valid; wire mem_local_read_req; wire mem_local_ready; wire [ 5: 0] mem_local_size; wire [127: 0] mem_local_wdata; wire mem_local_write_req; wire [ 0: 0] mem_odt; wire mem_ras_n; wire mem_reset_n; wire mem_we_n; wire phy_clk; wire pnf; wire [ 15: 0] pnf_per_byte; wire reset_phy_clk_n; wire test_complete; wire [ 7: 0] test_status; wire tie_high; wire tie_low; // // assign mem_cs_n = cs_n; //<< END MEGAWIZARD INSERT MODULE assign tie_high = 1'b1; assign tie_low = 1'b0; //<< START MEGAWIZARD INSERT WRAPPER_NAME ddr3_int ddr3_int_inst ( .aux_full_rate_clk (mem_aux_full_rate_clk), .aux_half_rate_clk (mem_aux_half_rate_clk), .dll_reference_clk (dll_reference_clk_sig), .dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig), .global_reset_n (global_reset_n), .local_address (mem_local_addr), .local_be (mem_local_be), .local_burstbegin (local_burstbegin_sig), .local_init_done (), .local_rdata (mem_local_rdata), .local_rdata_valid (mem_local_rdata_valid), .local_read_req (mem_local_read_req), .local_ready (mem_local_ready), .local_refresh_ack (), .local_size (mem_local_size), .local_wdata (mem_local_wdata), .local_wdata_req (), .local_write_req (mem_local_write_req), .mem_addr (mem_addr[12 : 0]), .mem_ba (mem_ba), .mem_cas_n (mem_cas_n), .mem_cke (mem_cke), .mem_clk (mem_clk), .mem_clk_n (mem_clk_n), .mem_cs_n (cs_n), .mem_dm (mem_dm[3 : 0]), .mem_dq (mem_dq), .mem_dqs (mem_dqs[3 : 0]), .mem_dqsn (mem_dqsn[3 : 0]), .mem_odt (mem_odt), .mem_ras_n (mem_ras_n), .mem_reset_n (mem_reset_n), .mem_we_n (mem_we_n), .phy_clk (phy_clk), .pll_ref_clk (clock_source), .reset_phy_clk_n (reset_phy_clk_n), .reset_request_n (), .soft_reset_n (tie_high) ); //<< END MEGAWIZARD INSERT WRAPPER_NAME //<< START MEGAWIZARD INSERT CS_ADDR_MAP //connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2]; //<< END MEGAWIZARD INSERT CS_ADDR_MAP //<< START MEGAWIZARD INSERT EXAMPLE_DRIVER //Self-test, synthesisable code to exercise the DDR SDRAM Controller ddr3_int_example_driver driver ( .clk (phy_clk), .local_bank_addr (mem_local_addr[23 : 21]), .local_be (mem_local_be), .local_burstbegin (local_burstbegin_sig), .local_col_addr (mem_local_col_addr), .local_cs_addr (mem_local_cs_addr), .local_rdata (mem_local_rdata), .local_rdata_valid (mem_local_rdata_valid), .local_read_req (mem_local_read_req), .local_ready (mem_local_ready), .local_row_addr (mem_local_addr[20 : 8]), .local_size (mem_local_size), .local_wdata (mem_local_wdata), .local_write_req (mem_local_write_req), .pnf_per_byte (pnf_per_byte[15 : 0]), .pnf_persist (pnf), .reset_n (reset_phy_clk_n), .test_complete (test_complete), .test_status (test_status) ); //<< END MEGAWIZARD INSERT EXAMPLE_DRIVER //<< START MEGAWIZARD INSERT DLL //<< END MEGAWIZARD INSERT DLL //<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE //<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE //<< start europa endmodule
module cic_decim ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); parameter bw = 16; parameter N = 4; parameter log2_of_max_rate = 7; parameter maxbitgain = N * log2_of_max_rate; input clock; input reset; input enable; input [7:0] rate; input strobe_in,strobe_out; input [bw-1:0] signal_in; output [bw-1:0] signal_out; reg [bw-1:0] signal_out; wire [bw-1:0] signal_out_unreg; wire [bw+maxbitgain-1:0] signal_in_ext; reg [bw+maxbitgain-1:0] integrator [0:N-1]; reg [bw+maxbitgain-1:0] differentiator [0:N-1]; reg [bw+maxbitgain-1:0] pipeline [0:N-1]; reg [bw+maxbitgain-1:0] sampler; integer i; sign_extend #(bw,bw+maxbitgain) ext_input (.in(signal_in),.out(signal_in_ext)); always @(posedge clock) if(reset) for(i=0;i<N;i=i+1) integrator[i] <= #1 0; else if (enable && strobe_in) begin integrator[0] <= #1 integrator[0] + signal_in_ext; for(i=1;i<N;i=i+1) integrator[i] <= #1 integrator[i] + integrator[i-1]; end always @(posedge clock) if(reset) begin sampler <= #1 0; for(i=0;i<N;i=i+1) begin pipeline[i] <= #1 0; differentiator[i] <= #1 0; end end else if (enable && strobe_out) begin sampler <= #1 integrator[N-1]; differentiator[0] <= #1 sampler; pipeline[0] <= #1 sampler - differentiator[0]; for(i=1;i<N;i=i+1) begin differentiator[i] <= #1 pipeline[i-1]; pipeline[i] <= #1 pipeline[i-1] - differentiator[i]; end end // if (enable && strobe_out) wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1]; cic_dec_shifter #(bw) cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg); always @(posedge clock) signal_out <= #1 signal_out_unreg; endmodule
module cic_decim ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); parameter bw = 16; parameter N = 4; parameter log2_of_max_rate = 7; parameter maxbitgain = N * log2_of_max_rate; input clock; input reset; input enable; input [7:0] rate; input strobe_in,strobe_out; input [bw-1:0] signal_in; output [bw-1:0] signal_out; reg [bw-1:0] signal_out; wire [bw-1:0] signal_out_unreg; wire [bw+maxbitgain-1:0] signal_in_ext; reg [bw+maxbitgain-1:0] integrator [0:N-1]; reg [bw+maxbitgain-1:0] differentiator [0:N-1]; reg [bw+maxbitgain-1:0] pipeline [0:N-1]; reg [bw+maxbitgain-1:0] sampler; integer i; sign_extend #(bw,bw+maxbitgain) ext_input (.in(signal_in),.out(signal_in_ext)); always @(posedge clock) if(reset) for(i=0;i<N;i=i+1) integrator[i] <= #1 0; else if (enable && strobe_in) begin integrator[0] <= #1 integrator[0] + signal_in_ext; for(i=1;i<N;i=i+1) integrator[i] <= #1 integrator[i] + integrator[i-1]; end always @(posedge clock) if(reset) begin sampler <= #1 0; for(i=0;i<N;i=i+1) begin pipeline[i] <= #1 0; differentiator[i] <= #1 0; end end else if (enable && strobe_out) begin sampler <= #1 integrator[N-1]; differentiator[0] <= #1 sampler; pipeline[0] <= #1 sampler - differentiator[0]; for(i=1;i<N;i=i+1) begin differentiator[i] <= #1 pipeline[i-1]; pipeline[i] <= #1 pipeline[i-1] - differentiator[i]; end end // if (enable && strobe_out) wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1]; cic_dec_shifter #(bw) cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg); always @(posedge clock) signal_out <= #1 signal_out_unreg; endmodule
module cic_decim ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); parameter bw = 16; parameter N = 4; parameter log2_of_max_rate = 7; parameter maxbitgain = N * log2_of_max_rate; input clock; input reset; input enable; input [7:0] rate; input strobe_in,strobe_out; input [bw-1:0] signal_in; output [bw-1:0] signal_out; reg [bw-1:0] signal_out; wire [bw-1:0] signal_out_unreg; wire [bw+maxbitgain-1:0] signal_in_ext; reg [bw+maxbitgain-1:0] integrator [0:N-1]; reg [bw+maxbitgain-1:0] differentiator [0:N-1]; reg [bw+maxbitgain-1:0] pipeline [0:N-1]; reg [bw+maxbitgain-1:0] sampler; integer i; sign_extend #(bw,bw+maxbitgain) ext_input (.in(signal_in),.out(signal_in_ext)); always @(posedge clock) if(reset) for(i=0;i<N;i=i+1) integrator[i] <= #1 0; else if (enable && strobe_in) begin integrator[0] <= #1 integrator[0] + signal_in_ext; for(i=1;i<N;i=i+1) integrator[i] <= #1 integrator[i] + integrator[i-1]; end always @(posedge clock) if(reset) begin sampler <= #1 0; for(i=0;i<N;i=i+1) begin pipeline[i] <= #1 0; differentiator[i] <= #1 0; end end else if (enable && strobe_out) begin sampler <= #1 integrator[N-1]; differentiator[0] <= #1 sampler; pipeline[0] <= #1 sampler - differentiator[0]; for(i=1;i<N;i=i+1) begin differentiator[i] <= #1 pipeline[i-1]; pipeline[i] <= #1 pipeline[i-1] - differentiator[i]; end end // if (enable && strobe_out) wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1]; cic_dec_shifter #(bw) cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg); always @(posedge clock) signal_out <= #1 signal_out_unreg; endmodule
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used); parameter width=32; parameter depth=10; input reset; // Asynchronous input [width-1:0] data; input write; input wrclk; output [depth-1:0] wr_used; output [width-1:0] q; input read_ack; input rdclk; output [depth-1:0] rd_used; reg [depth-1:0] read_addr, write_addr, read_addr_gray, read_addr_gray_sync, write_addr_gray, write_addr_gray_sync; // Pseudo-dual-port RAM dpram #(.depth(10),.width(width),.size(1024)) fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write), .rclk(rdclk), .rdata(q),.raddr(read_addr) ); wire [depth-1:0] wag,rag; // Keep track of own side's pointer always @(posedge wrclk or posedge reset) if(reset) write_addr <= #1 0; else if(write) write_addr <= #1 write_addr + 1; always @(posedge rdclk or posedge reset) if(reset) read_addr <= #1 0; else if(read_ack) read_addr <= #1 read_addr + 1; // Convert own side pointer to gray bin2gray #(depth) write_b2g (write_addr,wag); bin2gray #(depth) read_b2g (read_addr,rag); // Latch it always @(posedge wrclk or posedge reset) if(reset) write_addr_gray <= #1 0; else write_addr_gray <= #1 wag; always @(posedge rdclk or posedge reset) if(reset) read_addr_gray <= #1 0; else read_addr_gray <= #1 rag; // Send it to other side and latch always @(posedge wrclk or posedge reset) if(reset) read_addr_gray_sync <= #1 0; else read_addr_gray_sync <= #1 read_addr_gray; always @(posedge rdclk or posedge reset) if(reset) write_addr_gray_sync <= #1 0; else write_addr_gray_sync <= #1 write_addr_gray; wire [depth-1:0] write_addr_sync, read_addr_sync; // Convert back to binary gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync); gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync); assign rd_used = write_addr_sync - read_addr; assign wr_used = write_addr - read_addr_sync; endmodule
module bin2gray(bin_val,gray_val); parameter width = 8; input [width-1:0] bin_val; output reg [width-1:0] gray_val; integer i; always @* begin gray_val[width-1] = bin_val[width-1]; for(i=0;i<width-1;i=i+1) gray_val[i] = bin_val[i] ^ bin_val[i+1]; end endmodule
module gray2bin(gray_val,bin_val); parameter width = 8; input [width-1:0] gray_val; output reg [width-1:0] bin_val; integer i; always @* begin bin_val[width-1] = gray_val[width-1]; for(i=width-2;i>=0;i=i-1) bin_val[i] = bin_val[i+1] ^ gray_val[i]; end endmodule
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used); parameter width=32; parameter depth=10; input reset; // Asynchronous input [width-1:0] data; input write; input wrclk; output [depth-1:0] wr_used; output [width-1:0] q; input read_ack; input rdclk; output [depth-1:0] rd_used; reg [depth-1:0] read_addr, write_addr, read_addr_gray, read_addr_gray_sync, write_addr_gray, write_addr_gray_sync; // Pseudo-dual-port RAM dpram #(.depth(10),.width(width),.size(1024)) fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write), .rclk(rdclk), .rdata(q),.raddr(read_addr) ); wire [depth-1:0] wag,rag; // Keep track of own side's pointer always @(posedge wrclk or posedge reset) if(reset) write_addr <= #1 0; else if(write) write_addr <= #1 write_addr + 1; always @(posedge rdclk or posedge reset) if(reset) read_addr <= #1 0; else if(read_ack) read_addr <= #1 read_addr + 1; // Convert own side pointer to gray bin2gray #(depth) write_b2g (write_addr,wag); bin2gray #(depth) read_b2g (read_addr,rag); // Latch it always @(posedge wrclk or posedge reset) if(reset) write_addr_gray <= #1 0; else write_addr_gray <= #1 wag; always @(posedge rdclk or posedge reset) if(reset) read_addr_gray <= #1 0; else read_addr_gray <= #1 rag; // Send it to other side and latch always @(posedge wrclk or posedge reset) if(reset) read_addr_gray_sync <= #1 0; else read_addr_gray_sync <= #1 read_addr_gray; always @(posedge rdclk or posedge reset) if(reset) write_addr_gray_sync <= #1 0; else write_addr_gray_sync <= #1 write_addr_gray; wire [depth-1:0] write_addr_sync, read_addr_sync; // Convert back to binary gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync); gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync); assign rd_used = write_addr_sync - read_addr; assign wr_used = write_addr - read_addr_sync; endmodule
module bin2gray(bin_val,gray_val); parameter width = 8; input [width-1:0] bin_val; output reg [width-1:0] gray_val; integer i; always @* begin gray_val[width-1] = bin_val[width-1]; for(i=0;i<width-1;i=i+1) gray_val[i] = bin_val[i] ^ bin_val[i+1]; end endmodule
module gray2bin(gray_val,bin_val); parameter width = 8; input [width-1:0] gray_val; output reg [width-1:0] bin_val; integer i; always @* begin bin_val[width-1] = gray_val[width-1]; for(i=width-2;i>=0;i=i-1) bin_val[i] = bin_val[i+1] ^ gray_val[i]; end endmodule
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used); parameter width=32; parameter depth=10; input reset; // Asynchronous input [width-1:0] data; input write; input wrclk; output [depth-1:0] wr_used; output [width-1:0] q; input read_ack; input rdclk; output [depth-1:0] rd_used; reg [depth-1:0] read_addr, write_addr, read_addr_gray, read_addr_gray_sync, write_addr_gray, write_addr_gray_sync; // Pseudo-dual-port RAM dpram #(.depth(10),.width(width),.size(1024)) fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write), .rclk(rdclk), .rdata(q),.raddr(read_addr) ); wire [depth-1:0] wag,rag; // Keep track of own side's pointer always @(posedge wrclk or posedge reset) if(reset) write_addr <= #1 0; else if(write) write_addr <= #1 write_addr + 1; always @(posedge rdclk or posedge reset) if(reset) read_addr <= #1 0; else if(read_ack) read_addr <= #1 read_addr + 1; // Convert own side pointer to gray bin2gray #(depth) write_b2g (write_addr,wag); bin2gray #(depth) read_b2g (read_addr,rag); // Latch it always @(posedge wrclk or posedge reset) if(reset) write_addr_gray <= #1 0; else write_addr_gray <= #1 wag; always @(posedge rdclk or posedge reset) if(reset) read_addr_gray <= #1 0; else read_addr_gray <= #1 rag; // Send it to other side and latch always @(posedge wrclk or posedge reset) if(reset) read_addr_gray_sync <= #1 0; else read_addr_gray_sync <= #1 read_addr_gray; always @(posedge rdclk or posedge reset) if(reset) write_addr_gray_sync <= #1 0; else write_addr_gray_sync <= #1 write_addr_gray; wire [depth-1:0] write_addr_sync, read_addr_sync; // Convert back to binary gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync); gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync); assign rd_used = write_addr_sync - read_addr; assign wr_used = write_addr - read_addr_sync; endmodule
module bin2gray(bin_val,gray_val); parameter width = 8; input [width-1:0] bin_val; output reg [width-1:0] gray_val; integer i; always @* begin gray_val[width-1] = bin_val[width-1]; for(i=0;i<width-1;i=i+1) gray_val[i] = bin_val[i] ^ bin_val[i+1]; end endmodule
module gray2bin(gray_val,bin_val); parameter width = 8; input [width-1:0] gray_val; output reg [width-1:0] bin_val; integer i; always @* begin bin_val[width-1] = gray_val[width-1]; for(i=width-2;i>=0;i=i-1) bin_val[i] = bin_val[i+1] ^ gray_val[i]; end endmodule
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); parameter width = 32; parameter depth = 2048; //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req input [31:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [31:0] q; output rdfull; output rdempty; output [10:0] rdusedw; output wrfull; output wrempty; output [10:0] wrusedw; reg [width-1:0] mem [0:depth-1]; reg [7:0] rdptr; reg [7:0] wrptr; `ifdef rd_req reg [width-1:0] q; `else wire [width-1:0] q; `endif reg [10:0] rdusedw; reg [10:0] wrusedw; integer i; always @( aclr) begin wrptr <= #1 0; rdptr <= #1 0; for(i=0;i<depth;i=i+1) mem[i] <= #1 0; end always @(posedge wrclk) if(wrreq) begin wrptr <= #1 wrptr+1; mem[wrptr] <= #1 data; end always @(posedge rdclk) if(rdreq) begin rdptr <= #1 rdptr+1; `ifdef rd_req q <= #1 mem[rdptr]; `endif end `ifdef rd_req `else assign q = mem[rdptr]; `endif // Fix these always @(posedge wrclk) wrusedw <= #1 wrptr - rdptr; always @(posedge rdclk) rdusedw <= #1 wrptr - rdptr; assign wrempty = (wrusedw == 0); assign wrfull = (wrusedw == depth-1); assign rdempty = (rdusedw == 0); assign rdfull = (rdusedw == depth-1); endmodule
module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); parameter width = 32; parameter depth = 2048; //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req input [31:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [31:0] q; output rdfull; output rdempty; output [10:0] rdusedw; output wrfull; output wrempty; output [10:0] wrusedw; reg [width-1:0] mem [0:depth-1]; reg [7:0] rdptr; reg [7:0] wrptr; `ifdef rd_req reg [width-1:0] q; `else wire [width-1:0] q; `endif reg [10:0] rdusedw; reg [10:0] wrusedw; integer i; always @( aclr) begin wrptr <= #1 0; rdptr <= #1 0; for(i=0;i<depth;i=i+1) mem[i] <= #1 0; end always @(posedge wrclk) if(wrreq) begin wrptr <= #1 wrptr+1; mem[wrptr] <= #1 data; end always @(posedge rdclk) if(rdreq) begin rdptr <= #1 rdptr+1; `ifdef rd_req q <= #1 mem[rdptr]; `endif end `ifdef rd_req `else assign q = mem[rdptr]; `endif // Fix these always @(posedge wrclk) wrusedw <= #1 wrptr - rdptr; always @(posedge rdclk) rdusedw <= #1 wrptr - rdptr; assign wrempty = (wrusedw == 0); assign wrfull = (wrusedw == depth-1); assign rdempty = (rdusedw == 0); assign rdfull = (rdusedw == depth-1); endmodule
module gen_sync ( input clock, input reset, input enable, input [7:0] rate, output wire sync ); // parameter width = 8; reg [7:0] counter; assign sync = \|(((rate+1)>>1)& counter); always @(posedge clock) if(reset \|\| ~enable) counter <= #1 0; else if(counter == rate) counter <= #1 0; else counter <= #1 counter + 8'd1; endmodule
module gen_sync ( input clock, input reset, input enable, input [7:0] rate, output wire sync ); // parameter width = 8; reg [7:0] counter; assign sync = \|(((rate+1)>>1)& counter); always @(posedge clock) if(reset \|\| ~enable) counter <= #1 0; else if(counter == rate) counter <= #1 0; else counter <= #1 counter + 8'd1; endmodule
module dspclkpll ( inclk0, c0, c1); input inclk0; output c0; output c1; endmodule
module addsub16 ( add_sub, dataa, datab, clock, aclr, clken, result)/* synthesis synthesis_clearbox = 1 */; input add_sub; input [15:0] dataa; input [15:0] datab; input clock; input aclr; input clken; output [15:0] result; endmodule
module addsub16 ( add_sub, dataa, datab, clock, aclr, clken, result)/* synthesis synthesis_clearbox = 1 */; input add_sub; input [15:0] dataa; input [15:0] datab; input clock; input aclr; input clken; output [15:0] result; endmodule
module addsub16 ( add_sub, dataa, datab, clock, aclr, clken, result)/* synthesis synthesis_clearbox = 1 */; input add_sub; input [15:0] dataa; input [15:0] datab; input clock; input aclr; input clken; output [15:0] result; endmodule
module add32 ( dataa, datab, result)/* synthesis synthesis_clearbox = 1 */; input [7:0] dataa; input [7:0] datab; output [7:0] result; endmodule
module add32 ( dataa, datab, result)/* synthesis synthesis_clearbox = 1 */; input [7:0] dataa; input [7:0] datab; output [7:0] result; endmodule
module add32 ( dataa, datab, result)/* synthesis synthesis_clearbox = 1 */; input [7:0] dataa; input [7:0] datab; output [7:0] result; endmodule
module accum32 ( data, clock, clken, aclr, result)/* synthesis synthesis_clearbox = 1 */; input [31:0] data; input clock; input clken; input aclr; output [31:0] result; endmodule
module addsub16_add_sub_gp9 ( aclr, add_sub, clken, clock, dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input aclr; input add_sub; input clken; input clock; input [15:0] dataa; input [15:0] datab; output [15:0] result; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [0:0] wire_add_sub_cella_10cout; wire [0:0] wire_add_sub_cella_11cout; wire [0:0] wire_add_sub_cella_12cout; wire [0:0] wire_add_sub_cella_13cout; wire [0:0] wire_add_sub_cella_14cout; wire [15:0] wire_add_sub_cella_dataa; wire [15:0] wire_add_sub_cella_datab; wire [15:0] wire_add_sub_cella_regout; wire wire_strx_lcell1_cout; stratix_lcell add_sub_cella_0 ( .aclr(aclr), .cin(wire_strx_lcell1_cout), .clk(clock), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[0:0])); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "96e8", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_1 ( .aclr(aclr), .cin(wire_add_sub_cella_0cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[1:1])); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "96e8", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_2 ( .aclr(aclr), .cin(wire_add_sub_cella_1cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[2:2])); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "96e8", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_3 ( .aclr(aclr), .cin(wire_add_sub_cella_2cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[3:3])); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "96e8", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_4 ( .aclr(aclr), .cin(wire_add_sub_cella_3cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[4:4])); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "96e8", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_5 ( .aclr(aclr), .cin(wire_add_sub_cella_4cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[5:5])); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "96e8", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_6 ( .aclr(aclr), .cin(wire_add_sub_cella_5cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[6:6])); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "96e8", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_7 ( .aclr(aclr), .cin(wire_add_sub_cella_6cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[7:7])); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "96e8", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_8 ( .aclr(aclr), .cin(wire_add_sub_cella_7cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[8:8])); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "96e8", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_9 ( .aclr(aclr), .cin(wire_add_sub_cella_8cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[9:9])); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "96e8", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_10 ( .aclr(aclr), .cin(wire_add_sub_cella_9cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_10cout[0:0]), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[10:10])); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "96e8", add_sub_cella_10.operation_mode = "arithmetic", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_11 ( .aclr(aclr), .cin(wire_add_sub_cella_10cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_11cout[0:0]), .dataa(wire_add_sub_cella_dataa[11:11]), .datab(wire_add_sub_cella_datab[11:11]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[11:11])); defparam add_sub_cella_11.cin_used = "true", add_sub_cella_11.lut_mask = "96e8", add_sub_cella_11.operation_mode = "arithmetic", add_sub_cella_11.sum_lutc_input = "cin", add_sub_cella_11.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_12 ( .aclr(aclr), .cin(wire_add_sub_cella_11cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_12cout[0:0]), .dataa(wire_add_sub_cella_dataa[12:12]), .datab(wire_add_sub_cella_datab[12:12]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[12:12])); defparam add_sub_cella_12.cin_used = "true", add_sub_cella_12.lut_mask = "96e8", add_sub_cella_12.operation_mode = "arithmetic", add_sub_cella_12.sum_lutc_input = "cin", add_sub_cella_12.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_13 ( .aclr(aclr), .cin(wire_add_sub_cella_12cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_13cout[0:0]), .dataa(wire_add_sub_cella_dataa[13:13]), .datab(wire_add_sub_cella_datab[13:13]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[13:13])); defparam add_sub_cella_13.cin_used = "true", add_sub_cella_13.lut_mask = "96e8", add_sub_cella_13.operation_mode = "arithmetic", add_sub_cella_13.sum_lutc_input = "cin", add_sub_cella_13.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_14 ( .aclr(aclr), .cin(wire_add_sub_cella_13cout[0:0]), .clk(clock), .cout(wire_add_sub_cella_14cout[0:0]), .dataa(wire_add_sub_cella_dataa[14:14]), .datab(wire_add_sub_cella_datab[14:14]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[14:14])); defparam add_sub_cella_14.cin_used = "true", add_sub_cella_14.lut_mask = "96e8", add_sub_cella_14.operation_mode = "arithmetic", add_sub_cella_14.sum_lutc_input = "cin", add_sub_cella_14.lpm_type = "stratix_lcell"; stratix_lcell add_sub_cella_15 ( .aclr(aclr), .cin(wire_add_sub_cella_14cout[0:0]), .clk(clock), .dataa(wire_add_sub_cella_dataa[15:15]), .datab(wire_add_sub_cella_datab[15:15]), .ena(clken), .inverta((~ add_sub)), .regout(wire_add_sub_cella_regout[15:15])); defparam add_sub_cella_15.cin_used = "true", add_sub_cella_15.lut_mask = "9696", add_sub_cella_15.operation_mode = "normal", add_sub_cella_15.sum_lutc_input = "cin", add_sub_cella_15.lpm_type = "stratix_lcell"; assign wire_add_sub_cella_dataa = datab, wire_add_sub_cella_datab = dataa; stratix_lcell strx_lcell1 ( .cout(wire_strx_lcell1_cout), .dataa(1'b0), .datab((~ add_sub)), .inverta((~ add_sub))); defparam strx_lcell1.cin_used = "false", strx_lcell1.lut_mask = "00cc", strx_lcell1.operation_mode = "arithmetic", strx_lcell1.lpm_type = "stratix_lcell"; assign result = wire_add_sub_cella_regout; endmodule
module addsub16 ( add_sub, dataa, datab, clock, aclr, clken, result)/* synthesis synthesis_clearbox = 1 */; input add_sub; input [15:0] dataa; input [15:0] datab; input clock; input aclr; input clken; output [15:0] result; wire [15:0] sub_wire0; wire [15:0] result = sub_wire0[15:0]; addsub16_add_sub_gp9 addsub16_add_sub_gp9_component ( .dataa (dataa), .add_sub (add_sub), .datab (datab), .clken (clken), .aclr (aclr), .clock (clock), .result (sub_wire0)); endmodule

module fifo_4k_a_gray2bin_9m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [11:0] bin; input [11:0] gray; wire xor0; wire xor1; wire xor10; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor10 = (gray[11] ^ gray[10]), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[9] ^ xor10); endmodule

module fifo_4k_a_graycounter_826 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule

module fifo_4k_a_graycounter_3r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [11:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [0:0] wire_countera_10cout; wire [11:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [11:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_10cout[0:0]), .dataa(power_modified_counter_values[9]), .datab(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "6c50", countera_10.operation_mode = "arithmetic", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell countera_11 ( .aclr(aclr), .cin(wire_countera_10cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[11]), .ena(1'b1), .regout(wire_countera_regout[11:11]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_11.cin_used = "true", countera_11.lut_mask = "5a5a", countera_11.operation_mode = "normal", countera_11.sum_lutc_input = "cin", countera_11.synch_mode = "on", countera_11.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule

module fifo_4k_altsyncram_8pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [11:0] address_a; input [11:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [11:0] address_a_wire; wire [11:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 12, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 4095, ram_block3a_0.port_a_logical_ram_depth = 4096, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 12, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 4095, ram_block3a_0.port_b_logical_ram_depth = 4096, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 12, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 4095, ram_block3a_1.port_a_logical_ram_depth = 4096, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 12, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 4095, ram_block3a_1.port_b_logical_ram_depth = 4096, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 12, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 4095, ram_block3a_2.port_a_logical_ram_depth = 4096, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 12, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 4095, ram_block3a_2.port_b_logical_ram_depth = 4096, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 12, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 4095, ram_block3a_3.port_a_logical_ram_depth = 4096, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 12, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 4095, ram_block3a_3.port_b_logical_ram_depth = 4096, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 12, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 4095, ram_block3a_4.port_a_logical_ram_depth = 4096, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 12, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 4095, ram_block3a_4.port_b_logical_ram_depth = 4096, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 12, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 4095, ram_block3a_5.port_a_logical_ram_depth = 4096, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 12, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 4095, ram_block3a_5.port_b_logical_ram_depth = 4096, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 12, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 4095, ram_block3a_6.port_a_logical_ram_depth = 4096, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 12, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 4095, ram_block3a_6.port_b_logical_ram_depth = 4096, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 12, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 4095, ram_block3a_7.port_a_logical_ram_depth = 4096, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 12, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 4095, ram_block3a_7.port_b_logical_ram_depth = 4096, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 12, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 4095, ram_block3a_8.port_a_logical_ram_depth = 4096, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 12, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 4095, ram_block3a_8.port_b_logical_ram_depth = 4096, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 12, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 4095, ram_block3a_9.port_a_logical_ram_depth = 4096, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 12, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 4095, ram_block3a_9.port_b_logical_ram_depth = 4096, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 12, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 4095, ram_block3a_10.port_a_logical_ram_depth = 4096, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 12, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 4095, ram_block3a_10.port_b_logical_ram_depth = 4096, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 12, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 4095, ram_block3a_11.port_a_logical_ram_depth = 4096, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 12, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 4095, ram_block3a_11.port_b_logical_ram_depth = 4096, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 12, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 4095, ram_block3a_12.port_a_logical_ram_depth = 4096, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 12, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 4095, ram_block3a_12.port_b_logical_ram_depth = 4096, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 12, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 4095, ram_block3a_13.port_a_logical_ram_depth = 4096, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 12, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 4095, ram_block3a_13.port_b_logical_ram_depth = 4096, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 12, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 4095, ram_block3a_14.port_a_logical_ram_depth = 4096, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 12, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 4095, ram_block3a_14.port_b_logical_ram_depth = 4096, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[11:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[11:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 12, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 4095, ram_block3a_15.port_a_logical_ram_depth = 4096, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 12, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 4095, ram_block3a_15.port_b_logical_ram_depth = 4096, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule

module fifo_4k_dffpipe_bb3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe4a_D; reg [11:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; // synopsys translate_off initial dffe4a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0; else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11]; assign wire_dffe4a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule

module fifo_4k_dffpipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffe6a_D; reg [11:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; // synopsys translate_off initial dffe6a[11:11] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[11:11] <= 1'b1; else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0; else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11]; assign wire_dffe6a_D = (d & {12{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule

module fifo_4k_alt_synch_pipe_em2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [11:0] d; output [11:0] q; wire [11:0] wire_dffpipe5_q; fifo_4k_dffpipe_em2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule

module fifo_4k_add_sub_b18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [11:0] dataa; input [11:0] datab; output [11:0] result; wire [11:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [0:0] wire_add_sub_cella_10cout; wire [11:0] wire_add_sub_cella_dataa; wire [11:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(wire_add_sub_cella_10cout[0:0]), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "69b2", add_sub_cella_10.operation_mode = "arithmetic", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_11 ( .cin(wire_add_sub_cella_10cout[0:0]), .combout(wire_add_sub_cella_combout[11:11]), .cout(), .dataa(wire_add_sub_cella_dataa[11:11]), .datab(wire_add_sub_cella_datab[11:11]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_11.cin_used = "true", add_sub_cella_11.lut_mask = "6969", add_sub_cella_11.operation_mode = "normal", add_sub_cella_11.sum_lutc_input = "cin", add_sub_cella_11.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule

module fifo_4k_dcfifo_6cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [11:0] rdusedw; input wrclk; output wrfull; input wrreq; output [11:0] wrusedw; wire [11:0] wire_rdptr_g_gray2bin_bin; wire [11:0] wire_rs_dgwp_gray2bin_bin; wire [11:0] wire_wrptr_g_gray2bin_bin; wire [11:0] wire_ws_dgrp_gray2bin_bin; wire [11:0] wire_rdptr_g_q; wire [11:0] wire_rdptr_g1p_q; wire [11:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [11:0] delayed_wrptr_g; reg [11:0] wrptr_g; wire [11:0] wire_rs_brp_q; wire [11:0] wire_rs_bwp_q; wire [11:0] wire_rs_dgwp_q; wire [11:0] wire_ws_brp_q; wire [11:0] wire_ws_bwp_q; wire [11:0] wire_ws_dgrp_q; wire [11:0] wire_rdusedw_sub_result; wire [11:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [11:0] wire_rdempty_eq_comp_dataa; wire [11:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [11:0] wire_wrfull_eq_comp_dataa; wire [11:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_4k_a_graycounter_826 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_4k_a_graycounter_3r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_4k_a_graycounter_3r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_4k_altsyncram_8pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq | int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 12'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 12'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_4k_dffpipe_bb3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_4k_dffpipe_bb3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_4k_alt_synch_pipe_em2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_4k_dffpipe_bb3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_4k_dffpipe_bb3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_4k_alt_synch_pipe_em2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_4k_add_sub_b18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_4k_add_sub_b18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule

module fifo_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [11:0] rdusedw; output wrfull; output [11:0] wrusedw; wire sub_wire0; wire [11:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [11:0] sub_wire4; wire rdempty = sub_wire0; wire [11:0] wrusedw = sub_wire1[11:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [11:0] rdusedw = sub_wire4[11:0]; fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule