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H: 5v to 12 Power Supply
I have really no idea about electronics.
I am trying to provide IR lighting for my night camera that I use with the raspberry Pi.
The Pi is powered by a 5v usb power bank. The IR requires 12v.
I purchased these:
https://uk.banggood.com/DC-12V-48LED-IR-940nm-Night-Vision-Infrared-Illuminator-Board-For-CCTV-Home-Security-Camera-p-1280391.html?rmmds=myorder&cur_warehouse=CN
https://uk.banggood.com/48pcs-IR-LEDs-Light-Board-Infrared-Illuminator-940nm-Invisible-Light-at-Night-No-Red-Exposure-Camera-p-1281930.html?rmmds=myorder&cur_warehouse=CN
And thought getting this:
https://www.amazon.co.uk/gp/product/B071X6VYXR/ref=ppx_yo_dt_b_asin_title_o01_s00?ie=UTF8&psc=1
to power from a 5V USB Power bank would work.
But it did not.
I cannot seem to find anything that will power these lights.
I also rather not do any soldering.
AI: Using power formula for DC circuits: Power [Watts] = Voltage [Volts] x Current [Amps]
If you are stuck with USB 2.0, then you are limited in how much current you can draw by the USB 2.0 specifications, which is 2A @ 5V, for a total of 2 * 5 = 10W.
So, you then need to increase the voltage using what's called a boost converter, which will boost the voltage up to a certain level; but unfortunately the total power you can draw still depends on the USB port, that being 10 Watts.
If we assume a 100% efficiency of the converter (ideal), when boosting from 5V to 12V and having 10W available, we will get 10 / 12 = 833 mA maximum output current.
Since the product page of the first lamp says that 1 Amp of current is required at 12V, i don't think you can ever hope to power said lamp with a USB 2.0 boost converter.
I tried to look around for a USB 3.0 boost converter with support for the Power Delivery protocol, but couldn't find any: these would support higher power, but would in turn require a USB 3.0 power back with Power Delivery protocol support.
They also might be more expensive.
Meanwhile, you could check with a multimeter the output of your USB 2.0 boost converter to see if it still works, and saved itself thanks to internal over-current protection, or if it's actually dead.
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H: Power supply problem, what is the correct solution?
My result is "No" because the DC voltage is around 14.86 v and the ripple voltage is around 9.9 volts but I'm not convinced about the result especially for the ripple voltage. Does anybody get the same result?
Here are my calculations
$$V_{peak} = 15 * 1.414 - 1.4 = 19.81$$
$$V_{rip} = \frac{1}{f \times R_{load} \times C} \times V_{peak} = \frac{1}{100 \times 20 \times .001 }\times 19.81 = 9.905V$$
$$V_{dc} = 1-1/(2 \times f \times R_{load} \times C) \times V_{peak} = 14.86V $$
AI: So, the question is whether the supply is operating correctly or not.
A practical answer:
The LM7812CT requires a voltage difference of at least 2VDC across its input and output terminals. This voltage is called Dropout Voltage. So the minimum input voltage for proper operation should be \$\mathrm{V_O+V_{DROP}=12+2=14V}\$. Since the input voltage comes from a bridge rectifier+smoothing capacitor, the valley of the ripple should not be below 14VDC.
According to the given info in the question, the valley of the ripple is \$\mathrm{V_{in-min}=V_{DC} - (V_{rpp}/2)=17.64-4.22/2=15.53V}\$. This is higher than the required minimum input voltage. So the answer is yes, the supply is operating correctly.
A detailed answer:
The ripple factor formula you're using is a simplified form. When it comes to practice, there are some other things to consider like the ripple current flowing through the smoothing capacitor. Anyways, let's use the simplified formula:
$$\mathrm{V_{rpp}=\frac{I_{LOAD}}{2\cdot f_L\cdot C}}
$$
If the circuit is operating correctly, the output voltage should be pure 12VDC. So the output current is \$\mathrm{I_{O}=12V/20\Omega}=0.6A\$. Since 7812 is a linear regulator, its input and output currents are equal. Thus \$\mathrm{I_{LOAD}=I_O}\$ and \$\mathrm{V_{rpp}=0.6A/(2\cdot 50Hz\cdot 1000\mu F)=6Vpp}\$. The expected ripple voltage is 6V and the measured ripple voltage is 4.22V which is lower than expected. This is good. So, the answer is yes, the supply is operating correctly.
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H: Locally create 3V3 from 5V for small load and uP GPIO
I am designing a 5V board and i need to read two outputs from the lithium charger using the 3V3-only uP GPIO, while also using them the same output pins to drive user LEDs; charger outputs are either GND or Hi-Z.
While trying to come up with a solution that ticks most boxes (all round optimal for cost, size, footprint, but not best in any regards) i came up with this:
R_LED and G_LED nodes are the charger outputs.
I used these P-mosfets because i already have pleny on the board, thus avoiding an extra part in the BOM.
Datasheets:
battery charger IC
P channel MOSFET
LED to drive
Zener diode
My reasoning:
Zener datasheet states PD max = 500 mW: at Zener voltage of 1.8 V that translates to I max of 277 mA; so i think i can pull 20 mA for each led without issues.
When both input nodes are Hi-Z, zener will drop 1.8V allowing 320 uA to flow through R98, creating a 3.2 V reference for the High state of the 3V3 uP GPIO input (although GPIOs will be connected to this reference voltage via R93 and R94, which concerns me).
When either input node transitions from Hi-Z to GND, uP GPIO which is tied to directly will move from 3.2 V to GND; also, the mosfets will start conducting, turning on the LED.
The questions:
Am i correct in assuming that this will work?
Is there a better way to achieve the same?
AI: Low-voltage Zeners have lousy characteristics:
I would replace the MMSZ4678 with an adjustable shunt regulator like the TLV431/TLVH431/AZ431L, or just use an LDO.
And connecting the GPIO to 3.3 V might be able to power up the µC, or, if the voltage falls low enough, to switch on the MOSFETs.
The x_LED outputs of the charger are designed to drive LEDs directly (10 mA is more than enough), so the simplest circuit actually does this.
To get a 3.3 V signal for the µC, use this level shifter, which is commonly used for slow open-drain signals like I²C:
simulate this circuit – Schematic created using CircuitLab
This requires one low-voltage N-channel MOSFET per signal.
When the 3.3 V supply is switched off, the MOSFET is also switched off, and the LED state does not affect the GPIO.
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H: Please help me identify this connector type
Can anyone help me identify this connector types? I have tried finding this connector online and the closest one seems to be tamiya connector. But the ones I found being sold online has different locking mechanism.
This is the female counter parts:
It's used for a washing machine coin sensor.
AI: that sure looks like molex mini-fit JR
https://www.digikey.co.nz/product-detail/en/molex/0015311032/WM2586-ND/2405493
https://www.digikey.co.nz/product-detail/en/molex/1726460313/WM20748-ND/5116928
contact pins and crimp tool sold separately.
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H: Why use a tantalum instead of a ceramic capacitor?
On page 72 of the AD7124-4 datasheet it says:
Decouple AVDD with a 1 μF tantalum capacitor in parallel with a 0.1 μF capacitor to AVSS on each pin.
Why would this capacitor be specified to be a tantalum?
At this low capacitance a ceramic MLCC is cheaper and has superior ESL and ESR.
Is there a reason for this?
AI: The LDO built into the chip needs an ESR that is high enough to ensure stability under all conditions.
You can use a 1uF ceramic capacitor with a series resistor of 5 or 10 ohms in place of the tantalum capacitor. And keep the 100nF capacitor in parallel.
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H: How many amps between batteries that are wired in parallel?
How many amps will flow through the cables between my batteries if I have 2 batteries wired in parallel?
Let's look at a simple example:
We've got 2 batteries in parallel, and one 12v lamp that requires 3 amps. The wire from the battery to the lamp will require a wire that can handle 3amps, but how many amps will go through the cables between the batteries in this example?
AI: If they are identical batteries with identical charge (an ideal assumption and not the case, but its safe to assume so hypothetically) then half the current will be drawn from both each such that the required 3A comes from 1.5A of each of the batteries - they can be seen as mutually exclusive in the way that the current from the 2nd battery doesnt have to go through the 1st one - i.e. the positive conenctor of 1st battery which connects to the 2nd battery wire AND the 3A wire, is thick enough to support the 3A so the 1st battery and 2nd each give out 1.5A to a seemingly 1.5A load each. Because of this, the wire from 1st to 2nd (essentially the same wire as the 2nd to the connector to the 3A wire) should handle 1.5A minimum.
This is, again, assuming both batteries uniformly give 1.5A. Voltage imbalances (which wouldn't happen as they are in parallel, but nonetheless there are other chemical imbalances) mean that there might be slight differences in the current draw. For safety I would personally use 2A wire to account for any current imbalances.
To answer your question in at the start of your post, though; if the load requires 3A at 12 V (and assuming your power source can provide this without dropping voltage - a couple of car batteries should do it just fine) it will draw 3A. Just as much as it needs, despite the power source being able to supply more. You could connect 10 car batteries in parallel and it would still only draw 3A in total because that's all it needs (in this case, each one would supply 0.3 A if they are identical)
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H: What's a pigtail with regards to antennas?
Can somebody explain to me what a pigtail is with regards to antennas? I bought a 434 MHz rod antenna with an SMA plug and what I got was the antenna as expected and another short piece of wire with another SMA plug (female plug type):
Is the picture above a pigtail? What's it's usage? I was able to screw on my antenna to my 434 MHz receiver without issues and have no apparent use for this other cable...
AI: Pictured is a SMA connector with a pigtail,
A pigtail is a wire that ends with no connector.
you could solder that wire to something else to connect the antenna to that.
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H: How do I test a lawn mower magneto?
I'm trying to test the magneto from my riding mower. I followed some YouTube videos and tested it with a multimeter putting one probe where the spark plug would go and touching the other to the metal plates. I get a resistance of about 5.84 kilo-ohms. But I don't know what that means. Is it too high? Are there any other tests I should do? (the mower has no spark).
The mower has a Briggs & Stratton 11.5hp engine, model 28D707-0123-01 (1996). I tested for a spark by holding the plug to the engine while turning the key. (Maybe the "redneck" method but recommended by my service manual too in the absence of a spark tester.) The starter motor appears to work properly and the flywheel turns freely by hand. I also tried a new spark plug and all the safety interlocks appear good. The replacement part is here https://www.jackssmallengines.com/jacks-parts-lookup/part/briggs-stratton/591459 but I can't find any specifications for the old or new one. I'm not yet 100% sure that the magneto is the problem so I'd rather confirm that it's bad before replacing it.
AI: Do you see the single spade terminal that is on the coil? If that is grounded, the coil won't fire. Pull the engine shroud off and disconnect the wire from that terminal. Next check the spacing from the coil to the flywheel is good. I like to use a business card but a thin piece of plastic works too. When the magnet is facing the coil the gap between the coil and magnet should be even and about that much.
Get a good new spark plug. Put it on the coil wire. Touch the threads of the spark plug to the block and have a second person crank it for you. This way you can easily keep an eye on the spark plug. If it does not spark at this point, you have a bad coil.
If it sparks then plug the wire back in. If the sparking stops then there is a short to ground on that wire.
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H: What are the values of these 2 resistors?
What are the values of the two highlighted resistors?
Considering the brown band as tolerance and ignoring the first (black) band, I came to the conclusion that the values are 680 and 220 milliohms. Is that correct? Thanks.
AI: 0.68\$\Omega\$ +/-1% and 0.22\$\Omega\$ +/-1%
Probably both 1/4-W.
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H: How do I calculate how long it will take for a capacitor to discharge when shorted?
If I know the capacitance, series resistance, and the voltage it is charged to. I tried using a graph y=x/0.003
Where y is current and x is voltage, but now i'm lost, because I don't know where to put the capacitance. And then I wouldn't know how to get time.
AI: The discharge equation is:
\$V_c = V_0\cdot e^{\frac{-t}{R\cdot C}}\$
If this is re-arranged to isolate t:
\$t = -R\cdot C \cdot ln(\frac{V_c}{V_0}) \$
if R is a true short and there is no series resistance then the capacitor will instantly discharge (with infinite current). In a real-world situation with a finite resistance it will discharge "quickly" with an exponential characteristic
use python/excel/calculator and plug your numbers in but use something like 1e-6 for the final capacitor voltage Vc
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H: Probing With Multimeter Breaks LED - Happened Twice
Qucik background info:
I am using a 117 Fluke, brand new bought in 2020 from Amazon.
What happened/happens:
This is a very simple circuit, but for some reason the resistor keeps heating when I try to use red LED's which are rated at 0.007 Amperes, so I tried to check the current going through the resistor, which caused the problem.
The LED simply goes out, and it won't turn on again. I tested this with a white LED also, same problem.
I can test the LEDs fine, and they show 0.0087 amps, which is fine, but the second I touch the resistor it burns up.
Does anyone have an idea, why this happens?
AI: You are not using the multi-meter correctly. To measure voltage you can just put the probes across the component you want to measure. It's like measuring water temperature. You just need to stick your finger in and feel it. No need to divert the water.
But measuring current is like measuring water flow. You need to divert all the water through your measurement device. When set to measure current, the multimeter probes will be changed they basically act as the same piece of wire since the multi-meter is expecting you to send all the current to be measured through it. If you place the probes across something in current mode, it diverts current and causes a short-circuit across the component.
You must actually break the circuit and stick your multimeter into it to measure current. When in ammeter mode, your two probes are basically the same piece of wire. If your meter is in current measurement mode and you stick the probes into your circuit across the resistor as if you were measuring voltage it will be as if you stuck a piece of wire across your resistor. This will divert all current that would otherwise flow through your resistor through the multi-meter instead. In other words, it shorts out your resistor and removes it from the circuit, then your LED explodes.
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H: I removed a little motor from my laptop fan and it won't run using a 9V battery
I realize this is may be a noob question so please point me to the right place to ask it if this isn't so. Anyway, I'm trying to build a little magnetic blender using a spare laptop fan. I tried plugging the red and black wires (and every other possible combination) into a 9V battery but it didn't run at all. So I broke the whole thing apart and ended up with the motor inside:
When I plug the + and - ports from my battery to the metal things in the motor (A and B in the picture), it turns about half turn and then it stops, and when I switch the poles it runs a little more, and so on, always on the same direction. So I guess the poles need to switch intermittently, which I understand means I need AC instead of DC? Is there a way to easily have this motor work using a battery or power from my outlet using simple tools? I understand home current is AC, but I'd need a way to lower the voltage while keeping it AC, and I believe phone chargers all output DC.
AI: You are on the right track, in thought process at least, not procedure.
Know that fundamentally, there is no such thing as a DC motor. All motors operate based on changing (alternating/rotating) magnetic fields which are produced by changing (alternating) currents. They are all "AC" so to speak at the lowest level. What goes into the coils is always some form of AC.
You only have motors that take DC and convert it into AC. The brushes on a brushed motor do this by taking the DC you put into the wires and making the current change directions through the coils when it turns, thereby producing the "AC", so that it can continue to turn instead of just turning a bit and locking up.
In a brushless motor, like your computer fan, electronics are required to do the job of the brushes. It needs some smarts. A computer fan has the electronics integrated into it, but it appears you might have ripped those out.
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H: Simplifying boolean equations with K-map
My professor told me that I could arrive at the simplified solution using the K-map, which I guess I did, however it does not seem correct.
The equation and corresponding solution are shown in the pictures below.
My simplification steps were:
ABCD' + A(B' + C' + D') + (A'B'C'D') -> used two De Morgan's rules
A(B' + C' + D') = AB'CD + AB'CD' + ABC'D + ABC'D' + ABC'D +ABC'D' + AB'C'D + AB'C'D' + ABCD' + ABC'D + AB'CD' + AB'C'D' (opened up the brackets using the identity)
Draw the K-map and arrived at this simplified equation: A + AB + B'C'D' (the drawing is attached down below)
Obviously, this is incorrect, could someone help me pointing on the mistake I did and also helping to find simplification without K-map?
AI: Here's the initial k-map:
$$
\begin{array}{rl}
\begin{smallmatrix}\begin{array}{r|cccc}
&\overline{A}\:\overline{B}&\overline{A}\: B&A\: B&A\: \overline{B}\\
\hline
\overline{C}\:\overline{D}&1&0&1&1\\
\overline{C}\:D&0&0&1&1\\
C\: D&0&0&0&1\\
C\:\overline{D}&0&0&1&1
\end{array}\end{smallmatrix}
\end{array}
$$
And here's how I circled things (using Paint):
A brute force algebra method might go like this:
$$\begin{align*}
& A\,B\,C\,\overline{D} + A\left(\overline{B} + \overline{C} + \overline{D}\right) + \overline{A}\,\overline{B}\,\overline{C}\,\overline{D}\\\\
& A\,B\,C\,\overline{D} + \overline{A}\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B} + A\,\overline{C} + A\,\overline{D}\\\\
& A\,B\,C\,\overline{D} + \overline{A}\,\overline{B}\,\overline{C}\,\overline{D}\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,\overline{C}\,D + A\,\overline{B}\,C\,\overline{D} + A\,\overline{B}\,C\,D\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,\overline{C}\,D + A\,B\,\overline{C}\,\overline{D} + A\,B\,\overline{C}\,D\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,C\,\overline{D} + A\,B\,\overline{C}\,\overline{D} + A\,B\,C\,\overline{D}\\\\
& A\,B\,C\,\overline{D} + \left(\overline{A}\,\overline{B}\,\overline{C}\,\overline{D}\right.\\&\quad\quad\quad\quad\quad\quad + \left.A\,\overline{B}\,\overline{C}\,\overline{D}\right) + A\,\overline{B}\,\overline{C}\,D + A\,\overline{B}\,C\,\overline{D} + A\,\overline{B}\,C\,D\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,\overline{C}\,D + A\,B\,\overline{C}\,\overline{D} + A\,B\,\overline{C}\,D\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,C\,\overline{D} + A\,B\,\overline{C}\,\overline{D} + A\,B\,C\,\overline{D}\\\\
& \overline{B}\,\overline{C}\,\overline{D}\\&\quad\quad\quad\quad\quad\quad + A\,B\,C\,\overline{D} + A\,\overline{B}\,\overline{C}\,D + A\,\overline{B}\,C\,\overline{D} + A\,\overline{B}\,C\,D\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,\overline{C}\,D + A\,B\,\overline{C}\,\overline{D} + A\,B\,\overline{C}\,D\\&\quad\quad\quad\quad\quad\quad + A\,\overline{B}\,\overline{C}\,\overline{D} + A\,\overline{B}\,C\,\overline{D} + A\,B\,\overline{C}\,\overline{D} + A\,B\,C\,\overline{D}\\\\
& \overline{B}\,\overline{C}\,\overline{D} + A\left(\overline{B}\left[\overline{C}\,\overline{D} + \overline{C}\,D + C\,\overline{D} + C\,D\right] + B\left[\overline{C}\,\overline{D} + \overline{C}\,D + C\,\overline{D}\right]\right)\\\\
& \overline{B}\,\overline{C}\,\overline{D} + A\left(\overline{B} + B\left[\overline{C}\,\overline{D} + \overline{C}\,D + C\,\overline{D}\right]\right)\\\\
& \overline{B}\,\overline{C}\,\overline{D} + A\left(\overline{B} + \overline{C}\,\overline{D} + \overline{C}\,D + C\,\overline{D}\right)\\\\
& \overline{B}\,\overline{C}\,\overline{D} + A\left(\overline{B} + \overline{C} + C\,\overline{D}\right)\\\\
& \overline{B}\,\overline{C}\,\overline{D} + A\left(\overline{B} + \overline{C} + \overline{D}\right)
\end{align*}$$
I hope you follow those steps okay.
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H: How to avoid negative voltage on MCU pin from RCV420 converter?
I am working on a circuit to convert 4-20 mA signal to 0-5 V to finnaly read with an analog input of an MCU (PIC16F886). The IC I'm using to convert the signal is the RCV420K which works fine. On the documentation of the IC it says that it needs to have -1.25 V on the output at 0 mA so at 4 mA can be 0 V.
I am reading the voltage signal with no problems but when I unplug the signal from the IC the voltage goes negative and I suspect it is going to be harmful for the MCU.
The thing is the IC outputs very little current (0.10 mA on my readings) but when the signal source is removed it reads -1.0 mA. Is this safe for my MCU? If not, Is there any way to ground the negative signal so it doesn't affect the MCU?
Thanks in advance!! I'll attach an schematic.
AI: It's probably safe enough but datasheet says the current could be as much as -13mA which is less than the absolute maximum of 20mA for chip survival but could cause odd things to happen with the MCU.
You can simply add a Schottky diode such as BAT54 from the ADC input to ground, which solves the problem related to your question here.
You might also consider an RC filter and clamping the receiver output on the positive side, but that's outside the scope of this answer.
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H: Diode identification - zener?
I’m trying to replace what I believe to be a glass zener diode which I determined was overloaded in an electronic automobile delay module. Cathode was attached to a PCB (labeled “Z1”) and the anode was soldered directly to one of five “blades" which extends through the module and to the female plug of the module bank. While the diode was a bit damaged, I was able to read alphanumeric codes. They are as follows:
PH
3ZX
79C
35*
I’m fairly certain of accuracy, but the cathode side was charred enough to make any characters illegible if there were any. I don’t think that was the case, though. The “35” could be a “36."
The module is of European manufacture—Pektron.
Any help would be appreciated!
AI: It is a 36V +/-5% 500mW Zener diode.
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H: How to find the right battery for my project
I am working on a project that requires 12v 12A of power. But I can't find the right battery. I have been looking at a few online tutorials about choosing batteries but they have not been very helpful.
The battery I am requiring is 12v 12A DC. and it needs to be rechargeable. It also needs to be less than 2.5 inches tall, since there is not much clearance space in my robot. Any help I can get would be greatly appreciated.
AI: There are only a limited number of battery chemistries and each one has its own voltage so there are only a limited number of voltages. Also, battery voltage drops as they get discharged so you won't find exactly 12V. Search radio-controlled hobby websites.
The most likely chemistries available to you, in order of increasing cost, increasing performance, decreasing weight, and decreased tolerance to electrical and mechanical for abuse, are:
lead-acid
NiMh
Lithium-Polymer or Lithium Iron Phosphate (or the other lithium
variants, just not lithium-ion...too low power to move a robot)
You will need a specialized charger for the better types of batteries such as Lithium Polymer and its variants such as Lithium Iron Phosphate since they real fire hazards (due to their high energy density) if mishandled, both electrical and physically.
A battery's energy capacity is rated in Amp-hours (Ah).
A battery's power capability is a C-rating and tells you how much current the battery can supply relative to its Amp-hour rating.
7Ah means (theoretically) it can provide 7A for one hour before it is dead. Drawing 7A out of a 7Ah battery is a discharge of 1C, and it should run for 1 hour.
If that same 7Ah battery is rated for 3C, then that means it can supply a maximum of 21 Amps. Drawing 3C worth of current from that battery will runs it down three times faster, so it will only run 1/3 of an hour.
So the fact you say you need 12A only tells us the power you need the battery to supply, not how long it needs to run for.
$$ Max.Amps = C.rating \times Amp.hours$$
$$ Run.Hours = \frac{1}{discharge.C.value}$$
$$discharge.C.value = \frac{Discharge.Current}{Amp.hours}$$
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H: Lattice XP2 -- Different voltages for different IO banks?
As the subject indicates: can I use different voltages for the different IO banks? (1.8V for some, 3.3V for some others)
Neither the datasheet nor the hardware checklist technical note explicitly say, AFAICS.
AI: The key document is one you didn't link to, but which is linked from the datasheet, the Lattice XP2 SysIO Usage Guide.
The most explicit indicator that the VCCIOs can have different values is on page 8-4:
There are further contextual cues that VCCIO's can be different for different banks:
The VCCJ supply voltage is explicitly described as being "independent of the bank VCCIO supplies". (note the plural)
It's explicitly mentioned that input pin voltage levels can be different in a bank (under the heading "mixed voltage support in a bank").
To be sure, you could create a simple design that uses differently-supplied output pins in different banks, and one that uses differently-supplied output pins in the same bank. The place and route tool should give an error for the second case but not the first.
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H: Power saving circuit in pneumatic valve
I am looking for a pneumatic valve and I refereed a catalog. It has a power saving circuit in the valve and there is a circuit diagram and description of that.
I couldn't understand how this power saving circuit works. Below is the description about that as the catalog.
Can someone explain about function and how it saves power ?
This is the full catalog. ( See page 44 for above description)
AI: The valve works by attracting an iron armature into a solenoid. This means that when un-energised, there's a large airgap in the magnetic circuit. When it's energised, the airgap is much smaller.
The large initial airgap means that a large current is required to develop enough force to move the armature. When the airgap is smaller, less current is needed to develop the same force.
The power saving circuit appears to be integrated into the valve. When you apply power to the valve from your control, the timer circuit turns the transistor on, which applies the full voltage across the valve coil. After a while, during which it's assumed that the valve has pulled in, the timer circuit turns the transistor off, and the coil is now only supplied through the resistor. This lowers the voltage to the coil, causing it to draw less current, but still enough to hold the valve on.
This is a quite inefficient method of doing it. Had they used a buck converter instead of the resistor, then the power consumption could be reduced yet further, albeit at a higher cost for components.
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H: What is the AUX_IN and CD_IN connection on old Soundblaster sound cards?
What is the AUX_IN and CD_IN 4-pin connection on old Soundblaster sound cards? The card's model is CT4170. Here is an example
I think its some sort of input. Is there any schematic which tells me which pin is what? There was also a connector on one of those inputs with three wires. Here is how it was connected
AI: Those are analog inputs for a CD drive and whatever auxiliary device such as another CD drive.
The pinout is Left Ground Ground Right.
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H: How to use chip XL6007E1 to build a boost ciruit?
My ciruit:
Input: 3.7V
But no matter how I adjust the potentiometer, the voltage did not rise.
How can I solve it?
AI: Look here: -
The most obvious problem is that the enable pin (EN) is floating. Try connecting it to Vin as per the data sheet: -
Other potential issues?
Why haven't you got 220 uF on the output like the data sheet suggests?
What output voltage are you trying to achieve?
What is SW1 all about?
Why haven't you got the recommended input capacitance?
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H: Powering opamp from unregulated DC-DC Converter?
When using one of those unregulated, isolated DC-DC bricks (its output voltage can be as much as a few volts higher than its rating and varies with load) to power an opamp is a voltage regulator a good idea even if the opamp can handle the higher voltage? What would be some of the benefits of doing this?
AI: What would be some of the benefits of doing this?
Power supply noise regulation is the main benefit - op-amps are good but they won't deal with power supply rail voltage variations without producing some distortion on the output signal. For an op-amp, it's called PSRR (power supply rejection ratio) and tells you (in the data sheet for the op-amp) what effects power line variations might have on the output signal.
The figures in the data sheet usually refer to an equivalent interfering input voltage so, if PSRR is 40 dB (100:1) then 1 volt p-p of ripple or noise on the power rail is equivalent to 10 mV p-p at the op-amp inputs.
PSRR also usually gets worse at higher frequencies so beware of this. But it can be 100 dB (100,000:1) or so at DC.
Using a voltage regulator stabilizes the power rails and reduces noise and ripple therefore making fewer problems with rejection of said interference for the op-amp. However, not all voltage regulators are noise-free; some are a lot worse than others and, in some applications the added noise introduced by a regulator may end up being worse than the effect of ripple should a regulator not have been used.
Pick your regulator carefully if your target circuit is very sensitive.
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H: On/off switches board pinout labels
I would like to know if there is a pattern to name switches board pinout, at least, for these boards.
The boards are parts of a piano toy. First one for some effects buttons and second one is the piano keyboard.
The pins are named as P10, P11,P12, P13, P20, P22, P23, P40, P43 for a 10 switches board.
At the reverse it's easy to see how switches are connected to pinout.
The reason because I ask for the labeling pattern is because I would like to connect the piano keyboard to an Arduino with Midi and, the keyboard, looks with the same labeling pattern:
Here the reverse:
Here schematic pinout for 10 switches
AI: They all start with "P" other than that no obvious pattern.
they seem to be different at each end of the cable, this suggests that they are just net names allocated automatically by the design software used to design the device.
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H: Switching Relay at Zero_Cross Point
I'm controlling 4 Relays(10A) with a controller. While randomly switching it without zero-cross my controller gets restart. To avoid this I'm switching relays at the zero-cross point, But my question is every relay had the different operating time(on time) and different release time(off time) in the datasheet.
Should I add these times with zero-cross detect time or directly switch relay whenever zero-cross occurred.???
Little bit confused with these time durations, Can anyone explains how to use zero-crossing for relays switching exactly???
AI: While randomly switching it without zero-cross my controller gets
restart
That's a susceptibility weakness of your controller.
To avoid this I'm switching relays at the zero-cross point
Sounds like you intend to swallow a spider to catch a fly. Where does this stop I wonder?
Use this opportunity for improving the EMI rejection of your controller. The controller (any controller) should not be susceptible to this. Fixing your controller is the best long-term advice you will get.
Should you not heed this advice and one day you are presented with a load that is inductive in nature, instead of switching at the voltage zero-cross you will need to switch at the peak of the voltage (where the current passes through zero).
And, if you do decide to press ahead with synchronizing the switching then, it would be better to switch at the load current zero-cross. Of course, you may have been planning to do that all-along but, your question wasn't clear. Take into account both switching times and, if it's 10 ms (for example) then begin switching 5 ms before the zero-cross.
You might also consider that when switching off you shouldn't use a diode clamp on your relay but a zener/diode clamp to ensure the off-speed is minimized.
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H: What was used as paint on insulation/conformal coating in the 1950s?
I'm restoring a multimeter from the 1950s and I was wondering what was used as paint-on insulation/conformal coating. It's the yellow/brownish stuff smeared on the screws and leads in the photo.
I suspect it is shellac, was this commonly used in the 1950s in electronics?
It is not greasy and quite hard. It will melt a bit with a soldering iron.
AI: Photographs are not reliable color indicators. And there are greases near that color.
But that really looks like the signature color of GE’s Glyptal, which is an insulating paint specifically made for electrical equipment. Glyptal comes in very basic colors like black and white, but that particular burgundy is their signature.
Given the 1950s era, Glyptal makes a world of sense, since the product was in its heyday then.
I’ve never had occasion to stick a soldering iron on Glyptal, so I don’t know what it does. But it does not like to burn, unlike normal paint.
Glyptal is readily available today, and is used for such purposes. Also, auto racers paint the inside of engine blocks to capture any remaining casting sand, so it doesn’t wind up in the lubricating oil. I suspect they are after the “non-flammable” characteristic, not its dielectric strength.
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H: Collector current in a BJT transistor whose base and emitter are forward biased
I'm reading a book about electronics and I have a doubt about a NAND gate implemented with Transistor-Transistor Logic. The question I have is actually about BJT transistors specifically (not the gate itself). I thought I understood how BJTs work, however, in my book, there is a new type of connection I don't understand very well, let me explain:
The NAND implementation the book provides is the following:
Now, my question is about Q1. Quoting the book:
[...] If both A and B are high, Q1 has no emitter current; however, its base-collector junction is forward biased, supplying base current to Q2. [...]
My understanding is that, if A and B are high, the voltage between them is 0, therefore the BJT is opened, so no current flows from its colletor to its emitter. However, the book states that the Q2 base receives current. That is what I don't understand.
Does this mean that the voltage in the Q1 base drives current to the Q2 base as well? If so, does this work the same way (but with voltages) with MOSFETs?
Here (BJT regions of operation), the BJT regions of operation can be seen. However, there is no region for B = E > C. What region of operation in the above table is supposed to describe this one?
AI: Does this mean that the voltage in the Q1 base drives current to the
Q2 base as well? If so, does this work the same way (but with
voltages) with MOSFETs?
Don't know what you mean by Q1 voltage driving current to Q2 base. Q2's base current is common with current through Q1's base-collector diode junction, and through 4K pull-up as well. With no emitter current(s), Q1 is simply a base-to-collector forward-biased diode. The characteristic curves that might be included in a transistor data sheet don't address this biasing arrangement...more concerned with active-region transistor operation.
Logic threshold voltage for TTL is in the 1.2V to 1.3V ballpark. Consider the situation when A & B are logic high. Q2 is a bipolar switch that is saturated "ON". If you simplify transistor "ON" base-emitter voltage as 0.6V, then Q2 base is around +1.2V... because Q2 is switched "ON" and Q4 is saturated "ON" as well.
If Q2 base is 1.2V, so is Q1 collector. Q1 base is 0.6V higher, at 1.8V. If DC supply is +5V, then Q1 base current is \$ (5-1.8)\over{4000}\$ = 0.8mA. All this base current flows through 4k, and through Q1 base-emitter junction, into Q2 base. That's enough current to saturate Q2 fully "ON"...Q2 collector-to-emitter voltage clamps to a fraction of a volt. Q2 collector-to-emitter current is established by 1600 ohm resistor...around 2mA or a bit more.
Only when input A or input B falls below the 1.2V threshold does Q1 start acting as a transistor, when its base-emitter becomes forward biased. Q1 collector then pulls Q2's base toward ground, releasing it from its "ON" state, and pulling it out of saturation.
About MOSfets:
I suppose you could re-arrange a TTL input stage to use MOSfets. Getting MOSfet threshold voltage to be "TTL-compatible" would be a problem. MOSfets might pull Q2 base up, or allow "Rpulldown" to pull Q2 base down to ground to switch the NAND gate output to "high" state. Or MOSfets might replace Q1, Q2 entirely. A strange brew - not practical.
simulate this circuit – Schematic created using CircuitLab
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H: Floating traces on MCU dev boards bad for noise?
When you have development boards for microprocessors with every GPIO pinned out on headers around the edge of the board, is the board more susceptible to picking up noise than a board without all those unconnected lines?
For example say you were using the ADC on the board but everything else is disconnected (like in the image):
Would the signal being read be noisier than if all those pink unused traces didn't exist if the board was placed near noisy things like SMPSs?
AI: Probably not by a lot. Proper grounding of the PCB and filtering of the input signal, the analog reference and PCB layout are more of an issue. That's built on a cheap 2-layer board so the layout cannot be all that great.
If you flip that board over, you'll probably find large areas of copper pour that are at AC ground potential (either tied to GND or to a power supply rail).
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H: DC offset before signal being fed into an instrumentation amplifier from a bio potential source
I am trying to design an instrumentation amplifier, having 2 bio-potential sources as its differential inputs, each having peaks in the order of 10's of uV and a frequency band of 3-50 Hz. One of the main characteristics of the input signals, however, is a DC offset and depending on different conditions, it is about 600-800 mV.
This limits the gain of the amplifier, as it will also shift the output signal up about (Gain * DC-offset) and this in turn, will limit the gain and for a small signal, this means a noisy output (from different sources). One obvious solution is to put a DC blocking capacitor prior to the positive input into the InAmp. This, to me seems not to be a problem, but I am not really familiar with noise sources in capacitors (like Johnson noise in resistors), but i know that some ceramic caps experience that microphone effect, and most of the surface mount caps I have on hand are SMD MLCCs.
Would this be a good solution, or would it cause strange behaviour?
AI: I would have agreed with the below Cap material choices, NP0/C0G or Film without thinking about it. But after consideration for EMG, you don't need more than 10nF * 10M but for ECG or EEG, you may want 1M*1uF=T. (EMG for muscle signals, ECG for cardio-heart and EEG for brainwaves.)
Choosing 0.1uF or more might lead you to expensive or non-existent solutions in NP0 or film. The value can be small if the value is 1nF for higher frequency muscle signals as this material are low density (Dk) so the values for inexpensive caps are limited yet input impedances to bias might be small by choosing a large bias resistor. e.g. 10M+1uF More about this at the end.
Thus the next choice is the low-frequency cutoff. Due to galvanic motional skin voltage there is a chemical offset modulated by electrode pressure and motion that can also be a nuisance as noise. So you can determine what is your ideal Bandwidth for SNR and compute the breakpoint for ω=1/RC for the high pass filter, HPF.
But in the end, the most important design criteria is reduction of stray line noise which is a large high impedance V/m stray electric field. This creates a Common Mode noise to both signals and returns cables and the INA IC's are already designed for you with -120 dB CMRR rejection ratio with laser-trimmed resistor matching to 1 part per million. So do yourself a favour and choose an INstrument Amplifier (INA) IC. Some also do multi-channel and allow selection of common-mode inputs to invert for providing biometric 0V return signal shared by all other electrodes so you get the best CMRR from > 50V/m E-fields from nearby line voltage. This is also called Right Leg Drive (RLD) signal = 0V return.
What's all this stuff about Cap. Noise?
I thought it was only resistors that make noise. Well-known are the microphonic effects of ceramic capacitors when you hit the board. But what if the ceramic was ruggedized? Well, it turns out you can do that. SMD's will pick up on the audio resonance frequencies of stiff circuit boards together with the ceramic electrode noise.
But it turns outs, Capacitors on their own do not make noise, but it is also the Electrostrictive effects of ceramic capacitor current in addition to external vibration, that current creates a force to make ceramic crystals resonate from the excitation frequency voltage. The external ruggedized 1uF ceramic cap is available and looks like this from Murata in the KRM series.
They also make an internal ruggedized ceramic in the GJ8 series, but not this large value of 0.1uF, also neither in NP0/C0G, the thermally stable series. Murata's general-purpose (GP) ceramic is called the GRM series.
But what if the cap never sees any large excitation currents? Then it won't create any noise. True except for the microphonic effects, which you can minimize by using an epoxy leaded part that doesn't resonate audio with the board. Yes, let's go for this leaded ceramic cap. or the Murata KRM series SMD part (~$0.5 to $1 1pc).
Now, these leaded parts are rapidly going expensive $2 (1pc) before they get obsolete, but your lab may have plenty of stock. The SMD
TL;DR
Ceramic Cap's do not generate thermal noise but rather conduct noise by;
Electrostrictive effects from excitation current and frequency,
Mechanical microphonic effects in vibrational bandwidth together with PCB resonance
Galvanic skin response from electrode motion creates low-frequency noise and then we have DC input offset to deal with high gain amplifier requirements.
But fortunately for most biometric sensing, we do not need a DC response.
So I'm saying for low current uV level signals you can use your lab stock of general purpose 0.1 to 1uF ceramic X7R thru-hole caps.
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H: What is the practical probability of a bit getting flipped during transmission?
We know that Coding Theory depends on the fact that the probability p of a bit flip must be less than 0.5. From Fundamentals of Error-Correcting Codes (pg.39), it states
In most practical situations p is very small.
Using the technology we have in 2020 such as Fiber-optic cable, other types of cables, or wireless medium, what is the practical probability a bit encountering a flip during transmission?
AI: For fiber optic communications the design point is frequently taken as an error rate of 1 in 10**12 bits.
For wired links such as ethernet the raw bit rate is approximately 1 in 10**14.
Error rates and testability
WHAT IS BER (BIT ERROR RATIO)
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H: Is voltage reduced when load increases?
Would the voltage of a power source decrease if multiple loads / more load is added to it?
I am researching battery types, and wanted to know, if I added enough load to a battery how much / would there be any voltage drop?
Example: I have a 12 V set of batteries in series. The batteries' rated current is 48 A.
I have four loads that each require 12 V and 13 A of electricity. Would there be any voltage drop, would the load have to be significantly higher to actually see a decrease, or would the voltage stay the same?
AI: Yes, the output voltage of a battery decreases (roughly) in proportion to the current drawn from it. This behavior is usually characterized as an internal resistance of the battery, although its actual physical origin may be related more to the chemical properties of the battery than to the actual resistance of any conductive part of the battery.
For the second part of your question, you'd need to consult the data sheet of the battery you are using. This has been discussed in a previous question: Internal resistance of batteries?
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H: Why can't a single-supply comparator handle negative inputs?
I tried simulating a basic comparator configuration in Proteus with only a single supply. The reference/trip-point is 2V. However when I simulated the DC transfer curve, all negative input voltages are saturated to +VCC and not to the lower rail voltage (+1V).
Why can't a single-supply comparator handle negative inputs? Why won't the output be at the lower rail when the noninverting input is negative?
The comparator that I used is LM311 with pull up resistor at the output.
AI: [ at end of this answer, we compare the LM311 with the LM339 (which will function down to GROUND)]
After examining the LM311 datasheet/schematic (from Texas Instruments page 10), here is what occurs:
signal comes to base of PNP level shifter, emitter current set by current source up at +VDD
the emitter of that PNP shifter comes to base of one NPN of a diffpair(A)
the collector of that NPN goes to load resistor, which is biased one_diode_drop below +VDD; this load resistor feeds the base of a 2nd NPN diffpair(B); with signal near ground, the headroom is quite large, so this does not upset the comparision balance.
THE LIMITING FACTOR is the NPN current mirror for tail current for diffpair(A)
SUMMARY: the input voltage is shifted up ONE diode drop, but then enters a stack of transistors (diffpair(A) and its current source) that needs TWO diode drops to function accurately.
Fundamentally that first diffpair/tailcurrent become CUTOFF.
Cutoff is a strong word; if the bipolar has 10mA at 0.8 volts Vbe, then at 0.4 volts the current will be (approximately) [ (0.8 - 0.4) / 0.058 ] = 0.4/0.058 ~~ 6 decades less current.
Again examining the LM311 schematic, if that constant current source (tail current, the first transistor from the lower left) is disrupted, then the base biasing (partly established by the solitary JFET) is disrupted, and the 2nd tail current is also disrupted.
Notice the collector resistors of the 2nd diffpair(B) are IMBALANCED. One is 750 ohms, one is 600 ohms. These two resistors control behavior of the rail_rail high_voltage amplifier, which has a constant_current pulldown and a NPN emitter follower which controlled the base of PNP which is making the crude comparison about "HIGH? LOW?".
There is a CLUE about imbalanced behavior as the Vin approaches -VDD. The imbalanced resistor values (top center) of 750 and 600 ohms are probably attempting to adjust for imbalanced Vbe of the NPN emitter follower and the PNP base connected to that emitter follower.
As the tail currents (constant current transistors, the 2 at very bottom left) are disrupted, voltage drops across 750 and 600 resistors may be the cause of output default behavior.
Regarding modeling in Proteus, I have no opinions.
You could BUILD one of these, using 2N3904 NPNs and 2N2906 PNPs. Just don't try to operate at 50 volts.
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Had the LM311 been designed 20 years later, good CMOS devices could have been used; FETs can be fabricated inside WELLS, and the WELLS can be tied to convenient voltages inside the circuit. Some diffpair WELLS are exploited to cause enormous increases in Vthreshold, and that effect allows Pchannel FETS to measure below ground, and allows Nchannel FETs to measure above VDD (this method is called "body effect" where the well/body/tub voltage is NOT same as the Source).
==========================================
Comparing LM311 to LM339
LM311 has PNP (moves signal UP) followed by 2_diode_drop NPN diffpair + NPN current mirror. This comparator in NOT spec'd to work down to GROUND.
LN339 has PNP DARLINGTON diffpair (uses 4 PNPs) and a current source up at rail.
This comparator is spec'd to work down to GROUND.
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H: Bypass cap on reference voltage?
For a voltage reference providing a reference to multiple devices, ADC, DAC, instrumentation amp... would there be some benefit in placing bypass caps right at the reference input to these devices even though they have high input impedance?
AI: Modern ADCs use charge_balancing or charge_eating conversion methods.
That means the VREF must supply big hunks of charge, very fast, or the internal binary_search behaviors will make WRONG DECISIONS. The "very fast" means less than 1 nanosecond, or as fast as a tiny onchip FET switch can turn on.
So yes, you need a bypass capacitor on the VREF signal.
ADCs use approximately 10pF in their internal charge_eating. I'd make the cap at least
10pF * 2^number_bits
Thus for a 16_bit ADC, use 10pF * 2^16 == 10pF * 64,000 == 0.6uF
For delta_sigma (or sigma_delta) oversampling ADCs, the conversion system will grab many hunks of charge during any single conversion. See what the datasheet or the manufacture Apps Engr suggests.
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If you use an OPAMP to buffer the external VREF, ensure the opamp will not oscillate or have a RINGING response to those 1nanoSecond demands for charge.
To model this, you need to know the Output Inductance of the opamp. The datasheets do not tell you this. But some datasheets do specify Rout. And all opamp datasheets are proud to tell you the Unity Gain Band Width.
So let us use Rout and UGBW to compute OutputInductance. (The Output Inductance comes from the 90_degree_phaseshift of the 1_pole rolloff, and the constantly falling open_loop_gain).
We know Z_inductance = 2 * PI * Frequency * Inductance; re_arrange that, to find
Inductance= Z_inductance / ( 2 * PI * Frequency)
Many opamps have an Rout of 100 ohms; some much higher (100,000 ohms for long_channel CMOS output devices; as low as 10 ohms or lower for fast bipolars).
And since we want the VREF buffer opamp to quickly re_settle, have UGBW = 10MHz.
Effective_Inductance = 100 ohms / ( 6.28 * 10MHz) = 100 / 63,00,000
Effective_Inductance = 1/630,000 = 1.59 microHenries
And if you use an external 0.6uF cap, the Fring will be 1,000,000/6.3 = 160KHz
Now you want to dampen that. Will the 100 ohms Rout of opamp be adequate?
With the 10MHz UGBW opamp, Rout of 100 ohms, and Cexternal of 0.6uF, we have 35 dB peaking at 165,000 Hertz.
Using 1 ohm external between UnityGain opamp buffer, and a 0.6uF cap,
we see (in Signal Chain Explorer) a 4.5 peaking at 150,000 Hertz.
Using 2 ohm external, and 0.6uF cap, we have 0.26 dB peaking at 90,000 Hertz.
Using 3.3 ohms (you can buy those), we have NO PEAKING, and are down 2.8dB at 100,000Hz.
Notice we now have a control_system design, with NO RINGING as the goal. And the present response is SLOW.
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Now let us use a FASTER opamp, and much smaller C_external, and larger R_dampen.
Use 100MHz opamp with Rout of 100 (1-0-0) ohms, and 0.01uF cap, and 1 ohm resistor. Notice the VDD bypassing on the opamp becomes a challenge and a part of the design, because at high frequencies, no opamp has any PSRR worth mentioning, so YOU must provide a very clean (well dampened) VDD.
With those params, the circuit (our magical VREF) has 11 dB peaking at 8MHz.
Let us increase Rdampen to 10 ohms (notice 10 ohms and 0.01 uF has 100 nanosecond time constant, needing 1,000 hanoSecond for 10 Tau settling which gives 87dB accuracy (10 nepers) on VREF.)
Result? NO PEAKING, and response is -1dB at 1MHz.
Notice a CLEAN VREF becomes a big deal. Of course, in a over_sampling ADC to get those 18/20/22/24 bit systems, you will have 100,000 samples of the VREF every second. Tho some audio quality ADCs with 192,000 conversions per second, seem to use well over 1Million input and VREF samples per second.
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H: Transformer Measurement and Simulation
I have a 220VAC:1200VAC 800VA 60Hz toroidal voltage transformer and I'd like to measure its parameters to simulate a circuit I'm gonna build with it, in order to understand better the transients. The measurements doesn't need to be very accurate. I have a very limited knowledge about transformers. My questions are:
Is it OK to measure the primary leakage inductance using and LCR meter @ 120Hz? The secondary should be open or shorted (and why)?
Is it OK to measure the secondary leakage inductance using and LCR meter @ 120Hz? The primary should be open or shorted?
Is it OK to measure the winding resistances with the LCR?
How to measure the magnetizing inductance and resistance related to core losses?
Also, I'm having trouble to simulate transformer models in OrCAD Capture CIS. Would something like this be fine for my analyzis?
AI: 120 Hz as a test frequency is close enough to 60 Hz to get reasonable results.
The problem when measuring transformer leakage inductance is that you cannot avoid measuring the combined primary and secondary leakages of the transformer i.e. you measure a composite number either referred to the primary (when the secondary is shorted) or referred to the secondary when you short the primary.
To do this you have to apply shorts to the winding you are not measuring. This means that the magnetization inductance is largely removed from the measurement. And, when measuring magnetization inductance you run the opposite winding open circuit so that the effects of leakage inductance are largely not considered when making the measurement.
Because the magnetization inductance is usually at least 20 times more that the leakage inductance, shorting the secondary puts the secondary inductance in parallel with the magnetization inductance and, the number you read is therefore mainly the leakage inductance (because it is so much smaller in value): -
So, for a 1:1 transformer (as an example) if the secondary is shorted, (and ignoring copper losses), \$L_S\$ becomes in parallel with \$L_M\$ and, because \$L_S\$ is around +20 times lower in value compared to \$L_M\$, \$L_M\$ is more or less removed from the resulting number.
Additionally, you only need to do one measurement of leakage inductance because, which ever direction you do it in, it will be a combined measurement of primary and secondary. So, choose a measurement winding and then short the other winding out.
I'm having trouble to simulate transformer models in OrCAD
If I am making a transformer equivalent model in a simulator I try and mimic the full circuit shown above. I cannot say why your model isn't working for you.
Measuring core losses is more problematic because you have to apply full supply voltage to the primary and use a watt-meter.
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H: How do these Zener diodes limit the maximum voltage seen by other circuit components?
This schematic is given in Texas Instrument's AN-1533 Application Note (Over Voltage Protection Circuit for Automotive Load Dump)
On page 4, the author says that the D3 Zener prevents the cathode of D1 from exceeding its maximum voltage of 35V.
Similarly, this same D3 Zener limits the Gate-to-Source voltage seen by Q2 to 20V.
How exactly is this limiting behaviour happening, and what would be the calculation that shows this at a Vin of 60V?
To me it looks like both D2 and D3 will breakdown and end up taking the full load current.
AI: D2 and D3 will limit the voltage, as they have limiting resistors, full load current does not go through them.
If there is 60V at Vin, and you assume the zeners to be ideal, D3 will limit to 6.8V and since current is provided only via resistor R3, there will be 60V-6.8V = 53.2V over R3, so only about 0.5mA will flow. So D3 protects the Vgs of Q2 and limits it to 6.8V.
Same thing with D2 really. D2 does nothing, unless voltage over R5 grows to 6.8V, and then it limits the voltage over R5 to 6.8V. This is the Vgs of Q1 it is protecting. And the current is again limited by R6, so only about 2.7mA will flow.
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H: Input filter on DC-DC converter when it is the only load on a source?
Many app notes recommend placing an LC filter on the input of a buck converter to stop switching noise travelling back and thereby affecting other parts of the circuitry. But in the scenario where everything in the circuit is powered off the buck converter which is connected to a say a battery, would you still get some benefit in terms of cleanliness on the output of the buck converter by having the input filter?
AI: would you still get some benefit in terms of cleanliness on the output
of the buck converter by having the input filter?
You would get reduced EMI and that could make a whole heap of difference if it allows your circuit//module/system to pass EMC regulations. If your battery has wires feeding your circuit then even more so because you don't want the battery and battery wires acting as a loop antenna and emitting any significant level of switching noise.
Even if you don't have wires (or the wires are very short), there is a still a loop formed because your battery has a large physical size compared to most other electronic components.
It is advantageous to use a shielded inductor and one that is self-resonant at a frequency (SRF) at least ten times (or more) than that of the buck switching frequency. Having said that, using one that isn't can be supplemented by a smaller value inductor in series that does have a high SRF. Sometimes it's a good idea to model these components and ascertain their net effect. Sometimes it's even beneficial to force the smaller inductor to self resonate at a frequency below its SRF in order to minimize EMI.
All tricks of the trade.
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H: Damping to reduce error signals
So ive been doing some research on how overshoot can be reduced in an AC servo position system. I found out that tacho generators are used connected from the load to the motor that drives this load. However I found out that it may cause velocity lag and error. I found out this can be overcome by replacing the tachogenerator with an RC network error rate damping but im not too sure about its operation, can someone explain it to me?
AI: For a servo position control loop then using a tacho-generator can reduce the speed at which the motor approaches the optimum demanded position. This means that there is less overshoot because the mass of the "thing" being moved is less likely to significantly overshoot the demand point because it doesn't have as much momentum/energy.
Because a tacho-generator produces an output voltage that is proportional to speed, that output voltage can be used to reduce the error signal and therefore control the speed of approach thus reducing overshoot.
Using R1, R2 and C in the circuit can do the same thing. If the output from the error detector circuit (not a great choice of words IMHO) is rapidly changing then the capacitor's impedance will be lower and the error signal amplitude will be reduced by the effect of the potential divider. For a steady error value, the capacitor will look like an open circuit and there will be no attenuation to the error signal.
Hence, the RC circuit behaves like a tacho-generator used to stop speed getting excessive.
However I found out that it (tacho-generator) may cause velocity lag and error
Both will cause velocity lag but neither will create an error unless the open-loop response is low in gain and there is stiction in the system
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H: Building primitive FGMOSFET for educational purposes
To illustrate how flash memory works, I thought to build a primitive FGMOSFET and show that it stores a single bit of information (charged, uncharged).
It would require a high voltage to charge, it could be unreliable and leak current, but it would show the basic idea, and I could disconnect and reconnect it, and show with a multimeter that it remains charged or uncharged.
Is that viable?
How would I do it?
AI: These FETs rely on tunneling.
To deposit charge into a bit, the insulation must be very thin, so under the stresses of high_voltage, the probability of electron movement becomes high/certain.
And afterward, with "normal" operating voltage, the probability of electron escaping becomes near zero, so the "bit" remains charged.
Thus you need to build a system with extremely thin insulation, that is of very high quality, very pure.
And with those skills, semiconductor fabs will want to hire you.
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H: 1-2 second home power loss: some circuits stay powered - computer doesn't turn off. How is this possible?
We've been having some local power outages which last for about 1-2 seconds and maybe at times are only 500ms.
I've noticed that we have two computers which stay powered and I'm trying to figure out why.
The first computer is a tower with a Gigabyte m/b, AMD chip, etc. which I have plugged into a power strip with a few other items.
I noticed that when the power loss occurred our wifi router and cable modem (on another circuit also plugged into their own surge protector strips) would both get rebooted. Other things (lamps, etc.) flicker off and back on.
I was guessing that it was because this computer happened to be on a home circuit that had nothing else on it and that was why it stayed powered.
This computer is plugged into a power protector strip but that's it.
Today I remembered my headless MacMini is also plugged into that same power strip (and obviously on the same home circuit) however, the 1-2 second power loss does indeed cause the Mac Mini to turn off.
There's another desktop computer in the house that is on a different circuit that also does not experience power loss during these outages.
Is this related to something about the power supply in my desktop?
Is it related to the home circuit I happen to be on?
Maybe you can't tell with this information, but I'm wondering if this is a common thing or if it just so happens that the two computers' power supplies / surge strip are helping in some way.
AI: its related to the (internal energy storage) power supply of the computer that remains functioning.
A load of 20 watts and energy storage of 200 watt-seconds would (at best) allow 10 seconds of operation.
If the power line voltage were 10% higher, just before the dropout, you'd get an extra 20% time.
Energy storage in a capacitor is
energy = 0.5 * C * V^2
Thus 180 volts on the cap, and 500uF, stores 0.5 * 0.0005 * 180 * 180 == 8 watt seconds.
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H: Validity of superposition when summing powers from each harmonic
In Boylestad's Introductory Circuit Analysis 13th edition page 1176, there's an example about working out the total power dissipated by a circuit fed a nonsinusoidal signal. The signal is decomposed into:
DC component: 63.6 V
Fundamental: 70.71 V RMS
Second harmonic: -29.98 V RMS
And the circuit is drawn like below in order to apply superposition.
(Not shown in the drawing above: the phase angle of the second harmonic is then changed to -90 so that all sources have the same polarity)
The current and average power for each component are found like this:
DC component
I0 = 10.6 A
P0 = I02R = (10.6 A)2 (6 Ω) = 674.2 W
Fundamental
I1 = 1.85 A ∠-80.96°
P1 = I12R = (1.85 A)2 (6 Ω) = 20.54 W
Second harmonic
I2 = 0.396 A ∠-174.45°
P2 = I22R = (0.396 A)2 (6 Ω) = 0.941 W
And the total RMS current and total average power are found to be:
Irms = square root ((10.6 A)2 + (1.85 A)2 + (0.396 A)2) = 10.77 A
PT = Irms2R = (10.77 A)2 (6 Ω) = 695.96 W = P0 + P1 + P2
Why the total average power equals the sum of the powers from each component if the superposition theorem can't be applied to power? I understand PT = Irms2R, what I can't understand is why it's valid to sum P0 + P1 + P2.
(For context: I'm reviewing a few fine points I may have overlooked during EE undergraduation years ago)
AI: Why the total average power equals the sum of the powers from each component if the superposition theorem can't be applied to power?
This is a consequence of Parseval's theorem, which says that the the integral of the square of a function is equal to the sum of the square of its Fourier series.
Put another way, the power in the signal is the same whether you represent it in the time domain or the frequency domain.
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H: Nichrome powder acting as a resistor
I’ve been doing some experiments recently with metal powders and I’m wondering if someone can help me interpret the results and give me some advice.
I wanted to test how the metal powder would work in a circuit. I tested some graphite powder and some nichrome powder.
I made a circuit using two AAA 1.5 V batteries in series and some PVC insulated solid core 1.5 mm diameter copper wire. I pulled some of the PVC insulation off the copper wire a little and then packed some metal powder into the tube. Next I pushed another copper wire into the tube. This made two pieces of copper wire connected by some densely packed powder. I then tested the amps running through the circuit using a multimeter.
The results were -
Control circuit (using only copper wire - no powder) 400 micro amps
Graphite circuit 10 micro amps
Nichrome circuit 0 micro amps
What happened here? Obviously the graphite has a much higher conductivity than the nichrome. Is the nichrome acting as a resistor in my circuit?
How can I get my circuit to run using the nichrome powder? Do I need to increase the amps with the batteries in parallel, or the volts with the batteries in series?
I know the conductivity of the nichrome in relation to the graphite - can I calculate how much more power is needed in the circuit based on a comparison of the conductivity of the two materials?
AI: Nichrome develops a passivation layer on its outer surface. That's what prevents it from oxidizing any further. Would a batch of nichrome powder even be conductive with so much surface area to oxidize?
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H: Some basic questions about an accelerometer's unexpected behavior while tilted
I have an ADXL335 accelerometer connected to my Arduino. Here is some code that I am running based off a tutorial:
xaccl[a] = float(analogRead(xpin) - 345);
yaccl[a] = float(analogRead(ypin) - 346);
zaccl[a] = float(analogRead(zpin) - 416);
float length = sqrt((xaccl[a] * xaccl[a]) + (yaccl[a] * yaccl[a]) + (zval[a] * zval[a]));
Serial.println(length);
When the accelerometer is flat on my desk, the vector length is around 128. When the accelerometer is tilted, the length of the vector increases even if it is not moving. The 3d vector length should stay constant regardless of the angle.
Could someone explain what is happening?
Also, what unit of
measurement does the accelerometer output? I assume m/s^2.
Lastly, some sample code I found for reading values:
xaccl[a] = float(analogRead(xpin) - 345);
yaccl[a] = float(analogRead(ypin) - 346);
zaccl[a] = float(analogRead(zpin) - 416);
Why is the code subtracting 345, 345, and 416?
AI: The vector magnitude is constant regardless of orientation, but you are applying offsets in one direction which throws off the symmetry.
You can't calibrate away gravity in only one orientation and expect it to work for all orientations. Thinking about what you did and if you flipped it upside down instead of a slight tilt. Would you expect it to be zero? It's adding all your offsets in the wrong direction.
Those gravity offsets are only useful if the accelerometer moves but orientation doesn't change. In that scenario, gravity is calibrated out because its direction and magnitude are always known.
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H: Which cable connection will result in a greater loss of power?
I know that running a power cable (the cable is carrying 5V DC, I plug in an AC to DC converter to the mains) that is, for example, 50m will cause losses in the power output. So if you measure at the source it will be 5V but when you measure at the end it might be 4.3V.
However, if I connect a mains extension cable that is 50m (the cable is carrying 230V AC) and then plugs in my AC to DC supply (this DC power cable is only 5cm) to my mains extension cable. Now I measure the output of the AC to DC power cable (at the end of the 5cm power cable) will I still get 5V or will the mains extension cable incur losses along the 50m and thus reduce the output of the AC to DC power supply from 5V to 4.3V?
Which is better Scenario 1 or 2, in order to minimize losses?
The AC mains extension is coming straight from the house's wall socket. There is no AC converter. just a three-pin plug plugged into the wall socket.
Please don't ask to go and buy a 50m AC extension cable and test it. This question is asking about the principle of running an AC extension or a DC extension in order to reduce power losses. What if the cable is 5km long....?
AI: You should run the higher voltage in the long cable. Higher voltage results to less current drawn for the same load.
Another reason is that the AC/DC converters usually have no problems providing stable 5 V even if the input drop a few volts. Some even work at a range from 100 V to 230 V, to be usable in ~110 V system.
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H: SRAM/DRAM Price Difference
An SRAM cell uses 6 CMOS transistors to store 1 bit of information. A DRAM cell uses 1 transistor and 1 capacitor to store a bit. So one could guess that for the same amount of information (say, 1GB), SRAM would be around 6 times more expensive than DRAM (if capacitors were free). In the real world, however, this difference seems to be much larger than a factor of 6. What's the reason for that?
AI: So one could guess that for the same amount of information (say, 1GB), SRAM would be around 6 times more expensive than DRAM (if capacitors were free).
Actually, making the capacitor is the hard part.
In the real world, however, this difference seems to be much larger than a factor of 6. What's the reason for that?
SRAM itself isn't that expensive when it's made at high volumes. Go buy a few hundred dollar GPU and you're getting a lot of SRAM, in some cases more than 100MB worth ... as well as thousands of graphics cores and gigabytes of GDDR. Factor in the fraction of the die that is actually SRAM (not that much) and the fraction of the cost that is the die and you aren't paying that much per MB of SRAM.
But if you're looking at discrete 512 Mbit SRAMs (rather than a similar amount of SRAM integrated into a GPU or similar mass market product), that's an extreme niche part made in tiny volumes and priced accordingly.
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H: Unknown indicator of package specification
I am creating the footprint of an IC, and the manufacturer has specified this below:
I cannot figure out what C0.3 stands for. Is it the length of the diagonal? If it helps, according to another drawing for this rectangular pad, X=1.55mm and Y=1.40mm
AI: C stands for chamfer in mechanical drawings.
C0.3 means that the chamfer is 45° and 0.3mm is the dimension as shown below on the X axis (also 0.3mm along the Y axis):
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H: What is the meaning of this schematic symbol (labelled COMP.J1 JPAD3)
I am trying understand the schematic for a Waveshare Core 407I board, with an STM32F407IGT6 MCu. What is the meaning of this schematic symbol (labelled COMP.J1 JPAD3)?
Link to full schematic: https://www.waveshare.com/w/upload/4/4a/XCore407I-Schematic.pdf
I've identified it on the board to be a blob of solder next to a square contact. What component is this if I were to draw it myself in an EDA program?
AI: It's known as solder bridge.
A solder bridge consists of two, closely-placed SMD pads that can be shorted easily with solder.
The one shown in the question is a 3-terminal solder bridge. Think of it as an SPDT switch. PDR_ON signal is the COMMON terminal. It can be shorted to either +3.3V or GND.
NOTE: Your EDA software (probably Altium) may not have a solder bridge component or equivalent. You may need to build your own.
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H: Adjusting Potentiometer Range
I'm using two 1K potentiometers and I want to achieve this result:
When the first pot is set to 1K (100%), adjusting the second pot should change the output from 0 to 1Kohms.
When the first pot is set to 500 ohms (50%), adjusting the second pot should change the output from 0 to 500ohms.
I have wired the potentiometer like this schematic. but the lower range changes too. for example when I set the first pot to 120 ohms, turning the second pot changes the output to Arduino from 60 to 120 when I want it to be 0 to 120.
I want the output to be linear. How can I approach this problem?
AI: Here's how, if I have understood it right.
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H: Need help with reading mosfet datasheet (safe operating area graph)
What does indicated time in below graph means?
datasheet
AI: What does indicated time in below graph means?
It's the length of time that the MOSFET can reliably conduct for the applied drain-source voltage and drain current. For instance, with a drain current of 10 amps, the drain-source voltage can be about 15 volts - that's a power dissipation of 150 watts and, that power can be "safely" dissipated for a maximum duration of 10 ms.
Or, if the drain-source voltage is 10 volts, the drain current could be around 15 amps. Again that's a power dissipation maximum of 150 watts: -
What you see is a constant power line of 150 watts and, given that case temperature and junction temperature are stated (25 °C and 175 °C), we see that the thermal impedance is: -
$$\boxed{\text{150 °C / 150 watts or 1 °C / watt}}$$
If the dissipation time period is reduced to 1 ms, then the drain current could be about 45 amps at a drain-source voltage of 10 volts - that's a power dissipation of about 450 watts
So, generally, the shorter the time period, the bigger the power event can be.
But, be very aware that approaching these limits must be done with proper consideration of ambient temperature and heat-sinking requirements as specified in the data sheet.
How SOA relates to transient thermal impedance (data sheet fig 11)
SOA stands for Safe Operating Area but it's sometimes better to think of it as showing the unsafe operating area! The Thermal impedance graph implies the same power vs time information: -
I've added three points to the above graph at: -
10 ms (1 °C / watt),
1 ms (0.35 °C / watt) and
0.1 ms (0.1 °C / watt).
I've covered the 10 ms thermal impedance further above.
At 1 ms, it's 0.35 °C / watt hence, with a maximum case to junction temperature difference of 150 °C we can expect to cope with a power of 150/0.35 = 429 watts. I estimated 450 watts from the earlier SOA graph and this ties in nicely albeit with some slight error. In other words, it's better to use the thermal impedance graph because it's more relevant especially when it also plots duty cycle - the SOA graph assumes a single pulse and is unrealistic in many practical cases.
At 0.1 ms the thermal impedance is 0.1 °C / watt and, with a case/junction difference of 150 °C, that allows a peak power of 1500 watts. If you look at the SOA graph for 0.1 ms, you can see that it bisects the co-ordinates 50 amps and 30 volts i.e. 1500 watts.
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H: How do you split a summing point into two?
I am solving a control system example on block reduction rules and stuck on this particular step. According to me, I can move the summing point ahead of the middle block to get G4 multiplied to both but that would not get the summing points in the form that they are in the next figure. Would appreciate any help or pointers on this.
AI: Start with this: -
Then, with the two summing blocks in the middle area you can combine them or separate them in many ways. This for instance: -
And it's a really small step to break them into two again: -
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H: Controlling Z axis placement
What techniques are there for placing the components on a PCB at a desired height? e.g. so that potentiometers and switches can be both panel mounted and board mounted?
For example, are there adapter components designed to lift other components away from the plane of the board?
Reading the answers here I'd guess that nobody has invented such a thing yet, and that instead PCB designers have just had to come up with ways around the problem such as wired connections, actuator extensions, etc.
AI: are there adapter components designed to lift other components away
from the plane of the board?
There are plenty of them. Here's one type for instance that uses plug-in headers: -
But, they needn't be plug-in headers. They can be soldered at both ends such as this: -
Or taller ones like this: -
You can get many varieties such as this range from Samtec (amongst others): -
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H: Position components in KiCad for a test rig
I'm designing a test rig for a product. There's a number of test pads and a power connector on the PCB, which I want to match up with a tester device, i.e. the tester PCB should have pogo pins and the mating power connector in matching places.
The question: given the PCB of the product, how do I export from KiCad, for example, a .dxf such that it has only a few of the components? I could simply export the whole PCB as .dxf and import that to the user.dwgs layer in the tester PCB, but this will have a lot of visual noise as all components are visible. Is there a way I could export only the few selected components (test pads and power connector), or perhaps some other easy way to guarantee that the tester PCB will match with the testee.
AI: ...or perhaps some other easy way to guarantee that the tester PCB
will match with the testee
The way I'd do it is this: -
Save the design under a new name (say "fixture")
Lock the mating components needed on the "fixture"
Delete all the components apart from those needed
Use this as the basis for your fixture design
Develop the fixture design but,
Make sure the component copper/pads/holes that align with the original PCB are position-locked on the fixture design.
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H: Is this analog switch good for UART lines?
Currently designing a circuit to switch between two UART lines using an analog dpdt switch. Been searching for a while and found the BL1532. The datasheet says it's a DPDT USB2.0 Analog Switch, but not sure if this chip will work for UART since USB is pretty fast (not an expert in this field).
Here is my circuit:
The MCU can communicate from 9600 to 115200 baud rate.
As you can see I drive the BL1532 select pin with an spdt switch for 3.3V HIGH and GND LOW. Any advice or opinion is appreciated
AI: The IC in itself should be fine. I didn't see anything in the datasheet which would indicate that it wouldn't work with the voltages or speeds you have in mind.
What I checked were the supply voltage characteristics and general voltage limitations on the pins.
I also checked that there is no indication of some DC blocking or differential signaling is going on.
For your schematic: I would use pull-ups on the RX lines (all of them, can be in the 10-100 kOhm range) to prevent glitches when switching between the modes.
And some current limiting resistors like 1 kOhm in the lines for the external connection, you might switch things up and then your MCU might get damaged. Series resistors help in this case.
And if your header is going to be used by "the general public" you should probably beef it up against ESD with some protection diodes at least.
Another thing which isn't shown if there is a common ground for the external headers available. That is needed for the communication to work. It might work ok on your test because you have a hidden shared common ground but will not work if you connect it to a battery running device.
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H: Can you dim already dimmed LED lights
Ive installed LED downlights in my room, these :
https://www.screwfix.com/p/lap-fixed-led-downlight-contractor-pack-white-370lm-5w-220-240v-10-pack/728fj
they are controller via a smart dimmer switch, this :
https://www.amazon.co.uk/gp/product/B07BKXMS6C/
they work fine, dim up and down but the lowest brightness is 10% (is still super bright), using the smart app you can set them to 1% which is much better
as the lights are all wired one to the next, to the next, i just wondered if i could permently reduce the current flow by using an inline resistor or an inline dimmer to lower the effective brightness? Basically so when the switch thinks the lights are at 10%, the power they are actually recieveing is more like under 5% brightness?
Im not an electricial so please dont shout at me if im asking for the impossible!!!
Thanks,
AI: What you want is not possible, these lights work from mains voltage (240 V AC) which the LEDs in the lamp cannot handle. So there's a power converter circuit present that transforms the 240 V AC into a (much lower) DC voltage (at a high current) that the LEDs can handle.
For dimming usually some form of PWM (switching on/off faster than human eyes can see) to reduce the power to the LEDs. Other dimming schemes are possible also.
You cannot control the dimming other than through the remote control because a smaller input voltage (for example 180 V AC) would be compensated for by the electronics. Or the circuit would just stop working properly.
The lowest setting at which the LEDs will work is determined by the design of the circuit that powers the LEDs. You can only influence the lowest setting by changing that circuit and that isn't something a beginner can do. It might not even be possible for an advanced engineer to do that as the components (chips) that are used might determine the lowest brightness setting.
So if you really need these lamps to output less light you will need to replace them with ones that have a lower light output (like 2 W instead of 5 W).
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H: FTDI and ST LINK devices together to STM32
I have an STM32 board (blue pill) that I am programming with the Arduino IDE.
I couldn't program it using an FTDI adapter because I couldn't make the Arduino IDE communicate trough the USART for uploading codes, so I am using a ST LINK V2 to program the STM32.
On the other hand, once the program is on the STM32 I can use the FTDI to communicate to the STM32 via the USART using the COM ports.
So, I am planning to use the FTDI when running and the ST LINK adapter when uploading codes.
My question (before I short circuit something doing it):
Can I connect the two devices to the STM32 and leave them connected to the host PC with power ON? That way the only thing I have to do is selecting one for programming and the other one when running. The STM32 is never connected directly to the PC. See picture.
AI: Having multiple interfaces connected to a development target is fairly common. When they all go back to the same PC, it's also fairly simple.
You should really make sure that only one source is providing power (ie the positive power supply line) to the target, for example, the USB connector on the board.
Normally each interface should have a ground connection, eg a "common ground" with the target, and by extension every other system the target is connected to. When everything goes back to your laptop over short USB-derived interfaces, you can sometimes get away with being sloppy, but still it's better that each cable assembly have a ground.
Note that an SWD connection typically does not provide power, rather a supply line present on one is formally supposed to be used as an input to a better tier of SWD adapter which will adapt its signaling to the voltage at which the target is operating. You don't show any connection there, which is probably appropriate; your clone adapter doesn't adjust its voltage anyway, it could (in deviation from tradition) supply a small amount of current to a target that doesn't need much power, but in your setup you seem to have other means of powering the board.
Your drawing is too pixelated to be certain, but it appears that you may be powering the board through the FTDI adapter. While this may work, it is probably unwise; the internal regulator in an FTDI chip is really only meant to power the chip itself, and extremely low power auxiliary loads. Depending on what you are doing, you might get away with that, but really it is not the best idea. Your target board has its own regulator, which you should probably utilize either by feeding power through the USB connector or via some other 5v input line on the board.
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H: Damaged OLED LCD voltage regulator replacement
I have a 128*32 OLED LCD that is used with an Arduino. I recently damaged the voltage regulator and was hoping to be able to repair the board by soldering off the damaged component and replacing it with a new component. What should I replace it with? The datasheet can be found here: https://www.waveshare.com/wiki/0.91inch_OLED_Module
AI: Easiest to just replace it with the component you removed unless there's something else that makes more sense based on how you damaged it?
Schematic calls out a XC6206P332MR-G which outputs 3.3V based on a ~5V input. Were you trying to use this with a 12V supply when you broke it?
If you have another good source of 3.3V somewhere in your project you might not even need the voltage regulator so you'd just desolder and pump in 3.3V from that 3.3V supply to the desoldered pin where you need it.
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H: Why does voltage drop across resistance contradict Ohm's law?
Very basic question here.
I have been learning a ton about Ohm's law, and I don’t seem to ever be able to completely understand it.
One of which I am getting particularly confused about is voltage drop and Ohm's law.
According to what I know about Ohm's law, if you increase the resistance, the current decreases, but the voltage stays the same. See below figures:
From: learn.sparkfun.com
Example:
Here is a graph of the voltages of my 5V battery with resistors in the circuit:
simulate this circuit – Schematic created using CircuitLab
The questions I have are:
What are the physics behind this?
Is there another law that covers this?
Why does this contradict Ohm's law, or is there something that makes this inline with Ohm's law?
AI: Firstly, Ohm's law only states that current through a metallic conductor is directly, proportional to the potential difference across it. There are several cases like semiconductors, electrolyte solutions, gas mediums where ohm's law does not apply.
According to what I know about ohms law, if you increase the resistance, the current decreases, but the voltage stays the same
Yes, if the driving source is an ideal voltage source, the voltage across the resistance will stay the same no matter the magnitude of the resistance.
But, if it is an ideal current source,the the voltage WILL change according to the resistance connected across its terminals, but the current will stay as a constant. Both the scenarios satisfy Ohm's law.
However, In reality, I know there would be a voltage decrease if I “increased” the Resistance.
This case, I assume you are talking about a real voltage source, for e.g, a dry cell. And by increasing the "resistance", I can only assume you are talking about increasing the load since in real life increasing the resistance will not decrease the voltage output of a real life voltage source.
Please not that any and all voltage sources in the real world has some internal resistance. See figure below,
Here when current flows in this circuit, due to ohm's some voltage has to be dropped across the internal resistance r, causing the output voltage, i.e, the voltage available at cell terminals across resistance R, to drop or increase as R is decreased or increased.
I hope this clarifies your doubt.
EDIT:
Please note that the circuit you provided is an improper method for measuring voltage across an element. Here you are not measuring the voltage across the resistance but you are measuring the voltage a across the cell terminals with the series resistance appearing as the internal resistance of the cell. So, it is wrong to apply Ohm's law the way you stated in this scenario. Remember voltmeter is connected in parallel while ammeter in series.
Here in this scenario the internal resistance of the cell increases and it act like a dead cell, with diminishing voltage.
The reason for this is that every analog voltmeter has an internal series resistor which can hamper the reading if the internal impedance of the source too high. An analog voltmeter needs a minimum current through it for the pointer to move as it employs electromagnetic effects. If the internal impedance of the source is too high this minimum current will not flow and the meter will show less than it should. For example a voltmeter might need 100microamps for full deflection, if the internal resistance of source limits this current to 95 microamps from the same source, the meter will show a less small value.
In the case of digital voltmeters, there too exists a potential divider network plus the input impedance of the active device(s), which will also give low value readings it the driving source have too high impedance.
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H: Sourcing Transformer with Specific Turns Ratio
I am looking at a building an electronics project that calls for a transformer with a specific turns ratio '1:4:50', and am trying to source a component. I am working on the project from this tutorial: https://circuitdigest.com/electronic-circuits/diy-stun-gun-circuit
When I search power transformers on Mouser or Digi-Key there is no option in the parametric search for turns ratio. The only category that does have a turns ratio option is 'Current Sense Transformers', but after reading up on these devices (used for metering AC current draw) they seem incorrect for my application. The purpose of this project is to use the transformer in "flyback mode", building up a large DC charge from a small AC signal at the input. I am assuming for this application I need a power transformer.
This part has been weirdly impossible to source, which seems strange as the application isn't that esoteric. Can anyone give advice on how I would go about searching for correct component?
AI: Transformers are difficult to source in general. My recommendation based on past experience designing low volume one-off flyback transformers is to build your design around the transformer, not vice-versa. Coilcraft is an example of a company that sources stock transformers suitable for flyback applications.
I'm providing this as general advice for people designing transformer-based circuits. DO NOT use this design, or one like it, on a human being. High voltage converters are not toys and should be taken seriously.
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H: Using audio isolation transformer to clean power to a Raspberry pi
I want to "clean up" the powersupply to a raspberry pi that I am using for audio recordings.
I am getting a lot of low frequency buzz, i.e. 60 to 2000 hz.
I am wondering if I can use an 1:1 audio transformer to reduce the interference from the PSU to the pi, alternately to isolate the usb-soundcard power that I suspect may also be culprit.
The pi PSU is 5.1v 3A
THis is the transformer:
Max voltage: 100V
Isolation coil+coil: 100Mohm min
Dämpning Dampening: 2.5dB max (1kHz)
Primary impedans (1kHz): 600ohm ±5%
Secondary impedans (1kHz): 600ohm ±5%
Primary DC-resistans: 50ohm ±5%
Secondary DC-resistans: 60ohm ±5%
Primär induktans (1kHz): 310mH
Sekundär induktans (1kHz): 330mH
relationship: 1:1
(please excuse my poor translation of technical terms)
EDIT
From what I have gathered in many posts poor power supplies(PSUs) can give interference in auxiliery equipment plugged into the Pi, e.g via USB or GPIO.
As for audio the answer to this post gives an example of a homemade PSU that provides "clean" power to the RPI to improve sound recording. However, this is takes a little too much space for the project I working on (networked wildlife cameras). Theoretically using powerbanks should be better than regular PSUs but powerbanks have their own step-up or step-down circuits that I find give as much intereference.
What I am looking for is a simpler, "good enough" solution to filter power to either the Pi or the USB soundcard so that I can remove some of the noise in region I want, i.e. 50 to 3000 Hz. How can I create a filter from 50 to 3000Hz?
Is the culprit likely to be the PSU or the pi itself?
Should said filter be placed between PSU and pi, or between soundcard and pi?
AI: Probably the black_brick power supply is your problem. Those supplies have a large capacitor (several nanoFarads) from primary to secondary, so as to pass the FCC interference tests. But lots of fast-edge trash also gets coupled from secondary to primary, and like all charges,
will explore and use ALL POSSIBLE PATHS to get back home
To block those charges, you need a common_mode filter, and possible differential_PI L+C filters (here "differential" means FerriteBeads in both
DC_GROUND
and in
DC_RAIL
Those black bricks are cheap, and you get the noise_supression you have (not) paid for. So you get to add noise suppression.
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H: Is this signal reflection or a damaged transmitter?
This is (an isolated, differential) capture, 1µs/div, of some Profibus communication over about 10m of cable. The first image is typical for about 90% of packets and seem fine. Most are +/-5v with slight deviation from device-to-device as they reply with data. Transitions are ok with a little ringing evident:
But this is what happens when one particular Profibus device replies:
This output is complete garbage and generates Profibus errors. Only from this device... other devices (same bus) work fine. Which seems to infer that the cable must be ok and that this device can listen just fine, since it does try to reply.
From this capture, is it discernible whether the issue is an open terminator at the device, or a damaged transmitter? To me, it looks the transition timings are still good but it's swamped in reflections or some crazy additional inductance, leading to peaks as high as +/-10v. What is going on here?
Edit: suspect device is a Beckhoff brand BK3150 model "PROFIBUS Compact Bus Coupler." There are several, and the others work fine; just one in particular sends garbage. Speed is 1.5Mbaud. Connector is DB-9, such as this.
AI: It's hard to tell. What I have learnt from Profibus is that usually the problem lies elsewhere, but not near the device with comm. errors. It can drive you crazy, so forget about that specific device, search entire bus. Measure the resistance A to B, A to GND and B to GND. If you have the possibility, get the Siemens Profibus tester BT200, it's the best tool I have tried so far (tried: DSO, Profitrace).
Some non-Siemens connectors have a GND pin, spike like shaped to grab the shield - well they damage A and B wires, too. The ones on the photo are problematic, the wires can break when you mount it. The best so far are Siemens Fast Connect.
If you undo the wires, you have to redo the connection by cutting a piece of cable and strip again. Original Siemens stripping tool is highly recommended, we don't strip any cable (profibus or profinet) without orig. tool - too many times we spent hours, days to find the problem like you.
I do suggest you to redo all the bus, with correct tools.
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H: Should a diode and/or transistor be used with an automotive (Bosch style) relay for accessory power?
I am a total beginner with electronics, so I apologize if this question has been answered already, I find similar questions but they seem to always be some variant and not quite what I am seeking, so I am asking here..
My automobile has power ports (cigarette lighter) that is always on. If I forget to unplug my dashcam I have a dead battery in a couple of days. To avoid this I would like to add a relay and tap into the accessory position circuit. Seems pretty straight forward, but then I see a bunch of videos on the importance of diodes due to kickback voltage as the magnetic field on the coil collapses which could cause a problem with the trigger circuit. When looking at the image below we see a manual switch activates the relay...
... but my automobile has something called "Retained Accessory Power" (A.K.A., RAP) which is what I will attempt to tap into. My concern is that a voltage spike on this RAP circuit could be problematic. So I am seriously considering using a diode. Then when I investigate all the circuits I find describing diodes includes the use of a transistor too. Question: Should I use a diode? Should I use a transistor? If so, what kind/size? Using this image as an example, how would the diode and/or transistor be wired to protect the trigger circuit?
AI: You should put one in though it is not as critical in this case since the a manual switch is a lot hardier to voltage spikes than a transistor which is often the first thing to blow from the spike. Even so, having one will prevent the switch from arcing and wearing it out.
You should put one in anyways just so the spike doesn't affect other things connected to your battery. Place the diode parallel to the relay coil in the direction that does NOT normally conduct current and short the battery out.
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H: Is voltage selector on 5v or 3.3v?
I bought this USB to TTL converter and it came with the option to switch between 5v and 3.3v. I want to use it at 3.3v, but I'm not sure where the (grounder?) should be placed? Thanks, see image below. (5v and 3v3 option is on the side upside down).
AI: Based on the photo, the thing is set for 3.3 Volts. To set it for 5 V, move the black jumper to cover the center and right pins.
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H: Duty cycle of 555 timer
I am trying to understand the exact working of this circuit, I have been told that this circuit provides a duty cycle of 50% from my previous questions, the same which I successfully verified in LTSpice simulation also, but when I built the exact circuit on a breadboard and observed the waveform on a CRO, I got the following which is clearly not 50%.
I have used the exact same value of components except for R4 which is variable. Can someone tell me what the mistake is as to why I am not able to obtain a 50% duty cycle?
My ultimate objective is note down the corresponding frequencies for different values of R4, but I am confused whether to consider the ON time or OFF time for my application since both are different now?
Apologies if the time scale data of the CRO isn't clear.
AI: The circuit is theoretically correct, the faults are probably due to the assembly.
(Is R2 likely to be connected to the Discharge pin?) R1 is not required for proper operation at all. The frequency depends on R4 and the duty cycle is always 50%.
EDIT:
NE555 at 3V. You built it well and measured accurately. :)
The NE555 need a minimum operating voltage of 5V.
NE555 at 5V:
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H: Building a power strip from scratch
I'm considering building my own power strip for multiple different reasons.
I've been trying to research these, but haven't found much information.
I obviously know what makes up a power strip, but I'm wondering if the copper(?) rails within the strip housing are something you can buy premade and then build the housing myself? If so, what would these rails be called?
Thanks!
AI: No, you can't make outlets from scratch like that. You must use UL-approved outlets from the hardware store; otherwise, your insurance company could deny your claim when your house burns down.
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H: Configure SPI Slave to handle data coming at the wrong time
I am experimenting with the SPI protocol (fast speeds where 5 bytes of data is transferred in slightly less than 500us) on the STM32F410 configured as a SPI full duplex slave. A master device sends a command byte to the STM32F4 and the STM32F4 responds with 4 acknowledge bytes followed by a routine that executes at about 1.3ms (measured through the DWT clock cycle count). This 5 byte data transfer is expected to happen around 25 to 27 times a second.
I notice that sometimes, the master device can send the exact same data consecutively in a span of 90us (The STM32F4 slave should expect to receive alternating data through SPI in a span of at least 4ms in between). I have attached screenshots of the logic analyzer showing this occurrence:
The first 0x42 byte received is to be expected, and the STM32F4 slave responded with the appropriate bytes (note that the second 0x42 afterwards should not be there):
The second 0x42 byte received should not have occurred (Master device cannot be configured/programmed in this scenario):
After the occurrence above, the STM32F4 slave could never respond to the master device correctly again (the acknowledge bytes sent back to the master is always 0x99 - which is the byte configured in the SPI interrupt send buffer):
In this situation, I tried removing the function call __AppliSendBuff(), which commands an RF transceiver to transmit data, and when the unusual occurrence happens, the STM32F4 slave is still able to correctly respond to the master.
My question is: How could I ignore the SPI data coming from the master at unexpected times? Why is it that one failed SPI transaction causes every other future SPI transactions to fail? What precautions should I take when writing code for the STM32F4 slave?
What I tried: Disabling the SPI_CS GPIO interrupts whenever the CS chip is pulled down so that in the middle of the whole process, the SPI transaction would not occur until I re-enable the SPI_CS GPIO interrupt. Before this change, in the second 0x42 command received, the STM32F4 slave would just respond 0x99 to the 0x42 and 0xFF's tailing the 0x42. Despite this, every other SPI transactions still fail and the slave would respond with 0x99's.
My STM32F4 code:
The interrupt segment:
/*** STM32F4 INTERRUPT HANDLERS ***/
/* GPIO Interrupt Handler */
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
if(GPIO_Pin == SPI2_CS_PIN) {
/* Temporarily disable SPI2 CS interrupt */
HAL_NVIC_DisableIRQ(EXTI1_IRQn);
/* Generate interrupt flags when master device sends SPI data */
/* dummybyte is a uint8_t array of size 1, with the element being 0x99 */
HAL_SPI_TransmitReceive_IT(&hspi2, (uint8_t*)dummybyte, (uint8_t*)pSpi2RxBuff, cSpi2RxLen);
}
else if (...) {
...
}
}
/* SPI Interrupt Handler */
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
if(hspi->Instance == SPI2) {
if (...) {
...
}
else if(pSpi2RxBuff[0] == 0x41) {
/* Activate 0x41 flag for further processing in main loop if 0x41 was received */
xFlag_41 = SET;
}
else if(pSpi2RxBuff[0] == 0x42) {
/* Activate 0x42 flag for further processing in main loop if 0x42 was received */
xFlag_42 = SET;
}
else {
/* Discard data by doing nothing */
}
}
}
The main loop:
while (1) {
if(xFlag_41 == SET) {
/* Respond back to system with acknowledge bytes */
HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)pSend41Data, (uint8_t*)pTempRxBuff, cSpi2TxLen, SPI2_TIMEOUT);
/* Commands RF Transceiver to transmit data respective to received command from master */
__AppliSendBuff(&command41);
xFlag_41 = RESET;
/* Re-enable SPI2_CS interrupts. Note that priority was set in MX_GPIO_Init() */
HAL_NVIC_EnableIRQ(EXTI1_IRQn);
}
else if(xFlag_42 == SET) {
/* Respond back to system with acknowledge bytes */
HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)pSend42Data, (uint8_t*)pTempRxBuff, cSpi2TxLen, SPI2_TIMEOUT);
/* Commands RF Transceiver to transmit data respective to received command from master */
__AppliSendBuff(&command42);
xFlag_42 = RESET;
/* Re-enable SPI2_CS interrupts. Note that priority was set in MX_GPIO_Init() */
HAL_NVIC_EnableIRQ(EXTI1_IRQn);
}
}
Do I also have to configure the SPI slave to transmit 4 dummy bytes (maybe to flush the SPI data registers) in the event that I do receive a junk/unregistered command byte?
Thank you!
Update:
I omitted disabling the CS Line interrupt disable (which is a GPIO interrupt disable) and moved the flag reset actions to be the first line in the else if blocks and there were some changes shown in the logic analyzer (the first correct sequence was still the same):
Second incorrect sequence:
0x41 exactly after the second incorrect sequence above:
0x42 exactly after the 0x41 above (incorrect bytes sent back to master):
And all the bytes exchanged afterwards are as below (regardless 0x41 or 0x42):
I forgot to include the Interrupt Priorities in the original post above:
/* SPI CS line has the highest interrupt priority */
HAL_NVIC_SetPriority(EXTI1_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(EXTI1_IRQn);
/* SPI Peripheral connected to the master device */
HAL_NVIC_SetPriority(SPI2_IRQn, 1, 1);
HAL_NVIC_EnableIRQ(SPI2_IRQn);
AI: I'm having a little trouble following what happened before you added the GPIO interrupt, and after. If I understand correctly, what was happening before you added it was:
After the first (correct) sequence, you come out of the ISR with xFlag_42 set, and so eventually you end up in __AppliSendBuff(&command42).
Midway through the __AppliSendBuff, the interrupt reasserts due to the incorrect sequence.
The ISR sets the buffer to send 0x99, and returns to the point where it was executing before it got the interrupt.
The next line unsets xFlag_42, and so 0x99 is sent after that.
That all makes sense. From your description, it sounds like subsequent transactions would also receive the 0x99 response, which doesn't make sense to me, since the whole thing should start over at that point.
Things become considerably more complicated when you add the interrupt to disable the GPIO. You don't mention what the interrupt priority is, but overall you have two ISRs messing about with the SPI buffer, one after the other, and that is probably not what you want.
You could try moving this xFlag_42 = RESET; to be the first line of the else if. That would result in the whole thing executing twice. If that result is undesirable, you could add a flag that says you're in the processing the first traffic, and write your ISR so it returns immediately without doing anything if that flag is set.
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H: Applying Thevenin's theorem between 3 points
I'm studying about transistor polarisation and got confused by this application of Thevenin's theorem, can someone please explain why eT is between B and M and why Vcc stayed even though it's not removed when finding eT? I'm not familiar with using Thevenin's theorem to a charge that's connected to the circuit via 3 points.
AI: The images you gave are IMO a kind of roundabout way of the following:
simulate this circuit – Schematic created using CircuitLab
This circuit is equivalent to the one shown in your figures. And calculating the Thevenin-equivalent of the boxed part will get you your answers:
$$e_T = \frac{R_{B1}}{R_{B1}+R_{B2}}\cdot V_{CC}$$
$$R_T = R_{B1}//R_{B2}$$
\$e_T\$ is the output voltage of the boxed part if Q1 is not connected, or in that case \$v_B = e_T\$. After connecting Q1, the voltage \$v_B\$ will be partially pulled to GND via \$B\$ -> Base-Emitter-diode -> RE -> GND. Hence,
$$e_T > v_B > v_M=0V$$
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H: Relays and mains voltage (Europe 220V+US 120V)
I initially used a DPST relay to switch both the live and neutral inputs of a computer, but someone told me it was a bad idea and that I should only switch the live input.
I live in Europe and here we have power strips with DPST switches. It is mandatory in some countries to install two pole switches in bathrooms. Plus RCD (EU equivalent to GFCI) is present on every plug (if the electrical installation was updated within the last 20 years that is).
But it's technically possible to plug your device into a socket that is not connected to earth (non polarized plugs)...
I know that the US system is completely different. So here's my question:
If I want to design a universal system with a relay that switches on/off mains power (ie 120V US AND 220/240V EU), what kind of relay is safest to use? 1 Form A (SPST) or 1 Form C (SPDT), 2 Form A (DPST) or 2 Form C (DPDT)?
Thanks!
AI: Well, you don't have to blindly believe everything you are told on the Internet. Someone saying so can be wrong or just trolling.
Safest is to switch both live and neutral, because in some countries you can freely orient the mains plug in any orientation so you don't know which of the wires is live or neutral.
Another thing is if you plug the computer into old ungrounded plug, and only switch off the neutral wire by accident, you have a metal PC case connected to mains live via a capacitor, and that's dangerous.
Oh and old buildings do not necessarily have grounded outlets or RCDs so do not build anything that relies on the electrical system to be newly installed.
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H: Connecting iM881A-M to Arduino
I want to connect iM881A-M LoRa module to arduino.
And I want to ask which external parts I need to connect it.
In datasheet there are many parts that I think I don't need to use.
Please help me , I am only student.
AI: You will need the filter C1 over the power supply, but all the switches and LEDs seem to be for debug and indication. It would be recommended to have them especially during bring up. Once you are happy with its functionality you could possibly remove some of the LEDs / Switches.
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H: How to measure the On/Off current ratio in TFETs and MOSFETs
I saw the conventional understandings other questions: MOSFET ON and OFF current
As I know, the off current is not zero, however very small, in the cut-off region. When we discuss TFETs, one of the critical issues is On/Off current ratio. And the characteristics of TFETs are quite different from the MOSFETs'.
Can we measure the On/Off current ratio from transfer and output characteristic curves? If there are many ways to measure, at least I would like to confine it to low power devices. And, I read that somebody talks with the figure of merit. What is it?
AI: How do I measure the On/Off current ratio?
I found the following picture of an output characteristic on Wikipedia (note that the y-axis is log-scale, so the drain-current never reaches zero). I am not familiar with TFET's, but if the principle is similar to that of CMOS we'll be fine.
The ON-current would be the current that you achieve at a logical "high" gate-voltage. This high voltage will depend on the process that you're using. Similarly, the OFF-current would be the drain current with a logical "low" gate-voltage. The ratio, I imagine, is then the ratio of these two currents.
Both of these curves were measured at a constant drain-source voltage, and if you wish to measure the worst-case scenario you may want to measure a few curves.
So you simply need to know:
\$i_{On} = i_{DS}\$ at \$v_{GS}\$ HIGH and \$v_{DS}\$ constant.
\$i_{Off} = i_{DS}\$ at \$v_{GS}\$ LOW and \$v_{DS}\$ constant.
From which kind of curves you get these numbers don't matter.
What is a Figure of Merit (FOM)?
A FOM is pretty much an invented quantity that tries to eliminate known intrinsic properties and constraints to compare performance across different technologies, implementations, etc. A FOM is constructed in such a way that a higher FOM is better. The world of FOM's is a pretty vague one, as a FOM can apply to specific target applications, and can change shape depending on how or who you look at it, making it a more subjective part of research. My advise to you is - whenever you're dealing with FOM's - not to get hung-up too much over it.
For example, the OFF-current in a CMOS transistor depends on the width of the transistor (\$i_{Off}\$ ~ \$W\$). So if we say that our CMOS transistor has a lower/better \$i_{Off}\$ than someone else's transistor, then you could just be using a smaller transistor and you might be reaching the wrong conclusion that your technology is better than his.
It makes more sense to calculate \$i_{On}/i_{Off}\$ because this figure is independent of the width, hence the On/Off current ratio can be considered a FOM.
Things can get much more complicated quickly as you find out more and more things. For example, I came across this FOM for CMOS transimpedance amplifiers:
$$FOM = \frac{\sqrt{BW}\cdot R_T\cdot C_T}{Noise\cdot P}$$
(\$BW\$ = bandwidth in GHz, \$R_T\$ is the TIA gain, \$C_T\$ is the input capacitance, \$Noise\$ is the noise in \$pA/\sqrt{Hz}\$ and \$P\$ is the power in mW)
This FOM allows us to compare CMOS TIA's with different BW's, gains, capacitances, noise and power consumption. To the average designer, this can be interesting; however, in an application where you're only interested in bandwidth and power consumption is not an issue, this FOM may not be useful to you.
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H: Voltage divider for a voltage range spanning negative voltages
We have a sensor giving out a signal between -10 V and +10 V, and a signal acqusition device that only accepts voltages between -2 V and +2 V. So we need to scale down the signal into the smaller range. As possible solutions I have identified:
A. Use a voltage divider
Following the information in this page: https://learn.sparkfun.com/tutorials/voltage-dividers, I could use two resistance, R1 = 5000 Ohm, and R2 = 1200 Ohm.
I am not sure what am I allowed to use a Ground. Both devices (sensor and acqusition) have a ground connection, which are connected to each other. Can I use this common ground as for the ground of the voltage divider ?
The impedance of the signal acquisition device is specified as 1 MegaOhm. Why is this value given at all? Should I include it somehow in my voltage divider calculations ?
B. Buy some off the shell device
I have seen some voltage down regulators, but they appear to only address power applications. I assume they are too noisy to be used for sensor read-out. Furthermore, there appears to be no device offering downscaling negative voltages.
Are there commercial voltage downscaling devices made for sensor reading ? I am not familiar in this area and I might be just ignorant of a family of devices that already does this in a plug an play manner.
AI: I am not sure what am I allowed to use a Ground. Both devices (sensor and acqusition) have a ground connection, which are connected to each other. Can I use this common ground as for the ground of the voltage divider ?
If your circuit has a ground, then that's the one you need to use here.
The impedance of the signal acquisition device is specified as 1 MegaOhm. Why is this value given at all? Should I include it somehow in my voltage divider calculations ?
The impedance is in parallel with R2. If it is much greater than R2, you can ignore it. If it isn't, then you need to ensure that your voltage divider gives the correct scaling using R2 in parallel with the input impedance, rather than just R2.
Are there commercial voltage downscaling devices made for sensor reading ? I am not familiar in this area and I might be just ignorant of a family of devices that already does this in a plug an play manner.
I'm not aware of any, but that doesn't mean they don't exist. A high-impedance op-amp set up to give the desired gain would make an alternative to a simple resistive divider.
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H: I2C bus level shifting
I want to interface with two I2C slaves operating in different voltages. By searching around for possible solutions, I stumbled upon this AN by NXP. Although I understood everything and makes perfect sense, I am still a little skeptic about it for possible pitfalls since I don't want to ruin the entire design due to I2C interface failure.
The slaves operate in 1.8V and 3.3V respectively, the I2C clock line should operate in 400 kHz (both devices support that) and the master has configurable I/O levels, so I can connect it on either side. I am thinking of using either a single SSM6N7002KFU or two 2N7002NXAKR for the job.
As far as I can see, it should work fine. Am I missing anything?
There is, also, the option to connect the ICs separately, so each one has its own dedicated bus and voltage levels, but I would like to avoid that for obvious reasons (layout + firmware complexity).
AI: After some serach on web I have found TI LSF0102.
CERN
Intel
There are also other possibilities, different packages, other manufacturers. What's important that those devices are made just for resolving your issue, high speed, stable.
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H: Digital control stability for more than impulse response stability?
I have a digital control system which is described by the transfer function
$$
Y(z) = \frac{-\beta}{z - 1 + k \beta} X(z)
$$
where \$\beta\$ is a real parameter I can adjust to modify the characteristics of the system, and \$k\$ is a positive real constant.
Using the BIBO stability criteria that the poles must be inside the unit circle, this means that for BIBO stability I need
$$
0 < k \beta < 2
$$
which is exactly what I observe when \$x[n]\$ is an impulse response:
$$
x[n] = \begin{cases}0 & n < 0\\
x_0 & n \ge 0\end{cases}
$$
However, I am trying to design my system to handle "arbitrary" inputs. For example, in the above example suppose I have an input which jumps between two values:
$$x[n] =
\begin{cases}
x_0 & n~\text{is even}\\
-x_0 & n~\text{is odd}
\end{cases}
$$
The z-transform for this particular input is
$$
X(z) = x_0 \frac{1 - \frac{\cos(\pi)}{z}}{1 - \frac{2 \cos(\pi)}{z} + \frac{1}{z^2}} =
x_0 \frac{z (z + 1)}{z^2 + 2 z + 1}
$$
If I try to simulate the system with this input, for \$k \beta > 1\$, \$y[n]\$ actually tends towards \$\pm \infty\$ (oscillating), which I would consider unstable, or at the very least unacceptable.
How would I go about analyzing (and designing) a control system when I have to consider other possible input responses than just the basic impulse response? Are there any useful search terms I could use for solving this type of problem?
AI: There might be a problem with your simulation, because for an oscillating input signal (with constant amplitude), the output is also an oscillating signal with constant amplitude, as long as the system is stable, i.e., as long as \$0<k\beta <2\$ is satisfied.
For the given oscillating input signal, the output is given by
$$y[n]=\frac{\beta x_0}{2-k\beta}(-1)^n,\qquad 0<k\beta<2\tag{1}$$
Of course, if the input is switched on at some finite point in time, there will be transients before the output approaches \$(1)\$, but these transients will decay as long as the stability condition \$0<k\beta <2\$ is satisfied.
For values of \$k\beta\$ close to \$2\$ you might be observing the transient, which will increase in amplitude for quite a while, but the output will finally settle at its maximum amplitude \$\beta/(2-k\beta)\$, which can be quite large for values of \$k\beta\$ close to \$2\$.
The figure below shows the output for an oscillating input signal (\$x_0=1\$) starting at \$n=0\$, and for two different values of \$k\beta\$:
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H: How to calculate base resistor of a NPN transistor that drives a MOSFET?
I'm currently trying to design a circuit that allows me to control a water pump running on 12V through an ESP32 microcontroller. The GPIO pins deliver only 3.3V, so I ended up controlling a NPN transistor (e.g. 2N2222) with the microcontroller and the transitor is connected to the MOSFET. Below is a schematic of what my circuit looks like:
D7 is connected to the microcontroller. My question is: How do I know what value of resistor I should use for R2? Usually that isn't such a big problem to figure out, but since I'm using a MOSFET I'm not quite sure how to do it.
AI: The circuit won't work regardless of the value of R2. The MOSFET will remain partially on all the time (due to R1), and possibly burn up. Even if R1 was to ground, the emitter-follower would only give you 2.6V from a 3.3V output regardless of whether the supply is 5V or 12V.
You could do something like this (logic is inverted):
simulate this circuit – Schematic created using CircuitLab
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H: when should I use a tuned amplifier circuit compared to a LCR bandpass circuit?
I am reading Microelectronic Circuits by Sedra and Smith. When should I use a tuned amplifier circuit compared to a LCR bandpass circuit? The text does not explain it well.
AI: When should I use a tuned amplifier circuit compared to a LCR bandpass
circuit?
In power applications, you have to use passive components for filtering because to try and use a transistor or amplifier is missing the point. So, if you have a QI type charger circuit and you are trying to pass energy from a transmit coil to receive coil, you would only use passive components for producing voltage amplification efficiently. There is no feasible option to use regular amplifiers tuned or otherwise.
However, if you are trying to amplify an RF signal prior to demodulation it makes sense to use a tuned amplifier because you are trying to increase the power of your signal.
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H: How to drive a PMOS with higher Gate than Source voltage?
I want to switch on/off a sensor which runs at 3.7V using a logic level P-Channel Mosfet. Unfortunately, the microcontroller which drives the P-Channel Gate is powered with a higher voltage (5V) compared to the PMOS Source voltage.
Please check the below circuit diagram. Let's assume, the diode is not in place. I assume current would "leak" from the higher potential (MCU PGIO Pin, when high) to the 3.7V voltage rail.
I added the diode to fix current flowing to the 3.7V rail but I'm unsure, if this is a good practice.
My questions are:
Is the diode enough or are there better practice how to control the PMOS with higher Gate voltage than the source voltage?
Thank you very much!
AI: You don't need either the 10K or the diode.
The gate is insulated and provided you stay within the Vgs voltage rating, driving it higher than the source will have no ill effects.
Some MOSFETs have gate protection zeners gate to source, but that's calculated into the maximum Vgs rating. Most are rated for at least 8V.
Just make sure your MOSFET is guaranteed to be turned on adequately with the minimum 3.7V rail voltage.
Edit: To cover situation with MCU not powered:
simulate this circuit – Schematic created using CircuitLab
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H: STM32 HAL I2C always sends 0xFF as first byte when responding to master using HAL_I2C_Slave_Transmit
I have an STM32G4 using the HAL function HAL_I2C_Slave_Transmit to respond with some data when requested by a master on the I2C bus. In the image below you can see the device sends 0xFF followed by the actual data it was meant to send (the data I am expecting is 0x11 0x01 0x00).
I have tried this with the minimal test program below so I don't believe it's anything to do with my full program having a delay:
/* USER CODE BEGIN 2 */
typedef struct {
char id;
char payload[2];
} I2C_RSP_TO_MASTER;
I2C_RSP_TO_MASTER I2C_response;
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
I2C_response.id = 0x11;
I2C_response.payload[0] = 0x01;
I2C_response.payload[1] = 0x00;
HAL_I2C_Slave_Transmit(&hi2c2, (uint8_t*) &I2C_response, 3, 10);
while (HAL_I2C_GetState(&hi2c2) != HAL_I2C_STATE_READY) {
}
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
For my current testing the master is an Arduino Nano using the Arduino function:
Wire.requestFrom(ADDR, 4);
I am requesting 4 bytes because the initial byte is garbage (0xFF). The STM32 is clocked at 128MHz so I don't believe it is possible that it is running too slowly to respond to the first byte - I think it may be a problem with the HAL! Is there a way to fix this problem?
AI: If you have enabled "No Clock Stretch" mode, you can't expect the thing to react to it's address and send the first byte correctly, because it does not stretch the clock to make the master wait until the slave code has loaded the first byte into its I2C engine.
If you want to do it without clock stretching, be prepared to write your own I2C routines. The HAL functions can be used as a good starting point, but many times they just are not the best for special needs.
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H: Identify power cable connector
I need help identifying this connector. It looks a bit like a Mate-n-Lock but I was not able to find this layout in their list. I also browsed Digi-Key, Mouser and a couple of auto parts sites, to no avail.
This carries 230 VAC, about 30 mA.
AI: Looks like a 3-pin Molex 3191.
It's available on both Digi-Key and Mouser.
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H: Current mirror with mosfets
This is a current mirror circuit with 2 op amp stages.
First stage on the left
Voltage from a DAC gets fed into U1 which creates a reference current through Rmir (via the N channel MOSFET) by sensing the voltage across Rset in its feedback loop.
Second stage
U2 (the 2nd stage amplifier) needs to keep the voltage at its two inputs equal as do any op amp. We feed in the voltage across Rsns and the voltage across Rmir to the two inputs respectively.
Non-inverting input
The current across Rmir (reference current) and the resistance of Rmir are constant. Therefore the voltage fed into the non-inverting input is also constant.
Inverting input
The resistance of Rsns is fixed. U2 varies the voltage across Rsns (to match with that across Rmir) by outputting a higher voltage across the MOSFET that then draws more current from PVDD. Hence, across Rsns (and across Rload), we now have a higher current value that is greater than the reference current and that is also constant.
My question is this:
Instead of the constant source that is fed into the non-inverting input of the 2nd stage op-amp, if I feed in the voltage from the DAC directly, why don’t I see a constant current through Rload? I’m aware that the source providing VDAC isn’t a constant current source. But, the current flowing into an op amp is almost negligible right? And it is wholly dependent on the input voltage right?
I know this circuit doesn't work as when I change the Rload to say 2 ohms, the output current changes i.e. doesn't stay constant no matter what Rload's resistance is. Not sure why though.
Also, what would be the feedback loop equation for the 2nd opamp stage with the Mosfet in its way?
AI: Instead of the constant source that is fed into the non-inverting
input of the 2nd stage op-amp, if I feed in the voltage from the DAC
directly, why don’t I see a constant current through Rload?
It won't work as it stands - to make this work you need to make VM2 (the input demand signal voltage) referenced to the positive supply rail (PVDD) so that the op-amp can manipulate its MOSFET in order to make the voltage at the inverting input PVDD minus VM2. In effect, the first circuit relocated VM2 (with a bit of gain change) up at PVDD.
That's what the original circuit did - if RSET and PMIR were equal values then Vin+ of the op-amp equals PVDD - VM2. The fact that RSET and PMIR are different values is just a signal gain change and not about ensuring that the offsets are correct.
To make this easier to see, consider the constant current sink using an N channel MOSFET: -
The op-amp tries to ensure that the voltage across Rs is the same as Vin.
Turning it upside down and use a P channel MOSFET means that the demand reference point instead of being ground is now the positive rail.
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H: DC-DC converter isolation capacitance return path?
For those isolated DC-DC converter bricks like seen in the photo below:
The data sheet specifies an isolation capacitance in the order of picofarads. And in order to meet EMC requirements they recommend coupling either side of the isolation barrier with a cap to reduce loop area of the current leakage. That part makes sense to me, but I am struggling to see how else the current could return say if the cap weren't there? (assuming the DC-DC converter is the only component "bridging" the two isolated circuits).
AI: Consider the two below circuits. They are identical except for C7 100nF between input and output. There is an unbalanced coupling of 5pF between primary and secondary as shown. Output capacitor is unrealistically low in both cases so it starts up quickly for simulation.
simulate this circuit – Schematic created using CircuitLab
Both circuits provide a stable output voltage of about 25VDC, but the output voltage varies wrt the input ground in the first case.
Without C7 the isolated part of your circuit waggles around all over the place at high frequency. It won't in reality be as bad as the top simulation because there will be stray capacitance between your isolated circuit and earth most likely but that will have a very large loop area.
With C7 the output sits close to the input ground.
However this compromises the AC isolation as you've probably surmised. Aside from making the transformers with fancier construction to minimize the capacitive coupling and divert any such currents to one or more shields, that's kind of the way it is.
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H: Film capacitor identification
I tried to repair a device and these two film capacitors were broken. I can read "393K 250V" on one cap but can't recognise the manufacturer logo due to the scratches.
Could you help me identify the manufacturer? Otherwise I guess any cap can work.
AI: Google is an amazing thing
https://www.tdk-electronics.tdk.com/download/530780/7a11ce85afa1498543bf984153733752/pdf-markingandorderingcodesystem.pdf
Anyhow, if you don't wanna read that
The one you can read is "39 * 10^3 pf" or 39,000pf or 39nF, 250V
NOTE: THe OTHER one has "630V" partially visible. i.e. THAT'S A HIGHER VOLTAGE CAP. Don't drop a 250V in there.
Since it's about the same size, but much higher voltage, it is likely to be a lower capacitance than the 39nF part
The "k" is a tolerance
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H: Why isn't the input impedance mentioned in the datasheet of the AD8597 operational amplifier?
I am trying to look for a high input impedance op-amp to use as a buffer to prevent source loading.
When I started checking the input impedance value for different op-amps, I noticed that some of the amplifiers mention it and others don't.
For example, the AD8597 datasheet doesn't mention the input impedance value.
In this case, how do I determine the input impedance?
AI: As a bipolar-input amplifier, The input impedance of that part is relatively low, less than 1G ohm, typically as you can see from the change in input bias current with CM voltage. Eg. Fig.15.
Typically, to get the benefit of the front end which is run at relatively high current with super beta transistors, you’d want a source impedance less than 1K so that’s of little concern.
The input bias current is typically only 40nA (still quite high) but can be as high as 340nA over temperature, which, along with the large offset voltage, are probably bigger concerns.
It’s optimal for low impedance AC sources where noise is a primary concern.
If high input resistance and bias current is your main concern, you can get CMOS-input amplifiers with bias currents in the double digit fA range, which is more than 7 orders of magnitude less.
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H: Why is my output signal aliased when my sampling rate is decently above the Nyquist theorem?
I'm really confused on what's happening here.
I have my ADC sampling at 44.410kHz and any frequency above 11Khz it would alias the output signal.
The max target frequency is 20kHz for clarification.
What I have checked so far is:
if the ADC is actually sampling at 44.410kHz. Checked & good.
if the DAC is bottle necking in any sort of way. I found this. STM32L43KC
Checked my scope sampling rate. Used a trigger to get the most out of the sampling. Still the samething.
Mentioned in the datasheet on page 128:
\$t_{SAMP} typical = 2us\$ which should be good as the DAC is outputting at 44.410kHz which is 22us.
So I dont understand as to why my DAC is behaving like this.
Notes:
If you are curious as how I checked if the ADC is good, is two ways.
In programming personally checked the register values
Sampling at 44.410kHz, 4 samples in should finish around ~90us. Checked with scope and confirmed.
Pictures:
Code:
#include "main.h"
#include <stdint.h>
void init_Interrupt(void);
void init_Clock(void);
void init_Interrupt(void);
void init_DAC(void);
void init_ADC(void);
void init_GPIO_Test(void);
void init_Debug(void);
void print_ADC(short);
void init_Timer(void);
char buffer[20] = "ADC Value: \n\r";
typedef struct PLL{
uint8_t PLLN;
uint8_t PLLR;
uint8_t PLLM;
uint8_t PLLSAI1N;
uint8_t PLLSAI1R;
} PLL;
PLL find_PLL(uint32_t, uint32_t);
PLL CFGR;
uint8_t escape = 0;
uint8_t half_transfer_complete = 0;
uint8_t transfer_complete = 0;
uint32_t PLLN_MAX = 86;
uint32_t PLLSAI1N_MAX = 86;
uint32_t PLLR_MAX = 8;
uint32_t PLLSAI1R_MAX = 8;
uint32_t PLLM_MAX = 8;
uint32_t CPU_Speed = 80000000;
uint32_t ADC_Speed = 29000000;
uint16_t ADC_Value[8]; // Hold 8 Samples
void DMA2_Channel3_IRQHandler(void){
if (((DMA2->ISR) & (DMA_ISR_HTIF3)) != 0){
half_transfer_complete = 1;
DMA2->IFCR |= DMA_IFCR_CHTIF3;
} else if (((DMA2->ISR) & (DMA_ISR_TCIF3)) != 0){
transfer_complete = 1;
DMA2->IFCR |= DMA_IFCR_CTCIF3;
}
}
int main(void) {
init_Clock();
//init_Debug();
init_ADC();
init_DAC();
init_GPIO_Test();
init_Interrupt();
init_Timer();
while (1) {
if (half_transfer_complete == 1){
TIM6 ->CR1 |= TIM_CR1_CEN;
GPIOA->BSRR |= GPIO_BSRR_BS0;
half_transfer_complete = 0;
}
if (transfer_complete == 1){
GPIOA->BSRR |= GPIO_BSRR_BR0;
transfer_complete = 0;
}
};
}
PLL find_PLL(uint32_t CPU_Speed, uint32_t ADC_Speed) {
PLL settings;
for (int PLLN = 8; PLLN <= PLLN_MAX; PLLN ++){
if (escape == 1){
break;
}
for (int PLLM = 1; PLLM <= PLLM_MAX; PLLM ++){
if (escape == 1){
break;
}
for (int PLLR = 2; PLLR <= PLLR_MAX ; PLLR +=2){
if ((((4000000/PLLM) * PLLN) >= 64000000) & (((4000000/PLLM) * PLLN) <= 344000000)){
if (((4000000/PLLM) >= 4000000) & ((4000000/PLLM) <= 16000000)) {
if (((((4000000/PLLM)*PLLN)/PLLR) >= 8000000) & ((((4000000/PLLM)*PLLN)/PLLR) <= 80000000)){
uint32_t PLL_CALC = (((4000000/PLLM)*PLLN)/PLLR);
if (PLL_CALC == CPU_Speed){
settings.PLLM = PLLM;
settings.PLLR = PLLR;
settings.PLLN = PLLN;
escape = 1;
break;
}
}
}
}
}
}
}
escape = 0;
for (int PLLSAI1N = 8; PLLSAI1N <= PLLSAI1N_MAX; PLLSAI1N ++){
if (escape == 1){
break;
}
for (int PLLSAI1R = 2; PLLSAI1R <= PLLSAI1R_MAX; PLLSAI1R += 2){
if ((((4000000/settings.PLLM) * PLLSAI1N) >= 64000000) & (((4000000/settings.PLLM) * PLLSAI1N) <= 344000000)){
if (((((4000000/settings.PLLM)*PLLSAI1N)/PLLSAI1R) >= 8000000) & ((((4000000/settings.PLLM)*PLLSAI1N)/PLLSAI1R) <= 80000000)){
uint32_t PLLSAI1_CALC = (((4000000/settings.PLLM)*PLLSAI1N)/PLLSAI1R);
if (PLLSAI1_CALC == ADC_Speed){
settings.PLLSAI1R = PLLSAI1R;
settings.PLLSAI1N = PLLSAI1N;
escape = 1;
break;
}
}
}
}
}
return settings;
}
void init_ADC(){
//Pin - A6
RCC -> AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_ADCEN;
RCC -> AHB1ENR |= RCC_AHB1ENR_DMA2EN;
RCC -> CCIPR |= RCC_CCIPR_ADCSEL_1;
GPIOA -> MODER &= ~GPIO_MODER_MODE7;
GPIOA -> MODER |= GPIO_MODER_MODE7_Analog; //PIN A6
// |------------------- ADC VALUE ----------------------|
// 16-bit @ Sampling ~44.410kHZ
//Holding 8 samples at a time
// 16-bit = 2 byte * 8 = 16 bytes
DMA2_Channel3 -> CCR |= (DMA_CCR_PSIZE_16_Bit) |
(DMA_CCR_MSIZE_16_Bit) |
(DMA_CCR_MINC) |
(DMA_CCR_CIRC) |
(DMA_CCR_TCIE) |
(DMA_CCR_HTIE) |
(DMA_CCR_PL_Very_High);
DMA2_CSELR -> CSELR &= ~DMA_CSELR_C3S;
DMA2_Channel3 -> CNDTR |= 0x08;
DMA2_Channel3 -> CMAR = (uint32_t)ADC_Value; //Memory Address
DMA2_Channel3 -> CPAR = (uint32_t)&ADC1->DR; //Peripheral Addres
DMA2_Channel3 -> CCR |= DMA_CCR_EN;
ADC1 -> CR &= ~ADC_CR_DEEPPWD;
ADC1 -> CR |= ADC_CR_ADVREGEN;
ADC1 -> CR &= ~ADC_CR_ADCALDIF;
ADC1 -> CR |= ADC_CR_ADCAL;
while((ADC1->CR & ADC_CR_ADCAL) != 0) //Wait for Calibration to be done
;
ADC1 -> CFGR |= ADC_CFGR_CONT | ADC_CFGR_DMACFG;
ADC1 -> CFGR &= ~ADC_CFGR_ALIGN_RIGHT | ADC_CFGR_RES_12_Bit;
ADC1 -> SMPR2 |= ADC_SMPR2_SMP12_640_ADC_CYCLES;
ADC1 -> SQR1 |= ADC_SQR1_SQ1_12;
ADC1 -> ISR |= ADC_ISR_ADRDY;
ADC1 -> CR |= ADC_CR_ADEN; //Enable: ADC
while((ADC1->ISR & ADC_ISR_ADRDY) == 0) //Wait for the ADC to be ready
;
ADC1 -> ISR |= ADC_ISR_ADRDY; //Clear the ARDYFlAG
ADC1 -> CR |= ADC_CR_ADSTART; //Start the ADC
ADC1 -> CFGR |= ADC_CFGR_DMAEN;
}
void init_Clock() {
CFGR = find_PLL(CPU_Speed, ADC_Speed);
// |----------------------------------- WAIT STATE: 0 -----------------------------------|
if (CPU_Speed <= 16000000) {
FLASH -> ACR &= ~FLASH_ACR_LATENCY_Msk;
FLASH -> ACR |= FLASH_ACR_LATENCY_0WS;
if ((FLASH -> ACR & FLASH_ACR_LATENCY_0WS) != FLASH_ACR_LATENCY_0WS){
//ERROR: System didn't change wait states properly
} else{
//Success
}
// |----------------------------------- WAIT STATE: 1 -----------------------------------|
} else if (CPU_Speed <= 32000000){
FLASH -> ACR &= ~FLASH_ACR_LATENCY_Msk;
FLASH -> ACR |= FLASH_ACR_LATENCY_1WS;
if ((FLASH -> ACR & FLASH_ACR_LATENCY_1WS) != FLASH_ACR_LATENCY_1WS){
//ERROR: System didn't change wait states properly
} else{
//Success
}
// |----------------------------------- WAIT STATE: 2 -----------------------------------|
} else if (CPU_Speed <= 48000000){
FLASH -> ACR &= ~FLASH_ACR_LATENCY_Msk;
FLASH -> ACR |= FLASH_ACR_LATENCY_2WS;
if ((FLASH -> ACR & FLASH_ACR_LATENCY_2WS) != FLASH_ACR_LATENCY_2WS){
//ERROR: System didn't change wait states properly
} else{
//Success
}
// |----------------------------------- WAIT STATE: 3 -----------------------------------|
} else if (CPU_Speed <= 64000000){
FLASH -> ACR &= ~FLASH_ACR_LATENCY_Msk;
FLASH -> ACR |= FLASH_ACR_LATENCY_3WS;
if ((FLASH -> ACR & FLASH_ACR_LATENCY_3WS) != FLASH_ACR_LATENCY_3WS){
//ERROR: System didn't change wait states properly
} else{
//Success
}
// |----------------------------------- WAIT STATE: 4 -----------------------------------|
} else if (CPU_Speed <= 80000000){
FLASH -> ACR &= ~FLASH_ACR_LATENCY_Msk;
FLASH -> ACR |= FLASH_ACR_LATENCY_4WS;
if ((FLASH -> ACR & FLASH_ACR_LATENCY_4WS) != FLASH_ACR_LATENCY_4WS){
//ERROR: System didn't change wait states properly
} else{
//Success
}
} else{
//Error: Clock Speed too high
}
RCC -> CFGR |= RCC_CFGR_SW_PLL;
PWR -> CR1 &= ~PWR_CR1_VOS_Msk;
PWR -> CR1 |= PWR_CR1_VOS_0;
RCC -> CR |= RCC_CR_MSIRGSEL | RCC_CR_MSIRANGE_6;
// |----------------------------------- PLLCFGR: R -----------------------------------|
if (CFGR.PLLR == 2){
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLLR_Msk;
RCC -> PLLCFGR |= RCC_PLLCFGR_PLLR_2;
} else if (CFGR.PLLR == 4){
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLLR_Msk;
RCC -> PLLCFGR |= RCC_PLLCFGR_PLLR_4;
} else if (CFGR.PLLR == 6){
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLLR_Msk;
RCC -> PLLCFGR |= RCC_PLLCFGR_PLLR_6;
} else if (CFGR.PLLR == 8){
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLLR_Msk;
RCC -> PLLCFGR |= RCC_PLLCFGR_PLLR_8;
}
// |----------------------------------- PLLCFGR: M -----------------------------------|
if (CFGR.PLLM == 1){
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLLM_Msk;
} else {
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLLM_Msk;
RCC -> PLLCFGR |= (CFGR.PLLM-1) << RCC_PLLCFGR_PLLM_Pos;
}
// |----------------------------------- PLLCFGR: N -----------------------------------|
RCC -> PLLCFGR &= ~(RCC_PLLCFGR_PLLN_Msk);
RCC -> PLLCFGR |= ((CFGR.PLLN) << RCC_PLLCFGR_PLLN_Pos) | (RCC_PLLCFGR_PLLREN) | (RCC_PLLCFGR_PLLSRC_MSI);
// |----------------------------------- PLLSAI1CFGR: R -----------------------------------|
if (CFGR.PLLSAI1R == 2){
RCC -> PLLSAI1CFGR &= ~RCC_PLLSAI1CFGR_PLLSAI1R_Msk;
RCC -> PLLSAI1CFGR |= RCC_PLLSAI1CFGR_PLLSAI1R_2;
} else if (CFGR.PLLSAI1R == 4){
RCC -> PLLSAI1CFGR &= ~RCC_PLLSAI1CFGR_PLLSAI1R_Msk;
RCC -> PLLSAI1CFGR |= RCC_PLLSAI1CFGR_PLLSAI1R_4;
} else if (CFGR.PLLSAI1R == 6){
RCC -> PLLSAI1CFGR &= ~RCC_PLLSAI1CFGR_PLLSAI1R_Msk;
RCC -> PLLSAI1CFGR |= RCC_PLLSAI1CFGR_PLLSAI1R_6;
} else if (CFGR.PLLSAI1R == 8){
RCC->PLLSAI1CFGR &= ~RCC_PLLSAI1CFGR_PLLSAI1R_Msk;
RCC->PLLSAI1CFGR |= RCC_PLLSAI1CFGR_PLLSAI1R_8;
}
// |----------------------------------- PLLSAI1CFGR: N -----------------------------------|
RCC -> PLLSAI1CFGR &= ~(RCC_PLLSAI1CFGR_PLLSAI1N_Msk);
RCC -> PLLSAI1CFGR |= RCC_PLLSAI1CFGR_PLLSAI1REN | (CFGR.PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
RCC -> CR |= RCC_CR_PLLON;
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
RCC -> CR |= RCC_CR_PLLSAI1ON;
while ((RCC -> CR & RCC_CR_PLLSAI1RDY) == 0)
;
if ((RCC -> CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL ) {
//Error: Clock Didn't switch
}
}
void init_DAC(){
//Pin A3
RCC -> APB1ENR1 |= RCC_APB1ENR1_DAC1EN;
RCC -> AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
GPIOA -> MODER &= ~GPIO_MODER_MODE4;
GPIOA -> MODER |= GPIO_MODER_MODE4_Analog;
DAC1 -> CR |= DAC_CR_EN1;
}
void init_Interrupt(){
NVIC_EnableIRQ(DMA2_Channel3_IRQn);
NVIC_SetPriority(DMA2_Channel3_IRQn,0);
}
void init_GPIO_Test(){
RCC -> AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
GPIOA -> MODER &= ~GPIO_MODER_MODE0;
GPIOA -> MODER |= GPIO_MODER_MODE0_Gen_Purpose;
}
void print_ADC(short adcValue){
short counter = 0;
while (adcValue > 0){
buffer[14-counter] = (adcValue % 10) + '0';
adcValue = adcValue / 10;
counter++;
}
if (counter == 0){
buffer[14] = adcValue + '0';
buffer[13] = ' ';
buffer[12] = ' ';
buffer[11] = ' ';
} else if (counter == 1){
buffer[13] = ' ';
buffer[12] = ' ';
buffer[11] = ' ';
} else if (counter == 2){
buffer[12] = ' ';
buffer[11] = ' ';
} else if (counter == 3){
buffer[11] = ' ';
}
counter = 0;
}
void init_Debug(){
RCC -> APB1ENR1 |= RCC_APB1ENR1_USART2EN;
RCC -> AHB1ENR |= RCC_AHB1ENR_DMA1EN;
RCC -> AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
RCC -> CCIPR |= RCC_CCIPR_USART2SEL_System_Clock;
GPIOA -> MODER &= ~GPIO_MODER_MODE2;
GPIOA -> MODER |= GPIO_MODER_MODE2_Alt_Function;
GPIOA -> AFR[0] |= GPIO_AFRL_AFSEL2_USART2;
DMA1_Channel7 -> CCR |= DMA_CCR_PL_High |
DMA_CCR_MSIZE_8_Bit |
DMA_CCR_PSIZE_8_Bit |
DMA_CCR_MINC |
DMA_CCR_CIRC |
DMA_CCR_DIR;
DMA1_CSELR -> CSELR |= DMA_CSELR_C7S_USART2;
DMA1_Channel7 -> CNDTR = 0x14; // 20
DMA1_Channel7 -> CMAR = (uint32_t)buffer;
DMA1_Channel7 -> CPAR = (uint32_t)&USART2 -> TDR;
DMA1_Channel7 -> CCR |= DMA_CCR_EN;
USART2 -> CR1 &= ~USART_CR1_M1 | ~USART_CR1_OVER16;
USART2 -> CR1 |= USART_CR1_TE;
USART2 -> CR3 |= USART_CR3_DMAT;
USART2 -> BRR = 0x208D;
USART2 -> CR1 |= USART_CR1_UE;
}
void init_Timer(){
RCC -> AHB1ENR |= RCC_AHB1ENR_DMA1EN;
RCC -> APB1ENR1 |= RCC_APB1ENR1_TIM6EN;
DMA1_Channel3 -> CCR |= DMA_CCR_PL_Very_High |
DMA_CCR_MSIZE_16_Bit |
DMA_CCR_PSIZE_16_Bit |
DMA_CCR_MINC |
DMA_CCR_CIRC |
DMA_CCR_DIR;
DMA1_Channel3 -> CNDTR = 0x08;
DMA1_Channel3 -> CPAR = (uint32_t)&DAC1->DHR12R1;
DMA1_Channel3 -> CMAR = (uint32_t)ADC_Value;
DMA1_CSELR -> CSELR |= DMA_CSELR_C3S_TIM_6_UP;
DMA1_Channel3 -> CCR |= DMA_CCR_EN;
TIM6 -> DIER |= TIM_DIER_UDE;
TIM6 -> ARR = 0x708;
TIM6 -> PSC = 0x0;
}
EDIT: Added a FFT using the 13kHz signal.
EDIT 2: Added a new 13kHz picture but changing the scope's sampling rate to 50kSa/s from the previous higher sampling rate.
AI: Here's a graph I quickly threw together with Excel.
Does it look at all familiar? Maybe just a little like your last scope capture?
That's because this is what you get when you sample a 13kHz sine wave at 44.41kHz.
What you're seeing is exactly what you should expect to see. What you're definitely not seeing there is aliasing.
When you only sample 3 or 4 points for every cycle of the sine wave, you're never going to be able to just push those samples out of a DAC and expect to see something resembling that original sine wave.
You would need to feed your samples through a reconstruction filter, and you can do that in the analog domain after the DAC or in the digital domain before the DAC, or even a bit of both.
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H: Question about mixing battery sizes and quantities
Ok. I have searched everywhere and can't find a definite answer on this:
My first question, Is, Can you mix 2 lithium batteries of different sizes together? (Like mixing an 18650 lithium battery with a 3v coin cell lithium battery). would that be be damaging? What effects would it have?
My second question is if it would be ok to mix 4 lithium batteries of the same size and brand together. What about NiMh batteries? How many of the same brand and size of that battery type are ok to mix?
AI: All high energy and high power density battery chemistries are dangerous by definition. Do not mix batteries of different sizes. Do not mix different battery chemistries of any type.
Even cells of the same chemistry, size, and brand cannot be connected together in parallel before carefully matching their voltages or else they will try and charge each other, and for batteries that need careful charging (like lithium batteries) this is dangerous.
You've heard of smartphone battery fires, right? That's what happens when you do not charge lithium polymer properly or mis-used. Radio-controlled models use particularly large versions of the same battery and they are extra careful and use expensive chargers. Models, homes, and lives have been lost from mischarged and over-discharged lithium polymer batteries. For their batteries with series connected cells, the battery chargers basically monitor and charge each cell individually so it does not differ from the other cells. They are not blindly charged as a group.
Also, a 18650 lithium battery is not the same as a 3V coin cell lithium battery, not even in chemistry. That's almost like calling both NiCd and NiMh nickel batteries. There are at least several different kind of "lithium" batteries out there. If all you know about a battery is that it is "lithium" then you don't know anything about the battery. There's Lithium ion, lithium polymer, lithium iron phosphate, and whatever crappy non-rechargeable AA and AAA batteries labelled Lithium are. They're all different.
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H: Values of currents in inverting and non-inverting terminal of Op-Amp
In the given solved example from a textbook on electronic devices, the author has use the voltage divider rule after assuming \$V_{s2}=0\$. Clearly for equation 1 to be true, the current in the non inverting terminal \$i\$ must be 0.
Why is this true? In few other examples current is taken as zero in the inverting input terminal. I wish to know the reason behind this assumption and how to know out of the two which input terminal has zero current? Can the current be ever taken zero in both of them?
AI: It's one of the ideal op-amp assumptions that the current into either input pin is zero.
In even a crummy real op-amp it's generally less than 1 uA. In FET-input op-amps it can be as low as femtoamps.
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H: Comparing power consumption of different FPGAs
I want to compare power dissipation of FPGAs from different vendors, the I/O count and the logic resource shall be matched as close as possible when choosing the FPGAs.
I want to create a trivial design that would utilize a big chunk of the logic resource and the I/O pins. This design shall be implemented across the different FPGAs and the power dissipation shall be measured on each power rail.
The problem as it exists is that, there is no simple way to create a design for this. The design being sought does not need to do anything productive but merely needs to implement switching activity, it should just occupy say X% of resource inside an FPGA and this number can be specified as amount of LUTs also.
Is there a standard way to produce such a design that would have huge amount of logic which keeps switching and helps us make the power measurements? I do not think any standard method to create design of such nature exists.
AI: To produce an unbiased report on performance comparison of FPGAs from different vendors you need to care not only about "the I/O count and the logic resource", each of which you are going to match "as close as possible when choosing the FPGAs". The FPGA architecture -- how LUTs are aggregated into logic elements, in particular -- can be a game changer when comparing against selected applications. If your understanding of matching "logic resource" embraces details of the logic block implementation solutions, the gamut of vendors under test is narrowed, sometimes to a single vendor. If you refer to "the logic resource" as a coarse quantification of LUTs per chip or even a transistor logic gate count parameter, you may end comparing the efficiency of FPGA development tools for selected applications, not hardware.
All these said, the power performance measurements of FPGA designs is anything but an uncultivated land. See a review of GPU vs FPGA Performance Comparison for applications as diverse as image processing, cloud computing, wideband communications, Big Data, robotics, high-definition video. An article "TinySDR: Low-Power SDR Platform" presents a detailed report on testbed development for SDR and IoT implementations. Pay attention to a github reference in this article.
Studying references from searches for "testbeds for fpga power consumption" may give you ideas for your research, if not satisfying the request of your SE question in full. Or, perhaps, it will convince you to modify your research subject.
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H: Compare register value using logical AND (&) and ==
// Hardware sets a RIS interrupt status bit
if(GPIO_PORTE_RIS_R & 0x10)
{
// Software acknowledges the flag and clears the read-only RIS bit by setting ICR
GPIO_PORTE_ICR_R = 0x10;
// something useful
}
The above code should be self explanatory - the hardware flags a register bit, the software clears it. What I don't understand is why the code uses GPIO_PORTE_RIS_R & 0x10 to compare register value instead of GPIO_PORTE_RIS_R == 0x10.
== operation would probably equivalent to a CMP followed by a BEQ or BNE in assembly, or it can be SUBS with a branch by flagging the Z (Zero) bit. Either way using == is straightforward and intuitive - I don't have to convert values into binaries to predict an outcome.
But with & and say if GPIO_PORTE_RIS_R = 0x20, the logical bitwise AND operation between 0x20 & 0x10 or 0010.0000 & 0001.0000 in binary will result in 0000.0000 or a false. And imagine if GPIO_PORTE_RIS_R = 0x30 or 0011.0000 in binary, the condition statement would return true even if the two operands (0x30 & 0x10) don't equate. It seems as if the & operator checks if a register contains a value (or vice versa, a register is subset of a value). It's just confusing to think or use.
In what situation should I use & instead of == and why? And is there a simpler way to think about it?
AI: When you write if REG & 0x10 you're checking whether bit 4 of the register REG is set.
If the value of REG is 0x30, then bit 4 is set, and you should do the thing you want to do when bit 4 is set.
If the value of the REG is 0x20 then bit 4 isn't set, so you shouldn't do the thing you want to do when bit 4 is set.
And that's exactly the behavior you get if you write if REG & 0x10 {...}.
What I don't understand is why the code uses GPIO_PORTE_RIS_R & 0x10 to compare register value instead of GPIO_PORTE_RIS_R == 0x10.
If you used == then if bit 4 was set, but some other bit was also set, then you wouldn't do whatever it is you want to do when bit 4 is set.
But since you want to do that thing when bit 4 is set regardless of what other bits are set, then this is wrong.
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H: current analysis with pre-carried current in the inductor .- confused
The direction of the reference i(t) current is certain. When we add the pre-existing currents, it will be -12 amperes, thats okay. But why did we multiply it by - (minus) when we integrating the expression Voltage and multiply it by inductance (I marked it with a yellow marker)?
AI: When a inductor is modelled as
\$v(t) = L \frac{d\ i(t)}{dt}\$,
the reference polarity of the current is an arrow pointing from +ve part of \$v(t)\$ to -ve part.
In the question, the current reference direction is marked in the opposite direction. Hence the equation for these inductors would be
\$v(t) = - L \frac{d\ i(t)}{dt}\$.
Above image taken from slide 24 for a reference.
Note
The fact that the current values are negative and the voltage values are negative (-1800V), do not affect how the equations are setup. The numerical values are substituted after setting up the equations. The negative sign appears while setting up the equations. Th screen shots do not show the details as two separate steps (writing equations in terms of symbols and then substituting values).
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H: How are other chipmakers keeping up with TSMC if their processes are just the best?
In the news recently was Intel's stock falling 20% because its 7nm processes are being delayed by 6+ months. The argument seems to be that Intel is already behind (since they're using 10nm processes while TSMC is on 7nm processes, soon to be 3nm processes), so it's only going to get worse for Intel. The entire chipmaking process isn't something I understand very well however, so I'm hoping someone can enlighten me.
Why exactly is it important to be on 3nm processes instead of 5nm or 7nm? This article says:
There are a few major underlying technologies that dictate the potency of any chip. The most fundamental rule of processors still holds true: The densest process nodes, provided they have decent power, performance, and area (PPA) characteristics, will often win the battle if paired with a solid microarchitecture.
I'm guessing this means that 3nm processes are "better" because for whatever reason I don't understand, it fundamentally improves the PPA characteristics. In other words, although you can improve while on 10nm processes, you'll never catch someone on 3nm processes - sort of like how a 40-year old can run faster with training, but will never catch someone who's 25 years old.
But if this is the case, then TSMC's processes are just the best in market, and they'll be leaving everyone else in the rear-view mirror. That hasn't happened though - the same article notes that Intel's processors still leads in certain categories, such as overclocking and gaming performance. Somehow Intel has managed to remain competitive with TSMC in spite of poorer technology. Even more surprisingly, SMIC manages to rake in billions of dollars in revenue in spite of using only 14nm processes. Perhaps one could say "therefore their revenues are going down", but they aren't, and that's in spite of Intel/TSMC/Samsung being on 10nm and smaller processes for years. Can someone explain what's going on?
I'm sure there are other applicable tags than just "Intel" and "fabrication", but I genuinely don't know what they are - if you do feel free to edit them into the question.
AI: Somehow Intel has managed to remain competitive with TSMC in spite of
poorer technology
Intel has a lot of experience in designing CPUs. A "stupid" design using the fastest technology can be worse (performance wise) than a "smart" design using somewhat older (and slower) technology.
TSMC only does chip-making they do not design, they are a foundry , so whatever chips are made by TSMC are not designed by them. The chips are designed by Qualcomm, Broadcomm and many other "fabless" semiconductor companies.
SMIC is also a foundry, just like TSMC. SMIC concentrates on older technology nodes that are "less interesting" to foundries like TSMC. A lot of chips are needed in mobile phones, cars etc. Not all of these need to be made in the latest-and-greatest fastest technology.
Realize that making a "simple" chip which can be made (or is already an existing design) in for example 14 nm (or much older, larger feature size technologies) is much, much cheaper than using the latest technology node. I mean: very often there is simply no need to use the newest technology node.
... up with TSMC if their processes are just the best?
Are they "the best"? What is "the best"? For a Soc powering the latest and greatest smartphone, indeed using the smallest manufacturing node might be essential.
But how about a chip used in a pocket calculator or microcontroller in an espresso machine? For these applications the chip needs to be cheap. A simple microcontroller, when bought in large quantities, can be had for a few cents per chip. I guarantee you that these chips will be made in an "ancient" technology, like 0.35 um CMOS (just my guess). The (at the time very expensive) equipment needed for making such chips has been written off long ago so you don't need to pay a premium price because expensive equipment is needed. That allows for chips that are extremely cheap. In many applications "cheap" is much better than "latest and greatest".
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H: Unable to find MOSFET type and specs
Recently I've been trying to fix a motor-controling board in my pool cleaner. After some measuring, I've figured out, that two MOSFETs are behaving strangely and their behaviour varies from the other two paires.
Unfortunately I am unable to find the types and specs of the FETs. This is what is written on them:
D409 BA6X17
VNH38 ON 58 65NLG
Isn't someone familiar with these?
AI: The ON semiconductor device is a NVD5865NL: -
The other device: -
Looks like it has the Alpha & Omega Semiconductor symbol: -
I thinks it's the AOD409: -
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H: What parts/sections of a CPU take the biggest number of transistors?
I was surprised to hear CPUs only have a number of ALUs. What are most of the transistors in a CPU dedicated to?
AI: From Quora.com:
How you spend your transistors really depends on the problem you're
trying to solve.
If you open up a 1 billion-transistor x86 processor, you'll see a
handful of very complex CPU cores, with many transistors dedicated to
decoding and scheduling instructions, predicting branches, and
managing virtual memory. You'll also see many transistors dedicated to
very fast cache memories. This mix of transistors reflect the general
purpose, varied workloads a typical Windows or Mac might encounter.
If you open up a 1 billion-transistor SPARC server processor, you'll
find a bunch of fairly simple in-order SPARC cores and a ton of cache.
These guys are optimized for many parallel database threads operating
on huge database working sets.
If you open up a 1 billion-transistor GPU processor, you'll see
hundreds of very specialized, deeply pipelined floating point compute
datapaths, fine-grain thread schedulers, and memory transfer engines
designed to stream texture, vertex and other data through the
processor efficiently. There isn't much branch control logic, but a
ton of matrix-friendly floating point compute hardware, along with RAM
to buffer the data as it passes through.
If you open up a 1 billion-transistor DSP optimized for cellular base
station applications (something I worked with in a previous job),
you'll find multiple dedicated signal processing blocks for handling
various over-the-air encoding protocols, a large network-accelerating
block for handling millions of packets whizzing through the device at
microsecond latencies, some highly capable general purpose DSPs
dedicating most of their transistors to multiply-accumulate
operations, and some ARMs to schedule everything. The transistors
there are split maybe 50-50 between compute/data movement and memory.
(Or maybe closer to 40-60.)
If you open up a 1 billion-transistor cell phone processor, you'll
find the most varied mix of all. You'll see a few general purpose ARM
processors (most likely), some GPUs, some video encode/decode
accelerators, maybe some DSPs, some networking peripherals, and many
other peripherals for managing USB, Bluetooth, WiFi, and interfacing
to cameras, mics and speakers.
It all depends on what you're trying to do...
A billion transistors seems like a lot, but a trillion is now the record to beat, or at least a common ground to start from. Granted this is only for the most demanding applications. Analog and RF IC's have no desire to be so complex, not to mention the cost. The following blog is amazing that it happened so soon. From ExtremeTech.com
Cerebras Systems Unveils 1.2 Trillion Transistor Wafer-Scale Processor
for AI By Joel Hruska on August 20, 2019 at 9:00 am
Modern CPU transistor counts are enormous — AMD announced earlier this
month that a full implementation of its 7nm Epyc “Rome” CPU weighs in
at 32 billion transistors. To this, Cerebras Technology says: “Hold my
beer.” The AI-focused company has designed what it calls a Wafer Scale
Engine. The WSE is a square, approximately eight inches by nine
inches, and contains roughly 1.2 trillion transistors.
I’m genuinely surprised to see a company bringing a wafer-scale
product to market this quickly. The idea of wafer-scale processing has
attracted some attention recently as a potential solution to
performance scaling difficulties. In the study we discussed earlier
this year, researchers evaluated the idea of building an enormous GPU
across most or all of a 100mm wafer. They found that the technique
could product viable, high-performance processors and that it could
also scale effectively to larger node sizes. The Cerebras WSE
definitely qualifies as lorge large — its total surface area is much
larger than the hypothetical designs we considered earlier this year.
It’s not a full-sized 300mm wafer, but it’s got a higher surface area
than a 200mm does.
The largest GPU, measures 815 square millimeters and packs 21.1B
transistors. So the Cerebras WSE is just a bit bigger, as these things
go. Some companies send out pictures of their chips held up next to a
diminutive common object, like a quarter.
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H: Air gap for a coil calculation
i would a help calculating the necessary air gap for a coil assuming an ideal magnetic material:
Cross sectional area of active material = 100 mm2
number of turns= 30
Inductance= 1mH
Thanks in advance
AI: We could just plug numbers into the formula, but it's more instructive to do it from first principles. Then if you forget the exact form of the formula, you can re-derive it.
You've already suggested some numbers for turns and pole area, so let's do it for a specific airgap as well, say 1 mm. Inductance is inversely proportional to it (assuming perfect magnetic material), so it's easy to scale afterwards.
Inductance is flux linkage per amp.
1 amp in 30 turns is 30 Ampere.Turns. This produces an H field across a 1 mm airgap of 30 kA/m.
This produces a B field in the airgap of μ0H = 4π*10-7 * 30k = 37.7 mT
This produces a flux of B*pole_area = 37.7m * 100μ = 3.77 μW
This produces a total flux linkage of flux*turns = 113 μW
So the inductance with a 1 mm airgap would be 113 μH.
On the face of it, all we have to do is scale down the airgap from 1 mm to 113 μm to get 1 mH. However, with an airgap this small, I doubt that we could approximate the magnetic core as ideal, and so the actual gap would need to be reduced further to allow for the finite reluctance of the core.
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H: Trigger relay at different voltages with voltage comparator
TL;DR - I need help on making a relay with voltage comparator which accepts two reference voltages.
Aim
My project needs to run a Raspberry Pi on solar power. Solar panel will be connected to a power bank which will then be connected to Raspberry Pi.
Challenge
Running on solar means there won't be enough power left in the power bank for the Pi. In this case I will shut it down and turn it back on when there is enough power. This process needs to be automatic since the project will be installed at a remote place.
Since Raspberry Pi doesn't have ability to detect power from the power bank directly I'm planning to install a circuit between Pi and the power bank. I will use a MCP3008 - Analogue to Digital Converter to detect the voltage level of the power bank. The schematic diagram will look like this.
I will run a script to shut down Pi if it detects only 5% of power is left.
Problem
After shutting down Pi, I want to close the circuit between Pi and the power bank completely so I'm planning to use a relay for this. I think Relay with LM393 like this will do the job.
The problem is I want to switch off the relay when the voltage equals to 5% power of the battery and switch it on automatically when the battery reaches 25% of its power. The module I consider can set only one value of voltage.
So is there any way I can set one value of voltage for the relay to switch off and another value for it to switch on?
AI: So is there any way I can set one value of voltage for the relay to
switch off and another value for it to switch on?
You can use a comparator with hysteresis like this: -
This circuit was designed to be a low power (sub 1 uA) comparator that works around 3 volts. It uses R5 to set the hysteresis: -
V3 (the battery) is ramped up from 1.5 volts to 4 volts and the comparator output switches high at about 3.1 volts and then switches low at about 2.9 volts.
If you fiddle with the values a bit you'll get what you want but concentrate on the mid-point between 5% and 25% for the actual set-point and let the hysteresis give you the margins you want.
For instance, if I change R5 to 1 Mohm I get this: -
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H: Does multiplying range affect accuracy of an analog to digital converter?
Suppose the built in analog to digital converter of a microcontroller has an operating voltage of 0-5 V. These values are converted to integers ranging from 0-1023. So the resolution is 5/1024.
I want to measure an analog value ranging from 0-1 V.
If I multiply the analog value by 5 in a microcontroller that reads the value (using the multiplication operator in software,) will the resolution be 1/1024?
AI: If I multiply the analog value by 5 in a microcontroller that reads
the value (using the multiplication operator in software), will the
resolution be 1/1024?
No the resolution will be one-fifth of that at best. 1 volt applied to a 10-bit ADC with 5 volt input full-scale will result in a digital number of 204. That has a resolution of 1 in 204 or 0.49% and will remain at 0.49% even when you multiply up 204 by 5.
Be aware that gain errors and offset errors in the ADC means you can't truly use the full 0 to 5 volt input of an ADC. Maybe 98% of it but not 100%.
Many ADCs can work at a much lower reference voltage and this of course might help you get a better solution.
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H: Cost effective way to protect circuit from overvoltage
Which is the most cost effective way to protect a DC circuit that requires 5V input (and draw up to 1A) from external power supply?
Suppose that a careless user can accidentally attach an external power supply and power up with 6-9-12-24V, this situation can literally blow up my circuit!
This can appear to be a silly question but i don't have any ideas!
AI: Probably the most common method is to use a fuse with any (and sometimes all) of the following: -
A regular power zener diode
A power shunt regulator (like a zener but programmable)
A crow-bar circuit (on over-voltage, it clamps to close to 0 volts)
So, if the voltage exceeds a certain level, too much current will flow into the aforementioned devices/circuits and then the fuse blows.
You can use resettable fuses too (polyfuses they are sometimes called). Once power is removed, the polyfuse resets.
An alternative is a series-connected over-voltage circuit that "disconnects" when the input voltage exceeds a certain critical level. Not too tricky to design but, they should also be used in conjunction with a zener to ensure that fast voltage rising events are dealt with effectively.
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H: Does a 4 pin smd crystal need external capacitors to work properly?
My understanding of how this works is quite poor, I've tried reading many sources but just got even more confused by the terms crystals, crystal resonators, ceramic resonators, oscillators, crystal oscillators.
What I know is that when you have a simple 2 pin crystal you add 2 caps to it so that it resonates properly. And the AVR chip I am connecting it too (Atmega328p) has some other internal circuitry for it to work.
I am looking at using an smd crystal in my design and my question is, for a crystal like this:
Do I still need the external capacitors or not? I originally thought I would but looking at the specs of the parts they all have a label "capacitance". Does that imply it has caps inside? Or is that recommended value for my caps? Or is that some other capacitance?
Sorry if this doesn't make sense I am just really confused.
Thanks in advance!
Edit to include specifics:
I have these crystals https://lcsc.com/product-detail/SMD-Crystal-Resonators_Seiko-Epson-X1E000021011900_C89371.html
But it seems they are quite standard so here is one with English datasheet:
https://www.mouser.co.uk/ProductDetail/ECS/ECS-160-12-37B-CTN-TR?qs=sGAEpiMZZMukHu%252BjC5l7Yb4vS8HZNl%252BL%2F78jMNI6Q2E%3D
AI: These parts are crystals that can be used with typical microcontrollers that have a built-in Pierce oscillator, and thus require the rated external load capacitance in order to oscillate at the rated frequency.
So yes, external capacitors are needed as usual for crystals. The extra two pins are just to ground the metal lid.
And no, the rated load capacitance does not mean the value of the capacitors. It is the total capacitance as seen by the crystal, which includes the capacitors, PCB wire capacitance, MCU IO pin capacitance and other stray capacitances. The ECS part is rated for 12pF load capacitance, so two 24pF capacitors would give it 12pF of load if no other capacitances are considered. But the capacitors must have smaller value due to the other stray capacitances.16pF capacitors would be used to give 8pF load if the stray capacitances are approximated to be 4pF.
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H: Zener diode response time
I have the below circuit:
Forward diode D0002 - Datasheet SIJ series for reverse protection and C0001-C0004 capacitors for ESD protection.
Zener diode - Datasheet - 36V reverse breakdown.
Question :
BATT1 is the Vcc supply for certain ICs in my design whose absolute maximum ratings is 40V.
I have provided the Zener diode circuitry to clamp if the battery voltage goes above 36V (during transient ISO7637 pulses namely pulses 2a,3b and 5a.)
I have performed simulations in Simetrix with the proper models for each part, but the Zener diode circuitry is not clamping the voltage to 36V during these ISO7637 positive pulses. Why is it so? Is the Zener diode slow to respond or react to the input transient pulses 2a, 3b and 5a?
Please let me know like if there is something like Zener response time which makes it unable to do this clamping. Or what might be the reason?
AI: Consider the two components in red below: -
The resistors in red are the only paths for current to flow when the transistor is attempting to clamp. Ask your self how much current they are going to shunt away and whether they are actually the right values.
A voltage clamp works by taking a large shunt current. Having a 100 kohm resistor in series with the transistor is not going to pass more than a few tens of micro-amps when the 36 volt is exceeded. This does not constitute a clamp in my book.
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H: Operating a 12V electric lock with arduino
I have a similar electric lock-style solenoid like this one.
If we trust the manufacturer it draws between 1.2A and 2A at 12V .I'm currently using a N-Channel MOSFET 60V 30A - FQP30N06L it works just fine but it's probably an overkill for this project but it's what I had in hand, I want to redesign my board with an SMD part but I'm not sure how to properly dimension it. I could go with the SMD equivalent FQD30N06L but any better choice?
AI: The mosfet looks fine.
The things you need to worry about when selecing a mosfet for an application like this are:
1) Will the gate voltage turn on
The Vgs is 2.5V for the FQP30N06L so a 3.3V signal from an arudio will be more than enough.
2) Will it overheat?
In your case no, the Rdson will be about 0.04Ω which at 2A would be roughly 0.08W which would contribue less than 1C of temperature rise
3) Will the Vdss of the part ever be exceeded. The 60V of Vdss would be plenty for a 12V application, except for one detail. The coil in the lock has inductance, when you turn inductors off the voltage get's very high. Make sure you protect the mosfet with a diode:
Source: http://www.coilgun.eclipse.co.uk/switching_devices.html
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H: What frequency do BLDC motors generate?
When BLDC motor is used as generator, how does the amount of poles effect the frequency of the 3 phase AC that it generates? For example, if I had a motor with 8 poles and I spun it at 50 rpm, what frequency 3 phase AC would it generate?
AI: For an 8-pole motor there are 4 complete cycles of each phase per rotation, so rotating it at 50 RPM gives you 200 cycles per minute or 200/60 Hz.
BTW, an "8-pole" 3-phase motor has 24 magnetic poles.
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H: I have an LED with no specs, but it does have a resistor. I want to double the voltage
It's one of those "stick anywhere" lights that look like a household switch.
It's powered by 4 AAA batteries and has two-2 inch LED strips connected in series with a 3 ohm resistor(looks like a 1 watt).
I want to cannibalize the parts and reassemble into a ceiling fixture I bought at the thrift store. That way I can use it in my 12 volt system I'm installing in my house.
I'm having a heck of a time figuring out what resistance to use so I can up the voltage to 12 volts. I'm probably just looking at it wrong, I normally have the specs on the LEDs.
Thanks in advance for any help with this.
AI: Get a multimeter.
Switch it to 2000 mA range. Connect leads to mA and COM socket.
Wire the meter in series with the (good set of) batteries. Record the current 'i' converting it from mA to amps (A).
Your additional resistor needs to drop 6 V when passing i. We can calculate the required resistor value from Ohms law.
$$ R = \frac {V}{I} = \frac {6}{i} $$.
Pick the nearest standard value.
You might want to check the power rating required.
$$ P = VI = 6i $$
Chose a power rating greater or equal to that value.
As an alternative, buy a second lamp and just wire the two 6 V units in series in your new fitting. You'll have twice as much light for the same current draw on your battery.
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H: Is this a reasonable way to get >50 capacitive touch sensors?
I'm looking to include 50-100 capacitive-touch sensors in a project. I've found these SPI 12-key capacitive touch sensors. Would it be reasonable to use several of these for such a project, or is there a more natural solution?
I'm building a chessboard-like "grid" with 7x7-10x10 touchable squares, ca 3x3cm.
AI: With that many active zones, you're going to want to think about matrix methods rather than completely individual electrodes. Here's a relevant application note from Freescale:
Designing Touch Sensing Electrodes
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H: How much FLASH memory is free for a program?
I'm programming for a STM32F103C8T6 (aka blue pill), with the be datasheet here.
On page 14 it states:
2.3.2 Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data.
Now mine has 64 KB, however, does this mean I have 100% available, or is there some part reduced? And if so, how much? Or is there a way to find out when it will not 'fit' (like an error will show up?).
I use an STM32 ST-LINK V2, and afaik I'm not using any special bootloader, development environment is Workbench 4 STM / Eclipse, and using HAL/STMCube.
Currently I'm using only about 19KB but I'm not finished (and running my unit tests also within this code, although I can switch it off, which saves half).
AI: In a typical microcontroller, you can program all of the flash with your code. You can check the TRM to be sure -- if it talks about a boot loader in the first sector or tells you there are parts of the flash you can't erase, then those parts are reserved. But normally you get it all.
Note that that doesn't mean 100% of the flash will be used for code! You'll have interrupt vector addresses at the start of the flash. Constants and initialization values for static variables will also be stored in the flash. Your linker should take care of this for you, probably using a linker script supplied by the manufacturer (ST). The linker should give an error if your program is too big to fit in flash.
Advanced programmers can write their own linker scripts and manually assign code and data to whatever parts of the flash they want. For example, a default linker script from a manufacturer will normally put the interrupt vectors at the start of flash (or RAM, if running out of RAM).
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H: Analog Vref for ADC on STM's Blue-Pill
I am piecing together my own ADC example for STM's blue-pill module by reading the reference manual (btw I an inexperienced in embedded development).
The code outline so far is:
void do_adc(void)
{
unsigned int ra;
ra=GET32(ADC_CR2);
ra|=1; // ADON
PUT32(ADC_CR2, ra);
// wait for EOC flag
while ((GET32(ADC_SR) & 0x02) == 1)
{
led_blink();
}
ra = GET16(ADC_DR);
PUT32(USART1_DR,ra);
sleep();
PUT32(USART1_DR,'\r');
sleep();
PUT32(USART1_DR,'\n');
sleep();
}
int notmain(void)
{
init_led_adc_and_uart();
disable_adc();
calibrate_adc();
enable_adc();
while (1)
{
led_blink();
do_adc();
}
}
I have written code for each of those functions which most probably is not correct, but that's not the question at the moment. I am still wondering where the Vref pin on the blue-pill; based on this diagram, is?
If my understanding is correct, then I would connect a temperature sensor to physical pin 10 (aka ADC channel 0), ensure that sensor has a voltage of ~3.3v. Then for reference, connect the same input somewhere on the blue-pill so it can do the conversion.
However based on the diagram I linked, I am not sure where the analog referene is?
Btw: I flashed my code onto the chip and the led continuously blinks, so the code is probably fine, but I need to workout the connections!
AI: There isn't one in a 48 pin package, it's too small to have extra functions like that. Even the 64 pin doesn't have one, only when you get to 100 do they include the ref pins.
They do have an internal reference, you'll have to configure it.
Sources: https://www.st.com/resource/en/datasheet/cd00161566.pdf
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H: Triggering a camera flash with a microcontroller
I took apart a "one-way-camera" for the flash part and found a circuit very similar to the image. For a project I need to trigger the flash with a microcontroller (attiny25/45/85v, low voltage version, operates with 1.8-5v). To do that I simply need to bridge the charge switch on turn on and then trigger the flash by replacing the trigger mechanical switch with something else. I am considering several options for this and am hoping on input on what would be the easiest and cheapest option, as I need to produce many of these circuits.
What makes this tricky is that the flash uses more than 1000 volts to trigger and most transistors are not build for that kind of application. Relays have worked fine but especially low coil voltage ones are hard to get/expensive and im wondering if there is a good alternative.
Thank you for your input in advance.
PS: The whole circuit should ideally run on 2 AA batteries (=3v)
AI: I suggest driving the TIC206 triac as suggested in data sheet from say 3V with current limiting R to gate. The transformer boosts the voltage to >1kV to a plate across tube but the storage cap is only 250Vdc or so conducts the energy across to the tube.
The Triac shuts off below a low holding current which is decayed by cap discharge to ionized tube.
So the secondary trigger voltage is not applied to Triac during trigger, only the stored Cap voltage which is across the tube electrodes thru the Triac switch. The Triac latches on the leading edge of the pulse with about 2 diode drops of Vbe’s.
You must control the semi-random intervals.
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