text
stringlengths 83
79.5k
|
|---|
H: AC Induction Motor Slip and Torque control Vs V/f control
I am trying to understand this github code for speed control of AC Induction Motor. It calculates slip value to adjust the speed of motor. I wonder if its the same thing that is called constant V/f speed control? Is it just difference in the terminology, V and f being electrical while slip and torque being mechanical?
Here is the code for quick look.
// Globals for data that is either persistent or used for debuging
int i1, i2, i3; // Phase currents
int total_current; // Total instantaneous current
int angle; // The angle of the stator voltage
int voltage; // The magnitude of the stator voltage
int encoder_position_previous; // The previous encoder value
// Analog to digital converter DMA data
uint16_t adc_data[4]; // [i1, i2, i3, throttle]
// Motor parameters
#define MOTOR_POLES 4
#define ENCODER_RESOLUTION 2400
#define MAGNETIZING_CURRENT 3000
#define MAX_TORQUE_CURRENT 7000
#define GAIN 2
// This runs at the PWM frequency: 9765.625Hz
// It runs 0.000048s after it's triggered (approx half the PWM period)
// This means data is collected during the first half of each
// pwm cycle ready for calculations in the second half.
void DMA1_Channel1_IRQHandler(void) {
// Fetch the phase currents
i1 = adc_data[0] - 32840; // Offset to 0A
i2 = adc_data[1] - 32840; // Offset to 0A
i3 = adc_data[2] - 32840; // Offset to 0A
// Calculate the total current (FPU operation)
total_current = sqrtf((float)i1*(float)i1 + (float)i2*(float)i2 + (float)i3*(float)i3);
// Calculate encoder ticks change since the last iteration
uint32_t encoder_position_current = TIM2->CNT; // Atomic as possible
int encoder_position_change = encoder_position_current - encoder_position_previous; // Nasty casting to signed here
encoder_position_previous = encoder_position_current;
// Determine slip from the throttle
// By happy coincidence this gives +/- 32768 (+/- 5Hz)
int slip = adc_data[3] - 32768;
// Increment the angle by the requested slip
angle += slip;
// Increment the angle by the encoder measurement
angle += encoder_position_change * 67108864 / ENCODER_RESOLUTION * MOTOR_POLES / 2;
// Calculate the target current.
// This starts at MAGNETIZING_CURRENT and increases wih slip
// up to a maximum of MAGNETIZING_CURRENT + MAX_TORQUE_CURRENT.
// We use floating point operations here to avoid overflows
if(slip >= 0) {
target_current = (float)MAGNETIZING_CURRENT + (float)MAX_TORQUE_CURRENT * (float)slip / 32768.0f;
} else {
target_current = (float)MAGNETIZING_CURRENT - (float)MAX_TORQUE_CURRENT * (float)slip / 32768.0f;
}
// Apply current error to voltage output
if(total_current < target_current && voltage < 4000) voltage += GAIN;
if(total_current > target_current && voltage > 0) voltage -= GAIN;
// Update PWM outputs from SVM style lookup table
TIM1->CCR3 = (voltage * table1[angle >> 13]) >> 15;
TIM1->CCR2 = (voltage * table2[angle >> 13]) >> 15;
TIM1->CCR1 = (voltage * table3[angle >> 13]) >> 15;
// Clear interrupt
DMA1->IFCR = 0xFFFFFFFF;
}
void TIM1_UP_TIM16_IRQHandler(void) {
// Start ADC conversions each time PWM restarts
// This runs at 80000000/8192 = 9765.625Hz
ADC1->CR |= ADC_CR_ADSTART;
TIM1->SR = ~TIM_SR_UIF;
}
AI: From the link " this github code"
STM32 variable frequency drive controller
This project aims to be an open source torque controller for AC induction motors.
Overview
The software generates a 3-phase output using PWM. The frequency and voltage are adjusted to create a torque proportional to the "throttle" input.
As stated above, the code is for controlling the torque of the motor not the speed. The speed is controlled manually by the person operating the throttle.
|
H: Chrome plating current control
I am an electronics hobbyist and this is my first attempt at an analog circuit of this type. Mostly I stick to arduino and LED stuff or just wiring up kits, etc. This is my first attempt at designing a "real" circuit. I think I have a really good start here, maybe my circuit would even work great without any modification. I have a kit for DIY chrome plating and need a power supply for the chrome bath. It requires very high currents (.75-1 A per sq in surface area of item to be plated). You can of course buy these power supplies off the shelf, but they are extremely expensive for anything that can put out more than 20-30 A. The items that i would like to plate will require 50-60 A. The chrome plating portion of the process only take 2-5 minutes though. So this circuit will only be running for that amount of time. I wanted to see if anyone had any tips or input for what I have so far before I start building. I have all of the components in the schematic and have done a few small tests but have not fully assembled everything and run it. I only have basic circuit test equipment like a DVOM. Here is the schematic.
EDIT: This MOSFET is not rated for linear operation and is not a good fit for this application. I am looking for MOSFETS that would work but I'm not sure what to look for. I can only find one line of products made by IXYS that is specifically stated that it is designed for linear use.
EDIT #2: This datasheet is for a MOSFET that is used by another person to make a very similar circuit https://m.littelfuse.com/~/media/electronics/datasheets/discrete_mosfets/littelfuse_discrete_mosfets_n-channel_linear_ixt_90n25_datasheet.pdf.pdf
This is the link to the project: http://www.kerrywong.com/2017/01/15/a-400w-1kw-peak-100a-electronic-load-using-linear-mosfets/
The MOSFET IRF2804 is something that I have 8 of from taking things apart and saving their components. It's rated for 75 A and 300 W (with a huge heat sink)
The TC7650 is just there to amplify the voltage from the shunt up to a usable voltage so that I can measure the current with an arduino and have it display that on an LCD. I also thought that it would make the 100k pot have an easier time adjusting the input voltage if it was adjusting from 0-5 V rather than 0-.075 V. In the data sheet you will notice that you are supposed to have two 0.1 uF capacitors with it also. I have them but I couldn't find a schematic symbol with the correct number of pins so I left them out in the picture, but I do have them in the circuit.
I went through my resistor bins and measured them all to get as close to the exact numbers as I could find. The values in the schematic are from my measurements. I was trying to get the gain on the TC7650 so that I could use the max output voltage swing without clipping it.
Oh, also chrome plating really like very smooth DC current with very low or zero ripple for the best adhesion and smoothness which I think is what makes the power supplies so expensive. I lot of people have used a car battery in the past with good results and in the old days they would use a salt water rheostat to control the current. A lot of folks commented that it was not very fun to keep the current stable and the plating was very difficult with that method, so I thought I would try this circuit.
Here are the data sheets for the parts.
https://www.infineon.com/dgdl/irf2804pbf.pdf?fileId=5546d462533600a4015355de76f818e3
http://ww1.microchip.com/downloads/en/DeviceDoc/21463C.pdf
https://www.ti.com/lit/ds/symlink/lm324-n.pdf?ts=1591077649948
I also have a giant heat sink and thermal paste and I was thinking that I might put a TEC on there too just for good measure and since I have some 12V 60W peltiers.
AI: LM324 problems
The LM324 is a poor choice when its feedback loop incorporates another op-amp and an external MOSFET. The reason is that the data sheet just does not give enough information about: -
Phase margin
Capacitive loading
This means that it's really difficult to determine if it can be stable with these extras in the feedback loop. I couldn't use an LM324 in this application for that reason alone. It may have circa 45 degrees phase margin (a guess) and, I would trust this for normal types of feedback but, not with a MOSFET and another op-amp within the feedback loop.
The MOSFET has a forward transconductance stated in the data sheet of 130 siemens; in other words, the drain current will change by 130 amps for each volt change on the gate. Let's just call it 100 amps per volt because that's what it will be below the ZTC of the MOSFET (another story told further down).
Basically (and cutting a few corners) if the LM324 output changes 10 mV, the drain current changes 1 amp and this means the source voltage changes by about 1 mV because of the 1 milli ohm shunt. In other words, the MOSFET is not like an emitter follower (where we can assume emitter voltage follows base voltage). However, for this particular analysis that isn't a bad thing because the MOSFET acts like a 10:1 attenuator (less feedback = more stability). But then the extra op-amp (TC7650) applies a gain of 67 so, what we are feeding back to the LM324 is 6.7 times bigger than what it is outputting.
If the LM324 was run in unity gain, what is fed back is 1:1 but now, we are feeding back a signal that is 6.7 times bigger than the output and, in all certainty, who could expect the LM324 to remain stable? It might remain stable or it might not - there is not enough information in the data sheet to make a decision on this. Who would be surprised if it went unstable?
Then there is the bad side of the MOSFET acting as a 10:1 attenuator - in effect, the LM324 output pin sees all the gate-source capacitance and it will likely de-stabilize it for that reason alone. Does the data sheet help? Not really - the bottom of page 11 tells us that values up to 50 pF can be tolerated in unity gain situations. Have we got unity gain? No, we have worse scenario than unity gain because the signal fed-back is 6.7 times bigger. Will the LM324 remain stable - there is not enough information in the data sheet to make a rational choice. Again, who would be surprised if it went unstable?
What if a simulation showed it to be stable? It might but, then again, the bottom line is the data sheet and not the model and, if the data sheet isn't stating how the LM324 performs regards phase response or capacitive loading, then don't use it - pick an op-amp where the stability can be analysed on paper and verified in a simulator and validated in a real test.
MOSFET problems
Clearly on page 1 this MOSFET is intended for switching applications - read the "features" part. If it was intended for linear applications (the question is about a linear application) then the data sheet would say so. Added to this is this graph on a later page: -
The above graph tells you that when gate source voltage is 6.3 volts or above, the MOSFET will have a temperature coefficient that prevents thermal runaway. Below 6.3 volts (it can runaway and destroy itself). Where will the OP's circuit be running? The OP says 75 amps so, given that the ZTC (zero temperature coefficient) is at 300 amps, the MOSFET will likely be very susceptible to thermal runaway. See this answer and this answer for an explanation of the Spirito effect that will dog switching MOSFETs in linear applications.
But, simply put, if you look at the graph above and you were controlling the gate to produce 10 amps drain current, the gate voltage would be around 4.6 volts. Within possibly a millisecond (and there's a lot of evidence that suggests it's significantly less than 100 us), a hot spot can occur on the MOSFET die and that spot will hog all the MOSFET current and rapidly (and I mean rapidly) destroy it.
This happens because the device has to get warmer because it's dissipating power and, as it warms its drain current rises and it gets even warmer - you can see the upper curve for a junction temperature of 175 degC - at this temperature, the drain current could be 60 amps before the closed loop control has had a chance to respond (this problem happens very quickly). But it won't end at the 175 degC curve - it'll keep rising and destroy itself. The hot-spot that occurs will have a much lower on resistance locally and pretty much all the current will flow through this hot spot instead of evenly flowing across all the channel area of the MOSFET; the outer areas away from the hot-spot will hardly take any current and the MOSFET will fuse at that hot-spot.
Use a MOSFET intended for linear applications or one with much less thermal runaway when driven below the ZTC point.
Possible solution
Firstly, get rid of the LM324 and use the TC7650 in its place like this: -
Notice that I've added a gate series resistor and an extra feedback resistor and capacitor to quench the control-loop speed. This isn't proven by any means but is a recognized technique for averting feedback loop instabilities.
Then I'd consider using a MOSFET like the IXTT110N10L2 because of its transconductance graph: -
Things to note: -
To get 10 amps flowing at 25 degC requires a gate source voltage of about 5.4 volts.
If the MOSFET warmed to 125 degC the drain current would rise to about 18 amps (i.e. the rise is likely to be significantly less than for the proposed MOSFET in the question).
It's a linear MOSFET as stated on the data sheet front page and therefore can be trusted more than a MOSFET intended for switching applications
Safe operating area curves: -
The red lines show the operation at 75 amps. I would prefer a little more clearance but maybe a better MOSFET can be found. The original proposed MOSFET doesn't even list a DC safe operating area (minimum is for 10 ms): -
And, importantly, linear MOSFETs are designed to avoid hot-spots (the main problem that will dog a switching MOSFET).
|
H: Do I have to supply an analog switch IC with a voltage level higher than the switched voltage level?
I have an analog switch circuit as seen in the image above.
I want to switch a digital signal which has either -5.4V or +5.4 level.
My analog switch is MC74VHC4316.
According to the datasheet, the VCC voltage can be in the interval of [+2.0V, +6.0V], and the VEE voltage can be between [-6.0V, 0V].
I understand that the internal impedance of the switch varies according the applied VCC and VEE voltage levels (see: datasheet, 4th page, 2nd table).
I want to know if I need to apply at least +5.4V VCC and -5.4V VEE voltages in order to transfer a \$\pm\$5.4V signal. What happens if I supply the IC with lower VCC and VEE voltages (e.g.; VCC = +3.3V, VEE = 0V). Does my digital signal get clamped? Does anything bad happens other than seeing a higher switch channel impedance?
AI: The recommended operating conditions suggest your input signal should not be outside the power supply range. The absolute maximum ratings state that exceeding the power rails by more than 0.5 volts may damage the device (orange rectangle below).
I want to know if I need to apply at least +5.4V VCC and -5.4V VEE
voltages in order to transfer a ±5.4V signal.
Yes that would be OK
What happens if I supply the IC with lower VCC and VEE voltages (e.g.;
VCC = +3.3V, VEE = 0V). Does my digital signal get clamped? Does
anything bad happens other than seeing a higher switch channel
impedance?
You risk damaging the chip. However, if you limit the current drive capacity of your slightly excessive signal to significantly within the +/- 25 mA specified in the absolute maximum ratings, then this should be fine but, your signal will become clipped.
|
H: Beginner: Issues wiring up a simple LED circuit
I'm a programmer, but a complete beginner in electronics. I've been following this guide where one of the first projects is to create a LED circuit using this circuit diagram. I've tried wiring up the simple LED circuit, but it doesn't work.
I'm guessing some of these parts have a significant change of failing due to poor production, so I swapped out the LED's, jumper wires, and resistors for identical parts. Note: I am using a 220Ohm resistor
I also moved the position of where the jumper wires connect from the Arduino to the board, i.e. moved them up and down, and have done the same for the LED, resistor and other jumper wire. I have made sure that the LED cathode and anode are in the correct arrangement on the breadboard. I also made sure to push down on the components to make sure they made contact with the board.
When the GND and 5V aren't both connected to the breadboard at the same time, the "ON" led on the Arduino is solid red, and the "L" led is blinking. But when I connect both the jumper wires as below, those two led's stop emitting light. Is this normal behaviour?
I am a beginner so I probably messed up the wiring somehow. I would also very much appreciate any guidance on resources or methods on how to learn about electronics. If the wiring is fine, is it possible that the breadboard isn't working?
AI: First lets get the wiring diagram from the tutorial in here:
Note that it is a wiring diagram, not a schematic diagram. Yours shows you which wires to connect to what. A schematic diagram shows how the the circuit works.
That said, your breadboard and the breadboard in the wiring diagram are different. That's the danger of following a wiring diagram - it doesn't show you how it works, only how to wire it on the assumption that all of your parts are identical.
A schematic diagram of the tutorial circuit would look like this:
simulate this circuit – Schematic created using CircuitLab
If I trace out the circuit from your photo and draw a schematic diagram from it, it looks like this:
simulate this circuit
Breadboards have certain conventions that they follow, but that you don't know about yet. Your "tutorial" also didn't bother to explain it. I am very wary of tutorials because they almost never include all the details.
The breadboard in the tutorial has the following connections:
The holes in columns along the edges are connected together. There are two such columns on each edge:
The rows of five holes each are connected together:
(Imagine the red lines as wires. The pins are connected together inside the breadboard, and so act as wires.)
The breadboard you are using doesn't have the columns on the edges. It only has the rows of 5.
Now lets take your photo and draw the connections in:
As you can see, you've shorted the power supply and the LED and resistor are off floating in space by themselves.
The same thing done with the tutorial wiring diagram looks like this:
That has power properly connected to the LED, and the LED in series with the resistor.
I'll leave the correct wiring of your breadboard as a learning exercise for you. I think it should be fairly simple to figure it out. If not, leave a comment and I'll sketch it for your.
|
H: Short to battery & short to ground
In automobile industry, while some of the sensor & valves were connected with electronic control unit, short to battery & short to ground test conditions are taken care against the loads.
What is the reason for this test condition?
AI: Any wire connecting to a sensor can touch or short with another wire that is battery positive ie 12V+ so the sensor is fed directly from the battery. What will the sensor do in those conditions? Fail open circuit or fail short circuit? If short circuit then will that cause a fire or damage to other wiring? Failing open circuit does not tend to cause wiring damage.
If the sensor wire is shorting to the body or ground, i.e. battery negative then will that damage the sensor or other wiring or the unit supplying the sensor?
All these need to be checked and accounted for, and fuses or current limiters need to be fitted as appropriate.
|
H: RAST 2.5 pcb design
Currently I am designing a pcb and I need a RAST 2.5 connected to my board DIRECT MATING as seen as picture below (example from google).
But as I am searching in the library, I am using EAGLE, I couldn't find the exact component for that particular connector. I'm searching on google and couldn't find the right one. Anybody has the library for that component and kind enough to share it with me?
DATASHEET : https://downloads.lumberg.com/datenblaetter/en/3521.pdf
AI: The part: -
The part isn't a PCB solderable connector - it has wires on one end and sliding contacts on the other hence, why should there be a part for it in EAGLE or any PCB/schematic CAD package? It doesn't solder to the PCB cannot be regarded as having anything other than a schematic symbol - it can't have an EAGLE footprint because it has no solderable pins. Yes it might have wires connecting to it that get soldered to the PCB but, it won't have a footprint hence it will never be regarded as a valid component for EAGLE.
|
H: What protective device can be used to avoid no-load operation in a dc series motor?
I think there must be some relay or converter which automatically shuts the machine on no load condition.
( Just Guessing )
The following para is a quora answer which I am not sure is correct, please share your thoughts-
You can modify it by putting resistor in parallel to armature winding, such that will draw current. So now field current = armature + external resistor current.
AI: Ordinarily, it is not necessary to protect a series motor against no-load operation. The motor's own mechanical losses will be sufficient to prevent the motor from operating at a speed that would cause damage. If the driven machine requires protection from excessive speed, a centrifugal switch can be used shut the motor off when an above-normal speed is reached.
|
H: How does Synchronous Transmission provide synchronized clocks?
I was reading a textbook which says:
in synchronous transmission, the bit stream is combined into longer “frames,” which may contain multiple bytes. Each byte, however, is introduced onto the transmission link without a gap between it and the next one.
as the picture below shows:
and I was also told in Synchronous Transmission, the sender and receiver should have synchronized clocks before data transmission.
so how does clock get synchronized before data transmission? all I can see i the picture is, the sender sends many bits in frame, how could it synchronize the clock?
AI: There are many ways and I've only covered a few things....
so how does clock get synchronized before data transmission?
In many cases the receiver doesn't acquire sync until it recognizes a frame header. And this means that some initial data is never recognized and is lost forever. However, for things like CCTVs and remote monitoring of signals this simply doesn't matter.
Once the receiver has "locked" to the frame then it can acquire data. This means that the receiver must know the data layout i.e. header followed by a byte representing the payload byte length followed by payload data and possibly appended with a CRC error check byte(s). That was just a typical example.
And it must recognize the next frame header or else it might consider discarding what it thought was the previous frame of data.
And, in many cases, the data has to be modulated in one form or another to ensure that there are sufficient bit changes so that the receiver can keep its automatically generated internal clock synchronized to the incoming data. This can be achieved by: -
Manchester encoding (example)
Data scrambling
Both of which are too deep to go into here.
Of course, the transmitter could just ship-out a clock signal on another wire for use by the receiver and that solves a lot of problems.
|
H: Is Gaussian noise equal to white noise?
If noise on a signal is randomly fluctuating in time domain around its mean following a Gaussian normal distribution (Gaussian noise), would this be equivalent to an constant intensity in the frequency space (white noise)?
Can we somehow relate the frequency distribution to the amplitude distribution?
AI: No, they are completely orthogonal concepts. The probability distribution says nothing about the frequency content, and the power distribution across frequency says nothing about the sample probability distribution. You have to specify both.
|
H: DC Power Jack pinout
This question is related to part with part number PJ-102AH (CUI Devices).
Digikey link: https://www.digikey.com/products/en?keywords=PJ-102AH
Datasheet: https://www.cuidevices.com/product/resource/pj-102ah.pdf
The datasheet shows this:
For this, I understand that pin 1 is positive.
What is really the negative? 2 or 3?
And how the remaining pin work? Does it connected to negative when the cable is plugged-in?
AI: Pin 1 is "positive" if your system is setup like that. THERE IS NO REASON IT COULDN'T BE NEGATIVE! "Positive Tip" is something of a common standard, but there are examples where this is not true (for example - guitar pedals pretty much are all negative-tip, positive shield)
Pin #3 is a switch that is 'normal closed'. When no plug is in the jack, pins #2 and #3 are shorted together. When you insert a plug, pin #3 actually moves and becomes disconnected from pin #2. In this state, there is no electrical connection between pin #3 and the plug.
This is useful when the device has both batteries and wall-power input. When you insert the plug, it automatically disconnects the batteries (thus preventing your wall-power from charging the batteries)
Most likely, in your case, you would make pin #1 "positive", pin #2 "negative" and pin 3 not connected. But only you can know if this is right or not as we don't have access to the rest of your circuit or understanding of what you're trying to accomplish.
|
H: Buck converters duty cycle
From this article: Power Tips: Power converter topology... they say that:
Moreover, buck-converter duty cycles become extremely small in
high-voltage AC/DC conversion. For a 440VAC to 15VDC conversion, the
duty cycle could be smaller than 2% in a DCM buck converter. When
operating the converter at a high switching frequency, it is possible
to hit the controller minimum on-time limitation; for example, the
UCC28911 requires a 420nS minimum on time. In other words, if you use
the UCC28911 in a 440VAC to 15VDC conversion as a buck-converter
controller, the converter must operate at a switching frequency lower
than 45kHz.
What I understand is this. Let's say the duty cycle is 2%. If the switching frequency is 60 kHz, then the minimum time would be 0.02*(1/60k) = 333 ns. And the UCC28911 wouldn't start because their minimum time is 420 ns according to the datasheet. Then the article says that the converter must operate at a switching frequency lower than 45kHz. However, the datasheet says the minimum switching frequency is 420 Hz. Would the controller adjust the frequency itself if this situation with the minimum time happen?
AI: As per the datasheet:
https://www.ti.com/lit/ds/symlink/ucc28911.pdf?ts=1591886894954&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCC28911
During voltage regulation, the controller operates in frequency
modulation mode and amplitude modulation mode. The internal operating
frequency limits of the controller are 115 kHz maximum and 420 Hz
minimum. The transformer primary inductance and turns ratio sets the
maximum operating frequency of the converter. The output preload
resistor and efficiency at low power determines the converter minimum
operating frequency. There is no external compensation required for
the UCC2891x devices.
as long as the loading isn't too light and the voltage conversion range is too large that the lower frequency limit is hit, the controller shall regulate the switching frequency according to the operating case e
|
H: Purpose of capacitor and resistors on the output of three-state buffer
I intend to use a buffer with three-state output in one of my designs. The datasheet of the buffer IC shows the following circuit:
What's the purpose of CL, RD and RU on the output of the buffer. As I understand the values of RU and RD are equal - leaving the output floating between VI and GND maybe? But why?
Link to the datasheet: NC7SZ125
AI: The datasheet is showing you the test circuit they used to test the buffer.
The propagation delay are specified into a certain CL.
The output enable and disable times are specified with a certain CL, RU and RD.
If your circuit stray capacitance and load capacitance are less than CL, then you should get at least the specified performance from the buffer.
|
H: Beginner: How to wire up a navigation button / joystick?
I have a joystick that I wish to connect to my Arduino uno. However, there's no VCC or 5V or GND pins to connect to. I do see a COM pin, but I'm unsure how I should wire that to the Arduino. My objective is to take an input that determines whether LEDs should be emitting light or not.
I can't find any model number on the PCB or on the listing where I bought it from. The only information provided on the listing:
AI: The device is likely a just a set of passive switches. There is no "VCC".
"COM" would be the "common" pin. You can supply it with a voltage (5V
for example) and then each signal (UP/DOWN/etc) would go to something
like inputs on your microcontroller.
You could also use it the
other way around by connecting COM to ground, and the signal pins
could have their own pull-ups.
|
H: What would happen if I used a potentiometer to produce a 5V DC signal for an Arduino from a 9V battery?
What makes the potentiometer not a good component to use for reducing the 9V to 5V DC for an Arduino?
I thought of using it but I been told it is not a good idea, so I am looking into the reasons why.
AI: When I was young and innocent I tried the same for a bunch of relays, and my potentiometer caught fire!
First off, as you allude to, it is in some cases possible to regulate load voltage with a potentiometer. You can use it as a divider (three terminals) or as a series resistor (two terminals). However, this involves you adjusting the potentiometer depending on the drawn current. For constant loads this is feasible, but not so for fluctuating loads from a processors, as others here pointed out.
Your circuitry, including it's input/outputs and peripherals, use different currents depending on their state/mode. And their reliable operation depends on a constant load-independent supply voltage. That said, if the current fluctuation and the ensuing voltage fluctuation do not affect the operation of a (perhaps fixed) load, then the potentiometer or voltage divider can be used.
But there are other factors too: heat and efficiency. The current through the potentiometer, and the ensuing I^R heat, generates heat in both configurations. And in the divider configuration you have a current running even if there is no load.
Since my pyrotechnic experience, I instead use a "LM7805" integrated regulator for simple cases (https://en.wikipedia.org/wiki/Voltage_regulator)
These regulators keep the 5V constant practically for all (fluctuating) current loads from your Arduino and any peripherals (sensors, LEDs etc..). They are very easy to use, and quite suitable for a simple table-top home lab, but they are not very efficient. In other applications they can get hot, and so now I only occasionally lightly burn a finger.
If power efficiency / battery life matters, look at switch mode power supplies, like the LM2674
https://en.wikipedia.org/wiki/Switched-mode_power_supply
|
H: Does dividing a clock increase its jitter?
I want to have my microcontroller and ADC using a clock derived from the same source in an effort to avoid intermodulation effects. All clocks are under 50 MHz.
The maximum SNR out of an ADC is bounded by the jitter of its sampling clock. This means that I want to make sure to keep the jitter of the sampling clock below some threshold.
Does anyone have some information on a good way to handle this, or some information about gotchas? I looked at some of the fancy clock/divider ICs, but they are overkill in price, power, and frequency.
So far I've thought about two methods.
Use external ICs like flipflops to divide down the clock.
Use the timers/counters in the MCU to divide down the clock and output it to the ADC.
I tried to find some information about how much a clock will degrade when passed through flipflops or MCU timers/counters, but I couldn't find any information.
AI: As long as the divider is using only one edge of the input clock, and only one edge of the output clock is being used by the ADC, then no, there will be no significant increase in jitter.
The output edges will have the same peak-to-peak jitter as the input edges, in terms of absolute time (ps or ns). But expressed as a fraction of the output clock period (% UI), the jitter will be reduced by the division ratio.
|
H: Help understanding open collector comparator
I am working on a simple circuit based on the LM311 comparator. It has an open collector, which is not something that I've used before, and I have a few questions. First, my understanding of the open collector model is that the internal comparator switches between open and connected to ground, requiring a source at the output to create a current. If that is the case, what is the purpose of the VCC rail voltages? Finally, I've tried modeling the circuit in multisim but I keep getting 5v at the output regardless of what the + and - inputs are. I assume that is due to my pull-up resistor, but I think I am just misunderstanding somewhat how this comparator is meant to be setup. My circuit is below, I've tried tying pin 4 (VCC-) to ground, and pin 8 (VCC+) to my 5v VCC, but I get the same result regardless.
AI: The comparator still has Vcc pins because the comparator still needs power to run.
Also, you are probing the +5V power supply, not the output which is Pin 7. So of course you would always see 5V. Durr moment.
|
H: Vacuum Fluorescent Display: What are the benefits of an AC filament driver instead of DC?
Question is already in the title:
What is/are the benefit(s) of an AC filament driver instead of DC for VFD displays?
It works with DC so why to invest in an AC driver?
Anyone?
AI: The filament is also the cathode of the device.
With DC excitation one end has essentially a different DC bias voltage than the other and will result in different emission. This may give uneven illumination or wear out characteristics than when using AC which evens out the bias.
As other posters have commented it is also preferable to provide the DC bias relative to the center tap of the filament or to have a center-tapped AC supply.
|
H: Kelvin Source Terminal on MOSFETs
On MOSFETs with multiple source pins, is the so-called "Kelvin-connected source pin" connected any different internally? Or is it just like every other source pin?
EDIT: Just to be clear, I am not asking what the Kelvin connection is for. I'm asking whether it is physically implemented any differently than the other source pins or whether it is just an extra regular, old source pin.
AI: The Kelvin connection is basically a dedicated small signal connection straight from the SOURCE/EMITTER of the die, dedicated for control.
The reason this is done as oppose to using the SOURCE/EMITTER which carries the main current is to mitigate inductive voltage changes on the gate-source/emitter when switching current.
As devices switch faster this inductive drop can be enough to turn the device in/off.
It can be compared to the Kelvin connections on sensing components (sense resistors, NTC/PTC) where their primary concern is to minimise measurement error due to additional voltage due to harnessing and associated current.
Consider the image below. A MOSFET and a gate drive as part of a H-Bridge. Essentially this is how you would capture the circuit, but this is not the complete picture:
The package will have stray inductance and equally a classic 3-pin FET/IGBT will have lead inductance, and poor layout can result in poor control.
With higher current or higher switching speed, the voltage developed across the stray source inductance will increase. A TO-247 will typically have around 20nH of D-S inductance, roughly speaking split in half per pin. With current of 100A switching in 200ns, the resultant voltage developed across this pin, \$V = L \frac{dI}{dt}\$ or 5V, while the gate is being charged or discharged, effectively reduces the voltage from the driver, reducing or limiting switching speed.
To mitigate this, manufacturers of devices for power applications provide an auxiliary Source/Emitter connection to permit gate voltage control without transient behaviour due to the main current carrying connection:
Typically this is done via an additional bondwire (thinner gauge as it does not need to carry current) onto the Source/Emitter pad of the die, routed to the auxiliary Source/Emitter pin.
From: CREE 1200V SiC Module teardown reverse costing report published by Yole Developpement - slideshare.net
Another example of the kelvin source connection:
From: The Odd Couple: Silicon and Carbon Don’t Love Each Other. But When They Iron Out Differences, Their Marriage Can Be Revolutionary - GE
|
H: Fluctuating ADC results - is it normal and characterized in a datasheet?
As I have been reading [1], there exist four different DAC error types, which contribute to the overall error:
Offset Error
Gain Error
INL Error
DNL Error
Is my understanding correct, that these are static errors?
So if I was to take a measurement of a stable analog voltage,
the obtained result by the ADC has a certain error.
However, If I am to repeat the measurement x times, I would still obtain the same result, no fluctuation?
[1] https://www.maximintegrated.com/en/design/technical-documents/tutorials/7/748.html
Background:
I am using a 10 bit ADC, and my voltage reading fluctuate all the time.
The ADC accuracy specs are:
Integral Nonlinearity INL ±0.5 LSB (typ) ±1 LSB (max)
Differential Nonlinearity DNL ±0.25 LSB (typ) ±1 LSB (max)
Offset Error ±1.5 LSB max
Gain Error ±1.0 LSB max
I took multiple readings with a voltage divider formed of 2 1k Ohm resistors, sourced by 3v3 on a raspberry pi 3.
The results are (left column is the abs. frequency, right col gives the voltage value):
4 1.633887
14 1.637109
57 1.640332
7927 1.643555
7585 1.646777
9042 1.650000
605 1.653223
9 1.656445
2 1.659668
With a better circuit board would I ideally only obtain the same value all the time, regardless of how large INL, DNL and other errors are?
Thank you!
Edit:
As suggested by @JRE and @JustMe the unclean voltage and breadboard setup was indeed causing all the fluctuations. I am still using the poor setup on a breadboard as before where I had the fluctuating readings.
For anyone else with the same problem, a capacitor next to the ADC on the breadboard (as it would have been suggested for PCB designs anyway) fixed things nicely (used a Panasonic FR capacitor with 270 uF). My readings are now repeatedly 1.65 V without any fluctuations.
AI: Yes, the ADC lists those parameters under "DC Accuracy", meaning even if these DC parameters are non-ideal, it should give same value when sampling an ideal noise-free DC voltage source, assuming it is connected to ideal noise-free DC power supply. Some other additional assumptions may apply as well.
So, in light of this, under non-ideal conditions, fluctuating results due to external sources of fluctuations is normal, but they can't be characterized in the datasheet, because the datasheet won't know what signal you are measuring, how noisy the ADC power supply, and how the signal or supplies fluctuate.
|
H: 4 Pins Potentiometer (Replacement)
I am trying to repair a very expensive manlift joystick.
It has 4 pins total, three like a normal rotary potentiometer and then a fourth across from the other three pins.
It is PEO 284-04378 Type EJ pot. It has another number stamped "5k 1342"
The company not produce it more and I'm looking if there is something similar to do the same work I was looking for P271-DS21BR10K but is 10K would that affect?
AI: It seems almost certain that you are looking for a "center tapped potentiometer" If you search using that term, you should be able to find a replacement. It seems likely that the pictured pot is 5K ohms. You may or may not be able to use a different value. You can not find the correct value, you could try a different value and see what happens. Trying 10K rather than 1K would seem to me to be the safest thing to try if you can not find 5K.
|
H: Simple circuit for a single 10 ms pulse when closing a contact switch
I have a simple circuit (see image below) that creates a single 10 ms pulse when closing a contact switch (SPST) but I also need that after generating a pulse the circuit will wait some time (500 ms for example) until being able to generate a new pulse. The pulse generation works fine but I'm having trouble implementing the wait time, my circuit will generate a pulse each time the contact is closed. Any clues on how to do this please?
AI: If I were going to design such a circuit, I would borrow techniques from the traditional transistor multivibrator.
simulate this circuit – Schematic created using CircuitLab
If you run the simulation, you'll see that it produces one output pulse for every six input pulses. The lockout period is just over 500 ms.
Adjust C1 and R4 to control the output pulse width.
Adjust C2 and R6 to control the lockout period.
R2 and D2 make sure that the output pulse is the full width even if the switch closure is shorter.
D3 and D4 are required because the supply voltage is so high relative to the reverse BE breakdown voltage of the transistors. If the circuit could be run on, say 5V, they could be eliminated.
Note that my original circuit shown above (now slightly modified to save a part) will "auto repeat" at about a 2 Hz rate if the switch is held down. A slight additional modification (C3, R7, R8, below) eliminates this behavior, giving one pulse per switch operation, regardless of how long it is held.
simulate this circuit
|
H: Does Slave Select have to be sychronous with Clock?
I'm working on the SC18IS600 chip (SPI to I2C converter) and have been having issues just communicating with it. At the moment I am attempting to configure the I2C Address register and set it to 0x3F or 0x00. When reading the address back however, I am getting (afaik) gibberish - it's not even reading back the default address value. While testing I noticed that the CS line goes low much earlier than the clock signal and want to know if the CS line must be synchronous with the clock when using SPI, or if a delay like the below image is acceptable. If anyone has other suggestions as to why this might not be working, please feel free to make them.
Edit for explanation: The 'gibberish' I was receiving was a result of not allowing for an 8us gap between each data word. The SC18IS600 requires this gap, further explained here for anyone else: https://community.nxp.com/thread/461576
Image: yellow = MISO/rx, blue = MOSI/tx, pink = clk. Image taken while trying to read the address. Sorry for the image quality, it's a very old oscilloscope that can't save images anymore.
datasheet at https://www.nxp.com/docs/en/data-sheet/SC18IS600.pdf
AI: No, in fact there's usually a minimum time that the CS signal must be pulled high/low before you can start clocking in data.
From your datasheet (pg 19):
:
$$ t_{SPILEAD} $$ is the minimum time, in your chips case 4µs (datasheet pg 18). Make sure your transmission follows those timing requirements/transmission protocol.
|
H: Charge carriers of an electric current
I was under the impression that electric current was caused exclusively by the flow of electrons moving through the wire.
However upon doing a little more research on electric current, it is said that charge carriers are often electrons moving through a wire. What other charge carriers are there besides electrons when applied to electric circuits?
AI: As the reference from your question states, "An electric current is the rate of flow of electric charge past a point or region". The rate of flow IS an electric current, not that the flow CAUSES electric current, according to the Wikipedia article.
Both electromagnetic and non-electromagnetic forces can CAUSE the movement of charge carriers. In the context of semiconductor devices, there are two kinds of current regarding "flow of electric charge". The drift current is caused by an electric field; the diffusion current is a current caused by the diffusion of charge carriers. Both kinds of current can include movement of positive (holes) and/or negative (electrons) charge carriers. This statement answers your question "in the context of semiconductor devices".
ADDENDUM:
Be careful when learning and using terminology, in particular, in electronic engineering. As with language in general, EE terminology is a result of historical process; its use and understanding can include intricate details.
For example, Ampère's circuital law, one of Maxwell equations, includes a term named "displacement current", which is not associated with any movement of charges.
Make sure your understand these intricacies and know the electromagnetic theory and you will not be baffled by seeming paradoxes, as, for example, the fact that the signal velocity in wires is higher than the speed of charge carrier transport.
|
H: STM32F051 ADC DMA overrun
I am trying to use ADC with 2 channels and DMA, but I only get 1 reading before the overrun bit gets set. Also the 1 reading is wrong, I am expecting a value of approx 2100, but I am getting around 70. I can see in the hadc->DR that the value are correct, but it is not transferred to the array somehow (adc_value in runADC200Hz function below).
here is the code I am using:
main.c
static void MX_ADC_Init(void)
{
ADC_ChannelConfTypeDef sConfig = {0};
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc.Instance = ADC1;
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc.Init.Resolution = ADC_RESOLUTION_12B;
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
hadc.Init.EOCSelection = ADC_EOC_SEQ_CONV;
hadc.Init.LowPowerAutoWait = DISABLE;
hadc.Init.LowPowerAutoPowerOff = DISABLE;
hadc.Init.ContinuousConvMode = ENABLE;
hadc.Init.DiscontinuousConvMode = DISABLE;
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc.Init.DMAContinuousRequests = ENABLE;
hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
if (HAL_ADC_Init(&hadc) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_0;
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel to be converted.
*/
sConfig.Channel = ADC_CHANNEL_1;
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
{
Error_Handler();
}
}
static void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
}
stm32f0xx_hal_msp.c
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hadc->Instance==ADC1)
{
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**ADC GPIO Configuration
PA0 ------> ADC_IN0
PA1 ------> ADC_IN1
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* ADC1 DMA Init */
/* ADC Init */
hdma_adc.Instance = DMA1_Channel1;
hdma_adc.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_adc.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_adc.Init.MemInc = DMA_MINC_ENABLE;
hdma_adc.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_adc.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_adc.Init.Mode = DMA_CIRCULAR;
hdma_adc.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_adc) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc);
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_COMP_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(ADC1_COMP_IRQn);
}
}
stm32f0xx_it.c
void DMA1_Channel1_IRQHandler(void)
{
HAL_DMA_IRQHandler(&hdma_adc);
}
/**
* @brief This function handles ADC and COMP interrupts (COMP interrupts through EXTI lines 21 and 22).
*/
void ADC1_COMP_IRQHandler(void)
{
HAL_ADC_IRQHandler(&hadc);
}
I am running the ADC every 5ms like this:
static uint32_t adc_value[2];
void runADC200Hz(void)
{
if (HAL_ADC_Start_DMA(&hadc, (uint32_t*) &adc_value[0], 2) != HAL_OK){
asm("nop");
}
}
After the first conversion these flags are set:
ADC ready (ADRDY)
End of sampling (EOSMP)
End of conversion (EOC)
End of sequence (EOS)
ADC overrun (OVR)
I have been setting up ADC with DMA several times before with no problems, but that was on F2 and F7. Strange thing is that I have access to another code which works for the exact same chip, with the exact same code I have written above. I have no idea where I should look and compare beyond those functions above. Any suggestion on what Im doing wrong here? I have tried every type of sampletime but it is the same result. thanks for any comments!
AI: You are repeatedly calling the ADC in DMA mode, yet you have configured it to run continuous conversion mode. Meaning it will never stop sampling, repeating the sequence until stopped.
If your goal is to sample at 200 Hz, change it to these:
hadc.Init.ContinuousConvMode = DISABLE;
hadc.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_xxx;
hadc.Init.ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Rising;
And configure a timer to trigger the sampling sequence.
I forgot, you also need to qualify adc_value as volatile since it changes outside of the compilers knowledge (the dma changes it).
The static keyword is poorly named and actually means private in this context. It has no effect other than reducing scope.
|
H: How does my breadboard circuit diagram look? Is my circuit going to explode?
I'm working on my first Arduino project and I thought I picked something simple enough. But before I set my breadboard on fire or ruin any of my components, I wanted to make sure my plan made since because I'm synthesizing several tutorials and data sources.
I am mostly confident I have selected the right components, but want to be sure I am connecting everything in the right order.
The goal of this project is to press a button which will activate an LED (internal to the button) and activate a solenoid valve. The button/LED and Arduino Uno board require 5V power and the solenoid valve requires 12V power.
Below is a diagram of my planned circuitry and here is a quick description of it:
Right Side of Breadboard (12V power circuit):
Power Arduino board with 12V power source
Pass 12V power to one row on the breadboard through the VIN pin
Pass power from the 12V row to a 12V solenoid valve
Connect the other solenoid wire to an empty row on the breadboard
Attach a diode from the row with the negative solenoid wire to the row with the row used to pass a 12V current through the positive solenoid wire to restrict the flow in that direction
Attach one ground pin on the Arduino board to another row on the breadboard
Attach a darlington transistor with the base pin connected to the ground row from the Arduino board
Connect the collector pin from the transistor to the row with the negative solenoid wire
Attach a 1K Ohm resistor to the emitter in of the transistor and attach the other end of the resistor to a new row
Finally, attach that row containing the other end of the resistor to a digital I/O pin on the Arduino
Left Side of Breadboard (5V power circuit):
Connect 5V pin on Arduino to new row on breadboard
Connect one positive wire to button switch contact and one to LED contact (integrated with button)
Connect another ground pin on Arduino to a new row on breadboard
Connect 10K Ohm resistor from ground row to new row on breadboard
From that row, connect one wire to the positive button switch contact and another wire to a new Arduino I/O pin
Connect 220 Ohm resistor from ground row to new row on breadboard
From that row, connect one wire to the positive LED contact and another wire to a new Arduino I/O pin
Some of the resources I referenced:
https://www.bc-robotics.com/tutorials/controlling-a-solenoid-valve-with-arduino/
https://core-electronics.com.au/tutorials/solenoid-control-with-arduino.html
https://www.arduino.cc/en/tutorial/button
https://www.instructables.com/id/Plug-and-Play-Arcade-Buttons/
Some of my components:
Arduino 12V Power Supply (https://thepihut.com/products/arduino-universal-power-supply-12v-2a-high-voltage)
12V Solenoid Valve (https://ussolid.com/u-s-solid-electric-solenoid-valve-1-4-12v-dc-solenoid-valve-brass-body-normally-closed-viton-seal.html)
Arcade Button (https://www.adafruit.com/product/3491)
Arduino Uno REV3
Tiny breadboard, breadboard wires, quick connect wires
1N4001 Rectifier Diode
TIP120 Power Darlington Transistor
Resistors of various values
EDIT 6-21-20
Below is my second attempt at a circuit schematic.
The first "half" of my project is complete, with the button and LEDs working as expected (obviously this part was easier). I don't have the 12V power supply yet so I can't test the other "half."
EDIT
I'd love to hear any feedback on my circuit schematic (first time making a diagram like this as well):
AI: You're not going to explode yourself, but your circuit isn't going to work.
According to your wiring diagram, your transistor is connected wrong.
Your control signal from the Arduino (D4) is connected to the emitter of the TIP120, while the base is connected to ground and the collector is connected to the motor. It won't work that way. Luckiliy, you have a 1k resistor in series between D4 and the emitter so it won't burn out your Arduino.
A proper low side switch looks like this:
Note where the base, emitter, and collector are connected.
Besides the transistor, you'll want to consider the current it takes to operate the valve.
According to the info page for the valve you linked to, the valve uses 15 watts at 12 volts when activated. That's over 1 ampere of current. Depending on the quality of your breadboard, that may be too much. The contacts might get hot and no longer properly hold the wires. Worst case you melt the plastic on your breadboard and ruin a bunch of contacts on your breadboard.
It would have been nice if you had posted a schematic diagram as well as the wiring diagram.
In this case, the wiring diagram was OK because you are specifically asking about the breadboard.
It's easier to discuss the circuit itself if you have a schematic diagram with part designators. It is much easier to say "R1" rather than "that 1k resistor connected to the base of the TIP120."
|
H: If AA batteries don't supply sufficient power, will adding more of them in parallel help?
My device requires ~4.5 V.
I'm using 4 battery packs connected in parallel
Each battery pack contains 3 metal-encased non-rechargeable alkaline AA batteries.
I used voltmeter and verified that each battery pack individually provides ~4.5 V.
I have also used voltmeter to verify that all battery packs are correctly connected in parallel.
All the batteries are of the same nominal voltage, the same brand and product name (Varta Longlife).
(It shouldn't matter here, but for completeness: The batteries are used as a backup to the main power supply, which supplies about 0.5V more than the batteries. Both the power supply and the batteries are connected via a Shottky diode [1N5822 40V/3A DO201] to prevent "charging" each other.)
The device runs fine on the battery packs, but sometimes, obviously when a load spike comes, the device suddenly switches off.
I measured that the device, when connected to the power supply, draws 1.6 A during spikes. Normally it draws about 300-500 mA.
Question 1: Shall I keep adding more battery packs in parallel? Will it help or does it only increase the lifetime, but not max current/power?
Question 2: If I use a battery with higher mAh rating, will it help, or does it only increase the lifetime?
As a side note: I am also going to try top-notch lithium AA battery instead of alkaline to see if it handles the spikes.
Thank you.
EDIT: The backup is not supposed to be used much, just very rarely, during a power outage (which we haven't had in years).
UPDATE: I've tried the best lithium AA batteries on the market, replaced the alkaline batteries, and found out that they didn't handle the spikes, either. Moreover, they supply ~5.5V instead of the ~4.7V that the alkaline batteries do. So that's not nice, either, because that is higher voltage than that of the power supply.
I'm thinking about using the capacitors or the suggested buck converter with 12 batteries in parallel. The thing is, I have no experience with capacitors and I don't even know what the circuit should look like.
As for buck converter I don't know anything about them, either, and am a bit worried that they would introduce more complexity to the system, possibly increasing the chance of failure.
So adding more battery packs in parallel, and changing to D-type batteries as some suggested, still seems to me to be the simplest (least complex) solution, which I feel capable of designing and building myself.
UPDATE 2: 4x3 D-type batteries (instead of the AA-type batteries I original used) did help and the device no longer shuts down during high-drain events.
AI: At 1.6A you're shorting the battery. Maximum load is about 500mA, this is already <1 hour.
Internal resistance is about 0.3 Ohm, at 1.6A sets you back half a volt per cell. So, for one pack with 4.5V (real 4.2V ) you go down to 2.7V in real conditions.
If equally divided over 4 packs this 1.6A is maybe fine (0.4A per pack), but if one cell fails, your pack cascades into failure. In theory with 4 packs you have 0.1 Ohm internal resistance, which is about 120mV drop during you worst case condition. For the entire pack that is about a drop to 3.72V. (4.2 - (0.12*4) when full. In theory.
Can you retry and measure the current of each pack vs the supplied voltage? This should give you insight in the paralleling behavior.
I also suggest rethinking this backup solution. Either
Put all the 12 cells in series and use a buck converter. (less current, same power, better power point)
Use C or D-cells.
Use protected lithium cells eg: 14500 (in series).
Maybe even consider lead acid if that fits.
Now you're abusing the poor AA's.
|
H: Understanding the role of a pull-up resistor
I am trying to understand the role of the transistor R11 in the following schematic:
The schematic simply generates a pulse at R5 when the switch is pressed.
If I understand correctly R11 is what one calls a "pull-up resistor" and it ensures that we can reliably switch on and switch off the circuit using the transistor. More precisely the presence of R11 (at a smaller resistance) allows us to reliably connect R4 + C2 to the ground. It makes sense that this is helpful.
But I don't understand why this is necessary. For instance is it possible to remove R11 from the schematic and connect directly R4 + C2 as the collector of the transistor?
Is it correct for me to assume that this will not work because the voltage across the capacitor will be sometimes negative? And as a result the transistor would not act like a switch but more like an amplifier?.
I'm sorry if these questions are trivial, I'm still learning about transistors...
AI: The circuit is an edge detector. When SW3 is pressed, it generates a brief 5 V pulse at Q3's Collector, Q3[c]. The pulse generation is centred around R4 and C2.
At rest with Q4 off, R11 pulls Q4[c] high and also R4 drives Q3[b] to switch on Q3 and drive Q3[c] low (around 0.3 V). Q3[b]->Q3[e] acts like a forward-biased diode so Q3[b] is at around 0.7 V. So C2 has 5 V at its 'bottom' end and 0.7 V at its 'top' end, charging it to -4.3 V.
At the moment SW3 is pressed, Q4 switches on and Q4[c] drops to 0.3 V or thereabouts. Vc2 is still -4.3 V so Q3[b] tries to instantaneously go to -4 V. The 2N3904 has a Veb max of 6 V i.e. a Vbe min or -6 V so this is OK but not ideal. C4 then charges through the connection to 5 V by R4.
However, when R4/C2 reaches about 0. 7V, Q3[b] conducts to switch on Q3 and its sort-of-diode (base diode) within Q3[b]->Q3[e] keeps Q3[b] clamped at 0.7 V. C2 has 0.3 V at its 'bottom' end and 0.7 V at its 'top end', so it stays charged to 0.4 V.
Holding down SW3 then does nothing more to Q3, which was briefly switched off by the pressing of SW3 but now stays on. When SW3 is released, Q4 goes off and Q4[c] is pulled to 5 V by R11. C2 is charged to 0.4 V so C2/R4 would go to 5.4 V but the Q3 base diode keeps its top at 0.7 V and is charges instead to -4.3 V, back to the rest state. Q3[b] doesn't fall below 0.7 V during this so Q3 stays on.
R11 is therefore the source of drive current from the Q4 stage. Without it, Q4 could deliver (a) a low sink current conducted down to 0 V or (b) a high-impedance 'floating' connection i.e. nothing. Adding R11 lets Q4 source current when on and sink current when off. As the R11 value is a tenth of R4, it has a much smaller effect on the time constant of C2 than R4 has.
Without R11, C2 'bottom' would be left floating when Q4 is off and could not charge to -4.3 V. Instead, C2 would stay charged, theoretically to 0.4 V. So R11 is essential for the circuit to clear itself on an SW3 release, ready for the next SW3 press.
Note that the transistor voltages given above are approximates.
|
H: Why is the datasheet showing VGS at absolute maximum?
I'm looking at IRLZ44N datasheet.
In the ABSOLUTE MAXIMUM section it is listed that for VGS it is 5V. However in the SPECIFICATIONS section below VGS threshold is listed as 1V to 2V.
At the same time in the ABSOLUTE MAXIMUM section the continuous drain current is given as 36A to 50A at 5V VGS.
Isn't the absolute maximum a value that you should normally stay away from to prolong the component's lifetime? I understand that this is in the absolute maximums section which is probably why they put such test conditions to achieve maximum results but if you go down to the SPECIFICATIONS section you'll see that RDSon is also given at 5V and 4V VGS.
Excuse my ignorance but this is slightly confusing to me. If my assumption is correct that you should stay away from the 5V VGS then how can I calculate the expected RDSon at 1V to 2V?
AI: The absolute maximum voltage rating of Vgs for the IRLZ44N is +-10V. Above this rating the device could be damaged
The Vgs threshold for guaranteed to be ON is 2V and the voltage for the device to be guaranteed to be OFF is 1V
Driving this device with 5V Gate-Source potential is perfectly fine and is a good choice to ensure the device is ON
|
H: How is the "I" current calculated in this circuit?
I found Vo with these processes
[10 - (- 2)] / (1200 4700) = 2.033mA
1200 * 0.002033 = 2,43V
Vo = 10 to 2.43 = 7,57V
but I can't find the "I" current. Can you help me?
AI: To find I it is a similar process and you can take credit for the fact that there is no load at Vo
Determine the voltage difference: 10V -> -2V = 12V
remove additional voltage drop: assume diode is 0.6V: 12 - 0.6V = 11.4V
calculate current through the resistive chain: 11.4/(1200+4700) = 1.932mA
|
H: Software oscilloscope
I have been developing a C language software for software oscilloscope
which is part of a control software. From timing point of view the
software consists of two execution loops.
The first execution loop (let´s say "fast loop"- FL) is interrupt service
routine (ISR) for the "end of A/D conversion" interrupt. This ISR is
invoked with \$100 \mu\mathrm{s}\$ period and is responsible for recording samples of
given physical quantities into associated circular buffers which creat
core of the oscilloscope. It is also responsible for pushing samples
into another circular buffers for FIR filter calculations.
The second execution loop (let´s say "slow loop" - SL) is a FreeRTOS task
which is executed after 8 executions of FL. This loop is responsible for
dividing the oscilloscope circular buffers into the "pre-trigger"
and "post-trigger" parts based on commands comming from software running on the
PC, storing the osciloscope records into the external flash memory and FIR filters
calculations based on values in the associated circular buffers.
I have been thinking about robust solution for exchanging data between
the FL and SL and vice versa. I need to ensure:
a) as soon as the SL starts calculation of the FIR filters these calculations
has to be done with 8 values gathered in the last 8 executions of the FL i.e.
it has to be ensured that despite the FL is still running and periodically
interrupting execution of the SL and has new samples the SL still uses the
same "snapshot" of the 8 samples (which was valid at the beginnig of SL
execution) for whole SL execution time.
b) as soon as the SL decides to change the division between "pre-trigger" and
"post-trigger" (based on command comming from the PC) by changing position
of a dividing point the dividing point position is allowed to change at the
beginning of next FL execution despite the fact that the request could come
during FL execution.
Can anybody give me an advice how to solve that? Thanks in advance for any
suggestions.
AI: The a) problem is trivial, I can't understand the b) problem.
Add a):
As you already mention a circular buffer, you will need a wr_pointer and rd_ponter. Now, when you update new sample, the wr_pointer is incremented in the ISR routine (FL): wr_pointer = (wr_pointer + 1) AND mask
buffer[wr_pointer] = ADC_value
wr_pointer = (wr_pointer + 1) AND mask
When the (wr_pointer - rd_pointer) AND mask >= 8 then you execute the SL, this can be done in main cycle, not need to have an additional ISR. You then read from buffer and increment the rd_pointer - only here. rd_pointer = (rd_pointer + 1) AND mask. The wr_pointer can change its value meantime, but it doesn't care.
if ((wr_pointer - rd_pointer) AND mask) >=8{
for .... 8 x read 8 sample
{
value[i] = buffer[rd_pointer]
rd_pointer = (rd_pointer + 1) AND mask
}
}
The mask is a size of buffer-1 , it's a power of 2. For example 8k bufer if 8192 cells, hence mask is 8191. At least that's how do I implement circular bufer.
The only caveat is that a wr_pointer shall be a variable type that is written all in one piece, for example a 8-bit MCU can split this into more values. It shall write the whole value in a single write.
EDIT:
ad 2)
You need to have a single whole buffer that has size of 2^N cells (power of two) to simplify the relative positions calculation with masking. You can calculate anything you want by simply using an "AND mask" operation after the arithmetic operation.
So let's assume that you have a SL thread that initially computes a sub-buffer of size 8, then in the middle of computation this is changed to 10:
divisions_temp = divisions
if ((wr_pointer - rd_pointer) AND mask) >=divisions_temp{
for 1 to divisions_temp // read divisions_temp samples
{
value[i] = buffer[rd_pointer]
rd_pointer = (rd_pointer + 1) AND mask
}
}
The same rule applies here. You may need to put some semaphore if the variable is not written all in one piece - this may happen if this variable is received though a communication directly. But if it is received consistently, let's say the communication routine receives bytes and then fills a structure of variables, you can copy the whole struct to another one, when the comm. is complete and without errors - let the comm. routine is a different thread. You can even place a semaphore when you copy the struct and you clear it when the copy process is finished. You look for this semaphore in FL thread, before using divisions variable.
EDIT2:
But let' assume your processor is 32-bit and the array indexes as well the divisions variable is also 32-bit, then the CPU will write all these variables in a single instruction, no need to worry and use semaphores.
|
H: Identify components in an audio circuit schematic
In the attached image you can see a circuit part of a commercial audio amplifier. I'm trying to determine what kind of component is R-CH and what role it plays in the circuit. I'd also like to figure out whether this circuit is on the audio signal path of the amplifier or not. What clues would give that away?
AI: I'm trying to determine what kind of component is R-CH and what role
it plays in the circuit.
R-CH is the right-hand channel. Above it you see the circuit for the left-hand channel. The total circuit is for a stereo amplifier of some sort that has left and right channels.
They don't bother showing the right-hand circuit details because it's a repeat of the left-hand circuit.
|
H: How to connect a low impedance RF amplifier to an antenna?
I'm trying to maximize power transfer from my amplifier to my custom antenna, but am unsure about how to properly impedance match the system.
My amplifier has an output impedance of 4Ω, but is connected with a BNC cable, which are usually 50Ω.
My custom antenna has an input impedance of 35Ω.
My signal frequency is 1860 kHz.
To maximize power in my antenna, should I create a matching network to make my source impedance 35Ω as well (I am afraid the off-axis inductance this creates will eat away more power from the antenna)? Or is it better to keep my source impedance low? And isn't the 50Ω cable messing things up in general?
Thanks for the help!
AI: isn't the 50Ω cable messing things up in general?
No, the important thing is the coax - it has a fixed 50 ohm characteristic impedance and therefore, to prevent reflections from the antenna (35 ohms), you should use an RF transformer to back-convert 35 ohms to 50 ohms. This then matches the antenna to 50 ohms.
A simple 1.2:1 step down RF transformer will do this because the square root of the impedance ratio is 1.195 and 1.2:1 is good enough. This transformer needs to be placed at the antenna end of the coax. The voltage step-down is towards the antenna.
So now, your transmitter will see 50 ohms and you can stop at this point. 12 turns to 10 turns seems nearly perfect at the antenna end.
However, if you truly want to maximize power transfer then you can step up (using another RF transformer at the amplifier end) the 4 ohm amplifier output to circa 50 ohms. The square root of the impedance ratio is 3.54 so a 10:35 ratio step up transformer would be good if you really wanted to push things. Of course you may be limited by power output and by legislation.
General idea: -
Transformer design needs care and I've estimated the number of turns based on good RF ferrite material and a typical pot-core. The devil, as always, is in the detail and, this design should be undertaken methodically so as to produce sufficient magnetization inductance in order to minimize unnecessary amplifier loading.
|
H: I2S audio interface - sync of MCLK and LRCLK signals
I plan to use IC AK4430, an I2S digital interface sound output chip, to be connecte to an ESP-07 Wifi module via 3 wires (BITclk, LRclk and DATA). But the IC also require an input signal that they call as MCLK (master clock).
AK4430 on Digikey: https://www.digikey.com/product-detail/en/AK4430ET/974-1017-1-ND/2333403/?itemSeq=329224867
AK4430 HTML datasheet: https://www.digikey.com/htmldatasheets/production/755129/0/0/1/ak4430.html
Page 9 of datasheet shows this:
The external clocks required to operate the AK4430 are MCLK, LRCK, and BICK. The master clock (MCLK) should be
synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master
clock is set to the appropriate frequency (Table 1).
The AK4430 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation
mode, and the analog output goes to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4430 is powered
up. After exiting reset following power-up, the AK4430 is not fully operational until MCLK, LRCK and BICK are input.
And also shows the following table also at page 9:
From the table, if I pick freqSampling/fs = 44.1 Khz and MCLK = 512*fs, then MCLK would be 22.5792 Mhz.
That 22.5792Mhz SMD 4-pin oscillator could be used: https://www.digikey.com/product-detail/en/KC2520Z22.5792C1KX00/1253-KC2520Z22.5792C1KX00CT-ND/11610678/?itemSeq=329226141
The question is that the text above (shown on page 9) states that "The master clock (MCLK) should be synchronized with LRCK". So, how can I achieve such synchronization?
This is the basic schematic of the IC:
Another simple question is about the type of audio amplifier that is required to connect to the analog output... it should be class A, B, AB, H?
AI: The master clock (MCLK) should be synchronized with LRCK, but the phase is not critical.
What this means is that MCLK and LRCK should be derived from the same clock source, so there is a constant number of MCLK cycles for each sample. For example at MCLK=512Fs you get 512 MCLK cycles per sample.
"Phase is not critical" means any amount of phase delay between MCLK and the other signals doesn't matter.
If they are derived from different clock sources, say MCLK from a 22.5792 Mhz oscillator, and whatever oscillator the ESP has for BCLK/LRCK, then both clocks won't be exactly synchronized. For example one oscillator could be a few ppm faster than the other. So instead of having 512 MCLK cycles per sample, you could have 512.01 or 511.99 MCLK cycles per sample. In this case it's hard to say what the DAC will do, it could just skip or duplicate samples once in a while, which shouldn't be audible, but it could also shift in the bits wrong and output garbage, or just decide to shut down.
Possible solutions:
ESP-07 doesn't have a MCLK output, so "feed MCLK from ESP-07 to the DAC" is out.
One solution is to use a clock oscillator of the correct frequency for the DAC chip and configure the DAC in Master mode so it outputs BCK/LRCK which feed into the corresponding inputs on the ESP to synchronize it to the DAC. Presumably then, the ESP I2S output will synchronize to this BCK/LRCK, and you can just feed the ESP's I2S data output to the DAC. However you need another DAC that supports master mode. Also you need two oscillators if you want to support 44.1/48k sample rates.
Another solution is to use an asynchronous sample rate converter chip which will convert the ESP's output to the DAC's clock domain. That's an extra chip though. You could also use a DAC which doesn't need a MCLK signal but instead reconstructs one from BCLK using an internal PLL.
I'd just use an ES9023 DAC with a local 25MHz oscillator. This chip sounds very good, it is simple to use, and it has an internal sample rate converter which will accept whatever you feed it and convert it to the local clock domain. You can probably find ready-made available modules with it.
Another simple question is about the type of audio amplifier that is required to connect to the analog output... it should be class A, B, AB, H?
That depends on your speakers, how many watts you want, etc. I'd just get a used vintage stereo "hi-fi" amp from the pawn shop and stick your WiFi ESP-based device inside.
EDIT:
If you only need 0.5W, then I assume you're going to use a small loudspeaker, so you could use a tiny and cheap Class-D amplifier with I2S input which does not require MCLK...
|
H: Wall supply Plug-in "noise"
We have had some issues with resonance overshoot from our 10W wall supply to a products LDO. The theory is that this overshoot will destroy the LDO once in a while rendering the product useless.
While investigating this I examined the difference between having the wall supply plugged in the wall first and then into the product and the other way around.
So when having the wall supply plugged into the product first, and then into the wall I will get this static on the supply input of the product (see first picture). Down to -5 V for a short time . Second picture shows how long before this small static event is before the voltage ramps up to normal on the product.
Is this problematic for an LDO with Absolute maximum input -0.3 - 6 V? Is there any way to mitigate this in the future?
AI: The first scope trace could be a measurement artifact:
When you plug in the wall supply, a large inrush current will charge the input caps. There will also be a current spike through the primary-to-secondary capacitance. This could cause some common mode noise which could be displayed by the scope as an actual signal. Also your probe's ground clip may pick up some of th magnetic field due to the capacitor charging current.
If the input supply voltage was probed on a capacitor, especially a ceramic capacitor which has low ESR and inductance, these high frequency +/- 5V oscillations would look suspicious.
Think about the current that would have to flow in a 100nF ceramic cap to get voltage to spike up by 5V in one scope pixel, say 200ns at 2µs/div. That's more than 2 Amps! Pretty unlikely.
I'd recommend not using the scope probe, and soldering a coax to the input ceramic cap instead, with a 50R resistor in series. Also place a ferrite sleeve on the coax, set the scope to 50R input impedance (make sure it can take the DC voltage), and measure again.
|
H: Powering sewing machine card
Hi, I received an electronic card to repair. The user says that it doesn't work and didn't say anything more, such as why it was broken or which part is not working.
So I want to plug in an energy source to the board to check capacitor's voltages, or if is there too much warming parts on board. But I dont have any experience on this kind of board, this is the first time that I get a sewing machine's electronic board.
this question is for general situations.
If I want to give energy to an electronic board, how should I do successfully? There is a 250V 6.3A fuse, and there are fuse varistors which are 220V rated. Also there is a GND point on board (first image) left up, at the side of varistor and a +33V point just below the fuse. There are lots of clues. How can I give energy to this board, reading correctly thoses clues?
AI: Since you asked for general situation advice, I will offer some general recommendations.
If your first impulse on troubleshooting an unknown board is "let's just apply power and see what happens", I think you should reconsider your approach. You don't know what the appropriate input actually is, what the expected outputs are, or if there is any sequencing or fail-safe circuitry needed to make the board do anything. I would start by first asking more questions from the person who supplied the board:
Which product did this board come from? (Manufacturer, model number, etc.)
Have them provide a picture of any labels on the device for clues about input requirements (voltage, frequency, etc.)
Ask them to describe the fault in more detail.
Contact the manufacturer and ask if they have any schematics or repair resources available. Alternately, scour the Internet and see if you can find this from any third-party sources.
Continue your reverse-engineering activities to understand the basic flow and sequencing of the circuit. Draw your own block diagram. Identify test points (which you have already done) and voltage rails (based on capacitor ratings and ICs connected to those rails)
Conduct a visual inspection of the board for components which look damaged; probe and measure before applying power.
Try powering DC rails by connecting a current-limited DC source to the rail. Slowly walk the voltage up and watch the current meter, gently relax the current limit and bring the rail up to the expected voltage if it is possible to do so.
Once you are confident that the DC rails are OK, identify which parts of the board are primary (mains-connected) so that you will not incidentally contact or probe any dangerous areas. I would use a small variac with a conservative fuse rating (equal or lower than the fuse in the product) and walk the AC voltage up slowly to see if any on-board power supplies are operating correctly. (I didn't see any transformers on this board so it's possible the entire assembly is mains-connected.)
It is quite likely that without the complete sewing machine, it will be impossible to diagnose everything fully so there may be some back-and-forth with this particular customer if they are unable or unwilling to send the machine.
|
H: Some confusions on a basic CMOS multivibrator question
This is a previous exam question, so I do have a solution already, I am not trying to make you solve my homework etc.
Few questions in my mind regarding this question above,
There is not a given information about initial capacitor voltage, so I assume it should be understood from the given informatin as "assume the MV is in steady-state for t<0". But I could not be sure how to relate capacitor voltage to steady state. Will I replace it with open circuit and then say that V2 has to be @ 9V so that the KCL satisfied at that node, then the gate on the right will outputs 0V, then the left one output 10V. Is this the approach I should follow?
Right after the trigger pulse applied, node V1 jumps to 0V, which results node V2 to jump -1V becuause the voltage across a capacitor cannot change instantaneously, right? If so, after this step, I am really having a hard time on how to find the curve for capacitor voltage, initially, it looks like node V2 is qt -1V, so there should be currents flowing towards node V2 both from ground and Vdd, however, this behaviour should change when V2 reaches 0V, after that, the only charging path will(should) be Vdd & R1. So the computations for the time it takes for V2 to reach 5V looks pretty complicated to me. However, in the solution of the question, it is taken such that the capacitor will charge up to 9V from -1V with a time constant of (R1//R2). This doesn't seem correct to me. How does it sound to you?
Thanks in advance.
update : While -1<=V2<=0 , there is a current flow from GND to V2 and to + terminal of the capacitor. However, once V2 reaches and passes 0V, now there should be the reverse, a current flow from V2 towards GND. This blows my mind.
AI: Yes u r right completely.
your first sentence is right. so what to do next...
The simplest way is to find an equivalent circuit that represents the Vdd, R1 and R2 circuit. It's so simple, in equivalent circuit we have a voltage source of 9 volt (because of resistor division), a equivalent R of 0.9K (1K parallel with 10K), a cap with an initial value. So, we have 3 components: a 9v voltage source in series with a 0.9K resistor and in series with a cap. The cap's initial value is -1v, its final value is 9v and its time-constant (RC) value is (cap*0.9Kohm). So, place them in the exponential charging equation of capacitor and calculate the time when the cap's voltage reaches 5v.
Note that the sentence "this behaviour should change when Vc reaches 0V" is totally wrong here because your circuit (in charging mode) is a pure linear circuit!!!
Generally, we can calculate the equivalent circuit like this: calculate two parameters V_open_circuit and I_short_circuit. Voc in this circuit is 9v (Vdd * R2/(R1+R2)). Isc = Vdd/R1. so the equivalent resistor would be Voc/Isc = 0.9K and the equivalent voltage source is Voc itself.
Let's evaluate and calculate my equivalent circuit with the real one. At (Vc = -1) the current into cap is (11v/1K + 1v/9K) which is equal to the equivalent circuit (10v/0.9K). At Vc=0 the current of cap is (Vdd/R1 + 0/R2) which is equivalent to (9v/0.9K)
|
H: Are there any real world examples of encoding data in EM polarization?
Data can be encoded by modulating the frequency, amplitude and phase. But I can't find any references for encoding data in the polarization of EM waves (either analog or digital). This is probably for a good reason which I do not understand. Are there any examples of such schemes?
AI: It certainly can be done, it just isn't very useful, except in certain situations.
For example, ham radio operators sometimes like to do experiments with reflecting signals off the moon (EME, or earth-moon-earth, a.k.a. "moonbounce"). It's useful to transmit with circular polarization, because the reflection comes back with the opposite polarization, which means that the receiving antenna is better at rejecting unwanted terrestrial reflections.
However, in the general case, different polarizations have different propagation characteristics, which makes it difficult to maintain coherency in terms of demodulating a useful payload at the receiving end.
|
H: Can signals be used directly in conditional statements in lieu of comparison to 0/1?
Can a signal (of type std_logic) be used directly as the condition in an 'if' statement? For example, can I write
if (A and not B) then
instead of
if (A = '1' and B = '0') then ?
I realize something wonky may happen if the signals take other values like 'Z', but aside from that sort of thing, is this syntactically valid? The first one seems much briefer, especially for more complicated logical expressions.
Addendum: What worries me is whether the argument of the "if" is of the right type, if that matters. I'm from a programming (C++) background, so I routinely use things like if( my_int ) instead of if( my_int != 0 ) where my_int is implicitly cast to a bool. Just wasn't sure if the same thing is really going on here. I presume the result of the VHDL comparison A = '1' is an abstract logical value ("true" or "false") and not some concrete std_logic value.
AI: Signals of type Boolean : yes of course.
And you can happily use boolean types for synthesis, making life simpler, especially in internal signals, cases where 'Z' and 'X' etc cannot happen.
Signals of type std_logic : yes in VHDL-2008 mode.
It's one of the additions I least like in VHDL-2008 because it implicitly equates '1' and TRUE, and '0' and FALSE. If this is combined with negative logic or active-low signals (as are often used for resets, RESET_N, imposed by external requirements) the result is an atrocious mess like
if RESET_N then
-- non-reset case
else
-- reset case
end if;
Even worse, sometimes the signal is active low but named RESET.
In such cases, please PLEASE please write out if RESET_N = '0' then longhand...
In other cases, use judgment whether the shorter implicit version, or the longer explicit version, will make more sense to the next guy. Both have their uses.
|
H: Resistive AC voltage divider and phase
I built myself a power monitor a few years ago that works and I was trying to simplify mine by cutting out an expensive and hard to find 12V ac:ac adapter. I am familiar with a voltage divider and it's operation makes perfect sense to me in the context of a DC circuit. Ie the voltage drop across elements is proportional to their resistance vs the series resistance. But I realized that I actually built a AC voltage divider (a 10:1 transformer with a voltage divider). I was surprised when I looked up an AC voltage divider and found it is exactly the same for resistive dividers.
In my head the voltage comes from one direction in an DC circuit. It starts high (we'll say 12V) and drops say 10V as it runs through the first resistor (10kohm) and drops the last 2 volts as it goes through the last resistor (2kohm). But in an AC circuit, as the phase goes past 180 degrees the voltage on the 2kohm side would now go to 12V (lets just talk absolute amplitude to keep it simple), so I would expect that it would drop 2V and the voltage divider to measure 10V now, and the last 10V to drop as it goes across the 10kohm resistor. The one on my power monitor makes sense to me because I add a DC bias which prevents it from ever changing directions, but none of the online resources I have seen indicate that that is necessary.
Can anyone explain to me why the direction of current flow doesn't matter for the AC voltage divider? I mean if I flip the polarity on a DC voltage divider, it makes a different, so why not for an AC divider? Or does it make a difference and I am just missing something in my search online, like they are only considering voltage at 90deg or something like that?
AI: Resistive voltage dividers divide voltage. It does not matter what the voltage is or does it change, it is always proportional to the instantaneous voltage. And AC voltage is nothing more than voltage than changes and if you stop the time at some instant you can view it as DC.
|
H: What's is yx8018b and what is it symbol?
I am trying to fix some solar lamps, that contain pretty much only a handful of electrical components:
A switch
a solar panel
a 1.2 V AAA batery
an LED
a resistor (inside its "home" it measures ca 45 mOhm, it's labeled in Red-brown-violet-Silver [210 MOhm?!])
and then a little black 4-legged thingy labeled
yx8018b av7n1
While I could find replacement parts under the part number "yx8018", I have no idea what the item is called and how to note it down in the accompanying sketch - an if there is a difference between XY8018 and YX8018B.
AI: Although I can't answer the details about the variations of the YX8018 (with or without a B suffix) it is a solar LED driver, similar to the YX8050 whose output waveform I captured in a previous answer.
The datasheet for the YX8018 shows a sample schematic like this:
The inductor (marked "L" in the schematic), required for the boost converter inside this IC, is what you have misidentified as a 270 MOhm resistor. In fact, it is a 220 µH inductor - that is why it measures as such a low resistance.
This additional photo supplied from comments, shows two of the inductors: The "loose" one on the left side of the photo shows the red, red, brown, silver colour bands more clearly than the one still soldered to the PCB on the right side:
Different inductor values are used to change the LED current, as described in the datasheet's table:
I have no idea what the item is called
Solar LED driver.
and how to note it down in the accompanying sketch
See the schematic sample above. There is no specific standardized symbol - so use a rectangle as shown with the part-number on it.
|
H: What kind of transformer is this?
What kind of transformer is this and how is it used?
I'm also confused about why there are only 3 wires. I don't see any other pins on it. Although on the opposite side, you use the number 4 on one side and RT on the other.
AI: That's an auto-transformer. It is used to step down from 120 V to 45.5 V but without isolation between the inputs and outputs.
simulate this circuit – Schematic created using CircuitLab
Figure 1. A poor drawing of an auto-transformer. In practice there is one coil with a tap-off point on it.
On a large auto-transformer the lower winding might be thicker than the upper as it will be carrying more current. For one this size the saving in copper cost might not be worth the trouble.
The transformer turns ratio applies to this type of transformer also so the number of turns on the lower half will be 45.5/120 times the total number of turns.
|
H: Measuring resistance with ohmmeter over resistor and capacitor in parallel
In "Teach Yourself Electricity and Electronics, 6th Ed." [Gibilisco] (2016) a test question reads as follows:
A DC ohmmeter will give us a correct reading for a component in isolation (not connected to anything else) if that component"
(a) contains inductance and resistance in series.
(b) contains capacitance and resistance in parallel.
(c) contains pure resistance.
(d) contains pure inductance.
(e) Any of the above.
The correct answer is claimed to be (e).
My question pertains to (b): Assuming a large capacitance inside the component, wouldn't it take some time before the correct reading could be obtained, since it would take some time for the voltage across the capacitance to creep asymptotically towards the voltage of the internal battery of the ohmmeter (during which time the ohm-reading would be too low, because of higher-than-final current through the internal ammeter of the ohmmeter)?
EDIT: When posing the question, I was unaware of the different ways of measuring resistance, e.g. keep voltage stable and measure current OR keep current stable and measure voltage, the LATTER being the preferred method in modern multi-meters. I naïvely assumed stable voltage.
With my question I was asking for confirmation that the resistance reading can take some time to settle to the actual value. This has been confirmed by the accepted answer to be the case, regardless of the type of ohmmeter employed. (With a large internal capacitance in the measured component and an ohmmeter using a small fixed current, presumably the measurement could take a LONG time to settle to the resistance value of the resistor.)
AI: Assuming a large capacitance inside the component, would it not be the case, that it could take some time before the correct reading could be obtained, since it would take some time for the voltage across the capacitance to creep asymptotically towards the voltage of the internal battery of the ohmmeter (during which time the ohm-reading would be too low, because of higher than final current through the internal ammeter of the ohmmeter)?
Yes, this is correct.
The time taken would depend on the test current and the capacitor value.
|
H: Source Resistor of JFET Source-Follower
I am designing a simple Buffer to get the voltage of a high-impedanze source to an ADC (60k Impedance).
For that I choosed an JFET in the source-follower configuration.
simulate this circuit – Schematic created using CircuitLab
To bias the gate to ground and keep the input-resistance high, there will be an >1Meg Gate-Risistor.
I am a little bit confused about how to select the Source-Risistor, because the Output-Voltage (Voltage at the source) should be nearly independend of the load. So it should not matter, if I am using a 1k or 100k resistor, does it?
Some resources say, with Rs, you bias the JFET.
Could someone please clarify this to me?
A second Question:
To get better linearity, I may use a current Source at the Source (biasing the Gate to Vcc/2 with a single supply-voltage)
What is the approach to choose a current for that?
Thanks for any advice
AI: Indeed, with \$R_S\$ you choose the DC operating point of the JFET. An n-type JFET will start conducting as soon as the voltage \$V_{GS}\$ between gate and source is higher than some negative pinch-off voltage \$V_P\$ that depends on the type of the transistor. From this point, the drain current will rise quadratically with \$V_{GS}\$,
\$I_D=I_{DSS} \left( 1-\frac{V_{GS}}{V_P}\right)^2 \$,
where \$I_{DSS}\$ is the drain current at \$V_{GS} =0\$. Therefore \$V_{GS}\$ is usually negative. Since the gate is at ground level (due to \$R_G\$), the source must be positive. This is done by \$R_S\$, since \$V_S = I_D\cdot R_S\$ and finally \$V_{GS} =-I_D\cdot R_S\$.
So \$I_D\$ depends on \$V_{GS} \$ and \$V_{GS}\$ depends on \$I_D\$ and on \$R_S\$. The value of \$R_S\$ for a given \$I_D\$ can be found either graphically or by solving the equation. Small changes in the transistor parameters (\$V_P\$, \$I_{DSS} \$) will not have a huge effect on \$I_D\$.
A simple recipe: Choose an \$I_D\$. For a source follower, a good starting point would be \$I_D\approx I_{DSS}/2\$. From the formula above (or from the characteristic curve of the transistor), determine \$V_{GS} \$. Finally, \$R_S=-\frac{V_{GS}}{I_D} \$ (remember that \$V_{GS} \$ will be negative).
However, with a source follower the gate is usually not set to 0 volts. Instead, a voltage divider is used to set the gate voltage so that the source terminal is at about half the supply voltage.
|
H: Can FPGA VGA be used as DAC?
Can a VGA output be used to output an analog signal?
I'm using an FPGA to program and control the VGA output.
I want to use it as a DAC to control an external circuit (I'll be doing PID control). Could I just stick individual wires into ports corresponding to certain colors and program those colors accordingly or is there a better/more efficient method?
My board is the Basys 3.
AI: For a better quality of producing RGB signals you could use 4,5 or 6 digital signal (FPGA pins) and use a resistor-network (as a DAC). Take a look at this schematic which is used in an FPGA evaluation board (ALINX-AX309) and check out how it produces the VGA signals:
https://github.com/alinxalinx/AX309/tree/master/SCH
And you can also produce an analog signal with PWM. It can be implemented by a counter and a comparator in FPGA. Then filter the output PWM signal simply by a RC filter to obtain a smooth analog signal.
|
H: Can't solve the math related to power factor improvement
Image source - Fundamentals of Electric Circuit by Alexander & Sadiku, Practice problem 11.15.
I tried to solve the math in the following way.
\begin{equation}
S_{old}=140000\angle cos^{-1}(0.85) = 119000+j73749.576\\
S_{new}=140000\angle cos^{-1}(1.00) = 140000+j0.00 \;\;\;\;\;\;\;\;\;\; \\
So, Q_c = 73749.576 \\
And,\; C=\frac{Q_c}{2\pi f {V_{RMS}} ^2} = \frac{73749.576}{2\pi 60 (110) ^2} = 0.0161675\;F
\end{equation}
Which is a wrong answer. Can anyone provide me the correct way?
AI: They tell you it is 140 kVAR, so you need to determine capacitance that will provide 140 kVAR.
$$X_C = \frac{110^2}{140,000}$$
From that you can easily calculate C.
|
H: Drive LED with open-drain active-low signal
I am planning on using an IC (https://datasheets.maximintegrated.com/en/ds/MAX38888.pdf) which has the following output pin:
It is an open-drain active-low backup indicator. The BKUPB is held low when the part is in backup mode. I would like an LED to light up when the IC is in backup mode.
I was wondering, is the following solution okay:
Do I need an additional resistor in series with the PMOS gate to limit current to the gate?
AI: Depending on BKUPB current capabilities you could just connect the LED cathode to the port pin and the anode to a current limiting resistor and then to 5V.
Updated schematic to show ~1.5mA draw with a 2.5kΩ resistor.
simulate this circuit – Schematic created using CircuitLab
Below is the other common way to do it using an P-Channel enhancement mode MOSFET , and then you don't have to worry about the current draw of your open collector pin.
simulate this circuit
|
H: Why did this triac driver resistor let the magic smoke out?
I hope the title is acceptable under this website rules but it is exactly what happened. I wired up this circuit that I thought I tested in the past multiple times, but I might have wired up slightly different. However the following schematic is an accurate description on what I had.
The optocoupler triac driver is for the sake of this experiment always kept "on". When this works it will be controlled by a microcontroller, but for now it's tied to Vcc. NOTE: No, I do not want to use a zero-crossing sensing driver. This circuit will be used in a way that will make that inherent, but that part is not the subject of my tests and I want to understand why this circuit blew up.
The load is an oven element that works with the typical 240VAC split phase common in North America. The power triac is a beefy BTA40 mounted on a big heatsink. Datasheet links below.
When I was about to close the breaker to power this circuit, resistor R4 immediately became white incandescent. However, I have tested a variation of this circuit successfully in the past. What is really going on?
R4 at 330R should guarantee that even at peak voltage (240*SQRT(2)) there is never more than one amp through the MOC3053 (Itsm max = 1A according to the datasheet). In reality, as also the datasheet says:
The power dissipation of this current limiting resistor and the triac driver is very small because the power triac carries the load current as soon as the current through driver and current limiting resistor reaches the trigger current of the power triac. The switching transition times for the driver is only one micro second and for power triacs typical four micro seconds.
However it looks like that in this configuration the poor resistor had to dissipate so much more than that.
Datasheets:
MOC3053, BTA40
EDIT: I was suggested to move the load, so I tried to put it "under" the triac; will this work?
AI: Your wiring is wrong- the optotriac should go from MT2 to the gate.
It doesn’t matter whether the load is on one side of the triac or the other, so long as the optotriac + resistor goes from MT2 to gate.
Either of the below is okay:
simulate this circuit – Schematic created using CircuitLab
|
H: Understanding Diode ROM
I read that the intersection of a row and column represents a bit, and if an intersection is linked with a diode the corresponding data output line goes low or 0. But why?
Take the following figure for example. An input of \$ A_2 A_1 A_0 = \{0, 0, 0\}\$ gives a 0 (LOW) out of a's NAND gate and 1 (HIGH) out of b-h's NAND gate. The low potential of a's NAND gate sinks all current in the circuit, and there will be four parallel currents from \$ 5V \$ voltage supply, each through \$ R_3, R_2, R_1, R_0 \$ into a's NAND gate. For \$ D3 \$ to be 1 (pulled HIGH), the impedance of a's NAND gate has to be significantly larger than \$ R_3 \$ keeping \$ D_3 \$ at a potential close to \$ 5V \$.
Current through \$ R_2 \$ will then get a diode voltage drop (e.g. -0.6V) before reaching a's NAND gate. Assuming all four pull-up resistors have the same value, then voltage difference between \$ D_3 \$ and \$ D_2 \$ is just that diode voltage drop (i.e. 5V vs. 4.4V), but a 4.4V will not get interpreted as a LOW (0). So instead of outputting 1011, I should get 1111.
Above is my interpretation which make sense to me, but it got to be wrong.
To output 1011, there has to be no current through \$ R_3, R_1, and R_0 \$, pulling \$ D_3, D_2, and D_0 \$ to HIGH (5V), leaving only current running through \$ R_2 \$ and the diode into a's NAND gate. The voltage drop of \$ R_2 \$ and the diode takes \$ D_2 \$ low. This has to be what's happening but nothing sense to me: a's NAND has the lowest potential in the circuit and sinks all current through all four pull-up resistors.
AI: There are no connections where the lines cross (there's no black dot to indicate a connection) so only D2 is pulled low. The others stay high, so the voltages are 5/0.7/5/5 = 1011.
The diodes are to prevent sneak paths as would occur if the diodes were replaced by shorts. Only a is low, so the other diodes (where present) are either unbiased or reverse biased. Only the one diode to D2 comes into play.
|
H: Connection a Low Amp wire to High Amp wire
Suppose 5 Amps of current runs from point A to C.(20V) I want to connect a thin wire(I believe not for more than 1Amp) to a point B in between A and C. Will the amps melt the wire where it is connected to 5 amps wire? The wire will only be powering 350 milliamps load.
AI: If the load only draws 350mA then that is what the wire will carry.
The potential problem arises that if the 5A circuit is fused at current that is much higher than the thin wire can handle without overheating, you could potentially have a fire or a burn if the thin wire becomes shorted. So generally it's "better" to keep the wires similar size or separately fuse any taps off of a bus bar or thick wire right where it is tapped off.
|
H: Multiple Switch Equation to NAND Only equation
I'm trying to convert a regular Boolean equation that has multiple inputs into a NAND only equation. My guess is that I'm supposed to convert using DeMorgan's law, but I'm not entirely sure how to do that. The equation I'm trying to convert is (A&~B)|(C&D).
I've created a logic circuit that implements the regular gates and its NAND equivalent:
I also have the diagrams on how a NAND gate is used to create difference gates, but still not quite sure how to convert it to an equation. I'm trying to create an equation I can implement in Vivado (if anyone has experience with that). Is there a Boolean symbol for NAND?
Any help and direction would be greatly appreciated. Thank you all so much.
AI: The commonly used boolean symbols in Digital Electronics are for AND, OR, Exclusive-OR, Exclusive-NOR and NOT operations. See Wikipedia: List of logic symbols.
The NAND operator symbol is Sheffer Stroke, which is uncommon in Digital Electronics.
You can convert a Boolean equation to NAND form by replacing each gate with it's NAND equivalent, but as you have seen some gates become redundant. Hence the algebraic method is preferred as it is shorter.
Taking the double complement as we know, does not modify the equation, because \$\overline{\bar{A}} = A \$.
As you mentioned in the question, you are supposed to convert the equation to NAND form using De Morgan's laws. Applying De Morgan's law is easier when you have an expression that is complemented i.e \$\overline{(some\_ expression)}\$.
But we can't just complement the expression once as that would be modifying it, so we take the double complement of the expression. This does not modify the expression and makes it easier to apply De Morgan's law.
We need to apply De Morgan's law to the inner negation operator of the expression. The outer negation operator is applied so that the equation won't be modified. And as shown in the below example, the outer negation operator will be the NAND gate at the output when the expression it operates on is the conjunction of outputs of other NAND operations.
To convert to NAND form, the method for small problems which can be solved manually:
Find the minimum sum-of-products form of the given expression.
Take the Double complement
Simplify it using De Morgan's laws till you get it in NAND form.
For your question, it takes 2 steps as it is already in the minimum sum-of-products form:
\$(\overline{\overline{{A}.\bar{B} + C.D}}) = \overline{\overline{A.\bar{B}}.\overline{C.D}}\$
The circuit implementation requires 4 NAND gates.
simulate this circuit – Schematic created using CircuitLab
|
H: Calculate voltage drop across Linear MOSFET in saturation region
Considering the below schematic, how is the voltage drop across the MOSFET calculated when it is operated in the saturation region? I am trying to calculate the power dissipated by the MOSFET so that I can choose an appropriate heat sink. RDS(on) is only listed for one V(gs) in the datasheet, but in this use case, the gate voltage will be varied in order to achieve a programable constant current through the MOSFET. For example, see the datasheet for IXTK90N25L2 which is designed to be used in linear mode. The "Input Admittance" graph in Fig. 7 shows the relationship of V(gs) and I(D) but there is no V(DS) listed.
EDIT: I think I might be misunderstanding what the "Output Characteristics" graph is showing. According to this article, that graph is showing the voltage drop. But I don't understand how that graph is being read. Can anyone explain that?
Based on this article, when in the saturation region, the drain current is related to the gate-source voltage and the threshold voltage and not RDS(on). Does this mean that the RDS(on) is always the same for all V(gs) that are above the threshold voltage? If that is true then the transistor in question would only dissipate 16.2W at its rated 90A (.18V=90A x 0.002 Ohm) but then why is it rated for P(D) = 960W?
After reviewing answers on this site (ie this one) related to MOSFET power ratings, they are all referring to switching losses which does not seem to be relevant here.
AI: The "Input Admittance" graph in Fig. 7 shows the relationship of V(gs)
and I(D) but there is no V(DS) listed.
\$V_{DS}\$ is held constant at 10 volts as per this statement: -
The symbol \$g_{fs}\$ (transconductance) is called input admittance in Fig. 7 but should be called transconductance. You'll get used to it! Anyway, the point I'm making is that the table above refers to transconductance (\$g_{fs}\$) and therefore \$V_{DS}\$ will also "be held" at 10 volts for the graphs.
I think I might be misunderstanding what the "Output Characteristics"
graph is showing. According to this article, that graph is showing the
voltage drop. But I don't understand how that graph is being read. Can
anyone explain that?
There are several gate-source voltage trajectories and when each gate-source voltage is applied, \$V_{DS}\$ is adjusted and drain current is recorded. The vertical line corresponding to \$V_{DS}\$ = 10 volts yields the admittance graph in your first question above.
Does this mean that the RDS(on) is always the same for all V(gs) that
are above the threshold voltage?
RDS(on) is irrelevant for your particular application but, if you want an answer, it's the inverse-slope of the above trajectories when drain current is 0.5 amps (as per the statement in the top picture). The slop is I/V therefore the inverse is V/I which is resistance.
why is it rated for P(D) = 960W?
If you look at the safe operating area graph you can see that it is capable of handling a power of 960 watts if the case temperature is held at 25 degC (harder than you think): -
Approximate estimations: -
red circle = 250 volts x 4 amps = 1000 watts
purple circle = 100 volts x 10 amps = 1000 watts
blue circle = 30 volts x 30 amps = 900 watts
green circle = 10 volts x 100 amps = 1000 watts
Never get close to these levels in practice except for very short periods of time.
PS, I'm glad to see that you took on board some of my simplified circuit recommendations: -
But you really do need to use the RC network around the op-amp!
|
H: Why is my IRL540 slow to turn off?
I'm trying to switch 12V with an IRL540 from a 5V micro. Right now I have it a 1k resistor between 12V and the drain, the source to ground, and the gate has a 100kHz 5V square wave on it. That's the whole circuit, this was just to validate the switching.
If I go faster than this it starts to not even reach 12V before I turn on the FET and pull it down again.
As we can see from the capture there's quite a lag in rise time, I suspect by the charge needing to return to the drain of the FET. But should it really take this long? It's at least an order of magnitude longer than what's specified in the data sheet (given that's with Vdd at 50V, but this seems very slow). My square wave seems fine. What can I do to fix this?
AI: The IRL540 has a parasitic capacitor between drain and source so, when you "turn off" the MOSFET, that capacitor (\$C_{OSS}\$) takes time to charge via the 1 kohm drain pull-up resistor. To add a little misery/complication, \$C_{OSS}\$ changes with \$V_{DS}\$ as per this graph: -
So, when you initially turn-off the gate voltage (\$V_{GS}\$), \$V_{DS}\$ starts at 0 volts and \$C_{OSS}\$ is about 2200 pF - this has an RC time-constant of 2.2 μs (1 kohm pull-up) and so the output rises relatively slowly initially. As \$V_{DS}\$ rises to (say) 3 volts, \$C_{OSS}\$ drops to around 1400 pF and things start to speed up but, it's a law of diminishing returns when charging a capacitor from a resistor and, despite \$C_{OSS}\$ falling to about 800 pF when \$V_{DS}\$ is 10 volts, there is still an overall time period of several micro seconds involved.
If you used a 100 ohm load you would see \$C_{OSS}\$ charge much more quickly.
Even though \$C_{ISS}\$ (gate capacitance) is circa twice the value of \$C_{OSS}\$, I suspect that your gate driving impedance is no more than 50 ohms therefore, \$C_{ISS}\$ isn't a significant issue. Its effect will be about ten times less than a 1 kohm drain resistor and \$C_{OSS}\$.
|
H: breakpoints in baremetal code for arm stm32
I am writing a simple baremetal code for STM32. I wrote the linker and the startup code similar to this . My understanding is that the .text section will be placed in the flash memory of the controller.
Question:
In such a case, it is not possible to use software breakpoints right? From what I've read sw bp replace in memory the optocode with the break optcode (and keep the real optocode in some table, etc. ) in order to halt the processor. This cannot be done on non-writable memories like flash, where my code is, and hence where the program counter points to.
AI: Your understanding of software breakpoints is basically correct: the code is modified, i.e. a breakpoint instruction is inserted in place of the real instruction and the real instruction is saved somewhere else. The specific technique depends on the debugger, CPU and operating system.
Few debuggers are capable of applying software breakpoints in MCUs with the code residing in flash memory. But since flash memory can be changed (after all you upload your code to it), sophisticated debuggers can still use them.
One of them is SEGGER's J-Link (at least certain versions). See their Unlimited Flash Breakpoints feature for more information. They don't give away all the details of the implementation though.
So with the right debugger, you can still use software breakpoints in your bare metal project.
|
H: Connecting Wattmeter in Proteus
I want to check the power across a device in Proteus. But I am unable to understand how to connect Wattmeter pins to the circuit. Please Help me to understand this or suggest any other method to calculate power.
Thanks
AI: Wattmeter has a voltmeter and an ammeter. You need to connect the voltage coil across the load and current coil in series with the load.
If you double click on the wattmeter, it will show you options for seeing real/reactive/complex power.
|
H: Calculate lifespan of BLE ESP-32 module
I have purchased an ESP-32 BLE module. I have programmed it to turn on to broadcast a Bluetooth text to my phone and then enter the deep sleep mode. Then continue this loop.
When the Bluetooth text code it been to run the current it pulls is around 150mA. Then the module enters the deep sleep mode for 15 seconds at which time the module now pulls only 10mA.
I want to know if I ran it of lithium battery like the 18650 with a capacity of 2600mAH, how long will the battery last?
Please note I know how to calculate the lifespan of the battery it is just the current pulled by the device divided by the capacity of the battery. But how is it done when the current is not constant but changes between 'two current states' i.e. 150mA for 2secs then 10mA for 15secs and then loops again?
AI: But how is it done when the current is not constant but changes
between 'two current states' i.e. 150mA for 2secs then 10mA for 15secs
and then loops again?
The average current taken is: -
$$ 10 \text{ mA} + \dfrac{140 \text{ mA} \times 2\text{ seconds}}{2\text{ seconds}+15\text{ seconds}} = 26.5 \text{ mA}$$
That should be the current used.
Please note I know how to calculate the lifespan of the battery it is
just the current pulled by the device divided by the capacity of the
battery.
That assumes a fully charged battery discharged to a voltage level that may be below the minimum operating voltage for the blue tooth module so, you need to be aware of this and make plans accordingly. Maybe use a buck-boost converter to extract the maximum range. You should also consider that charging a lithium battery to its full level repeatedly may not give the best lifetime for said battery.
|
H: Need help identifying this little chip
So, I was changing some thermal material on my Sony A5100 camera, but somehow must've damaged one of the chips (below). Right now, the LCD display has a slight green tint to it.
I swapped an LCD screen for a new one, but the green tint remains (the video recorded is 100% fine.)
I'm assuming it's something having to do with this damaged chip since all 7 of the other ones that are near it are close to the LCD flex connector (shown below).
Can someone help me identify this chip? Also, how difficult would it be to solder a new one on the motherboard?
(Also it seems that this particular chip doesn't have connections to it on PCB like the rest of the chips? The wires go around it — if that helps with anything).
Thanks in advance!
AI: That's not a chip but a missing resistor network. Most likely identical to the ones near it.
|
H: How do I measure the reactive power of a single phase system?
In books and various websites, I have seen that the reactive power is measured using two wattmeter method. This method is applicable to a balanced three-phase system.
But at home, just a single phase is supplied. And we use different types of load. For example water pumps, electric fans, LED, etc. Is there any way to find the value of the imaginary power? The load impedance is also unknown. (As it varies time to time)
AI: Measure the real power and also calculate the apparent power from V and I (RMS values) then, use Pythagoras to compute the other side of the triangle (the so-called reactive power): -
|
H: Making mod-12 counter using ic7492
There is this exercise in my book said to make a mod 6, mod 4, mod 3, mod 12 counter using 7492. I can do mod 6, 4, and 3 but there is a problem when doing mod 12.
The circuit counts to 5 then skip to 8, how can I fix this problem?
AI: In the datasheet of the 7492 we can easily confirm that the mod12 counter has 12 different states but the codes do not match a binary counter.
|
H: How can I order a custom IC?
I'm new to IC design and just wondering if it possible to order IC production if you have all necessary design files (like RTL design, chip layout from Cadence for example, etc.)
If it is then what are these companies and what is the approximate cost (for a relatively small IC like for example an ethernet PHY?)
\$ \ \ \ \$
AI: The short answer to ‘how’: contact fab vendors and describe what your requirements are to figure out what services you will need. They will walk you through the process and identify your costs for budgeting.
Who are these companies? The best-known wafer fabs are TSMC and GlobalFoundries. Samsung also offers this service. There are others that specialize in smaller wafers/older processes, like SMIC in China.
A lower-cost way to do that is to put your die on a ‘shuttle’ - a multi-project wafer - to get some sample chips for testing. The majors provide this service, as well as smaller outfits like Tower Semiconductor, UMC, and others.
Fab companies provide various levels of service depending on your needs and how much money you have to spend. Unsurprisingly, part of the process of engaging a multinational like TSMC is qualifying your business. Not only will this determine if they will take your order, but your pricing and delivery as well.
In your case doing your first ASIC you might need to work with a third-party provider who can do all the back-end work for you vs. working directly with a fab. Fabs can identify appropriate partners who do that service. I've worked with several; a well-known one is Socionext.
What’s it going to cost? The main up-front cost is the mask set. Three factors influence this: die size, number of layers, and process node. For a small, mixed-signal chip like an Ethernet PHY, it could use an older process like 180 or 120nm. Ballpark for such a mask set would be about $75-150k.
The next fixed expense is test fixtures and test development. This can run to multiple tens of thousands. Add to that fixtures for accelerated-life and ESD/latchup testing.
You must also do a package. Even if you choose a standard type, it needs to be laid out with an appropriate bonding scheme for your die.
Your Ethernet PHY example is somewhat more complicated, as it includes a mixed-signal hard macro block, that is, the PHY itself. Most people license these things from third parties, for good reason: designing a PHY is a specialty skill, and is considerably more expensive to qualify in silicon than a logic block. If you intend to design your own PHY, expect needing access to some expensive front-end-design tools, and later, access to expensive test gear to qualify your PHY, and hiring an expert to develop and run your tests.
There’s other expenses I’m certainly missing here but you get the point: expect up-front costs in the multiple hundreds of thousands even before you get your first packaged part.
Different companies can negotiate pricing. In one model, they can bury some of the fixed expense by increasing the cost of the delivered IC, but they will pressure you to take agreed-upon quantities.
Finally, if your design is of good quality with unique differentiation, you could possibly sell or license it to an existing company in that market space and defray some of your costs. But for it to have value, it needs to be proven in silicon.
|
H: Audio ADC - grounding problem
I searched through the internet but couldn't find an answer to my question. Maybe I just don't know what to search for.
I want to convert an audio signal coming from a stage box from analog to digital. I found some integrated circuits which seem to be suited just for that (like this one).
But here is the problem. The audio signal coming from the stage box is referenced to the wall plug ground. Which means that the audio signal oscillates between negative and positive voltages. But the analog-digital converter I linked works only for positive input voltages. I found that there are also some ADCs (like this one) which seem to be able to handle also negative voltages. But is it the best solution? Is there some way to "lift" the audio signal potential so that it oscillates only in positive voltage range?
Thank you in advance for all your suggestions.
AI: The PCM1803A shows you how to couple audio signals (see red box below): -
All you have to do is ensure the signal doesn't exceed 3 volts p-p or you will clip the digital conversion. Also tied in with this are strict requirements to ensure that excessive voltages are not present at the input that could damage the ADC but, this is common to any type of ADC.
So, you need to match and condition any audio signal to suit the ADC. If the source is differential or balanced then you need an op-amp circuit to convert it to single ended and that op-amp circuit can give you the protection to the PCM chip. You might also need TVS diodes to protect the op-amp but that's a necessary evil that any circuit has to cope with.
Regards WiFi transmission - you may not be aware that it may not produce a contiguous data-stream and that there may be a significant delay required at the receiving end in order to join things up for audio reconstruction.
|
H: How can I overcome the distortion using in this circuit by using same products as we see in picture ? Or we can use 2n700 series, 3906 and 3904 bjts
Or we can use 2n700 series, 3906 and 3904 bjts. My aim is 10W, gain 100-1000 (adjustable), 50hz-20khz amplifier by using this basic components.
AI: You can try something like this: -
It will certainly reduce cross over distortion. Try it in your simulator.
However, you have another problem - either your circuit or my modified circuit can only use a maximum voltage of +/- 18 volts for the LM358 (in the real world) and this means that the maximum peak-to-peak signal it can produce at node Vf is around 30 volts peak-to-peak and, given that your output stage is a push-pull emitter follower, the maximum output voltage will also be 30 volts peak-to-peak.
Given also that your output stage has +/- 50 volt rails, you may be expecting some form of magic to make your output signal bigger than 30 volts peak-to-peak. That magic won't happen. Also, you'll be lucky if the LM358 can drive anything like the current needed into the bases of the output pair when connected to an 8 ohm load.
|
H: Assymmetrical vs symmetrical voltage blocking
I'm studing power electronics.
There is property for BJT, GTO, IGBT which says:
"blocks voltage symmetricaly" or "blocks voltage asymmetricaly"
What does it mean?
What is the difference between each?
AI: It is more accurately described as current blocking, not voltage blocking since voltage does not flow. Current does.
Asymmetrical current blocking means that it can only block current in one direction but in the other direction it can't block it and the current goes straight through. These devices can conduct symmetrically (in both directions). Kind of like a switch with a diode in parallel with it (like the parasitic anti-parallel body diode in most discrete MOSFETs).
So for something like MOSFETs to block AC you need two of them in series back-to-back so each one blocks current flowing in one direction.
Note that this is different than asymmetrical current conduction. This is when a device can only conduct it in one direction but might be able to block current symmetrically (in both directions). Kind of like a switch with a diode in series with it.
Thyristors are an example of this. For thyristors to conduct AC, you need to have two of them anti-parallel so that current passing in each direction goes through a different thyristor since current can't pass both ways through the same thyristor.
An ideal switch or relay has symmetrical blocking and conduction. A diode has assymetrical conduction and blocking and such behaviour makes a third control terminal useless since there is no switching state that can be controlled independently.
|
H: Altium Designer : How to make a custom Top paste for D2PAK pad
I know my way around altium designer but i am not finding a good way to make openings in the solder paste layer for the tab pad of D2pak .
This is what i want :
Altium only allows me to make the paste increase or decrease in size , but it stays a square , so i cannot make multiple smaller squares as the recommended Stencil.
best regards
AI: Decrease the size of the automatically generated paste feature to zero (by making the paste mask expansion a negative number).
Then add whatever shapes you want to the paste mask layer using the Place Region command.
|
H: DC Power Supply: Turns Ratio Calculation
I am an electronics newbie looking to broaden my horizons, so I'm going through The Great Courses's Understanding Modern Electronics course. In Lecture 4, they give a project in which the goal is to simulate a DC power supply.
The supply should step-down a 120-volt rms, 60 hertz AC signal to a 5-volt DC signal. I got the correct schematic, but I came up with a different turns ratio than the one given in the project solution. The solution gives a turns ratio of 28:1, but I calculate a turns ratio of 21:1 by solving: $$5.7V=\frac{N_2}{N_1}(120V)$$
where 5.7 volts is the voltage before the voltage drop across the diode.
I simulated the circuit in LTspice XVIII, and it confirms that the turns ratio should be approximately 28:1, not 21:1. The closest guess I have as to why this would be would be that I ought to use a value of 4.3 volts instead of 5.7 volts, which corresponds to 5 volts dropping across the diode. However, this conclusion is contradicted by my simulation below, which has the expected value of 5V, not 4.3V, across the load.
How can I correctly calculate the turns ratio for my transformer?
AI: The answer is in your simulation voltage source. The 120VAC is quoted as RMS which is \$1\over\sqrt{2}\$ times the peak value, so the simulation uses 170V as the peak voltage (340Vp-p) 60Hz.
That's what comes out of the wall in North America.
So use the peak voltage in your calculation (169.7 or 170V) rather than 120V.
In general, if you see a power source given in volts AC it will usually mean RMS unless otherwise specified. For a sine wave the ratio of peak to RMS is \$\sqrt{2}\$. For other waveforms it generally differs.
|
H: 78L24 outputs high voltage >24v - Harman Kardon AVR 151
I'm trying to repair my broken Harman Kardon AVR151.
Looking at the SMPS schematic, to my very limited knowledge I do not understand,
The 78L24 is a high side 24V regulator.
Why does the schematic say tge output is 38V?
Is the circuitry show below designed such a way to output a higher voltage?
When measuring I get a reading about 35V at VKK.
78L24 (actual part No. CVIL78L24AB)
Harman Kardon AVR 151/230C Service Manual page 123
AI: The zener voltage ends up being added to the voltage stamped on the part, so 12V+24V = 36V.
Pin 2 of the 78L24 acts as an almost constant current source of about 4.5mA, which flows through Zener diode D929 and therefore 12V will appear across that. The 78L24 provides 24V on pin 1 relative to pin 2, which is thus 12V higher than ground.
As it happens, Izt for the zener is 5mA, close enough to the operating current.
|
H: Average input current in forward converter
I am trying to understand how to calculate the average input current of a typical forward converter. If the converter has negligible magnetizing current, a large inductance and a turns ration of n1:n2:n3, based on my understanding, the input current would be:
Ig = D*Iinductor * n3/n1
But this does not seem to be correct.
Any help/pointer will be much appreciated.
Thanks
AI: In a forward converter, the primary current is the sum of the magnetizing current \$I_{mag}\$ and the reflected inductor current \$I_L\$ which, on average, is the output current \$I_{out}\$ scaled by the transformer turns ratio 1:N. This current circulates in the primary side during the on-time duration. The below drawing shows a typical waveform excerpted from a report I posted on the over-power phenomenon in the forward converter:
If we neglect the magnetizing current circulation, it is possible to approximate the triangular waveform into a square waveform and easily calculate the average input current. Average calculations are about area determination. Look at the below picture to see how to simply determine the average value by stretching the original area along the switching cycle:
Assume you have a forward converter delivering 5 V 10 A with a transformer turns ratio 1:N=1:0.16. The input voltage is 100 V and the duty ratio is 31.3% (neglecting all the drops). The below Mathcad sheet shows the input current to be, on average, 502 mA:
|
H: How do capacitors in series work?
If capacitors are connected in series with a vltg source, then how would each plates get the polarity? For a single capacitor, the electrons from one plate are pumped by the source towards the other side of the plate, but for series connection how would the flow of electrons be in between the capacitors (i.e. for the inner plates of the capacitors). Say, if three capacitors are connected in series, how would the middle capacitor gets charged? Would current exist between each capacitors?
AI: Since we are on Electrical Engineering, let us consider workings in your serial network Vsource+=Capacitor1=...=CapacitorN=Vsource- in the circuit-analysis context, the Vsource+ and Vsource- are poles of the DC voltage source.
Let N=1, i.e., a single capacitor is connected to a voltage source. To be able to speak of transient process of charging the capacitor, we have to add to our circuit one more serial component, a switch. So, we have a serial network Vsource+=Switch=Capacitor=Vsource-. When performing transient analysis, we must specify initial conditions in a network. Let it be zero initial current (switch is OFF) and zero voltage across the capacitor. Closing the switch in the moment t=0 initiates infinite current in the network that charges the capacitor with the charge Q=V·C. In reality, the resistances and inductances of network components limit the current and may result in decaying oscillations, but the circuit "steady state" is the capacitor with the voltage equal to DC source voltage. Notice that if the initial voltage of the capacitor is equal to a DC source voltage, closing the switch would not result in current surge and any transient process in the circuit.
For a network of Vsrc+=Switch=C1=...=CN=Vsrc- (i.e., multiple serially connected capacitors), if the sum of voltages across C1, ..., CN is equal to the Vsrc voltage, closing the switch does not start the current in the network. The initial voltages across C1, ..., CN can be assigned any values, assuming these values add to the Vsrc voltage, and closing the switch does not change these values. I won't bore you with the truth ((C) Homer Simpson), but this fact gives you a hint that the problem of finding steady state in serial network Vsrc+=Switch=C1...=CN=Vsrc- with ideal components does not have a unique solution. To arrive at a sensible result, you have to consider non-idealities of circuit components.
Examination of a serial network of multiple capacitors and a current source (instead of voltage source) will give more elucidating insight into workings of electrical circuits -- how Kirchhoff's laws and charge conservation agree with apparent discontinuity of circuit between capacitor plates.
We have a network with a switch Sw1. The switch Sw1 either connects a network branch with serially connected capacitors to the current source I1 or disconnects this branch while short-circuiting the current source. The current source must be connected to some load (Kirchhoff's nodal rule at current source poles requires it!)
simulate this circuit – Schematic created using CircuitLab
Initial conditions: before t=0, the switch diverts the current away from the capacitor branch; the voltages across each of capacitors is zero. At t=0, switch flips to the capacitor branch side. Current I1 flows thru each of capacitors C1, C2, C3. How it can be, knowing that capacitors plates are isolated form each other in capacitors and charge carriers cannot be transported thru dielectric medium? The seeming current path discontinuity at the gap of conductive media inside capacitors, how can we reconcile it with Kirchhoff's nodal rule?
James Clerk Maxwell considered a problem of the sort when building classical electromagnetism theory. He solved it with the concept of displacement current, proportional to the rate of change of electric field.
Constant current from the current source flows in a capacitor and charges the capacitor plates. Electric field linearly increases with time; in a medium between plates this increase produces constant displacement current. The total current at each point is the sum of charge carrier current plus displacement current. In wires, we have charge carrier current, in dielectric we have displacement current, and Kirchhoff's law can be satisfied.
The solution for the transient process in a serial network of three capacitors and a current source with zero initial voltages across capacitors:
V_c1 = I1*t/C1; V_c2 = I1*t/C2; v_c3 = I1*t/C3.
|
H: Node voltage equation with weird solutions
I recently had an exam with the following multiple choice problem:
Consider the circuit below:
The node voltage equation for node A is which of the following?:
\$ \frac{V_A-kV_a}{R_1}+ \frac{V_A-V_3}{R_2} + \frac{V_A-V_B}{R_6} = 0 \$
\$ \frac{V_A+kV_A}{R_1} + \frac{V_A-V_3}{R_2} + \frac{V_A-V_B}{R_6} = 0 \$
\$ \frac{V_A-kV_A}{R_1} + \frac{V_A+V_3}{R_2} + \frac{V_A+V_B}{R_6} = 0 \$
\$ \frac{V_A+kV_A}{R_1} + \frac{V_A+V_3}{R_2} + \frac{V_A+V_B}{R_6} = 0 \$
\$ \frac{2V_A}{R_1} + \frac{V_A+V_3}{R_2} + \frac{V_A+V_B}{R_6} = 0\$
\$ \frac{V_A-V_3}{R_2} + \frac{V_A-V_B}{R_6} = 0\$
My attempt
This is how I would make the node voltage equation for node A:
\$ \frac{V_A}{R_1} + \frac{V_A-V_3}{R_2} + \frac{V_A-V_B}{R_6} + ki_1 = 0 \$
But as you can see, it doesn't match any of the options above and I can't figure out how I'm supposed to reach on of those solutions.
Can somebody help me out?
AI: A tricky case.
V3=(I1-I2)R3. Va=-(I1)R1. With these you can fade the controlled current source from your equation.
|
H: Switch individual MOSFETs connected across lithium-ion cell for passive balancing
I am working on a passive cell balancing circuit using N-MOSFET. The cell voltage will be monitored by the micro-controller and it can also generate corresponding logic level signal according to over charge for a particular cell. I want to build a control circuit that can individually switch the N-MOSFET connected in series so that the a particular cell which is overcharged is discharged via resistor and the overcharge cell is balanced. How can I build a drive circuit for the N-MOSFET?
AI: The important thing to remember about this arrangement is that each FET gate switching voltage is (e.g. 0V = OFF, 10V = ON : 10V being right for most MOSFETs) ... but relative to its own source voltage.
So for Q1. source = 3 * Vcell, gate = source + 0 (off) or source + 10V (on).
Your task is to generate each such individual gate voltage.
There are many ways to do this but the simplest is to use a chip designed for the job as Tomas suggests.
|
H: STEP7 MICROWIN PLC Ladder Diagram
I draw like the first figure in the program, but when I save the program it automatically becomes the second shape. Do the two mean the same thing?
AI: Yes, of course.
The ladder diagram is a representation of the logic in an electrical diagram format. In relay logic the two circuits are equivalent.
See if you can convert it to STL (statement list) and understand the logic being executed by the PLC. Doing this will help you appreciate the sequence of instructions and their execution order by the controller.
|
H: how bits are still synchronized in asynchronous transmission?
I was reading a textbook which syas:
In asynchronous transmission, we send 1 start bit (0) at the beginning and 1 or more
stop bits (1s) at the end of each byte. There may be a gap between bytes.Asynchronous here means “asynchronous at the byte level,” but the bits are still synchronized; their durations are the same.
I am a little bit confused here, what does bits are still synchronized mean? how does bits gets synchronized and whom those bits gets synchronized to?
AI: I find that textbook description very confusing.
The sender of the data is generating a clock which determines where the edges of the bits are.
The receiver generates its own clock which determines, in simple terms, when we sample the data stream to get the correct bit values. This clock will not be synchronised with the senders clock, even if it starts off synchronised the frequency will be a little off and it will drift over time.
So the receiver re-synchronises its clock every byte by sensing the edge of the start bit. This means that the bits in a byte are synchronised and they are synchronised to the start bit.
|
H: the output in buck converter multi sim 14 is too low
it is required to use UC3842 to make a Buck converter that has 68V input and 29 output. i did the calculations for the buck circuit however not for the UC3842. i dont know how to calculate it. i been playing with its values for a while , the max i got was 9.8 volt. any help would be great. best help is telling me how to calculate these values or just telling me the values .
AI: it is required to use UC3842 to make a Buck converter that has 68V
input and 29 output.
Read the "featured" data sheet: -
Your supply is 68 volts and it will blow the back off the device (and probably the front). Also, it is intended only for low power buck operations without a transistor but, even if it could support an output transistor (for buck operations), using an N channel MOSFET as a source follower is missing the point entirely.
|
H: Why do I get such high values when calculating the power dissipation of MOSFET in boost-converter circuit?
I'm a hobbist interested in electronics so I don't have any "professional" training on that.
Currently I'm trying to design a boost converter and now I'm stuck at some calculations.
I wonder if it's possible to calculate how much the mosfet is going to heat up. I'm using two inductors in series which add up to 134uH and an IRFP460 as the mosfet. The converter runs on 12v and is driven at 4.7KHz with 78.38% duty cycle.
simulate this circuit – Schematic created using CircuitLab
My first idea was to calculate the mean resistance of the inductor which I did by calculating the ripple current through the inductor and dividing it by two:
$$\Delta I_{L} = \frac{V_{In} * D}{f_{s} * L} = \frac{12v * 0.7838}{4700 * 0.000134H} = 14.93A$$
$$I_{mean} = \frac{\Delta I_{L}}{2} = \frac{14.93A}{2} = 7.465A$$
$$R_{mean} = \frac{V_{in}}{I_{mean}} = \frac{12v}{7.465A} = 1.608Ohms$$
Then I proceeded to look up the RDS(on) of the mosfet which is 0.27Ohms so when the mosfet is on the total resistance is: 0.27Ohms + 1.608Ohms = 1.878Ohms
So there should be 6.39A flowing through the mosfet and thus 76.68W right? (I = 12v/1.878Ohms and P = 12v*6.39A)
The RthJA (Max. junction to Ambient) of the IRFP460 is 40°C/W so at 76.68W it is 40°C/W * 76.68W = 3067C°!!! This can't be correct that's why I'm asking what I'm doing wrong...
AI: I wonder if it's possible to calculate how much the mosfet is going to
heat up
14.93 amps is the correct figure for the DCM peak inductor current but then your calculations go wrong. You cannot calculate the resistance of the inductor that way but, it's pointless anyway - you are trying to find the MOSFET power dissipation and so the resistance of the inductor is irrelevant.
Use the red waveform above and calculate the power dissipated in the MOSFET's conduction period (\$D\cdot T_{SW}\$). Then average that power over one full cycle (\$T_{SW}\$). That's how much heat will be generated by the MOSFET.
What you will find is that if the MOSFET waveform were a continuous saw-tooth waveform then the RMS current is: -
$$\dfrac{I_P}{\sqrt3}$$
And the power would therefore be: -
$$\dfrac{I_P^2\cdot R_{DS(ON)}}{3} = 19.32 \text{ watts}$$
But this power is only dissipated for 78.38% of the time hence the real power dissipated by the MOSFET is 15.14 watts.
I assumed 0.26 ohms for \$R_{DS(ON)}\$ in the above calculation because the gate drive voltage might be 12 volts instead of the 10 volt figure in the data sheet. I would also highly recommend that a device with significantly smaller on-resistance be used because the IRFP460 is pretty shabby in this respect.
Calculating RMS of a voltage or current triangle or saw-tooth waveform.
|
H: Direction of the main beam of an antenna
How can I find direction of the main beam of an antenna if antenna has radiation intensity as following?
$$U=[\dfrac{sin(5\pi cos\theta)}{10sin(\pi cos(\theta/2))}]^2$$
Where
$$0<\theta<\pi$$
My first trial is to find the places where derivatives equal to zero. But the results also give places of the nulls. So, how should I distinguish themain beam between the all nulls (zeros) and sidelobe peaks (local maximas)?
AI: But the results also give places of the nulls. So, how should I
distinguish themain beam between the all nulls (zeros) and sidelobe
peaks (local maximas)?
Use your favourite spreadsheet and produce a graph then you get all your information together. The formula is not hard to use in (say) excel.
|
H: Relay pins too close on PCB by design?
I'm designing an intermittent wiper motor controller to be fitted on a classic car.
As I'm selecting components, I came around this relay that seems to be fitting my needs (PCB mount, automotive, high current).
When looking at the PCB layout, I find pin 3 and 5 way too close to each other to allow for drilling plus some copper around the holes for soldering.
This makes me think I can't use this relay as I need wide copper path for the current demand (20A). I'm not familiar with relays, am I missing something ? I find it strange that it is designed that way.
AI: If you use the recommended 2.1mm holes (in my experience the recommended sizes tend to be pretty sloppy and designed for ease of automated assembly rather than being optimal in other ways) then you can have pads with annular ring 0.36mm (14 mils, quite acceptable) and space 0.36mm. Then you can apply traces as so:
|
H: Semaphore in FreeRTOS doesn’t work
I am a newbie to freeRTOS and I was trying to learn about semaphores,I am using ATmega32a microcontroller, the plan was to create 3 tasks each is blinking the same led for some time with different frequencies the result was the led is just on forever.
so I canceled 2 tasks and kept only one task to catch the problem and the led is just on forever again.
I used the debugger and what happens is that it never continue the loop of for loop it toggles the bit and then delay and then toggle again and then go out to check the semaphore and repeat, this is very strange behavior.
but that's in the debugger, in reality, it never toggles it's on forever.
can you help me?
#include <avr/io.h>
/* FreeRTOS files. */
#include "FreeRTOS.h"
#include "task.h"
#include "croutine.h"
#include "FreeRTOSConfig.h"
#include "semphr.h"
#include <avr/interrupt.h>
/* Define all the tasks */
static void ledBlinkingtask1(void* pvParameters);
xSemaphoreHandle MySemaphore = 0;
int main(void) {
DDRB=0xff;
/* Call FreeRTOS APIs to create tasks, all tasks has the same priority "1" with the
same stack size*/
xTaskCreate(ledBlinkingtask1,"LED1",
configMINIMAL_STACK_SIZE, NULL, 1, NULL );
// Start the RTOS kernel
vTaskStartScheduler();
return 0;
}
static void ledBlinkingtask1(void* pvParameters){
const uint16_t blinkDelay = 500;
while (1)
{
if (xSemaphoreTake(MySemaphore,2000))
{
for (int i =0;i<9;i++)
{
PORTB ^= (1<<0); //toggle PB0 //PB0
vTaskDelay(blinkDelay); //wait some time
}
xSemaphoreGive(MySemaphore);
}
}
}
AI: Somewhere in your main or before the while(1) you should have created the semaphore with one of the following
xSemaphoreCreateBinary
xSemaphoreCreateBinaryStatic
xSemaphoreCreateCounting
xSemaphoreCreateCountingStatic
xSemaphoreCreateMutex
xSemaphoreCreateMutexStatic
xSemaphoreCreateRecursiveMutex
xSemaphoreCreateRecursiveMutexStatic
|
H: Importance of 2nd or 3rd order RC Low Pass Filter in noise/ripple filtering
I dont quite understand what importance does having a 2nd or 3rd order RC Lowpass filter do to filtering power rail noises. If the first stage filter only allows frequencies below 15.9 Hz arent the other stages unnecessary? Adding more series resistance to the rail will always not benefit the load since it would be receiving slightly less voltage.
Does adding more stages equate to less noise than the previous one ?
simulate this circuit – Schematic created using CircuitLab
AI: I would say the second and third stages are there to deal with self-resonance issues in the capacitors. (So this really isn't a "third-order filter", for any practical purposes.)
If the capacitors were ideal capacitors, then the second and third stages would have no appreciable effect. In an ideal capacitor, the impedance of the capacitor keeps getting lower as the frequency gets higher.
In the real world, all capacitors have some parasitic inductance. At low frequencies, this effect of this parasitic inductance is inconsequential, so the impedance-vs-frequency relationship resembles an ideal capacitor. But at higher frequencies the effect of the parasitic inductance becomes more and more significant (the capacitor actually looks like an inductor-capacitor "LC" circuit). At some point there will be a resonant frequency just like with any other LC circuit, and beyond that frequency the impedance of the capacitor will increase as frequency increases, just like an inductor. At this point the low-pass filter is no longer a low-pass filter!
https://resources.pcb.cadence.com/blog/2019-capacitor-self-resonant-frequency-and-signal-integrity
As you'd probably imagine, larger capacitors have a lower self-resonant frequency and smaller capacitors have a higher self-resonant frequency. So, it is a common practice to put multiple capacitors in parallel -- for example a 0.1µF capacitor in parallel with a 10µF capacitor -- to overcome this effect. Once the frequency gets high enough that the 10µF capacitor is no longer effective, the 0.1µF capacitor is still acting as an effective capacitor so the circuit overall still works.
The extra resistors in this circuit are new to me, but as this article suggests perhaps they are there to dampen out other resonant effects that could happen otherwise.
https://incompliancemag.com/article/using-capacitors-in-parallel-dangerous/
|
H: Transformer cooling difference between water cooling and air cooling
I just know air cooling method is cheaper than water cooling method. Please tell me what is the difference between air cooling and water cooling? And if you could please use some pictures to explain it.
AI: For air the specific heat capacity Cv is about 0.72 kJ/kgK and water is about 4.18 kJ/kgK. This really means that per kg water moves more heat by a factor of just over 4.
This makes it a question of space on one hand as air cooling needs a large surface area and airflow either forced or natural.
Water cooling can take less space and have the possible advantage of part of the system can be remote but can require more parts to the system like pumps and control. Water has the disadvantage of conducting electricity...
Oil is also used to control transformer temperature and is basically as simple as a tank filled with oil with cooling tubes.
One part is also maintenance as the tubes need cleaning to stay efficient and I have spent many hours sanding and spraying oil cooled transformers..
A simple google search for “cooling transformers” gives: https://www.electricaleasy.com/2014/06/cooling-methods-of-transformer.html?m=1
|
H: What are the units used in Shannon formula calculation?
I'm a CompSci student with absolutely no background in wireless communication who recently needs to do something with the Shannon formula:
$$
R = W log_2\bigg(1+\frac{P_t H^2}{N_0 W}\bigg)
$$
I need to calculate the achievable data rate \$R\$ given:
Bandwidth \$W=2\$ MHz.
Transmit power \$P_t=0.2\$ Watt.
Path loss model: \$128.1 + 37.6log_{10}(d)\$, where d = 0.45 km.
Noise power density \$N_0 = -174\$ dBm/Hz.
This is how I'm calculating \$R\$:
Convert bandwidth \$W\$ to Hz, so now \$W=2\times10^6\$ Hz.
Leave the transmit power as is (Watt).
Given the path loss model, we have \$H=10^{-12.81}(450)^{-3.76}\approx 1.64\times10^{-23}\$.
Convert noise power density \$N_0\$ to W/Hz, so now \$N_0=10^{\frac{-174-30}{10}}=10^{-20.4}\$ W/Hz.
Finally, the data rate
$$
R = 2\times10^6\times log_2\bigg(1 + \frac{0.2\times(1.64\times10^{-23})^2}{10^{-20.4}\times 2\times10^6}\bigg) \approx 0 \text{ bps (?!?)}
$$
The resulted data rate is extremely small - close to zero. I reckon because the channel gain is too small? Could someone please tell me what went wrong in my calculation above? I'm quite confused with all the different units of measurement in wireless communication.
I already went over this relevant question (Calculating Data Rate using Bandwidth, Transmission Power, Noise Power Spectrum Density and Channel Gain) but still couldn't figure out.
UPDATE 1:
I just found out that the path loss model: \$128.1 \text{dB} + 37.6log_{10}(d)\$ is equivalent to \$ \frac{P_r}{P_t}=\frac{10^{-12.81}}{d^{3.76}} \$. So that we can find the actual received power \$P_r\$ (transmit power minus the power lost by distance during the transmission). I guess the numerator in the formula (\$P_t H^2\$) should be replaced by this \$P_r\$. The data rate now is:
$$
R = 2\times10^6\times log_2\bigg(1 + \frac{0.2\times \frac{10^{-12.81}}{d^{3.76}}}{10^{-20.4}\times 2\times10^6}\bigg)\approx 0.5 \text{ Mbps}
$$
I'm not sure whether distance \$d\$ should be meter or kilometer. If meter, the data rate is 70.2Mbps, which is crazily high. If kilometer, we have spectral efficiency (the log part of the formula) \$=0.25\$ bps/Hz, and data rate \$R=0.5\$ Mbps, which makes more sense. Am I doing this right? Is this number realistic given all the settings above?
~~
Alternatively, I've seen the channel gain being calculated like this \$H=d^{-\alpha}\$, where distance \$d\$ is in meter, and path loss exponent is, say, 3.76. If I apply this to the original formula above. The data rate is now:
$$
R = 2\times10^6\times log_2\bigg(1 + \frac{0.2\times (450^{-3.76})^2}{10^{-20.4}\times 2\times10^6}\bigg) \approx 0.8 \text{ bps} \approx 8.1\times 10^{-7} \text{ Mbps}
$$
which seems quite small compared to what I got above (0.5 Mbps). I know the setting here (channel gain calculation) is different but I wasn't expecting such a large difference.
Is there anything wrong? Which calculation is more realistic in practice?
For those interested, I found these lecture notes quite useful. They contain some example calculations.
http://weber.itn.liu.se/~vanan11/TNK080/Lecture1.pdf
http://weber.itn.liu.se/~vanan11/TNK080/Lecture2.pdf
AI: Your formula for data rate combines Shannon's equation and signal propagation loss into one row. Shannon's equation for an analog communication channel subject to additive white Gaussian noise (AWGN) of power N:
R = W∙log2(1+S/N)
Assuming your receiver amplifier's noise is negligible and the signal bandwidth is W, we can aspire to reach data rate as high as
R = W∙log2(1+P_R/(N_0∙W))
where P_R is a signal power at the receiver, N_0 is a noise power density.
With the freespace propagation loss model, the signal power at the receiver can be expressed as
P_R = P_T∙G_T∙G_R∙(lambda/(4πd))^2
where P_T is a full transmitted power, G_T and G_R are "directional gains" of transmitting and receiving antennas respectively, lambda is a wavelength, d is a distance between transmitting and receiving antennas.
Expressing wavelength lambda via frequency f in megahertz units (lambda = c/f, c = 299792km/sec), we arrive at the formula (d in kilometers)
P_R/P_T = G_T∙G_R∙0.57∙10^(-3)/(d∙f)^2
In engineering calculations, the ratio P_R/P_N is expressed in decibels:
(P_R/P_T)(dB) = (G_T)(dB) + (G_R)(dB) - (32.44 + 20∙lg(d) + 20∙lg(f))(dB) (lg is decimal logarithm)
The quantity 32.44 + 20∙lg(d) + 20∙lg(f) is termed "path loss in empty space", the losses, calculated under assumption that there are no signal reflection and no absorption of radiation in the medium.
You never mentioned the derivation of an H_0 quantity in your formulas, so I carry out the numerical calculation for half-wave dipole antennas at both transmitter and receiver ends. Therefore, the directional gains are
G_T = G_R ≈ 2.15 dB
Also, you do not specify the radio frequency f. I assume f = 2400 MHz.
With your data d = 0.45km and my assumed radio frequency f = 2400MHz,
(P_R/P_T)(dB) = 2∙2.15 - 32.44 - 20∙lg(0.45) - 20∙lg(2400) = -88.8
With your data P_T = 0.2W, N_0 = -174dBm/Hz = 10^(-20.4)W/Hz,
R = 2∙10^6∙log2(1+0.2∙10^(-8.88)/(10^(-20.4)∙2∙10^6)) ≈ 30 Mbps
With your data and under assumptions I specified above, we can achieve a data rate of approx. 30Mbps. That good value for a 2MHz bandwith is not unbelievable, because noise figure is quite low. Indeed, -174dBm/Hz is the thermal noise at 290K and therefore the low limit for conventional designs.
|
H: What happens when a computer is plugged into another computer by USB?
I am just curious about what happens when you have a USB 2.0 cable with two male ports, and plug both the ends in two different computers (not for data transfer reason, or any other reason, just curious)?
I have read this similar question on quora, where a writer says:
Answer
My actual concern
I purchased one 4 port USB hub and one input cable for the USB hub. I want to power my HDD + USB keyboard + mouse, and charge a phone from the USB hub.
I successfully plugged that into my laptop with the power bank, and nothing happened.
But when I write data to the HDD, the power drawn by the HDD from the power bank is significant, despite connected to the laptop as well:
So I have to keep the power bank plugged in, and maybe replace the power bank with a 5v 3 AMP phone charger. My concern is can it damage my laptop (and / or laptop's USB port) in a long run?
AI: It should not damage your laptop as long as the power bank keeps working normally (gives approximately 5V).
Of course the voltage from the laptop and the power bank can never be exactly same, but these interfaces are safe for use with slight voltage differences (up to 5.5 V should be definitely safe). There is usually no path for any significant amount of current to flow backwards into a USB port of a computer, except when the voltage rises to unusually high values, e.g. 12V.
|
H: Propagation delay in shift register - in the context of a serial adder
The first figure (from Fundamentals of Logic Design, Roth/Kinney, 6th Ed, p.404) shows a serial adder which feeds in operand bits and stores the sum, and uses a D flip-flop to store the carry-out from each bit pair and load it back in as the next carry-in.
The second figure (from Fundamentals of Logic Design, Roth/Kinney, 6th Ed, p.405) shows a timing diagram for this same serial adder.
My question is: is there a good reason why the delay in loading the operand bits (x_i and y_i) would be depicted as being longer than the delay in loading the carry-in (c_i)? This seems important, because (as shown in the timing diagram) it leads to glitches in the sum, s_i.
I have assumed (though the textbook does not absolutely confirm this) that shift registers made of D-type flip-flops (like the one for the carries) would be used to feed in the operand bits and store the sum. If so, surely the delay for loading x_i and y_i would be identical to the delay for loading c_i?
If not, can anyone cast light on another reason why the timing diagram depicts things this way? I have searched unsuccessfully online for an answer, and one is not contained in the textbook itself to my knowledge.
To be clear: my suspicion is that the authors made a mistake (I am guessing they did not allow for flip-flop propagation delay in loading c_i) -- but I'd like to get a knee-jerk response from more experienced folks indicating whether they would tend to agree with me, or whether I'm missing something really obvious? Thanks!
AI: The reason is probably that x and y are coming from other combinational logic with a little bit of delay, while c_i comes directly from a DFF close by.
It's not that important. In sequential logic like this you should always assume glitches during the start of a clock cycle (signals toggling up and down). As long as you are stable before the next clock edge, you are fine. Stable here means that all signals have had time to propagate to the the next DFF - your design reached timing.
|
H: Measuring Current in Coax Cable Using Clamp on Current Probe
I once again find myself needing to measure the RF current in a coaxial cable.
The signal in question is a high power (100W-1kW range) signal which is a stepped waveform with a 5MHz fundemental with multiple harmonics (the 7th harmonic is highest of any interest). I have to hand an active oscilloscope current probe of the clamp-on style (specifically Keysight N2893A) which has sufficient bandwidth to do the job. The question is one of building some form of adapter to connect the probe and coax cable.
I did wonder whether the probe could simply be clamped around the coax cable directly, however I'm not sure this will work - AFAIK the magnetic fields of current flowing through the sheild and central conductor should cancel out (?).
In the past I have used an adapter we built which is nothing more than two BNC connectors attached to a metal box (connects the sheilds), and a length of single core wire connecting the signal lines which the clamp can then attach to (pictured below).
Unfortunately I don't currently have access to this adapter, so I am going to need to build a new one.
I can probably cobble together something similar to the previous adapter with bits to hand, but I was wondering if there is any standard or common approach to doing this, or whether the DIY adapter we made previously is the best way to go.
AI: AFAIK the magnetic fields of current flowing through the sheild and
central conductor should cancel out
Theoretically and practically they do - the external magnetic field (beyond the shield) produced by the inner conductor current is exactly opposite to the magnetic field outside the shield from the returning current in the shield.
The only magnetic field that exists inside a coax cable is between inner conductor and shield.
This is why coax is so sexy - the outer shield (being a tube) is unaffected by the internal magnetic field therefore, from that standpoint, the shield has zero inductance and, given that the fields cancel outside the shield, the shield can be well and truly regarded as having zero inductance because it isn't subject to any net flux changes that induce voltage in it.
Unfortunately I don't currently have access to this adapter, so I am
going to need to build a new one.
That seems the only route given that (a) it works, (b) you've used one before and (c) the theory is sound. That would be my choice. The 7th harmonic of 5 MHz is 35 MHz and the wavelength is therefore around 10 metres so a few inches of extracted inner isn't going to make a whole deal of difference to impedance balancing or reflections.
|
H: Delta Servo Drive 220V/400V Series
ASDA-A2 Delta Servo Drives including two types: 220V and 400V series that it seems the difference is input voltage of the Servo Derive. but i doubt 220VAC or 400VAC is line to line voltage or line to neutral voltage of The local electricity grid? and if it's refers to line to line voltage, is it possible to feed 220VAC Servo Drive with 400 VAC (line to line voltage) with some considerations or not?
AI: It is connector to connector voltage. It can be line to line if you connect all three phases or it is line to neutral if you connect a single phase (if allowed).
No, you may not use 3ph 400V fo a device that has 220VAC input, only phase + neutral (if single phase is allowed, only low power servo drive). If you intend to connect all three phases 400VAC to your servo drive, then you should use an autotransformer 400/220.
I do think the manual is self explanatory:
|
H: Create a synchronous network of 400 devices
I have around 400 devices that i want to address in a star topology. Each device controls a set of LED strips (27*12 resolution). The idea is display a video animation in a good frame per second rate (at least 25fps).
I was successful controlling one set using Arduino (working code in this post). The step of transforming the video into RGB values was done with ffmpeg tool in Linux , the program then transform RGB values to a raw binary frames ready to be sent by the Arduino to the LED strip.
So to send these frames from the Linux program to all the Arduinos i have made an MQTT layer through TCP/IP where each device listen on a topic and the Linux program send according frame to it.
The problem is the heavy delay between sending the frames to all of the 400 devices and the start of the animation (trust me it seems awful resolution where each LED strips shows the RGB values in delay from the others).
I want to stay at 60fps which gives around 16ms between each frame being converted ,sent and displayed. So we are on a milliseconds tolerant architecture.
My question is how to implement a synchronized network with above considerations ?
Below a picture of a 12 pixel strip :
AI: First, synchronize all of the devices to a common timebase using NTP, PTP or GPS, depending on your actual accuracy requirements (on the order of ms, µs, or ns, respectively).1 NTP should be sufficient for "a window of 10 ms".
Your command packets should include both the action to be performed along with a timestamp (a short time into the future) that indicates when the action should happen. The device then performs the action at the specified time.2
1 "Exact same" is not an engineering specification. You need to specify a tolerance.
2 Many years ago, I was able to use this general strategy — GPS synchronization plus delayed action — to synchronize multiple simulcast transmitters across an entire metropolitan area to within ±1 µs.
|
H: 9 pole mini din identification
I need to buy a 9 pole mini din plug (male) to create a ps2 -> quadrature mouse adapter but I'm a little concerned the socket I'm connecting to is non-standard:
[
The reason I think this is the top 3 pins are not evenly distributed and the data sheets I look at for ordering online have them evenly distributed.
So my questions are:
Is this socket standard?
Are the datasheets wrong?
Could I buy a 10 pin, and just pull one of the pins out of the plug?
AI: Is this socket standard?
Pinwise, yes, it seems to me that all 9-pin mini din connectors are that way, with an uneven first row, which is also found in the 10-pin model. If there are no differences in dimension, there shouldn't be any problems using a 9-pin din on it. Although that happens to be my experience, the fact that the datasheets indicate otherwise would make me second-guess myself.
Although, it does not seem to feature the two little notches near the bottom, common in the mini din connector, which might make it incompatible.(EDIT: A new picture shows that it does indeed have the notches.)
Are the datasheets wrong?
Well, it seems to me that they could, but it is hard to say, really. You should look for a datasheet with measurements to see if it really is non-standard.
Could I buy a 10 pin, and just pull one of the pins out of the plug?
I don't think the two bottom row pins would necessary align if you remove the middle one of a 10-pin. But perhaps with some force you could, although it would not be ideal.
|
H: Using QSFP28 Module at Lower Lane Rate
I have an application that requires optical transmission of 4x16 Gbps SERDES lanes over fiber. A QSFP28 module for 100G ethernet seems like a great commercial solution--it can take the four lanes and combine them over a single fiber channel. The only hitch is that all of the QSFP28 modules I can find are only characterized over a narrow electrical lane rate, about 25-27 Gbps.
Here's an example from FS, but it's a similar story for all vendors I've checked: https://www.fs.com/products/75309.html
I understand why the datasheet recommended range is so limited, since they are designed for a singular networking application. However, my gut also says that a lower but not-too-low lane rate like 16 Gbps would be okay for the internal SERDES transceivers. It would also enable the modules to be used in 40G/4x10G applications, so I'm wondering if there are any resources that would serve as evidence to this point.
Additional Research
I accepted Joren's answer since it showed quite clearly that the limitations of the CDR/retiming functionality of QSFP28 modules would be the foremost barrier. I also did a little research that I want to share here. There is a workaround provided in the QSFP28 memory map. See the snippet below from SFF-8636: Management Interface for 4-lane Modules and Cables, which shows that it is possible to disable retiming functionality. This presumably comes at the expense of signal integrity at the receiving end and consequent maximum link length.
I'll probably run some tests, and also take advice to look at alternate fiber specifications.
AI: The problem is often in clock-recovery circuits. The CDR chips used in these kinds of modules have PLLs/recovery loops with limited locking rates. An example (but made for QFSP40) is the Semtech GN2405A. As a result, you can only use them with symbol rates that match them. Sometimes, as is the case with the Semtech IC I linked to, you can have modules that can lock to lower rates too, but again only fixed windows. Sometimes you can also disable the retiming circuits of such a chip. However, all of this stuff is controlled by the microcontroller integrated in the QSFP module, and is not something you have access to as user.
|
H: BALUN vs other methods
I have a differential analog signal traveling over 2 coaxial wires. I need to convert to single ended. When should I use a BALUN ? When are other solutions such as OPAMPS more appropriate ?
AI: Use the appropriate one for the frequency range.
Anything less than 100 kHz, use an opamp. Anything over 50 MHz, use a transformer balun. Between those frequencies, depending on your signal level, or distortion requirements, you'll need to choose your component carefully, paying a bit more for a faster opamp, or testing your magnetics critically.
|
H: LTSpice provides incorrect bode plot
I want to replicate this structure in LTspice where the components 1, 3 et 4 are resistors with the same resistance R and 2 et 5 are two capacitors and opamp LT1356
this is the schema I made
this is the bode plot:
I think it's wrong because the max value of the gain is -50 dB while I need to find the frequency at -3 dB
AI: Good intuition that something is wrong. As soon as you see weird things in the AC response, you need to head back to TRANsient or DC to figure out what's going on. However, I did spot two things:
Your negative power supply is supplying +15V instead of -15V. Your circuit is basically unpowered as there is no voltage across the VDD/VSS pins of your op-amp. Either rotate V2 or make the value of V2 negative.
Don't connect two wires directly to the pin of a schematic symbol - it's hard to read and your CAD system might not make one of the three connections you're expecting it to.
|
H: How would you all implement a simple delay of a signal?
I am a console game developer by profession, and has no formal education on electronics / electrical engineering. In gaming lingo, a 'noob' if you will, at it. And yet I have a new found passion for fiddling with this wonderful craft.
At the moment, I am trying to learn and have fun while make a 'scrolling LED' toy for my daughter. My idea for it is quite simple, I have a shift register (SN74HC595), and 8 LEDs taking input from it. There will be two buttons. When button A is pressed, it 'inserts' a 1 into the register, and when B is pressed, it pushes a 0 into the register. With this you can 'program your LED pattern'. And then with the flick of another toggle, the shift register will get clocked (using a simple RC astable multi vibrator) (looping QH' to QA). Making the pattern to scroll. Simple enough.
But, my problem comes at the part which does the 'inserting' of data into the register. Let's say, to insert a 1 to the register when button A is pressed and released, I first have to pull the 'SER' (data) line of the register high, then after a brief period of time (setup time, 25ns for the register's datasheet) pull the SRCLK (Shift register clock) high. And that's it. However..
My switch buttons are debounced. I learned about debouncing from this wonderful article : Debouncing. I didn't had any parts that would help me with hysterisis so I had to just ignore it. But using the methods specified there, I was able to calculate the exact values of my resistors and cap, to keep the voltage just right while my switch clank and knock with itself. The switch bounces for 10ms ( got myself a cheap O-scope, china one. But does the job ), so am keeping it steady for about 20ms. My calculations and the results of simulating it using Multisim.com matched. So my button debouncing works as expected.
Except, when I try to use that 'signal'. I have to do two things with this signal. First, route it to SER line of the register. And then after a brief delay (25ns - a few ms?) route it to SRCLK line to clock it. In other words, first pull SER high, then pull SRCLK high. And to introduce this 'delay' I turned to the only delay mechanism I know - RC network. So once I get the debounced output, I charge a cap through a resistor, and that charged output is what I use to drive SRCLK.
The moment this new capacitor and resistor gets added to my 'debounce circuit',my calculations for the parts value doesn't hold true anymore because the new 'delay' capacitor and resistor is now in parallel or serial (I don't even know anymore) with my good and previously well behaving 'debounce' capacitor.
All this predicament makes me wonder if even using an RC delay timer is even the right thing to do. How do I connect input from a debounced switch to a node that already has a capacitor, without messing up all my calculations.,or to rephrase it, How would you all implement a simple delay of a signal without using all fancy micro controller etc..?
Here is the schematic of the denounce and delay. Note that this is only addressing the single button (not both A and B). SW2 in the first image is just for debugging.
simulate this circuit – Schematic created using CircuitLab
AI: There is just one problem, the debouncing method you use will make extremely slowly rising and falling signal edges, and the 74HC595 can work improperly because of it. The chip datasheet says that at 5V supply, signal edges must change faster than 500ns/V, so for a 5V change, it must use not more than 2.5 microseconds during the transition (or maybe 1.5 microseconds during the range between 1.5V and 3.5V)
Ganssle article does use resistors and capacitors to filter short spikes into slowly changing voltage, but it also mentions that many chips don't like it when they are triggered with slow edges, and it is squared up into single fast edge with a Schmitt trigger logic gate.
Other than that, you can use a Schmitt trigger to square up a signal for data input, and simply use a fast RC filter after that to delay a signal for few nanoseconds and another Schmitt trigger to square up the clock pulse.
|
H: Help with TDA2030A Amplifier circuit
I am designing an amplifier circuit using TDA2030A, but now I am stuck in providing power to the circuit. As mentioned in the datasheet, I copied single power supply circuit for my amp. But the simulation in proteus is showing an error if I just test the same single power supply circuit from the Datasheet, but if, I provide it a negative supply (split power mode), the simulation works.
Circuit similar to that in the datasheet for a single power supply. (Not working)
These are the two circuits from the datasheet. (I want single power supply)
I want to drive a 5W speaker, please tell me what I am doing wrong in the circuit.
secondly, is it good idea to transfer the second circuit (Proteus simulation) to the breadboard and check it.
If possible please tell me how can I provide a split power supply to it using only one 12V 2Amp adapter.
Thankyou
AI: You need to look at (and compare) the DC voltage at the + input of TDA2030.
You made a mistake in connecting the output of RV1 to the net between R6 and R7. Compare your schematic to those from the datasheet!
I would connect the output of RV1 only to C2. RV1 now pulls the DC voltage at the + input to around 0 V, then the TDA2030 can only work if it has a negative supply that is at a lower voltage than 0 V.
In case of a single supply solution the DC voltage at the + input needs to be about 6 V DC.
Do a DC operating point simulation and check the DC voltages of the TDA2030's inputs for both circuits.
|
H: How are LAN routers, WAN routers and eNodeBs connected to each other (TCP/IP)?
I'm new to telecommunication, and from what I understand, an user equipement is either connected to a LAN router or an eNodeB, and a LAN router is connected to a WAN router, and routers send the packets to the correct destination with a routing table. The part that I don't understand is how does all this work with IP/TCP? Let's say UE1 is a stationary device connected to a LAN router and sends a message to UE2, which is a mobile device connected to an eNodeB, how would that work? As far as I understand :
UE1 sends a message to the LAN router
the LAN router sees that the message is not intended for the local network, and sends the message to the corresponding WAN router.
the WAN router sends that message to the corresponding eNodeB
the eNodeB sends the message to UE2
Is this correct? Also, is I understand correctly, an eNodeB is basically a bounch of antennas with some software that can send/receive data from UEs in it's covered area, and a router does pretty much the same thing, so what are the differences between the 2 in terms of functionality (except that the eNodeB covers a wider area)?
Thanks
AI: I'm neither an IP Guru, but think i have a solid understanding of it and I just started working in mobile telecommunications. So I will try to help you here.
The problem in your understanding might be the fact, that the eNodeB is not directly connected to the Internet.
You probably should follow @Bimpelrekkie advice and have a look at the OSI Model to understand how this all works together.
Directly jumping into a mixture of Ethernet and mobile communications is hard. Maybe you should have a look at the EUTRAN=LTE basics, e.g. see https://en.wikipedia.org/wiki/System_Architecture_Evolution.
You simplified the eNodeB pretty much to some antennas and software. That might be true if you simplify it really much. I'll simplify as well, maybe it helps you.
The (simplified) task of the eNodeB is to transmit Data over the Air interface while making sure that each user gets a fair share of the air interface.
What Data is transferred must be differentiated between Userplane Data (Data that is actually "useful") and Control Plane data (data that is used to control the connection).
the eNodeB (simplified) transfers the Userplane data to the Packet Gateway and from the Packet Gateway to the UE. The Packet Gateway is between the eNodeB and the Internet.
Have a look at this figure (you will understand it easier, if you have understood the OSI model):
https://www.slideshare.net/sofianonline/ip-concept-in-lte/7
(You can also search for "LTE Stack OSI model" or similar to get some other diagrams).
If you understand Ethernet or "LAN" a bit better, you should maybe compare the eNodeB to a WiFi Access Point. The WiFi Access Point does not directly "talk" IP. It gets IP packets from somewhere and is just (simplified) an Antenna which will put the IP Packet on the Air...
hope that helps
|
H: Speaker producing static noise
I have a set of speakers which has been standing in a humid place for a few months. One of them still works perfectly fine, the other not so. The other speaker creates a very static noise, barely rendering it's audio source.
Following link is a recording of what it sounds like:
Good speaker vs bad speaker
The speaker consists of a sub and a tweeter, connected together by a bipolar capacitor. The circuit gets fed by a copper cable from my amplifier.
I've checked the copper cable ends, but I don't see any oxidization.
When I tap the cone, there's a lot of friction, whereas the cone of the other (good) speaker feels very smooth and reacts to my tap. I notice a very big difference between the two.
Does anyone have an idea what I should be looking for and what the cause might be?
AI: The cone and/or its suspension (the "spider") has warped, and now the voice coil is rubbing against the magnetic pole pieces. It needs to be replaced, or repaired by a technician who knows what he's doing.
|
H: Automatic series/parallel configuration
I've been thinking about this issue for a while now and came here for your guided assistance.
Situation:
Ik have 4 resistors (12V/1.25W heater pads). I need to power them with either a 12 or 24V battery.
The problem rises when I've physically placed the resistors. I cannot change the placement nor connections of the resistors on the PCB after physically placing them. However the input voltage can and will continuously change and be EITHER 12 or 24 volt. nothing in between.
So my thought process was basically:
Option1: When powering the resistors with a 12V battery I simply put all the resistors in parallel.
Option2: When powering the resistors with a 24V battery I configure it as 2x 4 resistors in parallel.
With some help on other forums and some finetuning afterwards I came up with the following Mosfet circuit:
Issue:
I'm having trouble and a hard time finding the values for the 3 mosfets. I came up with the following thought process but now I'm stuck.
-Q1 should have a VGSth of around -20V, so that when powered by a 12V battery the resistors are all in parallel.
-Q2 should have a Vgsth of around 20V. This so the current can flow to ground when 2 resistors are in series and powered by a 24V source.
Q3 should have a Vgsth of around -20V.
Keeping in mind that the battery is a Lead-Acid Battery which means that the maximum precision of the configuation will be the charged and decharged value of that battery, so about +/- delta 2V.
My problem is that If I lookup digikey I just cant find mosfet's with these parameters, where I'm I going wrong here? And is there a better way to do this with mosfets? I know one can use a relay but I want a mosfet solution.
Thank you for your time!
AI: The thought process of design should be to define all the input and output requirements with all the ambient stress environmental specs and assumptions needed and make a list of these specs. It should not limit the specs to any parts or configuration or imagined implementation. Think about what is really important.
I am guessing you need to heat 4 locations evenly with 5W like a coffee cup heater and it must work off a car or truck so what counts is the temperature and not just the voltage.
Now if you define the output in terms of power instead of voltage and thermal resistance with temp rise, you can imagine PWM with a regulated thermal sensed solution.
Design Problems:
FETS make lousy comparators due to wide variation of Vt=Vgs(th)
Old power FETS were typically Vt= 2~4V @250uA i.e. 3V +/-33%
They do make Vt=8.5V but never 20V . The trend now is sub-threshold FETs Vt<~1V
BTW if I guessed what you were thinking. look at Mercedes heater-cooler dual cup solution using thermal heatpump chip to make cold one side hot the other
|
H: BJT Transistors: understanding Vbe measured (model "DCIL TIP 112 N2")
On my protoboard have a BJT CDIL transistor TIP 112 N2, working in the way that on base I have a Vbb = 5V and Rb = 450 Ohms. On Collector, Vcc 24V and Ic = 0.13A. A gearmotor is working properly on that way, (covered by a diode and a capacitor).
So I tried to measure voltages on BJT just for verifying everything is ok, and then simply do some other calculations. If I assume Vbe is approx 0.7 V, then I should expect Ib have an approx value of (5-0.7)V/450 Ohms = 9.5 mA... However when using the multimeter, a current of 7.8 mA is measured.
The fact is when I measure voltage between base and emitter I notice that Vbe = 1450 mV (!!!)... I was expecting a value near 700 mV as I had learnt, but there's no way to let it down (tried replacing the gearmotor for a cooler, increasing Rb, etc). That value of Vbe reamains pretty constant. Is it ok?? Why is Vbe >> 0.7V?
PD: other measures Vce = 0.71 V and Vcb = -0.75.
Thanks a lot (not an electronic here, please be patient :)
AI: The TIP112 is a Darlington device and as such will have essentially 2 diode drops between base and emitter when conducting. (Darlington Transistor.
Since the base-emitter voltage is higher than in your calculation this would account for the difference between the measurement of the base current and the calculation.
Furthermore, you will often see differences between calculated and measured values for other reasons such as the tolerance of components and the fact that inserting a meter into the circuit will alter the circuit- a current meter, for example, will typically drop from 200-500mV when at full scale.
TIP 112 datasheet
|
H: Measuring power consumption of system with buck converters
I'm trying to measure the power consumption of a circuit which utilizes a buck converter. If I know the circuit in absence of the converter utilizes 5.125V @ 142ma, then I introduce a 12V battery source with a buck converter to drop the voltage to 5.125V, should I see ~0.061ma going into the converter (assuming 100% efficiency)? In other words, is it right to assume conservation (if 100% efficient)? If the converter is not 100% efficient, does that mean I should see a higher current flowing into the converter, where the difference between that measured and the theoretical conservation is the power loss across the converter?
Overall, I'm trying to understand where I should be measuring the power consumption of my system. I have 2 devices connected to a battery in parallel (i.e. 12V going to each device). Both devices have buck converters, which drop the voltage to ~5V. Currently I measure the battery at ~12V then put my multi-meter inline with the hot lead of the battery and measured ~300ma, which I'm assuming means my system utilizes ~3.6W. The one circuit/device I mentioned above uses ~0.72W, which means the other must use ~2.88W, but the datasheet says that it should be 1W. I'm trying to determine if the datasheet is publishing power consumption values not representative of full load or if I'm testing the system incorrectly. A discrepancy of 1.88W is a lot and I'm not sure how to explain it.
AI: The method you're proposing is correct. Efficiency is (power out) / (power in).
The efficiency for the buck regulator varies with load, and may be fairly low at light load. The regulator datasheet will have an efficiency vs. load characteristic. Check that and see if this correlates with what you're seeing. If it does, you have your answer. If not, you may have some other problem with your design.
|
H: how the area is exactly zero?
I was reading this PDF which tries to explain the concept of poles and zeros of Laplace transform.
My question is about FIGURE 32-5(b) on page #591.
I don't understand why the area is said to be zero when, as shown, it should clearly be some negative number. The mentioned PDF does try to give an answer which I don't understand.
Figure (b) shows one of the special cases we have been looking for.
When this waveform is multiplied by the impulse response, the
resulting integral has a value of zero. This occurs because the area
above the x-axis (from the delta function) is exactly equal to the
area below (from the rectified sinusoid). The values for σ and ω that
produce this type of cancellation are called a zero of the system. As
shown in the s-plane diagram of Fig. 32-4, zeros are indicated by
small circles.
You can consider it to be a follow-on question to this comment where @AJN tried to explain it further but unfortunately I still couldn't get it. I thought it'd be better to ask it separately. I'd appreciate if you could help me with it?
AI: The dirac-delta function has an area of 1 when integrated. The red area and the delta function have the same area. When integrated from t = (0-) to t -> inf the total area is 0.
|
H: How to design a low pass filter for Fourier Square Wave
I am trying to create a low pass filter with a cut-off frequency of 100Hz to retrieve a sine wave from a Fourier Square Wave. I am only able to achieve a sine wave with transients. How can I edit my filter design to achieve my desired output?
AI: Where is your filter math? RC for -3db at 100HZ is 10K/160nF. Or you can swap the RC values to be 16K/100nF. I would keep R >= 10K to avoid loading the summing op-amp, as the inverting input is treated as a virtual ground. From what I see you could increase the value of all resistors by a factor of 10.
The triangle output may be from using R values that are too low for the op-amp to drive. If 1.59K becomes 15.9K, then your 1uF capacitor needs to be just 100nF, avoiding the need for aluminum or tantalum capacitors. R6 becomes 15.9K which avoids loading the output of the op-amp. For LM324 normal minimum load is about 2.2K ohm.
Your program maybe interpreting values the way a real LM324 op-amp would see them.
|
H: Does decoupling capacitors try to charge the fluctuating source back?
In common examples of decoupling capacitors, the scenario is like this:
When the voltage fluctuates below or above its ideal value, capacitor either stores or releases energy to compensate the fluctuation in power so that the load gets a nice, flat voltage.
simulate this circuit – Schematic created using CircuitLab
Now, when I read the circuit form left to right (first looking at the source, then the cap parallel to it, then the load parallel to it) this explanation sounds right because it seems like power is delivered from left to right and capacitor behaves like a buffer in between.
But when I think about it, if cap is at 1V and power source suddenly drops to 0.95 volts, there is a short circuit between 1V and 0.95V so a relatively high current must flow from the cap to the voltage source. This not only tries to charge the source back but also wastes most of the power on that little short between 1V and 0.95V.
So, how should I think so that this circuit will make sense to me?
AI: Generally speaking, it isn't the source that fluctuates, it's the load. One common example is digital circuits that draw short-term spikes of current when their outputs switch. And the best way to think about it is that there is some significant impedance between the source and the decoupling cap, especially at higher frequencies.
simulate this circuit – Schematic created using CircuitLab
So while the DC signal flows from the source to the load, the high-frequency AC noise imposed by the load flows mostly through the capacitor, both charging and discharging it. It "decouples" the noise from flowing through the power supply impedance, shorting it to ground instead. The goal is to keep the green noise loop as short as possible.
The peak noise current is never greater than the DC current, so there is never a net flow "backwards" through the power supply.
|
H: Can I put my battery in the middle of my parallel circuit?
This is a small project, basically cosplay, four 5mm LEDs wired in parallel. Normally, I put the battery at the end:
But could I put the battery in the middle with the same result? I'm researching simple circuits but couldn't find theory on placing a battery (3.7V Li-Ion battery). This layout helps me fit the LEDs in a smaller space without extra wire. Any online resources appreciated.
AI: The two circuits shown are exactly the same. Both use parallel connection of four sets of LED plus resistor and battery. Placing battery at top, middle, or bottom (or anywhere in between) while leaving the same connections unchanged will give the same result. This is because for parallel connection, the battery’s connected to the same points. You can see this by moving your fingers over the two places where battery is connected and see that they are in fact the same points on the wire. If you want to save wire length or optimal placement of battery then by all means keep battery in middle as long as you keep it connected to same points shown in your picture. For examples of circuits that are similar, I’d just recommend googling “parallel led circuits”.
|
H: Difference between reactive load and source?
Probably a silly question, but I am coming across terms like reactive power load and reactive power source in some articles in web. Does it matter if a reactive component is a source or load? Say between an inductor in induction motor and coils in synchronous generator, is there any difference in the way they work?
Also, direction of current tells if a component is load or source in DC. How to get similar sense in AC, and understand if something is load or source?
AI: The concept of reactive power was invented to explain why the power consumed by an indiction motor is not simply voltage multiplied by current. Since the motor is inductive, the convention is to say that inductors consume reactive power and capacitors supply it. We say that a synchronous generator functions as a capacitor because it can be a source of reactive power consumed by an induction motor. The terminology is difficult to follow, because the concept of "consuming" reactive power is not technically correct, but it is convenient for the situations in which it is used.
Here is an explanation of the naming convention.
See also: What is reactive energy?
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.