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H: Phase between two sinusoids and which one is leading
that's my first question here.
I'm studying fundamentals of electric ciruits
and I faced this question:
Determine which one leads and by how much:
$$v1(t) = 4*\cos(377t + 10)$$
$$v2(t) = -20*\cos (377t)$$
So I converted
$$v2 = -20*\cos (377t)$$ to
$$v2 = +20*\cos (377t+180)$$
and graphed the two sinusoids on the unit circuit but I'm confused about which one is leading the other and by how much
Thanks in advance!! =)
EDIT!!:
AI: You have got these two equations:
$$v1(t) = 4*cos(377t + 10)$$ and
$$v2(t) = 20*cos (377t+180)$$
If you substitute t=0, you will get \$v1(0) = 4*cos(10)\$ and \$v2(0) = 20*cos(180)\$. From the values you can conclude that at t =0, v2 has a value which cosine does at the end of its period and v1 has a value which cosine does at the beginning of its period.
So, we can say v2 is leading v1.
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H: Obtain audio information from mic and play in MATLAB
I am trying to make a basic VoIP implementation and I am stuck obtaining sound samples from the mic and playing the read data on a computer. I tried to sample the voice from the microphone and send it to the serial terminal using a very minimal code:
void setup() {
Serial.begin(9600);
}
void loop() {
int sensorValue = analogRead(A0);
Serial.println(sensorValue);
delayMicroseconds(122);
}
The delayMicroseconds(122) causes the sample rate to be around 8192 Hz. I also tried with a sample rate of 1000 Hz. The data plot obtained looks good, however, when I try to play it with the MATLAB command
sound(csvread('samples.csv'), 8192);
I do not really hear what it should be (I just hear random noise). I am attaching a graph of the obtained data and my microphone circuit. (I also tried subtracting the average from the array so the values are centered around zero, but no use).
Data Obtained:
Microphone Circuit:
AI: Input:
Your signal looks like it doesn't have much dynamic range.
You may want to look into amplifying it before it reaches the arduino's ADC.
The AVR based Arduinos have a 10 bit ADC -- 0 to 1024.
At 5 volts Vref that is
\$ \frac{5volts}{ 1024 counts} = 4.9 \frac{mVolt }{ count}\$
Your signal ranges from ~150 to ~225. This is 75 counts of range or 7% of the ADC's resolution. Your input signal varies by about 366mV peak to peak.
It should vary by about 2.5v peak to peak.
Output:
Matlab's documentation on audio files states the following:
The MATLAB sound and soundsc functions support only single- or double-precision values between -1 and 1.
Your arduino code is printing values from 0-1024. Integers.
You will need to normalize them and remove the DC bias: make the signal have an average of 0, and a range of [-1 1].
input = double(csvread('samples.csv'));
input = input - 512; % convert the [0 to 1024] range to [-512 to 512]
input = input ./ 512; % convert the [-512 to 512] range to [-1 to 1]
sound(input, 8192);
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H: Altium Designer New Template
I have just prepared a new template for Altium Designer schematics. I included an image to template. My question is that if i prepare a project with this template, how can i embed this image when i need to send another person? Because after i sent a project with my new template, i realized that the template image could not be seen on an another computer (It wrote on template as "Cannot open file C:...) I have some examples which are embedded for these situations however i don't know how i can do. This photo shows when i sent to another computer:
AI: Double click image to get to properties. Click "embedded." You should do this in the actual .SchDot template file, it's not clickable once the template is instantiated.
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H: What reduced the noise when multiplying neighbor samples?
Is this a common filtering technique? I multiplied each sample with it's neighbor.
I was trying to distinguish the spikes from the noise. Low-pass filtering wasn't as helpful maybe because both the spikes and the noise are kind of high frequency.
TOP: filtered, BOTTOM: unfiltered
AI: You basically squared the signal. If you were sampling properly fast, then the small shift due to multiplying by the next sample instead of the same sample only had minor effect on high frequencies.
Squaring a signal is a non-linear operation. The reason it appears to give lower signal to noise ratio is only because your noise was already lower than the signal spikes you are looking for. Squaring de-emphasizes weak signals proportional to their weak-ness.
For example, consider a raw signal that contains noise with amplitude ±.1, and the spikes you are looking for go to 1.0. That is a 10:1 signal to noise ratio. After squaring, the noise is ±.01 and the spikes still 1.0, for a apparent ratio of 100:1.
However, in the above example you haven't really reduced the noise relative to the signal, just made the noise less obvious. Let's say that after looking at the "cleaned" signal, you decide to set the threshold for detecting a spike to 0.5. This is exactly the same as starting with the original signal and setting the threshold to 0.71. You only have the illusion of more noise immunity, not actual noise immunity. Any noise in the original signal rising to 0.71, on in the squared signal to 0.50, will be interpreted as a spike.
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H: What is the proportion of the strength signals between wired and wireless mouse/keyboard?
I understand that the PSU of a desktop PC is creating noise (ripples and ringing) at frequencies that propagate along the cable of the mouse and the keyboard, and radiate those signals through them. The frequencies may be beyond 100 Mhz.
My question is: what is the proportion between the strength of the wired mouse/keyboard radiated signals (which radiate that > 100 Mhz noise signals) opposed to the strength of the signals that radiate from wireless (WiFi) mouse/keyboard?
AI: There's orders of magnitude difference in the signal strength. Although virtually every electronic thing radiates some RF energy, most don't radiate much at all unless they're designed to. There's two reasons for this.
1) Making electronics radiate RF effectively usually requires you to have a resonant setup. There's an entire field of electrical engineering just dealing with antenna design to come up with effective ways to resonate electrical signals to allow them to effectively convert the energy into RF. The wireless mouse/keyboard have an antenna specifically designed to convert electricity into RF.
2) Most electronics that could resonate easily creating unwanted RF are purposely designed or changed to not emit RF easily. The FCC states that electronics must not cause unwanted interference so designers have to ensure they don't do so. One example of engineers lowering the amount of RF noise is with CPU clocking. Instead of clocking at the same frequency constantly creating an RF noise spike, they perform spread spectrum clocking so the noise is distributed over a wider bandwidth and is therefore lower at any given frequency.
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H: A confusion on flash memory map of an AVR micro-controller
I'm trying to figure out the flash memory map of ATmega328P:
Below is from the datasheet:
Program Memory Map for ATmega328P is given as 32KB: 32Kbytes = 32K * bytes
0x0000 means 16 bit wide (for each line of memory there is 2 bytes)
which is 16K * 16bit
What I understand from this, the flash memory is made up of 16K lines of 16 bit wide registers. So for an instruction on the flash memory the maximum address number is 16K.
Is this 16K 2^16 or 16000?
The last three X Y Z general purpose registers which are used for holding the addresses(pointers) are 16-bit which can store up to 2^16 = 65536 addresses.
So I would guess 16K means 65536 here?
But if it is, in the above figure it shows the last memory line as 0x3FFF which corresponds to 16383.
What am I knowing wrong here?
AI: What you are knowing wrong are a couple of things.
Not all AVR devices have the same amount of actual available on-chip program memory. Some may have 8K bytes, 16K bytes, 32K bytes or even 64K bytes. Yours happens to have the advertised 32K bytes.
The X, Y and Z registers are 16-bits wide. These are generically designed to support a data memory map up to 64K bytes. Once again the size of available data memory can vary from device to device type so the whole 64K byte addressability may not be used on all devices.
The X, Y and Z registers are generically indicated right in the data sheet description to be used for accessing data memory. Data memory is not to be confused with program memory. The Z register can be used, in conjunction with certain specific opcodes, to access tables in the program memory (Z still 16-bits to support up to a generic 64K bytes even though the program memory available may be less).
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H: DIY zero-crossing circuit, how crucial are component values?
I want to build this circuit, taken from here, and I'm wondering exactly how crucial exact component values are.
I don't have any 220k, 22k, or 4.7k resistors. I'm wondering if I can substitute two 100k in series for the 220k, two 10k for the 22k and a 5.1k for the 4.7k. Of course I could do two 100k and two 10k to make the 220k, but that's 4 resistors in place of one. Will the 20k difference make that much of a...difference?
Also the circuit calls for 1n4148 or equivalent diodes. I have 1n4007. Since those are really just to make a bridge rectifier, could I just use a bridge rectifier component, or just substitute the 1n4007 diodes?
Finally, is a 2N2222 an acceptable substitute in this case for a 2N3904?
AI: There's a basic problem with the circuit around the 2N3904 transistor and how it gets biased (more further down)...
For the resistors yes, and given the applied voltages, two in series will likely be better in terms of voltage rating - read the data sheets of the resistors you want to use because voltage rating is important and so is power rating.
For the diodes, possibly (although the reverse turn off time for the 1N400x series is particularly crappy compared to the 1N4148). However, I expect that a 30 us delay isn't going to make a big deal. Also with using the 1N4007 there is zero doubt it can survive the full voltage applied whereas the 1N4148 would not if mis-connected.
The 2N3904 is only rated at 40 volts from collector to emitter but I'm struggling to see how that device works in the circuit so I think you have a basic problem here with the original circuit. I'm struggling with this probably because it's been a long day but do consider simulating it to see if it works or wait for someone to explain away my doubt.
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H: Determine which wire goes to which connection?
I am repairing a pair of headphones that had one earpiece come out (poor workmanship sadly...). They have two wires and two connections to solder them to, but I don't see an easy way to tell which goes to which.
Is there a way I can do so easily without trying one and having to redo it if it's wrong? Is it possible they can go to either one? One wire is red, one is gold, but I don't see any differentiation on the connection on the earpiece.
Also, should I attempt to remove the old solder (or even melt it and reuse it?) or is it okay in this kind of situation to solder over it?
AI: The audio signal is AC, so soldering the wires on either way should function.
However, the phase of the audio output will depend on the wiring orientation. One of those wires is ground, and the other is the signal. Depending on which way you solder them to the speaker, the speaker cone will either push out or pull in with the same input signal. If you wire it such that the right headphone speaker is pushing out while the left one is pulling in, it might sound wrong. It might also be inaudible. If you can, open up the working side of the headphones and see how they did it there.
If you simply melt the solder that's there, there will be little or no flux to clean any oxides off the metal surfaces, and you may end up with a 'cold' joint. It would be best to add fresh flux, or fresh solder that contains flux.
As far as joints go, this is about as easy as soldering rework can get. Test it before reassembling. Then if you have to reverse the orientation, it will be quite easy.
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H: Finding the operating point of a transistor circuit
I want to find the operating point of this circuit:
where we have an NPN transistor and \$R_V = 47\text{ k}\Omega\$, \$R_C = 1\text{ k}\Omega\$, \$R_E = 4,7\text{ k}\Omega\$, \$\beta = 100 \$,
\$+U_B = 10\text{ V}\$ and \$-U_B = -10\text{ V}\$.
My problem is, that I don't even know what the operating point really is.
In the exercise it says, that the operating point is the pair \$U_{CEA}\$, and \$I_{CA}\$. But there is no letter A in the circuit shown.
So what is the operating point in general, and how would I go about finding it here?
AI: The A probably means 'Absent of any other input'. What you have to find is the Uce, the voltage collector to emitter, and Ic, the collector current. Taken as a pair, they give you the operating point of the transistor.
Let's assume you have sufficient notes on transistors to take the thinnest of hints.
Start by assuming infinite current gain beta, so no base current. Work out what voltages you can, then currents, then more voltages. That gives you a rough cut at the answer.
Now assume finite gain, and work it out properly. Make sure it's fairly close to your rough cut, to check for correctness.
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H: Is there anything wrong with this heat sink design?
If not, is it any better that the conventional fin-based heatsink? It attaches at the bottom, and looks exactly the same in the back. It is supposed to be a passive cooling type heat-sink, therefore there is no fan attached.
AI: It appears to be a bad rendering of a dumb and wasteful design. The air channels are probably too narrow, the material should taper to the tips of the heat exchange areas etc. etc.. It could only be made by wire EDM or some similarly expensive process.
It it almost as if a heatsink was 'designed' by an artist rather than an engineer who understands Nusselt numbers, laminar vs. turbulent flow, etc. etc.
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H: Design Asynchronous State Machine using T flip-flop
There is this question that i don't really get the solution:
Design a pulse-mode circuit having two input lines x1 and x2, and one output line z. The circuit should produce an output pulse coincide with the last input pulse in the sequence x1-x2-x2. No other input sequence should produce an output pulse.
Use T-FF: T = 1, C acts as input
this is the solution that the book gives:
First, I don't really get the part in step 4 and 5 where do they get the table with Transition and C?
second,I don't really understand step 6 where you implement the equation, Why do we have to use negative edge triggered T flip-flop? why not positive edge triggered T flip-flop?
thank you in advance :)
AI: OK, I hope this helps. I think the confusion for C1,C2 comes from going directly from the state diagram to the Karnaugh map. Here is a state table showing how you go from one state to the next.
Notice from state B(01) X1 causes the machine to go to A(00). That means [C1,C2] must be [0,1]. Only Y2 must toggle. From B(01) X2 causes the machine to go to C(10). This means [C1,C2] must be [1,1]. The both must toggle. Form this table you should be able to see how the values of C1 and C2 are determined. Now If you take the C1 columns and put them together you get the C1 Karnaugh map from the answer. Similarly put the C2 columns together to get the C2 Karnaugh map.
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H: Are there chips encoded with fixed 8bit values?
I am assembling a few data acquisition fixtures and would like my software to be able to identify the fixtures programatically. I have a breadboard that I can use for basic circuits. The DUT signals come into the fixture, can interact with the circuits on the breadboard, then from there it is connected to the DAQ hardware.
The DAQ hardware has 16 available digital IO lines I can use. At first I thought I would just pull some of the pins up and down with jumpers to put an 8bit identifier but then I thought it would be cool if there were chips that presented a fixed value.
To clarify, I would like to direct connect a chips pins to my DAQ digital IO pins so that I can read a value encoded in the chip. This is to prevent someone tampering with it and generally raise the level of security for the solution.
I searched for such a chip but cannot find one. I do not want anything I need to program or that requires significant support circuitry; just looking for a super simple, single chip solution to put a fixed value on my digital lines.
BTW, in case it's not obvious: I'm an electronics newbie... big time.
AI: Usually when we need something like that, an EEPROM is used. It's convenient to be able to change the numbers at will then lock them. Some EEPROMs are available pre-programmed with unique numbers such as MAC addresses.
For a few bits, these things are still available (called DIP shunts).
To program them to any of the 255 other possible combinations, you poke through the hole and break the connection as so:
Of course you could always use a DIP switch, but that would be easier to change.
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H: why ultrasonic module sends out 8 cycles ? and , why the trigger pulse is 10us?
this is the operation of the ultarsonic module HC-sr04 :
The timing diagram of HC-SR04 is shown. To start measurement, Trig of
SR04 must receive a pulse of high (5V) for at least 10us, this will
initiate the sensor will transmit out 8 cycle of ultrasonic burst at
40kHz and wait for the reflected ultrasonic burst. When the sensor
detected ultrasonic from receiver, it will set the Echo pin to high
(5V) and delay for a period (width) which proportion to distance. To
obtain the distance, measure the width (Ton) of Echo pin.
is the number of 8 cycles related to the microcontroller of the module ,I think that but why?
don't forget the second question why the trigger is 10us ?
AI: The receiver and transmitter are mechanically tuned to the frequency, so it will take a few cycles for the amplitude to ring up to the maximum (the transmitter will ring up in amplitude as you drive it, and the receiver needs to 'hear' a number of cycles before it reaches full output, so you better drive it for enough cycles). It's also of no advantage to have too long a sequence of cycles.
That is why the designer programmed the microcontroller to output 8 cycles in particular, in answer to your first question.
Read any reference on 2nd order systems for an explanation of Q and resonance. The center frequency of this mechanical resonance is typically specified to +/- 1kHz (+/-2.5%). Here is a typical one:
Note the ringing specification of 1.2ms for this product, which implies a much higher Q. It is a waterproof type and has too high a Q for good results in a ranging application. You can find more information in this answer.
In answer to your second question, the 10us is probably to allow the firmware in the microcontroller to recognize the input. If they don't use an interrupt but rather a tight loop it might take that long to traverse the loop so a shorter pulse might be missed some of the time.
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H: Why I need those capacitors in USB 3.0 transmission lines?
In this picture (originally posted in this thread), there are capacitors called "AC Capacitor". Why do I need those capacitors? It is a USB 3.0 SuperSpeed connection, so it would not be an AC-Powered device.
AI: While it's powered by DC, the signals are high frequency differential pairs on transformers to prevent the need for dc coupled devices. The AC capacitors couple the differential pairs between the transceiver and receiver, and managed the dc bias blocking.
See the answer by Some-Hardware-Guy on AC-coupling capacitors for high-speed differential interfaces for a full explanation.
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H: Using an earth bonding plug for grounding server rack enclosure
I have a 18U server rack enclosure in my 4th storey home and want to connect the metal frame to electrical earth. The rails are already bonded to the frame with 2 wires by the manufacturer.
My wall sockets are 3 pin plugs with earth, live and neutral wiring. Would it be safe to use something like an Earth Bonding Plug for grounding the enclosure frame?
AI: No!
That plug has a 1MEG series resistance to earth that allows static charge accumulation to bleed away to earth. This prevents you from destroying a component during handling with a static shock from your body to the chip. This resistor will explode if there is a fault to the chassis that causes large fault current to flow. Then the chassis could be live and floating. If you touch it, you are liable to die.
The earth connection is for safety. It must handle large fault currents to ensure that the circuit breaker protecting the circuit has time to trip.
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H: Which transistor should I use in my circuit?
I've made a rudimentary flood alarm (a circuit that rings a buzzer when the water in a reservoir is full) using a 9V battery and a cheap Chinese buzzer that came without a current rating. All I know is that it operates between 6V-12V. There's no power rating on it either, and my multimeter is broken so I can't measure the current myself. There are two parts to the circuit I'm trying to modify it into.
Connect a small low-heat capacity resistor in series with the
battery (to limit current) and put the two open ends of the circuit
as probes in the water, so that the probes are connected by the
water, the circuit is completed. I want this part to act as the
control voltage, applied to the base of the NPN transistor (since I
want the circuit to close only when the HIGH signal is applied to
the base).
I also want to supply the transistor with 9V which is passed only when the voltage at the base is also applied (i.e., circuit is complete due to the water).
Here's a basic circuit diagram of what I'm trying to create:
I'm new to this, and have no idea what transistor to use. What should be the value of the resistor? Also, do I need to use any other parts to ensure the proper behavior? Please advise.
Also, is this circuit feasible for long term use? When the battery voltage degrades, will the transistor be able to adapt? I can't use an AC source coupled with a 7809 IC as I want this to be battery operated. Please suggest a better way if need be.
AI: Here is a bit better way:
simulate this circuit – Schematic created using CircuitLab
If the probe resistance drops below some tens of M ohms, the beeper will sound. No more than 9uA flows through the probe so electrolysis is minimal. This will work with beepers up to at least a couple hundred mA, above that and Q2 may get too hot while partly on for a TO-92, so you could use a TIP31 or similar TO-220 part (just for Q1).
C1 is to keep the battery voltage more steady as the battery ages (under varying load during the audio frequency beeping cycle), C2 prevents RFI from triggering the beeper. R4 and R2 prevent leakage from triggering the beepr and control the maximum resistance that will trigger the beeper. R1 limits the probe current to prevent electrolysis or overdriving the base of Q1.
Q1 and Q2 are in a Darlington configuration which provides a theoretical current gain of perhaps 50,000, which is tamed somewhat by R2/R4.
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H: What is the difference between RS-232 and TTL UART?
I always need to communicate with the TTL UART port on the MCU with a computer. When I talked about that, people always refer the UART port as an RS-232 port. Are they correct? If not, what is the difference between them?
Also, can I use a RS-232-to-USB converter for a TTL UART port?
AI: The port on your USB<->RS-232 converter will output something like +/-9V and can accept +/-25V or short circuit without damage.
The UART on your MCU uses logic level (0V/3.3V or 0V/5V typically). Applying less than 0V or more than Vcc can destroy the MCU chip.
Also the logic levels are inverted between the two types (excepting an option on a very few MCUs).
To bidirectionally invert and convert between the UART levels and RS-232 levels one would typically use a chip such as the MAX232 (for 5V logic). The MAX232 also generates its own +/-9V supplies from a single +5V supply using a charge pump voltage doubler.
TL;DR:
No you cannot use the USB-RS-232 (aka USB-serial) cable to connect the two. There are USB-TTL Serial converters available cheaply. There are some gotchas with the cheapest Chinese ones as far as 3.3V operation goes, be sure to research it a bit. Adafruit carries such devices for $10. I think you can find them at Digikey and other sources as well.
Since the hardware interface is not defined by any standard at the MCU end they are typically furnished with uncommitted fly wires with female terminals to mate with 0.025" square pins as you would find on a 0.1" pitch header. I bought half a dozen similar devices for my firmware programmer and she's been using them to talk to various development boards.
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H: Sending a pulse from alternating constant output
I have an overlapping XOR gate which alternated from 0 to 1 whenever one of the inputs is turned on. Basically, it's off when there are even high input and on when there are odd high input. The problem with this is I'm only able to send a pulse when the said overlapping XOR gate goes from low to high. How can I also send a pulse when the output goes from low to high. I tried simulating using resistor capacitor but it always fails and I'm not sure why.
AI: Sounds like you need an XOR gate edge detector: -
I would use a schmitt trigger version of the XOR gate.
For reference, maybe you have used an OR or AND gate and this is why you don't get pulses on both edge transitions: -
Added section - here's the circuit the OP posted as a comment: -
And my advice was "You don't need the inverters but you do need pull-down resistors on gate inputs connected to switches. You need pull-down resistors because without them the inputs would float to an unknown value rendering the circuit unstable and unpredictable."
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H: What kind USB Cable connector of connector is this?
Which connector is this? It has a USB-A Male on one side, but what is the other connector on the right?
AI: It's a variant of 1S connectors typically used for Lipo battery chargers
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H: Analog Dimmer Circuit Analysis
I am trying to analyse the basic circuit of a dimmer. I don't have much experience in AC circuits, so I am not sure how do I need to proceed. My circuit is the next:
I have something like this:
I have found some interesting relationships. Like the output vrms based on the firing angle θ:
Using:
$$ V_{rms} = \sqrt{ \frac{1}{T} \int_0^T v^2(t) dt } $$ we obtain:
$$ V_{rms} = \sqrt{ \frac{1}{ \pi } [ \int_0^{ \theta } 0 d(\omega t) + \int_{\theta}^{ \pi} Sin^2(\omega t) d(\omega t) ] } = \sqrt{ \frac{ V_{max}^2 }{ \pi} \int_{\theta}^{ \pi} \frac{1}{2} [1-Cos(2 \omega t) d(\omega t)]} = \sqrt{ \frac{V_{max}^2}{2 \pi} (\omega t-\frac{Sin(2 \omega t)}{2} ) \Big|_{\theta}^{\pi}} = \sqrt{ \frac{V_{max}^2}{2 \pi} [ \pi-\frac{1}{2}Sin(2 \pi) - ( \theta - \frac{1}{2}Sin(2 \theta) ) ]} = \sqrt{ \frac{V_{max}^2}{2 \pi} ( \pi \theta + \frac{Sin(2 \theta)}{2} ) } = V_{max} \sqrt{ \frac{1}{2} - \frac{\theta}{2 \pi} + \frac{Sin(2 \theta)}{4 \pi} } $$
But I don't know how to obtain the phase angle based on the values of the resistance, the capacitance and the load
AI: Solution is all but trivial.
A rather good starting point would be doing the following assumptions valid for a resistive load:
1)Each cycle will start with C1 fully discharged and open TRIAC U2.
2)Load resistance is much lower than R3+RV1, hence you will have full half sine mains voltage across TRIAC.
3)DIAC is open circuit untill its breakover voltage VBO (approx 30V) is reached.
4)Now we have to write the transient of C1 being fed with sine voltage via R3+RV1.
5)When vc(t)=VBO TRIAC is fired, capacitor is discharged and your load is being fed.
So KVL to the source, R, C mesh would be
$$V_\text{max}\sin\omega t=v_\text{C}(t)+RC\,\frac{\text{d}\,v_\text{C}(t)}{\text{dt}}$$
the usual first order ODE to be solved in \$v_\text{C}(0)=0\$ boundary (or more generally some initial voltage as per Spehro's comment).
This is known to have solution sum of its general \$\breve{v}_\text{C}(t)=A\,\text{e}^{-t/\tau}\quad\tau=RC\$
and particular one \$\hat{v}_\text{C}(t)=\frac{V_\text{max}}{\sqrt{1+\omega^2\tau^2}}\sin\left(\omega t- \arctan(\omega\, \tau)\,\right)\$
Combining them in the above constraint and applying a little trigo gives
$$v_\text{C}(t)=\frac{V_\text{max}}{\sqrt{1+\omega^2\tau^2}}\sin\left(\omega t- \arctan(\omega\, \tau)\,\right)+\frac{V_\text{max}\,\omega\, \tau}{1+\omega^2\tau^2}\text{e}^{-t/\tau}$$
which equated to DIAC break over would give TRIAC on time.
$$\frac{V_\text{BO}}{V_\text{max}}=\frac{\sin(\omega\, t_\text{on}- \arctan(\omega\, \tau)\,)}{\sqrt{1+\omega^2\tau^2}}+\frac{\omega\,\tau\,\text{e}^{-t_\text{on}/\tau}}{1+\omega^2\tau^2}$$
What we really understand from the above is that's indeed job for a numeric solutor.
Edit: one sign fixed upon @Delfin suggestion.
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H: Why change microcontroller's PWM frequency?
What are exactly the pros/cons of changing the PWM frequency?
I don't think I need to change any PWM frequency at this very moment - but since I don't know the benefits of doing it, how can I really know if it's useful for me?
I'd like a general answer (which I and other people reading this post can apply in different situations), but if someone wants some data to answer, here are those of the project I'm working on at the moment:
ATmega328 microcnotroller @16Mhz (it stands alone, it's not in an Arduino board)
4 independent small brushed motors, each with a propeller (propeller's diameter: around 6 cm), on pins 3,5,6,11, controlled by a BUK9840-55 trasnsistor (datasheet)
a simple RF receiver is placed nearby and needs to receive a 433MHz
signal (the RF comminication is quite slow (500bits/sec), and doesn't
need to be very reliable).
EDIT: how does the PWM speed influence the RF communication?
AI: PWM units, typically, work the following way, or equivalent¹.
Set up:
an initial output value, ie. either high or low and
the "counter reset value", to which the counter is reset after reaching
the "counter maximum value", as well as
the "counter flip value", where the output state is toggled
After that, you just let the counter run – for example, you might set
initial state high,
reset value 0,
max value 100,
flip threshold 25
Then your counter would start at 0, and increment once every clock cycle, and at 25, the output would be set to low, until the counter reaches 100 and is reset to 0. That way, the output would be high for 25 time units, and low for 75 – a duty cycle of \$\frac14=25\%\$.
Now, the PWM frequency is typically defined as the time between the reset and reaching the maximum.
So, this inherently is one aspect of choosing a PWM frequency: if there's 100 time units (which, by the way, are typically clock ticks of something like the CPU clock divided by some \$N\$), your duty cycle "granularity" cannot be better than 1%.
On the other hand, if you let's say set the max value to 106, then you might get super nice resolution on the duty cycle, but that doesn't help you, because now the output might be low and high for so long that whatever you drive with the PWM simply sees "on" and "off", unless you go through great lengths (build a mechanically large low-pass filter) to "smoothen" things out, and then you'd lose all ability to quickly adjust the duty cycle (because the filter will also smoothen out your adjusting).
PWMs are used for very different things – for example, to generate an analog voltage, as mentioned above, by low-pass filtering. In that case, using a high frequency might be beneficial, because your low-pass filter, needing to cut off the PWM frequency, is much easier to build when that frequency is high. On the other hand, in circuits where you work with sensitive analog voltages, having a fastly switching PWM signal is dangerous, due to that signal potentially coupling over.
Other uses are, and that's probably what your motor does internally, more digital: the PWM simply controls for how long something is switched on or off, for example, the internal power supply in DC brushless motors (which are, in fact, 3-phase AC motors that have a supply that generates three sine signals from the DC voltage it takes). For these applications, as said, the PWM frequency mustn't be too low, because then your motor will stop, start, stop,…, but it mustn't be higher than the frequencies the internal supply uses to generate the AC voltages.
Yet other uses are actually signal generation usages – for example, assume you have a microcontroller with a CPU clock of 16 MHz, and you want to generate a set of different frequencies (for example, you have a Modem that uses frequency shifting as modulation, so one frequency means "0", the other one means "1") – in that application, you might use a fixed duty cycle, and what you're really interested in is the PWM frequency!
There's also devices that communicate measurement values by PWM duty cycle – or take PWM duty cycle as input, for example these "neopixels" that you might have heard of. Of course, their interface controller has a specific timing range, so you have to configure your PWM frequency to make things work.
¹ this, for example, assumes you can both set the upper and lower limit, and that the counter counts up – there's no reason that all of that is true, you can implement PWM by counting down, or by not having a variable upper limit, but that's details.
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H: Two step up converters to build dual supply with a virtual ground
I would like to amplify a difference signal from two electret microphones.
I would like to use an instrumentation amplifier with dual supply (AD620 for testing, probably INA103 for the final product).
Using dual power supply close to the maximum rating e.g -15V and +15 V will allow higher gain, and higher gain will result in much higher CMRR. I need high CMRR because the common mode signal will be far more louder than the differential signal.
I'll use a factory calibrated instrumentation amplifier instead of a simple differential amplifier for the same reason.
In the environment where this will be used, there is only a (noisy) +12 V power supply. My idea is to use to DC/DC converters, create +15 V and +30 V, and use the middle point as a new ground.
Suppose that the whole circuit will be isolated from the common ground, what are the disadvantages of using 0, +15, +30 V instead of -15, 0, 15 V?
(The DC/DC converters can do at least 1000 mA, much more than I need)
UPDATE: modified the requirements to +/-5V for making the design simpler. Would this circuit work, or should I use 7905 instead of 7805? I'm not sure.
simulate this circuit – Schematic created using CircuitLab
AI: While this is certainly a viable design, it might turn out more frustrating than other approaches:
The "virtual" ground at +15 V is actually the output voltage of your "lower" step-up converter instead of the usually very well-grounded actual ground. That means that unlike "true" dual supplies, your approach means that the stability and accuracy of your power supply defines the 0V point – which isn't free of effect on your measurement. You can of course stabilize that by overdimensioning that supply, making sure that there's no oscillation of energy between the two supplies, large decoupling networks...
But in the end, you want to not go through extra lengths in an attempt to make a circuit less complicated or error prone.
Really, let's have a look at what we're talking about. This is the CMR curve from the AD620 datasheet:
So we're talking about the difference between 90 dB CMR and let's say 130 dB CMR, or rather 80 dB and 100 dB for a 1 kHz signal. 80dB+ are definitively impressive rejections already (assume you have a common-mode voltage of 1 V, how much of that do you get on the output? How far is that above Johnson-Nyquist thermal noise voltage over your next stage's input resistance?), and I'd be very surprised if adding a second supply to your problem wouldn't introduce more noise than you gain rejection …
Really, for least-noise, high rejection, not using your 12V SMPS to use two further SMPSes to generate a dual supply might be a pretty good idea, even cost-wise.
However, you say there's only one noisy 12V supply – so try to add as little additional noise as possible.
I'd personally go for something relatively simple, maybe a flyback supply where the secondary side has a center tap to provide your virtual ground, and use relatively massive capacitors to flatten the output voltage, followed by positive and negative linear voltage regulators (negative ones are a bit harder to get, but do exist).
Or, really, generate e.g. +10 V from your +12 V using a positive regulator, and a well-regulated +5 V – and really check if your system really benefits from the additional CMR in a real-world environment.
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H: Differential amplifier with differential output and common-mode shift
Summary: I would like to build a differential amplifier with differential output, but shift the common mode to a different level from the original.
My current knowledge takes me this far: Take the traditional 3-opamp instrumentation amplifier, like the one in this image:
Now if you take the left two opamps without the third, those already give you almost what I want, that is, amplify the differential input and give a differential output. The only problem is it preserves the common-mode of the input. Adding the 3rd opamp on the right, it is easy to shift the CM by biasing its ground (in fact this is what most single-chip instr. amplifiers do when they provide a Vbias pin), but the output of the circuit is now single-ended.
So what is the best way of keeping both the differential output and the CM-shift? One way is, I guess, to take only the left two opamps of the above instrumentation amplifier, and shift the ground of each separately.
Another option that comes to my mind is to take only the left two opamps again, and (using an example when I want to halve the CM) use twice the gain as needed, and then divide each output by 2.
Unfortunately both of these solutions require more (in quantity) highly matched resistors with low TCR (I'm trying to keep temperature drift of the circuit very low), and those are bloody expensive.
So how would you go about this problem? Maybe taking an instrumentation amplifier is the wrong start? Is one of my above solutions the "standard" way of doing this, or are there better circuits for this purpose?
EDIT: Clarification on matching resistors: What I mean is to match them in TCR, because I am aiming to minimize temperature drift. This means I need to match resistors in TCR, not in absolute value, so that when they drift due to temperature, they will keep their original ratios. Actually I am uninterested in matching absolute values (almost, I still need a little bit of matching to maintain CMRR), for two reasons: 1) a mismatch in absolute value causes offset and gain errors, both of which are easy to calibrate out at system level. Measuring and correcting temperature drift is a lot more difficult. 2) Most of the offset errors will be non-existent anyway without even calibrating, because this will be a frontend to a sensor, and offset errors will cancel out due to AC excitation of the sensor. Anyway: closely TCR-matched resistors are expensive (easily more expensive than precision opamps), so I want to minimize their use.
AI: This does what the OP wanted, a differential output around a defined output common mode, with no more, and in fact fewer, precision resistors.
simulate this circuit – Schematic created using CircuitLab
If the common mode voltage does not match the input at Vcm, then OA3 drives an input voltage into both inverting inputs, with the same gain, which will cause both output voltages to move the same amount in the same direction, maintaining the existing differential gain, but shifting the common mode until there is no error.
Stability may be an issue, as there are two amps in a feedback loop. I suspect it would be easy to stabilise by clobbering the OA3 bandwidth, and/or speeding up OA1/2 a little with a small C across R3 and R5, which may or may not be desirable from the differential behaviour point of view.
Note that the only resistors that need to be matched are R1 and R2, which set the two output terminals to be equally disposed around Vcm. The differential gain is just (R3+R4+R5+R6)/(R4+R6), it does not need matched resistors, these can be four arbitrary value resistors, subject to getting the correct gain of course. I emphasise that fact by putting 4 unmatched values in the diagram for those resistors. The diff gain is 7 (21k/7k), with the outputs exactly disposed around Vcm because of R1==R2, and OA3. Try it!
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H: bypassing vs. decoupling capacitors
I often see those two terms explicitly used as synonyms, but sometimes from the context I would say they're not.
So, is a bypass capacitor exactly the same as a decoupling capacitor?
AI: Yes, decoupling capacitor and bypass capacitor are the same thing.
These refer to a capacitor located physically close to something drawing power. The capacitor holds the local voltage up for the short time until the current feed can catch up. Due to inevitable inductance of longer lines back to the power supply, the current in these lines takes a little while to change. The purpose of a bypass or decoupling capacitor is to provide the little extra energy during sudden current demands until more current can be supplied from further away.
Since decoupling or bypassing is a high frequency issue, the caps for this purpose must be chosen for low impedance at high frequencies. Their bulk storage capability is not of much importance. In a practical sense, this means they are usually ceramic.
In ye olde days (1980s, or even back into the pleistocene like the 1970s), such capacitors were usually 100 nF ceramic disks. That was about the largest ceramic that was small and affordable. Nowadays, SMD multi-layer ceramic 1 µF capacitors have better characteristics, and are cheap and readily available.
For ordinary use, like around a microcontroller or digital chips connected to one, 1 µF ceramic is a good choice. If you're doing RF, then you have to look at the capacitor impedance charts more carefully. I once used a specific model of 100 pF cap for bypassing a RF chip because they had lower impedance at the frequency of interest than other caps with higher values.
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H: Charge 3.7 Li-ion Battery with 5V battery charger?
Is it possible/save to charge a 3.7V Li-ion Battery with a 5V battery charger like this one: https://www.amazon.de/gp/product/B0191EVW0C/ref=oh_aui_detailpage_o00_s00?ie=UTF8&psc=1
Additional question: Would this be sufficient for an Arduino Pro Mini 5V using the VCC Pin?
Thanks!
AI: Yes, this charger is okay for a single 3,6-4,2V li-ion cell. An ATmega328 will run fine at this voltage when you obey the clock speed limit (section 29.3 of the datasheet). Make sure to measure battery voltage using the Arduino, so you don't discharge the battery too deep.
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H: Consequences of inrush current out of specifications in AC/DC power supply
What would be the consequence of an inrush current bigger than acceptable limits at the output of a AC/DC power supply? We are currently using a MeanWell model (GST160A15) whose datasheet reports a maximum inrush current of 120A. We are using the power supply to power a control card. We just figured out that the inrush current flowing into the control card is in excess of 175A with a following negative pulse of ca 200A. The whole is happening into the Mhz frequency range. The measurements where taken with a Tektronix 100 Mhz oscilloscope and a shunt resistor - because the current measuring instrument we have just arrives in the range of 500 KHz.
We noticed that 1-2 power supplies out of 15 got broken in a time span of 6 months. Could the failures be entirely due to the inrush current over specs? Or are they other possible reasons? Please look at the attached measurement.
AI: The inrush current of the GST160A15 applies to its inputs i.e. how big the surge of current it might take when it is initially powered. This isn't an output spec for anything connected to it's outputs; it's an input specification.
The inrush into the control card may well be what you said but that does not relate to what the Meanwell power supply takes from its power source.
Could the failures be entirely due to the inrush current over specs?
No but you need to read the data sheet carefully about what current may damage the Meanwell supply due to an excessive load on the output however, I suspect that it protects itself.
Or are they other possible reasons?
Yes, possibly other reasons that may not be at all related to the observations posted in your question.
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H: output voltage of an operational amplifier
A student designs an electronic sensor to monitor whether the temperature in a refrigerator
is above or below a particular value. The circuit is shown below.
Question: An operational amplifier (op-amp) is used as the processing unit. Describe the function
of this processing unit.
Solution: gives a high or a low output / +5 V or –5 V output
dependent on which of the inputs is at a higher potential
My enquiry: Can the output value be between +5 V to -5 V in this case? Or should it only be saturated( +5V or -5V) because this is an ideal op-amp? Or should it be saturated because of other reasons such as: there is no negative feedback to reduce gain. Hence, it has to be saturated. So that, only types of circuits (op-amps), which can be both saturated and non-saturated are those with negative feedback -only inverting and non-inverting amplifiers.
To be more specific, my question is that which type of circuit can the output voltage be saturated or non-saturated.
Thank you very much for your help. My writing is quite poor. If you don't understand anything, please leave a comment. I would try my best to clarify.><
AI: Ideally, the output will always be saturated. This is because a ideal opamp has infinite gain.
Back here in the real world, there are some issues with this circuit:
There is always some inevitable noise on any signal. When the temperature is close to the threshold, then this noise will cause the temperature signal to go back and forth between being above and below the threshold. This will make the opamp output appear to be at a in-between level.
If the noise is fast enough, the opamp output will actually be at a in-between level most of the time due to the finite output voltage slew rate. Put another way, the opamp can't go instantly from full high to full low. If you keep jerking it around faster than it can react to, it will spend most of its time going back and forth without getting to either extreme.
To be a useful circuit, there really should be some hysteresis. This is a little positive feedback. It creates a little dead band around the threshold. For example, if the threshold is set to 0 V, then it might take +100 mV to go high when low, then -100 mV to go low once high. The size of the hystersis band should be enough to cover most ordinary noise. That prevents the case described in #1, above.
There should be a resistor in series with the opamp output, or each LED. If the opamp were perfect, it would drive the output to either +5 V or -5V. That would blow up the LEDs. With a real opamp, you don't know what might get damaged.
The right resistor allows for the desired current thru the LEDs. For example, let's say these are typical green LEDs that drop 2.1 V and you want to run them at 10 mA. When the opamp puts out 5 V, then the resistor is dropping 2.9 V. From Ohm's law, (2.9 V)/(10 mA) = 290 Ω. The common value of 300 Ω would be a reasonable choice then.
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H: Compliance test mode in Gen1/2 and Gen3
I'm looking the mindshare book for TX compliance test.
Somehow I'm confused about the method to enter the Polling.Compliance substate.
In Gen1/2, it seems that of the transmitter detects a 50 Ohm load, it'll enter the compliance substate.
However, in Gen3, I can't find such condition.
Can anyone help me on this?
Thanks.
AI: The Detect state machine (in detect.detect) looks for a valid link partner electrically by (effectively) measuring the load impedance on a transmitter port.
If this is successful, the state machine will enter the polling state machine where it will start transmitting (and hopefully receiving) TS1 and TS2 ordered sets. This is true for all versions of PCI express.
The details of Gen 3 (different speed capabilities, different line coding) are done later in the sequence.
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H: Confusion over current divider rule
I asked a question here about calculating the resistance an unknown resistor using superposition.
As part of the answer I was given $$I_1=I_3\frac{R_2+R_i}{R_1+R_2+R_i}$$ and $$I_2=I_3\frac{R_1}{R_1+R_2+R_i}$$ as the third case of the superposition method involving a current source.
My confusion is that firstly, I understood that the current divider rule was $$\frac{I_0}{I_n}=\frac{R_{sum}}{R_n}$$ and the above answer is opposite.
Secondly I see \$R_1\$ in parallel with \$R_2+R_i\$ so I don't understand why $$I_1=I_3\frac{R_2+R_i}{R_1+R_2+R_i}$$
I have the feeling there's something that i have fundamentally misunderstood.
My understanding is $$I_n=\frac{V_n}{R_n}$$ and the voltage in a parallel circuit is $$V_n=V_{total}=R_{total}\cdot I_{total}$$ so that $$I_n=\frac{R_{total}\cdot I_{total}}{R_n}$$ which is just what is says here. What people are telling me on here seems to be that the resistance in the other branch divided by the total resistance is equal to the resistance I'm looking for.
I've looked for proofs, but I seem to just find the formula which I knew to begin with, which I'm being told here is wrong. What am I missing?
AI: For two resistors R1 and R2 in parallel the current divider rule is
$$
I_1 = I \cdot \frac{R_2}{R1+R_2}
$$
where I is the total current and I1 the current through R1.
For two resistors the current through one resistor is the total current times the current of the other resistor divided by the sum of the resistors.
The proof is trivial but here it is:
For two parallel resistors with the same voltage V across them the current through one of them is given by
$$
I_1 = \frac{V}{R_1} = I \cdot \frac{R_1 R_2}{R_1 + R_2} \cdot \frac{1}{R_1}= I \cdot \frac{R_2}{R_1 + R_2}
$$
since V can be expressed as the product of the total current I times the resistance of R1 and R2 in parallel.
In your first example the total current is I3. The current I1 flows through R1, the other resistor is R2+Ri, the sum is R1+R2+Ri which results in
$$I_1=I_3\frac{R_2+R_i}{R_1+R_2+R_i}$$
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H: Power Control in CDMA
It is commonly known that power control in CDMA is needed since all users/base stations transmit on the same frequency, and power control would help to limit the interference received at the base station.
My question is more fundamental - Why is it a problem that the various incoming signals (at the base station) are received with different power? Can we not distinguish each signal as per the Spreading Code or Walsh Code?
AI: The various codes in each handset are not fully orthogonal so some interference occurs between the received signals at the base-station. The signal from the handset varies with distance from the base station and there are other real-world imperfections such as multi-path, building attenuation, intermodulation etc.
The range of those attenuations is more than the signal to interference ratio of the coding so it is useful to adjust the power of the handset to normalize the signals at the base station so that there is a lower ratio between the weakest handset signal and the strongest.
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H: How to store 8 bit character in 32 bit Data Flash memory?
Is it possible to store 8 bit character to 32 bit Internal Data Flash in the Microcontroller by just using only 8 bit of space for each bytes?,by using a combination of 4 bytes which can be also recovered as individual bytes later.
I'm using Nuc240 (ARM-M0) Microcontoller with 32 bit Data Flash and 512 bytes erase limit,read write limit is 32 bit.
Please explain a code template if possible.
AI: Yes, by either array or structure.
char memory [4] = { 'a', 'b', 'c', 'd' }; // Uses 4-bytes (32-bits)
// memory [0] = 'a';
// memory [1] = 'b';
// memory [2] = 'c';
// memory [3] = 'd';
// ... store 'memory' in internal flash memory ...
Or
typedef struct
{
char byte_0;
char byte_1;
char byte_2;
char byte_3;
} memory_t;
memory_t memory; // Uses 4-bytes (32-bits );
memory.byte_0 = 'a';
memory.byte_1 = 'b';
memory.byte_2 = 'c';
memory.byte_3 = 'd';
// ... store 'memory' in internal flash memory ...
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H: 2D parity code error detection/correction?
If we assume the following: the received bits were encoded using a 2-D even-parity code, what is min #of error is there.
I am a little bit confused , it is clear that the third column has an error and ( second , fourth and sixth ) rows have errors.
For example, If we change the bit location(2,3) the third column and second row will indicate there are no errors and we lift with only two rows (fourth and sixth) with no column. What can I say about this , the minimum # of error in this case?
Can someone help me with this? Thank you
AI: With this kind of parity only a single bit error can be corrected. So not a single error can be corrected in this example.
Here one column and three rows contain an error. To rows could be corrected by flipping two bits in any arbitrary row (where they intersect with the two rows that contain an error), it wouldn't change their parity bit. The remaining error could be fixed at the intersection of the row and column with the remaining error.
However, since the choice of the first column is arbitrary, the errors cannot be corrected.
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H: in host to device communication protocol, what does high and low mean?
I'm trying to learn about the PS/2 protocol from here. At about 4:00 he talks about low and high values.
This part is to let the host send data to the device but the clock should come from the device.
My question is what is zero, what is one and what is z (high impedance) in this context?
Meaning; when he says "high" or "release the clock" for example, does he mean one or Z? (I'm thinking Z)
AI: I am not going to watch a 16 minute video, but I do know the PS/2 interface.
It uses open collector (drain) outputs and pullups to +5V, so high-Z is the same as '1' and the same as +5.0V. Low is 0V.
The outputs can only pull down to 0V and are never 'driven' to +5V, rather an external pullup resistor pulls the output logic state up to +5 when the output goes high impedance. Picture below from here
It's possible to simulate open-collector outputs with most micros by switching the port pin from an output with '0' state to an input, and never having it as an output with '1' state.
The distinction between 'release' and '1' is more of logical distinction than a description of what is happening in the hardware of the physical interface. When you want to transmit a '1' you allow it to go to high. When you are finished with sending data you 'release' it (allow it to go high) so that something else (the other end of the communication) can use it.
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H: cable size vs current rating
I would like to know if using two 2.5mm² cables has a greater current rating than one 6mm² cable. The ratio of CSA is 2.4x and so I would have expected to need three 2.5mm² cables. However, I then looked at the actual current ratings tables for different cable sizes and see that 2.5mm² is rated at 18.5A while 6mm² is only at 32A. Hence presumably two 2.5mm² cables would have a joint rating of 37A and so exceed the 6mm² cable.
I have read other posts that the deciding factor is the amount of copper, which would suggest that three 2.5mm² cables are needed.
However based on the current rating tables, only two cables are needed.
So I don't understand why the tables contradict the advice in posts on this site.
I would like to know if I have understood the tables correctly, or if my logic is flawed.
Also, my cable is single strand. Should I use multiple strand, as this seems to be used in the tables?
Source: http://www.diydoctor.org.uk/projects/cablesizes.htm
AI: When comparing single to multiple cables current capability you need to consider that multiple cables will run hotter (for the same current capability) than does a single cable in free air. As soon as you see multiple cable bundles, you will see the current rating being reduced because of thermal restrictions.
Get a good Cable chart like this ...Engineering Toolbox is your friend.
And a cable areas conversion like this
If you are in EU then I'm sure there are similar cable company or website that cover mm cabling.
Adding this link to an excellent treatise on the de-rating of bundled cables due to increase in thermal resistivity.
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H: Four state switching
I'm building a light indicator system with four states (All lights off, Red light on, Amber light on, and Green light on). I want to be able to go from one state to the next with just one button press, which rules out having individual on/off switches for each light, and also a rotary switch because going from Green back to Off would require switching on Amber and Red. A momentary push button is the preferred option.
I've been looking at Set/Reset Latches with NAND gates similar to the "Sequential Logic -> Flip-Flips -> SR Flip-Flop" example on http://www.falstad.com/circuit/. This example uses two two-input NAND gates where one input is pulled high and grounded on button press, the other input is tied to the output of the other NAND gate. To get this to work with four states I was thinking about using two 4012 Dual 4-input NAND gate CMOS integrated circuits, but the wiring becomes significantly more complicated compared to using a simple rotary switch.
Is there a simple way to achieve this functionality, with a type of mechanical switch or an integrated circuit that just takes the 4 inputs and has 4 outputs?
AI: You could use a CD4022 Octal Counter, with fully decoded outputs 0 to 7, and tie output 4 to RESET so it wraps around after 4 counts instead of 8. It is available in a 14-pin DIP from Digi-Key for 52 cents. You will want to provid some debounce circuitry on the input so it advances only once per push-button press.
Since I am using the 4000B CMOS family, the circuit will work with any VCC voltage from about 5V to 18V (5V minimum, not 3V to allow a little headroom for the LEDs). For this reason I haven't listed any values for R4 through R6, as they will depend on VCC and the LEDs chosen.
If you want to use a SPST button instead of SPDT, you will need a different debounce circuit. There are hundreds of references on the web for this. A good one is here, which starts off describing the SR latch used here, as well as a reliable circuit for use with a SPST switch.
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H: capacitor voltage ripple in buck converter
I am struggling with output voltage ripple calculation of the buck converter below. Firstly, I don't understand the following statement from the lecture. Can anyone explain it?
If the capacitor voltage ripple is small, then essentially all of the
ac component of inductor current flows through the capacitor.
The images are from the lecture here (pages 39-40).
AI: If the capacitor voltage ripple is small, then essentially all of the
ac component of inductor current flows through the capacitor.
Paint a scenario and examine the currents: -
Ripple is 50 mV p-p, nominally triangular and 100 kHz
Output load is 10 ohm
Output capacitor is 100 uF
The AC ripple current through the load is simply 5 mA p-p - this is the baseline for comparison. The RMS is the peak value (2.5 mA) x 0.577 = 1.443 mA
For the capacitor, we have to calculate the slope of the voltage. It rises 50 mV in 5 us so that's a rate of 10 kV/s. Going back to basics, Q=CV and differentiating we get: -
\$\dfrac{dq}{dt} = C\dfrac{dv}{dt}\$ which of course equals current.
Therefore current is 10,000 x 100uF = +/-1 amp and square in shape. RMS is 1 A.
1 amp is a lot bigger than 1.443 mA and "C" is always chosen to minimize ripple so, as C gets bigger, then the ripple gets smaller (hence a lower AC current through the load resistor). Ultimately the AC ripple current through the resistor tends towards zero and the ripple current in the capacitor remains at a constant.
Capacitor ripple current remains constant because it is defined by the inductor and input voltage to the regulator and, to make this analysis clearer it makes sense to consider the input voltage to be constant.
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H: Boost converter design help - NJM2360D
So, I purchased a NJM2360D boost converter from Mouser. Using two 6V batteries in series to create a 12V supply, I'm trying to obtain a 40V output.
The "typical application" circuit from the datasheet is shown below:
Can you guys offer any insight into the design of such a circuit?
How are the capacitor sizes chosen?
What size inductor will I need?
What type of inductor will I need? (when I try to find a simple "inductor", there are many options)
What does the voltage at pin 5 do? How do I select the resistors for the voltage division?
Any help would be greatly appreciated!
AI: The Texas Instruments MC33063A appears to be an equivalent to the NJM2360D and, has a much more informative data sheet containing PCB layout guidelines and formula tables for all main components. It also contains a detailed design procedure for boost and buck operation.
When it comes to questions about capacitors and inductors generally used for boost or buck regulators, ANY source of information from ANY recognized supplier of switching regulators will be as good as each other. For instance, if you look at Linear technology, they are very good at delivering part names and numbers in the vast majority of their switching regulator circuits and, generally speaking, what is usually good for one boost regulator operating at a specific frequency will be good for any other.
So if you don't understand how an inductor value is chosen, you might not expect the data sheet to help you there - you have to go out and google stuff but, it's worth looking at LT's data sheets because, in the main, I find them to be much more useful in this situation. Maybe other folk will also name other suppliers who provide such information readily to hand.
It's also worth going to TI's website and seeing if the MC33063 is available as a design in their webench - if it is then you should get some great knowledge just by using it.
Pin 5 attempts, via the feedback to maintain itself at 1.25 volts. Hence the circuit in your question appears to be a 30 volt regulator because 1.25 volts across 2 kohm sets a current of 0.625 mA flowing - this drops 28.75 volts across the 46 kohm resistor and therefore the voltage at the top of the 46 kohm is (28.75 + 1.25) volts.
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H: NPN Transistor choice
A few months ago, I realised a meter reading system following this french guide: http://www.magdiblog.fr/gpio/teleinfo-edf-suivi-conso-de-votre-compteur-electrique/
I use the following circuit:
(source: magdiblog.fr)
Which is connected to my Raspberry Pi B+, it works really well but now i'm trying to improve the system to read two electric meters using the same circuit.
I was told that an NPN transistor would allow me to "switch" between the two electric meters. But I don't know how to choose the transistor and where should I place this transistor in the current circuit.
AI: The meter sends data continuously on the serial port. If you use two meters but have only one serial port available on the pi, combining both RX lines will lead to collisions and the data frames will get corrupted.
But maybe listening to one meter at a given time is acceptable, if the meters repeats the same info regularily. For example if you listen to one meter during 0.5 seconds, then the other meter for 0.5 seconds, you'll miss some information, but you may still get the relevant info you need at the frequency you require.
If this is the case, then it is easy: just use the same circuit as above on the second meter, and use a 2-to-1 MUX (e.g. SN74LVC2G157) to switch the RX line from one meter to the second. You'll need an additional GPIO configured as an output on the pi to select one meter or the other. You could use transistors for this, but a single multiplexer chip is simpler.
On the other hand, if you really need to listen to all the frames of both meters continuously, and you can't afford missing frames, you'll absolutely need two serial ports on the pi.
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H: Quarter-wave length antenna shape
I built a simple RF communication system with a 433MHz transmitter and a receiver. The transmitter needs to transmit in a 180º range (I mean in one half of a sphere, I don't know how to say that in English), the receiver must be omni-directional.
I was told that a good antenna for small 433MHz modules is a one quarter wave length wire, and also that the shape is important, but I didn't found on google what are the best shapes.
What are the possible shapes for such an antenna? What are the pros and cons of each of them?
AI: What you are describing is a Monopole Antenna. This should be perpendicular to your ground plane - that is pointing straight up into the air.
The radiation pattern for a monopole antenna is like this:
That is seen from the side, so it actually looks a bit like a deformed doughnut:
As you can see, the best signal strength is actually away from the antenna, not close to it. If you want better "close" coverage you can go for 3/4 wavelength which adds an extra bubble on top. Other lengths give even more bizarre shapes:
In all cases the "shape" is a vertical rod.
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H: Prerequisites for Power Integrity Analysis
I try to learn about the topic of Power Integrity Analysis of an PCB, i.e. analysing the Power Distribution network (PDN) of a PCB to locate the regions of biggest noise or DC voltage droop.
Independent of the concrete CAD package used, where and how can I learn about the device models used for such an analysis. There are e.g. IBIS models for many ICs that provide the information for signal integrity simulations - what would be the analogy for PI Analysis? Do manufacturers usually provide models for PI or do engineers create there own ones based on assumptions on current peak amplitudes and frequencies? I doubt that because I suppose that would be plain guessing most of the times since the device-internal behaviour is only known by the manufacturer.
AI: What you need to get is the s-parameter measurements of the capacitors. Some manufacturers are better than others. Murata, for example, have a really detailed online tool. It's a good idea to think about this before choosing components.
The current draw is a big problem. Manufacturers very rarely, read almost never, provide the shape of the drawn current pulses. This is because it all depends on the application. However, you can have some assumptions. The worst case scenario is a Dirac pulse, which has a flat frequency domain representation. You can relax that to say a 10th of the clock period.
After you have that there are generally two steps to PI analysis. You simulate the impedance of the power network at each IC. This will show you whether you need to place more decoupling capacitors to lower the impedance at specific frequencies. You can also check the resonant frequencies of the planes. After that, you need to put your current draw model on the ICs, and do a frequency sweep. Now, you will be able to see what the noise is etc.
In the majority of cases I have worked on, the impedance analysis, which requires only the capacitor data, is all you need. You can do the more detailed analysis, if you want to minimize the capacitance or are worried about current loops crossing each other. Generally, you can assume that current is drawn in Dirac pulses, and design the impedance budget for that. It works surprisingly well even for Gbps applications.
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H: Convert a [0,5]V wave to [-2,2]V wave
Using a PIC, I got a signal oscillating around 2.5V +-[0,2.5]V approximately. This is intended to generate a simple sound through a small speaker.
The speaker, unfortunately works with 0V +-[0,2]V, and I expect the direct usage of 0-5V not resulting in the same sound (or even breaking the speaker). Consequently, I would need to displace the ground to 2.5 for the speaker.
simulate this circuit – Schematic created using CircuitLab
Could someone indicate me the direction for a solution?
Current status:
I did not managed to go very far,
Using opamp, but they mostly threat the input voltage, so a negative voltage source is required. I should probably reminder how they work in case it is the solution.
Splitting the voltage with resistors, but that did not convinced me due to attenuation.
I finally looked for some LM317 to generate a ground at 2.5V; However, I am not sure if it would work when the wave provide "negative" values.
AI: simulate this circuit – Schematic created using CircuitLab
Use an LM4865
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H: Why would you short two pins of a potentiometer?
I've found a potentiometer which controls the heat of a cook top. One of the outer pins and the centre pin were shorted with a soldered jumper.
Why would someone do that? What does this achieve?
AI: Tying the wiper and one end pole together effectively turns the potentiometer into a simple variable resistor (or "rheostat").
It no longer functions as a voltage divider would, but it does mean that in the case of a failure of the wiper contact (intermittent contact with the carbon track), you'll still have a known maximum resistance value, instead of becoming an open circuit.
Depending on how your cooker works this might be a crude failsafe to reduce the heat in case of a failure of the wiper. I would still expect other failsafes to be in place too of course.
It is not unusual for a 2 pole variable resistor of equivalent ratings to be more expensive than a potentiometer, so to save cost sometimes a designer will choose to use a pot and simply tie the wiper to one end.
EDIT: Thanks to @winny for reminding me that "rheostat" is another name for a variable resistor.
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H: Wien Bridge Oscillator - LT Super Low Distortion Variable Sine Wave Oscillator Debug
I have been setting up a low distortion sine wave generator based on this design from LT (http://www.linear.com/solutions/1623):
For resistors R1 and R2 I am using a ganged pot so that both change together, however, I have found that when I change the resistance of my ganged pot the amplitude also changes which is not what I expected. Other simpler Wien bridge type circuits that I have seen use the same set up for changing the frequency so I'm a bit stumped as to why the amplitude changes in this circuit provided by LT. To make sure the ganged pot wasn't doing anything strange I replaced it with different values of fixed resistance and I still see the amplitude change with the frequency.
Can anyone offer some insight into why I'm seeing this behaviour?
Thanks
AI: It is the task of the LT1055 opamp to (nearly) act as peak rectifier. However, because the rectified voltage must be able to change in both directions (control function) there must be the possibility for (slowly) decreasing of the peak value (discharging of the feedback cap). That is the function of the 22k parallel resistor. Hence, the whole rectifying circuit has a fixed time constant which must be at least 10 times the oscillation period (rule of thumb).
As a consequence, the time for discharging the feedback capacitor depends on the oscillation period (when the diode is off). That means: The rectified mean voltage which controls the FET resistance - and, thus, the oscillation condition (and the oscillation amplitude) - is NOT independent on frequency.
With other words: To meet the oscillation condition (opamp gain of "3") the FET resistance must always have the same value. Hence, the rectified voltage must have the same fixed value (control voltage). But this voltage depends somewhat on the oscillation period (more time for discharging the cap for lower frequencies). Thus, the control voltage lowers for smaller frequencies. This "drift" of the rectified voltage is automatically compensated by a larger oscillation amplitude.
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H: What happens to current if I change dielectric from air to material with Ɛr>1
Electrostatics: One of the job interview question:
Plate capacitor, with area of electrodes S, and distance between them d,has air as dielectric. Capacitor is connected to constant voltage source. Then, it is disconnected and dielectric is introduced between plates with relative permitivity Ɛr>1,
What happens to current between plates? does current drops (asuming to zero if there is no voltage), increases, or stays the same?
AI: It's not completely clear if you are talking about a floating capacitor with no external connections and a fixed charge Q, or if this cap is somehow being used in a circuit. Since you say "current" this becomes ambiguous because this implies the flow of charges.
From a electrostatics point of view, assume that the capacitor is not connected to anything but has a fixed initial charge Qo.
Q = CV so V = Q/C; and a voltage will be across the capacitor plates.
When you replace the dielectric, you will increase the capacitance. So the voltage across the plates will decrease (for fixed initial charge Qo).
But if you are asking how the charging current on such a capacitor would change for the same input voltage, then it would increase. This is because it now takes more charge to create a change in voltage on the plates (with the higher dielectric).
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H: Teardrops in Eagle
Is there an good and easy way to add teardrops to traces in Eagle? See the red trace in the following image.
I have a board with a lot of vias and drawing the teardrops manually (as I have done in the image above) is not an option.
AI: Eagle comes with an ULP called teardrops.upl, which does what you want:
You should do this as last step on a copy of your board, since this can not easily be undone.
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H: 1PPS signal from GPS: do the electrical connections need special treatment?
I have an arduino (interrupt pin) listen to the 1PPS signal from this GPS (from the Adafruit ultimate GPS breakout).
However, sometimes it doesn't pick up the signal. Occasionally, I've been able to make it pick up a signal by fidgeting with the electrical connections, making me think a loose connection somewhere could be the problem.
The GPS is connected to the ATMEGA328P by a combination of screw terminals, male-female headers, and IC socket. I'm certain that these are fine for ordinary arduino use, but maybe the 1PPS pulse is so brief that it requires stronger connections?
Does anybody know best practices for carrying the 1PPS signal?
AI: The 1-pps pulse is not particularly brief; I've never seen one that is less than 100 µs, and some as long as 1 ms or even 10 ms. The key is the timing of the rising edge of the pulse, and how accurately you want to capture it. If you're just triggering a microcontroller timer or interrupt using it, it shouldn't require any special treatment; just a reliable connection.
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H: AND gate IC with internal pullup
I'm currently using a dual-input AND gate similar to the Texas Instruments SN74LVC2G08.
I'm wondering if any manufacturers make an AND gate with internal pull-ups so the inputs would default to TRUE when the device driving them tri-states. If so, can anyone point me to an example?
Thanks.
AI: The inputs of bipolar TTL logic (74xx, 74LSxx) normallly appear as High when not connected - but even with them, it is advised to provide a pull-up resistor to ensure that unconnected inputs will really be taken as High.
CMOS parts (74HCxx, 74ACxx, etc.) have very high input impedances, and MUST have a pull-up or pull-down resistor to be reliably detected as High or Low, respectively.
Added, following a "not an answer" comment:
I'm not aware of any common logic parts (gates, flipflops, counters...) that have built-in pull-up resistors on their inputs, but many microcontrollers do have pull-up resistors that can be enabled or disabled by software on their I/O pins.
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H: using headphones as microphone
I am learning about headphones and microphones and I have 2 questions.
I bought a few pairs of headphones from the dollar store and took one pair apart. There is a weak little magnet in the center with very thin insulated wire coiled around it and there is a very delicate plastic sheet covering this little assembly. Now, the headphones worked before I took them apart so it's very exciting to see the guts. I've also studied this design and I think I understand the physics of it.
My questions are:
Should I be able to use these kinds of headphones as microphones? I've thus far been unsuccessful.
The headphone jack is tip-ring-sleeve. If I connect sleeve (which I think is common ground) to either tip or ring (and thus completing the circuit), can I use my multimeter to measure the current/voltage if I yell into the headphone?
My goal is to see (detect) this thing at work. I've learned a bit about op-amps too, and I wonder if I cannot do what I want without making a slightly more advanced circuit.
Kindly,
AI: In most cases, headphone transducers will also work as dynamic microphone transducers. However, they put out a VERY SMALL amount of signal which you will never see on a regular meter. No it cannot be "amplified" by simply applying a DC voltage (from a battery or whatever). You need a high-gain AC amplifier. Specifically a microphone preamp to bring a "mic-level" signal level up to "line-level" which can be seen on a meter. Typically 40dB (10,000 x) of gain. There are hundreds of examples of mic preamp circuits online.
Most small microphone capsules used with computers, etc. these days are electret condenser microphones which are quite different than dynamic microphones.
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H: Verilog preventing latches
I created a simple Verilog module that displays random numbers. This module has a counter that counts up at every clock edge and at the press of a button, whatever the number is in the counter at that time is displayed. Here is my code:
module counter (input wire in, input wire clock, input wire reset, output reg [3:0] number)
reg [3:0] cur_state;
reg [3:0] next_state;
always @ (posedge clock) begin
if (reset) cur_state <= 4'b0;
else cur_state <= next_state;
end
// next state function
always @ (*) begin
next_state = cur_state + 4'b1;
end
// output
always @ (*) begin
if (in) number = cur_state;
end
number[3:0] is sent to a display module to display the corresponding number. (Inputs are debounced properly.)
Everything works fine on the FPGA, but the program notifies me that I've used a latch in output. Is there any way to prevent this and implement the same behavior using a flip-flop?
Thank you.
AI: Your problem lies in that you are describing an asynchronous circuit which requires its previous state.
// output
always @ (*) begin
if (in) number = cur_state;
end
When in is high, all is well - number is assigned to the value of cur_state. However, what happens when in is low?
When in is low, number does not have a new value specified (i.e. via else) which means that you are inferring that it must hold its value. Whenever a combinational circuit is asked to hold its value, you get a latch.
The way to prevent latches then is to ensure that in every combinationally inferred logic, you fully define the assigned value to never require itself. You can do this in one of two ways.
First, if you don't care about the value when in is low, then you can assign some constant:
// output
always @ (*) begin
if (in) begin
number = cur_state; //If in is high, output the current state
end else begin
number = 4'b0000; //If in is low, output is don't care so avoid latch by assigning value
end
end
Second, if you need the output to hold its state, then you need to make it a clocked process:
// output
always @ (posedge clock) begin
if (in) number = cur_state;
end
Now that it is synchronous, you can have the output hold its state because you are now inferring a flip-flop. The down side to this is you have a 1 cycle latency from when you change the in signal to when the number value updates.
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H: What is the minimum distance that BLE 4.0 capable device be programmed for..?
After Searching on Web found out that the range/Distance of BLE device transmission can be controlled by varying its transmission power and frequency. But could not get how specific can we bet on the minimum distance covered by reducing the transmission power of a BLE capable device to the lowest.
AI: The goal of this rather long analysis is to ensure you look like the sharpest RF dude your company has ever hired :)
The free space path loss range of a an RF system can be calculated.
For a typical class 2 Bluetooth system, assuming +4dBm of transmit power, -70dBm receiver, & unity gain antennas, you will find that the range that gives you 74 dB of path loss (the maximum path loss that still works) is 50 meters.
Below I did it in one of the many online path loss calculators:
From the path loss equation you will note that power is a function of the square of range, so, if you reduce the range by a factor of 2, the required transmit power (or receive sensitivity) falls by a factor of 4. (i.e. 6dB).
For example, if we reduce the transmit power from 4 dB to -2dB, the free space range will reduce to 25 meters. Lose another 6dB and you are around 12.5 meters.
Sounds easy huh? Nope...
Mobile links such as Bluetooth move around in a complex environment of objects that randomly reflect the signals. At the receiver, these multiple paths can either support or cancel each other, so as the mobile unit moves around, the signal power fluctuates wildly. How wildly? Well, it turns out that it's all statistics: The received signal strength turns out to be our old friend the normal distribution. The average signal strength is simply what is predicted by the path loss equation.
So first bad news is that if you depended on that 50m free space range, your link will only work half of the time. (top half of the distribution)
The second bad news is the standard deviation, which in this case turns out to be roughly 6dB. You'll see from this rule that 99.7% of signal strengths fall within -3 and +3 standard deviations.
That can be stated in a different way, and you are not going to like it: Your mobile Bluetooth signal will vary over a -18dB to +18db range around the mean value predicted by the path loss model!
Since range-squared and power is related through the first equation, we can also state the rule-of-thumb that your operating range will regularly vary between (roughly) 1/8x to 8x of the 50m estimated free space value!
In practice, this means that for around 0.15% of the time, you won't even be able to make the 50m link work at 50/8 = 6 meters, but on the other hand, for .15% of the time you will "get lucky" and the link will work as far out as 400 meters. If you are a smart product marketer, you will quote the range as 6 meters. Your product will meet your spec 99.85% of the time!
Why this long story? To provide you with sound reasoning regarding why you have to be very alert to the statistical nature of mobile links like Blueooth!
Your intended RF minimum distance is going going to vary over a 1:64 range! Is that OK?
If the range you are thinking of is less than, say, one meter, inductively coupled systems could be your answer, the key reason being that unlike RF, where received power is a function of 1/range-squared, in magnetically coupled systems power drops with 1/range-cubed. That extra order really takes care of "accidental" successes at further distances, but it's also the reason why the range is typically constrained to less than a meter.
Also, you might want to look at Alan Bensky's book on Wireless Positioning Technologies and Applications.
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H: What are the limitations of macro in embedded programming?
What could be the limitations of macros in embedded system programming.
In contrast to c programming.
AI: As it is worded, the question you quote makes no sense. Macro facilities are a part of C, C++, assembler, and probably a lot of other languages. If I was asked this question I would politely explain this if I wanted the job. When no explanation was offered and the guy still insisted on an answer, I would probably walk away from this company in disgust.
There are explanations that could make sense of this question:
Macro is sometimes used a s a shorthand for 'macro assembler', in which case the question would be about C versus assembler. My standard answer is: "Assembler is better, on the condition that you get enough time. When was the last project you were given enough time?"
Another interpretation would be the use of macro's versus the use of functions, both within C. There are lots of texts about that, the general idea is that you always use functions, unless you really need to use a macro. And even then you should think twice.
Note that in neither case there is anything specific about embedded. That makes sense, because embedded is to wide a term to have any specific consequences on programming style. For very small systems (code size limited) the use of marcos instead of function calls could lead to code bloat. But carefull use of macros could reduce code size, so even then there is no definite answer.
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H: STM32L011 RTC wakeup function
I have a battery-constrained device with STM32L011. Right now I am using Nucleo-32 development board. In the end I want to use suspend mode with RTC to wake up every couple of minutes. First I want the RTC to generate an interrupt using the wakeup function.
I can see in my UART log, that the RTC is running (RTC_TR is incremented), I can also see that RTC_ISR is initially 0x23 and in the next second it is 0x423, which means that WUTF flag has been set. However no interrupt occurs.
My ISR just turns a LED on and clears EXTI flag. When I do EXTI_SWIER |= BIT17; the interrupt fires correctly (so I guess that EXTI and NVIC are set correctly). My problem is that even though the interrupt is enabled, RTC is running, WUTF flag is set - the interrupt does not occur. I have no hard faults, nor resets.
This is my RTC code:
RCC_APB1ENR |= BIT28; //turn on power control circuit clock
PWR_CR |= BIT8; //unlock the RTC domain, set DBP in PWR_CR
RCC_CSR |= BIT0; //rurn on LSI
while ( (RCC_CSR & BIT1) == 0); //wait for LSI to be ready
RCC_CSR |= BIT19; //put RTC into reset
RCC_CSR &= ~BIT19; //take it back out of reset
//RTC on, use LSI
RCC_CSR |= BIT17;
RCC_CSR &= ~BIT16;
RCC_CSR |= BIT18; //RTC enable
RTC_WPR = 0xca; //RTC unlock
RTC_WPR = 0x53;
// RTC Initialization procedure (see reference manual)
RTC_ISR |= BIT7; //set INIT bit, request RTC stop
while ((RTC_ISR & BIT6)==0); //wait for RTC to stop
ISER |= BIT2; // enable RTC IRQ in NVIC (via EXTI line)
//wakeup configuration
RTC_CR &= ~BIT10; //clear WUTE bit
while( !(RTC_ISR & BIT2 /*WUTWF*/) ){} //wait for the bit to be set
uart_puts("RTC_ISR=");
uart_puthex(RTC_ISR);
RTC_ISR |= BIT10/*WUTWF*/; //has to be set before writing to WUTR (manual 22.7.6)
RTC_WUTR = 0x9C0; //very short wakeup period
RTC_CR = BIT14 /*WUTIE*/ | BIT10 /*WUTE*/ | BIT0|BIT1 /*WUCKSEL - RTC/2 wakeup clock*/ ; //enable wakeup function and interrupt, RTC/2 clock
RTC_ISR &= ~BIT7; //start the RTC (clear INIT bit)
EXTI_IMR |= BIT17; //enable RTC alarm going through EXTI 17 line to NVIC
EXTI_EMR |= BIT17;
EXTI_RTSR |= BIT17;
This is my UART log (repeats approximately every second):
------
Hello
RTC_ISR=c7
wutr=2496
RTC_ISR=23
RTC_TR=0
RTC_CR=4403
EXTI_PR=0
wutr=2496
RTC_ISR=423
RTC_TR=1
RTC_CR=4403
EXTI_PR=0
wutr=2496
RTC_ISR=423
RTC_TR=1
RTC_CR=4403
EXTI_PR=0
wutr=2496
RTC_ISR=423
RTC_TR=2
RTC_CR=4403
EXTI_PR=0
wutr=2496
RTC_ISR=423
RTC_TR=3
RTC_CR=4403
EXTI_PR=0
wutr=2496
RTC_ISR=423
RTC_TR=4
AI: My bad. RTC wakeup uses EXTI line 20, not line 17 (as RTC alarms do) - table 53, RM0337. Now works fine.
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H: Anti-Aliasing filter design
I appreciate that different applications have different criteria, but could someone give a ball park figure of how much attenuation is needed for an anti aliasing filter at the Nyquist frequency to prevent aliasing?
For example I'm building a filter for the input of my PIC which samples at 10KHz and therefore the Nyquist frequency is 5KHz. I'm only interested at parts of the signal below 3KHz, so I have some leeway in my design as to whether I choose a second order/third order low pass filter, but I don't know which to design because I don't know how much attenuation at 5KHz would be sufficient?
AI: If you are interested only in signals in the range DC to 3kHz, then only signals above 7kHz will alias onto those.
This means that you need a filter with ...
a passband to 3kHz
a transition band from 3kHz to 7kHz
a stopband from 7kHz upwards
Note this doesn't define the 5kHz attenuation, and doesn't need to.
The stopband must have enough attenuation to protect your signals. If you want 0.1% fidelity for your lowpass signals, you need 60dB attenuation in your stopband. You will usually find it more practical to design an elliptic filter than a classical Butterworth or Cheby to get adequate stopband attenuation.
Now comes some subtlety, follow me carefully.
What does 'if you are only interested in signals in the DC to 3kHz' really mean?
If you are bandpass analysing signals up to 3kHz, for instance estimating the power in the bandwidth 2.5kHz to 2.7kHz, using a good digital filter to isolate the band, or an FFT which is equivalent, then having a transition band from 3kHz to 7kHz is just fine.
Although it allows signals in the 5k to 7k band to alias down to below 5kHz, they are still above 3kHz, and you're going to ignore/reject those signals anyway.
If however you are plotting the samples on a scope trace, then you may have inadvertent energy above 3kHz that is still valid. For instance if you have a 1.1kHz square wave, you will have harmonics at 3.3kHz, 5.5kHz, 7.7kHz.
Now, the crucial point is that the 3.3kHz harmonic will be coherent with the fundamental, and if you plot it, it will look OK, even if its amplitude has been suppressed a little by the filter. However, the 5.5kHz harmonic will be aliased to 4.5kHz, and will be incoherent with the fundamental because its frequency has been reflected through Nyquist, and will breathe in and out as its phase changes, and will generally look wrong.
What this means is, if you are going to end up making use of energy in the 3kHz to 5kHz band anyway (even though you've said in the OP that you're not), then your transition band should only go to 5kHz, not 7kHz, so that no aliasing at all is permitted into the DC to 5kHz band.
Whether your filter has a stopband from 7kHz, or from 5kHz, depends crucially on what you intend to do with your signals. Needless to say, it's much harder to make a filter with a 3k-5k transition band, than a 3k-7k transition band.
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H: Double BiQuad sector antenna
I want to DIY a double BiQuad antenna . But I find they are different from different web. As the picture first of below, the board under the antenna is flat, but the second has two orthogonal bend. I just want high dBi and use for 5.8G wireless image transmission. Which is better ?
AI: The metal plane really just has the purpose of acting as a reflector – due to symmetry, the biquad has the same pattern into the "front" and back, and adding a simple metal plane in the right distance from the antenna will make the reflections add up constructively with the "forward" direction, thus adding a 3dB to gain (in theory).
You want an infinitely sized, perfectly conducting ground plane. You don't get that, but something around two times the quad side length in each direction around the driven element should do most of the work – you don't lose that much if you don't have that.
The bent "legs" might have the purpose of electrically "enlarging" the plane area, but they might also serve as mechanical improvements, making the ground plane more rigid.
I'd recommend simulating this stuff – OpenEMS, free as it is, already comes with a Biquad example, and you'd only need to add a reflector to that and play with the parameters.
The problem I often encounter when researching this kind of question is that many Antenna "theory" on the internet is written by Hams that assume that SWR (standing wave ratio) is the final and best and only measure for antenna quality, totally ignoring that an impedance-matched terminator has perfect SWR; so for example, I found one source that claimed that a driven element-plane distance that would lead to destructive interference is the optimal configuration – probably just because he saw a better impedance matching that way. But that's the dominant quality of antenna discussions – based on not-really-understood measures and vague heuristics rather than actual simulation and understanding :(
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H: (How) does blocking a (servo/DC) motor break it?
I don't know why, where or how I picked this up, but I believe that if you power an electric motor while blocking it, and thus stopping it from moving, you'll damage it. I'm thinking of the following type of motor, and possibly servo motors:
Is it indeed true that holding the shaft in place while powering it will damage it? And if so, why? And could this be prevented by simple measures? (Like putting a resistor in front of it.)
Is the "damaging process" any different in servos, or do they get damaged in the same way?
AI: Simply stopping a motor from turning does not by itself hurt it. Think about it. The motor is stopped when you first apply power, and nothing gets hurt.
Most motors are designed so that the mechanical forces from the maximum torque won't hurt the motor.
The reason some motors shouldn't be stalled with full voltage applied is heat. All the electrical power going into the motor goes to heating the motor. Many motors can be over-heated this way. Designing them to be able to dissipate the heat from maximum applied voltage while stalled would require making other parameters less desirable. In many cases that's not worth it.
What makes stalling a motor even worse is that's when it draws the most current. So not only is more electrical power being dumped into the motor, but a higher fraction of that is turned into heat in the motor at low speed.
To a pretty good first approximation, think of a motor as a resistor in series with a voltage source. The resistor is just the DC resistance of the windings. The voltage source represents the motor acting as a generator as it turns. The voltage is proportional to speed, and opposes the applied voltage when the motor is turning due to this applied voltage. A stalled motor therefore only looks like a resistor. As the motor speeds up, that resistor is still there, but less voltage is effectively applied to it, thereby causing it to draw less current.
Sophisticated motor controllers either model the motor's internal temperature, or measure it outright. This includes tracking how much of the power delivered to the motor is transferred away by the rotating shaft, and how much is dissipated by the motor as heat. When the motor gets too hot, the drive power is reduced to avoid damage.
Since the damage is due to heat, stalling a motor under full power is OK for at least "short" intervals. How short "short" is depends on the design of the motor, and is something that good datasheets give you guidance on.
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H: Create multiple clocks on FPGA or create clock dividers
I am thinking in a design and I have a doubt about clocking. What is better? Do I create different clocks or create clock enables and only use one? What is the best option in terms of resources? What is more reusable?
Thanks!
AI: There are different reasons why someone wants/needs to have different clocks in a design.
Most of the time I try to keep all my design running with the same clock.
When working with several clocks, we talk about different clock domains. Each signal has its home clock domain. These clock domains are needed by the routing tools to find a layout that meets the timing (= maximum acceptable delay).
If a signal crosses from one clock domain to the other, it is highly recommended to use some crossing logic in order to avoid problems like metastability. Most of the time this is done by FIFOs or Dual-port-BRAM. (More informations about this topic can be found here: http://www.gstitt.ece.ufl.edu/courses/spring11/eel4712/lectures/metastability/EEIOL_2007DEC24_EDA_TA_01.pdf)
Often external interfaces are driven by theire own clocks. In this cases we can not avoid having different clock domains. Use the interface clock to sample the data and maybe do some preprocessing and then migrate the data to the system clock.
Clock Enables: In FPGA designs, clock enables lead to gated clocks and should be avoided by all means. Clocks are routed on special nets. These clock infrastructure takes care of delivering the clock signal to each gate at the same time. After adding logic into the clock path (for example an enable) the clock signal will be routed on normal signal paths. The place-and-route process will have a hard time to make sure, all timing requirements are still met.
Better than enabling the clock, would be to make an ENABLE entry to your logic. The clock stays untouched, but the logic knows if it has to react or not. In VHDL this would look something like this:
enable_example: process(clk_C)
begin
if rising_edge(clk_C) then
if enable_DI = '1' then
<< write your logic here>>
end if;
end if;
end process enable_example;
Resources: In therms of resources we need to specify a little bit what kind of resources. There are mainly 3 types of resources we could talk about:
Time:
Running everything with the highest clock makes your design easy to read and understand but may lead to bad timing. High frequencys allow only short routing and logic propagation delays. The lower your clock, the better the chance of achieveing timing constraints.
FPGA Resources:
Modern FPGAs have enough clock nets that you don't need to worry about running out of nets in most cases. But crossing clock domains may need quite some space (FIFO in BRAM or different logic).
Energy: (I don't have enough knowledge to give a good answer to this)
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H: Suppressing sparks when attaching buck converter to battery
i have bought a cheap DC/DC converter (24v to 19v, 15A, link). When i attach a 24v battery pack to the converter input i get sparks. Is there any way to suppress these sparks when i attach the converter?
Edit: I want to power a Intel NUC mini computer with the converter. My idea was to use a relay to turn the dcdc output on and off. Wouldn't the sparks damage the relay contacts or weld them ?
AI: Is there any way to suppress these sparks when i attach the converter?
This is caused by inrush current and, for many devices like this can be several tens or even hundreds of amps i.e. much more than the normal full-load running input current. It can be particularly bad on on-line SMPS units and a lot of them use a negative temperature coefficient thermistor to reduce this transient effect.
The thermistor has an initially high resistance when cold thus lowering inrush current but, as it warms over the period of a few seconds, its resistance drops significantly. However, it represents a loss in efficiency even when warm so some circuits have evolved to use a MOSFET to control the inrush: -
Q1 initially does not switch on when power is applied due to the capacitor C1. That capacitor gradually (over a second or so) charges and as it does so the MOSFET is turned on gradually thus alleviating the inrush problem.
Here's another example with values: -
Image stolen from here and here's a version with a little more sophistication: -
The extra transistor guarantees that the current cannot rise above a certain value.
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H: Silicon purity and electronic feature density
During development of an integrated circuit it is my understanding that you require a silicon purity of 99.99999999%.
Has this always been the case? In 1971, had the first commercially available microprocessor (Intel 4004, 10 micron process) reached this level of purity?
How has the purity of silicon for electronic purposes increased as the feature size (gate electrode width) decreased?
I've searched online for multiple days with little success. I'm aware of Silicon purification processes and really only seeking a definitive data set on the increase of purity during feature reduction; if any at all?
AI: That's a surprisingly involved question.
So, first of all, the critical thing for commercially available microprocessors is reliable, well-defined transistors and diodes, based on pn-junctions.
Reliable implies that under no circumstances should a semiconductor junction act like a metal. However, all semiconductors do that as soon as you dope them too heavily.
This implies that for commercial semiconductor devices, you need so-called lightly doped semiconductors. Obviously, you want the doping atoms to be the dominant non-Silicon atoms - so every other kind of atom, lest it be really insignificant for the bands involved, must be at least two or three orders of magnitude rarer.
So, what is a lightly-doped semiconductor? Definitions differ, but the takeaway is that the semiconductor must not be degenerate, that is
$$\begin{align}
E_c - \mu &\gg k_BT \\
\mu - E_v &\gg k_BT \\
\end{align}$$
must hold.
Here, \$E_c\$ and \$E_v\$ are the energies in the conducting and valence bands, each, which are fixed for a given semiconductor. \$\mu\$ however, is the so-called Fermi-level, which is the level of "occupancy probability equilibrium". In other words, at room temperature, an electron is as likely as not (50%) to be at that level of energy. What the inequalities above demand is that the distance from that level to the band edges is big enough to avoid charges to suddenly flow spontaneously.
\$\mu\$ depends on the doping, since it is a function of the number of charge carriers. Now, I'm not an expert on semiconductor production itself, but I'd assume that with typical doting in the region of \$10^{-15}\text{cm}^{-3}\$, and the molar mass of silicon, you can get far enough to get an idea of what's technically necessary for pure silicon-based bijunction transistors. Then, add some security margin – structures are very small, so a cluster of lets say 3 unwanted atoms might already be pretty much, so the likelihood of that must be suppressed sufficiently below your acceptable yield. It boils down to a size/cost/reliability/yield trade-off and no general answer can be given.
Now, these calculations are based on the assumption that we're working on a silicon wafer with the "natural" silicon lattice – and in reality, modern ICs are based on SOI – silicon stretched on an isolator (SiO2, typically). It's very hard to actually talk about purity in this context.
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H: Used Fluke 87V multimeter working correctly?
I'm just a hobbyist but I like to purchase quality tools so I purchased an "only used once" Fluke 87V on eBay. The calibration sticker says the calibration expired last year.
Anyways, when I turn on the multimeter the milliamp reading shows a few mA even when I'm not touching anything. It usually settles down to 0 mA after about 10 seconds though.
Is this normal?
Also, when I'm checking capacitance it always shows an nF value and never gets to 0 nF.
AI: Yes it is perfectly normal. Most measuring instruments need a little warm up time. This time allows electronics component to stabilise at a certain working temperature where the calibration is made. 10 seconds warm up seems about right.
As others said, it is impossible to measure a zero capacitance as there will always be a parasitic capacitance between leads and between the pcb traces of the instrument.
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H: Modern alternative to TRIAC for switching alternating current?
The only alternative I know is a high power MOSFET wrapped with diode bridge.
AI: An SSR (solid state relay) doesn't need a bridge: -
It handles AC and DC very nicely without using a bridge rectifier.
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H: Arduino HF Interference Protection
I'm working on creating a relatively simple project where I'm using an Arduino as a remote garage door opener. Part of this project has a reed switch near the bottom of the door to detect when its closed.
My issue is this requires a pretty long wire run for the switch (probably about 10-15 feet). My dad does a lot of ham radio communications and as such the house has a ton of HF radio being emitted. I'm wondering how I can protect the Arduino from any damaging interference and still reliably detect when the reed switch closes. I found this article but I'm not sure if it'll help me or not. I'm sure I would need a ferrite bead and probably a twisted pair for the wiring but not sure what else I will need to protect the Arduino. Thanks!
AI: IMPEDANCE - Use a very low input impedance so that it responds well to a "dead short" like a switch, but is "de-sensitized" to random EMI floating around in the air. As FakeMoustache suggested perhaps using a pull-up resistor around 1K would make it nice and "stiff". And even some significant capacitance on the order on 1nF wouldn't hurt because you are dealing with a very low-speed circuit here and it might even benefit from some "debounce" help.
FILTERING - You can use parallel capacitance and series inductance to block high frequencies (like RFI) while still allowing DC (like from your switch) to work normally. For example look up a "pi-filter" (nothing to do with the Raspberry Pi).
ISOLATION - In extreme conditions (unlikely in this case) sometmes techniques such as optical isolation are used to further decouple the control electronics from long distance signal connections through "hostile territories".
Ref: https://en.wikipedia.org/wiki/Capacitor-input_filter
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H: Common Collector Biasing
The common terminal of the transistor configuration is also the GND of the circuit, right? I get it that emitter is GND but how is it possible for NPN transistor that base or collector is GND?
AI: The expressions "common (terminal)" are confusing. It refers to the terminal that doesn't carry a signal, so it's considered common to both the input and output. It's not necessarily ground. In the circuit of your diagram the input is the base and the output is the emitter, so it's called a common collector. That particular configuration is more commonly called an "emitter follower," BTW.
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H: What do thermocouple type names (eg K, L, B) signify?
What does the K in a type K thermocouple mean and likewise for the rest?
Is it elemental (I don't see any potassium in there though) or something else?
Thanks.
AI: The letters are arbitrary "nicknames" for various common types. For example:
E = chromel–constantan
J = iron–constantan
K = chromel–alumel which is probably the most popular kind.
T = copper–constantan
and many others which you should have looked up in Wikipedia or some similar online source. Really, you could have found the answer to your question in much less time than it took to come here and type it in. This forum is rather averse to simple questions like yours which could have been easily researched on your own.
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H: Current Sensing with Non-Inverting Amplifier
Hello, I'm implementing a current sensing circuit as shown in the schematic. The simulation works but the physical circuit does not. On the breadboard if I measure between the shunt and the load to the ground on the power supply I get 67.3mV, however if I measure across the shunt I get 27mV (expected value since current @ 100ohm load is 110mA). As a result the Op-Amp amplifies the 67.3mV and I get the wrong amplified voltage. I've connected all the ground rails together and to the power supply. Can anyone say what's the possible problem ?
EDIT: I changed the shunt resistor to 1ohm and it works as expected, so why doesn't it work with the 0.25 ohm shunt ?
AI: In all probability you are using an op-amp that just cannot work with the inputs close to its most negative power rail (0 volts in your example). Most "regular" op-amps need a couple of volts headroom within the power rails for inputs. This also applies to outputs.
If you are using an LM324 you might get this to work by loading the output with a 1 kohm resistor. It says something to these ends in the data sheet.
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H: How to turn on LED with only a cathode pin
I'm looking at the datasheet for some TIL311 hexadecimal displays which I ordered (but have not yet arrived. (Actually they appear to be TIL311 clones, but should be compatible.))
According to the datasheet, the left and right decimal point LEDs have their cathodes exposed via pins 4 and 10. The anodes are not connected to a pin; I assume they are hardwired to Vcc within the IC.
I want to turn the decimal point ON when I have +5v on a certain wire.
Am I correct in thinking that the right way to do this would be to use a discrete transistor to allow current to flow from the cathode to ground when it (the transistor) turns on? If so, what's a good kind of transistor to use?
Or is there a simpler way that I haven't thought of?
AI: You could use a low-side NPN transistor (e.g. 2N4401) or N-channel MOSFET (e.g. 2N7000). Connect the dot pin to a resistor (~1kOhm), and connect the other end of the resistor into the switch's collector/drain. Connect the switch's emitter/source to ground and feed an on/off signal to the base/gate through a resistor (say 10~100 Ohms).
Unless you want it always on -- then you could just connect a resistor to the dot pin to ground (again, ~1k Ohm).
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H: CMOS Logic Design
How to represent such an equation using CMOS inverter (The whole equation is inverted)
Z=~[(A.B)+C.(A+B)]
The load equation will be :
[(A'+B').C'+(A'.B')]
' means it is inverted
The driver equation will be :
[(A.B)+C.(A+B)]
The problem is how am i going to use transistor A and B in parallel(OR) and in
series(AND) in one diagram ?
And how is the layout gonna be drawn ?
AI: The logic circuit below is what you are trying to achieve with simple logic gates. To bring it up further, you can find CMOS Logic circuit for each of those elements and tie the outputs together to complete your required circuit.
simulate this circuit – Schematic created using CircuitLab
The circuit for a CMOS AND Gate is the following:
And the circuit for a CMOS OR Gate is the following:
You can change the logic symbol by those CMOS circuits and you should be able to get what you are looking for. Note that you will have A and B tied together to drive one OR gate and one AND gate. The output of the first OR gate is tied to the input of the second AND gate and C is the other input for this AND gate. Both outputs of the AND gates are the inputs for the last OR gate that will determine output Z.
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H: How does the voltage division on this work?
How does the voltage division of this work? I understanding other types using KVL, but this I am just lost. Im not comfortable blindly taking the answer and would like to know. Or is the answer just flat out wrong?
AI: So in this particular circuit, we can see that the overall voltage across the RC branch of the circuit containing Vφ is equal to Vo. Given this fact, we can then use the impedances of the resistor and the capacitor to determine Vφ. The voltage division rule for two series impedances Z1 and Z2 (where Z2 is tied to ground) is given by: $$ V_o = \frac{Z_2}{Z_1+Z_2}V_{source} $$If this is true, we can identify both the bottommost wire in the diagram as ground and the capacitor as Z2 in our voltage divider equation (which, consequently, leaves the resistor as Z1). Given this information, the equation for Vφ becomes: $$ V_{\phi} = \frac{\frac{10^4}{s}}{50+\frac{10^4}{s}}V_o $$ From here, we can multiply this equation by 1,which is the same as multiplying both top and bottom by s, which transforms the equation into: $$ V_\phi = \frac{10^4}{50s+10^4}V_o $$ Hope this was helpful!
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H: Signal processing to demodulate LF RFID
I'm trying to read a LF (low frequency) RFID transponder. The carrier frequency is 125kHz and the base band signal has a 20kHz bandwidth. The modulation is in load modulation, a kind of AM modulation.
I'm using the following approach to process the signal:
Downconversion by sampling
Low pass filtering
DC blocker filtering
Comparator with hysteresis
Below, there is a figure with the modulated signal in blue and my demodulation of this signal in red.
There is a delay, of course, between the received signal and the processed result in red. The processed result is only the symbols and are not decoded in bits yet. But the delay is not the problem, the problem is that there is an error that happens when a short-time simbol is received. The transponder sent the following information repeatedly:
Period of carrier cycle is 1/125kHz => 8us
16 cycles => 128 us
32 cycles => 256 us
48 cycles => 384 us
64 cycles => 512 us
But after processing, the intervals above were meassured different. Each step ( the 16, 64, 32...) was meassured as follwing:
16 => 176 us => difference of 48 us => 37%
32 => 288 us => difference of 32 us => 12.5%
48 => 353 us => difference of -31 us => -8%
64 => 465 us => difference of -47 us => -9%
So The problem is the 37% of error, until the 12.5 %, ok I can handle, but 37% I think is a big error. So, I was wondering if I'm doing something wrong, or, if there is a better approach. I will explain each processing step next.
1. Downconversion by samplig
The carrier frequency (Fc) is 125kHz, so I used 62.5 kHz sampling frequency, this is Fc/2. I used downconversion by sampling based on fact of replicas, in frequency domain, being generated by sampling. So, I will have a base band signal at DC frequency that I can filter with a low pass filter. This is good thing, because the lower sampling allows me to design a filter with a lower degree and I have processing time savings too.
2. Low pass filtering
I designed a low pass FIR filter using windowed sinc with window function being Kaiser-Bessel, -3dB frequency of 25kHz and 16 taps (coeficients). To determine the number of taps I relied on the Fred Harris formula:
$$
N = \frac{Attenuation}{22\times B_T}
$$
$$
B_T = \frac{F_{stop} - F_{pass}}{F_S}
$$
\$Attenuation = 60dB \$ ( Chosen arbitrarily )
\$F_{stop} = 35 kHz \$ ( Chosen arbitrarily )
\$F_{pass} = 25 kHz \$ ( Chosen because the base band has a 20 kHz band-width.)
\$ F_S = 62.5 kHz \$ ( Chosen to perform downconversion )
This gives me 17 taps, but I decided to use 16,because I already had the coefficients calculated, I think one tap less will not degrade so much.
3. DC blocker filtering
After the FIR low pass filter, there is a DC component present, so, I decided to use a Fixed-point dc blocking filter. The algorithm used was based on the following:
http://www.dspguru.com/dsp/tricks/fixed-point-dc-blocking-filter-with-noise-shaping
http://www.ingelec.uns.edu.ar/pds2803/Materiales/Articulos/04472252.pdf
I do not know yet, but I think that the time errors that I mentioned above were of the responsibility of this block, more than the others.
4. Comparator with hysteresis
I digitally implemented a comparator with hysteresis. It uses two level of comparison. If the level is above predetermined level, it recognizes as HIGH, and if it is below a second determined level, it is considered LOW. This way I translate the filter output to simbols and rebuild the modulating signal from transponder.
The problem that I see here is that this predetermined value is fixed, and the amplitude of modulation can vary.
So, what do you think ? The approach was pertinent ?Someone has some clue about the difference in time that is happening ?
With my best regards,
Daniel.
AI: Fundamentally your approach is sound, but there are a few caveats.
First, your "downconversion" is really AM detection. Since you are sampling every second cycle of the carrier, and hopefully synchronous to the carrier, the end result will be envelope detection. However, there are traps: 1. You have to sample near the peak of the carrier (to minimize phase noise) and you have to be synchronous with the carrier (to sample at the same point every time). A simple diode detector might be a lot easier for you - no need for carrier sync, no need to sample so fast, reducing DSP load.
Regarding your pulse width distortion "issue", it's almost certainly the low pass filter. Fortunately, it's easy to verify - simply capture and plot some of the output of each stage. The plots will quickly tell you where/what the issue is, and if you may be experiencing implementation issues such as overflow.
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H: Thermal Runaway in batteries
The place where I work has a fairly large UPS comprising of rows of sealed lead acid batteries (Haze HZS-7.5HR). The batteries are now 6 years old and are not holding charge very well.
The service technician report states, among other things that ".. the batteries may go into thermal runaway and therefore become a danger to the site."
Is this statement fair, and if so, why would older batteries - which I assume have less energy then new batteries be more likely to suffer from thermal runaway?
AI: I am afraid your service tech is right, older sealed lead acid batteries are more prone to develop thermal runaway. This article summarizes this nicely.
Older batteries do have higher internal impedance, and therefore tend to dissipate more internal heat under the same charge-discharge conditions as new ones. However, if the UPS is well designed and has proper system of sensors, the runaway should never occur, and near-faulty cells should be marked for replacement long before the run-away can occur.
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H: how many 7400 can the 74LS04 safely drive
how many 7400 can the 74LS04 safely drive ?
74LS04 Specs :
I output low : 8 mA
7400 Specs :
I input low : -1.6 mA
PS : I know that the answer either 5 or 2. The only thing I am not sure is that do you consider each input for 7400 separately or not. So each 00 would need 3.2 mA or only 1.6 mA ?
AI: This seems like a bit of a trick question. If both the 7400 inputs are tied together, the total current draw when low will still be 1.6mA, as should be obvious from the schematic below.
The same can not be said of many other gates such as, say, 7402.
So you can drive any combination of individual inputs or pairs of inputs on the same gate that add up to 5 total. Trivially, if you hold the other input low the gate does not draw any current (nor will the output change). I don't think your question is stated unambiguously enough to give a numeric answer, but if you read the problem statement carefully you should be able to figure it out with this major clue.
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H: Internal input overvoltage protection
On schematic below LDO U4 is disabled and U2 is not powered.
Can the high output from U1 feed U2 inadvertently through the ESD protection diodes on U2's input?
simulate this circuit – Schematic created using CircuitLab
Assume that U2's input protection is implemented this (rather standard) way:
simulate this circuit
AI: ESD diodes can be a drag
You are correct that U2 can be powered this way -- I've seen this before when trying to hook programming cables up to otherwise unpowered circuit boards, aggravated by the typical order of connections where GND is connected first and disconnected last. While it won't necessarily trigger latchup as C2 will be mostly charged when the Vcc is turned back on, it can be quite aggravating as U2 may run when it shouldn't.
There are a couple possible fixes. If U1 and U2 are on separate boards, mating the GND connection between the boards last works around this problem -- it's what I did to avoid this for things like programming cable hookups. If U1 and U2 are on the same board, or the connector mating order needs to be GND-first, a suitable isolator (if this is a low speed digital signal, a jellybean 4N35 optocoupler and its associated resistors will do the job) will break the power path up as long as the output side supply/pullup is wired to U2's Vcc supply. (In the two-board case, this means it goes on the same board as U2.)
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H: RMS switch current in boost converter
I'm struck in calculating the I(switch,rms) in boost converter. Average current through diode = average o/p current , also average current through the inductor = average current through the source. From this I drew the following waveform. So,
EDIT
This was the part of the following question.
A DC-DC boost converter, as shown in the figure below, is used to
boost 360V to 400 V, at a power of 4 kW. All devices are ideal.
Considering continuous inductor current, the rms current in the solid
state switch (S), in ampere, is _________.
AI: From first principles for a waveform repeating over a period Tp being a current rising from Ii to Ii+Id.
\begin{equation}
I_{RMS}=\sqrt{\frac{1}{Tp}\int_0^{Tp} (I_i+\frac{I_d.t}{Tp})².dt}
\end{equation}
\begin{equation}
=\sqrt{\frac{1}{Tp}\int_0^{Tp} (I_i^2+\frac{2.I_i.I_d.t}{Tp}+\frac{I_d².t^2}{Tp²}).dt}
\end{equation}
\begin{equation}
=\sqrt {\frac{1}{Tp}(I_i^2.t+\frac{I_i.I_d.t^2}{Tp}+\frac{I_d².t^3}{3Tp²})_{t=0}^{t=Tp}}
\end{equation}
\begin{equation}
=\sqrt{ \frac{1}{Tp}(I_i^2.Tp+\frac{I_i.I_d.Tp^2}{Tp}+\frac{I_d².Tp^3}{3Tp²})}
\end{equation}
\begin{equation}
I_{RMS}=\sqrt {I_i^2+I_i.I_d+\frac{I_d²}{3}}
\end{equation}
If instead you consider this to be a ramp rising from i1 to i2 substitute i1 for Ii and i2-i1 for Id and you get
\begin{equation}
I_{RMS}=\sqrt {i1^2+i1.(i2-i1)+\frac{(i2-i1)^2}{3}}
\end{equation}
\begin{equation}
=\sqrt {i1.i2+\frac{(i2^2-2i1.i2+i1^2)}{3}}
\end{equation}
\begin{equation}
=\sqrt {\frac{(i2^2+i1.i2+i1^2)}{3}}
\end{equation}
This is independent of time and i1 and i2 are interchangable so where you have a ramp going from i1 to i2 and then back to i1 in one period this is your result and it is independent of duty cycle.
Now you need to average the result from above out over time.
To average two different RMS currents over a longer period (clue one of these can be zero).
Say we have Irms1 for t1 and Irms2 for t2.
\begin{equation}
I_{RMS}=\sqrt{\frac{I_{RMS1}^2.t_1+I_{RMS2}^2.t_2}{t1+t2}}
\end{equation}
So where you have a ramp going from i1 to i2 for t1 and no current for t2 we get.
\begin{equation}
I_{RMS}=\sqrt {\frac{t1}{t1+t2}.\frac{(i2^2+i1.i2+i1^2)}{3}}
\end{equation}
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H: Is this transformer-less power supply a good idea?
This is based on a design I found somewhere , I just wanted to know whether this is a good idea ,I intend to use this to power a microcontroller and a 70 ohm 5 V relay . The cap c1 limits the current to about 200 mA , well below the 500 mA rating of my zener diode . Without the zener diode , it looks like there would be about 7 volts across r1 which the zener should regulate . Ripples might be a problem though but I don't think it should affect switching that much , I'll also add a flyback diode to this .
Also , I get it that no insulation is a bad idea in general but I need this to be cheap and small . If anyone has got any better idea , I'll be happy to hear .
edit: C1 should be 3 uF
AI: I've used this type of design before but it should only be used with care and packaged in such a way so that nobody can easily access any connections - all connections have to be regarded as lethal.
I would add a current limiting resistor in series with the input capacitor because you cannot rule out fast transients occurring on the incoming AC supply and this could cause very large current peaks and potentially destroy the zener and then you have a knock-on problem if it goes open circuit.
Clearly also your diodes need to be rated at the correct reverse potential for AC mains in your neck of the woods.
C1 does seem excessive at 3uF - it's impedance at 50 Hz will be about 1000 ohms and, from a 230 V AC supply will draw a standing current of about 220 mA RMS - that's quite a lot of bad power factor load but if it's a one-off then probably OK.
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H: Opamps used in low voltage applications
How is it possible to use op amps on a supply of (+3v), for example: mp3 player and other battery operated devices?
What type of op amps do we use in low voltage applications?
How is it possible they have such a big output voltage in relation to the supply voltage?
This is my first time dealing with op amps in low voltage applications. I'm grateful for any kind of feedback.
AI: How is it possible to use opamps on a supply of (+3v), for example:
mp3 player and other battery operated devices?
Bipolar transistors in linear operation probably only need about 0.6 volts to operate properly at the base and maybe 1 volt across collector to emitter to yield a usable output voltage range. MOSFETs need a little more but not much more. Both/either are used in op-amps.
what type of opamps do we use in low voltage applications?
We have to use what are called rail-to-rail opamps because these are specifically designed to maximize the range of the low voltage available for powering the device. "Rail" aka power supply rail or supply voltage.
how is it possible they have such a big output voltages in relation to
the supply voltage?
They can only produce output voltages within the power supply range. For instance, if the power rails are 0V and 1.8 volts then the output will be limited to a range of 20 mV to 1.78 volts (under no-load conditions). Some are worse than others of course.
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H: DC motor noise filtering
I have some brushed motors near to a 433 MHz RF receiver. They're controlled by a 490 Hz PWM signal. The electrical noise they produce is not a problem for the circuit, but it is for the receiver.
How can I reduce the noise, at least on the frequencies interfering with the transmitter?
I read that putting a ceramic capacitor across the motor's terminals and one from each terminal to the motor's case would help; if it's true, what size should they be? I unfortunately don't have technical information about the motors. I'm quite sure they're the same as those, but there isn't much data on that site...
AI: I read that putting a ceramic capacitor across the motor's terminals and one from each terminal to the motor's case would help; if it's true, what size should they be?
You read the truth. Keep the leads to the caps short. 10nF is a reasonable sort of size, but you can go bigger or smaller if you have other sizes to hand.
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H: Saving component library preferences in KiCAD
I have a local component library that I use in most designs. I've been adding this to the library list in Eschema for each new design because I can't figure out how to add this permanently via preferences or something. Is creating a template the right/only way to make this permanent, or is there a better solution.
Thanks.
AI: The libraries are populated by the default template, so you would need to adjust that to have additional libraries added by default.
Personally, I find Chris Pavlina's solution to be the cleanest:
https://raw.githubusercontent.com/cpavlina/kicad-schlib/master/create_project.sh
This creates a new directory with a shallow copy of footprints and libraries and maps the config files appropriately. I use a fork of this to maintain my own libraries and push back to GitHub any changes, so my next project inherits the updates.
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H: Does a simple bug detector detect electric field or magnetic field?
Hi.
This is a very cheap and simple bug detector that is supposed to make sound
when it detect RF signals between 100Mhz-2600Mhz.
I found out that it doesn't do what it supposed to do,since its
sensitivity is very poor.It detects signals of some mobile phones(while some mobile phones it doesn't detect),wi-fi transmitters,garage doors remote control signals etc.at a distance of maximum 5 cm in the best case.Thats all.
Regard to my description,What may be the method of that cheap bug detector:detection of magnetic fields,electric fields or maybe both?
EDIT:
This is the pcb circuit of the detector.
AI: It detects radio waves – it has an antenna. And: It's completely useless by design.
One thing to realize is that if someone clever was to construct a bug in the year 2016, it's not going to be an FM transmitter generating 100mW of output power constantly; that would both waste power and make it easy to find.
It's much more likely to be a "silent" recorder (you can record years of cell-phone-quality audio on a microSD card...) that can be triggered remotely to transmit its data only when the sniffing party considers it safe to transmit. There's a famous example of a small sculpture that contained a membrane that could vibrate with air pressure – turning it into a audio-modulated RF retroflector when illuminated with radio waves from across the street. Of course, that illumination did not happen while the friendly intelligence service was scanning the room for active transmitters.
So, having one of these is essentially snake oil. This isn't the movie, where you can rush into a room, scan it with a magical electronic device, and declare it "clean".
Another thing to consider is that even when the bug was actively transmitting, it would almost certainly use spread-spectrum technologies. Spread Spectrum is a World War II invention (aka "old news"); it's used to distribute power in a wider part of the spectrum, either to make it possible to make communication more resilient to interference, or to hide the transmission, even below the level of noise that is inevitable in every receiver at room temperature.
Yet another thing to consider is that you need much less power to transmit little information over short distance (like a bug probably does) compared to transmitting much information over large distance (like a TV tower does). In fact, if you are within 10 km of a 660 MHz TV station (secondary, or so-called "low-power") with 15 kW power, you'd get about -28 dBm ("dB Milliwatt", usual unit when dealing with radio communication devices) at where you are. If your bug chose a frequency right between two TV channels, and only needed to transmit 30 m instead of the 10 km, and the bug receiver was as sensitive as 25-year-old cellphones (-120 dBm sensitivity), the signal transmitted by the active bug would need to be 20 dB, or 100 times, weaker than the power of the TV station that you receive at the same place.
In other words, you can't "see" that bug between the TV stations without knowing that there should be nothing between the TV channels. And even if you knew, TV is just one of hundreds of things that communicate. I have absolutely no idea how you'd go and find an even mediocre clever unknown bug without military/intelligence agency-class automated signal classifiers...
No matter how you put it, if you need to be paranoid about bugs, you need to live in a copper-shielded hole in the ground, or make mechanically sure the room your sitting is free of bugs and holes through which acoustics could be extracted.
In no case whatsoever is this device capable of doing anything useful.
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H: Why do (microphone) preamp designs tend to limit opamp gain to max 60 dB?
Looking at many pro recording quality microphone preamps, I noticed that every design I looked at that uses an opamp (discrete or IC) limits the gain provided by the opamp to about max 60dB. While most preamps use another stage (transformer(s) or another opamp) to get to 70db or even 80dB, I wonder why they don't just use the first opamp to get there. From what I understand, there would be some advantages:
better signal-to-noise ratio as voltage gain rises,
simpler audio path,
less parts & cost.
Does it have something to do with opamp stability over 60dB?
Here is a typical schematic. R12 limits gain to 40.1dB. I'm using these formulas:
$$A = 1 + (R_{fb}/R_{in})$$
$$gain_{dB} = 20 * log(A)$$
I also noticed that complete mic preamp ICs made by THAT-Corp also have a maximum gain of 60dB.
AI: Gain/Bandwidth product, you want maybe 50KHz bandwidth at 60dB (1,000 times), so you need somewhere around 50MHz, gain/bandwidth product (And more would lower HF distortion)... Make it 80dB and now you need 500MHz GBP, which is getting difficult if you want low noise down near DC (And is getting really bad news to stabilise at low gain).
Also consider that the noise is completely dominated by the noise for the stage having the first 20 or 30dB of gain (Do the maths), there is a lot to be said for splitting things so that the first maybe 30dB of gain happens in a low noise stage designed for low Z sources and low 1/F noise, which now only needs a few MHz of GBP and will be easy to stabilise even with weird source impedance. Then do the rest in a second stage (where noise matters less and you have a known source impedance).
The other difficult thing is that control laws that make sense become increasingly tricky if going for a one knob gain control, a classic instrumentation stage with have a gain setting resistor varying from a few ohms to maybe a few k ohms, which if you think about it is only maybe 3 orders of magnitude, very difficult to make a reverse log pot have more range then that.
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H: small brushed motors thrust
I built a quadcopter. It had a very low total thrust/weight ratio, and after I added some components it doesn't fly any more, so I want to change its motors and propellers in order to increase thrust.
The total weight is around 90g; of this, 26g are the motors (20mm brushed motors).
Is it possible to generate [64 + motor weight]g of thrust with 4 brushed motors, each with a small propeller?
If it's possible, what kind of brushed motors and propellers should I use?
Here are my actual motors/propellers; I don't have technical data about them because I don't remember where they come from (I have the since a very long time).
Looking around on Google I found those images; in the motor image's site I found some information, but not very precise...
AI: I recommend looking for spare motors for existing quadrotors and back-calculating from here. Here is one example:
Google for "quadcopter dc motor"
First link: http://www.robotshop.com/en/crazyflie-20-mini-quadcopter-motor.html
Corresponding quadrotor: http://www.robotshop.com/en/crazyflie-20-mini-quadcopter.html
Notice motor weight: 2.7 gramm and whole copter: 27 g + 15g payload
This means total trust is 31g + motors' weight
So these motors do not work. Search for the next motor and repeat the exercise. Keep the notes in spreadsheet or a text file. If you checked 30 motors and none of them worked it is time to give up.
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H: NOT gate with transistor
(source: electronics-tutorials.ws)
When A is powered, why does the current go to the ground and not to Q?
AI: For the purposes of the NOT gate, you are looking at voltage and not looking at the current. The next "logic unit" that follows will be designed to consider the voltage at OUT, not the current.
Mostly.
In order to consider the voltage, the next circuit will necessarily sink or source a little current (into or out of OUT.) So in reality some current also actually does get exchanged through the OUT pin. And the more logic unit inputs you tie to this output, the larger this current becomes. At some point, the circuit you show won't be able to properly do its job. So there is a limit called "fanout."
But for understanding it, you only need to realize that it is the voltage present at OUT, not the current, which defines the meaning of OUT.
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H: Mixer line in max voltage
I have built a tube amplifier and modded it with a line out for headphones based on this article.
I measured the output voltage on the artificial "line out" is peaking around 4-5V.
As a reference I also tested what my mp3 player delivers and that is around 500 mV
is it safe to introduce 5 V to my mixer (Behringer Xenyx 502) line in?
the manual specifies that the line ins are "designed to handle typical line level signals".
based on this post typical is around 300mV, however it may peak to 3 V
I might have answered my own qustion, but a confirmation would be nice
thanks
AI: It should be fine. If it's too loud, just turn down the gain in the mixer.
I don't know about the Behringer1 specifically, but most professional audio gear uses ±15 V power rails on its line input and line output circuits, because peak signal levels can readily reach ±12 V or more.
1 The manual states that it can handle +22 dBu, which would be a signal that reaches ±13.8 V peaks. (0 dBu is 0.775 Vrms, multiply this by 1022/20 and then by √2 to convert from RMS to peak for a sine wave.)
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H: Low-cost way of shining a wide line of light, kind of like some bar code scanners do
What is a cost-effective way (say roughly $15) to shine a wide but thin beam of light, directly away from the source, so that it would project a line onto a nearby surface?
My particular beam would need to be about 4' wide and maybe 1mm-4mm thick. The light would not necessarily need to be parallel like a laser, but needs to be pretty focused (1-4mm) for the full range between 1" and 4" from the source, so that if an object is moved within that range, the beam projected on it is always thin, and fairly parallel so that ~0.25" bumps on the object would not block parts of the line.
I considered using a strip of SMD LEDs behind an acrylic lense that is concave along the thin axis, and plano (straight) along the long 4' axis, at a distance such that the light focuses to a line in that 1"-4" range...but that would probably be a long focal length, which would require more space than I might have. Also the LEDs would need to be spaced such that the overlap of each LED's contribution makes the line fairly even in intensity. But before going that direction, I wonder if there is a better solution.
AI: Laser line projectors are very cheap and range from $2 - $20+ based on power and color. The cheapest are Red, the more expensive are Green or Blue. Some of the power ratings are getting quite high now...for example here's a 20mW Blue with a decent mounting/heatsink and line or cross lens
If you need a white line then your idea with LED's is OK.
I have built an edge light using a simple Acrylic rod as the focus element with narrow angle SMT white LED's, but it's really difficult to get a focused line of your size, but it's not bad at 10-15 mm width.
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H: What is the meaning / significance of this Capacitor Symbol?
In the SanKen data sheet for an Off-Line PWM Controller (found here) they use, in several places, a schematic symbol for an electrolytic capacitor that I haven't seen before (see C6 in the image below).
The image was taken from Chapter 12. Reference Design of Power Supply. And from the Bill of Materials they list "C6 Electrolytic 22 μF, 50V".
What is the meaning / significance of the the three slanted lines on the capacitor symbol?
AI: It's just a electrolytic capacitor. That's a old way of drawing it not used much anymore. They aren't trying to tell you anything special, which is confirmed by the BOM.
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H: Should I use li-ion CR1220 cell or a different chemical type?
I have bought an RTC module that needs a CR1220 coin cell, but is supplied without one. Should I use a Li-ion cell or a different chemical type, and what advantages or differences are there between them? I cannot find any guidance at all so far on-line.
AI: A CR1220 is a lithium/manganese dioxide cell at 3V. It's a non-rechargeable coin cell battery with about 40mAh capacity.
A lithium ion cell is a 3.7V rechargeable cell with a massive range of capacities.
Can your RTC operate on up to 3.85V without issue? Do you require increased capacity or rechargeability?
I would just go with the CR1220. You'll get a higher energy density from the Li/MnO\$_2\$ and the proper voltage.
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H: Purpose of capacitors and extra resistors in the feedback of the inverting op amp?
I'm trying to fully understand this opamp configuration but i can't. The signal enters through R19 and i understand that is an inverting configuration and is attenuating the signal with a gain of G=1.2/7.5, but i cannot truly understand what are the functions of both capacitors and the resistor of 24ohm. I think the 24 ohm is a current limiter resistor, but why put in the feedback loop ? And i think the feedback capacitor creates a low pass filter.What would be the cutoff frequency of this filter ? Because in the literature of this circuit its written it has a -3dB frequency of approximately 198kHz
AI: It is a fairly standard ADC driver topology.
Modern ADCs often have switched capacitor architectures that need a fairly large cap local to the input to provide the very fast current pulses that the things draw while performing the conversion, 10nF is a bit larger then you usually see, but not orders of magnitude so.
Now, opamps do not do well directly driving capacitive loads, as it can very easily cause a stability problem, but often you really want good accurate control of the ADC input voltage, so what is a guy to do?
The first thing you do is place a resistor between the opamp and the cap, a few tens of ohms is typical, which isolates the capacitive load from the opamp output, but hurts accuracy, as the feedback is now taken from the wrong side of that resistor (But at least the thing no longer honks)...
If you move the feedback tap to the load cap side of the resistor then the effective output impedance goes down, but now you have the stability problem back again.
However, the phase shift due to the load is frequency dependent so by placing a cap directly around the opamp then you can ensure that both the gain rolls off with a corner at roughly 1k2 * 820pf, and that at high frequency the feedback phase angle is dominated by the 820pF cap and not the phase lag due to the 10n cap.
At low frequency the gain as seen at ADC3 is -1.2/7.5 with good dc accuracy, there is a -3dB breakpoint at w = Rfb * Cfb, which serves to both limit the bandwidth at the converter and reduce the stability damaging phase lag from the 10nF cap at high frequency.
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H: Read Fuel Tank level voltage and send via Wifi
In most cars the fuel level is measured by a floater connected to a potentiometer and it's quite likely that the panel is reading an analogue voltage signal coming from the fuel sender unit.
What would be the cheapest way to read that voltage, then send it via WiFi to a listening unit. (the listening unit is already finished and awaiting implementation)
I'm looking for a permanent solution, something that can be placed in the vehicle with an autonomous battery (or connected to the car battery).
Please keep in mind that i'm not an Electrical Engineer, i'm a software engineer with a hobby in this area, but i've never done anything this complex before, so if you can point out ideas or components used that be great.
^^That is the fuel tank pump.
AI: You can use an ESP8266. It takes care of the Wifi and has a suitable ADC (10-bits which is more than good enough for gas tank level).
The level sensor (aka 'sender' in automotive parlance) will be something like a low resistance rheostat. Getting specs on it may be challenging or you could just test one. You will need a small bit of circuitry between the two.
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H: Cost Effective Laser Detection
I am a novice / hobbyist and I have a project in mind that involves detecting where a laser is aimed at on a relatively large scale (300+ sensors). I've found circuits that would work on a small scale such as a phototransistor or a comparator IC to compare resistances, but I have absolutely no idea how to scale this up in a cost effective manor. This will be used to then output digital logic signals to a microprocessor. Any ideas?
AI: you could assemble a photo-resistor array, if you're looking for a cheap, small, precise measurement of the location of a dot. You will need a number of Input equal to the number of rows + the number of columns, wired up like so:
instead of LEDs, use photoresistors. wire all 'R' wires to a 5k pullup, and all 'C' Wires to a 5k pulldown
You can buy a hundred of these for about 10 cents a piece, probably less, and make a 10x10 matrix for 10 USD.
if you don't need that sort of precision, I agree with ambitoise, and check out some image recognition solutions.
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H: ID Resistor value
Working on a Ferguson 14M2 CRT TV (220V/50Hz). Dead.
Have identified at least one suspect in the hot zone. R88.
Have tried for hours to find a diagram online, but to no avail.
I believe it to be a 1.8 Ω resistor, but would appreciate a trained eye to have a look before I order. (Not a single shop in the entire capital of Norway that sells this over the counter :()
Here are some images:
Could it be a 1.9 Ω? And if so, what is the risk of inserting the wrong one?
1.8 Ω ± 5% => 1.790 - 1.890
1.9 Ω ± 5% => 1.805 - 1.995
AI: It is/was very likely a 1.8 \$\Omega\$ resistor, as 1.8 is member of the common E12 series.
Also the second ring still looks gray (8), not white (9); although it could have changed it's color a little bit by overheating.
Without knowing more about the circuit there is no way to tell anything about the risk of using a (totally) wrong value. Although using a 1.9 \$\Omega\$ one (if you find one) instead of a 1.8 \$\Omega\$ with 5% tolerance obviously wouldn't be a problem.
What's more important is to make sure
no other parts are damaged
the problem that is the cause for overheating has been fixed.
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H: Increased current draw in data transmission circuit
Ok so here's my question. I'm fairly new to electronics research, my background is chemical engineering, but I'm attempting to improve my understanding of basic circuits and data transmission for my work. For this issue; I have a problem, and a solution, and I'm trying to work backwards to figure out why that solution solves that problem.
What I'm working with is a device that's transmitting data. DC voltage is supplied to a device, the device then attenuates the DC voltage to create a modulated current which is sent back to a computer and interpreted as a digital information signal. An issue was occurring where a new version of these devices would not transmit any data all. The way it was explained to me was that the new versions were not drawing as much current as anticipated so the modulated current being sent back was not high enough to be interpreted as a logical 1, so the computer was essentially receiving all 0's.
I don't have specifics about the circuitry of the end device, nor any diagrams or anything like that, but I have the solution. To solve this problem one standard ~10,000 ohm resistor was installed, that's it. Again I don't know exactly where or how. I want to know how this could work.
My only theory that makes sense to me is that this resistor must have been installed in parallel to the circuit, reducing overall resistance and allowing enough current to flow that the computer could distinguish the incoming modulated current between logical 1's and 0's. Does this sound on track at all?? I'm sorry if this was confusing, but it's a bit of a puzzle and I'm very curious to see if my theory is correct and to learn a bit more about electronics. Thank you. Ask questions if you have any.
AI: It's a question of switching threshold.
For simplicity, let's suppose that the supply voltage is 10 V, so that the added 10 kΩ resistor is drawing 1 mA.
The device receiving the data (Rx) is monitoring the current being drawn by the transmitting device (Tx) from the 10 V supply. If this current is above a certain value, say 5 mA, then the Rx tells the computer that the value is "1", and if the current is below that value, the Rx tells the computer that the value is "0".
So, we'll postulate that the older Tx devices drew either 4.5 mA to send a "0" or 5.5 mA to send a "1".
The newer Tx devices, for some reason, are only drawing 3.5 mA for "0" and 4.5 for "1". Since both of these values are less than 5 mA, the Rx device always reports this as "0". But by adding the 1 mA drawn by the resistor, the total current seen by Rx is now 4.5 mA and 5.5 mA, respectively, allowing it to decode the data as intended.
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H: Clarification on using software serial with AVR's
Arduino appears to be able to use software serial on any pins you choose. I am trying to test the same scenario on an atMega128 however, all of the examples and notes I find require using the RX pin on External Interrupt 0 which is PIND0. I have successfully implemented TX on any pin I choose. My question is very specific. Can a RX pin for software serial be implemented on any GPIO pin I choose? If so, is there an example of how to test this. I Have not been able to get the RX working in my environment. Thanks
AI: AVR305 explains how to implement a software UART on any two pins. Note that not using an interrupt means that the CPU busy-waits on the start bit instead of being notified when reception should begin.
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H: Altium Panelizing
I want to send my board to production however i am not sure a component's actual sizes because there is not enough information on its datasheet. I put its image and the necessary dimension "x".
This is the datasheet information;
This is the necessary size for me, shown by "x".
I could not find "x" from datasheet drawing that i put above. This is a "Vectronix DMC-pico" digital magnetic compass. I am considering to send for prototyping as versions because i am not sure actual dimensions. I mean i want to prepare 10 versions on a single board like panelizing for protoype on Altium, however i intent to draw different size of "x" as 0.85 mm, 0.90 mm, ... , 1 mm, 1.05 mm for a more precise result. I tried to do this on Altium but it allows me panelizing the same board only. Do you know a way that i can put different versions on a single panelized board on Altium Designer?
Thank you
AI: The option you are looking for is called Embedded Board Array.
I do not have access to the data sheet. Notify the manufacturer of the error. Some will fix it within days. You can take these measurements of they supplied a .step or dxf of the product. My usual method is counting pixels and it gave me a measurement of 1.2mm ± 0.1mm on a scanned version of the module.
Good luck!
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H: What effect does using a termination resistor that is larger than the characteristic impedance of the transmission line?
I have seen that when terminating an RS422 point-to-point connection, you should terminate the signals with a parallel resistor that matches the characteristic impedance of the transmission line. Most sources recommend 100-120ohms. I saw another post here that mentioned the effects of using too small of a terminating resistor, but what happens if you use a terminating resistor that is double, or 10 times the value of the characteristic impedance of the line?
AI: On an open end, a short pulse will be reflected and travel back the line.
On a shorted end, a short pulse will also be reflected, but inverted, too.
A resistor dampens this effect, i.e. the amplitude of the reflected signal will be smaller. And for a certain value, the pulse will not be reflected at all. This is the value used for termination.
Usually, transmitted signals are not short enough to be reflected completely, but every edge would cause a reflected pulse, which causes all kinds of trouble.
See also What and Why's of termination?
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H: Switch quickly between sets of layers in eagle
Is there a way in eagle to quickly switch between sets of layers? e.g. all top layers, all bottom layers, both top and bottom.
Currently, when I want to see only the top layers, I have to click / unselect, Bottom, bPlace, bOrigins, bNames, bValues, bCream, bDocu.
AI: Are you aware of layer presets?
Select the layers you need for the current view and then click and hold the layer button to create a new preset.
Repeat for the common layer configurations you need. Something like "Top routing", "Bottom routing", "Mechanical", "Placement" and so on.
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H: delta-wye with dependent sources
I was looking through some problems in Nilsson's book and this one caught my attention:
The variable of the dependente source is in the \$4\Omega\$ resistor, which is part of a "delta" type of resistor's network. If I perform the delta-wye transformation: (1) the resistance values would change; (2) the variable could be in two different resistors. I made a simple simulation of another delta network comparing with the wye equivalente and the current values were very distinct, the topology of the circuit was also very different .The original problem wants you to use SPICE, but I am curious on how to deal with it theoretically, or if it is possible to perform the transformation in this case. Thanks for your attention.
AI: If you delta-wye three components, and without mathematical errors, then the currents and voltages at the 3 nodes of the triangle you have transformed will be identical. This can allow you to series or parallel with other components to simplify the circuit more easily. Because you have changed the topology of the components within the triangle, their conditions will be very different.
Of course if you have made your target component vanish by doing a delta-wye, then you will have to get it back again at some stage to answer your question. If after a delta-wye, you absorb some of that component into others, then that's going to be tricky!
Where delta-wye might help is if you can use it to solve all the voltage and current sources. Then when you go back to the original problem, you know all the sources, and the solution of the original mesh might be easier.
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H: BLDC motor control hall effect invalid
I am a student EE major working on a control algorithm for a 3 phase sensored BLDC motor. Currently the motor is running well. I'm currently pursuing fault condition safety software for the motor. One possible fault that could occur is an invalid state read in for the hall effect sensors.
If the hall effect sensors read in 000 or 111 that means either one of the hall effect sensor's is shorted (111) or one is disconnected (000). My question derives from how to respond (in my control software) to a condition such as this?
Obviously if a hall effect sensor has gone corrupt (short / disconnected) I need to stop the motor from commutating. However, I'm worried that if this invalid state is caused by a fluke then I would not want to force the motor to stop immediately.
My current thoughts would be to just increment a counter each time an invalid state gets read in, then if 10 invalid reads come in consecutively I would stop the motor for good.
Thoughts? Am I crazy to think that hall effect sensor inputs straight from the motor could randomly be incorrect?
The more I think about this "issue" the more I'm leaning towards trusting the hall effect sensor data absolutely. If a random bit were to flip in the transmission the commutation pattern wouldn't be correct...
Thanks
AI: You could implement back-emf as a backup control system to aid detecting fault conditions matching sensor data and rotor position calculated by back-emf, thus being able to detect even those fault conditions producing a "good looking" set of values, and eventually bring the motor to a soft stop using BEMF for rotor position detection.
Another option, if you want to go the fault detection way, is to implement redundancy in your sensors and communication line.
This can be implemented in various ways and probably is the best way to add a functional fault detection that not only detect faults but also enables you to not have to immediately halt the motor.
If both such solutions seems too complicate you probably are in a case were a serious fault detection algorithm is not needed and stopping the motor in case of incoherent data is "just the right solution" so you can fix that cold soldered hall sensor before finals :-)
As far as fault detection goes is probably more important to focus on current detection.
Have fun! :-)
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H: How to get -5 to 5V with AD5668
I'm more programmer than electrical engineer. I have connected Arduino with an AD5668 DAC. I want to control analog synth such as Korg MS-20M. For the filter, it takes -5 to 5V.
Right now I can generate only 0-5V with digital values 0-65535.
I want to generate -5V to 5V straight out of Arduino with digital values 0-65535.
AD5668 takes a reference voltage. Right now I supply it 5V from Arduino. Could this be a solution? To supply -5V reference voltage? I would like to make some simple DIY solution hopefully without any new parts in the circuit. I was thinking that AD5668 has all the required in itself like OP-AMP, but I guess it does not generate smooth -5 to 5V voltage.
AI: The AD5668 can only supply 0-5V at its outputs (or 2.5V if you use the -1 version with internal reference). The reference voltage has to be essentially within the supply rails. Applying -5V will destroy the chip.
If you need -5 to +5 you will need to add an amplifier/level shifter at a given output- to multiply by 2 and add a suitable offset. That will require a negative supply of at least -5V (you won't quite get to +5 or -5 with a +/-5V supply).
Here is how I would do it with this particular chip (-2 version with 0-5V out):
simulate this circuit – Schematic created using CircuitLab
You only need one reference buffer (OA2) but you do need one amplifier per output. The output op-amps require power supplies of at least +/-5V. If you use closer to +/-5V you will need rail-to-rail output and input common mode range must include 3.33V. eg. OPA2188. You do need the reference buffer because the output impedance of the internal reference is 7.5K ohms.
The stability will only be as good as the reference, so using the internal precision reference makes a lot of sense. If you were to use the power supply you would add a lot of noise and imprecision into the output.
If you want high accuracy commensurate with the 16-bit DAC you can use a single precision resistor array for the two pairs of resistors such as a Vishay ACASA1002S2002P1AT.
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H: Is there any difference between the terminals of the rheostat
This is probably a dumb question but I just wanted to be sure for my practical exams.
Is there any difference between the upper or the lower terminal of the rheostat? Are you supposed to connect the positive terminal of the battery to any specific terminal of the rheostat or is it all the same? Thanks in advance.
AI: No there are no differences other than physical position. The rheostat is just a variable resistor with no regard to polarity. After all, it works perfectly well on AC but, if you pushed the frequency up to the MHz and beyond then maybe you'd start see some effects. You might also see some polarity effects in a damp corrosive atmoshphere too.
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H: AC and DC voltage wire areas
is their a difference between the surface area of the weir that i use for 1A AC voltage source and 1A DC voltage source ?
AI: Skin effect and proximity effects are caused by AC magnetic fields affecting the usable part of a conductor for passing current. As frequency rises skin effect worsens but only as a square root of the frequency increase.
This means that DC resistance is lower than AC resistance (and I'm not talking about inductive reactance here). Skin effect: -
Skin effect is not negligible at 50 Hz for power transmission systems. At 50 Hz copper has a skin depth of about 9 mm making it very problematic for power distribution: -
Proximity effect occurs when AC currents are flowing in side-by-side conductors - the interactions between the magnetic fields produced tend to reduce the usable conductive part of a cable even more: -
The picture above is when the AC currents in each wire are in-phase (as happens in power distribution cable bundles. The picture also shows a level of skin effect.
This is a useful link for understanding both effects.
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H: Understanding voltage and current of a phototransistor w/ collector resistor
I want to study the circuit of an Infrared proximity sensor, so I assembled a circuit with an infrared LED (940nm) and a phototransistor.
When no current passes from the LED, obviously the phototransistor is switched Off, thus the whole amount of current passes from the A0 branch. In that case I read from A0 a 1023 value which is equal to 5V for a 10bit ADC (Arduino).
When current passes from the IR Led, thus the Led is on, the phototransistor should be switched On, thus a considerable amount of current should pass from the phototransistor to Ground. Yet, even if LED and phototransistor are positioned extremely close, I read from A0 a value no less than 900, which means that only a 10% of the total current reaches the Ground.
I expected (and desired) when the IR Led is On, the value of A0 to be near zero, thus the phototransistor to be fully open and almost the whole current to pass from it.
Do I miss something there? Should I change something to the circuit or the components, in order to get an almost clear 0V or 5V?
AI: Read the datasheet. It should tell you what the expected phototransistor current will be. That is apparently not enough to cause 5 V across a 10 kΩ resistor.
Do the math. At full illumination, the A/D reads 900 out of a 0-1023 full scale range, which is 5 V. That means the output is at 4.4 V, which means that there is 600 mV across the 10 kΩ resistor, which means that the current is 60 µA. That is apparently the current your phototransistor can support with the illumination you are supplying.
There are several things you can do about this:
Nothing. As things are now, you can read the illumination to one part in 123, or basically 7 bits. Is that perhaps already good enough? What are you really trying to measure. For many applications, 7 bits plenty.
Use a larger resistor. In this case, the pullup resistor is being used as a current to voltage converter. You can think of the resistance as being the gain of the conversion. A 20 kΩ resistor would give you twice the voltage, for example.
The downside to this is that the impedance of the voltage signal goes up. Check the A/D datasheet to see how high a source impedance it is specified to work with. For some A/Ds, higher source impedance can be tolerated if the acquisition time is lengthened. Again, consult the A/D datasheet to see what your A/D needs.
Amplify. You have a 600 mV signal that you want to be closer to a 5 V signal. That's exactly what amplifiers do.
In that case, I'd probably flip the phototransistor and resistor so that the signal starts at 0 V with no light and goes up with more light. A gain of 8 would just about do it.
If the value at low light levels is important, then make sure to use a opamp that can handle signals down to ground on both the input and output. Or, use a small negative supply from a charge pump or something so that 0 V is well within the opamps linear region.
Use a higher resolution A/D. Many microcontrollers have 12 bit A/Ds built in nowadays. Changing only the 10 bit A/D to a 12 bit A/D gives you 4x the resolution, or about 9 bits in this case. Is that enough?
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H: How is the minimum reasonable distance for the far field of a dipole antenna calculated?
First let me try to explain what I think the near field is about:
At very close ranges, due to the differences between instantanous voltage and current on each small segment of an antenna at any given time, the EM field is not uniform (spherically) yet. If the antennas (reciever and transmitter) are this close, the mutual inductions are lame and reactive. Induced currents at various segments of the recieving antenna could contradict and impede each other.
But I can't be certain about how the minimum distance (to avoid these negative effects) is calculated?
Some sources say the distance should be more than 2 wavelengths. Others say 10 wavelengths. Some calculate it as 50(L^2)/λ (L:antenna length) or 5λ/2π or λ/2π or 2(L^2)/λ. They all seem to be based on different ways of understanding/analysing.
Is there a safe method/equation commonly used in practice to calculate this minimum distance?
Edit due to comments:
You describe the near field as lame and reactive but they will still produce a decent signal in a receiving antenna so please explain your doubt or what the real problem is.
I have no references for this but if the EM waves have a finite and constant velocity, then the EM fields expanding from each segment of the antenna should be ariving at the other segments of the other antenna with a delay high enough to cause contradicting currents.
The "contradiction" should be more if,
1- The change rates of current and voltage over the antenna length from segment to segment is higher. It's hard to explain for me. If all segments of the antenna was introduced to a EM plane wave, all electrons would be forced to move at the same time, blocking or impeding each others movement/momentum less (like the situation in Betz limit or Carnot limit as a rough analogy. You try to push air with air and some of the momentum you give is turned into heat which I could define as "a sum of chaotic momentums with zero net momentum vector in total").
However, when the rate of change in magnetic and electric fields are more different on each segment of the recieving antenna, there should be disorder, concentration and rarefication of electrons at the same instant thus causing joule heating, impedance and "turbulant micro-currents" so to say. The efficiency of power transmission would be "lame".
All these simply mean that the wavelength of AC would be smaller relative to the antenna length (assuming the electrical signal velocity and AC amplitude is kept constant).
2- The distance between the antenna becomes smaller relative to the antenna length so that there would be longer time lags (phase delays) between various segments of each antenna. It's also not easy to describe. I
These are just my reasonings based mostly on studies on credible sources but don't anybody take them as scientific knowledge.
First you would need to define what you mean by "safe" or "reasonable" and that will be in terms of, what error can you accept, or what deviation from the far field model is acceptable in your specific application?
To clarify this I have little choice but to introduce the main problem I've been struggling to solve which is on the Physics Stack Exchange section. I don't know if this is against the forum rules so apologies in advance. I don't mean to ask the same question here of course:
https://physics.stackexchange.com/questions/293097/average-force-between-two-parallel-finite-wires-with-ac
Please check out the last comment made by Void. According to this comment, what I mean by "safe" is the distance that the electric and magnetic fields expanding from the antenna start behaving like a regular EM wave.
Interest only: The near field of the Jodrell Bank Radio Telescope - also used for deep space communications, extends to beyond the atmosphere. This tends to make pre-flight integrated system testing "hard" :-).
Wouldn't this like measuring the minute changes in the stray/parasitic inductances of a huge transformer? Just a wild guess.
Sorry for the lengthy edit. Maybe because I have too few friends around to talk about science.
AI: An antenna produces fields that fall into three categories: -
And, the generally accepted formulas for these are: -
So, if the largest dimension were 0.75 metres and the frequency was 100 MHz (i.e. a quarter wave monopole), the reactive near field is done at 24 cm and the far field begins at about 38 cm.
However, for a dish with diameter 7.5 metres (at 100 MHz), the reactive near field extends to about 7.4 metres and the far field begins at about 37.5 metres.
This site has a calculator and is where I took the formulas from. The formulas are generally accepted as being meaningful but, there are no hard and fast rules or limits.
This site also uses the same formulas and has a nice picture that shows how the fields gradually converge in amplitude to produce a proper EM wave at an impedance of 377 ohms (free space impedance). This is for an electrically "short" antenna: -
Wiki(Near and far field) also uses the same system for calculating the near and far fields: -
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