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H: How can I connect a USB keyboard to a DE1-SoC?
I recently got a DE1-SoC development board from Intel and I wanted to use it to instantiate a computer design I created while following along the Nand2Tetris course on Coursera. Unfortunately, this design requires a keyboard to be connected to the board and I do not have PS2 keyboards (only USB ones) or USB to PS2 adapters. While I could go and get the required hardware, I think that PS2 keyboards are becoming outdated, so I want to be able to use my USB keyboard. The board has 2 USB ports and according to this document, they should be able to interface to the FPGA fabric. Unfortunately, this guide specifies only how to instantiate a USB OTG port and how to connect its clock to the top-level design. It does not specify how to access the data coming from the USB. I have searched for specific instructions online, but so far I have found nothing. Is there a way to, say, display the scan code of the key pressed on a USB keyboard on the board's LEDs?
AI: The DE1-SoC Cyclon-V is a System-on-Chip, with dual ARM9 processors. The DE1 system board has a ULPI port connected to ULPI PHY, which is connected to a USB hub with two user ports.
As I understand from specifications, AN702, and from comments from Chris Stratton, the SoC provides two "USB On-the-Go(OTG) controllers". The USB 2.0 Hi‑Speed On‑The‑Go DWC_otg controller (see Chapter 18) is something that was created by Synopsis - a provider of hard IP - in place of more widespread and established EHCI controller.
To connect a keyboard to this system via USB, you need to make the system a USB host. To make it a USB host, you would need to enable the DWC_otg controller. To get across across the soldered-on USB hub, you will need split-transaction support. To make the DWC_otg operational, you would need to load full Linux OS with USB hub support, which means that you need a full running OS with proprietary DWC_otg support (actual datasheets for register-based access, AFAIK, are available only under NDA).
So, the USB access is "interfaced with FPGA fabric" via DWC_OTG controller, you just need a proper software to use it. Only then you will be able to communicate with USB keyboard on the DE1-SoC Cyclon-V.
Good things are that the DWC_otg hardware seems to be also used in Broadcom BCM2836 SoC, which is the core of Raspberry Pi, so the software might be running more or less smoothly. However, one needs to keep in mind that it took about 15 years for entire Microsoft to make the EHCI USB host running on PCs, so expect some glitches on the way with DWC_otg.
Alternatively, you can select three GPIO at 3.3V CMOS level, and emulate the entire USB host functionality (LS only) via bit-banging. Or create your own LS host controller with your own proprietary interface, to drive the ULPI interface and PHY directly.
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H: Self-made Schottky transistor doesn't behave as I'd expect
For a project of mine I need to generate UART-like signals with higher voltage (up to 18V) and a baudrate of 115200 bps and later possibly 250000 bps. I tried a basic BJT level shifter which worked as shown below:
(here and later: yellow in IN, green is OUT, plots are 2V/div and 5us/div)
I decided the delay due to BJT saturation may become problematic at higher baudrates, so I threw in a Schottky diode which helped:
However, that's not how a traditional Schottky transistor is made, and I have seen advice that it's better to avoid saturation in the first place rather than fighting the consequences. So I implemented the third prototype which didn't work as I expected:
I understand that the higher LOW level is due to the fact that I now avoid saturation, but the shape of the edges is totally unexpected, and can hardly be called an improvement.
Is this how a Schottky transistor is supposed to work, or can anyone offer an explanation as to why it didn't?
AI: Your Schottky diode is in lieu of a Baker clamp, which is like this:
simulate this circuit – Schematic created using CircuitLab
and the diodes are switch diodes; that 1N5819 diode is a rectifier, which has higher current (and stray capactance) than a switch. The 1N5819 is about 110 pF of capacitance, while a 1N4148 switch is 4 pF.
Circuit #2 might be showing the benefit of paralleling the base resistor with
a 100 pF capacitor, which speeds up transistor turnon and turnoff,
rather than the clamp benefit of reducing base charge storage. Your circuit #3 might be showing the capacitance C-B causing that ramp, so a change of component, from Schottky rectifier 1N5819 to Schottky
switch 1N5711, about 2 pF, should help. A small capacitor across R1 is
a good bet, too.
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H: Voltage induced in aircraft high-tension magneto ignition system
Why is there no voltage induced into the secondary winding (in high-voltage step-up transformer) when the ignition switch is closed (OFF)? When the current flows in the primary winding of the coil a magnetic field is generated. This interacts with the flux from the magnet. Assuming that the ignition switch (stop switch) is closed, the flow of alternating current created by the interaction of the two magnetic fields will flow to ground. Will the flow of alternating current in the primary (while the ignition switch is closed, OFF position) induce a current in the secondary? If it does not, why not?
AI: The switch does the same thing the breaker points do.
The breaker points open to cause a spark. At all other times the breaker points are closed.
This causes a magnetic field to build up - a flowing current causes a magnetic field.
Because the coil is shorted, the current is high but the voltage is low. So, if there's any voltage on the secondary it will be low as well.
Now, when you open the breaker points, the magnetic field tries to keep the current flowing. Since the breaker is open, the voltage needed to keep the current flowing would be high.
The transformer multiplies this high voltage (the voltage across the breaker can reach several hundred volts) to reach the tens of thousands of volts needed for the sparkplug.
The same thing happens when you close the stop switch. The current through the primary is high, the voltage is low, and so the secondary voltage is too low to fire a spark.
It is in fact the sudden opening of the breaker that causes the spark.
The more current flow through the primary, the stronger the magnetic field it can build up - it stores more energy in the magnetic field.
With more energy stored, you get more energy delivered to the primary when the points open - so, you also get more energy transferred to the secondary. More energy in the secondary means more voltage and current (for a longer time) through the sparkplug. That gives you a hotter, longer lasting spark that does a better job of igniting the fuel.
This is also why electronic ignition systems work better. They switch faster, so there's a faster change in the primary current. That leads to a faster change in current, which leads to a higher primary voltage and better use of the energy stored in the magnetic field.
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H: Can I touch resistor connected to mains power?
Can I touch resistor connected to mains power?
simulate this circuit – Schematic created using CircuitLab
AI: Of course you can.
Of course, a certain percentage of the times you do that you will die, but that's not what you asked.
Your circuit, as shown, is guaranteed to kill the LED, since on the negative halves of the power cycle as much as 310 volts will appear across the LED and destroy it. If you are lucky, the LED will fail short, and this will protect you. Murphy's Law ("Anything which can go wrong, will.") suggests that the LED will instead fail open, so touching your point will apply 220 volts to you. Of course, the 100k resistor will limit that current, but the result will still not be good.
As KH has answered, at your stage of knowledge, you should make an ironclad rule NEVER to deal with mains voltages directly. You simply don't know enough to deal with the hazards in a safe manner. Know your limitations.
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H: Why does an Instrumentation Amplifier need a reference?
I am working with the INA826EVM board and I am wondering why it needs an additional op-amp for a reference in the Instrumentation Amplifier?
AI: The core of an instrumentation amplifier is a differential amplifier, it simply subtracts voltages. To increase the impedance (the current from the output or reference can affect the signal, because there are only resistors separating the two) the input was buffered on the inputs of the differential amplifier.
People quickly realized that by tying the feedback loops of the buffer amplifiers, the Common Mode Ratio Could be increased.
The differential amplifier is the part that needs a reference, or at least needs to be grounded, otherwise the resistor matching wouldn't take hold and it would simply be an opamp with feedback, so in the least the resistor divider needs to be connected to ground. Or you can connect it to a different voltage to shift the output. This is extremely useful, because many ADC's are not bipolar (many go from 0 to 5V) and a bipolar signal needs to be shifted (by 2.5V) to get into that range. Or you could ground it and not need the shift.
Source: https://www.electronics-tutorials.ws/opamp/opamp_5.html
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H: Switching Regulator Voltage Dropping Unexpectedly
I am trying to determine what exactly is causing the below switching regulator/ DC-DC converter module to not maintain its rated output voltage.
http://www.meanwellusa.com/productPdf.aspx?i=794
I am using the SPBW03G-03, which has a listed maximum output current of 700mA and an output voltage of 3.3V. The input side of the regulator is driven by approximately 45 VDC (32 VAC rectified), which is within the 18-75V input voltage limit.
What I have observed is that essentially any load will draw down the output voltage of the regulator. At full load (all inputs on, all outputs/relays activated), I am drawing approximately 150 mA, which is well within the maximum output current of the regulator. The output voltage at my full load case drops to right at 2.98V, and holds there. When the load is removed, the regulator returns to just under 3.3V (measures at about 3.28 with DMM and Oscope). The voltage drop is most pronounced when the three relays are activated (note: the relays are rated for 3V operation) with the rest of the circuit having relatively small impacts on the voltage.
Below are snapshots of my schematic. I should note I have a dummy load in for the TeensyLC just for circuit testing, and am manually triggering inputs and outputs. I apologize for the regulator not being shown, I have not gotten around to adding it to my schematic yet.
This is the first project for which I have used a switching regulator, so am am wondering if there are any significant pitfalls that I could be missing. The Meanwell documentation is limited, but I know most of the other DC/DC modules suggest input and output capacitors, which I currently have not implemented.
If anyone has some suggestions as to what the issue might be, or what noobie mistakes I have made, I would appreciate the feedback.
AI: As embarrassing as it is to admit, it looks like the culprit is simply a bad breadboard connection. Replacing two jumper wires at a specific point on my + / - DC rails fixed the problem. Voltage is now 3.24V steady at full load.
I appreciate everyone's input, and will investigate my board a little more thoroughly before asking a question next time.
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H: Switch high voltage with triggered spark gap
I want to switch a high current/voltage pulse (up to few 10kV, <1kA) from a capacitor as supply. It needs to be cheap and I don't care about efficiency too much yet.
I took a look at using thyristors in series but I think it'll cost too much and could possibly be dangerous as without the correct balancing the thyristors break. I found old Thyratron tubes that I think would work, however I couldn't find them to buy (let alone buying newly made ones that are made for power electronics).
From the search of the vacuum tubes and getting to know all available tech I decided it would be cheapest to use a triggered spark gap.
Do gas discharge tubes (i.e. https://www.littelfuse.com/products/gas-discharge-tubes/high-voltage-gdt/cg3.aspx) work like a spark gap? My idea is to have a high voltage GDT in series with a smaller voltage triggered spark gap (i.e. https://uk.rs-online.com/web/p/gas-discharge-tubes/7606807/ / or homemade). I would then balance the voltage with resistors in parallel. I imagined to have it like this:
(I used a thyristor symbol as I couldn't find any triggered spark gap symbol.)
My thought is that by this arrangement the voltage supplied would divide to ~9 parts over the spark gap and ~1 part to the switch (when it is off). When the switch opens the resistance drops and the voltage over the spark gap rises creating an arc (when the voltage is sufficient). I know the resistance values are too low for above specs but this circuit is only for reference.
Would such approach work for switching an energy pulse of above specs?
(I didn't calculate the duration of the pulse yet, but I'd be surprised if the cap held for long as the spark gap would no longer arc at some point.)
If not please point out why and maybe guide me in a direction how I could realize this with cheap parts.
AI: Gas discharge tubes work like a spark gap, the difference is they have a gas encapsulated in glass. This lets you determine the breakdown voltage, whereas the breakdown of a spark gap in air would be different depending on conditions such as pressure, humidity, ect.
Source: http://g3ynh.info/disch_tube/intro.html
The circuit above may work, but you'd have to get a GDT that would trigger below the 10kV and above the voltage of the resistor divider.
Another option might be a triggered spark gap.
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H: Hold Pushbutton for soft latch after X seconds
What I'm trying to achieve is have a momentary push button that must be held for say 5 seconds before latching on permanently.
But the button must be held for entire duration or else timer will reset.
I'm looking at 555 timers but struggling to figure out how to auto reset on button release before timer finished.
AI: Try this.
S1 is normally ON. It keeps C1 discharged via the output of comparator U1.
When S1 is pressed continuously long enough, C1 gets charged to Vref. The comparator output jumps high. It stays latched because releasing S1 does not suck C1 empty.
Pressing S2 resets the circuit. R4 is only small, say 100 Ohm. It prevents the spark in S2. R3 can be for ex. 47 kOhm and R5 a few, say 2 kOhm.
Comparator U1 must have open collector output. It cannot drive any substantial load. You need for it a mosfet or other high current gain buffer circuit.
Not asked:
Like your 555, it uses only about 40 years old technology and is totally free of software problems, computer viruses, need of web connection, subscription payments etc...
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H: Why is this BJT Schmitt trigger producing a sine wave?
I am trying to build a Schmitt trigger from a pair of BJTs to convert a sine to a square wave.
The sine wave is from a Colpitts oscillator running at over 150 MHz. I want to measure the frequency using something like the SN74LV4040, which is why I want to square the sine wave somewhat.
This is the relevant part of the Schmitt trigger (with V1 representing the oscillator). Emitter current was set to 2 mA, high voltage to 3 V, low voltage to 2 V.
simulate this circuit – Schematic created using CircuitLab
But this is the output I get in LTspice.
Why am I getting a sine wave output from the Schmitt trigger?
This is the whole schematic (with some voltages plotted), if that helps:
AI: Kilo-ohms and over 100 MHz! You cannot get anything rectangular looking due the time constants caused by the parasitic capacitances, which can easily be 10 pF or more.
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H: Analysis of a modified Howland Current Pump
I am trying to do an analysis of the following modified howland current pump based on the circuit description in the datasheet of the LMP7701. This is a voltage controlled current pump that is driven by a sine generator with aroung 10 kHz.
simulate this circuit – Schematic created using CircuitLab
I want to derive the formula for the output current, that should only depend on the resistor \$R_s\$ and the input \$V_{in}\$. The formula is already given in the datasheet of the LMP7701 and in AN-1515:
\$ i_l = \frac{V_{in}}{R_s} \$
In order to derive this, I started with the followng nodal equations:
\$ i_1 = i_2 \Longleftrightarrow \frac{V}{R_1} = \frac{V_{out}-V}{R_2} \Longleftrightarrow V=\frac{R_1}{R_1 + R_2} V_{out} \ \ (1) \$
\$ i_3 = i_4 \Longleftrightarrow \frac{V-V_{in}}{R_3} = \frac{V_{L}-V}{R_4} \Longleftrightarrow V=\frac{R_4 V_{in} + R_3 V_L}{R_3 + R_4} \ \ (2) \$
\$ i_l = i_s \Longleftrightarrow \frac{V_{out}-V_L}{R_s} = \frac{V_L}{R_L} \Longleftrightarrow V_{out}=\frac{R_LV_L + R_sV_L}{R_L} \ \ (3) \$
Now I set \$ (1) = (2) \$ and derived after \$ V_{out} \$ to get
\$ V_{out} = \frac{(R_1 + R_2)(R_4 V_{in} + R_3 V_L)}{R_1 (R3 + R4)} \ \ (4) \$
Now I set \$ (3) = (4) \$ and solve after \$ V_in \$ to get
\$ V_{in} = \frac{R_3 R_s V_L}{R_4 R_L} \ \ (5) \$
Now, assuming that \$ R_1 = R_2 = R_3 = R_4 \$ and setting \$ V_L = \frac{R_L}{i_L} \$ I get that
\$ V_{in} = \frac{i_L * R_s}{R_L^2} \$
Which seems to be wrong, or am Imissing something? Are some of my assumptions wrong or are some things missing? I recalculated many times and tried different approaches but this is not my field and do not really now how to proceed further, would appreciate some help.
Thanks in advance.
AI: Unfortunately, for some reason I made a mistake and assumed that \$ V_L = R_L/i_L\$, which is obviously wrong. Setting \$ V_L = R_L*i_L\$ and doing the calculations again I get now \$ i_L = V_{in}/R_S \$ which is what I wanted to derive.
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H: What if I cut off an NC pin from an IC?
I am designing a circuit using an IC, LTC7004, which is a high-side MOSFET driver. There is one pin (10th) marked as NC.
NC (Pin 10): No Connect. This pin should be floated.
In my PCB design, I'm pulling out a track from the 8th pin which is the pin to connect the source of a FET as in the figure below.
If I can pass the bootstrap (9th) track over the 10th pin, I can have a wider track for the source connector than the one I currently have.
Since the 10th pin is a no connect pin, will it make a mess if I bend and break away the 10th pin from the IC? (Then I can design a custom foot print to have only 9 pins with the MSOP10 package dimensions). Should NC pins need to be soldered onto a PCB with isolated pads by any means?
AI: From an electrical point of view, NC pins need not to be soldered. Ripping it off or soldering it to a (small) pad makes no difference.
From a mechanical point of view, having it soldered or not can make a difference though. I am fairly sure that the manufacturer recommends a certain footprint in the datasheet, and that that footprint includes the pad for pin 10.
If you are confident that the other pins give enough mechanical stability, you can just cut it away as per your plans.
An even better option, from a manufacturing point of view, would be to just remove the pad for pin 10 from your PCB, and route the track from pin 9 right below it. The solder mask will guarantee electrical isolation, and there is no need to add a manual step to the manufacturing process. As Tom Carpenter as commented, there is a drawback: the solder mask thickness can prevent the chip to seat flush on the copper, thus leading to soldering issues in some cases.
Whether you trust your solder mask enough for this is a decision you should make.
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H: Quartus II selected a signal as a clock in combinational circuit
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port(
input1: in std_logic_vector(31 downto 0);
input2: in std_logic_vector(31 downto 0);
reset: in std_logic; --Asynchronous Reset
operation: in std_logic_vector(3 downto 0);
zero_flag: out std_logic;
ov_flag: out std_logic;
output: out std_logic_vector(31 downto 0)
);
end ALU;
architecture hybrid of ALU is
-------------------------Component Declaration------------------------
component kogge_stone_adder is
port(
input1: in std_logic_vector(31 downto 0);
input2: in std_logic_vector(31 downto 0);
ov_flag: out std_logic;
zero_flag: out std_logic;
output: out std_logic_vector(31 downto 0)
);
end component;
component two_complement is
port(
input: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0)
);
end component;
----------------------End Component Declaration-----------------------
--------------------------Signal Declaration--------------------------
signal adder_in_1: std_logic_vector(31 downto 0);
signal adder_in_2: std_logic_vector(31 downto 0);
signal adder_ov_flag: std_logic;
signal adder_zero_flag: std_logic;
signal adder_output: std_logic_vector(31 downto 0);
signal input2_comp: std_logic_vector(31 downto 0);
-----------------------End Signal Declaration------------------------
begin
process(all)
begin
---------------------------------Reset-------------------------------
if reset = '1' then
output <= x"00000000";
zero_flag <= '0';
ov_flag <= '0';
----------------------------End Reset----------------------------------
else
------------Case Statement to Perform the required operation-----------
case operation is
when "0000" => --ADD
adder_in_1 <= input1;
adder_in_2 <= input2;
ov_flag <= adder_ov_flag;
zero_flag <= adder_zero_flag;
output <= adder_output;
when "0001" => --SUBTRACT
adder_in_1 <= input1;
adder_in_2 <= input2_comp;
zero_flag <= adder_zero_flag;
ov_flag <= adder_ov_flag;
output <= adder_output;
--when "0010" => --MULTIPLY
when "0011" => -- COMPARE EQUAL
adder_in_1 <= input1;
adder_in_2 <= input2_comp;
ov_flag <= adder_ov_flag;
zero_flag <= adder_zero_flag;
if adder_zero_flag = '1' then
output <= x"00000001";
else
output <= x"00000000";
end if;
when "0100" => --COMPARE LESS THAN
adder_in_1 <= input1;
adder_in_2 <= input2_comp;
ov_flag <= adder_ov_flag;
zero_flag <= adder_zero_flag;
if adder_output(31) = '1' then
output <= x"00000001";
else
output <= x"00000000";
end if;
when "0101" => --COMPARE LESS THAN OR EQUAL
adder_in_1 <= input1;
adder_in_2 <= input2_comp;
ov_flag <= adder_ov_flag;
zero_flag <= adder_zero_flag;
if adder_output(31) = '1' or adder_zero_flag = '1' then
output <= x"00000001";
else
output <= x"00000000";
end if;
when "0110" => --SHIFT RIGHT
output <= '0' & input1(31 downto 1);
when "0111" => --SHIFT LEFT
output <= input1(30 downto 0) & '0';
when "1000" => --ARITHMECTIC SHIFT RIGHT
output <= input1(31) & input1(31 downto 1);
when "1001" => -- BITWISE AND
and_gate: for counter in 0 to 31 loop
output(counter) <= input1(counter) and input2(counter);
end loop;
when "1010" => -- BITWISE OR
or_gate: for counter in 0 to 31 loop
output(counter) <= input1(counter) or input2(counter);
end loop;
when "1011" => -- BITWISE XOR
xor_gate: for counter in 0 to 31 loop
output(counter) <= input1(counter) xor input2(counter);
end loop;
when "1100" => -- BITWISE XNOR
xnor_gate: for counter in 0 to 31 loop
output(counter) <= input1(counter) xnor input2(counter);
end loop;
when "1101" => -- BITWISE NOT
not_gate: for counter in 0 to 31 loop
output(counter) <= not input1(counter);
end loop;
when "1110" => --ROTATE RIGHT
output <= input1(0) & input1(31 downto 1);
when "1111" => --ROTATE LEFT
output <= input1(30 downto 0) & input1(31);
when others =>
output <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
zero_flag <= 'Z';
ov_flag <= 'Z';
end case;
end if;
end process;
------------------------Component Instantiation-------------------------
adder: kogge_stone_adder port map(
input1 => adder_in_1,
input2 => adder_in_2,
ov_flag => adder_ov_flag,
zero_flag => adder_zero_flag,
output => adder_output
);
complementer: two_complement port map(
input => input2,
output => input2_comp
);
----------------------End Component Instantiation-----------------------
end hybrid;
While synthesizing a combinational circuit, quartus II reported in timing analyzer that a signal called operation(1) is the clock and reported negative slack, operation is a 4-bit bus I really don't know why it chose this specific bit,so the question is How can I remove the clock from the design or How can I tell quartus that this is a combinational circuit ?
This is the full RTL view:
This is zoomed RTL view (the rest of the rtl is the doing the same thing to the other bits):
This message also appeared in the console during synthesis:
Does the above message is the reason for quartus to assign a clock ?(Synthesize latches instead of combinational logic)
AI: The Quartus toolset (and FPGA tools in general) are intended for synchronous design. Trying to use them to develop a purely asynchronous design requires a great deal of experience, and is still often an exercise in frustration.
Timing analysis in particular requires a clock, and if you don't assign one, the tools will try to pick a likely candidate — with less than optimal results, as you have found.
You're going to have to constrain every combination of input and output from your circuit independently if you want the synthesis tools to opimize the implementation correctly. This quickly becomes unmanageable for anything but the most trivial of circuits.
Note that this is a generic answer. If you want help with your specific problem, show us your code.
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H: Slow build-up and discharge LED effect
I was trying to build a circuit that if switched on would slowly (in span of of 1~5s) light up around 20 LEDs - progressively, not all at once.
To achieve that i used one capacitor to initiate the "build up" effect (and discharge when switched off) and then used NPN transistor's emitter as a base input for next transistor, as shown on diagram below.
It works but with each consecutive "part" the light is dimmer and fades out completely after 3rd LED. Which leads me to suspect that power on base of transistor is getting weaker - but it shouldn't require much to let power through.
Transistors i have used are BC337-25.
Resistors vary, i was experimenting with different ones but R1 is 1.5k Ohm, R2 is 100k Ohm, resistors between emitters and LEDs are 220 Ohm, and one between emitters and bases are 1k Ohm
As for Voltages, both inputs are currently 3.3V, but final version will be charged off one 3.9V 18650 battery.
The question is: is it possible to achieve that gradually lighting up effect (similar to "percentage charged") with this design, and if yes what is the problem with my design?
Note that while I only have some understanding of a topic I did my research around the Internet was unable to find good enough resources that I could apply to my problem.
AI: An LM3914 will replace the transistors and resistors driving the LEDs. Each one has 10 output and two can be joined for 20 outputs.
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H: I have an outlet adapter that is clicking at 260bpm. What is happening?
I plugged this adapter, GE Grounded Adapter-Spaced Six-Outlet Tap, into my outlet the other day. I noticed a clicking noise in my apartment, and it's coming from the adaptor. I used an online app to measure its BPM. 260 BPM. But 260 isn't an even multiple of 60 or 120 (I live in the US).
Can anyone explain what might be happening?
AI: This is purely an adapter, i.e. there should be no components in there that go "click".
This points to the adapter sparking internally, or at the plug. That should not happen. Return the device. You link to a product page of the adapter that's only available through third-party seller on amazon, and these are known to sometimes ship counterfeits. I wouldn't know how to make an adapter cheaper by decreasing conductor distances, but maybe these were factory rejects? (Pretty sure that GE tests everything they put on the market for arcing)
The 260 bpm are probably a measurement error; 60 Hz is 3600 bpm, and that's probably much faster than that app expects, and thus, you get a bogus beat estimate. Try with something less music-centric instead, e.g. the Phyphox app, which comes with audio spectrum plots.
You commented later on:
@replete when nothing is plugged in, it still makes the noise...when I unplug it, the clicking speeds up, then stops
Um, what? This is really supposed to be a passive device; there should be nothing inside to produce clicking after completely disconnecting it (I assume you have nothing plugged into the in-, and power output side).
This invalidates my answer: there's something about this device that is more than just an adapter. (PLEASEPLEASEPLEASE don't be something obnoxious.)
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H: earthing conductor
I'm studying the subject Electrical Safety in Engineering and a special term really drew my attention. When I tried to google it, no any option was suggested but Protective conductors.
In the presentation slide, the definition of the term is explained in a such way.
**Earthing conductor: A protective conductor connecting the main
earthing terminal of an installation to an earth electrode or to other
means of earthing (e.g. TN systems);
Could anyone explain the exact meaning of the term Earthing conductor?
AI: In electronics, we call anything that is defined as the 0V reference as "ground" to be shared by a circuit, regardless of whether it is floating or "earth-bonded". This "earth" goes to the network and your home, to your outlets and the equipment which uses it.
However, this "Protective Conductor" term is used for the power grid network in many places and with different specifications how it is implemented.
The earth-connection generally serves 2 purposes, a drain for EMI and a safety wire for appliances, residential and grid power in case of faults or lightning.
Depending on the network, there are different ways to connecting "ground = 0V" of a system to an earth terminal.
TT system
TN-C
TN-S
IT System
Ref
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H: voltage output and flip flop output
Shown below is the circuit I would like to implement. (the circuit is from this paper).
Basically, it's a circuit designed to cut off voltage when electrochemical etching is done. The sudden drop in current flow is taken as the signal to stop the voltage bias.
I circled the two parts I would like to better understand.
Given the schematic of the circuit, I would like to know the voltage difference between 'WIRE' and 'RING' (circled in blue), assuming the state where Q1 and Q2 have zero Gate voltage and hence all the current is just flowing down to WIRE and RING.
There is a switch (circled in red) connected to CLR pin of the flip-flop. I looked at the datasheet of DM7474 flip-flop. I initially thought it was some manual switch that maintained the voltage between 'WIRE' and 'RING' but given the output of Q's dependence on CLR input, it doesn't seem so obvious. Neither high nor low of CLR fixes the output of Q.
-----added-------
Thank you for your suggestion.
After your explanation, I wrote down what voltage value the gate of Q3 would get as a function of resistance values of 'WIRE/RING' and potentiometer.
Since no current goes into Q3 gate, I \$= \frac{8V}{R_2 + x_w + x_p} \$.
So I guess I have to choose my potentiometer value such that the gate voltage of Q3 gets some voltage above the threshold when in the process of etching and gets zero when the etching is over (since when etching is done, the resistance value will shoot up).
-----added-------
I circled the potentiometer, capacitor, and another switch. I think I understand why the potentiometer is there. It is to introduce a potential value change to the input of the flip-flop.
I am not sure what role the capacitor and switch in parallel with the potentiometer serves.
AI: Q1's gate is fed from a flip-flop hence it's fairly clear that Q1 is used as an enable control for Q4. When Q1 is off Q4's gate is pulled to 12 volts via R1 and this means that at the source of Q4 is a voltage of around 8 volts to 10 volts.
I can't be more precise than this because Q4 is used as a source follower and the voltage it develops at the source is dependent on the gate threshold voltage of that MOSFET and the load current being taken through "wire" and "ring".
The voltage at "ring" is also current dependent because it is connected to ground via a 500 ohm potentiometer and this could be set to 500 ohms and drop 500 mV if 1 mA was flowing through "wire" and "ring".
So without knowing the current through "wire" and "ring" and the value if the potentiometer it's impossible to state what the voltage across them is.
Regarding the switch in red, if the circuit is currently driving current through "wire" and "ring" then closing the red switch will stop that current by turning off Q1 and this in turn simulates the current dropping as per what you say is the purpose of the circuit. On this basis, it seems to me like it functions as a "test" switch.
I think that this switch is part of the chip referred to as U24 and, as such U24 is probably an analogue switch controlled by another part of your circuit (unseen in your question).
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H: Adapating a single cell Li-ion battery voltage to 3.3V low power application
I'm planning to use a single cell Li-ion battery to power up a custom made circuit.
I'm planning on using a ESP-12E module board as the application will need to connect every once in a while to internet to gather data, acquire sensor data, before displaying them on an e-paper screen, and then fall in a deep-sleep for a given time.
So globally the application tends to be low-powered, with currents ranging from approximately 50µA to 500mA.
Knowing this, the problem is that I'm not sure how to design the power supply.
I first planned to use a LDO regulator, but my protection chip allows voltages down to 2.5V. So I was planning to allow the circuit to function with voltages down to 3V.
I looked toward Buck-Boost converters, and the LTC3440 chip seemed to fit my needs. However, the datasheet doesn't mention how it would behave in low load current situation (<1mA).
Consequently, my question is:
Should I review my application voltage range higher, meaning that it should consider voltages ranging from something like 3.5V to 4V+, or is the LTC3440 Buck-Boost converter would do a great job whatsoever and allow the application to work between 3V to 4V+ power?
AI: By far the best solution is to use an LDO with low quiescent current.
What is the quiescent current (aka Iq) of a regulator? This is the current consumed by the regulator when output current is zero. In general, if you look for a linear regulator with low Iq, it will have much lower Iq than a buck converter with low Iq (compared to other buck converters). During times when output current is very low, the LDO will actually consume less power than the buck or other DC-DC converter. This means that the system level battery life will likely be better with an LDO than with a buck converter.
But aren't LDO's inefficient? Well let's look at that. What is the efficiency of an LDO? Assuming the quiescent current is low, the efficiency can be simplified to Vout/Vin. The average Vin for a lithium ion battery is 3.7V. 3.3/3.7 = 89%. So a low Iq LDO can achieve 89% average efficiency. Even if you use a 3V LDO, the average efficiency is still 81%. It is doubtful that using a buck will be worthwile even if VCC is 3V. Also, the buck will cost more (this only matters if you are going into volume production).
But lithium ion (and lithium polymer) batteries can be discharged below 3.3V. Most of the time, this is just a red herring. In reality, a lithium ion battery at 3.4V is pretty much fully discharged. You can continue to discharge it to a lower voltage, but the battery life extension gained by that is really minimal.
So it is still probably going to be better and easier to just use an LDO. Make sure it can support 500mA max, and make sure its Iq is acceptably low (maybe around 10uA or less).
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H: How to use 8 IR receives that when one of them sense IR turn on a LED?
I want to use 8 IR sensors (4 on front of vest, 2 on back and 2 on headband like lazertag vest) that when each of sensors hit by IR, turn on a led. I don't want to use any microcontroller so a simple circuit is what I want.
I can achieve this by one IR receiver but I want to use 8 sensor. Help me please.
AI: Sorry, but your schematic can be considered only to be a concept drawing without any actual circuit details. As a drawing of an electronic circuit it's never going to work.
I bet you are not gaming in darkness. In daylight or under lamps there's plenty of other IR radiation which your circuit must be able to ignore. You need a recognizable modulation in the transmitted IR. Your receiver must be able to filter what IR radiation detectors (photodiodes or phototransistors) output, recognize the right code and trigger the action that is wanted. Detecting only the IR radiation strength needs full darkness.
I recommend you to search for IR remote contol receiving ICs such as TDA8160 by SGS-Thomson. It can have several IR photodiodes in parallel. It detects no special complex codes, only pulses which have high enough repetition frequency.
A little more sophisticated signal is used in IRM-2638T by Everlight. It needs pulses which have the right frequency. The sensor and pulse frequency detection circuit are integrated, so you need many of them for one person. But the outputs are easily combined.
If you search a little, you'll find more.
BTW. Your schematic shows that you need a competent partner for circuit details and tests.
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H: Axial capacitor terminal leads snapped!
Unfortunately, while in transport, my capacitor's terminal leads have snapped right to the bottom. What can I do? Can I solder something in their place, so it can work?
Many thanks.
AI: The lead was welded to the bottom of the aluminum can.
There's no easy good way to connect to that can without either a spot welder or perhaps conductive epoxy, neither of which would be all that great.
Ordinary solder won't work at all, and getting it hot enough to solder with special aluminum solder/flux would damage the capacitor/
I suggest trying to fit a radial cap in the space, if you can't find another axial one, they're quite cheap. That part also looks very old and electrolytic capacitors do not age well, they're often the first parts to "wear out".
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H: Maximum Vpp that doesn't change the output offset
I have a homework problem:
We have a non-inverting amplifier, \$G=+20V/V\$, which amplifies a perfect square wave, \$\overline{V_{IN}}=0.5V, \ V_{PP}=0.05V, \ f=50kHz\$. The output signal has offset equal to \$\overline{V_{OUT}}=10V\$. We also know that the smallest resistance value in this circuit is \$2k\Omega\$. What is the maximum \$V_{PP}\$ (peak peak input value) for this circuit, that will not change \$\overline{V_{OUT}}\$?
\$f_c=2MHz, \ f_{DP}=10HZ, \ SR=1V/\mu s, \ |V_{OUT(max)}|=13.5V\$
And, to be quite honest, I do not know what should I check and what will cause the change
EDIT:
The schematics:
And the smallest resistance will be \$R_r\$, i.e. the compensating resistor.
\$R_r=R_1 || R_2=2k\Omega \wedge R_2=19R_1\rightarrow R_1=2.11k\Omega, \ R_2=40k\Omega\$
AI: As long as the average input voltage does not change, an ideal amplifier will produce the same average output voltage. The average output voltage thus changes if the non-ideal nature of the actual amplifier kicks in, and does so in a way that affects the negative and the positive part of the square wave differently.
In your exercise, exceeding the slew rate or the gain-bandwidth product will deform the upper and the lower part of the square wave the same way and not affect the average. But if the amplifier clips the positive side of the wave at +13.5V, it still has enough headroom on the negative side, due to the large offset voltage.
I hope this answer is able to give you an idea where to start with the task.
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H: How to calculate voltage drop across multiple wire gauges?
This seems like a googleable question, but I simply cannot come across anything.
I'm working on a 12v system (aluminum boat), trying to supply power to a motor 12ft away from the circuit breaker. Through online sources, I was able to determine that at the 45amp max, 6awg wire could handle it, with a 5% voltage drop.
The confusion enters when I try to calculate the voltage drop with this 6awg wire, plus the potentially 8awg wire that runs 1.5 feet from the battery to the circuit breaker.
How does one correctly calculate the voltage drop over two different gauged pieces of wire?
AI: Each piece of wire is a resistor. Add up the resistance of all the wire that the current to the motor runs thru. Remember to consider both directions.
You find the resistance of each piece of wire by looking in a wire chart to get the resistance per unit length. Multiply that by the actual length of the wire segment to get the resistance of that segment.
Add up all the individual resistances of the individual wire segments. That's the total wire resistance in your installation. Multiply that by the current, and you have the voltage drop caused by the wire.
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H: Auto LED dimly lit when off
I bought an LED bulb, W5W, to replace the position lights, number plate lights and maybe the interior reading lamps. However they stay dimly lit when they're off.
I am thinking that the current is already flowing through the wires when the lights are off and the key is out.
So the circuit is closed, but with an incandescent lamp, not enough current exists to heat the coil, but with LEDs there is enough of it to light it.
Some people advise to put a resistor before the bulb, to fix this.
Will these LEDs drain the battery if they stay partially lit (I don't mind them staying like this)? If I add a resistor, won't that one drain the battery too?
AI: Cars often pass a little bit of current through "off" bulbs in order to determine if the (previously incandescent) bulb was working normally.
Depending on the replacement LED bulb circuitry, this can either cause intermittent flashing (when the LED driver circuitry builds up enough charge to light up), or constantly light an LED dimly (if it's a simple resistor in series with the LED). Yours sounds like the latter.
Olin is right with the suggested workaround - adding a bleed resistor in parallel with your LED bulb. The parallel resistor can provide an alternate path for the small "off" state current, meaning the voltage across the LEDs never gets high enough to cause them to light up.
simulate this circuit – Schematic created using CircuitLab
Please note that all values here are placeholders. You'll need to do some experimentation to find a bleed resistor value that works. 10k is probably a good starting point.
In "on" mode, the parallel resistor will just waste a tiny bit of power - it make the bulb visibly dimmer.
The replacement LED bulb will almost certainly be wasting less power than the original incandescent when "off". You could confirm that by checking the voltage across a working incandescent and your new LED bulb, and calculating the current through the bulb check resistor with V=I*R. Lower voltage across the bulb means higher voltage across the bulb check resistor, which means higher current wasted.
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H: I'm planning to put lots of phone chargers on one circuit, how to calculate this
This would be primarily for samsung S7 devices. Would like to be able to charge, say, 256 of them.
They will work in groups of 16, trying to design the power flow of this. Was imagining that each group of 16 would plug into a USB power strip of some kind, and then each group of 16 would link up to another power strip.
So, 16 groups of 16.
But I think that this will not work on a single 120V/15A power source. I would like to understand the math involved with how to scale this.
It will probably be more like 100 devices at a time, but trying to understand how to calculate this and know what the limits are.
AI: Each device would draw up to 10 Watts (assuming 2 amps at 5 volts). If you are using a quick charger, this will be higher.
256 devices at 10 Watts each will draw 2,560 Watts, plus a bit more for power supply inefficiencies, so say 3,000 Watts to get a round number.
A US 15 amp circuit a handle 1,440 Watts, though, to be safe, you should derate it to 80% or 1,152 Watts. A 20 amp circuit will handle 2,400 or 1,920 Watts at 80%.
Summary, you’ll need to split them up onto separate circuits, either 3 x 15 amp or 2 x 20 amp.
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H: Mains Filter for Power Line Comunication
I have two questions about Mains filters and their impedance effect on PLC.
1) With respect to signal propagation relative to the Line impedance:
As the signal is sent, via the power line, it will take the path of least resistance. Therefore the line to the PSU needs to have a high impedance (greater than 50 Ohm) to ensure the signal is not sent to the PSU. What is the Max impedance I can add to my filter before the PSU stops working?
There are two PSU's I am using. The 5 Watt PSU and the 10 Watt PSU.
simulate this circuit – Schematic created using CircuitLab
2) With respect to the prescribed circuitry in the 5 Watt and 10 Watt data sheets.
There are a fuse and an NTC used in series with one another. The fuse is required to prevent fires from starting. I would like to know if a PTC could replace the function of the fuse. If so would having a PTC in series with an NTC be contradicting in their functionality, or would they just need to be placed far enough apart so that their temp's do not interfere with one another?
For question one the PTC and NTC resulting impedance will be included in the overall impedance of the filter.
AI: The more optimal solution is to make an impedance from a parallel LC circuit so that at the transmission frequency the impedance is high. The parallel LC network would go in series with the line feeding the power supply. Choose the L so that at regular AC frequencies the impedance it presents is just a few ohms then it won't impede AC power voltages reaching the power supply.
You need to have the fuse if you are going to obey regulations for usage of this device - pretty much all SMPS devices have a fuse - it's the last line of defence against your house burning down. Install a fuse.
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H: What does this mosfet switch circuit do?
I found this piece of circuit in a battery powered sensor. It's a magnetic door sensor.
I am not able to figure out what does this do?
AI: It's battery reverse polarity protection like this circuit: -
When the battery is connected correctly, the PMOSFET turns on and acts like a low ohmic path for current to the load. If the battery is reversed, the gate is higher than the source in voltage and the PMOSFET does not turn on thus, it "protects" the load.
The gate resistor is optional and is not needed for batteries of lower voltage than typically 10 to 15 volts but if the battery were 15 volts or more, the resistor AND an added zener diode would protect the gate-source region getting too much voltage and breaking down: -
It's probably a good idea to have a resistor anyway because it does offer some ESD protection to the gate (that would otherwise be directly connected to a battery terminal and could be vulnerable).
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H: Amplification of sinusoidal signal from filter circuit
Intention of the project is to obtain sinusoidal signal generator of frequency range 10Hz to 100Hz and 5v signal from microcontroller i.e arduino uno,
using pwm from arduino uno I got the square waves of 4.3v - 5v, the signal was fed into the RC low pass filter of four stages and cut-off frequency of 50Hz, the output after simulation was found to be a sinusoidal signal of 50Hz but with low volts of about 400mv, I tried to amplify the signal using OPamp amplifier with LM324 IC but the output was found to decrease to almost zero volts, But after swapping between filter and amplifier, now the I'm amplifying the square wave before filtering the signal voltage raised to almost 900mv. Intention is obtain sinusoidal signal with 5v and frequency between 10Hz and 100Hz. Please any best way to accomplish this.
AI: edit
When using a very high Q, Wein bridge or Barkhausen unity gain positive feedback oscillator, the time to grow oscillations depends on the excess gain and the initial condition. I supposed Proteus may not have the necessary initial condition to "kickstart" oscillation.
This is normally done by natural noise or DC offset. But here is a trick that can guarantee instant oscillation with the initial condition of a DC step voltage to start oscillation. Assuming the initial condition of 0 voltage across each capacitor, arrange to ensure the desired startup output voltage. This is similar to a logic power-on reset cap. ( see the simulation link in my last comment, as shown below.)
Power on kick-start to Osc. depends on the placement of Cap to Vin+ guaranteed by design. otherwise, noise or offset voltage has to grow slowly from excess over-unity gain with "Barkhausen criteria".
1) Learn the fundamentals of learning
learn how to find a good answer before making too many errors.
learn how to find the right keywords
use good keywords such as "low-frequency sine oscillator schematic"
choose multiple search engines; including this site and even specific users "user:joeblow sine Hz oscillator" but spelling must be correct
in Google, you can also "exclude" words with "-minus"
oscillator sin -vibrator ,
also select "images" results in google with "schematic"
2) Learn the fundamentals of electronics before making too many misteaks
never cascade RC filters of the same value. Why? the impedance of each stage loads the previous stage and results in a weaker knee at the breakpoint when you want a sharper higher order filter.
capacitors can become inductors in active filters by impedance inversion from negative feedback, to make better active high order filters
there are lots of really good active filters, so don't try to reinvent a better wheel until you study how wheels are made
instead of a square wave and fixed filter, try searching for a "low-frequency oscillator using the fundamentals of learning above".
on schematics, be more logical and do not run inputs and outputs in big loops, off the page, either use labels or Ref.Designators or learn how to draw neat block diagrams, besides big loops on signals, in reality, can cause big problems.
Duplicate answers:
If you just learning, changes are pretty high there are duplicate answers so learn 1) then 2)
Is this a suitable sine wave osc? how would I control the frequency?
What's the easiest/cheapest variable-frequency sine wave oscillator?
you don't need an Arduino to make a good low freq. sine generator
1Hz Sine wave oscillator - Multisim
Here's my simple 50Hz sine (split supply)
[ or +5V only but Rail to Rail output type]
using LED's to soft limit the gain to x1
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H: Regarding Power Market demand and supply
As I have read, that power supply should be equal to demand. As it can't be stored .So basically this means power is generated in real time.
Consider an area where power comes from a Substation A, which receives power generated from power plant B.Of this area suppose each device is currently switched off till now power plant B should not generate anything.
Now I switched on appliances, then at the same time power should be generated by powerplant and transmitted also in real time. So how they Know when to generate? Or correct me If I am wrong somewhere. This might seem silly but I am bit confused.
AI: In order to meet changes in demand, the generation authority always has more generators running at any time than is needed to meet the present consumption.
Assume we just have rotating generators. The instant a load is switched onto the grid, the current that flows creates a braking torque in the generators, and they start to slow down. The instantaneous energy needed to power our load comes from the kinetic rotational energy stored in the generators.
As the generators start to slow down, the speed regulators kick in, and increase the mechanical power to the generators to maintain their speed.
The generation authority would notice that supply A was starting to get close to its maximum, so would start up supply B, just in case there was a further increase in demand. If that increase happened before B was up to speed and connected to the grid, then you would have at best a voltage sag (brownout) as A failed to cope, and at worst a power cut.
If a further increase did not happen, then B has been started, not supplied any power, and been a net cost. The margin between the maximum capacity of all the running generators, and the present consumption, is known as the 'spinning reserve'.
This is why forecasting is a very important part of running an electrical supply. You need to be able to guess from the weather, and from the TV schedules, when, and how big, the load demand spikes will be, to have enough, but no more, extra capacity already running to cope. Too much spinning reserve will reduce the profits. With too little spinning reserve, an unexpected demand spike could leave you having to explain an embarrassing and unnecessary power cut.
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H: How to boost 12V DC to 24V DC?
I am trying to power an ultrasonic mist module, which works at 24V and requires a few milliAmps. I have a 12V DC power supply, how can I use it to power my ultrasonic module?
I searched on the internet and there are multiple(rather complex for a beginner) ways given to do so, is there a simple way a beginner can get his way around it?
AI: The two basic methods are to use a crude voltage doubler, or a fairly simple boost switching regulator. If you cannot build one from scratch parts, a pre made module can be purchased on good electronic sourcing sites like Digikey, Farnell, etc, or less quality sites like eBay Amazon etc.
Or buy a 24V supply. A cheap wallwart can be found on the same sites, or a thrift shop.
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H: Can I replace these many capacitors with just one?
I'm designing a schematic for an addressable RGB LEDs array and I've chosen the WS2812B because of how common and cheap they are. Looking at the typical application circuit, I noticed there is a capacitor for each LED.
Can the multiple capacitors be replaced with just one single capacitor? What would the capacitance need to be for that single cap?
I'm thinking of placing 50 LEDs per array and it would be very nice if I didn't need to place 50 capacitors too.
AI: The goal of each capacitor here is to smooth out the power supply of each WS2812B. When you power an array of LEDs, there is a good chance that a transient voltage drop will occur and create a flickering effect on your LED strip and most likely on other LEDs that are currently on. If you were directly powering a LED from the power supply, you wouldn't need a bypass cap. However, The WS2812B is a LED coupled with a integrated circuit. The IC is far more sensitive to voltage variation on the supply. The flickering will be caused by the IC going haywire. As it was pointed out on the comment, you would need a far bigger variation on a power supply to see actual flickering when directly powered.
By assigning one cap per circuit, you reduce the amount of calculation required to compensate. You don't need to take into account as much information. Also, you can place the cap really close to where it is actually needed. What is important here is the close proximity of the caps to minimize trace inductance.
You can also take a look at this question for further details.
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H: Loop Gain and Phase Margin Correlation
I have found a definition of phase margin of amplifier system from Texas Instruments application report. This definition looks like this:
$$\phi = tan^{-1} (A \beta)$$
where \$ A\$ is amplifiers open-loop gain (aka direct gain) and \$ \beta \$ is feedback return signal ratio - or \$ A \beta \$ known as loop gain. Now, \$ A\beta \$ would typically be a value ranging \$ 1000000 \$ to \$ 10000 \$ (in opamp amplifier systems, where open-loop gain is usually around \$ 120 dB \$).
Such values of \$ A\beta \$ inserted into upper definition of phase margin always equals (approximately) \$ \phi = 90° \$. So, using that equation for definition of phase margin must be definitely wrong, because it is not possible, for amplifier's phase margin to be \$ 90° \$ in all scenarios possible. Unless we would be discussing an example with \$ A\beta < 100 \$, which is very unlikely to happen.
Also, it would seem more logical if phase margin definition equation would
be described as a function, dependent on poles of amplifier or \$s\$, damping factor or \$\zeta\$, frequency or \$\omega\$, etc.
I know how to find phase margin (and gain margin) from already drawn Bode plot, but I cannot solve it, using mathematical ways, not graphical.
Can anyone tell me, if this is the actual formula for calculation of phase margin? Or are there more data needed to solve such case? Would "fully defined" transfer function provide enough data for proper calculation of phase margin?
AI: Now, Aβ would typically be a value ranging 1000000 to 10000 (in opamp
amplifier systems, where open-loop gain is usually around 120dB).
That's at DC where nobody really worries about phase margin because it's never going to be an issue. Look at a typical open-loop response of an op-amp: -
Picture source and other relevant information that could be useful.
At 1 kHz the open loop response might have dropped to 60 dB (G = 1000). At 1 MHz, the o/l gain is only 10 and this is an area where quite a few op-amp circuits have problems. Arctan of 10 (assuming a unity gain situation) is 84 degrees and consistent with the graph above. At 10 MHz the gain is unity and arctan of 1 is 45 degrees i.e. not a million miles off.
If you know the T.F. of the forward gain device and you know the feedback T.F. then certainly you can calculate phase margin by considering the loop broken with a signal being injected at the input and the output being taken from where the break is. But you have to respect impedances and loading when you open the loop and sometimes it can be difficult to realize.
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H: Potentiometer/attenuator between amp and speaker
I have a setup where an amplifier with 2 channels drives four 8 ohms 80 watts speakers on each channel. The amplifier has a single volume knob which controls volume of both channels at once. What I would like to do is add a volume control for both channels separately between amplifier and speaker. This as I understand is not the right way because the potentiometer required will have to handle 80 watts of power, and thats why a volume knob is used at the input of amplifier instead of output. Unfortunately i have to use the setup i described. I have looked into T-pad and L-pad attenuaters/resistor divider.
I would like to know whether I can get some good ones in Europe? I am presently living in Austria, and I really cannot find anyone who deals with it in Europe. Also does anyone have experience/suggestions with controlling volumes of 2 channels separately?
AI: There are a couple of ways of doing what you want.
The most obvious method is to use a commercially-available "L-Pad". I've seen these available with power ratings up to about 100 Watts. The higher-power versions can be expensive.
Note that the internal wire-wound resistor elements have an appropriate audio taper. The larger versions have resistance elements that change wire size as the resistance gets lower and the power being handled gets higher.
Another method is to use a tapped transformer. These are available for both 70V and 25V distributed loudspeaker systems.
What is not commonly known about these transformers is that although they are intended for use in a constant-voltage loudspeaker distribution system, they can be used directly between a low-impedance amplifier and a low-impedance speaker. It is simply a matter of choosing the right transformer.
Look for a tapped transformer that will work with both 70V and 25V systems with a power rating of at least 100W. Depending upon how low you want the frequency response to go, they can be relatively inexpensive. The least expensive versions of these only go down to about 200Hz and are intended for ceiling speakers. The better ones go much lower and are used in large venues such as sporting facilities (with much better speakers).
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H: what is the function of the trigger coupling in an oscilloscope?
Could someone please explain to me what's the functionality of the trigger coupling in an oscilloscope (the difference between ac trigger coupling and the dc trigger coupling) ?
Thank you .
AI: Let's say you have a scope with an "intrinsic" sensitivity of 10 volts full scale. That is, with no amplification it shows a range of 0 to 10 volts. Consider a 0.1 volt AC signal riding on a 100 volt baseline. How would you display it? Using DC coupling, by scaling down to 10 volts (DC) you could show it, but the AC component would be reduced by a factor of 10 as well. This would have you trying to see a .01 volt signal on a 10 volt signal, or approximately 0.1% of the screen. You would find that very difficult to see. Instead, if you use AC coupling, you can then eliminate the DC, then add a gain of 100 to the result, and see the 0.1 volts occupying the entire vertical range of the screen.
Now let's think about triggering. With the triggering run from the same input signal as the display, it is reasonable to think of the triggering circuit as being in essentially the same position as the display. So it should come as no surprise that the trigger will have a hard time reliably picking up a 10 mV level riding on 10 volts. Instead, by using AC coupling and gain, the trigger level can be precisely adjusted to give a stable display.
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H: What should I do to unused input parts/features (analog and digital input pins, and power pins) of a video scaler chip?
I am working on a video scaler chip which has multiple inputs (i.e HDMI, DP, VGA) but I only want to use the VGA input. (Choosing another chip with only one input is not an option).
The friendly datasheet did not mention any instruction on what to do with unused pins, so I tried searching the internet and the forums, below are the items I got. (If I got them right)
Digital pins - tie to Vdd/Gnd with pull-up or pulldown
Analog pins - tie to DC potential
And based on my search, the configuration (where to pull) for the lowest power consumption will vary per IC.
I was about to just pull down the DP and HDMI receiver pins (analog) to mimic a DP/HDMI port that is not connected to any source (standby). But then I realized there are these receiver VDD and VSS pins that I do not know what to do. DP, HDMI (as well as VGA) each have their own VDD and VSS pins (e.g. DP_VSS, DP_VDD). The datasheet mentions in the pin list tables that XX_VSS* 'must' be connected to ground, XX_VDD 'must' be bypassed with cap to ground. (XX - DP/HDMI/VGA) I assumed the 'must' is mentioned in the datasheet so that the DP or HDMI receiver would work. (But I will not use them)
I was thinking, since they apparently have independent VDD and VSS for each receiver type (DP,HDMI,VGA), each receiver pin type is powered by independent XX_VSS and XX_VDD. So, If I leave the power pins of an unused feature floating, no power will be given to receiver pins of that feature, and that feature will be totally shutoff, hence, I might not need to pullup/pulldown the pins. Note though that the chip itself has its core and ring VDD and VSS.
If I will not use DP and/or HDMI, is it safe to leave their power pins floating? And if I would leave their power pins floating, is it safe to leave the analog receiver pins floating as well?
Or should I connect the power pins and then pulldown(or up) the analog input pins?
Which configuration would have the lowest power consumption (in general)?
I tried contacting the website for this chip, but they can't give technical support anymore because this is already a legacy chip. I am working on an STDP60XX.
(P.S. I am new to the stackexchange, if I've missed some rules, please let me know and I'll edit my question immediately. Thanks)
AI: Regarding the power pins, you almost certainly need to connect them the same way that you would if you were actively using those interfaces on the IC. In devices that have multiple sets of power pins that are called out as being specifically for different parts of the device, they are quite often still connected to other pins on the device internally--they are called out as being for a specific part because they are most closely connected to that part of the die and will thus supply the bulk of the current to that area.
The exception to this is when different parts of the IC are designed to run at different voltages at the same time, or when the IC supports certain power supplies being shut down while other parts of the device are still active. The former is common in fast mixed-signal devices (like Ethernet switches/PHYs) and high performance processors or FPGAs. In these cases, any power pins that are always expected to be at the same voltage may still be connected internally.
In your case, if the DP_VDD (for example) pins are internally connected to the VGA_VDD pins, then leaving the DP_VDD pins unconnected means that the DP interface will still be active and will be drawing current through the VGA_VDD pins. In the best case, the DisplayPort electronics will be inactive and won't draw enough current to matter. In the worse case, the DisplayPort electronics will still be active and can draw enough current through the other pins to disrupt operation in other parts of the IC. In extreme cases, the DisplayPort electronics will draw enough current that you could wind up exceeding the absolute maximum input current per pin on the VGA_VDD pins, or enough current flows across the die that the IC is damaged internally.
Devices that do have internally separate power networks and are designed to operate with one or more of those networks unpowered have to take special precautions wherever signals cross from one power domain to another to avoid problems, so even if the DP_VDD pins on your device are not internally connected to the VGA_VDD pins, this is no guarantee that the device will function properly with the DP_VDD pins unpowered.
So as a general rule, unless the datasheet explicitly states that you can leave those power pins unconnected in your application, you should power them as you would if you were using that interface. In any case, generally, you should ALWAYS connect the ground pins.
The signal pins are a little trickier. If the chip requires pullups/downs to operate properly when the DisplayPort cable is disconnected, then you should probably use the same pullup/down configuration in your application. If it does not require pullups/downs normally, then you probably don't need them either.
If the IC supports configuration via pin strapping or via a digital interface that allows you to completely shut down the unused interfaces, then it's more likely that you'll be able to leave off pullups/downs that would otherwise be required on those interfaces.
If in doubt, it's always a good idea to place the footprints for pullups/downs so that you can make adjustments in testing. In production, you can then simply fit or not fit whatever parts you find you need or don't need. Empty PCB footprints are essentially free.
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H: Understanding atomic writes to GPIO on different ARM Cortex-M's
This video succinctly describes why the read/modify/store has potential problems when it comes to interrupts. Very clear and understandable.
He uses the TI Stelarris Cortex-M4 as a teaching board and in the minute I linked above describes how that board was designed such that one can write to each GPIO bit or a group of bits as it were a single address using 256 different 32-bit registers.
I am following along with a blue-pill STM32F103C8T6 board and page 150 of the reference manual says:
Note: For atomic bit set/reset, the ODR bits can be individually set
and cleared by writing to the GPIOx_BSRR register (x = A .. G).
Dave Welche's code does exactly this. It works exactly as expected and blinks the onboard LED.
My question then: Is there a way to do atomic writes to the blue-pill board in the way that's described in the video? Or is that each manufacturer handles this type of thing differently and in the case of the blue-pill ST has decided to use a single register to handle this?
AI: GPIO design is nominally unique to each ARM licensee, and potentially can differ between a vendor's different sub-families.
However, most ARM MCUs are setup to put the GPIO in the bit-banding region, which aliases each individual bit to its own distinct address - a feature provided by the ARM design, rather than the vendor.
The Stellaris parts in question however have a novel capability that appears to be an aspect of their GPIO design, rather than an ARM bit-banding:
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 662) by using bits [9:2] of the address bus as a mask.
In this manner, software drivers can modify individual GPIO pins in a single instruction without
affecting the state of the other pins. This method is more efficient than the conventional method of
performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this
feature, the GPIODATA register covers 256 locations in the memory map.
The implication here is that you can mask off any combination of 8 bits in one of this chips relatively large number of relatively small 8-bit ports.
In contrast, the STM32 BSRR/BRR is another vendor-unique scheme. Note that because the BSRR register has distinct bits for each of set and reset, it is also possible to do a masked operation on an arbitrary combination of bits of a wider 16-bit GPIO register here. However, the data would have to be pre-processed to split the sets from the resets (vs. the TI solution which is a masked binary write) and reading would appear to require post-masking by software.
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H: What do we mean by "gate plateau voltage"?
While reading some semiconductors datasheets, I've found something called "gate plateau".
What do we mean by this term ?
Reference:
AND8029 application note page 2, from ON Semiconductor written by Christoph Basso.
AI: It's called a plateau because it's relatively flat, compared to the steep line before and after it.
It's caused by the Miller effect of the drain-gate capacitance holding the gate voltage relatively constant, despite charge being supplied to the gate by the gate driver.
In the first steeply rising below gate threshold region, the gate current is only charging the small inter-electrode capacitances.
At gate threshold, the Miller effect multiplies the DG capacitance by several orders of magnitude, reducing the rate of rise.
Once above the gate threshhold, the capacitance reverts to the inter-electrode capacitances, and the voltage rises steeply again.
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H: Defining a circular cutout in a pad in Altium
I'm creating the footprint for a Wurth inductor, 744043100. The recommended land pattern is below.
They use a radius 1.8 mm circle in the middle of the component to define a void in the pad. I'm trying to create the same shape in Altium, but am running into some trouble with it. In the screenshot below, I've tried two methods.
Pad 2 uses a region with six vertices and an arc to define the curved region, which works but seems prone to some round-off errors. It's not a big deal, but I can measure my radius to be ~1.76 mm at y = 0 mm. It also requires some math to find the vertices and arc angle, and no one likes that.
Pad 1 shows what I'd like to be able to do. My preference here would be to define a rectangular fill, define a circle of radius 1.8 mm, and use the circle as a cutout to modify the fill. Is it possible to do this from within the PCB library editor? Is there another way to define this shape that I've missed?
I'm using Altium 18.1.7.
AI: I would do this by defining the outline and then creating a solid region from the outline. Eg. Snap grid set to 0.025mm. Set at 0,0 for center so that the center arc can be used to snap to the ends of the lines (do them first). Takes just a few seconds to draw this.
Then Tools->Convert->Create Region from Selected Primitives
And then add a pad to the region etc.
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H: What is this three pin, cyclindrical component?
I'm curious as to what the component is on this PCB. It is surrounded by a polyfuse / zener arrangement (for overvolt / fusing) - I believe it is something to do with the AC input but am not completely sure. It appears to be polarized.
What is it and what might it be used for?
AI: It's an unshielded inductor of some sort, wound on a ferrite spool and covered with heat shrink tubing.
It may be a simple inductor, perhaps with the middle lead used to stabilize it mechanically or it may be a tapped inductor.
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H: KiCAD 5 --- what is the significance of the various GND symbols?
I'm new to KiCAD. I see symbols for GND, GNDA (analog), GNDD (digital), GNDPWR, GNDREF, etc.
Is there any significance aside from "schematic documentation"?
I was expecting that maybe the reason for the multiple symbols is that the PCB layout tool can use those to somehow enforce separation of ground planes? But it instead seems buggy in the sense that not only the ratsnets connect GNDDs and GNDAs together: in the PCB, it actually renames all the GNDD pads to GNDA !!!
Am I missing something, or doing something wrong?
AI: There are a couple question here, so I'll start with the various grounds.
Kinds of Ground
Standard ground symbol. If you don't have a specific use for the other symbols, then just use this one. More often than not, separating grounds will lead to trouble, so if you don't know that you need to do it, then avoid it altogether.
This is your "analog" ground. Typically used for referencing the analog inputs in an analog to digital (A/D) converter. Note that while the symbol is the same as the plain GND, the label name is different and thus they will not connect by default.
This is your "digital" ground. This is the other side of the A/D converter. It provides the reference for your digital outputs.
This is a "power" ground or chassis ground. This symbol is used in circuits to represent the local reference potential. Usually, the ground of the metal case that holds your circuit. It can indicate that there is a substantial potential difference between this ground and the earth ground or structure in which the chassis is mounted. Note that IEC and ANSI both use 3 prongs in their symbol but KiCad uses 5.
Earth ground. Also known as reference ground or "real" ground. This usually represents the 0 voltage of your building. If you use this symbol in your schematic, you are saying that the point is meant to connect directly to some physical piece of metal in your room that is connected to the actual dirt. In a standard 220V AC power cord, this would be your third (green) wire. N.B. This does not mean that this voltage is clean or steady or any other variation of perfect. It only indicates that there is no circuitry between it and the dirt outside.
This symbol (IEC 60417 #5018) represents a "clean" ground. In this sense, it means a specially-designated ground that is protected from noise sources to ensure correct operation of sensitive equipment.
This symbol (IEC 60417 #5019) represents a terminal that is designated for protection against external shock in case of a system malfunction. Note that the symbol name is "protective" and not "protected". That is to say, things connecting here are meant to protect you and not the items connected to this terminal.
Grounds in KiCad
To examine grounds in KiCad, let's open the standard GND symbol in the Symbol Library Editor.
There are a few things to note here. First, all of the grey text are marked "Invisible" in the schematic, so you will not see them by default when you place the symbol.
The #PWR? is the symbol reference. By prefixing it with #, the symbol is not added to your Bill of Materials. The ? is not part of the reference string (you will not see it when editing the reference). It is a placeholder to denote the unique number that will be assigned during schematic annotation depending on the other #PWR symbols in your schematic.
The pin on the symbol is pin number 1 and is labeled GND. Because it is an invisible power input pin, KiCad will create a global label for it. The global label will be named GND as that is the name of the pin.
In the case of GNDA, the invisible power input pin is labeled GNDA. and creates a new global label with that name. These do not connect between grounds. So, you can have GNDD and GNDA in your circuit and they will be seen by KiCad as distinct nets.
Connecting Grounds
If you use multiple grounds, it is usually (read: always!) necessary to connect them together at some point. If you plan on disconnecting the grounds at some point, you might use a 0-ohm resistor or inductor to connect them. However, most applications will want to simply isolate the current loops in a section of the board and then want a single, common connection point that is printed on the circuit.
In KiCad, these are called "Net Ties". You can find them in the common v5 libraries under "Device". They look like this:
And the standard footprint looks like this:
Note that you can adjust this footprint to your liking. The "magic" of a net ties is that there needs to be a polygon on the F.Cu layer that overlaps the two SMD pads. This allows you to connect to distinct nets, e.g. GNDA and GNDD at a specific point in your circuit while still maintaining separate nets and ground planes.
Connecting Nets
If you connect the two ground nets together with just a wire like this:
Then, KiCad will recognize this as a single net with two labels (GNDA and GNDD). In your netlist and by extension pcbnew, KiCad will choose GNDA for the single net label because it is alphabetically first.
If you want to keep the two nets distinct in your layout and only connect them with a net tie, then you need to set up the connection in your schematic to look like this:
Placing the net tie between the two nets tells KiCad that you want two nets with a single connection between them.
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H: multiple RGB LEDs with common resistors for each color
I am modifying a pcb with 9 RGB LEDs having three resistors each normally. I know that it is the proper way of doing it. However what is the disadvantage of connecting them as below?
Resistors being higher power rated compared to three resistor each setup.
AI: It won't work well, or not at all.
If a single resistor goes to multiple LED's of the same color, then current will be split, so that as each additional LED turns on, that group becomes dimmer.
If a single resistor goes to LED's of different colors, not all will light, since they have different minimum required voltages. For example, if a red LED turns on at ~1.5 V, then it will sink all current before a blue LED needing ~3.2 V, even begins to glow.
Resit the temptation -- it's not too bright an idea.
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H: Bench Supply Amps - 4AA Batteries
I have a battery powered device that runs from 4 AA batteries. Whilst testing, I am wanting to power it from an adjustable bench power supply.
How can I work out what amperage to set my bench supply at? Do AA batteries have a standard amp rating? There is nothing mentioned on the battery itself.
AI: I found this note on size AA batteries at this website blog. It is a large blog that clears the air about amps vs. amp/hour ratings. Based on this blog I would limit current to 500 mA. Though a Alkaline battery might be rated for 2000 to 3000 mAh, that could be a overload value and not the nominal current drain expected by the battery manufacture.
Speaking in general terms, you could expect the battery to run for about 10 hours at 10% of its mAh rating, but not all battery types follow such a drain curve, and not all loads react to a low battery the same way. Please read the blog.
Pololu Blog » Engage Your Brain » Understanding battery capacity: Ah
is not A Posted by Jan on 12 November 2010
AA batteries. A typical alkaline or NiMH battery in the standard “AA”
size has about 2000 to 3000 mAh (or 2 to 3 Ah). With a cell voltage of
1.2 V to 1.5V, this corresponds to 2 to 4 Wh per cell.
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H: Bit order of ADV7125 ADC
Datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/ADV7125.pdf
Assuming R0, G0 and B0 are the least significant bits of each channel, but cannot find it specified anywhere in the datasheet explicitly.
Is there a convention for this that the higher the bit number, the higher its significance?
AI: "R0, G0, and B0 are the least significant data bits."
Found this on page 10, table 7.
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H: What is the meaning of the "lasso loop" on circuit diagram?
I've never seen this "loop" structure in a circuit diagram before.
Pin 6 has a line that loops around the lines from pins 5 and 9.
Pin 7 has a line that loops around all other lines, except the ?resistor? between pins 1 and 6.
NOTE: This pinout diagram is for the db9 connector on a Nellcor Pulse Oximeter
AI: The loops represent a shield around cable that then connects to the connector pin indicated by the line from the loop.
In your example there is a two wire pair that is shielded and then that is contained with some other wires and an overall outer shield.
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H: First Order Filter - Voltage Follower Attenuation
I have a first order filter. It is supposed to have unity gain at frequencies below the 3dB frequency of 50Hz. I have simulated two of these first order RC filters. One where the signal is fed into a universal op-amp acting as a voltage follower and another as a simple RC network. I have attached images of both the schematic and the response.
When conducting an AC sweep of the circuit the signal given into the op-amp voltage follower there is a constant -2dB attenuation. Universal opamp 2 has been chosen from the LTSpice component list. For the RC network not fed into a voltage follower there is 0dB gain below the cut off frequency which is what is desired.
Why is there -2dB gain for the voltage follower and how can this be corrected?
AI: Very simple answer. Your op amp is meant to receive signals 0V to 5V but AC signals can go to negative, example +1V to -1V.
What you need is capacitor in series and bias to 2.5V, so your signals would be between 1.5V to 3.5V. Which allows the op amp to work properly.
You may download this pdf for reference: http://www.analog.com/en/analog-dialogue/articles/avoiding-op-amp-instability-problems.html
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H: What is the miminum voltage for series NiMH pack?
Suppose a pack of 8 AA NiMH cells are serially attached and its known NiMH cells should not go below 900mV per cell.
Does this really mean the pack should not be discharged past 7.2v?
AI: Your sums are right, 900 mV * 8 = 7.2v.
However, what happens if the pack is unbalanced, has 7 cells at 1.0 v, and one cell at 200 mV? That measures 7.2 V at the pack terminals as well.
The cells may not start out this unbalanced, and of course they get charge balanced on each full charge. However, as they wear out, they may wear at different rates, and their capacities may drift apart a little.
Although the 200 mV cell is completely exhausted, it's likely not yet permanently damaged. That will happen if you use the pack for just a moment longer, and the cell goes down through 0 V, and keeps on going, getting 'charged' in reverse by the other cells. Note that's applicable to nickel chemistries only, lead and lithium have different damage voltages. Once you've reverse biassed a cell, the battery pack becomes more or less unusable.
When you're using a battery of series cells, without access to the internal cell voltages for monitoring, you need to have some extra cushion voltage to allow for cell mismatch. The endpoint voltage you choose will result in a tradeoff. A higher endpoint results in less usable capacity per cycle, but more expected cycles lifetime before you damage the pack through this mechanism.
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H: Schematic indicator interpretation
I was attempting to get familiar with the Texas Instruments CDCE62002.
While checking the datasheet of the evaluation module, I came across the following indicator in the schematic. I'm curious about the dashed line which is visible. For a full view of the schematic please check page 11 of the EVM datasheet
Reasons I could think of why they did this:
I am overthinking a random scribbly line
They want these ground points to be as close together as possible? (if this is the case, why would you place such information inside a schematic instead of a pcb layout/guidelines section)
TL;DR: Why is there a dashed line connecting grounds in this schematic?
AI: It is most likely that the cap should be grounded close to pin 21.
The layouter will look at the schematic while doing the layout, so its a big help if all relevant information is in the schematic.
There are various ways to indicate if a capacitor should be placed close to a specific pin on an IC.
There could be a note next to the cap, the end of the cap could be connected between pin 21 and the GND symbol, or a dotted line like your example.
It depends on the style of the engineer drawing the schematic.
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H: Negative Edge Trigger and Asynchronous Clear not working in ModelSim
I have created a 4 bit counter with the following inputs and outputs
clockN: active low clock
clearN: active low clear
cP: When high, the counter counts. When low, the counter stays the same.
eP: Active high. This activates the tri-state buffer at the outputs
When I simulate this, and assert the clearN (N meaning active low) at t=0, it does not actually clear until the next positive clock edge. I do not understand why. Also, each time qOut counts up by one, it does it on the positive clock edge even though my code is telling it to do it on the negative clock edge. My code, testbench, and modelsim output are shown below.
Here is the counter code
--Program Counter for SAP-1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; --This is required when doing additions to STD_LOGIC_VECTORs
ENTITY PROG_COUNT_SAP_1 IS
GENERIC(size: INTEGER:= 3); --This is the size of the register
PORT(
clockN, clearN, cP, eP: IN STD_LOGIC;
qOut: OUT STD_LOGIC_VECTOR(size DOWNTO 0));
END PROG_COUNT_SAP_1;
ARCHITECTURE Behavioral OF PROG_COUNT_SAP_1 IS
SIGNAL valueBeforeTriBuffer: STD_LOGIC_VECTOR(size DOWNTO 0);
BEGIN
PROCESS(clockN, clearN, cP, eP)
BEGIN
IF(clearN = '0') THEN
valueBeforeTriBuffer<=(OTHERS=>'0');
ELSIF (falling_edge(clockN)) THEN
IF (cP = '1') THEN
valueBeforeTriBuffer<= valueBeforeTriBuffer + 1;
END IF;
END IF;
IF (eP = '1') THEN
qOut<= valueBeforeTriBuffer;
ELSE
qOut<=(OTHERS=>'Z');
END IF;
END PROCESS;
END Behavioral;
Here is the testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TB_PROG_COUNT_SAP_1 is
end TB_PROG_COUNT_SAP_1;
architecture test of TB_PROG_COUNT_SAP_1 is
--create time constant
constant CLOCK_PERIOD: time:=2 us;
--create constants for all generics.
constant size: INTEGER:=3;
--create signals for every port
signal clockN: std_logic;
signal clearN: std_logic;
signal cP: std_logic;
signal eP: std_logic;
signal qOut: std_logic_vector(size DOWNTO 0);
begin
dut: entity work.PROG_COUNT_SAP_1
generic map(size=>size)
port map(clockN=>clockN,
clearN=>clearN,
cP=>cP,
eP=>eP,
qOut=>qOut);
--simulate the clock
clockNSimulation: process
BEGIN
FOR count IN 1 TO 16 LOOP
clockN<= '0';
wait for CLOCK_PERIOD/2;
clockN<='1';
wait for CLOCK_PERIOD/2;
END LOOP;
END PROCESS clockNSimulation;
--simulate the clearN
clearNSimulation: process
BEGIN
clearN<='0';
wait for 3 us;
clearN<='1';
wait for 7 us;
clearN<='0';
wait for 2 us;
clearN<='1';
wait;
END PROCESS clearNSimulation;
--simulate the cP
cPSimulation: process
BEGIN
cP<='1';
wait;
END PROCESS cPSimulation;
ePSimulation: process
BEGIN
eP<='1';
wait;
END PROCESS ePSimulation;
end architecture test;
Here is the output waveform from modelsim:
AI: As mentioned by user8352 in the comments: your problem is that you need to induce an extra delta cycle when you have updated valuebeforetribuffer (pro-tip: VHDL is case-insensitive). The quick and dirty solution is to add valuebeforetribuffer to your sensitivity list. At that point you're gravitating towards a bigger and bigger mess of a code, though.
Cleaner is:
p_main: process(clk, clear_n, enable_out)
variable r_value_before_tri_buffer : unsigned(size-1 downto 0);
begin
if clear_n = '0' then
r_value_before_tri_buffer := (others=>'0');
elsif falling_edge(clk) then
if c_p = '1' then
r_value_before_tri_buffer := r_value_before_tri_buffer +1;
end if;
end if;
if enable_out then
q_out <= std_logic_vector(r_value_before_tri_buffer);
else
q_out <= (others=>'Z');
end if;
end process;
Other remarks:
I use numeric_std instead of the mess that is std_logic_unsigned
size downto 0 declares a vector of size+1
no need to have c_p in your sensitivity list if you only use it at clock flanks, also cuts down on your simulation time
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H: How to program SoC chips like CC2541F128RHAT
I am working on a BLE project. As per initial research, decided to use the cc2541 chip as BLE module. I have found one here. As per the datasheet, it shows it contains BLE and MCU. I need to program the MCU for accessing the GPIO pins. Can I connect a USB-TTL converter and program SoC like this or is it requires special development kits for development.
AI: Official tools are listed at TI's site http://www.ti.com/product/CC2541/toolssoftware
You need an 8051 toolchain (compiler and friends). You also need a programmer like the CC-DEBUGGER. There may be some software that can bit-bang an FTDI chip to program the CC2541.
Development kit is the easiest option to get started with a new chip.
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H: Intel max 10 dimensions - datasheet & BSDL mismatch
TL;DR: The BSD file from Intel doesn't match the datasheet. What are the right dimensions?
BSD: https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/bsdl/10M02SCM153.bsd
Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00471-00.pdf
So I was drawing a max 10 (10M02SCM153) and afterwards saw that you can download the BSD files from Intel (see link above). I crosschecked the imported BSD drawing and the Intel datasheet and came to the conclusion that they don't match.
The number and the layout of the pins match.
According to Intel and the datasheet their BSC informations are in milimeters: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07152011_585.html
I have a 10M50DAF484 besides me and measured his dimensions and crosschecked with the datasheet: Everything Ok.
Then I checked the BSD file of the 10M50DAF484 and the dimensions where ok too.
In the case of the 10M02SCM153, which dimensions are the correct ones?
AI: The datasheet will be correct. Notice the table states that the unit is "millimeters".
I dont know why the Eagle dimensions are wrong. There doesn't seem to be any dimensional data in the BSD file, so I'm not sure how Eagle can interpret it.
In fact, in the BSD file it says at the top:
Package : 8 mm 153 MBGA
Which matches the 8mm of the datasheet.
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H: What is the purpose of this two pin component?
What is the purpose of this two pin component (circled)?
It looks to me like a jumper, but it seems strange that it would be so complex for just a jumper (that apparently does nothing). Sits between an AC input and a bridge rectifier.
AI: It's a solderless spade connector, soldered to the PCB.
Like this:
http://www.keyelco.com/product-pdf.cfm?p=681
(www.digikey.com Keystone: 3547)
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H: Altium Gerber File Copper Breaks
I'm getting some really weird effects on my Gerber File outputs from Altium
Altium 18.1.9, using OutJob Files, here are my settings
My layers look completely normal with a copper pour for the ground plane like shown here
However, when I export Gerber files, I get these bizarre lines through everything that seem like they would cause everything to be connected to ground,
I have no idea what is causing this, have any of you seen this before or have any suggestions for things to try? I'd appreciate any help!
AI: You're ADDING three mechanical layers to each copper plot. Don't do that.
Welcome, and thanks for the well-written question with all the information provided up front. +1
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H: How do I calculate the unknowns of the current equation for a RLC series circuit?
Suppose I was dealing with the following voltage equation for the RLC series circuit:
\$ v(t) = Ae^{m_1t} + Be^{m_2t} + V_s \$
To know the values of A and B I would do the two initial conditions:
voltage at t=0 (I would solve the equation for t=0)
dv/dt at t=0 (I would derivate the equation and solve for t=0)
Now suppose that I want to do the particular conditions for the current case to discover A and B.
\$ i(t) = Ae^{m_1t} + Be^{m_2t} \$
What should I do? I suppose the conditions are the same, so, if I have the current equation, I have to integrate that to get voltage's but doing so, I will generate a constant of integration that will be a third unknown (I suppose it will be V0).
The whole thing is sounding a little strange.
In resume: I give you the i(t) equation of a series RLC circuit in the form
\$ i(t) = Ae^{m_1t} + Be^{m_2t} \$
How do you get, for example, the values of A and B in the form of variables, I mean in terms of formula that can be used for any case?
How is that really solved?
AI: Now suppose that I want to do the particular conditions for the
current case to discover A and B. What should I do? I suppose the
conditions are the same, so, if I have the current equation, I have to
integrate that to get voltage's
If you have the current equation then A = current at t = 0 and B = di/dt at t = 0. Because all components are in series, the inductor defines the current and, di/dt = V/L as per the well-known equation for an inductor: -
$$V = L\dfrac{di}{dt}$$
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H: How do I connect up a replacement run capacitor
I have bought a replacement Run Capacitor for a forced action mixer (special cement mixer), as the run cap on the mixer blew. The mixer has a single phase motor, and although we are in the UK, it runs from a 110V power supply (standard on UK construction sites).
Possible reason it blew is that we used a power supply that didn't provide enough continuous power. Manufacturer recommends 5KVA continuous but we used 3KVA. Or we left the mixer on too long. Either way we have purchased a new 10KVA power converter and the electrician connected up to a 32A type C RCBO.
The motor is labelled with run cap and start cap values (130uF and 1200uF respectively) and I have researched a replacement capacitor and purchased this: https://www.mouser.co.uk/ProductDetail/80-C9TS6MD6137AARX. Unfortunately the manufacturer was unable to send a like-for-like replacement as the mixer is an old model.
I researched the subject and bought a polypropylene / film capacitor of 137uF, slightly more than the old one.
However my new replacement capacitor has three terminal blocks on the top, not two, and came with a tag on the connectors. I have looked at the data sheet but still don't know how to hook this up, or what the tag does. Behind the label of the tag appears to be PCB traces. The tab may be there to keep it discharged?
I am aware of the dangers of handling capacitors and how to discharge them.
1/ Have I bought the right capacitor? It is much larger in physical size than the original.
2/ Should this tab be removed? What is it for?
3/ Please see photo, showing three connections on the new cap. Which terminals do I hook up to the brown and blue wires (i.e. + and -) on the capacitor connection box on the back of the motor?
AI: It looks like you bought a 3 phase PFC cap for a single phase motor.
There must be a neutral connection (lower terminals) to 3 separate caps with 1 for each phase (upper terminals).
Datasheet says "aluminum can capacitors are three-phase capacitors for power factor correction (PFC). KEMET C9T 415 / 440VAC rated voltage capacitors feature polypropylene metallized film and include an overpressure safety device. C9T PFC capacitors are also available with delta connections"
The Run cap is chosen to shift the phase of the coil to maximize torque and minimize conduction heat losses from excess current during operation.
simulate this circuit – Schematic created using CircuitLab
Unfortunately between any 2 pins of a 3 phase delta cap is the equivalent circuit of 3 caps = 1.5x C. If two pins were shorted then it would be 2xC.
You really want a single cap equivalent to ~ 130uF within 20% or so, but perhaps the 3 phase 92.2uF cap (138uF) is close enough and is Amp rated to exceed your needs. KEMET C9TS5MD5920AARX
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H: What is the typical value for thickness of via plating?
I use PCB tools and sometimes they ask for via plating thickness, what is a value that I can approximate most via plating thickness? What value would you use and why? If I wanted to bound the thickness (min,max) what values could I use?
AI: Standard Spec for Beta-layout (https://us.beta-layout.com/pcb/technology/specifications/ Material construction tab) is 16-23 \$\mu \mathrm{m}\$ for copper in barrel. I suppose you can ask for whatever you need, but this is their standard board.
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H: Powerbank from laptop battery
So I just found an old netbook which battery has 6x 18650-26F cells and thought of trying to make a powerbank out of them. This is the specs page:
http://gamma.spb.ru/media/pdf/liion-lipolymer-lifepo4-akkumulyatory/ICR18650-26F.pdf
I just need some ICs and a bit of soldering to make them work but I still have some simple questions.
Which is the best configuration about parallel/series? So I can use a boost converter.
Should I need a battery management system for each pair?
Sorry for the basic questions, not much into electronics yet.
AI: Your simplest solution would be all parallel. That way, there's no need for balancing, as there would be with a series string.
Equalise the voltages before connecting the cells in parallel, connect cells with resistors for a while to do this easily. This is very important, dangerous currents can flow if you connect unequal batteries directly.
Use a fuse per cell when connecting in parallel, to prevent a single battery fault becoming a disaster as the other 5 batteries gang up on it.
A boost converter up to 5v output would be needed from the 4.2 to 3(ish) (depending on your chosen endpoint) voltage range of the cells.
If you only want 5v at 1A, then a single 18650 plus boost converter will meet that requirement. Add more cells to last longer, or for higher current output.
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H: How to read Capacitance Table?
I bought a 30pF Variable Trimmer Capacitor, but am unsure how to adjust it. The lowest capacitance I am getting by adjusting the screw is 50pf, and it doesn't seem to matter which way I turn it. I contacted the seller again to get more info about the range (I need 2-22pf for my fm transmitter project) and he sent me this image, which I don't know how to read. I would really appreciate a pair of more experienced eyes telling me if this is the right capacitor (COLOR GREEN) for my project
AI: How are you measuring the capacitance? It doesn't take much to pick up 10's of pF of stray capacitance, and measuring single digit pF capacitors isn't easy.
The green body 30pF cap has a range of 6.2pF (maximum that you can expect the lowest capacitance to be) to 30pF +50/-10% (range you can expect the maximum to be, or 27pF to 45pF).
So it does not appear to be suitable to get your minimum capacitance required, especially if you have to account for some layout and other stray capacitance in your circuit. You might consider re-design of your circuit so that the minimum capacitance required isn't so low.
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H: Need to find a compatible ac adapter
I have a Syemour Duncan guitar effects pedal that I bought several years back. I seem to have lost the power adapter for it and they don't make them anymore. I looked at the power input on the pedal and it says 16V~ / 560mA. The manual says
Do not try to substitute a DC power supply or another AC supply with a
different voltage or current rating.
They give a website where you can buy a replacement adapter, but the only applicable replacement I could find is no longer carried.
However, I did find this adapter on amazon. The voltage matches but the current is 1000 mA. It's my (fairly uninformed) understanding that it's okay for the adapter's current to be higher than the device's. At least that supposedly true for DC current. Not sure about AC. Would the amazon adapter be safe to use?
I also notice that the amazon adapter lists the plug as being 2.1mm. I'm not sure if that's compatible with my pedal. Is there anyway to know?
AI: It's my (fairly uninformed) understanding that it's okay for the adapter's current to be higher than the device's.
That is true. The adapter rating is the maximum current it is can supply. It will work quite happily with lower current loads.
Would the amazon adapter be safe to use?
Yes, if the voltage matches what the pedal requires - 16V AC.
I assume it is well-made and meets all local regulations. Not everything sold on Amazon is.
the plug as being 2.1mm. I'm not sure if that's compatible
That is a very common standard. Unfortunately the problem with standards is that there are so many to choose from.
It is actually not hard to change the connector with a wire-cutter and soldering iron. You can buy or make adapters quite easily. Parts are available from lots of places (eBay, Amazon, electrical distribution businesses, hobby-electronics online stores, ...) For a 16V AC supply, there should not be any safety concern in making these sort of changes at the low-voltage end.
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H: Which DC power jack to use with AC-AC adapter
I bought an AC-AC adapter for a project (takes 120 VAC mains and produces 12 VAC/3.5 A). It has a regular DC power jack (2.5mm I.D., 5.5mm O.D.) and I want to purchase a DC power jack to connect to it.
However, all DC power jacks I could find are rated for a specific DC voltage and current.
Are there any AC-rated DC power jacks on the market, or must I use a DC-rated one? Are there any special considerations I should be aware of?
AI: You can use DC barrel jack for AC. In fact, the jack that can handle 12VDC @3.5A would be more than sufficient for 12VAC, since AC RMS power will be less than corresponding DC power (that's assuming your AC voltage spec is peak amplitude)
See for example this digikey search
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H: How do the Ripple Limit lines get determined on antenna measurements?
I'm doing an S21 ripple measurement through a VNA and I understand how the measurement is done, but I don't understand how the limit is determined. I know you can specify the limit in dB and then you specify the Hz where that limit applies.
However, how does the VNA determine where to draw the limit lines for the ripple test?
For example, when looking at this test, it puts one limit line at -1.58 dB and another at -2.58 dB. Why does it choose to put the lines here and not at the line I drew in yellow for example?
If anyone can point out what I'm missing, it would be appreciated.
AI: It looks like the limit lines are \$x\$ dB away from the midpoint between the highest value in your graph and the lowest value. This makes sense for a ripple measurement, as any measurement that has a peak to peak ripple of less than (for example) 3 dB, all points on the graph will be less 1.5 db from the "middle" of the graph.
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H: Control large voltage supply using smaller voltage
I have a 6 volt supply that I need enable/disable using another 3 volt supply.
If I use a PNP Darlington set-up like this:
Then I get just under 6 volts at the Output node.
My problem is that I don't have any PNP transistors but I do have several NPN transistors and I was hoping that setting up a NPN Darlington would give me similar results, but building something like this yields about 2 volts at the Output node:
My question is; is there a circuit I can make using NPN transistors (2N2222 to be exact) what will give me a voltage close to V2 voltage when V1 is enabled?
AI: Try this circuit:
simulate this circuit – Schematic created using CircuitLab
The reason your circuit doesn't work is because you're using an "emitter follower" circuit. Basically what it does is the transistor maintains a voltage at the emitter that is the same as that at the base, minus a diode drop. Using a darlington in this case doesn't help because the transistor will not conduct if the base is lower than the emitter.
Note that the voltage at the collector of the transistor will not be 6 volts when it is on (you don't want that anyway), however the load will have very close to 6 volts across it when the transistor is switched on.
Edit: as mentioned by @jonk, your micro's output pin does not source enough current to drive this transistor enough to switch your pump. You have a couple of options here, you could buffer the output of your microcontroller through a buffer like a 74HC34, or you could use a darlington configuration with 2 2n2222 transistors as shown here.
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H: How to create custom through hole pad shapes in Altium Designer?
I'm trying to create a footprint for the ACS770 current sensor in Altium Designer (17.1), which has a quite irregular shaped pad: ('round' pad shape with slot hole, and then a small cutoff in the middle). How do I generate such a pad shape?
This is what it should become: (Datasheet)
This is how far I get in Altium:
The vias are no problem, but I don't know how to create the 1 mm 'cut-off-space' between the two pads.
Everything I can find on custom pad shapes for Altium is with SMD pads, in which case you can just draw a small pad, then extend the surfaces using regions or other primitives, but no results for through hole / multilayer pads...
AI: Figured it out!
You can do the same trick as with the SMT pads, but draw on the 'multilayer' layer.
Steps:
1) Draw Small pad with correct slotted hole
2) Draw half a circle (on the left of the left pad) on the 'Multilayer'-layer. Set soldermask / paste expansion to 'from rules'.
3) Draw the cutoff circle on the right (using circles and lines). Use Tools --> Convert--> Create Region from selected primitives to get the shape in the center of the pads, set the soldermask / paste expansion to 'from rules' for this region.
Result:
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H: Problems extending a 12V power lead to an RGB-LED strip
I need advise on the following problem: I am connecting a 5 metres WS2812B based RGB-LED strip to an extension cord. This is a 12V version, where two LEDs are coupled in terms of their addressing and IC. There are 100 addresses and 200 LEDs. I am generating the control signal from a Raspberry Pi.
I connect the ground of the Pi's GPIO and the ground of the external 12V power supply (a strong 150W laptop power adaptor)
I connect GPIO 18 out (3.3V) to the DI of the LED strip
I connect the 12V to the LED strip
This works
Now I want to insert an extension between power supply and Pi on one end, and the LED strip on the other end. I bought a 3x 0.75mm 20 metres cable for that. (Here is the product description in German if you are curious).
I inserted two wires between the 12V power supply and the GND/12V pins of the LED strip
I inserted the third wire between GPIO out and the strip's Digital In.
This doesn't work
Simply powering the strip seems fine; all LEDs go on. If I run the modulating program on the Pi, the first three or four LEDs are erratically flickering, that's it. Now I tried all sorts of combinations to figure out what is going on. For example,
I inserted a LLC to lift the digital output signal from 3.3V to 5V. Makes no difference. Does not work.
I extended only the power but connected the digital signal directly without extension. Makes no difference. Does not work.
I extended only the digital connection, leaving the power supply directly connected to the strip. This works.
This result was very surprising to me. I kind of feel relieved that I won't have trouble extending the digital signal, but now I'm baffled why the power extension apparently doesn't work. Using a volt metre, I saw that over the 20 m, the voltage drops from 12V to 9V. However, compensating by setting a higher voltage at the adapter, e.g. 15 to 18V to measure around 12V on the other end, did not change the situation.
My question is: What is the reason for this problem, and what should I do to properly extend the power connection by 20 metres? Is this simply a fault of the diametre, or am I looking at the wrong type of cable? Because even a standard 240V euro cable only has 0.75mm diametre. (In German this type of cable is called H03VV-F). The cable needs to work in outside space.
AI: The voltage drop over 20 meters of cable will vary based on the load, which you will no doubt be varying based on the number and color of leds you turn on. The change in voltage will cause issues with the led controllers. Use a local regulator, or capacitors, or both. Or use standard AC extensions and keep the power supply local to the strip.
The diameter of the cable will affect it, because a smaller diameter wire has a higher resistance and a higher resistance means a bigger voltage drop as the current increases.
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H: What equipment do I need to test an eye diagram for USB?
I'd like to test USB full speed with a goal of testing high speed (480 Mbit/s), I have a tek scope that does 300 MHz (which I could upgrade to 500 MHz) and I'm looking at a 500 MHz differential probe. As I understand it I also need a breakout board (which I'm not quite sure is the best thing to get), but I'm looking at this board from tek and one listed here.
What are the minimum requirements for a test like this?
Is this equipment list sufficient to preform an eye diagram test for full speed USB?
Is this equipment list sufficient to preform an eye diagram test for full speed USB if I have a 500 MHz scope?
AI: What are the minimum requirements for a test like this?
Minimum requirements for test equipment to use for USB 2.0 signal quality evaluation is listed at USB.org in the following place. There are links that describe electrical test procedures and tool requirement for Rohde & Schwarz, Tektronix, Agilent, LeCroy, and Yokogawa oscilloscopes.
Typically the eye evaluation software tools are offered on scopes with no less than 2GHz bandwidth. For Tektronix, the eligible scope series are TDS7254/B, TDS7704/B, CSA7404/B, TDS6604/B, TDS6804/B, TDS6404, DPO7254, DPO7354, and DPO/DSA70000. The smallest eligible oscilloscope for USB 2.0 testing is MSO/DPO5204.
For FS evaluation you don't need differential probes, the scope does it mathematically using single-ended probes.
However, the software package can't be installed on smaller bandwidth scopes, so, even if 500 MHz bandwidth is OK for FS eyes, it is unlikely that you can use this scope.
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H: What is the "Nyquist" rate for sampling the derivative of a signal?
Background: I'm sampling the current through a capacitor. The signal of interest is the voltage across the capacitor. I will digitally integrate the current measurement to obtain the voltage.
Question: Given that the voltage across the capacitor is bandwidth limited, and I am sampling the derivative of this voltage, what is the minimum sample rate required to perfectly reconstruct the voltage signal from the current samples?
If there is no canned answer to this question, anything that could point me in the right direction would be helpful. Thank you in advance for any help!!
AI: Taking a derivative (or an integral) is a linear operation — it doesn't create any frequencies that weren't in the original signal (or remove any), it just changes their relative levels.
So the Nyquist rate for the derivative is the same as that for the original signal.
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H: Cheap way to get 5V DC from 12V AC?
I'm currently doing a home automation project which involves my intercom system being controlled by a NodeMCU. The intercom system runs off 12V AC. As for the actual automation/wiring itself, I think I have that fairly well covered. However, I would love to be able to power the NodeMCU directly from the 12V AC rather than having to bring in an extremely long extension cord just to supply 5V DC.
Whilst I am aware that there are plenty of options available for getting 5V DC from 12V DC, I have been almost completely unsuccessful in finding a simple convertor to do exactly what I intend at a low price.
I would really appreciate it if someone could give me some guidance as to how they may think to overcome this problem.
Thank you in advance for any help.
AI: Generating 5V @500mA is easy, all you need is a bridge rectifier, largish capacitor and a 5V switching regulator.
The switching regulator is a replacement for the older linear regulators, you can use something like the R-78E-0.5 from Digikey or there are dozens of cheaper units on Ebay.
Since you are only adding about 2.5-3.5W maximum to your 12V AC input supply, I'd imagine you would have no problems.
simulate this circuit – Schematic created using CircuitLab
BUT THERE IS A PROBLEM ...in all probability the 12V AC is converted into at least one supply within your intercom. This means you CANNOT connect DIO pins or ground on the ESP8266 to points within the intercom as it may damage one or both.
You can overcome this problem in several ways:
Opto isolate all signals going to/fron the ESP8266 and the intercom
Find a DC supply voltage inside the intercom that can be used to power your ESP8266, then you can have a common ground. (You might even be able to find a 5VDC supply)
Use an isolated switching regulator such as the TEL 3-2011 from Digikey, and then connect the grounds together.
Update:
Since #3 seems to be a better fit from the comments, this would be the schematic:
simulate this circuit
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H: Wiring for a 12V AC relay module?
I'm currently trying to automate my intercom system. My overall aim is to have it so that I can both detect when the buzzer has been pressed and then also to have it so I can open the door. I am using a NodeMCU as the main controller. I'm fairly familiar with DC but have had virtually no experience with AC. Therefore, it has been easy for me to simply wire a relay triggered by the NodeMCU to open the door when requested.
However, I have been stuck trying to work out a method of detecting the buzzer press with the NodeMCU. This is due to the fact that the intercom system runs off 12V AC. After some searching around, my options were narrowed to either a Current Sensor or a Relay. The Current Sensor seems to be too much detail for what my purposes are; leaving me to fall once again on Relays. This time, however, due to the fact that the thing triggering the relay (the buzzer in this case) is using 12V AC rather than DC it has left me in a slightly awkward position as I am unsure exactly what I am looking for.
I have found myself upon this relay which seems to be what I am looking for. I would really appreciate it if someone could:
A) Let me know if this is the right sort of relay for my use case. And if not then what is (and costs little)?
B) Point me in the right direction of exactly how to wire this sort of relay.
This is because, unlike DC relays, I expect that AC relays only take 2 inputs (compared to 3); i.e. the relay gets triggered when electricity flows into the module. Is this correct?
Thank you in advance for any help.
AI: Both AC and DC relays should have two terminals for the coil - apply the appropriate voltage between those terminals to operate the relay. For the relay you linked to, you would apply 12 Volts AC to those terminals.
Any relay will have two or more contacts for the contacts (the switch part of the relay) Although the Amazon listing doesn't say, with 8 terminals that relay must be a DPDT (Double pole, double throw) type.
A schematic symbol for that relay would be:
simulate this circuit – Schematic created using CircuitLab
Circuitlab won't let me place the labels where I want - hope you'll understand things.
To operate the realy, you apply 12 volts between terminals "Coil 1" and "Coil 2".
The contacts for one pole of the relay are "COM1" - the moving contact, "NC1" Normally closed contact - connected to "COM1" when the relay is not operated, and "NO1" - Normally open - connected to "COM1" when you apply power to the coil (similar for COM2, NC2, and NO2).
You don't have to use both sets of contacts - only connect the terminals that you need for your application.
I don't understand what you mean by "This is because, unlike DC relays, I expect that AC relays only take 2 inputs (compared to 3); i.e. the relay gets triggered when electricity flows into the module. Is this correct?", but I hope I've explained that relay's operation sufficiently.
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H: Alternatives to High Wattage Resistors? (Do multiple low-wattage resistors equal a single higher wattage resistor?)
I am a beginner, so I may have made a horrible mistake in my diagram, but I am trying to learn.
According as I have figured it, I am having an issue wherein I need a resistor rated for a minimum of about 1.07 Watts; this is well, however, I do not have any resistors rated that highly heat-wise. I figured that I could just use a group of five 1/4W resistors, similarly to how a pair of two different resistors adds to a higher resistance.
*That does say 20kΩ and 29.6kΩ in the schem.; I have no idea why I opted to not write the capital omega in those two places.
AI: Why yes, you can certainly combine multiple resistors to spread out the power dissipation.
I see you've planned to have 177.5V across and 6mA through R1.
You can parallel 5 resistors that will take 1.2mA each.
177.5V / 1.2mA gives 147916 ohms, probably 150k ohms will be close enough. Then put 5 of them in parallel. The overall resistance will work out to 30k ohms (150k / 5).
Note that 1/4W resistors, even though they're rated for 1/4W, can still get rather hot when dissipating 1/4W, enough to burn you. Make sure to leave room in between for airflow (don't just bunch them all up together).
Also note that you probably won't be able to turn the anode off with this circuit. And if you do manage to turn it off, your Arduino will be fried.
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H: Finding the unknowns of a current equation leads to non-sense
Suppose a series RLC circuit that is critically damped.
Circuit is RLC in series with a DC voltage source \$ V_S \$ and a switch initially open. Capacitor and inductor are both discharged.
at t=0 the switch is closed.
I am trying to analyze what happens during the transient phase.
The circuit equation is
\$ i(t) = (At + B)e^{-\alpha t} \$
I want to find A and B.
So I apply the initial conditions.
The first condition is current when t=0. We know that the inductor will resist the initial current, so i(0) = 0.
If this is true and I apply that to the equation, to find A/B, I get
\$ i(t) = (At + B)e^{-\alpha t} \$
\$ 0 = (At + B)e^{-\alpha t} \$
at t=0
\$ 0 = (0 + B)e^{0} \$
\$ B = 0 \$
The other condition, di/dt at t=0.
We know that current will be zero, because the inductor will guarantee that, so
\$ \frac{di}{dt} = \frac{V}{L} = 0 \$
so,
\$ i(t) = (At + B)e^{-\alpha t} \$
\$ \frac{di}{dt} = 0 = -\alpha A t e^{-\alpha t} -\alpha B e^{-\alpha t} \$
when t= 0
\$ \frac{di}{dt} = 0 = -\alpha B \$
\$ B = 0 \$
again... I don't get it.
What am I doing wrong?
AI: $$ i_{(0+)}= i_{(0-)}= 0 $$
$$ v_{L_{(0-)}} = 0 $$
$$ v_{L_{(0+)}} = L \left[ \frac{di}{dt} \right]_{t=t_{0+}} $$
Note that \$\left[ \frac{di}{dt} \right]_{t=t_{0+}} \neq 0 \$
From \$ i_{(0+)} \$ , \$ B = 0 \$
From the derivative of response \$i(t)\$:
$$\left[ \frac{di}{dt} \right]_{t=t_{o+}}= \frac{v_{L_{(0+)}}}{L} = A$$
From the KVL (\$V\$ is the source voltage and \$V_{C_{(0+)}}\$ is the voltage on capacitor in \$t=t_{o+}\$):
$$ v_{L_{(0+)}} = -V_{C_{(0+)}} + V -Ri_{(0+)}$$
or
$$ v_{L_{(0+)}} = V$$
Therefore:
$$ A=\frac{V}{L}$$
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H: UL Clamping Voltage Ratings on Surge Protectors
I have been looking for some new surge protectors for my devices, and I am having trouble understanding the meaning of the voltage clamping ratings on many surge protectors. It seems that all of the UL ratings are much higher than one would expect, as the lowest one is 330v, whereas mains voltage in North America is 120v. Would this mean that even if there was a surge that went to 300v, the surge protector would do nothing to protect the connected devices?
AI: Having been in the SPD industry I did a lot of product and MOV testing. The reason for the high values is that these devices are tested at either 10,000 amps for 5,000 hits of 16 to 20 uS duration, or 8 by 20 as we call it. 8 uS rise time and a duration of 16 to 20 uS at the 50% of peak voltage point. Another option is 15 hits at 20,000 amps, spread out over an hour.
The results from vendors is kept secret, as there is tough competition between SquareD, Seimens, APC and APT (which I worked for). Note that it is surge current of tight accuracy and specific waveforms used for repetitious testing, while a single voltage clamp test (At 1.00mA) was used to validate the survival of the surge protection device, and was done before surge testing to establish a baseline clamp value. After testing a drift in the baseline of more than 10% meant the device failed testing.
The severe testing is to prove to UL 1449 3rd and 4th edition standards that the device can withstand severe current (simulated lightning strike) by simply absorbing it or failing by blowing an internal fuse. Ferraz/Shawmut makes MOV's with thermal cut-offs built in so along with 30 amp 600 volt fuses per MOV bank it is supposed to shut down with no out gassing or explosions.
An MOV's 1 mA test is the rating on the MOV plus about 50%. That is called the "soft clamp" rating. Also, 150 volt MOV's are used on 120 VAC circuits. MOV's marked 320 are for 208 to 240 VAC. 420 volts MOV's are for 277 VAC (USA) and 347 VAC Canadian power feeds. We put 2 in series to handle 600 VAC delta power used in Canada or 480 VAC delta used in US industry.
You are correct in that the "hard clamp" voltage is way above the supply voltage. Even the "soft-clamp" voltage is 30% to 50% above the line voltage.
This is because decades ago the surge industry learned a hard lesson. MOV's rated at 130 VAC were bursting into flames because of slight rises and variations in a 120 VAC source. In my house it is as high as 125 VAC sometimes. Then UL stepped in and mandated the 30% to 50% safety margin. 130 VAC MOV's are no longer made or allowed to be used in any surge suppression device.
During the last 2 decades UL and now ISO have become very stern about testing, pass ok modes and allowed fail modes. If a huge surge suppressor is installed in a hospital at the service entrance panel it can only fail by shutting down quietly, no matter how severe the lightning strike may have been. These devices include mica barriers between phases to prevent flash-over and give the platinum fuses time to blow.
The end results of all of this regulation is a surge suppressor that may clamp higher than ideal (though expensive Sidac based units have a tighter clamp voltage), but in the long run safety dominates, especially in other countries where the power grid is a bit unstable.
Better safe than sorry. Never buy a surge suppressor that does not have UL and ISO stickers on it. The ISO labels are holographic so they cannot be copied and used on cheap and dangerous rip-offs.
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H: Power Supply - Shorting a cable creates a ground?
I used a power supply the other day to power an op-amp. I was told to set it up in the following configuration, however I do not completely understand why this works.
The shorted cable acts as ground??
AI: You can pick anything you want and call it ground.
This power supply box has two power supplies in it.
Shorting the + of one to the - of the other puts the two power supplies in series. That gives you a so-called "split" power supply.
You can call the middle connection ground and then you have +15V, 0V and -15V wires.
Or you can call the right connection ground, and then you have +30V, +15V and 0V wires.
Or you can call the left connection ground, and you get 0V, -15V and -30V wires.
Note - some dual power supplies have the - of both supplies connected, inside the box. In that case, shorting the + of one to the - of the other would short out one of the supplies. This one doesn't have them connected.
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H: Is group delay the same as the delay of a certain frequency?
I know that group delay is the delay of the envelope, or the derivative of the phase with respect to \$\omega\$. What I want to know is what exactly happens in the time domain.
For instance take the following graph of the group delay of a bessel filter (there are several curves depending on the order of the filter)
Consider the curve at the very top which is near the 0.6s mark, does it mean that if I inject a normalized 1.1Hz frequency into the filter, will that signal be time delayed almost 0.6s at the output? meaning that the difference in time between the output and the input at that frequency is 0.6s?
A thing that also makes me believe that the group delay means time delay is the step response. Here's the step response of the same Bessel Filter
It seems like there is a delay from the 0 second point.
AI: The group delay is a function of frequency, so you cannot really say it's the same as the delay of a certain frequency -- that would be a particular case. Also, the step response is an infinite sum of sines plus DC, which means that the Heaviside function is not really proper to determine the group delay (since you are measuring a combined effect of group delays, given the infinite sum of sines), particularly when negative group delays come into play. Exceptions to the rule are the linear phase FIRs.
So, the correct way to determine the delay (group or phase) at a certain frequency, is to feed the filter a harmonic signal, a sine, that has, ideally, no other harmonics than the fundamental. Whether you modulate the input with a gaussian pulse, or not, depends on your approach, but modulating the pulse diminishes the possible transient settling times associated with more "unruly" magnitude reponses around the corner frequency.
For the Bessel filter, the transients of the step response are very small (it's not quite critically damped), for Gaussian they're (ideally) null, but for Butterworth and up (Papoulis, Pascal, Chebyshev, etc), and even for transitional filters (Butterworth<->Bessel), the magnitude response around the corner frequency tends to be sharper and sharper, translating into less linear phase characteristics, thus a more "wobbly" derivative of the phase.
In time domain, this can be viewed as decaying oscillations. For a sudden input, such as a step, or cosine, the output will take time to settle until a proper measurement can be made. Modulating the input with a gaussian pulse, for example, will cause the derivative of the envelope to be smooth, thus mitigating the transients.
Consider the curve at the very top which is near the 0.6s mark, does it mean that if I inject a normalized 1.1Hz frequency into the filter, will that signal be time delayed almost 0.6s at the output? meaning that the difference in time between the output and the input at that frequency is 0.6s?
If you are referring to the particular reading of [email protected], then yes. But take note that the group delay and the phase delay are different beasts. What you are measuring is called the phase delay, that is, the delay of the phase of the signal compared to the input. This becomes more apparent for filters with less linear phase. For example a 2nd order Chebyshev, fp=1Hz, 1dB ripple, has 302ms@1Hz (group delay is the dotted trace):
If you run a time domain test with a 1Hz sine, modulated by a gaussian pulse (input is V(x)), this is what you get:
and zoomed in:
Notice that the reading says the difference is 234.67ms, which might be close to 302ms, but it's not it. If, on the other hand, we calculate the phase delay:
$$H(s)=\frac{1.1025103}{s^2+1.0977343*s+1.1025103}$$
$$t_{pd}(\omega)=-\frac{\arctan H(j\omega)}{\omega}
=-\frac{\arctan\frac{1.1025103\omega}{1.1025103(1.1025103-\omega^2)}}{\omega}$$
$$t_{pd}(1\text{Hz})=\arctan\frac{1.1025103}{1.1025103^2-1)}=0.23518$$
Compare 235.18ms with 234.67ms, and you get really close, save minor misalignments of the cursors, roundings, few points/dec, etc. So you should take care what you are measuring.
I would've answered in the comments, but it deserves a bit more explanation. The Bessel filters are a happy case since they are approximations of the Laplace \$e^{-s}\$, which translates into more and more linear phase as the order goes higher. This, in turn, means constant group delay. So, at this point, you can see that the phase delay, calculated as above, means the phase divided by frequency (pulsation), which means a linear variable divided by another linear variable => constant. For the group delay, you have the derivative of a linear variable => constant. Here's how the plot of the two look like for the textbook definition of the 2nd order Bessel filter:
$$H(s)=\frac{3}{s^2+3s+3}$$
As you can see, both the phase delay (blue) and the group delay are flat and equal, at least until around the corner frequency, where the phase becomes less linear, thus the phase and the derivative diverge. If you increase the order to, say, 4:
$$H(s)=\frac{105}{s^4+10s^3+45s^2+105s+105}$$
The phase delay here is a bit approximated since I had to get around the atan2() quadrant limitations, but you can see that they get more similar.
So what you are measuring when you are trying to determine the single frequency input (as above) is actually the phase delay. The group delay would measuring the envelope (as you, yourself say it) of the modulated sine. Also see the paper I linked in the beginning, there are some nice explanations in there, worth reading.
I'll also give a few examples of why you cannot say that the step response gives you the "group delay" because, as stated in the beginning, the delay (phase or group) is a function of frequency and, unless you are talking about a linear phase FIR, you cannot say that a filter has a group (or phase) delay of X, or that the Heaviside function gives you the group (or phase) delay, because the delay varies with frequency.
Here's a 2nd order Bessel's step response and measure @50% rise time. Notice that the readings get closer to the DC value of the group delay as the order increases, but that number would only be an exact match if the filter had the ideal \$e^{-s}\$ transfer function, thus a constant delay from DC to light, which will never have since it is an approximation:
and the readings of the group delay at DC and corner frequency:
And here are the same two readings for an 8th order:
Just for comparison, a 5th order Chebyshev, 1dB ripple:
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H: Can someone explain me the role of MOSFET in this circuit ? Are these MOSFET working as a switch here?
This Image is taken from the PIC16(L)F15356/75/76/85/86 MCU datasheet
datasheet- go to page number 286 for more details
AI: Your question is answered on page 28.
Because they are enable bits, yes, they are being used as switches, turning the inputs/outputs on or off.
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H: Explanation of the circuit in an LED bulb
I just know the basic electronics, not an expert in the area :)
When I dismantled a broken LED lamp, I could see the circuit below (section after the rectifier, the DC part). 15 LEDs in series. There are two such lines. If they were just parallel lines I know how the circuit works, but they are inter connected here.
Two of the LEDs in a row were broken, So I thought of adding an equivalent resistor value as I did not have the right LED with me. Then the bulb started blinking when powered. Then instead of resistor I just shorted the position of broken LEDs and now it works.
Can anybody explain me the working of this circuit, especially what happens when the parallel lines are interconnected?
AI: LED bulbs usually use a current source. That is a driver that provide a constant current through the LEDs. Putting the LEDs in series is then the logical way to connect multiple LEDs to the same driver.
The reason the leds are put in in a series string of parallel pairs is to add some redundancy if one LED fails and to avoid mismatched LEDs making one string brighter than the other.
If you short out a single LED the voltage across them all will be dropped by the driver so the current matches what it was programmed to emit. The matching led will not light up anymore.
The reason it started blinking when you replace an LED with a resistor is because the driver will have open circuit detection and reset itself if it cannot supply the voltage needed for the current it wants to drive.
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H: Use USART pin in UART mode
I want to use a device who has an USART interface. But my microcontroller has only a UART communication.
Can I connect the UART_TX and UART_RX on USART_RX and USART_TX?
Thanks
AI: Yes you can if you use only asynchronous communication (ie. without separate clock line).
By definition an UART is a special case of an USART.
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H: Is there an "L" type of five wire connector?
With the controller shown,
notice the connector heads "west" (yellow),
meaning a tight enclosing cabinet needs to be as wide as the red indication.
However, if the white connector immediately did a 90 degree turn down
(direction downwards in blue)
you can see it would drastically save width of a tight enclosure.
Is there such a thing? A 90° version of the white connector seen?
(I suppose ... a 180 degree would be even better, a "backwards" connector)
Note - of course, for a one-off one could just modify the board and I guess solder on five wires which could hang straight down. However it's not a reliable pipeline when producing many of them, allowing for easy field repairs, etc etc.
(FWIW I considered just specifying to "bend down" the five pins on all units, but then the "locking tongue" of the white connector would have to not exist ... again it's a flakey solution.)
thanks @RemcoVik, trying my best to add more photos!
It has no identifying marks I can see :/
AI: I doubt you'll find a right angle version of that particular one. As Jasen says, the pins are crimped onto the wire and inserted into the housing and that's not really possible with right angles.
But if you measure the pitch you can probably find an IDC connector that will fit where the wires go in at right angles - something like this:
Alternatively, make a small adaptor board that will sit at right angles with a vertical socket at the top and the same connector as the controller at the bottom pointing downwards. Or even a different socket if it makes assembly easier.
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H: DAC negative bias reference voltage
I'm using TI's 18-bit DAC9881 and need the output to go a little below 0Volts in order to account for offset voltages of following Op-Amp stages.
The DAC allows to provide a "low reference" between -0.2V and 0.2V to offset the output, which is just what I need.
My question is how to generate this reference voltage? It does not need to be very accurate (I need to calibrate the whole circuit anyway), but should be precise, i.e. stable over time. I have +5V/-5V LDO output power supply rails (TI LM27762).
One option would be to use a voltage divider connected to Op-Amp in voltage follower configuration. However, supply noise and load transients will disturb this poor man's reference.
The other option I see is a shunt regulator. I didn't find any with a fixed reference voltage of 0.1V-0.2V, so the suggestion in this answer https://electronics.stackexchange.com/a/383440/197145 does not work.
I did find a 4.9V reference (Diodes ZRT050) though, which could be used like this:
simulate this circuit – Schematic created using CircuitLab
However, this way (if it works?) the reference voltage is established with respect to the -5V power supply instead of GND, so I fear to get the same problems with noise and transients as with the op-amp solution.
Does anyone have a better option to implement a reference voltage of -0.1V to -0.2V from a 5V/-5V supply? If not, which of the two solutions seems more suitable and why?
Cheers,
Kai
EDIT:
I built the circuit from the accepted answer and it provided the expected bias voltage. However, I read the datasheet of the DAC9881 wrong and found that my goal of shifting the output below GND by providing a negative bias voltage to the REFL input does not work. The amplifier in the output stage of the DAC has some fixed headroom to the negative supply (GND), which cannot be worked around by adding a negative offset. This can only be achieved with external circuity behind the DAC output.
AI: The reference inputs are low impedance, typically 5K ohms, so you should drive them with low impedance sources.
The easiest approach is to use an op-amp from your existing positive reference voltage. I'll assume that's 2.5V here. If it's something else, just alter R2 appropriately.
You can choose an appropriate op-amp to meet your purposes.
simulate this circuit – Schematic created using CircuitLab
The output voltage is -Vref*(R1/R2)
R3, D1 prevent the output reference voltage from going too far negative, even during transient conditions. C1 enhances stability.
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H: Capacitor in common collector circuit
I have a question regarding \$C_1\$ capacitor - do we really need it in this circuit if we know, that the input signal will have no offset (i.e. \$\overline{V_{IN}}=0V\$)?
AI: do we really need it in this circuit if we know, that the input signal will have no offset
You mean, can we remove C1 (replace it with a short) if the DC voltage of Eg is 0 V ?
Well in this case: no.
Look at the circuit and think what would happen if you would remove C1. Let's look only at the situation for DC. Since the DC voltage of Eg = 0 V, we can remove Eg as well. Now Rg connects the base of the NPN to ground.
Under normal operation, in the circuit as you have drawn it (with nothing removed), what is the DC voltage at the base of the NPN?
Is it 0 V or something different?
Now what would happen if we connect Rg between that base of the NPN and ground?
What will happen to the base current Ib? Will it still all flow into the base of the NPN? I think not. I think part of the current will flow through Rg.
So what does C1 do? It blocks Ib from flowing into Rg and Eg.
Only if you would make sure that there is no DC voltage (VDC = 0 V) present at the base of the NPN then C1 could be removed. But that would require a negative supply voltage. Another solution is to give Eg a DC voltage (offset) that is exactly the same as the DC voltage at the base of the NPN.
But that DC voltage depends on Vbe, Ic and Re. Especially Vbe is very temperature dependent, making it difficult to always have the right offset. It is much easier to just use a DC blocking capacitor: C1.
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H: Tolerance on SMD Aluminum Electrolytic Capacitors
I'm searching for some polarized surface mount device capacitors on lcsc.com and notice that they only have tolerances of \$20\%\$ tolerance devices in their catalog for this type of SMD device whereas the through hole counter parts have much lower tolerances. Is this normal for this type of device? My inherent feeling is that a \$20\%\$ tolerance is rather large.
edit:
The capacitors will be used in a Li-Po charge management circuit as shown below:
AI: Yes, it's completely normal. Electrolytic capacitors (and also typically high capacitance MLCC capacitors) are not usually designed into applications where tight tolerance is important. For a filter capacitor -20/+80% is sometimes just fine.
You should use an MLCC ceramic capacitor, but keep in mind that the tolerance can be worse than 20%, and almost always in the wrong direction- down, when you take voltage coefficient into account. Very small (physically) capacitors operated at close to the rated voltage are usually the worst in that regard.
Ceramic caps are what is recommended in the datasheet. Ceramic capacitors have lower ESR (they are "better") but that may cause problems in some situations, but in this case there are no issues from ESR.
The datasheet says (for a particular configuration):
Use standard value 10 μF, 25 V, X5R, ±20% ceramic capacitor (that is, Panasonic 1206 ECJ-3YB1E106M
If you were to subsitute a Murata 0402 10uF/6.3V cap (adequate for a single 4.2V cell) the tolerance is given as +/-20% but typically at 4.2V the capacitance would be less than 3uF, and probably less than 2uF if you take temperature and bias and tolerance into account. So +/-20% is a bit of a dream. Maybe at room temperature and with 0V across it, plus they can actually make the capacitors much more accurately than +/-20% under set conditions so they're actually cutting it on the low side (typically 9uF at room temperature with 0V bias).
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H: What kind of breadboard and prototyping board do I need for this right-angle DB25 connector?
What kind of breadboard and prototyping board do I need to fit this right-angle DB25 connector?
I'm new to soldering and don't know what the standards are. Additional information on this subject would be helpful as well.
AI: What you are searching for is a DB25 breadboard adapter, looking like this:
Website (example): Example
They also exist in a smaller (double row) format like on this website
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H: Fire danger when using IoT components
I am automating my house using components like ESP8266, 220 to 5V converters, relays etc.
How big is the risk of a fire starting from a component malfunction and how can I mitigate this? What should contain my design in order to minimize this risk?
Is there a book or some documentation that I should read?
AI: Depending on where you live there should be a set of regulations governing the proper installation of electrical equipment. In the US that is the National Electric Code. Find the corresponding document for your region and follow all of its rules.
When purchasing equipment, be sure to buy devices that have been safety certified as necessary in your region. In the US, as Bimpelrekkie said, that is typically an Underwriter's Laboratory certification.
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H: Choosing inductor to limit inrush current
I have a 12V DC input to a circuit. There is a 660uF Aluminum cap on the input.
The 12 volt source is not in my control and can come from anywhere. So it could be a noisy source or a high current clean source.
I am wondering if it's worth it to put an inductor in series with the input to limit inrush current? Or even if it's worth limiting the inrush current in this specific case at all?
I know that there are ICL devices and MOSFET devices that can limit the rise time and they are made for this.
One device is the TI TPS22810DBVR. And is pretty cheap in volume.
But, I already have a cheap 4.7uH inductor that can handle my 2Amp max draw from my circuit. And i'm hoping I can use this for 2 reasons:
Limit inrush current
Help clean up the 12V input.
I have done some simulations.
Cap: 660uF with 130mOhms ESR
Inductor: 4.7uH with 37mOhm resistance.
12V DC input with 1V/uS rise time. (Just guessing on that one since I don't have control over what the source is.
This gives me:
This gives a peak current of 62Amps. Now I may not have control over the 12V input source, but i'm pretty sure it's not going to be from a source that can output 62Amps. Maybe a 12Amp source that can handle 12Amps peak loads for a short time.
So since the peak current allowed (theoretically) is 62Amps, but is limited by the source, I would say there is no point in putting the 4.7uH inductor in there because it's still going to allow the same peak current of 12Amps whether it's there or not. Is this a good answer for my questions?
It should still help clean up the 12V input though right? A cutoff frequency of around 2857.6Hz. Maybe get rid of switching noise if it's a SMPS.
Please let me know your thoughts and experience with this situation. I could put a bigger inductor in there, but I am very limited on PCB space.
AI: No you should not use an inductor to limit the inrush current to your circuit for a lot of reasons, one of them being that it could actually induce ringing (oscilations) in your circuit.
First of all you should ask yourself; why do you even want to limit the inrush current? It would only serve to protect the thing that is supplying the 12v power to your circuit and since you dont know what is going to supply the 12v you dont know what the limitations of that thing is in terms of peak current either. If the thing you use to supply the 12v to your circuit has a limitation on the peak current that it can handle then the protection should be on the output of that device not on the input of yours.
You should also considder that what ever you use to supply 12v to your device is going to have an output resistance greater than 0ohm and that is generally what is going to dictate how large the inrush current will be. You should only think of reducing the inrush current if you know that you are going to supply power from a device that is capable of producing a larger peak inrush current than that device is capable of handling.
If you want filtering on the input of your circuit you should use a common mode choke, if you want to get rid of switching noise from the 12v source then you should put some low esr/high frequency caps in parallel with the caps on your input, and if you want to reduce the ripple on your input then you should put more caps on.
In the case that you absolutely need to limit the inrush current on your device then you should use a transistor or a resistor, generally you dont want to use a resistor because it is going to also reduce your efficiency due to the power lost in the resistor. The way it is usually done is with a transistor which at the same time function as a reverse polarity protection.
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H: Series RL AC circuit Laplace analysis
Question: Find the complete expression for i(t) in a series RL circuit with source \$Vsin(\omega t)\$.
simulate this circuit – Schematic created using CircuitLab
So to attack this I thought to bring out the ol' ant trusty Laplace tranform.
The final eqn I get is
\$ V \frac{\omega}{s^2+\omega^2} = (Ls+R)I(s)\$.
which becomes \$ V\omega \frac{1}{s^2+\omega^2} \frac{1}{(Ls+R)} = I(s)\$.
Can someone suggest a good method to move forward from here? I've tried fraction decomposition but I just can't move forward :(
AI: Take partial fractions: -
\$\dfrac{1}{(s^2+\omega^2)(s+b)}\$ becomes \$\dfrac{b-s}{(\omega^2+b^2)(s^2+\omega^2)}+\dfrac{1}{(\omega^2+b^2)(s+b)}\$
The reverse laplace of this is moderate to easy. I don't think you need me to help you with the \$\omega\$ on top or the reduction of (sL + R) to (s + b).
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H: FIFO Buffer (Circular/ring buffer) for packet storage
I am developing a simple radio transmission network using B-L072Z-LRWAN1 boards. The network structure is formed by:
One board acting as a gateway (where data is received).
Multiple boards acting as nodes (which send data to the gateway).
The packet payload sent by nodes is N bytes long and I want to store this packet's information in case gateway stops working and nodes cannot communicate with it. I want to keep data that could not be sent by the node and send it once the gateway is active again.
Let's say I want to keep the last M messages that node could not send to the gateway. The buffer size should be M*N bytes long, but how do I implement this type of buffer in C?
Thank you in advance!
AI: //pseudo algorithm First In First Out
int FIFO[16]; // size of 2^N
int WR_Ptr, RD_Ptr; // Write and read pointer
int Input, Output;
// On write event
FIFO[WR_Ptr] = Input;
WR_Ptr++; //increment WR pointer
WR_Ptr &= 15 // apply mask 2^N-1, turn over in circular manner
if WR_Ptr==RD_Ptr //buffer overrun?
{
//handle error
}
//On read event
if WR_Ptr<>RD_Ptr //check if FIFO is not empty
{
Output = FIFO[RD_Ptr];
RD_Ptr++; //increment RD pointer
RD_Ptr &= 15 // apply mask 2^N-1, turn over in circular manner
}
//clear FIFO
RD_Ptr = 0;
WR_Ptr = 0;
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H: How to set output voltage on this dual output buck converter board?
I guess this board's dual output voltage is configured by the EN terminal?
Resistance to ground? (Link to the eBay listing: 20W DC-DC Step UP & Down 5V-35V 12V 24V to ±5V ±9V ±12V ±15V Dual Power Supply.)
These are cheap on eBay, but I bet they arrive undocumented and there is no indication of how to set the voltage on the listing. I've asked the seller and had no reply as yet. I would be very grateful for advice, it looks a very good solution for powering a graphic EQ module.
AI: Note that as always when asking for help on someone else's product, this is an educated guess about possible explanations. You can only get a definite answer from someone who knows that specific product. As one of the moderators here correctly points out: We are not tech support for Ebay sellers :-)
In the Ebay listing you mentioned, the lack of documentation and the deliberately obscured part number of the main IC would be enough to stop me from buying that module. Without that part number, I can't easily lookup the datasheet of the IC (without spending lots of time searching for ICs which match that pinout). With that part number, reverse-engineering the rest of the circuit would be simple.
However to answer your question, and since that Ebay listing doesn't allow you to choose one of the listed output voltages, here is one hypothesis since the listing you linked says:
Output voltage: adjustable ( test: ± 5v 12w 77% / ± 9v 15w 84% / ± 12v 20w 86% / ± 15v 20w 88% )
(My emphasis above.)
In other words, the fixed voltages mentioned in the listing (±5V, ±9V etc.) are just examples.
After some searching, I found this almost identical PCB but with a variable resistor exactly where we would expect to see one, varying voltage to a feedback pin on a typical regulator:
(Cropped image from this Ebay listing)
The Ebay listing with that PCB photo has a very similar description to yours: "20W DC-DC Step UP & Down 5V-35V 12V to ±5V ±9V ±12V ±15V Dual Power Supply Board" but as you see, I have highlighted the variable resistor which is present on that board.
So possibilities for the confusion on the listing you mentioned include:
The photo on the listing you gave is correct for a single, fixed voltage board and you really would get a fixed voltage board, without being able to specify the voltage when you buy it.
That means that some of the text in the listing (which specifies a variable output voltage) is wrong. Or...
The photo in the listing you gave is wrong, and the board being shipped is actually like the one shown in the photo above, with a variable resistor to change the output voltage. That would match with the description text saying that the output voltage is variable, and would mean that the photo in the listing you gave is wrong.
I don't see any way for the photo in your listing and the text in that listing, to both be correct.
However, as you said, it will likely come without documentation (as such boards typically do from Ebay) and you cannot expect the vendor to actually know anything about it (many are just warehouses / resellers, with no technical knowledge about what they sell). This is the risk you take, when buying from such vendors.
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H: Is it better on two closely connected microcontrollers to send nibbles with an ack or a byte with a delay for an ack?
I'm trying to figure out the best approach to transfer high-speed data one way between two microcontrollers (with their own crystals of the same speed) of the same variety (between AT89C4051 and AT89S52) from an electrical standpoint.
I have them wired up as follows:
AT89S52 P0 is connected to AT89C4051 P1
AT89S52 P1.1 is connected to AT89C4051 P3.7
The AT89C4051 has 6 bytes of data that the AT89S52 needs, and the AT89S52 always initiates the download.
My options are as follows:
** OPTION 1. Transfer byte-wide. **
Code in AT89C4051 (transmitter) will be this:
mov R1,#DATALOCATION
jb P3.7,$ ;Wait for falling edge
mov P1,@R1 ;send out byte
inc R1 ;Increment pointer
jnb P3.7,$ ;Wait for rising edge
mov P1,@R1
inc R1
;and this code (minus first line) repeats twice for remaining bytes
And the AT89S52 will have this code:
mov R0,#DATASPACE
mov P0,#0FFh ;Make ports accept data
clr P1.1 ;lower line to get first byte
mov @R0,P1 ;Load next byte in
inc R0 ;increment pointer
nop ;waste cycles to let AT89C4051
nop ;be ready for next byte. Is this wait time enough under worst
;case scenarios???
setb P1.1 ;raise line to get next byte
mov @R0,P1 ;Load next byte in
inc R0 ;increment pointer
nop ;waste cycles to let AT89C4051
nop ;be ready for next byte
;and this code (minus first line) repeats twice for remaining bytes
That is my 8-bit approach which seems fast, but I didn't have enough pins free to use one for an acknowledgement pin as the rest are used.
** OPTION 2. Transfer nibble-wide **
Code in AT89C4051 (transmitter) will be this:
mov R1,#DATALOCATION ;pointer = start of data
jb P3.7,$ ;Wait for falling edge (but this means stalls which I don't like)
mov A,@R1 ;get byte
orl A,#0F0h ;and accept lower nibble.
clr ACC.7 ;Make P1.7 our ack bit (ack=0)
mov P1,A ;return data in lower nibble with P1.7=0 as ack
jnb P3.7,$ ;Wait for rising edge
mov A,@R1 ;get byte
orl A,#0Fh ;and accept high nibble. (ack=1)
swap A ;and put it in our low nibble slot
mov P1,A ;return data in lower nibble with P1.7=1 as ack
inc R1
;and this code (minus first line) repeats 5x for remaining bytes
Code in AT89S52 (receiver) will be like this:
mov R0,#DATALOCATION ;pointer = start of data
mov A,@R0 ;Load byte
orl A,#0F0h ;set our nibble and make rest of lines high to receive ack
mov P1,A ;and show it
clr P1.1 ;lower clock
jb P1.7,$ ;wait till remote is ready
mov A,@R0 ;Load byte again
orl A,#0Fh ;set our nibble and make rest of lines high to receive ack
swap A ;swap nibbles so we get right nibble
mov P1,A ;show data
setb P1.1 ;raise clock
jnb P1.7,$ ;wait till remote is ready
inc R0
;and this code (minus first line) repeats 5x for remaining bytes
which is best?
But the part that makes me concerned is timing and hardware.
The micros are connected no more than 10cm away from each other and all PCB traces are 12mils wide with 12mils clearance. When I run any microcontroller circuit, if my hand touches both leads of the crystal, then the speed of operation seems to vary (probably because human resistance affects crystal frequency?)
Given all environments the micros can be exposed to (except water), which of my two ideas is best to ensure I get data at the highest speed possible? and I only have 9 I/O lines to play with here.
So do I resort to the nibble method and wait for acknowledgements even if the response takes a while? or am I safe to use the byte method?
Remember, we have to assume worst-case scenarios. fingers touching crystal area (as a test), weak batteries, etc. because the last thing I want to happen is data loss.
For clarification, each crystal lead is connected to 33pF ceramic capacitors which are also grounded. (I'm using the standard microcontroller crystal setup). and my ground planes are large.
UPDATE
As requested, I included the important connections. Both crystals are 22.1184Mhz. The capacitor and resistor connected to the reset pin is 47nF and 100K. All other capacitors are 33pF.
I also included a basic timing diagram. I had to use paint to draw the lines in because I have no program on my computer to do professional diagrams.
AI: First of all, you need to put your project in an enclosure that prevents human fingers (or anything else) from getting so close to the crystal that it has a major effect on the frequency.
Once you have the clocks under control, the first method should be fine, assuming that you have accounted for the worst-case delays through the I/O synchronizers on both chips. Keep in mind that although the two processors are at the same nominal frequency, their actual frequencies will vary slightly and the phase relationship between them can be anything at all.
You'll probably need a few more nop instructions on the master side (the one generating the clock). Also, those nop instructions should come before the instruction that reads the data — this gives the slave procesor the time it needs to recognize the clock transition and actually put the data on the 8-bit bus.
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H: Hand-cranked vs hydro-turbine generator for single potential energy (no continuos flow)
Let's say you have a certain amount of water at a height; think a bucket with 3 liters of water in it on a 4 meters tall wall. By letting this water to fall, we'd have an opportunity to convert some of this potential energy into electricity.
By using cheap commercial gadgets, one could achieve this by:
Hand-cranked generator, using the falling mass of the full bucket to do the cranking (using pulleys to get the right torque). example
Micro water turbine, letting the water flow from top to bottom, where the turbine would be located. example
There are many options on the market for each strategy. Some are more expensive, some have very specific limitations in terms of working pressure, minimum rpm, etc.
My question is: is there a preferred method between these two from a purely conceptual point of view? Should one of these methods achieve higher efficiency in most cases under similar limitations?
AI: With 3 kg of water falling 4m, you're talking about a very small amount of energy, 120 Joules, or 20 watts for 6 seconds.
While both hydro and hand-cranked generators can be very efficient, the question is how well they keep their efficiency when scaled down to this very low power.
My money is on a mechanical solution scaling better, the thought of 4m of pipe and all that turbulence just feels very lossy indeed. Most machines get better as they get bigger.
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H: How to read wire wrap labels?
This image is an example of a wire wrap label that lists multiple AWG numbers.
What does it mean? How could it be anything but a single specific gauge?
AI: The part number (P/N B-30-1000) indicates it is AWG30 (and black and 305m = 1000').
The part number is printed onto a pre-printed 2-color label which contains the UL specification numbers and well as the brand. UL is "a global safety consulting and certification company headquartered in Northbrook, Illinois. It maintains offices in 46 countries."
The relevant UL specification number in this case is UL1423 since it's AWG30. The standard is "Appliance Wiring Material UL 758".
That tells you (follow the link) that it's 105°C Polyvinylidene Fluoride (PVDF) Resin Insulated Wire, and provides some test parameters.
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H: Apply voltage to a solar cell
I was thinking about a power circuit in which the power can be supplied on the same rail through a solar panel or an ac adapter. I automatically thought to add diodes in series to form an OR gate, so the panel wont supply the ac adapter and vice versa. But then I thought- do I really need to protect the solar panel from reverse current? What would actually happen?
What happens if you supply power to the solar panel, not from it? I would appreciate all help.
AI: Your solar panel may already have a series diode to prevent it from sinking current, in which case you're fine. But otherwise, yeah, it will draw reverse current from the supply.
Referring to the standard equivalent circuit of a solar cell, if you exceed the threshold voltage on the shunt diode, the cell will begin to conduct reverse current.
If you've got a commercial solar panel, I believe they typically have reverse protection diodes built in to prevent a shaded panel from sinking current from the rest of the array. You'll want to verify that's the case for the exact panel you're using, of course.
simulate this circuit – Schematic created using CircuitLab
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H: Why does Channel Length Modulation Increase with Higher Vgs
I'm curious as to the physical reason as to why the effect of channel length modulation in an N-MOS actually increases when the Vgs voltage is increased?
See the plot below:
For a long channel device, as the Vg is increased, the R0 is actually decreasing. This makes sense if you think about channel length modulation as the inverse of the slope of the Ids-Vds in the saturation region, and that all of these slopes have to intersect at the early voltage.
But physically why does this occur?
AI: Stated simply, higher gate voltage means more electrons in the channel. That means more current can flow between drain and source; thus lower resistance.
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H: How to rotate several parts with respect to origin without changing its (x,y) coordinates in KiCAD?
Say I have a part located at coordinates (50,50) and I want to rotate it 10 degrees w.r.t. origin. To do so, I will select the part and press "Move Exactly" and key in these values:
Now the problem is I have 50 seperate parts that I need to rotate in this manner. Viewing each part's coordinates individually and rotating them manually is very repetitive and I'm sure I'm missing some shortcut. Is there a better way to do this?
EDIT:
Before photo:
What I'm intending to do link:
Now I am unable to simply rotate it then position it afterwards, as I need the pcb to match with my keyboard switch plate, which is generated from
AI: Rotating a group requires selecting the group first. Note here I am selecting right-to-left which selects everything that touches the selection box.
Then apply the rotation
Result:
Edit
To answer your comment, let's say that your reference footprint is at 50,50 in x,y and you would like to rotate your group of footprints 10° about the grid origin, keeping the footprints aligned with the radial.
To do this, start with the same procedure as before and select the group you wish to move.
Next, use the same move command as before but this time enter the coordinates of the top left pad in your selection into the x/y boxes
Next, change the coordinates type to "Polar". This will change the values from 50/50 to their equivalent r/theta values. Now, since you are rotating the group by 10°, you need to adjust the radial position by -10°. I have also selected "Override default footprint anchor" otherwise, the default anchor will be the center of the group.
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H: MCP73831: VBat Voltage drop with new uncharged batteries
I made a circuit for charging a 40mah lipo battery (381018), my problem appears when a new uncharged battery is connected. The battery measures 0V at the begining, when it's conected the VBAT pin only goes to 1.58V, so the battery is not getting charged at all.
The problem doesn't appear if the battery have some voltage on it, in that case the battery charges normally.
I have a 25k (0402) resistor connected to Rprog, if I change that resistor to 10K the problem dissapears but I'm charging a 40mah battery with 100mA, it's not safe.
1) Could the problem be the size of the resistor (0402)?
2) Should I put an special array for the 0V uncharged batteries?
AI: This is most likely self-discharging of the defective battery, or - hopefully - a feature of the charging IC to prevent the battery from catching fire. LiPo batteries should be disposed of if they're discharged below 3 volts or so because they get damaged when they're over-discharged.
Don't continue using this battery. It is a fire hazard. Get a new one.
Also, don't throw the battery in the trash - put it into a battery recycling container.
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H: Why is resistor in parallel with capacitor needed in capacitor bank?
Capacitor bank in power supply compensates for when input voltage is shortly disconnected (50ms lets say). Do capacitors in this setup (between input and the output of power supply), get initially charged and then remain charged until input power gets disconnected? After that, do capacitors discharge their energy at the output load. If the output load is there to discharge capacitors, why would resistors in parallel to capacitor bank be needed?
AI: A typical DC power supply (like you might find in your phone charger) will look something like this (probably with more protection devices and other extras). The AC will be rectified by a bridge rectifier and smoothed by a capacitor to create high voltage DC. Then a power supply IC will quickly switch the current through a transformer on and off to step down the voltage to say 5V. The output is once again rectified and smoothed, then fed to your phone:
simulate this circuit – Schematic created using CircuitLab
The resistors across the capacitors (especially R1/C1 because they are at high voltage) are there to discharge the capacitors when the device is unplugged, so that if someone touches the output they won't get shocked. Because the capacitors are there only for smoothing, and not to allow the device to function for a while after power is removed, having the capacitors discharge quickly when the device is unplugged does not hinder their operation and improves safety, so they're included almost everywhere.
Note: I have omitted several things from the schematic, such as a power rail for the converter chip, feedback windings, or flyback configuration, as they do not help to illustrate the functioning of the capacitors and discharge resistors.
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H: How much voltage and current to charge a 24V battery?
If I have two 12V 18A batteries and I want to charge them in series making a 24V 18A battery, how much voltage and current do I need to charge this 24V without damaging the batteries?
AI: You need to get the voltage and current charge information for the battery. It may be written on the side of the battery, otherwise you'll have to look up the data from the manufacturer.
The numbers you're looking for are "float voltage" (more conservative) or "cycle voltage" (less conservative). The charge current may not be specified, but if it is then use it. If it is not, then "1C" is generally a safe charge current. To calculate 1C, get the capacity of the battery in amp-hours (often written "Ah"). It may be that the "18A" figure you state is actually "18Ah". Then replace "Ah" with "A" to get the "1C" charge rate. For example, if your battery has a capacitor of 18Ah, then the 1C charge rate is 18A.
Finally, and critically, when you put the two batteries in series you must double the charge voltage, but keep the charge current the same.
For example, suppose your float voltage is 13.8V and your 1C rate is 18A. Then to charge two batteries in series, apply a maximum voltage of 27.6V and a maximum current of 18A.
Remember, you can always make this safer by lowering the max current. I advise starting at 1/4C or lower and only increase to 1C if you really want fast charge and are well prepared to handle the potential heat and gas production. See Peter Bennett's 0.2C recommendation in the comments below.
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H: Identify the op amp IC
I am repairing a board, that has an IC labelled K72 J46 P.
I know it is an op amp MSOP8, and that pin 4 is GND, but I cannot find the manufacturer part number so that I can buy a replacement.
AI: It appears to be an NCV20072 or NCS20072, which is a 3MHz dual rail-to-rail output op-amp. Datasheet: https://www.onsemi.com/pub/Collateral/NCS20071-D.PDF
For the record, this was found by searching for the string "k72" top mark op amp. The datasheet shows that K72 is the device-specific marking, J46 is a date code (year and work week), P signifies the manufacturing location, and the dot indicates that the package is lead-free.
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H: If I convert 10 V, 1 ampere to 5 V, do I get 5 V 2 ampere?
I know the current in the circuit is the same.
And also,
Power = 10* 1 = 10 watts.
So,
10 = 5 V * (x) ampere,
X = 10/5,
X = 2 ampere,
With some loss while using a voltage regulator, I will get some loss in current also ... That's not a problem. All I need is: if I reduce the voltage, do I get the same 5 V 2 ampere?
AI: If you use a linear regulator, no. You get 5 V, 1 A.
If you use a buck converter, not quite. The converter is not 100% efficient. Maybe you get 8.5 or 9 W out, so 5 V, 1.7 or 1.8 A.
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H: Using SFP modules from a microcontroller
I'm interested in having an embedded device send data optically. This is for test and measurement, where having conductive cables is problematic since it will perturb the measurement. The device is built as a prototype now except for the data sending interface. The data rate requirements are moderate (10-20Mbps one way). The distance is short, 5-10ft. This is somewhat power limited, but using 0.2-0.5W for comms is okay.
I looked at IrDA but that seems to be almost completely obsolete, and the data rates are too low (other than the very unavailable UFIR/GigaIR). I also looked at TOSLINK, and that seems to be almost-obsolete, and I can't source fast (125Mbps) transceivers, nor can I figure out how to run the slower 10MBps ones reliably at anything close to their max rated speed.
Now, I could hack some kind of completely proprietary UART-over-fiber protocol, or wait for LiFi, or mod some of the really expensive Corning optical USB cables to not have a power conductor... all of these are problematic in various ways. Then I thought, why not just use SFP transceivers on both ends?
I have only a very basic idea of what is inside a SFP, and essentially no idea how to talk to it. Could someone explain to me how to drive a SFP from a microcontroller? Either (a) a UART-over-fiber using SFP and microcontrollers on both ends, or (b) ethernet using SFP from a microcontroller and regular SFP ethernet device on the other end?
P.S. If it matters, the microcontroller is a STM32F446; I would like to stick with STM32 if possible. The device is battery powered from a 2500mAh lithium ion battery.
P.P.S. I can build devices on both sides of the link; the near side would probably have some kind of optical-to-USB-serial converter, if it is not simply ethernet.
AI: Looking at what's in the SFP modules, it may not be all that difficult to use them directly.
Since the signals are AC coupled to LVDS, you'll need to communicate in a DC balanced protocol such as Manchester, which your chosen ARM may or may not support (my current favorite Microchip SAME70 does support it). And, of course, add LVDS receiver/transmitters. You may be able to ignore the EEPROM since you only want to work with a single type of SFP module.
Judging by the values shown, you'd probably have to keep the frequency at 10MHz or higher, which you will need to do anyway for that data rate.
May or may not be worth looking into further, but it does look promising to me. Here's an excerpt from the above pdf document:
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H: What is PVDD and AVDD?
I know VDD,VCC,VEE and VSS and what they stand for. But when I came across this circuit:
I saw this. Those PVDD and AVDD terms?
What to do they convey or stand for?
This circuit is amplifier circuit of PAM8403 DS.
AI: The answer is right in the datasheet for PAM8403:
So P stands for "power" and A stands for "analog".
Chip vendors and board designers are essentially free to name pins or nets however they like. The "AVDD" designation is pretty common for the pin powering the analog part of a chip. I've never seen "PVDD" before, but I don't work in audio, so I wouldn't know if it's common or not in that field.
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H: Can really small transistors be modeled as in undergrad textbooks?
Most undergrad textbooks on microelectronics (those covering semiconductors, diodes, BJT's, FET's, etc.) that I have laid my hands on discuss semiconductor concepts such as charge carries, drift, recombination, among others, to explain why transistors behave the way they do, and then present mathematical models for how different types of transistors work (e.g. IV curves) in order to analyse circuits involving them.
My question is, can state-of-the-art transistors such as those in modern CPU's be modeled by similar formulas? Given that modern transistors based on 7 nm technology can be only a few atoms in size (~30), do the same concepts apply, or do you really need PhD-level knowledge to even begin to understand how they actually work?
I've seen from other sources how ASIC foundries will share pspice models of the transistors that they can handle to customers and that they tend to be extremely complicated with dozens if not hundreds of parameters, so I got curious about this.
AI: My question is, can state-of-the-art transistors such as those in modern CPU's be modeled by similar formulas?
Yes
You need to understand what a model is.
A model is a description of a subset of the behaviours of something, that is sufficiently accurate for some stated purpose.
That is why you have different levels of model for the same thing, you have different purposes for using the model.
One model of a bipolar transistor is a IBE-dependent CE current source. This is enough for many purposes, crudely biassing a transistor for instance, or understanding a logic gate.
However, you need a more accurate model for building an amplifier, or a high speed logic gate. This is why you have Ebers-Moll, Gummel-Poon, behavioural SPICE models, measured S_parameters, and a few more besides.
Each is as simple as possible, while being good enough for the job in hand. None captures the entire range of behaviour shown by a real life transistor.
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H: Electromagnetic wave equation for GPS waves
Recently, I came across a source which stated the model of a GPS L1 wave was:
My question is, how was this equation derived?
AI: That equation isn't derived, it describes the contents of a GPS signal that is created by the electronics in the transmitter in the GPS satellites.
The electronics create quadrature signals (I and Q) so that the available spectrum can be used more efficiently. Using a quadrature signal positive and negative frequencies (relative to the RF carrier) can be used separately.
So it is not that the GPS engineers have build a system and then derived the equation from that. It is the opposite, it was decided that the GPS system should use quadrature signals and that means this equation is what needs to be implemented in the system.
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H: Why is digital serial transmission used everywhere? i.e. SATA, PCIe, USB
While looking at SATA, PCIe, USB, SD UHS-II it struck me that they are all the same: digital serial bitstream, transmitted using differential pairs (usually 8b/10b coded), with some differences in link/protocol layers.
Why so? Why did this become the standard?
Why are there no widespread system communication protocols that heavily employ some advanced modulation methods for a better symbol rate? Am I missing something?
This is not a question of "serial vs parallel" but a question of "digital signaling vs modulated analog"
AI: Why there are no widespread system communication protocols that
heavily employ some advanced modulation methods for a better symbol
rate?
If the basic copper connection between two points supports a digital bit rate that is in excess of the data rate needed to be transmitted by the "application", then why bother with anything else other than standard differential high-speed signalling?
Employing an advanced modulation scheme is usually done when the "channel" has a bandwidth that is much more limited than copper or fibre.
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H: 4th order (active) filter, I want constant phase shift band
I'm needing to improve an existing fourth order active filter design.
The filter amplifies 10-100 kHz signals as desired, however the phase shift is causing problems. 10 kHz signals are phase shifted around 200 degrees, but 100 kHz signals are phase shifted around 600 degrees.
The varying phase shift for desired signals is rather unhelpful. Ideally I would want the same phase shift for the entire frequency range. The magnitude of phase shift itself is of no concern, so increasing the phase shift at 10 kHz so that it is constant up to 100 kHz wouldn't be a problem.
Is there a type of (allpass) filter that introduces a decreasing phase shift? - for instance 360 degrees for 10 kHz and 180 degrees for 100 kHz?
Where should I start, how should I work, when trying to achieve constant phase shift in filter design?
AI: There are two ways to approach getting a filter with a flat linear phase passband.
a) Flatten the phase of a conventional steep filter. You can design all-pass phase correctors. You don't say what your 4th order filter is, some types have flatter phase than others. It's easier to flatten the first half of the passband where the non-linearity is small, it gets harder as you near the edge of the passband.
You need to start out with as flat a passband phase, which means as wide a passband, as possible, while still meeting your stopband requirement. If you're not using stopband zeroes yet in an elliptic design, then you have a lot of scope for widening the passband, while keeping your attenuation to specification.
b) Flatten the amplitude of a linear phase filter. These have a fairly soggy stopband, which will almost certainly need to be augmented with stopband zeroes. There are published designs for this for up to 8th order, so the basic design should be no trouble.
Do you have a stopband specification? If not, that's the first thing to fix, because otherwise, how will you know how wide you can make your passband?
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