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int32
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bool
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16,831
uint64_t ldq_be_phys(target_phys_addr_t addr) { return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); }
false
qemu
a8170e5e97ad17ca169c64ba87ae2f53850dab4c
uint64_t ldq_be_phys(target_phys_addr_t addr) { return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); }
{ "code": [], "line_no": [] }
uint64_t FUNC_0(target_phys_addr_t addr) { return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); }
[ "uint64_t FUNC_0(target_phys_addr_t addr)\n{", "return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);", "}" ]
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16,832
static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) { hwaddr addr; addr = ((uint64_t)ubase << 32) | lbase; return addr; }
false
qemu
9be385980d37e8f4fd33f605f5fb1c3d144170a8
static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) { hwaddr addr; addr = ((uint64_t)ubase << 32) | lbase; return addr; }
{ "code": [], "line_no": [] }
static hwaddr FUNC_0(uint32_t lbase, uint32_t ubase) { hwaddr addr; addr = ((uint64_t)ubase << 32) | lbase; return addr; }
[ "static hwaddr FUNC_0(uint32_t lbase, uint32_t ubase)\n{", "hwaddr addr;", "addr = ((uint64_t)ubase << 32) | lbase;", "return addr;", "}" ]
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16,833
static int nbd_send_rep(int csock, uint32_t type, uint32_t opt) { uint64_t magic; uint32_t len; magic = cpu_to_be64(NBD_REP_MAGIC); if (write_sync(csock, &magic, sizeof(magic)) != sizeof(magic)) { LOG("write failed (rep magic)"); return -EINVAL; } opt = cpu_to_be32(opt); if (write_sync(csock, &opt, sizeof(opt)) != sizeof(opt)) { LOG("write failed (rep opt)"); return -EINVAL; } type = cpu_to_be32(type); if (write_sync(csock, &type, sizeof(type)) != sizeof(type)) { LOG("write failed (rep type)"); return -EINVAL; } len = cpu_to_be32(0); if (write_sync(csock, &len, sizeof(len)) != sizeof(len)) { LOG("write failed (rep data length)"); return -EINVAL; } return 0; }
false
qemu
1a6245a5b0b4e8d822c739b403fc67c8a7bc8d12
static int nbd_send_rep(int csock, uint32_t type, uint32_t opt) { uint64_t magic; uint32_t len; magic = cpu_to_be64(NBD_REP_MAGIC); if (write_sync(csock, &magic, sizeof(magic)) != sizeof(magic)) { LOG("write failed (rep magic)"); return -EINVAL; } opt = cpu_to_be32(opt); if (write_sync(csock, &opt, sizeof(opt)) != sizeof(opt)) { LOG("write failed (rep opt)"); return -EINVAL; } type = cpu_to_be32(type); if (write_sync(csock, &type, sizeof(type)) != sizeof(type)) { LOG("write failed (rep type)"); return -EINVAL; } len = cpu_to_be32(0); if (write_sync(csock, &len, sizeof(len)) != sizeof(len)) { LOG("write failed (rep data length)"); return -EINVAL; } return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(int VAR_0, uint32_t VAR_1, uint32_t VAR_2) { uint64_t magic; uint32_t len; magic = cpu_to_be64(NBD_REP_MAGIC); if (write_sync(VAR_0, &magic, sizeof(magic)) != sizeof(magic)) { LOG("write failed (rep magic)"); return -EINVAL; } VAR_2 = cpu_to_be32(VAR_2); if (write_sync(VAR_0, &VAR_2, sizeof(VAR_2)) != sizeof(VAR_2)) { LOG("write failed (rep VAR_2)"); return -EINVAL; } VAR_1 = cpu_to_be32(VAR_1); if (write_sync(VAR_0, &VAR_1, sizeof(VAR_1)) != sizeof(VAR_1)) { LOG("write failed (rep VAR_1)"); return -EINVAL; } len = cpu_to_be32(0); if (write_sync(VAR_0, &len, sizeof(len)) != sizeof(len)) { LOG("write failed (rep data length)"); return -EINVAL; } return 0; }
[ "static int FUNC_0(int VAR_0, uint32_t VAR_1, uint32_t VAR_2)\n{", "uint64_t magic;", "uint32_t len;", "magic = cpu_to_be64(NBD_REP_MAGIC);", "if (write_sync(VAR_0, &magic, sizeof(magic)) != sizeof(magic)) {", "LOG(\"write failed (rep magic)\");", "return -EINVAL;", "}", "VAR_2 = cpu_to_be32(VAR_2);", "if (write_sync(VAR_0, &VAR_2, sizeof(VAR_2)) != sizeof(VAR_2)) {", "LOG(\"write failed (rep VAR_2)\");", "return -EINVAL;", "}", "VAR_1 = cpu_to_be32(VAR_1);", "if (write_sync(VAR_0, &VAR_1, sizeof(VAR_1)) != sizeof(VAR_1)) {", "LOG(\"write failed (rep VAR_1)\");", "return -EINVAL;", "}", "len = cpu_to_be32(0);", "if (write_sync(VAR_0, &len, sizeof(len)) != sizeof(len)) {", "LOG(\"write failed (rep data length)\");", "return -EINVAL;", "}", "return 0;", "}" ]
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16,834
void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, VirtIOBlockDataPlane **dataplane, Error **errp) { VirtIOBlockDataPlane *s; Error *local_err = NULL; BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev))); VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); *dataplane = NULL; if (!conf->data_plane && !conf->iothread) { return; } /* Don't try if transport does not support notifiers. */ if (!k->set_guest_notifiers || !k->set_host_notifier) { error_setg(errp, "device is incompatible with x-data-plane " "(transport does not support notifiers)"); return; } /* If dataplane is (re-)enabled while the guest is running there could be * block jobs that can conflict. */ if (bdrv_op_is_blocked(conf->conf.bs, BLOCK_OP_TYPE_DATAPLANE, &local_err)) { error_setg(errp, "cannot start dataplane thread: %s", error_get_pretty(local_err)); error_free(local_err); return; } s = g_new0(VirtIOBlockDataPlane, 1); s->vdev = vdev; s->conf = conf; if (conf->iothread) { s->iothread = conf->iothread; object_ref(OBJECT(s->iothread)); } else { /* Create per-device IOThread if none specified. This is for * x-data-plane option compatibility. If x-data-plane is removed we * can drop this. */ object_initialize(&s->internal_iothread_obj, sizeof(s->internal_iothread_obj), TYPE_IOTHREAD); user_creatable_complete(OBJECT(&s->internal_iothread_obj), &error_abort); s->iothread = &s->internal_iothread_obj; } s->ctx = iothread_get_aio_context(s->iothread); s->bh = aio_bh_new(s->ctx, notify_guest_bh, s); error_setg(&s->blocker, "block device is in use by data plane"); bdrv_op_block_all(conf->conf.bs, s->blocker); bdrv_op_unblock(conf->conf.bs, BLOCK_OP_TYPE_RESIZE, s->blocker); bdrv_op_unblock(conf->conf.bs, BLOCK_OP_TYPE_DRIVE_DEL, s->blocker); *dataplane = s; }
false
qemu
4be746345f13e99e468c60acbd3a355e8183e3ce
void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, VirtIOBlockDataPlane **dataplane, Error **errp) { VirtIOBlockDataPlane *s; Error *local_err = NULL; BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev))); VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); *dataplane = NULL; if (!conf->data_plane && !conf->iothread) { return; } if (!k->set_guest_notifiers || !k->set_host_notifier) { error_setg(errp, "device is incompatible with x-data-plane " "(transport does not support notifiers)"); return; } if (bdrv_op_is_blocked(conf->conf.bs, BLOCK_OP_TYPE_DATAPLANE, &local_err)) { error_setg(errp, "cannot start dataplane thread: %s", error_get_pretty(local_err)); error_free(local_err); return; } s = g_new0(VirtIOBlockDataPlane, 1); s->vdev = vdev; s->conf = conf; if (conf->iothread) { s->iothread = conf->iothread; object_ref(OBJECT(s->iothread)); } else { object_initialize(&s->internal_iothread_obj, sizeof(s->internal_iothread_obj), TYPE_IOTHREAD); user_creatable_complete(OBJECT(&s->internal_iothread_obj), &error_abort); s->iothread = &s->internal_iothread_obj; } s->ctx = iothread_get_aio_context(s->iothread); s->bh = aio_bh_new(s->ctx, notify_guest_bh, s); error_setg(&s->blocker, "block device is in use by data plane"); bdrv_op_block_all(conf->conf.bs, s->blocker); bdrv_op_unblock(conf->conf.bs, BLOCK_OP_TYPE_RESIZE, s->blocker); bdrv_op_unblock(conf->conf.bs, BLOCK_OP_TYPE_DRIVE_DEL, s->blocker); *dataplane = s; }
{ "code": [], "line_no": [] }
void FUNC_0(VirtIODevice *VAR_0, VirtIOBlkConf *VAR_1, VirtIOBlockDataPlane **VAR_2, Error **VAR_3) { VirtIOBlockDataPlane *s; Error *local_err = NULL; BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(VAR_0))); VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); *VAR_2 = NULL; if (!VAR_1->data_plane && !VAR_1->iothread) { return; } if (!k->set_guest_notifiers || !k->set_host_notifier) { error_setg(VAR_3, "device is incompatible with x-data-plane " "(transport does not support notifiers)"); return; } if (bdrv_op_is_blocked(VAR_1->VAR_1.bs, BLOCK_OP_TYPE_DATAPLANE, &local_err)) { error_setg(VAR_3, "cannot start VAR_2 thread: %s", error_get_pretty(local_err)); error_free(local_err); return; } s = g_new0(VirtIOBlockDataPlane, 1); s->VAR_0 = VAR_0; s->VAR_1 = VAR_1; if (VAR_1->iothread) { s->iothread = VAR_1->iothread; object_ref(OBJECT(s->iothread)); } else { object_initialize(&s->internal_iothread_obj, sizeof(s->internal_iothread_obj), TYPE_IOTHREAD); user_creatable_complete(OBJECT(&s->internal_iothread_obj), &error_abort); s->iothread = &s->internal_iothread_obj; } s->ctx = iothread_get_aio_context(s->iothread); s->bh = aio_bh_new(s->ctx, notify_guest_bh, s); error_setg(&s->blocker, "block device is in use by data plane"); bdrv_op_block_all(VAR_1->VAR_1.bs, s->blocker); bdrv_op_unblock(VAR_1->VAR_1.bs, BLOCK_OP_TYPE_RESIZE, s->blocker); bdrv_op_unblock(VAR_1->VAR_1.bs, BLOCK_OP_TYPE_DRIVE_DEL, s->blocker); *VAR_2 = s; }
[ "void FUNC_0(VirtIODevice *VAR_0, VirtIOBlkConf *VAR_1,\nVirtIOBlockDataPlane **VAR_2,\nError **VAR_3)\n{", "VirtIOBlockDataPlane *s;", "Error *local_err = NULL;", "BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(VAR_0)));", "VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);", "*VAR_2 = NULL;", "if (!VAR_1->data_plane && !VAR_1->iothread) {", "return;", "}", "if (!k->set_guest_notifiers || !k->set_host_notifier) {", "error_setg(VAR_3,\n\"device is incompatible with x-data-plane \"\n\"(transport does not support notifiers)\");", "return;", "}", "if (bdrv_op_is_blocked(VAR_1->VAR_1.bs, BLOCK_OP_TYPE_DATAPLANE,\n&local_err)) {", "error_setg(VAR_3, \"cannot start VAR_2 thread: %s\",\nerror_get_pretty(local_err));", "error_free(local_err);", "return;", "}", "s = g_new0(VirtIOBlockDataPlane, 1);", "s->VAR_0 = VAR_0;", "s->VAR_1 = VAR_1;", "if (VAR_1->iothread) {", "s->iothread = VAR_1->iothread;", "object_ref(OBJECT(s->iothread));", "} else {", "object_initialize(&s->internal_iothread_obj,\nsizeof(s->internal_iothread_obj),\nTYPE_IOTHREAD);", "user_creatable_complete(OBJECT(&s->internal_iothread_obj), &error_abort);", "s->iothread = &s->internal_iothread_obj;", "}", "s->ctx = iothread_get_aio_context(s->iothread);", "s->bh = aio_bh_new(s->ctx, notify_guest_bh, s);", "error_setg(&s->blocker, \"block device is in use by data plane\");", "bdrv_op_block_all(VAR_1->VAR_1.bs, s->blocker);", "bdrv_op_unblock(VAR_1->VAR_1.bs, BLOCK_OP_TYPE_RESIZE, s->blocker);", "bdrv_op_unblock(VAR_1->VAR_1.bs, BLOCK_OP_TYPE_DRIVE_DEL, s->blocker);", "*VAR_2 = s;", "}" ]
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16,835
uint32_t HELPER(servc)(uint32_t r1, uint64_t r2) { if (sclp_service_call(env, r1, r2)) { return 3; } return 0; }
false
qemu
9abf567d95a4e840df868ca993219175fbef8c22
uint32_t HELPER(servc)(uint32_t r1, uint64_t r2) { if (sclp_service_call(env, r1, r2)) { return 3; } return 0; }
{ "code": [], "line_no": [] }
uint32_t FUNC_0(servc)(uint32_t r1, uint64_t r2) { if (sclp_service_call(env, r1, r2)) { return 3; } return 0; }
[ "uint32_t FUNC_0(servc)(uint32_t r1, uint64_t r2)\n{", "if (sclp_service_call(env, r1, r2)) {", "return 3;", "}", "return 0;", "}" ]
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16,836
void ff_acelp_interpolate( int16_t* out, const int16_t* in, const int16_t* filter_coeffs, int precision, int frac_pos, int filter_length, int length) { int n, i; assert(pitch_delay_frac >= 0 && pitch_delay_frac < precision); for(n=0; n<length; n++) { int idx = 0; int v = 0x4000; for(i=0; i<filter_length;) { /* The reference G.729 and AMR fixed point code performs clipping after each of the two following accumulations. Since clipping affects only the synthetic OVERFLOW test without causing an int type overflow, it was moved outside the loop. */ /* R(x):=ac_v[-k+x] v += R(n-i)*ff_acelp_interp_filter(t+6i) v += R(n+i+1)*ff_acelp_interp_filter(6-t+6i) */ v += in[n + i] * filter_coeffs[idx + frac_pos]; idx += precision; i++; v += in[n - i] * filter_coeffs[idx - frac_pos]; } out[n] = av_clip_int16(v >> 15); } }
false
FFmpeg
2ad0d96a24879b96153a3fbbc1707372baa2615e
void ff_acelp_interpolate( int16_t* out, const int16_t* in, const int16_t* filter_coeffs, int precision, int frac_pos, int filter_length, int length) { int n, i; assert(pitch_delay_frac >= 0 && pitch_delay_frac < precision); for(n=0; n<length; n++) { int idx = 0; int v = 0x4000; for(i=0; i<filter_length;) { v += in[n + i] * filter_coeffs[idx + frac_pos]; idx += precision; i++; v += in[n - i] * filter_coeffs[idx - frac_pos]; } out[n] = av_clip_int16(v >> 15); } }
{ "code": [], "line_no": [] }
void FUNC_0( int16_t* VAR_0, const int16_t* VAR_1, const int16_t* VAR_2, int VAR_3, int VAR_4, int VAR_5, int VAR_6) { int VAR_7, VAR_8; assert(pitch_delay_frac >= 0 && pitch_delay_frac < VAR_3); for(VAR_7=0; VAR_7<VAR_6; VAR_7++) { int VAR_9 = 0; int VAR_10 = 0x4000; for(VAR_8=0; VAR_8<VAR_5;) { VAR_10 += VAR_1[VAR_7 + VAR_8] * VAR_2[VAR_9 + VAR_4]; VAR_9 += VAR_3; VAR_8++; VAR_10 += VAR_1[VAR_7 - VAR_8] * VAR_2[VAR_9 - VAR_4]; } VAR_0[VAR_7] = av_clip_int16(VAR_10 >> 15); } }
[ "void FUNC_0(\nint16_t* VAR_0,\nconst int16_t* VAR_1,\nconst int16_t* VAR_2,\nint VAR_3,\nint VAR_4,\nint VAR_5,\nint VAR_6)\n{", "int VAR_7, VAR_8;", "assert(pitch_delay_frac >= 0 && pitch_delay_frac < VAR_3);", "for(VAR_7=0; VAR_7<VAR_6; VAR_7++)", "{", "int VAR_9 = 0;", "int VAR_10 = 0x4000;", "for(VAR_8=0; VAR_8<VAR_5;)", "{", "VAR_10 += VAR_1[VAR_7 + VAR_8] * VAR_2[VAR_9 + VAR_4];", "VAR_9 += VAR_3;", "VAR_8++;", "VAR_10 += VAR_1[VAR_7 - VAR_8] * VAR_2[VAR_9 - VAR_4];", "}", "VAR_0[VAR_7] = av_clip_int16(VAR_10 >> 15);", "}", "}" ]
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16,837
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) { env->reserve = -1; /* Default MMU definitions */ env->nb_BATs = -1; env->nb_tlb = 0; env->nb_ways = 0; /* XXX: missing: * 32 bits PowerPC: * - MPC5xx(x) * - MPC8xx(x) * - RCPU (same as MPC5xx ?) */ spr_register(env, SPR_PVR, "PVR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, def->pvr); printf("%s: PVR %08x mask %08x => %08x\n", __func__, def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); switch (def->pvr) { /* Embedded PowerPC from IBM */ case CPU_PPC_401A1: /* 401 A1 family */ case CPU_PPC_401B2: /* 401 B2 family */ case CPU_PPC_401C2: /* 401 C2 family */ case CPU_PPC_401D2: /* 401 D2 family */ case CPU_PPC_401E2: /* 401 E2 family */ case CPU_PPC_401F2: /* 401 F2 family */ case CPU_PPC_401G2: /* 401 G2 family */ case CPU_PPC_IOP480: /* IOP 480 family */ case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); #if defined (TODO) /* XXX: optional ? */ gen_spr_compress(env); #endif env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; case CPU_PPC_403GA: /* 403 GA family */ case CPU_PPC_403GB: /* 403 GB family */ case CPU_PPC_403GC: /* 403 GC family */ case CPU_PPC_403GCX: /* 403 GCX family */ gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); gen_spr_403(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; case CPU_PPC_405CR: /* 405 GP/CR family */ case CPU_PPC_405EP: /* 405 EP family */ case CPU_PPC_405GPR: /* 405 GPR family */ case CPU_PPC_405D2: /* 405 D2 family */ case CPU_PPC_405D4: /* 405 D4 family */ gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* Allocate hardware IRQ controller */ ppc405_irq_init(env); break; case CPU_PPC_NPE405H: /* NPe405 H family */ case CPU_PPC_NPE405H2: case CPU_PPC_NPE405L: /* Npe405 L family */ gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* Allocate hardware IRQ controller */ ppc405_irq_init(env); break; #if defined (TODO) case CPU_PPC_STB01000: #endif #if defined (TODO) case CPU_PPC_STB01010: #endif #if defined (TODO) case CPU_PPC_STB0210: #endif case CPU_PPC_STB03: /* STB03 family */ #if defined (TODO) case CPU_PPC_STB043: /* STB043 family */ #endif #if defined (TODO) case CPU_PPC_STB045: /* STB045 family */ #endif case CPU_PPC_STB25: /* STB25 family */ #if defined (TODO) case CPU_PPC_STB130: /* STB130 family */ #endif gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* Allocate hardware IRQ controller */ ppc405_irq_init(env); break; case CPU_PPC_440EP: /* 440 EP family */ case CPU_PPC_440GP: /* 440 GP family */ case CPU_PPC_440GX: /* 440 GX family */ case CPU_PPC_440GXc: /* 440 GXc family */ case CPU_PPC_440GXf: /* 440 GXf family */ case CPU_PPC_440SP: /* 440 SP family */ case CPU_PPC_440SP2: case CPU_PPC_440SPE: /* 440 SPE family */ gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_BookE(env); gen_spr_440(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; /* Embedded PowerPC from Freescale */ #if defined (TODO) case CPU_PPC_5xx: break; #endif #if defined (TODO) case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ break; #endif #if defined (TODO) case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ break; #endif #if defined (TODO) case CPU_PPC_827x: /* MPC 827x / 828x */ break; #endif /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */ case CPU_PPC_e500v110: case CPU_PPC_e500v120: case CPU_PPC_e500v210: case CPU_PPC_e500v220: gen_spr_generic(env); /* Time base */ gen_tbl(env); gen_spr_BookE(env); gen_spr_BookE_FSL(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; #if defined (TODO) case CPU_PPC_e600: break; #endif /* 32 bits PowerPC */ case CPU_PPC_601: /* PowerPC 601 */ gen_spr_generic(env); gen_spr_ne_601(env); gen_spr_601(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_601_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_601_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ #if 0 /* ? */ spr_register(env, SPR_601_HID15, "HID15", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); #endif env->nb_tlb = 64; env->nb_ways = 2; env->id_tlbs = 0; env->id_tlbs = 0; /* XXX: TODO: allocate internal IRQ controller */ break; case CPU_PPC_602: /* PowerPC 602 */ gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_602(env); /* hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_603: /* PowerPC 603 */ case CPU_PPC_603E: /* PowerPC 603e */ case CPU_PPC_603E7v: case CPU_PPC_603E7v2: case CPU_PPC_603P: /* PowerPC 603p */ case CPU_PPC_603R: /* PowerPC 603r */ gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_603(env); /* hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_G2: /* PowerPC G2 family */ case CPU_PPC_G2H4: case CPU_PPC_G2gp: case CPU_PPC_G2ls: case CPU_PPC_G2LE: /* PowerPC G2LE family */ case CPU_PPC_G2LEgp: case CPU_PPC_G2LEls: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); /* Memory management */ gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_G2_755(env); gen_spr_G2(env); /* Hardware implementation register */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_604: /* PowerPC 604 */ case CPU_PPC_604E: /* PowerPC 604e */ case CPU_PPC_604R: /* PowerPC 604r */ gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_spr_604(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_74x: /* PowerPC 740 / 750 */ case CPU_PPC_740E: case CPU_PPC_750E: case CPU_PPC_74xP: /* PowerPC 740P / 750P */ case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ case CPU_PPC_750CXE22: case CPU_PPC_750CXE23: case CPU_PPC_750CXE24: case CPU_PPC_750CXE24b: case CPU_PPC_750CXE31: case CPU_PPC_750CXE31b: case CPU_PPC_750CXR: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_spr_7xx(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ case CPU_PPC_750FX20: case CPU_PPC_750FX21: case CPU_PPC_750FX22: case CPU_PPC_750FX23: case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ case CPU_PPC_750GX11: case CPU_PPC_750GX12: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ gen_high_BATs(env); /* Time base */ gen_tbl(env); gen_spr_7xx(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; case CPU_PPC_755_10: /* PowerPC 755 */ case CPU_PPC_755_11: case CPU_PPC_755_20: case CPU_PPC_755D: case CPU_PPC_755E: gen_spr_generic(env); gen_spr_ne_601(env); /* Memory management */ gen_low_BATs(env); /* Time base */ gen_tbl(env); /* Memory management */ gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_G2_755(env); /* L2 cache control */ /* XXX : not implemented */ spr_register(env, SPR_ICTC, "ICTC", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_L2PM, "L2PM", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc6xx_irq_init(env); break; #if defined (TODO) /* G4 family */ case CPU_PPC_7400: /* PowerPC 7400 */ case CPU_PPC_7410C: /* PowerPC 7410 */ case CPU_PPC_7410D: case CPU_PPC_7410E: case CPU_PPC_7441: /* PowerPC 7441 */ case CPU_PPC_7445: /* PowerPC 7445 */ case CPU_PPC_7447: /* PowerPC 7447 */ case CPU_PPC_7447A: /* PowerPC 7447A */ case CPU_PPC_7448: /* PowerPC 7448 */ case CPU_PPC_7450: /* PowerPC 7450 */ case CPU_PPC_7450b: case CPU_PPC_7451: /* PowerPC 7451 */ case CPU_PPC_7451G: case CPU_PPC_7455: /* PowerPC 7455 */ case CPU_PPC_7455F: case CPU_PPC_7455G: case CPU_PPC_7457: /* PowerPC 7457 */ case CPU_PPC_7457C: case CPU_PPC_7457A: /* PowerPC 7457A */ break; #endif /* 64 bits PowerPC */ #if defined (TARGET_PPC64) #if defined (TODO) case CPU_PPC_620: /* PowerPC 620 */ case CPU_PPC_630: /* PowerPC 630 (Power 3) */ case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ case CPU_PPC_POWER4: /* Power 4 */ case CPU_PPC_POWER4P: /* Power 4+ */ case CPU_PPC_POWER5: /* Power 5 */ case CPU_PPC_POWER5P: /* Power 5+ */ #endif break; case CPU_PPC_970: /* PowerPC 970 */ case CPU_PPC_970FX10: /* PowerPC 970 FX */ case CPU_PPC_970FX20: case CPU_PPC_970FX21: case CPU_PPC_970FX30: case CPU_PPC_970FX31: case CPU_PPC_970MP10: /* PowerPC 970 MP */ case CPU_PPC_970MP11: gen_spr_generic(env); gen_spr_ne_601(env); /* XXX: not correct */ gen_low_BATs(env); /* Time base */ gen_tbl(env); gen_spr_7xx(env); /* Hardware implementation registers */ /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* Allocate hardware IRQ controller */ ppc970_irq_init(env); break; #if defined (TODO) case CPU_PPC_CELL10: /* Cell family */ case CPU_PPC_CELL20: case CPU_PPC_CELL30: case CPU_PPC_CELL31: #endif break; #if defined (TODO) case CPU_PPC_RS64: /* Apache (RS64/A35) */ case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ #endif break; #endif /* defined (TARGET_PPC64) */ #if defined (TODO) /* POWER */ case CPU_POWER: /* POWER */ case CPU_POWER2: /* POWER2 */ break; #endif default: gen_spr_generic(env); /* XXX: TODO: allocate internal IRQ controller */ break; } if (env->nb_BATs == -1) env->nb_BATs = 4; /* Allocate TLBs buffer when needed */ if (env->nb_tlb != 0) { int nb_tlb = env->nb_tlb; if (env->id_tlbs != 0) nb_tlb *= 2; env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t)); /* Pre-compute some useful values */ env->tlb_per_way = env->nb_tlb / env->nb_ways; } }
false
qemu
2662a059aa2affddfbe42e78b11c802cf30a970f
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) { env->reserve = -1; env->nb_BATs = -1; env->nb_tlb = 0; env->nb_ways = 0; spr_register(env, SPR_PVR, "PVR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, def->pvr); printf("%s: PVR %08x mask %08x => %08x\n", __func__, def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); switch (def->pvr) { case CPU_PPC_401A1: case CPU_PPC_401B2: case CPU_PPC_401C2: case CPU_PPC_401D2: case CPU_PPC_401E2: case CPU_PPC_401F2: case CPU_PPC_401G2: case CPU_PPC_IOP480: case CPU_PPC_COBRA: gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); #if defined (TODO) gen_spr_compress(env); #endif env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; break; case CPU_PPC_403GA: case CPU_PPC_403GB: case CPU_PPC_403GC: case CPU_PPC_403GCX: gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); gen_spr_403(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; break; case CPU_PPC_405CR: case CPU_PPC_405EP: case CPU_PPC_405GPR: case CPU_PPC_405D2: case CPU_PPC_405D4: gen_spr_generic(env); gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; ppc405_irq_init(env); break; case CPU_PPC_NPE405H: case CPU_PPC_NPE405H2: case CPU_PPC_NPE405L: gen_spr_generic(env); gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; ppc405_irq_init(env); break; #if defined (TODO) case CPU_PPC_STB01000: #endif #if defined (TODO) case CPU_PPC_STB01010: #endif #if defined (TODO) case CPU_PPC_STB0210: #endif case CPU_PPC_STB03: #if defined (TODO) case CPU_PPC_STB043: #endif #if defined (TODO) case CPU_PPC_STB045: #endif case CPU_PPC_STB25: #if defined (TODO) case CPU_PPC_STB130: #endif gen_spr_generic(env); gen_tbl(env); gen_spr_40x(env); gen_spr_405(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; ppc405_irq_init(env); break; case CPU_PPC_440EP: case CPU_PPC_440GP: case CPU_PPC_440GX: case CPU_PPC_440GXc: case CPU_PPC_440GXf: case CPU_PPC_440SP: case CPU_PPC_440SP2: case CPU_PPC_440SPE: gen_spr_generic(env); gen_tbl(env); gen_spr_BookE(env); gen_spr_440(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; break; #if defined (TODO) case CPU_PPC_5xx: break; #endif #if defined (TODO) case CPU_PPC_8xx: break; #endif #if defined (TODO) case CPU_PPC_82xx_HIP3: case CPU_PPC_82xx_HIP4: break; #endif #if defined (TODO) case CPU_PPC_827x: break; #endif case CPU_PPC_e500v110: case CPU_PPC_e500v120: case CPU_PPC_e500v210: case CPU_PPC_e500v220: gen_spr_generic(env); gen_tbl(env); gen_spr_BookE(env); gen_spr_BookE_FSL(env); env->nb_BATs = 0; env->nb_tlb = 64; env->nb_ways = 1; env->id_tlbs = 0; break; #if defined (TODO) case CPU_PPC_e600: break; #endif case CPU_PPC_601: gen_spr_generic(env); gen_spr_ne_601(env); gen_spr_601(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_601_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_601_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); #if 0 spr_register(env, SPR_601_HID15, "HID15", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); #endif env->nb_tlb = 64; env->nb_ways = 2; env->id_tlbs = 0; env->id_tlbs = 0; break; case CPU_PPC_602: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_602(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; case CPU_PPC_603: case CPU_PPC_603E: case CPU_PPC_603E7v: case CPU_PPC_603E7v2: case CPU_PPC_603P: case CPU_PPC_603R: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_603(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; case CPU_PPC_G2: case CPU_PPC_G2H4: case CPU_PPC_G2gp: case CPU_PPC_G2ls: case CPU_PPC_G2LE: case CPU_PPC_G2LEgp: case CPU_PPC_G2LEls: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_G2_755(env); gen_spr_G2(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; case CPU_PPC_604: case CPU_PPC_604E: case CPU_PPC_604R: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_spr_604(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; case CPU_PPC_74x: case CPU_PPC_740E: case CPU_PPC_750E: case CPU_PPC_74xP: case CPU_PPC_750CXE21: case CPU_PPC_750CXE22: case CPU_PPC_750CXE23: case CPU_PPC_750CXE24: case CPU_PPC_750CXE24b: case CPU_PPC_750CXE31: case CPU_PPC_750CXE31b: case CPU_PPC_750CXR: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_spr_7xx(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; case CPU_PPC_750FX10: case CPU_PPC_750FX20: case CPU_PPC_750FX21: case CPU_PPC_750FX22: case CPU_PPC_750FX23: case CPU_PPC_750GX10: case CPU_PPC_750GX11: case CPU_PPC_750GX12: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_high_BATs(env); gen_tbl(env); gen_spr_7xx(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; case CPU_PPC_755_10: case CPU_PPC_755_11: case CPU_PPC_755_20: case CPU_PPC_755D: case CPU_PPC_755E: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); gen_spr_G2_755(env); spr_register(env, SPR_ICTC, "ICTC", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_L2PM, "L2PM", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(env); break; #if defined (TODO) case CPU_PPC_7400: case CPU_PPC_7410C: case CPU_PPC_7410D: case CPU_PPC_7410E: case CPU_PPC_7441: case CPU_PPC_7445: case CPU_PPC_7447: case CPU_PPC_7447A: case CPU_PPC_7448: case CPU_PPC_7450: case CPU_PPC_7450b: case CPU_PPC_7451: case CPU_PPC_7451G: case CPU_PPC_7455: case CPU_PPC_7455F: case CPU_PPC_7455G: case CPU_PPC_7457: case CPU_PPC_7457C: case CPU_PPC_7457A: break; #endif #if defined (TARGET_PPC64) #if defined (TODO) case CPU_PPC_620: case CPU_PPC_630: case CPU_PPC_631: case CPU_PPC_POWER4: case CPU_PPC_POWER4P: case CPU_PPC_POWER5: case CPU_PPC_POWER5P: #endif break; case CPU_PPC_970: case CPU_PPC_970FX10: case CPU_PPC_970FX20: case CPU_PPC_970FX21: case CPU_PPC_970FX30: case CPU_PPC_970FX31: case CPU_PPC_970MP10: case CPU_PPC_970MP11: gen_spr_generic(env); gen_spr_ne_601(env); gen_low_BATs(env); gen_tbl(env); gen_spr_7xx(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(env, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc970_irq_init(env); break; #if defined (TODO) case CPU_PPC_CELL10: case CPU_PPC_CELL20: case CPU_PPC_CELL30: case CPU_PPC_CELL31: #endif break; #if defined (TODO) case CPU_PPC_RS64: case CPU_PPC_RS64II: case CPU_PPC_RS64III: case CPU_PPC_RS64IV: #endif break; #endif #if defined (TODO) case CPU_POWER: case CPU_POWER2: break; #endif default: gen_spr_generic(env); break; } if (env->nb_BATs == -1) env->nb_BATs = 4; if (env->nb_tlb != 0) { int nb_tlb = env->nb_tlb; if (env->id_tlbs != 0) nb_tlb *= 2; env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t)); env->tlb_per_way = env->nb_tlb / env->nb_ways; } }
{ "code": [], "line_no": [] }
static void FUNC_0 (CPUPPCState *VAR_0, ppc_def_t *VAR_1) { VAR_0->reserve = -1; VAR_0->nb_BATs = -1; VAR_0->VAR_2 = 0; VAR_0->nb_ways = 0; spr_register(VAR_0, SPR_PVR, "PVR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, VAR_1->pvr); printf("%s: PVR %08x mask %08x => %08x\n", __func__, VAR_1->pvr, VAR_1->pvr_mask, VAR_1->pvr & VAR_1->pvr_mask); switch (VAR_1->pvr) { case CPU_PPC_401A1: case CPU_PPC_401B2: case CPU_PPC_401C2: case CPU_PPC_401D2: case CPU_PPC_401E2: case CPU_PPC_401F2: case CPU_PPC_401G2: case CPU_PPC_IOP480: case CPU_PPC_COBRA: gen_spr_generic(VAR_0); gen_spr_40x(VAR_0); gen_spr_401_403(VAR_0); #if defined (TODO) gen_spr_compress(VAR_0); #endif VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; break; case CPU_PPC_403GA: case CPU_PPC_403GB: case CPU_PPC_403GC: case CPU_PPC_403GCX: gen_spr_generic(VAR_0); gen_spr_40x(VAR_0); gen_spr_401_403(VAR_0); gen_spr_403(VAR_0); VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; break; case CPU_PPC_405CR: case CPU_PPC_405EP: case CPU_PPC_405GPR: case CPU_PPC_405D2: case CPU_PPC_405D4: gen_spr_generic(VAR_0); gen_tbl(VAR_0); gen_spr_40x(VAR_0); gen_spr_405(VAR_0); VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; ppc405_irq_init(VAR_0); break; case CPU_PPC_NPE405H: case CPU_PPC_NPE405H2: case CPU_PPC_NPE405L: gen_spr_generic(VAR_0); gen_tbl(VAR_0); gen_spr_40x(VAR_0); gen_spr_405(VAR_0); VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; ppc405_irq_init(VAR_0); break; #if defined (TODO) case CPU_PPC_STB01000: #endif #if defined (TODO) case CPU_PPC_STB01010: #endif #if defined (TODO) case CPU_PPC_STB0210: #endif case CPU_PPC_STB03: #if defined (TODO) case CPU_PPC_STB043: #endif #if defined (TODO) case CPU_PPC_STB045: #endif case CPU_PPC_STB25: #if defined (TODO) case CPU_PPC_STB130: #endif gen_spr_generic(VAR_0); gen_tbl(VAR_0); gen_spr_40x(VAR_0); gen_spr_405(VAR_0); VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; ppc405_irq_init(VAR_0); break; case CPU_PPC_440EP: case CPU_PPC_440GP: case CPU_PPC_440GX: case CPU_PPC_440GXc: case CPU_PPC_440GXf: case CPU_PPC_440SP: case CPU_PPC_440SP2: case CPU_PPC_440SPE: gen_spr_generic(VAR_0); gen_tbl(VAR_0); gen_spr_BookE(VAR_0); gen_spr_440(VAR_0); VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; break; #if defined (TODO) case CPU_PPC_5xx: break; #endif #if defined (TODO) case CPU_PPC_8xx: break; #endif #if defined (TODO) case CPU_PPC_82xx_HIP3: case CPU_PPC_82xx_HIP4: break; #endif #if defined (TODO) case CPU_PPC_827x: break; #endif case CPU_PPC_e500v110: case CPU_PPC_e500v120: case CPU_PPC_e500v210: case CPU_PPC_e500v220: gen_spr_generic(VAR_0); gen_tbl(VAR_0); gen_spr_BookE(VAR_0); gen_spr_BookE_FSL(VAR_0); VAR_0->nb_BATs = 0; VAR_0->VAR_2 = 64; VAR_0->nb_ways = 1; VAR_0->id_tlbs = 0; break; #if defined (TODO) case CPU_PPC_e600: break; #endif case CPU_PPC_601: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_spr_601(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_601_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_601_HID5, "HID5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); #if 0 spr_register(VAR_0, SPR_601_HID15, "HID15", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); #endif VAR_0->VAR_2 = 64; VAR_0->nb_ways = 2; VAR_0->id_tlbs = 0; VAR_0->id_tlbs = 0; break; case CPU_PPC_602: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_6xx_7xx_soft_tlb(VAR_0, 64, 2); gen_spr_602(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; case CPU_PPC_603: case CPU_PPC_603E: case CPU_PPC_603E7v: case CPU_PPC_603E7v2: case CPU_PPC_603P: case CPU_PPC_603R: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_6xx_7xx_soft_tlb(VAR_0, 64, 2); gen_spr_603(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; case CPU_PPC_G2: case CPU_PPC_G2H4: case CPU_PPC_G2gp: case CPU_PPC_G2ls: case CPU_PPC_G2LE: case CPU_PPC_G2LEgp: case CPU_PPC_G2LEls: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_high_BATs(VAR_0); gen_6xx_7xx_soft_tlb(VAR_0, 64, 2); gen_spr_G2_755(VAR_0); gen_spr_G2(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; case CPU_PPC_604: case CPU_PPC_604E: case CPU_PPC_604R: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_spr_604(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; case CPU_PPC_74x: case CPU_PPC_740E: case CPU_PPC_750E: case CPU_PPC_74xP: case CPU_PPC_750CXE21: case CPU_PPC_750CXE22: case CPU_PPC_750CXE23: case CPU_PPC_750CXE24: case CPU_PPC_750CXE24b: case CPU_PPC_750CXE31: case CPU_PPC_750CXE31b: case CPU_PPC_750CXR: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_spr_7xx(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; case CPU_PPC_750FX10: case CPU_PPC_750FX20: case CPU_PPC_750FX21: case CPU_PPC_750FX22: case CPU_PPC_750FX23: case CPU_PPC_750GX10: case CPU_PPC_750GX11: case CPU_PPC_750GX12: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_high_BATs(VAR_0); gen_tbl(VAR_0); gen_spr_7xx(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; case CPU_PPC_755_10: case CPU_PPC_755_11: case CPU_PPC_755_20: case CPU_PPC_755D: case CPU_PPC_755E: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_high_BATs(VAR_0); gen_6xx_7xx_soft_tlb(VAR_0, 64, 2); gen_spr_G2_755(VAR_0); spr_register(VAR_0, SPR_ICTC, "ICTC", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_L2PM, "L2PM", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc6xx_irq_init(VAR_0); break; #if defined (TODO) case CPU_PPC_7400: case CPU_PPC_7410C: case CPU_PPC_7410D: case CPU_PPC_7410E: case CPU_PPC_7441: case CPU_PPC_7445: case CPU_PPC_7447: case CPU_PPC_7447A: case CPU_PPC_7448: case CPU_PPC_7450: case CPU_PPC_7450b: case CPU_PPC_7451: case CPU_PPC_7451G: case CPU_PPC_7455: case CPU_PPC_7455F: case CPU_PPC_7455G: case CPU_PPC_7457: case CPU_PPC_7457C: case CPU_PPC_7457A: break; #endif #if defined (TARGET_PPC64) #if defined (TODO) case CPU_PPC_620: case CPU_PPC_630: case CPU_PPC_631: case CPU_PPC_POWER4: case CPU_PPC_POWER4P: case CPU_PPC_POWER5: case CPU_PPC_POWER5P: #endif break; case CPU_PPC_970: case CPU_PPC_970FX10: case CPU_PPC_970FX20: case CPU_PPC_970FX21: case CPU_PPC_970FX30: case CPU_PPC_970FX31: case CPU_PPC_970MP10: case CPU_PPC_970MP11: gen_spr_generic(VAR_0); gen_spr_ne_601(VAR_0); gen_low_BATs(VAR_0); gen_tbl(VAR_0); gen_spr_7xx(VAR_0); spr_register(VAR_0, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_HID1, "HID1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); spr_register(VAR_0, SPR_750_HID2, "HID2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); ppc970_irq_init(VAR_0); break; #if defined (TODO) case CPU_PPC_CELL10: case CPU_PPC_CELL20: case CPU_PPC_CELL30: case CPU_PPC_CELL31: #endif break; #if defined (TODO) case CPU_PPC_RS64: case CPU_PPC_RS64II: case CPU_PPC_RS64III: case CPU_PPC_RS64IV: #endif break; #endif #if defined (TODO) case CPU_POWER: case CPU_POWER2: break; #endif default: gen_spr_generic(VAR_0); break; } if (VAR_0->nb_BATs == -1) VAR_0->nb_BATs = 4; if (VAR_0->VAR_2 != 0) { int VAR_2 = VAR_0->VAR_2; if (VAR_0->id_tlbs != 0) VAR_2 *= 2; VAR_0->tlb = qemu_mallocz(VAR_2 * sizeof(ppc_tlb_t)); VAR_0->tlb_per_way = VAR_0->VAR_2 / VAR_0->nb_ways; } }
[ "static void FUNC_0 (CPUPPCState *VAR_0, ppc_def_t *VAR_1)\n{", "VAR_0->reserve = -1;", "VAR_0->nb_BATs = -1;", "VAR_0->VAR_2 = 0;", "VAR_0->nb_ways = 0;", "spr_register(VAR_0, SPR_PVR, \"PVR\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, SPR_NOACCESS,\nVAR_1->pvr);", "printf(\"%s: PVR %08x mask %08x => %08x\\n\", __func__,\nVAR_1->pvr, VAR_1->pvr_mask, VAR_1->pvr & VAR_1->pvr_mask);", "switch (VAR_1->pvr) {", "case CPU_PPC_401A1:\ncase CPU_PPC_401B2:\ncase CPU_PPC_401C2:\ncase CPU_PPC_401D2:\ncase CPU_PPC_401E2:\ncase CPU_PPC_401F2:\ncase CPU_PPC_401G2:\ncase CPU_PPC_IOP480:\ncase CPU_PPC_COBRA:\ngen_spr_generic(VAR_0);", "gen_spr_40x(VAR_0);", "gen_spr_401_403(VAR_0);", "#if defined (TODO)\ngen_spr_compress(VAR_0);", "#endif\nVAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "break;", "case CPU_PPC_403GA:\ncase CPU_PPC_403GB:\ncase CPU_PPC_403GC:\ncase CPU_PPC_403GCX:\ngen_spr_generic(VAR_0);", "gen_spr_40x(VAR_0);", "gen_spr_401_403(VAR_0);", "gen_spr_403(VAR_0);", "VAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "break;", "case CPU_PPC_405CR:\ncase CPU_PPC_405EP:\ncase CPU_PPC_405GPR:\ncase CPU_PPC_405D2:\ncase CPU_PPC_405D4:\ngen_spr_generic(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_40x(VAR_0);", "gen_spr_405(VAR_0);", "VAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "ppc405_irq_init(VAR_0);", "break;", "case CPU_PPC_NPE405H:\ncase CPU_PPC_NPE405H2:\ncase CPU_PPC_NPE405L:\ngen_spr_generic(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_40x(VAR_0);", "gen_spr_405(VAR_0);", "VAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "ppc405_irq_init(VAR_0);", "break;", "#if defined (TODO)\ncase CPU_PPC_STB01000:\n#endif\n#if defined (TODO)\ncase CPU_PPC_STB01010:\n#endif\n#if defined (TODO)\ncase CPU_PPC_STB0210:\n#endif\ncase CPU_PPC_STB03:\n#if defined (TODO)\ncase CPU_PPC_STB043:\n#endif\n#if defined (TODO)\ncase CPU_PPC_STB045:\n#endif\ncase CPU_PPC_STB25:\n#if defined (TODO)\ncase CPU_PPC_STB130:\n#endif\ngen_spr_generic(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_40x(VAR_0);", "gen_spr_405(VAR_0);", "VAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "ppc405_irq_init(VAR_0);", "break;", "case CPU_PPC_440EP:\ncase CPU_PPC_440GP:\ncase CPU_PPC_440GX:\ncase CPU_PPC_440GXc:\ncase CPU_PPC_440GXf:\ncase CPU_PPC_440SP:\ncase CPU_PPC_440SP2:\ncase CPU_PPC_440SPE:\ngen_spr_generic(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_BookE(VAR_0);", "gen_spr_440(VAR_0);", "VAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "break;", "#if defined (TODO)\ncase CPU_PPC_5xx:\nbreak;", "#endif\n#if defined (TODO)\ncase CPU_PPC_8xx:\nbreak;", "#endif\n#if defined (TODO)\ncase CPU_PPC_82xx_HIP3:\ncase CPU_PPC_82xx_HIP4:\nbreak;", "#endif\n#if defined (TODO)\ncase CPU_PPC_827x:\nbreak;", "#endif\ncase CPU_PPC_e500v110:\ncase CPU_PPC_e500v120:\ncase CPU_PPC_e500v210:\ncase CPU_PPC_e500v220:\ngen_spr_generic(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_BookE(VAR_0);", "gen_spr_BookE_FSL(VAR_0);", "VAR_0->nb_BATs = 0;", "VAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 1;", "VAR_0->id_tlbs = 0;", "break;", "#if defined (TODO)\ncase CPU_PPC_e600:\nbreak;", "#endif\ncase CPU_PPC_601:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_spr_601(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_601_HID2, \"HID2\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_601_HID5, \"HID5\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "#if 0\nspr_register(VAR_0, SPR_601_HID15, \"HID15\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "#endif\nVAR_0->VAR_2 = 64;", "VAR_0->nb_ways = 2;", "VAR_0->id_tlbs = 0;", "VAR_0->id_tlbs = 0;", "break;", "case CPU_PPC_602:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_6xx_7xx_soft_tlb(VAR_0, 64, 2);", "gen_spr_602(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "case CPU_PPC_603:\ncase CPU_PPC_603E:\ncase CPU_PPC_603E7v:\ncase CPU_PPC_603E7v2:\ncase CPU_PPC_603P:\ncase CPU_PPC_603R:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_6xx_7xx_soft_tlb(VAR_0, 64, 2);", "gen_spr_603(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "case CPU_PPC_G2:\ncase CPU_PPC_G2H4:\ncase CPU_PPC_G2gp:\ncase CPU_PPC_G2ls:\ncase CPU_PPC_G2LE:\ncase CPU_PPC_G2LEgp:\ncase CPU_PPC_G2LEls:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_high_BATs(VAR_0);", "gen_6xx_7xx_soft_tlb(VAR_0, 64, 2);", "gen_spr_G2_755(VAR_0);", "gen_spr_G2(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID2, \"HID2\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "case CPU_PPC_604:\ncase CPU_PPC_604E:\ncase CPU_PPC_604R:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_604(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "case CPU_PPC_74x:\ncase CPU_PPC_740E:\ncase CPU_PPC_750E:\ncase CPU_PPC_74xP:\ncase CPU_PPC_750CXE21:\ncase CPU_PPC_750CXE22:\ncase CPU_PPC_750CXE23:\ncase CPU_PPC_750CXE24:\ncase CPU_PPC_750CXE24b:\ncase CPU_PPC_750CXE31:\ncase CPU_PPC_750CXE31b:\ncase CPU_PPC_750CXR:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_7xx(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "case CPU_PPC_750FX10:\ncase CPU_PPC_750FX20:\ncase CPU_PPC_750FX21:\ncase CPU_PPC_750FX22:\ncase CPU_PPC_750FX23:\ncase CPU_PPC_750GX10:\ncase CPU_PPC_750GX11:\ncase CPU_PPC_750GX12:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_high_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_7xx(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_750_HID2, \"HID2\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "case CPU_PPC_755_10:\ncase CPU_PPC_755_11:\ncase CPU_PPC_755_20:\ncase CPU_PPC_755D:\ncase CPU_PPC_755E:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_high_BATs(VAR_0);", "gen_6xx_7xx_soft_tlb(VAR_0, 64, 2);", "gen_spr_G2_755(VAR_0);", "spr_register(VAR_0, SPR_ICTC, \"ICTC\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_L2PM, \"L2PM\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID2, \"HID2\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc6xx_irq_init(VAR_0);", "break;", "#if defined (TODO)\ncase CPU_PPC_7400:\ncase CPU_PPC_7410C:\ncase CPU_PPC_7410D:\ncase CPU_PPC_7410E:\ncase CPU_PPC_7441:\ncase CPU_PPC_7445:\ncase CPU_PPC_7447:\ncase CPU_PPC_7447A:\ncase CPU_PPC_7448:\ncase CPU_PPC_7450:\ncase CPU_PPC_7450b:\ncase CPU_PPC_7451:\ncase CPU_PPC_7451G:\ncase CPU_PPC_7455:\ncase CPU_PPC_7455F:\ncase CPU_PPC_7455G:\ncase CPU_PPC_7457:\ncase CPU_PPC_7457C:\ncase CPU_PPC_7457A:\nbreak;", "#endif\n#if defined (TARGET_PPC64)\n#if defined (TODO)\ncase CPU_PPC_620:\ncase CPU_PPC_630:\ncase CPU_PPC_631:\ncase CPU_PPC_POWER4:\ncase CPU_PPC_POWER4P:\ncase CPU_PPC_POWER5:\ncase CPU_PPC_POWER5P:\n#endif\nbreak;", "case CPU_PPC_970:\ncase CPU_PPC_970FX10:\ncase CPU_PPC_970FX20:\ncase CPU_PPC_970FX21:\ncase CPU_PPC_970FX30:\ncase CPU_PPC_970FX31:\ncase CPU_PPC_970MP10:\ncase CPU_PPC_970MP11:\ngen_spr_generic(VAR_0);", "gen_spr_ne_601(VAR_0);", "gen_low_BATs(VAR_0);", "gen_tbl(VAR_0);", "gen_spr_7xx(VAR_0);", "spr_register(VAR_0, SPR_HID0, \"HID0\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_HID1, \"HID1\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "spr_register(VAR_0, SPR_750_HID2, \"HID2\",\nSPR_NOACCESS, SPR_NOACCESS,\n&spr_read_generic, &spr_write_generic,\n0x00000000);", "ppc970_irq_init(VAR_0);", "break;", "#if defined (TODO)\ncase CPU_PPC_CELL10:\ncase CPU_PPC_CELL20:\ncase CPU_PPC_CELL30:\ncase CPU_PPC_CELL31:\n#endif\nbreak;", "#if defined (TODO)\ncase CPU_PPC_RS64:\ncase CPU_PPC_RS64II:\ncase CPU_PPC_RS64III:\ncase CPU_PPC_RS64IV:\n#endif\nbreak;", "#endif\n#if defined (TODO)\ncase CPU_POWER:\ncase CPU_POWER2:\nbreak;", "#endif\ndefault:\ngen_spr_generic(VAR_0);", "break;", "}", "if (VAR_0->nb_BATs == -1)\nVAR_0->nb_BATs = 4;", "if (VAR_0->VAR_2 != 0) {", "int VAR_2 = VAR_0->VAR_2;", "if (VAR_0->id_tlbs != 0)\nVAR_2 *= 2;", "VAR_0->tlb = qemu_mallocz(VAR_2 * sizeof(ppc_tlb_t));", "VAR_0->tlb_per_way = VAR_0->VAR_2 / VAR_0->nb_ways;", "}", "}" ]
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16,838
static void nop(DBDMA_channel *ch) { dbdma_cmd *current = &ch->current; if (conditional_wait(ch)) goto wait; current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); dbdma_cmdptr_save(ch); conditional_interrupt(ch); conditional_branch(ch); wait: qemu_bh_schedule(dbdma_bh); }
false
qemu
ad674e53b5cce265fadafbde2c6a4f190345cd00
static void nop(DBDMA_channel *ch) { dbdma_cmd *current = &ch->current; if (conditional_wait(ch)) goto wait; current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); dbdma_cmdptr_save(ch); conditional_interrupt(ch); conditional_branch(ch); wait: qemu_bh_schedule(dbdma_bh); }
{ "code": [], "line_no": [] }
static void FUNC_0(DBDMA_channel *VAR_0) { dbdma_cmd *current = &VAR_0->current; if (conditional_wait(VAR_0)) goto wait; current->xfer_status = cpu_to_le16(be32_to_cpu(VAR_0->regs[DBDMA_STATUS])); dbdma_cmdptr_save(VAR_0); conditional_interrupt(VAR_0); conditional_branch(VAR_0); wait: qemu_bh_schedule(dbdma_bh); }
[ "static void FUNC_0(DBDMA_channel *VAR_0)\n{", "dbdma_cmd *current = &VAR_0->current;", "if (conditional_wait(VAR_0))\ngoto wait;", "current->xfer_status = cpu_to_le16(be32_to_cpu(VAR_0->regs[DBDMA_STATUS]));", "dbdma_cmdptr_save(VAR_0);", "conditional_interrupt(VAR_0);", "conditional_branch(VAR_0);", "wait:\nqemu_bh_schedule(dbdma_bh);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9, 11 ], [ 15 ], [ 17 ], [ 21 ], [ 23 ], [ 27, 29 ], [ 31 ] ]
16,839
static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle) { unsigned opc = get_Opcode_Y1(bundle); unsigned ext = get_RRROpcodeExtension_Y1(bundle); unsigned dest = get_Dest_Y1(bundle); unsigned srca = get_SrcA_Y1(bundle); unsigned srcb; int imm; switch (get_Opcode_Y1(bundle)) { case RRR_1_OPCODE_Y1: if (ext == UNARY_RRR_1_OPCODE_Y0) { ext = get_UnaryOpcodeExtension_Y1(bundle); return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca); } /* fallthru */ case RRR_0_OPCODE_Y1: case RRR_2_OPCODE_Y1: case RRR_3_OPCODE_Y1: case RRR_4_OPCODE_Y1: case RRR_5_OPCODE_Y1: case RRR_6_OPCODE_Y1: case RRR_7_OPCODE_Y1: srcb = get_SrcB_Y1(bundle); return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb); case SHIFT_OPCODE_Y1: ext = get_ShiftOpcodeExtension_Y1(bundle); imm = get_ShAmt_Y1(bundle); return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm); case ADDI_OPCODE_Y1: case ADDXI_OPCODE_Y1: case ANDI_OPCODE_Y1: case CMPEQI_OPCODE_Y1: case CMPLTSI_OPCODE_Y1: imm = (int8_t)get_Imm8_Y1(bundle); return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm); default: return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; } }
false
qemu
dd8070d865ad1b32876931f812a80645f97112ff
static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle) { unsigned opc = get_Opcode_Y1(bundle); unsigned ext = get_RRROpcodeExtension_Y1(bundle); unsigned dest = get_Dest_Y1(bundle); unsigned srca = get_SrcA_Y1(bundle); unsigned srcb; int imm; switch (get_Opcode_Y1(bundle)) { case RRR_1_OPCODE_Y1: if (ext == UNARY_RRR_1_OPCODE_Y0) { ext = get_UnaryOpcodeExtension_Y1(bundle); return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca); } case RRR_0_OPCODE_Y1: case RRR_2_OPCODE_Y1: case RRR_3_OPCODE_Y1: case RRR_4_OPCODE_Y1: case RRR_5_OPCODE_Y1: case RRR_6_OPCODE_Y1: case RRR_7_OPCODE_Y1: srcb = get_SrcB_Y1(bundle); return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb); case SHIFT_OPCODE_Y1: ext = get_ShiftOpcodeExtension_Y1(bundle); imm = get_ShAmt_Y1(bundle); return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm); case ADDI_OPCODE_Y1: case ADDXI_OPCODE_Y1: case ANDI_OPCODE_Y1: case CMPEQI_OPCODE_Y1: case CMPLTSI_OPCODE_Y1: imm = (int8_t)get_Imm8_Y1(bundle); return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm); default: return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; } }
{ "code": [], "line_no": [] }
static TileExcp FUNC_0(DisasContext *dc, tilegx_bundle_bits bundle) { unsigned VAR_0 = get_Opcode_Y1(bundle); unsigned VAR_1 = get_RRROpcodeExtension_Y1(bundle); unsigned VAR_2 = get_Dest_Y1(bundle); unsigned VAR_3 = get_SrcA_Y1(bundle); unsigned VAR_4; int VAR_5; switch (get_Opcode_Y1(bundle)) { case RRR_1_OPCODE_Y1: if (VAR_1 == UNARY_RRR_1_OPCODE_Y0) { VAR_1 = get_UnaryOpcodeExtension_Y1(bundle); return gen_rr_opcode(dc, OE(VAR_0, VAR_1, Y1), VAR_2, VAR_3); } case RRR_0_OPCODE_Y1: case RRR_2_OPCODE_Y1: case RRR_3_OPCODE_Y1: case RRR_4_OPCODE_Y1: case RRR_5_OPCODE_Y1: case RRR_6_OPCODE_Y1: case RRR_7_OPCODE_Y1: VAR_4 = get_SrcB_Y1(bundle); return gen_rrr_opcode(dc, OE(VAR_0, VAR_1, Y1), VAR_2, VAR_3, VAR_4); case SHIFT_OPCODE_Y1: VAR_1 = get_ShiftOpcodeExtension_Y1(bundle); VAR_5 = get_ShAmt_Y1(bundle); return gen_rri_opcode(dc, OE(VAR_0, VAR_1, Y1), VAR_2, VAR_3, VAR_5); case ADDI_OPCODE_Y1: case ADDXI_OPCODE_Y1: case ANDI_OPCODE_Y1: case CMPEQI_OPCODE_Y1: case CMPLTSI_OPCODE_Y1: VAR_5 = (int8_t)get_Imm8_Y1(bundle); return gen_rri_opcode(dc, OE(VAR_0, 0, Y1), VAR_2, VAR_3, VAR_5); default: return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; } }
[ "static TileExcp FUNC_0(DisasContext *dc, tilegx_bundle_bits bundle)\n{", "unsigned VAR_0 = get_Opcode_Y1(bundle);", "unsigned VAR_1 = get_RRROpcodeExtension_Y1(bundle);", "unsigned VAR_2 = get_Dest_Y1(bundle);", "unsigned VAR_3 = get_SrcA_Y1(bundle);", "unsigned VAR_4;", "int VAR_5;", "switch (get_Opcode_Y1(bundle)) {", "case RRR_1_OPCODE_Y1:\nif (VAR_1 == UNARY_RRR_1_OPCODE_Y0) {", "VAR_1 = get_UnaryOpcodeExtension_Y1(bundle);", "return gen_rr_opcode(dc, OE(VAR_0, VAR_1, Y1), VAR_2, VAR_3);", "}", "case RRR_0_OPCODE_Y1:\ncase RRR_2_OPCODE_Y1:\ncase RRR_3_OPCODE_Y1:\ncase RRR_4_OPCODE_Y1:\ncase RRR_5_OPCODE_Y1:\ncase RRR_6_OPCODE_Y1:\ncase RRR_7_OPCODE_Y1:\nVAR_4 = get_SrcB_Y1(bundle);", "return gen_rrr_opcode(dc, OE(VAR_0, VAR_1, Y1), VAR_2, VAR_3, VAR_4);", "case SHIFT_OPCODE_Y1:\nVAR_1 = get_ShiftOpcodeExtension_Y1(bundle);", "VAR_5 = get_ShAmt_Y1(bundle);", "return gen_rri_opcode(dc, OE(VAR_0, VAR_1, Y1), VAR_2, VAR_3, VAR_5);", "case ADDI_OPCODE_Y1:\ncase ADDXI_OPCODE_Y1:\ncase ANDI_OPCODE_Y1:\ncase CMPEQI_OPCODE_Y1:\ncase CMPLTSI_OPCODE_Y1:\nVAR_5 = (int8_t)get_Imm8_Y1(bundle);", "return gen_rri_opcode(dc, OE(VAR_0, 0, Y1), VAR_2, VAR_3, VAR_5);", "default:\nreturn TILEGX_EXCP_OPCODE_UNIMPLEMENTED;", "}", "}" ]
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16,840
static void versatile_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, int board_id) { CPUState *env; ram_addr_t ram_offset; qemu_irq *cpu_pic; qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev; PCIBus *pci_bus; NICInfo *nd; int n; int done_smc = 0; if (!cpu_model) cpu_model = "arm926"; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } ram_offset = qemu_ram_alloc(ram_size); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); arm_sysctl_init(0x10000000, 0x41007004); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_varargs("pl190", 0x10140000, cpu_pic[0], cpu_pic[1], NULL); for (n = 0; n < 32; n++) { pic[n] = qdev_get_gpio_in(dev, n); } dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); for (n = 0; n < 32; n++) { sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]); sic[n] = qdev_get_gpio_in(dev, n); } sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); dev = sysbus_create_varargs("versatile_pci", 0x40000000, sic[27], sic[28], sic[29], sic[30], NULL); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); /* The Versatile PCI bridge does not provide access to PCI IO space, so many of the qemu PCI devices are not useable. */ for(n = 0; n < nb_nics; n++) { nd = &nd_table[n]; if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) { smc91c111_init(nd, 0x10010000, sic[25]); done_smc = 1; } else { pci_nic_init_nofail(nd, "rtl8139", NULL); } } if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } n = drive_get_max_bus(IF_SCSI); while (n >= 0) { pci_create_simple(pci_bus, -1, "lsi53c895a"); n--; } sysbus_create_simple("pl011", 0x101f1000, pic[12]); sysbus_create_simple("pl011", 0x101f2000, pic[13]); sysbus_create_simple("pl011", 0x101f3000, pic[14]); sysbus_create_simple("pl011", 0x10009000, sic[6]); sysbus_create_simple("pl080", 0x10130000, pic[17]); sysbus_create_simple("sp804", 0x101e2000, pic[4]); sysbus_create_simple("sp804", 0x101e3000, pic[5]); /* The versatile/PB actually has a modified Color LCD controller that includes hardware cursor support from the PL111. */ sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); /* Add PL031 Real Time Clock. */ sysbus_create_simple("pl031", 0x101e8000, pic[10]); /* Memory map for Versatile/PB: */ /* 0x10000000 System registers. */ /* 0x10001000 PCI controller config registers. */ /* 0x10002000 Serial bus interface. */ /* 0x10003000 Secondary interrupt controller. */ /* 0x10004000 AACI (audio). */ /* 0x10005000 MMCI0. */ /* 0x10006000 KMI0 (keyboard). */ /* 0x10007000 KMI1 (mouse). */ /* 0x10008000 Character LCD Interface. */ /* 0x10009000 UART3. */ /* 0x1000a000 Smart card 1. */ /* 0x1000b000 MMCI1. */ /* 0x10010000 Ethernet. */ /* 0x10020000 USB. */ /* 0x10100000 SSMC. */ /* 0x10110000 MPMC. */ /* 0x10120000 CLCD Controller. */ /* 0x10130000 DMA Controller. */ /* 0x10140000 Vectored interrupt controller. */ /* 0x101d0000 AHB Monitor Interface. */ /* 0x101e0000 System Controller. */ /* 0x101e1000 Watchdog Interface. */ /* 0x101e2000 Timer 0/1. */ /* 0x101e3000 Timer 2/3. */ /* 0x101e4000 GPIO port 0. */ /* 0x101e5000 GPIO port 1. */ /* 0x101e6000 GPIO port 2. */ /* 0x101e7000 GPIO port 3. */ /* 0x101e8000 RTC. */ /* 0x101f0000 Smart card 0. */ /* 0x101f1000 UART0. */ /* 0x101f2000 UART1. */ /* 0x101f3000 UART2. */ /* 0x101f4000 SSPI. */ versatile_binfo.ram_size = ram_size; versatile_binfo.kernel_filename = kernel_filename; versatile_binfo.kernel_cmdline = kernel_cmdline; versatile_binfo.initrd_filename = initrd_filename; versatile_binfo.board_id = board_id; arm_load_kernel(env, &versatile_binfo); }
false
qemu
26e92f65525ef4446a500d85e185cf78835922aa
static void versatile_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, int board_id) { CPUState *env; ram_addr_t ram_offset; qemu_irq *cpu_pic; qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev; PCIBus *pci_bus; NICInfo *nd; int n; int done_smc = 0; if (!cpu_model) cpu_model = "arm926"; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } ram_offset = qemu_ram_alloc(ram_size); cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); arm_sysctl_init(0x10000000, 0x41007004); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_varargs("pl190", 0x10140000, cpu_pic[0], cpu_pic[1], NULL); for (n = 0; n < 32; n++) { pic[n] = qdev_get_gpio_in(dev, n); } dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); for (n = 0; n < 32; n++) { sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]); sic[n] = qdev_get_gpio_in(dev, n); } sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); dev = sysbus_create_varargs("versatile_pci", 0x40000000, sic[27], sic[28], sic[29], sic[30], NULL); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); for(n = 0; n < nb_nics; n++) { nd = &nd_table[n]; if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) { smc91c111_init(nd, 0x10010000, sic[25]); done_smc = 1; } else { pci_nic_init_nofail(nd, "rtl8139", NULL); } } if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } n = drive_get_max_bus(IF_SCSI); while (n >= 0) { pci_create_simple(pci_bus, -1, "lsi53c895a"); n--; } sysbus_create_simple("pl011", 0x101f1000, pic[12]); sysbus_create_simple("pl011", 0x101f2000, pic[13]); sysbus_create_simple("pl011", 0x101f3000, pic[14]); sysbus_create_simple("pl011", 0x10009000, sic[6]); sysbus_create_simple("pl080", 0x10130000, pic[17]); sysbus_create_simple("sp804", 0x101e2000, pic[4]); sysbus_create_simple("sp804", 0x101e3000, pic[5]); sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); sysbus_create_simple("pl031", 0x101e8000, pic[10]); versatile_binfo.ram_size = ram_size; versatile_binfo.kernel_filename = kernel_filename; versatile_binfo.kernel_cmdline = kernel_cmdline; versatile_binfo.initrd_filename = initrd_filename; versatile_binfo.board_id = board_id; arm_load_kernel(env, &versatile_binfo); }
{ "code": [], "line_no": [] }
static void FUNC_0(ram_addr_t VAR_0, const char *VAR_1, const char *VAR_2, const char *VAR_3, const char *VAR_4, const char *VAR_5, int VAR_6) { CPUState *env; ram_addr_t ram_offset; qemu_irq *cpu_pic; qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev; PCIBus *pci_bus; NICInfo *nd; int VAR_7; int VAR_8 = 0; if (!VAR_5) VAR_5 = "arm926"; env = cpu_init(VAR_5); if (!env) { fprintf(stderr, "Unable to find CPU definition\VAR_7"); exit(1); } ram_offset = qemu_ram_alloc(VAR_0); cpu_register_physical_memory(0, VAR_0, ram_offset | IO_MEM_RAM); arm_sysctl_init(0x10000000, 0x41007004); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_varargs("pl190", 0x10140000, cpu_pic[0], cpu_pic[1], NULL); for (VAR_7 = 0; VAR_7 < 32; VAR_7++) { pic[VAR_7] = qdev_get_gpio_in(dev, VAR_7); } dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); for (VAR_7 = 0; VAR_7 < 32; VAR_7++) { sysbus_connect_irq(sysbus_from_qdev(dev), VAR_7, pic[VAR_7]); sic[VAR_7] = qdev_get_gpio_in(dev, VAR_7); } sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); dev = sysbus_create_varargs("versatile_pci", 0x40000000, sic[27], sic[28], sic[29], sic[30], NULL); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); for(VAR_7 = 0; VAR_7 < nb_nics; VAR_7++) { nd = &nd_table[VAR_7]; if ((!nd->model && !VAR_8) || strcmp(nd->model, "smc91c111") == 0) { smc91c111_init(nd, 0x10010000, sic[25]); VAR_8 = 1; } else { pci_nic_init_nofail(nd, "rtl8139", NULL); } } if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } VAR_7 = drive_get_max_bus(IF_SCSI); while (VAR_7 >= 0) { pci_create_simple(pci_bus, -1, "lsi53c895a"); VAR_7--; } sysbus_create_simple("pl011", 0x101f1000, pic[12]); sysbus_create_simple("pl011", 0x101f2000, pic[13]); sysbus_create_simple("pl011", 0x101f3000, pic[14]); sysbus_create_simple("pl011", 0x10009000, sic[6]); sysbus_create_simple("pl080", 0x10130000, pic[17]); sysbus_create_simple("sp804", 0x101e2000, pic[4]); sysbus_create_simple("sp804", 0x101e3000, pic[5]); sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); sysbus_create_simple("pl031", 0x101e8000, pic[10]); versatile_binfo.VAR_0 = VAR_0; versatile_binfo.VAR_2 = VAR_2; versatile_binfo.VAR_3 = VAR_3; versatile_binfo.VAR_4 = VAR_4; versatile_binfo.VAR_6 = VAR_6; arm_load_kernel(env, &versatile_binfo); }
[ "static void FUNC_0(ram_addr_t VAR_0,\nconst char *VAR_1,\nconst char *VAR_2, const char *VAR_3,\nconst char *VAR_4, const char *VAR_5,\nint VAR_6)\n{", "CPUState *env;", "ram_addr_t ram_offset;", "qemu_irq *cpu_pic;", "qemu_irq pic[32];", "qemu_irq sic[32];", "DeviceState *dev;", "PCIBus *pci_bus;", "NICInfo *nd;", "int VAR_7;", "int VAR_8 = 0;", "if (!VAR_5)\nVAR_5 = \"arm926\";", "env = cpu_init(VAR_5);", "if (!env) {", "fprintf(stderr, \"Unable to find CPU definition\\VAR_7\");", "exit(1);", "}", "ram_offset = qemu_ram_alloc(VAR_0);", "cpu_register_physical_memory(0, VAR_0, ram_offset | IO_MEM_RAM);", "arm_sysctl_init(0x10000000, 0x41007004);", "cpu_pic = arm_pic_init_cpu(env);", "dev = sysbus_create_varargs(\"pl190\", 0x10140000,\ncpu_pic[0], cpu_pic[1], NULL);", "for (VAR_7 = 0; VAR_7 < 32; VAR_7++) {", "pic[VAR_7] = qdev_get_gpio_in(dev, VAR_7);", "}", "dev = sysbus_create_simple(\"versatilepb_sic\", 0x10003000, NULL);", "for (VAR_7 = 0; VAR_7 < 32; VAR_7++) {", "sysbus_connect_irq(sysbus_from_qdev(dev), VAR_7, pic[VAR_7]);", "sic[VAR_7] = qdev_get_gpio_in(dev, VAR_7);", "}", "sysbus_create_simple(\"pl050_keyboard\", 0x10006000, sic[3]);", "sysbus_create_simple(\"pl050_mouse\", 0x10007000, sic[4]);", "dev = sysbus_create_varargs(\"versatile_pci\", 0x40000000,\nsic[27], sic[28], sic[29], sic[30], NULL);", "pci_bus = (PCIBus *)qdev_get_child_bus(dev, \"pci\");", "for(VAR_7 = 0; VAR_7 < nb_nics; VAR_7++) {", "nd = &nd_table[VAR_7];", "if ((!nd->model && !VAR_8) || strcmp(nd->model, \"smc91c111\") == 0) {", "smc91c111_init(nd, 0x10010000, sic[25]);", "VAR_8 = 1;", "} else {", "pci_nic_init_nofail(nd, \"rtl8139\", NULL);", "}", "}", "if (usb_enabled) {", "usb_ohci_init_pci(pci_bus, -1);", "}", "VAR_7 = drive_get_max_bus(IF_SCSI);", "while (VAR_7 >= 0) {", "pci_create_simple(pci_bus, -1, \"lsi53c895a\");", "VAR_7--;", "}", "sysbus_create_simple(\"pl011\", 0x101f1000, pic[12]);", "sysbus_create_simple(\"pl011\", 0x101f2000, pic[13]);", "sysbus_create_simple(\"pl011\", 0x101f3000, pic[14]);", "sysbus_create_simple(\"pl011\", 0x10009000, sic[6]);", "sysbus_create_simple(\"pl080\", 0x10130000, pic[17]);", "sysbus_create_simple(\"sp804\", 0x101e2000, pic[4]);", "sysbus_create_simple(\"sp804\", 0x101e3000, pic[5]);", "sysbus_create_simple(\"pl110_versatile\", 0x10120000, pic[16]);", "sysbus_create_varargs(\"pl181\", 0x10005000, sic[22], sic[1], NULL);", "sysbus_create_varargs(\"pl181\", 0x1000b000, sic[23], sic[2], NULL);", "sysbus_create_simple(\"pl031\", 0x101e8000, pic[10]);", "versatile_binfo.VAR_0 = VAR_0;", "versatile_binfo.VAR_2 = VAR_2;", "versatile_binfo.VAR_3 = VAR_3;", "versatile_binfo.VAR_4 = VAR_4;", "versatile_binfo.VAR_6 = VAR_6;", "arm_load_kernel(env, &versatile_binfo);", "}" ]
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16,841
static void tftp_send_next_block(struct tftp_session *spt, struct tftp_t *recv_tp) { struct sockaddr_in saddr, daddr; struct mbuf *m; struct tftp_t *tp; int nobytes; m = m_get(spt->slirp); if (!m) { return; } memset(m->m_data, 0, m->m_size); m->m_data += IF_MAXLINKHDR; tp = (void *)m->m_data; m->m_data += sizeof(struct udpiphdr); tp->tp_op = htons(TFTP_DATA); tp->x.tp_data.tp_block_nr = htons((spt->block_nr + 1) & 0xffff); saddr.sin_addr = recv_tp->ip.ip_dst; saddr.sin_port = recv_tp->udp.uh_dport; daddr.sin_addr = spt->client_ip; daddr.sin_port = spt->client_port; nobytes = tftp_read_data(spt, spt->block_nr, tp->x.tp_data.tp_buf, 512); if (nobytes < 0) { m_free(m); /* send "file not found" error back */ tftp_send_error(spt, 1, "File not found", tp); return; } m->m_len = sizeof(struct tftp_t) - (512 - nobytes) - sizeof(struct ip) - sizeof(struct udphdr); udp_output2(NULL, m, &saddr, &daddr, IPTOS_LOWDELAY); if (nobytes == 512) { tftp_session_update(spt); } else { tftp_session_terminate(spt); } spt->block_nr++; }
false
qemu
5379229a2708df3a1506113315214c3ce5325859
static void tftp_send_next_block(struct tftp_session *spt, struct tftp_t *recv_tp) { struct sockaddr_in saddr, daddr; struct mbuf *m; struct tftp_t *tp; int nobytes; m = m_get(spt->slirp); if (!m) { return; } memset(m->m_data, 0, m->m_size); m->m_data += IF_MAXLINKHDR; tp = (void *)m->m_data; m->m_data += sizeof(struct udpiphdr); tp->tp_op = htons(TFTP_DATA); tp->x.tp_data.tp_block_nr = htons((spt->block_nr + 1) & 0xffff); saddr.sin_addr = recv_tp->ip.ip_dst; saddr.sin_port = recv_tp->udp.uh_dport; daddr.sin_addr = spt->client_ip; daddr.sin_port = spt->client_port; nobytes = tftp_read_data(spt, spt->block_nr, tp->x.tp_data.tp_buf, 512); if (nobytes < 0) { m_free(m); tftp_send_error(spt, 1, "File not found", tp); return; } m->m_len = sizeof(struct tftp_t) - (512 - nobytes) - sizeof(struct ip) - sizeof(struct udphdr); udp_output2(NULL, m, &saddr, &daddr, IPTOS_LOWDELAY); if (nobytes == 512) { tftp_session_update(spt); } else { tftp_session_terminate(spt); } spt->block_nr++; }
{ "code": [], "line_no": [] }
static void FUNC_0(struct tftp_session *VAR_0, struct tftp_t *VAR_1) { struct sockaddr_in VAR_2, VAR_3; struct mbuf *VAR_4; struct tftp_t *VAR_5; int VAR_6; VAR_4 = m_get(VAR_0->slirp); if (!VAR_4) { return; } memset(VAR_4->m_data, 0, VAR_4->m_size); VAR_4->m_data += IF_MAXLINKHDR; VAR_5 = (void *)VAR_4->m_data; VAR_4->m_data += sizeof(struct udpiphdr); VAR_5->tp_op = htons(TFTP_DATA); VAR_5->x.tp_data.tp_block_nr = htons((VAR_0->block_nr + 1) & 0xffff); VAR_2.sin_addr = VAR_1->ip.ip_dst; VAR_2.sin_port = VAR_1->udp.uh_dport; VAR_3.sin_addr = VAR_0->client_ip; VAR_3.sin_port = VAR_0->client_port; VAR_6 = tftp_read_data(VAR_0, VAR_0->block_nr, VAR_5->x.tp_data.tp_buf, 512); if (VAR_6 < 0) { m_free(VAR_4); tftp_send_error(VAR_0, 1, "File not found", VAR_5); return; } VAR_4->m_len = sizeof(struct tftp_t) - (512 - VAR_6) - sizeof(struct ip) - sizeof(struct udphdr); udp_output2(NULL, VAR_4, &VAR_2, &VAR_3, IPTOS_LOWDELAY); if (VAR_6 == 512) { tftp_session_update(VAR_0); } else { tftp_session_terminate(VAR_0); } VAR_0->block_nr++; }
[ "static void FUNC_0(struct tftp_session *VAR_0,\nstruct tftp_t *VAR_1)\n{", "struct sockaddr_in VAR_2, VAR_3;", "struct mbuf *VAR_4;", "struct tftp_t *VAR_5;", "int VAR_6;", "VAR_4 = m_get(VAR_0->slirp);", "if (!VAR_4) {", "return;", "}", "memset(VAR_4->m_data, 0, VAR_4->m_size);", "VAR_4->m_data += IF_MAXLINKHDR;", "VAR_5 = (void *)VAR_4->m_data;", "VAR_4->m_data += sizeof(struct udpiphdr);", "VAR_5->tp_op = htons(TFTP_DATA);", "VAR_5->x.tp_data.tp_block_nr = htons((VAR_0->block_nr + 1) & 0xffff);", "VAR_2.sin_addr = VAR_1->ip.ip_dst;", "VAR_2.sin_port = VAR_1->udp.uh_dport;", "VAR_3.sin_addr = VAR_0->client_ip;", "VAR_3.sin_port = VAR_0->client_port;", "VAR_6 = tftp_read_data(VAR_0, VAR_0->block_nr, VAR_5->x.tp_data.tp_buf, 512);", "if (VAR_6 < 0) {", "m_free(VAR_4);", "tftp_send_error(VAR_0, 1, \"File not found\", VAR_5);", "return;", "}", "VAR_4->m_len = sizeof(struct tftp_t) - (512 - VAR_6) -\nsizeof(struct ip) - sizeof(struct udphdr);", "udp_output2(NULL, VAR_4, &VAR_2, &VAR_3, IPTOS_LOWDELAY);", "if (VAR_6 == 512) {", "tftp_session_update(VAR_0);", "}", "else {", "tftp_session_terminate(VAR_0);", "}", "VAR_0->block_nr++;", "}" ]
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16,843
static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, unsigned max_lvl, unsigned *compat_lvl, unsigned *cpu_version) { unsigned lvl = get_compat_level(pvr); bool is205, is206; if (!lvl) { return; } /* If it is a logical PVR, try to determine the highest level */ is205 = (pcc->pcr_mask & PCR_COMPAT_2_05) && (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); is206 = (pcc->pcr_mask & PCR_COMPAT_2_06) && ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); if (is205 || is206) { if (!max_lvl) { /* User did not set the level, choose the highest */ if (*compat_lvl <= lvl) { *compat_lvl = lvl; *cpu_version = pvr; } } else if (max_lvl >= lvl) { /* User chose the level, don't set higher than this */ *compat_lvl = lvl; *cpu_version = pvr; } } }
false
qemu
8cd2ce7aaa3c3fadc561f40045d4d53ff72e94ef
static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, unsigned max_lvl, unsigned *compat_lvl, unsigned *cpu_version) { unsigned lvl = get_compat_level(pvr); bool is205, is206; if (!lvl) { return; } is205 = (pcc->pcr_mask & PCR_COMPAT_2_05) && (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); is206 = (pcc->pcr_mask & PCR_COMPAT_2_06) && ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); if (is205 || is206) { if (!max_lvl) { if (*compat_lvl <= lvl) { *compat_lvl = lvl; *cpu_version = pvr; } } else if (max_lvl >= lvl) { *compat_lvl = lvl; *cpu_version = pvr; } } }
{ "code": [], "line_no": [] }
static void FUNC_0(PowerPCCPUClass *VAR_0, uint32_t VAR_1, unsigned VAR_2, unsigned *VAR_3, unsigned *VAR_4) { unsigned VAR_5 = get_compat_level(VAR_1); bool is205, is206; if (!VAR_5) { return; } is205 = (VAR_0->pcr_mask & PCR_COMPAT_2_05) && (VAR_5 == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); is206 = (VAR_0->pcr_mask & PCR_COMPAT_2_06) && ((VAR_5 == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || (VAR_5 == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); if (is205 || is206) { if (!VAR_2) { if (*VAR_3 <= VAR_5) { *VAR_3 = VAR_5; *VAR_4 = VAR_1; } } else if (VAR_2 >= VAR_5) { *VAR_3 = VAR_5; *VAR_4 = VAR_1; } } }
[ "static void FUNC_0(PowerPCCPUClass *VAR_0, uint32_t VAR_1,\nunsigned VAR_2, unsigned *VAR_3,\nunsigned *VAR_4)\n{", "unsigned VAR_5 = get_compat_level(VAR_1);", "bool is205, is206;", "if (!VAR_5) {", "return;", "}", "is205 = (VAR_0->pcr_mask & PCR_COMPAT_2_05) &&\n(VAR_5 == get_compat_level(CPU_POWERPC_LOGICAL_2_05));", "is206 = (VAR_0->pcr_mask & PCR_COMPAT_2_06) &&\n((VAR_5 == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) ||\n(VAR_5 == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS)));", "if (is205 || is206) {", "if (!VAR_2) {", "if (*VAR_3 <= VAR_5) {", "*VAR_3 = VAR_5;", "*VAR_4 = VAR_1;", "}", "} else if (VAR_2 >= VAR_5) {", "*VAR_3 = VAR_5;", "*VAR_4 = VAR_1;", "}", "}", "}" ]
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[ [ 1, 3, 5, 7 ], [ 9 ], [ 11 ], [ 15 ], [ 17 ], [ 19 ], [ 25, 27 ], [ 29, 31, 33 ], [ 37 ], [ 39 ], [ 43 ], [ 45 ], [ 47 ], [ 49 ], [ 51 ], [ 55 ], [ 57 ], [ 59 ], [ 61 ], [ 63 ] ]
16,844
static void qobject_input_type_str(Visitor *v, const char *name, char **obj, Error **errp) { QObjectInputVisitor *qiv = to_qiv(v); QObject *qobj = qobject_input_get_object(qiv, name, true, errp); QString *qstr; *obj = NULL; if (!qobj) { return; } qstr = qobject_to_qstring(qobj); if (!qstr) { error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null", "string"); return; } *obj = g_strdup(qstring_get_str(qstr)); }
true
qemu
a9fc37f6bc3f2ab90585cb16493da9f6dcfbfbcf
static void qobject_input_type_str(Visitor *v, const char *name, char **obj, Error **errp) { QObjectInputVisitor *qiv = to_qiv(v); QObject *qobj = qobject_input_get_object(qiv, name, true, errp); QString *qstr; *obj = NULL; if (!qobj) { return; } qstr = qobject_to_qstring(qobj); if (!qstr) { error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null", "string"); return; } *obj = g_strdup(qstring_get_str(qstr)); }
{ "code": [ " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\",", " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\",", " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\",", " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\",", " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\",", " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\",", " \"string\");", " error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : \"null\"," ], "line_no": [ 27, 27, 27, 27, 27, 27, 29, 27 ] }
static void FUNC_0(Visitor *VAR_0, const char *VAR_1, char **VAR_2, Error **VAR_3) { QObjectInputVisitor *qiv = to_qiv(VAR_0); QObject *qobj = qobject_input_get_object(qiv, VAR_1, true, VAR_3); QString *qstr; *VAR_2 = NULL; if (!qobj) { return; } qstr = qobject_to_qstring(qobj); if (!qstr) { error_setg(VAR_3, QERR_INVALID_PARAMETER_TYPE, VAR_1 ? VAR_1 : "null", "string"); return; } *VAR_2 = g_strdup(qstring_get_str(qstr)); }
[ "static void FUNC_0(Visitor *VAR_0, const char *VAR_1, char **VAR_2,\nError **VAR_3)\n{", "QObjectInputVisitor *qiv = to_qiv(VAR_0);", "QObject *qobj = qobject_input_get_object(qiv, VAR_1, true, VAR_3);", "QString *qstr;", "*VAR_2 = NULL;", "if (!qobj) {", "return;", "}", "qstr = qobject_to_qstring(qobj);", "if (!qstr) {", "error_setg(VAR_3, QERR_INVALID_PARAMETER_TYPE, VAR_1 ? VAR_1 : \"null\",\n\"string\");", "return;", "}", "*VAR_2 = g_strdup(qstring_get_str(qstr));", "}" ]
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[ [ 1, 3, 5 ], [ 7 ], [ 9 ], [ 11 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ], [ 27, 29 ], [ 31 ], [ 33 ], [ 37 ], [ 39 ] ]
16,845
static void gen_or(DisasContext *ctx) { int rs, ra, rb; rs = rS(ctx->opcode); ra = rA(ctx->opcode); rb = rB(ctx->opcode); /* Optimisation for mr. ri case */ if (rs != ra || rs != rb) { if (rs != rb) tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); else tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[ra]); } else if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_Rc0(ctx, cpu_gpr[rs]); #if defined(TARGET_PPC64) } else { int prio = 0; switch (rs) { case 1: /* Set process priority to low */ prio = 2; break; case 6: /* Set process priority to medium-low */ prio = 3; break; case 2: /* Set process priority to normal */ prio = 4; break; #if !defined(CONFIG_USER_ONLY) case 31: if (!ctx->pr) { /* Set process priority to very low */ prio = 1; } break; case 5: if (!ctx->pr) { /* Set process priority to medium-hight */ prio = 5; } break; case 3: if (!ctx->pr) { /* Set process priority to high */ prio = 6; } break; case 7: if (ctx->hv) { /* Set process priority to very high */ prio = 7; } break; #endif default: /* nop */ break; } if (prio) { TCGv t0 = tcg_temp_new(); gen_load_spr(t0, SPR_PPR); tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); gen_store_spr(SPR_PPR, t0); tcg_temp_free(t0); } #endif } }
true
qemu
b68e60e6f0d2865e961a800fb8db96a7fc6494c4
static void gen_or(DisasContext *ctx) { int rs, ra, rb; rs = rS(ctx->opcode); ra = rA(ctx->opcode); rb = rB(ctx->opcode); if (rs != ra || rs != rb) { if (rs != rb) tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); else tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[ra]); } else if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_Rc0(ctx, cpu_gpr[rs]); #if defined(TARGET_PPC64) } else { int prio = 0; switch (rs) { case 1: prio = 2; break; case 6: prio = 3; break; case 2: prio = 4; break; #if !defined(CONFIG_USER_ONLY) case 31: if (!ctx->pr) { prio = 1; } break; case 5: if (!ctx->pr) { prio = 5; } break; case 3: if (!ctx->pr) { prio = 6; } break; case 7: if (ctx->hv) { prio = 7; } break; #endif default: break; } if (prio) { TCGv t0 = tcg_temp_new(); gen_load_spr(t0, SPR_PPR); tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); gen_store_spr(SPR_PPR, t0); tcg_temp_free(t0); } #endif } }
{ "code": [ " if (ctx->hv) {" ], "line_no": [ 109 ] }
static void FUNC_0(DisasContext *VAR_0) { int VAR_1, VAR_2, VAR_3; VAR_1 = rS(VAR_0->opcode); VAR_2 = rA(VAR_0->opcode); VAR_3 = rB(VAR_0->opcode); if (VAR_1 != VAR_2 || VAR_1 != VAR_3) { if (VAR_1 != VAR_3) tcg_gen_or_tl(cpu_gpr[VAR_2], cpu_gpr[VAR_1], cpu_gpr[VAR_3]); else tcg_gen_mov_tl(cpu_gpr[VAR_2], cpu_gpr[VAR_1]); if (unlikely(Rc(VAR_0->opcode) != 0)) gen_set_Rc0(VAR_0, cpu_gpr[VAR_2]); } else if (unlikely(Rc(VAR_0->opcode) != 0)) { gen_set_Rc0(VAR_0, cpu_gpr[VAR_1]); #if defined(TARGET_PPC64) } else { int prio = 0; switch (VAR_1) { case 1: prio = 2; break; case 6: prio = 3; break; case 2: prio = 4; break; #if !defined(CONFIG_USER_ONLY) case 31: if (!VAR_0->pr) { prio = 1; } break; case 5: if (!VAR_0->pr) { prio = 5; } break; case 3: if (!VAR_0->pr) { prio = 6; } break; case 7: if (VAR_0->hv) { prio = 7; } break; #endif default: break; } if (prio) { TCGv t0 = tcg_temp_new(); gen_load_spr(t0, SPR_PPR); tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); gen_store_spr(SPR_PPR, t0); tcg_temp_free(t0); } #endif } }
[ "static void FUNC_0(DisasContext *VAR_0)\n{", "int VAR_1, VAR_2, VAR_3;", "VAR_1 = rS(VAR_0->opcode);", "VAR_2 = rA(VAR_0->opcode);", "VAR_3 = rB(VAR_0->opcode);", "if (VAR_1 != VAR_2 || VAR_1 != VAR_3) {", "if (VAR_1 != VAR_3)\ntcg_gen_or_tl(cpu_gpr[VAR_2], cpu_gpr[VAR_1], cpu_gpr[VAR_3]);", "else\ntcg_gen_mov_tl(cpu_gpr[VAR_2], cpu_gpr[VAR_1]);", "if (unlikely(Rc(VAR_0->opcode) != 0))\ngen_set_Rc0(VAR_0, cpu_gpr[VAR_2]);", "} else if (unlikely(Rc(VAR_0->opcode) != 0)) {", "gen_set_Rc0(VAR_0, cpu_gpr[VAR_1]);", "#if defined(TARGET_PPC64)\n} else {", "int prio = 0;", "switch (VAR_1) {", "case 1:\nprio = 2;", "break;", "case 6:\nprio = 3;", "break;", "case 2:\nprio = 4;", "break;", "#if !defined(CONFIG_USER_ONLY)\ncase 31:\nif (!VAR_0->pr) {", "prio = 1;", "}", "break;", "case 5:\nif (!VAR_0->pr) {", "prio = 5;", "}", "break;", "case 3:\nif (!VAR_0->pr) {", "prio = 6;", "}", "break;", "case 7:\nif (VAR_0->hv) {", "prio = 7;", "}", "break;", "#endif\ndefault:\nbreak;", "}", "if (prio) {", "TCGv t0 = tcg_temp_new();", "gen_load_spr(t0, SPR_PPR);", "tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);", "tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);", "gen_store_spr(SPR_PPR, t0);", "tcg_temp_free(t0);", "}", "#endif\n}", "}" ]
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16,846
target_ulong helper_dvpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; do { /* Turn off all VPEs except the one executing the dvpe. */ if (other_cpu != env) { other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); mips_vpe_sleep(other_cpu); } other_cpu = other_cpu->next_cpu; } while (other_cpu); return prev; }
true
qemu
81bad50ec40311797c38a7691844c7d2df9b3823
target_ulong helper_dvpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; do { if (other_cpu != env) { other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); mips_vpe_sleep(other_cpu); } other_cpu = other_cpu->next_cpu; } while (other_cpu); return prev; }
{ "code": [ " CPUMIPSState *other_cpu = first_cpu;", " if (other_cpu != env) {", " other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);", " mips_vpe_sleep(other_cpu);", " other_cpu = other_cpu->next_cpu;", " } while (other_cpu);", " CPUMIPSState *other_cpu = first_cpu;", " other_cpu = other_cpu->next_cpu;", " } while (other_cpu);" ], "line_no": [ 5, 15, 17, 19, 23, 25, 5, 23, 25 ] }
target_ulong FUNC_0(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; do { if (other_cpu != env) { other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); mips_vpe_sleep(other_cpu); } other_cpu = other_cpu->next_cpu; } while (other_cpu); return prev; }
[ "target_ulong FUNC_0(CPUMIPSState *env)\n{", "CPUMIPSState *other_cpu = first_cpu;", "target_ulong prev = env->mvp->CP0_MVPControl;", "do {", "if (other_cpu != env) {", "other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);", "mips_vpe_sleep(other_cpu);", "}", "other_cpu = other_cpu->next_cpu;", "} while (other_cpu);", "return prev;", "}" ]
[ 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0 ]
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16,847
static int sbr_make_f_master(AACContext *ac, SpectralBandReplication *sbr, SpectrumParameters *spectrum) { unsigned int temp, max_qmf_subbands; unsigned int start_min, stop_min; int k; const int8_t *sbr_offset_ptr; int16_t stop_dk[13]; if (sbr->sample_rate < 32000) { temp = 3000; } else if (sbr->sample_rate < 64000) { temp = 4000; } else temp = 5000; switch (sbr->sample_rate) { case 16000: sbr_offset_ptr = sbr_offset[0]; break; case 22050: sbr_offset_ptr = sbr_offset[1]; break; case 24000: sbr_offset_ptr = sbr_offset[2]; break; case 32000: sbr_offset_ptr = sbr_offset[3]; break; case 44100: case 48000: case 64000: sbr_offset_ptr = sbr_offset[4]; break; case 88200: case 96000: case 128000: case 176400: case 192000: sbr_offset_ptr = sbr_offset[5]; break; default: av_log(ac->avctx, AV_LOG_ERROR, "Unsupported sample rate for SBR: %d\n", sbr->sample_rate); return -1; } start_min = ((temp << 7) + (sbr->sample_rate >> 1)) / sbr->sample_rate; stop_min = ((temp << 8) + (sbr->sample_rate >> 1)) / sbr->sample_rate; sbr->k[0] = start_min + sbr_offset_ptr[spectrum->bs_start_freq]; if (spectrum->bs_stop_freq < 14) { sbr->k[2] = stop_min; make_bands(stop_dk, stop_min, 64, 13); qsort(stop_dk, 13, sizeof(stop_dk[0]), qsort_comparison_function_int16); for (k = 0; k < spectrum->bs_stop_freq; k++) sbr->k[2] += stop_dk[k]; } else if (spectrum->bs_stop_freq == 14) { sbr->k[2] = 2*sbr->k[0]; } else if (spectrum->bs_stop_freq == 15) { sbr->k[2] = 3*sbr->k[0]; } else { av_log(ac->avctx, AV_LOG_ERROR, "Invalid bs_stop_freq: %d\n", spectrum->bs_stop_freq); return -1; } sbr->k[2] = FFMIN(64, sbr->k[2]); // Requirements (14496-3 sp04 p205) if (sbr->sample_rate <= 32000) { max_qmf_subbands = 48; } else if (sbr->sample_rate == 44100) { max_qmf_subbands = 35; } else if (sbr->sample_rate >= 48000) max_qmf_subbands = 32; if (sbr->k[2] - sbr->k[0] > max_qmf_subbands) { av_log(ac->avctx, AV_LOG_ERROR, "Invalid bitstream, too many QMF subbands: %d\n", sbr->k[2] - sbr->k[0]); return -1; } if (!spectrum->bs_freq_scale) { int dk, k2diff; dk = spectrum->bs_alter_scale + 1; sbr->n_master = ((sbr->k[2] - sbr->k[0] + (dk&2)) >> dk) << 1; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; for (k = 1; k <= sbr->n_master; k++) sbr->f_master[k] = dk; k2diff = sbr->k[2] - sbr->k[0] - sbr->n_master * dk; if (k2diff < 0) { sbr->f_master[1]--; sbr->f_master[2]-= (k2diff < -1); } else if (k2diff) { sbr->f_master[sbr->n_master]++; } sbr->f_master[0] = sbr->k[0]; for (k = 1; k <= sbr->n_master; k++) sbr->f_master[k] += sbr->f_master[k - 1]; } else { int half_bands = 7 - spectrum->bs_freq_scale; // bs_freq_scale = {1,2,3} int two_regions, num_bands_0; int vdk0_max, vdk1_min; int16_t vk0[49]; if (49 * sbr->k[2] > 110 * sbr->k[0]) { two_regions = 1; sbr->k[1] = 2 * sbr->k[0]; } else { two_regions = 0; sbr->k[1] = sbr->k[2]; } num_bands_0 = lrintf(half_bands * log2f(sbr->k[1] / (float)sbr->k[0])) * 2; if (num_bands_0 <= 0) { // Requirements (14496-3 sp04 p205) av_log(ac->avctx, AV_LOG_ERROR, "Invalid num_bands_0: %d\n", num_bands_0); return -1; } vk0[0] = 0; make_bands(vk0+1, sbr->k[0], sbr->k[1], num_bands_0); qsort(vk0 + 1, num_bands_0, sizeof(vk0[1]), qsort_comparison_function_int16); vdk0_max = vk0[num_bands_0]; vk0[0] = sbr->k[0]; for (k = 1; k <= num_bands_0; k++) { if (vk0[k] <= 0) { // Requirements (14496-3 sp04 p205) av_log(ac->avctx, AV_LOG_ERROR, "Invalid vDk0[%d]: %d\n", k, vk0[k]); return -1; } vk0[k] += vk0[k-1]; } if (two_regions) { int16_t vk1[49]; float invwarp = spectrum->bs_alter_scale ? 0.76923076923076923077f : 1.0f; // bs_alter_scale = {0,1} int num_bands_1 = lrintf(half_bands * invwarp * log2f(sbr->k[2] / (float)sbr->k[1])) * 2; make_bands(vk1+1, sbr->k[1], sbr->k[2], num_bands_1); vdk1_min = array_min_int16(vk1 + 1, num_bands_1); if (vdk1_min < vdk0_max) { int change; qsort(vk1 + 1, num_bands_1, sizeof(vk1[1]), qsort_comparison_function_int16); change = FFMIN(vdk0_max - vk1[1], (vk1[num_bands_1] - vk1[1]) >> 1); vk1[1] += change; vk1[num_bands_1] -= change; } qsort(vk1 + 1, num_bands_1, sizeof(vk1[1]), qsort_comparison_function_int16); vk1[0] = sbr->k[1]; for (k = 1; k <= num_bands_1; k++) { if (vk1[k] <= 0) { // Requirements (14496-3 sp04 p205) av_log(ac->avctx, AV_LOG_ERROR, "Invalid vDk1[%d]: %d\n", k, vk1[k]); return -1; } vk1[k] += vk1[k-1]; } sbr->n_master = num_bands_0 + num_bands_1; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; memcpy(&sbr->f_master[0], vk0, (num_bands_0 + 1) * sizeof(sbr->f_master[0])); memcpy(&sbr->f_master[num_bands_0 + 1], vk1 + 1, num_bands_1 * sizeof(sbr->f_master[0])); } else { sbr->n_master = num_bands_0; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; memcpy(sbr->f_master, vk0, (num_bands_0 + 1) * sizeof(sbr->f_master[0])); } } return 0; }
true
FFmpeg
c6d3b3be1555257ff3f88da6b8dca2158dad2a85
static int sbr_make_f_master(AACContext *ac, SpectralBandReplication *sbr, SpectrumParameters *spectrum) { unsigned int temp, max_qmf_subbands; unsigned int start_min, stop_min; int k; const int8_t *sbr_offset_ptr; int16_t stop_dk[13]; if (sbr->sample_rate < 32000) { temp = 3000; } else if (sbr->sample_rate < 64000) { temp = 4000; } else temp = 5000; switch (sbr->sample_rate) { case 16000: sbr_offset_ptr = sbr_offset[0]; break; case 22050: sbr_offset_ptr = sbr_offset[1]; break; case 24000: sbr_offset_ptr = sbr_offset[2]; break; case 32000: sbr_offset_ptr = sbr_offset[3]; break; case 44100: case 48000: case 64000: sbr_offset_ptr = sbr_offset[4]; break; case 88200: case 96000: case 128000: case 176400: case 192000: sbr_offset_ptr = sbr_offset[5]; break; default: av_log(ac->avctx, AV_LOG_ERROR, "Unsupported sample rate for SBR: %d\n", sbr->sample_rate); return -1; } start_min = ((temp << 7) + (sbr->sample_rate >> 1)) / sbr->sample_rate; stop_min = ((temp << 8) + (sbr->sample_rate >> 1)) / sbr->sample_rate; sbr->k[0] = start_min + sbr_offset_ptr[spectrum->bs_start_freq]; if (spectrum->bs_stop_freq < 14) { sbr->k[2] = stop_min; make_bands(stop_dk, stop_min, 64, 13); qsort(stop_dk, 13, sizeof(stop_dk[0]), qsort_comparison_function_int16); for (k = 0; k < spectrum->bs_stop_freq; k++) sbr->k[2] += stop_dk[k]; } else if (spectrum->bs_stop_freq == 14) { sbr->k[2] = 2*sbr->k[0]; } else if (spectrum->bs_stop_freq == 15) { sbr->k[2] = 3*sbr->k[0]; } else { av_log(ac->avctx, AV_LOG_ERROR, "Invalid bs_stop_freq: %d\n", spectrum->bs_stop_freq); return -1; } sbr->k[2] = FFMIN(64, sbr->k[2]); if (sbr->sample_rate <= 32000) { max_qmf_subbands = 48; } else if (sbr->sample_rate == 44100) { max_qmf_subbands = 35; } else if (sbr->sample_rate >= 48000) max_qmf_subbands = 32; if (sbr->k[2] - sbr->k[0] > max_qmf_subbands) { av_log(ac->avctx, AV_LOG_ERROR, "Invalid bitstream, too many QMF subbands: %d\n", sbr->k[2] - sbr->k[0]); return -1; } if (!spectrum->bs_freq_scale) { int dk, k2diff; dk = spectrum->bs_alter_scale + 1; sbr->n_master = ((sbr->k[2] - sbr->k[0] + (dk&2)) >> dk) << 1; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; for (k = 1; k <= sbr->n_master; k++) sbr->f_master[k] = dk; k2diff = sbr->k[2] - sbr->k[0] - sbr->n_master * dk; if (k2diff < 0) { sbr->f_master[1]--; sbr->f_master[2]-= (k2diff < -1); } else if (k2diff) { sbr->f_master[sbr->n_master]++; } sbr->f_master[0] = sbr->k[0]; for (k = 1; k <= sbr->n_master; k++) sbr->f_master[k] += sbr->f_master[k - 1]; } else { int half_bands = 7 - spectrum->bs_freq_scale; int two_regions, num_bands_0; int vdk0_max, vdk1_min; int16_t vk0[49]; if (49 * sbr->k[2] > 110 * sbr->k[0]) { two_regions = 1; sbr->k[1] = 2 * sbr->k[0]; } else { two_regions = 0; sbr->k[1] = sbr->k[2]; } num_bands_0 = lrintf(half_bands * log2f(sbr->k[1] / (float)sbr->k[0])) * 2; if (num_bands_0 <= 0) { av_log(ac->avctx, AV_LOG_ERROR, "Invalid num_bands_0: %d\n", num_bands_0); return -1; } vk0[0] = 0; make_bands(vk0+1, sbr->k[0], sbr->k[1], num_bands_0); qsort(vk0 + 1, num_bands_0, sizeof(vk0[1]), qsort_comparison_function_int16); vdk0_max = vk0[num_bands_0]; vk0[0] = sbr->k[0]; for (k = 1; k <= num_bands_0; k++) { if (vk0[k] <= 0) { av_log(ac->avctx, AV_LOG_ERROR, "Invalid vDk0[%d]: %d\n", k, vk0[k]); return -1; } vk0[k] += vk0[k-1]; } if (two_regions) { int16_t vk1[49]; float invwarp = spectrum->bs_alter_scale ? 0.76923076923076923077f : 1.0f; int num_bands_1 = lrintf(half_bands * invwarp * log2f(sbr->k[2] / (float)sbr->k[1])) * 2; make_bands(vk1+1, sbr->k[1], sbr->k[2], num_bands_1); vdk1_min = array_min_int16(vk1 + 1, num_bands_1); if (vdk1_min < vdk0_max) { int change; qsort(vk1 + 1, num_bands_1, sizeof(vk1[1]), qsort_comparison_function_int16); change = FFMIN(vdk0_max - vk1[1], (vk1[num_bands_1] - vk1[1]) >> 1); vk1[1] += change; vk1[num_bands_1] -= change; } qsort(vk1 + 1, num_bands_1, sizeof(vk1[1]), qsort_comparison_function_int16); vk1[0] = sbr->k[1]; for (k = 1; k <= num_bands_1; k++) { if (vk1[k] <= 0) { av_log(ac->avctx, AV_LOG_ERROR, "Invalid vDk1[%d]: %d\n", k, vk1[k]); return -1; } vk1[k] += vk1[k-1]; } sbr->n_master = num_bands_0 + num_bands_1; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; memcpy(&sbr->f_master[0], vk0, (num_bands_0 + 1) * sizeof(sbr->f_master[0])); memcpy(&sbr->f_master[num_bands_0 + 1], vk1 + 1, num_bands_1 * sizeof(sbr->f_master[0])); } else { sbr->n_master = num_bands_0; if (check_n_master(ac->avctx, sbr->n_master, sbr->spectrum_params.bs_xover_band)) return -1; memcpy(sbr->f_master, vk0, (num_bands_0 + 1) * sizeof(sbr->f_master[0])); } } return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(AACContext *VAR_0, SpectralBandReplication *VAR_1, SpectrumParameters *VAR_2) { unsigned int VAR_3, VAR_4; unsigned int VAR_5, VAR_6; int VAR_7; const int8_t *VAR_8; int16_t stop_dk[13]; if (VAR_1->sample_rate < 32000) { VAR_3 = 3000; } else if (VAR_1->sample_rate < 64000) { VAR_3 = 4000; } else VAR_3 = 5000; switch (VAR_1->sample_rate) { case 16000: VAR_8 = sbr_offset[0]; break; case 22050: VAR_8 = sbr_offset[1]; break; case 24000: VAR_8 = sbr_offset[2]; break; case 32000: VAR_8 = sbr_offset[3]; break; case 44100: case 48000: case 64000: VAR_8 = sbr_offset[4]; break; case 88200: case 96000: case 128000: case 176400: case 192000: VAR_8 = sbr_offset[5]; break; default: av_log(VAR_0->avctx, AV_LOG_ERROR, "Unsupported sample rate for SBR: %d\n", VAR_1->sample_rate); return -1; } VAR_5 = ((VAR_3 << 7) + (VAR_1->sample_rate >> 1)) / VAR_1->sample_rate; VAR_6 = ((VAR_3 << 8) + (VAR_1->sample_rate >> 1)) / VAR_1->sample_rate; VAR_1->VAR_7[0] = VAR_5 + VAR_8[VAR_2->bs_start_freq]; if (VAR_2->bs_stop_freq < 14) { VAR_1->VAR_7[2] = VAR_6; make_bands(stop_dk, VAR_6, 64, 13); qsort(stop_dk, 13, sizeof(stop_dk[0]), qsort_comparison_function_int16); for (VAR_7 = 0; VAR_7 < VAR_2->bs_stop_freq; VAR_7++) VAR_1->VAR_7[2] += stop_dk[VAR_7]; } else if (VAR_2->bs_stop_freq == 14) { VAR_1->VAR_7[2] = 2*VAR_1->VAR_7[0]; } else if (VAR_2->bs_stop_freq == 15) { VAR_1->VAR_7[2] = 3*VAR_1->VAR_7[0]; } else { av_log(VAR_0->avctx, AV_LOG_ERROR, "Invalid bs_stop_freq: %d\n", VAR_2->bs_stop_freq); return -1; } VAR_1->VAR_7[2] = FFMIN(64, VAR_1->VAR_7[2]); if (VAR_1->sample_rate <= 32000) { VAR_4 = 48; } else if (VAR_1->sample_rate == 44100) { VAR_4 = 35; } else if (VAR_1->sample_rate >= 48000) VAR_4 = 32; if (VAR_1->VAR_7[2] - VAR_1->VAR_7[0] > VAR_4) { av_log(VAR_0->avctx, AV_LOG_ERROR, "Invalid bitstream, too many QMF subbands: %d\n", VAR_1->VAR_7[2] - VAR_1->VAR_7[0]); return -1; } if (!VAR_2->bs_freq_scale) { int VAR_9, VAR_10; VAR_9 = VAR_2->bs_alter_scale + 1; VAR_1->n_master = ((VAR_1->VAR_7[2] - VAR_1->VAR_7[0] + (VAR_9&2)) >> VAR_9) << 1; if (check_n_master(VAR_0->avctx, VAR_1->n_master, VAR_1->spectrum_params.bs_xover_band)) return -1; for (VAR_7 = 1; VAR_7 <= VAR_1->n_master; VAR_7++) VAR_1->f_master[VAR_7] = VAR_9; VAR_10 = VAR_1->VAR_7[2] - VAR_1->VAR_7[0] - VAR_1->n_master * VAR_9; if (VAR_10 < 0) { VAR_1->f_master[1]--; VAR_1->f_master[2]-= (VAR_10 < -1); } else if (VAR_10) { VAR_1->f_master[VAR_1->n_master]++; } VAR_1->f_master[0] = VAR_1->VAR_7[0]; for (VAR_7 = 1; VAR_7 <= VAR_1->n_master; VAR_7++) VAR_1->f_master[VAR_7] += VAR_1->f_master[VAR_7 - 1]; } else { int VAR_11 = 7 - VAR_2->bs_freq_scale; int VAR_12, VAR_13; int VAR_14, VAR_15; int16_t vk0[49]; if (49 * VAR_1->VAR_7[2] > 110 * VAR_1->VAR_7[0]) { VAR_12 = 1; VAR_1->VAR_7[1] = 2 * VAR_1->VAR_7[0]; } else { VAR_12 = 0; VAR_1->VAR_7[1] = VAR_1->VAR_7[2]; } VAR_13 = lrintf(VAR_11 * log2f(VAR_1->VAR_7[1] / (float)VAR_1->VAR_7[0])) * 2; if (VAR_13 <= 0) { av_log(VAR_0->avctx, AV_LOG_ERROR, "Invalid VAR_13: %d\n", VAR_13); return -1; } vk0[0] = 0; make_bands(vk0+1, VAR_1->VAR_7[0], VAR_1->VAR_7[1], VAR_13); qsort(vk0 + 1, VAR_13, sizeof(vk0[1]), qsort_comparison_function_int16); VAR_14 = vk0[VAR_13]; vk0[0] = VAR_1->VAR_7[0]; for (VAR_7 = 1; VAR_7 <= VAR_13; VAR_7++) { if (vk0[VAR_7] <= 0) { av_log(VAR_0->avctx, AV_LOG_ERROR, "Invalid vDk0[%d]: %d\n", VAR_7, vk0[VAR_7]); return -1; } vk0[VAR_7] += vk0[VAR_7-1]; } if (VAR_12) { int16_t vk1[49]; float VAR_16 = VAR_2->bs_alter_scale ? 0.76923076923076923077f : 1.0f; int VAR_17 = lrintf(VAR_11 * VAR_16 * log2f(VAR_1->VAR_7[2] / (float)VAR_1->VAR_7[1])) * 2; make_bands(vk1+1, VAR_1->VAR_7[1], VAR_1->VAR_7[2], VAR_17); VAR_15 = array_min_int16(vk1 + 1, VAR_17); if (VAR_15 < VAR_14) { int VAR_18; qsort(vk1 + 1, VAR_17, sizeof(vk1[1]), qsort_comparison_function_int16); VAR_18 = FFMIN(VAR_14 - vk1[1], (vk1[VAR_17] - vk1[1]) >> 1); vk1[1] += VAR_18; vk1[VAR_17] -= VAR_18; } qsort(vk1 + 1, VAR_17, sizeof(vk1[1]), qsort_comparison_function_int16); vk1[0] = VAR_1->VAR_7[1]; for (VAR_7 = 1; VAR_7 <= VAR_17; VAR_7++) { if (vk1[VAR_7] <= 0) { av_log(VAR_0->avctx, AV_LOG_ERROR, "Invalid vDk1[%d]: %d\n", VAR_7, vk1[VAR_7]); return -1; } vk1[VAR_7] += vk1[VAR_7-1]; } VAR_1->n_master = VAR_13 + VAR_17; if (check_n_master(VAR_0->avctx, VAR_1->n_master, VAR_1->spectrum_params.bs_xover_band)) return -1; memcpy(&VAR_1->f_master[0], vk0, (VAR_13 + 1) * sizeof(VAR_1->f_master[0])); memcpy(&VAR_1->f_master[VAR_13 + 1], vk1 + 1, VAR_17 * sizeof(VAR_1->f_master[0])); } else { VAR_1->n_master = VAR_13; if (check_n_master(VAR_0->avctx, VAR_1->n_master, VAR_1->spectrum_params.bs_xover_band)) return -1; memcpy(VAR_1->f_master, vk0, (VAR_13 + 1) * sizeof(VAR_1->f_master[0])); } } return 0; }
[ "static int FUNC_0(AACContext *VAR_0, SpectralBandReplication *VAR_1,\nSpectrumParameters *VAR_2)\n{", "unsigned int VAR_3, VAR_4;", "unsigned int VAR_5, VAR_6;", "int VAR_7;", "const int8_t *VAR_8;", "int16_t stop_dk[13];", "if (VAR_1->sample_rate < 32000) {", "VAR_3 = 3000;", "} else if (VAR_1->sample_rate < 64000) {", "VAR_3 = 4000;", "} else", "VAR_3 = 5000;", "switch (VAR_1->sample_rate) {", "case 16000:\nVAR_8 = sbr_offset[0];", "break;", "case 22050:\nVAR_8 = sbr_offset[1];", "break;", "case 24000:\nVAR_8 = sbr_offset[2];", "break;", "case 32000:\nVAR_8 = sbr_offset[3];", "break;", "case 44100: case 48000: case 64000:\nVAR_8 = sbr_offset[4];", "break;", "case 88200: case 96000: case 128000: case 176400: case 192000:\nVAR_8 = sbr_offset[5];", "break;", "default:\nav_log(VAR_0->avctx, AV_LOG_ERROR,\n\"Unsupported sample rate for SBR: %d\\n\", VAR_1->sample_rate);", "return -1;", "}", "VAR_5 = ((VAR_3 << 7) + (VAR_1->sample_rate >> 1)) / VAR_1->sample_rate;", "VAR_6 = ((VAR_3 << 8) + (VAR_1->sample_rate >> 1)) / VAR_1->sample_rate;", "VAR_1->VAR_7[0] = VAR_5 + VAR_8[VAR_2->bs_start_freq];", "if (VAR_2->bs_stop_freq < 14) {", "VAR_1->VAR_7[2] = VAR_6;", "make_bands(stop_dk, VAR_6, 64, 13);", "qsort(stop_dk, 13, sizeof(stop_dk[0]), qsort_comparison_function_int16);", "for (VAR_7 = 0; VAR_7 < VAR_2->bs_stop_freq; VAR_7++)", "VAR_1->VAR_7[2] += stop_dk[VAR_7];", "} else if (VAR_2->bs_stop_freq == 14) {", "VAR_1->VAR_7[2] = 2*VAR_1->VAR_7[0];", "} else if (VAR_2->bs_stop_freq == 15) {", "VAR_1->VAR_7[2] = 3*VAR_1->VAR_7[0];", "} else {", "av_log(VAR_0->avctx, AV_LOG_ERROR,\n\"Invalid bs_stop_freq: %d\\n\", VAR_2->bs_stop_freq);", "return -1;", "}", "VAR_1->VAR_7[2] = FFMIN(64, VAR_1->VAR_7[2]);", "if (VAR_1->sample_rate <= 32000) {", "VAR_4 = 48;", "} else if (VAR_1->sample_rate == 44100) {", "VAR_4 = 35;", "} else if (VAR_1->sample_rate >= 48000)", "VAR_4 = 32;", "if (VAR_1->VAR_7[2] - VAR_1->VAR_7[0] > VAR_4) {", "av_log(VAR_0->avctx, AV_LOG_ERROR,\n\"Invalid bitstream, too many QMF subbands: %d\\n\", VAR_1->VAR_7[2] - VAR_1->VAR_7[0]);", "return -1;", "}", "if (!VAR_2->bs_freq_scale) {", "int VAR_9, VAR_10;", "VAR_9 = VAR_2->bs_alter_scale + 1;", "VAR_1->n_master = ((VAR_1->VAR_7[2] - VAR_1->VAR_7[0] + (VAR_9&2)) >> VAR_9) << 1;", "if (check_n_master(VAR_0->avctx, VAR_1->n_master, VAR_1->spectrum_params.bs_xover_band))\nreturn -1;", "for (VAR_7 = 1; VAR_7 <= VAR_1->n_master; VAR_7++)", "VAR_1->f_master[VAR_7] = VAR_9;", "VAR_10 = VAR_1->VAR_7[2] - VAR_1->VAR_7[0] - VAR_1->n_master * VAR_9;", "if (VAR_10 < 0) {", "VAR_1->f_master[1]--;", "VAR_1->f_master[2]-= (VAR_10 < -1);", "} else if (VAR_10) {", "VAR_1->f_master[VAR_1->n_master]++;", "}", "VAR_1->f_master[0] = VAR_1->VAR_7[0];", "for (VAR_7 = 1; VAR_7 <= VAR_1->n_master; VAR_7++)", "VAR_1->f_master[VAR_7] += VAR_1->f_master[VAR_7 - 1];", "} else {", "int VAR_11 = 7 - VAR_2->bs_freq_scale;", "int VAR_12, VAR_13;", "int VAR_14, VAR_15;", "int16_t vk0[49];", "if (49 * VAR_1->VAR_7[2] > 110 * VAR_1->VAR_7[0]) {", "VAR_12 = 1;", "VAR_1->VAR_7[1] = 2 * VAR_1->VAR_7[0];", "} else {", "VAR_12 = 0;", "VAR_1->VAR_7[1] = VAR_1->VAR_7[2];", "}", "VAR_13 = lrintf(VAR_11 * log2f(VAR_1->VAR_7[1] / (float)VAR_1->VAR_7[0])) * 2;", "if (VAR_13 <= 0) {", "av_log(VAR_0->avctx, AV_LOG_ERROR, \"Invalid VAR_13: %d\\n\", VAR_13);", "return -1;", "}", "vk0[0] = 0;", "make_bands(vk0+1, VAR_1->VAR_7[0], VAR_1->VAR_7[1], VAR_13);", "qsort(vk0 + 1, VAR_13, sizeof(vk0[1]), qsort_comparison_function_int16);", "VAR_14 = vk0[VAR_13];", "vk0[0] = VAR_1->VAR_7[0];", "for (VAR_7 = 1; VAR_7 <= VAR_13; VAR_7++) {", "if (vk0[VAR_7] <= 0) {", "av_log(VAR_0->avctx, AV_LOG_ERROR, \"Invalid vDk0[%d]: %d\\n\", VAR_7, vk0[VAR_7]);", "return -1;", "}", "vk0[VAR_7] += vk0[VAR_7-1];", "}", "if (VAR_12) {", "int16_t vk1[49];", "float VAR_16 = VAR_2->bs_alter_scale ? 0.76923076923076923077f\n: 1.0f;", "int VAR_17 = lrintf(VAR_11 * VAR_16 *\nlog2f(VAR_1->VAR_7[2] / (float)VAR_1->VAR_7[1])) * 2;", "make_bands(vk1+1, VAR_1->VAR_7[1], VAR_1->VAR_7[2], VAR_17);", "VAR_15 = array_min_int16(vk1 + 1, VAR_17);", "if (VAR_15 < VAR_14) {", "int VAR_18;", "qsort(vk1 + 1, VAR_17, sizeof(vk1[1]), qsort_comparison_function_int16);", "VAR_18 = FFMIN(VAR_14 - vk1[1], (vk1[VAR_17] - vk1[1]) >> 1);", "vk1[1] += VAR_18;", "vk1[VAR_17] -= VAR_18;", "}", "qsort(vk1 + 1, VAR_17, sizeof(vk1[1]), qsort_comparison_function_int16);", "vk1[0] = VAR_1->VAR_7[1];", "for (VAR_7 = 1; VAR_7 <= VAR_17; VAR_7++) {", "if (vk1[VAR_7] <= 0) {", "av_log(VAR_0->avctx, AV_LOG_ERROR, \"Invalid vDk1[%d]: %d\\n\", VAR_7, vk1[VAR_7]);", "return -1;", "}", "vk1[VAR_7] += vk1[VAR_7-1];", "}", "VAR_1->n_master = VAR_13 + VAR_17;", "if (check_n_master(VAR_0->avctx, VAR_1->n_master, VAR_1->spectrum_params.bs_xover_band))\nreturn -1;", "memcpy(&VAR_1->f_master[0], vk0,\n(VAR_13 + 1) * sizeof(VAR_1->f_master[0]));", "memcpy(&VAR_1->f_master[VAR_13 + 1], vk1 + 1,\nVAR_17 * sizeof(VAR_1->f_master[0]));", "} else {", "VAR_1->n_master = VAR_13;", "if (check_n_master(VAR_0->avctx, VAR_1->n_master, VAR_1->spectrum_params.bs_xover_band))\nreturn -1;", "memcpy(VAR_1->f_master, vk0, (VAR_13 + 1) * sizeof(VAR_1->f_master[0]));", "}", "}", "return 0;", "}" ]
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16,848
static void event_loop(VideoState *cur_stream) { SDL_Event event; double incr, pos, frac; for (;;) { double x; refresh_loop_wait_event(cur_stream, &event); switch (event.type) { case SDL_KEYDOWN: if (exit_on_keydown) { do_exit(cur_stream); break; } switch (event.key.keysym.sym) { case SDLK_ESCAPE: case SDLK_q: do_exit(cur_stream); break; case SDLK_f: toggle_full_screen(cur_stream); cur_stream->force_refresh = 1; break; case SDLK_p: case SDLK_SPACE: toggle_pause(cur_stream); break; case SDLK_s: // S: Step to next frame step_to_next_frame(cur_stream); break; case SDLK_a: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_AUDIO); break; case SDLK_v: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_VIDEO); break; case SDLK_t: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_SUBTITLE); break; case SDLK_w: toggle_audio_display(cur_stream); break; case SDLK_PAGEUP: incr = 600.0; goto do_seek; case SDLK_PAGEDOWN: incr = -600.0; goto do_seek; case SDLK_LEFT: incr = -10.0; goto do_seek; case SDLK_RIGHT: incr = 10.0; goto do_seek; case SDLK_UP: incr = 60.0; goto do_seek; case SDLK_DOWN: incr = -60.0; do_seek: if (seek_by_bytes) { if (cur_stream->video_stream >= 0 && cur_stream->video_current_pos >= 0) { pos = cur_stream->video_current_pos; } else if (cur_stream->audio_stream >= 0 && cur_stream->audio_pkt.pos >= 0) { pos = cur_stream->audio_pkt.pos; } else pos = avio_tell(cur_stream->ic->pb); if (cur_stream->ic->bit_rate) incr *= cur_stream->ic->bit_rate / 8.0; else incr *= 180000.0; pos += incr; stream_seek(cur_stream, pos, incr, 1); } else { pos = get_master_clock(cur_stream); if (isnan(pos)) pos = (double)cur_stream->seek_pos / AV_TIME_BASE; pos += incr; if (cur_stream->ic->start_time != AV_NOPTS_VALUE && pos < cur_stream->ic->start_time / (double)AV_TIME_BASE) pos = cur_stream->ic->start_time / (double)AV_TIME_BASE; stream_seek(cur_stream, (int64_t)(pos * AV_TIME_BASE), (int64_t)(incr * AV_TIME_BASE), 0); } break; default: break; } break; case SDL_VIDEOEXPOSE: cur_stream->force_refresh = 1; break; case SDL_MOUSEBUTTONDOWN: if (exit_on_mousedown) { do_exit(cur_stream); break; } case SDL_MOUSEMOTION: if (cursor_hidden) { SDL_ShowCursor(1); cursor_hidden = 0; } cursor_last_shown = av_gettime(); if (event.type == SDL_MOUSEBUTTONDOWN) { x = event.button.x; } else { if (event.motion.state != SDL_PRESSED) break; x = event.motion.x; } if (seek_by_bytes || cur_stream->ic->duration <= 0) { uint64_t size = avio_size(cur_stream->ic->pb); stream_seek(cur_stream, size*x/cur_stream->width, 0, 1); } else { int64_t ts; int ns, hh, mm, ss; int tns, thh, tmm, tss; tns = cur_stream->ic->duration / 1000000LL; thh = tns / 3600; tmm = (tns % 3600) / 60; tss = (tns % 60); frac = x / cur_stream->width; ns = frac * tns; hh = ns / 3600; mm = (ns % 3600) / 60; ss = (ns % 60); fprintf(stderr, "Seek to %2.0f%% (%2d:%02d:%02d) of total duration (%2d:%02d:%02d) \n", frac*100, hh, mm, ss, thh, tmm, tss); ts = frac * cur_stream->ic->duration; if (cur_stream->ic->start_time != AV_NOPTS_VALUE) ts += cur_stream->ic->start_time; stream_seek(cur_stream, ts, 0, 0); } break; case SDL_VIDEORESIZE: screen = SDL_SetVideoMode(event.resize.w, event.resize.h, 0, SDL_HWSURFACE|SDL_RESIZABLE|SDL_ASYNCBLIT|SDL_HWACCEL); screen_width = cur_stream->width = event.resize.w; screen_height = cur_stream->height = event.resize.h; cur_stream->force_refresh = 1; break; case SDL_QUIT: case FF_QUIT_EVENT: do_exit(cur_stream); break; case FF_ALLOC_EVENT: alloc_picture(event.user.data1); break; default: break; } } }
true
FFmpeg
87917a328320ce77992ed4d87d8825c7216f6f32
static void event_loop(VideoState *cur_stream) { SDL_Event event; double incr, pos, frac; for (;;) { double x; refresh_loop_wait_event(cur_stream, &event); switch (event.type) { case SDL_KEYDOWN: if (exit_on_keydown) { do_exit(cur_stream); break; } switch (event.key.keysym.sym) { case SDLK_ESCAPE: case SDLK_q: do_exit(cur_stream); break; case SDLK_f: toggle_full_screen(cur_stream); cur_stream->force_refresh = 1; break; case SDLK_p: case SDLK_SPACE: toggle_pause(cur_stream); break; case SDLK_s: step_to_next_frame(cur_stream); break; case SDLK_a: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_AUDIO); break; case SDLK_v: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_VIDEO); break; case SDLK_t: stream_cycle_channel(cur_stream, AVMEDIA_TYPE_SUBTITLE); break; case SDLK_w: toggle_audio_display(cur_stream); break; case SDLK_PAGEUP: incr = 600.0; goto do_seek; case SDLK_PAGEDOWN: incr = -600.0; goto do_seek; case SDLK_LEFT: incr = -10.0; goto do_seek; case SDLK_RIGHT: incr = 10.0; goto do_seek; case SDLK_UP: incr = 60.0; goto do_seek; case SDLK_DOWN: incr = -60.0; do_seek: if (seek_by_bytes) { if (cur_stream->video_stream >= 0 && cur_stream->video_current_pos >= 0) { pos = cur_stream->video_current_pos; } else if (cur_stream->audio_stream >= 0 && cur_stream->audio_pkt.pos >= 0) { pos = cur_stream->audio_pkt.pos; } else pos = avio_tell(cur_stream->ic->pb); if (cur_stream->ic->bit_rate) incr *= cur_stream->ic->bit_rate / 8.0; else incr *= 180000.0; pos += incr; stream_seek(cur_stream, pos, incr, 1); } else { pos = get_master_clock(cur_stream); if (isnan(pos)) pos = (double)cur_stream->seek_pos / AV_TIME_BASE; pos += incr; if (cur_stream->ic->start_time != AV_NOPTS_VALUE && pos < cur_stream->ic->start_time / (double)AV_TIME_BASE) pos = cur_stream->ic->start_time / (double)AV_TIME_BASE; stream_seek(cur_stream, (int64_t)(pos * AV_TIME_BASE), (int64_t)(incr * AV_TIME_BASE), 0); } break; default: break; } break; case SDL_VIDEOEXPOSE: cur_stream->force_refresh = 1; break; case SDL_MOUSEBUTTONDOWN: if (exit_on_mousedown) { do_exit(cur_stream); break; } case SDL_MOUSEMOTION: if (cursor_hidden) { SDL_ShowCursor(1); cursor_hidden = 0; } cursor_last_shown = av_gettime(); if (event.type == SDL_MOUSEBUTTONDOWN) { x = event.button.x; } else { if (event.motion.state != SDL_PRESSED) break; x = event.motion.x; } if (seek_by_bytes || cur_stream->ic->duration <= 0) { uint64_t size = avio_size(cur_stream->ic->pb); stream_seek(cur_stream, size*x/cur_stream->width, 0, 1); } else { int64_t ts; int ns, hh, mm, ss; int tns, thh, tmm, tss; tns = cur_stream->ic->duration / 1000000LL; thh = tns / 3600; tmm = (tns % 3600) / 60; tss = (tns % 60); frac = x / cur_stream->width; ns = frac * tns; hh = ns / 3600; mm = (ns % 3600) / 60; ss = (ns % 60); fprintf(stderr, "Seek to %2.0f%% (%2d:%02d:%02d) of total duration (%2d:%02d:%02d) \n", frac*100, hh, mm, ss, thh, tmm, tss); ts = frac * cur_stream->ic->duration; if (cur_stream->ic->start_time != AV_NOPTS_VALUE) ts += cur_stream->ic->start_time; stream_seek(cur_stream, ts, 0, 0); } break; case SDL_VIDEORESIZE: screen = SDL_SetVideoMode(event.resize.w, event.resize.h, 0, SDL_HWSURFACE|SDL_RESIZABLE|SDL_ASYNCBLIT|SDL_HWACCEL); screen_width = cur_stream->width = event.resize.w; screen_height = cur_stream->height = event.resize.h; cur_stream->force_refresh = 1; break; case SDL_QUIT: case FF_QUIT_EVENT: do_exit(cur_stream); break; case FF_ALLOC_EVENT: alloc_picture(event.user.data1); break; default: break; } } }
{ "code": [ " screen = SDL_SetVideoMode(event.resize.w, event.resize.h, 0,", " screen_width = cur_stream->width = event.resize.w;", " screen_height = cur_stream->height = event.resize.h;" ], "line_no": [ 267, 271, 273 ] }
static void FUNC_0(VideoState *VAR_0) { SDL_Event event; double VAR_1, VAR_2, VAR_3; for (;;) { double VAR_4; refresh_loop_wait_event(VAR_0, &event); switch (event.type) { case SDL_KEYDOWN: if (exit_on_keydown) { do_exit(VAR_0); break; } switch (event.key.keysym.sym) { case SDLK_ESCAPE: case SDLK_q: do_exit(VAR_0); break; case SDLK_f: toggle_full_screen(VAR_0); VAR_0->force_refresh = 1; break; case SDLK_p: case SDLK_SPACE: toggle_pause(VAR_0); break; case SDLK_s: step_to_next_frame(VAR_0); break; case SDLK_a: stream_cycle_channel(VAR_0, AVMEDIA_TYPE_AUDIO); break; case SDLK_v: stream_cycle_channel(VAR_0, AVMEDIA_TYPE_VIDEO); break; case SDLK_t: stream_cycle_channel(VAR_0, AVMEDIA_TYPE_SUBTITLE); break; case SDLK_w: toggle_audio_display(VAR_0); break; case SDLK_PAGEUP: VAR_1 = 600.0; goto do_seek; case SDLK_PAGEDOWN: VAR_1 = -600.0; goto do_seek; case SDLK_LEFT: VAR_1 = -10.0; goto do_seek; case SDLK_RIGHT: VAR_1 = 10.0; goto do_seek; case SDLK_UP: VAR_1 = 60.0; goto do_seek; case SDLK_DOWN: VAR_1 = -60.0; do_seek: if (seek_by_bytes) { if (VAR_0->video_stream >= 0 && VAR_0->video_current_pos >= 0) { VAR_2 = VAR_0->video_current_pos; } else if (VAR_0->audio_stream >= 0 && VAR_0->audio_pkt.VAR_2 >= 0) { VAR_2 = VAR_0->audio_pkt.VAR_2; } else VAR_2 = avio_tell(VAR_0->ic->pb); if (VAR_0->ic->bit_rate) VAR_1 *= VAR_0->ic->bit_rate / 8.0; else VAR_1 *= 180000.0; VAR_2 += VAR_1; stream_seek(VAR_0, VAR_2, VAR_1, 1); } else { VAR_2 = get_master_clock(VAR_0); if (isnan(VAR_2)) VAR_2 = (double)VAR_0->seek_pos / AV_TIME_BASE; VAR_2 += VAR_1; if (VAR_0->ic->start_time != AV_NOPTS_VALUE && VAR_2 < VAR_0->ic->start_time / (double)AV_TIME_BASE) VAR_2 = VAR_0->ic->start_time / (double)AV_TIME_BASE; stream_seek(VAR_0, (int64_t)(VAR_2 * AV_TIME_BASE), (int64_t)(VAR_1 * AV_TIME_BASE), 0); } break; default: break; } break; case SDL_VIDEOEXPOSE: VAR_0->force_refresh = 1; break; case SDL_MOUSEBUTTONDOWN: if (exit_on_mousedown) { do_exit(VAR_0); break; } case SDL_MOUSEMOTION: if (cursor_hidden) { SDL_ShowCursor(1); cursor_hidden = 0; } cursor_last_shown = av_gettime(); if (event.type == SDL_MOUSEBUTTONDOWN) { VAR_4 = event.button.VAR_4; } else { if (event.motion.state != SDL_PRESSED) break; VAR_4 = event.motion.VAR_4; } if (seek_by_bytes || VAR_0->ic->duration <= 0) { uint64_t size = avio_size(VAR_0->ic->pb); stream_seek(VAR_0, size*VAR_4/VAR_0->width, 0, 1); } else { int64_t ts; int VAR_5, VAR_6, VAR_7, VAR_8; int VAR_9, VAR_10, VAR_11, VAR_12; VAR_9 = VAR_0->ic->duration / 1000000LL; VAR_10 = VAR_9 / 3600; VAR_11 = (VAR_9 % 3600) / 60; VAR_12 = (VAR_9 % 60); VAR_3 = VAR_4 / VAR_0->width; VAR_5 = VAR_3 * VAR_9; VAR_6 = VAR_5 / 3600; VAR_7 = (VAR_5 % 3600) / 60; VAR_8 = (VAR_5 % 60); fprintf(stderr, "Seek to %2.0f%% (%2d:%02d:%02d) of total duration (%2d:%02d:%02d) \n", VAR_3*100, VAR_6, VAR_7, VAR_8, VAR_10, VAR_11, VAR_12); ts = VAR_3 * VAR_0->ic->duration; if (VAR_0->ic->start_time != AV_NOPTS_VALUE) ts += VAR_0->ic->start_time; stream_seek(VAR_0, ts, 0, 0); } break; case SDL_VIDEORESIZE: screen = SDL_SetVideoMode(event.resize.w, event.resize.h, 0, SDL_HWSURFACE|SDL_RESIZABLE|SDL_ASYNCBLIT|SDL_HWACCEL); screen_width = VAR_0->width = event.resize.w; screen_height = VAR_0->height = event.resize.h; VAR_0->force_refresh = 1; break; case SDL_QUIT: case FF_QUIT_EVENT: do_exit(VAR_0); break; case FF_ALLOC_EVENT: alloc_picture(event.user.data1); break; default: break; } } }
[ "static void FUNC_0(VideoState *VAR_0)\n{", "SDL_Event event;", "double VAR_1, VAR_2, VAR_3;", "for (;;) {", "double VAR_4;", "refresh_loop_wait_event(VAR_0, &event);", "switch (event.type) {", "case SDL_KEYDOWN:\nif (exit_on_keydown) {", "do_exit(VAR_0);", "break;", "}", "switch (event.key.keysym.sym) {", "case SDLK_ESCAPE:\ncase SDLK_q:\ndo_exit(VAR_0);", "break;", "case SDLK_f:\ntoggle_full_screen(VAR_0);", "VAR_0->force_refresh = 1;", "break;", "case SDLK_p:\ncase SDLK_SPACE:\ntoggle_pause(VAR_0);", "break;", "case SDLK_s:\nstep_to_next_frame(VAR_0);", "break;", "case SDLK_a:\nstream_cycle_channel(VAR_0, AVMEDIA_TYPE_AUDIO);", "break;", "case SDLK_v:\nstream_cycle_channel(VAR_0, AVMEDIA_TYPE_VIDEO);", "break;", "case SDLK_t:\nstream_cycle_channel(VAR_0, AVMEDIA_TYPE_SUBTITLE);", "break;", "case SDLK_w:\ntoggle_audio_display(VAR_0);", "break;", "case SDLK_PAGEUP:\nVAR_1 = 600.0;", "goto do_seek;", "case SDLK_PAGEDOWN:\nVAR_1 = -600.0;", "goto do_seek;", "case SDLK_LEFT:\nVAR_1 = -10.0;", "goto do_seek;", "case SDLK_RIGHT:\nVAR_1 = 10.0;", "goto do_seek;", "case SDLK_UP:\nVAR_1 = 60.0;", "goto do_seek;", "case SDLK_DOWN:\nVAR_1 = -60.0;", "do_seek:\nif (seek_by_bytes) {", "if (VAR_0->video_stream >= 0 && VAR_0->video_current_pos >= 0) {", "VAR_2 = VAR_0->video_current_pos;", "} else if (VAR_0->audio_stream >= 0 && VAR_0->audio_pkt.VAR_2 >= 0) {", "VAR_2 = VAR_0->audio_pkt.VAR_2;", "} else", "VAR_2 = avio_tell(VAR_0->ic->pb);", "if (VAR_0->ic->bit_rate)\nVAR_1 *= VAR_0->ic->bit_rate / 8.0;", "else\nVAR_1 *= 180000.0;", "VAR_2 += VAR_1;", "stream_seek(VAR_0, VAR_2, VAR_1, 1);", "} else {", "VAR_2 = get_master_clock(VAR_0);", "if (isnan(VAR_2))\nVAR_2 = (double)VAR_0->seek_pos / AV_TIME_BASE;", "VAR_2 += VAR_1;", "if (VAR_0->ic->start_time != AV_NOPTS_VALUE && VAR_2 < VAR_0->ic->start_time / (double)AV_TIME_BASE)\nVAR_2 = VAR_0->ic->start_time / (double)AV_TIME_BASE;", "stream_seek(VAR_0, (int64_t)(VAR_2 * AV_TIME_BASE), (int64_t)(VAR_1 * AV_TIME_BASE), 0);", "}", "break;", "default:\nbreak;", "}", "break;", "case SDL_VIDEOEXPOSE:\nVAR_0->force_refresh = 1;", "break;", "case SDL_MOUSEBUTTONDOWN:\nif (exit_on_mousedown) {", "do_exit(VAR_0);", "break;", "}", "case SDL_MOUSEMOTION:\nif (cursor_hidden) {", "SDL_ShowCursor(1);", "cursor_hidden = 0;", "}", "cursor_last_shown = av_gettime();", "if (event.type == SDL_MOUSEBUTTONDOWN) {", "VAR_4 = event.button.VAR_4;", "} else {", "if (event.motion.state != SDL_PRESSED)\nbreak;", "VAR_4 = event.motion.VAR_4;", "}", "if (seek_by_bytes || VAR_0->ic->duration <= 0) {", "uint64_t size = avio_size(VAR_0->ic->pb);", "stream_seek(VAR_0, size*VAR_4/VAR_0->width, 0, 1);", "} else {", "int64_t ts;", "int VAR_5, VAR_6, VAR_7, VAR_8;", "int VAR_9, VAR_10, VAR_11, VAR_12;", "VAR_9 = VAR_0->ic->duration / 1000000LL;", "VAR_10 = VAR_9 / 3600;", "VAR_11 = (VAR_9 % 3600) / 60;", "VAR_12 = (VAR_9 % 60);", "VAR_3 = VAR_4 / VAR_0->width;", "VAR_5 = VAR_3 * VAR_9;", "VAR_6 = VAR_5 / 3600;", "VAR_7 = (VAR_5 % 3600) / 60;", "VAR_8 = (VAR_5 % 60);", "fprintf(stderr, \"Seek to %2.0f%% (%2d:%02d:%02d) of total duration (%2d:%02d:%02d) \\n\", VAR_3*100,\nVAR_6, VAR_7, VAR_8, VAR_10, VAR_11, VAR_12);", "ts = VAR_3 * VAR_0->ic->duration;", "if (VAR_0->ic->start_time != AV_NOPTS_VALUE)\nts += VAR_0->ic->start_time;", "stream_seek(VAR_0, ts, 0, 0);", "}", "break;", "case SDL_VIDEORESIZE:\nscreen = SDL_SetVideoMode(event.resize.w, event.resize.h, 0,\nSDL_HWSURFACE|SDL_RESIZABLE|SDL_ASYNCBLIT|SDL_HWACCEL);", "screen_width = VAR_0->width = event.resize.w;", "screen_height = VAR_0->height = event.resize.h;", "VAR_0->force_refresh = 1;", "break;", "case SDL_QUIT:\ncase FF_QUIT_EVENT:\ndo_exit(VAR_0);", "break;", "case FF_ALLOC_EVENT:\nalloc_picture(event.user.data1);", "break;", "default:\nbreak;", "}", "}", "}" ]
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16,849
sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { SDHCIState *s = (SDHCIState *)opaque; unsigned shift = 8 * (offset & 0x3); uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); uint32_t value = val; value <<= shift; switch (offset & ~0x3) { case SDHC_SYSAD: s->sdmasysad = (s->sdmasysad & mask) | value; MASKED_WRITE(s->sdmasysad, mask, value); /* Writing to last byte of sdmasysad might trigger transfer */ if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { sdhci_sdma_transfer_multi_blocks(s); break; case SDHC_BLKSIZE: if (!TRANSFERRING_DATA(s->prnsts)) { MASKED_WRITE(s->blksize, mask, value); MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); break; case SDHC_ARGUMENT: MASKED_WRITE(s->argument, mask, value); break; case SDHC_TRNMOD: /* DMA can be enabled only if it is supported as indicated by * capabilities register */ if (!(s->capareg & SDHC_CAN_DO_DMA)) { value &= ~SDHC_TRNS_DMA; MASKED_WRITE(s->trnmod, mask, value); MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); /* Writing to the upper byte of CMDREG triggers SD command generation */ if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { break; sdhci_send_command(s); break; case SDHC_BDATA: if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { sdhci_write_dataport(s, value >> shift, size); break; case SDHC_HOSTCTL: if (!(mask & 0xFF0000)) { sdhci_blkgap_write(s, value >> 16); MASKED_WRITE(s->hostctl, mask, value); MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { s->pwrcon &= ~SDHC_POWER_ON; break; case SDHC_CLKCON: if (!(mask & 0xFF000000)) { sdhci_reset_write(s, value >> 24); MASKED_WRITE(s->clkcon, mask, value); MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); if (s->clkcon & SDHC_CLOCK_INT_EN) { s->clkcon |= SDHC_CLOCK_INT_STABLE; } else { s->clkcon &= ~SDHC_CLOCK_INT_STABLE; break; case SDHC_NORINTSTS: if (s->norintstsen & SDHC_NISEN_CARDINT) { value &= ~SDHC_NIS_CARDINT; s->norintsts &= mask | ~value; s->errintsts &= (mask >> 16) | ~(value >> 16); if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; } else { s->norintsts &= ~SDHC_NIS_ERR; sdhci_update_irq(s); break; case SDHC_NORINTSTSEN: MASKED_WRITE(s->norintstsen, mask, value); MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); s->norintsts &= s->norintstsen; s->errintsts &= s->errintstsen; if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; } else { s->norintsts &= ~SDHC_NIS_ERR; sdhci_update_irq(s); break; case SDHC_NORINTSIGEN: MASKED_WRITE(s->norintsigen, mask, value); MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); sdhci_update_irq(s); break; case SDHC_ADMAERR: MASKED_WRITE(s->admaerr, mask, value); break; case SDHC_ADMASYSADDR: s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | (uint64_t)mask)) | (uint64_t)value; break; case SDHC_ADMASYSADDR + 4: s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | ((uint64_t)mask << 32))) | ((uint64_t)value << 32); break; case SDHC_FEAER: s->acmd12errsts |= value; s->errintsts |= (value >> 16) & s->errintstsen; if (s->acmd12errsts) { s->errintsts |= SDHC_EIS_CMD12ERR; if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; sdhci_update_irq(s); break; default: ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", size, (int)offset, value >> shift, value >> shift); break; DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", size, (int)offset, value >> shift, value >> shift);
true
qemu
9201bb9a8c7cd3ba2382b7db5b2e40f603e61528
sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { SDHCIState *s = (SDHCIState *)opaque; unsigned shift = 8 * (offset & 0x3); uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); uint32_t value = val; value <<= shift; switch (offset & ~0x3) { case SDHC_SYSAD: s->sdmasysad = (s->sdmasysad & mask) | value; MASKED_WRITE(s->sdmasysad, mask, value); if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { sdhci_sdma_transfer_multi_blocks(s); break; case SDHC_BLKSIZE: if (!TRANSFERRING_DATA(s->prnsts)) { MASKED_WRITE(s->blksize, mask, value); MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); break; case SDHC_ARGUMENT: MASKED_WRITE(s->argument, mask, value); break; case SDHC_TRNMOD: if (!(s->capareg & SDHC_CAN_DO_DMA)) { value &= ~SDHC_TRNS_DMA; MASKED_WRITE(s->trnmod, mask, value); MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { break; sdhci_send_command(s); break; case SDHC_BDATA: if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { sdhci_write_dataport(s, value >> shift, size); break; case SDHC_HOSTCTL: if (!(mask & 0xFF0000)) { sdhci_blkgap_write(s, value >> 16); MASKED_WRITE(s->hostctl, mask, value); MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { s->pwrcon &= ~SDHC_POWER_ON; break; case SDHC_CLKCON: if (!(mask & 0xFF000000)) { sdhci_reset_write(s, value >> 24); MASKED_WRITE(s->clkcon, mask, value); MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); if (s->clkcon & SDHC_CLOCK_INT_EN) { s->clkcon |= SDHC_CLOCK_INT_STABLE; } else { s->clkcon &= ~SDHC_CLOCK_INT_STABLE; break; case SDHC_NORINTSTS: if (s->norintstsen & SDHC_NISEN_CARDINT) { value &= ~SDHC_NIS_CARDINT; s->norintsts &= mask | ~value; s->errintsts &= (mask >> 16) | ~(value >> 16); if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; } else { s->norintsts &= ~SDHC_NIS_ERR; sdhci_update_irq(s); break; case SDHC_NORINTSTSEN: MASKED_WRITE(s->norintstsen, mask, value); MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); s->norintsts &= s->norintstsen; s->errintsts &= s->errintstsen; if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; } else { s->norintsts &= ~SDHC_NIS_ERR; sdhci_update_irq(s); break; case SDHC_NORINTSIGEN: MASKED_WRITE(s->norintsigen, mask, value); MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); sdhci_update_irq(s); break; case SDHC_ADMAERR: MASKED_WRITE(s->admaerr, mask, value); break; case SDHC_ADMASYSADDR: s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | (uint64_t)mask)) | (uint64_t)value; break; case SDHC_ADMASYSADDR + 4: s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | ((uint64_t)mask << 32))) | ((uint64_t)value << 32); break; case SDHC_FEAER: s->acmd12errsts |= value; s->errintsts |= (value >> 16) & s->errintstsen; if (s->acmd12errsts) { s->errintsts |= SDHC_EIS_CMD12ERR; if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; sdhci_update_irq(s); break; default: ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", size, (int)offset, value >> shift, value >> shift); break; DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", size, (int)offset, value >> shift, value >> shift);
{ "code": [], "line_no": [] }
FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2, unsigned VAR_3) { SDHCIState *s = (SDHCIState *)VAR_0; unsigned VAR_4 = 8 * (VAR_1 & 0x3); uint32_t mask = ~(((1ULL << (VAR_3 * 8)) - 1) << VAR_4); uint32_t value = VAR_2; value <<= VAR_4; switch (VAR_1 & ~0x3) { case SDHC_SYSAD: s->sdmasysad = (s->sdmasysad & mask) | value; MASKED_WRITE(s->sdmasysad, mask, value); if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { sdhci_sdma_transfer_multi_blocks(s); break; case SDHC_BLKSIZE: if (!TRANSFERRING_DATA(s->prnsts)) { MASKED_WRITE(s->blksize, mask, value); MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); break; case SDHC_ARGUMENT: MASKED_WRITE(s->argument, mask, value); break; case SDHC_TRNMOD: if (!(s->capareg & SDHC_CAN_DO_DMA)) { value &= ~SDHC_TRNS_DMA; MASKED_WRITE(s->trnmod, mask, value); MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { break; sdhci_send_command(s); break; case SDHC_BDATA: if (sdhci_buff_access_is_sequential(s, VAR_1 - SDHC_BDATA)) { sdhci_write_dataport(s, value >> VAR_4, VAR_3); break; case SDHC_HOSTCTL: if (!(mask & 0xFF0000)) { sdhci_blkgap_write(s, value >> 16); MASKED_WRITE(s->hostctl, mask, value); MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { s->pwrcon &= ~SDHC_POWER_ON; break; case SDHC_CLKCON: if (!(mask & 0xFF000000)) { sdhci_reset_write(s, value >> 24); MASKED_WRITE(s->clkcon, mask, value); MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); if (s->clkcon & SDHC_CLOCK_INT_EN) { s->clkcon |= SDHC_CLOCK_INT_STABLE; } else { s->clkcon &= ~SDHC_CLOCK_INT_STABLE; break; case SDHC_NORINTSTS: if (s->norintstsen & SDHC_NISEN_CARDINT) { value &= ~SDHC_NIS_CARDINT; s->norintsts &= mask | ~value; s->errintsts &= (mask >> 16) | ~(value >> 16); if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; } else { s->norintsts &= ~SDHC_NIS_ERR; sdhci_update_irq(s); break; case SDHC_NORINTSTSEN: MASKED_WRITE(s->norintstsen, mask, value); MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); s->norintsts &= s->norintstsen; s->errintsts &= s->errintstsen; if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; } else { s->norintsts &= ~SDHC_NIS_ERR; sdhci_update_irq(s); break; case SDHC_NORINTSIGEN: MASKED_WRITE(s->norintsigen, mask, value); MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); sdhci_update_irq(s); break; case SDHC_ADMAERR: MASKED_WRITE(s->admaerr, mask, value); break; case SDHC_ADMASYSADDR: s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | (uint64_t)mask)) | (uint64_t)value; break; case SDHC_ADMASYSADDR + 4: s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | ((uint64_t)mask << 32))) | ((uint64_t)value << 32); break; case SDHC_FEAER: s->acmd12errsts |= value; s->errintsts |= (value >> 16) & s->errintstsen; if (s->acmd12errsts) { s->errintsts |= SDHC_EIS_CMD12ERR; if (s->errintsts) { s->norintsts |= SDHC_NIS_ERR; sdhci_update_irq(s); break; default: ERRPRINT("bad %ub write VAR_1: addr[0x%04x] <- %u(0x%x)\n", VAR_3, (int)VAR_1, value >> VAR_4, value >> VAR_4); break; DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", VAR_3, (int)VAR_1, value >> VAR_4, value >> VAR_4);
[ "FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2, unsigned VAR_3)\n{", "SDHCIState *s = (SDHCIState *)VAR_0;", "unsigned VAR_4 = 8 * (VAR_1 & 0x3);", "uint32_t mask = ~(((1ULL << (VAR_3 * 8)) - 1) << VAR_4);", "uint32_t value = VAR_2;", "value <<= VAR_4;", "switch (VAR_1 & ~0x3) {", "case SDHC_SYSAD:\ns->sdmasysad = (s->sdmasysad & mask) | value;", "MASKED_WRITE(s->sdmasysad, mask, value);", "if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&\ns->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {", "sdhci_sdma_transfer_multi_blocks(s);", "break;", "case SDHC_BLKSIZE:\nif (!TRANSFERRING_DATA(s->prnsts)) {", "MASKED_WRITE(s->blksize, mask, value);", "MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);", "break;", "case SDHC_ARGUMENT:\nMASKED_WRITE(s->argument, mask, value);", "break;", "case SDHC_TRNMOD:\nif (!(s->capareg & SDHC_CAN_DO_DMA)) {", "value &= ~SDHC_TRNS_DMA;", "MASKED_WRITE(s->trnmod, mask, value);", "MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);", "if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {", "break;", "sdhci_send_command(s);", "break;", "case SDHC_BDATA:\nif (sdhci_buff_access_is_sequential(s, VAR_1 - SDHC_BDATA)) {", "sdhci_write_dataport(s, value >> VAR_4, VAR_3);", "break;", "case SDHC_HOSTCTL:\nif (!(mask & 0xFF0000)) {", "sdhci_blkgap_write(s, value >> 16);", "MASKED_WRITE(s->hostctl, mask, value);", "MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);", "MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);", "if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||\n!(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {", "s->pwrcon &= ~SDHC_POWER_ON;", "break;", "case SDHC_CLKCON:\nif (!(mask & 0xFF000000)) {", "sdhci_reset_write(s, value >> 24);", "MASKED_WRITE(s->clkcon, mask, value);", "MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);", "if (s->clkcon & SDHC_CLOCK_INT_EN) {", "s->clkcon |= SDHC_CLOCK_INT_STABLE;", "} else {", "s->clkcon &= ~SDHC_CLOCK_INT_STABLE;", "break;", "case SDHC_NORINTSTS:\nif (s->norintstsen & SDHC_NISEN_CARDINT) {", "value &= ~SDHC_NIS_CARDINT;", "s->norintsts &= mask | ~value;", "s->errintsts &= (mask >> 16) | ~(value >> 16);", "if (s->errintsts) {", "s->norintsts |= SDHC_NIS_ERR;", "} else {", "s->norintsts &= ~SDHC_NIS_ERR;", "sdhci_update_irq(s);", "break;", "case SDHC_NORINTSTSEN:\nMASKED_WRITE(s->norintstsen, mask, value);", "MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);", "s->norintsts &= s->norintstsen;", "s->errintsts &= s->errintstsen;", "if (s->errintsts) {", "s->norintsts |= SDHC_NIS_ERR;", "} else {", "s->norintsts &= ~SDHC_NIS_ERR;", "sdhci_update_irq(s);", "break;", "case SDHC_NORINTSIGEN:\nMASKED_WRITE(s->norintsigen, mask, value);", "MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);", "sdhci_update_irq(s);", "break;", "case SDHC_ADMAERR:\nMASKED_WRITE(s->admaerr, mask, value);", "break;", "case SDHC_ADMASYSADDR:\ns->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |\n(uint64_t)mask)) | (uint64_t)value;", "break;", "case SDHC_ADMASYSADDR + 4:\ns->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |\n((uint64_t)mask << 32))) | ((uint64_t)value << 32);", "break;", "case SDHC_FEAER:\ns->acmd12errsts |= value;", "s->errintsts |= (value >> 16) & s->errintstsen;", "if (s->acmd12errsts) {", "s->errintsts |= SDHC_EIS_CMD12ERR;", "if (s->errintsts) {", "s->norintsts |= SDHC_NIS_ERR;", "sdhci_update_irq(s);", "break;", "default:\nERRPRINT(\"bad %ub write VAR_1: addr[0x%04x] <- %u(0x%x)\\n\",\nVAR_3, (int)VAR_1, value >> VAR_4, value >> VAR_4);", "break;", "DPRINT_L2(\"write %ub: addr[0x%04x] <- %u(0x%x)\\n\",\nVAR_3, (int)VAR_1, value >> VAR_4, value >> VAR_4);" ]
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16,851
static void filter_samples(AVFilterLink *inlink, AVFilterBufferRef *buf) { AVFilterContext *ctx = inlink->dst; ASyncContext *s = ctx->priv; AVFilterLink *outlink = ctx->outputs[0]; int nb_channels = av_get_channel_layout_nb_channels(buf->audio->channel_layout); int64_t pts = (buf->pts == AV_NOPTS_VALUE) ? buf->pts : av_rescale_q(buf->pts, inlink->time_base, outlink->time_base); int out_size; int64_t delta; /* buffer data until we get the first timestamp */ if (s->pts == AV_NOPTS_VALUE) { if (pts != AV_NOPTS_VALUE) { s->pts = pts - get_delay(s); } write_to_fifo(s, buf); return; } /* now wait for the next timestamp */ if (pts == AV_NOPTS_VALUE) { write_to_fifo(s, buf); return; } /* when we have two timestamps, compute how many samples would we have * to add/remove to get proper sync between data and timestamps */ delta = pts - s->pts - get_delay(s); out_size = avresample_available(s->avr); if (labs(delta) > s->min_delta) { av_log(ctx, AV_LOG_VERBOSE, "Discontinuity - %"PRId64" samples.\n", delta); out_size += delta; } else if (s->resample) { int comp = av_clip(delta, -s->max_comp, s->max_comp); av_log(ctx, AV_LOG_VERBOSE, "Compensating %d samples per second.\n", comp); avresample_set_compensation(s->avr, delta, inlink->sample_rate); } if (out_size > 0) { AVFilterBufferRef *buf_out = ff_get_audio_buffer(outlink, AV_PERM_WRITE, out_size); if (!buf_out) return; avresample_read(s->avr, (void**)buf_out->extended_data, out_size); buf_out->pts = s->pts; if (delta > 0) { av_samples_set_silence(buf_out->extended_data, out_size - delta, delta, nb_channels, buf->format); } ff_filter_samples(outlink, buf_out); } else { av_log(ctx, AV_LOG_WARNING, "Non-monotonous timestamps, dropping " "whole buffer.\n"); } /* drain any remaining buffered data */ avresample_read(s->avr, NULL, avresample_available(s->avr)); s->pts = pts - avresample_get_delay(s->avr); avresample_convert(s->avr, NULL, 0, 0, (void**)buf->extended_data, buf->linesize[0], buf->audio->nb_samples); avfilter_unref_buffer(buf); }
true
FFmpeg
f297dd3812510fc83080e265dc4534a3898005b0
static void filter_samples(AVFilterLink *inlink, AVFilterBufferRef *buf) { AVFilterContext *ctx = inlink->dst; ASyncContext *s = ctx->priv; AVFilterLink *outlink = ctx->outputs[0]; int nb_channels = av_get_channel_layout_nb_channels(buf->audio->channel_layout); int64_t pts = (buf->pts == AV_NOPTS_VALUE) ? buf->pts : av_rescale_q(buf->pts, inlink->time_base, outlink->time_base); int out_size; int64_t delta; if (s->pts == AV_NOPTS_VALUE) { if (pts != AV_NOPTS_VALUE) { s->pts = pts - get_delay(s); } write_to_fifo(s, buf); return; } if (pts == AV_NOPTS_VALUE) { write_to_fifo(s, buf); return; } delta = pts - s->pts - get_delay(s); out_size = avresample_available(s->avr); if (labs(delta) > s->min_delta) { av_log(ctx, AV_LOG_VERBOSE, "Discontinuity - %"PRId64" samples.\n", delta); out_size += delta; } else if (s->resample) { int comp = av_clip(delta, -s->max_comp, s->max_comp); av_log(ctx, AV_LOG_VERBOSE, "Compensating %d samples per second.\n", comp); avresample_set_compensation(s->avr, delta, inlink->sample_rate); } if (out_size > 0) { AVFilterBufferRef *buf_out = ff_get_audio_buffer(outlink, AV_PERM_WRITE, out_size); if (!buf_out) return; avresample_read(s->avr, (void**)buf_out->extended_data, out_size); buf_out->pts = s->pts; if (delta > 0) { av_samples_set_silence(buf_out->extended_data, out_size - delta, delta, nb_channels, buf->format); } ff_filter_samples(outlink, buf_out); } else { av_log(ctx, AV_LOG_WARNING, "Non-monotonous timestamps, dropping " "whole buffer.\n"); } avresample_read(s->avr, NULL, avresample_available(s->avr)); s->pts = pts - avresample_get_delay(s->avr); avresample_convert(s->avr, NULL, 0, 0, (void**)buf->extended_data, buf->linesize[0], buf->audio->nb_samples); avfilter_unref_buffer(buf); }
{ "code": [ " } else if (s->resample) {", " int comp = av_clip(delta, -s->max_comp, s->max_comp);", " av_log(ctx, AV_LOG_VERBOSE, \"Compensating %d samples per second.\\n\", comp);", " avresample_set_compensation(s->avr, delta, inlink->sample_rate);" ], "line_no": [ 69, 71, 73, 75 ] }
static void FUNC_0(AVFilterLink *VAR_0, AVFilterBufferRef *VAR_1) { AVFilterContext *ctx = VAR_0->dst; ASyncContext *s = ctx->priv; AVFilterLink *outlink = ctx->outputs[0]; int VAR_2 = av_get_channel_layout_nb_channels(VAR_1->audio->channel_layout); int64_t pts = (VAR_1->pts == AV_NOPTS_VALUE) ? VAR_1->pts : av_rescale_q(VAR_1->pts, VAR_0->time_base, outlink->time_base); int VAR_3; int64_t delta; if (s->pts == AV_NOPTS_VALUE) { if (pts != AV_NOPTS_VALUE) { s->pts = pts - get_delay(s); } write_to_fifo(s, VAR_1); return; } if (pts == AV_NOPTS_VALUE) { write_to_fifo(s, VAR_1); return; } delta = pts - s->pts - get_delay(s); VAR_3 = avresample_available(s->avr); if (labs(delta) > s->min_delta) { av_log(ctx, AV_LOG_VERBOSE, "Discontinuity - %"PRId64" samples.\n", delta); VAR_3 += delta; } else if (s->resample) { int VAR_4 = av_clip(delta, -s->max_comp, s->max_comp); av_log(ctx, AV_LOG_VERBOSE, "Compensating %d samples per second.\n", VAR_4); avresample_set_compensation(s->avr, delta, VAR_0->sample_rate); } if (VAR_3 > 0) { AVFilterBufferRef *buf_out = ff_get_audio_buffer(outlink, AV_PERM_WRITE, VAR_3); if (!buf_out) return; avresample_read(s->avr, (void**)buf_out->extended_data, VAR_3); buf_out->pts = s->pts; if (delta > 0) { av_samples_set_silence(buf_out->extended_data, VAR_3 - delta, delta, VAR_2, VAR_1->format); } ff_filter_samples(outlink, buf_out); } else { av_log(ctx, AV_LOG_WARNING, "Non-monotonous timestamps, dropping " "whole buffer.\n"); } avresample_read(s->avr, NULL, avresample_available(s->avr)); s->pts = pts - avresample_get_delay(s->avr); avresample_convert(s->avr, NULL, 0, 0, (void**)VAR_1->extended_data, VAR_1->linesize[0], VAR_1->audio->nb_samples); avfilter_unref_buffer(VAR_1); }
[ "static void FUNC_0(AVFilterLink *VAR_0, AVFilterBufferRef *VAR_1)\n{", "AVFilterContext *ctx = VAR_0->dst;", "ASyncContext *s = ctx->priv;", "AVFilterLink *outlink = ctx->outputs[0];", "int VAR_2 = av_get_channel_layout_nb_channels(VAR_1->audio->channel_layout);", "int64_t pts = (VAR_1->pts == AV_NOPTS_VALUE) ? VAR_1->pts :\nav_rescale_q(VAR_1->pts, VAR_0->time_base, outlink->time_base);", "int VAR_3;", "int64_t delta;", "if (s->pts == AV_NOPTS_VALUE) {", "if (pts != AV_NOPTS_VALUE) {", "s->pts = pts - get_delay(s);", "}", "write_to_fifo(s, VAR_1);", "return;", "}", "if (pts == AV_NOPTS_VALUE) {", "write_to_fifo(s, VAR_1);", "return;", "}", "delta = pts - s->pts - get_delay(s);", "VAR_3 = avresample_available(s->avr);", "if (labs(delta) > s->min_delta) {", "av_log(ctx, AV_LOG_VERBOSE, \"Discontinuity - %\"PRId64\" samples.\\n\", delta);", "VAR_3 += delta;", "} else if (s->resample) {", "int VAR_4 = av_clip(delta, -s->max_comp, s->max_comp);", "av_log(ctx, AV_LOG_VERBOSE, \"Compensating %d samples per second.\\n\", VAR_4);", "avresample_set_compensation(s->avr, delta, VAR_0->sample_rate);", "}", "if (VAR_3 > 0) {", "AVFilterBufferRef *buf_out = ff_get_audio_buffer(outlink, AV_PERM_WRITE,\nVAR_3);", "if (!buf_out)\nreturn;", "avresample_read(s->avr, (void**)buf_out->extended_data, VAR_3);", "buf_out->pts = s->pts;", "if (delta > 0) {", "av_samples_set_silence(buf_out->extended_data, VAR_3 - delta,\ndelta, VAR_2, VAR_1->format);", "}", "ff_filter_samples(outlink, buf_out);", "} else {", "av_log(ctx, AV_LOG_WARNING, \"Non-monotonous timestamps, dropping \"\n\"whole buffer.\\n\");", "}", "avresample_read(s->avr, NULL, avresample_available(s->avr));", "s->pts = pts - avresample_get_delay(s->avr);", "avresample_convert(s->avr, NULL, 0, 0, (void**)VAR_1->extended_data,\nVAR_1->linesize[0], VAR_1->audio->nb_samples);", "avfilter_unref_buffer(VAR_1);", "}" ]
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16,852
static void bmdma_irq(void *opaque, int n, int level) { BMDMAState *bm = opaque; if (!level) { /* pass through lower */ qemu_set_irq(bm->irq, level); return; } if (bm) { bm->status |= BM_STATUS_INT; } /* trigger the real irq */ qemu_set_irq(bm->irq, level); }
true
qemu
1635eecc413ed680013cf77e6994901cafe15590
static void bmdma_irq(void *opaque, int n, int level) { BMDMAState *bm = opaque; if (!level) { qemu_set_irq(bm->irq, level); return; } if (bm) { bm->status |= BM_STATUS_INT; } qemu_set_irq(bm->irq, level); }
{ "code": [ " if (bm) {", " bm->status |= BM_STATUS_INT;" ], "line_no": [ 21, 23 ] }
static void FUNC_0(void *VAR_0, int VAR_1, int VAR_2) { BMDMAState *bm = VAR_0; if (!VAR_2) { qemu_set_irq(bm->irq, VAR_2); return; } if (bm) { bm->status |= BM_STATUS_INT; } qemu_set_irq(bm->irq, VAR_2); }
[ "static void FUNC_0(void *VAR_0, int VAR_1, int VAR_2)\n{", "BMDMAState *bm = VAR_0;", "if (!VAR_2) {", "qemu_set_irq(bm->irq, VAR_2);", "return;", "}", "if (bm) {", "bm->status |= BM_STATUS_INT;", "}", "qemu_set_irq(bm->irq, VAR_2);", "}" ]
[ 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9 ], [ 13 ], [ 15 ], [ 17 ], [ 21 ], [ 23 ], [ 25 ], [ 31 ], [ 33 ] ]
16,853
iscsi_aio_cancel(BlockDriverAIOCB *blockacb) { IscsiAIOCB *acb = (IscsiAIOCB *)blockacb; IscsiLun *iscsilun = acb->iscsilun; acb->common.cb(acb->common.opaque, -ECANCELED); acb->canceled = 1; /* send a task mgmt call to the target to cancel the task on the target */ iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task, iscsi_abort_task_cb, NULL); /* then also cancel the task locally in libiscsi */ iscsi_scsi_task_cancel(iscsilun->iscsi, acb->task); }
true
qemu
64e69e80920d82df3fa679bc41b13770d2f99360
iscsi_aio_cancel(BlockDriverAIOCB *blockacb) { IscsiAIOCB *acb = (IscsiAIOCB *)blockacb; IscsiLun *iscsilun = acb->iscsilun; acb->common.cb(acb->common.opaque, -ECANCELED); acb->canceled = 1; iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task, iscsi_abort_task_cb, NULL); iscsi_scsi_task_cancel(iscsilun->iscsi, acb->task); }
{ "code": [ " acb->common.cb(acb->common.opaque, -ECANCELED);", " iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task,", " iscsi_abort_task_cb, NULL);", " iscsi_scsi_task_cancel(iscsilun->iscsi, acb->task);" ], "line_no": [ 11, 19, 21, 27 ] }
FUNC_0(BlockDriverAIOCB *VAR_0) { IscsiAIOCB *acb = (IscsiAIOCB *)VAR_0; IscsiLun *iscsilun = acb->iscsilun; acb->common.cb(acb->common.opaque, -ECANCELED); acb->canceled = 1; iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task, iscsi_abort_task_cb, NULL); iscsi_scsi_task_cancel(iscsilun->iscsi, acb->task); }
[ "FUNC_0(BlockDriverAIOCB *VAR_0)\n{", "IscsiAIOCB *acb = (IscsiAIOCB *)VAR_0;", "IscsiLun *iscsilun = acb->iscsilun;", "acb->common.cb(acb->common.opaque, -ECANCELED);", "acb->canceled = 1;", "iscsi_task_mgmt_abort_task_async(iscsilun->iscsi, acb->task,\niscsi_abort_task_cb, NULL);", "iscsi_scsi_task_cancel(iscsilun->iscsi, acb->task);", "}" ]
[ 0, 0, 0, 1, 0, 1, 1, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 11 ], [ 13 ], [ 19, 21 ], [ 27 ], [ 29 ] ]
16,854
static int rm_read_packet(AVFormatContext *s, AVPacket *pkt) { RMDemuxContext *rm = s->priv_data; AVStream *st; int i, len, res, seq = 1; int64_t timestamp, pos; int flags; for (;;) { if (rm->audio_pkt_cnt) { // If there are queued audio packet return them first st = s->streams[rm->audio_stream_num]; res = ff_rm_retrieve_cache(s, s->pb, st, st->priv_data, pkt); if(res < 0) return res; flags = 0; } else { if (rm->old_format) { RMStream *ast; st = s->streams[0]; ast = st->priv_data; timestamp = AV_NOPTS_VALUE; len = !ast->audio_framesize ? RAW_PACKET_SIZE : ast->coded_framesize * ast->sub_packet_h / 2; flags = (seq++ == 1) ? 2 : 0; pos = avio_tell(s->pb); } else { len=sync(s, &timestamp, &flags, &i, &pos); if (len > 0) st = s->streams[i]; } if(len<0 || url_feof(s->pb)) return AVERROR(EIO); res = ff_rm_parse_packet (s, s->pb, st, st->priv_data, len, pkt, &seq, flags, timestamp); if((flags&2) && (seq&0x7F) == 1) av_add_index_entry(st, pos, timestamp, 0, 0, AVINDEX_KEYFRAME); if (res) continue; } if( (st->discard >= AVDISCARD_NONKEY && !(flags&2)) || st->discard >= AVDISCARD_ALL){ av_free_packet(pkt); } else break; } return 0; }
true
FFmpeg
7fc73d9ab781f66b63f3bbe2f384f4f639ae78e9
static int rm_read_packet(AVFormatContext *s, AVPacket *pkt) { RMDemuxContext *rm = s->priv_data; AVStream *st; int i, len, res, seq = 1; int64_t timestamp, pos; int flags; for (;;) { if (rm->audio_pkt_cnt) { st = s->streams[rm->audio_stream_num]; res = ff_rm_retrieve_cache(s, s->pb, st, st->priv_data, pkt); if(res < 0) return res; flags = 0; } else { if (rm->old_format) { RMStream *ast; st = s->streams[0]; ast = st->priv_data; timestamp = AV_NOPTS_VALUE; len = !ast->audio_framesize ? RAW_PACKET_SIZE : ast->coded_framesize * ast->sub_packet_h / 2; flags = (seq++ == 1) ? 2 : 0; pos = avio_tell(s->pb); } else { len=sync(s, &timestamp, &flags, &i, &pos); if (len > 0) st = s->streams[i]; } if(len<0 || url_feof(s->pb)) return AVERROR(EIO); res = ff_rm_parse_packet (s, s->pb, st, st->priv_data, len, pkt, &seq, flags, timestamp); if((flags&2) && (seq&0x7F) == 1) av_add_index_entry(st, pos, timestamp, 0, 0, AVINDEX_KEYFRAME); if (res) continue; } if( (st->discard >= AVDISCARD_NONKEY && !(flags&2)) || st->discard >= AVDISCARD_ALL){ av_free_packet(pkt); } else break; } return 0; }
{ "code": [ " AVStream *st;" ], "line_no": [ 7 ] }
static int FUNC_0(AVFormatContext *VAR_0, AVPacket *VAR_1) { RMDemuxContext *rm = VAR_0->priv_data; AVStream *st; int VAR_2, VAR_3, VAR_4, VAR_5 = 1; int64_t timestamp, pos; int VAR_6; for (;;) { if (rm->audio_pkt_cnt) { st = VAR_0->streams[rm->audio_stream_num]; VAR_4 = ff_rm_retrieve_cache(VAR_0, VAR_0->pb, st, st->priv_data, VAR_1); if(VAR_4 < 0) return VAR_4; VAR_6 = 0; } else { if (rm->old_format) { RMStream *ast; st = VAR_0->streams[0]; ast = st->priv_data; timestamp = AV_NOPTS_VALUE; VAR_3 = !ast->audio_framesize ? RAW_PACKET_SIZE : ast->coded_framesize * ast->sub_packet_h / 2; VAR_6 = (VAR_5++ == 1) ? 2 : 0; pos = avio_tell(VAR_0->pb); } else { VAR_3=sync(VAR_0, &timestamp, &VAR_6, &VAR_2, &pos); if (VAR_3 > 0) st = VAR_0->streams[VAR_2]; } if(VAR_3<0 || url_feof(VAR_0->pb)) return AVERROR(EIO); VAR_4 = ff_rm_parse_packet (VAR_0, VAR_0->pb, st, st->priv_data, VAR_3, VAR_1, &VAR_5, VAR_6, timestamp); if((VAR_6&2) && (VAR_5&0x7F) == 1) av_add_index_entry(st, pos, timestamp, 0, 0, AVINDEX_KEYFRAME); if (VAR_4) continue; } if( (st->discard >= AVDISCARD_NONKEY && !(VAR_6&2)) || st->discard >= AVDISCARD_ALL){ av_free_packet(VAR_1); } else break; } return 0; }
[ "static int FUNC_0(AVFormatContext *VAR_0, AVPacket *VAR_1)\n{", "RMDemuxContext *rm = VAR_0->priv_data;", "AVStream *st;", "int VAR_2, VAR_3, VAR_4, VAR_5 = 1;", "int64_t timestamp, pos;", "int VAR_6;", "for (;;) {", "if (rm->audio_pkt_cnt) {", "st = VAR_0->streams[rm->audio_stream_num];", "VAR_4 = ff_rm_retrieve_cache(VAR_0, VAR_0->pb, st, st->priv_data, VAR_1);", "if(VAR_4 < 0)\nreturn VAR_4;", "VAR_6 = 0;", "} else {", "if (rm->old_format) {", "RMStream *ast;", "st = VAR_0->streams[0];", "ast = st->priv_data;", "timestamp = AV_NOPTS_VALUE;", "VAR_3 = !ast->audio_framesize ? RAW_PACKET_SIZE :\nast->coded_framesize * ast->sub_packet_h / 2;", "VAR_6 = (VAR_5++ == 1) ? 2 : 0;", "pos = avio_tell(VAR_0->pb);", "} else {", "VAR_3=sync(VAR_0, &timestamp, &VAR_6, &VAR_2, &pos);", "if (VAR_3 > 0)\nst = VAR_0->streams[VAR_2];", "}", "if(VAR_3<0 || url_feof(VAR_0->pb))\nreturn AVERROR(EIO);", "VAR_4 = ff_rm_parse_packet (VAR_0, VAR_0->pb, st, st->priv_data, VAR_3, VAR_1,\n&VAR_5, VAR_6, timestamp);", "if((VAR_6&2) && (VAR_5&0x7F) == 1)\nav_add_index_entry(st, pos, timestamp, 0, 0, AVINDEX_KEYFRAME);", "if (VAR_4)\ncontinue;", "}", "if( (st->discard >= AVDISCARD_NONKEY && !(VAR_6&2))\n|| st->discard >= AVDISCARD_ALL){", "av_free_packet(VAR_1);", "} else", "break;", "}", "return 0;", "}" ]
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[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 17 ], [ 19 ], [ 23 ], [ 25 ], [ 27, 29 ], [ 31 ], [ 33 ], [ 35 ], [ 37 ], [ 41 ], [ 43 ], [ 45 ], [ 47, 49 ], [ 51 ], [ 53 ], [ 55 ], [ 57 ], [ 59, 61 ], [ 63 ], [ 67, 69 ], [ 73, 75 ], [ 77, 79 ], [ 81, 83 ], [ 85 ], [ 89, 91 ], [ 93 ], [ 95 ], [ 97 ], [ 99 ], [ 103 ], [ 105 ] ]
16,855
static void do_pci_unregister_device(PCIDevice *pci_dev) { pci_dev->bus->devices[pci_dev->devfn] = NULL; pci_config_free(pci_dev); memory_region_del_subregion(&pci_dev->bus_master_container_region, &pci_dev->bus_master_enable_region); address_space_destroy(&pci_dev->bus_master_as); }
true
qemu
193982c6f9424779b53a168fe32ebc30a776cbf1
static void do_pci_unregister_device(PCIDevice *pci_dev) { pci_dev->bus->devices[pci_dev->devfn] = NULL; pci_config_free(pci_dev); memory_region_del_subregion(&pci_dev->bus_master_container_region, &pci_dev->bus_master_enable_region); address_space_destroy(&pci_dev->bus_master_as); }
{ "code": [ " memory_region_del_subregion(&pci_dev->bus_master_container_region,", " &pci_dev->bus_master_enable_region);" ], "line_no": [ 11, 13 ] }
static void FUNC_0(PCIDevice *VAR_0) { VAR_0->bus->devices[VAR_0->devfn] = NULL; pci_config_free(VAR_0); memory_region_del_subregion(&VAR_0->bus_master_container_region, &VAR_0->bus_master_enable_region); address_space_destroy(&VAR_0->bus_master_as); }
[ "static void FUNC_0(PCIDevice *VAR_0)\n{", "VAR_0->bus->devices[VAR_0->devfn] = NULL;", "pci_config_free(VAR_0);", "memory_region_del_subregion(&VAR_0->bus_master_container_region,\n&VAR_0->bus_master_enable_region);", "address_space_destroy(&VAR_0->bus_master_as);", "}" ]
[ 0, 0, 0, 1, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 11, 13 ], [ 15 ], [ 17 ] ]
16,857
static void vhost_user_cleanup(NetClientState *nc) { VhostUserState *s = DO_UPCAST(VhostUserState, nc, nc); vhost_user_stop(s); qemu_purge_queued_packets(nc); }
false
qemu
b931bfbf042983f311b3b09894d8030b2755a638
static void vhost_user_cleanup(NetClientState *nc) { VhostUserState *s = DO_UPCAST(VhostUserState, nc, nc); vhost_user_stop(s); qemu_purge_queued_packets(nc); }
{ "code": [], "line_no": [] }
static void FUNC_0(NetClientState *VAR_0) { VhostUserState *s = DO_UPCAST(VhostUserState, VAR_0, VAR_0); vhost_user_stop(s); qemu_purge_queued_packets(VAR_0); }
[ "static void FUNC_0(NetClientState *VAR_0)\n{", "VhostUserState *s = DO_UPCAST(VhostUserState, VAR_0, VAR_0);", "vhost_user_stop(s);", "qemu_purge_queued_packets(VAR_0);", "}" ]
[ 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9 ], [ 11 ], [ 13 ] ]
16,858
static void virtio_net_tx_timer(void *opaque) { VirtIONetQueue *q = opaque; VirtIONet *n = q->n; VirtIODevice *vdev = VIRTIO_DEVICE(n); assert(vdev->vm_running); q->tx_waiting = 0; /* Just in case the driver is not ready on more */ if (!(vdev->status & VIRTIO_CONFIG_S_DRIVER_OK)) { return; } virtio_queue_set_notification(q->tx_vq, 1); virtio_net_flush_tx(q); }
false
qemu
0187c7989a5cedd4f88bba76839cc9c44fb3fc81
static void virtio_net_tx_timer(void *opaque) { VirtIONetQueue *q = opaque; VirtIONet *n = q->n; VirtIODevice *vdev = VIRTIO_DEVICE(n); assert(vdev->vm_running); q->tx_waiting = 0; if (!(vdev->status & VIRTIO_CONFIG_S_DRIVER_OK)) { return; } virtio_queue_set_notification(q->tx_vq, 1); virtio_net_flush_tx(q); }
{ "code": [], "line_no": [] }
static void FUNC_0(void *VAR_0) { VirtIONetQueue *q = VAR_0; VirtIONet *n = q->n; VirtIODevice *vdev = VIRTIO_DEVICE(n); assert(vdev->vm_running); q->tx_waiting = 0; if (!(vdev->status & VIRTIO_CONFIG_S_DRIVER_OK)) { return; } virtio_queue_set_notification(q->tx_vq, 1); virtio_net_flush_tx(q); }
[ "static void FUNC_0(void *VAR_0)\n{", "VirtIONetQueue *q = VAR_0;", "VirtIONet *n = q->n;", "VirtIODevice *vdev = VIRTIO_DEVICE(n);", "assert(vdev->vm_running);", "q->tx_waiting = 0;", "if (!(vdev->status & VIRTIO_CONFIG_S_DRIVER_OK)) {", "return;", "}", "virtio_queue_set_notification(q->tx_vq, 1);", "virtio_net_flush_tx(q);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 15 ], [ 21 ], [ 23 ], [ 25 ], [ 29 ], [ 31 ], [ 33 ] ]
16,859
static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, unsigned size) { struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; if (size != 1) { return omap_badwidth_read8(opaque, addr); } switch (offset) { case 0x00: /* PWL_LEVEL */ return s->level; case 0x04: /* PWL_CTRL */ return s->enable; } OMAP_BAD_REG(addr); return 0; }
false
qemu
a8170e5e97ad17ca169c64ba87ae2f53850dab4c
static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr, unsigned size) { struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; if (size != 1) { return omap_badwidth_read8(opaque, addr); } switch (offset) { case 0x00: return s->level; case 0x04: return s->enable; } OMAP_BAD_REG(addr); return 0; }
{ "code": [], "line_no": [] }
static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr, unsigned size) { struct omap_pwl_s *VAR_0 = (struct omap_pwl_s *) opaque; int VAR_1 = addr & OMAP_MPUI_REG_MASK; if (size != 1) { return omap_badwidth_read8(opaque, addr); } switch (VAR_1) { case 0x00: return VAR_0->level; case 0x04: return VAR_0->enable; } OMAP_BAD_REG(addr); return 0; }
[ "static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr,\nunsigned size)\n{", "struct omap_pwl_s *VAR_0 = (struct omap_pwl_s *) opaque;", "int VAR_1 = addr & OMAP_MPUI_REG_MASK;", "if (size != 1) {", "return omap_badwidth_read8(opaque, addr);", "}", "switch (VAR_1) {", "case 0x00:\nreturn VAR_0->level;", "case 0x04:\nreturn VAR_0->enable;", "}", "OMAP_BAD_REG(addr);", "return 0;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5 ], [ 7 ], [ 9 ], [ 13 ], [ 15 ], [ 17 ], [ 21 ], [ 23, 25 ], [ 27, 29 ], [ 31 ], [ 33 ], [ 35 ], [ 37 ] ]
16,860
int ff_parse_packing_format(int *ret, const char *arg, void *log_ctx) { char *tail; int planar = strtol(arg, &tail, 10); if (*tail) { planar = (strcmp(arg, "packed") != 0); } else if (planar != 0 && planar != 1) { av_log(log_ctx, AV_LOG_ERROR, "Invalid packing format '%s'\n", arg); return AVERROR(EINVAL); } *ret = planar; return 0; }
false
FFmpeg
a7196795613f2cd416cf2c51c767a1125e27b057
int ff_parse_packing_format(int *ret, const char *arg, void *log_ctx) { char *tail; int planar = strtol(arg, &tail, 10); if (*tail) { planar = (strcmp(arg, "packed") != 0); } else if (planar != 0 && planar != 1) { av_log(log_ctx, AV_LOG_ERROR, "Invalid packing format '%s'\n", arg); return AVERROR(EINVAL); } *ret = planar; return 0; }
{ "code": [], "line_no": [] }
int FUNC_0(int *VAR_0, const char *VAR_1, void *VAR_2) { char *VAR_3; int VAR_4 = strtol(VAR_1, &VAR_3, 10); if (*VAR_3) { VAR_4 = (strcmp(VAR_1, "packed") != 0); } else if (VAR_4 != 0 && VAR_4 != 1) { av_log(VAR_2, AV_LOG_ERROR, "Invalid packing format '%s'\n", VAR_1); return AVERROR(EINVAL); } *VAR_0 = VAR_4; return 0; }
[ "int FUNC_0(int *VAR_0, const char *VAR_1, void *VAR_2)\n{", "char *VAR_3;", "int VAR_4 = strtol(VAR_1, &VAR_3, 10);", "if (*VAR_3) {", "VAR_4 = (strcmp(VAR_1, \"packed\") != 0);", "} else if (VAR_4 != 0 && VAR_4 != 1) {", "av_log(VAR_2, AV_LOG_ERROR, \"Invalid packing format '%s'\\n\", VAR_1);", "return AVERROR(EINVAL);", "}", "*VAR_0 = VAR_4;", "return 0;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ] ]
16,861
static int kvm_get_debugregs(CPUState *env) { #ifdef KVM_CAP_DEBUGREGS struct kvm_debugregs dbgregs; int i, ret; if (!kvm_has_debugregs()) { return 0; } ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); if (ret < 0) { return ret; } for (i = 0; i < 4; i++) { env->dr[i] = dbgregs.db[i]; } env->dr[4] = env->dr[6] = dbgregs.dr6; env->dr[5] = env->dr[7] = dbgregs.dr7; #endif return 0; }
false
qemu
b9bec74bcb16519a876ec21cd5277c526a9b512d
static int kvm_get_debugregs(CPUState *env) { #ifdef KVM_CAP_DEBUGREGS struct kvm_debugregs dbgregs; int i, ret; if (!kvm_has_debugregs()) { return 0; } ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); if (ret < 0) { return ret; } for (i = 0; i < 4; i++) { env->dr[i] = dbgregs.db[i]; } env->dr[4] = env->dr[6] = dbgregs.dr6; env->dr[5] = env->dr[7] = dbgregs.dr7; #endif return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(CPUState *VAR_0) { #ifdef KVM_CAP_DEBUGREGS struct kvm_debugregs dbgregs; int i, ret; if (!kvm_has_debugregs()) { return 0; } ret = kvm_vcpu_ioctl(VAR_0, KVM_GET_DEBUGREGS, &dbgregs); if (ret < 0) { return ret; } for (i = 0; i < 4; i++) { VAR_0->dr[i] = dbgregs.db[i]; } VAR_0->dr[4] = VAR_0->dr[6] = dbgregs.dr6; VAR_0->dr[5] = VAR_0->dr[7] = dbgregs.dr7; #endif return 0; }
[ "static int FUNC_0(CPUState *VAR_0)\n{", "#ifdef KVM_CAP_DEBUGREGS\nstruct kvm_debugregs dbgregs;", "int i, ret;", "if (!kvm_has_debugregs()) {", "return 0;", "}", "ret = kvm_vcpu_ioctl(VAR_0, KVM_GET_DEBUGREGS, &dbgregs);", "if (ret < 0) {", "return ret;", "}", "for (i = 0; i < 4; i++) {", "VAR_0->dr[i] = dbgregs.db[i];", "}", "VAR_0->dr[4] = VAR_0->dr[6] = dbgregs.dr6;", "VAR_0->dr[5] = VAR_0->dr[7] = dbgregs.dr7;", "#endif\nreturn 0;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5, 7 ], [ 9 ], [ 13 ], [ 15 ], [ 17 ], [ 21 ], [ 23 ], [ 25 ], [ 27 ], [ 29 ], [ 31 ], [ 33 ], [ 35 ], [ 37 ], [ 39, 43 ], [ 45 ] ]
16,863
static void scsi_hd_realize(SCSIDevice *dev, Error **errp) { SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, dev); blkconf_blocksizes(&s->qdev.conf); s->qdev.blocksize = s->qdev.conf.logical_block_size; s->qdev.type = TYPE_DISK; if (!s->product) { s->product = g_strdup("QEMU HARDDISK"); } scsi_realize(&s->qdev, errp); }
false
qemu
df1d4c341a735334de23513f17bf110c8c49b3e7
static void scsi_hd_realize(SCSIDevice *dev, Error **errp) { SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, dev); blkconf_blocksizes(&s->qdev.conf); s->qdev.blocksize = s->qdev.conf.logical_block_size; s->qdev.type = TYPE_DISK; if (!s->product) { s->product = g_strdup("QEMU HARDDISK"); } scsi_realize(&s->qdev, errp); }
{ "code": [], "line_no": [] }
static void FUNC_0(SCSIDevice *VAR_0, Error **VAR_1) { SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, VAR_0); blkconf_blocksizes(&s->qdev.conf); s->qdev.blocksize = s->qdev.conf.logical_block_size; s->qdev.type = TYPE_DISK; if (!s->product) { s->product = g_strdup("QEMU HARDDISK"); } scsi_realize(&s->qdev, VAR_1); }
[ "static void FUNC_0(SCSIDevice *VAR_0, Error **VAR_1)\n{", "SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, VAR_0);", "blkconf_blocksizes(&s->qdev.conf);", "s->qdev.blocksize = s->qdev.conf.logical_block_size;", "s->qdev.type = TYPE_DISK;", "if (!s->product) {", "s->product = g_strdup(\"QEMU HARDDISK\");", "}", "scsi_realize(&s->qdev, VAR_1);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ] ]
16,864
static ssize_t virtio_net_receive(NetClientState *nc, const uint8_t *buf, size_t size) { VirtIONet *n = qemu_get_nic_opaque(nc); VirtIONetQueue *q = virtio_net_get_subqueue(nc); VirtIODevice *vdev = VIRTIO_DEVICE(n); struct iovec mhdr_sg[VIRTQUEUE_MAX_SIZE]; struct virtio_net_hdr_mrg_rxbuf mhdr; unsigned mhdr_cnt = 0; size_t offset, i, guest_offset; if (!virtio_net_can_receive(nc)) { return -1; } /* hdr_len refers to the header we supply to the guest */ if (!virtio_net_has_buffers(q, size + n->guest_hdr_len - n->host_hdr_len)) { return 0; } if (!receive_filter(n, buf, size)) return size; offset = i = 0; while (offset < size) { VirtQueueElement elem; int len, total; const struct iovec *sg = elem.in_sg; total = 0; if (virtqueue_pop(q->rx_vq, &elem) == 0) { if (i == 0) return -1; error_report("virtio-net unexpected empty queue: " "i %zd mergeable %d offset %zd, size %zd, " "guest hdr len %zd, host hdr len %zd " "guest features 0x%" PRIx64, i, n->mergeable_rx_bufs, offset, size, n->guest_hdr_len, n->host_hdr_len, vdev->guest_features); exit(1); } if (elem.in_num < 1) { error_report("virtio-net receive queue contains no in buffers"); exit(1); } if (i == 0) { assert(offset == 0); if (n->mergeable_rx_bufs) { mhdr_cnt = iov_copy(mhdr_sg, ARRAY_SIZE(mhdr_sg), sg, elem.in_num, offsetof(typeof(mhdr), num_buffers), sizeof(mhdr.num_buffers)); } receive_header(n, sg, elem.in_num, buf, size); offset = n->host_hdr_len; total += n->guest_hdr_len; guest_offset = n->guest_hdr_len; } else { guest_offset = 0; } /* copy in packet. ugh */ len = iov_from_buf(sg, elem.in_num, guest_offset, buf + offset, size - offset); total += len; offset += len; /* If buffers can't be merged, at this point we * must have consumed the complete packet. * Otherwise, drop it. */ if (!n->mergeable_rx_bufs && offset < size) { virtqueue_discard(q->rx_vq, &elem, total); return size; } /* signal other side */ virtqueue_fill(q->rx_vq, &elem, total, i++); } if (mhdr_cnt) { virtio_stw_p(vdev, &mhdr.num_buffers, i); iov_from_buf(mhdr_sg, mhdr_cnt, 0, &mhdr.num_buffers, sizeof mhdr.num_buffers); } virtqueue_flush(q->rx_vq, i); virtio_notify(vdev, q->rx_vq); return size; }
false
qemu
51b19ebe4320f3dcd93cea71235c1219318ddfd2
static ssize_t virtio_net_receive(NetClientState *nc, const uint8_t *buf, size_t size) { VirtIONet *n = qemu_get_nic_opaque(nc); VirtIONetQueue *q = virtio_net_get_subqueue(nc); VirtIODevice *vdev = VIRTIO_DEVICE(n); struct iovec mhdr_sg[VIRTQUEUE_MAX_SIZE]; struct virtio_net_hdr_mrg_rxbuf mhdr; unsigned mhdr_cnt = 0; size_t offset, i, guest_offset; if (!virtio_net_can_receive(nc)) { return -1; } if (!virtio_net_has_buffers(q, size + n->guest_hdr_len - n->host_hdr_len)) { return 0; } if (!receive_filter(n, buf, size)) return size; offset = i = 0; while (offset < size) { VirtQueueElement elem; int len, total; const struct iovec *sg = elem.in_sg; total = 0; if (virtqueue_pop(q->rx_vq, &elem) == 0) { if (i == 0) return -1; error_report("virtio-net unexpected empty queue: " "i %zd mergeable %d offset %zd, size %zd, " "guest hdr len %zd, host hdr len %zd " "guest features 0x%" PRIx64, i, n->mergeable_rx_bufs, offset, size, n->guest_hdr_len, n->host_hdr_len, vdev->guest_features); exit(1); } if (elem.in_num < 1) { error_report("virtio-net receive queue contains no in buffers"); exit(1); } if (i == 0) { assert(offset == 0); if (n->mergeable_rx_bufs) { mhdr_cnt = iov_copy(mhdr_sg, ARRAY_SIZE(mhdr_sg), sg, elem.in_num, offsetof(typeof(mhdr), num_buffers), sizeof(mhdr.num_buffers)); } receive_header(n, sg, elem.in_num, buf, size); offset = n->host_hdr_len; total += n->guest_hdr_len; guest_offset = n->guest_hdr_len; } else { guest_offset = 0; } len = iov_from_buf(sg, elem.in_num, guest_offset, buf + offset, size - offset); total += len; offset += len; if (!n->mergeable_rx_bufs && offset < size) { virtqueue_discard(q->rx_vq, &elem, total); return size; } virtqueue_fill(q->rx_vq, &elem, total, i++); } if (mhdr_cnt) { virtio_stw_p(vdev, &mhdr.num_buffers, i); iov_from_buf(mhdr_sg, mhdr_cnt, 0, &mhdr.num_buffers, sizeof mhdr.num_buffers); } virtqueue_flush(q->rx_vq, i); virtio_notify(vdev, q->rx_vq); return size; }
{ "code": [], "line_no": [] }
static ssize_t FUNC_0(NetClientState *nc, const uint8_t *buf, size_t size) { VirtIONet *n = qemu_get_nic_opaque(nc); VirtIONetQueue *q = virtio_net_get_subqueue(nc); VirtIODevice *vdev = VIRTIO_DEVICE(n); struct iovec VAR_0[VIRTQUEUE_MAX_SIZE]; struct virtio_net_hdr_mrg_rxbuf VAR_1; unsigned VAR_2 = 0; size_t offset, i, guest_offset; if (!virtio_net_can_receive(nc)) { return -1; } if (!virtio_net_has_buffers(q, size + n->guest_hdr_len - n->host_hdr_len)) { return 0; } if (!receive_filter(n, buf, size)) return size; offset = i = 0; while (offset < size) { VirtQueueElement elem; int VAR_3, VAR_4; const struct iovec *VAR_5 = elem.in_sg; VAR_4 = 0; if (virtqueue_pop(q->rx_vq, &elem) == 0) { if (i == 0) return -1; error_report("virtio-net unexpected empty queue: " "i %zd mergeable %d offset %zd, size %zd, " "guest hdr VAR_3 %zd, host hdr VAR_3 %zd " "guest features 0x%" PRIx64, i, n->mergeable_rx_bufs, offset, size, n->guest_hdr_len, n->host_hdr_len, vdev->guest_features); exit(1); } if (elem.in_num < 1) { error_report("virtio-net receive queue contains no in buffers"); exit(1); } if (i == 0) { assert(offset == 0); if (n->mergeable_rx_bufs) { VAR_2 = iov_copy(VAR_0, ARRAY_SIZE(VAR_0), VAR_5, elem.in_num, offsetof(typeof(VAR_1), num_buffers), sizeof(VAR_1.num_buffers)); } receive_header(n, VAR_5, elem.in_num, buf, size); offset = n->host_hdr_len; VAR_4 += n->guest_hdr_len; guest_offset = n->guest_hdr_len; } else { guest_offset = 0; } VAR_3 = iov_from_buf(VAR_5, elem.in_num, guest_offset, buf + offset, size - offset); VAR_4 += VAR_3; offset += VAR_3; if (!n->mergeable_rx_bufs && offset < size) { virtqueue_discard(q->rx_vq, &elem, VAR_4); return size; } virtqueue_fill(q->rx_vq, &elem, VAR_4, i++); } if (VAR_2) { virtio_stw_p(vdev, &VAR_1.num_buffers, i); iov_from_buf(VAR_0, VAR_2, 0, &VAR_1.num_buffers, sizeof VAR_1.num_buffers); } virtqueue_flush(q->rx_vq, i); virtio_notify(vdev, q->rx_vq); return size; }
[ "static ssize_t FUNC_0(NetClientState *nc, const uint8_t *buf, size_t size)\n{", "VirtIONet *n = qemu_get_nic_opaque(nc);", "VirtIONetQueue *q = virtio_net_get_subqueue(nc);", "VirtIODevice *vdev = VIRTIO_DEVICE(n);", "struct iovec VAR_0[VIRTQUEUE_MAX_SIZE];", "struct virtio_net_hdr_mrg_rxbuf VAR_1;", "unsigned VAR_2 = 0;", "size_t offset, i, guest_offset;", "if (!virtio_net_can_receive(nc)) {", "return -1;", "}", "if (!virtio_net_has_buffers(q, size + n->guest_hdr_len - n->host_hdr_len)) {", "return 0;", "}", "if (!receive_filter(n, buf, size))\nreturn size;", "offset = i = 0;", "while (offset < size) {", "VirtQueueElement elem;", "int VAR_3, VAR_4;", "const struct iovec *VAR_5 = elem.in_sg;", "VAR_4 = 0;", "if (virtqueue_pop(q->rx_vq, &elem) == 0) {", "if (i == 0)\nreturn -1;", "error_report(\"virtio-net unexpected empty queue: \"\n\"i %zd mergeable %d offset %zd, size %zd, \"\n\"guest hdr VAR_3 %zd, host hdr VAR_3 %zd \"\n\"guest features 0x%\" PRIx64,\ni, n->mergeable_rx_bufs, offset, size,\nn->guest_hdr_len, n->host_hdr_len,\nvdev->guest_features);", "exit(1);", "}", "if (elem.in_num < 1) {", "error_report(\"virtio-net receive queue contains no in buffers\");", "exit(1);", "}", "if (i == 0) {", "assert(offset == 0);", "if (n->mergeable_rx_bufs) {", "VAR_2 = iov_copy(VAR_0, ARRAY_SIZE(VAR_0),\nVAR_5, elem.in_num,\noffsetof(typeof(VAR_1), num_buffers),\nsizeof(VAR_1.num_buffers));", "}", "receive_header(n, VAR_5, elem.in_num, buf, size);", "offset = n->host_hdr_len;", "VAR_4 += n->guest_hdr_len;", "guest_offset = n->guest_hdr_len;", "} else {", "guest_offset = 0;", "}", "VAR_3 = iov_from_buf(VAR_5, elem.in_num, guest_offset,\nbuf + offset, size - offset);", "VAR_4 += VAR_3;", "offset += VAR_3;", "if (!n->mergeable_rx_bufs && offset < size) {", "virtqueue_discard(q->rx_vq, &elem, VAR_4);", "return size;", "}", "virtqueue_fill(q->rx_vq, &elem, VAR_4, i++);", "}", "if (VAR_2) {", "virtio_stw_p(vdev, &VAR_1.num_buffers, i);", "iov_from_buf(VAR_0, VAR_2,\n0,\n&VAR_1.num_buffers, sizeof VAR_1.num_buffers);", "}", "virtqueue_flush(q->rx_vq, i);", "virtio_notify(vdev, q->rx_vq);", "return size;", "}" ]
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16,865
int usb_claim_port(USBDevice *dev) { USBBus *bus = usb_bus_from_device(dev); USBPort *port; assert(dev->port == NULL); if (dev->port_path) { QTAILQ_FOREACH(port, &bus->free, next) { if (strcmp(port->path, dev->port_path) == 0) { break; } } if (port == NULL) { error_report("Error: usb port %s (bus %s) not found (in use?)", dev->port_path, bus->qbus.name); return -1; } } else { if (bus->nfree == 1 && strcmp(object_get_typename(OBJECT(dev)), "usb-hub") != 0) { /* Create a new hub and chain it on */ usb_create_simple(bus, "usb-hub"); } if (bus->nfree == 0) { error_report("Error: tried to attach usb device %s to a bus " "with no free ports", dev->product_desc); return -1; } port = QTAILQ_FIRST(&bus->free); } trace_usb_port_claim(bus->busnr, port->path); QTAILQ_REMOVE(&bus->free, port, next); bus->nfree--; dev->port = port; port->dev = dev; QTAILQ_INSERT_TAIL(&bus->used, port, next); bus->nused++; return 0; }
false
qemu
7d553f27fce284805d7f94603932045ee3bbb979
int usb_claim_port(USBDevice *dev) { USBBus *bus = usb_bus_from_device(dev); USBPort *port; assert(dev->port == NULL); if (dev->port_path) { QTAILQ_FOREACH(port, &bus->free, next) { if (strcmp(port->path, dev->port_path) == 0) { break; } } if (port == NULL) { error_report("Error: usb port %s (bus %s) not found (in use?)", dev->port_path, bus->qbus.name); return -1; } } else { if (bus->nfree == 1 && strcmp(object_get_typename(OBJECT(dev)), "usb-hub") != 0) { usb_create_simple(bus, "usb-hub"); } if (bus->nfree == 0) { error_report("Error: tried to attach usb device %s to a bus " "with no free ports", dev->product_desc); return -1; } port = QTAILQ_FIRST(&bus->free); } trace_usb_port_claim(bus->busnr, port->path); QTAILQ_REMOVE(&bus->free, port, next); bus->nfree--; dev->port = port; port->dev = dev; QTAILQ_INSERT_TAIL(&bus->used, port, next); bus->nused++; return 0; }
{ "code": [], "line_no": [] }
int FUNC_0(USBDevice *VAR_0) { USBBus *bus = usb_bus_from_device(VAR_0); USBPort *port; assert(VAR_0->port == NULL); if (VAR_0->port_path) { QTAILQ_FOREACH(port, &bus->free, next) { if (strcmp(port->path, VAR_0->port_path) == 0) { break; } } if (port == NULL) { error_report("Error: usb port %s (bus %s) not found (in use?)", VAR_0->port_path, bus->qbus.name); return -1; } } else { if (bus->nfree == 1 && strcmp(object_get_typename(OBJECT(VAR_0)), "usb-hub") != 0) { usb_create_simple(bus, "usb-hub"); } if (bus->nfree == 0) { error_report("Error: tried to attach usb device %s to a bus " "with no free ports", VAR_0->product_desc); return -1; } port = QTAILQ_FIRST(&bus->free); } trace_usb_port_claim(bus->busnr, port->path); QTAILQ_REMOVE(&bus->free, port, next); bus->nfree--; VAR_0->port = port; port->VAR_0 = VAR_0; QTAILQ_INSERT_TAIL(&bus->used, port, next); bus->nused++; return 0; }
[ "int FUNC_0(USBDevice *VAR_0)\n{", "USBBus *bus = usb_bus_from_device(VAR_0);", "USBPort *port;", "assert(VAR_0->port == NULL);", "if (VAR_0->port_path) {", "QTAILQ_FOREACH(port, &bus->free, next) {", "if (strcmp(port->path, VAR_0->port_path) == 0) {", "break;", "}", "}", "if (port == NULL) {", "error_report(\"Error: usb port %s (bus %s) not found (in use?)\",\nVAR_0->port_path, bus->qbus.name);", "return -1;", "}", "} else {", "if (bus->nfree == 1 && strcmp(object_get_typename(OBJECT(VAR_0)), \"usb-hub\") != 0) {", "usb_create_simple(bus, \"usb-hub\");", "}", "if (bus->nfree == 0) {", "error_report(\"Error: tried to attach usb device %s to a bus \"\n\"with no free ports\", VAR_0->product_desc);", "return -1;", "}", "port = QTAILQ_FIRST(&bus->free);", "}", "trace_usb_port_claim(bus->busnr, port->path);", "QTAILQ_REMOVE(&bus->free, port, next);", "bus->nfree--;", "VAR_0->port = port;", "port->VAR_0 = VAR_0;", "QTAILQ_INSERT_TAIL(&bus->used, port, next);", "bus->nused++;", "return 0;", "}" ]
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16,866
lqspi_read(void *opaque, hwaddr addr, unsigned int size) { int i; XilinxQSPIPS *q = opaque; XilinxSPIPS *s = opaque; uint32_t ret; if (addr >= q->lqspi_cached_addr && addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2]; DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret); return ret; } else { int flash_addr = (addr / num_effective_busses(s)); int slave = flash_addr >> LQSPI_ADDRESS_BITS; int cache_entry = 0; DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]); fifo8_reset(&s->tx_fifo); fifo8_reset(&s->rx_fifo); s->regs[R_CONFIG] &= ~CS; s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS; xilinx_spips_update_cs_lines(s); /* instruction */ DB_PRINT("pushing read instruction: %02x\n", (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE)); fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); /* read address */ DB_PRINT("pushing read address %06x\n", flash_addr); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); /* mode bits */ if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_MODE_SHIFT, LQSPI_CFG_MODE_WIDTH)); } /* dummy bytes */ for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, LQSPI_CFG_DUMMY_WIDTH)); ++i) { DB_PRINT("pushing dummy byte\n"); fifo8_push(&s->tx_fifo, 0); } xilinx_spips_update_cs_lines(s); xilinx_spips_flush_txfifo(s); fifo8_reset(&s->rx_fifo); DB_PRINT("starting QSPI data read\n"); for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) { tx_data_bytes(s, 0, 4); xilinx_spips_flush_txfifo(s); rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); cache_entry++; } xilinx_spips_update_cs_lines(s); s->regs[R_CONFIG] |= CS; xilinx_spips_update_cs_lines(s); q->lqspi_cached_addr = addr; return lqspi_read(opaque, addr, size); } }
false
qemu
15408b428f5b4db56da555fbda4f1aaf40d77f4b
lqspi_read(void *opaque, hwaddr addr, unsigned int size) { int i; XilinxQSPIPS *q = opaque; XilinxSPIPS *s = opaque; uint32_t ret; if (addr >= q->lqspi_cached_addr && addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2]; DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret); return ret; } else { int flash_addr = (addr / num_effective_busses(s)); int slave = flash_addr >> LQSPI_ADDRESS_BITS; int cache_entry = 0; DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]); fifo8_reset(&s->tx_fifo); fifo8_reset(&s->rx_fifo); s->regs[R_CONFIG] &= ~CS; s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS; xilinx_spips_update_cs_lines(s); DB_PRINT("pushing read instruction: %02x\n", (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE)); fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); DB_PRINT("pushing read address %06x\n", flash_addr); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_MODE_SHIFT, LQSPI_CFG_MODE_WIDTH)); } for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, LQSPI_CFG_DUMMY_WIDTH)); ++i) { DB_PRINT("pushing dummy byte\n"); fifo8_push(&s->tx_fifo, 0); } xilinx_spips_update_cs_lines(s); xilinx_spips_flush_txfifo(s); fifo8_reset(&s->rx_fifo); DB_PRINT("starting QSPI data read\n"); for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) { tx_data_bytes(s, 0, 4); xilinx_spips_flush_txfifo(s); rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); cache_entry++; } xilinx_spips_update_cs_lines(s); s->regs[R_CONFIG] |= CS; xilinx_spips_update_cs_lines(s); q->lqspi_cached_addr = addr; return lqspi_read(opaque, addr, size); } }
{ "code": [], "line_no": [] }
FUNC_0(void *VAR_0, hwaddr VAR_1, unsigned int VAR_2) { int VAR_3; XilinxQSPIPS *q = VAR_0; XilinxSPIPS *s = VAR_0; uint32_t ret; if (VAR_1 >= q->lqspi_cached_addr && VAR_1 <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { ret = q->lqspi_buf[(VAR_1 - q->lqspi_cached_addr) >> 2]; DB_PRINT("VAR_1: %08x, data: %08x\n", (unsigned)VAR_1, (unsigned)ret); return ret; } else { int VAR_4 = (VAR_1 / num_effective_busses(s)); int VAR_5 = VAR_4 >> LQSPI_ADDRESS_BITS; int VAR_6 = 0; DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]); fifo8_reset(&s->tx_fifo); fifo8_reset(&s->rx_fifo); s->regs[R_CONFIG] &= ~CS; s->regs[R_CONFIG] |= ((~(1 << VAR_5) << CS_SHIFT) & CS) | MANUAL_CS; xilinx_spips_update_cs_lines(s); DB_PRINT("pushing read instruction: %02x\n", (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE)); fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); DB_PRINT("pushing read address %06x\n", VAR_4); fifo8_push(&s->tx_fifo, (uint8_t)(VAR_4 >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(VAR_4 >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)VAR_4); if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_MODE_SHIFT, LQSPI_CFG_MODE_WIDTH)); } for (VAR_3 = 0; VAR_3 < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, LQSPI_CFG_DUMMY_WIDTH)); ++VAR_3) { DB_PRINT("pushing dummy byte\n"); fifo8_push(&s->tx_fifo, 0); } xilinx_spips_update_cs_lines(s); xilinx_spips_flush_txfifo(s); fifo8_reset(&s->rx_fifo); DB_PRINT("starting QSPI data read\n"); for (VAR_3 = 0; VAR_3 < LQSPI_CACHE_SIZE / 4; ++VAR_3) { tx_data_bytes(s, 0, 4); xilinx_spips_flush_txfifo(s); rx_data_bytes(s, &q->lqspi_buf[VAR_6], 4); VAR_6++; } xilinx_spips_update_cs_lines(s); s->regs[R_CONFIG] |= CS; xilinx_spips_update_cs_lines(s); q->lqspi_cached_addr = VAR_1; return FUNC_0(VAR_0, VAR_1, VAR_2); } }
[ "FUNC_0(void *VAR_0, hwaddr VAR_1, unsigned int VAR_2)\n{", "int VAR_3;", "XilinxQSPIPS *q = VAR_0;", "XilinxSPIPS *s = VAR_0;", "uint32_t ret;", "if (VAR_1 >= q->lqspi_cached_addr &&\nVAR_1 <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {", "ret = q->lqspi_buf[(VAR_1 - q->lqspi_cached_addr) >> 2];", "DB_PRINT(\"VAR_1: %08x, data: %08x\\n\", (unsigned)VAR_1, (unsigned)ret);", "return ret;", "} else {", "int VAR_4 = (VAR_1 / num_effective_busses(s));", "int VAR_5 = VAR_4 >> LQSPI_ADDRESS_BITS;", "int VAR_6 = 0;", "DB_PRINT(\"config reg status: %08x\\n\", s->regs[R_LQSPI_CFG]);", "fifo8_reset(&s->tx_fifo);", "fifo8_reset(&s->rx_fifo);", "s->regs[R_CONFIG] &= ~CS;", "s->regs[R_CONFIG] |= ((~(1 << VAR_5) << CS_SHIFT) & CS) | MANUAL_CS;", "xilinx_spips_update_cs_lines(s);", "DB_PRINT(\"pushing read instruction: %02x\\n\",\n(uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));", "fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);", "DB_PRINT(\"pushing read address %06x\\n\", VAR_4);", "fifo8_push(&s->tx_fifo, (uint8_t)(VAR_4 >> 16));", "fifo8_push(&s->tx_fifo, (uint8_t)(VAR_4 >> 8));", "fifo8_push(&s->tx_fifo, (uint8_t)VAR_4);", "if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {", "fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],\nLQSPI_CFG_MODE_SHIFT,\nLQSPI_CFG_MODE_WIDTH));", "}", "for (VAR_3 = 0; VAR_3 < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,", "LQSPI_CFG_DUMMY_WIDTH)); ++VAR_3) {", "DB_PRINT(\"pushing dummy byte\\n\");", "fifo8_push(&s->tx_fifo, 0);", "}", "xilinx_spips_update_cs_lines(s);", "xilinx_spips_flush_txfifo(s);", "fifo8_reset(&s->rx_fifo);", "DB_PRINT(\"starting QSPI data read\\n\");", "for (VAR_3 = 0; VAR_3 < LQSPI_CACHE_SIZE / 4; ++VAR_3) {", "tx_data_bytes(s, 0, 4);", "xilinx_spips_flush_txfifo(s);", "rx_data_bytes(s, &q->lqspi_buf[VAR_6], 4);", "VAR_6++;", "}", "xilinx_spips_update_cs_lines(s);", "s->regs[R_CONFIG] |= CS;", "xilinx_spips_update_cs_lines(s);", "q->lqspi_cached_addr = VAR_1;", "return FUNC_0(VAR_0, VAR_1, VAR_2);", "}", "}" ]
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16,867
static int send_jpeg_rect(VncState *vs, int x, int y, int w, int h, int quality) { struct jpeg_compress_struct cinfo; struct jpeg_error_mgr jerr; struct jpeg_destination_mgr manager; JSAMPROW row[1]; uint8_t *buf; int dy; if (ds_get_bytes_per_pixel(vs->ds) == 1) return send_full_color_rect(vs, w, h); buf = qemu_malloc(w * 3); row[0] = buf; buffer_reserve(&vs->tight_jpeg, 2048); cinfo.err = jpeg_std_error(&jerr); jpeg_create_compress(&cinfo); cinfo.client_data = vs; cinfo.image_width = w; cinfo.image_height = h; cinfo.input_components = 3; cinfo.in_color_space = JCS_RGB; jpeg_set_defaults(&cinfo); jpeg_set_quality(&cinfo, quality, true); manager.init_destination = jpeg_init_destination; manager.empty_output_buffer = jpeg_empty_output_buffer; manager.term_destination = jpeg_term_destination; cinfo.dest = &manager; jpeg_start_compress(&cinfo, true); for (dy = 0; dy < h; dy++) { jpeg_prepare_row(vs, buf, x, y + dy, w); jpeg_write_scanlines(&cinfo, row, 1); } jpeg_finish_compress(&cinfo); jpeg_destroy_compress(&cinfo); vnc_write_u8(vs, VNC_TIGHT_JPEG << 4); tight_send_compact_size(vs, vs->tight_jpeg.offset); vnc_write(vs, vs->tight_jpeg.buffer, vs->tight_jpeg.offset); buffer_reset(&vs->tight_jpeg); return 1; }
false
qemu
245f7b51c0ea04fb2224b1127430a096c91aee70
static int send_jpeg_rect(VncState *vs, int x, int y, int w, int h, int quality) { struct jpeg_compress_struct cinfo; struct jpeg_error_mgr jerr; struct jpeg_destination_mgr manager; JSAMPROW row[1]; uint8_t *buf; int dy; if (ds_get_bytes_per_pixel(vs->ds) == 1) return send_full_color_rect(vs, w, h); buf = qemu_malloc(w * 3); row[0] = buf; buffer_reserve(&vs->tight_jpeg, 2048); cinfo.err = jpeg_std_error(&jerr); jpeg_create_compress(&cinfo); cinfo.client_data = vs; cinfo.image_width = w; cinfo.image_height = h; cinfo.input_components = 3; cinfo.in_color_space = JCS_RGB; jpeg_set_defaults(&cinfo); jpeg_set_quality(&cinfo, quality, true); manager.init_destination = jpeg_init_destination; manager.empty_output_buffer = jpeg_empty_output_buffer; manager.term_destination = jpeg_term_destination; cinfo.dest = &manager; jpeg_start_compress(&cinfo, true); for (dy = 0; dy < h; dy++) { jpeg_prepare_row(vs, buf, x, y + dy, w); jpeg_write_scanlines(&cinfo, row, 1); } jpeg_finish_compress(&cinfo); jpeg_destroy_compress(&cinfo); vnc_write_u8(vs, VNC_TIGHT_JPEG << 4); tight_send_compact_size(vs, vs->tight_jpeg.offset); vnc_write(vs, vs->tight_jpeg.buffer, vs->tight_jpeg.offset); buffer_reset(&vs->tight_jpeg); return 1; }
{ "code": [], "line_no": [] }
static int FUNC_0(VncState *VAR_0, int VAR_1, int VAR_2, int VAR_3, int VAR_4, int VAR_5) { struct jpeg_compress_struct VAR_6; struct jpeg_error_mgr VAR_7; struct jpeg_destination_mgr VAR_8; JSAMPROW row[1]; uint8_t *buf; int VAR_9; if (ds_get_bytes_per_pixel(VAR_0->ds) == 1) return send_full_color_rect(VAR_0, VAR_3, VAR_4); buf = qemu_malloc(VAR_3 * 3); row[0] = buf; buffer_reserve(&VAR_0->tight_jpeg, 2048); VAR_6.err = jpeg_std_error(&VAR_7); jpeg_create_compress(&VAR_6); VAR_6.client_data = VAR_0; VAR_6.image_width = VAR_3; VAR_6.image_height = VAR_4; VAR_6.input_components = 3; VAR_6.in_color_space = JCS_RGB; jpeg_set_defaults(&VAR_6); jpeg_set_quality(&VAR_6, VAR_5, true); VAR_8.init_destination = jpeg_init_destination; VAR_8.empty_output_buffer = jpeg_empty_output_buffer; VAR_8.term_destination = jpeg_term_destination; VAR_6.dest = &VAR_8; jpeg_start_compress(&VAR_6, true); for (VAR_9 = 0; VAR_9 < VAR_4; VAR_9++) { jpeg_prepare_row(VAR_0, buf, VAR_1, VAR_2 + VAR_9, VAR_3); jpeg_write_scanlines(&VAR_6, row, 1); } jpeg_finish_compress(&VAR_6); jpeg_destroy_compress(&VAR_6); vnc_write_u8(VAR_0, VNC_TIGHT_JPEG << 4); tight_send_compact_size(VAR_0, VAR_0->tight_jpeg.offset); vnc_write(VAR_0, VAR_0->tight_jpeg.buffer, VAR_0->tight_jpeg.offset); buffer_reset(&VAR_0->tight_jpeg); return 1; }
[ "static int FUNC_0(VncState *VAR_0, int VAR_1, int VAR_2, int VAR_3, int VAR_4, int VAR_5)\n{", "struct jpeg_compress_struct VAR_6;", "struct jpeg_error_mgr VAR_7;", "struct jpeg_destination_mgr VAR_8;", "JSAMPROW row[1];", "uint8_t *buf;", "int VAR_9;", "if (ds_get_bytes_per_pixel(VAR_0->ds) == 1)\nreturn send_full_color_rect(VAR_0, VAR_3, VAR_4);", "buf = qemu_malloc(VAR_3 * 3);", "row[0] = buf;", "buffer_reserve(&VAR_0->tight_jpeg, 2048);", "VAR_6.err = jpeg_std_error(&VAR_7);", "jpeg_create_compress(&VAR_6);", "VAR_6.client_data = VAR_0;", "VAR_6.image_width = VAR_3;", "VAR_6.image_height = VAR_4;", "VAR_6.input_components = 3;", "VAR_6.in_color_space = JCS_RGB;", "jpeg_set_defaults(&VAR_6);", "jpeg_set_quality(&VAR_6, VAR_5, true);", "VAR_8.init_destination = jpeg_init_destination;", "VAR_8.empty_output_buffer = jpeg_empty_output_buffer;", "VAR_8.term_destination = jpeg_term_destination;", "VAR_6.dest = &VAR_8;", "jpeg_start_compress(&VAR_6, true);", "for (VAR_9 = 0; VAR_9 < VAR_4; VAR_9++) {", "jpeg_prepare_row(VAR_0, buf, VAR_1, VAR_2 + VAR_9, VAR_3);", "jpeg_write_scanlines(&VAR_6, row, 1);", "}", "jpeg_finish_compress(&VAR_6);", "jpeg_destroy_compress(&VAR_6);", "vnc_write_u8(VAR_0, VNC_TIGHT_JPEG << 4);", "tight_send_compact_size(VAR_0, VAR_0->tight_jpeg.offset);", "vnc_write(VAR_0, VAR_0->tight_jpeg.buffer, VAR_0->tight_jpeg.offset);", "buffer_reset(&VAR_0->tight_jpeg);", "return 1;", "}" ]
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16,869
static int alsa_init_out (HWVoiceOut *hw, audsettings_t *as) { ALSAVoiceOut *alsa = (ALSAVoiceOut *) hw; struct alsa_params_req req; struct alsa_params_obt obt; snd_pcm_t *handle; audsettings_t obt_as; req.fmt = aud_to_alsafmt (as->fmt); req.freq = as->freq; req.nchannels = as->nchannels; req.period_size = conf.period_size_out; req.buffer_size = conf.buffer_size_out; req.size_in_usec = conf.size_in_usec_out; req.override_mask = !!conf.period_size_out_overridden | (!!conf.buffer_size_out_overridden << 1); if (alsa_open (0, &req, &obt, &handle)) { return -1; } obt_as.freq = obt.freq; obt_as.nchannels = obt.nchannels; obt_as.fmt = obt.fmt; obt_as.endianness = obt.endianness; audio_pcm_init_info (&hw->info, &obt_as); hw->samples = obt.samples; alsa->pcm_buf = audio_calloc (AUDIO_FUNC, obt.samples, 1 << hw->info.shift); if (!alsa->pcm_buf) { dolog ("Could not allocate DAC buffer (%d samples, each %d bytes)\n", hw->samples, 1 << hw->info.shift); alsa_anal_close (&handle); return -1; } alsa->handle = handle; return 0; }
false
qemu
1ea879e5580f63414693655fcf0328559cdce138
static int alsa_init_out (HWVoiceOut *hw, audsettings_t *as) { ALSAVoiceOut *alsa = (ALSAVoiceOut *) hw; struct alsa_params_req req; struct alsa_params_obt obt; snd_pcm_t *handle; audsettings_t obt_as; req.fmt = aud_to_alsafmt (as->fmt); req.freq = as->freq; req.nchannels = as->nchannels; req.period_size = conf.period_size_out; req.buffer_size = conf.buffer_size_out; req.size_in_usec = conf.size_in_usec_out; req.override_mask = !!conf.period_size_out_overridden | (!!conf.buffer_size_out_overridden << 1); if (alsa_open (0, &req, &obt, &handle)) { return -1; } obt_as.freq = obt.freq; obt_as.nchannels = obt.nchannels; obt_as.fmt = obt.fmt; obt_as.endianness = obt.endianness; audio_pcm_init_info (&hw->info, &obt_as); hw->samples = obt.samples; alsa->pcm_buf = audio_calloc (AUDIO_FUNC, obt.samples, 1 << hw->info.shift); if (!alsa->pcm_buf) { dolog ("Could not allocate DAC buffer (%d samples, each %d bytes)\n", hw->samples, 1 << hw->info.shift); alsa_anal_close (&handle); return -1; } alsa->handle = handle; return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0 (HWVoiceOut *VAR_0, audsettings_t *VAR_1) { ALSAVoiceOut *alsa = (ALSAVoiceOut *) VAR_0; struct alsa_params_req VAR_2; struct alsa_params_obt VAR_3; snd_pcm_t *handle; audsettings_t obt_as; VAR_2.fmt = aud_to_alsafmt (VAR_1->fmt); VAR_2.freq = VAR_1->freq; VAR_2.nchannels = VAR_1->nchannels; VAR_2.period_size = conf.period_size_out; VAR_2.buffer_size = conf.buffer_size_out; VAR_2.size_in_usec = conf.size_in_usec_out; VAR_2.override_mask = !!conf.period_size_out_overridden | (!!conf.buffer_size_out_overridden << 1); if (alsa_open (0, &VAR_2, &VAR_3, &handle)) { return -1; } obt_as.freq = VAR_3.freq; obt_as.nchannels = VAR_3.nchannels; obt_as.fmt = VAR_3.fmt; obt_as.endianness = VAR_3.endianness; audio_pcm_init_info (&VAR_0->info, &obt_as); VAR_0->samples = VAR_3.samples; alsa->pcm_buf = audio_calloc (AUDIO_FUNC, VAR_3.samples, 1 << VAR_0->info.shift); if (!alsa->pcm_buf) { dolog ("Could not allocate DAC buffer (%d samples, each %d bytes)\n", VAR_0->samples, 1 << VAR_0->info.shift); alsa_anal_close (&handle); return -1; } alsa->handle = handle; return 0; }
[ "static int FUNC_0 (HWVoiceOut *VAR_0, audsettings_t *VAR_1)\n{", "ALSAVoiceOut *alsa = (ALSAVoiceOut *) VAR_0;", "struct alsa_params_req VAR_2;", "struct alsa_params_obt VAR_3;", "snd_pcm_t *handle;", "audsettings_t obt_as;", "VAR_2.fmt = aud_to_alsafmt (VAR_1->fmt);", "VAR_2.freq = VAR_1->freq;", "VAR_2.nchannels = VAR_1->nchannels;", "VAR_2.period_size = conf.period_size_out;", "VAR_2.buffer_size = conf.buffer_size_out;", "VAR_2.size_in_usec = conf.size_in_usec_out;", "VAR_2.override_mask = !!conf.period_size_out_overridden\n| (!!conf.buffer_size_out_overridden << 1);", "if (alsa_open (0, &VAR_2, &VAR_3, &handle)) {", "return -1;", "}", "obt_as.freq = VAR_3.freq;", "obt_as.nchannels = VAR_3.nchannels;", "obt_as.fmt = VAR_3.fmt;", "obt_as.endianness = VAR_3.endianness;", "audio_pcm_init_info (&VAR_0->info, &obt_as);", "VAR_0->samples = VAR_3.samples;", "alsa->pcm_buf = audio_calloc (AUDIO_FUNC, VAR_3.samples, 1 << VAR_0->info.shift);", "if (!alsa->pcm_buf) {", "dolog (\"Could not allocate DAC buffer (%d samples, each %d bytes)\\n\",\nVAR_0->samples, 1 << VAR_0->info.shift);", "alsa_anal_close (&handle);", "return -1;", "}", "alsa->handle = handle;", "return 0;", "}" ]
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16,871
static int query_format(struct vf_instance *vf, unsigned int fmt) { /* FIXME - figure out which other formats work */ switch (fmt) { case IMGFMT_YV12: case IMGFMT_IYUV: case IMGFMT_I420: return ff_vf_next_query_format(vf, fmt); } return 0; }
false
FFmpeg
04001767728fd4ed8b4f9d2ebbb9f9a8c9a7be0d
static int query_format(struct vf_instance *vf, unsigned int fmt) { switch (fmt) { case IMGFMT_YV12: case IMGFMT_IYUV: case IMGFMT_I420: return ff_vf_next_query_format(vf, fmt); } return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(struct vf_instance *VAR_0, unsigned int VAR_1) { switch (VAR_1) { case IMGFMT_YV12: case IMGFMT_IYUV: case IMGFMT_I420: return ff_vf_next_query_format(VAR_0, VAR_1); } return 0; }
[ "static int FUNC_0(struct vf_instance *VAR_0, unsigned int VAR_1)\n{", "switch (VAR_1) {", "case IMGFMT_YV12:\ncase IMGFMT_IYUV:\ncase IMGFMT_I420:\nreturn ff_vf_next_query_format(VAR_0, VAR_1);", "}", "return 0;", "}" ]
[ 0, 0, 0, 0, 0, 0 ]
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16,872
static void vfio_probe_ati_bar4_quirk(VFIOPCIDevice *vdev, int nr) { VFIOQuirk *quirk; VFIOConfigWindowQuirk *window; /* This windows doesn't seem to be used except by legacy VGA code */ if (!vfio_pci_is(vdev, PCI_VENDOR_ID_ATI, PCI_ANY_ID) || !vdev->has_vga || nr != 4) { return; } quirk = g_malloc0(sizeof(*quirk)); quirk->mem = g_new0(MemoryRegion, 2); quirk->nr_mem = 2; window = quirk->data = g_malloc0(sizeof(*window) + sizeof(VFIOConfigWindowMatch)); window->vdev = vdev; window->address_offset = 0; window->data_offset = 4; window->nr_matches = 1; window->matches[0].match = 0x4000; window->matches[0].mask = PCIE_CONFIG_SPACE_SIZE - 1; window->bar = nr; window->addr_mem = &quirk->mem[0]; window->data_mem = &quirk->mem[1]; memory_region_init_io(window->addr_mem, OBJECT(vdev), &vfio_generic_window_address_quirk, window, "vfio-ati-bar4-window-address-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, window->address_offset, window->addr_mem, 1); memory_region_init_io(window->data_mem, OBJECT(vdev), &vfio_generic_window_data_quirk, window, "vfio-ati-bar4-window-data-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, window->data_offset, window->data_mem, 1); QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); trace_vfio_quirk_ati_bar4_probe(vdev->vbasedev.name); }
false
qemu
f5793fd9e1fd89808f4adbfe690235b094176a37
static void vfio_probe_ati_bar4_quirk(VFIOPCIDevice *vdev, int nr) { VFIOQuirk *quirk; VFIOConfigWindowQuirk *window; if (!vfio_pci_is(vdev, PCI_VENDOR_ID_ATI, PCI_ANY_ID) || !vdev->has_vga || nr != 4) { return; } quirk = g_malloc0(sizeof(*quirk)); quirk->mem = g_new0(MemoryRegion, 2); quirk->nr_mem = 2; window = quirk->data = g_malloc0(sizeof(*window) + sizeof(VFIOConfigWindowMatch)); window->vdev = vdev; window->address_offset = 0; window->data_offset = 4; window->nr_matches = 1; window->matches[0].match = 0x4000; window->matches[0].mask = PCIE_CONFIG_SPACE_SIZE - 1; window->bar = nr; window->addr_mem = &quirk->mem[0]; window->data_mem = &quirk->mem[1]; memory_region_init_io(window->addr_mem, OBJECT(vdev), &vfio_generic_window_address_quirk, window, "vfio-ati-bar4-window-address-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, window->address_offset, window->addr_mem, 1); memory_region_init_io(window->data_mem, OBJECT(vdev), &vfio_generic_window_data_quirk, window, "vfio-ati-bar4-window-data-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, window->data_offset, window->data_mem, 1); QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); trace_vfio_quirk_ati_bar4_probe(vdev->vbasedev.name); }
{ "code": [], "line_no": [] }
static void FUNC_0(VFIOPCIDevice *VAR_0, int VAR_1) { VFIOQuirk *quirk; VFIOConfigWindowQuirk *window; if (!vfio_pci_is(VAR_0, PCI_VENDOR_ID_ATI, PCI_ANY_ID) || !VAR_0->has_vga || VAR_1 != 4) { return; } quirk = g_malloc0(sizeof(*quirk)); quirk->mem = g_new0(MemoryRegion, 2); quirk->nr_mem = 2; window = quirk->data = g_malloc0(sizeof(*window) + sizeof(VFIOConfigWindowMatch)); window->VAR_0 = VAR_0; window->address_offset = 0; window->data_offset = 4; window->nr_matches = 1; window->matches[0].match = 0x4000; window->matches[0].mask = PCIE_CONFIG_SPACE_SIZE - 1; window->bar = VAR_1; window->addr_mem = &quirk->mem[0]; window->data_mem = &quirk->mem[1]; memory_region_init_io(window->addr_mem, OBJECT(VAR_0), &vfio_generic_window_address_quirk, window, "vfio-ati-bar4-window-address-quirk", 4); memory_region_add_subregion_overlap(&VAR_0->bars[VAR_1].region.mem, window->address_offset, window->addr_mem, 1); memory_region_init_io(window->data_mem, OBJECT(VAR_0), &vfio_generic_window_data_quirk, window, "vfio-ati-bar4-window-data-quirk", 4); memory_region_add_subregion_overlap(&VAR_0->bars[VAR_1].region.mem, window->data_offset, window->data_mem, 1); QLIST_INSERT_HEAD(&VAR_0->bars[VAR_1].quirks, quirk, next); trace_vfio_quirk_ati_bar4_probe(VAR_0->vbasedev.name); }
[ "static void FUNC_0(VFIOPCIDevice *VAR_0, int VAR_1)\n{", "VFIOQuirk *quirk;", "VFIOConfigWindowQuirk *window;", "if (!vfio_pci_is(VAR_0, PCI_VENDOR_ID_ATI, PCI_ANY_ID) ||\n!VAR_0->has_vga || VAR_1 != 4) {", "return;", "}", "quirk = g_malloc0(sizeof(*quirk));", "quirk->mem = g_new0(MemoryRegion, 2);", "quirk->nr_mem = 2;", "window = quirk->data = g_malloc0(sizeof(*window) +\nsizeof(VFIOConfigWindowMatch));", "window->VAR_0 = VAR_0;", "window->address_offset = 0;", "window->data_offset = 4;", "window->nr_matches = 1;", "window->matches[0].match = 0x4000;", "window->matches[0].mask = PCIE_CONFIG_SPACE_SIZE - 1;", "window->bar = VAR_1;", "window->addr_mem = &quirk->mem[0];", "window->data_mem = &quirk->mem[1];", "memory_region_init_io(window->addr_mem, OBJECT(VAR_0),\n&vfio_generic_window_address_quirk, window,\n\"vfio-ati-bar4-window-address-quirk\", 4);", "memory_region_add_subregion_overlap(&VAR_0->bars[VAR_1].region.mem,\nwindow->address_offset,\nwindow->addr_mem, 1);", "memory_region_init_io(window->data_mem, OBJECT(VAR_0),\n&vfio_generic_window_data_quirk, window,\n\"vfio-ati-bar4-window-data-quirk\", 4);", "memory_region_add_subregion_overlap(&VAR_0->bars[VAR_1].region.mem,\nwindow->data_offset,\nwindow->data_mem, 1);", "QLIST_INSERT_HEAD(&VAR_0->bars[VAR_1].quirks, quirk, next);", "trace_vfio_quirk_ati_bar4_probe(VAR_0->vbasedev.name);", "}" ]
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16,873
int coroutine_fn bdrv_co_write_zeroes(BlockDriverState *bs, int64_t sector_num, int nb_sectors, BdrvRequestFlags flags) { trace_bdrv_co_write_zeroes(bs, sector_num, nb_sectors, flags); if (!(bs->open_flags & BDRV_O_UNMAP)) { flags &= ~BDRV_REQ_MAY_UNMAP; } return bdrv_co_do_writev(bs, sector_num, nb_sectors, NULL, BDRV_REQ_ZERO_WRITE | flags); }
false
qemu
fc3959e4669a1c2149b91ccb05101cfc7ae1fc05
int coroutine_fn bdrv_co_write_zeroes(BlockDriverState *bs, int64_t sector_num, int nb_sectors, BdrvRequestFlags flags) { trace_bdrv_co_write_zeroes(bs, sector_num, nb_sectors, flags); if (!(bs->open_flags & BDRV_O_UNMAP)) { flags &= ~BDRV_REQ_MAY_UNMAP; } return bdrv_co_do_writev(bs, sector_num, nb_sectors, NULL, BDRV_REQ_ZERO_WRITE | flags); }
{ "code": [], "line_no": [] }
int VAR_0 bdrv_co_write_zeroes(BlockDriverState *bs, int64_t sector_num, int nb_sectors, BdrvRequestFlags flags) { trace_bdrv_co_write_zeroes(bs, sector_num, nb_sectors, flags); if (!(bs->open_flags & BDRV_O_UNMAP)) { flags &= ~BDRV_REQ_MAY_UNMAP; } return bdrv_co_do_writev(bs, sector_num, nb_sectors, NULL, BDRV_REQ_ZERO_WRITE | flags); }
[ "int VAR_0 bdrv_co_write_zeroes(BlockDriverState *bs,\nint64_t sector_num, int nb_sectors,\nBdrvRequestFlags flags)\n{", "trace_bdrv_co_write_zeroes(bs, sector_num, nb_sectors, flags);", "if (!(bs->open_flags & BDRV_O_UNMAP)) {", "flags &= ~BDRV_REQ_MAY_UNMAP;", "}", "return bdrv_co_do_writev(bs, sector_num, nb_sectors, NULL,\nBDRV_REQ_ZERO_WRITE | flags);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5, 7 ], [ 9 ], [ 13 ], [ 15 ], [ 17 ], [ 21, 23 ], [ 25 ] ]
16,874
void axisdev88_init (ram_addr_t ram_size, int vga_ram_size, const char *boot_device, DisplayState *ds, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env; struct etraxfs_pic *pic; void *etraxfs_dmac; struct etraxfs_dma_client *eth[2] = {NULL, NULL}; int kernel_size; int i; int nand_regs; int gpio_regs; ram_addr_t phys_ram; ram_addr_t phys_intmem; /* init CPUs */ if (cpu_model == NULL) { cpu_model = "crisv32"; } env = cpu_init(cpu_model); qemu_register_reset(main_cpu_reset, env); /* allocate RAM */ phys_ram = qemu_ram_alloc(ram_size); cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM); /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the internal memory. */ phys_intmem = qemu_ram_alloc(INTMEM_SIZE); cpu_register_physical_memory(0x38000000, INTMEM_SIZE, phys_intmem | IO_MEM_RAM); /* Attach a NAND flash to CS1. */ nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state); cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); gpio_state.nand = &nand_state; gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state); cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); pic = etraxfs_pic_init(env, 0x3001c000); etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10); for (i = 0; i < 10; i++) { /* On ETRAX, odd numbered channels are inputs. */ etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1); } /* Add the two ethernet blocks. */ eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0x30034000); if (nb_nics > 1) eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0x30036000); /* The DMA Connector block is missing, hardwire things for now. */ etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]); etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1); if (eth[1]) { etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]); etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1); } /* 2 timers. */ etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3001e000); etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3005e000); for (i = 0; i < 4; i++) { if (serial_hds[i]) { etraxfs_ser_init(env, pic->irq + 0x14 + i, serial_hds[i], 0x30026000 + i * 0x2000); } } if (kernel_filename) { uint64_t entry, high; int kcmdline_len; /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis devboard SDK. */ kernel_size = load_elf(kernel_filename, -0x80000000LL, &entry, NULL, &high); bootstrap_pc = entry; if (kernel_size < 0) { /* Takes a kimage from the axis devboard SDK. */ kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000); bootstrap_pc = 0x40004000; env->regs[9] = 0x40004000 + kernel_size; } env->regs[8] = 0x56902387; /* RAM init magic. */ if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) { if (kcmdline_len > 256) { fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n"); exit(1); } pstrcpy_targphys(high, 256, kernel_cmdline); /* Let the kernel know we are modifying the cmdline. */ env->regs[10] = 0x87109563; env->regs[11] = high; } } env->pc = bootstrap_pc; printf ("pc =%x\n", env->pc); printf ("ram size =%ld\n", ram_size); }
false
qemu
c1e1a491906bd1d769edb16f2b2be7ff6833d26f
void axisdev88_init (ram_addr_t ram_size, int vga_ram_size, const char *boot_device, DisplayState *ds, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env; struct etraxfs_pic *pic; void *etraxfs_dmac; struct etraxfs_dma_client *eth[2] = {NULL, NULL}; int kernel_size; int i; int nand_regs; int gpio_regs; ram_addr_t phys_ram; ram_addr_t phys_intmem; if (cpu_model == NULL) { cpu_model = "crisv32"; } env = cpu_init(cpu_model); qemu_register_reset(main_cpu_reset, env); phys_ram = qemu_ram_alloc(ram_size); cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM); phys_intmem = qemu_ram_alloc(INTMEM_SIZE); cpu_register_physical_memory(0x38000000, INTMEM_SIZE, phys_intmem | IO_MEM_RAM); nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state); cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); gpio_state.nand = &nand_state; gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state); cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); pic = etraxfs_pic_init(env, 0x3001c000); etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10); for (i = 0; i < 10; i++) { etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1); } eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0x30034000); if (nb_nics > 1) eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0x30036000); etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]); etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1); if (eth[1]) { etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]); etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1); } etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3001e000); etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3005e000); for (i = 0; i < 4; i++) { if (serial_hds[i]) { etraxfs_ser_init(env, pic->irq + 0x14 + i, serial_hds[i], 0x30026000 + i * 0x2000); } } if (kernel_filename) { uint64_t entry, high; int kcmdline_len; kernel_size = load_elf(kernel_filename, -0x80000000LL, &entry, NULL, &high); bootstrap_pc = entry; if (kernel_size < 0) { kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000); bootstrap_pc = 0x40004000; env->regs[9] = 0x40004000 + kernel_size; } env->regs[8] = 0x56902387; if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) { if (kcmdline_len > 256) { fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n"); exit(1); } pstrcpy_targphys(high, 256, kernel_cmdline); env->regs[10] = 0x87109563; env->regs[11] = high; } } env->pc = bootstrap_pc; printf ("pc =%x\n", env->pc); printf ("ram size =%ld\n", ram_size); }
{ "code": [], "line_no": [] }
void FUNC_0 (ram_addr_t VAR_0, int VAR_1, const char *VAR_2, DisplayState *VAR_3, const char *VAR_4, const char *VAR_5, const char *VAR_6, const char *VAR_7) { CPUState *env; struct etraxfs_pic *VAR_8; void *VAR_9; struct etraxfs_dma_client *VAR_10[2] = {NULL, NULL}; int VAR_11; int VAR_12; int VAR_13; int VAR_14; ram_addr_t phys_ram; ram_addr_t phys_intmem; if (VAR_7 == NULL) { VAR_7 = "crisv32"; } env = cpu_init(VAR_7); qemu_register_reset(main_cpu_reset, env); phys_ram = qemu_ram_alloc(VAR_0); cpu_register_physical_memory(0x40000000, VAR_0, phys_ram | IO_MEM_RAM); phys_intmem = qemu_ram_alloc(INTMEM_SIZE); cpu_register_physical_memory(0x38000000, INTMEM_SIZE, phys_intmem | IO_MEM_RAM); nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); VAR_13 = cpu_register_io_memory(0, nand_read, nand_write, &nand_state); cpu_register_physical_memory(0x10000000, 0x05000000, VAR_13); gpio_state.nand = &nand_state; VAR_14 = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state); cpu_register_physical_memory(0x3001a000, 0x5c, VAR_14); VAR_8 = etraxfs_pic_init(env, 0x3001c000); VAR_9 = etraxfs_dmac_init(env, 0x30000000, 10); for (VAR_12 = 0; VAR_12 < 10; VAR_12++) { etraxfs_dmac_connect(VAR_9, VAR_12, VAR_8->irq + 7 + VAR_12, VAR_12 & 1); } VAR_10[0] = etraxfs_eth_init(&nd_table[0], env, VAR_8->irq + 25, 0x30034000); if (nb_nics > 1) VAR_10[1] = etraxfs_eth_init(&nd_table[1], env, VAR_8->irq + 26, 0x30036000); etraxfs_dmac_connect_client(VAR_9, 0, VAR_10[0]); etraxfs_dmac_connect_client(VAR_9, 1, VAR_10[0] + 1); if (VAR_10[1]) { etraxfs_dmac_connect_client(VAR_9, 6, VAR_10[1]); etraxfs_dmac_connect_client(VAR_9, 7, VAR_10[1] + 1); } etraxfs_timer_init(env, VAR_8->irq + 0x1b, VAR_8->nmi + 1, 0x3001e000); etraxfs_timer_init(env, VAR_8->irq + 0x1b, VAR_8->nmi + 1, 0x3005e000); for (VAR_12 = 0; VAR_12 < 4; VAR_12++) { if (serial_hds[VAR_12]) { etraxfs_ser_init(env, VAR_8->irq + 0x14 + VAR_12, serial_hds[VAR_12], 0x30026000 + VAR_12 * 0x2000); } } if (VAR_4) { uint64_t entry, high; int VAR_15; VAR_11 = load_elf(VAR_4, -0x80000000LL, &entry, NULL, &high); bootstrap_pc = entry; if (VAR_11 < 0) { VAR_11 = load_image(VAR_4, phys_ram_base + 0x4000); bootstrap_pc = 0x40004000; env->regs[9] = 0x40004000 + VAR_11; } env->regs[8] = 0x56902387; if (VAR_5 && (VAR_15 = strlen(VAR_5))) { if (VAR_15 > 256) { fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n"); exit(1); } pstrcpy_targphys(high, 256, VAR_5); env->regs[10] = 0x87109563; env->regs[11] = high; } } env->pc = bootstrap_pc; printf ("pc =%x\n", env->pc); printf ("ram size =%ld\n", VAR_0); }
[ "void FUNC_0 (ram_addr_t VAR_0, int VAR_1,\nconst char *VAR_2, DisplayState *VAR_3,\nconst char *VAR_4, const char *VAR_5,\nconst char *VAR_6, const char *VAR_7)\n{", "CPUState *env;", "struct etraxfs_pic *VAR_8;", "void *VAR_9;", "struct etraxfs_dma_client *VAR_10[2] = {NULL, NULL};", "int VAR_11;", "int VAR_12;", "int VAR_13;", "int VAR_14;", "ram_addr_t phys_ram;", "ram_addr_t phys_intmem;", "if (VAR_7 == NULL) {", "VAR_7 = \"crisv32\";", "}", "env = cpu_init(VAR_7);", "qemu_register_reset(main_cpu_reset, env);", "phys_ram = qemu_ram_alloc(VAR_0);", "cpu_register_physical_memory(0x40000000, VAR_0, phys_ram | IO_MEM_RAM);", "phys_intmem = qemu_ram_alloc(INTMEM_SIZE);", "cpu_register_physical_memory(0x38000000, INTMEM_SIZE,\nphys_intmem | IO_MEM_RAM);", "nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);", "VAR_13 = cpu_register_io_memory(0, nand_read, nand_write, &nand_state);", "cpu_register_physical_memory(0x10000000, 0x05000000, VAR_13);", "gpio_state.nand = &nand_state;", "VAR_14 = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state);", "cpu_register_physical_memory(0x3001a000, 0x5c, VAR_14);", "VAR_8 = etraxfs_pic_init(env, 0x3001c000);", "VAR_9 = etraxfs_dmac_init(env, 0x30000000, 10);", "for (VAR_12 = 0; VAR_12 < 10; VAR_12++) {", "etraxfs_dmac_connect(VAR_9, VAR_12, VAR_8->irq + 7 + VAR_12, VAR_12 & 1);", "}", "VAR_10[0] = etraxfs_eth_init(&nd_table[0], env, VAR_8->irq + 25, 0x30034000);", "if (nb_nics > 1)\nVAR_10[1] = etraxfs_eth_init(&nd_table[1], env, VAR_8->irq + 26, 0x30036000);", "etraxfs_dmac_connect_client(VAR_9, 0, VAR_10[0]);", "etraxfs_dmac_connect_client(VAR_9, 1, VAR_10[0] + 1);", "if (VAR_10[1]) {", "etraxfs_dmac_connect_client(VAR_9, 6, VAR_10[1]);", "etraxfs_dmac_connect_client(VAR_9, 7, VAR_10[1] + 1);", "}", "etraxfs_timer_init(env, VAR_8->irq + 0x1b, VAR_8->nmi + 1, 0x3001e000);", "etraxfs_timer_init(env, VAR_8->irq + 0x1b, VAR_8->nmi + 1, 0x3005e000);", "for (VAR_12 = 0; VAR_12 < 4; VAR_12++) {", "if (serial_hds[VAR_12]) {", "etraxfs_ser_init(env, VAR_8->irq + 0x14 + VAR_12,\nserial_hds[VAR_12], 0x30026000 + VAR_12 * 0x2000);", "}", "}", "if (VAR_4) {", "uint64_t entry, high;", "int VAR_15;", "VAR_11 = load_elf(VAR_4, -0x80000000LL,\n&entry, NULL, &high);", "bootstrap_pc = entry;", "if (VAR_11 < 0) {", "VAR_11 = load_image(VAR_4, phys_ram_base + 0x4000);", "bootstrap_pc = 0x40004000;", "env->regs[9] = 0x40004000 + VAR_11;", "}", "env->regs[8] = 0x56902387;", "if (VAR_5 && (VAR_15 = strlen(VAR_5))) {", "if (VAR_15 > 256) {", "fprintf(stderr, \"Too long CRIS kernel cmdline (max 256)\\n\");", "exit(1);", "}", "pstrcpy_targphys(high, 256, VAR_5);", "env->regs[10] = 0x87109563;", "env->regs[11] = high;", "}", "}", "env->pc = bootstrap_pc;", "printf (\"pc =%x\\n\", env->pc);", "printf (\"ram size =%ld\\n\", VAR_0);", "}" ]
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16,875
uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b) { float32 f0 = make_float32(a); float32 f1 = make_float32(b); return float32_val((float32_compare_quiet(f0, f1, NFS) == 1) ? float32_sub(f0, f1, NFS) : float32_sub(f1, f0, NFS)); }
false
qemu
79c18be7dfe660ab48f9f535e6cabd38c9f1d73b
uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b) { float32 f0 = make_float32(a); float32 f1 = make_float32(b); return float32_val((float32_compare_quiet(f0, f1, NFS) == 1) ? float32_sub(f0, f1, NFS) : float32_sub(f1, f0, NFS)); }
{ "code": [], "line_no": [] }
uint32_t FUNC_0(neon_abd_f32)(uint32_t a, uint32_t b) { float32 f0 = make_float32(a); float32 f1 = make_float32(b); return float32_val((float32_compare_quiet(f0, f1, NFS) == 1) ? float32_sub(f0, f1, NFS) : float32_sub(f1, f0, NFS)); }
[ "uint32_t FUNC_0(neon_abd_f32)(uint32_t a, uint32_t b)\n{", "float32 f0 = make_float32(a);", "float32 f1 = make_float32(b);", "return float32_val((float32_compare_quiet(f0, f1, NFS) == 1)\n? float32_sub(f0, f1, NFS)\n: float32_sub(f1, f0, NFS));", "}" ]
[ 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9, 11, 13 ], [ 15 ] ]
16,876
static void xen_init_pv(MachineState *machine) { DriveInfo *dinfo; int i; /* Initialize backend core & drivers */ if (xen_be_init() != 0) { fprintf(stderr, "%s: xen backend core setup failed\n", __FUNCTION__); exit(1); } switch (xen_mode) { case XEN_ATTACH: /* nothing to do, xend handles everything */ break; #ifdef CONFIG_XEN_PV_DOMAIN_BUILD case XEN_CREATE: { const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; if (xen_domain_build_pv(kernel_filename, initrd_filename, kernel_cmdline) < 0) { fprintf(stderr, "xen pv domain creation failed\n"); exit(1); } break; } #endif case XEN_EMULATE: fprintf(stderr, "xen emulation not implemented (yet)\n"); exit(1); break; default: fprintf(stderr, "unhandled xen_mode %d\n", xen_mode); exit(1); break; } xen_be_register_common(); xen_be_register("vfb", &xen_framebuffer_ops); xen_be_register("qnic", &xen_netdev_ops); /* configure framebuffer */ if (xenfb_enabled) { xen_config_dev_vfb(0, "vnc"); xen_config_dev_vkbd(0); } /* configure disks */ for (i = 0; i < 16; i++) { dinfo = drive_get(IF_XEN, 0, i); if (!dinfo) continue; xen_config_dev_blk(dinfo); } /* configure nics */ for (i = 0; i < nb_nics; i++) { if (!nd_table[i].model || 0 != strcmp(nd_table[i].model, "xen")) continue; xen_config_dev_nic(nd_table + i); } /* config cleanup hook */ atexit(xen_config_cleanup); /* setup framebuffer */ xen_init_display(xen_domid); }
false
qemu
9f2130f58d5dd4e1fcb435cca08bf77e7c32e6c6
static void xen_init_pv(MachineState *machine) { DriveInfo *dinfo; int i; if (xen_be_init() != 0) { fprintf(stderr, "%s: xen backend core setup failed\n", __FUNCTION__); exit(1); } switch (xen_mode) { case XEN_ATTACH: break; #ifdef CONFIG_XEN_PV_DOMAIN_BUILD case XEN_CREATE: { const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; if (xen_domain_build_pv(kernel_filename, initrd_filename, kernel_cmdline) < 0) { fprintf(stderr, "xen pv domain creation failed\n"); exit(1); } break; } #endif case XEN_EMULATE: fprintf(stderr, "xen emulation not implemented (yet)\n"); exit(1); break; default: fprintf(stderr, "unhandled xen_mode %d\n", xen_mode); exit(1); break; } xen_be_register_common(); xen_be_register("vfb", &xen_framebuffer_ops); xen_be_register("qnic", &xen_netdev_ops); if (xenfb_enabled) { xen_config_dev_vfb(0, "vnc"); xen_config_dev_vkbd(0); } for (i = 0; i < 16; i++) { dinfo = drive_get(IF_XEN, 0, i); if (!dinfo) continue; xen_config_dev_blk(dinfo); } for (i = 0; i < nb_nics; i++) { if (!nd_table[i].model || 0 != strcmp(nd_table[i].model, "xen")) continue; xen_config_dev_nic(nd_table + i); } atexit(xen_config_cleanup); xen_init_display(xen_domid); }
{ "code": [], "line_no": [] }
static void FUNC_0(MachineState *VAR_0) { DriveInfo *dinfo; int VAR_1; if (xen_be_init() != 0) { fprintf(stderr, "%s: xen backend core setup failed\n", __FUNCTION__); exit(1); } switch (xen_mode) { case XEN_ATTACH: break; #ifdef CONFIG_XEN_PV_DOMAIN_BUILD case XEN_CREATE: { const char *kernel_filename = VAR_0->kernel_filename; const char *kernel_cmdline = VAR_0->kernel_cmdline; const char *initrd_filename = VAR_0->initrd_filename; if (xen_domain_build_pv(kernel_filename, initrd_filename, kernel_cmdline) < 0) { fprintf(stderr, "xen pv domain creation failed\n"); exit(1); } break; } #endif case XEN_EMULATE: fprintf(stderr, "xen emulation not implemented (yet)\n"); exit(1); break; default: fprintf(stderr, "unhandled xen_mode %d\n", xen_mode); exit(1); break; } xen_be_register_common(); xen_be_register("vfb", &xen_framebuffer_ops); xen_be_register("qnic", &xen_netdev_ops); if (xenfb_enabled) { xen_config_dev_vfb(0, "vnc"); xen_config_dev_vkbd(0); } for (VAR_1 = 0; VAR_1 < 16; VAR_1++) { dinfo = drive_get(IF_XEN, 0, VAR_1); if (!dinfo) continue; xen_config_dev_blk(dinfo); } for (VAR_1 = 0; VAR_1 < nb_nics; VAR_1++) { if (!nd_table[VAR_1].model || 0 != strcmp(nd_table[VAR_1].model, "xen")) continue; xen_config_dev_nic(nd_table + VAR_1); } atexit(xen_config_cleanup); xen_init_display(xen_domid); }
[ "static void FUNC_0(MachineState *VAR_0)\n{", "DriveInfo *dinfo;", "int VAR_1;", "if (xen_be_init() != 0) {", "fprintf(stderr, \"%s: xen backend core setup failed\\n\", __FUNCTION__);", "exit(1);", "}", "switch (xen_mode) {", "case XEN_ATTACH:\nbreak;", "#ifdef CONFIG_XEN_PV_DOMAIN_BUILD\ncase XEN_CREATE: {", "const char *kernel_filename = VAR_0->kernel_filename;", "const char *kernel_cmdline = VAR_0->kernel_cmdline;", "const char *initrd_filename = VAR_0->initrd_filename;", "if (xen_domain_build_pv(kernel_filename, initrd_filename,\nkernel_cmdline) < 0) {", "fprintf(stderr, \"xen pv domain creation failed\\n\");", "exit(1);", "}", "break;", "}", "#endif\ncase XEN_EMULATE:\nfprintf(stderr, \"xen emulation not implemented (yet)\\n\");", "exit(1);", "break;", "default:\nfprintf(stderr, \"unhandled xen_mode %d\\n\", xen_mode);", "exit(1);", "break;", "}", "xen_be_register_common();", "xen_be_register(\"vfb\", &xen_framebuffer_ops);", "xen_be_register(\"qnic\", &xen_netdev_ops);", "if (xenfb_enabled) {", "xen_config_dev_vfb(0, \"vnc\");", "xen_config_dev_vkbd(0);", "}", "for (VAR_1 = 0; VAR_1 < 16; VAR_1++) {", "dinfo = drive_get(IF_XEN, 0, VAR_1);", "if (!dinfo)\ncontinue;", "xen_config_dev_blk(dinfo);", "}", "for (VAR_1 = 0; VAR_1 < nb_nics; VAR_1++) {", "if (!nd_table[VAR_1].model || 0 != strcmp(nd_table[VAR_1].model, \"xen\"))\ncontinue;", "xen_config_dev_nic(nd_table + VAR_1);", "}", "atexit(xen_config_cleanup);", "xen_init_display(xen_domid);", "}" ]
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16,877
static void iohandler_init(void) { if (!iohandler_ctx) { iohandler_ctx = aio_context_new(&error_abort); } }
false
qemu
c2b38b277a7882a592f4f2ec955084b2b756daaa
static void iohandler_init(void) { if (!iohandler_ctx) { iohandler_ctx = aio_context_new(&error_abort); } }
{ "code": [], "line_no": [] }
static void FUNC_0(void) { if (!iohandler_ctx) { iohandler_ctx = aio_context_new(&error_abort); } }
[ "static void FUNC_0(void)\n{", "if (!iohandler_ctx) {", "iohandler_ctx = aio_context_new(&error_abort);", "}", "}" ]
[ 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ] ]
16,878
static void tcg_out_tb_finalize(TCGContext *s) { static const void * const helpers[8] = { helper_ret_stb_mmu, helper_le_stw_mmu, helper_le_stl_mmu, helper_le_stq_mmu, helper_ret_ldub_mmu, helper_le_lduw_mmu, helper_le_ldul_mmu, helper_le_ldq_mmu, }; tcg_insn_unit *thunks[8] = { }; TCGLabelQemuLdst *l; for (l = s->be->labels; l != NULL; l = l->next) { long x = l->is_ld * 4 + l->size; tcg_insn_unit *dest = thunks[x]; /* The out-of-line thunks are all the same; load the return address from B0, load the GP, and branch to the code. Note that we are always post-call, so the register window has rolled, so we're using incoming parameter register numbers, not outgoing. */ if (dest == NULL) { uintptr_t *desc = (uintptr_t *)helpers[x]; uintptr_t func = desc[0], gp = desc[1], disp; thunks[x] = dest = s->code_ptr; tcg_out_bundle(s, mlx, INSN_NOP_M, tcg_opc_l2 (gp), tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, gp)); tcg_out_bundle(s, mii, INSN_NOP_M, INSN_NOP_I, tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, l->is_ld ? TCG_REG_R35 : TCG_REG_R36, TCG_REG_B0)); disp = (tcg_insn_unit *)func - s->code_ptr; tcg_out_bundle(s, mLX, INSN_NOP_M, tcg_opc_l3 (disp), tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, disp)); } reloc_pcrel21b_slot2(l->label_ptr, dest); } }
false
qemu
23dceda62a3643f734b7aa474fa6052593ae1a70
static void tcg_out_tb_finalize(TCGContext *s) { static const void * const helpers[8] = { helper_ret_stb_mmu, helper_le_stw_mmu, helper_le_stl_mmu, helper_le_stq_mmu, helper_ret_ldub_mmu, helper_le_lduw_mmu, helper_le_ldul_mmu, helper_le_ldq_mmu, }; tcg_insn_unit *thunks[8] = { }; TCGLabelQemuLdst *l; for (l = s->be->labels; l != NULL; l = l->next) { long x = l->is_ld * 4 + l->size; tcg_insn_unit *dest = thunks[x]; if (dest == NULL) { uintptr_t *desc = (uintptr_t *)helpers[x]; uintptr_t func = desc[0], gp = desc[1], disp; thunks[x] = dest = s->code_ptr; tcg_out_bundle(s, mlx, INSN_NOP_M, tcg_opc_l2 (gp), tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, gp)); tcg_out_bundle(s, mii, INSN_NOP_M, INSN_NOP_I, tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, l->is_ld ? TCG_REG_R35 : TCG_REG_R36, TCG_REG_B0)); disp = (tcg_insn_unit *)func - s->code_ptr; tcg_out_bundle(s, mLX, INSN_NOP_M, tcg_opc_l3 (disp), tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, disp)); } reloc_pcrel21b_slot2(l->label_ptr, dest); } }
{ "code": [], "line_no": [] }
static void FUNC_0(TCGContext *VAR_0) { static const void * const VAR_1[8] = { helper_ret_stb_mmu, helper_le_stw_mmu, helper_le_stl_mmu, helper_le_stq_mmu, helper_ret_ldub_mmu, helper_le_lduw_mmu, helper_le_ldul_mmu, helper_le_ldq_mmu, }; tcg_insn_unit *thunks[8] = { }; TCGLabelQemuLdst *l; for (l = VAR_0->be->labels; l != NULL; l = l->next) { long x = l->is_ld * 4 + l->size; tcg_insn_unit *dest = thunks[x]; if (dest == NULL) { uintptr_t *desc = (uintptr_t *)VAR_1[x]; uintptr_t func = desc[0], gp = desc[1], disp; thunks[x] = dest = VAR_0->code_ptr; tcg_out_bundle(VAR_0, mlx, INSN_NOP_M, tcg_opc_l2 (gp), tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, gp)); tcg_out_bundle(VAR_0, mii, INSN_NOP_M, INSN_NOP_I, tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, l->is_ld ? TCG_REG_R35 : TCG_REG_R36, TCG_REG_B0)); disp = (tcg_insn_unit *)func - VAR_0->code_ptr; tcg_out_bundle(VAR_0, mLX, INSN_NOP_M, tcg_opc_l3 (disp), tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, disp)); } reloc_pcrel21b_slot2(l->label_ptr, dest); } }
[ "static void FUNC_0(TCGContext *VAR_0)\n{", "static const void * const VAR_1[8] = {", "helper_ret_stb_mmu,\nhelper_le_stw_mmu,\nhelper_le_stl_mmu,\nhelper_le_stq_mmu,\nhelper_ret_ldub_mmu,\nhelper_le_lduw_mmu,\nhelper_le_ldul_mmu,\nhelper_le_ldq_mmu,\n};", "tcg_insn_unit *thunks[8] = { };", "TCGLabelQemuLdst *l;", "for (l = VAR_0->be->labels; l != NULL; l = l->next) {", "long x = l->is_ld * 4 + l->size;", "tcg_insn_unit *dest = thunks[x];", "if (dest == NULL) {", "uintptr_t *desc = (uintptr_t *)VAR_1[x];", "uintptr_t func = desc[0], gp = desc[1], disp;", "thunks[x] = dest = VAR_0->code_ptr;", "tcg_out_bundle(VAR_0, mlx,\nINSN_NOP_M,\ntcg_opc_l2 (gp),\ntcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,\nTCG_REG_R1, gp));", "tcg_out_bundle(VAR_0, mii,\nINSN_NOP_M,\nINSN_NOP_I,\ntcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,\nl->is_ld ? TCG_REG_R35 : TCG_REG_R36,\nTCG_REG_B0));", "disp = (tcg_insn_unit *)func - VAR_0->code_ptr;", "tcg_out_bundle(VAR_0, mLX,\nINSN_NOP_M,\ntcg_opc_l3 (disp),\ntcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, disp));", "}", "reloc_pcrel21b_slot2(l->label_ptr, dest);", "}", "}" ]
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16,880
void bdrv_set_dirty_iter(HBitmapIter *hbi, int64_t offset) { assert(hbi->hb); hbitmap_iter_init(hbi, hbi->hb, offset); }
false
qemu
dc162c8e4f088b08575460cca35b042d58c141aa
void bdrv_set_dirty_iter(HBitmapIter *hbi, int64_t offset) { assert(hbi->hb); hbitmap_iter_init(hbi, hbi->hb, offset); }
{ "code": [], "line_no": [] }
void FUNC_0(HBitmapIter *VAR_0, int64_t VAR_1) { assert(VAR_0->hb); hbitmap_iter_init(VAR_0, VAR_0->hb, VAR_1); }
[ "void FUNC_0(HBitmapIter *VAR_0, int64_t VAR_1)\n{", "assert(VAR_0->hb);", "hbitmap_iter_init(VAR_0, VAR_0->hb, VAR_1);", "}" ]
[ 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ] ]
16,881
static uint32_t qpi_mem_readw(void *opaque, target_phys_addr_t addr) { return 0; }
false
qemu
4a1418e07bdcfaa3177739e04707ecaec75d89e1
static uint32_t qpi_mem_readw(void *opaque, target_phys_addr_t addr) { return 0; }
{ "code": [], "line_no": [] }
static uint32_t FUNC_0(void *opaque, target_phys_addr_t addr) { return 0; }
[ "static uint32_t FUNC_0(void *opaque, target_phys_addr_t addr)\n{", "return 0;", "}" ]
[ 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ] ]
16,882
static av_always_inline void hl_decode_mb_idct_luma(const H264Context *h, H264SliceContext *sl, int mb_type, int simple, int transform_bypass, int pixel_shift, const int *block_offset, int linesize, uint8_t *dest_y, int p) { void (*idct_add)(uint8_t *dst, int16_t *block, int stride); int i; block_offset += 16 * p; if (!IS_INTRA4x4(mb_type)) { if (IS_INTRA16x16(mb_type)) { if (transform_bypass) { if (h->sps.profile_idc == 244 && (sl->intra16x16_pred_mode == VERT_PRED8x8 || sl->intra16x16_pred_mode == HOR_PRED8x8)) { h->hpc.pred16x16_add[sl->intra16x16_pred_mode](dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize); } else { for (i = 0; i < 16; i++) if (sl->non_zero_count_cache[scan8[i + p * 16]] || dctcoef_get(sl->mb, pixel_shift, i * 16 + p * 256)) h->h264dsp.h264_add_pixels4_clear(dest_y + block_offset[i], sl->mb + (i * 16 + p * 256 << pixel_shift), linesize); } } else { h->h264dsp.h264_idct_add16intra(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); } } else if (sl->cbp & 15) { if (transform_bypass) { const int di = IS_8x8DCT(mb_type) ? 4 : 1; idct_add = IS_8x8DCT(mb_type) ? h->h264dsp.h264_add_pixels8_clear : h->h264dsp.h264_add_pixels4_clear; for (i = 0; i < 16; i += di) if (sl->non_zero_count_cache[scan8[i + p * 16]]) idct_add(dest_y + block_offset[i], sl->mb + (i * 16 + p * 256 << pixel_shift), linesize); } else { if (IS_8x8DCT(mb_type)) h->h264dsp.h264_idct8_add4(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); else h->h264dsp.h264_idct_add16(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); } } } }
false
FFmpeg
3176217c60ca7828712985092d9102d331ea4f3d
static av_always_inline void hl_decode_mb_idct_luma(const H264Context *h, H264SliceContext *sl, int mb_type, int simple, int transform_bypass, int pixel_shift, const int *block_offset, int linesize, uint8_t *dest_y, int p) { void (*idct_add)(uint8_t *dst, int16_t *block, int stride); int i; block_offset += 16 * p; if (!IS_INTRA4x4(mb_type)) { if (IS_INTRA16x16(mb_type)) { if (transform_bypass) { if (h->sps.profile_idc == 244 && (sl->intra16x16_pred_mode == VERT_PRED8x8 || sl->intra16x16_pred_mode == HOR_PRED8x8)) { h->hpc.pred16x16_add[sl->intra16x16_pred_mode](dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize); } else { for (i = 0; i < 16; i++) if (sl->non_zero_count_cache[scan8[i + p * 16]] || dctcoef_get(sl->mb, pixel_shift, i * 16 + p * 256)) h->h264dsp.h264_add_pixels4_clear(dest_y + block_offset[i], sl->mb + (i * 16 + p * 256 << pixel_shift), linesize); } } else { h->h264dsp.h264_idct_add16intra(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); } } else if (sl->cbp & 15) { if (transform_bypass) { const int di = IS_8x8DCT(mb_type) ? 4 : 1; idct_add = IS_8x8DCT(mb_type) ? h->h264dsp.h264_add_pixels8_clear : h->h264dsp.h264_add_pixels4_clear; for (i = 0; i < 16; i += di) if (sl->non_zero_count_cache[scan8[i + p * 16]]) idct_add(dest_y + block_offset[i], sl->mb + (i * 16 + p * 256 << pixel_shift), linesize); } else { if (IS_8x8DCT(mb_type)) h->h264dsp.h264_idct8_add4(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); else h->h264dsp.h264_idct_add16(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); } } } }
{ "code": [], "line_no": [] }
static av_always_inline void FUNC_0(const H264Context *h, H264SliceContext *sl, int mb_type, int simple, int transform_bypass, int pixel_shift, const int *block_offset, int linesize, uint8_t *dest_y, int p) { void (*VAR_0)(uint8_t *VAR_1, int16_t *VAR_2, int VAR_3); int VAR_4; block_offset += 16 * p; if (!IS_INTRA4x4(mb_type)) { if (IS_INTRA16x16(mb_type)) { if (transform_bypass) { if (h->sps.profile_idc == 244 && (sl->intra16x16_pred_mode == VERT_PRED8x8 || sl->intra16x16_pred_mode == HOR_PRED8x8)) { h->hpc.pred16x16_add[sl->intra16x16_pred_mode](dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize); } else { for (VAR_4 = 0; VAR_4 < 16; VAR_4++) if (sl->non_zero_count_cache[scan8[VAR_4 + p * 16]] || dctcoef_get(sl->mb, pixel_shift, VAR_4 * 16 + p * 256)) h->h264dsp.h264_add_pixels4_clear(dest_y + block_offset[VAR_4], sl->mb + (VAR_4 * 16 + p * 256 << pixel_shift), linesize); } } else { h->h264dsp.h264_idct_add16intra(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); } } else if (sl->cbp & 15) { if (transform_bypass) { const int VAR_5 = IS_8x8DCT(mb_type) ? 4 : 1; VAR_0 = IS_8x8DCT(mb_type) ? h->h264dsp.h264_add_pixels8_clear : h->h264dsp.h264_add_pixels4_clear; for (VAR_4 = 0; VAR_4 < 16; VAR_4 += VAR_5) if (sl->non_zero_count_cache[scan8[VAR_4 + p * 16]]) VAR_0(dest_y + block_offset[VAR_4], sl->mb + (VAR_4 * 16 + p * 256 << pixel_shift), linesize); } else { if (IS_8x8DCT(mb_type)) h->h264dsp.h264_idct8_add4(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); else h->h264dsp.h264_idct_add16(dest_y, block_offset, sl->mb + (p * 256 << pixel_shift), linesize, sl->non_zero_count_cache + p * 5 * 8); } } } }
[ "static av_always_inline void FUNC_0(const H264Context *h, H264SliceContext *sl,\nint mb_type, int simple,\nint transform_bypass,\nint pixel_shift,\nconst int *block_offset,\nint linesize,\nuint8_t *dest_y, int p)\n{", "void (*VAR_0)(uint8_t *VAR_1, int16_t *VAR_2, int VAR_3);", "int VAR_4;", "block_offset += 16 * p;", "if (!IS_INTRA4x4(mb_type)) {", "if (IS_INTRA16x16(mb_type)) {", "if (transform_bypass) {", "if (h->sps.profile_idc == 244 &&\n(sl->intra16x16_pred_mode == VERT_PRED8x8 ||\nsl->intra16x16_pred_mode == HOR_PRED8x8)) {", "h->hpc.pred16x16_add[sl->intra16x16_pred_mode](dest_y, block_offset,\nsl->mb + (p * 256 << pixel_shift),\nlinesize);", "} else {", "for (VAR_4 = 0; VAR_4 < 16; VAR_4++)", "if (sl->non_zero_count_cache[scan8[VAR_4 + p * 16]] ||\ndctcoef_get(sl->mb, pixel_shift, VAR_4 * 16 + p * 256))\nh->h264dsp.h264_add_pixels4_clear(dest_y + block_offset[VAR_4],\nsl->mb + (VAR_4 * 16 + p * 256 << pixel_shift),\nlinesize);", "}", "} else {", "h->h264dsp.h264_idct_add16intra(dest_y, block_offset,\nsl->mb + (p * 256 << pixel_shift),\nlinesize,\nsl->non_zero_count_cache + p * 5 * 8);", "}", "} else if (sl->cbp & 15) {", "if (transform_bypass) {", "const int VAR_5 = IS_8x8DCT(mb_type) ? 4 : 1;", "VAR_0 = IS_8x8DCT(mb_type) ? h->h264dsp.h264_add_pixels8_clear\n: h->h264dsp.h264_add_pixels4_clear;", "for (VAR_4 = 0; VAR_4 < 16; VAR_4 += VAR_5)", "if (sl->non_zero_count_cache[scan8[VAR_4 + p * 16]])\nVAR_0(dest_y + block_offset[VAR_4],\nsl->mb + (VAR_4 * 16 + p * 256 << pixel_shift),\nlinesize);", "} else {", "if (IS_8x8DCT(mb_type))\nh->h264dsp.h264_idct8_add4(dest_y, block_offset,\nsl->mb + (p * 256 << pixel_shift),\nlinesize,\nsl->non_zero_count_cache + p * 5 * 8);", "else\nh->h264dsp.h264_idct_add16(dest_y, block_offset,\nsl->mb + (p * 256 << pixel_shift),\nlinesize,\nsl->non_zero_count_cache + p * 5 * 8);", "}", "}", "}", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5, 7, 9, 11, 13, 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ], [ 27 ], [ 29, 31, 33 ], [ 35, 37, 39 ], [ 41 ], [ 43 ], [ 45, 47, 49, 51, 53 ], [ 55 ], [ 57 ], [ 59, 61, 63, 65 ], [ 67 ], [ 69 ], [ 71 ], [ 73 ], [ 75, 77 ], [ 79 ], [ 81, 83, 85, 87 ], [ 89 ], [ 91, 93, 95, 97, 99 ], [ 101, 103, 105, 107, 109 ], [ 111 ], [ 113 ], [ 115 ], [ 117 ] ]
16,883
static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) { TCGv_i32 r_asi, r_size, r_sign; TCGv_i64 s64, d64 = tcg_temp_new_i64(); r_asi = gen_get_asi(dc, insn); r_size = tcg_const_i32(1); r_sign = tcg_const_i32(0); gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_size, r_sign); tcg_temp_free_i32(r_sign); s64 = tcg_const_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size); tcg_temp_free_i64(s64); tcg_temp_free_i32(r_size); tcg_temp_free_i32(r_asi); tcg_gen_trunc_i64_tl(dst, d64); tcg_temp_free_i64(d64); }
false
qemu
7ec1e5ea4bd0700fa48da86bffa2fcc6146c410a
static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) { TCGv_i32 r_asi, r_size, r_sign; TCGv_i64 s64, d64 = tcg_temp_new_i64(); r_asi = gen_get_asi(dc, insn); r_size = tcg_const_i32(1); r_sign = tcg_const_i32(0); gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_size, r_sign); tcg_temp_free_i32(r_sign); s64 = tcg_const_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size); tcg_temp_free_i64(s64); tcg_temp_free_i32(r_size); tcg_temp_free_i32(r_asi); tcg_gen_trunc_i64_tl(dst, d64); tcg_temp_free_i64(d64); }
{ "code": [], "line_no": [] }
static void FUNC_0(DisasContext *VAR_0, TCGv VAR_1, TCGv VAR_2, int VAR_3) { TCGv_i32 r_asi, r_size, r_sign; TCGv_i64 s64, d64 = tcg_temp_new_i64(); r_asi = gen_get_asi(VAR_0, VAR_3); r_size = tcg_const_i32(1); r_sign = tcg_const_i32(0); gen_helper_ld_asi(d64, cpu_env, VAR_2, r_asi, r_size, r_sign); tcg_temp_free_i32(r_sign); s64 = tcg_const_i64(0xff); gen_helper_st_asi(cpu_env, VAR_2, s64, r_asi, r_size); tcg_temp_free_i64(s64); tcg_temp_free_i32(r_size); tcg_temp_free_i32(r_asi); tcg_gen_trunc_i64_tl(VAR_1, d64); tcg_temp_free_i64(d64); }
[ "static void FUNC_0(DisasContext *VAR_0, TCGv VAR_1, TCGv VAR_2, int VAR_3)\n{", "TCGv_i32 r_asi, r_size, r_sign;", "TCGv_i64 s64, d64 = tcg_temp_new_i64();", "r_asi = gen_get_asi(VAR_0, VAR_3);", "r_size = tcg_const_i32(1);", "r_sign = tcg_const_i32(0);", "gen_helper_ld_asi(d64, cpu_env, VAR_2, r_asi, r_size, r_sign);", "tcg_temp_free_i32(r_sign);", "s64 = tcg_const_i64(0xff);", "gen_helper_st_asi(cpu_env, VAR_2, s64, r_asi, r_size);", "tcg_temp_free_i64(s64);", "tcg_temp_free_i32(r_size);", "tcg_temp_free_i32(r_asi);", "tcg_gen_trunc_i64_tl(VAR_1, d64);", "tcg_temp_free_i64(d64);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 23 ], [ 25 ], [ 27 ], [ 29 ], [ 31 ], [ 35 ], [ 37 ], [ 39 ] ]
16,884
float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env) { return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status)); }
false
qemu
e8ede0a8bb5298a6979bcf7ed84ef64a64a4e3fe
float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env) { return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status)); }
{ "code": [], "line_no": [] }
float32 FUNC_0(ucf64_df2si)(float64 x, CPUUniCore32State *env) { return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status)); }
[ "float32 FUNC_0(ucf64_df2si)(float64 x, CPUUniCore32State *env)\n{", "return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));", "}" ]
[ 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ] ]
16,885
static int local_link(FsContext *ctx, V9fsPath *oldpath, V9fsPath *dirpath, const char *name) { int ret; V9fsString newpath; char buffer[PATH_MAX], buffer1[PATH_MAX]; v9fs_string_init(&newpath); v9fs_string_sprintf(&newpath, "%s/%s", dirpath->data, name); ret = link(rpath(ctx, oldpath->data, buffer), rpath(ctx, newpath.data, buffer1)); /* now link the virtfs_metadata files */ if (!ret && (ctx->export_flags & V9FS_SM_MAPPED_FILE)) { /* Link the .virtfs_metadata files. Create the metada directory */ ret = local_create_mapped_attr_dir(ctx, newpath.data); if (ret < 0) { goto err_out; } ret = link(local_mapped_attr_path(ctx, oldpath->data, buffer), local_mapped_attr_path(ctx, newpath.data, buffer1)); if (ret < 0 && errno != ENOENT) { goto err_out; } } err_out: v9fs_string_free(&newpath); return ret; }
false
qemu
4fa4ce7107c6ec432f185307158c5df91ce54308
static int local_link(FsContext *ctx, V9fsPath *oldpath, V9fsPath *dirpath, const char *name) { int ret; V9fsString newpath; char buffer[PATH_MAX], buffer1[PATH_MAX]; v9fs_string_init(&newpath); v9fs_string_sprintf(&newpath, "%s/%s", dirpath->data, name); ret = link(rpath(ctx, oldpath->data, buffer), rpath(ctx, newpath.data, buffer1)); if (!ret && (ctx->export_flags & V9FS_SM_MAPPED_FILE)) { ret = local_create_mapped_attr_dir(ctx, newpath.data); if (ret < 0) { goto err_out; } ret = link(local_mapped_attr_path(ctx, oldpath->data, buffer), local_mapped_attr_path(ctx, newpath.data, buffer1)); if (ret < 0 && errno != ENOENT) { goto err_out; } } err_out: v9fs_string_free(&newpath); return ret; }
{ "code": [], "line_no": [] }
static int FUNC_0(FsContext *VAR_0, V9fsPath *VAR_1, V9fsPath *VAR_2, const char *VAR_3) { int VAR_4; V9fsString newpath; char VAR_5[PATH_MAX], buffer1[PATH_MAX]; v9fs_string_init(&newpath); v9fs_string_sprintf(&newpath, "%s/%s", VAR_2->data, VAR_3); VAR_4 = link(rpath(VAR_0, VAR_1->data, VAR_5), rpath(VAR_0, newpath.data, buffer1)); if (!VAR_4 && (VAR_0->export_flags & V9FS_SM_MAPPED_FILE)) { VAR_4 = local_create_mapped_attr_dir(VAR_0, newpath.data); if (VAR_4 < 0) { goto err_out; } VAR_4 = link(local_mapped_attr_path(VAR_0, VAR_1->data, VAR_5), local_mapped_attr_path(VAR_0, newpath.data, buffer1)); if (VAR_4 < 0 && errno != ENOENT) { goto err_out; } } err_out: v9fs_string_free(&newpath); return VAR_4; }
[ "static int FUNC_0(FsContext *VAR_0, V9fsPath *VAR_1,\nV9fsPath *VAR_2, const char *VAR_3)\n{", "int VAR_4;", "V9fsString newpath;", "char VAR_5[PATH_MAX], buffer1[PATH_MAX];", "v9fs_string_init(&newpath);", "v9fs_string_sprintf(&newpath, \"%s/%s\", VAR_2->data, VAR_3);", "VAR_4 = link(rpath(VAR_0, VAR_1->data, VAR_5),\nrpath(VAR_0, newpath.data, buffer1));", "if (!VAR_4 && (VAR_0->export_flags & V9FS_SM_MAPPED_FILE)) {", "VAR_4 = local_create_mapped_attr_dir(VAR_0, newpath.data);", "if (VAR_4 < 0) {", "goto err_out;", "}", "VAR_4 = link(local_mapped_attr_path(VAR_0, VAR_1->data, VAR_5),\nlocal_mapped_attr_path(VAR_0, newpath.data, buffer1));", "if (VAR_4 < 0 && errno != ENOENT) {", "goto err_out;", "}", "}", "err_out:\nv9fs_string_free(&newpath);", "return VAR_4;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5 ], [ 7 ], [ 9 ], [ 11 ], [ 15 ], [ 17 ], [ 21, 23 ], [ 29 ], [ 33 ], [ 35 ], [ 37 ], [ 39 ], [ 41, 43 ], [ 45 ], [ 47 ], [ 49 ], [ 51 ], [ 53, 55 ], [ 57 ], [ 59 ] ]
16,886
void ff_avg_h264_qpel4_mc02_msa(uint8_t *dst, const uint8_t *src, ptrdiff_t stride) { avc_luma_vt_and_aver_dst_4x4_msa(src - (stride * 2), stride, dst, stride); }
false
FFmpeg
72dbc610be3272ba36603f78a39cc2d2d8fe0cc3
void ff_avg_h264_qpel4_mc02_msa(uint8_t *dst, const uint8_t *src, ptrdiff_t stride) { avc_luma_vt_and_aver_dst_4x4_msa(src - (stride * 2), stride, dst, stride); }
{ "code": [], "line_no": [] }
void FUNC_0(uint8_t *VAR_0, const uint8_t *VAR_1, ptrdiff_t VAR_2) { avc_luma_vt_and_aver_dst_4x4_msa(VAR_1 - (VAR_2 * 2), VAR_2, VAR_0, VAR_2); }
[ "void FUNC_0(uint8_t *VAR_0, const uint8_t *VAR_1,\nptrdiff_t VAR_2)\n{", "avc_luma_vt_and_aver_dst_4x4_msa(VAR_1 - (VAR_2 * 2), VAR_2, VAR_0, VAR_2);", "}" ]
[ 0, 0, 0 ]
[ [ 1, 3, 5 ], [ 7 ], [ 9 ] ]
16,887
static void commit_complete(BlockJob *job, void *opaque) { CommitBlockJob *s = container_of(job, CommitBlockJob, common); CommitCompleteData *data = opaque; BlockDriverState *active = s->active; BlockDriverState *top = blk_bs(s->top); BlockDriverState *base = blk_bs(s->base); BlockDriverState *overlay_bs = bdrv_find_overlay(active, top); int ret = data->ret; if (!block_job_is_cancelled(&s->common) && ret == 0) { /* success */ ret = bdrv_drop_intermediate(active, top, base, s->backing_file_str); } /* restore base open flags here if appropriate (e.g., change the base back * to r/o). These reopens do not need to be atomic, since we won't abort * even on failure here */ if (s->base_flags != bdrv_get_flags(base)) { bdrv_reopen(base, s->base_flags, NULL); } if (overlay_bs && s->orig_overlay_flags != bdrv_get_flags(overlay_bs)) { bdrv_reopen(overlay_bs, s->orig_overlay_flags, NULL); } g_free(s->backing_file_str); blk_unref(s->top); blk_unref(s->base); block_job_completed(&s->common, ret); g_free(data); }
false
qemu
8dfba2797761d8a43744e4e6571c8175e448a478
static void commit_complete(BlockJob *job, void *opaque) { CommitBlockJob *s = container_of(job, CommitBlockJob, common); CommitCompleteData *data = opaque; BlockDriverState *active = s->active; BlockDriverState *top = blk_bs(s->top); BlockDriverState *base = blk_bs(s->base); BlockDriverState *overlay_bs = bdrv_find_overlay(active, top); int ret = data->ret; if (!block_job_is_cancelled(&s->common) && ret == 0) { ret = bdrv_drop_intermediate(active, top, base, s->backing_file_str); } if (s->base_flags != bdrv_get_flags(base)) { bdrv_reopen(base, s->base_flags, NULL); } if (overlay_bs && s->orig_overlay_flags != bdrv_get_flags(overlay_bs)) { bdrv_reopen(overlay_bs, s->orig_overlay_flags, NULL); } g_free(s->backing_file_str); blk_unref(s->top); blk_unref(s->base); block_job_completed(&s->common, ret); g_free(data); }
{ "code": [], "line_no": [] }
static void FUNC_0(BlockJob *VAR_0, void *VAR_1) { CommitBlockJob *s = container_of(VAR_0, CommitBlockJob, common); CommitCompleteData *data = VAR_1; BlockDriverState *active = s->active; BlockDriverState *top = blk_bs(s->top); BlockDriverState *base = blk_bs(s->base); BlockDriverState *overlay_bs = bdrv_find_overlay(active, top); int VAR_2 = data->VAR_2; if (!block_job_is_cancelled(&s->common) && VAR_2 == 0) { VAR_2 = bdrv_drop_intermediate(active, top, base, s->backing_file_str); } if (s->base_flags != bdrv_get_flags(base)) { bdrv_reopen(base, s->base_flags, NULL); } if (overlay_bs && s->orig_overlay_flags != bdrv_get_flags(overlay_bs)) { bdrv_reopen(overlay_bs, s->orig_overlay_flags, NULL); } g_free(s->backing_file_str); blk_unref(s->top); blk_unref(s->base); block_job_completed(&s->common, VAR_2); g_free(data); }
[ "static void FUNC_0(BlockJob *VAR_0, void *VAR_1)\n{", "CommitBlockJob *s = container_of(VAR_0, CommitBlockJob, common);", "CommitCompleteData *data = VAR_1;", "BlockDriverState *active = s->active;", "BlockDriverState *top = blk_bs(s->top);", "BlockDriverState *base = blk_bs(s->base);", "BlockDriverState *overlay_bs = bdrv_find_overlay(active, top);", "int VAR_2 = data->VAR_2;", "if (!block_job_is_cancelled(&s->common) && VAR_2 == 0) {", "VAR_2 = bdrv_drop_intermediate(active, top, base, s->backing_file_str);", "}", "if (s->base_flags != bdrv_get_flags(base)) {", "bdrv_reopen(base, s->base_flags, NULL);", "}", "if (overlay_bs && s->orig_overlay_flags != bdrv_get_flags(overlay_bs)) {", "bdrv_reopen(overlay_bs, s->orig_overlay_flags, NULL);", "}", "g_free(s->backing_file_str);", "blk_unref(s->top);", "blk_unref(s->base);", "block_job_completed(&s->common, VAR_2);", "g_free(data);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 21 ], [ 25 ], [ 27 ], [ 37 ], [ 39 ], [ 41 ], [ 43 ], [ 45 ], [ 47 ], [ 49 ], [ 51 ], [ 53 ], [ 55 ], [ 57 ], [ 59 ] ]
16,889
static int ide_drive_post_load(void *opaque, int version_id) { IDEState *s = opaque; if (s->identify_set) { blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5))); } return 0; }
false
qemu
6b896ab261942f441a16836e3fa3c83f3f4488b9
static int ide_drive_post_load(void *opaque, int version_id) { IDEState *s = opaque; if (s->identify_set) { blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5))); } return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(void *VAR_0, int VAR_1) { IDEState *s = VAR_0; if (s->identify_set) { blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5))); } return 0; }
[ "static int FUNC_0(void *VAR_0, int VAR_1)\n{", "IDEState *s = VAR_0;", "if (s->identify_set) {", "blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));", "}", "return 0;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ] ]
16,892
void do_migrate_set_downtime(Monitor *mon, const QDict *qdict) { char *ptr; double d; const char *value = qdict_get_str(qdict, "value"); d = strtod(value, &ptr); if (!strcmp(ptr,"ms")) { d *= 1000000; } else if (!strcmp(ptr,"us")) { d *= 1000; } else if (!strcmp(ptr,"ns")) { } else { /* all else considered to be seconds */ d *= 1000000000; } max_downtime = (uint64_t)d; }
false
qemu
b0fbf7d3420f5f66be9728b1b070846bb054c872
void do_migrate_set_downtime(Monitor *mon, const QDict *qdict) { char *ptr; double d; const char *value = qdict_get_str(qdict, "value"); d = strtod(value, &ptr); if (!strcmp(ptr,"ms")) { d *= 1000000; } else if (!strcmp(ptr,"us")) { d *= 1000; } else if (!strcmp(ptr,"ns")) { } else { d *= 1000000000; } max_downtime = (uint64_t)d; }
{ "code": [], "line_no": [] }
void FUNC_0(Monitor *VAR_0, const QDict *VAR_1) { char *VAR_2; double VAR_3; const char *VAR_4 = qdict_get_str(VAR_1, "VAR_4"); VAR_3 = strtod(VAR_4, &VAR_2); if (!strcmp(VAR_2,"ms")) { VAR_3 *= 1000000; } else if (!strcmp(VAR_2,"us")) { VAR_3 *= 1000; } else if (!strcmp(VAR_2,"ns")) { } else { VAR_3 *= 1000000000; } max_downtime = (uint64_t)VAR_3; }
[ "void FUNC_0(Monitor *VAR_0, const QDict *VAR_1)\n{", "char *VAR_2;", "double VAR_3;", "const char *VAR_4 = qdict_get_str(VAR_1, \"VAR_4\");", "VAR_3 = strtod(VAR_4, &VAR_2);", "if (!strcmp(VAR_2,\"ms\")) {", "VAR_3 *= 1000000;", "} else if (!strcmp(VAR_2,\"us\")) {", "VAR_3 *= 1000;", "} else if (!strcmp(VAR_2,\"ns\")) {", "} else {", "VAR_3 *= 1000000000;", "}", "max_downtime = (uint64_t)VAR_3;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ], [ 29 ], [ 31 ], [ 35 ], [ 37 ] ]
16,893
int kvm_set_ioeventfd_pio_word(int fd, uint16_t addr, uint16_t val, bool assign) { struct kvm_ioeventfd kick = { .datamatch = val, .addr = addr, .len = 2, .flags = KVM_IOEVENTFD_FLAG_DATAMATCH | KVM_IOEVENTFD_FLAG_PIO, .fd = fd, }; int r; if (!kvm_enabled()) return -ENOSYS; if (!assign) kick.flags |= KVM_IOEVENTFD_FLAG_DEASSIGN; r = kvm_vm_ioctl(kvm_state, KVM_IOEVENTFD, &kick); if (r < 0) return r; return 0; }
false
qemu
98c8573eb37bf5d7bb0c07225985a78537c73101
int kvm_set_ioeventfd_pio_word(int fd, uint16_t addr, uint16_t val, bool assign) { struct kvm_ioeventfd kick = { .datamatch = val, .addr = addr, .len = 2, .flags = KVM_IOEVENTFD_FLAG_DATAMATCH | KVM_IOEVENTFD_FLAG_PIO, .fd = fd, }; int r; if (!kvm_enabled()) return -ENOSYS; if (!assign) kick.flags |= KVM_IOEVENTFD_FLAG_DEASSIGN; r = kvm_vm_ioctl(kvm_state, KVM_IOEVENTFD, &kick); if (r < 0) return r; return 0; }
{ "code": [], "line_no": [] }
int FUNC_0(int VAR_0, uint16_t VAR_1, uint16_t VAR_2, bool VAR_3) { struct kvm_ioeventfd VAR_4 = { .datamatch = VAR_2, .VAR_1 = VAR_1, .len = 2, .flags = KVM_IOEVENTFD_FLAG_DATAMATCH | KVM_IOEVENTFD_FLAG_PIO, .VAR_0 = VAR_0, }; int VAR_5; if (!kvm_enabled()) return -ENOSYS; if (!VAR_3) VAR_4.flags |= KVM_IOEVENTFD_FLAG_DEASSIGN; VAR_5 = kvm_vm_ioctl(kvm_state, KVM_IOEVENTFD, &VAR_4); if (VAR_5 < 0) return VAR_5; return 0; }
[ "int FUNC_0(int VAR_0, uint16_t VAR_1, uint16_t VAR_2, bool VAR_3)\n{", "struct kvm_ioeventfd VAR_4 = {", ".datamatch = VAR_2,\n.VAR_1 = VAR_1,\n.len = 2,\n.flags = KVM_IOEVENTFD_FLAG_DATAMATCH | KVM_IOEVENTFD_FLAG_PIO,\n.VAR_0 = VAR_0,\n};", "int VAR_5;", "if (!kvm_enabled())\nreturn -ENOSYS;", "if (!VAR_3)\nVAR_4.flags |= KVM_IOEVENTFD_FLAG_DEASSIGN;", "VAR_5 = kvm_vm_ioctl(kvm_state, KVM_IOEVENTFD, &VAR_4);", "if (VAR_5 < 0)\nreturn VAR_5;", "return 0;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7, 9, 11, 13, 15, 17 ], [ 19 ], [ 21, 23 ], [ 25, 27 ], [ 29 ], [ 31, 33 ], [ 35 ], [ 37 ] ]
16,896
static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest) { if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); tcg_gen_exit_tb((uintptr_t)s->tb + n); } else { TCGv addr = tcg_temp_new(); gen_set_pc_im(s, dest); tcg_gen_extu_i32_tl(addr, cpu_R[15]); tcg_gen_lookup_and_goto_ptr(addr); tcg_temp_free(addr); } }
false
qemu
8a6b28c7b5104263344508df0f4bce97f22cfcaf
static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest) { if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); tcg_gen_exit_tb((uintptr_t)s->tb + n); } else { TCGv addr = tcg_temp_new(); gen_set_pc_im(s, dest); tcg_gen_extu_i32_tl(addr, cpu_R[15]); tcg_gen_lookup_and_goto_ptr(addr); tcg_temp_free(addr); } }
{ "code": [], "line_no": [] }
static inline void FUNC_0(DisasContext *VAR_0, int VAR_1, target_ulong VAR_2) { if (use_goto_tb(VAR_0, VAR_2)) { tcg_gen_goto_tb(VAR_1); gen_set_pc_im(VAR_0, VAR_2); tcg_gen_exit_tb((uintptr_t)VAR_0->tb + VAR_1); } else { TCGv addr = tcg_temp_new(); gen_set_pc_im(VAR_0, VAR_2); tcg_gen_extu_i32_tl(addr, cpu_R[15]); tcg_gen_lookup_and_goto_ptr(addr); tcg_temp_free(addr); } }
[ "static inline void FUNC_0(DisasContext *VAR_0, int VAR_1, target_ulong VAR_2)\n{", "if (use_goto_tb(VAR_0, VAR_2)) {", "tcg_gen_goto_tb(VAR_1);", "gen_set_pc_im(VAR_0, VAR_2);", "tcg_gen_exit_tb((uintptr_t)VAR_0->tb + VAR_1);", "} else {", "TCGv addr = tcg_temp_new();", "gen_set_pc_im(VAR_0, VAR_2);", "tcg_gen_extu_i32_tl(addr, cpu_R[15]);", "tcg_gen_lookup_and_goto_ptr(addr);", "tcg_temp_free(addr);", "}", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ], [ 27 ], [ 29 ] ]
16,899
static int img_convert(int argc, char **argv) { int c, n, n1, bs_n, bs_i, compress, cluster_sectors, skip_create; int64_t ret = 0; int progress = 0, flags; const char *fmt, *out_fmt, *cache, *out_baseimg, *out_filename; BlockDriver *drv, *proto_drv; BlockDriverState **bs = NULL, *out_bs = NULL; int64_t total_sectors, nb_sectors, sector_num, bs_offset; int64_t *bs_sectors = NULL; uint8_t * buf = NULL; size_t bufsectors = IO_BUF_SIZE / BDRV_SECTOR_SIZE; const uint8_t *buf1; BlockDriverInfo bdi; QemuOpts *opts = NULL; QemuOptsList *create_opts = NULL; const char *out_baseimg_param; char *options = NULL; const char *snapshot_name = NULL; int min_sparse = 8; /* Need at least 4k of zeros for sparse detection */ bool quiet = false; Error *local_err = NULL; QemuOpts *sn_opts = NULL; fmt = NULL; out_fmt = "raw"; cache = "unsafe"; out_baseimg = NULL; compress = 0; skip_create = 0; for(;;) { c = getopt(argc, argv, "f:O:B:s:hce6o:pS:t:qnl:"); if (c == -1) { break; } switch(c) { case '?': case 'h': help(); break; case 'f': fmt = optarg; break; case 'O': out_fmt = optarg; break; case 'B': out_baseimg = optarg; break; case 'c': compress = 1; break; case 'e': error_report("option -e is deprecated, please use \'-o " "encryption\' instead!"); ret = -1; goto fail_getopt; case '6': error_report("option -6 is deprecated, please use \'-o " "compat6\' instead!"); ret = -1; goto fail_getopt; case 'o': if (!is_valid_option_list(optarg)) { error_report("Invalid option list: %s", optarg); ret = -1; goto fail_getopt; } if (!options) { options = g_strdup(optarg); } else { char *old_options = options; options = g_strdup_printf("%s,%s", options, optarg); g_free(old_options); } break; case 's': snapshot_name = optarg; break; case 'l': if (strstart(optarg, SNAPSHOT_OPT_BASE, NULL)) { sn_opts = qemu_opts_parse(&internal_snapshot_opts, optarg, 0); if (!sn_opts) { error_report("Failed in parsing snapshot param '%s'", optarg); ret = -1; goto fail_getopt; } } else { snapshot_name = optarg; } break; case 'S': { int64_t sval; char *end; sval = strtosz_suffix(optarg, &end, STRTOSZ_DEFSUFFIX_B); if (sval < 0 || *end) { error_report("Invalid minimum zero buffer size for sparse output specified"); ret = -1; goto fail_getopt; } min_sparse = sval / BDRV_SECTOR_SIZE; break; } case 'p': progress = 1; break; case 't': cache = optarg; break; case 'q': quiet = true; break; case 'n': skip_create = 1; break; } } /* Initialize before goto out */ if (quiet) { progress = 0; } qemu_progress_init(progress, 1.0); bs_n = argc - optind - 1; out_filename = bs_n >= 1 ? argv[argc - 1] : NULL; if (options && has_help_option(options)) { ret = print_block_option_help(out_filename, out_fmt); goto out; } if (bs_n < 1) { error_exit("Must specify image file name"); } if (bs_n > 1 && out_baseimg) { error_report("-B makes no sense when concatenating multiple input " "images"); ret = -1; goto out; } qemu_progress_print(0, 100); bs = g_new0(BlockDriverState *, bs_n); bs_sectors = g_new(int64_t, bs_n); total_sectors = 0; for (bs_i = 0; bs_i < bs_n; bs_i++) { char *id = bs_n > 1 ? g_strdup_printf("source %d", bs_i) : g_strdup("source"); bs[bs_i] = bdrv_new_open(id, argv[optind + bs_i], fmt, BDRV_O_FLAGS, true, quiet); g_free(id); if (!bs[bs_i]) { error_report("Could not open '%s'", argv[optind + bs_i]); ret = -1; goto out; } bs_sectors[bs_i] = bdrv_nb_sectors(bs[bs_i]); if (bs_sectors[bs_i] < 0) { error_report("Could not get size of %s: %s", argv[optind + bs_i], strerror(-bs_sectors[bs_i])); ret = -1; goto out; } total_sectors += bs_sectors[bs_i]; } if (sn_opts) { ret = bdrv_snapshot_load_tmp(bs[0], qemu_opt_get(sn_opts, SNAPSHOT_OPT_ID), qemu_opt_get(sn_opts, SNAPSHOT_OPT_NAME), &local_err); } else if (snapshot_name != NULL) { if (bs_n > 1) { error_report("No support for concatenating multiple snapshot"); ret = -1; goto out; } bdrv_snapshot_load_tmp_by_id_or_name(bs[0], snapshot_name, &local_err); } if (local_err) { error_report("Failed to load snapshot: %s", error_get_pretty(local_err)); error_free(local_err); ret = -1; goto out; } /* Find driver and parse its options */ drv = bdrv_find_format(out_fmt); if (!drv) { error_report("Unknown file format '%s'", out_fmt); ret = -1; goto out; } proto_drv = bdrv_find_protocol(out_filename, true); if (!proto_drv) { error_report("Unknown protocol '%s'", out_filename); ret = -1; goto out; } create_opts = qemu_opts_append(create_opts, drv->create_opts); create_opts = qemu_opts_append(create_opts, proto_drv->create_opts); opts = qemu_opts_create(create_opts, NULL, 0, &error_abort); if (options && qemu_opts_do_parse(opts, options, NULL)) { error_report("Invalid options for file format '%s'", out_fmt); ret = -1; goto out; } qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_sectors * 512); ret = add_old_style_options(out_fmt, opts, out_baseimg, NULL); if (ret < 0) { goto out; } /* Get backing file name if -o backing_file was used */ out_baseimg_param = qemu_opt_get(opts, BLOCK_OPT_BACKING_FILE); if (out_baseimg_param) { out_baseimg = out_baseimg_param; } /* Check if compression is supported */ if (compress) { bool encryption = qemu_opt_get_bool(opts, BLOCK_OPT_ENCRYPT, false); const char *preallocation = qemu_opt_get(opts, BLOCK_OPT_PREALLOC); if (!drv->bdrv_write_compressed) { error_report("Compression not supported for this file format"); ret = -1; goto out; } if (encryption) { error_report("Compression and encryption not supported at " "the same time"); ret = -1; goto out; } if (preallocation && strcmp(preallocation, "off")) { error_report("Compression and preallocation not supported at " "the same time"); ret = -1; goto out; } } if (!skip_create) { /* Create the new image */ ret = bdrv_create(drv, out_filename, opts, &local_err); if (ret < 0) { error_report("%s: error while converting %s: %s", out_filename, out_fmt, error_get_pretty(local_err)); error_free(local_err); goto out; } } flags = min_sparse ? (BDRV_O_RDWR | BDRV_O_UNMAP) : BDRV_O_RDWR; ret = bdrv_parse_cache_flags(cache, &flags); if (ret < 0) { error_report("Invalid cache option: %s", cache); goto out; } out_bs = bdrv_new_open("target", out_filename, out_fmt, flags, true, quiet); if (!out_bs) { ret = -1; goto out; } bs_i = 0; bs_offset = 0; /* increase bufsectors from the default 4096 (2M) if opt_transfer_length * or discard_alignment of the out_bs is greater. Limit to 32768 (16MB) * as maximum. */ bufsectors = MIN(32768, MAX(bufsectors, MAX(out_bs->bl.opt_transfer_length, out_bs->bl.discard_alignment)) ); buf = qemu_blockalign(out_bs, bufsectors * BDRV_SECTOR_SIZE); if (skip_create) { int64_t output_sectors = bdrv_nb_sectors(out_bs); if (output_sectors < 0) { error_report("unable to get output image length: %s\n", strerror(-output_sectors)); ret = -1; goto out; } else if (output_sectors < total_sectors) { error_report("output file is smaller than input file"); ret = -1; goto out; } } cluster_sectors = 0; ret = bdrv_get_info(out_bs, &bdi); if (ret < 0) { if (compress) { error_report("could not get block driver info"); goto out; } } else { compress = compress || bdi.needs_compressed_writes; cluster_sectors = bdi.cluster_size / BDRV_SECTOR_SIZE; } if (compress) { if (cluster_sectors <= 0 || cluster_sectors > bufsectors) { error_report("invalid cluster size"); ret = -1; goto out; } sector_num = 0; nb_sectors = total_sectors; for(;;) { int64_t bs_num; int remainder; uint8_t *buf2; nb_sectors = total_sectors - sector_num; if (nb_sectors <= 0) break; if (nb_sectors >= cluster_sectors) n = cluster_sectors; else n = nb_sectors; bs_num = sector_num - bs_offset; assert (bs_num >= 0); remainder = n; buf2 = buf; while (remainder > 0) { int nlow; while (bs_num == bs_sectors[bs_i]) { bs_offset += bs_sectors[bs_i]; bs_i++; assert (bs_i < bs_n); bs_num = 0; /* printf("changing part: sector_num=%" PRId64 ", " "bs_i=%d, bs_offset=%" PRId64 ", bs_sectors=%" PRId64 "\n", sector_num, bs_i, bs_offset, bs_sectors[bs_i]); */ } assert (bs_num < bs_sectors[bs_i]); nlow = remainder > bs_sectors[bs_i] - bs_num ? bs_sectors[bs_i] - bs_num : remainder; ret = bdrv_read(bs[bs_i], bs_num, buf2, nlow); if (ret < 0) { error_report("error while reading sector %" PRId64 ": %s", bs_num, strerror(-ret)); goto out; } buf2 += nlow * 512; bs_num += nlow; remainder -= nlow; } assert (remainder == 0); if (!buffer_is_zero(buf, n * BDRV_SECTOR_SIZE)) { ret = bdrv_write_compressed(out_bs, sector_num, buf, n); if (ret != 0) { error_report("error while compressing sector %" PRId64 ": %s", sector_num, strerror(-ret)); goto out; } } sector_num += n; qemu_progress_print(100.0 * sector_num / total_sectors, 0); } /* signal EOF to align */ bdrv_write_compressed(out_bs, 0, NULL, 0); } else { int64_t sectors_to_read, sectors_read, sector_num_next_status; bool count_allocated_sectors; int has_zero_init = min_sparse ? bdrv_has_zero_init(out_bs) : 0; if (!has_zero_init && bdrv_can_write_zeroes_with_unmap(out_bs)) { ret = bdrv_make_zero(out_bs, BDRV_REQ_MAY_UNMAP); if (ret < 0) { goto out; } has_zero_init = 1; } sectors_to_read = total_sectors; count_allocated_sectors = progress && (out_baseimg || has_zero_init); restart: sector_num = 0; // total number of sectors converted so far sectors_read = 0; sector_num_next_status = 0; for(;;) { nb_sectors = total_sectors - sector_num; if (nb_sectors <= 0) { if (count_allocated_sectors) { sectors_to_read = sectors_read; count_allocated_sectors = false; goto restart; } ret = 0; break; } while (sector_num - bs_offset >= bs_sectors[bs_i]) { bs_offset += bs_sectors[bs_i]; bs_i ++; assert (bs_i < bs_n); /* printf("changing part: sector_num=%" PRId64 ", bs_i=%d, " "bs_offset=%" PRId64 ", bs_sectors=%" PRId64 "\n", sector_num, bs_i, bs_offset, bs_sectors[bs_i]); */ } if ((out_baseimg || has_zero_init) && sector_num >= sector_num_next_status) { n = nb_sectors > INT_MAX ? INT_MAX : nb_sectors; ret = bdrv_get_block_status(bs[bs_i], sector_num - bs_offset, n, &n1); if (ret < 0) { error_report("error while reading block status of sector %" PRId64 ": %s", sector_num - bs_offset, strerror(-ret)); goto out; } /* If the output image is zero initialized, we are not working * on a shared base and the input is zero we can skip the next * n1 sectors */ if (has_zero_init && !out_baseimg && (ret & BDRV_BLOCK_ZERO)) { sector_num += n1; continue; } /* If the output image is being created as a copy on write * image, assume that sectors which are unallocated in the * input image are present in both the output's and input's * base images (no need to copy them). */ if (out_baseimg) { if (!(ret & BDRV_BLOCK_DATA)) { sector_num += n1; continue; } /* The next 'n1' sectors are allocated in the input image. * Copy only those as they may be followed by unallocated * sectors. */ nb_sectors = n1; } /* avoid redundant callouts to get_block_status */ sector_num_next_status = sector_num + n1; } n = MIN(nb_sectors, bufsectors); /* round down request length to an aligned sector, but * do not bother doing this on short requests. They happen * when we found an all-zero area, and the next sector to * write will not be sector_num + n. */ if (cluster_sectors > 0 && n >= cluster_sectors) { int64_t next_aligned_sector = (sector_num + n); next_aligned_sector -= next_aligned_sector % cluster_sectors; if (sector_num + n > next_aligned_sector) { n = next_aligned_sector - sector_num; } } n = MIN(n, bs_sectors[bs_i] - (sector_num - bs_offset)); sectors_read += n; if (count_allocated_sectors) { sector_num += n; continue; } n1 = n; ret = bdrv_read(bs[bs_i], sector_num - bs_offset, buf, n); if (ret < 0) { error_report("error while reading sector %" PRId64 ": %s", sector_num - bs_offset, strerror(-ret)); goto out; } /* NOTE: at the same time we convert, we do not write zero sectors to have a chance to compress the image. Ideally, we should add a specific call to have the info to go faster */ buf1 = buf; while (n > 0) { if (!has_zero_init || is_allocated_sectors_min(buf1, n, &n1, min_sparse)) { ret = bdrv_write(out_bs, sector_num, buf1, n1); if (ret < 0) { error_report("error while writing sector %" PRId64 ": %s", sector_num, strerror(-ret)); goto out; } } sector_num += n1; n -= n1; buf1 += n1 * 512; } qemu_progress_print(100.0 * sectors_read / sectors_to_read, 0); } } out: if (!ret) { qemu_progress_print(100, 0); } qemu_progress_end(); qemu_opts_del(opts); qemu_opts_free(create_opts); qemu_vfree(buf); if (sn_opts) { qemu_opts_del(sn_opts); } if (out_bs) { bdrv_unref(out_bs); } if (bs) { for (bs_i = 0; bs_i < bs_n; bs_i++) { if (bs[bs_i]) { bdrv_unref(bs[bs_i]); } } g_free(bs); } g_free(bs_sectors); fail_getopt: g_free(options); if (ret) { return 1; } return 0; }
false
qemu
40055951a7afbfc037c6c7351d72a5c5d83ed99b
static int img_convert(int argc, char **argv) { int c, n, n1, bs_n, bs_i, compress, cluster_sectors, skip_create; int64_t ret = 0; int progress = 0, flags; const char *fmt, *out_fmt, *cache, *out_baseimg, *out_filename; BlockDriver *drv, *proto_drv; BlockDriverState **bs = NULL, *out_bs = NULL; int64_t total_sectors, nb_sectors, sector_num, bs_offset; int64_t *bs_sectors = NULL; uint8_t * buf = NULL; size_t bufsectors = IO_BUF_SIZE / BDRV_SECTOR_SIZE; const uint8_t *buf1; BlockDriverInfo bdi; QemuOpts *opts = NULL; QemuOptsList *create_opts = NULL; const char *out_baseimg_param; char *options = NULL; const char *snapshot_name = NULL; int min_sparse = 8; bool quiet = false; Error *local_err = NULL; QemuOpts *sn_opts = NULL; fmt = NULL; out_fmt = "raw"; cache = "unsafe"; out_baseimg = NULL; compress = 0; skip_create = 0; for(;;) { c = getopt(argc, argv, "f:O:B:s:hce6o:pS:t:qnl:"); if (c == -1) { break; } switch(c) { case '?': case 'h': help(); break; case 'f': fmt = optarg; break; case 'O': out_fmt = optarg; break; case 'B': out_baseimg = optarg; break; case 'c': compress = 1; break; case 'e': error_report("option -e is deprecated, please use \'-o " "encryption\' instead!"); ret = -1; goto fail_getopt; case '6': error_report("option -6 is deprecated, please use \'-o " "compat6\' instead!"); ret = -1; goto fail_getopt; case 'o': if (!is_valid_option_list(optarg)) { error_report("Invalid option list: %s", optarg); ret = -1; goto fail_getopt; } if (!options) { options = g_strdup(optarg); } else { char *old_options = options; options = g_strdup_printf("%s,%s", options, optarg); g_free(old_options); } break; case 's': snapshot_name = optarg; break; case 'l': if (strstart(optarg, SNAPSHOT_OPT_BASE, NULL)) { sn_opts = qemu_opts_parse(&internal_snapshot_opts, optarg, 0); if (!sn_opts) { error_report("Failed in parsing snapshot param '%s'", optarg); ret = -1; goto fail_getopt; } } else { snapshot_name = optarg; } break; case 'S': { int64_t sval; char *end; sval = strtosz_suffix(optarg, &end, STRTOSZ_DEFSUFFIX_B); if (sval < 0 || *end) { error_report("Invalid minimum zero buffer size for sparse output specified"); ret = -1; goto fail_getopt; } min_sparse = sval / BDRV_SECTOR_SIZE; break; } case 'p': progress = 1; break; case 't': cache = optarg; break; case 'q': quiet = true; break; case 'n': skip_create = 1; break; } } if (quiet) { progress = 0; } qemu_progress_init(progress, 1.0); bs_n = argc - optind - 1; out_filename = bs_n >= 1 ? argv[argc - 1] : NULL; if (options && has_help_option(options)) { ret = print_block_option_help(out_filename, out_fmt); goto out; } if (bs_n < 1) { error_exit("Must specify image file name"); } if (bs_n > 1 && out_baseimg) { error_report("-B makes no sense when concatenating multiple input " "images"); ret = -1; goto out; } qemu_progress_print(0, 100); bs = g_new0(BlockDriverState *, bs_n); bs_sectors = g_new(int64_t, bs_n); total_sectors = 0; for (bs_i = 0; bs_i < bs_n; bs_i++) { char *id = bs_n > 1 ? g_strdup_printf("source %d", bs_i) : g_strdup("source"); bs[bs_i] = bdrv_new_open(id, argv[optind + bs_i], fmt, BDRV_O_FLAGS, true, quiet); g_free(id); if (!bs[bs_i]) { error_report("Could not open '%s'", argv[optind + bs_i]); ret = -1; goto out; } bs_sectors[bs_i] = bdrv_nb_sectors(bs[bs_i]); if (bs_sectors[bs_i] < 0) { error_report("Could not get size of %s: %s", argv[optind + bs_i], strerror(-bs_sectors[bs_i])); ret = -1; goto out; } total_sectors += bs_sectors[bs_i]; } if (sn_opts) { ret = bdrv_snapshot_load_tmp(bs[0], qemu_opt_get(sn_opts, SNAPSHOT_OPT_ID), qemu_opt_get(sn_opts, SNAPSHOT_OPT_NAME), &local_err); } else if (snapshot_name != NULL) { if (bs_n > 1) { error_report("No support for concatenating multiple snapshot"); ret = -1; goto out; } bdrv_snapshot_load_tmp_by_id_or_name(bs[0], snapshot_name, &local_err); } if (local_err) { error_report("Failed to load snapshot: %s", error_get_pretty(local_err)); error_free(local_err); ret = -1; goto out; } drv = bdrv_find_format(out_fmt); if (!drv) { error_report("Unknown file format '%s'", out_fmt); ret = -1; goto out; } proto_drv = bdrv_find_protocol(out_filename, true); if (!proto_drv) { error_report("Unknown protocol '%s'", out_filename); ret = -1; goto out; } create_opts = qemu_opts_append(create_opts, drv->create_opts); create_opts = qemu_opts_append(create_opts, proto_drv->create_opts); opts = qemu_opts_create(create_opts, NULL, 0, &error_abort); if (options && qemu_opts_do_parse(opts, options, NULL)) { error_report("Invalid options for file format '%s'", out_fmt); ret = -1; goto out; } qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_sectors * 512); ret = add_old_style_options(out_fmt, opts, out_baseimg, NULL); if (ret < 0) { goto out; } out_baseimg_param = qemu_opt_get(opts, BLOCK_OPT_BACKING_FILE); if (out_baseimg_param) { out_baseimg = out_baseimg_param; } if (compress) { bool encryption = qemu_opt_get_bool(opts, BLOCK_OPT_ENCRYPT, false); const char *preallocation = qemu_opt_get(opts, BLOCK_OPT_PREALLOC); if (!drv->bdrv_write_compressed) { error_report("Compression not supported for this file format"); ret = -1; goto out; } if (encryption) { error_report("Compression and encryption not supported at " "the same time"); ret = -1; goto out; } if (preallocation && strcmp(preallocation, "off")) { error_report("Compression and preallocation not supported at " "the same time"); ret = -1; goto out; } } if (!skip_create) { ret = bdrv_create(drv, out_filename, opts, &local_err); if (ret < 0) { error_report("%s: error while converting %s: %s", out_filename, out_fmt, error_get_pretty(local_err)); error_free(local_err); goto out; } } flags = min_sparse ? (BDRV_O_RDWR | BDRV_O_UNMAP) : BDRV_O_RDWR; ret = bdrv_parse_cache_flags(cache, &flags); if (ret < 0) { error_report("Invalid cache option: %s", cache); goto out; } out_bs = bdrv_new_open("target", out_filename, out_fmt, flags, true, quiet); if (!out_bs) { ret = -1; goto out; } bs_i = 0; bs_offset = 0; bufsectors = MIN(32768, MAX(bufsectors, MAX(out_bs->bl.opt_transfer_length, out_bs->bl.discard_alignment)) ); buf = qemu_blockalign(out_bs, bufsectors * BDRV_SECTOR_SIZE); if (skip_create) { int64_t output_sectors = bdrv_nb_sectors(out_bs); if (output_sectors < 0) { error_report("unable to get output image length: %s\n", strerror(-output_sectors)); ret = -1; goto out; } else if (output_sectors < total_sectors) { error_report("output file is smaller than input file"); ret = -1; goto out; } } cluster_sectors = 0; ret = bdrv_get_info(out_bs, &bdi); if (ret < 0) { if (compress) { error_report("could not get block driver info"); goto out; } } else { compress = compress || bdi.needs_compressed_writes; cluster_sectors = bdi.cluster_size / BDRV_SECTOR_SIZE; } if (compress) { if (cluster_sectors <= 0 || cluster_sectors > bufsectors) { error_report("invalid cluster size"); ret = -1; goto out; } sector_num = 0; nb_sectors = total_sectors; for(;;) { int64_t bs_num; int remainder; uint8_t *buf2; nb_sectors = total_sectors - sector_num; if (nb_sectors <= 0) break; if (nb_sectors >= cluster_sectors) n = cluster_sectors; else n = nb_sectors; bs_num = sector_num - bs_offset; assert (bs_num >= 0); remainder = n; buf2 = buf; while (remainder > 0) { int nlow; while (bs_num == bs_sectors[bs_i]) { bs_offset += bs_sectors[bs_i]; bs_i++; assert (bs_i < bs_n); bs_num = 0; } assert (bs_num < bs_sectors[bs_i]); nlow = remainder > bs_sectors[bs_i] - bs_num ? bs_sectors[bs_i] - bs_num : remainder; ret = bdrv_read(bs[bs_i], bs_num, buf2, nlow); if (ret < 0) { error_report("error while reading sector %" PRId64 ": %s", bs_num, strerror(-ret)); goto out; } buf2 += nlow * 512; bs_num += nlow; remainder -= nlow; } assert (remainder == 0); if (!buffer_is_zero(buf, n * BDRV_SECTOR_SIZE)) { ret = bdrv_write_compressed(out_bs, sector_num, buf, n); if (ret != 0) { error_report("error while compressing sector %" PRId64 ": %s", sector_num, strerror(-ret)); goto out; } } sector_num += n; qemu_progress_print(100.0 * sector_num / total_sectors, 0); } bdrv_write_compressed(out_bs, 0, NULL, 0); } else { int64_t sectors_to_read, sectors_read, sector_num_next_status; bool count_allocated_sectors; int has_zero_init = min_sparse ? bdrv_has_zero_init(out_bs) : 0; if (!has_zero_init && bdrv_can_write_zeroes_with_unmap(out_bs)) { ret = bdrv_make_zero(out_bs, BDRV_REQ_MAY_UNMAP); if (ret < 0) { goto out; } has_zero_init = 1; } sectors_to_read = total_sectors; count_allocated_sectors = progress && (out_baseimg || has_zero_init); restart: sector_num = 0; sectors_read = 0; sector_num_next_status = 0; for(;;) { nb_sectors = total_sectors - sector_num; if (nb_sectors <= 0) { if (count_allocated_sectors) { sectors_to_read = sectors_read; count_allocated_sectors = false; goto restart; } ret = 0; break; } while (sector_num - bs_offset >= bs_sectors[bs_i]) { bs_offset += bs_sectors[bs_i]; bs_i ++; assert (bs_i < bs_n); } if ((out_baseimg || has_zero_init) && sector_num >= sector_num_next_status) { n = nb_sectors > INT_MAX ? INT_MAX : nb_sectors; ret = bdrv_get_block_status(bs[bs_i], sector_num - bs_offset, n, &n1); if (ret < 0) { error_report("error while reading block status of sector %" PRId64 ": %s", sector_num - bs_offset, strerror(-ret)); goto out; } if (has_zero_init && !out_baseimg && (ret & BDRV_BLOCK_ZERO)) { sector_num += n1; continue; } if (out_baseimg) { if (!(ret & BDRV_BLOCK_DATA)) { sector_num += n1; continue; } nb_sectors = n1; } sector_num_next_status = sector_num + n1; } n = MIN(nb_sectors, bufsectors); if (cluster_sectors > 0 && n >= cluster_sectors) { int64_t next_aligned_sector = (sector_num + n); next_aligned_sector -= next_aligned_sector % cluster_sectors; if (sector_num + n > next_aligned_sector) { n = next_aligned_sector - sector_num; } } n = MIN(n, bs_sectors[bs_i] - (sector_num - bs_offset)); sectors_read += n; if (count_allocated_sectors) { sector_num += n; continue; } n1 = n; ret = bdrv_read(bs[bs_i], sector_num - bs_offset, buf, n); if (ret < 0) { error_report("error while reading sector %" PRId64 ": %s", sector_num - bs_offset, strerror(-ret)); goto out; } buf1 = buf; while (n > 0) { if (!has_zero_init || is_allocated_sectors_min(buf1, n, &n1, min_sparse)) { ret = bdrv_write(out_bs, sector_num, buf1, n1); if (ret < 0) { error_report("error while writing sector %" PRId64 ": %s", sector_num, strerror(-ret)); goto out; } } sector_num += n1; n -= n1; buf1 += n1 * 512; } qemu_progress_print(100.0 * sectors_read / sectors_to_read, 0); } } out: if (!ret) { qemu_progress_print(100, 0); } qemu_progress_end(); qemu_opts_del(opts); qemu_opts_free(create_opts); qemu_vfree(buf); if (sn_opts) { qemu_opts_del(sn_opts); } if (out_bs) { bdrv_unref(out_bs); } if (bs) { for (bs_i = 0; bs_i < bs_n; bs_i++) { if (bs[bs_i]) { bdrv_unref(bs[bs_i]); } } g_free(bs); } g_free(bs_sectors); fail_getopt: g_free(options); if (ret) { return 1; } return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(int VAR_0, char **VAR_1) { int VAR_2, VAR_3, VAR_4, VAR_5, VAR_6, VAR_7, VAR_8, VAR_9; int64_t ret = 0; int VAR_10 = 0, VAR_11; const char *VAR_12, *VAR_13, *VAR_14, *VAR_15, *VAR_16; BlockDriver *drv, *proto_drv; BlockDriverState **bs = NULL, *out_bs = NULL; int64_t total_sectors, nb_sectors, sector_num, bs_offset; int64_t *bs_sectors = NULL; uint8_t * buf = NULL; size_t bufsectors = IO_BUF_SIZE / BDRV_SECTOR_SIZE; const uint8_t *VAR_17; BlockDriverInfo bdi; QemuOpts *opts = NULL; QemuOptsList *create_opts = NULL; const char *VAR_18; char *VAR_19 = NULL; const char *VAR_20 = NULL; int VAR_21 = 8; bool quiet = false; Error *local_err = NULL; QemuOpts *sn_opts = NULL; VAR_12 = NULL; VAR_13 = "raw"; VAR_14 = "unsafe"; VAR_15 = NULL; VAR_7 = 0; VAR_9 = 0; for(;;) { VAR_2 = getopt(VAR_0, VAR_1, "f:O:B:s:hce6o:pS:t:qnl:"); if (VAR_2 == -1) { break; } switch(VAR_2) { case '?': case 'h': help(); break; case 'f': VAR_12 = optarg; break; case 'O': VAR_13 = optarg; break; case 'B': VAR_15 = optarg; break; case 'VAR_2': VAR_7 = 1; break; case 'e': error_report("option -e is deprecated, please use \'-o " "encryption\' instead!"); ret = -1; goto fail_getopt; case '6': error_report("option -6 is deprecated, please use \'-o " "compat6\' instead!"); ret = -1; goto fail_getopt; case 'o': if (!is_valid_option_list(optarg)) { error_report("Invalid option list: %s", optarg); ret = -1; goto fail_getopt; } if (!VAR_19) { VAR_19 = g_strdup(optarg); } else { char *VAR_22 = VAR_19; VAR_19 = g_strdup_printf("%s,%s", VAR_19, optarg); g_free(VAR_22); } break; case 's': VAR_20 = optarg; break; case 'l': if (strstart(optarg, SNAPSHOT_OPT_BASE, NULL)) { sn_opts = qemu_opts_parse(&internal_snapshot_opts, optarg, 0); if (!sn_opts) { error_report("Failed in parsing snapshot param '%s'", optarg); ret = -1; goto fail_getopt; } } else { VAR_20 = optarg; } break; case 'S': { int64_t sval; char *VAR_23; sval = strtosz_suffix(optarg, &VAR_23, STRTOSZ_DEFSUFFIX_B); if (sval < 0 || *VAR_23) { error_report("Invalid minimum zero buffer size for sparse output specified"); ret = -1; goto fail_getopt; } VAR_21 = sval / BDRV_SECTOR_SIZE; break; } case 'p': VAR_10 = 1; break; case 't': VAR_14 = optarg; break; case 'q': quiet = true; break; case 'VAR_3': VAR_9 = 1; break; } } if (quiet) { VAR_10 = 0; } qemu_progress_init(VAR_10, 1.0); VAR_5 = VAR_0 - optind - 1; VAR_16 = VAR_5 >= 1 ? VAR_1[VAR_0 - 1] : NULL; if (VAR_19 && has_help_option(VAR_19)) { ret = print_block_option_help(VAR_16, VAR_13); goto out; } if (VAR_5 < 1) { error_exit("Must specify image file name"); } if (VAR_5 > 1 && VAR_15) { error_report("-B makes no sense when concatenating multiple input " "images"); ret = -1; goto out; } qemu_progress_print(0, 100); bs = g_new0(BlockDriverState *, VAR_5); bs_sectors = g_new(int64_t, VAR_5); total_sectors = 0; for (VAR_6 = 0; VAR_6 < VAR_5; VAR_6++) { char *VAR_24 = VAR_5 > 1 ? g_strdup_printf("source %d", VAR_6) : g_strdup("source"); bs[VAR_6] = bdrv_new_open(VAR_24, VAR_1[optind + VAR_6], VAR_12, BDRV_O_FLAGS, true, quiet); g_free(VAR_24); if (!bs[VAR_6]) { error_report("Could not open '%s'", VAR_1[optind + VAR_6]); ret = -1; goto out; } bs_sectors[VAR_6] = bdrv_nb_sectors(bs[VAR_6]); if (bs_sectors[VAR_6] < 0) { error_report("Could not get size of %s: %s", VAR_1[optind + VAR_6], strerror(-bs_sectors[VAR_6])); ret = -1; goto out; } total_sectors += bs_sectors[VAR_6]; } if (sn_opts) { ret = bdrv_snapshot_load_tmp(bs[0], qemu_opt_get(sn_opts, SNAPSHOT_OPT_ID), qemu_opt_get(sn_opts, SNAPSHOT_OPT_NAME), &local_err); } else if (VAR_20 != NULL) { if (VAR_5 > 1) { error_report("No support for concatenating multiple snapshot"); ret = -1; goto out; } bdrv_snapshot_load_tmp_by_id_or_name(bs[0], VAR_20, &local_err); } if (local_err) { error_report("Failed to load snapshot: %s", error_get_pretty(local_err)); error_free(local_err); ret = -1; goto out; } drv = bdrv_find_format(VAR_13); if (!drv) { error_report("Unknown file format '%s'", VAR_13); ret = -1; goto out; } proto_drv = bdrv_find_protocol(VAR_16, true); if (!proto_drv) { error_report("Unknown protocol '%s'", VAR_16); ret = -1; goto out; } create_opts = qemu_opts_append(create_opts, drv->create_opts); create_opts = qemu_opts_append(create_opts, proto_drv->create_opts); opts = qemu_opts_create(create_opts, NULL, 0, &error_abort); if (VAR_19 && qemu_opts_do_parse(opts, VAR_19, NULL)) { error_report("Invalid VAR_19 for file format '%s'", VAR_13); ret = -1; goto out; } qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_sectors * 512); ret = add_old_style_options(VAR_13, opts, VAR_15, NULL); if (ret < 0) { goto out; } VAR_18 = qemu_opt_get(opts, BLOCK_OPT_BACKING_FILE); if (VAR_18) { VAR_15 = VAR_18; } if (VAR_7) { bool encryption = qemu_opt_get_bool(opts, BLOCK_OPT_ENCRYPT, false); const char *VAR_25 = qemu_opt_get(opts, BLOCK_OPT_PREALLOC); if (!drv->bdrv_write_compressed) { error_report("Compression not supported for this file format"); ret = -1; goto out; } if (encryption) { error_report("Compression and encryption not supported at " "the same time"); ret = -1; goto out; } if (VAR_25 && strcmp(VAR_25, "off")) { error_report("Compression and VAR_25 not supported at " "the same time"); ret = -1; goto out; } } if (!VAR_9) { ret = bdrv_create(drv, VAR_16, opts, &local_err); if (ret < 0) { error_report("%s: error while converting %s: %s", VAR_16, VAR_13, error_get_pretty(local_err)); error_free(local_err); goto out; } } VAR_11 = VAR_21 ? (BDRV_O_RDWR | BDRV_O_UNMAP) : BDRV_O_RDWR; ret = bdrv_parse_cache_flags(VAR_14, &VAR_11); if (ret < 0) { error_report("Invalid VAR_14 option: %s", VAR_14); goto out; } out_bs = bdrv_new_open("target", VAR_16, VAR_13, VAR_11, true, quiet); if (!out_bs) { ret = -1; goto out; } VAR_6 = 0; bs_offset = 0; bufsectors = MIN(32768, MAX(bufsectors, MAX(out_bs->bl.opt_transfer_length, out_bs->bl.discard_alignment)) ); buf = qemu_blockalign(out_bs, bufsectors * BDRV_SECTOR_SIZE); if (VAR_9) { int64_t output_sectors = bdrv_nb_sectors(out_bs); if (output_sectors < 0) { error_report("unable to get output image length: %s\VAR_3", strerror(-output_sectors)); ret = -1; goto out; } else if (output_sectors < total_sectors) { error_report("output file is smaller than input file"); ret = -1; goto out; } } VAR_8 = 0; ret = bdrv_get_info(out_bs, &bdi); if (ret < 0) { if (VAR_7) { error_report("could not get block driver info"); goto out; } } else { VAR_7 = VAR_7 || bdi.needs_compressed_writes; VAR_8 = bdi.cluster_size / BDRV_SECTOR_SIZE; } if (VAR_7) { if (VAR_8 <= 0 || VAR_8 > bufsectors) { error_report("invalid cluster size"); ret = -1; goto out; } sector_num = 0; nb_sectors = total_sectors; for(;;) { int64_t bs_num; int VAR_26; uint8_t *buf2; nb_sectors = total_sectors - sector_num; if (nb_sectors <= 0) break; if (nb_sectors >= VAR_8) VAR_3 = VAR_8; else VAR_3 = nb_sectors; bs_num = sector_num - bs_offset; assert (bs_num >= 0); VAR_26 = VAR_3; buf2 = buf; while (VAR_26 > 0) { int VAR_27; while (bs_num == bs_sectors[VAR_6]) { bs_offset += bs_sectors[VAR_6]; VAR_6++; assert (VAR_6 < VAR_5); bs_num = 0; } assert (bs_num < bs_sectors[VAR_6]); VAR_27 = VAR_26 > bs_sectors[VAR_6] - bs_num ? bs_sectors[VAR_6] - bs_num : VAR_26; ret = bdrv_read(bs[VAR_6], bs_num, buf2, VAR_27); if (ret < 0) { error_report("error while reading sector %" PRId64 ": %s", bs_num, strerror(-ret)); goto out; } buf2 += VAR_27 * 512; bs_num += VAR_27; VAR_26 -= VAR_27; } assert (VAR_26 == 0); if (!buffer_is_zero(buf, VAR_3 * BDRV_SECTOR_SIZE)) { ret = bdrv_write_compressed(out_bs, sector_num, buf, VAR_3); if (ret != 0) { error_report("error while compressing sector %" PRId64 ": %s", sector_num, strerror(-ret)); goto out; } } sector_num += VAR_3; qemu_progress_print(100.0 * sector_num / total_sectors, 0); } bdrv_write_compressed(out_bs, 0, NULL, 0); } else { int64_t sectors_to_read, sectors_read, sector_num_next_status; bool count_allocated_sectors; int VAR_28 = VAR_21 ? bdrv_has_zero_init(out_bs) : 0; if (!VAR_28 && bdrv_can_write_zeroes_with_unmap(out_bs)) { ret = bdrv_make_zero(out_bs, BDRV_REQ_MAY_UNMAP); if (ret < 0) { goto out; } VAR_28 = 1; } sectors_to_read = total_sectors; count_allocated_sectors = VAR_10 && (VAR_15 || VAR_28); restart: sector_num = 0; sectors_read = 0; sector_num_next_status = 0; for(;;) { nb_sectors = total_sectors - sector_num; if (nb_sectors <= 0) { if (count_allocated_sectors) { sectors_to_read = sectors_read; count_allocated_sectors = false; goto restart; } ret = 0; break; } while (sector_num - bs_offset >= bs_sectors[VAR_6]) { bs_offset += bs_sectors[VAR_6]; VAR_6 ++; assert (VAR_6 < VAR_5); } if ((VAR_15 || VAR_28) && sector_num >= sector_num_next_status) { VAR_3 = nb_sectors > INT_MAX ? INT_MAX : nb_sectors; ret = bdrv_get_block_status(bs[VAR_6], sector_num - bs_offset, VAR_3, &VAR_4); if (ret < 0) { error_report("error while reading block status of sector %" PRId64 ": %s", sector_num - bs_offset, strerror(-ret)); goto out; } if (VAR_28 && !VAR_15 && (ret & BDRV_BLOCK_ZERO)) { sector_num += VAR_4; continue; } if (VAR_15) { if (!(ret & BDRV_BLOCK_DATA)) { sector_num += VAR_4; continue; } nb_sectors = VAR_4; } sector_num_next_status = sector_num + VAR_4; } VAR_3 = MIN(nb_sectors, bufsectors); if (VAR_8 > 0 && VAR_3 >= VAR_8) { int64_t next_aligned_sector = (sector_num + VAR_3); next_aligned_sector -= next_aligned_sector % VAR_8; if (sector_num + VAR_3 > next_aligned_sector) { VAR_3 = next_aligned_sector - sector_num; } } VAR_3 = MIN(VAR_3, bs_sectors[VAR_6] - (sector_num - bs_offset)); sectors_read += VAR_3; if (count_allocated_sectors) { sector_num += VAR_3; continue; } VAR_4 = VAR_3; ret = bdrv_read(bs[VAR_6], sector_num - bs_offset, buf, VAR_3); if (ret < 0) { error_report("error while reading sector %" PRId64 ": %s", sector_num - bs_offset, strerror(-ret)); goto out; } VAR_17 = buf; while (VAR_3 > 0) { if (!VAR_28 || is_allocated_sectors_min(VAR_17, VAR_3, &VAR_4, VAR_21)) { ret = bdrv_write(out_bs, sector_num, VAR_17, VAR_4); if (ret < 0) { error_report("error while writing sector %" PRId64 ": %s", sector_num, strerror(-ret)); goto out; } } sector_num += VAR_4; VAR_3 -= VAR_4; VAR_17 += VAR_4 * 512; } qemu_progress_print(100.0 * sectors_read / sectors_to_read, 0); } } out: if (!ret) { qemu_progress_print(100, 0); } qemu_progress_end(); qemu_opts_del(opts); qemu_opts_free(create_opts); qemu_vfree(buf); if (sn_opts) { qemu_opts_del(sn_opts); } if (out_bs) { bdrv_unref(out_bs); } if (bs) { for (VAR_6 = 0; VAR_6 < VAR_5; VAR_6++) { if (bs[VAR_6]) { bdrv_unref(bs[VAR_6]); } } g_free(bs); } g_free(bs_sectors); fail_getopt: g_free(VAR_19); if (ret) { return 1; } return 0; }
[ "static int FUNC_0(int VAR_0, char **VAR_1)\n{", "int VAR_2, VAR_3, VAR_4, VAR_5, VAR_6, VAR_7, VAR_8, VAR_9;", "int64_t ret = 0;", "int VAR_10 = 0, VAR_11;", "const char *VAR_12, *VAR_13, *VAR_14, *VAR_15, *VAR_16;", "BlockDriver *drv, *proto_drv;", "BlockDriverState **bs = NULL, *out_bs = NULL;", "int64_t total_sectors, nb_sectors, sector_num, bs_offset;", "int64_t *bs_sectors = NULL;", "uint8_t * buf = NULL;", "size_t bufsectors = IO_BUF_SIZE / BDRV_SECTOR_SIZE;", "const uint8_t *VAR_17;", "BlockDriverInfo bdi;", "QemuOpts *opts = NULL;", "QemuOptsList *create_opts = NULL;", "const char *VAR_18;", "char *VAR_19 = NULL;", "const char *VAR_20 = NULL;", "int VAR_21 = 8;", "bool quiet = false;", "Error *local_err = NULL;", "QemuOpts *sn_opts = NULL;", "VAR_12 = NULL;", "VAR_13 = \"raw\";", "VAR_14 = \"unsafe\";", "VAR_15 = NULL;", "VAR_7 = 0;", "VAR_9 = 0;", "for(;;) {", "VAR_2 = getopt(VAR_0, VAR_1, \"f:O:B:s:hce6o:pS:t:qnl:\");", "if (VAR_2 == -1) {", "break;", "}", "switch(VAR_2) {", "case '?':\ncase 'h':\nhelp();", "break;", "case 'f':\nVAR_12 = optarg;", "break;", "case 'O':\nVAR_13 = optarg;", "break;", "case 'B':\nVAR_15 = optarg;", "break;", "case 'VAR_2':\nVAR_7 = 1;", "break;", "case 'e':\nerror_report(\"option -e is deprecated, please use \\'-o \"\n\"encryption\\' instead!\");", "ret = -1;", "goto fail_getopt;", "case '6':\nerror_report(\"option -6 is deprecated, please use \\'-o \"\n\"compat6\\' instead!\");", "ret = -1;", "goto fail_getopt;", "case 'o':\nif (!is_valid_option_list(optarg)) {", "error_report(\"Invalid option list: %s\", optarg);", "ret = -1;", "goto fail_getopt;", "}", "if (!VAR_19) {", "VAR_19 = g_strdup(optarg);", "} else {", "char *VAR_22 = VAR_19;", "VAR_19 = g_strdup_printf(\"%s,%s\", VAR_19, optarg);", "g_free(VAR_22);", "}", "break;", "case 's':\nVAR_20 = optarg;", "break;", "case 'l':\nif (strstart(optarg, SNAPSHOT_OPT_BASE, NULL)) {", "sn_opts = qemu_opts_parse(&internal_snapshot_opts, optarg, 0);", "if (!sn_opts) {", "error_report(\"Failed in parsing snapshot param '%s'\",\noptarg);", "ret = -1;", "goto fail_getopt;", "}", "} else {", "VAR_20 = optarg;", "}", "break;", "case 'S':\n{", "int64_t sval;", "char *VAR_23;", "sval = strtosz_suffix(optarg, &VAR_23, STRTOSZ_DEFSUFFIX_B);", "if (sval < 0 || *VAR_23) {", "error_report(\"Invalid minimum zero buffer size for sparse output specified\");", "ret = -1;", "goto fail_getopt;", "}", "VAR_21 = sval / BDRV_SECTOR_SIZE;", "break;", "}", "case 'p':\nVAR_10 = 1;", "break;", "case 't':\nVAR_14 = optarg;", "break;", "case 'q':\nquiet = true;", "break;", "case 'VAR_3':\nVAR_9 = 1;", "break;", "}", "}", "if (quiet) {", "VAR_10 = 0;", "}", "qemu_progress_init(VAR_10, 1.0);", "VAR_5 = VAR_0 - optind - 1;", "VAR_16 = VAR_5 >= 1 ? VAR_1[VAR_0 - 1] : NULL;", "if (VAR_19 && has_help_option(VAR_19)) {", "ret = print_block_option_help(VAR_16, VAR_13);", "goto out;", "}", "if (VAR_5 < 1) {", "error_exit(\"Must specify image file name\");", "}", "if (VAR_5 > 1 && VAR_15) {", "error_report(\"-B makes no sense when concatenating multiple input \"\n\"images\");", "ret = -1;", "goto out;", "}", "qemu_progress_print(0, 100);", "bs = g_new0(BlockDriverState *, VAR_5);", "bs_sectors = g_new(int64_t, VAR_5);", "total_sectors = 0;", "for (VAR_6 = 0; VAR_6 < VAR_5; VAR_6++) {", "char *VAR_24 = VAR_5 > 1 ? g_strdup_printf(\"source %d\", VAR_6)\n: g_strdup(\"source\");", "bs[VAR_6] = bdrv_new_open(VAR_24, VAR_1[optind + VAR_6], VAR_12, BDRV_O_FLAGS,\ntrue, quiet);", "g_free(VAR_24);", "if (!bs[VAR_6]) {", "error_report(\"Could not open '%s'\", VAR_1[optind + VAR_6]);", "ret = -1;", "goto out;", "}", "bs_sectors[VAR_6] = bdrv_nb_sectors(bs[VAR_6]);", "if (bs_sectors[VAR_6] < 0) {", "error_report(\"Could not get size of %s: %s\",\nVAR_1[optind + VAR_6], strerror(-bs_sectors[VAR_6]));", "ret = -1;", "goto out;", "}", "total_sectors += bs_sectors[VAR_6];", "}", "if (sn_opts) {", "ret = bdrv_snapshot_load_tmp(bs[0],\nqemu_opt_get(sn_opts, SNAPSHOT_OPT_ID),\nqemu_opt_get(sn_opts, SNAPSHOT_OPT_NAME),\n&local_err);", "} else if (VAR_20 != NULL) {", "if (VAR_5 > 1) {", "error_report(\"No support for concatenating multiple snapshot\");", "ret = -1;", "goto out;", "}", "bdrv_snapshot_load_tmp_by_id_or_name(bs[0], VAR_20, &local_err);", "}", "if (local_err) {", "error_report(\"Failed to load snapshot: %s\",\nerror_get_pretty(local_err));", "error_free(local_err);", "ret = -1;", "goto out;", "}", "drv = bdrv_find_format(VAR_13);", "if (!drv) {", "error_report(\"Unknown file format '%s'\", VAR_13);", "ret = -1;", "goto out;", "}", "proto_drv = bdrv_find_protocol(VAR_16, true);", "if (!proto_drv) {", "error_report(\"Unknown protocol '%s'\", VAR_16);", "ret = -1;", "goto out;", "}", "create_opts = qemu_opts_append(create_opts, drv->create_opts);", "create_opts = qemu_opts_append(create_opts, proto_drv->create_opts);", "opts = qemu_opts_create(create_opts, NULL, 0, &error_abort);", "if (VAR_19 && qemu_opts_do_parse(opts, VAR_19, NULL)) {", "error_report(\"Invalid VAR_19 for file format '%s'\", VAR_13);", "ret = -1;", "goto out;", "}", "qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_sectors * 512);", "ret = add_old_style_options(VAR_13, opts, VAR_15, NULL);", "if (ret < 0) {", "goto out;", "}", "VAR_18 = qemu_opt_get(opts, BLOCK_OPT_BACKING_FILE);", "if (VAR_18) {", "VAR_15 = VAR_18;", "}", "if (VAR_7) {", "bool encryption =\nqemu_opt_get_bool(opts, BLOCK_OPT_ENCRYPT, false);", "const char *VAR_25 =\nqemu_opt_get(opts, BLOCK_OPT_PREALLOC);", "if (!drv->bdrv_write_compressed) {", "error_report(\"Compression not supported for this file format\");", "ret = -1;", "goto out;", "}", "if (encryption) {", "error_report(\"Compression and encryption not supported at \"\n\"the same time\");", "ret = -1;", "goto out;", "}", "if (VAR_25\n&& strcmp(VAR_25, \"off\"))\n{", "error_report(\"Compression and VAR_25 not supported at \"\n\"the same time\");", "ret = -1;", "goto out;", "}", "}", "if (!VAR_9) {", "ret = bdrv_create(drv, VAR_16, opts, &local_err);", "if (ret < 0) {", "error_report(\"%s: error while converting %s: %s\",\nVAR_16, VAR_13, error_get_pretty(local_err));", "error_free(local_err);", "goto out;", "}", "}", "VAR_11 = VAR_21 ? (BDRV_O_RDWR | BDRV_O_UNMAP) : BDRV_O_RDWR;", "ret = bdrv_parse_cache_flags(VAR_14, &VAR_11);", "if (ret < 0) {", "error_report(\"Invalid VAR_14 option: %s\", VAR_14);", "goto out;", "}", "out_bs = bdrv_new_open(\"target\", VAR_16, VAR_13, VAR_11, true, quiet);", "if (!out_bs) {", "ret = -1;", "goto out;", "}", "VAR_6 = 0;", "bs_offset = 0;", "bufsectors = MIN(32768,\nMAX(bufsectors, MAX(out_bs->bl.opt_transfer_length,\nout_bs->bl.discard_alignment))\n);", "buf = qemu_blockalign(out_bs, bufsectors * BDRV_SECTOR_SIZE);", "if (VAR_9) {", "int64_t output_sectors = bdrv_nb_sectors(out_bs);", "if (output_sectors < 0) {", "error_report(\"unable to get output image length: %s\\VAR_3\",\nstrerror(-output_sectors));", "ret = -1;", "goto out;", "} else if (output_sectors < total_sectors) {", "error_report(\"output file is smaller than input file\");", "ret = -1;", "goto out;", "}", "}", "VAR_8 = 0;", "ret = bdrv_get_info(out_bs, &bdi);", "if (ret < 0) {", "if (VAR_7) {", "error_report(\"could not get block driver info\");", "goto out;", "}", "} else {", "VAR_7 = VAR_7 || bdi.needs_compressed_writes;", "VAR_8 = bdi.cluster_size / BDRV_SECTOR_SIZE;", "}", "if (VAR_7) {", "if (VAR_8 <= 0 || VAR_8 > bufsectors) {", "error_report(\"invalid cluster size\");", "ret = -1;", "goto out;", "}", "sector_num = 0;", "nb_sectors = total_sectors;", "for(;;) {", "int64_t bs_num;", "int VAR_26;", "uint8_t *buf2;", "nb_sectors = total_sectors - sector_num;", "if (nb_sectors <= 0)\nbreak;", "if (nb_sectors >= VAR_8)\nVAR_3 = VAR_8;", "else\nVAR_3 = nb_sectors;", "bs_num = sector_num - bs_offset;", "assert (bs_num >= 0);", "VAR_26 = VAR_3;", "buf2 = buf;", "while (VAR_26 > 0) {", "int VAR_27;", "while (bs_num == bs_sectors[VAR_6]) {", "bs_offset += bs_sectors[VAR_6];", "VAR_6++;", "assert (VAR_6 < VAR_5);", "bs_num = 0;", "}", "assert (bs_num < bs_sectors[VAR_6]);", "VAR_27 = VAR_26 > bs_sectors[VAR_6] - bs_num\n? bs_sectors[VAR_6] - bs_num : VAR_26;", "ret = bdrv_read(bs[VAR_6], bs_num, buf2, VAR_27);", "if (ret < 0) {", "error_report(\"error while reading sector %\" PRId64 \": %s\",\nbs_num, strerror(-ret));", "goto out;", "}", "buf2 += VAR_27 * 512;", "bs_num += VAR_27;", "VAR_26 -= VAR_27;", "}", "assert (VAR_26 == 0);", "if (!buffer_is_zero(buf, VAR_3 * BDRV_SECTOR_SIZE)) {", "ret = bdrv_write_compressed(out_bs, sector_num, buf, VAR_3);", "if (ret != 0) {", "error_report(\"error while compressing sector %\" PRId64\n\": %s\", sector_num, strerror(-ret));", "goto out;", "}", "}", "sector_num += VAR_3;", "qemu_progress_print(100.0 * sector_num / total_sectors, 0);", "}", "bdrv_write_compressed(out_bs, 0, NULL, 0);", "} else {", "int64_t sectors_to_read, sectors_read, sector_num_next_status;", "bool count_allocated_sectors;", "int VAR_28 = VAR_21 ? bdrv_has_zero_init(out_bs) : 0;", "if (!VAR_28 && bdrv_can_write_zeroes_with_unmap(out_bs)) {", "ret = bdrv_make_zero(out_bs, BDRV_REQ_MAY_UNMAP);", "if (ret < 0) {", "goto out;", "}", "VAR_28 = 1;", "}", "sectors_to_read = total_sectors;", "count_allocated_sectors = VAR_10 && (VAR_15 || VAR_28);", "restart:\nsector_num = 0;", "sectors_read = 0;", "sector_num_next_status = 0;", "for(;;) {", "nb_sectors = total_sectors - sector_num;", "if (nb_sectors <= 0) {", "if (count_allocated_sectors) {", "sectors_to_read = sectors_read;", "count_allocated_sectors = false;", "goto restart;", "}", "ret = 0;", "break;", "}", "while (sector_num - bs_offset >= bs_sectors[VAR_6]) {", "bs_offset += bs_sectors[VAR_6];", "VAR_6 ++;", "assert (VAR_6 < VAR_5);", "}", "if ((VAR_15 || VAR_28) &&\nsector_num >= sector_num_next_status) {", "VAR_3 = nb_sectors > INT_MAX ? INT_MAX : nb_sectors;", "ret = bdrv_get_block_status(bs[VAR_6], sector_num - bs_offset,\nVAR_3, &VAR_4);", "if (ret < 0) {", "error_report(\"error while reading block status of sector %\"\nPRId64 \": %s\", sector_num - bs_offset,\nstrerror(-ret));", "goto out;", "}", "if (VAR_28 && !VAR_15 && (ret & BDRV_BLOCK_ZERO)) {", "sector_num += VAR_4;", "continue;", "}", "if (VAR_15) {", "if (!(ret & BDRV_BLOCK_DATA)) {", "sector_num += VAR_4;", "continue;", "}", "nb_sectors = VAR_4;", "}", "sector_num_next_status = sector_num + VAR_4;", "}", "VAR_3 = MIN(nb_sectors, bufsectors);", "if (VAR_8 > 0 && VAR_3 >= VAR_8) {", "int64_t next_aligned_sector = (sector_num + VAR_3);", "next_aligned_sector -= next_aligned_sector % VAR_8;", "if (sector_num + VAR_3 > next_aligned_sector) {", "VAR_3 = next_aligned_sector - sector_num;", "}", "}", "VAR_3 = MIN(VAR_3, bs_sectors[VAR_6] - (sector_num - bs_offset));", "sectors_read += VAR_3;", "if (count_allocated_sectors) {", "sector_num += VAR_3;", "continue;", "}", "VAR_4 = VAR_3;", "ret = bdrv_read(bs[VAR_6], sector_num - bs_offset, buf, VAR_3);", "if (ret < 0) {", "error_report(\"error while reading sector %\" PRId64 \": %s\",\nsector_num - bs_offset, strerror(-ret));", "goto out;", "}", "VAR_17 = buf;", "while (VAR_3 > 0) {", "if (!VAR_28 ||\nis_allocated_sectors_min(VAR_17, VAR_3, &VAR_4, VAR_21)) {", "ret = bdrv_write(out_bs, sector_num, VAR_17, VAR_4);", "if (ret < 0) {", "error_report(\"error while writing sector %\" PRId64\n\": %s\", sector_num, strerror(-ret));", "goto out;", "}", "}", "sector_num += VAR_4;", "VAR_3 -= VAR_4;", "VAR_17 += VAR_4 * 512;", "}", "qemu_progress_print(100.0 * sectors_read / sectors_to_read, 0);", "}", "}", "out:\nif (!ret) {", "qemu_progress_print(100, 0);", "}", "qemu_progress_end();", "qemu_opts_del(opts);", "qemu_opts_free(create_opts);", "qemu_vfree(buf);", "if (sn_opts) {", "qemu_opts_del(sn_opts);", "}", "if (out_bs) {", "bdrv_unref(out_bs);", "}", "if (bs) {", "for (VAR_6 = 0; VAR_6 < VAR_5; VAR_6++) {", "if (bs[VAR_6]) {", "bdrv_unref(bs[VAR_6]);", "}", "}", "g_free(bs);", "}", "g_free(bs_sectors);", "fail_getopt:\ng_free(VAR_19);", "if (ret) {", "return 1;", "}", "return 0;", "}" ]
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16,900
static void musb_packet(MUSBState *s, MUSBEndPoint *ep, int epnum, int pid, int len, USBCallback cb, int dir) { USBDevice *dev; int ret; int idx = epnum && dir; int ttype; /* ep->type[0,1] contains: * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow) * in bits 5:4 the transfer type (BULK / INT) * in bits 3:0 the EP num */ ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0; ep->timeout[dir] = musb_timeout(ttype, ep->type[idx] >> 6, ep->interval[idx]); ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT; ep->delayed_cb[dir] = cb; /* A wild guess on the FADDR semantics... */ usb_packet_setup(&ep->packey[dir].p, pid, ep->faddr[idx], ep->type[idx] & 0xf); usb_packet_addbuf(&ep->packey[dir].p, ep->buf[idx], len); ep->packey[dir].ep = ep; ep->packey[dir].dir = dir; dev = usb_find_device(&s->port, ep->packey[dir].p.devaddr); ret = usb_handle_packet(dev, &ep->packey[dir].p); if (ret == USB_RET_ASYNC) { ep->status[dir] = len; return; } ep->status[dir] = ret; musb_schedule_cb(&s->port, &ep->packey[dir].p); }
false
qemu
079d0b7f1eedcc634c371fe05b617fdc55c8b762
static void musb_packet(MUSBState *s, MUSBEndPoint *ep, int epnum, int pid, int len, USBCallback cb, int dir) { USBDevice *dev; int ret; int idx = epnum && dir; int ttype; ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0; ep->timeout[dir] = musb_timeout(ttype, ep->type[idx] >> 6, ep->interval[idx]); ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT; ep->delayed_cb[dir] = cb; usb_packet_setup(&ep->packey[dir].p, pid, ep->faddr[idx], ep->type[idx] & 0xf); usb_packet_addbuf(&ep->packey[dir].p, ep->buf[idx], len); ep->packey[dir].ep = ep; ep->packey[dir].dir = dir; dev = usb_find_device(&s->port, ep->packey[dir].p.devaddr); ret = usb_handle_packet(dev, &ep->packey[dir].p); if (ret == USB_RET_ASYNC) { ep->status[dir] = len; return; } ep->status[dir] = ret; musb_schedule_cb(&s->port, &ep->packey[dir].p); }
{ "code": [], "line_no": [] }
static void FUNC_0(MUSBState *VAR_0, MUSBEndPoint *VAR_1, int VAR_2, int VAR_3, int VAR_4, USBCallback VAR_5, int VAR_6) { USBDevice *dev; int VAR_7; int VAR_8 = VAR_2 && VAR_6; int VAR_9; VAR_9 = VAR_2 ? (VAR_1->type[VAR_8] >> 4) & 3 : 0; VAR_1->timeout[VAR_6] = musb_timeout(VAR_9, VAR_1->type[VAR_8] >> 6, VAR_1->interval[VAR_8]); VAR_1->interrupt[VAR_6] = VAR_9 == USB_ENDPOINT_XFER_INT; VAR_1->delayed_cb[VAR_6] = VAR_5; usb_packet_setup(&VAR_1->packey[VAR_6].p, VAR_3, VAR_1->faddr[VAR_8], VAR_1->type[VAR_8] & 0xf); usb_packet_addbuf(&VAR_1->packey[VAR_6].p, VAR_1->buf[VAR_8], VAR_4); VAR_1->packey[VAR_6].VAR_1 = VAR_1; VAR_1->packey[VAR_6].VAR_6 = VAR_6; dev = usb_find_device(&VAR_0->port, VAR_1->packey[VAR_6].p.devaddr); VAR_7 = usb_handle_packet(dev, &VAR_1->packey[VAR_6].p); if (VAR_7 == USB_RET_ASYNC) { VAR_1->status[VAR_6] = VAR_4; return; } VAR_1->status[VAR_6] = VAR_7; musb_schedule_cb(&VAR_0->port, &VAR_1->packey[VAR_6].p); }
[ "static void FUNC_0(MUSBState *VAR_0, MUSBEndPoint *VAR_1,\nint VAR_2, int VAR_3, int VAR_4, USBCallback VAR_5, int VAR_6)\n{", "USBDevice *dev;", "int VAR_7;", "int VAR_8 = VAR_2 && VAR_6;", "int VAR_9;", "VAR_9 = VAR_2 ? (VAR_1->type[VAR_8] >> 4) & 3 : 0;", "VAR_1->timeout[VAR_6] = musb_timeout(VAR_9,\nVAR_1->type[VAR_8] >> 6, VAR_1->interval[VAR_8]);", "VAR_1->interrupt[VAR_6] = VAR_9 == USB_ENDPOINT_XFER_INT;", "VAR_1->delayed_cb[VAR_6] = VAR_5;", "usb_packet_setup(&VAR_1->packey[VAR_6].p, VAR_3, VAR_1->faddr[VAR_8],\nVAR_1->type[VAR_8] & 0xf);", "usb_packet_addbuf(&VAR_1->packey[VAR_6].p, VAR_1->buf[VAR_8], VAR_4);", "VAR_1->packey[VAR_6].VAR_1 = VAR_1;", "VAR_1->packey[VAR_6].VAR_6 = VAR_6;", "dev = usb_find_device(&VAR_0->port, VAR_1->packey[VAR_6].p.devaddr);", "VAR_7 = usb_handle_packet(dev, &VAR_1->packey[VAR_6].p);", "if (VAR_7 == USB_RET_ASYNC) {", "VAR_1->status[VAR_6] = VAR_4;", "return;", "}", "VAR_1->status[VAR_6] = VAR_7;", "musb_schedule_cb(&VAR_0->port, &VAR_1->packey[VAR_6].p);", "}" ]
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[ [ 1, 3, 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 27 ], [ 31, 33 ], [ 35 ], [ 37 ], [ 43, 45 ], [ 47 ], [ 49 ], [ 51 ], [ 55 ], [ 57 ], [ 61 ], [ 63 ], [ 65 ], [ 67 ], [ 71 ], [ 73 ], [ 75 ] ]
16,901
static bool net_tx_pkt_parse_headers(struct NetTxPkt *pkt) { struct iovec *l2_hdr, *l3_hdr; size_t bytes_read; size_t full_ip6hdr_len; uint16_t l3_proto; assert(pkt); l2_hdr = &pkt->vec[NET_TX_PKT_L2HDR_FRAG]; l3_hdr = &pkt->vec[NET_TX_PKT_L3HDR_FRAG]; bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, 0, l2_hdr->iov_base, ETH_MAX_L2_HDR_LEN); if (bytes_read < sizeof(struct eth_header)) { l2_hdr->iov_len = 0; return false; } l2_hdr->iov_len = sizeof(struct eth_header); switch (be16_to_cpu(PKT_GET_ETH_HDR(l2_hdr->iov_base)->h_proto)) { case ETH_P_VLAN: l2_hdr->iov_len += sizeof(struct vlan_header); break; case ETH_P_DVLAN: l2_hdr->iov_len += 2 * sizeof(struct vlan_header); break; } if (bytes_read < l2_hdr->iov_len) { l2_hdr->iov_len = 0; return false; } l3_proto = eth_get_l3_proto(l2_hdr->iov_base, l2_hdr->iov_len); switch (l3_proto) { case ETH_P_IP: l3_hdr->iov_base = g_malloc(ETH_MAX_IP4_HDR_LEN); bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len, l3_hdr->iov_base, sizeof(struct ip_header)); if (bytes_read < sizeof(struct ip_header)) { l3_hdr->iov_len = 0; return false; } l3_hdr->iov_len = IP_HDR_GET_LEN(l3_hdr->iov_base); pkt->l4proto = ((struct ip_header *) l3_hdr->iov_base)->ip_p; /* copy optional IPv4 header data */ bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len + sizeof(struct ip_header), l3_hdr->iov_base + sizeof(struct ip_header), l3_hdr->iov_len - sizeof(struct ip_header)); if (bytes_read < l3_hdr->iov_len - sizeof(struct ip_header)) { l3_hdr->iov_len = 0; return false; } break; case ETH_P_IPV6: if (!eth_parse_ipv6_hdr(pkt->raw, pkt->raw_frags, l2_hdr->iov_len, &pkt->l4proto, &full_ip6hdr_len)) { l3_hdr->iov_len = 0; return false; } l3_hdr->iov_base = g_malloc(full_ip6hdr_len); bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len, l3_hdr->iov_base, full_ip6hdr_len); if (bytes_read < full_ip6hdr_len) { l3_hdr->iov_len = 0; return false; } else { l3_hdr->iov_len = full_ip6hdr_len; } break; default: l3_hdr->iov_len = 0; break; } net_tx_pkt_calculate_hdr_len(pkt); pkt->packet_type = get_eth_packet_type(l2_hdr->iov_base); return true; }
false
qemu
eb700029c7836798046191d62d595363d92c84d4
static bool net_tx_pkt_parse_headers(struct NetTxPkt *pkt) { struct iovec *l2_hdr, *l3_hdr; size_t bytes_read; size_t full_ip6hdr_len; uint16_t l3_proto; assert(pkt); l2_hdr = &pkt->vec[NET_TX_PKT_L2HDR_FRAG]; l3_hdr = &pkt->vec[NET_TX_PKT_L3HDR_FRAG]; bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, 0, l2_hdr->iov_base, ETH_MAX_L2_HDR_LEN); if (bytes_read < sizeof(struct eth_header)) { l2_hdr->iov_len = 0; return false; } l2_hdr->iov_len = sizeof(struct eth_header); switch (be16_to_cpu(PKT_GET_ETH_HDR(l2_hdr->iov_base)->h_proto)) { case ETH_P_VLAN: l2_hdr->iov_len += sizeof(struct vlan_header); break; case ETH_P_DVLAN: l2_hdr->iov_len += 2 * sizeof(struct vlan_header); break; } if (bytes_read < l2_hdr->iov_len) { l2_hdr->iov_len = 0; return false; } l3_proto = eth_get_l3_proto(l2_hdr->iov_base, l2_hdr->iov_len); switch (l3_proto) { case ETH_P_IP: l3_hdr->iov_base = g_malloc(ETH_MAX_IP4_HDR_LEN); bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len, l3_hdr->iov_base, sizeof(struct ip_header)); if (bytes_read < sizeof(struct ip_header)) { l3_hdr->iov_len = 0; return false; } l3_hdr->iov_len = IP_HDR_GET_LEN(l3_hdr->iov_base); pkt->l4proto = ((struct ip_header *) l3_hdr->iov_base)->ip_p; bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len + sizeof(struct ip_header), l3_hdr->iov_base + sizeof(struct ip_header), l3_hdr->iov_len - sizeof(struct ip_header)); if (bytes_read < l3_hdr->iov_len - sizeof(struct ip_header)) { l3_hdr->iov_len = 0; return false; } break; case ETH_P_IPV6: if (!eth_parse_ipv6_hdr(pkt->raw, pkt->raw_frags, l2_hdr->iov_len, &pkt->l4proto, &full_ip6hdr_len)) { l3_hdr->iov_len = 0; return false; } l3_hdr->iov_base = g_malloc(full_ip6hdr_len); bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len, l3_hdr->iov_base, full_ip6hdr_len); if (bytes_read < full_ip6hdr_len) { l3_hdr->iov_len = 0; return false; } else { l3_hdr->iov_len = full_ip6hdr_len; } break; default: l3_hdr->iov_len = 0; break; } net_tx_pkt_calculate_hdr_len(pkt); pkt->packet_type = get_eth_packet_type(l2_hdr->iov_base); return true; }
{ "code": [], "line_no": [] }
static bool FUNC_0(struct NetTxPkt *pkt) { struct iovec *VAR_0, *VAR_1; size_t bytes_read; size_t full_ip6hdr_len; uint16_t l3_proto; assert(pkt); VAR_0 = &pkt->vec[NET_TX_PKT_L2HDR_FRAG]; VAR_1 = &pkt->vec[NET_TX_PKT_L3HDR_FRAG]; bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, 0, VAR_0->iov_base, ETH_MAX_L2_HDR_LEN); if (bytes_read < sizeof(struct eth_header)) { VAR_0->iov_len = 0; return false; } VAR_0->iov_len = sizeof(struct eth_header); switch (be16_to_cpu(PKT_GET_ETH_HDR(VAR_0->iov_base)->h_proto)) { case ETH_P_VLAN: VAR_0->iov_len += sizeof(struct vlan_header); break; case ETH_P_DVLAN: VAR_0->iov_len += 2 * sizeof(struct vlan_header); break; } if (bytes_read < VAR_0->iov_len) { VAR_0->iov_len = 0; return false; } l3_proto = eth_get_l3_proto(VAR_0->iov_base, VAR_0->iov_len); switch (l3_proto) { case ETH_P_IP: VAR_1->iov_base = g_malloc(ETH_MAX_IP4_HDR_LEN); bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, VAR_0->iov_len, VAR_1->iov_base, sizeof(struct ip_header)); if (bytes_read < sizeof(struct ip_header)) { VAR_1->iov_len = 0; return false; } VAR_1->iov_len = IP_HDR_GET_LEN(VAR_1->iov_base); pkt->l4proto = ((struct ip_header *) VAR_1->iov_base)->ip_p; bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, VAR_0->iov_len + sizeof(struct ip_header), VAR_1->iov_base + sizeof(struct ip_header), VAR_1->iov_len - sizeof(struct ip_header)); if (bytes_read < VAR_1->iov_len - sizeof(struct ip_header)) { VAR_1->iov_len = 0; return false; } break; case ETH_P_IPV6: if (!eth_parse_ipv6_hdr(pkt->raw, pkt->raw_frags, VAR_0->iov_len, &pkt->l4proto, &full_ip6hdr_len)) { VAR_1->iov_len = 0; return false; } VAR_1->iov_base = g_malloc(full_ip6hdr_len); bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, VAR_0->iov_len, VAR_1->iov_base, full_ip6hdr_len); if (bytes_read < full_ip6hdr_len) { VAR_1->iov_len = 0; return false; } else { VAR_1->iov_len = full_ip6hdr_len; } break; default: VAR_1->iov_len = 0; break; } net_tx_pkt_calculate_hdr_len(pkt); pkt->packet_type = get_eth_packet_type(VAR_0->iov_base); return true; }
[ "static bool FUNC_0(struct NetTxPkt *pkt)\n{", "struct iovec *VAR_0, *VAR_1;", "size_t bytes_read;", "size_t full_ip6hdr_len;", "uint16_t l3_proto;", "assert(pkt);", "VAR_0 = &pkt->vec[NET_TX_PKT_L2HDR_FRAG];", "VAR_1 = &pkt->vec[NET_TX_PKT_L3HDR_FRAG];", "bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, 0, VAR_0->iov_base,\nETH_MAX_L2_HDR_LEN);", "if (bytes_read < sizeof(struct eth_header)) {", "VAR_0->iov_len = 0;", "return false;", "}", "VAR_0->iov_len = sizeof(struct eth_header);", "switch (be16_to_cpu(PKT_GET_ETH_HDR(VAR_0->iov_base)->h_proto)) {", "case ETH_P_VLAN:\nVAR_0->iov_len += sizeof(struct vlan_header);", "break;", "case ETH_P_DVLAN:\nVAR_0->iov_len += 2 * sizeof(struct vlan_header);", "break;", "}", "if (bytes_read < VAR_0->iov_len) {", "VAR_0->iov_len = 0;", "return false;", "}", "l3_proto = eth_get_l3_proto(VAR_0->iov_base, VAR_0->iov_len);", "switch (l3_proto) {", "case ETH_P_IP:\nVAR_1->iov_base = g_malloc(ETH_MAX_IP4_HDR_LEN);", "bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, VAR_0->iov_len,\nVAR_1->iov_base, sizeof(struct ip_header));", "if (bytes_read < sizeof(struct ip_header)) {", "VAR_1->iov_len = 0;", "return false;", "}", "VAR_1->iov_len = IP_HDR_GET_LEN(VAR_1->iov_base);", "pkt->l4proto = ((struct ip_header *) VAR_1->iov_base)->ip_p;", "bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags,\nVAR_0->iov_len + sizeof(struct ip_header),\nVAR_1->iov_base + sizeof(struct ip_header),\nVAR_1->iov_len - sizeof(struct ip_header));", "if (bytes_read < VAR_1->iov_len - sizeof(struct ip_header)) {", "VAR_1->iov_len = 0;", "return false;", "}", "break;", "case ETH_P_IPV6:\nif (!eth_parse_ipv6_hdr(pkt->raw, pkt->raw_frags, VAR_0->iov_len,\n&pkt->l4proto, &full_ip6hdr_len)) {", "VAR_1->iov_len = 0;", "return false;", "}", "VAR_1->iov_base = g_malloc(full_ip6hdr_len);", "bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, VAR_0->iov_len,\nVAR_1->iov_base, full_ip6hdr_len);", "if (bytes_read < full_ip6hdr_len) {", "VAR_1->iov_len = 0;", "return false;", "} else {", "VAR_1->iov_len = full_ip6hdr_len;", "}", "break;", "default:\nVAR_1->iov_len = 0;", "break;", "}", "net_tx_pkt_calculate_hdr_len(pkt);", "pkt->packet_type = get_eth_packet_type(VAR_0->iov_base);", "return true;", "}" ]
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16,902
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) { PCIBonitoState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); uint32_t cfgaddr; uint32_t idsel; uint32_t devno; uint32_t funno; uint32_t regno; uint32_t pciaddr; /* support type0 pci config */ if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { return 0xffffffff; } cfgaddr = addr & 0xffff; cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; devno = ffs(idsel) - 1; funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; if (idsel == 0) { fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); exit(1); } pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); return pciaddr; }
false
qemu
a8170e5e97ad17ca169c64ba87ae2f53850dab4c
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) { PCIBonitoState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); uint32_t cfgaddr; uint32_t idsel; uint32_t devno; uint32_t funno; uint32_t regno; uint32_t pciaddr; if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { return 0xffffffff; } cfgaddr = addr & 0xffff; cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; devno = ffs(idsel) - 1; funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; if (idsel == 0) { fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); exit(1); } pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); return pciaddr; }
{ "code": [], "line_no": [] }
static uint32_t FUNC_0(void *opaque, target_phys_addr_t addr) { PCIBonitoState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); uint32_t cfgaddr; uint32_t idsel; uint32_t devno; uint32_t funno; uint32_t regno; uint32_t pciaddr; if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { return 0xffffffff; } cfgaddr = addr & 0xffff; cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; devno = ffs(idsel) - 1; funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; if (idsel == 0) { fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); exit(1); } pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); return pciaddr; }
[ "static uint32_t FUNC_0(void *opaque, target_phys_addr_t addr)\n{", "PCIBonitoState *s = opaque;", "PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);", "uint32_t cfgaddr;", "uint32_t idsel;", "uint32_t devno;", "uint32_t funno;", "uint32_t regno;", "uint32_t pciaddr;", "if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {", "return 0xffffffff;", "}", "cfgaddr = addr & 0xffff;", "cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;", "idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;", "devno = ffs(idsel) - 1;", "funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;", "regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;", "if (idsel == 0) {", "fprintf(stderr, \"error in bonito pci config address \" TARGET_FMT_plx\n\",pcimap_cfg=%x\\n\", addr, s->regs[BONITO_PCIMAP_CFG]);", "exit(1);", "}", "pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);", "DPRINTF(\"cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\\n\",\ncfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);", "return pciaddr;", "}" ]
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16,903
static void ide_init1(IDEBus *bus, int unit) { static int drive_serial = 1; IDEState *s = &bus->ifs[unit]; s->bus = bus; s->unit = unit; s->drive_serial = drive_serial++; /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */ s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); memset(s->io_buffer, 0, s->io_buffer_total_len); s->smart_selftest_data = qemu_blockalign(s->bs, 512); memset(s->smart_selftest_data, 0, 512); s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ide_sector_write_timer_cb, s); }
false
qemu
4be746345f13e99e468c60acbd3a355e8183e3ce
static void ide_init1(IDEBus *bus, int unit) { static int drive_serial = 1; IDEState *s = &bus->ifs[unit]; s->bus = bus; s->unit = unit; s->drive_serial = drive_serial++; s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); memset(s->io_buffer, 0, s->io_buffer_total_len); s->smart_selftest_data = qemu_blockalign(s->bs, 512); memset(s->smart_selftest_data, 0, 512); s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ide_sector_write_timer_cb, s); }
{ "code": [], "line_no": [] }
static void FUNC_0(IDEBus *VAR_0, int VAR_1) { static int VAR_2 = 1; IDEState *s = &VAR_0->ifs[VAR_1]; s->VAR_0 = VAR_0; s->VAR_1 = VAR_1; s->VAR_2 = VAR_2++; s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len); memset(s->io_buffer, 0, s->io_buffer_total_len); s->smart_selftest_data = qemu_blockalign(s->bs, 512); memset(s->smart_selftest_data, 0, 512); s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ide_sector_write_timer_cb, s); }
[ "static void FUNC_0(IDEBus *VAR_0, int VAR_1)\n{", "static int VAR_2 = 1;", "IDEState *s = &VAR_0->ifs[VAR_1];", "s->VAR_0 = VAR_0;", "s->VAR_1 = VAR_1;", "s->VAR_2 = VAR_2++;", "s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;", "s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);", "memset(s->io_buffer, 0, s->io_buffer_total_len);", "s->smart_selftest_data = qemu_blockalign(s->bs, 512);", "memset(s->smart_selftest_data, 0, 512);", "s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,\nide_sector_write_timer_cb, s);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 11 ], [ 13 ], [ 15 ], [ 19 ], [ 21 ], [ 23 ], [ 27 ], [ 29 ], [ 33, 35 ], [ 37 ] ]
16,904
int qcow2_grow_l1_table(BlockDriverState *bs, uint64_t min_size, bool exact_size) { BDRVQcowState *s = bs->opaque; int new_l1_size2, ret, i; uint64_t *new_l1_table; int64_t new_l1_table_offset, new_l1_size; uint8_t data[12]; if (min_size <= s->l1_size) return 0; if (exact_size) { new_l1_size = min_size; } else { /* Bump size up to reduce the number of times we have to grow */ new_l1_size = s->l1_size; if (new_l1_size == 0) { new_l1_size = 1; } while (min_size > new_l1_size) { new_l1_size = (new_l1_size * 3 + 1) / 2; } } if (new_l1_size > INT_MAX) { return -EFBIG; } #ifdef DEBUG_ALLOC2 fprintf(stderr, "grow l1_table from %d to %" PRId64 "\n", s->l1_size, new_l1_size); #endif new_l1_size2 = sizeof(uint64_t) * new_l1_size; new_l1_table = g_malloc0(align_offset(new_l1_size2, 512)); memcpy(new_l1_table, s->l1_table, s->l1_size * sizeof(uint64_t)); /* write new table (align to cluster) */ BLKDBG_EVENT(bs->file, BLKDBG_L1_GROW_ALLOC_TABLE); new_l1_table_offset = qcow2_alloc_clusters(bs, new_l1_size2); if (new_l1_table_offset < 0) { g_free(new_l1_table); return new_l1_table_offset; } ret = qcow2_cache_flush(bs, s->refcount_block_cache); if (ret < 0) { goto fail; } /* the L1 position has not yet been updated, so these clusters must * indeed be completely free */ ret = qcow2_pre_write_overlap_check(bs, QCOW2_OL_DEFAULT, new_l1_table_offset, new_l1_size2); if (ret < 0) { goto fail; } BLKDBG_EVENT(bs->file, BLKDBG_L1_GROW_WRITE_TABLE); for(i = 0; i < s->l1_size; i++) new_l1_table[i] = cpu_to_be64(new_l1_table[i]); ret = bdrv_pwrite_sync(bs->file, new_l1_table_offset, new_l1_table, new_l1_size2); if (ret < 0) goto fail; for(i = 0; i < s->l1_size; i++) new_l1_table[i] = be64_to_cpu(new_l1_table[i]); /* set new table */ BLKDBG_EVENT(bs->file, BLKDBG_L1_GROW_ACTIVATE_TABLE); cpu_to_be32w((uint32_t*)data, new_l1_size); cpu_to_be64wu((uint64_t*)(data + 4), new_l1_table_offset); ret = bdrv_pwrite_sync(bs->file, offsetof(QCowHeader, l1_size), data,sizeof(data)); if (ret < 0) { goto fail; } g_free(s->l1_table); qcow2_free_clusters(bs, s->l1_table_offset, s->l1_size * sizeof(uint64_t), QCOW2_DISCARD_OTHER); s->l1_table_offset = new_l1_table_offset; s->l1_table = new_l1_table; s->l1_size = new_l1_size; return 0; fail: g_free(new_l1_table); qcow2_free_clusters(bs, new_l1_table_offset, new_l1_size2, QCOW2_DISCARD_OTHER); return ret; }
false
qemu
fda74f826baec78d685e5a87fd8a95bfb7bb2243
int qcow2_grow_l1_table(BlockDriverState *bs, uint64_t min_size, bool exact_size) { BDRVQcowState *s = bs->opaque; int new_l1_size2, ret, i; uint64_t *new_l1_table; int64_t new_l1_table_offset, new_l1_size; uint8_t data[12]; if (min_size <= s->l1_size) return 0; if (exact_size) { new_l1_size = min_size; } else { new_l1_size = s->l1_size; if (new_l1_size == 0) { new_l1_size = 1; } while (min_size > new_l1_size) { new_l1_size = (new_l1_size * 3 + 1) / 2; } } if (new_l1_size > INT_MAX) { return -EFBIG; } #ifdef DEBUG_ALLOC2 fprintf(stderr, "grow l1_table from %d to %" PRId64 "\n", s->l1_size, new_l1_size); #endif new_l1_size2 = sizeof(uint64_t) * new_l1_size; new_l1_table = g_malloc0(align_offset(new_l1_size2, 512)); memcpy(new_l1_table, s->l1_table, s->l1_size * sizeof(uint64_t)); BLKDBG_EVENT(bs->file, BLKDBG_L1_GROW_ALLOC_TABLE); new_l1_table_offset = qcow2_alloc_clusters(bs, new_l1_size2); if (new_l1_table_offset < 0) { g_free(new_l1_table); return new_l1_table_offset; } ret = qcow2_cache_flush(bs, s->refcount_block_cache); if (ret < 0) { goto fail; } ret = qcow2_pre_write_overlap_check(bs, QCOW2_OL_DEFAULT, new_l1_table_offset, new_l1_size2); if (ret < 0) { goto fail; } BLKDBG_EVENT(bs->file, BLKDBG_L1_GROW_WRITE_TABLE); for(i = 0; i < s->l1_size; i++) new_l1_table[i] = cpu_to_be64(new_l1_table[i]); ret = bdrv_pwrite_sync(bs->file, new_l1_table_offset, new_l1_table, new_l1_size2); if (ret < 0) goto fail; for(i = 0; i < s->l1_size; i++) new_l1_table[i] = be64_to_cpu(new_l1_table[i]); BLKDBG_EVENT(bs->file, BLKDBG_L1_GROW_ACTIVATE_TABLE); cpu_to_be32w((uint32_t*)data, new_l1_size); cpu_to_be64wu((uint64_t*)(data + 4), new_l1_table_offset); ret = bdrv_pwrite_sync(bs->file, offsetof(QCowHeader, l1_size), data,sizeof(data)); if (ret < 0) { goto fail; } g_free(s->l1_table); qcow2_free_clusters(bs, s->l1_table_offset, s->l1_size * sizeof(uint64_t), QCOW2_DISCARD_OTHER); s->l1_table_offset = new_l1_table_offset; s->l1_table = new_l1_table; s->l1_size = new_l1_size; return 0; fail: g_free(new_l1_table); qcow2_free_clusters(bs, new_l1_table_offset, new_l1_size2, QCOW2_DISCARD_OTHER); return ret; }
{ "code": [], "line_no": [] }
int FUNC_0(BlockDriverState *VAR_0, uint64_t VAR_1, bool VAR_2) { BDRVQcowState *s = VAR_0->opaque; int VAR_3, VAR_4, VAR_5; uint64_t *new_l1_table; int64_t new_l1_table_offset, new_l1_size; uint8_t data[12]; if (VAR_1 <= s->l1_size) return 0; if (VAR_2) { new_l1_size = VAR_1; } else { new_l1_size = s->l1_size; if (new_l1_size == 0) { new_l1_size = 1; } while (VAR_1 > new_l1_size) { new_l1_size = (new_l1_size * 3 + 1) / 2; } } if (new_l1_size > INT_MAX) { return -EFBIG; } #ifdef DEBUG_ALLOC2 fprintf(stderr, "grow l1_table from %d to %" PRId64 "\n", s->l1_size, new_l1_size); #endif VAR_3 = sizeof(uint64_t) * new_l1_size; new_l1_table = g_malloc0(align_offset(VAR_3, 512)); memcpy(new_l1_table, s->l1_table, s->l1_size * sizeof(uint64_t)); BLKDBG_EVENT(VAR_0->file, BLKDBG_L1_GROW_ALLOC_TABLE); new_l1_table_offset = qcow2_alloc_clusters(VAR_0, VAR_3); if (new_l1_table_offset < 0) { g_free(new_l1_table); return new_l1_table_offset; } VAR_4 = qcow2_cache_flush(VAR_0, s->refcount_block_cache); if (VAR_4 < 0) { goto fail; } VAR_4 = qcow2_pre_write_overlap_check(VAR_0, QCOW2_OL_DEFAULT, new_l1_table_offset, VAR_3); if (VAR_4 < 0) { goto fail; } BLKDBG_EVENT(VAR_0->file, BLKDBG_L1_GROW_WRITE_TABLE); for(VAR_5 = 0; VAR_5 < s->l1_size; VAR_5++) new_l1_table[VAR_5] = cpu_to_be64(new_l1_table[VAR_5]); VAR_4 = bdrv_pwrite_sync(VAR_0->file, new_l1_table_offset, new_l1_table, VAR_3); if (VAR_4 < 0) goto fail; for(VAR_5 = 0; VAR_5 < s->l1_size; VAR_5++) new_l1_table[VAR_5] = be64_to_cpu(new_l1_table[VAR_5]); BLKDBG_EVENT(VAR_0->file, BLKDBG_L1_GROW_ACTIVATE_TABLE); cpu_to_be32w((uint32_t*)data, new_l1_size); cpu_to_be64wu((uint64_t*)(data + 4), new_l1_table_offset); VAR_4 = bdrv_pwrite_sync(VAR_0->file, offsetof(QCowHeader, l1_size), data,sizeof(data)); if (VAR_4 < 0) { goto fail; } g_free(s->l1_table); qcow2_free_clusters(VAR_0, s->l1_table_offset, s->l1_size * sizeof(uint64_t), QCOW2_DISCARD_OTHER); s->l1_table_offset = new_l1_table_offset; s->l1_table = new_l1_table; s->l1_size = new_l1_size; return 0; fail: g_free(new_l1_table); qcow2_free_clusters(VAR_0, new_l1_table_offset, VAR_3, QCOW2_DISCARD_OTHER); return VAR_4; }
[ "int FUNC_0(BlockDriverState *VAR_0, uint64_t VAR_1,\nbool VAR_2)\n{", "BDRVQcowState *s = VAR_0->opaque;", "int VAR_3, VAR_4, VAR_5;", "uint64_t *new_l1_table;", "int64_t new_l1_table_offset, new_l1_size;", "uint8_t data[12];", "if (VAR_1 <= s->l1_size)\nreturn 0;", "if (VAR_2) {", "new_l1_size = VAR_1;", "} else {", "new_l1_size = s->l1_size;", "if (new_l1_size == 0) {", "new_l1_size = 1;", "}", "while (VAR_1 > new_l1_size) {", "new_l1_size = (new_l1_size * 3 + 1) / 2;", "}", "}", "if (new_l1_size > INT_MAX) {", "return -EFBIG;", "}", "#ifdef DEBUG_ALLOC2\nfprintf(stderr, \"grow l1_table from %d to %\" PRId64 \"\\n\",\ns->l1_size, new_l1_size);", "#endif\nVAR_3 = sizeof(uint64_t) * new_l1_size;", "new_l1_table = g_malloc0(align_offset(VAR_3, 512));", "memcpy(new_l1_table, s->l1_table, s->l1_size * sizeof(uint64_t));", "BLKDBG_EVENT(VAR_0->file, BLKDBG_L1_GROW_ALLOC_TABLE);", "new_l1_table_offset = qcow2_alloc_clusters(VAR_0, VAR_3);", "if (new_l1_table_offset < 0) {", "g_free(new_l1_table);", "return new_l1_table_offset;", "}", "VAR_4 = qcow2_cache_flush(VAR_0, s->refcount_block_cache);", "if (VAR_4 < 0) {", "goto fail;", "}", "VAR_4 = qcow2_pre_write_overlap_check(VAR_0, QCOW2_OL_DEFAULT,\nnew_l1_table_offset, VAR_3);", "if (VAR_4 < 0) {", "goto fail;", "}", "BLKDBG_EVENT(VAR_0->file, BLKDBG_L1_GROW_WRITE_TABLE);", "for(VAR_5 = 0; VAR_5 < s->l1_size; VAR_5++)", "new_l1_table[VAR_5] = cpu_to_be64(new_l1_table[VAR_5]);", "VAR_4 = bdrv_pwrite_sync(VAR_0->file, new_l1_table_offset, new_l1_table, VAR_3);", "if (VAR_4 < 0)\ngoto fail;", "for(VAR_5 = 0; VAR_5 < s->l1_size; VAR_5++)", "new_l1_table[VAR_5] = be64_to_cpu(new_l1_table[VAR_5]);", "BLKDBG_EVENT(VAR_0->file, BLKDBG_L1_GROW_ACTIVATE_TABLE);", "cpu_to_be32w((uint32_t*)data, new_l1_size);", "cpu_to_be64wu((uint64_t*)(data + 4), new_l1_table_offset);", "VAR_4 = bdrv_pwrite_sync(VAR_0->file, offsetof(QCowHeader, l1_size), data,sizeof(data));", "if (VAR_4 < 0) {", "goto fail;", "}", "g_free(s->l1_table);", "qcow2_free_clusters(VAR_0, s->l1_table_offset, s->l1_size * sizeof(uint64_t),\nQCOW2_DISCARD_OTHER);", "s->l1_table_offset = new_l1_table_offset;", "s->l1_table = new_l1_table;", "s->l1_size = new_l1_size;", "return 0;", "fail:\ng_free(new_l1_table);", "qcow2_free_clusters(VAR_0, new_l1_table_offset, VAR_3,\nQCOW2_DISCARD_OTHER);", "return VAR_4;", "}" ]
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16,905
static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size) { switch (size) { case 1: return cpu_inb(addr); case 2: return cpu_inw(addr); case 4: return cpu_inl(addr); } abort(); }
false
qemu
a8170e5e97ad17ca169c64ba87ae2f53850dab4c
static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size) { switch (size) { case 1: return cpu_inb(addr); case 2: return cpu_inw(addr); case 4: return cpu_inl(addr); } abort(); }
{ "code": [], "line_no": [] }
static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr, unsigned size) { switch (size) { case 1: return cpu_inb(addr); case 2: return cpu_inw(addr); case 4: return cpu_inl(addr); } abort(); }
[ "static uint64_t FUNC_0(void *opaque, target_phys_addr_t addr, unsigned size)\n{", "switch (size) {", "case 1:\nreturn cpu_inb(addr);", "case 2:\nreturn cpu_inw(addr);", "case 4:\nreturn cpu_inl(addr);", "}", "abort();", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7, 9 ], [ 11, 13 ], [ 15, 17 ], [ 19 ], [ 21 ], [ 23 ] ]
16,906
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) { int i; static int inited; if (!inited) { inited = 1; for(i = 0;i < 256; i++) rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */ rop_to_index[CIRRUS_ROP_0] = 0; rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1; rop_to_index[CIRRUS_ROP_NOP] = 2; rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3; rop_to_index[CIRRUS_ROP_NOTDST] = 4; rop_to_index[CIRRUS_ROP_SRC] = 5; rop_to_index[CIRRUS_ROP_1] = 6; rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7; rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8; rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9; rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10; rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11; rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12; rop_to_index[CIRRUS_ROP_NOTSRC] = 13; rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14; rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15; s->device_id = device_id; if (is_pci) s->bustype = CIRRUS_BUSTYPE_PCI; else s->bustype = CIRRUS_BUSTYPE_ISA; } register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s); register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s); register_ioport_write(0x3da, 1, 1, vga_ioport_write, s); register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s); register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s); register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read, cirrus_vga_mem_write, s); cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, s->vga_io_memory); qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); /* I/O handler for LFB */ s->cirrus_linear_io_addr = cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s); s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr); /* I/O handler for LFB */ s->cirrus_linear_bitblt_io_addr = cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write, s); /* I/O handler for memory-mapped I/O */ s->cirrus_mmio_io_addr = cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s); s->real_vram_size = (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; /* XXX: s->vram_size must be a power of two */ s->cirrus_addr_mask = s->real_vram_size - 1; s->linear_mmio_mask = s->real_vram_size - 256; s->get_bpp = cirrus_get_bpp; s->get_offsets = cirrus_get_offsets; s->get_resolution = cirrus_get_resolution; s->cursor_invalidate = cirrus_cursor_invalidate; s->cursor_draw_line = cirrus_cursor_draw_line; qemu_register_reset(cirrus_reset, s); cirrus_reset(s); register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s); }
false
qemu
1dcea8e82b1d7795e6719a8ac8762993fc1ed4b3
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) { int i; static int inited; if (!inited) { inited = 1; for(i = 0;i < 256; i++) rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; rop_to_index[CIRRUS_ROP_0] = 0; rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1; rop_to_index[CIRRUS_ROP_NOP] = 2; rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3; rop_to_index[CIRRUS_ROP_NOTDST] = 4; rop_to_index[CIRRUS_ROP_SRC] = 5; rop_to_index[CIRRUS_ROP_1] = 6; rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7; rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8; rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9; rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10; rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11; rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12; rop_to_index[CIRRUS_ROP_NOTSRC] = 13; rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14; rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15; s->device_id = device_id; if (is_pci) s->bustype = CIRRUS_BUSTYPE_PCI; else s->bustype = CIRRUS_BUSTYPE_ISA; } register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s); register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s); register_ioport_write(0x3da, 1, 1, vga_ioport_write, s); register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s); register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s); register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read, cirrus_vga_mem_write, s); cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, s->vga_io_memory); qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); s->cirrus_linear_io_addr = cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s); s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr); s->cirrus_linear_bitblt_io_addr = cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write, s); s->cirrus_mmio_io_addr = cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s); s->real_vram_size = (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; s->cirrus_addr_mask = s->real_vram_size - 1; s->linear_mmio_mask = s->real_vram_size - 256; s->get_bpp = cirrus_get_bpp; s->get_offsets = cirrus_get_offsets; s->get_resolution = cirrus_get_resolution; s->cursor_invalidate = cirrus_cursor_invalidate; s->cursor_draw_line = cirrus_cursor_draw_line; qemu_register_reset(cirrus_reset, s); cirrus_reset(s); register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s); }
{ "code": [], "line_no": [] }
static void FUNC_0(CirrusVGAState * VAR_0, int VAR_1, int VAR_2) { int VAR_3; static int VAR_4; if (!VAR_4) { VAR_4 = 1; for(VAR_3 = 0;VAR_3 < 256; VAR_3++) rop_to_index[VAR_3] = CIRRUS_ROP_NOP_INDEX; rop_to_index[CIRRUS_ROP_0] = 0; rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1; rop_to_index[CIRRUS_ROP_NOP] = 2; rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3; rop_to_index[CIRRUS_ROP_NOTDST] = 4; rop_to_index[CIRRUS_ROP_SRC] = 5; rop_to_index[CIRRUS_ROP_1] = 6; rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7; rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8; rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9; rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10; rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11; rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12; rop_to_index[CIRRUS_ROP_NOTSRC] = 13; rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14; rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15; VAR_0->VAR_1 = VAR_1; if (VAR_2) VAR_0->bustype = CIRRUS_BUSTYPE_PCI; else VAR_0->bustype = CIRRUS_BUSTYPE_ISA; } register_ioport_write(0x3c0, 16, 1, vga_ioport_write, VAR_0); register_ioport_write(0x3b4, 2, 1, vga_ioport_write, VAR_0); register_ioport_write(0x3d4, 2, 1, vga_ioport_write, VAR_0); register_ioport_write(0x3ba, 1, 1, vga_ioport_write, VAR_0); register_ioport_write(0x3da, 1, 1, vga_ioport_write, VAR_0); register_ioport_read(0x3c0, 16, 1, vga_ioport_read, VAR_0); register_ioport_read(0x3b4, 2, 1, vga_ioport_read, VAR_0); register_ioport_read(0x3d4, 2, 1, vga_ioport_read, VAR_0); register_ioport_read(0x3ba, 1, 1, vga_ioport_read, VAR_0); register_ioport_read(0x3da, 1, 1, vga_ioport_read, VAR_0); VAR_0->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read, cirrus_vga_mem_write, VAR_0); cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, VAR_0->vga_io_memory); qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); VAR_0->cirrus_linear_io_addr = cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, VAR_0); VAR_0->cirrus_linear_write = cpu_get_io_memory_write(VAR_0->cirrus_linear_io_addr); VAR_0->cirrus_linear_bitblt_io_addr = cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write, VAR_0); VAR_0->cirrus_mmio_io_addr = cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, VAR_0); VAR_0->real_vram_size = (VAR_0->VAR_1 == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; VAR_0->cirrus_addr_mask = VAR_0->real_vram_size - 1; VAR_0->linear_mmio_mask = VAR_0->real_vram_size - 256; VAR_0->get_bpp = cirrus_get_bpp; VAR_0->get_offsets = cirrus_get_offsets; VAR_0->get_resolution = cirrus_get_resolution; VAR_0->cursor_invalidate = cirrus_cursor_invalidate; VAR_0->cursor_draw_line = cirrus_cursor_draw_line; qemu_register_reset(cirrus_reset, VAR_0); cirrus_reset(VAR_0); register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, VAR_0); }
[ "static void FUNC_0(CirrusVGAState * VAR_0, int VAR_1, int VAR_2)\n{", "int VAR_3;", "static int VAR_4;", "if (!VAR_4) {", "VAR_4 = 1;", "for(VAR_3 = 0;VAR_3 < 256; VAR_3++)", "rop_to_index[VAR_3] = CIRRUS_ROP_NOP_INDEX;", "rop_to_index[CIRRUS_ROP_0] = 0;", "rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;", "rop_to_index[CIRRUS_ROP_NOP] = 2;", "rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;", "rop_to_index[CIRRUS_ROP_NOTDST] = 4;", "rop_to_index[CIRRUS_ROP_SRC] = 5;", "rop_to_index[CIRRUS_ROP_1] = 6;", "rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;", "rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;", "rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;", "rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;", "rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;", "rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;", "rop_to_index[CIRRUS_ROP_NOTSRC] = 13;", "rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;", "rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;", "VAR_0->VAR_1 = VAR_1;", "if (VAR_2)\nVAR_0->bustype = CIRRUS_BUSTYPE_PCI;", "else\nVAR_0->bustype = CIRRUS_BUSTYPE_ISA;", "}", "register_ioport_write(0x3c0, 16, 1, vga_ioport_write, VAR_0);", "register_ioport_write(0x3b4, 2, 1, vga_ioport_write, VAR_0);", "register_ioport_write(0x3d4, 2, 1, vga_ioport_write, VAR_0);", "register_ioport_write(0x3ba, 1, 1, vga_ioport_write, VAR_0);", "register_ioport_write(0x3da, 1, 1, vga_ioport_write, VAR_0);", "register_ioport_read(0x3c0, 16, 1, vga_ioport_read, VAR_0);", "register_ioport_read(0x3b4, 2, 1, vga_ioport_read, VAR_0);", "register_ioport_read(0x3d4, 2, 1, vga_ioport_read, VAR_0);", "register_ioport_read(0x3ba, 1, 1, vga_ioport_read, VAR_0);", "register_ioport_read(0x3da, 1, 1, vga_ioport_read, VAR_0);", "VAR_0->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,\ncirrus_vga_mem_write, VAR_0);", "cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,\nVAR_0->vga_io_memory);", "qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);", "VAR_0->cirrus_linear_io_addr =\ncpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, VAR_0);", "VAR_0->cirrus_linear_write = cpu_get_io_memory_write(VAR_0->cirrus_linear_io_addr);", "VAR_0->cirrus_linear_bitblt_io_addr =\ncpu_register_io_memory(0, cirrus_linear_bitblt_read,\ncirrus_linear_bitblt_write, VAR_0);", "VAR_0->cirrus_mmio_io_addr =\ncpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, VAR_0);", "VAR_0->real_vram_size =\n(VAR_0->VAR_1 == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;", "VAR_0->cirrus_addr_mask = VAR_0->real_vram_size - 1;", "VAR_0->linear_mmio_mask = VAR_0->real_vram_size - 256;", "VAR_0->get_bpp = cirrus_get_bpp;", "VAR_0->get_offsets = cirrus_get_offsets;", "VAR_0->get_resolution = cirrus_get_resolution;", "VAR_0->cursor_invalidate = cirrus_cursor_invalidate;", "VAR_0->cursor_draw_line = cirrus_cursor_draw_line;", "qemu_register_reset(cirrus_reset, VAR_0);", "cirrus_reset(VAR_0);", "register_savevm(\"cirrus_vga\", 0, 2, cirrus_vga_save, cirrus_vga_load, VAR_0);", "}" ]
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16,907
static void translate_priority(GICState *s, int irq, int cpu, uint32_t *field, bool to_kernel) { if (to_kernel) { *field = GIC_GET_PRIORITY(irq, cpu) & 0xff; } else { gic_set_priority(s, cpu, irq, *field & 0xff); } }
false
qemu
8150847061f8d2606101bfff77cc6ec86b081ab0
static void translate_priority(GICState *s, int irq, int cpu, uint32_t *field, bool to_kernel) { if (to_kernel) { *field = GIC_GET_PRIORITY(irq, cpu) & 0xff; } else { gic_set_priority(s, cpu, irq, *field & 0xff); } }
{ "code": [], "line_no": [] }
static void FUNC_0(GICState *VAR_0, int VAR_1, int VAR_2, uint32_t *VAR_3, bool VAR_4) { if (VAR_4) { *VAR_3 = GIC_GET_PRIORITY(VAR_1, VAR_2) & 0xff; } else { gic_set_priority(VAR_0, VAR_2, VAR_1, *VAR_3 & 0xff); } }
[ "static void FUNC_0(GICState *VAR_0, int VAR_1, int VAR_2,\nuint32_t *VAR_3, bool VAR_4)\n{", "if (VAR_4) {", "*VAR_3 = GIC_GET_PRIORITY(VAR_1, VAR_2) & 0xff;", "} else {", "gic_set_priority(VAR_0, VAR_2, VAR_1, *VAR_3 & 0xff);", "}", "}" ]
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16,908
static void FUNC(transquant_bypass32x32)(uint8_t *_dst, int16_t *coeffs, ptrdiff_t stride) { int x, y; pixel *dst = (pixel *)_dst; stride /= sizeof(pixel); for (y = 0; y < 32; y++) { for (x = 0; x < 32; x++) { dst[x] += *coeffs; coeffs++; } dst += stride; } }
false
FFmpeg
c9fe0caf7a1abde7ca0b1a359f551103064867b1
static void FUNC(transquant_bypass32x32)(uint8_t *_dst, int16_t *coeffs, ptrdiff_t stride) { int x, y; pixel *dst = (pixel *)_dst; stride /= sizeof(pixel); for (y = 0; y < 32; y++) { for (x = 0; x < 32; x++) { dst[x] += *coeffs; coeffs++; } dst += stride; } }
{ "code": [], "line_no": [] }
static void FUNC_0(transquant_bypass32x32)(uint8_t *_dst, int16_t *coeffs, ptrdiff_t stride) { int VAR_0, VAR_1; pixel *dst = (pixel *)_dst; stride /= sizeof(pixel); for (VAR_1 = 0; VAR_1 < 32; VAR_1++) { for (VAR_0 = 0; VAR_0 < 32; VAR_0++) { dst[VAR_0] += *coeffs; coeffs++; } dst += stride; } }
[ "static void FUNC_0(transquant_bypass32x32)(uint8_t *_dst, int16_t *coeffs,\nptrdiff_t stride)\n{", "int VAR_0, VAR_1;", "pixel *dst = (pixel *)_dst;", "stride /= sizeof(pixel);", "for (VAR_1 = 0; VAR_1 < 32; VAR_1++) {", "for (VAR_0 = 0; VAR_0 < 32; VAR_0++) {", "dst[VAR_0] += *coeffs;", "coeffs++;", "}", "dst += stride;", "}", "}" ]
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16,910
static void ppc_heathrow_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; ram_addr_t ram_offset, bios_offset; uint32_t kernel_base, initrd_base, cmdline_base = 0; int32_t kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem; MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2]; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) cpu_model = "G3"; for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } /* Set time-base frequency to 16.6 Mhz */ cpu_ppc_tb_init(env, 16600000UL); qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); } /* allocate RAM */ if (ram_size > (2047 << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", ((unsigned int)ram_size / (1 << 20))); exit(1); } ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size); cpu_register_physical_memory(0, ram_size, ram_offset); /* allocate and load BIOS */ bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); /* Load OpenBIOS (ELF) */ if (filename) { bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); g_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; for (i = 0; boot_device[i] != '\0'; i++) { /* TOFIX: for now, the second IDE channel is not properly * used by OHW. The Mac floppy disk are not emulated. * For now, OHW cannot boot from the network. */ #if 0 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } #else if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { ppc_boot_device = boot_device[i]; break; } #endif } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for G3 Beige machine\n"); exit(1); } } /* Register 2 MB of ISA IO space */ isa_mmio_init(0xfe000000, 0x00200000); /* XXX: we register only 1 output pin for heathrow PIC */ heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); heathrow_irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); /* Connect the heathrow PIC outputs to the 6xx bus */ for (i = 0; i < smp_cpus; i++) { switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); heathrow_irqs[i][0] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; break; default: hw_error("Bus model not supported on OldWorld Mac machine\n"); } } /* init basic PC hardware */ if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { hw_error("Only 6xx bus is supported on heathrow machine\n"); } pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); pci_bus = pci_grackle_init(0xfec00000, pic, get_system_memory(), get_system_io()); pci_vga_init(pci_bus); escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); memory_region_init_alias(escc_bar, "escc-bar", escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); /* First IDE channel is a MAC IDE on the MacIO bus */ dbdma = DBDMA_init(&dbdma_mem); ide_mem[0] = NULL; ide_mem[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]); /* Second IDE channel is a CMD646 on the PCI bus */ hd[0] = hd[MAX_IDE_DEVS]; hd[1] = hd[MAX_IDE_DEVS + 1]; hd[3] = hd[2] = NULL; pci_cmd646_ide_init(pci_bus, hd, 0); /* cuda also initialize ADB */ cuda_init(&cuda_mem, pic[0x12]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); nvr = macio_nvram_init(0x2000, 4); pmac_format_nvram_partition(nvr, 0x2000); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem, dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; /* No PCI init: the BIOS will do it */ fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = g_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
false
qemu
b39491a83d0b9d573d5fd21163f61f66a11b54b9
static void ppc_heathrow_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { CPUState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; ram_addr_t ram_offset, bios_offset; uint32_t kernel_base, initrd_base, cmdline_base = 0; int32_t kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem; MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2]; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; void *dbdma; linux_boot = (kernel_filename != NULL); if (cpu_model == NULL) cpu_model = "G3"; for (i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } cpu_ppc_tb_init(env, 16600000UL); qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); } if (ram_size > (2047 << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", ((unsigned int)ram_size / (1 << 20))); exit(1); } ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size); cpu_register_physical_memory(0, ram_size, ram_offset); bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); if (filename) { bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); g_free(filename); } else { bios_size = -1; } if (bios_size < 0 || bios_size > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (linux_boot) { uint64_t lowaddr = 0; int bswap_needed; #ifdef BSWAP_NEEDED bswap_needed = 1; #else bswap_needed = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(kernel_filename, kernel_base, ram_size - kernel_base, bswap_needed, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(kernel_filename, kernel_base, ram_size - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } if (initrd_filename) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(initrd_filename, initrd_base, ram_size - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", initrd_filename); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; for (i = 0; boot_device[i] != '\0'; i++) { #if 0 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { ppc_boot_device = boot_device[i]; break; } #else if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { ppc_boot_device = boot_device[i]; break; } #endif } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for G3 Beige machine\n"); exit(1); } } isa_mmio_init(0xfe000000, 0x00200000); heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); heathrow_irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); for (i = 0; i < smp_cpus; i++) { switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); heathrow_irqs[i][0] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; break; default: hw_error("Bus model not supported on OldWorld Mac machine\n"); } } if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { hw_error("Only 6xx bus is supported on heathrow machine\n"); } pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); pci_bus = pci_grackle_init(0xfec00000, pic, get_system_memory(), get_system_io()); pci_vga_init(pci_bus); escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); memory_region_init_alias(escc_bar, "escc-bar", escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); dbdma = DBDMA_init(&dbdma_mem); ide_mem[0] = NULL; ide_mem[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]); hd[0] = hd[MAX_IDE_DEVS]; hd[1] = hd[MAX_IDE_DEVS + 1]; hd[3] = hd[2] = NULL; pci_cmd646_ide_init(pci_bus, hd, 0); cuda_init(&cuda_mem, pic[0x12]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); nvr = macio_nvram_init(0x2000, 4); pmac_format_nvram_partition(nvr, 0x2000); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem, dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); } else { fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = g_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); }
{ "code": [], "line_no": [] }
static void FUNC_0 (ram_addr_t VAR_0, const char *VAR_1, const char *VAR_2, const char *VAR_3, const char *VAR_4, const char *VAR_5) { CPUState *env = NULL; char *VAR_6; qemu_irq *pic, **heathrow_irqs; int VAR_7, VAR_8; ram_addr_t ram_offset, bios_offset; uint32_t kernel_base, initrd_base, cmdline_base = 0; int32_t kernel_size, initrd_size; PCIBus *pci_bus; MacIONVRAMState *nvr; int VAR_9; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem; MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2]; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *VAR_10; void *VAR_11; VAR_7 = (VAR_2 != NULL); if (VAR_5 == NULL) VAR_5 = "G3"; for (VAR_8 = 0; VAR_8 < smp_cpus; VAR_8++) { env = cpu_init(VAR_5); if (!env) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } cpu_ppc_tb_init(env, 16600000UL); qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); } if (VAR_0 > (2047 << 20)) { fprintf(stderr, "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", ((unsigned int)VAR_0 / (1 << 20))); exit(1); } ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", VAR_0); cpu_register_physical_memory(0, VAR_0, ram_offset); bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; VAR_6 = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); if (VAR_6) { VAR_9 = load_elf(VAR_6, 0, NULL, NULL, NULL, NULL, 1, ELF_MACHINE, 0); g_free(VAR_6); } else { VAR_9 = -1; } if (VAR_9 < 0 || VAR_9 > BIOS_SIZE) { hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); exit(1); } if (VAR_7) { uint64_t lowaddr = 0; int VAR_12; #ifdef BSWAP_NEEDED VAR_12 = 1; #else VAR_12 = 0; #endif kernel_base = KERNEL_LOAD_ADDR; kernel_size = load_elf(VAR_2, translate_kernel_address, NULL, NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); if (kernel_size < 0) kernel_size = load_aout(VAR_2, kernel_base, VAR_0 - kernel_base, VAR_12, TARGET_PAGE_SIZE); if (kernel_size < 0) kernel_size = load_image_targphys(VAR_2, kernel_base, VAR_0 - kernel_base); if (kernel_size < 0) { hw_error("qemu: could not load kernel '%s'\n", VAR_2); exit(1); } if (VAR_4) { initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); initrd_size = load_image_targphys(VAR_4, initrd_base, VAR_0 - initrd_base); if (initrd_size < 0) { hw_error("qemu: could not load initial ram disk '%s'\n", VAR_4); exit(1); } cmdline_base = round_page(initrd_base + initrd_size); } else { initrd_base = 0; initrd_size = 0; cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); } ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; ppc_boot_device = '\0'; for (VAR_8 = 0; VAR_1[VAR_8] != '\0'; VAR_8++) { #if 0 if (VAR_1[VAR_8] >= 'a' && VAR_1[VAR_8] <= 'f') { ppc_boot_device = VAR_1[VAR_8]; break; } #else if (VAR_1[VAR_8] >= 'c' && VAR_1[VAR_8] <= 'd') { ppc_boot_device = VAR_1[VAR_8]; break; } #endif } if (ppc_boot_device == '\0') { fprintf(stderr, "No valid boot device for G3 Beige machine\n"); exit(1); } } isa_mmio_init(0xfe000000, 0x00200000); heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); heathrow_irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); for (VAR_8 = 0; VAR_8 < smp_cpus; VAR_8++) { switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: heathrow_irqs[VAR_8] = heathrow_irqs[0] + (VAR_8 * 1); heathrow_irqs[VAR_8][0] = ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; break; default: hw_error("Bus model not supported on OldWorld Mac machine\n"); } } if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { hw_error("Only 6xx bus is supported on heathrow machine\n"); } pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); pci_bus = pci_grackle_init(0xfec00000, pic, get_system_memory(), get_system_io()); pci_vga_init(pci_bus); escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); memory_region_init_alias(escc_bar, "escc-bar", escc_mem, 0, memory_region_size(escc_mem)); for(VAR_8 = 0; VAR_8 < nb_nics; VAR_8++) pci_nic_init_nofail(&nd_table[VAR_8], "ne2k_pci", NULL); ide_drive_get(hd, MAX_IDE_BUS); VAR_11 = DBDMA_init(&dbdma_mem); ide_mem[0] = NULL; ide_mem[1] = pmac_ide_init(hd, pic[0x0D], VAR_11, 0x16, pic[0x02]); hd[0] = hd[MAX_IDE_DEVS]; hd[1] = hd[MAX_IDE_DEVS + 1]; hd[3] = hd[2] = NULL; pci_cmd646_ide_init(pci_bus, hd, 0); cuda_init(&cuda_mem, pic[0x12]); adb_kbd_init(&adb_bus); adb_mouse_init(&adb_bus); nvr = macio_nvram_init(0x2000, 4); pmac_format_nvram_partition(nvr, 0x2000); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem, dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); } if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) graphic_depth = 15; VAR_10 = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(VAR_10, FW_CFG_ID, 1); fw_cfg_add_i64(VAR_10, FW_CFG_RAM_SIZE, (uint64_t)VAR_0); fw_cfg_add_i16(VAR_10, FW_CFG_MACHINE_ID, ARCH_HEATHROW); fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_SIZE, kernel_size); if (VAR_3) { fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_CMDLINE, cmdline_base); pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, VAR_3); } else { fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_CMDLINE, 0); } fw_cfg_add_i32(VAR_10, FW_CFG_INITRD_ADDR, initrd_base); fw_cfg_add_i32(VAR_10, FW_CFG_INITRD_SIZE, initrd_size); fw_cfg_add_i16(VAR_10, FW_CFG_BOOT_DEVICE, ppc_boot_device); fw_cfg_add_i16(VAR_10, FW_CFG_PPC_WIDTH, graphic_width); fw_cfg_add_i16(VAR_10, FW_CFG_PPC_HEIGHT, graphic_height); fw_cfg_add_i16(VAR_10, FW_CFG_PPC_DEPTH, graphic_depth); fw_cfg_add_i32(VAR_10, FW_CFG_PPC_IS_KVM, kvm_enabled()); if (kvm_enabled()) { #ifdef CONFIG_KVM uint8_t *hypercall; fw_cfg_add_i32(VAR_10, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); hypercall = g_malloc(16); kvmppc_get_hypercall(env, hypercall, 16); fw_cfg_add_bytes(VAR_10, FW_CFG_PPC_KVM_HC, hypercall, 16); fw_cfg_add_i32(VAR_10, FW_CFG_PPC_KVM_PID, getpid()); #endif } else { fw_cfg_add_i32(VAR_10, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); } qemu_register_boot_set(fw_cfg_boot_set, VAR_10); }
[ "static void FUNC_0 (ram_addr_t VAR_0,\nconst char *VAR_1,\nconst char *VAR_2,\nconst char *VAR_3,\nconst char *VAR_4,\nconst char *VAR_5)\n{", "CPUState *env = NULL;", "char *VAR_6;", "qemu_irq *pic, **heathrow_irqs;", "int VAR_7, VAR_8;", "ram_addr_t ram_offset, bios_offset;", "uint32_t kernel_base, initrd_base, cmdline_base = 0;", "int32_t kernel_size, initrd_size;", "PCIBus *pci_bus;", "MacIONVRAMState *nvr;", "int VAR_9;", "MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem;", "MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2];", "uint16_t ppc_boot_device;", "DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];", "void *VAR_10;", "void *VAR_11;", "VAR_7 = (VAR_2 != NULL);", "if (VAR_5 == NULL)\nVAR_5 = \"G3\";", "for (VAR_8 = 0; VAR_8 < smp_cpus; VAR_8++) {", "env = cpu_init(VAR_5);", "if (!env) {", "fprintf(stderr, \"Unable to find PowerPC CPU definition\\n\");", "exit(1);", "}", "cpu_ppc_tb_init(env, 16600000UL);", "qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);", "}", "if (VAR_0 > (2047 << 20)) {", "fprintf(stderr,\n\"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\\n\",\n((unsigned int)VAR_0 / (1 << 20)));", "exit(1);", "}", "ram_offset = qemu_ram_alloc(NULL, \"ppc_heathrow.ram\", VAR_0);", "cpu_register_physical_memory(0, VAR_0, ram_offset);", "bios_offset = qemu_ram_alloc(NULL, \"ppc_heathrow.bios\", BIOS_SIZE);", "if (bios_name == NULL)\nbios_name = PROM_FILENAME;", "VAR_6 = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);", "cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);", "if (VAR_6) {", "VAR_9 = load_elf(VAR_6, 0, NULL, NULL, NULL, NULL,\n1, ELF_MACHINE, 0);", "g_free(VAR_6);", "} else {", "VAR_9 = -1;", "}", "if (VAR_9 < 0 || VAR_9 > BIOS_SIZE) {", "hw_error(\"qemu: could not load PowerPC bios '%s'\\n\", bios_name);", "exit(1);", "}", "if (VAR_7) {", "uint64_t lowaddr = 0;", "int VAR_12;", "#ifdef BSWAP_NEEDED\nVAR_12 = 1;", "#else\nVAR_12 = 0;", "#endif\nkernel_base = KERNEL_LOAD_ADDR;", "kernel_size = load_elf(VAR_2, translate_kernel_address, NULL,\nNULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);", "if (kernel_size < 0)\nkernel_size = load_aout(VAR_2, kernel_base,\nVAR_0 - kernel_base, VAR_12,\nTARGET_PAGE_SIZE);", "if (kernel_size < 0)\nkernel_size = load_image_targphys(VAR_2,\nkernel_base,\nVAR_0 - kernel_base);", "if (kernel_size < 0) {", "hw_error(\"qemu: could not load kernel '%s'\\n\",\nVAR_2);", "exit(1);", "}", "if (VAR_4) {", "initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);", "initrd_size = load_image_targphys(VAR_4, initrd_base,\nVAR_0 - initrd_base);", "if (initrd_size < 0) {", "hw_error(\"qemu: could not load initial ram disk '%s'\\n\",\nVAR_4);", "exit(1);", "}", "cmdline_base = round_page(initrd_base + initrd_size);", "} else {", "initrd_base = 0;", "initrd_size = 0;", "cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);", "}", "ppc_boot_device = 'm';", "} else {", "kernel_base = 0;", "kernel_size = 0;", "initrd_base = 0;", "initrd_size = 0;", "ppc_boot_device = '\\0';", "for (VAR_8 = 0; VAR_1[VAR_8] != '\\0'; VAR_8++) {", "#if 0\nif (VAR_1[VAR_8] >= 'a' && VAR_1[VAR_8] <= 'f') {", "ppc_boot_device = VAR_1[VAR_8];", "break;", "}", "#else\nif (VAR_1[VAR_8] >= 'c' && VAR_1[VAR_8] <= 'd') {", "ppc_boot_device = VAR_1[VAR_8];", "break;", "}", "#endif\n}", "if (ppc_boot_device == '\\0') {", "fprintf(stderr, \"No valid boot device for G3 Beige machine\\n\");", "exit(1);", "}", "}", "isa_mmio_init(0xfe000000, 0x00200000);", "heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));", "heathrow_irqs[0] =\ng_malloc0(smp_cpus * sizeof(qemu_irq) * 1);", "for (VAR_8 = 0; VAR_8 < smp_cpus; VAR_8++) {", "switch (PPC_INPUT(env)) {", "case PPC_FLAGS_INPUT_6xx:\nheathrow_irqs[VAR_8] = heathrow_irqs[0] + (VAR_8 * 1);", "heathrow_irqs[VAR_8][0] =\n((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];", "break;", "default:\nhw_error(\"Bus model not supported on OldWorld Mac machine\\n\");", "}", "}", "if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {", "hw_error(\"Only 6xx bus is supported on heathrow machine\\n\");", "}", "pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);", "pci_bus = pci_grackle_init(0xfec00000, pic,\nget_system_memory(),\nget_system_io());", "pci_vga_init(pci_bus);", "escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],\nserial_hds[1], ESCC_CLOCK, 4);", "memory_region_init_alias(escc_bar, \"escc-bar\",\nescc_mem, 0, memory_region_size(escc_mem));", "for(VAR_8 = 0; VAR_8 < nb_nics; VAR_8++)", "pci_nic_init_nofail(&nd_table[VAR_8], \"ne2k_pci\", NULL);", "ide_drive_get(hd, MAX_IDE_BUS);", "VAR_11 = DBDMA_init(&dbdma_mem);", "ide_mem[0] = NULL;", "ide_mem[1] = pmac_ide_init(hd, pic[0x0D], VAR_11, 0x16, pic[0x02]);", "hd[0] = hd[MAX_IDE_DEVS];", "hd[1] = hd[MAX_IDE_DEVS + 1];", "hd[3] = hd[2] = NULL;", "pci_cmd646_ide_init(pci_bus, hd, 0);", "cuda_init(&cuda_mem, pic[0x12]);", "adb_kbd_init(&adb_bus);", "adb_mouse_init(&adb_bus);", "nvr = macio_nvram_init(0x2000, 4);", "pmac_format_nvram_partition(nvr, 0x2000);", "macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem,\ndbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar);", "if (usb_enabled) {", "usb_ohci_init_pci(pci_bus, -1);", "}", "if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)\ngraphic_depth = 15;", "VAR_10 = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);", "fw_cfg_add_i32(VAR_10, FW_CFG_ID, 1);", "fw_cfg_add_i64(VAR_10, FW_CFG_RAM_SIZE, (uint64_t)VAR_0);", "fw_cfg_add_i16(VAR_10, FW_CFG_MACHINE_ID, ARCH_HEATHROW);", "fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_ADDR, kernel_base);", "fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_SIZE, kernel_size);", "if (VAR_3) {", "fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_CMDLINE, cmdline_base);", "pstrcpy_targphys(\"cmdline\", cmdline_base, TARGET_PAGE_SIZE, VAR_3);", "} else {", "fw_cfg_add_i32(VAR_10, FW_CFG_KERNEL_CMDLINE, 0);", "}", "fw_cfg_add_i32(VAR_10, FW_CFG_INITRD_ADDR, initrd_base);", "fw_cfg_add_i32(VAR_10, FW_CFG_INITRD_SIZE, initrd_size);", "fw_cfg_add_i16(VAR_10, FW_CFG_BOOT_DEVICE, ppc_boot_device);", "fw_cfg_add_i16(VAR_10, FW_CFG_PPC_WIDTH, graphic_width);", "fw_cfg_add_i16(VAR_10, FW_CFG_PPC_HEIGHT, graphic_height);", "fw_cfg_add_i16(VAR_10, FW_CFG_PPC_DEPTH, graphic_depth);", "fw_cfg_add_i32(VAR_10, FW_CFG_PPC_IS_KVM, kvm_enabled());", "if (kvm_enabled()) {", "#ifdef CONFIG_KVM\nuint8_t *hypercall;", "fw_cfg_add_i32(VAR_10, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());", "hypercall = g_malloc(16);", "kvmppc_get_hypercall(env, hypercall, 16);", "fw_cfg_add_bytes(VAR_10, FW_CFG_PPC_KVM_HC, hypercall, 16);", "fw_cfg_add_i32(VAR_10, FW_CFG_PPC_KVM_PID, getpid());", "#endif\n} else {", "fw_cfg_add_i32(VAR_10, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());", "}", "qemu_register_boot_set(fw_cfg_boot_set, VAR_10);", "}" ]
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16,911
static void *qesd_thread_out (void *arg) { ESDVoiceOut *esd = arg; HWVoiceOut *hw = &esd->hw; int threshold; threshold = conf.divisor ? hw->samples / conf.divisor : 0; if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) { return NULL; } for (;;) { int decr, to_mix, rpos; for (;;) { if (esd->done) { goto exit; } if (esd->live > threshold) { break; } if (audio_pt_wait (&esd->pt, AUDIO_FUNC)) { goto exit; } } decr = to_mix = esd->live; rpos = hw->rpos; if (audio_pt_unlock (&esd->pt, AUDIO_FUNC)) { return NULL; } while (to_mix) { ssize_t written; int chunk = audio_MIN (to_mix, hw->samples - rpos); st_sample_t *src = hw->mix_buf + rpos; hw->clip (esd->pcm_buf, src, chunk); again: written = write (esd->fd, esd->pcm_buf, chunk << hw->info.shift); if (written == -1) { if (errno == EINTR || errno == EAGAIN) { goto again; } qesd_logerr (errno, "write failed\n"); return NULL; } if (written != chunk << hw->info.shift) { int wsamples = written >> hw->info.shift; int wbytes = wsamples << hw->info.shift; if (wbytes != written) { dolog ("warning: Misaligned write %d (requested %d), " "alignment %d\n", wbytes, written, hw->info.align + 1); } to_mix -= wsamples; rpos = (rpos + wsamples) % hw->samples; break; } rpos = (rpos + chunk) % hw->samples; to_mix -= chunk; } if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) { return NULL; } esd->rpos = rpos; esd->live -= decr; esd->decr += decr; } exit: audio_pt_unlock (&esd->pt, AUDIO_FUNC); return NULL; }
false
qemu
1ea879e5580f63414693655fcf0328559cdce138
static void *qesd_thread_out (void *arg) { ESDVoiceOut *esd = arg; HWVoiceOut *hw = &esd->hw; int threshold; threshold = conf.divisor ? hw->samples / conf.divisor : 0; if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) { return NULL; } for (;;) { int decr, to_mix, rpos; for (;;) { if (esd->done) { goto exit; } if (esd->live > threshold) { break; } if (audio_pt_wait (&esd->pt, AUDIO_FUNC)) { goto exit; } } decr = to_mix = esd->live; rpos = hw->rpos; if (audio_pt_unlock (&esd->pt, AUDIO_FUNC)) { return NULL; } while (to_mix) { ssize_t written; int chunk = audio_MIN (to_mix, hw->samples - rpos); st_sample_t *src = hw->mix_buf + rpos; hw->clip (esd->pcm_buf, src, chunk); again: written = write (esd->fd, esd->pcm_buf, chunk << hw->info.shift); if (written == -1) { if (errno == EINTR || errno == EAGAIN) { goto again; } qesd_logerr (errno, "write failed\n"); return NULL; } if (written != chunk << hw->info.shift) { int wsamples = written >> hw->info.shift; int wbytes = wsamples << hw->info.shift; if (wbytes != written) { dolog ("warning: Misaligned write %d (requested %d), " "alignment %d\n", wbytes, written, hw->info.align + 1); } to_mix -= wsamples; rpos = (rpos + wsamples) % hw->samples; break; } rpos = (rpos + chunk) % hw->samples; to_mix -= chunk; } if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) { return NULL; } esd->rpos = rpos; esd->live -= decr; esd->decr += decr; } exit: audio_pt_unlock (&esd->pt, AUDIO_FUNC); return NULL; }
{ "code": [], "line_no": [] }
static void *FUNC_0 (void *VAR_0) { ESDVoiceOut *esd = VAR_0; HWVoiceOut *hw = &esd->hw; int VAR_1; VAR_1 = conf.divisor ? hw->samples / conf.divisor : 0; if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) { return NULL; } for (;;) { int VAR_2, VAR_3, VAR_4; for (;;) { if (esd->done) { goto exit; } if (esd->live > VAR_1) { break; } if (audio_pt_wait (&esd->pt, AUDIO_FUNC)) { goto exit; } } VAR_2 = VAR_3 = esd->live; VAR_4 = hw->VAR_4; if (audio_pt_unlock (&esd->pt, AUDIO_FUNC)) { return NULL; } while (VAR_3) { ssize_t written; int VAR_5 = audio_MIN (VAR_3, hw->samples - VAR_4); st_sample_t *src = hw->mix_buf + VAR_4; hw->clip (esd->pcm_buf, src, VAR_5); again: written = write (esd->fd, esd->pcm_buf, VAR_5 << hw->info.shift); if (written == -1) { if (errno == EINTR || errno == EAGAIN) { goto again; } qesd_logerr (errno, "write failed\n"); return NULL; } if (written != VAR_5 << hw->info.shift) { int VAR_6 = written >> hw->info.shift; int VAR_7 = VAR_6 << hw->info.shift; if (VAR_7 != written) { dolog ("warning: Misaligned write %d (requested %d), " "alignment %d\n", VAR_7, written, hw->info.align + 1); } VAR_3 -= VAR_6; VAR_4 = (VAR_4 + VAR_6) % hw->samples; break; } VAR_4 = (VAR_4 + VAR_5) % hw->samples; VAR_3 -= VAR_5; } if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) { return NULL; } esd->VAR_4 = VAR_4; esd->live -= VAR_2; esd->VAR_2 += VAR_2; } exit: audio_pt_unlock (&esd->pt, AUDIO_FUNC); return NULL; }
[ "static void *FUNC_0 (void *VAR_0)\n{", "ESDVoiceOut *esd = VAR_0;", "HWVoiceOut *hw = &esd->hw;", "int VAR_1;", "VAR_1 = conf.divisor ? hw->samples / conf.divisor : 0;", "if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) {", "return NULL;", "}", "for (;;) {", "int VAR_2, VAR_3, VAR_4;", "for (;;) {", "if (esd->done) {", "goto exit;", "}", "if (esd->live > VAR_1) {", "break;", "}", "if (audio_pt_wait (&esd->pt, AUDIO_FUNC)) {", "goto exit;", "}", "}", "VAR_2 = VAR_3 = esd->live;", "VAR_4 = hw->VAR_4;", "if (audio_pt_unlock (&esd->pt, AUDIO_FUNC)) {", "return NULL;", "}", "while (VAR_3) {", "ssize_t written;", "int VAR_5 = audio_MIN (VAR_3, hw->samples - VAR_4);", "st_sample_t *src = hw->mix_buf + VAR_4;", "hw->clip (esd->pcm_buf, src, VAR_5);", "again:\nwritten = write (esd->fd, esd->pcm_buf, VAR_5 << hw->info.shift);", "if (written == -1) {", "if (errno == EINTR || errno == EAGAIN) {", "goto again;", "}", "qesd_logerr (errno, \"write failed\\n\");", "return NULL;", "}", "if (written != VAR_5 << hw->info.shift) {", "int VAR_6 = written >> hw->info.shift;", "int VAR_7 = VAR_6 << hw->info.shift;", "if (VAR_7 != written) {", "dolog (\"warning: Misaligned write %d (requested %d), \"\n\"alignment %d\\n\",\nVAR_7, written, hw->info.align + 1);", "}", "VAR_3 -= VAR_6;", "VAR_4 = (VAR_4 + VAR_6) % hw->samples;", "break;", "}", "VAR_4 = (VAR_4 + VAR_5) % hw->samples;", "VAR_3 -= VAR_5;", "}", "if (audio_pt_lock (&esd->pt, AUDIO_FUNC)) {", "return NULL;", "}", "esd->VAR_4 = VAR_4;", "esd->live -= VAR_2;", "esd->VAR_2 += VAR_2;", "}", "exit:\naudio_pt_unlock (&esd->pt, AUDIO_FUNC);", "return NULL;", "}" ]
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16,912
static void v9fs_mkdir(void *opaque) { V9fsPDU *pdu = opaque; size_t offset = 7; int32_t fid; struct stat stbuf; V9fsQID qid; V9fsString name; V9fsFidState *fidp; gid_t gid; int mode; int err = 0; pdu_unmarshal(pdu, offset, "dsdd", &fid, &name, &mode, &gid); trace_v9fs_mkdir(pdu->tag, pdu->id, fid, name.data, mode, gid); fidp = get_fid(pdu, fid); if (fidp == NULL) { err = -ENOENT; goto out_nofid; } err = v9fs_co_mkdir(pdu, fidp, &name, mode, fidp->uid, gid, &stbuf); if (err < 0) { goto out; } stat_to_qid(&stbuf, &qid); offset += pdu_marshal(pdu, offset, "Q", &qid); err = offset; trace_v9fs_mkdir_return(pdu->tag, pdu->id, qid.type, qid.version, qid.path, err); out: put_fid(pdu, fidp); out_nofid: complete_pdu(pdu->s, pdu, err); v9fs_string_free(&name); }
false
qemu
ddca7f86ac022289840e0200fd4050b2b58e9176
static void v9fs_mkdir(void *opaque) { V9fsPDU *pdu = opaque; size_t offset = 7; int32_t fid; struct stat stbuf; V9fsQID qid; V9fsString name; V9fsFidState *fidp; gid_t gid; int mode; int err = 0; pdu_unmarshal(pdu, offset, "dsdd", &fid, &name, &mode, &gid); trace_v9fs_mkdir(pdu->tag, pdu->id, fid, name.data, mode, gid); fidp = get_fid(pdu, fid); if (fidp == NULL) { err = -ENOENT; goto out_nofid; } err = v9fs_co_mkdir(pdu, fidp, &name, mode, fidp->uid, gid, &stbuf); if (err < 0) { goto out; } stat_to_qid(&stbuf, &qid); offset += pdu_marshal(pdu, offset, "Q", &qid); err = offset; trace_v9fs_mkdir_return(pdu->tag, pdu->id, qid.type, qid.version, qid.path, err); out: put_fid(pdu, fidp); out_nofid: complete_pdu(pdu->s, pdu, err); v9fs_string_free(&name); }
{ "code": [], "line_no": [] }
static void FUNC_0(void *VAR_0) { V9fsPDU *pdu = VAR_0; size_t offset = 7; int32_t fid; struct stat VAR_1; V9fsQID qid; V9fsString name; V9fsFidState *fidp; gid_t gid; int VAR_2; int VAR_3 = 0; pdu_unmarshal(pdu, offset, "dsdd", &fid, &name, &VAR_2, &gid); trace_v9fs_mkdir(pdu->tag, pdu->id, fid, name.data, VAR_2, gid); fidp = get_fid(pdu, fid); if (fidp == NULL) { VAR_3 = -ENOENT; goto out_nofid; } VAR_3 = v9fs_co_mkdir(pdu, fidp, &name, VAR_2, fidp->uid, gid, &VAR_1); if (VAR_3 < 0) { goto out; } stat_to_qid(&VAR_1, &qid); offset += pdu_marshal(pdu, offset, "Q", &qid); VAR_3 = offset; trace_v9fs_mkdir_return(pdu->tag, pdu->id, qid.type, qid.version, qid.path, VAR_3); out: put_fid(pdu, fidp); out_nofid: complete_pdu(pdu->s, pdu, VAR_3); v9fs_string_free(&name); }
[ "static void FUNC_0(void *VAR_0)\n{", "V9fsPDU *pdu = VAR_0;", "size_t offset = 7;", "int32_t fid;", "struct stat VAR_1;", "V9fsQID qid;", "V9fsString name;", "V9fsFidState *fidp;", "gid_t gid;", "int VAR_2;", "int VAR_3 = 0;", "pdu_unmarshal(pdu, offset, \"dsdd\", &fid, &name, &VAR_2, &gid);", "trace_v9fs_mkdir(pdu->tag, pdu->id, fid, name.data, VAR_2, gid);", "fidp = get_fid(pdu, fid);", "if (fidp == NULL) {", "VAR_3 = -ENOENT;", "goto out_nofid;", "}", "VAR_3 = v9fs_co_mkdir(pdu, fidp, &name, VAR_2, fidp->uid, gid, &VAR_1);", "if (VAR_3 < 0) {", "goto out;", "}", "stat_to_qid(&VAR_1, &qid);", "offset += pdu_marshal(pdu, offset, \"Q\", &qid);", "VAR_3 = offset;", "trace_v9fs_mkdir_return(pdu->tag, pdu->id,\nqid.type, qid.version, qid.path, VAR_3);", "out:\nput_fid(pdu, fidp);", "out_nofid:\ncomplete_pdu(pdu->s, pdu, VAR_3);", "v9fs_string_free(&name);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ], [ 27 ], [ 31 ], [ 35 ], [ 37 ], [ 39 ], [ 41 ], [ 43 ], [ 45 ], [ 47 ], [ 49 ], [ 51 ], [ 53 ], [ 55 ], [ 57 ], [ 59, 61 ], [ 63, 65 ], [ 67, 69 ], [ 71 ], [ 73 ] ]
16,913
static void peer_test_vnet_hdr(VirtIONet *n) { NetClientState *nc = qemu_get_queue(n->nic); if (!nc->peer) { return; } n->has_vnet_hdr = qemu_peer_has_vnet_hdr(nc); }
false
qemu
d6085e3ace20bc9b0fa625d8d79b22668710e217
static void peer_test_vnet_hdr(VirtIONet *n) { NetClientState *nc = qemu_get_queue(n->nic); if (!nc->peer) { return; } n->has_vnet_hdr = qemu_peer_has_vnet_hdr(nc); }
{ "code": [], "line_no": [] }
static void FUNC_0(VirtIONet *VAR_0) { NetClientState *nc = qemu_get_queue(VAR_0->nic); if (!nc->peer) { return; } VAR_0->has_vnet_hdr = qemu_peer_has_vnet_hdr(nc); }
[ "static void FUNC_0(VirtIONet *VAR_0)\n{", "NetClientState *nc = qemu_get_queue(VAR_0->nic);", "if (!nc->peer) {", "return;", "}", "VAR_0->has_vnet_hdr = qemu_peer_has_vnet_hdr(nc);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 15 ], [ 17 ] ]
16,914
static void tpm_tis_receive_bh(void *opaque) { TPMState *s = opaque; TPMTISEmuState *tis = &s->s.tis; uint8_t locty = s->locty_number; tis->loc[locty].sts = TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE; tis->loc[locty].state = TPM_TIS_STATE_COMPLETION; tis->loc[locty].r_offset = 0; tis->loc[locty].w_offset = 0; if (TPM_TIS_IS_VALID_LOCTY(tis->next_locty)) { tpm_tis_abort(s, locty); } #ifndef RAISE_STS_IRQ tpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE); #else tpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE | TPM_TIS_INT_STS_VALID); #endif }
false
qemu
fd859081453f94c3cbd6527289e41b7fddbf645f
static void tpm_tis_receive_bh(void *opaque) { TPMState *s = opaque; TPMTISEmuState *tis = &s->s.tis; uint8_t locty = s->locty_number; tis->loc[locty].sts = TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE; tis->loc[locty].state = TPM_TIS_STATE_COMPLETION; tis->loc[locty].r_offset = 0; tis->loc[locty].w_offset = 0; if (TPM_TIS_IS_VALID_LOCTY(tis->next_locty)) { tpm_tis_abort(s, locty); } #ifndef RAISE_STS_IRQ tpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE); #else tpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE | TPM_TIS_INT_STS_VALID); #endif }
{ "code": [], "line_no": [] }
static void FUNC_0(void *VAR_0) { TPMState *s = VAR_0; TPMTISEmuState *tis = &s->s.tis; uint8_t locty = s->locty_number; tis->loc[locty].sts = TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE; tis->loc[locty].state = TPM_TIS_STATE_COMPLETION; tis->loc[locty].r_offset = 0; tis->loc[locty].w_offset = 0; if (TPM_TIS_IS_VALID_LOCTY(tis->next_locty)) { tpm_tis_abort(s, locty); } #ifndef RAISE_STS_IRQ tpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE); #else tpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE | TPM_TIS_INT_STS_VALID); #endif }
[ "static void FUNC_0(void *VAR_0)\n{", "TPMState *s = VAR_0;", "TPMTISEmuState *tis = &s->s.tis;", "uint8_t locty = s->locty_number;", "tis->loc[locty].sts = TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE;", "tis->loc[locty].state = TPM_TIS_STATE_COMPLETION;", "tis->loc[locty].r_offset = 0;", "tis->loc[locty].w_offset = 0;", "if (TPM_TIS_IS_VALID_LOCTY(tis->next_locty)) {", "tpm_tis_abort(s, locty);", "}", "#ifndef RAISE_STS_IRQ\ntpm_tis_raise_irq(s, locty, TPM_TIS_INT_DATA_AVAILABLE);", "#else\ntpm_tis_raise_irq(s, locty,\nTPM_TIS_INT_DATA_AVAILABLE | TPM_TIS_INT_STS_VALID);", "#endif\n}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 23 ], [ 25 ], [ 27 ], [ 31, 33 ], [ 35, 37, 39 ], [ 41, 43 ] ]
16,915
static int omap_validate_imif_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); }
false
qemu
a8170e5e97ad17ca169c64ba87ae2f53850dab4c
static int omap_validate_imif_addr(struct omap_mpu_state_s *s, target_phys_addr_t addr) { return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); }
{ "code": [], "line_no": [] }
static int FUNC_0(struct omap_mpu_state_s *VAR_0, target_phys_addr_t VAR_1) { return range_covers_byte(OMAP_IMIF_BASE, VAR_0->sram_size, VAR_1); }
[ "static int FUNC_0(struct omap_mpu_state_s *VAR_0,\ntarget_phys_addr_t VAR_1)\n{", "return range_covers_byte(OMAP_IMIF_BASE, VAR_0->sram_size, VAR_1);", "}" ]
[ 0, 0, 0 ]
[ [ 1, 3, 5 ], [ 7 ], [ 9 ] ]
16,918
static void rtas_set_indicator(PowerPCCPU *cpu, sPAPRMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { uint32_t sensor_type; uint32_t sensor_index; uint32_t sensor_state; uint32_t ret = RTAS_OUT_SUCCESS; sPAPRDRConnector *drc; sPAPRDRConnectorClass *drck; if (nargs != 3 || nret != 1) { ret = RTAS_OUT_PARAM_ERROR; goto out; } sensor_type = rtas_ld(args, 0); sensor_index = rtas_ld(args, 1); sensor_state = rtas_ld(args, 2); if (!sensor_type_is_dr(sensor_type)) { goto out_unimplemented; } /* if this is a DR sensor we can assume sensor_index == drc_index */ drc = spapr_drc_by_index(sensor_index); if (!drc) { trace_spapr_rtas_set_indicator_invalid(sensor_index); ret = RTAS_OUT_PARAM_ERROR; goto out; } drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); switch (sensor_type) { case RTAS_SENSOR_TYPE_ISOLATION_STATE: ret = drck->set_isolation_state(drc, sensor_state); break; case RTAS_SENSOR_TYPE_DR: ret = drck->set_indicator_state(drc, sensor_state); break; case RTAS_SENSOR_TYPE_ALLOCATION_STATE: ret = drck->set_allocation_state(drc, sensor_state); break; default: goto out_unimplemented; } out: rtas_st(rets, 0, ret); return; out_unimplemented: /* currently only DR-related sensors are implemented */ trace_spapr_rtas_set_indicator_not_supported(sensor_index, sensor_type); rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); }
false
qemu
7b7258f810d2bd40e2fb99c469c5db318d6c3d92
static void rtas_set_indicator(PowerPCCPU *cpu, sPAPRMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets) { uint32_t sensor_type; uint32_t sensor_index; uint32_t sensor_state; uint32_t ret = RTAS_OUT_SUCCESS; sPAPRDRConnector *drc; sPAPRDRConnectorClass *drck; if (nargs != 3 || nret != 1) { ret = RTAS_OUT_PARAM_ERROR; goto out; } sensor_type = rtas_ld(args, 0); sensor_index = rtas_ld(args, 1); sensor_state = rtas_ld(args, 2); if (!sensor_type_is_dr(sensor_type)) { goto out_unimplemented; } drc = spapr_drc_by_index(sensor_index); if (!drc) { trace_spapr_rtas_set_indicator_invalid(sensor_index); ret = RTAS_OUT_PARAM_ERROR; goto out; } drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); switch (sensor_type) { case RTAS_SENSOR_TYPE_ISOLATION_STATE: ret = drck->set_isolation_state(drc, sensor_state); break; case RTAS_SENSOR_TYPE_DR: ret = drck->set_indicator_state(drc, sensor_state); break; case RTAS_SENSOR_TYPE_ALLOCATION_STATE: ret = drck->set_allocation_state(drc, sensor_state); break; default: goto out_unimplemented; } out: rtas_st(rets, 0, ret); return; out_unimplemented: trace_spapr_rtas_set_indicator_not_supported(sensor_index, sensor_type); rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); }
{ "code": [], "line_no": [] }
static void FUNC_0(PowerPCCPU *VAR_0, sPAPRMachineState *VAR_1, uint32_t VAR_2, uint32_t VAR_3, target_ulong VAR_4, uint32_t VAR_5, target_ulong VAR_6) { uint32_t sensor_type; uint32_t sensor_index; uint32_t sensor_state; uint32_t ret = RTAS_OUT_SUCCESS; sPAPRDRConnector *drc; sPAPRDRConnectorClass *drck; if (VAR_3 != 3 || VAR_5 != 1) { ret = RTAS_OUT_PARAM_ERROR; goto out; } sensor_type = rtas_ld(VAR_4, 0); sensor_index = rtas_ld(VAR_4, 1); sensor_state = rtas_ld(VAR_4, 2); if (!sensor_type_is_dr(sensor_type)) { goto out_unimplemented; } drc = spapr_drc_by_index(sensor_index); if (!drc) { trace_spapr_rtas_set_indicator_invalid(sensor_index); ret = RTAS_OUT_PARAM_ERROR; goto out; } drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); switch (sensor_type) { case RTAS_SENSOR_TYPE_ISOLATION_STATE: ret = drck->set_isolation_state(drc, sensor_state); break; case RTAS_SENSOR_TYPE_DR: ret = drck->set_indicator_state(drc, sensor_state); break; case RTAS_SENSOR_TYPE_ALLOCATION_STATE: ret = drck->set_allocation_state(drc, sensor_state); break; default: goto out_unimplemented; } out: rtas_st(VAR_6, 0, ret); return; out_unimplemented: trace_spapr_rtas_set_indicator_not_supported(sensor_index, sensor_type); rtas_st(VAR_6, 0, RTAS_OUT_NOT_SUPPORTED); }
[ "static void FUNC_0(PowerPCCPU *VAR_0, sPAPRMachineState *VAR_1,\nuint32_t VAR_2, uint32_t VAR_3,\ntarget_ulong VAR_4, uint32_t VAR_5,\ntarget_ulong VAR_6)\n{", "uint32_t sensor_type;", "uint32_t sensor_index;", "uint32_t sensor_state;", "uint32_t ret = RTAS_OUT_SUCCESS;", "sPAPRDRConnector *drc;", "sPAPRDRConnectorClass *drck;", "if (VAR_3 != 3 || VAR_5 != 1) {", "ret = RTAS_OUT_PARAM_ERROR;", "goto out;", "}", "sensor_type = rtas_ld(VAR_4, 0);", "sensor_index = rtas_ld(VAR_4, 1);", "sensor_state = rtas_ld(VAR_4, 2);", "if (!sensor_type_is_dr(sensor_type)) {", "goto out_unimplemented;", "}", "drc = spapr_drc_by_index(sensor_index);", "if (!drc) {", "trace_spapr_rtas_set_indicator_invalid(sensor_index);", "ret = RTAS_OUT_PARAM_ERROR;", "goto out;", "}", "drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);", "switch (sensor_type) {", "case RTAS_SENSOR_TYPE_ISOLATION_STATE:\nret = drck->set_isolation_state(drc, sensor_state);", "break;", "case RTAS_SENSOR_TYPE_DR:\nret = drck->set_indicator_state(drc, sensor_state);", "break;", "case RTAS_SENSOR_TYPE_ALLOCATION_STATE:\nret = drck->set_allocation_state(drc, sensor_state);", "break;", "default:\ngoto out_unimplemented;", "}", "out:\nrtas_st(VAR_6, 0, ret);", "return;", "out_unimplemented:\ntrace_spapr_rtas_set_indicator_not_supported(sensor_index, sensor_type);", "rtas_st(VAR_6, 0, RTAS_OUT_NOT_SUPPORTED);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5, 7, 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 25 ], [ 27 ], [ 29 ], [ 31 ], [ 35 ], [ 37 ], [ 39 ], [ 43 ], [ 45 ], [ 47 ], [ 53 ], [ 55 ], [ 57 ], [ 59 ], [ 61 ], [ 63 ], [ 65 ], [ 69 ], [ 71, 73 ], [ 75 ], [ 77, 79 ], [ 81 ], [ 83, 85 ], [ 87 ], [ 89, 91 ], [ 93 ], [ 97, 99 ], [ 101 ], [ 105, 109 ], [ 111 ], [ 113 ] ]
16,919
static int g2m_decode_frame(AVCodecContext *avctx, void *data, int *got_picture_ptr, AVPacket *avpkt) { const uint8_t *buf = avpkt->data; int buf_size = avpkt->size; G2MContext *c = avctx->priv_data; AVFrame *pic = data; GetByteContext bc, tbc; int magic; int got_header = 0; uint32_t chunk_size, cur_size; int chunk_type; int i; int ret; if (buf_size < 12) { av_log(avctx, AV_LOG_ERROR, "Frame should have at least 12 bytes, got %d instead\n", buf_size); return AVERROR_INVALIDDATA; } bytestream2_init(&bc, buf, buf_size); magic = bytestream2_get_be32(&bc); if ((magic & ~0xF) != MKBETAG('G', '2', 'M', '0') || (magic & 0xF) < 2 || (magic & 0xF) > 4) { av_log(avctx, AV_LOG_ERROR, "Wrong magic %08X\n", magic); return AVERROR_INVALIDDATA; } if ((magic & 0xF) != 4) { av_log(avctx, AV_LOG_ERROR, "G2M2 and G2M3 are not yet supported\n"); return AVERROR(ENOSYS); } while (bytestream2_get_bytes_left(&bc) > 5) { chunk_size = bytestream2_get_le32(&bc) - 1; chunk_type = bytestream2_get_byte(&bc); if (chunk_size > bytestream2_get_bytes_left(&bc)) { av_log(avctx, AV_LOG_ERROR, "Invalid chunk size %d type %02X\n", chunk_size, chunk_type); break; } switch (chunk_type) { case FRAME_INFO: c->got_header = 0; if (chunk_size < 21) { av_log(avctx, AV_LOG_ERROR, "Invalid frame info size %d\n", chunk_size); break; } c->width = bytestream2_get_be32(&bc); c->height = bytestream2_get_be32(&bc); if (c->width < 16 || c->width > avctx->width || c->height < 16 || c->height > avctx->height) { av_log(avctx, AV_LOG_ERROR, "Invalid frame dimensions %dx%d\n", c->width, c->height); c->width = c->height = 0; bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc)); } if (c->width != avctx->width || c->height != avctx->height) avcodec_set_dimensions(avctx, c->width, c->height); c->compression = bytestream2_get_be32(&bc); if (c->compression != 2 && c->compression != 3) { av_log(avctx, AV_LOG_ERROR, "Unknown compression method %d\n", c->compression); return AVERROR_PATCHWELCOME; } c->tile_width = bytestream2_get_be32(&bc); c->tile_height = bytestream2_get_be32(&bc); if (!c->tile_width || !c->tile_height) { av_log(avctx, AV_LOG_ERROR, "Invalid tile dimensions %dx%d\n", c->tile_width, c->tile_height); return AVERROR_INVALIDDATA; } c->tiles_x = (c->width + c->tile_width - 1) / c->tile_width; c->tiles_y = (c->height + c->tile_height - 1) / c->tile_height; c->bpp = bytestream2_get_byte(&bc); chunk_size -= 21; bytestream2_skip(&bc, chunk_size); if (g2m_init_buffers(c)) return AVERROR(ENOMEM); got_header = 1; break; case TILE_DATA: if (!c->tiles_x || !c->tiles_y) { av_log(avctx, AV_LOG_WARNING, "No frame header - skipping tile\n"); bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc)); break; } if (chunk_size < 2) { av_log(avctx, AV_LOG_ERROR, "Invalid tile data size %d\n", chunk_size); break; } c->tile_x = bytestream2_get_byte(&bc); c->tile_y = bytestream2_get_byte(&bc); if (c->tile_x >= c->tiles_x || c->tile_y >= c->tiles_y) { av_log(avctx, AV_LOG_ERROR, "Invalid tile pos %d,%d (in %dx%d grid)\n", c->tile_x, c->tile_y, c->tiles_x, c->tiles_y); break; } chunk_size -= 2; ret = 0; switch (c->compression) { case COMPR_EPIC_J_B: av_log(avctx, AV_LOG_ERROR, "ePIC j-b compression is not implemented yet\n"); return AVERROR(ENOSYS); case COMPR_KEMPF_J_B: ret = kempf_decode_tile(c, c->tile_x, c->tile_y, buf + bytestream2_tell(&bc), chunk_size); break; } if (ret && c->framebuf) av_log(avctx, AV_LOG_ERROR, "Error decoding tile %d,%d\n", c->tile_x, c->tile_y); bytestream2_skip(&bc, chunk_size); break; case CURSOR_POS: if (chunk_size < 5) { av_log(avctx, AV_LOG_ERROR, "Invalid cursor pos size %d\n", chunk_size); break; } c->cursor_x = bytestream2_get_be16(&bc); c->cursor_y = bytestream2_get_be16(&bc); bytestream2_skip(&bc, chunk_size - 4); break; case CURSOR_SHAPE: if (chunk_size < 8) { av_log(avctx, AV_LOG_ERROR, "Invalid cursor data size %d\n", chunk_size); break; } bytestream2_init(&tbc, buf + bytestream2_tell(&bc), chunk_size - 4); cur_size = bytestream2_get_be32(&tbc); c->cursor_w = bytestream2_get_byte(&tbc); c->cursor_h = bytestream2_get_byte(&tbc); c->cursor_hot_x = bytestream2_get_byte(&tbc); c->cursor_hot_y = bytestream2_get_byte(&tbc); c->cursor_fmt = bytestream2_get_byte(&tbc); if (cur_size >= chunk_size || c->cursor_w * c->cursor_h / 4 > cur_size) { av_log(avctx, AV_LOG_ERROR, "Invalid cursor data size %d\n", chunk_size); break; } g2m_load_cursor(c, &tbc); bytestream2_skip(&bc, chunk_size); break; case CHUNK_CC: case CHUNK_CD: bytestream2_skip(&bc, chunk_size); break; default: av_log(avctx, AV_LOG_WARNING, "Skipping chunk type %02X\n", chunk_type); bytestream2_skip(&bc, chunk_size); } } if (got_header) c->got_header = 1; if (c->width && c->height && c->framebuf) { if ((ret = ff_get_buffer(avctx, pic, 0)) < 0) { av_log(avctx, AV_LOG_ERROR, "get_buffer() failed\n"); return ret; } pic->key_frame = got_header; pic->pict_type = got_header ? AV_PICTURE_TYPE_I : AV_PICTURE_TYPE_P; for (i = 0; i < avctx->height; i++) memcpy(pic->data[0] + i * pic->linesize[0], c->framebuf + i * c->framebuf_stride, c->width * 3); g2m_paint_cursor(c, pic->data[0], pic->linesize[0]); *got_picture_ptr = 1; } return buf_size; }
false
FFmpeg
ada497e61660b4a23d49eaf07fe19386573a6ba9
static int g2m_decode_frame(AVCodecContext *avctx, void *data, int *got_picture_ptr, AVPacket *avpkt) { const uint8_t *buf = avpkt->data; int buf_size = avpkt->size; G2MContext *c = avctx->priv_data; AVFrame *pic = data; GetByteContext bc, tbc; int magic; int got_header = 0; uint32_t chunk_size, cur_size; int chunk_type; int i; int ret; if (buf_size < 12) { av_log(avctx, AV_LOG_ERROR, "Frame should have at least 12 bytes, got %d instead\n", buf_size); return AVERROR_INVALIDDATA; } bytestream2_init(&bc, buf, buf_size); magic = bytestream2_get_be32(&bc); if ((magic & ~0xF) != MKBETAG('G', '2', 'M', '0') || (magic & 0xF) < 2 || (magic & 0xF) > 4) { av_log(avctx, AV_LOG_ERROR, "Wrong magic %08X\n", magic); return AVERROR_INVALIDDATA; } if ((magic & 0xF) != 4) { av_log(avctx, AV_LOG_ERROR, "G2M2 and G2M3 are not yet supported\n"); return AVERROR(ENOSYS); } while (bytestream2_get_bytes_left(&bc) > 5) { chunk_size = bytestream2_get_le32(&bc) - 1; chunk_type = bytestream2_get_byte(&bc); if (chunk_size > bytestream2_get_bytes_left(&bc)) { av_log(avctx, AV_LOG_ERROR, "Invalid chunk size %d type %02X\n", chunk_size, chunk_type); break; } switch (chunk_type) { case FRAME_INFO: c->got_header = 0; if (chunk_size < 21) { av_log(avctx, AV_LOG_ERROR, "Invalid frame info size %d\n", chunk_size); break; } c->width = bytestream2_get_be32(&bc); c->height = bytestream2_get_be32(&bc); if (c->width < 16 || c->width > avctx->width || c->height < 16 || c->height > avctx->height) { av_log(avctx, AV_LOG_ERROR, "Invalid frame dimensions %dx%d\n", c->width, c->height); c->width = c->height = 0; bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc)); } if (c->width != avctx->width || c->height != avctx->height) avcodec_set_dimensions(avctx, c->width, c->height); c->compression = bytestream2_get_be32(&bc); if (c->compression != 2 && c->compression != 3) { av_log(avctx, AV_LOG_ERROR, "Unknown compression method %d\n", c->compression); return AVERROR_PATCHWELCOME; } c->tile_width = bytestream2_get_be32(&bc); c->tile_height = bytestream2_get_be32(&bc); if (!c->tile_width || !c->tile_height) { av_log(avctx, AV_LOG_ERROR, "Invalid tile dimensions %dx%d\n", c->tile_width, c->tile_height); return AVERROR_INVALIDDATA; } c->tiles_x = (c->width + c->tile_width - 1) / c->tile_width; c->tiles_y = (c->height + c->tile_height - 1) / c->tile_height; c->bpp = bytestream2_get_byte(&bc); chunk_size -= 21; bytestream2_skip(&bc, chunk_size); if (g2m_init_buffers(c)) return AVERROR(ENOMEM); got_header = 1; break; case TILE_DATA: if (!c->tiles_x || !c->tiles_y) { av_log(avctx, AV_LOG_WARNING, "No frame header - skipping tile\n"); bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc)); break; } if (chunk_size < 2) { av_log(avctx, AV_LOG_ERROR, "Invalid tile data size %d\n", chunk_size); break; } c->tile_x = bytestream2_get_byte(&bc); c->tile_y = bytestream2_get_byte(&bc); if (c->tile_x >= c->tiles_x || c->tile_y >= c->tiles_y) { av_log(avctx, AV_LOG_ERROR, "Invalid tile pos %d,%d (in %dx%d grid)\n", c->tile_x, c->tile_y, c->tiles_x, c->tiles_y); break; } chunk_size -= 2; ret = 0; switch (c->compression) { case COMPR_EPIC_J_B: av_log(avctx, AV_LOG_ERROR, "ePIC j-b compression is not implemented yet\n"); return AVERROR(ENOSYS); case COMPR_KEMPF_J_B: ret = kempf_decode_tile(c, c->tile_x, c->tile_y, buf + bytestream2_tell(&bc), chunk_size); break; } if (ret && c->framebuf) av_log(avctx, AV_LOG_ERROR, "Error decoding tile %d,%d\n", c->tile_x, c->tile_y); bytestream2_skip(&bc, chunk_size); break; case CURSOR_POS: if (chunk_size < 5) { av_log(avctx, AV_LOG_ERROR, "Invalid cursor pos size %d\n", chunk_size); break; } c->cursor_x = bytestream2_get_be16(&bc); c->cursor_y = bytestream2_get_be16(&bc); bytestream2_skip(&bc, chunk_size - 4); break; case CURSOR_SHAPE: if (chunk_size < 8) { av_log(avctx, AV_LOG_ERROR, "Invalid cursor data size %d\n", chunk_size); break; } bytestream2_init(&tbc, buf + bytestream2_tell(&bc), chunk_size - 4); cur_size = bytestream2_get_be32(&tbc); c->cursor_w = bytestream2_get_byte(&tbc); c->cursor_h = bytestream2_get_byte(&tbc); c->cursor_hot_x = bytestream2_get_byte(&tbc); c->cursor_hot_y = bytestream2_get_byte(&tbc); c->cursor_fmt = bytestream2_get_byte(&tbc); if (cur_size >= chunk_size || c->cursor_w * c->cursor_h / 4 > cur_size) { av_log(avctx, AV_LOG_ERROR, "Invalid cursor data size %d\n", chunk_size); break; } g2m_load_cursor(c, &tbc); bytestream2_skip(&bc, chunk_size); break; case CHUNK_CC: case CHUNK_CD: bytestream2_skip(&bc, chunk_size); break; default: av_log(avctx, AV_LOG_WARNING, "Skipping chunk type %02X\n", chunk_type); bytestream2_skip(&bc, chunk_size); } } if (got_header) c->got_header = 1; if (c->width && c->height && c->framebuf) { if ((ret = ff_get_buffer(avctx, pic, 0)) < 0) { av_log(avctx, AV_LOG_ERROR, "get_buffer() failed\n"); return ret; } pic->key_frame = got_header; pic->pict_type = got_header ? AV_PICTURE_TYPE_I : AV_PICTURE_TYPE_P; for (i = 0; i < avctx->height; i++) memcpy(pic->data[0] + i * pic->linesize[0], c->framebuf + i * c->framebuf_stride, c->width * 3); g2m_paint_cursor(c, pic->data[0], pic->linesize[0]); *got_picture_ptr = 1; } return buf_size; }
{ "code": [], "line_no": [] }
static int FUNC_0(AVCodecContext *VAR_0, void *VAR_1, int *VAR_2, AVPacket *VAR_3) { const uint8_t *VAR_4 = VAR_3->VAR_1; int VAR_5 = VAR_3->size; G2MContext *c = VAR_0->priv_data; AVFrame *pic = VAR_1; GetByteContext bc, tbc; int VAR_6; int VAR_7 = 0; uint32_t chunk_size, cur_size; int VAR_8; int VAR_9; int VAR_10; if (VAR_5 < 12) { av_log(VAR_0, AV_LOG_ERROR, "Frame should have at least 12 bytes, got %d instead\n", VAR_5); return AVERROR_INVALIDDATA; } bytestream2_init(&bc, VAR_4, VAR_5); VAR_6 = bytestream2_get_be32(&bc); if ((VAR_6 & ~0xF) != MKBETAG('G', '2', 'M', '0') || (VAR_6 & 0xF) < 2 || (VAR_6 & 0xF) > 4) { av_log(VAR_0, AV_LOG_ERROR, "Wrong VAR_6 %08X\n", VAR_6); return AVERROR_INVALIDDATA; } if ((VAR_6 & 0xF) != 4) { av_log(VAR_0, AV_LOG_ERROR, "G2M2 and G2M3 are not yet supported\n"); return AVERROR(ENOSYS); } while (bytestream2_get_bytes_left(&bc) > 5) { chunk_size = bytestream2_get_le32(&bc) - 1; VAR_8 = bytestream2_get_byte(&bc); if (chunk_size > bytestream2_get_bytes_left(&bc)) { av_log(VAR_0, AV_LOG_ERROR, "Invalid chunk size %d type %02X\n", chunk_size, VAR_8); break; } switch (VAR_8) { case FRAME_INFO: c->VAR_7 = 0; if (chunk_size < 21) { av_log(VAR_0, AV_LOG_ERROR, "Invalid frame info size %d\n", chunk_size); break; } c->width = bytestream2_get_be32(&bc); c->height = bytestream2_get_be32(&bc); if (c->width < 16 || c->width > VAR_0->width || c->height < 16 || c->height > VAR_0->height) { av_log(VAR_0, AV_LOG_ERROR, "Invalid frame dimensions %dx%d\n", c->width, c->height); c->width = c->height = 0; bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc)); } if (c->width != VAR_0->width || c->height != VAR_0->height) avcodec_set_dimensions(VAR_0, c->width, c->height); c->compression = bytestream2_get_be32(&bc); if (c->compression != 2 && c->compression != 3) { av_log(VAR_0, AV_LOG_ERROR, "Unknown compression method %d\n", c->compression); return AVERROR_PATCHWELCOME; } c->tile_width = bytestream2_get_be32(&bc); c->tile_height = bytestream2_get_be32(&bc); if (!c->tile_width || !c->tile_height) { av_log(VAR_0, AV_LOG_ERROR, "Invalid tile dimensions %dx%d\n", c->tile_width, c->tile_height); return AVERROR_INVALIDDATA; } c->tiles_x = (c->width + c->tile_width - 1) / c->tile_width; c->tiles_y = (c->height + c->tile_height - 1) / c->tile_height; c->bpp = bytestream2_get_byte(&bc); chunk_size -= 21; bytestream2_skip(&bc, chunk_size); if (g2m_init_buffers(c)) return AVERROR(ENOMEM); VAR_7 = 1; break; case TILE_DATA: if (!c->tiles_x || !c->tiles_y) { av_log(VAR_0, AV_LOG_WARNING, "No frame header - skipping tile\n"); bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc)); break; } if (chunk_size < 2) { av_log(VAR_0, AV_LOG_ERROR, "Invalid tile VAR_1 size %d\n", chunk_size); break; } c->tile_x = bytestream2_get_byte(&bc); c->tile_y = bytestream2_get_byte(&bc); if (c->tile_x >= c->tiles_x || c->tile_y >= c->tiles_y) { av_log(VAR_0, AV_LOG_ERROR, "Invalid tile pos %d,%d (in %dx%d grid)\n", c->tile_x, c->tile_y, c->tiles_x, c->tiles_y); break; } chunk_size -= 2; VAR_10 = 0; switch (c->compression) { case COMPR_EPIC_J_B: av_log(VAR_0, AV_LOG_ERROR, "ePIC j-b compression is not implemented yet\n"); return AVERROR(ENOSYS); case COMPR_KEMPF_J_B: VAR_10 = kempf_decode_tile(c, c->tile_x, c->tile_y, VAR_4 + bytestream2_tell(&bc), chunk_size); break; } if (VAR_10 && c->framebuf) av_log(VAR_0, AV_LOG_ERROR, "Error decoding tile %d,%d\n", c->tile_x, c->tile_y); bytestream2_skip(&bc, chunk_size); break; case CURSOR_POS: if (chunk_size < 5) { av_log(VAR_0, AV_LOG_ERROR, "Invalid cursor pos size %d\n", chunk_size); break; } c->cursor_x = bytestream2_get_be16(&bc); c->cursor_y = bytestream2_get_be16(&bc); bytestream2_skip(&bc, chunk_size - 4); break; case CURSOR_SHAPE: if (chunk_size < 8) { av_log(VAR_0, AV_LOG_ERROR, "Invalid cursor VAR_1 size %d\n", chunk_size); break; } bytestream2_init(&tbc, VAR_4 + bytestream2_tell(&bc), chunk_size - 4); cur_size = bytestream2_get_be32(&tbc); c->cursor_w = bytestream2_get_byte(&tbc); c->cursor_h = bytestream2_get_byte(&tbc); c->cursor_hot_x = bytestream2_get_byte(&tbc); c->cursor_hot_y = bytestream2_get_byte(&tbc); c->cursor_fmt = bytestream2_get_byte(&tbc); if (cur_size >= chunk_size || c->cursor_w * c->cursor_h / 4 > cur_size) { av_log(VAR_0, AV_LOG_ERROR, "Invalid cursor VAR_1 size %d\n", chunk_size); break; } g2m_load_cursor(c, &tbc); bytestream2_skip(&bc, chunk_size); break; case CHUNK_CC: case CHUNK_CD: bytestream2_skip(&bc, chunk_size); break; default: av_log(VAR_0, AV_LOG_WARNING, "Skipping chunk type %02X\n", VAR_8); bytestream2_skip(&bc, chunk_size); } } if (VAR_7) c->VAR_7 = 1; if (c->width && c->height && c->framebuf) { if ((VAR_10 = ff_get_buffer(VAR_0, pic, 0)) < 0) { av_log(VAR_0, AV_LOG_ERROR, "get_buffer() failed\n"); return VAR_10; } pic->key_frame = VAR_7; pic->pict_type = VAR_7 ? AV_PICTURE_TYPE_I : AV_PICTURE_TYPE_P; for (VAR_9 = 0; VAR_9 < VAR_0->height; VAR_9++) memcpy(pic->VAR_1[0] + VAR_9 * pic->linesize[0], c->framebuf + VAR_9 * c->framebuf_stride, c->width * 3); g2m_paint_cursor(c, pic->VAR_1[0], pic->linesize[0]); *VAR_2 = 1; } return VAR_5; }
[ "static int FUNC_0(AVCodecContext *VAR_0, void *VAR_1,\nint *VAR_2, AVPacket *VAR_3)\n{", "const uint8_t *VAR_4 = VAR_3->VAR_1;", "int VAR_5 = VAR_3->size;", "G2MContext *c = VAR_0->priv_data;", "AVFrame *pic = VAR_1;", "GetByteContext bc, tbc;", "int VAR_6;", "int VAR_7 = 0;", "uint32_t chunk_size, cur_size;", "int VAR_8;", "int VAR_9;", "int VAR_10;", "if (VAR_5 < 12) {", "av_log(VAR_0, AV_LOG_ERROR,\n\"Frame should have at least 12 bytes, got %d instead\\n\",\nVAR_5);", "return AVERROR_INVALIDDATA;", "}", "bytestream2_init(&bc, VAR_4, VAR_5);", "VAR_6 = bytestream2_get_be32(&bc);", "if ((VAR_6 & ~0xF) != MKBETAG('G', '2', 'M', '0') ||\n(VAR_6 & 0xF) < 2 || (VAR_6 & 0xF) > 4) {", "av_log(VAR_0, AV_LOG_ERROR, \"Wrong VAR_6 %08X\\n\", VAR_6);", "return AVERROR_INVALIDDATA;", "}", "if ((VAR_6 & 0xF) != 4) {", "av_log(VAR_0, AV_LOG_ERROR, \"G2M2 and G2M3 are not yet supported\\n\");", "return AVERROR(ENOSYS);", "}", "while (bytestream2_get_bytes_left(&bc) > 5) {", "chunk_size = bytestream2_get_le32(&bc) - 1;", "VAR_8 = bytestream2_get_byte(&bc);", "if (chunk_size > bytestream2_get_bytes_left(&bc)) {", "av_log(VAR_0, AV_LOG_ERROR, \"Invalid chunk size %d type %02X\\n\",\nchunk_size, VAR_8);", "break;", "}", "switch (VAR_8) {", "case FRAME_INFO:\nc->VAR_7 = 0;", "if (chunk_size < 21) {", "av_log(VAR_0, AV_LOG_ERROR, \"Invalid frame info size %d\\n\",\nchunk_size);", "break;", "}", "c->width = bytestream2_get_be32(&bc);", "c->height = bytestream2_get_be32(&bc);", "if (c->width < 16 || c->width > VAR_0->width ||\nc->height < 16 || c->height > VAR_0->height) {", "av_log(VAR_0, AV_LOG_ERROR,\n\"Invalid frame dimensions %dx%d\\n\",\nc->width, c->height);", "c->width = c->height = 0;", "bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc));", "}", "if (c->width != VAR_0->width || c->height != VAR_0->height)\navcodec_set_dimensions(VAR_0, c->width, c->height);", "c->compression = bytestream2_get_be32(&bc);", "if (c->compression != 2 && c->compression != 3) {", "av_log(VAR_0, AV_LOG_ERROR,\n\"Unknown compression method %d\\n\",\nc->compression);", "return AVERROR_PATCHWELCOME;", "}", "c->tile_width = bytestream2_get_be32(&bc);", "c->tile_height = bytestream2_get_be32(&bc);", "if (!c->tile_width || !c->tile_height) {", "av_log(VAR_0, AV_LOG_ERROR,\n\"Invalid tile dimensions %dx%d\\n\",\nc->tile_width, c->tile_height);", "return AVERROR_INVALIDDATA;", "}", "c->tiles_x = (c->width + c->tile_width - 1) / c->tile_width;", "c->tiles_y = (c->height + c->tile_height - 1) / c->tile_height;", "c->bpp = bytestream2_get_byte(&bc);", "chunk_size -= 21;", "bytestream2_skip(&bc, chunk_size);", "if (g2m_init_buffers(c))\nreturn AVERROR(ENOMEM);", "VAR_7 = 1;", "break;", "case TILE_DATA:\nif (!c->tiles_x || !c->tiles_y) {", "av_log(VAR_0, AV_LOG_WARNING,\n\"No frame header - skipping tile\\n\");", "bytestream2_skip(&bc, bytestream2_get_bytes_left(&bc));", "break;", "}", "if (chunk_size < 2) {", "av_log(VAR_0, AV_LOG_ERROR, \"Invalid tile VAR_1 size %d\\n\",\nchunk_size);", "break;", "}", "c->tile_x = bytestream2_get_byte(&bc);", "c->tile_y = bytestream2_get_byte(&bc);", "if (c->tile_x >= c->tiles_x || c->tile_y >= c->tiles_y) {", "av_log(VAR_0, AV_LOG_ERROR,\n\"Invalid tile pos %d,%d (in %dx%d grid)\\n\",\nc->tile_x, c->tile_y, c->tiles_x, c->tiles_y);", "break;", "}", "chunk_size -= 2;", "VAR_10 = 0;", "switch (c->compression) {", "case COMPR_EPIC_J_B:\nav_log(VAR_0, AV_LOG_ERROR,\n\"ePIC j-b compression is not implemented yet\\n\");", "return AVERROR(ENOSYS);", "case COMPR_KEMPF_J_B:\nVAR_10 = kempf_decode_tile(c, c->tile_x, c->tile_y,\nVAR_4 + bytestream2_tell(&bc),\nchunk_size);", "break;", "}", "if (VAR_10 && c->framebuf)\nav_log(VAR_0, AV_LOG_ERROR, \"Error decoding tile %d,%d\\n\",\nc->tile_x, c->tile_y);", "bytestream2_skip(&bc, chunk_size);", "break;", "case CURSOR_POS:\nif (chunk_size < 5) {", "av_log(VAR_0, AV_LOG_ERROR, \"Invalid cursor pos size %d\\n\",\nchunk_size);", "break;", "}", "c->cursor_x = bytestream2_get_be16(&bc);", "c->cursor_y = bytestream2_get_be16(&bc);", "bytestream2_skip(&bc, chunk_size - 4);", "break;", "case CURSOR_SHAPE:\nif (chunk_size < 8) {", "av_log(VAR_0, AV_LOG_ERROR, \"Invalid cursor VAR_1 size %d\\n\",\nchunk_size);", "break;", "}", "bytestream2_init(&tbc, VAR_4 + bytestream2_tell(&bc),\nchunk_size - 4);", "cur_size = bytestream2_get_be32(&tbc);", "c->cursor_w = bytestream2_get_byte(&tbc);", "c->cursor_h = bytestream2_get_byte(&tbc);", "c->cursor_hot_x = bytestream2_get_byte(&tbc);", "c->cursor_hot_y = bytestream2_get_byte(&tbc);", "c->cursor_fmt = bytestream2_get_byte(&tbc);", "if (cur_size >= chunk_size ||\nc->cursor_w * c->cursor_h / 4 > cur_size) {", "av_log(VAR_0, AV_LOG_ERROR, \"Invalid cursor VAR_1 size %d\\n\",\nchunk_size);", "break;", "}", "g2m_load_cursor(c, &tbc);", "bytestream2_skip(&bc, chunk_size);", "break;", "case CHUNK_CC:\ncase CHUNK_CD:\nbytestream2_skip(&bc, chunk_size);", "break;", "default:\nav_log(VAR_0, AV_LOG_WARNING, \"Skipping chunk type %02X\\n\",\nVAR_8);", "bytestream2_skip(&bc, chunk_size);", "}", "}", "if (VAR_7)\nc->VAR_7 = 1;", "if (c->width && c->height && c->framebuf) {", "if ((VAR_10 = ff_get_buffer(VAR_0, pic, 0)) < 0) {", "av_log(VAR_0, AV_LOG_ERROR, \"get_buffer() failed\\n\");", "return VAR_10;", "}", "pic->key_frame = VAR_7;", "pic->pict_type = VAR_7 ? AV_PICTURE_TYPE_I : AV_PICTURE_TYPE_P;", "for (VAR_9 = 0; VAR_9 < VAR_0->height; VAR_9++)", "memcpy(pic->VAR_1[0] + VAR_9 * pic->linesize[0],\nc->framebuf + VAR_9 * c->framebuf_stride,\nc->width * 3);", "g2m_paint_cursor(c, pic->VAR_1[0], pic->linesize[0]);", "*VAR_2 = 1;", "}", "return VAR_5;", "}" ]
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16,920
static inline void chroma_4mv_motion_lowres(MpegEncContext *s, uint8_t *dest_cb, uint8_t *dest_cr, uint8_t **ref_picture, h264_chroma_mc_func * pix_op, int mx, int my) { const int lowres = s->avctx->lowres; const int op_index = FFMIN(lowres, 2); const int block_s = 8 >> lowres; const int s_mask = (2 << lowres) - 1; const int h_edge_pos = s->h_edge_pos >> lowres + 1; const int v_edge_pos = s->v_edge_pos >> lowres + 1; int emu = 0, src_x, src_y, offset, sx, sy; uint8_t *ptr; if (s->quarter_sample) { mx /= 2; my /= 2; } /* In case of 8X8, we construct a single chroma motion vector with a special rounding */ mx = ff_h263_round_chroma(mx); my = ff_h263_round_chroma(my); sx = mx & s_mask; sy = my & s_mask; src_x = s->mb_x * block_s + (mx >> lowres + 1); src_y = s->mb_y * block_s + (my >> lowres + 1); offset = src_y * s->uvlinesize + src_x; ptr = ref_picture[1] + offset; if (s->flags & CODEC_FLAG_EMU_EDGE) { if ((unsigned) src_x > FFMAX(h_edge_pos - (!!sx) - block_s, 0) || (unsigned) src_y > FFMAX(v_edge_pos - (!!sy) - block_s, 0)) { s->vdsp.emulated_edge_mc(s->edge_emu_buffer, ptr, s->uvlinesize, 9, 9, src_x, src_y, h_edge_pos, v_edge_pos); ptr = s->edge_emu_buffer; emu = 1; } } sx = (sx << 2) >> lowres; sy = (sy << 2) >> lowres; pix_op[op_index](dest_cb, ptr, s->uvlinesize, block_s, sx, sy); ptr = ref_picture[2] + offset; if (emu) { s->vdsp.emulated_edge_mc(s->edge_emu_buffer, ptr, s->uvlinesize, 9, 9, src_x, src_y, h_edge_pos, v_edge_pos); ptr = s->edge_emu_buffer; } pix_op[op_index](dest_cr, ptr, s->uvlinesize, block_s, sx, sy); }
false
FFmpeg
0abe923d20db6280dfdfa8a4ed07710ad8376e97
static inline void chroma_4mv_motion_lowres(MpegEncContext *s, uint8_t *dest_cb, uint8_t *dest_cr, uint8_t **ref_picture, h264_chroma_mc_func * pix_op, int mx, int my) { const int lowres = s->avctx->lowres; const int op_index = FFMIN(lowres, 2); const int block_s = 8 >> lowres; const int s_mask = (2 << lowres) - 1; const int h_edge_pos = s->h_edge_pos >> lowres + 1; const int v_edge_pos = s->v_edge_pos >> lowres + 1; int emu = 0, src_x, src_y, offset, sx, sy; uint8_t *ptr; if (s->quarter_sample) { mx /= 2; my /= 2; } mx = ff_h263_round_chroma(mx); my = ff_h263_round_chroma(my); sx = mx & s_mask; sy = my & s_mask; src_x = s->mb_x * block_s + (mx >> lowres + 1); src_y = s->mb_y * block_s + (my >> lowres + 1); offset = src_y * s->uvlinesize + src_x; ptr = ref_picture[1] + offset; if (s->flags & CODEC_FLAG_EMU_EDGE) { if ((unsigned) src_x > FFMAX(h_edge_pos - (!!sx) - block_s, 0) || (unsigned) src_y > FFMAX(v_edge_pos - (!!sy) - block_s, 0)) { s->vdsp.emulated_edge_mc(s->edge_emu_buffer, ptr, s->uvlinesize, 9, 9, src_x, src_y, h_edge_pos, v_edge_pos); ptr = s->edge_emu_buffer; emu = 1; } } sx = (sx << 2) >> lowres; sy = (sy << 2) >> lowres; pix_op[op_index](dest_cb, ptr, s->uvlinesize, block_s, sx, sy); ptr = ref_picture[2] + offset; if (emu) { s->vdsp.emulated_edge_mc(s->edge_emu_buffer, ptr, s->uvlinesize, 9, 9, src_x, src_y, h_edge_pos, v_edge_pos); ptr = s->edge_emu_buffer; } pix_op[op_index](dest_cr, ptr, s->uvlinesize, block_s, sx, sy); }
{ "code": [], "line_no": [] }
static inline void FUNC_0(MpegEncContext *VAR_0, uint8_t *VAR_1, uint8_t *VAR_2, uint8_t **VAR_3, h264_chroma_mc_func * VAR_4, int VAR_5, int VAR_6) { const int VAR_7 = VAR_0->avctx->VAR_7; const int VAR_8 = FFMIN(VAR_7, 2); const int VAR_9 = 8 >> VAR_7; const int VAR_10 = (2 << VAR_7) - 1; const int VAR_11 = VAR_0->VAR_11 >> VAR_7 + 1; const int VAR_12 = VAR_0->VAR_12 >> VAR_7 + 1; int VAR_13 = 0, VAR_14, VAR_15, VAR_16, VAR_17, VAR_18; uint8_t *ptr; if (VAR_0->quarter_sample) { VAR_5 /= 2; VAR_6 /= 2; } VAR_5 = ff_h263_round_chroma(VAR_5); VAR_6 = ff_h263_round_chroma(VAR_6); VAR_17 = VAR_5 & VAR_10; VAR_18 = VAR_6 & VAR_10; VAR_14 = VAR_0->mb_x * VAR_9 + (VAR_5 >> VAR_7 + 1); VAR_15 = VAR_0->mb_y * VAR_9 + (VAR_6 >> VAR_7 + 1); VAR_16 = VAR_15 * VAR_0->uvlinesize + VAR_14; ptr = VAR_3[1] + VAR_16; if (VAR_0->flags & CODEC_FLAG_EMU_EDGE) { if ((unsigned) VAR_14 > FFMAX(VAR_11 - (!!VAR_17) - VAR_9, 0) || (unsigned) VAR_15 > FFMAX(VAR_12 - (!!VAR_18) - VAR_9, 0)) { VAR_0->vdsp.emulated_edge_mc(VAR_0->edge_emu_buffer, ptr, VAR_0->uvlinesize, 9, 9, VAR_14, VAR_15, VAR_11, VAR_12); ptr = VAR_0->edge_emu_buffer; VAR_13 = 1; } } VAR_17 = (VAR_17 << 2) >> VAR_7; VAR_18 = (VAR_18 << 2) >> VAR_7; VAR_4[VAR_8](VAR_1, ptr, VAR_0->uvlinesize, VAR_9, VAR_17, VAR_18); ptr = VAR_3[2] + VAR_16; if (VAR_13) { VAR_0->vdsp.emulated_edge_mc(VAR_0->edge_emu_buffer, ptr, VAR_0->uvlinesize, 9, 9, VAR_14, VAR_15, VAR_11, VAR_12); ptr = VAR_0->edge_emu_buffer; } VAR_4[VAR_8](VAR_2, ptr, VAR_0->uvlinesize, VAR_9, VAR_17, VAR_18); }
[ "static inline void FUNC_0(MpegEncContext *VAR_0,\nuint8_t *VAR_1, uint8_t *VAR_2,\nuint8_t **VAR_3,\nh264_chroma_mc_func * VAR_4,\nint VAR_5, int VAR_6)\n{", "const int VAR_7 = VAR_0->avctx->VAR_7;", "const int VAR_8 = FFMIN(VAR_7, 2);", "const int VAR_9 = 8 >> VAR_7;", "const int VAR_10 = (2 << VAR_7) - 1;", "const int VAR_11 = VAR_0->VAR_11 >> VAR_7 + 1;", "const int VAR_12 = VAR_0->VAR_12 >> VAR_7 + 1;", "int VAR_13 = 0, VAR_14, VAR_15, VAR_16, VAR_17, VAR_18;", "uint8_t *ptr;", "if (VAR_0->quarter_sample) {", "VAR_5 /= 2;", "VAR_6 /= 2;", "}", "VAR_5 = ff_h263_round_chroma(VAR_5);", "VAR_6 = ff_h263_round_chroma(VAR_6);", "VAR_17 = VAR_5 & VAR_10;", "VAR_18 = VAR_6 & VAR_10;", "VAR_14 = VAR_0->mb_x * VAR_9 + (VAR_5 >> VAR_7 + 1);", "VAR_15 = VAR_0->mb_y * VAR_9 + (VAR_6 >> VAR_7 + 1);", "VAR_16 = VAR_15 * VAR_0->uvlinesize + VAR_14;", "ptr = VAR_3[1] + VAR_16;", "if (VAR_0->flags & CODEC_FLAG_EMU_EDGE) {", "if ((unsigned) VAR_14 > FFMAX(VAR_11 - (!!VAR_17) - VAR_9, 0) ||\n(unsigned) VAR_15 > FFMAX(VAR_12 - (!!VAR_18) - VAR_9, 0)) {", "VAR_0->vdsp.emulated_edge_mc(VAR_0->edge_emu_buffer, ptr, VAR_0->uvlinesize,\n9, 9, VAR_14, VAR_15, VAR_11, VAR_12);", "ptr = VAR_0->edge_emu_buffer;", "VAR_13 = 1;", "}", "}", "VAR_17 = (VAR_17 << 2) >> VAR_7;", "VAR_18 = (VAR_18 << 2) >> VAR_7;", "VAR_4[VAR_8](VAR_1, ptr, VAR_0->uvlinesize, VAR_9, VAR_17, VAR_18);", "ptr = VAR_3[2] + VAR_16;", "if (VAR_13) {", "VAR_0->vdsp.emulated_edge_mc(VAR_0->edge_emu_buffer, ptr, VAR_0->uvlinesize, 9, 9,\nVAR_14, VAR_15, VAR_11, VAR_12);", "ptr = VAR_0->edge_emu_buffer;", "}", "VAR_4[VAR_8](VAR_2, ptr, VAR_0->uvlinesize, VAR_9, VAR_17, VAR_18);", "}" ]
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16,922
static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) { int num; if (!s->config || !s->enable) { return 0; } /* Check range and alignment. */ if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { return 0; } if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { return 0; } if (CMD(max) > SVGA_FIFO_SIZE || CMD(min) >= SVGA_FIFO_SIZE || CMD(stop) >= SVGA_FIFO_SIZE || CMD(next_cmd) >= SVGA_FIFO_SIZE) { return 0; } if (CMD(max) < CMD(min) + 10 * 1024) { return 0; } num = CMD(next_cmd) - CMD(stop); if (num < 0) { num += CMD(max) - CMD(min); } return num >> 2; }
true
qemu
7e486f7577764a07aa35588e119903c80a5c30a2
static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) { int num; if (!s->config || !s->enable) { return 0; } if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { return 0; } if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { return 0; } if (CMD(max) > SVGA_FIFO_SIZE || CMD(min) >= SVGA_FIFO_SIZE || CMD(stop) >= SVGA_FIFO_SIZE || CMD(next_cmd) >= SVGA_FIFO_SIZE) { return 0; } if (CMD(max) < CMD(min) + 10 * 1024) { return 0; } num = CMD(next_cmd) - CMD(stop); if (num < 0) { num += CMD(max) - CMD(min); } return num >> 2; }
{ "code": [ " if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {", " if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {", " if (CMD(max) > SVGA_FIFO_SIZE ||", " CMD(min) >= SVGA_FIFO_SIZE ||", " CMD(stop) >= SVGA_FIFO_SIZE ||", " CMD(next_cmd) >= SVGA_FIFO_SIZE) {", " if (CMD(max) < CMD(min) + 10 * 1024) {", " num = CMD(next_cmd) - CMD(stop);", " num += CMD(max) - CMD(min);" ], "line_no": [ 19, 25, 31, 33, 35, 37, 43, 51, 55 ] }
static inline int FUNC_0(struct vmsvga_state_s *VAR_0) { int VAR_1; if (!VAR_0->config || !VAR_0->enable) { return 0; } if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { return 0; } if (CMD(min) < (uint8_t *) VAR_0->cmd->fifo - (uint8_t *) VAR_0->fifo) { return 0; } if (CMD(max) > SVGA_FIFO_SIZE || CMD(min) >= SVGA_FIFO_SIZE || CMD(stop) >= SVGA_FIFO_SIZE || CMD(next_cmd) >= SVGA_FIFO_SIZE) { return 0; } if (CMD(max) < CMD(min) + 10 * 1024) { return 0; } VAR_1 = CMD(next_cmd) - CMD(stop); if (VAR_1 < 0) { VAR_1 += CMD(max) - CMD(min); } return VAR_1 >> 2; }
[ "static inline int FUNC_0(struct vmsvga_state_s *VAR_0)\n{", "int VAR_1;", "if (!VAR_0->config || !VAR_0->enable) {", "return 0;", "}", "if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {", "return 0;", "}", "if (CMD(min) < (uint8_t *) VAR_0->cmd->fifo - (uint8_t *) VAR_0->fifo) {", "return 0;", "}", "if (CMD(max) > SVGA_FIFO_SIZE ||\nCMD(min) >= SVGA_FIFO_SIZE ||\nCMD(stop) >= SVGA_FIFO_SIZE ||\nCMD(next_cmd) >= SVGA_FIFO_SIZE) {", "return 0;", "}", "if (CMD(max) < CMD(min) + 10 * 1024) {", "return 0;", "}", "VAR_1 = CMD(next_cmd) - CMD(stop);", "if (VAR_1 < 0) {", "VAR_1 += CMD(max) - CMD(min);", "}", "return VAR_1 >> 2;", "}" ]
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[ [ 1, 3 ], [ 5 ], [ 9 ], [ 11 ], [ 13 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ], [ 27 ], [ 29 ], [ 31, 33, 35, 37 ], [ 39 ], [ 41 ], [ 43 ], [ 45 ], [ 47 ], [ 51 ], [ 53 ], [ 55 ], [ 57 ], [ 59 ], [ 61 ] ]
16,923
static void disas_sparc_insn(DisasContext * dc) { unsigned int insn, opc, rs1, rs2, rd; insn = ldl_code(dc->pc); opc = GET_FIELD(insn, 0, 1); rd = GET_FIELD(insn, 2, 6); switch (opc) { case 0: /* branches/sethi */ { unsigned int xop = GET_FIELD(insn, 7, 9); int32_t target; switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ { int cc; target = GET_FIELD_SP(insn, 0, 18); target = sign_extend(target, 18); target <<= 2; cc = GET_FIELD_SP(insn, 20, 21); if (cc == 0) do_branch(dc, target, insn, 0); else if (cc == 2) do_branch(dc, target, insn, 1); else goto jmp_insn; } case 0x3: /* V9 BPr */ { target = GET_FIELD_SP(insn, 0, 13) | (GET_FIELD_SP(insn, 20, 21) << 14); target = sign_extend(target, 16); target <<= 2; rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); do_branch_reg(dc, target, insn); goto jmp_insn; } case 0x5: /* V9 FBPcc */ { int cc = GET_FIELD_SP(insn, 20, 21); if (gen_trap_ifnofpu(dc)) goto jmp_insn; target = GET_FIELD_SP(insn, 0, 18); target = sign_extend(target, 19); target <<= 2; do_fbranch(dc, target, insn, cc); goto jmp_insn; } #endif case 0x2: /* BN+x */ { target = GET_FIELD(insn, 10, 31); target = sign_extend(target, 22); target <<= 2; do_branch(dc, target, insn, 0); goto jmp_insn; } case 0x6: /* FBN+x */ { if (gen_trap_ifnofpu(dc)) goto jmp_insn; target = GET_FIELD(insn, 10, 31); target = sign_extend(target, 22); target <<= 2; do_fbranch(dc, target, insn, 0); goto jmp_insn; } case 0x4: /* SETHI */ #define OPTIM #if defined(OPTIM) if (rd) { // nop #endif uint32_t value = GET_FIELD(insn, 10, 31); gen_movl_imm_T0(value << 10); gen_movl_T0_reg(rd); #if defined(OPTIM) } #endif break; case 0x0: /* UNIMPL */ default: } break; } break; case 1: /*CALL*/ { target_long target = GET_FIELDs(insn, 2, 31) << 2; #ifdef TARGET_SPARC64 if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T0_im(dc->pc); } else { gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); } #else gen_op_movl_T0_im(dc->pc); #endif gen_movl_T0_reg(15); target += dc->pc; gen_mov_pc_npc(dc); dc->npc = target; } goto jmp_insn; case 2: /* FPU & Logical Operations */ { unsigned int xop = GET_FIELD(insn, 7, 12); if (xop == 0x3a) { /* generate trap */ int cond; rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELD(insn, 25, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } cond = GET_FIELD(insn, 3, 6); if (cond == 0x8) { save_state(dc); gen_op_trap_T0(); } else if (cond != 0) { #ifdef TARGET_SPARC64 /* V9 icc/xcc */ int cc = GET_FIELD_SP(insn, 11, 12); flush_T2(dc); save_state(dc); if (cc == 0) gen_cond[0][cond](); else if (cc == 2) gen_cond[1][cond](); else #else flush_T2(dc); save_state(dc); gen_cond[0][cond](); #endif gen_op_trapcc_T0(); } gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; goto jmp_insn; } else if (xop == 0x28) { rs1 = GET_FIELD(insn, 13, 17); switch(rs1) { case 0: /* rdy */ #ifndef TARGET_SPARC64 case 0x01 ... 0x0e: /* undefined in the SPARCv8 manual, rdy on the microSPARC II */ case 0x0f: /* stbar in the SPARCv8 manual, rdy on the microSPARC II */ case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 manual, rdy on the microSPARC II */ #endif gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); gen_movl_T0_reg(rd); break; #ifdef TARGET_SPARC64 case 0x2: /* V9 rdccr */ gen_op_rdccr(); gen_movl_T0_reg(rd); break; case 0x3: /* V9 rdasi */ gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); gen_movl_T0_reg(rd); break; case 0x4: /* V9 rdtick */ gen_op_rdtick(); gen_movl_T0_reg(rd); break; case 0x5: /* V9 rdpc */ if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T0_im(dc->pc); } else { gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); } gen_movl_T0_reg(rd); break; case 0x6: /* V9 rdfprs */ gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); gen_movl_T0_reg(rd); break; case 0xf: /* V9 membar */ break; /* no effect */ case 0x13: /* Graphics Status */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); gen_movl_T0_reg(rd); break; case 0x17: /* Tick compare */ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); gen_movl_T0_reg(rd); break; case 0x18: /* System tick */ gen_op_rdtick(); // XXX gen_movl_T0_reg(rd); break; case 0x19: /* System tick compare */ gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); gen_movl_T0_reg(rd); break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ case 0x14: /* Softint set, WO */ case 0x15: /* Softint clear, WO */ case 0x16: /* Softint write */ #endif default: } #if !defined(CONFIG_USER_ONLY) #ifndef TARGET_SPARC64 } else if (xop == 0x29) { /* rdpsr / V9 unimp */ if (!supervisor(dc)) goto priv_insn; gen_op_rdpsr(); gen_movl_T0_reg(rd); break; #endif } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) goto priv_insn; #ifdef TARGET_SPARC64 rs1 = GET_FIELD(insn, 13, 17); switch (rs1) { case 0: // tpc gen_op_rdtpc(); break; case 1: // tnpc gen_op_rdtnpc(); break; case 2: // tstate gen_op_rdtstate(); break; case 3: // tt gen_op_rdtt(); break; case 4: // tick gen_op_rdtick(); break; case 5: // tba gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); break; case 6: // pstate gen_op_rdpstate(); break; case 7: // tl gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); break; case 8: // pil gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp gen_op_rdcwp(); break; case 10: // cansave gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); break; case 11: // canrestore gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); break; case 12: // cleanwin gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); break; case 13: // otherwin gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); break; case 14: // wstate gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); break; case 31: // ver gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); break; case 15: // fq default: } #else gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); #endif gen_movl_T0_reg(rd); break; } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 gen_op_flushw(); #else if (!supervisor(dc)) goto priv_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); gen_movl_T0_reg(rd); #endif break; #endif } else if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); switch (xop) { case 0x1: /* fmovs */ gen_op_load_fpr_FT0(rs2); gen_op_store_FT0_fpr(rd); break; case 0x5: /* fnegs */ gen_op_load_fpr_FT1(rs2); gen_op_fnegs(); gen_op_store_FT0_fpr(rd); break; case 0x9: /* fabss */ gen_op_load_fpr_FT1(rs2); gen_op_fabss(); gen_op_store_FT0_fpr(rd); break; case 0x29: /* fsqrts */ gen_op_load_fpr_FT1(rs2); gen_op_fsqrts(); gen_op_store_FT0_fpr(rd); break; case 0x2a: /* fsqrtd */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsqrtd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x2b: /* fsqrtq */ goto nfpu_insn; case 0x41: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fadds(); gen_op_store_FT0_fpr(rd); break; case 0x42: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_faddd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x43: /* faddq */ goto nfpu_insn; case 0x45: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsubs(); gen_op_store_FT0_fpr(rd); break; case 0x46: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsubd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x47: /* fsubq */ goto nfpu_insn; case 0x49: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fmuls(); gen_op_store_FT0_fpr(rd); break; case 0x4a: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fmuld(); gen_op_store_DT0_fpr(rd); break; case 0x4b: /* fmulq */ goto nfpu_insn; case 0x4d: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fdivs(); gen_op_store_FT0_fpr(rd); break; case 0x4e: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdivd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x4f: /* fdivq */ goto nfpu_insn; case 0x69: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsmuld(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6e: /* fdmulq */ goto nfpu_insn; case 0xc4: gen_op_load_fpr_FT1(rs2); gen_op_fitos(); gen_op_store_FT0_fpr(rd); break; case 0xc6: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtos(); gen_op_store_FT0_fpr(rd); break; case 0xc7: /* fqtos */ goto nfpu_insn; case 0xc8: gen_op_load_fpr_FT1(rs2); gen_op_fitod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xc9: gen_op_load_fpr_FT1(rs2); gen_op_fstod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xcb: /* fqtod */ goto nfpu_insn; case 0xcc: /* fitoq */ goto nfpu_insn; case 0xcd: /* fstoq */ goto nfpu_insn; case 0xce: /* fdtoq */ goto nfpu_insn; case 0xd1: gen_op_load_fpr_FT1(rs2); gen_op_fstoi(); gen_op_store_FT0_fpr(rd); break; case 0xd2: gen_op_load_fpr_DT1(rs2); gen_op_fdtoi(); gen_op_store_FT0_fpr(rd); break; case 0xd3: /* fqtoi */ goto nfpu_insn; #ifdef TARGET_SPARC64 case 0x2: /* V9 fmovd */ gen_op_load_fpr_DT0(DFPREG(rs2)); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6: /* V9 fnegd */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fnegd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xa: /* V9 fabsd */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fabsd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x81: /* V9 fstox */ gen_op_load_fpr_FT1(rs2); gen_op_fstox(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x82: /* V9 fdtox */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtox(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x84: /* V9 fxtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fxtos(); gen_op_store_FT0_fpr(rd); break; case 0x88: /* V9 fxtod */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fxtod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x3: /* V9 fmovq */ case 0x7: /* V9 fnegq */ case 0xb: /* V9 fabsq */ case 0x83: /* V9 fqtox */ case 0x8c: /* V9 fxtoq */ goto nfpu_insn; #endif default: } } else if (xop == 0x35) { /* FPU Operations */ #ifdef TARGET_SPARC64 int cond; #endif if (gen_trap_ifnofpu(dc)) goto jmp_insn; rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); #ifdef TARGET_SPARC64 if ((xop & 0x11f) == 0x005) { // V9 fmovsr cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); flush_T2(dc); gen_cond_reg(cond); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); gen_cond_reg(cond); gen_op_fmovs_cc(); gen_op_store_DT0_fpr(rd); break; } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr goto nfpu_insn; } #endif switch (xop) { #ifdef TARGET_SPARC64 case 0x001: /* V9 fmovscc %fcc0 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[0][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x002: /* V9 fmovdcc %fcc0 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[0][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x003: /* V9 fmovqcc %fcc0 */ goto nfpu_insn; case 0x041: /* V9 fmovscc %fcc1 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[1][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x042: /* V9 fmovdcc %fcc1 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[1][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x043: /* V9 fmovqcc %fcc1 */ goto nfpu_insn; case 0x081: /* V9 fmovscc %fcc2 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[2][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x082: /* V9 fmovdcc %fcc2 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[2][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x083: /* V9 fmovqcc %fcc2 */ goto nfpu_insn; case 0x0c1: /* V9 fmovscc %fcc3 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[3][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x0c2: /* V9 fmovdcc %fcc3 */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[3][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x0c3: /* V9 fmovqcc %fcc3 */ goto nfpu_insn; case 0x101: /* V9 fmovscc %icc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_cond[0][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x102: /* V9 fmovdcc %icc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_cond[0][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x103: /* V9 fmovqcc %icc */ goto nfpu_insn; case 0x181: /* V9 fmovscc %xcc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_cond[1][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x182: /* V9 fmovdcc %xcc */ cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_cond[1][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x183: /* V9 fmovqcc %xcc */ goto nfpu_insn; #endif case 0x51: /* V9 %fcc */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 gen_fcmps[rd & 3](); #else gen_op_fcmps(); #endif break; case 0x52: /* V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 gen_fcmpd[rd & 3](); #else gen_op_fcmpd(); #endif break; case 0x53: /* fcmpq */ goto nfpu_insn; case 0x55: /* fcmpes, V9 %fcc */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 gen_fcmps[rd & 3](); #else gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */ #endif break; case 0x56: /* fcmped, V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 gen_fcmpd[rd & 3](); #else gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */ #endif break; case 0x57: /* fcmpeq */ goto nfpu_insn; default: } #if defined(OPTIM) } else if (xop == 0x2) { // clr/mov shortcut rs1 = GET_FIELD(insn, 13, 17); if (rs1 == 0) { // or %g0, x, y -> mov T1, x; mov y, T1 if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } gen_movl_T1_reg(rd); } else { gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ // or x, #0, y -> mov T1, x; mov y, T1 rs2 = GET_FIELDs(insn, 19, 31); if (rs2 != 0) { gen_movl_simm_T1(rs2); gen_op_or_T1_T0(); } } else { /* register */ // or x, %g0, y -> mov T1, x; mov y, T1 rs2 = GET_FIELD(insn, 27, 31); if (rs2 != 0) { gen_movl_reg_T1(rs2); gen_op_or_T1_T0(); } } gen_movl_T0_reg(rd); } #endif #ifdef TARGET_SPARC64 } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } gen_op_sll(); gen_movl_T0_reg(rd); } else if (xop == 0x26) { /* srl, V9 srlx */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_srlx(); else gen_op_srl(); gen_movl_T0_reg(rd); } else if (xop == 0x27) { /* sra, V9 srax */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_srax(); else gen_op_sra(); gen_movl_T0_reg(rd); #endif } else if (xop < 0x36) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (xop < 0x20) { switch (xop & ~0x10) { case 0x0: if (xop & 0x10) gen_op_add_T1_T0_cc(); else gen_op_add_T1_T0(); break; case 0x1: gen_op_and_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x2: gen_op_or_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x3: gen_op_xor_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x4: if (xop & 0x10) gen_op_sub_T1_T0_cc(); else gen_op_sub_T1_T0(); break; case 0x5: gen_op_andn_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x6: gen_op_orn_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x7: gen_op_xnor_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x8: if (xop & 0x10) gen_op_addx_T1_T0_cc(); else gen_op_addx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0x9: /* V9 mulx */ gen_op_mulx_T1_T0(); break; #endif case 0xa: gen_op_umul_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0xb: gen_op_smul_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0xc: if (xop & 0x10) gen_op_subx_T1_T0_cc(); else gen_op_subx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ gen_op_udivx_T1_T0(); break; #endif case 0xe: gen_op_udiv_T1_T0(); if (xop & 0x10) gen_op_div_cc(); break; case 0xf: gen_op_sdiv_T1_T0(); if (xop & 0x10) gen_op_div_cc(); break; default: } gen_movl_T0_reg(rd); } else { switch (xop) { case 0x20: /* taddcc */ gen_op_tadd_T1_T0_cc(); gen_movl_T0_reg(rd); break; case 0x21: /* tsubcc */ gen_op_tsub_T1_T0_cc(); gen_movl_T0_reg(rd); break; case 0x22: /* taddcctv */ gen_op_tadd_T1_T0_ccTV(); gen_movl_T0_reg(rd); break; case 0x23: /* tsubcctv */ gen_op_tsub_T1_T0_ccTV(); gen_movl_T0_reg(rd); break; case 0x24: /* mulscc */ gen_op_mulscc_T1_T0(); gen_movl_T0_reg(rd); break; #ifndef TARGET_SPARC64 case 0x25: /* sll */ gen_op_sll(); gen_movl_T0_reg(rd); break; case 0x26: /* srl */ gen_op_srl(); gen_movl_T0_reg(rd); break; case 0x27: /* sra */ gen_op_sra(); gen_movl_T0_reg(rd); break; #endif case 0x30: { switch(rd) { case 0: /* wry */ gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); break; #ifndef TARGET_SPARC64 case 0x01 ... 0x0f: /* undefined in the SPARCv8 manual, nop on the microSPARC II */ case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */ break; #else case 0x2: /* V9 wrccr */ gen_op_wrccr(); break; case 0x3: /* V9 wrasi */ gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); break; case 0x6: /* V9 wrfprs */ gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); break; case 0xf: /* V9 sir, nop if user */ #if !defined(CONFIG_USER_ONLY) if (supervisor(dc)) gen_op_sir(); #endif break; case 0x13: /* Graphics Status */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); break; case 0x18: /* System tick */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); break; case 0x19: /* System tick compare */ #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ case 0x14: /* Softint set */ case 0x15: /* Softint clear */ case 0x16: /* Softint write */ #endif default: } } break; #if !defined(CONFIG_USER_ONLY) case 0x31: /* wrpsr, V9 saved, restored */ { if (!supervisor(dc)) goto priv_insn; #ifdef TARGET_SPARC64 switch (rd) { case 0: gen_op_saved(); break; case 1: gen_op_restored(); break; default: } #else gen_op_xor_T1_T0(); gen_op_wrpsr(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; #endif } break; case 0x32: /* wrwim, V9 wrpr */ { if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); #ifdef TARGET_SPARC64 switch (rd) { case 0: // tpc gen_op_wrtpc(); break; case 1: // tnpc gen_op_wrtnpc(); break; case 2: // tstate gen_op_wrtstate(); break; case 3: // tt gen_op_wrtt(); break; case 4: // tick gen_op_wrtick(); break; case 5: // tba gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); break; case 6: // pstate gen_op_wrpstate(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; break; case 7: // tl gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); break; case 8: // pil gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp gen_op_wrcwp(); break; case 10: // cansave gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); break; case 11: // canrestore gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); break; case 12: // cleanwin gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); break; case 13: // otherwin gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); break; case 14: // wstate gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); break; default: } #else gen_op_wrwim(); #endif } break; #ifndef TARGET_SPARC64 case 0x33: /* wrtbr, V9 unimp */ { if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); } break; #endif #endif #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ { int cc = GET_FIELD_SP(insn, 11, 12); int cond = GET_FIELD_SP(insn, 14, 17); if (IS_IMM) { /* immediate */ rs2 = GET_FIELD_SPs(insn, 0, 10); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_movl_reg_T0(rd); flush_T2(dc); if (insn & (1 << 18)) { if (cc == 0) gen_cond[0][cond](); else if (cc == 2) gen_cond[1][cond](); else } else { gen_fcond[cc][cond](); } gen_op_mov_cc(); gen_movl_T0_reg(rd); break; } case 0x2d: /* V9 sdivx */ gen_op_sdivx_T1_T0(); gen_movl_T0_reg(rd); break; case 0x2e: /* V9 popc */ { if (IS_IMM) { /* immediate */ rs2 = GET_FIELD_SPs(insn, 0, 12); gen_movl_simm_T1(rs2); // XXX optimize: popc(constant) } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_op_popc(); gen_movl_T0_reg(rd); } case 0x2f: /* V9 movr */ { int cond = GET_FIELD_SP(insn, 10, 12); rs1 = GET_FIELD(insn, 13, 17); flush_T2(dc); gen_movl_reg_T0(rs1); gen_cond_reg(cond); if (IS_IMM) { /* immediate */ rs2 = GET_FIELD_SPs(insn, 0, 10); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_movl_reg_T0(rd); gen_op_mov_cc(); gen_movl_T0_reg(rd); break; } case 0x36: /* UltraSparc shutdown, VIS */ { int opf = GET_FIELD_SP(insn, 5, 13); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); switch (opf) { case 0x018: /* VIS I alignaddr */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_alignaddr(); gen_movl_T0_reg(rd); break; case 0x01a: /* VIS I alignaddrl */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; // XXX break; case 0x048: /* VIS I faligndata */ if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_faligndata(); gen_op_store_DT0_fpr(rd); break; default: } break; } #endif default: } } } else if (xop == 0x36 || xop == 0x37) { /* CPop1 & CPop2, V9 impdep1 & impdep2 */ #ifdef TARGET_SPARC64 #else goto ncp_insn; #endif #ifdef TARGET_SPARC64 } else if (xop == 0x39) { /* V9 return */ rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } gen_op_restore(); gen_mov_pc_npc(dc); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; goto jmp_insn; #endif } else { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } switch (xop) { case 0x38: /* jmpl */ { if (rd != 0) { #ifdef TARGET_SPARC64 if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T1_im(dc->pc); } else { gen_op_movq_T1_im64(dc->pc >> 32, dc->pc); } #else gen_op_movl_T1_im(dc->pc); #endif gen_movl_T1_reg(rd); } gen_mov_pc_npc(dc); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; } goto jmp_insn; #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: /* rett, V9 return */ { if (!supervisor(dc)) goto priv_insn; gen_mov_pc_npc(dc); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; gen_op_rett(); } goto jmp_insn; #endif case 0x3b: /* flush */ gen_op_flush_T0(); break; case 0x3c: /* save */ save_state(dc); gen_op_save(); gen_movl_T0_reg(rd); break; case 0x3d: /* restore */ save_state(dc); gen_op_restore(); gen_movl_T0_reg(rd); break; #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) case 0x3e: /* V9 done/retry */ { switch (rd) { case 0: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; gen_op_done(); goto jmp_insn; case 1: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; gen_op_retry(); goto jmp_insn; default: } } break; #endif default: } } break; } break; case 3: /* load/store instructions */ { unsigned int xop = GET_FIELD(insn, 7, 12); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \ (xop > 0x17 && xop < 0x1d ) || \ (xop > 0x2c && xop < 0x33) || xop == 0x1f) { switch (xop) { case 0x0: /* load word */ gen_op_ldst(ld); break; case 0x1: /* load unsigned byte */ gen_op_ldst(ldub); break; case 0x2: /* load unsigned halfword */ gen_op_ldst(lduh); break; case 0x3: /* load double word */ gen_op_ldst(ldd); gen_movl_T0_reg(rd + 1); break; case 0x9: /* load signed byte */ gen_op_ldst(ldsb); break; case 0xa: /* load signed halfword */ gen_op_ldst(ldsh); break; case 0xd: /* ldstub -- XXX: should be atomically */ gen_op_ldst(ldstub); break; case 0x0f: /* swap register with memory. Also atomically */ gen_movl_reg_T1(rd); gen_op_ldst(swap); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x10: /* load word alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_lda(insn, 1, 4, 0); break; case 0x11: /* load unsigned byte alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_lduba(insn, 1, 1, 0); break; case 0x12: /* load unsigned halfword alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_lduha(insn, 1, 2, 0); break; case 0x13: /* load double word alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldda(insn, 1, 8, 0); gen_movl_T0_reg(rd + 1); break; case 0x19: /* load signed byte alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldsba(insn, 1, 1, 1); break; case 0x1a: /* load signed halfword alternate */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldsha(insn, 1, 2 ,1); break; case 0x1d: /* ldstuba -- XXX: should be atomically */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldstuba(insn, 1, 1, 0); break; case 0x1f: /* swap reg with alt. memory. Also atomically */ #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_movl_reg_T1(rd); gen_op_swapa(insn, 1, 4, 0); break; #ifndef TARGET_SPARC64 case 0x30: /* ldc */ case 0x31: /* ldcsr */ case 0x33: /* lddc */ case 0x34: /* stc */ case 0x35: /* stcsr */ case 0x36: /* stdcq */ case 0x37: /* stdc */ goto ncp_insn; break; /* avoid warnings */ (void) &gen_op_stfa; (void) &gen_op_stdfa; (void) &gen_op_ldfa; (void) &gen_op_lddfa; #else #if !defined(CONFIG_USER_ONLY) (void) &gen_op_cas; (void) &gen_op_casx; #endif #endif #endif #ifdef TARGET_SPARC64 case 0x08: /* V9 ldsw */ gen_op_ldst(ldsw); break; case 0x0b: /* V9 ldx */ gen_op_ldst(ldx); break; case 0x18: /* V9 ldswa */ gen_op_ldswa(insn, 1, 4, 1); break; case 0x1b: /* V9 ldxa */ gen_op_ldxa(insn, 1, 8, 0); break; case 0x2d: /* V9 prefetch, no effect */ goto skip_move; case 0x30: /* V9 ldfa */ gen_op_ldfa(insn, 1, 8, 0); // XXX break; case 0x33: /* V9 lddfa */ gen_op_lddfa(insn, 1, 8, 0); // XXX break; case 0x3d: /* V9 prefetcha, no effect */ goto skip_move; case 0x32: /* V9 ldqfa */ goto nfpu_insn; #endif default: } gen_movl_T1_reg(rd); #ifdef TARGET_SPARC64 skip_move: ; #endif } else if (xop >= 0x20 && xop < 0x24) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (xop) { case 0x20: /* load fpreg */ gen_op_ldst(ldf); gen_op_store_FT0_fpr(rd); break; case 0x21: /* load fsr */ gen_op_ldst(ldf); gen_op_ldfsr(); break; case 0x22: /* load quad fpreg */ goto nfpu_insn; case 0x23: /* load double fpreg */ gen_op_ldst(lddf); gen_op_store_DT0_fpr(DFPREG(rd)); break; default: } } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ xop == 0xe || xop == 0x1e) { gen_movl_reg_T1(rd); switch (xop) { case 0x4: gen_op_ldst(st); break; case 0x5: gen_op_ldst(stb); break; case 0x6: gen_op_ldst(sth); break; case 0x7: flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_op_ldst(std); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_sta(insn, 0, 4, 0); break; case 0x15: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_stba(insn, 0, 1, 0); break; case 0x16: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_stha(insn, 0, 2, 0); break; case 0x17: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_op_stda(insn, 0, 8, 0); break; #endif #ifdef TARGET_SPARC64 case 0x0e: /* V9 stx */ gen_op_ldst(stx); break; case 0x1e: /* V9 stxa */ gen_op_stxa(insn, 0, 8, 0); // XXX break; #endif default: } } else if (xop > 0x23 && xop < 0x28) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (xop) { case 0x24: gen_op_load_fpr_FT0(rd); gen_op_ldst(stf); break; case 0x25: /* stfsr, V9 stxfsr */ gen_op_stfsr(); gen_op_ldst(stf); break; case 0x26: /* stdfq */ goto nfpu_insn; case 0x27: gen_op_load_fpr_DT0(DFPREG(rd)); gen_op_ldst(stdf); break; default: } } else if (xop > 0x33 && xop < 0x3f) { #ifdef TARGET_SPARC64 switch (xop) { case 0x34: /* V9 stfa */ gen_op_stfa(insn, 0, 0, 0); // XXX break; case 0x37: /* V9 stdfa */ gen_op_stdfa(insn, 0, 0, 0); // XXX break; case 0x3c: /* V9 casa */ gen_op_casa(insn, 0, 4, 0); // XXX break; case 0x3e: /* V9 casxa */ gen_op_casxa(insn, 0, 8, 0); // XXX break; case 0x36: /* V9 stqfa */ goto nfpu_insn; default: } #else #endif } else } break; } /* default case for non jump instructions */ if (dc->npc == DYNAMIC_PC) { dc->pc = DYNAMIC_PC; gen_op_next_insn(); } else if (dc->npc == JUMP_PC) { /* we can do a static jump */ gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]); dc->is_br = 1; } else { dc->pc = dc->npc; dc->npc = dc->npc + 4; } jmp_insn: return; illegal_insn: save_state(dc); gen_op_exception(TT_ILL_INSN); dc->is_br = 1; return; #if !defined(CONFIG_USER_ONLY) priv_insn: save_state(dc); gen_op_exception(TT_PRIV_INSN); dc->is_br = 1; return; #endif nfpu_insn: save_state(dc); gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); dc->is_br = 1; return; #ifndef TARGET_SPARC64 ncp_insn: save_state(dc); gen_op_exception(TT_NCP_INSN); dc->is_br = 1; return; #endif }
true
qemu
d4218d996d2274f4136b8bd22e946bf56f050c9e
static void disas_sparc_insn(DisasContext * dc) { unsigned int insn, opc, rs1, rs2, rd; insn = ldl_code(dc->pc); opc = GET_FIELD(insn, 0, 1); rd = GET_FIELD(insn, 2, 6); switch (opc) { case 0: { unsigned int xop = GET_FIELD(insn, 7, 9); int32_t target; switch (xop) { #ifdef TARGET_SPARC64 case 0x1: { int cc; target = GET_FIELD_SP(insn, 0, 18); target = sign_extend(target, 18); target <<= 2; cc = GET_FIELD_SP(insn, 20, 21); if (cc == 0) do_branch(dc, target, insn, 0); else if (cc == 2) do_branch(dc, target, insn, 1); else goto jmp_insn; } case 0x3: { target = GET_FIELD_SP(insn, 0, 13) | (GET_FIELD_SP(insn, 20, 21) << 14); target = sign_extend(target, 16); target <<= 2; rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); do_branch_reg(dc, target, insn); goto jmp_insn; } case 0x5: { int cc = GET_FIELD_SP(insn, 20, 21); if (gen_trap_ifnofpu(dc)) goto jmp_insn; target = GET_FIELD_SP(insn, 0, 18); target = sign_extend(target, 19); target <<= 2; do_fbranch(dc, target, insn, cc); goto jmp_insn; } #endif case 0x2: { target = GET_FIELD(insn, 10, 31); target = sign_extend(target, 22); target <<= 2; do_branch(dc, target, insn, 0); goto jmp_insn; } case 0x6: { if (gen_trap_ifnofpu(dc)) goto jmp_insn; target = GET_FIELD(insn, 10, 31); target = sign_extend(target, 22); target <<= 2; do_fbranch(dc, target, insn, 0); goto jmp_insn; } case 0x4: #define OPTIM #if defined(OPTIM) if (rd) { #endif uint32_t value = GET_FIELD(insn, 10, 31); gen_movl_imm_T0(value << 10); gen_movl_T0_reg(rd); #if defined(OPTIM) } #endif break; case 0x0: default: } break; } break; case 1: { target_long target = GET_FIELDs(insn, 2, 31) << 2; #ifdef TARGET_SPARC64 if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T0_im(dc->pc); } else { gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); } #else gen_op_movl_T0_im(dc->pc); #endif gen_movl_T0_reg(15); target += dc->pc; gen_mov_pc_npc(dc); dc->npc = target; } goto jmp_insn; case 2: { unsigned int xop = GET_FIELD(insn, 7, 12); if (xop == 0x3a) { int cond; rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELD(insn, 25, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } cond = GET_FIELD(insn, 3, 6); if (cond == 0x8) { save_state(dc); gen_op_trap_T0(); } else if (cond != 0) { #ifdef TARGET_SPARC64 int cc = GET_FIELD_SP(insn, 11, 12); flush_T2(dc); save_state(dc); if (cc == 0) gen_cond[0][cond](); else if (cc == 2) gen_cond[1][cond](); else #else flush_T2(dc); save_state(dc); gen_cond[0][cond](); #endif gen_op_trapcc_T0(); } gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; goto jmp_insn; } else if (xop == 0x28) { rs1 = GET_FIELD(insn, 13, 17); switch(rs1) { case 0: #ifndef TARGET_SPARC64 case 0x01 ... 0x0e: case 0x0f: case 0x10 ... 0x1f: #endif gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); gen_movl_T0_reg(rd); break; #ifdef TARGET_SPARC64 case 0x2: gen_op_rdccr(); gen_movl_T0_reg(rd); break; case 0x3: gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); gen_movl_T0_reg(rd); break; case 0x4: gen_op_rdtick(); gen_movl_T0_reg(rd); break; case 0x5: if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T0_im(dc->pc); } else { gen_op_movq_T0_im64(dc->pc >> 32, dc->pc); } gen_movl_T0_reg(rd); break; case 0x6: gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); gen_movl_T0_reg(rd); break; case 0xf: break; case 0x13: if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); gen_movl_T0_reg(rd); break; case 0x17: gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); gen_movl_T0_reg(rd); break; case 0x18: gen_op_rdtick(); gen_movl_T0_reg(rd); break; case 0x19: gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); gen_movl_T0_reg(rd); break; case 0x10: case 0x11: case 0x12: case 0x14: case 0x15: case 0x16: #endif default: } #if !defined(CONFIG_USER_ONLY) #ifndef TARGET_SPARC64 } else if (xop == 0x29) { if (!supervisor(dc)) goto priv_insn; gen_op_rdpsr(); gen_movl_T0_reg(rd); break; #endif } else if (xop == 0x2a) { if (!supervisor(dc)) goto priv_insn; #ifdef TARGET_SPARC64 rs1 = GET_FIELD(insn, 13, 17); switch (rs1) { case 0: gen_op_rdtpc(); break; case 1: gen_op_rdtnpc(); break; case 2: gen_op_rdtstate(); break; case 3: gen_op_rdtt(); break; case 4: gen_op_rdtick(); break; case 5: gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); break; case 6: gen_op_rdpstate(); break; case 7: gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); break; case 8: gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); break; case 9: gen_op_rdcwp(); break; case 10: gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); break; case 11: gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); break; case 12: gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); break; case 13: gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); break; case 14: gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); break; case 31: gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); break; case 15: default: } #else gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); #endif gen_movl_T0_reg(rd); break; } else if (xop == 0x2b) { #ifdef TARGET_SPARC64 gen_op_flushw(); #else if (!supervisor(dc)) goto priv_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); gen_movl_T0_reg(rd); #endif break; #endif } else if (xop == 0x34) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); switch (xop) { case 0x1: gen_op_load_fpr_FT0(rs2); gen_op_store_FT0_fpr(rd); break; case 0x5: gen_op_load_fpr_FT1(rs2); gen_op_fnegs(); gen_op_store_FT0_fpr(rd); break; case 0x9: gen_op_load_fpr_FT1(rs2); gen_op_fabss(); gen_op_store_FT0_fpr(rd); break; case 0x29: gen_op_load_fpr_FT1(rs2); gen_op_fsqrts(); gen_op_store_FT0_fpr(rd); break; case 0x2a: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsqrtd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x2b: goto nfpu_insn; case 0x41: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fadds(); gen_op_store_FT0_fpr(rd); break; case 0x42: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_faddd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x43: goto nfpu_insn; case 0x45: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsubs(); gen_op_store_FT0_fpr(rd); break; case 0x46: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsubd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x47: goto nfpu_insn; case 0x49: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fmuls(); gen_op_store_FT0_fpr(rd); break; case 0x4a: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fmuld(); gen_op_store_DT0_fpr(rd); break; case 0x4b: goto nfpu_insn; case 0x4d: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fdivs(); gen_op_store_FT0_fpr(rd); break; case 0x4e: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdivd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x4f: goto nfpu_insn; case 0x69: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsmuld(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6e: goto nfpu_insn; case 0xc4: gen_op_load_fpr_FT1(rs2); gen_op_fitos(); gen_op_store_FT0_fpr(rd); break; case 0xc6: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtos(); gen_op_store_FT0_fpr(rd); break; case 0xc7: goto nfpu_insn; case 0xc8: gen_op_load_fpr_FT1(rs2); gen_op_fitod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xc9: gen_op_load_fpr_FT1(rs2); gen_op_fstod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xcb: goto nfpu_insn; case 0xcc: goto nfpu_insn; case 0xcd: goto nfpu_insn; case 0xce: goto nfpu_insn; case 0xd1: gen_op_load_fpr_FT1(rs2); gen_op_fstoi(); gen_op_store_FT0_fpr(rd); break; case 0xd2: gen_op_load_fpr_DT1(rs2); gen_op_fdtoi(); gen_op_store_FT0_fpr(rd); break; case 0xd3: goto nfpu_insn; #ifdef TARGET_SPARC64 case 0x2: gen_op_load_fpr_DT0(DFPREG(rs2)); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fnegd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xa: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fabsd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x81: gen_op_load_fpr_FT1(rs2); gen_op_fstox(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x82: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtox(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x84: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fxtos(); gen_op_store_FT0_fpr(rd); break; case 0x88: gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fxtod(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x3: case 0x7: case 0xb: case 0x83: case 0x8c: goto nfpu_insn; #endif default: } } else if (xop == 0x35) { #ifdef TARGET_SPARC64 int cond; #endif if (gen_trap_ifnofpu(dc)) goto jmp_insn; rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); #ifdef TARGET_SPARC64 if ((xop & 0x11f) == 0x005) { cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); flush_T2(dc); gen_cond_reg(cond); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; } else if ((xop & 0x11f) == 0x006) { cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); gen_cond_reg(cond); gen_op_fmovs_cc(); gen_op_store_DT0_fpr(rd); break; } else if ((xop & 0x11f) == 0x007) { goto nfpu_insn; } #endif switch (xop) { #ifdef TARGET_SPARC64 case 0x001: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[0][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x002: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[0][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x003: goto nfpu_insn; case 0x041: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[1][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x042: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[1][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x043: goto nfpu_insn; case 0x081: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[2][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x082: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[2][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x083: goto nfpu_insn; case 0x0c1: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_fcond[3][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x0c2: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_fcond[3][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x0c3: goto nfpu_insn; case 0x101: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_cond[0][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x102: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_cond[0][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x103: goto nfpu_insn; case 0x181: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT1(rs2); flush_T2(dc); gen_cond[1][cond](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(rd); break; case 0x182: cond = GET_FIELD_SP(insn, 14, 17); gen_op_load_fpr_DT0(rd); gen_op_load_fpr_DT1(rs2); flush_T2(dc); gen_cond[1][cond](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(rd); break; case 0x183: goto nfpu_insn; #endif case 0x51: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 gen_fcmps[rd & 3](); #else gen_op_fcmps(); #endif break; case 0x52: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 gen_fcmpd[rd & 3](); #else gen_op_fcmpd(); #endif break; case 0x53: goto nfpu_insn; case 0x55: gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); #ifdef TARGET_SPARC64 gen_fcmps[rd & 3](); #else gen_op_fcmps(); #endif break; case 0x56: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); #ifdef TARGET_SPARC64 gen_fcmpd[rd & 3](); #else gen_op_fcmpd(); #endif break; case 0x57: goto nfpu_insn; default: } #if defined(OPTIM) } else if (xop == 0x2) { rs1 = GET_FIELD(insn, 13, 17); if (rs1 == 0) { if (IS_IMM) { rs2 = GET_FIELDs(insn, 19, 31); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } gen_movl_T1_reg(rd); } else { gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 19, 31); if (rs2 != 0) { gen_movl_simm_T1(rs2); gen_op_or_T1_T0(); } } else { rs2 = GET_FIELD(insn, 27, 31); if (rs2 != 0) { gen_movl_reg_T1(rs2); gen_op_or_T1_T0(); } } gen_movl_T0_reg(rd); } #endif #ifdef TARGET_SPARC64 } else if (xop == 0x25) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } gen_op_sll(); gen_movl_T0_reg(rd); } else if (xop == 0x26) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_srlx(); else gen_op_srl(); gen_movl_T0_reg(rd); } else if (xop == 0x27) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 20, 31); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (insn & (1 << 12)) gen_op_srax(); else gen_op_sra(); gen_movl_T0_reg(rd); #endif } else if (xop < 0x36) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 19, 31); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); } if (xop < 0x20) { switch (xop & ~0x10) { case 0x0: if (xop & 0x10) gen_op_add_T1_T0_cc(); else gen_op_add_T1_T0(); break; case 0x1: gen_op_and_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x2: gen_op_or_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x3: gen_op_xor_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x4: if (xop & 0x10) gen_op_sub_T1_T0_cc(); else gen_op_sub_T1_T0(); break; case 0x5: gen_op_andn_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x6: gen_op_orn_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x7: gen_op_xnor_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x8: if (xop & 0x10) gen_op_addx_T1_T0_cc(); else gen_op_addx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0x9: gen_op_mulx_T1_T0(); break; #endif case 0xa: gen_op_umul_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0xb: gen_op_smul_T1_T0(); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0xc: if (xop & 0x10) gen_op_subx_T1_T0_cc(); else gen_op_subx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0xd: gen_op_udivx_T1_T0(); break; #endif case 0xe: gen_op_udiv_T1_T0(); if (xop & 0x10) gen_op_div_cc(); break; case 0xf: gen_op_sdiv_T1_T0(); if (xop & 0x10) gen_op_div_cc(); break; default: } gen_movl_T0_reg(rd); } else { switch (xop) { case 0x20: gen_op_tadd_T1_T0_cc(); gen_movl_T0_reg(rd); break; case 0x21: gen_op_tsub_T1_T0_cc(); gen_movl_T0_reg(rd); break; case 0x22: gen_op_tadd_T1_T0_ccTV(); gen_movl_T0_reg(rd); break; case 0x23: gen_op_tsub_T1_T0_ccTV(); gen_movl_T0_reg(rd); break; case 0x24: gen_op_mulscc_T1_T0(); gen_movl_T0_reg(rd); break; #ifndef TARGET_SPARC64 case 0x25: gen_op_sll(); gen_movl_T0_reg(rd); break; case 0x26: gen_op_srl(); gen_movl_T0_reg(rd); break; case 0x27: gen_op_sra(); gen_movl_T0_reg(rd); break; #endif case 0x30: { switch(rd) { case 0: gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); break; #ifndef TARGET_SPARC64 case 0x01 ... 0x0f: case 0x10 ... 0x1f: break; #else case 0x2: gen_op_wrccr(); break; case 0x3: gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); break; case 0x6: gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); break; case 0xf: #if !defined(CONFIG_USER_ONLY) if (supervisor(dc)) gen_op_sir(); #endif break; case 0x13: if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); break; case 0x17: #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); break; case 0x18: #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); break; case 0x19: #if !defined(CONFIG_USER_ONLY) if (!supervisor(dc)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); break; case 0x10: case 0x11: case 0x12: case 0x14: case 0x15: case 0x16: #endif default: } } break; #if !defined(CONFIG_USER_ONLY) case 0x31: { if (!supervisor(dc)) goto priv_insn; #ifdef TARGET_SPARC64 switch (rd) { case 0: gen_op_saved(); break; case 1: gen_op_restored(); break; default: } #else gen_op_xor_T1_T0(); gen_op_wrpsr(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; #endif } break; case 0x32: { if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); #ifdef TARGET_SPARC64 switch (rd) { case 0: gen_op_wrtpc(); break; case 1: gen_op_wrtnpc(); break; case 2: gen_op_wrtstate(); break; case 3: gen_op_wrtt(); break; case 4: gen_op_wrtick(); break; case 5: gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); break; case 6: gen_op_wrpstate(); save_state(dc); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); dc->is_br = 1; break; case 7: gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); break; case 8: gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); break; case 9: gen_op_wrcwp(); break; case 10: gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); break; case 11: gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); break; case 12: gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); break; case 13: gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); break; case 14: gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); break; default: } #else gen_op_wrwim(); #endif } break; #ifndef TARGET_SPARC64 case 0x33: { if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); } break; #endif #endif #ifdef TARGET_SPARC64 case 0x2c: { int cc = GET_FIELD_SP(insn, 11, 12); int cond = GET_FIELD_SP(insn, 14, 17); if (IS_IMM) { rs2 = GET_FIELD_SPs(insn, 0, 10); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_movl_reg_T0(rd); flush_T2(dc); if (insn & (1 << 18)) { if (cc == 0) gen_cond[0][cond](); else if (cc == 2) gen_cond[1][cond](); else } else { gen_fcond[cc][cond](); } gen_op_mov_cc(); gen_movl_T0_reg(rd); break; } case 0x2d: gen_op_sdivx_T1_T0(); gen_movl_T0_reg(rd); break; case 0x2e: { if (IS_IMM) { rs2 = GET_FIELD_SPs(insn, 0, 12); gen_movl_simm_T1(rs2); optimize: popc(constant) } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_op_popc(); gen_movl_T0_reg(rd); } case 0x2f: { int cond = GET_FIELD_SP(insn, 10, 12); rs1 = GET_FIELD(insn, 13, 17); flush_T2(dc); gen_movl_reg_T0(rs1); gen_cond_reg(cond); if (IS_IMM) { rs2 = GET_FIELD_SPs(insn, 0, 10); gen_movl_simm_T1(rs2); } else { rs2 = GET_FIELD_SP(insn, 0, 4); gen_movl_reg_T1(rs2); } gen_movl_reg_T0(rd); gen_op_mov_cc(); gen_movl_T0_reg(rd); break; } case 0x36: { int opf = GET_FIELD_SP(insn, 5, 13); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); switch (opf) { case 0x018: if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_alignaddr(); gen_movl_T0_reg(rd); break; case 0x01a: if (gen_trap_ifnofpu(dc)) goto jmp_insn; break; case 0x048: if (gen_trap_ifnofpu(dc)) goto jmp_insn; gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_faligndata(); gen_op_store_DT0_fpr(rd); break; default: } break; } #endif default: } } } else if (xop == 0x36 || xop == 0x37) { #ifdef TARGET_SPARC64 #else goto ncp_insn; #endif #ifdef TARGET_SPARC64 } else if (xop == 0x39) { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } gen_op_restore(); gen_mov_pc_npc(dc); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; goto jmp_insn; #endif } else { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } switch (xop) { case 0x38: { if (rd != 0) { #ifdef TARGET_SPARC64 if (dc->pc == (uint32_t)dc->pc) { gen_op_movl_T1_im(dc->pc); } else { gen_op_movq_T1_im64(dc->pc >> 32, dc->pc); } #else gen_op_movl_T1_im(dc->pc); #endif gen_movl_T1_reg(rd); } gen_mov_pc_npc(dc); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; } goto jmp_insn; #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: { if (!supervisor(dc)) goto priv_insn; gen_mov_pc_npc(dc); gen_op_movl_npc_T0(); dc->npc = DYNAMIC_PC; gen_op_rett(); } goto jmp_insn; #endif case 0x3b: gen_op_flush_T0(); break; case 0x3c: save_state(dc); gen_op_save(); gen_movl_T0_reg(rd); break; case 0x3d: save_state(dc); gen_op_restore(); gen_movl_T0_reg(rd); break; #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) case 0x3e: { switch (rd) { case 0: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; gen_op_done(); goto jmp_insn; case 1: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; gen_op_retry(); goto jmp_insn; default: } } break; #endif default: } } break; } break; case 3: { unsigned int xop = GET_FIELD(insn, 7, 12); rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { rs2 = GET_FIELDs(insn, 19, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { rs2 = GET_FIELD(insn, 27, 31); #if defined(OPTIM) if (rs2 != 0) { #endif gen_movl_reg_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \ (xop > 0x17 && xop < 0x1d ) || \ (xop > 0x2c && xop < 0x33) || xop == 0x1f) { switch (xop) { case 0x0: gen_op_ldst(ld); break; case 0x1: gen_op_ldst(ldub); break; case 0x2: gen_op_ldst(lduh); break; case 0x3: gen_op_ldst(ldd); gen_movl_T0_reg(rd + 1); break; case 0x9: gen_op_ldst(ldsb); break; case 0xa: gen_op_ldst(ldsh); break; case 0xd: gen_op_ldst(ldstub); break; case 0x0f: gen_movl_reg_T1(rd); gen_op_ldst(swap); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x10: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_lda(insn, 1, 4, 0); break; case 0x11: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_lduba(insn, 1, 1, 0); break; case 0x12: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_lduha(insn, 1, 2, 0); break; case 0x13: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldda(insn, 1, 8, 0); gen_movl_T0_reg(rd + 1); break; case 0x19: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldsba(insn, 1, 1, 1); break; case 0x1a: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldsha(insn, 1, 2 ,1); break; case 0x1d: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_ldstuba(insn, 1, 1, 0); break; case 0x1f: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_movl_reg_T1(rd); gen_op_swapa(insn, 1, 4, 0); break; #ifndef TARGET_SPARC64 case 0x30: case 0x31: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: goto ncp_insn; break; (void) &gen_op_stfa; (void) &gen_op_stdfa; (void) &gen_op_ldfa; (void) &gen_op_lddfa; #else #if !defined(CONFIG_USER_ONLY) (void) &gen_op_cas; (void) &gen_op_casx; #endif #endif #endif #ifdef TARGET_SPARC64 case 0x08: gen_op_ldst(ldsw); break; case 0x0b: gen_op_ldst(ldx); break; case 0x18: gen_op_ldswa(insn, 1, 4, 1); break; case 0x1b: gen_op_ldxa(insn, 1, 8, 0); break; case 0x2d: goto skip_move; case 0x30: gen_op_ldfa(insn, 1, 8, 0); break; case 0x33: gen_op_lddfa(insn, 1, 8, 0); break; case 0x3d: goto skip_move; case 0x32: goto nfpu_insn; #endif default: } gen_movl_T1_reg(rd); #ifdef TARGET_SPARC64 skip_move: ; #endif } else if (xop >= 0x20 && xop < 0x24) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (xop) { case 0x20: gen_op_ldst(ldf); gen_op_store_FT0_fpr(rd); break; case 0x21: gen_op_ldst(ldf); gen_op_ldfsr(); break; case 0x22: goto nfpu_insn; case 0x23: gen_op_ldst(lddf); gen_op_store_DT0_fpr(DFPREG(rd)); break; default: } } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ xop == 0xe || xop == 0x1e) { gen_movl_reg_T1(rd); switch (xop) { case 0x4: gen_op_ldst(st); break; case 0x5: gen_op_ldst(stb); break; case 0x6: gen_op_ldst(sth); break; case 0x7: flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_op_ldst(std); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_sta(insn, 0, 4, 0); break; case 0x15: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_stba(insn, 0, 1, 0); break; case 0x16: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif gen_op_stha(insn, 0, 2, 0); break; case 0x17: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(dc)) goto priv_insn; #endif flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_op_stda(insn, 0, 8, 0); break; #endif #ifdef TARGET_SPARC64 case 0x0e: gen_op_ldst(stx); break; case 0x1e: gen_op_stxa(insn, 0, 8, 0); break; #endif default: } } else if (xop > 0x23 && xop < 0x28) { if (gen_trap_ifnofpu(dc)) goto jmp_insn; switch (xop) { case 0x24: gen_op_load_fpr_FT0(rd); gen_op_ldst(stf); break; case 0x25: gen_op_stfsr(); gen_op_ldst(stf); break; case 0x26: goto nfpu_insn; case 0x27: gen_op_load_fpr_DT0(DFPREG(rd)); gen_op_ldst(stdf); break; default: } } else if (xop > 0x33 && xop < 0x3f) { #ifdef TARGET_SPARC64 switch (xop) { case 0x34: gen_op_stfa(insn, 0, 0, 0); break; case 0x37: gen_op_stdfa(insn, 0, 0, 0); break; case 0x3c: gen_op_casa(insn, 0, 4, 0); break; case 0x3e: gen_op_casxa(insn, 0, 8, 0); break; case 0x36: goto nfpu_insn; default: } #else #endif } else } break; } if (dc->npc == DYNAMIC_PC) { dc->pc = DYNAMIC_PC; gen_op_next_insn(); } else if (dc->npc == JUMP_PC) { gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]); dc->is_br = 1; } else { dc->pc = dc->npc; dc->npc = dc->npc + 4; } jmp_insn: return; illegal_insn: save_state(dc); gen_op_exception(TT_ILL_INSN); dc->is_br = 1; return; #if !defined(CONFIG_USER_ONLY) priv_insn: save_state(dc); gen_op_exception(TT_PRIV_INSN); dc->is_br = 1; return; #endif nfpu_insn: save_state(dc); gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); dc->is_br = 1; return; #ifndef TARGET_SPARC64 ncp_insn: save_state(dc); gen_op_exception(TT_NCP_INSN); dc->is_br = 1; return; #endif }
{ "code": [], "line_no": [] }
static void FUNC_0(DisasContext * VAR_0) { unsigned int VAR_1, VAR_2, VAR_3, VAR_4, VAR_5; VAR_1 = ldl_code(VAR_0->pc); VAR_2 = GET_FIELD(VAR_1, 0, 1); VAR_5 = GET_FIELD(VAR_1, 2, 6); switch (VAR_2) { case 0: { unsigned int VAR_8 = GET_FIELD(VAR_1, 7, 9); int32_t target; switch (VAR_8) { #ifdef TARGET_SPARC64 case 0x1: { int cc; target = GET_FIELD_SP(VAR_1, 0, 18); target = sign_extend(target, 18); target <<= 2; cc = GET_FIELD_SP(VAR_1, 20, 21); if (cc == 0) do_branch(VAR_0, target, VAR_1, 0); else if (cc == 2) do_branch(VAR_0, target, VAR_1, 1); else goto jmp_insn; } case 0x3: { target = GET_FIELD_SP(VAR_1, 0, 13) | (GET_FIELD_SP(VAR_1, 20, 21) << 14); target = sign_extend(target, 16); target <<= 2; VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); do_branch_reg(VAR_0, target, VAR_1); goto jmp_insn; } case 0x5: { int cc = GET_FIELD_SP(VAR_1, 20, 21); if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; target = GET_FIELD_SP(VAR_1, 0, 18); target = sign_extend(target, 19); target <<= 2; do_fbranch(VAR_0, target, VAR_1, cc); goto jmp_insn; } #endif case 0x2: { target = GET_FIELD(VAR_1, 10, 31); target = sign_extend(target, 22); target <<= 2; do_branch(VAR_0, target, VAR_1, 0); goto jmp_insn; } case 0x6: { if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; target = GET_FIELD(VAR_1, 10, 31); target = sign_extend(target, 22); target <<= 2; do_fbranch(VAR_0, target, VAR_1, 0); goto jmp_insn; } case 0x4: #define OPTIM #if defined(OPTIM) if (VAR_5) { #endif uint32_t value = GET_FIELD(VAR_1, 10, 31); gen_movl_imm_T0(value << 10); gen_movl_T0_reg(VAR_5); #if defined(OPTIM) } #endif break; case 0x0: default: } break; } break; case 1: { target_long target = GET_FIELDs(VAR_1, 2, 31) << 2; #ifdef TARGET_SPARC64 if (VAR_0->pc == (uint32_t)VAR_0->pc) { gen_op_movl_T0_im(VAR_0->pc); } else { gen_op_movq_T0_im64(VAR_0->pc >> 32, VAR_0->pc); } #else gen_op_movl_T0_im(VAR_0->pc); #endif gen_movl_T0_reg(15); target += VAR_0->pc; gen_mov_pc_npc(VAR_0); VAR_0->npc = target; } goto jmp_insn; case 2: { unsigned int VAR_8 = GET_FIELD(VAR_1, 7, 12); if (VAR_8 == 0x3a) { int VAR_7; VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELD(VAR_1, 25, 31); #if defined(OPTIM) if (VAR_4 != 0) { #endif gen_movl_simm_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); #if defined(OPTIM) if (VAR_4 != 0) { #endif gen_movl_reg_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } VAR_7 = GET_FIELD(VAR_1, 3, 6); if (VAR_7 == 0x8) { save_state(VAR_0); gen_op_trap_T0(); } else if (VAR_7 != 0) { #ifdef TARGET_SPARC64 int cc = GET_FIELD_SP(VAR_1, 11, 12); flush_T2(VAR_0); save_state(VAR_0); if (cc == 0) gen_cond[0][VAR_7](); else if (cc == 2) gen_cond[1][VAR_7](); else #else flush_T2(VAR_0); save_state(VAR_0); gen_cond[0][VAR_7](); #endif gen_op_trapcc_T0(); } gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); VAR_0->is_br = 1; goto jmp_insn; } else if (VAR_8 == 0x28) { VAR_3 = GET_FIELD(VAR_1, 13, 17); switch(VAR_3) { case 0: #ifndef TARGET_SPARC64 case 0x01 ... 0x0e: case 0x0f: case 0x10 ... 0x1f: #endif gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); gen_movl_T0_reg(VAR_5); break; #ifdef TARGET_SPARC64 case 0x2: gen_op_rdccr(); gen_movl_T0_reg(VAR_5); break; case 0x3: gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); gen_movl_T0_reg(VAR_5); break; case 0x4: gen_op_rdtick(); gen_movl_T0_reg(VAR_5); break; case 0x5: if (VAR_0->pc == (uint32_t)VAR_0->pc) { gen_op_movl_T0_im(VAR_0->pc); } else { gen_op_movq_T0_im64(VAR_0->pc >> 32, VAR_0->pc); } gen_movl_T0_reg(VAR_5); break; case 0x6: gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); gen_movl_T0_reg(VAR_5); break; case 0xf: break; case 0x13: if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); gen_movl_T0_reg(VAR_5); break; case 0x17: gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); gen_movl_T0_reg(VAR_5); break; case 0x18: gen_op_rdtick(); gen_movl_T0_reg(VAR_5); break; case 0x19: gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); gen_movl_T0_reg(VAR_5); break; case 0x10: case 0x11: case 0x12: case 0x14: case 0x15: case 0x16: #endif default: } #if !defined(CONFIG_USER_ONLY) #ifndef TARGET_SPARC64 } else if (VAR_8 == 0x29) { if (!supervisor(VAR_0)) goto priv_insn; gen_op_rdpsr(); gen_movl_T0_reg(VAR_5); break; #endif } else if (VAR_8 == 0x2a) { if (!supervisor(VAR_0)) goto priv_insn; #ifdef TARGET_SPARC64 VAR_3 = GET_FIELD(VAR_1, 13, 17); switch (VAR_3) { case 0: gen_op_rdtpc(); break; case 1: gen_op_rdtnpc(); break; case 2: gen_op_rdtstate(); break; case 3: gen_op_rdtt(); break; case 4: gen_op_rdtick(); break; case 5: gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); break; case 6: gen_op_rdpstate(); break; case 7: gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); break; case 8: gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); break; case 9: gen_op_rdcwp(); break; case 10: gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); break; case 11: gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); break; case 12: gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); break; case 13: gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); break; case 14: gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); break; case 31: gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); break; case 15: default: } #else gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); #endif gen_movl_T0_reg(VAR_5); break; } else if (VAR_8 == 0x2b) { #ifdef TARGET_SPARC64 gen_op_flushw(); #else if (!supervisor(VAR_0)) goto priv_insn; gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); gen_movl_T0_reg(VAR_5); #endif break; #endif } else if (VAR_8 == 0x34) { if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; VAR_3 = GET_FIELD(VAR_1, 13, 17); VAR_4 = GET_FIELD(VAR_1, 27, 31); VAR_8 = GET_FIELD(VAR_1, 18, 26); switch (VAR_8) { case 0x1: gen_op_load_fpr_FT0(VAR_4); gen_op_store_FT0_fpr(VAR_5); break; case 0x5: gen_op_load_fpr_FT1(VAR_4); gen_op_fnegs(); gen_op_store_FT0_fpr(VAR_5); break; case 0x9: gen_op_load_fpr_FT1(VAR_4); gen_op_fabss(); gen_op_store_FT0_fpr(VAR_5); break; case 0x29: gen_op_load_fpr_FT1(VAR_4); gen_op_fsqrts(); gen_op_store_FT0_fpr(VAR_5); break; case 0x2a: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fsqrtd(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x2b: goto nfpu_insn; case 0x41: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); gen_op_fadds(); gen_op_store_FT0_fpr(VAR_5); break; case 0x42: gen_op_load_fpr_DT0(DFPREG(VAR_3)); gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_faddd(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x43: goto nfpu_insn; case 0x45: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); gen_op_fsubs(); gen_op_store_FT0_fpr(VAR_5); break; case 0x46: gen_op_load_fpr_DT0(DFPREG(VAR_3)); gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fsubd(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x47: goto nfpu_insn; case 0x49: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); gen_op_fmuls(); gen_op_store_FT0_fpr(VAR_5); break; case 0x4a: gen_op_load_fpr_DT0(DFPREG(VAR_3)); gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fmuld(); gen_op_store_DT0_fpr(VAR_5); break; case 0x4b: goto nfpu_insn; case 0x4d: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); gen_op_fdivs(); gen_op_store_FT0_fpr(VAR_5); break; case 0x4e: gen_op_load_fpr_DT0(DFPREG(VAR_3)); gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fdivd(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x4f: goto nfpu_insn; case 0x69: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); gen_op_fsmuld(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x6e: goto nfpu_insn; case 0xc4: gen_op_load_fpr_FT1(VAR_4); gen_op_fitos(); gen_op_store_FT0_fpr(VAR_5); break; case 0xc6: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fdtos(); gen_op_store_FT0_fpr(VAR_5); break; case 0xc7: goto nfpu_insn; case 0xc8: gen_op_load_fpr_FT1(VAR_4); gen_op_fitod(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0xc9: gen_op_load_fpr_FT1(VAR_4); gen_op_fstod(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0xcb: goto nfpu_insn; case 0xcc: goto nfpu_insn; case 0xcd: goto nfpu_insn; case 0xce: goto nfpu_insn; case 0xd1: gen_op_load_fpr_FT1(VAR_4); gen_op_fstoi(); gen_op_store_FT0_fpr(VAR_5); break; case 0xd2: gen_op_load_fpr_DT1(VAR_4); gen_op_fdtoi(); gen_op_store_FT0_fpr(VAR_5); break; case 0xd3: goto nfpu_insn; #ifdef TARGET_SPARC64 case 0x2: gen_op_load_fpr_DT0(DFPREG(VAR_4)); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x6: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fnegd(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0xa: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fabsd(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x81: gen_op_load_fpr_FT1(VAR_4); gen_op_fstox(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x82: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fdtox(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x84: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fxtos(); gen_op_store_FT0_fpr(VAR_5); break; case 0x88: gen_op_load_fpr_DT1(DFPREG(VAR_4)); gen_op_fxtod(); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; case 0x3: case 0x7: case 0xb: case 0x83: case 0x8c: goto nfpu_insn; #endif default: } } else if (VAR_8 == 0x35) { #ifdef TARGET_SPARC64 int VAR_7; #endif if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; VAR_3 = GET_FIELD(VAR_1, 13, 17); VAR_4 = GET_FIELD(VAR_1, 27, 31); VAR_8 = GET_FIELD(VAR_1, 18, 26); #ifdef TARGET_SPARC64 if ((VAR_8 & 0x11f) == 0x005) { VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); flush_T2(VAR_0); gen_cond_reg(VAR_7); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; } else if ((VAR_8 & 0x11f) == 0x006) { VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); gen_cond_reg(VAR_7); gen_op_fmovs_cc(); gen_op_store_DT0_fpr(VAR_5); break; } else if ((VAR_8 & 0x11f) == 0x007) { goto nfpu_insn; } #endif switch (VAR_8) { #ifdef TARGET_SPARC64 case 0x001: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); flush_T2(VAR_0); gen_fcond[0][VAR_7](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; case 0x002: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); gen_fcond[0][VAR_7](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(VAR_5); break; case 0x003: goto nfpu_insn; case 0x041: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); flush_T2(VAR_0); gen_fcond[1][VAR_7](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; case 0x042: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); gen_fcond[1][VAR_7](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(VAR_5); break; case 0x043: goto nfpu_insn; case 0x081: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); flush_T2(VAR_0); gen_fcond[2][VAR_7](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; case 0x082: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); gen_fcond[2][VAR_7](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(VAR_5); break; case 0x083: goto nfpu_insn; case 0x0c1: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); flush_T2(VAR_0); gen_fcond[3][VAR_7](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; case 0x0c2: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); gen_fcond[3][VAR_7](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(VAR_5); break; case 0x0c3: goto nfpu_insn; case 0x101: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); flush_T2(VAR_0); gen_cond[0][VAR_7](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; case 0x102: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); gen_cond[0][VAR_7](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(VAR_5); break; case 0x103: goto nfpu_insn; case 0x181: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_FT0(VAR_5); gen_op_load_fpr_FT1(VAR_4); flush_T2(VAR_0); gen_cond[1][VAR_7](); gen_op_fmovs_cc(); gen_op_store_FT0_fpr(VAR_5); break; case 0x182: VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); gen_op_load_fpr_DT0(VAR_5); gen_op_load_fpr_DT1(VAR_4); flush_T2(VAR_0); gen_cond[1][VAR_7](); gen_op_fmovd_cc(); gen_op_store_DT0_fpr(VAR_5); break; case 0x183: goto nfpu_insn; #endif case 0x51: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); #ifdef TARGET_SPARC64 gen_fcmps[VAR_5 & 3](); #else gen_op_fcmps(); #endif break; case 0x52: gen_op_load_fpr_DT0(DFPREG(VAR_3)); gen_op_load_fpr_DT1(DFPREG(VAR_4)); #ifdef TARGET_SPARC64 gen_fcmpd[VAR_5 & 3](); #else gen_op_fcmpd(); #endif break; case 0x53: goto nfpu_insn; case 0x55: gen_op_load_fpr_FT0(VAR_3); gen_op_load_fpr_FT1(VAR_4); #ifdef TARGET_SPARC64 gen_fcmps[VAR_5 & 3](); #else gen_op_fcmps(); #endif break; case 0x56: gen_op_load_fpr_DT0(DFPREG(VAR_3)); gen_op_load_fpr_DT1(DFPREG(VAR_4)); #ifdef TARGET_SPARC64 gen_fcmpd[VAR_5 & 3](); #else gen_op_fcmpd(); #endif break; case 0x57: goto nfpu_insn; default: } #if defined(OPTIM) } else if (VAR_8 == 0x2) { VAR_3 = GET_FIELD(VAR_1, 13, 17); if (VAR_3 == 0) { if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 19, 31); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); gen_movl_reg_T1(VAR_4); } gen_movl_T1_reg(VAR_5); } else { gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 19, 31); if (VAR_4 != 0) { gen_movl_simm_T1(VAR_4); gen_op_or_T1_T0(); } } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); if (VAR_4 != 0) { gen_movl_reg_T1(VAR_4); gen_op_or_T1_T0(); } } gen_movl_T0_reg(VAR_5); } #endif #ifdef TARGET_SPARC64 } else if (VAR_8 == 0x25) { VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 20, 31); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); gen_movl_reg_T1(VAR_4); } gen_op_sll(); gen_movl_T0_reg(VAR_5); } else if (VAR_8 == 0x26) { VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 20, 31); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); gen_movl_reg_T1(VAR_4); } if (VAR_1 & (1 << 12)) gen_op_srlx(); else gen_op_srl(); gen_movl_T0_reg(VAR_5); } else if (VAR_8 == 0x27) { VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 20, 31); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); gen_movl_reg_T1(VAR_4); } if (VAR_1 & (1 << 12)) gen_op_srax(); else gen_op_sra(); gen_movl_T0_reg(VAR_5); #endif } else if (VAR_8 < 0x36) { VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 19, 31); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); gen_movl_reg_T1(VAR_4); } if (VAR_8 < 0x20) { switch (VAR_8 & ~0x10) { case 0x0: if (VAR_8 & 0x10) gen_op_add_T1_T0_cc(); else gen_op_add_T1_T0(); break; case 0x1: gen_op_and_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0x2: gen_op_or_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0x3: gen_op_xor_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0x4: if (VAR_8 & 0x10) gen_op_sub_T1_T0_cc(); else gen_op_sub_T1_T0(); break; case 0x5: gen_op_andn_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0x6: gen_op_orn_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0x7: gen_op_xnor_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0x8: if (VAR_8 & 0x10) gen_op_addx_T1_T0_cc(); else gen_op_addx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0x9: gen_op_mulx_T1_T0(); break; #endif case 0xa: gen_op_umul_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0xb: gen_op_smul_T1_T0(); if (VAR_8 & 0x10) gen_op_logic_T0_cc(); break; case 0xc: if (VAR_8 & 0x10) gen_op_subx_T1_T0_cc(); else gen_op_subx_T1_T0(); break; #ifdef TARGET_SPARC64 case 0xd: gen_op_udivx_T1_T0(); break; #endif case 0xe: gen_op_udiv_T1_T0(); if (VAR_8 & 0x10) gen_op_div_cc(); break; case 0xf: gen_op_sdiv_T1_T0(); if (VAR_8 & 0x10) gen_op_div_cc(); break; default: } gen_movl_T0_reg(VAR_5); } else { switch (VAR_8) { case 0x20: gen_op_tadd_T1_T0_cc(); gen_movl_T0_reg(VAR_5); break; case 0x21: gen_op_tsub_T1_T0_cc(); gen_movl_T0_reg(VAR_5); break; case 0x22: gen_op_tadd_T1_T0_ccTV(); gen_movl_T0_reg(VAR_5); break; case 0x23: gen_op_tsub_T1_T0_ccTV(); gen_movl_T0_reg(VAR_5); break; case 0x24: gen_op_mulscc_T1_T0(); gen_movl_T0_reg(VAR_5); break; #ifndef TARGET_SPARC64 case 0x25: gen_op_sll(); gen_movl_T0_reg(VAR_5); break; case 0x26: gen_op_srl(); gen_movl_T0_reg(VAR_5); break; case 0x27: gen_op_sra(); gen_movl_T0_reg(VAR_5); break; #endif case 0x30: { switch(VAR_5) { case 0: gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); break; #ifndef TARGET_SPARC64 case 0x01 ... 0x0f: case 0x10 ... 0x1f: break; #else case 0x2: gen_op_wrccr(); break; case 0x3: gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); break; case 0x6: gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); break; case 0xf: #if !defined(CONFIG_USER_ONLY) if (supervisor(VAR_0)) gen_op_sir(); #endif break; case 0x13: if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); break; case 0x17: #if !defined(CONFIG_USER_ONLY) if (!supervisor(VAR_0)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); break; case 0x18: #if !defined(CONFIG_USER_ONLY) if (!supervisor(VAR_0)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); break; case 0x19: #if !defined(CONFIG_USER_ONLY) if (!supervisor(VAR_0)) #endif gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); break; case 0x10: case 0x11: case 0x12: case 0x14: case 0x15: case 0x16: #endif default: } } break; #if !defined(CONFIG_USER_ONLY) case 0x31: { if (!supervisor(VAR_0)) goto priv_insn; #ifdef TARGET_SPARC64 switch (VAR_5) { case 0: gen_op_saved(); break; case 1: gen_op_restored(); break; default: } #else gen_op_xor_T1_T0(); gen_op_wrpsr(); save_state(VAR_0); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); VAR_0->is_br = 1; #endif } break; case 0x32: { if (!supervisor(VAR_0)) goto priv_insn; gen_op_xor_T1_T0(); #ifdef TARGET_SPARC64 switch (VAR_5) { case 0: gen_op_wrtpc(); break; case 1: gen_op_wrtnpc(); break; case 2: gen_op_wrtstate(); break; case 3: gen_op_wrtt(); break; case 4: gen_op_wrtick(); break; case 5: gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); break; case 6: gen_op_wrpstate(); save_state(VAR_0); gen_op_next_insn(); gen_op_movl_T0_0(); gen_op_exit_tb(); VAR_0->is_br = 1; break; case 7: gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); break; case 8: gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); break; case 9: gen_op_wrcwp(); break; case 10: gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); break; case 11: gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); break; case 12: gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); break; case 13: gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); break; case 14: gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); break; default: } #else gen_op_wrwim(); #endif } break; #ifndef TARGET_SPARC64 case 0x33: { if (!supervisor(VAR_0)) goto priv_insn; gen_op_xor_T1_T0(); gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); } break; #endif #endif #ifdef TARGET_SPARC64 case 0x2c: { int cc = GET_FIELD_SP(VAR_1, 11, 12); int VAR_7 = GET_FIELD_SP(VAR_1, 14, 17); if (IS_IMM) { VAR_4 = GET_FIELD_SPs(VAR_1, 0, 10); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD_SP(VAR_1, 0, 4); gen_movl_reg_T1(VAR_4); } gen_movl_reg_T0(VAR_5); flush_T2(VAR_0); if (VAR_1 & (1 << 18)) { if (cc == 0) gen_cond[0][VAR_7](); else if (cc == 2) gen_cond[1][VAR_7](); else } else { gen_fcond[cc][VAR_7](); } gen_op_mov_cc(); gen_movl_T0_reg(VAR_5); break; } case 0x2d: gen_op_sdivx_T1_T0(); gen_movl_T0_reg(VAR_5); break; case 0x2e: { if (IS_IMM) { VAR_4 = GET_FIELD_SPs(VAR_1, 0, 12); gen_movl_simm_T1(VAR_4); optimize: popc(constant) } else { VAR_4 = GET_FIELD_SP(VAR_1, 0, 4); gen_movl_reg_T1(VAR_4); } gen_op_popc(); gen_movl_T0_reg(VAR_5); } case 0x2f: { int VAR_7 = GET_FIELD_SP(VAR_1, 10, 12); VAR_3 = GET_FIELD(VAR_1, 13, 17); flush_T2(VAR_0); gen_movl_reg_T0(VAR_3); gen_cond_reg(VAR_7); if (IS_IMM) { VAR_4 = GET_FIELD_SPs(VAR_1, 0, 10); gen_movl_simm_T1(VAR_4); } else { VAR_4 = GET_FIELD_SP(VAR_1, 0, 4); gen_movl_reg_T1(VAR_4); } gen_movl_reg_T0(VAR_5); gen_op_mov_cc(); gen_movl_T0_reg(VAR_5); break; } case 0x36: { int opf = GET_FIELD_SP(VAR_1, 5, 13); VAR_3 = GET_FIELD(VAR_1, 13, 17); VAR_4 = GET_FIELD(VAR_1, 27, 31); switch (opf) { case 0x018: if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; gen_movl_reg_T0(VAR_3); gen_movl_reg_T1(VAR_4); gen_op_alignaddr(); gen_movl_T0_reg(VAR_5); break; case 0x01a: if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; break; case 0x048: if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; gen_op_load_fpr_DT0(VAR_3); gen_op_load_fpr_DT1(VAR_4); gen_op_faligndata(); gen_op_store_DT0_fpr(VAR_5); break; default: } break; } #endif default: } } } else if (VAR_8 == 0x36 || VAR_8 == 0x37) { #ifdef TARGET_SPARC64 #else goto ncp_insn; #endif #ifdef TARGET_SPARC64 } else if (VAR_8 == 0x39) { VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 19, 31); #if defined(OPTIM) if (VAR_4) { #endif gen_movl_simm_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); #if defined(OPTIM) if (VAR_4) { #endif gen_movl_reg_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } gen_op_restore(); gen_mov_pc_npc(VAR_0); gen_op_movl_npc_T0(); VAR_0->npc = DYNAMIC_PC; goto jmp_insn; #endif } else { VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 19, 31); #if defined(OPTIM) if (VAR_4) { #endif gen_movl_simm_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); #if defined(OPTIM) if (VAR_4) { #endif gen_movl_reg_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } switch (VAR_8) { case 0x38: { if (VAR_5 != 0) { #ifdef TARGET_SPARC64 if (VAR_0->pc == (uint32_t)VAR_0->pc) { gen_op_movl_T1_im(VAR_0->pc); } else { gen_op_movq_T1_im64(VAR_0->pc >> 32, VAR_0->pc); } #else gen_op_movl_T1_im(VAR_0->pc); #endif gen_movl_T1_reg(VAR_5); } gen_mov_pc_npc(VAR_0); gen_op_movl_npc_T0(); VAR_0->npc = DYNAMIC_PC; } goto jmp_insn; #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: { if (!supervisor(VAR_0)) goto priv_insn; gen_mov_pc_npc(VAR_0); gen_op_movl_npc_T0(); VAR_0->npc = DYNAMIC_PC; gen_op_rett(); } goto jmp_insn; #endif case 0x3b: gen_op_flush_T0(); break; case 0x3c: save_state(VAR_0); gen_op_save(); gen_movl_T0_reg(VAR_5); break; case 0x3d: save_state(VAR_0); gen_op_restore(); gen_movl_T0_reg(VAR_5); break; #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) case 0x3e: { switch (VAR_5) { case 0: if (!supervisor(VAR_0)) goto priv_insn; VAR_0->npc = DYNAMIC_PC; VAR_0->pc = DYNAMIC_PC; gen_op_done(); goto jmp_insn; case 1: if (!supervisor(VAR_0)) goto priv_insn; VAR_0->npc = DYNAMIC_PC; VAR_0->pc = DYNAMIC_PC; gen_op_retry(); goto jmp_insn; default: } } break; #endif default: } } break; } break; case 3: { unsigned int VAR_8 = GET_FIELD(VAR_1, 7, 12); VAR_3 = GET_FIELD(VAR_1, 13, 17); gen_movl_reg_T0(VAR_3); if (IS_IMM) { VAR_4 = GET_FIELDs(VAR_1, 19, 31); #if defined(OPTIM) if (VAR_4 != 0) { #endif gen_movl_simm_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } else { VAR_4 = GET_FIELD(VAR_1, 27, 31); #if defined(OPTIM) if (VAR_4 != 0) { #endif gen_movl_reg_T1(VAR_4); gen_op_add_T1_T0(); #if defined(OPTIM) } #endif } if (VAR_8 < 4 || (VAR_8 > 7 && VAR_8 < 0x14 && VAR_8 != 0x0e) || \ (VAR_8 > 0x17 && VAR_8 < 0x1d ) || \ (VAR_8 > 0x2c && VAR_8 < 0x33) || VAR_8 == 0x1f) { switch (VAR_8) { case 0x0: gen_op_ldst(ld); break; case 0x1: gen_op_ldst(ldub); break; case 0x2: gen_op_ldst(lduh); break; case 0x3: gen_op_ldst(ldd); gen_movl_T0_reg(VAR_5 + 1); break; case 0x9: gen_op_ldst(ldsb); break; case 0xa: gen_op_ldst(ldsh); break; case 0xd: gen_op_ldst(ldstub); break; case 0x0f: gen_movl_reg_T1(VAR_5); gen_op_ldst(swap); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x10: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_lda(VAR_1, 1, 4, 0); break; case 0x11: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_lduba(VAR_1, 1, 1, 0); break; case 0x12: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_lduha(VAR_1, 1, 2, 0); break; case 0x13: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_ldda(VAR_1, 1, 8, 0); gen_movl_T0_reg(VAR_5 + 1); break; case 0x19: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_ldsba(VAR_1, 1, 1, 1); break; case 0x1a: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_ldsha(VAR_1, 1, 2 ,1); break; case 0x1d: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_ldstuba(VAR_1, 1, 1, 0); break; case 0x1f: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_movl_reg_T1(VAR_5); gen_op_swapa(VAR_1, 1, 4, 0); break; #ifndef TARGET_SPARC64 case 0x30: case 0x31: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: goto ncp_insn; break; (void) &gen_op_stfa; (void) &gen_op_stdfa; (void) &gen_op_ldfa; (void) &gen_op_lddfa; #else #if !defined(CONFIG_USER_ONLY) (void) &gen_op_cas; (void) &gen_op_casx; #endif #endif #endif #ifdef TARGET_SPARC64 case 0x08: gen_op_ldst(ldsw); break; case 0x0b: gen_op_ldst(ldx); break; case 0x18: gen_op_ldswa(VAR_1, 1, 4, 1); break; case 0x1b: gen_op_ldxa(VAR_1, 1, 8, 0); break; case 0x2d: goto skip_move; case 0x30: gen_op_ldfa(VAR_1, 1, 8, 0); break; case 0x33: gen_op_lddfa(VAR_1, 1, 8, 0); break; case 0x3d: goto skip_move; case 0x32: goto nfpu_insn; #endif default: } gen_movl_T1_reg(VAR_5); #ifdef TARGET_SPARC64 skip_move: ; #endif } else if (VAR_8 >= 0x20 && VAR_8 < 0x24) { if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; switch (VAR_8) { case 0x20: gen_op_ldst(ldf); gen_op_store_FT0_fpr(VAR_5); break; case 0x21: gen_op_ldst(ldf); gen_op_ldfsr(); break; case 0x22: goto nfpu_insn; case 0x23: gen_op_ldst(lddf); gen_op_store_DT0_fpr(DFPREG(VAR_5)); break; default: } } else if (VAR_8 < 8 || (VAR_8 >= 0x14 && VAR_8 < 0x18) || \ VAR_8 == 0xe || VAR_8 == 0x1e) { gen_movl_reg_T1(VAR_5); switch (VAR_8) { case 0x4: gen_op_ldst(st); break; case 0x5: gen_op_ldst(stb); break; case 0x6: gen_op_ldst(sth); break; case 0x7: flush_T2(VAR_0); gen_movl_reg_T2(VAR_5 + 1); gen_op_ldst(std); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_sta(VAR_1, 0, 4, 0); break; case 0x15: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_stba(VAR_1, 0, 1, 0); break; case 0x16: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif gen_op_stha(VAR_1, 0, 2, 0); break; case 0x17: #ifndef TARGET_SPARC64 if (IS_IMM) if (!supervisor(VAR_0)) goto priv_insn; #endif flush_T2(VAR_0); gen_movl_reg_T2(VAR_5 + 1); gen_op_stda(VAR_1, 0, 8, 0); break; #endif #ifdef TARGET_SPARC64 case 0x0e: gen_op_ldst(stx); break; case 0x1e: gen_op_stxa(VAR_1, 0, 8, 0); break; #endif default: } } else if (VAR_8 > 0x23 && VAR_8 < 0x28) { if (gen_trap_ifnofpu(VAR_0)) goto jmp_insn; switch (VAR_8) { case 0x24: gen_op_load_fpr_FT0(VAR_5); gen_op_ldst(stf); break; case 0x25: gen_op_stfsr(); gen_op_ldst(stf); break; case 0x26: goto nfpu_insn; case 0x27: gen_op_load_fpr_DT0(DFPREG(VAR_5)); gen_op_ldst(stdf); break; default: } } else if (VAR_8 > 0x33 && VAR_8 < 0x3f) { #ifdef TARGET_SPARC64 switch (VAR_8) { case 0x34: gen_op_stfa(VAR_1, 0, 0, 0); break; case 0x37: gen_op_stdfa(VAR_1, 0, 0, 0); break; case 0x3c: gen_op_casa(VAR_1, 0, 4, 0); break; case 0x3e: gen_op_casxa(VAR_1, 0, 8, 0); break; case 0x36: goto nfpu_insn; default: } #else #endif } else } break; } if (VAR_0->npc == DYNAMIC_PC) { VAR_0->pc = DYNAMIC_PC; gen_op_next_insn(); } else if (VAR_0->npc == JUMP_PC) { gen_branch2(VAR_0, (long)VAR_0->tb, VAR_0->jump_pc[0], VAR_0->jump_pc[1]); VAR_0->is_br = 1; } else { VAR_0->pc = VAR_0->npc; VAR_0->npc = VAR_0->npc + 4; } jmp_insn: return; illegal_insn: save_state(VAR_0); gen_op_exception(TT_ILL_INSN); VAR_0->is_br = 1; return; #if !defined(CONFIG_USER_ONLY) priv_insn: save_state(VAR_0); gen_op_exception(TT_PRIV_INSN); VAR_0->is_br = 1; return; #endif nfpu_insn: save_state(VAR_0); gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); VAR_0->is_br = 1; return; #ifndef TARGET_SPARC64 ncp_insn: save_state(VAR_0); gen_op_exception(TT_NCP_INSN); VAR_0->is_br = 1; return; #endif }
[ "static void FUNC_0(DisasContext * VAR_0)\n{", "unsigned int VAR_1, VAR_2, VAR_3, VAR_4, VAR_5;", "VAR_1 = ldl_code(VAR_0->pc);", "VAR_2 = GET_FIELD(VAR_1, 0, 1);", "VAR_5 = GET_FIELD(VAR_1, 2, 6);", "switch (VAR_2) {", "case 0:\n{", "unsigned int VAR_8 = GET_FIELD(VAR_1, 7, 9);", "int32_t target;", "switch (VAR_8) {", "#ifdef TARGET_SPARC64\ncase 0x1:\n{", "int cc;", "target = GET_FIELD_SP(VAR_1, 0, 18);", "target = sign_extend(target, 18);", "target <<= 2;", "cc = GET_FIELD_SP(VAR_1, 20, 21);", "if (cc == 0)\ndo_branch(VAR_0, target, VAR_1, 0);", "else if (cc == 2)\ndo_branch(VAR_0, target, VAR_1, 1);", "else\ngoto jmp_insn;", "}", "case 0x3:\n{", "target = GET_FIELD_SP(VAR_1, 0, 13) |\n(GET_FIELD_SP(VAR_1, 20, 21) << 14);", "target = sign_extend(target, 16);", "target <<= 2;", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "do_branch_reg(VAR_0, target, VAR_1);", "goto jmp_insn;", "}", "case 0x5:\n{", "int cc = GET_FIELD_SP(VAR_1, 20, 21);", "if (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "target = GET_FIELD_SP(VAR_1, 0, 18);", "target = sign_extend(target, 19);", "target <<= 2;", "do_fbranch(VAR_0, target, VAR_1, cc);", "goto jmp_insn;", "}", "#endif\ncase 0x2:\n{", "target = GET_FIELD(VAR_1, 10, 31);", "target = sign_extend(target, 22);", "target <<= 2;", "do_branch(VAR_0, target, VAR_1, 0);", "goto jmp_insn;", "}", "case 0x6:\n{", "if (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "target = GET_FIELD(VAR_1, 10, 31);", "target = sign_extend(target, 22);", "target <<= 2;", "do_fbranch(VAR_0, target, VAR_1, 0);", "goto jmp_insn;", "}", "case 0x4:\n#define OPTIM\n#if defined(OPTIM)\nif (VAR_5) {", "#endif\nuint32_t value = GET_FIELD(VAR_1, 10, 31);", "gen_movl_imm_T0(value << 10);", "gen_movl_T0_reg(VAR_5);", "#if defined(OPTIM)\n}", "#endif\nbreak;", "case 0x0:\ndefault:\n}", "break;", "}", "break;", "case 1:\n{", "target_long target = GET_FIELDs(VAR_1, 2, 31) << 2;", "#ifdef TARGET_SPARC64\nif (VAR_0->pc == (uint32_t)VAR_0->pc) {", "gen_op_movl_T0_im(VAR_0->pc);", "} else {", "gen_op_movq_T0_im64(VAR_0->pc >> 32, VAR_0->pc);", "}", "#else\ngen_op_movl_T0_im(VAR_0->pc);", "#endif\ngen_movl_T0_reg(15);", "target += VAR_0->pc;", "gen_mov_pc_npc(VAR_0);", "VAR_0->npc = target;", "}", "goto jmp_insn;", "case 2:\n{", "unsigned int VAR_8 = GET_FIELD(VAR_1, 7, 12);", "if (VAR_8 == 0x3a) {", "int VAR_7;", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELD(VAR_1, 25, 31);", "#if defined(OPTIM)\nif (VAR_4 != 0) {", "#endif\ngen_movl_simm_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "#if defined(OPTIM)\nif (VAR_4 != 0) {", "#endif\ngen_movl_reg_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n}", "VAR_7 = GET_FIELD(VAR_1, 3, 6);", "if (VAR_7 == 0x8) {", "save_state(VAR_0);", "gen_op_trap_T0();", "} else if (VAR_7 != 0) {", "#ifdef TARGET_SPARC64\nint cc = GET_FIELD_SP(VAR_1, 11, 12);", "flush_T2(VAR_0);", "save_state(VAR_0);", "if (cc == 0)\ngen_cond[0][VAR_7]();", "else if (cc == 2)\ngen_cond[1][VAR_7]();", "else\n#else\nflush_T2(VAR_0);", "save_state(VAR_0);", "gen_cond[0][VAR_7]();", "#endif\ngen_op_trapcc_T0();", "}", "gen_op_next_insn();", "gen_op_movl_T0_0();", "gen_op_exit_tb();", "VAR_0->is_br = 1;", "goto jmp_insn;", "} else if (VAR_8 == 0x28) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "switch(VAR_3) {", "case 0:\n#ifndef TARGET_SPARC64\ncase 0x01 ... 0x0e:\ncase 0x0f:\ncase 0x10 ... 0x1f:\n#endif\ngen_op_movtl_T0_env(offsetof(CPUSPARCState, y));", "gen_movl_T0_reg(VAR_5);", "break;", "#ifdef TARGET_SPARC64\ncase 0x2:\ngen_op_rdccr();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x3:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, asi));", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x4:\ngen_op_rdtick();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x5:\nif (VAR_0->pc == (uint32_t)VAR_0->pc) {", "gen_op_movl_T0_im(VAR_0->pc);", "} else {", "gen_op_movq_T0_im64(VAR_0->pc >> 32, VAR_0->pc);", "}", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x6:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));", "gen_movl_T0_reg(VAR_5);", "break;", "case 0xf:\nbreak;", "case 0x13:\nif (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x17:\ngen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x18:\ngen_op_rdtick();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x19:\ngen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x10:\ncase 0x11:\ncase 0x12:\ncase 0x14:\ncase 0x15:\ncase 0x16:\n#endif\ndefault:\n}", "#if !defined(CONFIG_USER_ONLY)\n#ifndef TARGET_SPARC64\n} else if (VAR_8 == 0x29) {", "if (!supervisor(VAR_0))\ngoto priv_insn;", "gen_op_rdpsr();", "gen_movl_T0_reg(VAR_5);", "break;", "#endif\n} else if (VAR_8 == 0x2a) {", "if (!supervisor(VAR_0))\ngoto priv_insn;", "#ifdef TARGET_SPARC64\nVAR_3 = GET_FIELD(VAR_1, 13, 17);", "switch (VAR_3) {", "case 0:\ngen_op_rdtpc();", "break;", "case 1:\ngen_op_rdtnpc();", "break;", "case 2:\ngen_op_rdtstate();", "break;", "case 3:\ngen_op_rdtt();", "break;", "case 4:\ngen_op_rdtick();", "break;", "case 5:\ngen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));", "break;", "case 6:\ngen_op_rdpstate();", "break;", "case 7:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, tl));", "break;", "case 8:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));", "break;", "case 9:\ngen_op_rdcwp();", "break;", "case 10:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));", "break;", "case 11:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));", "break;", "case 12:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));", "break;", "case 13:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));", "break;", "case 14:\ngen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));", "break;", "case 31:\ngen_op_movtl_T0_env(offsetof(CPUSPARCState, version));", "break;", "case 15:\ndefault:\n}", "#else\ngen_op_movl_T0_env(offsetof(CPUSPARCState, wim));", "#endif\ngen_movl_T0_reg(VAR_5);", "break;", "} else if (VAR_8 == 0x2b) {", "#ifdef TARGET_SPARC64\ngen_op_flushw();", "#else\nif (!supervisor(VAR_0))\ngoto priv_insn;", "gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));", "gen_movl_T0_reg(VAR_5);", "#endif\nbreak;", "#endif\n} else if (VAR_8 == 0x34) {", "if (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "VAR_8 = GET_FIELD(VAR_1, 18, 26);", "switch (VAR_8) {", "case 0x1:\ngen_op_load_fpr_FT0(VAR_4);", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x5:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fnegs();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x9:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fabss();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x29:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fsqrts();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x2a:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fsqrtd();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x2b:\ngoto nfpu_insn;", "case 0x41:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "gen_op_fadds();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x42:\ngen_op_load_fpr_DT0(DFPREG(VAR_3));", "gen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_faddd();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x43:\ngoto nfpu_insn;", "case 0x45:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "gen_op_fsubs();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x46:\ngen_op_load_fpr_DT0(DFPREG(VAR_3));", "gen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fsubd();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x47:\ngoto nfpu_insn;", "case 0x49:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "gen_op_fmuls();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x4a:\ngen_op_load_fpr_DT0(DFPREG(VAR_3));", "gen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fmuld();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x4b:\ngoto nfpu_insn;", "case 0x4d:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "gen_op_fdivs();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x4e:\ngen_op_load_fpr_DT0(DFPREG(VAR_3));", "gen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fdivd();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x4f:\ngoto nfpu_insn;", "case 0x69:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "gen_op_fsmuld();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x6e:\ngoto nfpu_insn;", "case 0xc4:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fitos();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0xc6:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fdtos();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0xc7:\ngoto nfpu_insn;", "case 0xc8:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fitod();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0xc9:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fstod();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0xcb:\ngoto nfpu_insn;", "case 0xcc:\ngoto nfpu_insn;", "case 0xcd:\ngoto nfpu_insn;", "case 0xce:\ngoto nfpu_insn;", "case 0xd1:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fstoi();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0xd2:\ngen_op_load_fpr_DT1(VAR_4);", "gen_op_fdtoi();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0xd3:\ngoto nfpu_insn;", "#ifdef TARGET_SPARC64\ncase 0x2:\ngen_op_load_fpr_DT0(DFPREG(VAR_4));", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x6:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fnegd();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0xa:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fabsd();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x81:\ngen_op_load_fpr_FT1(VAR_4);", "gen_op_fstox();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x82:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fdtox();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x84:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fxtos();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x88:\ngen_op_load_fpr_DT1(DFPREG(VAR_4));", "gen_op_fxtod();", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "case 0x3:\ncase 0x7:\ncase 0xb:\ncase 0x83:\ncase 0x8c:\ngoto nfpu_insn;", "#endif\ndefault:\n}", "} else if (VAR_8 == 0x35) {", "#ifdef TARGET_SPARC64\nint VAR_7;", "#endif\nif (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "VAR_8 = GET_FIELD(VAR_1, 18, 26);", "#ifdef TARGET_SPARC64\nif ((VAR_8 & 0x11f) == 0x005) {", "VAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "flush_T2(VAR_0);", "gen_cond_reg(VAR_7);", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "} else if ((VAR_8 & 0x11f) == 0x006) {", "VAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "gen_cond_reg(VAR_7);", "gen_op_fmovs_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "} else if ((VAR_8 & 0x11f) == 0x007) {", "goto nfpu_insn;", "}", "#endif\nswitch (VAR_8) {", "#ifdef TARGET_SPARC64\ncase 0x001:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[0][VAR_7]();", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x002:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[0][VAR_7]();", "gen_op_fmovd_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x003:\ngoto nfpu_insn;", "case 0x041:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[1][VAR_7]();", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x042:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[1][VAR_7]();", "gen_op_fmovd_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x043:\ngoto nfpu_insn;", "case 0x081:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[2][VAR_7]();", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x082:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[2][VAR_7]();", "gen_op_fmovd_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x083:\ngoto nfpu_insn;", "case 0x0c1:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[3][VAR_7]();", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x0c2:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "gen_fcond[3][VAR_7]();", "gen_op_fmovd_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x0c3:\ngoto nfpu_insn;", "case 0x101:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "flush_T2(VAR_0);", "gen_cond[0][VAR_7]();", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x102:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "gen_cond[0][VAR_7]();", "gen_op_fmovd_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x103:\ngoto nfpu_insn;", "case 0x181:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_FT0(VAR_5);", "gen_op_load_fpr_FT1(VAR_4);", "flush_T2(VAR_0);", "gen_cond[1][VAR_7]();", "gen_op_fmovs_cc();", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x182:\nVAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "gen_op_load_fpr_DT0(VAR_5);", "gen_op_load_fpr_DT1(VAR_4);", "flush_T2(VAR_0);", "gen_cond[1][VAR_7]();", "gen_op_fmovd_cc();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "case 0x183:\ngoto nfpu_insn;", "#endif\ncase 0x51:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "#ifdef TARGET_SPARC64\ngen_fcmps[VAR_5 & 3]();", "#else\ngen_op_fcmps();", "#endif\nbreak;", "case 0x52:\ngen_op_load_fpr_DT0(DFPREG(VAR_3));", "gen_op_load_fpr_DT1(DFPREG(VAR_4));", "#ifdef TARGET_SPARC64\ngen_fcmpd[VAR_5 & 3]();", "#else\ngen_op_fcmpd();", "#endif\nbreak;", "case 0x53:\ngoto nfpu_insn;", "case 0x55:\ngen_op_load_fpr_FT0(VAR_3);", "gen_op_load_fpr_FT1(VAR_4);", "#ifdef TARGET_SPARC64\ngen_fcmps[VAR_5 & 3]();", "#else\ngen_op_fcmps();", "#endif\nbreak;", "case 0x56:\ngen_op_load_fpr_DT0(DFPREG(VAR_3));", "gen_op_load_fpr_DT1(DFPREG(VAR_4));", "#ifdef TARGET_SPARC64\ngen_fcmpd[VAR_5 & 3]();", "#else\ngen_op_fcmpd();", "#endif\nbreak;", "case 0x57:\ngoto nfpu_insn;", "default:\n}", "#if defined(OPTIM)\n} else if (VAR_8 == 0x2) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "if (VAR_3 == 0) {", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 19, 31);", "gen_movl_simm_T1(VAR_4);", "} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "gen_movl_reg_T1(VAR_4);", "}", "gen_movl_T1_reg(VAR_5);", "} else {", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 19, 31);", "if (VAR_4 != 0) {", "gen_movl_simm_T1(VAR_4);", "gen_op_or_T1_T0();", "}", "} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "if (VAR_4 != 0) {", "gen_movl_reg_T1(VAR_4);", "gen_op_or_T1_T0();", "}", "}", "gen_movl_T0_reg(VAR_5);", "}", "#endif\n#ifdef TARGET_SPARC64\n} else if (VAR_8 == 0x25) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 20, 31);", "gen_movl_simm_T1(VAR_4);", "} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "gen_movl_reg_T1(VAR_4);", "}", "gen_op_sll();", "gen_movl_T0_reg(VAR_5);", "} else if (VAR_8 == 0x26) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 20, 31);", "gen_movl_simm_T1(VAR_4);", "} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "gen_movl_reg_T1(VAR_4);", "}", "if (VAR_1 & (1 << 12))\ngen_op_srlx();", "else\ngen_op_srl();", "gen_movl_T0_reg(VAR_5);", "} else if (VAR_8 == 0x27) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 20, 31);", "gen_movl_simm_T1(VAR_4);", "} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "gen_movl_reg_T1(VAR_4);", "}", "if (VAR_1 & (1 << 12))\ngen_op_srax();", "else\ngen_op_sra();", "gen_movl_T0_reg(VAR_5);", "#endif\n} else if (VAR_8 < 0x36) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 19, 31);", "gen_movl_simm_T1(VAR_4);", "} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "gen_movl_reg_T1(VAR_4);", "}", "if (VAR_8 < 0x20) {", "switch (VAR_8 & ~0x10) {", "case 0x0:\nif (VAR_8 & 0x10)\ngen_op_add_T1_T0_cc();", "else\ngen_op_add_T1_T0();", "break;", "case 0x1:\ngen_op_and_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0x2:\ngen_op_or_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0x3:\ngen_op_xor_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0x4:\nif (VAR_8 & 0x10)\ngen_op_sub_T1_T0_cc();", "else\ngen_op_sub_T1_T0();", "break;", "case 0x5:\ngen_op_andn_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0x6:\ngen_op_orn_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0x7:\ngen_op_xnor_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0x8:\nif (VAR_8 & 0x10)\ngen_op_addx_T1_T0_cc();", "else\ngen_op_addx_T1_T0();", "break;", "#ifdef TARGET_SPARC64\ncase 0x9:\ngen_op_mulx_T1_T0();", "break;", "#endif\ncase 0xa:\ngen_op_umul_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0xb:\ngen_op_smul_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_logic_T0_cc();", "break;", "case 0xc:\nif (VAR_8 & 0x10)\ngen_op_subx_T1_T0_cc();", "else\ngen_op_subx_T1_T0();", "break;", "#ifdef TARGET_SPARC64\ncase 0xd:\ngen_op_udivx_T1_T0();", "break;", "#endif\ncase 0xe:\ngen_op_udiv_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_div_cc();", "break;", "case 0xf:\ngen_op_sdiv_T1_T0();", "if (VAR_8 & 0x10)\ngen_op_div_cc();", "break;", "default:\n}", "gen_movl_T0_reg(VAR_5);", "} else {", "switch (VAR_8) {", "case 0x20:\ngen_op_tadd_T1_T0_cc();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x21:\ngen_op_tsub_T1_T0_cc();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x22:\ngen_op_tadd_T1_T0_ccTV();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x23:\ngen_op_tsub_T1_T0_ccTV();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x24:\ngen_op_mulscc_T1_T0();", "gen_movl_T0_reg(VAR_5);", "break;", "#ifndef TARGET_SPARC64\ncase 0x25:\ngen_op_sll();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x26:\ngen_op_srl();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x27:\ngen_op_sra();", "gen_movl_T0_reg(VAR_5);", "break;", "#endif\ncase 0x30:\n{", "switch(VAR_5) {", "case 0:\ngen_op_xor_T1_T0();", "gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));", "break;", "#ifndef TARGET_SPARC64\ncase 0x01 ... 0x0f:\ncase 0x10 ... 0x1f:\nbreak;", "#else\ncase 0x2:\ngen_op_wrccr();", "break;", "case 0x3:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, asi));", "break;", "case 0x6:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));", "break;", "case 0xf:\n#if !defined(CONFIG_USER_ONLY)\nif (supervisor(VAR_0))\ngen_op_sir();", "#endif\nbreak;", "case 0x13:\nif (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));", "break;", "case 0x17:\n#if !defined(CONFIG_USER_ONLY)\nif (!supervisor(VAR_0))\n#endif\ngen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));", "break;", "case 0x18:\n#if !defined(CONFIG_USER_ONLY)\nif (!supervisor(VAR_0))\n#endif\ngen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));", "break;", "case 0x19:\n#if !defined(CONFIG_USER_ONLY)\nif (!supervisor(VAR_0))\n#endif\ngen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));", "break;", "case 0x10:\ncase 0x11:\ncase 0x12:\ncase 0x14:\ncase 0x15:\ncase 0x16:\n#endif\ndefault:\n}", "}", "break;", "#if !defined(CONFIG_USER_ONLY)\ncase 0x31:\n{", "if (!supervisor(VAR_0))\ngoto priv_insn;", "#ifdef TARGET_SPARC64\nswitch (VAR_5) {", "case 0:\ngen_op_saved();", "break;", "case 1:\ngen_op_restored();", "break;", "default:\n}", "#else\ngen_op_xor_T1_T0();", "gen_op_wrpsr();", "save_state(VAR_0);", "gen_op_next_insn();", "gen_op_movl_T0_0();", "gen_op_exit_tb();", "VAR_0->is_br = 1;", "#endif\n}", "break;", "case 0x32:\n{", "if (!supervisor(VAR_0))\ngoto priv_insn;", "gen_op_xor_T1_T0();", "#ifdef TARGET_SPARC64\nswitch (VAR_5) {", "case 0:\ngen_op_wrtpc();", "break;", "case 1:\ngen_op_wrtnpc();", "break;", "case 2:\ngen_op_wrtstate();", "break;", "case 3:\ngen_op_wrtt();", "break;", "case 4:\ngen_op_wrtick();", "break;", "case 5:\ngen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));", "break;", "case 6:\ngen_op_wrpstate();", "save_state(VAR_0);", "gen_op_next_insn();", "gen_op_movl_T0_0();", "gen_op_exit_tb();", "VAR_0->is_br = 1;", "break;", "case 7:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, tl));", "break;", "case 8:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));", "break;", "case 9:\ngen_op_wrcwp();", "break;", "case 10:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));", "break;", "case 11:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));", "break;", "case 12:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));", "break;", "case 13:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));", "break;", "case 14:\ngen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));", "break;", "default:\n}", "#else\ngen_op_wrwim();", "#endif\n}", "break;", "#ifndef TARGET_SPARC64\ncase 0x33:\n{", "if (!supervisor(VAR_0))\ngoto priv_insn;", "gen_op_xor_T1_T0();", "gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));", "}", "break;", "#endif\n#endif\n#ifdef TARGET_SPARC64\ncase 0x2c:\n{", "int cc = GET_FIELD_SP(VAR_1, 11, 12);", "int VAR_7 = GET_FIELD_SP(VAR_1, 14, 17);", "if (IS_IMM) {", "VAR_4 = GET_FIELD_SPs(VAR_1, 0, 10);", "gen_movl_simm_T1(VAR_4);", "}", "else {", "VAR_4 = GET_FIELD_SP(VAR_1, 0, 4);", "gen_movl_reg_T1(VAR_4);", "}", "gen_movl_reg_T0(VAR_5);", "flush_T2(VAR_0);", "if (VAR_1 & (1 << 18)) {", "if (cc == 0)\ngen_cond[0][VAR_7]();", "else if (cc == 2)\ngen_cond[1][VAR_7]();", "else\n} else {", "gen_fcond[cc][VAR_7]();", "}", "gen_op_mov_cc();", "gen_movl_T0_reg(VAR_5);", "break;", "}", "case 0x2d:\ngen_op_sdivx_T1_T0();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x2e:\n{", "if (IS_IMM) {", "VAR_4 = GET_FIELD_SPs(VAR_1, 0, 12);", "gen_movl_simm_T1(VAR_4);", "optimize: popc(constant)\n}", "else {", "VAR_4 = GET_FIELD_SP(VAR_1, 0, 4);", "gen_movl_reg_T1(VAR_4);", "}", "gen_op_popc();", "gen_movl_T0_reg(VAR_5);", "}", "case 0x2f:\n{", "int VAR_7 = GET_FIELD_SP(VAR_1, 10, 12);", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "flush_T2(VAR_0);", "gen_movl_reg_T0(VAR_3);", "gen_cond_reg(VAR_7);", "if (IS_IMM) {", "VAR_4 = GET_FIELD_SPs(VAR_1, 0, 10);", "gen_movl_simm_T1(VAR_4);", "}", "else {", "VAR_4 = GET_FIELD_SP(VAR_1, 0, 4);", "gen_movl_reg_T1(VAR_4);", "}", "gen_movl_reg_T0(VAR_5);", "gen_op_mov_cc();", "gen_movl_T0_reg(VAR_5);", "break;", "}", "case 0x36:\n{", "int opf = GET_FIELD_SP(VAR_1, 5, 13);", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "switch (opf) {", "case 0x018:\nif (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "gen_movl_reg_T0(VAR_3);", "gen_movl_reg_T1(VAR_4);", "gen_op_alignaddr();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x01a:\nif (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "break;", "case 0x048:\nif (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "gen_op_load_fpr_DT0(VAR_3);", "gen_op_load_fpr_DT1(VAR_4);", "gen_op_faligndata();", "gen_op_store_DT0_fpr(VAR_5);", "break;", "default:\n}", "break;", "}", "#endif\ndefault:\n}", "}", "} else if (VAR_8 == 0x36 || VAR_8 == 0x37) {", "#ifdef TARGET_SPARC64\n#else\ngoto ncp_insn;", "#endif\n#ifdef TARGET_SPARC64\n} else if (VAR_8 == 0x39) {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 19, 31);", "#if defined(OPTIM)\nif (VAR_4) {", "#endif\ngen_movl_simm_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "#if defined(OPTIM)\nif (VAR_4) {", "#endif\ngen_movl_reg_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n}", "gen_op_restore();", "gen_mov_pc_npc(VAR_0);", "gen_op_movl_npc_T0();", "VAR_0->npc = DYNAMIC_PC;", "goto jmp_insn;", "#endif\n} else {", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 19, 31);", "#if defined(OPTIM)\nif (VAR_4) {", "#endif\ngen_movl_simm_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "#if defined(OPTIM)\nif (VAR_4) {", "#endif\ngen_movl_reg_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n}", "switch (VAR_8) {", "case 0x38:\n{", "if (VAR_5 != 0) {", "#ifdef TARGET_SPARC64\nif (VAR_0->pc == (uint32_t)VAR_0->pc) {", "gen_op_movl_T1_im(VAR_0->pc);", "} else {", "gen_op_movq_T1_im64(VAR_0->pc >> 32, VAR_0->pc);", "}", "#else\ngen_op_movl_T1_im(VAR_0->pc);", "#endif\ngen_movl_T1_reg(VAR_5);", "}", "gen_mov_pc_npc(VAR_0);", "gen_op_movl_npc_T0();", "VAR_0->npc = DYNAMIC_PC;", "}", "goto jmp_insn;", "#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)\ncase 0x39:\n{", "if (!supervisor(VAR_0))\ngoto priv_insn;", "gen_mov_pc_npc(VAR_0);", "gen_op_movl_npc_T0();", "VAR_0->npc = DYNAMIC_PC;", "gen_op_rett();", "}", "goto jmp_insn;", "#endif\ncase 0x3b:\ngen_op_flush_T0();", "break;", "case 0x3c:\nsave_state(VAR_0);", "gen_op_save();", "gen_movl_T0_reg(VAR_5);", "break;", "case 0x3d:\nsave_state(VAR_0);", "gen_op_restore();", "gen_movl_T0_reg(VAR_5);", "break;", "#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)\ncase 0x3e:\n{", "switch (VAR_5) {", "case 0:\nif (!supervisor(VAR_0))\ngoto priv_insn;", "VAR_0->npc = DYNAMIC_PC;", "VAR_0->pc = DYNAMIC_PC;", "gen_op_done();", "goto jmp_insn;", "case 1:\nif (!supervisor(VAR_0))\ngoto priv_insn;", "VAR_0->npc = DYNAMIC_PC;", "VAR_0->pc = DYNAMIC_PC;", "gen_op_retry();", "goto jmp_insn;", "default:\n}", "}", "break;", "#endif\ndefault:\n}", "}", "break;", "}", "break;", "case 3:\n{", "unsigned int VAR_8 = GET_FIELD(VAR_1, 7, 12);", "VAR_3 = GET_FIELD(VAR_1, 13, 17);", "gen_movl_reg_T0(VAR_3);", "if (IS_IMM) {", "VAR_4 = GET_FIELDs(VAR_1, 19, 31);", "#if defined(OPTIM)\nif (VAR_4 != 0) {", "#endif\ngen_movl_simm_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n} else {", "VAR_4 = GET_FIELD(VAR_1, 27, 31);", "#if defined(OPTIM)\nif (VAR_4 != 0) {", "#endif\ngen_movl_reg_T1(VAR_4);", "gen_op_add_T1_T0();", "#if defined(OPTIM)\n}", "#endif\n}", "if (VAR_8 < 4 || (VAR_8 > 7 && VAR_8 < 0x14 && VAR_8 != 0x0e) || \\\n(VAR_8 > 0x17 && VAR_8 < 0x1d ) || \\\n(VAR_8 > 0x2c && VAR_8 < 0x33) || VAR_8 == 0x1f) {", "switch (VAR_8) {", "case 0x0:\ngen_op_ldst(ld);", "break;", "case 0x1:\ngen_op_ldst(ldub);", "break;", "case 0x2:\ngen_op_ldst(lduh);", "break;", "case 0x3:\ngen_op_ldst(ldd);", "gen_movl_T0_reg(VAR_5 + 1);", "break;", "case 0x9:\ngen_op_ldst(ldsb);", "break;", "case 0xa:\ngen_op_ldst(ldsh);", "break;", "case 0xd:\ngen_op_ldst(ldstub);", "break;", "case 0x0f:\ngen_movl_reg_T1(VAR_5);", "gen_op_ldst(swap);", "break;", "#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)\ncase 0x10:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_lda(VAR_1, 1, 4, 0);", "break;", "case 0x11:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_lduba(VAR_1, 1, 1, 0);", "break;", "case 0x12:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_lduha(VAR_1, 1, 2, 0);", "break;", "case 0x13:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_ldda(VAR_1, 1, 8, 0);", "gen_movl_T0_reg(VAR_5 + 1);", "break;", "case 0x19:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_ldsba(VAR_1, 1, 1, 1);", "break;", "case 0x1a:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_ldsha(VAR_1, 1, 2 ,1);", "break;", "case 0x1d:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_ldstuba(VAR_1, 1, 1, 0);", "break;", "case 0x1f:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_movl_reg_T1(VAR_5);", "gen_op_swapa(VAR_1, 1, 4, 0);", "break;", "#ifndef TARGET_SPARC64\ncase 0x30:\ncase 0x31:\ncase 0x33:\ncase 0x34:\ncase 0x35:\ncase 0x36:\ncase 0x37:\ngoto ncp_insn;", "break;", "(void) &gen_op_stfa;", "(void) &gen_op_stdfa;", "(void) &gen_op_ldfa;", "(void) &gen_op_lddfa;", "#else\n#if !defined(CONFIG_USER_ONLY)\n(void) &gen_op_cas;", "(void) &gen_op_casx;", "#endif\n#endif\n#endif\n#ifdef TARGET_SPARC64\ncase 0x08:\ngen_op_ldst(ldsw);", "break;", "case 0x0b:\ngen_op_ldst(ldx);", "break;", "case 0x18:\ngen_op_ldswa(VAR_1, 1, 4, 1);", "break;", "case 0x1b:\ngen_op_ldxa(VAR_1, 1, 8, 0);", "break;", "case 0x2d:\ngoto skip_move;", "case 0x30:\ngen_op_ldfa(VAR_1, 1, 8, 0);", "break;", "case 0x33:\ngen_op_lddfa(VAR_1, 1, 8, 0);", "break;", "case 0x3d:\ngoto skip_move;", "case 0x32:\ngoto nfpu_insn;", "#endif\ndefault:\n}", "gen_movl_T1_reg(VAR_5);", "#ifdef TARGET_SPARC64\nskip_move: ;", "#endif\n} else if (VAR_8 >= 0x20 && VAR_8 < 0x24) {", "if (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "switch (VAR_8) {", "case 0x20:\ngen_op_ldst(ldf);", "gen_op_store_FT0_fpr(VAR_5);", "break;", "case 0x21:\ngen_op_ldst(ldf);", "gen_op_ldfsr();", "break;", "case 0x22:\ngoto nfpu_insn;", "case 0x23:\ngen_op_ldst(lddf);", "gen_op_store_DT0_fpr(DFPREG(VAR_5));", "break;", "default:\n}", "} else if (VAR_8 < 8 || (VAR_8 >= 0x14 && VAR_8 < 0x18) || \\", "VAR_8 == 0xe || VAR_8 == 0x1e) {", "gen_movl_reg_T1(VAR_5);", "switch (VAR_8) {", "case 0x4:\ngen_op_ldst(st);", "break;", "case 0x5:\ngen_op_ldst(stb);", "break;", "case 0x6:\ngen_op_ldst(sth);", "break;", "case 0x7:\nflush_T2(VAR_0);", "gen_movl_reg_T2(VAR_5 + 1);", "gen_op_ldst(std);", "break;", "#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)\ncase 0x14:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_sta(VAR_1, 0, 4, 0);", "break;", "case 0x15:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_stba(VAR_1, 0, 1, 0);", "break;", "case 0x16:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\ngen_op_stha(VAR_1, 0, 2, 0);", "break;", "case 0x17:\n#ifndef TARGET_SPARC64\nif (IS_IMM)\nif (!supervisor(VAR_0))\ngoto priv_insn;", "#endif\nflush_T2(VAR_0);", "gen_movl_reg_T2(VAR_5 + 1);", "gen_op_stda(VAR_1, 0, 8, 0);", "break;", "#endif\n#ifdef TARGET_SPARC64\ncase 0x0e:\ngen_op_ldst(stx);", "break;", "case 0x1e:\ngen_op_stxa(VAR_1, 0, 8, 0);", "break;", "#endif\ndefault:\n}", "} else if (VAR_8 > 0x23 && VAR_8 < 0x28) {", "if (gen_trap_ifnofpu(VAR_0))\ngoto jmp_insn;", "switch (VAR_8) {", "case 0x24:\ngen_op_load_fpr_FT0(VAR_5);", "gen_op_ldst(stf);", "break;", "case 0x25:\ngen_op_stfsr();", "gen_op_ldst(stf);", "break;", "case 0x26:\ngoto nfpu_insn;", "case 0x27:\ngen_op_load_fpr_DT0(DFPREG(VAR_5));", "gen_op_ldst(stdf);", "break;", "default:\n}", "} else if (VAR_8 > 0x33 && VAR_8 < 0x3f) {", "#ifdef TARGET_SPARC64\nswitch (VAR_8) {", "case 0x34:\ngen_op_stfa(VAR_1, 0, 0, 0);", "break;", "case 0x37:\ngen_op_stdfa(VAR_1, 0, 0, 0);", "break;", "case 0x3c:\ngen_op_casa(VAR_1, 0, 4, 0);", "break;", "case 0x3e:\ngen_op_casxa(VAR_1, 0, 8, 0);", "break;", "case 0x36:\ngoto nfpu_insn;", "default:\n}", "#else\n#endif\n}", "else\n}", "break;", "}", "if (VAR_0->npc == DYNAMIC_PC) {", "VAR_0->pc = DYNAMIC_PC;", "gen_op_next_insn();", "} else if (VAR_0->npc == JUMP_PC) {", "gen_branch2(VAR_0, (long)VAR_0->tb, VAR_0->jump_pc[0], VAR_0->jump_pc[1]);", "VAR_0->is_br = 1;", "} else {", "VAR_0->pc = VAR_0->npc;", "VAR_0->npc = VAR_0->npc + 4;", "}", "jmp_insn:\nreturn;", "illegal_insn:\nsave_state(VAR_0);", "gen_op_exception(TT_ILL_INSN);", "VAR_0->is_br = 1;", "return;", "#if !defined(CONFIG_USER_ONLY)\npriv_insn:\nsave_state(VAR_0);", "gen_op_exception(TT_PRIV_INSN);", "VAR_0->is_br = 1;", "return;", "#endif\nnfpu_insn:\nsave_state(VAR_0);", "gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);", "VAR_0->is_br = 1;", "return;", "#ifndef TARGET_SPARC64\nncp_insn:\nsave_state(VAR_0);", "gen_op_exception(TT_NCP_INSN);", "VAR_0->is_br = 1;", "return;", "#endif\n}" ]
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], [ 2953 ], [ 2955, 2957, 2959 ], [ 2961 ], [ 2963, 2965, 2967, 2969, 2971, 2973 ], [ 2975 ], [ 2977, 2979 ], [ 2981 ], [ 2983, 2985 ], [ 2987 ], [ 2989, 2991 ], [ 2993 ], [ 2995, 2997 ], [ 2999, 3001 ], [ 3003 ], [ 3005, 3007 ], [ 3011 ], [ 3013, 3015 ], [ 3017, 3019 ], [ 3021, 3023, 3026 ], [ 3028 ], [ 3030, 3032 ], [ 3034, 3036 ], [ 3038, 3040 ], [ 3042 ], [ 3044, 3046 ], [ 3048 ], [ 3050 ], [ 3052, 3054 ], [ 3056 ], [ 3058 ], [ 3060, 3062 ], [ 3064, 3066 ], [ 3068 ], [ 3070 ], [ 3072, 3075 ], [ 3077 ], [ 3079 ], [ 3081 ], [ 3083 ], [ 3085, 3087 ], [ 3089 ], [ 3091, 3093 ], [ 3095 ], [ 3097, 3099 ], [ 3101 ], [ 3103, 3107 ], [ 3109 ], [ 3111 ], [ 3113 ], [ 3115, 3117, 3119, 3121, 3124, 3126 ], [ 3128, 3130 ], [ 3132 ], [ 3134, 3136, 3138, 3141, 3143 ], [ 3145, 3147 ], [ 3149 ], [ 3151, 3153, 3155, 3158, 3160 ], [ 3162, 3164 ], [ 3166 ], [ 3168, 3170, 3172, 3175, 3177 ], [ 3179, 3183 ], [ 3185 ], [ 3187 ], [ 3189 ], [ 3191, 3193, 3195, 3197 ], [ 3199 ], [ 3201, 3203 ], [ 3205 ], [ 3207, 3209, 3212 ], [ 3214 ], [ 3216, 3218 ], [ 3220 ], [ 3222, 3224 ], [ 3226 ], [ 3228 ], [ 3230, 3232 ], [ 3234 ], [ 3236 ], [ 3238, 3240 ], [ 3242, 3244 ], [ 3246 ], [ 3248 ], [ 3250, 3253 ], [ 3255 ], [ 3257, 3259 ], [ 3261, 3263 ], [ 3265 ], [ 3267, 3269 ], [ 3271 ], [ 3273, 3275 ], [ 3277 ], [ 3279, 3281 ], [ 3283 ], [ 3285, 3287 ], [ 3289, 3292 ], [ 3294, 3297, 3299 ], [ 3301, 3304 ], [ 3306 ], [ 3308 ], [ 3312 ], [ 3314 ], [ 3316 ], [ 3318 ], [ 3322 ], [ 3324 ], [ 3326 ], [ 3328 ], [ 3330 ], [ 3332 ], [ 3334, 3336 ], [ 3338, 3340 ], [ 3342 ], [ 3344 ], [ 3346 ], [ 3348, 3350, 3352 ], [ 3354 ], [ 3356 ], [ 3358 ], [ 3360, 3362, 3364 ], [ 3366 ], [ 3368 ], [ 3370 ], [ 3372, 3374, 3376 ], [ 3378 ], [ 3380 ], [ 3382 ], [ 3384, 3386 ] ]
16,925
int av_buffersrc_buffer(AVFilterContext *ctx, AVFilterBufferRef *buf) { BufferSourceContext *s = ctx->priv; AVFrame *frame = NULL; AVBufferRef *dummy_buf = NULL; int ret = 0, planes, i; if (!buf) { s->eof = 1; return 0; } else if (s->eof) return AVERROR(EINVAL); frame = av_frame_alloc(); if (!frame) return AVERROR(ENOMEM); dummy_buf = av_buffer_create(NULL, 0, compat_free_buffer, buf, 0); if (!dummy_buf) { ret = AVERROR(ENOMEM); goto fail; } if ((ret = avfilter_copy_buf_props(frame, buf)) < 0) goto fail; #define WRAP_PLANE(ref_out, data, data_size) \ do { \ AVBufferRef *dummy_ref = av_buffer_ref(dummy_buf); \ if (!dummy_ref) { \ ret = AVERROR(ENOMEM); \ goto fail; \ } \ ref_out = av_buffer_create(data, data_size, compat_unref_buffer, \ dummy_ref, 0); \ if (!ref_out) { \ av_frame_unref(frame); \ ret = AVERROR(ENOMEM); \ goto fail; \ } \ } while (0) if (ctx->outputs[0]->type == AVMEDIA_TYPE_VIDEO) { const AVPixFmtDescriptor *desc = av_pix_fmt_desc_get(frame->format); planes = av_pix_fmt_count_planes(frame->format); if (!desc || planes <= 0) { ret = AVERROR(EINVAL); goto fail; } for (i = 0; i < planes; i++) { int v_shift = (i == 1 || i == 2) ? desc->log2_chroma_h : 0; int plane_size = (frame->height >> v_shift) * frame->linesize[i]; WRAP_PLANE(frame->buf[i], frame->data[i], plane_size); } } else { int planar = av_sample_fmt_is_planar(frame->format); int channels = av_get_channel_layout_nb_channels(frame->channel_layout); planes = planar ? channels : 1; if (planes > FF_ARRAY_ELEMS(frame->buf)) { frame->nb_extended_buf = planes - FF_ARRAY_ELEMS(frame->buf); frame->extended_buf = av_mallocz(sizeof(*frame->extended_buf) * frame->nb_extended_buf); if (!frame->extended_buf) { ret = AVERROR(ENOMEM); goto fail; } } for (i = 0; i < FFMIN(planes, FF_ARRAY_ELEMS(frame->buf)); i++) WRAP_PLANE(frame->buf[i], frame->extended_data[i], frame->linesize[0]); for (i = 0; i < planes - FF_ARRAY_ELEMS(frame->buf); i++) WRAP_PLANE(frame->extended_buf[i], frame->extended_data[i + FF_ARRAY_ELEMS(frame->buf)], frame->linesize[0]); } ret = av_buffersrc_add_frame(ctx, frame); fail: av_buffer_unref(&dummy_buf); av_frame_free(&frame); return ret; }
true
FFmpeg
617814b4a717b38add5ccb8dd200dbb655f98f09
int av_buffersrc_buffer(AVFilterContext *ctx, AVFilterBufferRef *buf) { BufferSourceContext *s = ctx->priv; AVFrame *frame = NULL; AVBufferRef *dummy_buf = NULL; int ret = 0, planes, i; if (!buf) { s->eof = 1; return 0; } else if (s->eof) return AVERROR(EINVAL); frame = av_frame_alloc(); if (!frame) return AVERROR(ENOMEM); dummy_buf = av_buffer_create(NULL, 0, compat_free_buffer, buf, 0); if (!dummy_buf) { ret = AVERROR(ENOMEM); goto fail; } if ((ret = avfilter_copy_buf_props(frame, buf)) < 0) goto fail; #define WRAP_PLANE(ref_out, data, data_size) \ do { \ AVBufferRef *dummy_ref = av_buffer_ref(dummy_buf); \ if (!dummy_ref) { \ ret = AVERROR(ENOMEM); \ goto fail; \ } \ ref_out = av_buffer_create(data, data_size, compat_unref_buffer, \ dummy_ref, 0); \ if (!ref_out) { \ av_frame_unref(frame); \ ret = AVERROR(ENOMEM); \ goto fail; \ } \ } while (0) if (ctx->outputs[0]->type == AVMEDIA_TYPE_VIDEO) { const AVPixFmtDescriptor *desc = av_pix_fmt_desc_get(frame->format); planes = av_pix_fmt_count_planes(frame->format); if (!desc || planes <= 0) { ret = AVERROR(EINVAL); goto fail; } for (i = 0; i < planes; i++) { int v_shift = (i == 1 || i == 2) ? desc->log2_chroma_h : 0; int plane_size = (frame->height >> v_shift) * frame->linesize[i]; WRAP_PLANE(frame->buf[i], frame->data[i], plane_size); } } else { int planar = av_sample_fmt_is_planar(frame->format); int channels = av_get_channel_layout_nb_channels(frame->channel_layout); planes = planar ? channels : 1; if (planes > FF_ARRAY_ELEMS(frame->buf)) { frame->nb_extended_buf = planes - FF_ARRAY_ELEMS(frame->buf); frame->extended_buf = av_mallocz(sizeof(*frame->extended_buf) * frame->nb_extended_buf); if (!frame->extended_buf) { ret = AVERROR(ENOMEM); goto fail; } } for (i = 0; i < FFMIN(planes, FF_ARRAY_ELEMS(frame->buf)); i++) WRAP_PLANE(frame->buf[i], frame->extended_data[i], frame->linesize[0]); for (i = 0; i < planes - FF_ARRAY_ELEMS(frame->buf); i++) WRAP_PLANE(frame->extended_buf[i], frame->extended_data[i + FF_ARRAY_ELEMS(frame->buf)], frame->linesize[0]); } ret = av_buffersrc_add_frame(ctx, frame); fail: av_buffer_unref(&dummy_buf); av_frame_free(&frame); return ret; }
{ "code": [], "line_no": [] }
int FUNC_0(AVFilterContext *VAR_0, AVFilterBufferRef *VAR_1) { BufferSourceContext *s = VAR_0->priv; AVFrame *frame = NULL; AVBufferRef *dummy_buf = NULL; int VAR_2 = 0, VAR_3, VAR_4; if (!VAR_1) { s->eof = 1; return 0; } else if (s->eof) return AVERROR(EINVAL); frame = av_frame_alloc(); if (!frame) return AVERROR(ENOMEM); dummy_buf = av_buffer_create(NULL, 0, compat_free_buffer, VAR_1, 0); if (!dummy_buf) { VAR_2 = AVERROR(ENOMEM); goto fail; } if ((VAR_2 = avfilter_copy_buf_props(frame, VAR_1)) < 0) goto fail; #define WRAP_PLANE(ref_out, data, data_size) \ do { \ AVBufferRef *dummy_ref = av_buffer_ref(dummy_buf); \ if (!dummy_ref) { \ VAR_2 = AVERROR(ENOMEM); \ goto fail; \ } \ ref_out = av_buffer_create(data, data_size, compat_unref_buffer, \ dummy_ref, 0); \ if (!ref_out) { \ av_frame_unref(frame); \ VAR_2 = AVERROR(ENOMEM); \ goto fail; \ } \ } while (0) if (VAR_0->outputs[0]->type == AVMEDIA_TYPE_VIDEO) { const AVPixFmtDescriptor *desc = av_pix_fmt_desc_get(frame->format); VAR_3 = av_pix_fmt_count_planes(frame->format); if (!desc || VAR_3 <= 0) { VAR_2 = AVERROR(EINVAL); goto fail; } for (VAR_4 = 0; VAR_4 < VAR_3; VAR_4++) { int v_shift = (VAR_4 == 1 || VAR_4 == 2) ? desc->log2_chroma_h : 0; int plane_size = (frame->height >> v_shift) * frame->linesize[VAR_4]; WRAP_PLANE(frame->VAR_1[VAR_4], frame->data[VAR_4], plane_size); } } else { int planar = av_sample_fmt_is_planar(frame->format); int channels = av_get_channel_layout_nb_channels(frame->channel_layout); VAR_3 = planar ? channels : 1; if (VAR_3 > FF_ARRAY_ELEMS(frame->VAR_1)) { frame->nb_extended_buf = VAR_3 - FF_ARRAY_ELEMS(frame->VAR_1); frame->extended_buf = av_mallocz(sizeof(*frame->extended_buf) * frame->nb_extended_buf); if (!frame->extended_buf) { VAR_2 = AVERROR(ENOMEM); goto fail; } } for (VAR_4 = 0; VAR_4 < FFMIN(VAR_3, FF_ARRAY_ELEMS(frame->VAR_1)); VAR_4++) WRAP_PLANE(frame->VAR_1[VAR_4], frame->extended_data[VAR_4], frame->linesize[0]); for (VAR_4 = 0; VAR_4 < VAR_3 - FF_ARRAY_ELEMS(frame->VAR_1); VAR_4++) WRAP_PLANE(frame->extended_buf[VAR_4], frame->extended_data[VAR_4 + FF_ARRAY_ELEMS(frame->VAR_1)], frame->linesize[0]); } VAR_2 = av_buffersrc_add_frame(VAR_0, frame); fail: av_buffer_unref(&dummy_buf); av_frame_free(&frame); return VAR_2; }
[ "int FUNC_0(AVFilterContext *VAR_0, AVFilterBufferRef *VAR_1)\n{", "BufferSourceContext *s = VAR_0->priv;", "AVFrame *frame = NULL;", "AVBufferRef *dummy_buf = NULL;", "int VAR_2 = 0, VAR_3, VAR_4;", "if (!VAR_1) {", "s->eof = 1;", "return 0;", "} else if (s->eof)", "return AVERROR(EINVAL);", "frame = av_frame_alloc();", "if (!frame)\nreturn AVERROR(ENOMEM);", "dummy_buf = av_buffer_create(NULL, 0, compat_free_buffer, VAR_1, 0);", "if (!dummy_buf) {", "VAR_2 = AVERROR(ENOMEM);", "goto fail;", "}", "if ((VAR_2 = avfilter_copy_buf_props(frame, VAR_1)) < 0)\ngoto fail;", "#define WRAP_PLANE(ref_out, data, data_size) \\\ndo { \\", "AVBufferRef *dummy_ref = av_buffer_ref(dummy_buf); \\", "if (!dummy_ref) { \\", "VAR_2 = AVERROR(ENOMEM); \\", "goto fail; \\", "} \\", "ref_out = av_buffer_create(data, data_size, compat_unref_buffer, \\\ndummy_ref, 0); \\", "if (!ref_out) { \\", "av_frame_unref(frame); \\", "VAR_2 = AVERROR(ENOMEM); \\", "goto fail; \\", "} \\", "} while (0)", "if (VAR_0->outputs[0]->type == AVMEDIA_TYPE_VIDEO) {", "const AVPixFmtDescriptor *desc = av_pix_fmt_desc_get(frame->format);", "VAR_3 = av_pix_fmt_count_planes(frame->format);", "if (!desc || VAR_3 <= 0) {", "VAR_2 = AVERROR(EINVAL);", "goto fail;", "}", "for (VAR_4 = 0; VAR_4 < VAR_3; VAR_4++) {", "int v_shift = (VAR_4 == 1 || VAR_4 == 2) ? desc->log2_chroma_h : 0;", "int plane_size = (frame->height >> v_shift) * frame->linesize[VAR_4];", "WRAP_PLANE(frame->VAR_1[VAR_4], frame->data[VAR_4], plane_size);", "}", "} else {", "int planar = av_sample_fmt_is_planar(frame->format);", "int channels = av_get_channel_layout_nb_channels(frame->channel_layout);", "VAR_3 = planar ? channels : 1;", "if (VAR_3 > FF_ARRAY_ELEMS(frame->VAR_1)) {", "frame->nb_extended_buf = VAR_3 - FF_ARRAY_ELEMS(frame->VAR_1);", "frame->extended_buf = av_mallocz(sizeof(*frame->extended_buf) *\nframe->nb_extended_buf);", "if (!frame->extended_buf) {", "VAR_2 = AVERROR(ENOMEM);", "goto fail;", "}", "}", "for (VAR_4 = 0; VAR_4 < FFMIN(VAR_3, FF_ARRAY_ELEMS(frame->VAR_1)); VAR_4++)", "WRAP_PLANE(frame->VAR_1[VAR_4], frame->extended_data[VAR_4], frame->linesize[0]);", "for (VAR_4 = 0; VAR_4 < VAR_3 - FF_ARRAY_ELEMS(frame->VAR_1); VAR_4++)", "WRAP_PLANE(frame->extended_buf[VAR_4],\nframe->extended_data[VAR_4 + FF_ARRAY_ELEMS(frame->VAR_1)],\nframe->linesize[0]);", "}", "VAR_2 = av_buffersrc_add_frame(VAR_0, frame);", "fail:\nav_buffer_unref(&dummy_buf);", "av_frame_free(&frame);", "return VAR_2;", "}" ]
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16,926
void msi_uninit(struct PCIDevice *dev) { uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev)); uint8_t cap_size = msi_cap_sizeof(flags); pci_del_capability(dev, PCI_CAP_ID_MSIX, cap_size); MSI_DEV_PRINTF(dev, "uninit\n"); }
true
qemu
45fe15c25a5c9feea6e0f78434f5e9f632de9d94
void msi_uninit(struct PCIDevice *dev) { uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev)); uint8_t cap_size = msi_cap_sizeof(flags); pci_del_capability(dev, PCI_CAP_ID_MSIX, cap_size); MSI_DEV_PRINTF(dev, "uninit\n"); }
{ "code": [ " uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));", " uint8_t cap_size = msi_cap_sizeof(flags);" ], "line_no": [ 5, 7 ] }
void FUNC_0(struct PCIDevice *VAR_0) { uint16_t flags = pci_get_word(VAR_0->config + msi_flags_off(VAR_0)); uint8_t cap_size = msi_cap_sizeof(flags); pci_del_capability(VAR_0, PCI_CAP_ID_MSIX, cap_size); MSI_DEV_PRINTF(VAR_0, "uninit\n"); }
[ "void FUNC_0(struct PCIDevice *VAR_0)\n{", "uint16_t flags = pci_get_word(VAR_0->config + msi_flags_off(VAR_0));", "uint8_t cap_size = msi_cap_sizeof(flags);", "pci_del_capability(VAR_0, PCI_CAP_ID_MSIX, cap_size);", "MSI_DEV_PRINTF(VAR_0, \"uninit\\n\");", "}" ]
[ 0, 1, 1, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ] ]
16,927
Object *user_creatable_add(const QDict *qdict, Visitor *v, Error **errp) { char *type = NULL; char *id = NULL; Object *obj = NULL; Error *local_err = NULL, *end_err = NULL; QDict *pdict; pdict = qdict_clone_shallow(qdict); visit_start_struct(v, NULL, NULL, 0, &local_err); if (local_err) { goto out; } qdict_del(pdict, "qom-type"); visit_type_str(v, "qom-type", &type, &local_err); if (local_err) { goto out_visit; } qdict_del(pdict, "id"); visit_type_str(v, "id", &id, &local_err); if (local_err) { goto out_visit; } obj = user_creatable_add_type(type, id, pdict, v, &local_err); if (local_err) { goto out_visit; } out_visit: visit_end_struct(v, &end_err); if (end_err) { error_propagate(&local_err, end_err); if (obj) { user_creatable_del(id, NULL); } goto out; } out: QDECREF(pdict); g_free(id); g_free(type); if (local_err) { error_propagate(errp, local_err); object_unref(obj); return NULL; } return obj; }
true
qemu
15c2f669e3fb2bc97f7b42d1871f595c0ac24af8
Object *user_creatable_add(const QDict *qdict, Visitor *v, Error **errp) { char *type = NULL; char *id = NULL; Object *obj = NULL; Error *local_err = NULL, *end_err = NULL; QDict *pdict; pdict = qdict_clone_shallow(qdict); visit_start_struct(v, NULL, NULL, 0, &local_err); if (local_err) { goto out; } qdict_del(pdict, "qom-type"); visit_type_str(v, "qom-type", &type, &local_err); if (local_err) { goto out_visit; } qdict_del(pdict, "id"); visit_type_str(v, "id", &id, &local_err); if (local_err) { goto out_visit; } obj = user_creatable_add_type(type, id, pdict, v, &local_err); if (local_err) { goto out_visit; } out_visit: visit_end_struct(v, &end_err); if (end_err) { error_propagate(&local_err, end_err); if (obj) { user_creatable_del(id, NULL); } goto out; } out: QDECREF(pdict); g_free(id); g_free(type); if (local_err) { error_propagate(errp, local_err); object_unref(obj); return NULL; } return obj; }
{ "code": [ " Error *local_err = NULL, *end_err = NULL;", " obj = user_creatable_add_type(type, id, pdict, v, &local_err);", " out_visit:", " visit_end_struct(v, &end_err);", " if (end_err) {", " error_propagate(&local_err, end_err);", " if (obj) {", " user_creatable_del(id, NULL);", " goto out;" ], "line_no": [ 13, 57, 67, 69, 71, 73, 75, 77, 27 ] }
Object *FUNC_0(const QDict *qdict, Visitor *v, Error **errp) { char *VAR_0 = NULL; char *VAR_1 = NULL; Object *obj = NULL; Error *local_err = NULL, *end_err = NULL; QDict *pdict; pdict = qdict_clone_shallow(qdict); visit_start_struct(v, NULL, NULL, 0, &local_err); if (local_err) { goto out; } qdict_del(pdict, "qom-VAR_0"); visit_type_str(v, "qom-VAR_0", &VAR_0, &local_err); if (local_err) { goto out_visit; } qdict_del(pdict, "VAR_1"); visit_type_str(v, "VAR_1", &VAR_1, &local_err); if (local_err) { goto out_visit; } obj = user_creatable_add_type(VAR_0, VAR_1, pdict, v, &local_err); if (local_err) { goto out_visit; } out_visit: visit_end_struct(v, &end_err); if (end_err) { error_propagate(&local_err, end_err); if (obj) { user_creatable_del(VAR_1, NULL); } goto out; } out: QDECREF(pdict); g_free(VAR_1); g_free(VAR_0); if (local_err) { error_propagate(errp, local_err); object_unref(obj); return NULL; } return obj; }
[ "Object *FUNC_0(const QDict *qdict,\nVisitor *v, Error **errp)\n{", "char *VAR_0 = NULL;", "char *VAR_1 = NULL;", "Object *obj = NULL;", "Error *local_err = NULL, *end_err = NULL;", "QDict *pdict;", "pdict = qdict_clone_shallow(qdict);", "visit_start_struct(v, NULL, NULL, 0, &local_err);", "if (local_err) {", "goto out;", "}", "qdict_del(pdict, \"qom-VAR_0\");", "visit_type_str(v, \"qom-VAR_0\", &VAR_0, &local_err);", "if (local_err) {", "goto out_visit;", "}", "qdict_del(pdict, \"VAR_1\");", "visit_type_str(v, \"VAR_1\", &VAR_1, &local_err);", "if (local_err) {", "goto out_visit;", "}", "obj = user_creatable_add_type(VAR_0, VAR_1, pdict, v, &local_err);", "if (local_err) {", "goto out_visit;", "}", "out_visit:\nvisit_end_struct(v, &end_err);", "if (end_err) {", "error_propagate(&local_err, end_err);", "if (obj) {", "user_creatable_del(VAR_1, NULL);", "}", "goto out;", "}", "out:\nQDECREF(pdict);", "g_free(VAR_1);", "g_free(VAR_0);", "if (local_err) {", "error_propagate(errp, local_err);", "object_unref(obj);", "return NULL;", "}", "return obj;", "}" ]
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16,928
int ff_h264_decode_seq_parameter_set(H264Context *h){ MpegEncContext * const s = &h->s; int profile_idc, level_idc, constraint_set_flags = 0; unsigned int sps_id; int i, log2_max_frame_num_minus4; SPS *sps; profile_idc= get_bits(&s->gb, 8); constraint_set_flags |= get_bits1(&s->gb) << 0; //constraint_set0_flag constraint_set_flags |= get_bits1(&s->gb) << 1; //constraint_set1_flag constraint_set_flags |= get_bits1(&s->gb) << 2; //constraint_set2_flag constraint_set_flags |= get_bits1(&s->gb) << 3; //constraint_set3_flag get_bits(&s->gb, 4); // reserved level_idc= get_bits(&s->gb, 8); sps_id= get_ue_golomb_31(&s->gb); if(sps_id >= MAX_SPS_COUNT) { av_log(h->s.avctx, AV_LOG_ERROR, "sps_id (%d) out of range\n", sps_id); return -1; } sps= av_mallocz(sizeof(SPS)); if(sps == NULL) return -1; sps->time_offset_length = 24; sps->profile_idc= profile_idc; sps->constraint_set_flags = constraint_set_flags; sps->level_idc= level_idc; memset(sps->scaling_matrix4, 16, sizeof(sps->scaling_matrix4)); memset(sps->scaling_matrix8, 16, sizeof(sps->scaling_matrix8)); sps->scaling_matrix_present = 0; if(sps->profile_idc >= 100){ //high profile sps->chroma_format_idc= get_ue_golomb_31(&s->gb); if(sps->chroma_format_idc > 3) { av_log(h->s.avctx, AV_LOG_ERROR, "chroma_format_idc (%u) out of range\n", sps->chroma_format_idc); goto fail; } else if(sps->chroma_format_idc == 3) { sps->residual_color_transform_flag = get_bits1(&s->gb); } sps->bit_depth_luma = get_ue_golomb(&s->gb) + 8; sps->bit_depth_chroma = get_ue_golomb(&s->gb) + 8; sps->transform_bypass = get_bits1(&s->gb); decode_scaling_matrices(h, sps, NULL, 1, sps->scaling_matrix4, sps->scaling_matrix8); }else{ sps->chroma_format_idc= 1; sps->bit_depth_luma = 8; sps->bit_depth_chroma = 8; } log2_max_frame_num_minus4 = get_ue_golomb(&s->gb); if (log2_max_frame_num_minus4 < MIN_LOG2_MAX_FRAME_NUM - 4 || log2_max_frame_num_minus4 > MAX_LOG2_MAX_FRAME_NUM - 4) { av_log(h->s.avctx, AV_LOG_ERROR, "log2_max_frame_num_minus4 out of range (0-12): %d\n", log2_max_frame_num_minus4); return AVERROR_INVALIDDATA; } sps->log2_max_frame_num = log2_max_frame_num_minus4 + 4; sps->poc_type= get_ue_golomb_31(&s->gb); if(sps->poc_type == 0){ //FIXME #define sps->log2_max_poc_lsb= get_ue_golomb(&s->gb) + 4; } else if(sps->poc_type == 1){//FIXME #define sps->delta_pic_order_always_zero_flag= get_bits1(&s->gb); sps->offset_for_non_ref_pic= get_se_golomb(&s->gb); sps->offset_for_top_to_bottom_field= get_se_golomb(&s->gb); sps->poc_cycle_length = get_ue_golomb(&s->gb); if((unsigned)sps->poc_cycle_length >= FF_ARRAY_ELEMS(sps->offset_for_ref_frame)){ av_log(h->s.avctx, AV_LOG_ERROR, "poc_cycle_length overflow %u\n", sps->poc_cycle_length); goto fail; } for(i=0; i<sps->poc_cycle_length; i++) sps->offset_for_ref_frame[i]= get_se_golomb(&s->gb); }else if(sps->poc_type != 2){ av_log(h->s.avctx, AV_LOG_ERROR, "illegal POC type %d\n", sps->poc_type); goto fail; } sps->ref_frame_count= get_ue_golomb_31(&s->gb); if(sps->ref_frame_count > MAX_PICTURE_COUNT-2 || sps->ref_frame_count >= 32U){ av_log(h->s.avctx, AV_LOG_ERROR, "too many reference frames\n"); goto fail; } sps->gaps_in_frame_num_allowed_flag= get_bits1(&s->gb); sps->mb_width = get_ue_golomb(&s->gb) + 1; sps->mb_height= get_ue_golomb(&s->gb) + 1; if((unsigned)sps->mb_width >= INT_MAX/16 || (unsigned)sps->mb_height >= INT_MAX/16 || av_image_check_size(16*sps->mb_width, 16*sps->mb_height, 0, h->s.avctx)){ av_log(h->s.avctx, AV_LOG_ERROR, "mb_width/height overflow\n"); goto fail; } sps->frame_mbs_only_flag= get_bits1(&s->gb); if(!sps->frame_mbs_only_flag) sps->mb_aff= get_bits1(&s->gb); else sps->mb_aff= 0; sps->direct_8x8_inference_flag= get_bits1(&s->gb); if(!sps->frame_mbs_only_flag && !sps->direct_8x8_inference_flag){ av_log(h->s.avctx, AV_LOG_ERROR, "This stream was generated by a broken encoder, invalid 8x8 inference\n"); goto fail; } #ifndef ALLOW_INTERLACE if(sps->mb_aff) av_log(h->s.avctx, AV_LOG_ERROR, "MBAFF support not included; enable it at compile-time.\n"); #endif sps->crop= get_bits1(&s->gb); if(sps->crop){ int crop_vertical_limit = sps->chroma_format_idc & 2 ? 16 : 8; int crop_horizontal_limit = sps->chroma_format_idc == 3 ? 16 : 8; sps->crop_left = get_ue_golomb(&s->gb); sps->crop_right = get_ue_golomb(&s->gb); sps->crop_top = get_ue_golomb(&s->gb); sps->crop_bottom= get_ue_golomb(&s->gb); if(sps->crop_left || sps->crop_top){ av_log(h->s.avctx, AV_LOG_ERROR, "insane cropping not completely supported, this could look slightly wrong ...\n"); } if(sps->crop_right >= crop_horizontal_limit || sps->crop_bottom >= crop_vertical_limit){ av_log(h->s.avctx, AV_LOG_ERROR, "brainfart cropping not supported, this could look slightly wrong ...\n"); } }else{ sps->crop_left = sps->crop_right = sps->crop_top = sps->crop_bottom= 0; } sps->vui_parameters_present_flag= get_bits1(&s->gb); if( sps->vui_parameters_present_flag ) if (decode_vui_parameters(h, sps) < 0) goto fail; if(!sps->sar.den) sps->sar.den= 1; if(s->avctx->debug&FF_DEBUG_PICT_INFO){ static const char csp[4][5] = { "Gray", "420", "422", "444" }; av_log(h->s.avctx, AV_LOG_DEBUG, "sps:%u profile:%d/%d poc:%d ref:%d %dx%d %s %s crop:%d/%d/%d/%d %s %s %d/%d\n", sps_id, sps->profile_idc, sps->level_idc, sps->poc_type, sps->ref_frame_count, sps->mb_width, sps->mb_height, sps->frame_mbs_only_flag ? "FRM" : (sps->mb_aff ? "MB-AFF" : "PIC-AFF"), sps->direct_8x8_inference_flag ? "8B8" : "", sps->crop_left, sps->crop_right, sps->crop_top, sps->crop_bottom, sps->vui_parameters_present_flag ? "VUI" : "", csp[sps->chroma_format_idc], sps->timing_info_present_flag ? sps->num_units_in_tick : 0, sps->timing_info_present_flag ? sps->time_scale : 0 ); } av_free(h->sps_buffers[sps_id]); h->sps_buffers[sps_id]= sps; h->sps = *sps; return 0; fail: av_free(sps); return -1; }
true
FFmpeg
072be3e8969f24113d599444be4d6a0ed04a6602
int ff_h264_decode_seq_parameter_set(H264Context *h){ MpegEncContext * const s = &h->s; int profile_idc, level_idc, constraint_set_flags = 0; unsigned int sps_id; int i, log2_max_frame_num_minus4; SPS *sps; profile_idc= get_bits(&s->gb, 8); constraint_set_flags |= get_bits1(&s->gb) << 0; constraint_set_flags |= get_bits1(&s->gb) << 1; constraint_set_flags |= get_bits1(&s->gb) << 2; constraint_set_flags |= get_bits1(&s->gb) << 3; get_bits(&s->gb, 4); level_idc= get_bits(&s->gb, 8); sps_id= get_ue_golomb_31(&s->gb); if(sps_id >= MAX_SPS_COUNT) { av_log(h->s.avctx, AV_LOG_ERROR, "sps_id (%d) out of range\n", sps_id); return -1; } sps= av_mallocz(sizeof(SPS)); if(sps == NULL) return -1; sps->time_offset_length = 24; sps->profile_idc= profile_idc; sps->constraint_set_flags = constraint_set_flags; sps->level_idc= level_idc; memset(sps->scaling_matrix4, 16, sizeof(sps->scaling_matrix4)); memset(sps->scaling_matrix8, 16, sizeof(sps->scaling_matrix8)); sps->scaling_matrix_present = 0; if(sps->profile_idc >= 100){ sps->chroma_format_idc= get_ue_golomb_31(&s->gb); if(sps->chroma_format_idc > 3) { av_log(h->s.avctx, AV_LOG_ERROR, "chroma_format_idc (%u) out of range\n", sps->chroma_format_idc); goto fail; } else if(sps->chroma_format_idc == 3) { sps->residual_color_transform_flag = get_bits1(&s->gb); } sps->bit_depth_luma = get_ue_golomb(&s->gb) + 8; sps->bit_depth_chroma = get_ue_golomb(&s->gb) + 8; sps->transform_bypass = get_bits1(&s->gb); decode_scaling_matrices(h, sps, NULL, 1, sps->scaling_matrix4, sps->scaling_matrix8); }else{ sps->chroma_format_idc= 1; sps->bit_depth_luma = 8; sps->bit_depth_chroma = 8; } log2_max_frame_num_minus4 = get_ue_golomb(&s->gb); if (log2_max_frame_num_minus4 < MIN_LOG2_MAX_FRAME_NUM - 4 || log2_max_frame_num_minus4 > MAX_LOG2_MAX_FRAME_NUM - 4) { av_log(h->s.avctx, AV_LOG_ERROR, "log2_max_frame_num_minus4 out of range (0-12): %d\n", log2_max_frame_num_minus4); return AVERROR_INVALIDDATA; } sps->log2_max_frame_num = log2_max_frame_num_minus4 + 4; sps->poc_type= get_ue_golomb_31(&s->gb); if(sps->poc_type == 0){ sps->log2_max_poc_lsb= get_ue_golomb(&s->gb) + 4; } else if(sps->poc_type == 1){ sps->delta_pic_order_always_zero_flag= get_bits1(&s->gb); sps->offset_for_non_ref_pic= get_se_golomb(&s->gb); sps->offset_for_top_to_bottom_field= get_se_golomb(&s->gb); sps->poc_cycle_length = get_ue_golomb(&s->gb); if((unsigned)sps->poc_cycle_length >= FF_ARRAY_ELEMS(sps->offset_for_ref_frame)){ av_log(h->s.avctx, AV_LOG_ERROR, "poc_cycle_length overflow %u\n", sps->poc_cycle_length); goto fail; } for(i=0; i<sps->poc_cycle_length; i++) sps->offset_for_ref_frame[i]= get_se_golomb(&s->gb); }else if(sps->poc_type != 2){ av_log(h->s.avctx, AV_LOG_ERROR, "illegal POC type %d\n", sps->poc_type); goto fail; } sps->ref_frame_count= get_ue_golomb_31(&s->gb); if(sps->ref_frame_count > MAX_PICTURE_COUNT-2 || sps->ref_frame_count >= 32U){ av_log(h->s.avctx, AV_LOG_ERROR, "too many reference frames\n"); goto fail; } sps->gaps_in_frame_num_allowed_flag= get_bits1(&s->gb); sps->mb_width = get_ue_golomb(&s->gb) + 1; sps->mb_height= get_ue_golomb(&s->gb) + 1; if((unsigned)sps->mb_width >= INT_MAX/16 || (unsigned)sps->mb_height >= INT_MAX/16 || av_image_check_size(16*sps->mb_width, 16*sps->mb_height, 0, h->s.avctx)){ av_log(h->s.avctx, AV_LOG_ERROR, "mb_width/height overflow\n"); goto fail; } sps->frame_mbs_only_flag= get_bits1(&s->gb); if(!sps->frame_mbs_only_flag) sps->mb_aff= get_bits1(&s->gb); else sps->mb_aff= 0; sps->direct_8x8_inference_flag= get_bits1(&s->gb); if(!sps->frame_mbs_only_flag && !sps->direct_8x8_inference_flag){ av_log(h->s.avctx, AV_LOG_ERROR, "This stream was generated by a broken encoder, invalid 8x8 inference\n"); goto fail; } #ifndef ALLOW_INTERLACE if(sps->mb_aff) av_log(h->s.avctx, AV_LOG_ERROR, "MBAFF support not included; enable it at compile-time.\n"); #endif sps->crop= get_bits1(&s->gb); if(sps->crop){ int crop_vertical_limit = sps->chroma_format_idc & 2 ? 16 : 8; int crop_horizontal_limit = sps->chroma_format_idc == 3 ? 16 : 8; sps->crop_left = get_ue_golomb(&s->gb); sps->crop_right = get_ue_golomb(&s->gb); sps->crop_top = get_ue_golomb(&s->gb); sps->crop_bottom= get_ue_golomb(&s->gb); if(sps->crop_left || sps->crop_top){ av_log(h->s.avctx, AV_LOG_ERROR, "insane cropping not completely supported, this could look slightly wrong ...\n"); } if(sps->crop_right >= crop_horizontal_limit || sps->crop_bottom >= crop_vertical_limit){ av_log(h->s.avctx, AV_LOG_ERROR, "brainfart cropping not supported, this could look slightly wrong ...\n"); } }else{ sps->crop_left = sps->crop_right = sps->crop_top = sps->crop_bottom= 0; } sps->vui_parameters_present_flag= get_bits1(&s->gb); if( sps->vui_parameters_present_flag ) if (decode_vui_parameters(h, sps) < 0) goto fail; if(!sps->sar.den) sps->sar.den= 1; if(s->avctx->debug&FF_DEBUG_PICT_INFO){ static const char csp[4][5] = { "Gray", "420", "422", "444" }; av_log(h->s.avctx, AV_LOG_DEBUG, "sps:%u profile:%d/%d poc:%d ref:%d %dx%d %s %s crop:%d/%d/%d/%d %s %s %d/%d\n", sps_id, sps->profile_idc, sps->level_idc, sps->poc_type, sps->ref_frame_count, sps->mb_width, sps->mb_height, sps->frame_mbs_only_flag ? "FRM" : (sps->mb_aff ? "MB-AFF" : "PIC-AFF"), sps->direct_8x8_inference_flag ? "8B8" : "", sps->crop_left, sps->crop_right, sps->crop_top, sps->crop_bottom, sps->vui_parameters_present_flag ? "VUI" : "", csp[sps->chroma_format_idc], sps->timing_info_present_flag ? sps->num_units_in_tick : 0, sps->timing_info_present_flag ? sps->time_scale : 0 ); } av_free(h->sps_buffers[sps_id]); h->sps_buffers[sps_id]= sps; h->sps = *sps; return 0; fail: av_free(sps); return -1; }
{ "code": [ " h->sps_buffers[sps_id]= sps;", " h->sps = *sps;" ], "line_no": [ 323, 325 ] }
int FUNC_0(H264Context *VAR_0){ MpegEncContext * const s = &VAR_0->s; int VAR_1, VAR_2, VAR_3 = 0; unsigned int VAR_4; int VAR_5, VAR_6; SPS *sps; VAR_1= get_bits(&s->gb, 8); VAR_3 |= get_bits1(&s->gb) << 0; VAR_3 |= get_bits1(&s->gb) << 1; VAR_3 |= get_bits1(&s->gb) << 2; VAR_3 |= get_bits1(&s->gb) << 3; get_bits(&s->gb, 4); VAR_2= get_bits(&s->gb, 8); VAR_4= get_ue_golomb_31(&s->gb); if(VAR_4 >= MAX_SPS_COUNT) { av_log(VAR_0->s.avctx, AV_LOG_ERROR, "VAR_4 (%d) out of range\n", VAR_4); return -1; } sps= av_mallocz(sizeof(SPS)); if(sps == NULL) return -1; sps->time_offset_length = 24; sps->VAR_1= VAR_1; sps->VAR_3 = VAR_3; sps->VAR_2= VAR_2; memset(sps->scaling_matrix4, 16, sizeof(sps->scaling_matrix4)); memset(sps->scaling_matrix8, 16, sizeof(sps->scaling_matrix8)); sps->scaling_matrix_present = 0; if(sps->VAR_1 >= 100){ sps->chroma_format_idc= get_ue_golomb_31(&s->gb); if(sps->chroma_format_idc > 3) { av_log(VAR_0->s.avctx, AV_LOG_ERROR, "chroma_format_idc (%u) out of range\n", sps->chroma_format_idc); goto fail; } else if(sps->chroma_format_idc == 3) { sps->residual_color_transform_flag = get_bits1(&s->gb); } sps->bit_depth_luma = get_ue_golomb(&s->gb) + 8; sps->bit_depth_chroma = get_ue_golomb(&s->gb) + 8; sps->transform_bypass = get_bits1(&s->gb); decode_scaling_matrices(VAR_0, sps, NULL, 1, sps->scaling_matrix4, sps->scaling_matrix8); }else{ sps->chroma_format_idc= 1; sps->bit_depth_luma = 8; sps->bit_depth_chroma = 8; } VAR_6 = get_ue_golomb(&s->gb); if (VAR_6 < MIN_LOG2_MAX_FRAME_NUM - 4 || VAR_6 > MAX_LOG2_MAX_FRAME_NUM - 4) { av_log(VAR_0->s.avctx, AV_LOG_ERROR, "VAR_6 out of range (0-12): %d\n", VAR_6); return AVERROR_INVALIDDATA; } sps->log2_max_frame_num = VAR_6 + 4; sps->poc_type= get_ue_golomb_31(&s->gb); if(sps->poc_type == 0){ sps->log2_max_poc_lsb= get_ue_golomb(&s->gb) + 4; } else if(sps->poc_type == 1){ sps->delta_pic_order_always_zero_flag= get_bits1(&s->gb); sps->offset_for_non_ref_pic= get_se_golomb(&s->gb); sps->offset_for_top_to_bottom_field= get_se_golomb(&s->gb); sps->poc_cycle_length = get_ue_golomb(&s->gb); if((unsigned)sps->poc_cycle_length >= FF_ARRAY_ELEMS(sps->offset_for_ref_frame)){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "poc_cycle_length overflow %u\n", sps->poc_cycle_length); goto fail; } for(VAR_5=0; VAR_5<sps->poc_cycle_length; VAR_5++) sps->offset_for_ref_frame[VAR_5]= get_se_golomb(&s->gb); }else if(sps->poc_type != 2){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "illegal POC type %d\n", sps->poc_type); goto fail; } sps->ref_frame_count= get_ue_golomb_31(&s->gb); if(sps->ref_frame_count > MAX_PICTURE_COUNT-2 || sps->ref_frame_count >= 32U){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "too many reference frames\n"); goto fail; } sps->gaps_in_frame_num_allowed_flag= get_bits1(&s->gb); sps->mb_width = get_ue_golomb(&s->gb) + 1; sps->mb_height= get_ue_golomb(&s->gb) + 1; if((unsigned)sps->mb_width >= INT_MAX/16 || (unsigned)sps->mb_height >= INT_MAX/16 || av_image_check_size(16*sps->mb_width, 16*sps->mb_height, 0, VAR_0->s.avctx)){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "mb_width/height overflow\n"); goto fail; } sps->frame_mbs_only_flag= get_bits1(&s->gb); if(!sps->frame_mbs_only_flag) sps->mb_aff= get_bits1(&s->gb); else sps->mb_aff= 0; sps->direct_8x8_inference_flag= get_bits1(&s->gb); if(!sps->frame_mbs_only_flag && !sps->direct_8x8_inference_flag){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "This stream was generated by a broken encoder, invalid 8x8 inference\n"); goto fail; } #ifndef ALLOW_INTERLACE if(sps->mb_aff) av_log(VAR_0->s.avctx, AV_LOG_ERROR, "MBAFF support not included; enable it at compile-time.\n"); #endif sps->crop= get_bits1(&s->gb); if(sps->crop){ int VAR_7 = sps->chroma_format_idc & 2 ? 16 : 8; int VAR_8 = sps->chroma_format_idc == 3 ? 16 : 8; sps->crop_left = get_ue_golomb(&s->gb); sps->crop_right = get_ue_golomb(&s->gb); sps->crop_top = get_ue_golomb(&s->gb); sps->crop_bottom= get_ue_golomb(&s->gb); if(sps->crop_left || sps->crop_top){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "insane cropping not completely supported, this could look slightly wrong ...\n"); } if(sps->crop_right >= VAR_8 || sps->crop_bottom >= VAR_7){ av_log(VAR_0->s.avctx, AV_LOG_ERROR, "brainfart cropping not supported, this could look slightly wrong ...\n"); } }else{ sps->crop_left = sps->crop_right = sps->crop_top = sps->crop_bottom= 0; } sps->vui_parameters_present_flag= get_bits1(&s->gb); if( sps->vui_parameters_present_flag ) if (decode_vui_parameters(VAR_0, sps) < 0) goto fail; if(!sps->sar.den) sps->sar.den= 1; if(s->avctx->debug&FF_DEBUG_PICT_INFO){ static const char VAR_9[4][5] = { "Gray", "420", "422", "444" }; av_log(VAR_0->s.avctx, AV_LOG_DEBUG, "sps:%u profile:%d/%d poc:%d ref:%d %dx%d %s %s crop:%d/%d/%d/%d %s %s %d/%d\n", VAR_4, sps->VAR_1, sps->VAR_2, sps->poc_type, sps->ref_frame_count, sps->mb_width, sps->mb_height, sps->frame_mbs_only_flag ? "FRM" : (sps->mb_aff ? "MB-AFF" : "PIC-AFF"), sps->direct_8x8_inference_flag ? "8B8" : "", sps->crop_left, sps->crop_right, sps->crop_top, sps->crop_bottom, sps->vui_parameters_present_flag ? "VUI" : "", VAR_9[sps->chroma_format_idc], sps->timing_info_present_flag ? sps->num_units_in_tick : 0, sps->timing_info_present_flag ? sps->time_scale : 0 ); } av_free(VAR_0->sps_buffers[VAR_4]); VAR_0->sps_buffers[VAR_4]= sps; VAR_0->sps = *sps; return 0; fail: av_free(sps); return -1; }
[ "int FUNC_0(H264Context *VAR_0){", "MpegEncContext * const s = &VAR_0->s;", "int VAR_1, VAR_2, VAR_3 = 0;", "unsigned int VAR_4;", "int VAR_5, VAR_6;", "SPS *sps;", "VAR_1= get_bits(&s->gb, 8);", "VAR_3 |= get_bits1(&s->gb) << 0;", "VAR_3 |= get_bits1(&s->gb) << 1;", "VAR_3 |= get_bits1(&s->gb) << 2;", "VAR_3 |= get_bits1(&s->gb) << 3;", "get_bits(&s->gb, 4);", "VAR_2= get_bits(&s->gb, 8);", "VAR_4= get_ue_golomb_31(&s->gb);", "if(VAR_4 >= MAX_SPS_COUNT) {", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"VAR_4 (%d) out of range\\n\", VAR_4);", "return -1;", "}", "sps= av_mallocz(sizeof(SPS));", "if(sps == NULL)\nreturn -1;", "sps->time_offset_length = 24;", "sps->VAR_1= VAR_1;", "sps->VAR_3 = VAR_3;", "sps->VAR_2= VAR_2;", "memset(sps->scaling_matrix4, 16, sizeof(sps->scaling_matrix4));", "memset(sps->scaling_matrix8, 16, sizeof(sps->scaling_matrix8));", "sps->scaling_matrix_present = 0;", "if(sps->VAR_1 >= 100){", "sps->chroma_format_idc= get_ue_golomb_31(&s->gb);", "if(sps->chroma_format_idc > 3) {", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"chroma_format_idc (%u) out of range\\n\", sps->chroma_format_idc);", "goto fail;", "} else if(sps->chroma_format_idc == 3) {", "sps->residual_color_transform_flag = get_bits1(&s->gb);", "}", "sps->bit_depth_luma = get_ue_golomb(&s->gb) + 8;", "sps->bit_depth_chroma = get_ue_golomb(&s->gb) + 8;", "sps->transform_bypass = get_bits1(&s->gb);", "decode_scaling_matrices(VAR_0, sps, NULL, 1, sps->scaling_matrix4, sps->scaling_matrix8);", "}else{", "sps->chroma_format_idc= 1;", "sps->bit_depth_luma = 8;", "sps->bit_depth_chroma = 8;", "}", "VAR_6 = get_ue_golomb(&s->gb);", "if (VAR_6 < MIN_LOG2_MAX_FRAME_NUM - 4 ||\nVAR_6 > MAX_LOG2_MAX_FRAME_NUM - 4) {", "av_log(VAR_0->s.avctx, AV_LOG_ERROR,\n\"VAR_6 out of range (0-12): %d\\n\",\nVAR_6);", "return AVERROR_INVALIDDATA;", "}", "sps->log2_max_frame_num = VAR_6 + 4;", "sps->poc_type= get_ue_golomb_31(&s->gb);", "if(sps->poc_type == 0){", "sps->log2_max_poc_lsb= get_ue_golomb(&s->gb) + 4;", "} else if(sps->poc_type == 1){", "sps->delta_pic_order_always_zero_flag= get_bits1(&s->gb);", "sps->offset_for_non_ref_pic= get_se_golomb(&s->gb);", "sps->offset_for_top_to_bottom_field= get_se_golomb(&s->gb);", "sps->poc_cycle_length = get_ue_golomb(&s->gb);", "if((unsigned)sps->poc_cycle_length >= FF_ARRAY_ELEMS(sps->offset_for_ref_frame)){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"poc_cycle_length overflow %u\\n\", sps->poc_cycle_length);", "goto fail;", "}", "for(VAR_5=0; VAR_5<sps->poc_cycle_length; VAR_5++)", "sps->offset_for_ref_frame[VAR_5]= get_se_golomb(&s->gb);", "}else if(sps->poc_type != 2){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"illegal POC type %d\\n\", sps->poc_type);", "goto fail;", "}", "sps->ref_frame_count= get_ue_golomb_31(&s->gb);", "if(sps->ref_frame_count > MAX_PICTURE_COUNT-2 || sps->ref_frame_count >= 32U){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"too many reference frames\\n\");", "goto fail;", "}", "sps->gaps_in_frame_num_allowed_flag= get_bits1(&s->gb);", "sps->mb_width = get_ue_golomb(&s->gb) + 1;", "sps->mb_height= get_ue_golomb(&s->gb) + 1;", "if((unsigned)sps->mb_width >= INT_MAX/16 || (unsigned)sps->mb_height >= INT_MAX/16 ||\nav_image_check_size(16*sps->mb_width, 16*sps->mb_height, 0, VAR_0->s.avctx)){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"mb_width/height overflow\\n\");", "goto fail;", "}", "sps->frame_mbs_only_flag= get_bits1(&s->gb);", "if(!sps->frame_mbs_only_flag)\nsps->mb_aff= get_bits1(&s->gb);", "else\nsps->mb_aff= 0;", "sps->direct_8x8_inference_flag= get_bits1(&s->gb);", "if(!sps->frame_mbs_only_flag && !sps->direct_8x8_inference_flag){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"This stream was generated by a broken encoder, invalid 8x8 inference\\n\");", "goto fail;", "}", "#ifndef ALLOW_INTERLACE\nif(sps->mb_aff)\nav_log(VAR_0->s.avctx, AV_LOG_ERROR, \"MBAFF support not included; enable it at compile-time.\\n\");", "#endif\nsps->crop= get_bits1(&s->gb);", "if(sps->crop){", "int VAR_7 = sps->chroma_format_idc & 2 ? 16 : 8;", "int VAR_8 = sps->chroma_format_idc == 3 ? 16 : 8;", "sps->crop_left = get_ue_golomb(&s->gb);", "sps->crop_right = get_ue_golomb(&s->gb);", "sps->crop_top = get_ue_golomb(&s->gb);", "sps->crop_bottom= get_ue_golomb(&s->gb);", "if(sps->crop_left || sps->crop_top){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"insane cropping not completely supported, this could look slightly wrong ...\\n\");", "}", "if(sps->crop_right >= VAR_8 || sps->crop_bottom >= VAR_7){", "av_log(VAR_0->s.avctx, AV_LOG_ERROR, \"brainfart cropping not supported, this could look slightly wrong ...\\n\");", "}", "}else{", "sps->crop_left =\nsps->crop_right =\nsps->crop_top =\nsps->crop_bottom= 0;", "}", "sps->vui_parameters_present_flag= get_bits1(&s->gb);", "if( sps->vui_parameters_present_flag )\nif (decode_vui_parameters(VAR_0, sps) < 0)\ngoto fail;", "if(!sps->sar.den)\nsps->sar.den= 1;", "if(s->avctx->debug&FF_DEBUG_PICT_INFO){", "static const char VAR_9[4][5] = { \"Gray\", \"420\", \"422\", \"444\" };", "av_log(VAR_0->s.avctx, AV_LOG_DEBUG, \"sps:%u profile:%d/%d poc:%d ref:%d %dx%d %s %s crop:%d/%d/%d/%d %s %s %d/%d\\n\",\nVAR_4, sps->VAR_1, sps->VAR_2,\nsps->poc_type,\nsps->ref_frame_count,\nsps->mb_width, sps->mb_height,\nsps->frame_mbs_only_flag ? \"FRM\" : (sps->mb_aff ? \"MB-AFF\" : \"PIC-AFF\"),\nsps->direct_8x8_inference_flag ? \"8B8\" : \"\",\nsps->crop_left, sps->crop_right,\nsps->crop_top, sps->crop_bottom,\nsps->vui_parameters_present_flag ? \"VUI\" : \"\",\nVAR_9[sps->chroma_format_idc],\nsps->timing_info_present_flag ? sps->num_units_in_tick : 0,\nsps->timing_info_present_flag ? sps->time_scale : 0\n);", "}", "av_free(VAR_0->sps_buffers[VAR_4]);", "VAR_0->sps_buffers[VAR_4]= sps;", "VAR_0->sps = *sps;", "return 0;", "fail:\nav_free(sps);", "return -1;", "}" ]
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16,929
void do_compute_hflags (CPUPPCState *env) { /* Compute current hflags */ env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) | (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) | (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_se << MSR_SE) | (msr_be << MSR_BE); #if defined (TARGET_PPC64) env->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV); #endif }
true
qemu
d9bce9d99f4656ae0b0127f7472db9067b8f84ab
void do_compute_hflags (CPUPPCState *env) { env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) | (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) | (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_se << MSR_SE) | (msr_be << MSR_BE); #if defined (TARGET_PPC64) env->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV); #endif }
{ "code": [ " (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | ", " env->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV);", "#endif", "#endif" ], "line_no": [ 11, 17, 19, 19 ] }
void FUNC_0 (CPUPPCState *VAR_0) { VAR_0->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) | (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) | (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_se << MSR_SE) | (msr_be << MSR_BE); #if defined (TARGET_PPC64) VAR_0->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV); #endif }
[ "void FUNC_0 (CPUPPCState *VAR_0)\n{", "VAR_0->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |\n(msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |\n(msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |\n(msr_se << MSR_SE) | (msr_be << MSR_BE);", "#if defined (TARGET_PPC64)\nVAR_0->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV);", "#endif\n}" ]
[ 0, 1, 1, 1 ]
[ [ 1, 3 ], [ 7, 9, 11, 13 ], [ 15, 17 ], [ 19, 21 ] ]
16,931
static void bonito_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = bonito_initfn; k->vendor_id = 0xdf53; k->device_id = 0x00d5; k->revision = 0x01; k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "Host bridge"; dc->no_user = 1; dc->vmsd = &vmstate_bonito; }
true
qemu
efec3dd631d94160288392721a5f9c39e50fb2bc
static void bonito_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = bonito_initfn; k->vendor_id = 0xdf53; k->device_id = 0x00d5; k->revision = 0x01; k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "Host bridge"; dc->no_user = 1; dc->vmsd = &vmstate_bonito; }
{ "code": [ " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;", " dc->no_user = 1;" ], "line_no": [ 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, 23 ] }
static void FUNC_0(ObjectClass *VAR_0, void *VAR_1) { DeviceClass *dc = DEVICE_CLASS(VAR_0); PCIDeviceClass *k = PCI_DEVICE_CLASS(VAR_0); k->init = bonito_initfn; k->vendor_id = 0xdf53; k->device_id = 0x00d5; k->revision = 0x01; k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "Host bridge"; dc->no_user = 1; dc->vmsd = &vmstate_bonito; }
[ "static void FUNC_0(ObjectClass *VAR_0, void *VAR_1)\n{", "DeviceClass *dc = DEVICE_CLASS(VAR_0);", "PCIDeviceClass *k = PCI_DEVICE_CLASS(VAR_0);", "k->init = bonito_initfn;", "k->vendor_id = 0xdf53;", "k->device_id = 0x00d5;", "k->revision = 0x01;", "k->class_id = PCI_CLASS_BRIDGE_HOST;", "dc->desc = \"Host bridge\";", "dc->no_user = 1;", "dc->vmsd = &vmstate_bonito;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ], [ 25 ], [ 27 ] ]
16,934
static void kvm_apic_realize(DeviceState *dev, Error **errp) { APICCommonState *s = APIC_COMMON(dev); memory_region_init_io(&s->io_memory, NULL, &kvm_apic_io_ops, s, "kvm-apic-msi", APIC_SPACE_SIZE); if (kvm_has_gsi_routing()) { msi_nonbroken = true; } }
true
qemu
365aa1131fa61815eb1d672df6ba451bfe7f2cea
static void kvm_apic_realize(DeviceState *dev, Error **errp) { APICCommonState *s = APIC_COMMON(dev); memory_region_init_io(&s->io_memory, NULL, &kvm_apic_io_ops, s, "kvm-apic-msi", APIC_SPACE_SIZE); if (kvm_has_gsi_routing()) { msi_nonbroken = true; } }
{ "code": [ " memory_region_init_io(&s->io_memory, NULL, &kvm_apic_io_ops, s, \"kvm-apic-msi\",", " APIC_SPACE_SIZE);" ], "line_no": [ 9, 11 ] }
static void FUNC_0(DeviceState *VAR_0, Error **VAR_1) { APICCommonState *s = APIC_COMMON(VAR_0); memory_region_init_io(&s->io_memory, NULL, &kvm_apic_io_ops, s, "kvm-apic-msi", APIC_SPACE_SIZE); if (kvm_has_gsi_routing()) { msi_nonbroken = true; } }
[ "static void FUNC_0(DeviceState *VAR_0, Error **VAR_1)\n{", "APICCommonState *s = APIC_COMMON(VAR_0);", "memory_region_init_io(&s->io_memory, NULL, &kvm_apic_io_ops, s, \"kvm-apic-msi\",\nAPIC_SPACE_SIZE);", "if (kvm_has_gsi_routing()) {", "msi_nonbroken = true;", "}", "}" ]
[ 0, 0, 1, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9, 11 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ] ]
16,935
static uint64_t *l2_allocate(BlockDriverState *bs, int l1_index) { BDRVQcowState *s = bs->opaque; int min_index; uint64_t old_l2_offset; uint64_t *l2_table, l2_offset; old_l2_offset = s->l1_table[l1_index]; /* allocate a new l2 entry */ l2_offset = qcow2_alloc_clusters(bs, s->l2_size * sizeof(uint64_t)); if (l2_offset < 0) { return NULL; } /* update the L1 entry */ s->l1_table[l1_index] = l2_offset | QCOW_OFLAG_COPIED; if (write_l1_entry(s, l1_index) < 0) { return NULL; } /* allocate a new entry in the l2 cache */ min_index = l2_cache_new_entry(bs); l2_table = s->l2_cache + (min_index << s->l2_bits); if (old_l2_offset == 0) { /* if there was no old l2 table, clear the new table */ memset(l2_table, 0, s->l2_size * sizeof(uint64_t)); } else { /* if there was an old l2 table, read it from the disk */ if (bdrv_pread(s->hd, old_l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return NULL; } /* write the l2 table to the file */ if (bdrv_pwrite(s->hd, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return NULL; /* update the l2 cache entry */ s->l2_cache_offsets[min_index] = l2_offset; s->l2_cache_counts[min_index] = 1; return l2_table; }
true
qemu
f4f0d391b26afcce86df85566788be7170127116
static uint64_t *l2_allocate(BlockDriverState *bs, int l1_index) { BDRVQcowState *s = bs->opaque; int min_index; uint64_t old_l2_offset; uint64_t *l2_table, l2_offset; old_l2_offset = s->l1_table[l1_index]; l2_offset = qcow2_alloc_clusters(bs, s->l2_size * sizeof(uint64_t)); if (l2_offset < 0) { return NULL; } s->l1_table[l1_index] = l2_offset | QCOW_OFLAG_COPIED; if (write_l1_entry(s, l1_index) < 0) { return NULL; } min_index = l2_cache_new_entry(bs); l2_table = s->l2_cache + (min_index << s->l2_bits); if (old_l2_offset == 0) { memset(l2_table, 0, s->l2_size * sizeof(uint64_t)); } else { if (bdrv_pread(s->hd, old_l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return NULL; } if (bdrv_pwrite(s->hd, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return NULL; s->l2_cache_offsets[min_index] = l2_offset; s->l2_cache_counts[min_index] = 1; return l2_table; }
{ "code": [ " uint64_t *l2_table, l2_offset;" ], "line_no": [ 11 ] }
static uint64_t *FUNC_0(BlockDriverState *bs, int l1_index) { BDRVQcowState *s = bs->opaque; int VAR_0; uint64_t old_l2_offset; uint64_t *l2_table, l2_offset; old_l2_offset = s->l1_table[l1_index]; l2_offset = qcow2_alloc_clusters(bs, s->l2_size * sizeof(uint64_t)); if (l2_offset < 0) { return NULL; } s->l1_table[l1_index] = l2_offset | QCOW_OFLAG_COPIED; if (write_l1_entry(s, l1_index) < 0) { return NULL; } VAR_0 = l2_cache_new_entry(bs); l2_table = s->l2_cache + (VAR_0 << s->l2_bits); if (old_l2_offset == 0) { memset(l2_table, 0, s->l2_size * sizeof(uint64_t)); } else { if (bdrv_pread(s->hd, old_l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return NULL; } if (bdrv_pwrite(s->hd, l2_offset, l2_table, s->l2_size * sizeof(uint64_t)) != s->l2_size * sizeof(uint64_t)) return NULL; s->l2_cache_offsets[VAR_0] = l2_offset; s->l2_cache_counts[VAR_0] = 1; return l2_table; }
[ "static uint64_t *FUNC_0(BlockDriverState *bs, int l1_index)\n{", "BDRVQcowState *s = bs->opaque;", "int VAR_0;", "uint64_t old_l2_offset;", "uint64_t *l2_table, l2_offset;", "old_l2_offset = s->l1_table[l1_index];", "l2_offset = qcow2_alloc_clusters(bs, s->l2_size * sizeof(uint64_t));", "if (l2_offset < 0) {", "return NULL;", "}", "s->l1_table[l1_index] = l2_offset | QCOW_OFLAG_COPIED;", "if (write_l1_entry(s, l1_index) < 0) {", "return NULL;", "}", "VAR_0 = l2_cache_new_entry(bs);", "l2_table = s->l2_cache + (VAR_0 << s->l2_bits);", "if (old_l2_offset == 0) {", "memset(l2_table, 0, s->l2_size * sizeof(uint64_t));", "} else {", "if (bdrv_pread(s->hd, old_l2_offset,\nl2_table, s->l2_size * sizeof(uint64_t)) !=\ns->l2_size * sizeof(uint64_t))\nreturn NULL;", "}", "if (bdrv_pwrite(s->hd, l2_offset,\nl2_table, s->l2_size * sizeof(uint64_t)) !=\ns->l2_size * sizeof(uint64_t))\nreturn NULL;", "s->l2_cache_offsets[VAR_0] = l2_offset;", "s->l2_cache_counts[VAR_0] = 1;", "return l2_table;", "}" ]
[ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 15 ], [ 23 ], [ 25 ], [ 27 ], [ 29 ], [ 37 ], [ 39 ], [ 41 ], [ 43 ], [ 51 ], [ 53 ], [ 57 ], [ 61 ], [ 63 ], [ 67, 69, 71, 73 ], [ 75 ], [ 79, 81, 83, 85 ], [ 93 ], [ 95 ], [ 99 ], [ 101 ] ]
16,936
static inline int op(uint8_t **dst, const uint8_t *dst_end, const uint8_t **buf, const uint8_t *buf_end, int pixel, int count, int *x, int width, int linesize) { int remaining = width - *x; while(count > 0) { int striplen = FFMIN(count, remaining); if (buf) { striplen = FFMIN(striplen, buf_end - *buf); if (*buf >= buf_end) goto exhausted; memcpy(*dst, *buf, striplen); *buf += striplen; } else if (pixel >= 0) memset(*dst, pixel, striplen); *dst += striplen; remaining -= striplen; count -= striplen; if (remaining <= 0) { *dst += linesize - width; remaining = width; } if (linesize > 0) { if (*dst >= dst_end) goto exhausted; } else { if (*dst <= dst_end) goto exhausted; } } *x = width - remaining; return 0; exhausted: *x = width - remaining; return 1; }
true
FFmpeg
5b4d026a030a775f0bd287e3a27188e8b5c9009f
static inline int op(uint8_t **dst, const uint8_t *dst_end, const uint8_t **buf, const uint8_t *buf_end, int pixel, int count, int *x, int width, int linesize) { int remaining = width - *x; while(count > 0) { int striplen = FFMIN(count, remaining); if (buf) { striplen = FFMIN(striplen, buf_end - *buf); if (*buf >= buf_end) goto exhausted; memcpy(*dst, *buf, striplen); *buf += striplen; } else if (pixel >= 0) memset(*dst, pixel, striplen); *dst += striplen; remaining -= striplen; count -= striplen; if (remaining <= 0) { *dst += linesize - width; remaining = width; } if (linesize > 0) { if (*dst >= dst_end) goto exhausted; } else { if (*dst <= dst_end) goto exhausted; } } *x = width - remaining; return 0; exhausted: *x = width - remaining; return 1; }
{ "code": [ " const uint8_t **buf, const uint8_t *buf_end,", " if (buf) {", " striplen = FFMIN(striplen, buf_end - *buf);", " if (*buf >= buf_end)", " memcpy(*dst, *buf, striplen);", " *buf += striplen;" ], "line_no": [ 3, 17, 19, 21, 25, 27 ] }
static inline int FUNC_0(uint8_t **VAR_0, const uint8_t *VAR_1, const uint8_t **VAR_2, const uint8_t *VAR_3, int VAR_4, int VAR_5, int *VAR_6, int VAR_7, int VAR_8) { int VAR_9 = VAR_7 - *VAR_6; while(VAR_5 > 0) { int VAR_10 = FFMIN(VAR_5, VAR_9); if (VAR_2) { VAR_10 = FFMIN(VAR_10, VAR_3 - *VAR_2); if (*VAR_2 >= VAR_3) goto exhausted; memcpy(*VAR_0, *VAR_2, VAR_10); *VAR_2 += VAR_10; } else if (VAR_4 >= 0) memset(*VAR_0, VAR_4, VAR_10); *VAR_0 += VAR_10; VAR_9 -= VAR_10; VAR_5 -= VAR_10; if (VAR_9 <= 0) { *VAR_0 += VAR_8 - VAR_7; VAR_9 = VAR_7; } if (VAR_8 > 0) { if (*VAR_0 >= VAR_1) goto exhausted; } else { if (*VAR_0 <= VAR_1) goto exhausted; } } *VAR_6 = VAR_7 - VAR_9; return 0; exhausted: *VAR_6 = VAR_7 - VAR_9; return 1; }
[ "static inline int FUNC_0(uint8_t **VAR_0, const uint8_t *VAR_1,\nconst uint8_t **VAR_2, const uint8_t *VAR_3,\nint VAR_4, int VAR_5,\nint *VAR_6, int VAR_7, int VAR_8)\n{", "int VAR_9 = VAR_7 - *VAR_6;", "while(VAR_5 > 0) {", "int VAR_10 = FFMIN(VAR_5, VAR_9);", "if (VAR_2) {", "VAR_10 = FFMIN(VAR_10, VAR_3 - *VAR_2);", "if (*VAR_2 >= VAR_3)\ngoto exhausted;", "memcpy(*VAR_0, *VAR_2, VAR_10);", "*VAR_2 += VAR_10;", "} else if (VAR_4 >= 0)", "memset(*VAR_0, VAR_4, VAR_10);", "*VAR_0 += VAR_10;", "VAR_9 -= VAR_10;", "VAR_5 -= VAR_10;", "if (VAR_9 <= 0) {", "*VAR_0 += VAR_8 - VAR_7;", "VAR_9 = VAR_7;", "}", "if (VAR_8 > 0) {", "if (*VAR_0 >= VAR_1) goto exhausted;", "} else {", "if (*VAR_0 <= VAR_1) goto exhausted;", "}", "}", "*VAR_6 = VAR_7 - VAR_9;", "return 0;", "exhausted:\n*VAR_6 = VAR_7 - VAR_9;", "return 1;", "}" ]
[ 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5, 7, 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21, 23 ], [ 25 ], [ 27 ], [ 29 ], [ 31 ], [ 33 ], [ 35 ], [ 37 ], [ 39 ], [ 41 ], [ 43 ], [ 45 ], [ 47 ], [ 49 ], [ 51 ], [ 53 ], [ 55 ], [ 57 ], [ 59 ], [ 61 ], [ 65, 67 ], [ 69 ], [ 71 ] ]
16,937
static void ra144_encode_subblock(RA144Context *ractx, const int16_t *sblock_data, const int16_t *lpc_coefs, unsigned int rms, PutBitContext *pb) { float data[BLOCKSIZE] = { 0 }, work[LPC_ORDER + BLOCKSIZE]; float coefs[LPC_ORDER]; float zero[BLOCKSIZE], cba[BLOCKSIZE], cb1[BLOCKSIZE], cb2[BLOCKSIZE]; int16_t cba_vect[BLOCKSIZE]; int cba_idx, cb1_idx, cb2_idx, gain; int i, n; unsigned m[3]; float g[3]; float error, best_error; for (i = 0; i < LPC_ORDER; i++) { work[i] = ractx->curr_sblock[BLOCKSIZE + i]; coefs[i] = lpc_coefs[i] * (1/4096.0); } /** * Calculate the zero-input response of the LPC filter and subtract it from * input data. */ ff_celp_lp_synthesis_filterf(work + LPC_ORDER, coefs, data, BLOCKSIZE, LPC_ORDER); for (i = 0; i < BLOCKSIZE; i++) { zero[i] = work[LPC_ORDER + i]; data[i] = sblock_data[i] - zero[i]; } /** * Codebook search is performed without taking into account the contribution * of the previous subblock, since it has been just subtracted from input * data. */ memset(work, 0, LPC_ORDER * sizeof(*work)); cba_idx = adaptive_cb_search(ractx->adapt_cb, work + LPC_ORDER, coefs, data); if (cba_idx) { /** * The filtered vector from the adaptive codebook can be retrieved from * work, see implementation of adaptive_cb_search(). */ memcpy(cba, work + LPC_ORDER, sizeof(cba)); ff_copy_and_dup(cba_vect, ractx->adapt_cb, cba_idx + BLOCKSIZE / 2 - 1); m[0] = (ff_irms(cba_vect) * rms) >> 12; } fixed_cb_search(work + LPC_ORDER, coefs, data, cba_idx, &cb1_idx, &cb2_idx); for (i = 0; i < BLOCKSIZE; i++) { cb1[i] = ff_cb1_vects[cb1_idx][i]; cb2[i] = ff_cb2_vects[cb2_idx][i]; } ff_celp_lp_synthesis_filterf(work + LPC_ORDER, coefs, cb1, BLOCKSIZE, LPC_ORDER); memcpy(cb1, work + LPC_ORDER, sizeof(cb1)); m[1] = (ff_cb1_base[cb1_idx] * rms) >> 8; ff_celp_lp_synthesis_filterf(work + LPC_ORDER, coefs, cb2, BLOCKSIZE, LPC_ORDER); memcpy(cb2, work + LPC_ORDER, sizeof(cb2)); m[2] = (ff_cb2_base[cb2_idx] * rms) >> 8; best_error = FLT_MAX; gain = 0; for (n = 0; n < 256; n++) { g[1] = ((ff_gain_val_tab[n][1] * m[1]) >> ff_gain_exp_tab[n]) * (1/4096.0); g[2] = ((ff_gain_val_tab[n][2] * m[2]) >> ff_gain_exp_tab[n]) * (1/4096.0); error = 0; if (cba_idx) { g[0] = ((ff_gain_val_tab[n][0] * m[0]) >> ff_gain_exp_tab[n]) * (1/4096.0); for (i = 0; i < BLOCKSIZE; i++) { data[i] = zero[i] + g[0] * cba[i] + g[1] * cb1[i] + g[2] * cb2[i]; error += (data[i] - sblock_data[i]) * (data[i] - sblock_data[i]); } } else { for (i = 0; i < BLOCKSIZE; i++) { data[i] = zero[i] + g[1] * cb1[i] + g[2] * cb2[i]; error += (data[i] - sblock_data[i]) * (data[i] - sblock_data[i]); } } if (error < best_error) { best_error = error; gain = n; } } put_bits(pb, 7, cba_idx); put_bits(pb, 8, gain); put_bits(pb, 7, cb1_idx); put_bits(pb, 7, cb2_idx); ff_subblock_synthesis(ractx, lpc_coefs, cba_idx, cb1_idx, cb2_idx, rms, gain); }
true
FFmpeg
c3390fd56cf55259ea7665ecea6c8aeddf56e2fc
static void ra144_encode_subblock(RA144Context *ractx, const int16_t *sblock_data, const int16_t *lpc_coefs, unsigned int rms, PutBitContext *pb) { float data[BLOCKSIZE] = { 0 }, work[LPC_ORDER + BLOCKSIZE]; float coefs[LPC_ORDER]; float zero[BLOCKSIZE], cba[BLOCKSIZE], cb1[BLOCKSIZE], cb2[BLOCKSIZE]; int16_t cba_vect[BLOCKSIZE]; int cba_idx, cb1_idx, cb2_idx, gain; int i, n; unsigned m[3]; float g[3]; float error, best_error; for (i = 0; i < LPC_ORDER; i++) { work[i] = ractx->curr_sblock[BLOCKSIZE + i]; coefs[i] = lpc_coefs[i] * (1/4096.0); } ff_celp_lp_synthesis_filterf(work + LPC_ORDER, coefs, data, BLOCKSIZE, LPC_ORDER); for (i = 0; i < BLOCKSIZE; i++) { zero[i] = work[LPC_ORDER + i]; data[i] = sblock_data[i] - zero[i]; } memset(work, 0, LPC_ORDER * sizeof(*work)); cba_idx = adaptive_cb_search(ractx->adapt_cb, work + LPC_ORDER, coefs, data); if (cba_idx) { memcpy(cba, work + LPC_ORDER, sizeof(cba)); ff_copy_and_dup(cba_vect, ractx->adapt_cb, cba_idx + BLOCKSIZE / 2 - 1); m[0] = (ff_irms(cba_vect) * rms) >> 12; } fixed_cb_search(work + LPC_ORDER, coefs, data, cba_idx, &cb1_idx, &cb2_idx); for (i = 0; i < BLOCKSIZE; i++) { cb1[i] = ff_cb1_vects[cb1_idx][i]; cb2[i] = ff_cb2_vects[cb2_idx][i]; } ff_celp_lp_synthesis_filterf(work + LPC_ORDER, coefs, cb1, BLOCKSIZE, LPC_ORDER); memcpy(cb1, work + LPC_ORDER, sizeof(cb1)); m[1] = (ff_cb1_base[cb1_idx] * rms) >> 8; ff_celp_lp_synthesis_filterf(work + LPC_ORDER, coefs, cb2, BLOCKSIZE, LPC_ORDER); memcpy(cb2, work + LPC_ORDER, sizeof(cb2)); m[2] = (ff_cb2_base[cb2_idx] * rms) >> 8; best_error = FLT_MAX; gain = 0; for (n = 0; n < 256; n++) { g[1] = ((ff_gain_val_tab[n][1] * m[1]) >> ff_gain_exp_tab[n]) * (1/4096.0); g[2] = ((ff_gain_val_tab[n][2] * m[2]) >> ff_gain_exp_tab[n]) * (1/4096.0); error = 0; if (cba_idx) { g[0] = ((ff_gain_val_tab[n][0] * m[0]) >> ff_gain_exp_tab[n]) * (1/4096.0); for (i = 0; i < BLOCKSIZE; i++) { data[i] = zero[i] + g[0] * cba[i] + g[1] * cb1[i] + g[2] * cb2[i]; error += (data[i] - sblock_data[i]) * (data[i] - sblock_data[i]); } } else { for (i = 0; i < BLOCKSIZE; i++) { data[i] = zero[i] + g[1] * cb1[i] + g[2] * cb2[i]; error += (data[i] - sblock_data[i]) * (data[i] - sblock_data[i]); } } if (error < best_error) { best_error = error; gain = n; } } put_bits(pb, 7, cba_idx); put_bits(pb, 8, gain); put_bits(pb, 7, cb1_idx); put_bits(pb, 7, cb2_idx); ff_subblock_synthesis(ractx, lpc_coefs, cba_idx, cb1_idx, cb2_idx, rms, gain); }
{ "code": [ " int16_t cba_vect[BLOCKSIZE];", " ff_copy_and_dup(cba_vect, ractx->adapt_cb, cba_idx + BLOCKSIZE / 2 - 1);", " m[0] = (ff_irms(cba_vect) * rms) >> 12;" ], "line_no": [ 17, 95, 97 ] }
static void FUNC_0(RA144Context *VAR_0, const int16_t *VAR_1, const int16_t *VAR_2, unsigned int VAR_3, PutBitContext *VAR_4) { float VAR_5[BLOCKSIZE] = { 0 }, work[LPC_ORDER + BLOCKSIZE]; float VAR_6[LPC_ORDER]; float VAR_7[BLOCKSIZE], cba[BLOCKSIZE], cb1[BLOCKSIZE], cb2[BLOCKSIZE]; int16_t cba_vect[BLOCKSIZE]; int VAR_8, VAR_9, VAR_10, VAR_11; int VAR_12, VAR_13; unsigned VAR_14[3]; float VAR_15[3]; float VAR_16, VAR_17; for (VAR_12 = 0; VAR_12 < LPC_ORDER; VAR_12++) { work[VAR_12] = VAR_0->curr_sblock[BLOCKSIZE + VAR_12]; VAR_6[VAR_12] = VAR_2[VAR_12] * (1/4096.0); } ff_celp_lp_synthesis_filterf(work + LPC_ORDER, VAR_6, VAR_5, BLOCKSIZE, LPC_ORDER); for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) { VAR_7[VAR_12] = work[LPC_ORDER + VAR_12]; VAR_5[VAR_12] = VAR_1[VAR_12] - VAR_7[VAR_12]; } memset(work, 0, LPC_ORDER * sizeof(*work)); VAR_8 = adaptive_cb_search(VAR_0->adapt_cb, work + LPC_ORDER, VAR_6, VAR_5); if (VAR_8) { memcpy(cba, work + LPC_ORDER, sizeof(cba)); ff_copy_and_dup(cba_vect, VAR_0->adapt_cb, VAR_8 + BLOCKSIZE / 2 - 1); VAR_14[0] = (ff_irms(cba_vect) * VAR_3) >> 12; } fixed_cb_search(work + LPC_ORDER, VAR_6, VAR_5, VAR_8, &VAR_9, &VAR_10); for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) { cb1[VAR_12] = ff_cb1_vects[VAR_9][VAR_12]; cb2[VAR_12] = ff_cb2_vects[VAR_10][VAR_12]; } ff_celp_lp_synthesis_filterf(work + LPC_ORDER, VAR_6, cb1, BLOCKSIZE, LPC_ORDER); memcpy(cb1, work + LPC_ORDER, sizeof(cb1)); VAR_14[1] = (ff_cb1_base[VAR_9] * VAR_3) >> 8; ff_celp_lp_synthesis_filterf(work + LPC_ORDER, VAR_6, cb2, BLOCKSIZE, LPC_ORDER); memcpy(cb2, work + LPC_ORDER, sizeof(cb2)); VAR_14[2] = (ff_cb2_base[VAR_10] * VAR_3) >> 8; VAR_17 = FLT_MAX; VAR_11 = 0; for (VAR_13 = 0; VAR_13 < 256; VAR_13++) { VAR_15[1] = ((ff_gain_val_tab[VAR_13][1] * VAR_14[1]) >> ff_gain_exp_tab[VAR_13]) * (1/4096.0); VAR_15[2] = ((ff_gain_val_tab[VAR_13][2] * VAR_14[2]) >> ff_gain_exp_tab[VAR_13]) * (1/4096.0); VAR_16 = 0; if (VAR_8) { VAR_15[0] = ((ff_gain_val_tab[VAR_13][0] * VAR_14[0]) >> ff_gain_exp_tab[VAR_13]) * (1/4096.0); for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) { VAR_5[VAR_12] = VAR_7[VAR_12] + VAR_15[0] * cba[VAR_12] + VAR_15[1] * cb1[VAR_12] + VAR_15[2] * cb2[VAR_12]; VAR_16 += (VAR_5[VAR_12] - VAR_1[VAR_12]) * (VAR_5[VAR_12] - VAR_1[VAR_12]); } } else { for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) { VAR_5[VAR_12] = VAR_7[VAR_12] + VAR_15[1] * cb1[VAR_12] + VAR_15[2] * cb2[VAR_12]; VAR_16 += (VAR_5[VAR_12] - VAR_1[VAR_12]) * (VAR_5[VAR_12] - VAR_1[VAR_12]); } } if (VAR_16 < VAR_17) { VAR_17 = VAR_16; VAR_11 = VAR_13; } } put_bits(VAR_4, 7, VAR_8); put_bits(VAR_4, 8, VAR_11); put_bits(VAR_4, 7, VAR_9); put_bits(VAR_4, 7, VAR_10); ff_subblock_synthesis(VAR_0, VAR_2, VAR_8, VAR_9, VAR_10, VAR_3, VAR_11); }
[ "static void FUNC_0(RA144Context *VAR_0,\nconst int16_t *VAR_1,\nconst int16_t *VAR_2, unsigned int VAR_3,\nPutBitContext *VAR_4)\n{", "float VAR_5[BLOCKSIZE] = { 0 }, work[LPC_ORDER + BLOCKSIZE];", "float VAR_6[LPC_ORDER];", "float VAR_7[BLOCKSIZE], cba[BLOCKSIZE], cb1[BLOCKSIZE], cb2[BLOCKSIZE];", "int16_t cba_vect[BLOCKSIZE];", "int VAR_8, VAR_9, VAR_10, VAR_11;", "int VAR_12, VAR_13;", "unsigned VAR_14[3];", "float VAR_15[3];", "float VAR_16, VAR_17;", "for (VAR_12 = 0; VAR_12 < LPC_ORDER; VAR_12++) {", "work[VAR_12] = VAR_0->curr_sblock[BLOCKSIZE + VAR_12];", "VAR_6[VAR_12] = VAR_2[VAR_12] * (1/4096.0);", "}", "ff_celp_lp_synthesis_filterf(work + LPC_ORDER, VAR_6, VAR_5, BLOCKSIZE,\nLPC_ORDER);", "for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) {", "VAR_7[VAR_12] = work[LPC_ORDER + VAR_12];", "VAR_5[VAR_12] = VAR_1[VAR_12] - VAR_7[VAR_12];", "}", "memset(work, 0, LPC_ORDER * sizeof(*work));", "VAR_8 = adaptive_cb_search(VAR_0->adapt_cb, work + LPC_ORDER, VAR_6,\nVAR_5);", "if (VAR_8) {", "memcpy(cba, work + LPC_ORDER, sizeof(cba));", "ff_copy_and_dup(cba_vect, VAR_0->adapt_cb, VAR_8 + BLOCKSIZE / 2 - 1);", "VAR_14[0] = (ff_irms(cba_vect) * VAR_3) >> 12;", "}", "fixed_cb_search(work + LPC_ORDER, VAR_6, VAR_5, VAR_8, &VAR_9, &VAR_10);", "for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) {", "cb1[VAR_12] = ff_cb1_vects[VAR_9][VAR_12];", "cb2[VAR_12] = ff_cb2_vects[VAR_10][VAR_12];", "}", "ff_celp_lp_synthesis_filterf(work + LPC_ORDER, VAR_6, cb1, BLOCKSIZE,\nLPC_ORDER);", "memcpy(cb1, work + LPC_ORDER, sizeof(cb1));", "VAR_14[1] = (ff_cb1_base[VAR_9] * VAR_3) >> 8;", "ff_celp_lp_synthesis_filterf(work + LPC_ORDER, VAR_6, cb2, BLOCKSIZE,\nLPC_ORDER);", "memcpy(cb2, work + LPC_ORDER, sizeof(cb2));", "VAR_14[2] = (ff_cb2_base[VAR_10] * VAR_3) >> 8;", "VAR_17 = FLT_MAX;", "VAR_11 = 0;", "for (VAR_13 = 0; VAR_13 < 256; VAR_13++) {", "VAR_15[1] = ((ff_gain_val_tab[VAR_13][1] * VAR_14[1]) >> ff_gain_exp_tab[VAR_13]) *\n(1/4096.0);", "VAR_15[2] = ((ff_gain_val_tab[VAR_13][2] * VAR_14[2]) >> ff_gain_exp_tab[VAR_13]) *\n(1/4096.0);", "VAR_16 = 0;", "if (VAR_8) {", "VAR_15[0] = ((ff_gain_val_tab[VAR_13][0] * VAR_14[0]) >> ff_gain_exp_tab[VAR_13]) *\n(1/4096.0);", "for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) {", "VAR_5[VAR_12] = VAR_7[VAR_12] + VAR_15[0] * cba[VAR_12] + VAR_15[1] * cb1[VAR_12] +\nVAR_15[2] * cb2[VAR_12];", "VAR_16 += (VAR_5[VAR_12] - VAR_1[VAR_12]) *\n(VAR_5[VAR_12] - VAR_1[VAR_12]);", "}", "} else {", "for (VAR_12 = 0; VAR_12 < BLOCKSIZE; VAR_12++) {", "VAR_5[VAR_12] = VAR_7[VAR_12] + VAR_15[1] * cb1[VAR_12] + VAR_15[2] * cb2[VAR_12];", "VAR_16 += (VAR_5[VAR_12] - VAR_1[VAR_12]) *\n(VAR_5[VAR_12] - VAR_1[VAR_12]);", "}", "}", "if (VAR_16 < VAR_17) {", "VAR_17 = VAR_16;", "VAR_11 = VAR_13;", "}", "}", "put_bits(VAR_4, 7, VAR_8);", "put_bits(VAR_4, 8, VAR_11);", "put_bits(VAR_4, 7, VAR_9);", "put_bits(VAR_4, 7, VAR_10);", "ff_subblock_synthesis(VAR_0, VAR_2, VAR_8, VAR_9, VAR_10, VAR_3,\nVAR_11);", "}" ]
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16,938
build_qp_table(PPS *pps, int index) { int i; for(i = 0; i < 255; i++) pps->chroma_qp_table[i & 0xff] = chroma_qp[av_clip(i + index, 0, 51)]; pps->chroma_qp_index_offset = index; }
true
FFmpeg
4691a77db4672026d62d524fd292fb17db6514b4
build_qp_table(PPS *pps, int index) { int i; for(i = 0; i < 255; i++) pps->chroma_qp_table[i & 0xff] = chroma_qp[av_clip(i + index, 0, 51)]; pps->chroma_qp_index_offset = index; }
{ "code": [ "build_qp_table(PPS *pps, int index)", " pps->chroma_qp_table[i & 0xff] = chroma_qp[av_clip(i + index, 0, 51)];", " pps->chroma_qp_index_offset = index;" ], "line_no": [ 1, 9, 11 ] }
FUNC_0(PPS *VAR_0, int VAR_1) { int VAR_2; for(VAR_2 = 0; VAR_2 < 255; VAR_2++) VAR_0->chroma_qp_table[VAR_2 & 0xff] = chroma_qp[av_clip(VAR_2 + VAR_1, 0, 51)]; VAR_0->chroma_qp_index_offset = VAR_1; }
[ "FUNC_0(PPS *VAR_0, int VAR_1)\n{", "int VAR_2;", "for(VAR_2 = 0; VAR_2 < 255; VAR_2++)", "VAR_0->chroma_qp_table[VAR_2 & 0xff] = chroma_qp[av_clip(VAR_2 + VAR_1, 0, 51)];", "VAR_0->chroma_qp_index_offset = VAR_1;", "}" ]
[ 1, 0, 0, 1, 1, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 11 ], [ 13 ] ]
16,939
static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { CPUPPCState *env = &cpu->env; int i; target_ulong rc = H_SUCCESS; for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { target_ulong *tsh = &args[i*2]; target_ulong tsl = args[i*2 + 1]; target_ulong v, r, ret; if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { break; } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { return H_PARAMETER; } *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; *tsh |= H_BULK_REMOVE_RESPONSE; if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { *tsh |= H_BULK_REMOVE_PARM; return H_PARAMETER; } ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, (*tsh & H_BULK_REMOVE_FLAGS) >> 26, &v, &r); *tsh |= ret << 60; switch (ret) { case REMOVE_SUCCESS: *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; break; case REMOVE_PARM: rc = H_PARAMETER; goto exit; case REMOVE_HW: rc = H_HARDWARE; goto exit; } } exit: check_tlb_flush(env); return rc; }
true
qemu
e3cffe6fad29e07d401eabb913a6d88501d5c143
static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { CPUPPCState *env = &cpu->env; int i; target_ulong rc = H_SUCCESS; for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { target_ulong *tsh = &args[i*2]; target_ulong tsl = args[i*2 + 1]; target_ulong v, r, ret; if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { break; } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { return H_PARAMETER; } *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; *tsh |= H_BULK_REMOVE_RESPONSE; if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { *tsh |= H_BULK_REMOVE_PARM; return H_PARAMETER; } ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, (*tsh & H_BULK_REMOVE_FLAGS) >> 26, &v, &r); *tsh |= ret << 60; switch (ret) { case REMOVE_SUCCESS: *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; break; case REMOVE_PARM: rc = H_PARAMETER; goto exit; case REMOVE_HW: rc = H_HARDWARE; goto exit; } } exit: check_tlb_flush(env); return rc; }
{ "code": [ " check_tlb_flush(env);", " check_tlb_flush(env);", " check_tlb_flush(env);", " check_tlb_flush(env);" ], "line_no": [ 95, 95, 95, 95 ] }
static target_ulong FUNC_0(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { CPUPPCState *env = &cpu->env; int VAR_0; target_ulong rc = H_SUCCESS; for (VAR_0 = 0; VAR_0 < H_BULK_REMOVE_MAX_BATCH; VAR_0++) { target_ulong *tsh = &args[VAR_0*2]; target_ulong tsl = args[VAR_0*2 + 1]; target_ulong v, r, ret; if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { break; } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { return H_PARAMETER; } *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; *tsh |= H_BULK_REMOVE_RESPONSE; if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { *tsh |= H_BULK_REMOVE_PARM; return H_PARAMETER; } ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, (*tsh & H_BULK_REMOVE_FLAGS) >> 26, &v, &r); *tsh |= ret << 60; switch (ret) { case REMOVE_SUCCESS: *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; break; case REMOVE_PARM: rc = H_PARAMETER; goto exit; case REMOVE_HW: rc = H_HARDWARE; goto exit; } } exit: check_tlb_flush(env); return rc; }
[ "static target_ulong FUNC_0(PowerPCCPU *cpu, sPAPRMachineState *spapr,\ntarget_ulong opcode, target_ulong *args)\n{", "CPUPPCState *env = &cpu->env;", "int VAR_0;", "target_ulong rc = H_SUCCESS;", "for (VAR_0 = 0; VAR_0 < H_BULK_REMOVE_MAX_BATCH; VAR_0++) {", "target_ulong *tsh = &args[VAR_0*2];", "target_ulong tsl = args[VAR_0*2 + 1];", "target_ulong v, r, ret;", "if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {", "break;", "} else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {", "return H_PARAMETER;", "}", "*tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;", "*tsh |= H_BULK_REMOVE_RESPONSE;", "if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {", "*tsh |= H_BULK_REMOVE_PARM;", "return H_PARAMETER;", "}", "ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,\n(*tsh & H_BULK_REMOVE_FLAGS) >> 26,\n&v, &r);", "*tsh |= ret << 60;", "switch (ret) {", "case REMOVE_SUCCESS:\n*tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;", "break;", "case REMOVE_PARM:\nrc = H_PARAMETER;", "goto exit;", "case REMOVE_HW:\nrc = H_HARDWARE;", "goto exit;", "}", "}", "exit:\ncheck_tlb_flush(env);", "return rc;", "}" ]
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[ [ 1, 3, 5 ], [ 7 ], [ 9 ], [ 11 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 25 ], [ 27 ], [ 29 ], [ 31 ], [ 33 ], [ 37 ], [ 39 ], [ 43 ], [ 45 ], [ 47 ], [ 49 ], [ 53, 55, 57 ], [ 61 ], [ 65 ], [ 67, 69 ], [ 71 ], [ 75, 77 ], [ 79 ], [ 83, 85 ], [ 87 ], [ 89 ], [ 91 ], [ 93, 95 ], [ 99 ], [ 101 ] ]
16,940
static void cpu_notify_map_clients(void) { MapClient *client; while (!LIST_EMPTY(&map_client_list)) { client = LIST_FIRST(&map_client_list); client->callback(client->opaque); LIST_REMOVE(client, link); } }
true
qemu
34d5e948e8a0d0d3a37801a418475a8632ce0891
static void cpu_notify_map_clients(void) { MapClient *client; while (!LIST_EMPTY(&map_client_list)) { client = LIST_FIRST(&map_client_list); client->callback(client->opaque); LIST_REMOVE(client, link); } }
{ "code": [ " LIST_REMOVE(client, link);" ], "line_no": [ 15 ] }
static void FUNC_0(void) { MapClient *client; while (!LIST_EMPTY(&map_client_list)) { client = LIST_FIRST(&map_client_list); client->callback(client->opaque); LIST_REMOVE(client, link); } }
[ "static void FUNC_0(void)\n{", "MapClient *client;", "while (!LIST_EMPTY(&map_client_list)) {", "client = LIST_FIRST(&map_client_list);", "client->callback(client->opaque);", "LIST_REMOVE(client, link);", "}", "}" ]
[ 0, 0, 0, 0, 0, 1, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ] ]
16,941
static int asf_read_stream_properties(AVFormatContext *s, int64_t size) { ASFContext *asf = s->priv_data; AVIOContext *pb = s->pb; AVStream *st; ASFStream *asf_st; ff_asf_guid g; enum AVMediaType type; int type_specific_size, sizeX; unsigned int tag1; int64_t pos1, pos2, start_time; int test_for_ext_stream_audio, is_dvr_ms_audio=0; if (s->nb_streams == ASF_MAX_STREAMS) { av_log(s, AV_LOG_ERROR, "too many streams\n"); return AVERROR(EINVAL); } pos1 = avio_tell(pb); st = avformat_new_stream(s, NULL); if (!st) return AVERROR(ENOMEM); avpriv_set_pts_info(st, 32, 1, 1000); /* 32 bit pts in ms */ asf_st = av_mallocz(sizeof(ASFStream)); if (!asf_st) return AVERROR(ENOMEM); st->priv_data = asf_st; start_time = asf->hdr.preroll; asf_st->stream_language_index = 128; // invalid stream index means no language info if(!(asf->hdr.flags & 0x01)) { // if we aren't streaming... int64_t fsize = avio_size(pb); if (fsize <= 0 || (int64_t)asf->hdr.file_size <= 0 || FFABS(fsize - (int64_t)asf->hdr.file_size) < 10000) st->duration = asf->hdr.play_time / (10000000 / 1000) - start_time; } ff_get_guid(pb, &g); test_for_ext_stream_audio = 0; if (!ff_guidcmp(&g, &ff_asf_audio_stream)) { type = AVMEDIA_TYPE_AUDIO; } else if (!ff_guidcmp(&g, &ff_asf_video_stream)) { type = AVMEDIA_TYPE_VIDEO; } else if (!ff_guidcmp(&g, &ff_asf_jfif_media)) { type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = AV_CODEC_ID_MJPEG; } else if (!ff_guidcmp(&g, &ff_asf_command_stream)) { type = AVMEDIA_TYPE_DATA; } else if (!ff_guidcmp(&g, &ff_asf_ext_stream_embed_stream_header)) { test_for_ext_stream_audio = 1; type = AVMEDIA_TYPE_UNKNOWN; } else { return -1; } ff_get_guid(pb, &g); avio_skip(pb, 8); /* total_size */ type_specific_size = avio_rl32(pb); avio_rl32(pb); st->id = avio_rl16(pb) & 0x7f; /* stream id */ // mapping of asf ID to AV stream ID; asf->asfid2avid[st->id] = s->nb_streams - 1; avio_rl32(pb); if (test_for_ext_stream_audio) { ff_get_guid(pb, &g); if (!ff_guidcmp(&g, &ff_asf_ext_stream_audio_stream)) { type = AVMEDIA_TYPE_AUDIO; is_dvr_ms_audio=1; ff_get_guid(pb, &g); avio_rl32(pb); avio_rl32(pb); avio_rl32(pb); ff_get_guid(pb, &g); avio_rl32(pb); } } st->codec->codec_type = type; if (type == AVMEDIA_TYPE_AUDIO) { int ret = ff_get_wav_header(pb, st->codec, type_specific_size); if (ret < 0) return ret; if (is_dvr_ms_audio) { // codec_id and codec_tag are unreliable in dvr_ms // files. Set them later by probing stream. st->request_probe= 1; st->codec->codec_tag = 0; } if (st->codec->codec_id == AV_CODEC_ID_AAC) { st->need_parsing = AVSTREAM_PARSE_NONE; } else { st->need_parsing = AVSTREAM_PARSE_FULL; } /* We have to init the frame size at some point .... */ pos2 = avio_tell(pb); if (size >= (pos2 + 8 - pos1 + 24)) { asf_st->ds_span = avio_r8(pb); asf_st->ds_packet_size = avio_rl16(pb); asf_st->ds_chunk_size = avio_rl16(pb); avio_rl16(pb); //ds_data_size avio_r8(pb); //ds_silence_data } if (asf_st->ds_span > 1) { if (!asf_st->ds_chunk_size || (asf_st->ds_packet_size/asf_st->ds_chunk_size <= 1) || asf_st->ds_packet_size % asf_st->ds_chunk_size) asf_st->ds_span = 0; // disable descrambling } } else if (type == AVMEDIA_TYPE_VIDEO && size - (avio_tell(pb) - pos1 + 24) >= 51) { avio_rl32(pb); avio_rl32(pb); avio_r8(pb); avio_rl16(pb); /* size */ sizeX= avio_rl32(pb); /* size */ st->codec->width = avio_rl32(pb); st->codec->height = avio_rl32(pb); /* not available for asf */ avio_rl16(pb); /* panes */ st->codec->bits_per_coded_sample = avio_rl16(pb); /* depth */ tag1 = avio_rl32(pb); avio_skip(pb, 20); if (sizeX > 40) { st->codec->extradata_size = sizeX - 40; st->codec->extradata = av_mallocz(st->codec->extradata_size + FF_INPUT_BUFFER_PADDING_SIZE); avio_read(pb, st->codec->extradata, st->codec->extradata_size); } /* Extract palette from extradata if bpp <= 8 */ /* This code assumes that extradata contains only palette */ /* This is true for all paletted codecs implemented in libavcodec */ if (st->codec->extradata_size && (st->codec->bits_per_coded_sample <= 8)) { #if HAVE_BIGENDIAN int i; for (i = 0; i < FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)/4; i++) asf_st->palette[i] = av_bswap32(((uint32_t*)st->codec->extradata)[i]); #else memcpy(asf_st->palette, st->codec->extradata, FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)); #endif asf_st->palette_changed = 1; } st->codec->codec_tag = tag1; st->codec->codec_id = ff_codec_get_id(ff_codec_bmp_tags, tag1); if(tag1 == MKTAG('D', 'V', 'R', ' ')){ st->need_parsing = AVSTREAM_PARSE_FULL; // issue658 containse wrong w/h and MS even puts a fake seq header with wrong w/h in extradata while a correct one is in te stream. maximum lameness st->codec->width = st->codec->height = 0; av_freep(&st->codec->extradata); st->codec->extradata_size=0; } if(st->codec->codec_id == AV_CODEC_ID_H264) st->need_parsing = AVSTREAM_PARSE_FULL_ONCE; } pos2 = avio_tell(pb); avio_skip(pb, size - (pos2 - pos1 + 24)); return 0; }
false
FFmpeg
80aa89bdff6e3e9dd6bc58d806db0cbe99403149
static int asf_read_stream_properties(AVFormatContext *s, int64_t size) { ASFContext *asf = s->priv_data; AVIOContext *pb = s->pb; AVStream *st; ASFStream *asf_st; ff_asf_guid g; enum AVMediaType type; int type_specific_size, sizeX; unsigned int tag1; int64_t pos1, pos2, start_time; int test_for_ext_stream_audio, is_dvr_ms_audio=0; if (s->nb_streams == ASF_MAX_STREAMS) { av_log(s, AV_LOG_ERROR, "too many streams\n"); return AVERROR(EINVAL); } pos1 = avio_tell(pb); st = avformat_new_stream(s, NULL); if (!st) return AVERROR(ENOMEM); avpriv_set_pts_info(st, 32, 1, 1000); asf_st = av_mallocz(sizeof(ASFStream)); if (!asf_st) return AVERROR(ENOMEM); st->priv_data = asf_st; start_time = asf->hdr.preroll; asf_st->stream_language_index = 128; if(!(asf->hdr.flags & 0x01)) { int64_t fsize = avio_size(pb); if (fsize <= 0 || (int64_t)asf->hdr.file_size <= 0 || FFABS(fsize - (int64_t)asf->hdr.file_size) < 10000) st->duration = asf->hdr.play_time / (10000000 / 1000) - start_time; } ff_get_guid(pb, &g); test_for_ext_stream_audio = 0; if (!ff_guidcmp(&g, &ff_asf_audio_stream)) { type = AVMEDIA_TYPE_AUDIO; } else if (!ff_guidcmp(&g, &ff_asf_video_stream)) { type = AVMEDIA_TYPE_VIDEO; } else if (!ff_guidcmp(&g, &ff_asf_jfif_media)) { type = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = AV_CODEC_ID_MJPEG; } else if (!ff_guidcmp(&g, &ff_asf_command_stream)) { type = AVMEDIA_TYPE_DATA; } else if (!ff_guidcmp(&g, &ff_asf_ext_stream_embed_stream_header)) { test_for_ext_stream_audio = 1; type = AVMEDIA_TYPE_UNKNOWN; } else { return -1; } ff_get_guid(pb, &g); avio_skip(pb, 8); type_specific_size = avio_rl32(pb); avio_rl32(pb); st->id = avio_rl16(pb) & 0x7f; asf->asfid2avid[st->id] = s->nb_streams - 1; avio_rl32(pb); if (test_for_ext_stream_audio) { ff_get_guid(pb, &g); if (!ff_guidcmp(&g, &ff_asf_ext_stream_audio_stream)) { type = AVMEDIA_TYPE_AUDIO; is_dvr_ms_audio=1; ff_get_guid(pb, &g); avio_rl32(pb); avio_rl32(pb); avio_rl32(pb); ff_get_guid(pb, &g); avio_rl32(pb); } } st->codec->codec_type = type; if (type == AVMEDIA_TYPE_AUDIO) { int ret = ff_get_wav_header(pb, st->codec, type_specific_size); if (ret < 0) return ret; if (is_dvr_ms_audio) { st->request_probe= 1; st->codec->codec_tag = 0; } if (st->codec->codec_id == AV_CODEC_ID_AAC) { st->need_parsing = AVSTREAM_PARSE_NONE; } else { st->need_parsing = AVSTREAM_PARSE_FULL; } pos2 = avio_tell(pb); if (size >= (pos2 + 8 - pos1 + 24)) { asf_st->ds_span = avio_r8(pb); asf_st->ds_packet_size = avio_rl16(pb); asf_st->ds_chunk_size = avio_rl16(pb); avio_rl16(pb); avio_r8(pb); } if (asf_st->ds_span > 1) { if (!asf_st->ds_chunk_size || (asf_st->ds_packet_size/asf_st->ds_chunk_size <= 1) || asf_st->ds_packet_size % asf_st->ds_chunk_size) asf_st->ds_span = 0; } } else if (type == AVMEDIA_TYPE_VIDEO && size - (avio_tell(pb) - pos1 + 24) >= 51) { avio_rl32(pb); avio_rl32(pb); avio_r8(pb); avio_rl16(pb); sizeX= avio_rl32(pb); st->codec->width = avio_rl32(pb); st->codec->height = avio_rl32(pb); avio_rl16(pb); st->codec->bits_per_coded_sample = avio_rl16(pb); tag1 = avio_rl32(pb); avio_skip(pb, 20); if (sizeX > 40) { st->codec->extradata_size = sizeX - 40; st->codec->extradata = av_mallocz(st->codec->extradata_size + FF_INPUT_BUFFER_PADDING_SIZE); avio_read(pb, st->codec->extradata, st->codec->extradata_size); } if (st->codec->extradata_size && (st->codec->bits_per_coded_sample <= 8)) { #if HAVE_BIGENDIAN int i; for (i = 0; i < FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)/4; i++) asf_st->palette[i] = av_bswap32(((uint32_t*)st->codec->extradata)[i]); #else memcpy(asf_st->palette, st->codec->extradata, FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)); #endif asf_st->palette_changed = 1; } st->codec->codec_tag = tag1; st->codec->codec_id = ff_codec_get_id(ff_codec_bmp_tags, tag1); if(tag1 == MKTAG('D', 'V', 'R', ' ')){ st->need_parsing = AVSTREAM_PARSE_FULL; st->codec->width = st->codec->height = 0; av_freep(&st->codec->extradata); st->codec->extradata_size=0; } if(st->codec->codec_id == AV_CODEC_ID_H264) st->need_parsing = AVSTREAM_PARSE_FULL_ONCE; } pos2 = avio_tell(pb); avio_skip(pb, size - (pos2 - pos1 + 24)); return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(AVFormatContext *VAR_0, int64_t VAR_1) { ASFContext *asf = VAR_0->priv_data; AVIOContext *pb = VAR_0->pb; AVStream *st; ASFStream *asf_st; ff_asf_guid g; enum AVMediaType VAR_2; int VAR_3, VAR_4; unsigned int VAR_5; int64_t pos1, pos2, start_time; int VAR_6, VAR_7=0; if (VAR_0->nb_streams == ASF_MAX_STREAMS) { av_log(VAR_0, AV_LOG_ERROR, "too many streams\n"); return AVERROR(EINVAL); } pos1 = avio_tell(pb); st = avformat_new_stream(VAR_0, NULL); if (!st) return AVERROR(ENOMEM); avpriv_set_pts_info(st, 32, 1, 1000); asf_st = av_mallocz(sizeof(ASFStream)); if (!asf_st) return AVERROR(ENOMEM); st->priv_data = asf_st; start_time = asf->hdr.preroll; asf_st->stream_language_index = 128; if(!(asf->hdr.flags & 0x01)) { int64_t fsize = avio_size(pb); if (fsize <= 0 || (int64_t)asf->hdr.file_size <= 0 || FFABS(fsize - (int64_t)asf->hdr.file_size) < 10000) st->duration = asf->hdr.play_time / (10000000 / 1000) - start_time; } ff_get_guid(pb, &g); VAR_6 = 0; if (!ff_guidcmp(&g, &ff_asf_audio_stream)) { VAR_2 = AVMEDIA_TYPE_AUDIO; } else if (!ff_guidcmp(&g, &ff_asf_video_stream)) { VAR_2 = AVMEDIA_TYPE_VIDEO; } else if (!ff_guidcmp(&g, &ff_asf_jfif_media)) { VAR_2 = AVMEDIA_TYPE_VIDEO; st->codec->codec_id = AV_CODEC_ID_MJPEG; } else if (!ff_guidcmp(&g, &ff_asf_command_stream)) { VAR_2 = AVMEDIA_TYPE_DATA; } else if (!ff_guidcmp(&g, &ff_asf_ext_stream_embed_stream_header)) { VAR_6 = 1; VAR_2 = AVMEDIA_TYPE_UNKNOWN; } else { return -1; } ff_get_guid(pb, &g); avio_skip(pb, 8); VAR_3 = avio_rl32(pb); avio_rl32(pb); st->id = avio_rl16(pb) & 0x7f; asf->asfid2avid[st->id] = VAR_0->nb_streams - 1; avio_rl32(pb); if (VAR_6) { ff_get_guid(pb, &g); if (!ff_guidcmp(&g, &ff_asf_ext_stream_audio_stream)) { VAR_2 = AVMEDIA_TYPE_AUDIO; VAR_7=1; ff_get_guid(pb, &g); avio_rl32(pb); avio_rl32(pb); avio_rl32(pb); ff_get_guid(pb, &g); avio_rl32(pb); } } st->codec->codec_type = VAR_2; if (VAR_2 == AVMEDIA_TYPE_AUDIO) { int VAR_8 = ff_get_wav_header(pb, st->codec, VAR_3); if (VAR_8 < 0) return VAR_8; if (VAR_7) { st->request_probe= 1; st->codec->codec_tag = 0; } if (st->codec->codec_id == AV_CODEC_ID_AAC) { st->need_parsing = AVSTREAM_PARSE_NONE; } else { st->need_parsing = AVSTREAM_PARSE_FULL; } pos2 = avio_tell(pb); if (VAR_1 >= (pos2 + 8 - pos1 + 24)) { asf_st->ds_span = avio_r8(pb); asf_st->ds_packet_size = avio_rl16(pb); asf_st->ds_chunk_size = avio_rl16(pb); avio_rl16(pb); avio_r8(pb); } if (asf_st->ds_span > 1) { if (!asf_st->ds_chunk_size || (asf_st->ds_packet_size/asf_st->ds_chunk_size <= 1) || asf_st->ds_packet_size % asf_st->ds_chunk_size) asf_st->ds_span = 0; } } else if (VAR_2 == AVMEDIA_TYPE_VIDEO && VAR_1 - (avio_tell(pb) - pos1 + 24) >= 51) { avio_rl32(pb); avio_rl32(pb); avio_r8(pb); avio_rl16(pb); VAR_4= avio_rl32(pb); st->codec->width = avio_rl32(pb); st->codec->height = avio_rl32(pb); avio_rl16(pb); st->codec->bits_per_coded_sample = avio_rl16(pb); VAR_5 = avio_rl32(pb); avio_skip(pb, 20); if (VAR_4 > 40) { st->codec->extradata_size = VAR_4 - 40; st->codec->extradata = av_mallocz(st->codec->extradata_size + FF_INPUT_BUFFER_PADDING_SIZE); avio_read(pb, st->codec->extradata, st->codec->extradata_size); } if (st->codec->extradata_size && (st->codec->bits_per_coded_sample <= 8)) { #if HAVE_BIGENDIAN int i; for (i = 0; i < FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)/4; i++) asf_st->palette[i] = av_bswap32(((uint32_t*)st->codec->extradata)[i]); #else memcpy(asf_st->palette, st->codec->extradata, FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)); #endif asf_st->palette_changed = 1; } st->codec->codec_tag = VAR_5; st->codec->codec_id = ff_codec_get_id(ff_codec_bmp_tags, VAR_5); if(VAR_5 == MKTAG('D', 'V', 'R', ' ')){ st->need_parsing = AVSTREAM_PARSE_FULL; st->codec->width = st->codec->height = 0; av_freep(&st->codec->extradata); st->codec->extradata_size=0; } if(st->codec->codec_id == AV_CODEC_ID_H264) st->need_parsing = AVSTREAM_PARSE_FULL_ONCE; } pos2 = avio_tell(pb); avio_skip(pb, VAR_1 - (pos2 - pos1 + 24)); return 0; }
[ "static int FUNC_0(AVFormatContext *VAR_0, int64_t VAR_1)\n{", "ASFContext *asf = VAR_0->priv_data;", "AVIOContext *pb = VAR_0->pb;", "AVStream *st;", "ASFStream *asf_st;", "ff_asf_guid g;", "enum AVMediaType VAR_2;", "int VAR_3, VAR_4;", "unsigned int VAR_5;", "int64_t pos1, pos2, start_time;", "int VAR_6, VAR_7=0;", "if (VAR_0->nb_streams == ASF_MAX_STREAMS) {", "av_log(VAR_0, AV_LOG_ERROR, \"too many streams\\n\");", "return AVERROR(EINVAL);", "}", "pos1 = avio_tell(pb);", "st = avformat_new_stream(VAR_0, NULL);", "if (!st)\nreturn AVERROR(ENOMEM);", "avpriv_set_pts_info(st, 32, 1, 1000);", "asf_st = av_mallocz(sizeof(ASFStream));", "if (!asf_st)\nreturn AVERROR(ENOMEM);", "st->priv_data = asf_st;", "start_time = asf->hdr.preroll;", "asf_st->stream_language_index = 128;", "if(!(asf->hdr.flags & 0x01)) {", "int64_t fsize = avio_size(pb);", "if (fsize <= 0 || (int64_t)asf->hdr.file_size <= 0 || FFABS(fsize - (int64_t)asf->hdr.file_size) < 10000)\nst->duration = asf->hdr.play_time /\n(10000000 / 1000) - start_time;", "}", "ff_get_guid(pb, &g);", "VAR_6 = 0;", "if (!ff_guidcmp(&g, &ff_asf_audio_stream)) {", "VAR_2 = AVMEDIA_TYPE_AUDIO;", "} else if (!ff_guidcmp(&g, &ff_asf_video_stream)) {", "VAR_2 = AVMEDIA_TYPE_VIDEO;", "} else if (!ff_guidcmp(&g, &ff_asf_jfif_media)) {", "VAR_2 = AVMEDIA_TYPE_VIDEO;", "st->codec->codec_id = AV_CODEC_ID_MJPEG;", "} else if (!ff_guidcmp(&g, &ff_asf_command_stream)) {", "VAR_2 = AVMEDIA_TYPE_DATA;", "} else if (!ff_guidcmp(&g, &ff_asf_ext_stream_embed_stream_header)) {", "VAR_6 = 1;", "VAR_2 = AVMEDIA_TYPE_UNKNOWN;", "} else {", "return -1;", "}", "ff_get_guid(pb, &g);", "avio_skip(pb, 8);", "VAR_3 = avio_rl32(pb);", "avio_rl32(pb);", "st->id = avio_rl16(pb) & 0x7f;", "asf->asfid2avid[st->id] = VAR_0->nb_streams - 1;", "avio_rl32(pb);", "if (VAR_6) {", "ff_get_guid(pb, &g);", "if (!ff_guidcmp(&g, &ff_asf_ext_stream_audio_stream)) {", "VAR_2 = AVMEDIA_TYPE_AUDIO;", "VAR_7=1;", "ff_get_guid(pb, &g);", "avio_rl32(pb);", "avio_rl32(pb);", "avio_rl32(pb);", "ff_get_guid(pb, &g);", "avio_rl32(pb);", "}", "}", "st->codec->codec_type = VAR_2;", "if (VAR_2 == AVMEDIA_TYPE_AUDIO) {", "int VAR_8 = ff_get_wav_header(pb, st->codec, VAR_3);", "if (VAR_8 < 0)\nreturn VAR_8;", "if (VAR_7) {", "st->request_probe= 1;", "st->codec->codec_tag = 0;", "}", "if (st->codec->codec_id == AV_CODEC_ID_AAC) {", "st->need_parsing = AVSTREAM_PARSE_NONE;", "} else {", "st->need_parsing = AVSTREAM_PARSE_FULL;", "}", "pos2 = avio_tell(pb);", "if (VAR_1 >= (pos2 + 8 - pos1 + 24)) {", "asf_st->ds_span = avio_r8(pb);", "asf_st->ds_packet_size = avio_rl16(pb);", "asf_st->ds_chunk_size = avio_rl16(pb);", "avio_rl16(pb);", "avio_r8(pb);", "}", "if (asf_st->ds_span > 1) {", "if (!asf_st->ds_chunk_size\n|| (asf_st->ds_packet_size/asf_st->ds_chunk_size <= 1)\n|| asf_st->ds_packet_size % asf_st->ds_chunk_size)\nasf_st->ds_span = 0;", "}", "} else if (VAR_2 == AVMEDIA_TYPE_VIDEO &&", "VAR_1 - (avio_tell(pb) - pos1 + 24) >= 51) {", "avio_rl32(pb);", "avio_rl32(pb);", "avio_r8(pb);", "avio_rl16(pb);", "VAR_4= avio_rl32(pb);", "st->codec->width = avio_rl32(pb);", "st->codec->height = avio_rl32(pb);", "avio_rl16(pb);", "st->codec->bits_per_coded_sample = avio_rl16(pb);", "VAR_5 = avio_rl32(pb);", "avio_skip(pb, 20);", "if (VAR_4 > 40) {", "st->codec->extradata_size = VAR_4 - 40;", "st->codec->extradata = av_mallocz(st->codec->extradata_size + FF_INPUT_BUFFER_PADDING_SIZE);", "avio_read(pb, st->codec->extradata, st->codec->extradata_size);", "}", "if (st->codec->extradata_size && (st->codec->bits_per_coded_sample <= 8)) {", "#if HAVE_BIGENDIAN\nint i;", "for (i = 0; i < FFMIN(st->codec->extradata_size, AVPALETTE_SIZE)/4; i++)", "asf_st->palette[i] = av_bswap32(((uint32_t*)st->codec->extradata)[i]);", "#else\nmemcpy(asf_st->palette, st->codec->extradata,\nFFMIN(st->codec->extradata_size, AVPALETTE_SIZE));", "#endif\nasf_st->palette_changed = 1;", "}", "st->codec->codec_tag = VAR_5;", "st->codec->codec_id = ff_codec_get_id(ff_codec_bmp_tags, VAR_5);", "if(VAR_5 == MKTAG('D', 'V', 'R', ' ')){", "st->need_parsing = AVSTREAM_PARSE_FULL;", "st->codec->width =\nst->codec->height = 0;", "av_freep(&st->codec->extradata);", "st->codec->extradata_size=0;", "}", "if(st->codec->codec_id == AV_CODEC_ID_H264)\nst->need_parsing = AVSTREAM_PARSE_FULL_ONCE;", "}", "pos2 = avio_tell(pb);", "avio_skip(pb, VAR_1 - (pos2 - pos1 + 24));", "return 0;", "}" ]
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16,944
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) { int mmu_idx, page_index, pd; void *p; MemoryRegion *mr; page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env1); if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != (addr & TARGET_PAGE_MASK))) { #ifdef CONFIG_TCG_PASS_AREG0 cpu_ldub_code(env1, addr); #else ldub_code(addr); #endif } pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; mr = iotlb_to_region(pd); if (mr != &io_mem_ram && mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device) { #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) cpu_unassigned_access(env1, addr, 0, 1, 0, 4); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); #endif } p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend); return qemu_ram_addr_from_host_nofail(p); }
false
qemu
32b089808f125470b3563bf4209c2301fa35c58e
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) { int mmu_idx, page_index, pd; void *p; MemoryRegion *mr; page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env1); if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != (addr & TARGET_PAGE_MASK))) { #ifdef CONFIG_TCG_PASS_AREG0 cpu_ldub_code(env1, addr); #else ldub_code(addr); #endif } pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; mr = iotlb_to_region(pd); if (mr != &io_mem_ram && mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device) { #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) cpu_unassigned_access(env1, addr, 0, 1, 0, 4); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); #endif } p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend); return qemu_ram_addr_from_host_nofail(p); }
{ "code": [], "line_no": [] }
tb_page_addr_t FUNC_0(CPUArchState *env1, target_ulong addr) { int VAR_0, VAR_1, VAR_2; void *VAR_3; MemoryRegion *mr; VAR_1 = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); VAR_0 = cpu_mmu_index(env1); if (unlikely(env1->tlb_table[VAR_0][VAR_1].addr_code != (addr & TARGET_PAGE_MASK))) { #ifdef CONFIG_TCG_PASS_AREG0 cpu_ldub_code(env1, addr); #else ldub_code(addr); #endif } VAR_2 = env1->iotlb[VAR_0][VAR_1] & ~TARGET_PAGE_MASK; mr = iotlb_to_region(VAR_2); if (mr != &io_mem_ram && mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device) { #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) cpu_unassigned_access(env1, addr, 0, 1, 0, 4); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); #endif } VAR_3 = (void *)((uintptr_t)addr + env1->tlb_table[VAR_0][VAR_1].addend); return qemu_ram_addr_from_host_nofail(VAR_3); }
[ "tb_page_addr_t FUNC_0(CPUArchState *env1, target_ulong addr)\n{", "int VAR_0, VAR_1, VAR_2;", "void *VAR_3;", "MemoryRegion *mr;", "VAR_1 = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);", "VAR_0 = cpu_mmu_index(env1);", "if (unlikely(env1->tlb_table[VAR_0][VAR_1].addr_code !=\n(addr & TARGET_PAGE_MASK))) {", "#ifdef CONFIG_TCG_PASS_AREG0\ncpu_ldub_code(env1, addr);", "#else\nldub_code(addr);", "#endif\n}", "VAR_2 = env1->iotlb[VAR_0][VAR_1] & ~TARGET_PAGE_MASK;", "mr = iotlb_to_region(VAR_2);", "if (mr != &io_mem_ram && mr != &io_mem_rom\n&& mr != &io_mem_notdirty && !mr->rom_device) {", "#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)\ncpu_unassigned_access(env1, addr, 0, 1, 0, 4);", "#else\ncpu_abort(env1, \"Trying to execute code outside RAM or ROM at 0x\" TARGET_FMT_lx \"\\n\", addr);", "#endif\n}", "VAR_3 = (void *)((uintptr_t)addr + env1->tlb_table[VAR_0][VAR_1].addend);", "return qemu_ram_addr_from_host_nofail(VAR_3);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 9 ], [ 13 ], [ 15 ], [ 17, 19 ], [ 21, 23 ], [ 25, 27 ], [ 29, 31 ], [ 33 ], [ 35 ], [ 37, 39 ], [ 41, 43 ], [ 45, 47 ], [ 49, 51 ], [ 53 ], [ 55 ], [ 57 ] ]
16,945
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) { PowerPCCPU *cpu = ppc_env_get_cpu(env); _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0); }
false
qemu
e81a982aa5398269a2cc344091ffa4930bdd242f
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) { PowerPCCPU *cpu = ppc_env_get_cpu(env); _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0); }
{ "code": [], "line_no": [] }
void FUNC_0 (CPUPPCState *VAR_0, uint32_t VAR_1) { PowerPCCPU *cpu = ppc_env_get_cpu(VAR_0); _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(VAR_0), VAR_1, 0); }
[ "void FUNC_0 (CPUPPCState *VAR_0, uint32_t VAR_1)\n{", "PowerPCCPU *cpu = ppc_env_get_cpu(VAR_0);", "_cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(VAR_0), VAR_1, 0);", "}" ]
[ 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 9 ], [ 11 ] ]
16,946
static void test_submit_co(void) { WorkerTestData data; Coroutine *co = qemu_coroutine_create(co_test_cb); qemu_coroutine_enter(co, &data); /* Back here once the worker has started. */ g_assert_cmpint(active, ==, 1); g_assert_cmpint(data.ret, ==, -EINPROGRESS); /* qemu_aio_flush will execute the rest of the coroutine. */ qemu_aio_flush(); /* Back here after the coroutine has finished. */ g_assert_cmpint(active, ==, 0); g_assert_cmpint(data.ret, ==, 0); }
false
qemu
8a805c222caa0e20bf11d2267f726d0bb5917d94
static void test_submit_co(void) { WorkerTestData data; Coroutine *co = qemu_coroutine_create(co_test_cb); qemu_coroutine_enter(co, &data); g_assert_cmpint(active, ==, 1); g_assert_cmpint(data.ret, ==, -EINPROGRESS); qemu_aio_flush(); g_assert_cmpint(active, ==, 0); g_assert_cmpint(data.ret, ==, 0); }
{ "code": [], "line_no": [] }
static void FUNC_0(void) { WorkerTestData data; Coroutine *co = qemu_coroutine_create(co_test_cb); qemu_coroutine_enter(co, &data); g_assert_cmpint(active, ==, 1); g_assert_cmpint(data.ret, ==, -EINPROGRESS); qemu_aio_flush(); g_assert_cmpint(active, ==, 0); g_assert_cmpint(data.ret, ==, 0); }
[ "static void FUNC_0(void)\n{", "WorkerTestData data;", "Coroutine *co = qemu_coroutine_create(co_test_cb);", "qemu_coroutine_enter(co, &data);", "g_assert_cmpint(active, ==, 1);", "g_assert_cmpint(data.ret, ==, -EINPROGRESS);", "qemu_aio_flush();", "g_assert_cmpint(active, ==, 0);", "g_assert_cmpint(data.ret, ==, 0);", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 11 ], [ 19 ], [ 21 ], [ 29 ], [ 37 ], [ 39 ], [ 41 ] ]
16,949
static int decode_profile_tier_level(HEVCContext *s, ProfileTierLevel *ptl) { int i; HEVCLocalContext *lc = s->HEVClc; GetBitContext *gb = &lc->gb; ptl->profile_space = get_bits(gb, 2); ptl->tier_flag = get_bits1(gb); ptl->profile_idc = get_bits(gb, 5); if (ptl->profile_idc == 1) av_log(s->avctx, AV_LOG_DEBUG, "Main profile bitstream\n"); else if (ptl->profile_idc == 2) av_log(s->avctx, AV_LOG_DEBUG, "Main10 profile bitstream\n"); else av_log(s->avctx, AV_LOG_WARNING, "No profile indication! (%d)\n", ptl->profile_idc); for (i = 0; i < 32; i++) ptl->profile_compatibility_flag[i] = get_bits1(gb); ptl->progressive_source_flag = get_bits1(gb); ptl->interlaced_source_flag = get_bits1(gb); ptl->non_packed_constraint_flag = get_bits1(gb); ptl->frame_only_constraint_flag = get_bits1(gb); if (get_bits(gb, 16) != 0) // XXX_reserved_zero_44bits[0..15] return -1; if (get_bits(gb, 16) != 0) // XXX_reserved_zero_44bits[16..31] return -1; if (get_bits(gb, 12) != 0) // XXX_reserved_zero_44bits[32..43] return -1; return 0; }
false
FFmpeg
dddc9b7a8ec3a03e48c69991ca7f20f10dd6f022
static int decode_profile_tier_level(HEVCContext *s, ProfileTierLevel *ptl) { int i; HEVCLocalContext *lc = s->HEVClc; GetBitContext *gb = &lc->gb; ptl->profile_space = get_bits(gb, 2); ptl->tier_flag = get_bits1(gb); ptl->profile_idc = get_bits(gb, 5); if (ptl->profile_idc == 1) av_log(s->avctx, AV_LOG_DEBUG, "Main profile bitstream\n"); else if (ptl->profile_idc == 2) av_log(s->avctx, AV_LOG_DEBUG, "Main10 profile bitstream\n"); else av_log(s->avctx, AV_LOG_WARNING, "No profile indication! (%d)\n", ptl->profile_idc); for (i = 0; i < 32; i++) ptl->profile_compatibility_flag[i] = get_bits1(gb); ptl->progressive_source_flag = get_bits1(gb); ptl->interlaced_source_flag = get_bits1(gb); ptl->non_packed_constraint_flag = get_bits1(gb); ptl->frame_only_constraint_flag = get_bits1(gb); if (get_bits(gb, 16) != 0) return -1; if (get_bits(gb, 16) != 0) return -1; if (get_bits(gb, 12) != 0) return -1; return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(HEVCContext *VAR_0, ProfileTierLevel *VAR_1) { int VAR_2; HEVCLocalContext *lc = VAR_0->HEVClc; GetBitContext *gb = &lc->gb; VAR_1->profile_space = get_bits(gb, 2); VAR_1->tier_flag = get_bits1(gb); VAR_1->profile_idc = get_bits(gb, 5); if (VAR_1->profile_idc == 1) av_log(VAR_0->avctx, AV_LOG_DEBUG, "Main profile bitstream\n"); else if (VAR_1->profile_idc == 2) av_log(VAR_0->avctx, AV_LOG_DEBUG, "Main10 profile bitstream\n"); else av_log(VAR_0->avctx, AV_LOG_WARNING, "No profile indication! (%d)\n", VAR_1->profile_idc); for (VAR_2 = 0; VAR_2 < 32; VAR_2++) VAR_1->profile_compatibility_flag[VAR_2] = get_bits1(gb); VAR_1->progressive_source_flag = get_bits1(gb); VAR_1->interlaced_source_flag = get_bits1(gb); VAR_1->non_packed_constraint_flag = get_bits1(gb); VAR_1->frame_only_constraint_flag = get_bits1(gb); if (get_bits(gb, 16) != 0) return -1; if (get_bits(gb, 16) != 0) return -1; if (get_bits(gb, 12) != 0) return -1; return 0; }
[ "static int FUNC_0(HEVCContext *VAR_0, ProfileTierLevel *VAR_1)\n{", "int VAR_2;", "HEVCLocalContext *lc = VAR_0->HEVClc;", "GetBitContext *gb = &lc->gb;", "VAR_1->profile_space = get_bits(gb, 2);", "VAR_1->tier_flag = get_bits1(gb);", "VAR_1->profile_idc = get_bits(gb, 5);", "if (VAR_1->profile_idc == 1)\nav_log(VAR_0->avctx, AV_LOG_DEBUG, \"Main profile bitstream\\n\");", "else if (VAR_1->profile_idc == 2)\nav_log(VAR_0->avctx, AV_LOG_DEBUG, \"Main10 profile bitstream\\n\");", "else\nav_log(VAR_0->avctx, AV_LOG_WARNING, \"No profile indication! (%d)\\n\", VAR_1->profile_idc);", "for (VAR_2 = 0; VAR_2 < 32; VAR_2++)", "VAR_1->profile_compatibility_flag[VAR_2] = get_bits1(gb);", "VAR_1->progressive_source_flag = get_bits1(gb);", "VAR_1->interlaced_source_flag = get_bits1(gb);", "VAR_1->non_packed_constraint_flag = get_bits1(gb);", "VAR_1->frame_only_constraint_flag = get_bits1(gb);", "if (get_bits(gb, 16) != 0)\nreturn -1;", "if (get_bits(gb, 16) != 0)\nreturn -1;", "if (get_bits(gb, 12) != 0)\nreturn -1;", "return 0;", "}" ]
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16,950
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu) { mmu_ctx_t ctx; int exception = 0, error_code = 0; int access_type; int ret = 0; if (rw == 2) { /* code access */ rw = 0; access_type = ACCESS_CODE; } else { /* data access */ /* XXX: put correct access by using cpu_restore_state() correctly */ access_type = ACCESS_INT; // access_type = env->access_type; } ret = get_physical_address(env, &ctx, address, rw, access_type, 1); if (ret == 0) { ret = tlb_set_page(env, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, is_user, is_softmmu); } else if (ret < 0) { #if defined (DEBUG_MMU) if (loglevel != 0) cpu_dump_state(env, logfile, fprintf, 0); #endif if (access_type == ACCESS_CODE) { exception = EXCP_ISI; switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: exception = EXCP_I_TLBMISS; env->spr[SPR_IMISS] = address; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; error_code = 1 << 18; goto tlb_miss; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: exception = EXCP_40x_ITLBMISS; error_code = 0; env->spr[SPR_40x_DEAR] = address; env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: error_code = 0x40000000; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_64BRIDGE: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; #endif case POWERPC_MMU_601: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(env, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; } break; case -2: /* Access rights violation */ error_code = 0x08000000; break; case -3: /* No execute protection violation */ error_code = 0x10000000; break; case -4: /* Direct store exception */ /* No code fetch is allowed in direct-store areas */ error_code = 0x10000000; break; case -5: /* No match in segment table */ exception = EXCP_ISEG; error_code = 0; break; } } else { exception = EXCP_DSI; switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (rw == 1) { exception = EXCP_DS_TLBMISS; error_code = 1 << 16; } else { exception = EXCP_DL_TLBMISS; error_code = 0; } env->spr[SPR_DMISS] = address; env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; tlb_miss: error_code |= ctx.key << 19; env->spr[SPR_HASH1] = ctx.pg_addr[0]; env->spr[SPR_HASH2] = ctx.pg_addr[1]; /* Do not alter DAR nor DSISR */ goto out; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: exception = EXCP_40x_DTLBMISS; error_code = 0; env->spr[SPR_40x_DEAR] = address; if (rw) env->spr[SPR_40x_ESR] = 0x00800000; else env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: error_code = 0x40000000; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_64BRIDGE: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; #endif case POWERPC_MMU_601: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(env, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; } break; case -2: /* Access rights violation */ error_code = 0x08000000; break; case -4: /* Direct store exception */ switch (access_type) { case ACCESS_FLOAT: /* Floating point load/store */ exception = EXCP_ALIGN; error_code = EXCP_ALIGN_FP; break; case ACCESS_RES: /* lwarx, ldarx or srwcx. */ error_code = 0x04000000; break; case ACCESS_EXT: /* eciwx or ecowx */ error_code = 0x04100000; break; default: printf("DSI: invalid exception (%d)\n", ret); exception = EXCP_PROGRAM; error_code = EXCP_INVAL | EXCP_INVAL_INVAL; break; } break; case -5: /* No match in segment table */ exception = EXCP_DSEG; error_code = 0; break; } if (exception == EXCP_DSI && rw == 1) error_code |= 0x02000000; /* Store fault address */ env->spr[SPR_DAR] = address; env->spr[SPR_DSISR] = error_code; } out: #if 0 printf("%s: set exception to %d %02x\n", __func__, exception, error_code); #endif env->exception_index = exception; env->error_code = error_code; ret = 1; } return ret; }
false
qemu
e1833e1f96456fd8fc17463246fe0b2050e68efb
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu) { mmu_ctx_t ctx; int exception = 0, error_code = 0; int access_type; int ret = 0; if (rw == 2) { rw = 0; access_type = ACCESS_CODE; } else { access_type = ACCESS_INT; } ret = get_physical_address(env, &ctx, address, rw, access_type, 1); if (ret == 0) { ret = tlb_set_page(env, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, is_user, is_softmmu); } else if (ret < 0) { #if defined (DEBUG_MMU) if (loglevel != 0) cpu_dump_state(env, logfile, fprintf, 0); #endif if (access_type == ACCESS_CODE) { exception = EXCP_ISI; switch (ret) { case -1: switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: exception = EXCP_I_TLBMISS; env->spr[SPR_IMISS] = address; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; error_code = 1 << 18; goto tlb_miss; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: exception = EXCP_40x_ITLBMISS; error_code = 0; env->spr[SPR_40x_DEAR] = address; env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: error_code = 0x40000000; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_64BRIDGE: cpu_abort(env, "MMU model not implemented\n"); return -1; #endif case POWERPC_MMU_601: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(env, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; } break; case -2: error_code = 0x08000000; break; case -3: error_code = 0x10000000; break; case -4: error_code = 0x10000000; break; case -5: exception = EXCP_ISEG; error_code = 0; break; } } else { exception = EXCP_DSI; switch (ret) { case -1: switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (rw == 1) { exception = EXCP_DS_TLBMISS; error_code = 1 << 16; } else { exception = EXCP_DL_TLBMISS; error_code = 0; } env->spr[SPR_DMISS] = address; env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; tlb_miss: error_code |= ctx.key << 19; env->spr[SPR_HASH1] = ctx.pg_addr[0]; env->spr[SPR_HASH2] = ctx.pg_addr[1]; goto out; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: exception = EXCP_40x_DTLBMISS; error_code = 0; env->spr[SPR_40x_DEAR] = address; if (rw) env->spr[SPR_40x_ESR] = 0x00800000; else env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: error_code = 0x40000000; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_64BRIDGE: cpu_abort(env, "MMU model not implemented\n"); return -1; #endif case POWERPC_MMU_601: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: cpu_abort(env, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(env, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; } break; case -2: error_code = 0x08000000; break; case -4: switch (access_type) { case ACCESS_FLOAT: exception = EXCP_ALIGN; error_code = EXCP_ALIGN_FP; break; case ACCESS_RES: error_code = 0x04000000; break; case ACCESS_EXT: error_code = 0x04100000; break; default: printf("DSI: invalid exception (%d)\n", ret); exception = EXCP_PROGRAM; error_code = EXCP_INVAL | EXCP_INVAL_INVAL; break; } break; case -5: exception = EXCP_DSEG; error_code = 0; break; } if (exception == EXCP_DSI && rw == 1) error_code |= 0x02000000; env->spr[SPR_DAR] = address; env->spr[SPR_DSISR] = error_code; } out: #if 0 printf("%s: set exception to %d %02x\n", __func__, exception, error_code); #endif env->exception_index = exception; env->error_code = error_code; ret = 1; } return ret; }
{ "code": [], "line_no": [] }
int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1, int VAR_2, int VAR_3, int VAR_4) { mmu_ctx_t ctx; int VAR_5 = 0, VAR_6 = 0; int VAR_7; int VAR_8 = 0; if (VAR_2 == 2) { VAR_2 = 0; VAR_7 = ACCESS_CODE; } else { VAR_7 = ACCESS_INT; } VAR_8 = get_physical_address(VAR_0, &ctx, VAR_1, VAR_2, VAR_7, 1); if (VAR_8 == 0) { VAR_8 = tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, VAR_3, VAR_4); } else if (VAR_8 < 0) { #if defined (DEBUG_MMU) if (loglevel != 0) cpu_dump_state(VAR_0, logfile, fprintf, 0); #endif if (VAR_7 == ACCESS_CODE) { VAR_5 = EXCP_ISI; switch (VAR_8) { case -1: switch (VAR_0->mmu_model) { case POWERPC_MMU_SOFT_6xx: VAR_5 = EXCP_I_TLBMISS; VAR_0->spr[SPR_IMISS] = VAR_1; VAR_0->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; VAR_6 = 1 << 18; goto tlb_miss; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: VAR_5 = EXCP_40x_ITLBMISS; VAR_6 = 0; VAR_0->spr[SPR_40x_DEAR] = VAR_1; VAR_0->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: VAR_6 = 0x40000000; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_64BRIDGE: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; #endif case POWERPC_MMU_601: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(VAR_0, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(VAR_0, "Unknown or invalid MMU model\n"); return -1; } break; case -2: VAR_6 = 0x08000000; break; case -3: VAR_6 = 0x10000000; break; case -4: VAR_6 = 0x10000000; break; case -5: VAR_5 = EXCP_ISEG; VAR_6 = 0; break; } } else { VAR_5 = EXCP_DSI; switch (VAR_8) { case -1: switch (VAR_0->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (VAR_2 == 1) { VAR_5 = EXCP_DS_TLBMISS; VAR_6 = 1 << 16; } else { VAR_5 = EXCP_DL_TLBMISS; VAR_6 = 0; } VAR_0->spr[SPR_DMISS] = VAR_1; VAR_0->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; tlb_miss: VAR_6 |= ctx.key << 19; VAR_0->spr[SPR_HASH1] = ctx.pg_addr[0]; VAR_0->spr[SPR_HASH2] = ctx.pg_addr[1]; goto out; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: VAR_5 = EXCP_40x_DTLBMISS; VAR_6 = 0; VAR_0->spr[SPR_40x_DEAR] = VAR_1; if (VAR_2) VAR_0->spr[SPR_40x_ESR] = 0x00800000; else VAR_0->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_32B: VAR_6 = 0x40000000; break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_64BRIDGE: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; #endif case POWERPC_MMU_601: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_BOOKE_FSL: cpu_abort(VAR_0, "MMU model not implemented\n"); return -1; case POWERPC_MMU_REAL_4xx: cpu_abort(VAR_0, "PowerPC 401 should never raise any MMU " "exceptions\n"); return -1; default: cpu_abort(VAR_0, "Unknown or invalid MMU model\n"); return -1; } break; case -2: VAR_6 = 0x08000000; break; case -4: switch (VAR_7) { case ACCESS_FLOAT: VAR_5 = EXCP_ALIGN; VAR_6 = EXCP_ALIGN_FP; break; case ACCESS_RES: VAR_6 = 0x04000000; break; case ACCESS_EXT: VAR_6 = 0x04100000; break; default: printf("DSI: invalid VAR_5 (%d)\n", VAR_8); VAR_5 = EXCP_PROGRAM; VAR_6 = EXCP_INVAL | EXCP_INVAL_INVAL; break; } break; case -5: VAR_5 = EXCP_DSEG; VAR_6 = 0; break; } if (VAR_5 == EXCP_DSI && VAR_2 == 1) VAR_6 |= 0x02000000; VAR_0->spr[SPR_DAR] = VAR_1; VAR_0->spr[SPR_DSISR] = VAR_6; } out: #if 0 printf("%s: set VAR_5 to %d %02x\n", __func__, VAR_5, VAR_6); #endif VAR_0->exception_index = VAR_5; VAR_0->VAR_6 = VAR_6; VAR_8 = 1; } return VAR_8; }
[ "int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1, int VAR_2,\nint VAR_3, int VAR_4)\n{", "mmu_ctx_t ctx;", "int VAR_5 = 0, VAR_6 = 0;", "int VAR_7;", "int VAR_8 = 0;", "if (VAR_2 == 2) {", "VAR_2 = 0;", "VAR_7 = ACCESS_CODE;", "} else {", "VAR_7 = ACCESS_INT;", "}", "VAR_8 = get_physical_address(VAR_0, &ctx, VAR_1, VAR_2, VAR_7, 1);", "if (VAR_8 == 0) {", "VAR_8 = tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,\nctx.raddr & TARGET_PAGE_MASK, ctx.prot,\nVAR_3, VAR_4);", "} else if (VAR_8 < 0) {", "#if defined (DEBUG_MMU)\nif (loglevel != 0)\ncpu_dump_state(VAR_0, logfile, fprintf, 0);", "#endif\nif (VAR_7 == ACCESS_CODE) {", "VAR_5 = EXCP_ISI;", "switch (VAR_8) {", "case -1:\nswitch (VAR_0->mmu_model) {", "case POWERPC_MMU_SOFT_6xx:\nVAR_5 = EXCP_I_TLBMISS;", "VAR_0->spr[SPR_IMISS] = VAR_1;", "VAR_0->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;", "VAR_6 = 1 << 18;", "goto tlb_miss;", "case POWERPC_MMU_SOFT_4xx:\ncase POWERPC_MMU_SOFT_4xx_Z:\nVAR_5 = EXCP_40x_ITLBMISS;", "VAR_6 = 0;", "VAR_0->spr[SPR_40x_DEAR] = VAR_1;", "VAR_0->spr[SPR_40x_ESR] = 0x00000000;", "break;", "case POWERPC_MMU_32B:\nVAR_6 = 0x40000000;", "break;", "#if defined(TARGET_PPC64)\ncase POWERPC_MMU_64B:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_64BRIDGE:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "#endif\ncase POWERPC_MMU_601:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_BOOKE:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_BOOKE_FSL:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_REAL_4xx:\ncpu_abort(VAR_0, \"PowerPC 401 should never raise any MMU \"\n\"exceptions\\n\");", "return -1;", "default:\ncpu_abort(VAR_0, \"Unknown or invalid MMU model\\n\");", "return -1;", "}", "break;", "case -2:\nVAR_6 = 0x08000000;", "break;", "case -3:\nVAR_6 = 0x10000000;", "break;", "case -4:\nVAR_6 = 0x10000000;", "break;", "case -5:\nVAR_5 = EXCP_ISEG;", "VAR_6 = 0;", "break;", "}", "} else {", "VAR_5 = EXCP_DSI;", "switch (VAR_8) {", "case -1:\nswitch (VAR_0->mmu_model) {", "case POWERPC_MMU_SOFT_6xx:\nif (VAR_2 == 1) {", "VAR_5 = EXCP_DS_TLBMISS;", "VAR_6 = 1 << 16;", "} else {", "VAR_5 = EXCP_DL_TLBMISS;", "VAR_6 = 0;", "}", "VAR_0->spr[SPR_DMISS] = VAR_1;", "VAR_0->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;", "tlb_miss:\nVAR_6 |= ctx.key << 19;", "VAR_0->spr[SPR_HASH1] = ctx.pg_addr[0];", "VAR_0->spr[SPR_HASH2] = ctx.pg_addr[1];", "goto out;", "case POWERPC_MMU_SOFT_4xx:\ncase POWERPC_MMU_SOFT_4xx_Z:\nVAR_5 = EXCP_40x_DTLBMISS;", "VAR_6 = 0;", "VAR_0->spr[SPR_40x_DEAR] = VAR_1;", "if (VAR_2)\nVAR_0->spr[SPR_40x_ESR] = 0x00800000;", "else\nVAR_0->spr[SPR_40x_ESR] = 0x00000000;", "break;", "case POWERPC_MMU_32B:\nVAR_6 = 0x40000000;", "break;", "#if defined(TARGET_PPC64)\ncase POWERPC_MMU_64B:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_64BRIDGE:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "#endif\ncase POWERPC_MMU_601:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_BOOKE:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_BOOKE_FSL:\ncpu_abort(VAR_0, \"MMU model not implemented\\n\");", "return -1;", "case POWERPC_MMU_REAL_4xx:\ncpu_abort(VAR_0, \"PowerPC 401 should never raise any MMU \"\n\"exceptions\\n\");", "return -1;", "default:\ncpu_abort(VAR_0, \"Unknown or invalid MMU model\\n\");", "return -1;", "}", "break;", "case -2:\nVAR_6 = 0x08000000;", "break;", "case -4:\nswitch (VAR_7) {", "case ACCESS_FLOAT:\nVAR_5 = EXCP_ALIGN;", "VAR_6 = EXCP_ALIGN_FP;", "break;", "case ACCESS_RES:\nVAR_6 = 0x04000000;", "break;", "case ACCESS_EXT:\nVAR_6 = 0x04100000;", "break;", "default:\nprintf(\"DSI: invalid VAR_5 (%d)\\n\", VAR_8);", "VAR_5 = EXCP_PROGRAM;", "VAR_6 = EXCP_INVAL | EXCP_INVAL_INVAL;", "break;", "}", "break;", "case -5:\nVAR_5 = EXCP_DSEG;", "VAR_6 = 0;", "break;", "}", "if (VAR_5 == EXCP_DSI && VAR_2 == 1)\nVAR_6 |= 0x02000000;", "VAR_0->spr[SPR_DAR] = VAR_1;", "VAR_0->spr[SPR_DSISR] = VAR_6;", "}", "out:\n#if 0\nprintf(\"%s: set VAR_5 to %d %02x\\n\",\n__func__, VAR_5, VAR_6);", "#endif\nVAR_0->exception_index = VAR_5;", "VAR_0->VAR_6 = VAR_6;", "VAR_8 = 1;", "}", "return VAR_8;", "}" ]
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16,951
static int qemu_signal_init(void) { int sigfd; sigset_t set; /* * SIG_IPI must be blocked in the main thread and must not be caught * by sigwait() in the signal thread. Otherwise, the cpu thread will * not catch it reliably. */ sigemptyset(&set); sigaddset(&set, SIG_IPI); sigaddset(&set, SIGIO); sigaddset(&set, SIGALRM); sigaddset(&set, SIGBUS); sigaddset(&set, SIGINT); sigaddset(&set, SIGHUP); sigaddset(&set, SIGTERM); pthread_sigmask(SIG_BLOCK, &set, NULL); sigdelset(&set, SIG_IPI); sigfd = qemu_signalfd(&set); if (sigfd == -1) { fprintf(stderr, "failed to create signalfd\n"); return -errno; } fcntl_setfl(sigfd, O_NONBLOCK); qemu_set_fd_handler2(sigfd, NULL, sigfd_handler, NULL, (void *)(intptr_t)sigfd); return 0; }
false
qemu
3e9418e160cd8901c83a3c88967158084f5b5c03
static int qemu_signal_init(void) { int sigfd; sigset_t set; sigemptyset(&set); sigaddset(&set, SIG_IPI); sigaddset(&set, SIGIO); sigaddset(&set, SIGALRM); sigaddset(&set, SIGBUS); sigaddset(&set, SIGINT); sigaddset(&set, SIGHUP); sigaddset(&set, SIGTERM); pthread_sigmask(SIG_BLOCK, &set, NULL); sigdelset(&set, SIG_IPI); sigfd = qemu_signalfd(&set); if (sigfd == -1) { fprintf(stderr, "failed to create signalfd\n"); return -errno; } fcntl_setfl(sigfd, O_NONBLOCK); qemu_set_fd_handler2(sigfd, NULL, sigfd_handler, NULL, (void *)(intptr_t)sigfd); return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(void) { int VAR_0; sigset_t set; sigemptyset(&set); sigaddset(&set, SIG_IPI); sigaddset(&set, SIGIO); sigaddset(&set, SIGALRM); sigaddset(&set, SIGBUS); sigaddset(&set, SIGINT); sigaddset(&set, SIGHUP); sigaddset(&set, SIGTERM); pthread_sigmask(SIG_BLOCK, &set, NULL); sigdelset(&set, SIG_IPI); VAR_0 = qemu_signalfd(&set); if (VAR_0 == -1) { fprintf(stderr, "failed to create signalfd\n"); return -errno; } fcntl_setfl(VAR_0, O_NONBLOCK); qemu_set_fd_handler2(VAR_0, NULL, sigfd_handler, NULL, (void *)(intptr_t)VAR_0); return 0; }
[ "static int FUNC_0(void)\n{", "int VAR_0;", "sigset_t set;", "sigemptyset(&set);", "sigaddset(&set, SIG_IPI);", "sigaddset(&set, SIGIO);", "sigaddset(&set, SIGALRM);", "sigaddset(&set, SIGBUS);", "sigaddset(&set, SIGINT);", "sigaddset(&set, SIGHUP);", "sigaddset(&set, SIGTERM);", "pthread_sigmask(SIG_BLOCK, &set, NULL);", "sigdelset(&set, SIG_IPI);", "VAR_0 = qemu_signalfd(&set);", "if (VAR_0 == -1) {", "fprintf(stderr, \"failed to create signalfd\\n\");", "return -errno;", "}", "fcntl_setfl(VAR_0, O_NONBLOCK);", "qemu_set_fd_handler2(VAR_0, NULL, sigfd_handler, NULL,\n(void *)(intptr_t)VAR_0);", "return 0;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3 ], [ 5 ], [ 7 ], [ 21 ], [ 23 ], [ 25 ], [ 27 ], [ 29 ], [ 31 ], [ 33 ], [ 35 ], [ 37 ], [ 41 ], [ 43 ], [ 45 ], [ 47 ], [ 49 ], [ 51 ], [ 55 ], [ 59, 61 ], [ 65 ], [ 67 ] ]
16,952
struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *env, target_ulong pc) { struct kvm_sw_breakpoint *bp; TAILQ_FOREACH(bp, &env->kvm_state->kvm_sw_breakpoints, entry) { if (bp->pc == pc) return bp; } return NULL; }
false
qemu
72cf2d4f0e181d0d3a3122e04129c58a95da713e
struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *env, target_ulong pc) { struct kvm_sw_breakpoint *bp; TAILQ_FOREACH(bp, &env->kvm_state->kvm_sw_breakpoints, entry) { if (bp->pc == pc) return bp; } return NULL; }
{ "code": [], "line_no": [] }
struct kvm_sw_breakpoint *FUNC_0(CPUState *VAR_0, target_ulong VAR_1) { struct kvm_sw_breakpoint *VAR_2; TAILQ_FOREACH(VAR_2, &VAR_0->kvm_state->kvm_sw_breakpoints, entry) { if (VAR_2->VAR_1 == VAR_1) return VAR_2; } return NULL; }
[ "struct kvm_sw_breakpoint *FUNC_0(CPUState *VAR_0,\ntarget_ulong VAR_1)\n{", "struct kvm_sw_breakpoint *VAR_2;", "TAILQ_FOREACH(VAR_2, &VAR_0->kvm_state->kvm_sw_breakpoints, entry) {", "if (VAR_2->VAR_1 == VAR_1)\nreturn VAR_2;", "}", "return NULL;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5 ], [ 7 ], [ 11 ], [ 13, 15 ], [ 17 ], [ 19 ], [ 21 ] ]
16,953
static inline void gen_intermediate_code_internal(TranslationBlock * tb, int spc, CPUSPARCState *env) { target_ulong pc_start, last_pc; uint16_t *gen_opc_end; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; int j, lj = -1; int num_insns; int max_insns; memset(dc, 0, sizeof(DisasContext)); dc->tb = tb; pc_start = tb->pc; dc->pc = pc_start; last_pc = dc->pc; dc->npc = (target_ulong) tb->cs_base; dc->cc_op = CC_OP_DYNAMIC; dc->mem_idx = cpu_mmu_index(env); dc->def = env->def; if ((dc->def->features & CPU_FEATURE_FLOAT)) dc->fpu_enabled = cpu_fpu_enabled(env); else dc->fpu_enabled = 0; #ifdef TARGET_SPARC64 dc->address_mask_32bit = env->pstate & PS_AM; #endif gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; cpu_tmp0 = tcg_temp_new(); cpu_tmp32 = tcg_temp_new_i32(); cpu_tmp64 = tcg_temp_new_i64(); cpu_dst = tcg_temp_local_new(); // loads and stores cpu_val = tcg_temp_local_new(); cpu_addr = tcg_temp_local_new(); num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) max_insns = CF_COUNT_MASK; gen_icount_start(); do { if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { TAILQ_FOREACH(bp, &env->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc, cpu_cond); gen_helper_debug(); tcg_gen_exit_tb(0); dc->is_br = 1; goto exit_gen_loop; } } } if (spc) { qemu_log("Search PC...\n"); j = gen_opc_ptr - gen_opc_buf; if (lj < j) { lj++; while (lj < j) gen_opc_instr_start[lj++] = 0; gen_opc_pc[lj] = dc->pc; gen_opc_npc[lj] = dc->npc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); last_pc = dc->pc; disas_sparc_insn(dc); num_insns++; if (dc->is_br) break; /* if the next PC is different, we abort now */ if (dc->pc != (last_pc + 4)) break; /* if we reach a page boundary, we stop generation so that the PC of a TT_TFAULT exception is always in the right page */ if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) break; /* if single step mode, we generate only one instruction and generate an exception */ if (env->singlestep_enabled || singlestep) { tcg_gen_movi_tl(cpu_pc, dc->pc); tcg_gen_exit_tb(0); break; } } while ((gen_opc_ptr < gen_opc_end) && (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) && num_insns < max_insns); exit_gen_loop: tcg_temp_free(cpu_addr); tcg_temp_free(cpu_val); tcg_temp_free(cpu_dst); tcg_temp_free_i64(cpu_tmp64); tcg_temp_free_i32(cpu_tmp32); tcg_temp_free(cpu_tmp0); if (tb->cflags & CF_LAST_IO) gen_io_end(); if (!dc->is_br) { if (dc->pc != DYNAMIC_PC && (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { /* static PC and NPC: we can use direct chaining */ gen_goto_tb(dc, 0, dc->pc, dc->npc); } else { if (dc->pc != DYNAMIC_PC) tcg_gen_movi_tl(cpu_pc, dc->pc); save_npc(dc, cpu_cond); tcg_gen_exit_tb(0); } } gen_icount_end(tb, num_insns); *gen_opc_ptr = INDEX_op_end; if (spc) { j = gen_opc_ptr - gen_opc_buf; lj++; while (lj <= j) gen_opc_instr_start[lj++] = 0; #if 0 log_page_dump(); #endif gen_opc_jump_pc[0] = dc->jump_pc[0]; gen_opc_jump_pc[1] = dc->jump_pc[1]; } else { tb->size = last_pc + 4 - pc_start; tb->icount = num_insns; } #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(pc_start, last_pc + 4 - pc_start, 0); qemu_log("\n"); } #endif }
false
qemu
72cf2d4f0e181d0d3a3122e04129c58a95da713e
static inline void gen_intermediate_code_internal(TranslationBlock * tb, int spc, CPUSPARCState *env) { target_ulong pc_start, last_pc; uint16_t *gen_opc_end; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; int j, lj = -1; int num_insns; int max_insns; memset(dc, 0, sizeof(DisasContext)); dc->tb = tb; pc_start = tb->pc; dc->pc = pc_start; last_pc = dc->pc; dc->npc = (target_ulong) tb->cs_base; dc->cc_op = CC_OP_DYNAMIC; dc->mem_idx = cpu_mmu_index(env); dc->def = env->def; if ((dc->def->features & CPU_FEATURE_FLOAT)) dc->fpu_enabled = cpu_fpu_enabled(env); else dc->fpu_enabled = 0; #ifdef TARGET_SPARC64 dc->address_mask_32bit = env->pstate & PS_AM; #endif gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; cpu_tmp0 = tcg_temp_new(); cpu_tmp32 = tcg_temp_new_i32(); cpu_tmp64 = tcg_temp_new_i64(); cpu_dst = tcg_temp_local_new(); cpu_val = tcg_temp_local_new(); cpu_addr = tcg_temp_local_new(); num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) max_insns = CF_COUNT_MASK; gen_icount_start(); do { if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { TAILQ_FOREACH(bp, &env->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc, cpu_cond); gen_helper_debug(); tcg_gen_exit_tb(0); dc->is_br = 1; goto exit_gen_loop; } } } if (spc) { qemu_log("Search PC...\n"); j = gen_opc_ptr - gen_opc_buf; if (lj < j) { lj++; while (lj < j) gen_opc_instr_start[lj++] = 0; gen_opc_pc[lj] = dc->pc; gen_opc_npc[lj] = dc->npc; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); last_pc = dc->pc; disas_sparc_insn(dc); num_insns++; if (dc->is_br) break; if (dc->pc != (last_pc + 4)) break; if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) break; if (env->singlestep_enabled || singlestep) { tcg_gen_movi_tl(cpu_pc, dc->pc); tcg_gen_exit_tb(0); break; } } while ((gen_opc_ptr < gen_opc_end) && (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) && num_insns < max_insns); exit_gen_loop: tcg_temp_free(cpu_addr); tcg_temp_free(cpu_val); tcg_temp_free(cpu_dst); tcg_temp_free_i64(cpu_tmp64); tcg_temp_free_i32(cpu_tmp32); tcg_temp_free(cpu_tmp0); if (tb->cflags & CF_LAST_IO) gen_io_end(); if (!dc->is_br) { if (dc->pc != DYNAMIC_PC && (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { gen_goto_tb(dc, 0, dc->pc, dc->npc); } else { if (dc->pc != DYNAMIC_PC) tcg_gen_movi_tl(cpu_pc, dc->pc); save_npc(dc, cpu_cond); tcg_gen_exit_tb(0); } } gen_icount_end(tb, num_insns); *gen_opc_ptr = INDEX_op_end; if (spc) { j = gen_opc_ptr - gen_opc_buf; lj++; while (lj <= j) gen_opc_instr_start[lj++] = 0; #if 0 log_page_dump(); #endif gen_opc_jump_pc[0] = dc->jump_pc[0]; gen_opc_jump_pc[1] = dc->jump_pc[1]; } else { tb->size = last_pc + 4 - pc_start; tb->icount = num_insns; } #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(pc_start, last_pc + 4 - pc_start, 0); qemu_log("\n"); } #endif }
{ "code": [], "line_no": [] }
static inline void FUNC_0(TranslationBlock * VAR_0, int VAR_1, CPUSPARCState *VAR_2) { target_ulong pc_start, last_pc; uint16_t *gen_opc_end; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; int VAR_3, VAR_4 = -1; int VAR_5; int VAR_6; memset(dc, 0, sizeof(DisasContext)); dc->VAR_0 = VAR_0; pc_start = VAR_0->pc; dc->pc = pc_start; last_pc = dc->pc; dc->npc = (target_ulong) VAR_0->cs_base; dc->cc_op = CC_OP_DYNAMIC; dc->mem_idx = cpu_mmu_index(VAR_2); dc->def = VAR_2->def; if ((dc->def->features & CPU_FEATURE_FLOAT)) dc->fpu_enabled = cpu_fpu_enabled(VAR_2); else dc->fpu_enabled = 0; #ifdef TARGET_SPARC64 dc->address_mask_32bit = VAR_2->pstate & PS_AM; #endif gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; cpu_tmp0 = tcg_temp_new(); cpu_tmp32 = tcg_temp_new_i32(); cpu_tmp64 = tcg_temp_new_i64(); cpu_dst = tcg_temp_local_new(); cpu_val = tcg_temp_local_new(); cpu_addr = tcg_temp_local_new(); VAR_5 = 0; VAR_6 = VAR_0->cflags & CF_COUNT_MASK; if (VAR_6 == 0) VAR_6 = CF_COUNT_MASK; gen_icount_start(); do { if (unlikely(!TAILQ_EMPTY(&VAR_2->breakpoints))) { TAILQ_FOREACH(bp, &VAR_2->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc, cpu_cond); gen_helper_debug(); tcg_gen_exit_tb(0); dc->is_br = 1; goto exit_gen_loop; } } } if (VAR_1) { qemu_log("Search PC...\n"); VAR_3 = gen_opc_ptr - gen_opc_buf; if (VAR_4 < VAR_3) { VAR_4++; while (VAR_4 < VAR_3) gen_opc_instr_start[VAR_4++] = 0; gen_opc_pc[VAR_4] = dc->pc; gen_opc_npc[VAR_4] = dc->npc; gen_opc_instr_start[VAR_4] = 1; gen_opc_icount[VAR_4] = VAR_5; } } if (VAR_5 + 1 == VAR_6 && (VAR_0->cflags & CF_LAST_IO)) gen_io_start(); last_pc = dc->pc; disas_sparc_insn(dc); VAR_5++; if (dc->is_br) break; if (dc->pc != (last_pc + 4)) break; if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) break; if (VAR_2->singlestep_enabled || singlestep) { tcg_gen_movi_tl(cpu_pc, dc->pc); tcg_gen_exit_tb(0); break; } } while ((gen_opc_ptr < gen_opc_end) && (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) && VAR_5 < VAR_6); exit_gen_loop: tcg_temp_free(cpu_addr); tcg_temp_free(cpu_val); tcg_temp_free(cpu_dst); tcg_temp_free_i64(cpu_tmp64); tcg_temp_free_i32(cpu_tmp32); tcg_temp_free(cpu_tmp0); if (VAR_0->cflags & CF_LAST_IO) gen_io_end(); if (!dc->is_br) { if (dc->pc != DYNAMIC_PC && (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { gen_goto_tb(dc, 0, dc->pc, dc->npc); } else { if (dc->pc != DYNAMIC_PC) tcg_gen_movi_tl(cpu_pc, dc->pc); save_npc(dc, cpu_cond); tcg_gen_exit_tb(0); } } gen_icount_end(VAR_0, VAR_5); *gen_opc_ptr = INDEX_op_end; if (VAR_1) { VAR_3 = gen_opc_ptr - gen_opc_buf; VAR_4++; while (VAR_4 <= VAR_3) gen_opc_instr_start[VAR_4++] = 0; #if 0 log_page_dump(); #endif gen_opc_jump_pc[0] = dc->jump_pc[0]; gen_opc_jump_pc[1] = dc->jump_pc[1]; } else { VAR_0->size = last_pc + 4 - pc_start; VAR_0->icount = VAR_5; } #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(pc_start, last_pc + 4 - pc_start, 0); qemu_log("\n"); } #endif }
[ "static inline void FUNC_0(TranslationBlock * VAR_0,\nint VAR_1, CPUSPARCState *VAR_2)\n{", "target_ulong pc_start, last_pc;", "uint16_t *gen_opc_end;", "DisasContext dc1, *dc = &dc1;", "CPUBreakpoint *bp;", "int VAR_3, VAR_4 = -1;", "int VAR_5;", "int VAR_6;", "memset(dc, 0, sizeof(DisasContext));", "dc->VAR_0 = VAR_0;", "pc_start = VAR_0->pc;", "dc->pc = pc_start;", "last_pc = dc->pc;", "dc->npc = (target_ulong) VAR_0->cs_base;", "dc->cc_op = CC_OP_DYNAMIC;", "dc->mem_idx = cpu_mmu_index(VAR_2);", "dc->def = VAR_2->def;", "if ((dc->def->features & CPU_FEATURE_FLOAT))\ndc->fpu_enabled = cpu_fpu_enabled(VAR_2);", "else\ndc->fpu_enabled = 0;", "#ifdef TARGET_SPARC64\ndc->address_mask_32bit = VAR_2->pstate & PS_AM;", "#endif\ngen_opc_end = gen_opc_buf + OPC_MAX_SIZE;", "cpu_tmp0 = tcg_temp_new();", "cpu_tmp32 = tcg_temp_new_i32();", "cpu_tmp64 = tcg_temp_new_i64();", "cpu_dst = tcg_temp_local_new();", "cpu_val = tcg_temp_local_new();", "cpu_addr = tcg_temp_local_new();", "VAR_5 = 0;", "VAR_6 = VAR_0->cflags & CF_COUNT_MASK;", "if (VAR_6 == 0)\nVAR_6 = CF_COUNT_MASK;", "gen_icount_start();", "do {", "if (unlikely(!TAILQ_EMPTY(&VAR_2->breakpoints))) {", "TAILQ_FOREACH(bp, &VAR_2->breakpoints, entry) {", "if (bp->pc == dc->pc) {", "if (dc->pc != pc_start)\nsave_state(dc, cpu_cond);", "gen_helper_debug();", "tcg_gen_exit_tb(0);", "dc->is_br = 1;", "goto exit_gen_loop;", "}", "}", "}", "if (VAR_1) {", "qemu_log(\"Search PC...\\n\");", "VAR_3 = gen_opc_ptr - gen_opc_buf;", "if (VAR_4 < VAR_3) {", "VAR_4++;", "while (VAR_4 < VAR_3)\ngen_opc_instr_start[VAR_4++] = 0;", "gen_opc_pc[VAR_4] = dc->pc;", "gen_opc_npc[VAR_4] = dc->npc;", "gen_opc_instr_start[VAR_4] = 1;", "gen_opc_icount[VAR_4] = VAR_5;", "}", "}", "if (VAR_5 + 1 == VAR_6 && (VAR_0->cflags & CF_LAST_IO))\ngen_io_start();", "last_pc = dc->pc;", "disas_sparc_insn(dc);", "VAR_5++;", "if (dc->is_br)\nbreak;", "if (dc->pc != (last_pc + 4))\nbreak;", "if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)\nbreak;", "if (VAR_2->singlestep_enabled || singlestep) {", "tcg_gen_movi_tl(cpu_pc, dc->pc);", "tcg_gen_exit_tb(0);", "break;", "}", "} while ((gen_opc_ptr < gen_opc_end) &&", "(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&\nVAR_5 < VAR_6);", "exit_gen_loop:\ntcg_temp_free(cpu_addr);", "tcg_temp_free(cpu_val);", "tcg_temp_free(cpu_dst);", "tcg_temp_free_i64(cpu_tmp64);", "tcg_temp_free_i32(cpu_tmp32);", "tcg_temp_free(cpu_tmp0);", "if (VAR_0->cflags & CF_LAST_IO)\ngen_io_end();", "if (!dc->is_br) {", "if (dc->pc != DYNAMIC_PC &&\n(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {", "gen_goto_tb(dc, 0, dc->pc, dc->npc);", "} else {", "if (dc->pc != DYNAMIC_PC)\ntcg_gen_movi_tl(cpu_pc, dc->pc);", "save_npc(dc, cpu_cond);", "tcg_gen_exit_tb(0);", "}", "}", "gen_icount_end(VAR_0, VAR_5);", "*gen_opc_ptr = INDEX_op_end;", "if (VAR_1) {", "VAR_3 = gen_opc_ptr - gen_opc_buf;", "VAR_4++;", "while (VAR_4 <= VAR_3)\ngen_opc_instr_start[VAR_4++] = 0;", "#if 0\nlog_page_dump();", "#endif\ngen_opc_jump_pc[0] = dc->jump_pc[0];", "gen_opc_jump_pc[1] = dc->jump_pc[1];", "} else {", "VAR_0->size = last_pc + 4 - pc_start;", "VAR_0->icount = VAR_5;", "}", "#ifdef DEBUG_DISAS\nif (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {", "qemu_log(\"--------------\\n\");", "qemu_log(\"IN: %s\\n\", lookup_symbol(pc_start));", "log_target_disas(pc_start, last_pc + 4 - pc_start, 0);", "qemu_log(\"\\n\");", "}", "#endif\n}" ]
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16,954
static void test_visitor_in_native_list_uint64(TestInputVisitorData *data, const void *unused) { test_native_list_integer_helper(data, unused, USER_DEF_NATIVE_LIST_UNION_KIND_U64); }
false
qemu
b3db211f3c80bb996a704d665fe275619f728bd4
static void test_visitor_in_native_list_uint64(TestInputVisitorData *data, const void *unused) { test_native_list_integer_helper(data, unused, USER_DEF_NATIVE_LIST_UNION_KIND_U64); }
{ "code": [], "line_no": [] }
static void FUNC_0(TestInputVisitorData *VAR_0, const void *VAR_1) { test_native_list_integer_helper(VAR_0, VAR_1, USER_DEF_NATIVE_LIST_UNION_KIND_U64); }
[ "static void FUNC_0(TestInputVisitorData *VAR_0,\nconst void *VAR_1)\n{", "test_native_list_integer_helper(VAR_0, VAR_1,\nUSER_DEF_NATIVE_LIST_UNION_KIND_U64);", "}" ]
[ 0, 0, 0 ]
[ [ 1, 3, 5 ], [ 7, 9 ], [ 11 ] ]
16,955
static int vtd_page_walk_level(dma_addr_t addr, uint64_t start, uint64_t end, vtd_page_walk_hook hook_fn, void *private, uint32_t level, bool read, bool write, bool notify_unmap) { bool read_cur, write_cur, entry_valid; uint32_t offset; uint64_t slpte; uint64_t subpage_size, subpage_mask; IOMMUTLBEntry entry; uint64_t iova = start; uint64_t iova_next; int ret = 0; trace_vtd_page_walk_level(addr, level, start, end); subpage_size = 1ULL << vtd_slpt_level_shift(level); subpage_mask = vtd_slpt_level_page_mask(level); while (iova < end) { iova_next = (iova & subpage_mask) + subpage_size; offset = vtd_iova_level_offset(iova, level); slpte = vtd_get_slpte(addr, offset); if (slpte == (uint64_t)-1) { trace_vtd_page_walk_skip_read(iova, iova_next); goto next; } if (vtd_slpte_nonzero_rsvd(slpte, level)) { trace_vtd_page_walk_skip_reserve(iova, iova_next); goto next; } /* Permissions are stacked with parents' */ read_cur = read && (slpte & VTD_SL_R); write_cur = write && (slpte & VTD_SL_W); /* * As long as we have either read/write permission, this is a * valid entry. The rule works for both page entries and page * table entries. */ entry_valid = read_cur | write_cur; if (vtd_is_last_slpte(slpte, level)) { entry.target_as = &address_space_memory; entry.iova = iova & subpage_mask; /* NOTE: this is only meaningful if entry_valid == true */ entry.translated_addr = vtd_get_slpte_addr(slpte); entry.addr_mask = ~subpage_mask; entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); if (!entry_valid && !notify_unmap) { trace_vtd_page_walk_skip_perm(iova, iova_next); goto next; } trace_vtd_page_walk_one(level, entry.iova, entry.translated_addr, entry.addr_mask, entry.perm); if (hook_fn) { ret = hook_fn(&entry, private); if (ret < 0) { return ret; } } } else { if (!entry_valid) { trace_vtd_page_walk_skip_perm(iova, iova_next); goto next; } ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte), iova, MIN(iova_next, end), hook_fn, private, level - 1, read_cur, write_cur, notify_unmap); if (ret < 0) { return ret; } } next: iova = iova_next; } return 0; }
false
qemu
37f51384ae05bd50f83308339dbffa3e78404874
static int vtd_page_walk_level(dma_addr_t addr, uint64_t start, uint64_t end, vtd_page_walk_hook hook_fn, void *private, uint32_t level, bool read, bool write, bool notify_unmap) { bool read_cur, write_cur, entry_valid; uint32_t offset; uint64_t slpte; uint64_t subpage_size, subpage_mask; IOMMUTLBEntry entry; uint64_t iova = start; uint64_t iova_next; int ret = 0; trace_vtd_page_walk_level(addr, level, start, end); subpage_size = 1ULL << vtd_slpt_level_shift(level); subpage_mask = vtd_slpt_level_page_mask(level); while (iova < end) { iova_next = (iova & subpage_mask) + subpage_size; offset = vtd_iova_level_offset(iova, level); slpte = vtd_get_slpte(addr, offset); if (slpte == (uint64_t)-1) { trace_vtd_page_walk_skip_read(iova, iova_next); goto next; } if (vtd_slpte_nonzero_rsvd(slpte, level)) { trace_vtd_page_walk_skip_reserve(iova, iova_next); goto next; } read_cur = read && (slpte & VTD_SL_R); write_cur = write && (slpte & VTD_SL_W); entry_valid = read_cur | write_cur; if (vtd_is_last_slpte(slpte, level)) { entry.target_as = &address_space_memory; entry.iova = iova & subpage_mask; entry.translated_addr = vtd_get_slpte_addr(slpte); entry.addr_mask = ~subpage_mask; entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); if (!entry_valid && !notify_unmap) { trace_vtd_page_walk_skip_perm(iova, iova_next); goto next; } trace_vtd_page_walk_one(level, entry.iova, entry.translated_addr, entry.addr_mask, entry.perm); if (hook_fn) { ret = hook_fn(&entry, private); if (ret < 0) { return ret; } } } else { if (!entry_valid) { trace_vtd_page_walk_skip_perm(iova, iova_next); goto next; } ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte), iova, MIN(iova_next, end), hook_fn, private, level - 1, read_cur, write_cur, notify_unmap); if (ret < 0) { return ret; } } next: iova = iova_next; } return 0; }
{ "code": [], "line_no": [] }
static int FUNC_0(dma_addr_t VAR_0, uint64_t VAR_1, uint64_t VAR_2, vtd_page_walk_hook VAR_3, void *VAR_4, uint32_t VAR_5, bool VAR_6, bool VAR_7, bool VAR_8) { bool read_cur, write_cur, entry_valid; uint32_t offset; uint64_t slpte; uint64_t subpage_size, subpage_mask; IOMMUTLBEntry entry; uint64_t iova = VAR_1; uint64_t iova_next; int VAR_9 = 0; trace_vtd_page_walk_level(VAR_0, VAR_5, VAR_1, VAR_2); subpage_size = 1ULL << vtd_slpt_level_shift(VAR_5); subpage_mask = vtd_slpt_level_page_mask(VAR_5); while (iova < VAR_2) { iova_next = (iova & subpage_mask) + subpage_size; offset = vtd_iova_level_offset(iova, VAR_5); slpte = vtd_get_slpte(VAR_0, offset); if (slpte == (uint64_t)-1) { trace_vtd_page_walk_skip_read(iova, iova_next); goto next; } if (vtd_slpte_nonzero_rsvd(slpte, VAR_5)) { trace_vtd_page_walk_skip_reserve(iova, iova_next); goto next; } read_cur = VAR_6 && (slpte & VTD_SL_R); write_cur = VAR_7 && (slpte & VTD_SL_W); entry_valid = read_cur | write_cur; if (vtd_is_last_slpte(slpte, VAR_5)) { entry.target_as = &address_space_memory; entry.iova = iova & subpage_mask; entry.translated_addr = vtd_get_slpte_addr(slpte); entry.addr_mask = ~subpage_mask; entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); if (!entry_valid && !VAR_8) { trace_vtd_page_walk_skip_perm(iova, iova_next); goto next; } trace_vtd_page_walk_one(VAR_5, entry.iova, entry.translated_addr, entry.addr_mask, entry.perm); if (VAR_3) { VAR_9 = VAR_3(&entry, VAR_4); if (VAR_9 < 0) { return VAR_9; } } } else { if (!entry_valid) { trace_vtd_page_walk_skip_perm(iova, iova_next); goto next; } VAR_9 = FUNC_0(vtd_get_slpte_addr(slpte), iova, MIN(iova_next, VAR_2), VAR_3, VAR_4, VAR_5 - 1, read_cur, write_cur, VAR_8); if (VAR_9 < 0) { return VAR_9; } } next: iova = iova_next; } return 0; }
[ "static int FUNC_0(dma_addr_t VAR_0, uint64_t VAR_1,\nuint64_t VAR_2, vtd_page_walk_hook VAR_3,\nvoid *VAR_4, uint32_t VAR_5,\nbool VAR_6, bool VAR_7, bool VAR_8)\n{", "bool read_cur, write_cur, entry_valid;", "uint32_t offset;", "uint64_t slpte;", "uint64_t subpage_size, subpage_mask;", "IOMMUTLBEntry entry;", "uint64_t iova = VAR_1;", "uint64_t iova_next;", "int VAR_9 = 0;", "trace_vtd_page_walk_level(VAR_0, VAR_5, VAR_1, VAR_2);", "subpage_size = 1ULL << vtd_slpt_level_shift(VAR_5);", "subpage_mask = vtd_slpt_level_page_mask(VAR_5);", "while (iova < VAR_2) {", "iova_next = (iova & subpage_mask) + subpage_size;", "offset = vtd_iova_level_offset(iova, VAR_5);", "slpte = vtd_get_slpte(VAR_0, offset);", "if (slpte == (uint64_t)-1) {", "trace_vtd_page_walk_skip_read(iova, iova_next);", "goto next;", "}", "if (vtd_slpte_nonzero_rsvd(slpte, VAR_5)) {", "trace_vtd_page_walk_skip_reserve(iova, iova_next);", "goto next;", "}", "read_cur = VAR_6 && (slpte & VTD_SL_R);", "write_cur = VAR_7 && (slpte & VTD_SL_W);", "entry_valid = read_cur | write_cur;", "if (vtd_is_last_slpte(slpte, VAR_5)) {", "entry.target_as = &address_space_memory;", "entry.iova = iova & subpage_mask;", "entry.translated_addr = vtd_get_slpte_addr(slpte);", "entry.addr_mask = ~subpage_mask;", "entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);", "if (!entry_valid && !VAR_8) {", "trace_vtd_page_walk_skip_perm(iova, iova_next);", "goto next;", "}", "trace_vtd_page_walk_one(VAR_5, entry.iova, entry.translated_addr,\nentry.addr_mask, entry.perm);", "if (VAR_3) {", "VAR_9 = VAR_3(&entry, VAR_4);", "if (VAR_9 < 0) {", "return VAR_9;", "}", "}", "} else {", "if (!entry_valid) {", "trace_vtd_page_walk_skip_perm(iova, iova_next);", "goto next;", "}", "VAR_9 = FUNC_0(vtd_get_slpte_addr(slpte), iova,\nMIN(iova_next, VAR_2), VAR_3, VAR_4,\nVAR_5 - 1, read_cur, write_cur,\nVAR_8);", "if (VAR_9 < 0) {", "return VAR_9;", "}", "}", "next:\niova = iova_next;", "}", "return 0;", "}" ]
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16,956
static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy, unsigned int queue_no, unsigned int vector) { VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector]; VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); VirtQueue *vq = virtio_get_queue(vdev, queue_no); EventNotifier *n = virtio_queue_get_guest_notifier(vq); int ret; ret = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq); return ret; }
false
qemu
9be385980d37e8f4fd33f605f5fb1c3d144170a8
static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy, unsigned int queue_no, unsigned int vector) { VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector]; VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); VirtQueue *vq = virtio_get_queue(vdev, queue_no); EventNotifier *n = virtio_queue_get_guest_notifier(vq); int ret; ret = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq); return ret; }
{ "code": [], "line_no": [] }
static int FUNC_0(VirtIOPCIProxy *VAR_0, unsigned int VAR_1, unsigned int VAR_2) { VirtIOIRQFD *irqfd = &VAR_0->vector_irqfd[VAR_2]; VirtIODevice *vdev = virtio_bus_get_device(&VAR_0->bus); VirtQueue *vq = virtio_get_queue(vdev, VAR_1); EventNotifier *n = virtio_queue_get_guest_notifier(vq); int VAR_3; VAR_3 = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq); return VAR_3; }
[ "static int FUNC_0(VirtIOPCIProxy *VAR_0,\nunsigned int VAR_1,\nunsigned int VAR_2)\n{", "VirtIOIRQFD *irqfd = &VAR_0->vector_irqfd[VAR_2];", "VirtIODevice *vdev = virtio_bus_get_device(&VAR_0->bus);", "VirtQueue *vq = virtio_get_queue(vdev, VAR_1);", "EventNotifier *n = virtio_queue_get_guest_notifier(vq);", "int VAR_3;", "VAR_3 = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq);", "return VAR_3;", "}" ]
[ 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
[ [ 1, 3, 5, 7 ], [ 9 ], [ 11 ], [ 13 ], [ 15 ], [ 17 ], [ 19 ], [ 21 ], [ 23 ] ]