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int32 0
27.3k
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stringlengths 26
142k
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bool 2
classes | project
stringclasses 2
values | commit_id
stringlengths 40
40
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stringlengths 26
131k
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dict | normalized_func
stringlengths 24
132k
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listlengths 1
2.8k
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|---|---|---|---|---|---|---|---|---|---|---|
10,203 | static void sigp_stop_and_store_status(CPUState *cs, run_on_cpu_data arg)
{
S390CPU *cpu = S390_CPU(cs);
SigpInfo *si = arg.host_ptr;
struct kvm_s390_irq irq = {
.type = KVM_S390_SIGP_STOP,
};
/* disabled wait - sleeping in user space */
if (s390_cpu_get_state(cpu) == CPU_STATE_OPERATING && cs->halted) {
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
}
switch (s390_cpu_get_state(cpu)) {
case CPU_STATE_OPERATING:
cpu->env.sigp_order = SIGP_STOP_STORE_STATUS;
kvm_s390_vcpu_interrupt(cpu, &irq);
/* store will be performed when handling the stop intercept */
break;
case CPU_STATE_STOPPED:
/* already stopped, just store the status */
cpu_synchronize_state(cs);
kvm_s390_store_status(cpu, KVM_S390_STORE_STATUS_DEF_ADDR, true);
break;
}
si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
}
| false | qemu | eabcea18f835178c1f8f088f88bf00e379f09438 | static void sigp_stop_and_store_status(CPUState *cs, run_on_cpu_data arg)
{
S390CPU *cpu = S390_CPU(cs);
SigpInfo *si = arg.host_ptr;
struct kvm_s390_irq irq = {
.type = KVM_S390_SIGP_STOP,
};
if (s390_cpu_get_state(cpu) == CPU_STATE_OPERATING && cs->halted) {
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
}
switch (s390_cpu_get_state(cpu)) {
case CPU_STATE_OPERATING:
cpu->env.sigp_order = SIGP_STOP_STORE_STATUS;
kvm_s390_vcpu_interrupt(cpu, &irq);
break;
case CPU_STATE_STOPPED:
cpu_synchronize_state(cs);
kvm_s390_store_status(cpu, KVM_S390_STORE_STATUS_DEF_ADDR, true);
break;
}
si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(CPUState *VAR_0, run_on_cpu_data VAR_1)
{
S390CPU *cpu = S390_CPU(VAR_0);
SigpInfo *si = VAR_1.host_ptr;
struct kvm_s390_irq VAR_2 = {
.type = KVM_S390_SIGP_STOP,
};
if (s390_cpu_get_state(cpu) == CPU_STATE_OPERATING && VAR_0->halted) {
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
}
switch (s390_cpu_get_state(cpu)) {
case CPU_STATE_OPERATING:
cpu->env.sigp_order = SIGP_STOP_STORE_STATUS;
kvm_s390_vcpu_interrupt(cpu, &VAR_2);
break;
case CPU_STATE_STOPPED:
cpu_synchronize_state(VAR_0);
kvm_s390_store_status(cpu, KVM_S390_STORE_STATUS_DEF_ADDR, true);
break;
}
si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
}
| [
"static void FUNC_0(CPUState *VAR_0, run_on_cpu_data VAR_1)\n{",
"S390CPU *cpu = S390_CPU(VAR_0);",
"SigpInfo *si = VAR_1.host_ptr;",
"struct kvm_s390_irq VAR_2 = {",
".type = KVM_S390_SIGP_STOP,\n};",
"if (s390_cpu_get_state(cpu) == CPU_STATE_OPERATING && VAR_0->halted) {",
"s390_cpu_set_state(CPU_STATE_STOPPED, cpu);",
"}",
"switch (s390_cpu_get_state(cpu)) {",
"case CPU_STATE_OPERATING:\ncpu->env.sigp_order = SIGP_STOP_STORE_STATUS;",
"kvm_s390_vcpu_interrupt(cpu, &VAR_2);",
"break;",
"case CPU_STATE_STOPPED:\ncpu_synchronize_state(VAR_0);",
"kvm_s390_store_status(cpu, KVM_S390_STORE_STATUS_DEF_ADDR, true);",
"break;",
"}",
"si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;",
"}"
]
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10,204 | static int xen_remove_from_physmap(XenIOState *state,
hwaddr start_addr,
ram_addr_t size)
{
unsigned long i = 0;
int rc = 0;
XenPhysmap *physmap = NULL;
hwaddr phys_offset = 0;
physmap = get_physmapping(state, start_addr, size);
if (physmap == NULL) {
return -1;
}
phys_offset = physmap->phys_offset;
size = physmap->size;
DPRINTF("unmapping vram to %"HWADDR_PRIx" - %"HWADDR_PRIx", at "
"%"HWADDR_PRIx"\n", start_addr, start_addr + size, phys_offset);
size >>= TARGET_PAGE_BITS;
start_addr >>= TARGET_PAGE_BITS;
phys_offset >>= TARGET_PAGE_BITS;
for (i = 0; i < size; i++) {
unsigned long idx = start_addr + i;
xen_pfn_t gpfn = phys_offset + i;
rc = xc_domain_add_to_physmap(xen_xc, xen_domid, XENMAPSPACE_gmfn, idx, gpfn);
if (rc) {
fprintf(stderr, "add_to_physmap MFN %"PRI_xen_pfn" to PFN %"
PRI_xen_pfn" failed: %d\n", idx, gpfn, rc);
return -rc;
}
}
QLIST_REMOVE(physmap, list);
if (state->log_for_dirtybit == physmap) {
state->log_for_dirtybit = NULL;
}
g_free(physmap);
return 0;
}
| false | qemu | 643f59322432d77165329dfabe2d040d7e30dae8 | static int xen_remove_from_physmap(XenIOState *state,
hwaddr start_addr,
ram_addr_t size)
{
unsigned long i = 0;
int rc = 0;
XenPhysmap *physmap = NULL;
hwaddr phys_offset = 0;
physmap = get_physmapping(state, start_addr, size);
if (physmap == NULL) {
return -1;
}
phys_offset = physmap->phys_offset;
size = physmap->size;
DPRINTF("unmapping vram to %"HWADDR_PRIx" - %"HWADDR_PRIx", at "
"%"HWADDR_PRIx"\n", start_addr, start_addr + size, phys_offset);
size >>= TARGET_PAGE_BITS;
start_addr >>= TARGET_PAGE_BITS;
phys_offset >>= TARGET_PAGE_BITS;
for (i = 0; i < size; i++) {
unsigned long idx = start_addr + i;
xen_pfn_t gpfn = phys_offset + i;
rc = xc_domain_add_to_physmap(xen_xc, xen_domid, XENMAPSPACE_gmfn, idx, gpfn);
if (rc) {
fprintf(stderr, "add_to_physmap MFN %"PRI_xen_pfn" to PFN %"
PRI_xen_pfn" failed: %d\n", idx, gpfn, rc);
return -rc;
}
}
QLIST_REMOVE(physmap, list);
if (state->log_for_dirtybit == physmap) {
state->log_for_dirtybit = NULL;
}
g_free(physmap);
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(XenIOState *VAR_0,
hwaddr VAR_1,
ram_addr_t VAR_2)
{
unsigned long VAR_3 = 0;
int VAR_4 = 0;
XenPhysmap *physmap = NULL;
hwaddr phys_offset = 0;
physmap = get_physmapping(VAR_0, VAR_1, VAR_2);
if (physmap == NULL) {
return -1;
}
phys_offset = physmap->phys_offset;
VAR_2 = physmap->VAR_2;
DPRINTF("unmapping vram to %"HWADDR_PRIx" - %"HWADDR_PRIx", at "
"%"HWADDR_PRIx"\n", VAR_1, VAR_1 + VAR_2, phys_offset);
VAR_2 >>= TARGET_PAGE_BITS;
VAR_1 >>= TARGET_PAGE_BITS;
phys_offset >>= TARGET_PAGE_BITS;
for (VAR_3 = 0; VAR_3 < VAR_2; VAR_3++) {
unsigned long idx = VAR_1 + VAR_3;
xen_pfn_t gpfn = phys_offset + VAR_3;
VAR_4 = xc_domain_add_to_physmap(xen_xc, xen_domid, XENMAPSPACE_gmfn, idx, gpfn);
if (VAR_4) {
fprintf(stderr, "add_to_physmap MFN %"PRI_xen_pfn" to PFN %"
PRI_xen_pfn" failed: %d\n", idx, gpfn, VAR_4);
return -VAR_4;
}
}
QLIST_REMOVE(physmap, list);
if (VAR_0->log_for_dirtybit == physmap) {
VAR_0->log_for_dirtybit = NULL;
}
g_free(physmap);
return 0;
}
| [
"static int FUNC_0(XenIOState *VAR_0,\nhwaddr VAR_1,\nram_addr_t VAR_2)\n{",
"unsigned long VAR_3 = 0;",
"int VAR_4 = 0;",
"XenPhysmap *physmap = NULL;",
"hwaddr phys_offset = 0;",
"physmap = get_physmapping(VAR_0, VAR_1, VAR_2);",
"if (physmap == NULL) {",
"return -1;",
"}",
"phys_offset = physmap->phys_offset;",
"VAR_2 = physmap->VAR_2;",
"DPRINTF(\"unmapping vram to %\"HWADDR_PRIx\" - %\"HWADDR_PRIx\", at \"\n\"%\"HWADDR_PRIx\"\\n\", VAR_1, VAR_1 + VAR_2, phys_offset);",
"VAR_2 >>= TARGET_PAGE_BITS;",
"VAR_1 >>= TARGET_PAGE_BITS;",
"phys_offset >>= TARGET_PAGE_BITS;",
"for (VAR_3 = 0; VAR_3 < VAR_2; VAR_3++) {",
"unsigned long idx = VAR_1 + VAR_3;",
"xen_pfn_t gpfn = phys_offset + VAR_3;",
"VAR_4 = xc_domain_add_to_physmap(xen_xc, xen_domid, XENMAPSPACE_gmfn, idx, gpfn);",
"if (VAR_4) {",
"fprintf(stderr, \"add_to_physmap MFN %\"PRI_xen_pfn\" to PFN %\"\nPRI_xen_pfn\" failed: %d\\n\", idx, gpfn, VAR_4);",
"return -VAR_4;",
"}",
"}",
"QLIST_REMOVE(physmap, list);",
"if (VAR_0->log_for_dirtybit == physmap) {",
"VAR_0->log_for_dirtybit = NULL;",
"}",
"g_free(physmap);",
"return 0;",
"}"
]
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|
10,205 | int json_lexer_flush(JSONLexer *lexer)
{
return lexer->state == IN_START ? 0 : json_lexer_feed_char(lexer, 0);
}
| false | qemu | b011f61931f0113b29b7cd7e921dd022e0b04834 | int json_lexer_flush(JSONLexer *lexer)
{
return lexer->state == IN_START ? 0 : json_lexer_feed_char(lexer, 0);
}
| {
"code": [],
"line_no": []
} | int FUNC_0(JSONLexer *VAR_0)
{
return VAR_0->state == IN_START ? 0 : json_lexer_feed_char(VAR_0, 0);
}
| [
"int FUNC_0(JSONLexer *VAR_0)\n{",
"return VAR_0->state == IN_START ? 0 : json_lexer_feed_char(VAR_0, 0);",
"}"
]
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|
10,206 | float64 helper_fxtod(CPUSPARCState *env, int64_t src)
{
float64 ret;
clear_float_exceptions(env);
ret = int64_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
}
| false | qemu | 7385aed20db5d83979f683b9d0048674411e963c | float64 helper_fxtod(CPUSPARCState *env, int64_t src)
{
float64 ret;
clear_float_exceptions(env);
ret = int64_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
}
| {
"code": [],
"line_no": []
} | float64 FUNC_0(CPUSPARCState *env, int64_t src)
{
float64 ret;
clear_float_exceptions(env);
ret = int64_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
}
| [
"float64 FUNC_0(CPUSPARCState *env, int64_t src)\n{",
"float64 ret;",
"clear_float_exceptions(env);",
"ret = int64_to_float64(src, &env->fp_status);",
"check_ieee_exceptions(env);",
"return ret;",
"}"
]
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|
10,207 | static void test_visitor_out_list(TestOutputVisitorData *data,
const void *unused)
{
const char *value_str = "list value";
TestStructList *p, *head = NULL;
const int max_items = 10;
bool value_bool = true;
int value_int = 10;
Error *err = NULL;
QListEntry *entry;
QObject *obj;
QList *qlist;
int i;
/* Build the list in reverse order... */
for (i = 0; i < max_items; i++) {
p = g_malloc0(sizeof(*p));
p->value = g_malloc0(sizeof(*p->value));
p->value->integer = value_int + (max_items - i - 1);
p->value->boolean = value_bool;
p->value->string = g_strdup(value_str);
p->next = head;
head = p;
}
visit_type_TestStructList(data->ov, &head, NULL, &err);
g_assert(!err);
obj = qmp_output_get_qobject(data->qov);
g_assert(obj != NULL);
g_assert(qobject_type(obj) == QTYPE_QLIST);
qlist = qobject_to_qlist(obj);
g_assert(!qlist_empty(qlist));
/* ...and ensure that the visitor sees it in order */
i = 0;
QLIST_FOREACH_ENTRY(qlist, entry) {
QDict *qdict;
g_assert(qobject_type(entry->value) == QTYPE_QDICT);
qdict = qobject_to_qdict(entry->value);
g_assert_cmpint(qdict_size(qdict), ==, 3);
g_assert_cmpint(qdict_get_int(qdict, "integer"), ==, value_int + i);
g_assert_cmpint(qdict_get_bool(qdict, "boolean"), ==, value_bool);
g_assert_cmpstr(qdict_get_str(qdict, "string"), ==, value_str);
i++;
}
g_assert_cmpint(i, ==, max_items);
QDECREF(qlist);
qapi_free_TestStructList(head);
}
| false | qemu | 3f66f764ee25f10d3e1144ebc057a949421b7728 | static void test_visitor_out_list(TestOutputVisitorData *data,
const void *unused)
{
const char *value_str = "list value";
TestStructList *p, *head = NULL;
const int max_items = 10;
bool value_bool = true;
int value_int = 10;
Error *err = NULL;
QListEntry *entry;
QObject *obj;
QList *qlist;
int i;
for (i = 0; i < max_items; i++) {
p = g_malloc0(sizeof(*p));
p->value = g_malloc0(sizeof(*p->value));
p->value->integer = value_int + (max_items - i - 1);
p->value->boolean = value_bool;
p->value->string = g_strdup(value_str);
p->next = head;
head = p;
}
visit_type_TestStructList(data->ov, &head, NULL, &err);
g_assert(!err);
obj = qmp_output_get_qobject(data->qov);
g_assert(obj != NULL);
g_assert(qobject_type(obj) == QTYPE_QLIST);
qlist = qobject_to_qlist(obj);
g_assert(!qlist_empty(qlist));
i = 0;
QLIST_FOREACH_ENTRY(qlist, entry) {
QDict *qdict;
g_assert(qobject_type(entry->value) == QTYPE_QDICT);
qdict = qobject_to_qdict(entry->value);
g_assert_cmpint(qdict_size(qdict), ==, 3);
g_assert_cmpint(qdict_get_int(qdict, "integer"), ==, value_int + i);
g_assert_cmpint(qdict_get_bool(qdict, "boolean"), ==, value_bool);
g_assert_cmpstr(qdict_get_str(qdict, "string"), ==, value_str);
i++;
}
g_assert_cmpint(i, ==, max_items);
QDECREF(qlist);
qapi_free_TestStructList(head);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(TestOutputVisitorData *VAR_0,
const void *VAR_1)
{
const char *VAR_2 = "list value";
TestStructList *p, *head = NULL;
const int VAR_3 = 10;
bool value_bool = true;
int VAR_4 = 10;
Error *err = NULL;
QListEntry *entry;
QObject *obj;
QList *qlist;
int VAR_5;
for (VAR_5 = 0; VAR_5 < VAR_3; VAR_5++) {
p = g_malloc0(sizeof(*p));
p->value = g_malloc0(sizeof(*p->value));
p->value->integer = VAR_4 + (VAR_3 - VAR_5 - 1);
p->value->boolean = value_bool;
p->value->string = g_strdup(VAR_2);
p->next = head;
head = p;
}
visit_type_TestStructList(VAR_0->ov, &head, NULL, &err);
g_assert(!err);
obj = qmp_output_get_qobject(VAR_0->qov);
g_assert(obj != NULL);
g_assert(qobject_type(obj) == QTYPE_QLIST);
qlist = qobject_to_qlist(obj);
g_assert(!qlist_empty(qlist));
VAR_5 = 0;
QLIST_FOREACH_ENTRY(qlist, entry) {
QDict *qdict;
g_assert(qobject_type(entry->value) == QTYPE_QDICT);
qdict = qobject_to_qdict(entry->value);
g_assert_cmpint(qdict_size(qdict), ==, 3);
g_assert_cmpint(qdict_get_int(qdict, "integer"), ==, VAR_4 + VAR_5);
g_assert_cmpint(qdict_get_bool(qdict, "boolean"), ==, value_bool);
g_assert_cmpstr(qdict_get_str(qdict, "string"), ==, VAR_2);
VAR_5++;
}
g_assert_cmpint(VAR_5, ==, VAR_3);
QDECREF(qlist);
qapi_free_TestStructList(head);
}
| [
"static void FUNC_0(TestOutputVisitorData *VAR_0,\nconst void *VAR_1)\n{",
"const char *VAR_2 = \"list value\";",
"TestStructList *p, *head = NULL;",
"const int VAR_3 = 10;",
"bool value_bool = true;",
"int VAR_4 = 10;",
"Error *err = NULL;",
"QListEntry *entry;",
"QObject *obj;",
"QList *qlist;",
"int VAR_5;",
"for (VAR_5 = 0; VAR_5 < VAR_3; VAR_5++) {",
"p = g_malloc0(sizeof(*p));",
"p->value = g_malloc0(sizeof(*p->value));",
"p->value->integer = VAR_4 + (VAR_3 - VAR_5 - 1);",
"p->value->boolean = value_bool;",
"p->value->string = g_strdup(VAR_2);",
"p->next = head;",
"head = p;",
"}",
"visit_type_TestStructList(VAR_0->ov, &head, NULL, &err);",
"g_assert(!err);",
"obj = qmp_output_get_qobject(VAR_0->qov);",
"g_assert(obj != NULL);",
"g_assert(qobject_type(obj) == QTYPE_QLIST);",
"qlist = qobject_to_qlist(obj);",
"g_assert(!qlist_empty(qlist));",
"VAR_5 = 0;",
"QLIST_FOREACH_ENTRY(qlist, entry) {",
"QDict *qdict;",
"g_assert(qobject_type(entry->value) == QTYPE_QDICT);",
"qdict = qobject_to_qdict(entry->value);",
"g_assert_cmpint(qdict_size(qdict), ==, 3);",
"g_assert_cmpint(qdict_get_int(qdict, \"integer\"), ==, VAR_4 + VAR_5);",
"g_assert_cmpint(qdict_get_bool(qdict, \"boolean\"), ==, value_bool);",
"g_assert_cmpstr(qdict_get_str(qdict, \"string\"), ==, VAR_2);",
"VAR_5++;",
"}",
"g_assert_cmpint(VAR_5, ==, VAR_3);",
"QDECREF(qlist);",
"qapi_free_TestStructList(head);",
"}"
]
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|
10,208 | static uint64_t qemu_opt_get_size_helper(QemuOpts *opts, const char *name,
uint64_t defval, bool del)
{
QemuOpt *opt = qemu_opt_find(opts, name);
uint64_t ret = defval;
if (opt == NULL) {
const QemuOptDesc *desc = find_desc_by_name(opts->list->desc, name);
if (desc && desc->def_value_str) {
parse_option_size(name, desc->def_value_str, &ret, &error_abort);
}
return ret;
}
assert(opt->desc && opt->desc->type == QEMU_OPT_SIZE);
ret = opt->value.uint;
if (del) {
qemu_opt_del_all(opts, name);
}
return ret;
}
| false | qemu | 435db4cf29b88b6612e30acda01cd18788dff458 | static uint64_t qemu_opt_get_size_helper(QemuOpts *opts, const char *name,
uint64_t defval, bool del)
{
QemuOpt *opt = qemu_opt_find(opts, name);
uint64_t ret = defval;
if (opt == NULL) {
const QemuOptDesc *desc = find_desc_by_name(opts->list->desc, name);
if (desc && desc->def_value_str) {
parse_option_size(name, desc->def_value_str, &ret, &error_abort);
}
return ret;
}
assert(opt->desc && opt->desc->type == QEMU_OPT_SIZE);
ret = opt->value.uint;
if (del) {
qemu_opt_del_all(opts, name);
}
return ret;
}
| {
"code": [],
"line_no": []
} | static uint64_t FUNC_0(QemuOpts *opts, const char *name,
uint64_t defval, bool del)
{
QemuOpt *opt = qemu_opt_find(opts, name);
uint64_t ret = defval;
if (opt == NULL) {
const QemuOptDesc *VAR_0 = find_desc_by_name(opts->list->VAR_0, name);
if (VAR_0 && VAR_0->def_value_str) {
parse_option_size(name, VAR_0->def_value_str, &ret, &error_abort);
}
return ret;
}
assert(opt->VAR_0 && opt->VAR_0->type == QEMU_OPT_SIZE);
ret = opt->value.uint;
if (del) {
qemu_opt_del_all(opts, name);
}
return ret;
}
| [
"static uint64_t FUNC_0(QemuOpts *opts, const char *name,\nuint64_t defval, bool del)\n{",
"QemuOpt *opt = qemu_opt_find(opts, name);",
"uint64_t ret = defval;",
"if (opt == NULL) {",
"const QemuOptDesc *VAR_0 = find_desc_by_name(opts->list->VAR_0, name);",
"if (VAR_0 && VAR_0->def_value_str) {",
"parse_option_size(name, VAR_0->def_value_str, &ret, &error_abort);",
"}",
"return ret;",
"}",
"assert(opt->VAR_0 && opt->VAR_0->type == QEMU_OPT_SIZE);",
"ret = opt->value.uint;",
"if (del) {",
"qemu_opt_del_all(opts, name);",
"}",
"return ret;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33
],
[
35
],
[
37
],
[
39
]
]
|
10,209 | static int foreach_device_config(int type, int (*func)(const char *cmdline))
{
struct device_config *conf;
int rc;
TAILQ_FOREACH(conf, &device_configs, next) {
if (conf->type != type)
continue;
rc = func(conf->cmdline);
if (0 != rc)
return rc;
}
return 0;
}
| false | qemu | 72cf2d4f0e181d0d3a3122e04129c58a95da713e | static int foreach_device_config(int type, int (*func)(const char *cmdline))
{
struct device_config *conf;
int rc;
TAILQ_FOREACH(conf, &device_configs, next) {
if (conf->type != type)
continue;
rc = func(conf->cmdline);
if (0 != rc)
return rc;
}
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(int VAR_0, int (*VAR_1)(const char *VAR_2))
{
struct device_config *VAR_3;
int VAR_4;
TAILQ_FOREACH(VAR_3, &device_configs, next) {
if (VAR_3->VAR_0 != VAR_0)
continue;
VAR_4 = VAR_1(VAR_3->VAR_2);
if (0 != VAR_4)
return VAR_4;
}
return 0;
}
| [
"static int FUNC_0(int VAR_0, int (*VAR_1)(const char *VAR_2))\n{",
"struct device_config *VAR_3;",
"int VAR_4;",
"TAILQ_FOREACH(VAR_3, &device_configs, next) {",
"if (VAR_3->VAR_0 != VAR_0)\ncontinue;",
"VAR_4 = VAR_1(VAR_3->VAR_2);",
"if (0 != VAR_4)\nreturn VAR_4;",
"}",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
11
],
[
13,
15
],
[
17
],
[
19,
21
],
[
23
],
[
25
],
[
27
]
]
|
10,210 | static BlockDriverState *bdrv_append_temp_snapshot(BlockDriverState *bs,
int flags,
QDict *snapshot_options,
Error **errp)
{
/* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */
char *tmp_filename = g_malloc0(PATH_MAX + 1);
int64_t total_size;
QemuOpts *opts = NULL;
BlockDriverState *bs_snapshot;
Error *local_err = NULL;
int ret;
/* if snapshot, we create a temporary backing file and open it
instead of opening 'filename' directly */
/* Get the required size from the image */
total_size = bdrv_getlength(bs);
if (total_size < 0) {
error_setg_errno(errp, -total_size, "Could not get image size");
goto out;
}
/* Create the temporary image */
ret = get_tmp_filename(tmp_filename, PATH_MAX + 1);
if (ret < 0) {
error_setg_errno(errp, -ret, "Could not get temporary filename");
goto out;
}
opts = qemu_opts_create(bdrv_qcow2.create_opts, NULL, 0,
&error_abort);
qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_size, &error_abort);
ret = bdrv_create(&bdrv_qcow2, tmp_filename, opts, errp);
qemu_opts_del(opts);
if (ret < 0) {
error_prepend(errp, "Could not create temporary overlay '%s': ",
tmp_filename);
goto out;
}
/* Prepare options QDict for the temporary file */
qdict_put_str(snapshot_options, "file.driver", "file");
qdict_put_str(snapshot_options, "file.filename", tmp_filename);
qdict_put_str(snapshot_options, "driver", "qcow2");
bs_snapshot = bdrv_open(NULL, NULL, snapshot_options, flags, errp);
snapshot_options = NULL;
if (!bs_snapshot) {
ret = -EINVAL;
goto out;
}
/* bdrv_append() consumes a strong reference to bs_snapshot (i.e. it will
* call bdrv_unref() on it), so in order to be able to return one, we have
* to increase bs_snapshot's refcount here */
bdrv_ref(bs_snapshot);
bdrv_append(bs_snapshot, bs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
ret = -EINVAL;
goto out;
}
g_free(tmp_filename);
return bs_snapshot;
out:
QDECREF(snapshot_options);
g_free(tmp_filename);
return NULL;
}
| false | qemu | ff6ed7141d87d26eafa2b8e4df969623e40fac49 | static BlockDriverState *bdrv_append_temp_snapshot(BlockDriverState *bs,
int flags,
QDict *snapshot_options,
Error **errp)
{
char *tmp_filename = g_malloc0(PATH_MAX + 1);
int64_t total_size;
QemuOpts *opts = NULL;
BlockDriverState *bs_snapshot;
Error *local_err = NULL;
int ret;
total_size = bdrv_getlength(bs);
if (total_size < 0) {
error_setg_errno(errp, -total_size, "Could not get image size");
goto out;
}
ret = get_tmp_filename(tmp_filename, PATH_MAX + 1);
if (ret < 0) {
error_setg_errno(errp, -ret, "Could not get temporary filename");
goto out;
}
opts = qemu_opts_create(bdrv_qcow2.create_opts, NULL, 0,
&error_abort);
qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_size, &error_abort);
ret = bdrv_create(&bdrv_qcow2, tmp_filename, opts, errp);
qemu_opts_del(opts);
if (ret < 0) {
error_prepend(errp, "Could not create temporary overlay '%s': ",
tmp_filename);
goto out;
}
qdict_put_str(snapshot_options, "file.driver", "file");
qdict_put_str(snapshot_options, "file.filename", tmp_filename);
qdict_put_str(snapshot_options, "driver", "qcow2");
bs_snapshot = bdrv_open(NULL, NULL, snapshot_options, flags, errp);
snapshot_options = NULL;
if (!bs_snapshot) {
ret = -EINVAL;
goto out;
}
bdrv_ref(bs_snapshot);
bdrv_append(bs_snapshot, bs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
ret = -EINVAL;
goto out;
}
g_free(tmp_filename);
return bs_snapshot;
out:
QDECREF(snapshot_options);
g_free(tmp_filename);
return NULL;
}
| {
"code": [],
"line_no": []
} | static BlockDriverState *FUNC_0(BlockDriverState *bs,
int flags,
QDict *snapshot_options,
Error **errp)
{
char *VAR_0 = g_malloc0(PATH_MAX + 1);
int64_t total_size;
QemuOpts *opts = NULL;
BlockDriverState *bs_snapshot;
Error *local_err = NULL;
int VAR_1;
total_size = bdrv_getlength(bs);
if (total_size < 0) {
error_setg_errno(errp, -total_size, "Could not get image size");
goto out;
}
VAR_1 = get_tmp_filename(VAR_0, PATH_MAX + 1);
if (VAR_1 < 0) {
error_setg_errno(errp, -VAR_1, "Could not get temporary filename");
goto out;
}
opts = qemu_opts_create(bdrv_qcow2.create_opts, NULL, 0,
&error_abort);
qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_size, &error_abort);
VAR_1 = bdrv_create(&bdrv_qcow2, VAR_0, opts, errp);
qemu_opts_del(opts);
if (VAR_1 < 0) {
error_prepend(errp, "Could not create temporary overlay '%s': ",
VAR_0);
goto out;
}
qdict_put_str(snapshot_options, "file.driver", "file");
qdict_put_str(snapshot_options, "file.filename", VAR_0);
qdict_put_str(snapshot_options, "driver", "qcow2");
bs_snapshot = bdrv_open(NULL, NULL, snapshot_options, flags, errp);
snapshot_options = NULL;
if (!bs_snapshot) {
VAR_1 = -EINVAL;
goto out;
}
bdrv_ref(bs_snapshot);
bdrv_append(bs_snapshot, bs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
VAR_1 = -EINVAL;
goto out;
}
g_free(VAR_0);
return bs_snapshot;
out:
QDECREF(snapshot_options);
g_free(VAR_0);
return NULL;
}
| [
"static BlockDriverState *FUNC_0(BlockDriverState *bs,\nint flags,\nQDict *snapshot_options,\nError **errp)\n{",
"char *VAR_0 = g_malloc0(PATH_MAX + 1);",
"int64_t total_size;",
"QemuOpts *opts = NULL;",
"BlockDriverState *bs_snapshot;",
"Error *local_err = NULL;",
"int VAR_1;",
"total_size = bdrv_getlength(bs);",
"if (total_size < 0) {",
"error_setg_errno(errp, -total_size, \"Could not get image size\");",
"goto out;",
"}",
"VAR_1 = get_tmp_filename(VAR_0, PATH_MAX + 1);",
"if (VAR_1 < 0) {",
"error_setg_errno(errp, -VAR_1, \"Could not get temporary filename\");",
"goto out;",
"}",
"opts = qemu_opts_create(bdrv_qcow2.create_opts, NULL, 0,\n&error_abort);",
"qemu_opt_set_number(opts, BLOCK_OPT_SIZE, total_size, &error_abort);",
"VAR_1 = bdrv_create(&bdrv_qcow2, VAR_0, opts, errp);",
"qemu_opts_del(opts);",
"if (VAR_1 < 0) {",
"error_prepend(errp, \"Could not create temporary overlay '%s': \",\nVAR_0);",
"goto out;",
"}",
"qdict_put_str(snapshot_options, \"file.driver\", \"file\");",
"qdict_put_str(snapshot_options, \"file.filename\", VAR_0);",
"qdict_put_str(snapshot_options, \"driver\", \"qcow2\");",
"bs_snapshot = bdrv_open(NULL, NULL, snapshot_options, flags, errp);",
"snapshot_options = NULL;",
"if (!bs_snapshot) {",
"VAR_1 = -EINVAL;",
"goto out;",
"}",
"bdrv_ref(bs_snapshot);",
"bdrv_append(bs_snapshot, bs, &local_err);",
"if (local_err) {",
"error_propagate(errp, local_err);",
"VAR_1 = -EINVAL;",
"goto out;",
"}",
"g_free(VAR_0);",
"return bs_snapshot;",
"out:\nQDECREF(snapshot_options);",
"g_free(VAR_0);",
"return NULL;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5,
7,
9
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
35
],
[
37
],
[
39
],
[
41
],
[
43
],
[
49
],
[
51
],
[
53
],
[
55
],
[
57
],
[
61,
63
],
[
65
],
[
67
],
[
69
],
[
71
],
[
73,
75
],
[
77
],
[
79
],
[
85
],
[
87
],
[
89
],
[
93
],
[
95
],
[
97
],
[
99
],
[
101
],
[
103
],
[
113
],
[
115
],
[
117
],
[
119
],
[
121
],
[
123
],
[
125
],
[
129
],
[
131
],
[
135,
137
],
[
139
],
[
141
],
[
143
]
]
|
10,211 | int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState *value)
{
int res;
res = bdrv_attach(value, dev);
if (res < 0) {
error_report("Can't attach drive %s to %s.%s: %s",
bdrv_get_device_name(value),
dev->id ? dev->id : dev->info->name,
name, strerror(-res));
return -1;
}
qdev_prop_set(dev, name, &value, PROP_TYPE_DRIVE);
return 0;
}
| false | qemu | fa879d62eb51253d00b6920ce1d1d9d261370a49 | int qdev_prop_set_drive(DeviceState *dev, const char *name, BlockDriverState *value)
{
int res;
res = bdrv_attach(value, dev);
if (res < 0) {
error_report("Can't attach drive %s to %s.%s: %s",
bdrv_get_device_name(value),
dev->id ? dev->id : dev->info->name,
name, strerror(-res));
return -1;
}
qdev_prop_set(dev, name, &value, PROP_TYPE_DRIVE);
return 0;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(DeviceState *VAR_0, const char *VAR_1, BlockDriverState *VAR_2)
{
int VAR_3;
VAR_3 = bdrv_attach(VAR_2, VAR_0);
if (VAR_3 < 0) {
error_report("Can't attach drive %s to %s.%s: %s",
bdrv_get_device_name(VAR_2),
VAR_0->id ? VAR_0->id : VAR_0->info->VAR_1,
VAR_1, strerror(-VAR_3));
return -1;
}
qdev_prop_set(VAR_0, VAR_1, &VAR_2, PROP_TYPE_DRIVE);
return 0;
}
| [
"int FUNC_0(DeviceState *VAR_0, const char *VAR_1, BlockDriverState *VAR_2)\n{",
"int VAR_3;",
"VAR_3 = bdrv_attach(VAR_2, VAR_0);",
"if (VAR_3 < 0) {",
"error_report(\"Can't attach drive %s to %s.%s: %s\",\nbdrv_get_device_name(VAR_2),\nVAR_0->id ? VAR_0->id : VAR_0->info->VAR_1,\nVAR_1, strerror(-VAR_3));",
"return -1;",
"}",
"qdev_prop_set(VAR_0, VAR_1, &VAR_2, PROP_TYPE_DRIVE);",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13,
15,
17,
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
]
]
|
10,214 | static inline int cris_lz(int x)
{
int r;
asm ("lz\t%1, %0\n" : "=r" (r) : "r" (x));
return r;
}
| true | qemu | 21ce148c7ec71ee32834061355a5ecfd1a11f90f | static inline int cris_lz(int x)
{
int r;
asm ("lz\t%1, %0\n" : "=r" (r) : "r" (x));
return r;
}
| {
"code": [
"static inline int cris_lz(int x)"
],
"line_no": [
1
]
} | static inline int FUNC_0(int VAR_0)
{
int VAR_1;
asm ("lz\t%1, %0\n" : "=VAR_1" (VAR_1) : "VAR_1" (VAR_0));
return VAR_1;
}
| [
"static inline int FUNC_0(int VAR_0)\n{",
"int VAR_1;",
"asm (\"lz\\t%1, %0\\n\" : \"=VAR_1\" (VAR_1) : \"VAR_1\" (VAR_0));",
"return VAR_1;",
"}"
]
| [
1,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
]
]
|
10,216 | static void amdvi_class_init(ObjectClass *klass, void* data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
X86IOMMUClass *dc_class = X86_IOMMU_CLASS(klass);
dc->reset = amdvi_reset;
dc->vmsd = &vmstate_amdvi;
dc->hotpluggable = false;
dc_class->realize = amdvi_realize;
} | true | qemu | e4f4fb1eca795e36f363b4647724221e774523c1 | static void amdvi_class_init(ObjectClass *klass, void* data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
X86IOMMUClass *dc_class = X86_IOMMU_CLASS(klass);
dc->reset = amdvi_reset;
dc->vmsd = &vmstate_amdvi;
dc->hotpluggable = false;
dc_class->realize = amdvi_realize;
} | {
"code": [],
"line_no": []
} | static void FUNC_0(ObjectClass *VAR_0, void* VAR_1)
{
DeviceClass *dc = DEVICE_CLASS(VAR_0);
X86IOMMUClass *dc_class = X86_IOMMU_CLASS(VAR_0);
dc->reset = amdvi_reset;
dc->vmsd = &vmstate_amdvi;
dc->hotpluggable = false;
dc_class->realize = amdvi_realize;
} | [
"static void FUNC_0(ObjectClass *VAR_0, void* VAR_1)\n{",
"DeviceClass *dc = DEVICE_CLASS(VAR_0);",
"X86IOMMUClass *dc_class = X86_IOMMU_CLASS(VAR_0);",
"dc->reset = amdvi_reset;",
"dc->vmsd = &vmstate_amdvi;",
"dc->hotpluggable = false;",
"dc_class->realize = amdvi_realize;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
11
],
[
13
],
[
15
],
[
17
],
[
24
]
]
|
10,217 | static void pci_ehci_config(void)
{
/* hands over all ports from companion uhci to ehci */
qpci_io_writew(ehci1.dev, ehci1.base + 0x60, 1);
}
| true | qemu | b4ba67d9a702507793c2724e56f98e9b0f7be02b | static void pci_ehci_config(void)
{
qpci_io_writew(ehci1.dev, ehci1.base + 0x60, 1);
}
| {
"code": [
" qpci_io_writew(ehci1.dev, ehci1.base + 0x60, 1);"
],
"line_no": [
7
]
} | static void FUNC_0(void)
{
qpci_io_writew(ehci1.dev, ehci1.base + 0x60, 1);
}
| [
"static void FUNC_0(void)\n{",
"qpci_io_writew(ehci1.dev, ehci1.base + 0x60, 1);",
"}"
]
| [
0,
1,
0
]
| [
[
1,
3
],
[
7
],
[
9
]
]
|
10,218 | static int v9fs_synth_renameat(FsContext *ctx, V9fsPath *olddir,
const char *old_name, V9fsPath *newdir,
const char *new_name)
{
errno = EPERM;
return -1;
}
| false | qemu | 364031f17932814484657e5551ba12957d993d7e | static int v9fs_synth_renameat(FsContext *ctx, V9fsPath *olddir,
const char *old_name, V9fsPath *newdir,
const char *new_name)
{
errno = EPERM;
return -1;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(FsContext *VAR_0, V9fsPath *VAR_1,
const char *VAR_2, V9fsPath *VAR_3,
const char *VAR_4)
{
errno = EPERM;
return -1;
}
| [
"static int FUNC_0(FsContext *VAR_0, V9fsPath *VAR_1,\nconst char *VAR_2, V9fsPath *VAR_3,\nconst char *VAR_4)\n{",
"errno = EPERM;",
"return -1;",
"}"
]
| [
0,
0,
0,
0
]
| [
[
1,
3,
5,
7
],
[
9
],
[
11
],
[
13
]
]
|
10,219 | static int vmdk_write_cid(BlockDriverState *bs, uint32_t cid)
{
char desc[DESC_SIZE], tmp_desc[DESC_SIZE];
char *p_name, *tmp_str;
BDRVVmdkState *s = bs->opaque;
memset(desc, 0, sizeof(desc));
if (bdrv_pread(bs->file, s->desc_offset, desc, DESC_SIZE) != DESC_SIZE) {
return -EIO;
}
tmp_str = strstr(desc,"parentCID");
pstrcpy(tmp_desc, sizeof(tmp_desc), tmp_str);
if ((p_name = strstr(desc,"CID")) != NULL) {
p_name += sizeof("CID");
snprintf(p_name, sizeof(desc) - (p_name - desc), "%x\n", cid);
pstrcat(desc, sizeof(desc), tmp_desc);
}
if (bdrv_pwrite_sync(bs->file, s->desc_offset, desc, DESC_SIZE) < 0) {
return -EIO;
}
return 0;
}
| false | qemu | ae261c86aaed62e7acddafab8262a2bf286d40b7 | static int vmdk_write_cid(BlockDriverState *bs, uint32_t cid)
{
char desc[DESC_SIZE], tmp_desc[DESC_SIZE];
char *p_name, *tmp_str;
BDRVVmdkState *s = bs->opaque;
memset(desc, 0, sizeof(desc));
if (bdrv_pread(bs->file, s->desc_offset, desc, DESC_SIZE) != DESC_SIZE) {
return -EIO;
}
tmp_str = strstr(desc,"parentCID");
pstrcpy(tmp_desc, sizeof(tmp_desc), tmp_str);
if ((p_name = strstr(desc,"CID")) != NULL) {
p_name += sizeof("CID");
snprintf(p_name, sizeof(desc) - (p_name - desc), "%x\n", cid);
pstrcat(desc, sizeof(desc), tmp_desc);
}
if (bdrv_pwrite_sync(bs->file, s->desc_offset, desc, DESC_SIZE) < 0) {
return -EIO;
}
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(BlockDriverState *VAR_0, uint32_t VAR_1)
{
char VAR_2[DESC_SIZE], tmp_desc[DESC_SIZE];
char *VAR_3, *VAR_4;
BDRVVmdkState *s = VAR_0->opaque;
memset(VAR_2, 0, sizeof(VAR_2));
if (bdrv_pread(VAR_0->file, s->desc_offset, VAR_2, DESC_SIZE) != DESC_SIZE) {
return -EIO;
}
VAR_4 = strstr(VAR_2,"parentCID");
pstrcpy(tmp_desc, sizeof(tmp_desc), VAR_4);
if ((VAR_3 = strstr(VAR_2,"CID")) != NULL) {
VAR_3 += sizeof("CID");
snprintf(VAR_3, sizeof(VAR_2) - (VAR_3 - VAR_2), "%x\n", VAR_1);
pstrcat(VAR_2, sizeof(VAR_2), tmp_desc);
}
if (bdrv_pwrite_sync(VAR_0->file, s->desc_offset, VAR_2, DESC_SIZE) < 0) {
return -EIO;
}
return 0;
}
| [
"static int FUNC_0(BlockDriverState *VAR_0, uint32_t VAR_1)\n{",
"char VAR_2[DESC_SIZE], tmp_desc[DESC_SIZE];",
"char *VAR_3, *VAR_4;",
"BDRVVmdkState *s = VAR_0->opaque;",
"memset(VAR_2, 0, sizeof(VAR_2));",
"if (bdrv_pread(VAR_0->file, s->desc_offset, VAR_2, DESC_SIZE) != DESC_SIZE) {",
"return -EIO;",
"}",
"VAR_4 = strstr(VAR_2,\"parentCID\");",
"pstrcpy(tmp_desc, sizeof(tmp_desc), VAR_4);",
"if ((VAR_3 = strstr(VAR_2,\"CID\")) != NULL) {",
"VAR_3 += sizeof(\"CID\");",
"snprintf(VAR_3, sizeof(VAR_2) - (VAR_3 - VAR_2), \"%x\\n\", VAR_1);",
"pstrcat(VAR_2, sizeof(VAR_2), tmp_desc);",
"}",
"if (bdrv_pwrite_sync(VAR_0->file, s->desc_offset, VAR_2, DESC_SIZE) < 0) {",
"return -EIO;",
"}",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
13
],
[
15
],
[
17
],
[
19
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33
],
[
35
],
[
39
],
[
41
],
[
43
],
[
45
],
[
47
]
]
|
10,220 | static void qemu_signal_lock(unsigned int msecs)
{
qemu_mutex_lock(&qemu_fair_mutex);
while (qemu_mutex_trylock(&qemu_global_mutex)) {
qemu_thread_signal(tcg_cpu_thread, SIGUSR1);
if (!qemu_mutex_timedlock(&qemu_global_mutex, msecs))
break;
}
qemu_mutex_unlock(&qemu_fair_mutex);
}
| false | qemu | cc84de9570ffe01a9c3c169bd62ab9586a9a080c | static void qemu_signal_lock(unsigned int msecs)
{
qemu_mutex_lock(&qemu_fair_mutex);
while (qemu_mutex_trylock(&qemu_global_mutex)) {
qemu_thread_signal(tcg_cpu_thread, SIGUSR1);
if (!qemu_mutex_timedlock(&qemu_global_mutex, msecs))
break;
}
qemu_mutex_unlock(&qemu_fair_mutex);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(unsigned int VAR_0)
{
qemu_mutex_lock(&qemu_fair_mutex);
while (qemu_mutex_trylock(&qemu_global_mutex)) {
qemu_thread_signal(tcg_cpu_thread, SIGUSR1);
if (!qemu_mutex_timedlock(&qemu_global_mutex, VAR_0))
break;
}
qemu_mutex_unlock(&qemu_fair_mutex);
}
| [
"static void FUNC_0(unsigned int VAR_0)\n{",
"qemu_mutex_lock(&qemu_fair_mutex);",
"while (qemu_mutex_trylock(&qemu_global_mutex)) {",
"qemu_thread_signal(tcg_cpu_thread, SIGUSR1);",
"if (!qemu_mutex_timedlock(&qemu_global_mutex, VAR_0))\nbreak;",
"}",
"qemu_mutex_unlock(&qemu_fair_mutex);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13,
15
],
[
17
],
[
19
],
[
21
]
]
|
10,223 | static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
/* NOP */ ;
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
/* NOP */ ;
else if (u == 0) {
switch (rd) {
case 1:
switch (sel) {
case 1:
gen_helper_mttc0_vpecontrol(cpu_env, t0);
break;
case 2:
gen_helper_mttc0_vpeconf0(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 2:
switch (sel) {
case 1:
gen_helper_mttc0_tcstatus(cpu_env, t0);
break;
case 2:
gen_helper_mttc0_tcbind(cpu_env, t0);
break;
case 3:
gen_helper_mttc0_tcrestart(cpu_env, t0);
break;
case 4:
gen_helper_mttc0_tchalt(cpu_env, t0);
break;
case 5:
gen_helper_mttc0_tccontext(cpu_env, t0);
break;
case 6:
gen_helper_mttc0_tcschedule(cpu_env, t0);
break;
case 7:
gen_helper_mttc0_tcschefback(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
case 10:
switch (sel) {
case 0:
gen_helper_mttc0_entryhi(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
case 12:
switch (sel) {
case 0:
gen_helper_mttc0_status(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
case 13:
switch (sel) {
case 0:
gen_helper_mttc0_cause(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 15:
switch (sel) {
case 1:
gen_helper_mttc0_ebase(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 23:
switch (sel) {
case 0:
gen_helper_mttc0_debug(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
default:
gen_mtc0(ctx, t0, rd, sel);
}
} else switch (sel) {
/* GPR registers. */
case 0:
gen_helper_0e1i(mttgpr, t0, rd);
break;
/* Auxiliary CPU registers */
case 1:
switch (rd) {
case 0:
gen_helper_0e1i(mttlo, t0, 0);
break;
case 1:
gen_helper_0e1i(mtthi, t0, 0);
break;
case 2:
gen_helper_0e1i(mttacx, t0, 0);
break;
case 4:
gen_helper_0e1i(mttlo, t0, 1);
break;
case 5:
gen_helper_0e1i(mtthi, t0, 1);
break;
case 6:
gen_helper_0e1i(mttacx, t0, 1);
break;
case 8:
gen_helper_0e1i(mttlo, t0, 2);
break;
case 9:
gen_helper_0e1i(mtthi, t0, 2);
break;
case 10:
gen_helper_0e1i(mttacx, t0, 2);
break;
case 12:
gen_helper_0e1i(mttlo, t0, 3);
break;
case 13:
gen_helper_0e1i(mtthi, t0, 3);
break;
case 14:
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
gen_helper_mttdsp(cpu_env, t0);
break;
default:
goto die;
}
break;
/* Floating point (COP1). */
case 2:
/* XXX: For now we support only a single FPU context. */
if (h == 0) {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, rd);
tcg_temp_free_i32(fp0);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(fp0, rd);
tcg_temp_free_i32(fp0);
}
break;
case 3:
/* XXX: For now we support only a single FPU context. */
{
TCGv_i32 fs_tmp = tcg_const_i32(rd);
gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
tcg_temp_free_i32(fs_tmp);
}
break;
/* COP2: Not implemented. */
case 4:
case 5:
/* fall through */
default:
goto die;
}
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
generate_exception(ctx, EXCP_RI);
}
| false | qemu | 7f6613cedc59fa849105668ae971dc31004bca1c | static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
;
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
;
else if (u == 0) {
switch (rd) {
case 1:
switch (sel) {
case 1:
gen_helper_mttc0_vpecontrol(cpu_env, t0);
break;
case 2:
gen_helper_mttc0_vpeconf0(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 2:
switch (sel) {
case 1:
gen_helper_mttc0_tcstatus(cpu_env, t0);
break;
case 2:
gen_helper_mttc0_tcbind(cpu_env, t0);
break;
case 3:
gen_helper_mttc0_tcrestart(cpu_env, t0);
break;
case 4:
gen_helper_mttc0_tchalt(cpu_env, t0);
break;
case 5:
gen_helper_mttc0_tccontext(cpu_env, t0);
break;
case 6:
gen_helper_mttc0_tcschedule(cpu_env, t0);
break;
case 7:
gen_helper_mttc0_tcschefback(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
case 10:
switch (sel) {
case 0:
gen_helper_mttc0_entryhi(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
case 12:
switch (sel) {
case 0:
gen_helper_mttc0_status(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
case 13:
switch (sel) {
case 0:
gen_helper_mttc0_cause(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 15:
switch (sel) {
case 1:
gen_helper_mttc0_ebase(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 23:
switch (sel) {
case 0:
gen_helper_mttc0_debug(cpu_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
break;
}
break;
default:
gen_mtc0(ctx, t0, rd, sel);
}
} else switch (sel) {
case 0:
gen_helper_0e1i(mttgpr, t0, rd);
break;
case 1:
switch (rd) {
case 0:
gen_helper_0e1i(mttlo, t0, 0);
break;
case 1:
gen_helper_0e1i(mtthi, t0, 0);
break;
case 2:
gen_helper_0e1i(mttacx, t0, 0);
break;
case 4:
gen_helper_0e1i(mttlo, t0, 1);
break;
case 5:
gen_helper_0e1i(mtthi, t0, 1);
break;
case 6:
gen_helper_0e1i(mttacx, t0, 1);
break;
case 8:
gen_helper_0e1i(mttlo, t0, 2);
break;
case 9:
gen_helper_0e1i(mtthi, t0, 2);
break;
case 10:
gen_helper_0e1i(mttacx, t0, 2);
break;
case 12:
gen_helper_0e1i(mttlo, t0, 3);
break;
case 13:
gen_helper_0e1i(mtthi, t0, 3);
break;
case 14:
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
gen_helper_mttdsp(cpu_env, t0);
break;
default:
goto die;
}
break;
case 2:
if (h == 0) {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, rd);
tcg_temp_free_i32(fp0);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(fp0, rd);
tcg_temp_free_i32(fp0);
}
break;
case 3:
{
TCGv_i32 fs_tmp = tcg_const_i32(rd);
gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
tcg_temp_free_i32(fs_tmp);
}
break;
case 4:
case 5:
default:
goto die;
}
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
generate_exception(ctx, EXCP_RI);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(CPUMIPSState *VAR_0, DisasContext *VAR_1, int VAR_2, int VAR_3,
int VAR_4, int VAR_5, int VAR_6)
{
int VAR_7 = VAR_0->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, VAR_3);
if ((VAR_0->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((VAR_0->tcs[VAR_7].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
(VAR_0->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
;
else if ((VAR_0->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
(VAR_0->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
;
else if (VAR_4 == 0) {
switch (VAR_2) {
case 1:
switch (VAR_5) {
case 1:
gen_helper_mttc0_vpecontrol(cpu_env, t0);
break;
case 2:
gen_helper_mttc0_vpeconf0(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 2:
switch (VAR_5) {
case 1:
gen_helper_mttc0_tcstatus(cpu_env, t0);
break;
case 2:
gen_helper_mttc0_tcbind(cpu_env, t0);
break;
case 3:
gen_helper_mttc0_tcrestart(cpu_env, t0);
break;
case 4:
gen_helper_mttc0_tchalt(cpu_env, t0);
break;
case 5:
gen_helper_mttc0_tccontext(cpu_env, t0);
break;
case 6:
gen_helper_mttc0_tcschedule(cpu_env, t0);
break;
case 7:
gen_helper_mttc0_tcschefback(cpu_env, t0);
break;
default:
gen_mtc0(VAR_1, t0, VAR_2, VAR_5);
break;
}
break;
case 10:
switch (VAR_5) {
case 0:
gen_helper_mttc0_entryhi(cpu_env, t0);
break;
default:
gen_mtc0(VAR_1, t0, VAR_2, VAR_5);
break;
}
case 12:
switch (VAR_5) {
case 0:
gen_helper_mttc0_status(cpu_env, t0);
break;
default:
gen_mtc0(VAR_1, t0, VAR_2, VAR_5);
break;
}
case 13:
switch (VAR_5) {
case 0:
gen_helper_mttc0_cause(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 15:
switch (VAR_5) {
case 1:
gen_helper_mttc0_ebase(cpu_env, t0);
break;
default:
goto die;
break;
}
break;
case 23:
switch (VAR_5) {
case 0:
gen_helper_mttc0_debug(cpu_env, t0);
break;
default:
gen_mtc0(VAR_1, t0, VAR_2, VAR_5);
break;
}
break;
default:
gen_mtc0(VAR_1, t0, VAR_2, VAR_5);
}
} else switch (VAR_5) {
case 0:
gen_helper_0e1i(mttgpr, t0, VAR_2);
break;
case 1:
switch (VAR_2) {
case 0:
gen_helper_0e1i(mttlo, t0, 0);
break;
case 1:
gen_helper_0e1i(mtthi, t0, 0);
break;
case 2:
gen_helper_0e1i(mttacx, t0, 0);
break;
case 4:
gen_helper_0e1i(mttlo, t0, 1);
break;
case 5:
gen_helper_0e1i(mtthi, t0, 1);
break;
case 6:
gen_helper_0e1i(mttacx, t0, 1);
break;
case 8:
gen_helper_0e1i(mttlo, t0, 2);
break;
case 9:
gen_helper_0e1i(mtthi, t0, 2);
break;
case 10:
gen_helper_0e1i(mttacx, t0, 2);
break;
case 12:
gen_helper_0e1i(mttlo, t0, 3);
break;
case 13:
gen_helper_0e1i(mtthi, t0, 3);
break;
case 14:
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
gen_helper_mttdsp(cpu_env, t0);
break;
default:
goto die;
}
break;
case 2:
if (VAR_6 == 0) {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, VAR_2);
tcg_temp_free_i32(fp0);
} else {
TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(fp0, VAR_2);
tcg_temp_free_i32(fp0);
}
break;
case 3:
{
TCGv_i32 fs_tmp = tcg_const_i32(VAR_2);
gen_helper_0e2i(ctc1, t0, fs_tmp, VAR_3);
tcg_temp_free_i32(fs_tmp);
}
break;
case 4:
case 5:
default:
goto die;
}
LOG_DISAS("mttr (reg %d VAR_4 %d VAR_5 %d VAR_6 %d)\n", VAR_2, VAR_4, VAR_5, VAR_6);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
LOG_DISAS("mttr (reg %d VAR_4 %d VAR_5 %d VAR_6 %d)\n", VAR_2, VAR_4, VAR_5, VAR_6);
generate_exception(VAR_1, EXCP_RI);
}
| [
"static void FUNC_0(CPUMIPSState *VAR_0, DisasContext *VAR_1, int VAR_2, int VAR_3,\nint VAR_4, int VAR_5, int VAR_6)\n{",
"int VAR_7 = VAR_0->CP0_VPEControl & (0xff << CP0VPECo_TargTC);",
"TCGv t0 = tcg_temp_local_new();",
"gen_load_gpr(t0, VAR_3);",
"if ((VAR_0->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&\n((VAR_0->tcs[VAR_7].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=\n(VAR_0->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))\n;",
"else if ((VAR_0->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >\n(VAR_0->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))\n;",
"else if (VAR_4 == 0) {",
"switch (VAR_2) {",
"case 1:\nswitch (VAR_5) {",
"case 1:\ngen_helper_mttc0_vpecontrol(cpu_env, t0);",
"break;",
"case 2:\ngen_helper_mttc0_vpeconf0(cpu_env, t0);",
"break;",
"default:\ngoto die;",
"break;",
"}",
"break;",
"case 2:\nswitch (VAR_5) {",
"case 1:\ngen_helper_mttc0_tcstatus(cpu_env, t0);",
"break;",
"case 2:\ngen_helper_mttc0_tcbind(cpu_env, t0);",
"break;",
"case 3:\ngen_helper_mttc0_tcrestart(cpu_env, t0);",
"break;",
"case 4:\ngen_helper_mttc0_tchalt(cpu_env, t0);",
"break;",
"case 5:\ngen_helper_mttc0_tccontext(cpu_env, t0);",
"break;",
"case 6:\ngen_helper_mttc0_tcschedule(cpu_env, t0);",
"break;",
"case 7:\ngen_helper_mttc0_tcschefback(cpu_env, t0);",
"break;",
"default:\ngen_mtc0(VAR_1, t0, VAR_2, VAR_5);",
"break;",
"}",
"break;",
"case 10:\nswitch (VAR_5) {",
"case 0:\ngen_helper_mttc0_entryhi(cpu_env, t0);",
"break;",
"default:\ngen_mtc0(VAR_1, t0, VAR_2, VAR_5);",
"break;",
"}",
"case 12:\nswitch (VAR_5) {",
"case 0:\ngen_helper_mttc0_status(cpu_env, t0);",
"break;",
"default:\ngen_mtc0(VAR_1, t0, VAR_2, VAR_5);",
"break;",
"}",
"case 13:\nswitch (VAR_5) {",
"case 0:\ngen_helper_mttc0_cause(cpu_env, t0);",
"break;",
"default:\ngoto die;",
"break;",
"}",
"break;",
"case 15:\nswitch (VAR_5) {",
"case 1:\ngen_helper_mttc0_ebase(cpu_env, t0);",
"break;",
"default:\ngoto die;",
"break;",
"}",
"break;",
"case 23:\nswitch (VAR_5) {",
"case 0:\ngen_helper_mttc0_debug(cpu_env, t0);",
"break;",
"default:\ngen_mtc0(VAR_1, t0, VAR_2, VAR_5);",
"break;",
"}",
"break;",
"default:\ngen_mtc0(VAR_1, t0, VAR_2, VAR_5);",
"}",
"} else switch (VAR_5) {",
"case 0:\ngen_helper_0e1i(mttgpr, t0, VAR_2);",
"break;",
"case 1:\nswitch (VAR_2) {",
"case 0:\ngen_helper_0e1i(mttlo, t0, 0);",
"break;",
"case 1:\ngen_helper_0e1i(mtthi, t0, 0);",
"break;",
"case 2:\ngen_helper_0e1i(mttacx, t0, 0);",
"break;",
"case 4:\ngen_helper_0e1i(mttlo, t0, 1);",
"break;",
"case 5:\ngen_helper_0e1i(mtthi, t0, 1);",
"break;",
"case 6:\ngen_helper_0e1i(mttacx, t0, 1);",
"break;",
"case 8:\ngen_helper_0e1i(mttlo, t0, 2);",
"break;",
"case 9:\ngen_helper_0e1i(mtthi, t0, 2);",
"break;",
"case 10:\ngen_helper_0e1i(mttacx, t0, 2);",
"break;",
"case 12:\ngen_helper_0e1i(mttlo, t0, 3);",
"break;",
"case 13:\ngen_helper_0e1i(mtthi, t0, 3);",
"break;",
"case 14:\ngen_helper_0e1i(mttacx, t0, 3);",
"break;",
"case 16:\ngen_helper_mttdsp(cpu_env, t0);",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 2:\nif (VAR_6 == 0) {",
"TCGv_i32 fp0 = tcg_temp_new_i32();",
"tcg_gen_trunc_tl_i32(fp0, t0);",
"gen_store_fpr32(fp0, VAR_2);",
"tcg_temp_free_i32(fp0);",
"} else {",
"TCGv_i32 fp0 = tcg_temp_new_i32();",
"tcg_gen_trunc_tl_i32(fp0, t0);",
"gen_store_fpr32h(fp0, VAR_2);",
"tcg_temp_free_i32(fp0);",
"}",
"break;",
"case 3:\n{",
"TCGv_i32 fs_tmp = tcg_const_i32(VAR_2);",
"gen_helper_0e2i(ctc1, t0, fs_tmp, VAR_3);",
"tcg_temp_free_i32(fs_tmp);",
"}",
"break;",
"case 4:\ncase 5:\ndefault:\ngoto die;",
"}",
"LOG_DISAS(\"mttr (reg %d VAR_4 %d VAR_5 %d VAR_6 %d)\\n\", VAR_2, VAR_4, VAR_5, VAR_6);",
"tcg_temp_free(t0);",
"return;",
"die:\ntcg_temp_free(t0);",
"LOG_DISAS(\"mttr (reg %d VAR_4 %d VAR_5 %d VAR_6 %d)\\n\", VAR_2, VAR_4, VAR_5, VAR_6);",
"generate_exception(VAR_1, EXCP_RI);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
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0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
13
],
[
15,
17,
19,
21
],
[
23,
25,
27
],
[
29
],
[
31
],
[
33,
35
],
[
37,
39
],
[
41
],
[
43,
45
],
[
47
],
[
49,
51
],
[
53
],
[
55
],
[
57
],
[
59,
61
],
[
63,
65
],
[
67
],
[
69,
71
],
[
73
],
[
75,
77
],
[
79
],
[
81,
83
],
[
85
],
[
87,
89
],
[
91
],
[
93,
95
],
[
97
],
[
99,
101
],
[
103
],
[
105,
107
],
[
109
],
[
111
],
[
113
],
[
115,
117
],
[
119,
121
],
[
123
],
[
125,
127
],
[
129
],
[
131
],
[
133,
135
],
[
137,
139
],
[
141
],
[
143,
145
],
[
147
],
[
149
],
[
151,
153
],
[
155,
157
],
[
159
],
[
161,
163
],
[
165
],
[
167
],
[
169
],
[
171,
173
],
[
175,
177
],
[
179
],
[
181,
183
],
[
185
],
[
187
],
[
189
],
[
191,
193
],
[
195,
197
],
[
199
],
[
201,
203
],
[
205
],
[
207
],
[
209
],
[
211,
213
],
[
215
],
[
217
],
[
221,
223
],
[
225
],
[
229,
231
],
[
233,
235
],
[
237
],
[
239,
241
],
[
243
],
[
245,
247
],
[
249
],
[
251,
253
],
[
255
],
[
257,
259
],
[
261
],
[
263,
265
],
[
267
],
[
269,
271
],
[
273
],
[
275,
277
],
[
279
],
[
281,
283
],
[
285
],
[
287,
289
],
[
291
],
[
293,
295
],
[
297
],
[
299,
301
],
[
303
],
[
305,
307
],
[
309
],
[
311,
313
],
[
315
],
[
317
],
[
321,
325
],
[
327
],
[
331
],
[
333
],
[
335
],
[
337
],
[
339
],
[
343
],
[
345
],
[
347
],
[
349
],
[
351
],
[
353,
357
],
[
359
],
[
363
],
[
365
],
[
367
],
[
369
],
[
373,
375,
379,
381
],
[
383
],
[
385
],
[
387
],
[
389
],
[
393,
395
],
[
397
],
[
399
],
[
401
]
]
|
10,224 | int net_init_slirp(const NetClientOptions *opts, const char *name,
NetClientState *peer, Error **errp)
{
/* FIXME error_setg(errp, ...) on failure */
struct slirp_config_str *config;
char *vnet;
int ret;
const NetdevUserOptions *user;
const char **dnssearch;
assert(opts->kind == NET_CLIENT_OPTIONS_KIND_USER);
user = opts->user;
vnet = user->has_net ? g_strdup(user->net) :
user->has_ip ? g_strdup_printf("%s/24", user->ip) :
NULL;
dnssearch = slirp_dnssearch(user->dnssearch);
/* all optional fields are initialized to "all bits zero" */
net_init_slirp_configs(user->hostfwd, SLIRP_CFG_HOSTFWD);
net_init_slirp_configs(user->guestfwd, 0);
ret = net_slirp_init(peer, "user", name, user->q_restrict, vnet,
user->host, user->hostname, user->tftp,
user->bootfile, user->dhcpstart, user->dns, user->smb,
user->smbserver, dnssearch);
while (slirp_configs) {
config = slirp_configs;
slirp_configs = config->next;
g_free(config);
}
g_free(vnet);
g_free(dnssearch);
return ret;
}
| false | qemu | 8d0bcba8370a4e8606dee602393a14d0c48e8bfc | int net_init_slirp(const NetClientOptions *opts, const char *name,
NetClientState *peer, Error **errp)
{
struct slirp_config_str *config;
char *vnet;
int ret;
const NetdevUserOptions *user;
const char **dnssearch;
assert(opts->kind == NET_CLIENT_OPTIONS_KIND_USER);
user = opts->user;
vnet = user->has_net ? g_strdup(user->net) :
user->has_ip ? g_strdup_printf("%s/24", user->ip) :
NULL;
dnssearch = slirp_dnssearch(user->dnssearch);
net_init_slirp_configs(user->hostfwd, SLIRP_CFG_HOSTFWD);
net_init_slirp_configs(user->guestfwd, 0);
ret = net_slirp_init(peer, "user", name, user->q_restrict, vnet,
user->host, user->hostname, user->tftp,
user->bootfile, user->dhcpstart, user->dns, user->smb,
user->smbserver, dnssearch);
while (slirp_configs) {
config = slirp_configs;
slirp_configs = config->next;
g_free(config);
}
g_free(vnet);
g_free(dnssearch);
return ret;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(const NetClientOptions *VAR_0, const char *VAR_1,
NetClientState *VAR_2, Error **VAR_3)
{
struct slirp_config_str *VAR_4;
char *VAR_5;
int VAR_6;
const NetdevUserOptions *VAR_7;
const char **VAR_8;
assert(VAR_0->kind == NET_CLIENT_OPTIONS_KIND_USER);
VAR_7 = VAR_0->VAR_7;
VAR_5 = VAR_7->has_net ? g_strdup(VAR_7->net) :
VAR_7->has_ip ? g_strdup_printf("%s/24", VAR_7->ip) :
NULL;
VAR_8 = slirp_dnssearch(VAR_7->VAR_8);
net_init_slirp_configs(VAR_7->hostfwd, SLIRP_CFG_HOSTFWD);
net_init_slirp_configs(VAR_7->guestfwd, 0);
VAR_6 = net_slirp_init(VAR_2, "VAR_7", VAR_1, VAR_7->q_restrict, VAR_5,
VAR_7->host, VAR_7->hostname, VAR_7->tftp,
VAR_7->bootfile, VAR_7->dhcpstart, VAR_7->dns, VAR_7->smb,
VAR_7->smbserver, VAR_8);
while (slirp_configs) {
VAR_4 = slirp_configs;
slirp_configs = VAR_4->next;
g_free(VAR_4);
}
g_free(VAR_5);
g_free(VAR_8);
return VAR_6;
}
| [
"int FUNC_0(const NetClientOptions *VAR_0, const char *VAR_1,\nNetClientState *VAR_2, Error **VAR_3)\n{",
"struct slirp_config_str *VAR_4;",
"char *VAR_5;",
"int VAR_6;",
"const NetdevUserOptions *VAR_7;",
"const char **VAR_8;",
"assert(VAR_0->kind == NET_CLIENT_OPTIONS_KIND_USER);",
"VAR_7 = VAR_0->VAR_7;",
"VAR_5 = VAR_7->has_net ? g_strdup(VAR_7->net) :\nVAR_7->has_ip ? g_strdup_printf(\"%s/24\", VAR_7->ip) :\nNULL;",
"VAR_8 = slirp_dnssearch(VAR_7->VAR_8);",
"net_init_slirp_configs(VAR_7->hostfwd, SLIRP_CFG_HOSTFWD);",
"net_init_slirp_configs(VAR_7->guestfwd, 0);",
"VAR_6 = net_slirp_init(VAR_2, \"VAR_7\", VAR_1, VAR_7->q_restrict, VAR_5,\nVAR_7->host, VAR_7->hostname, VAR_7->tftp,\nVAR_7->bootfile, VAR_7->dhcpstart, VAR_7->dns, VAR_7->smb,\nVAR_7->smbserver, VAR_8);",
"while (slirp_configs) {",
"VAR_4 = slirp_configs;",
"slirp_configs = VAR_4->next;",
"g_free(VAR_4);",
"}",
"g_free(VAR_5);",
"g_free(VAR_8);",
"return VAR_6;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
27,
29,
31
],
[
35
],
[
43
],
[
45
],
[
49,
51,
53,
55
],
[
59
],
[
61
],
[
63
],
[
65
],
[
67
],
[
71
],
[
73
],
[
77
],
[
79
]
]
|
10,225 | void bdrv_detach(BlockDriverState *bs, DeviceState *qdev)
{
assert(bs->peer == qdev);
bs->peer = NULL;
bs->change_cb = NULL;
bs->change_opaque = NULL;
}
| false | qemu | fa879d62eb51253d00b6920ce1d1d9d261370a49 | void bdrv_detach(BlockDriverState *bs, DeviceState *qdev)
{
assert(bs->peer == qdev);
bs->peer = NULL;
bs->change_cb = NULL;
bs->change_opaque = NULL;
}
| {
"code": [],
"line_no": []
} | void FUNC_0(BlockDriverState *VAR_0, DeviceState *VAR_1)
{
assert(VAR_0->peer == VAR_1);
VAR_0->peer = NULL;
VAR_0->change_cb = NULL;
VAR_0->change_opaque = NULL;
}
| [
"void FUNC_0(BlockDriverState *VAR_0, DeviceState *VAR_1)\n{",
"assert(VAR_0->peer == VAR_1);",
"VAR_0->peer = NULL;",
"VAR_0->change_cb = NULL;",
"VAR_0->change_opaque = NULL;",
"}"
]
| [
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
]
]
|
10,226 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
env->cp15.c2_base_mask = 0xffffc000u;
env->cp15.c2_control = 0;
env->cp15.c2_mask = 0;
}
| false | qemu | 8d5c773e323b22402abdd0beef4c7d2fc91dd0eb | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
env->cp15.c2_base_mask = 0xffffc000u;
env->cp15.c2_control = 0;
env->cp15.c2_mask = 0;
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(CPUARMState *VAR_0, const ARMCPRegInfo *VAR_1)
{
VAR_0->cp15.c2_base_mask = 0xffffc000u;
VAR_0->cp15.c2_control = 0;
VAR_0->cp15.c2_mask = 0;
}
| [
"static void FUNC_0(CPUARMState *VAR_0, const ARMCPRegInfo *VAR_1)\n{",
"VAR_0->cp15.c2_base_mask = 0xffffc000u;",
"VAR_0->cp15.c2_control = 0;",
"VAR_0->cp15.c2_mask = 0;",
"}"
]
| [
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
]
]
|
10,227 | static inline void helper_ret_protected(int shift, int is_iret, int addend)
{
uint32_t sp, new_cs, new_eip, new_eflags, new_esp, new_ss;
uint32_t new_es, new_ds, new_fs, new_gs;
uint32_t e1, e2, ss_e1, ss_e2;
int cpl, dpl, rpl, eflags_mask;
uint8_t *ssp;
sp = ESP;
if (!(env->segs[R_SS].flags & DESC_B_MASK))
sp &= 0xffff;
ssp = env->segs[R_SS].base + sp;
if (shift == 1) {
/* 32 bits */
if (is_iret)
new_eflags = ldl_kernel(ssp + 8);
new_cs = ldl_kernel(ssp + 4) & 0xffff;
new_eip = ldl_kernel(ssp);
if (is_iret && (new_eflags & VM_MASK))
goto return_to_vm86;
} else {
/* 16 bits */
if (is_iret)
new_eflags = lduw_kernel(ssp + 4);
new_cs = lduw_kernel(ssp + 2);
new_eip = lduw_kernel(ssp);
}
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (load_segment(&e1, &e2, new_cs) != 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (!(e2 & DESC_S_MASK) ||
!(e2 & DESC_CS_MASK))
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
cpl = env->hflags & HF_CPL_MASK;
rpl = new_cs & 3;
if (rpl < cpl)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
if (e2 & DESC_CS_MASK) {
if (dpl > rpl)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
} else {
if (dpl != rpl)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
}
if (!(e2 & DESC_P_MASK))
raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
if (rpl == cpl) {
/* return to same priledge level */
cpu_x86_load_seg_cache(env, R_CS, new_cs,
get_seg_base(e1, e2),
get_seg_limit(e1, e2),
e2);
new_esp = sp + (4 << shift) + ((2 * is_iret) << shift) + addend;
} else {
/* return to different priviledge level */
ssp += (4 << shift) + ((2 * is_iret) << shift) + addend;
if (shift == 1) {
/* 32 bits */
new_esp = ldl_kernel(ssp);
new_ss = ldl_kernel(ssp + 4) & 0xffff;
} else {
/* 16 bits */
new_esp = lduw_kernel(ssp);
new_ss = lduw_kernel(ssp + 2);
}
if ((new_ss & 3) != rpl)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (!(ss_e2 & DESC_S_MASK) ||
(ss_e2 & DESC_CS_MASK) ||
!(ss_e2 & DESC_W_MASK))
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
if (dpl != rpl)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (!(ss_e2 & DESC_P_MASK))
raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
cpu_x86_load_seg_cache(env, R_CS, new_cs,
get_seg_base(e1, e2),
get_seg_limit(e1, e2),
e2);
cpu_x86_load_seg_cache(env, R_SS, new_ss,
get_seg_base(ss_e1, ss_e2),
get_seg_limit(ss_e1, ss_e2),
ss_e2);
cpu_x86_set_cpl(env, rpl);
}
if (env->segs[R_SS].flags & DESC_B_MASK)
ESP = new_esp;
else
ESP = (ESP & 0xffff0000) |
(new_esp & 0xffff);
env->eip = new_eip;
if (is_iret) {
/* NOTE: 'cpl' can be different from the current CPL */
if (cpl == 0)
eflags_mask = FL_UPDATE_CPL0_MASK;
else
eflags_mask = FL_UPDATE_MASK32;
if (shift == 0)
eflags_mask &= 0xffff;
load_eflags(new_eflags, eflags_mask);
}
return;
return_to_vm86:
new_esp = ldl_kernel(ssp + 12);
new_ss = ldl_kernel(ssp + 16);
new_es = ldl_kernel(ssp + 20);
new_ds = ldl_kernel(ssp + 24);
new_fs = ldl_kernel(ssp + 28);
new_gs = ldl_kernel(ssp + 32);
/* modify processor state */
load_eflags(new_eflags, FL_UPDATE_CPL0_MASK | VM_MASK | VIF_MASK | VIP_MASK);
load_seg_vm(R_CS, new_cs);
cpu_x86_set_cpl(env, 3);
load_seg_vm(R_SS, new_ss);
load_seg_vm(R_ES, new_es);
load_seg_vm(R_DS, new_ds);
load_seg_vm(R_FS, new_fs);
load_seg_vm(R_GS, new_gs);
env->eip = new_eip;
ESP = new_esp;
}
| false | qemu | 7e84c2498f0ff3999937d18d1e9abaa030400000 | static inline void helper_ret_protected(int shift, int is_iret, int addend)
{
uint32_t sp, new_cs, new_eip, new_eflags, new_esp, new_ss;
uint32_t new_es, new_ds, new_fs, new_gs;
uint32_t e1, e2, ss_e1, ss_e2;
int cpl, dpl, rpl, eflags_mask;
uint8_t *ssp;
sp = ESP;
if (!(env->segs[R_SS].flags & DESC_B_MASK))
sp &= 0xffff;
ssp = env->segs[R_SS].base + sp;
if (shift == 1) {
if (is_iret)
new_eflags = ldl_kernel(ssp + 8);
new_cs = ldl_kernel(ssp + 4) & 0xffff;
new_eip = ldl_kernel(ssp);
if (is_iret && (new_eflags & VM_MASK))
goto return_to_vm86;
} else {
if (is_iret)
new_eflags = lduw_kernel(ssp + 4);
new_cs = lduw_kernel(ssp + 2);
new_eip = lduw_kernel(ssp);
}
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (load_segment(&e1, &e2, new_cs) != 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (!(e2 & DESC_S_MASK) ||
!(e2 & DESC_CS_MASK))
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
cpl = env->hflags & HF_CPL_MASK;
rpl = new_cs & 3;
if (rpl < cpl)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
if (e2 & DESC_CS_MASK) {
if (dpl > rpl)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
} else {
if (dpl != rpl)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
}
if (!(e2 & DESC_P_MASK))
raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
if (rpl == cpl) {
cpu_x86_load_seg_cache(env, R_CS, new_cs,
get_seg_base(e1, e2),
get_seg_limit(e1, e2),
e2);
new_esp = sp + (4 << shift) + ((2 * is_iret) << shift) + addend;
} else {
ssp += (4 << shift) + ((2 * is_iret) << shift) + addend;
if (shift == 1) {
new_esp = ldl_kernel(ssp);
new_ss = ldl_kernel(ssp + 4) & 0xffff;
} else {
new_esp = lduw_kernel(ssp);
new_ss = lduw_kernel(ssp + 2);
}
if ((new_ss & 3) != rpl)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (!(ss_e2 & DESC_S_MASK) ||
(ss_e2 & DESC_CS_MASK) ||
!(ss_e2 & DESC_W_MASK))
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
if (dpl != rpl)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (!(ss_e2 & DESC_P_MASK))
raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
cpu_x86_load_seg_cache(env, R_CS, new_cs,
get_seg_base(e1, e2),
get_seg_limit(e1, e2),
e2);
cpu_x86_load_seg_cache(env, R_SS, new_ss,
get_seg_base(ss_e1, ss_e2),
get_seg_limit(ss_e1, ss_e2),
ss_e2);
cpu_x86_set_cpl(env, rpl);
}
if (env->segs[R_SS].flags & DESC_B_MASK)
ESP = new_esp;
else
ESP = (ESP & 0xffff0000) |
(new_esp & 0xffff);
env->eip = new_eip;
if (is_iret) {
if (cpl == 0)
eflags_mask = FL_UPDATE_CPL0_MASK;
else
eflags_mask = FL_UPDATE_MASK32;
if (shift == 0)
eflags_mask &= 0xffff;
load_eflags(new_eflags, eflags_mask);
}
return;
return_to_vm86:
new_esp = ldl_kernel(ssp + 12);
new_ss = ldl_kernel(ssp + 16);
new_es = ldl_kernel(ssp + 20);
new_ds = ldl_kernel(ssp + 24);
new_fs = ldl_kernel(ssp + 28);
new_gs = ldl_kernel(ssp + 32);
load_eflags(new_eflags, FL_UPDATE_CPL0_MASK | VM_MASK | VIF_MASK | VIP_MASK);
load_seg_vm(R_CS, new_cs);
cpu_x86_set_cpl(env, 3);
load_seg_vm(R_SS, new_ss);
load_seg_vm(R_ES, new_es);
load_seg_vm(R_DS, new_ds);
load_seg_vm(R_FS, new_fs);
load_seg_vm(R_GS, new_gs);
env->eip = new_eip;
ESP = new_esp;
}
| {
"code": [],
"line_no": []
} | static inline void FUNC_0(int VAR_0, int VAR_1, int VAR_2)
{
uint32_t sp, new_cs, new_eip, new_eflags, new_esp, new_ss;
uint32_t new_es, new_ds, new_fs, new_gs;
uint32_t e1, e2, ss_e1, ss_e2;
int VAR_3, VAR_4, VAR_5, VAR_6;
uint8_t *ssp;
sp = ESP;
if (!(env->segs[R_SS].flags & DESC_B_MASK))
sp &= 0xffff;
ssp = env->segs[R_SS].base + sp;
if (VAR_0 == 1) {
if (VAR_1)
new_eflags = ldl_kernel(ssp + 8);
new_cs = ldl_kernel(ssp + 4) & 0xffff;
new_eip = ldl_kernel(ssp);
if (VAR_1 && (new_eflags & VM_MASK))
goto return_to_vm86;
} else {
if (VAR_1)
new_eflags = lduw_kernel(ssp + 4);
new_cs = lduw_kernel(ssp + 2);
new_eip = lduw_kernel(ssp);
}
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (load_segment(&e1, &e2, new_cs) != 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (!(e2 & DESC_S_MASK) ||
!(e2 & DESC_CS_MASK))
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
VAR_3 = env->hflags & HF_CPL_MASK;
VAR_5 = new_cs & 3;
if (VAR_5 < VAR_3)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
VAR_4 = (e2 >> DESC_DPL_SHIFT) & 3;
if (e2 & DESC_CS_MASK) {
if (VAR_4 > VAR_5)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
} else {
if (VAR_4 != VAR_5)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
}
if (!(e2 & DESC_P_MASK))
raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
if (VAR_5 == VAR_3) {
cpu_x86_load_seg_cache(env, R_CS, new_cs,
get_seg_base(e1, e2),
get_seg_limit(e1, e2),
e2);
new_esp = sp + (4 << VAR_0) + ((2 * VAR_1) << VAR_0) + VAR_2;
} else {
ssp += (4 << VAR_0) + ((2 * VAR_1) << VAR_0) + VAR_2;
if (VAR_0 == 1) {
new_esp = ldl_kernel(ssp);
new_ss = ldl_kernel(ssp + 4) & 0xffff;
} else {
new_esp = lduw_kernel(ssp);
new_ss = lduw_kernel(ssp + 2);
}
if ((new_ss & 3) != VAR_5)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (!(ss_e2 & DESC_S_MASK) ||
(ss_e2 & DESC_CS_MASK) ||
!(ss_e2 & DESC_W_MASK))
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
VAR_4 = (ss_e2 >> DESC_DPL_SHIFT) & 3;
if (VAR_4 != VAR_5)
raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
if (!(ss_e2 & DESC_P_MASK))
raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
cpu_x86_load_seg_cache(env, R_CS, new_cs,
get_seg_base(e1, e2),
get_seg_limit(e1, e2),
e2);
cpu_x86_load_seg_cache(env, R_SS, new_ss,
get_seg_base(ss_e1, ss_e2),
get_seg_limit(ss_e1, ss_e2),
ss_e2);
cpu_x86_set_cpl(env, VAR_5);
}
if (env->segs[R_SS].flags & DESC_B_MASK)
ESP = new_esp;
else
ESP = (ESP & 0xffff0000) |
(new_esp & 0xffff);
env->eip = new_eip;
if (VAR_1) {
if (VAR_3 == 0)
VAR_6 = FL_UPDATE_CPL0_MASK;
else
VAR_6 = FL_UPDATE_MASK32;
if (VAR_0 == 0)
VAR_6 &= 0xffff;
load_eflags(new_eflags, VAR_6);
}
return;
return_to_vm86:
new_esp = ldl_kernel(ssp + 12);
new_ss = ldl_kernel(ssp + 16);
new_es = ldl_kernel(ssp + 20);
new_ds = ldl_kernel(ssp + 24);
new_fs = ldl_kernel(ssp + 28);
new_gs = ldl_kernel(ssp + 32);
load_eflags(new_eflags, FL_UPDATE_CPL0_MASK | VM_MASK | VIF_MASK | VIP_MASK);
load_seg_vm(R_CS, new_cs);
cpu_x86_set_cpl(env, 3);
load_seg_vm(R_SS, new_ss);
load_seg_vm(R_ES, new_es);
load_seg_vm(R_DS, new_ds);
load_seg_vm(R_FS, new_fs);
load_seg_vm(R_GS, new_gs);
env->eip = new_eip;
ESP = new_esp;
}
| [
"static inline void FUNC_0(int VAR_0, int VAR_1, int VAR_2)\n{",
"uint32_t sp, new_cs, new_eip, new_eflags, new_esp, new_ss;",
"uint32_t new_es, new_ds, new_fs, new_gs;",
"uint32_t e1, e2, ss_e1, ss_e2;",
"int VAR_3, VAR_4, VAR_5, VAR_6;",
"uint8_t *ssp;",
"sp = ESP;",
"if (!(env->segs[R_SS].flags & DESC_B_MASK))\nsp &= 0xffff;",
"ssp = env->segs[R_SS].base + sp;",
"if (VAR_0 == 1) {",
"if (VAR_1)\nnew_eflags = ldl_kernel(ssp + 8);",
"new_cs = ldl_kernel(ssp + 4) & 0xffff;",
"new_eip = ldl_kernel(ssp);",
"if (VAR_1 && (new_eflags & VM_MASK))\ngoto return_to_vm86;",
"} else {",
"if (VAR_1)\nnew_eflags = lduw_kernel(ssp + 4);",
"new_cs = lduw_kernel(ssp + 2);",
"new_eip = lduw_kernel(ssp);",
"}",
"if ((new_cs & 0xfffc) == 0)\nraise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);",
"if (load_segment(&e1, &e2, new_cs) != 0)\nraise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);",
"if (!(e2 & DESC_S_MASK) ||\n!(e2 & DESC_CS_MASK))\nraise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);",
"VAR_3 = env->hflags & HF_CPL_MASK;",
"VAR_5 = new_cs & 3;",
"if (VAR_5 < VAR_3)\nraise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);",
"VAR_4 = (e2 >> DESC_DPL_SHIFT) & 3;",
"if (e2 & DESC_CS_MASK) {",
"if (VAR_4 > VAR_5)\nraise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);",
"} else {",
"if (VAR_4 != VAR_5)\nraise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);",
"}",
"if (!(e2 & DESC_P_MASK))\nraise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);",
"if (VAR_5 == VAR_3) {",
"cpu_x86_load_seg_cache(env, R_CS, new_cs,\nget_seg_base(e1, e2),\nget_seg_limit(e1, e2),\ne2);",
"new_esp = sp + (4 << VAR_0) + ((2 * VAR_1) << VAR_0) + VAR_2;",
"} else {",
"ssp += (4 << VAR_0) + ((2 * VAR_1) << VAR_0) + VAR_2;",
"if (VAR_0 == 1) {",
"new_esp = ldl_kernel(ssp);",
"new_ss = ldl_kernel(ssp + 4) & 0xffff;",
"} else {",
"new_esp = lduw_kernel(ssp);",
"new_ss = lduw_kernel(ssp + 2);",
"}",
"if ((new_ss & 3) != VAR_5)\nraise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);",
"if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)\nraise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);",
"if (!(ss_e2 & DESC_S_MASK) ||\n(ss_e2 & DESC_CS_MASK) ||\n!(ss_e2 & DESC_W_MASK))\nraise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);",
"VAR_4 = (ss_e2 >> DESC_DPL_SHIFT) & 3;",
"if (VAR_4 != VAR_5)\nraise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);",
"if (!(ss_e2 & DESC_P_MASK))\nraise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);",
"cpu_x86_load_seg_cache(env, R_CS, new_cs,\nget_seg_base(e1, e2),\nget_seg_limit(e1, e2),\ne2);",
"cpu_x86_load_seg_cache(env, R_SS, new_ss,\nget_seg_base(ss_e1, ss_e2),\nget_seg_limit(ss_e1, ss_e2),\nss_e2);",
"cpu_x86_set_cpl(env, VAR_5);",
"}",
"if (env->segs[R_SS].flags & DESC_B_MASK)\nESP = new_esp;",
"else\nESP = (ESP & 0xffff0000) |\n(new_esp & 0xffff);",
"env->eip = new_eip;",
"if (VAR_1) {",
"if (VAR_3 == 0)\nVAR_6 = FL_UPDATE_CPL0_MASK;",
"else\nVAR_6 = FL_UPDATE_MASK32;",
"if (VAR_0 == 0)\nVAR_6 &= 0xffff;",
"load_eflags(new_eflags, VAR_6);",
"}",
"return;",
"return_to_vm86:\nnew_esp = ldl_kernel(ssp + 12);",
"new_ss = ldl_kernel(ssp + 16);",
"new_es = ldl_kernel(ssp + 20);",
"new_ds = ldl_kernel(ssp + 24);",
"new_fs = ldl_kernel(ssp + 28);",
"new_gs = ldl_kernel(ssp + 32);",
"load_eflags(new_eflags, FL_UPDATE_CPL0_MASK | VM_MASK | VIF_MASK | VIP_MASK);",
"load_seg_vm(R_CS, new_cs);",
"cpu_x86_set_cpl(env, 3);",
"load_seg_vm(R_SS, new_ss);",
"load_seg_vm(R_ES, new_es);",
"load_seg_vm(R_DS, new_ds);",
"load_seg_vm(R_FS, new_fs);",
"load_seg_vm(R_GS, new_gs);",
"env->eip = new_eip;",
"ESP = new_esp;",
"}"
]
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| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
17
],
[
19,
21
],
[
23
],
[
25
],
[
29,
31
],
[
33
],
[
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[
37,
39
],
[
41
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[
45,
47
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[
49
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[
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[
53
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[
55,
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[
59,
61
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[
63,
65,
67
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[
69
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[
71
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[
73,
75
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[
77
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[
79
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[
81,
83
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[
85
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[
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89
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[
91
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[
93,
95
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[
99
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[
103,
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[
111
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113
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[
117
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[
119
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[
123
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125
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[
127
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[
131
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[
133
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[
135
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[
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[
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[
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[
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[
211,
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[
215
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217
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[
223,
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227
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[
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[
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[
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[
249
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[
251
],
[
253
],
[
255
],
[
259
],
[
261
],
[
263
]
]
|
10,228 | static int vnc_refresh_lossy_rect(VncDisplay *vd, int x, int y)
{
VncState *vs;
int sty = y / VNC_STAT_RECT;
int stx = x / VNC_STAT_RECT;
int has_dirty = 0;
y = y / VNC_STAT_RECT * VNC_STAT_RECT;
x = x / VNC_STAT_RECT * VNC_STAT_RECT;
QTAILQ_FOREACH(vs, &vd->clients, next) {
int j;
/* kernel send buffers are full -> refresh later */
if (vs->output.offset) {
continue;
}
if (!vs->lossy_rect[sty][stx]) {
continue;
}
vs->lossy_rect[sty][stx] = 0;
for (j = 0; j < VNC_STAT_RECT; ++j) {
vnc_set_bits(vs->dirty[y + j], x / 16, VNC_STAT_RECT / 16);
}
has_dirty++;
}
return has_dirty;
}
| false | qemu | 207f328afc2137d422f59293ba37b8be5d3e1617 | static int vnc_refresh_lossy_rect(VncDisplay *vd, int x, int y)
{
VncState *vs;
int sty = y / VNC_STAT_RECT;
int stx = x / VNC_STAT_RECT;
int has_dirty = 0;
y = y / VNC_STAT_RECT * VNC_STAT_RECT;
x = x / VNC_STAT_RECT * VNC_STAT_RECT;
QTAILQ_FOREACH(vs, &vd->clients, next) {
int j;
if (vs->output.offset) {
continue;
}
if (!vs->lossy_rect[sty][stx]) {
continue;
}
vs->lossy_rect[sty][stx] = 0;
for (j = 0; j < VNC_STAT_RECT; ++j) {
vnc_set_bits(vs->dirty[y + j], x / 16, VNC_STAT_RECT / 16);
}
has_dirty++;
}
return has_dirty;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(VncDisplay *VAR_0, int VAR_1, int VAR_2)
{
VncState *vs;
int VAR_3 = VAR_2 / VNC_STAT_RECT;
int VAR_4 = VAR_1 / VNC_STAT_RECT;
int VAR_5 = 0;
VAR_2 = VAR_2 / VNC_STAT_RECT * VNC_STAT_RECT;
VAR_1 = VAR_1 / VNC_STAT_RECT * VNC_STAT_RECT;
QTAILQ_FOREACH(vs, &VAR_0->clients, next) {
int j;
if (vs->output.offset) {
continue;
}
if (!vs->lossy_rect[VAR_3][VAR_4]) {
continue;
}
vs->lossy_rect[VAR_3][VAR_4] = 0;
for (j = 0; j < VNC_STAT_RECT; ++j) {
vnc_set_bits(vs->dirty[VAR_2 + j], VAR_1 / 16, VNC_STAT_RECT / 16);
}
VAR_5++;
}
return VAR_5;
}
| [
"static int FUNC_0(VncDisplay *VAR_0, int VAR_1, int VAR_2)\n{",
"VncState *vs;",
"int VAR_3 = VAR_2 / VNC_STAT_RECT;",
"int VAR_4 = VAR_1 / VNC_STAT_RECT;",
"int VAR_5 = 0;",
"VAR_2 = VAR_2 / VNC_STAT_RECT * VNC_STAT_RECT;",
"VAR_1 = VAR_1 / VNC_STAT_RECT * VNC_STAT_RECT;",
"QTAILQ_FOREACH(vs, &VAR_0->clients, next) {",
"int j;",
"if (vs->output.offset) {",
"continue;",
"}",
"if (!vs->lossy_rect[VAR_3][VAR_4]) {",
"continue;",
"}",
"vs->lossy_rect[VAR_3][VAR_4] = 0;",
"for (j = 0; j < VNC_STAT_RECT; ++j) {",
"vnc_set_bits(vs->dirty[VAR_2 + j], VAR_1 / 16, VNC_STAT_RECT / 16);",
"}",
"VAR_5++;",
"}",
"return VAR_5;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
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0,
0,
0,
0,
0,
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0,
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0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17
],
[
21
],
[
23
],
[
29
],
[
31
],
[
33
],
[
37
],
[
39
],
[
41
],
[
43
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[
45
],
[
47
],
[
49
],
[
51
],
[
53
],
[
55
],
[
57
]
]
|
10,229 | void cpu_exec_step_atomic(CPUState *cpu)
{
start_exclusive();
/* Since we got here, we know that parallel_cpus must be true. */
parallel_cpus = false;
cpu_exec_step(cpu);
parallel_cpus = true;
end_exclusive();
}
| false | qemu | ac03ee5331612e44beb393df2b578c951d27dc0d | void cpu_exec_step_atomic(CPUState *cpu)
{
start_exclusive();
parallel_cpus = false;
cpu_exec_step(cpu);
parallel_cpus = true;
end_exclusive();
}
| {
"code": [],
"line_no": []
} | void FUNC_0(CPUState *VAR_0)
{
start_exclusive();
parallel_cpus = false;
cpu_exec_step(VAR_0);
parallel_cpus = true;
end_exclusive();
}
| [
"void FUNC_0(CPUState *VAR_0)\n{",
"start_exclusive();",
"parallel_cpus = false;",
"cpu_exec_step(VAR_0);",
"parallel_cpus = true;",
"end_exclusive();",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
11
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[
13
],
[
15
],
[
19
],
[
21
]
]
|
10,230 | void acpi_build(AcpiBuildTables *tables)
{
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
GArray *table_offsets;
unsigned facs, dsdt, rsdt, fadt;
AcpiCpuInfo cpu;
AcpiPmInfo pm;
AcpiMiscInfo misc;
AcpiMcfgInfo mcfg;
PcPciInfo pci;
uint8_t *u;
size_t aml_len = 0;
GArray *tables_blob = tables->table_data;
AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
acpi_get_cpu_info(&cpu);
acpi_get_pm_info(&pm);
acpi_get_misc_info(&misc);
acpi_get_pci_info(&pci);
acpi_get_slic_oem(&slic_oem);
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
ACPI_BUILD_DPRINTF("init ACPI tables\n");
bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
64 /* Ensure FACS is aligned */,
false /* high memory */);
/*
* FACS is pointed to by FADT.
* We place it first since it's the only table that has alignment
* requirements.
*/
facs = tables_blob->len;
build_facs(tables_blob, tables->linker);
/* DSDT is pointed to by FADT */
dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci);
/* Count the size of the DSDT and SSDT, we will need it for legacy
* sizing of ACPI tables.
*/
aml_len += tables_blob->len - dsdt;
/* ACPI tables pointed to by RSDT */
fadt = tables_blob->len;
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
slic_oem.id, slic_oem.table_id);
aml_len += tables_blob->len - fadt;
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, &cpu);
if (misc.has_hpet) {
acpi_add_table(table_offsets, tables_blob);
build_hpet(tables_blob, tables->linker);
}
if (misc.tpm_version != TPM_VERSION_UNSPEC) {
acpi_add_table(table_offsets, tables_blob);
build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
if (misc.tpm_version == TPM_VERSION_2_0) {
acpi_add_table(table_offsets, tables_blob);
build_tpm2(tables_blob, tables->linker);
}
}
if (pcms->numa_nodes) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker);
}
if (acpi_get_mcfg(&mcfg)) {
acpi_add_table(table_offsets, tables_blob);
build_mcfg_q35(tables_blob, tables->linker, &mcfg);
}
if (acpi_has_iommu()) {
acpi_add_table(table_offsets, tables_blob);
build_dmar_q35(tables_blob, tables->linker);
}
if (acpi_has_nvdimm()) {
nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
}
/* Add tables supplied by user (if any) */
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
unsigned len = acpi_table_len(u);
acpi_add_table(table_offsets, tables_blob);
g_array_append_vals(tables_blob, u, len);
}
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets,
slic_oem.id, slic_oem.table_id);
/* RSDP is in FSEG memory, so allocate it separately */
build_rsdp(tables->rsdp, tables->linker, rsdt);
/* We'll expose it all to Guest so we want to reduce
* chance of size changes.
*
* We used to align the tables to 4k, but of course this would
* too simple to be enough. 4k turned out to be too small an
* alignment very soon, and in fact it is almost impossible to
* keep the table size stable for all (max_cpus, max_memory_slots)
* combinations. So the table size is always 64k for pc-i440fx-2.1
* and we give an error if the table grows beyond that limit.
*
* We still have the problem of migrating from "-M pc-i440fx-2.0". For
* that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
* than 2.0 and we can always pad the smaller tables with zeros. We can
* then use the exact size of the 2.0 tables.
*
* All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
*/
if (pcmc->legacy_acpi_table_size) {
/* Subtracting aml_len gives the size of fixed tables. Then add the
* size of the PIIX4 DSDT/SSDT in QEMU 2.0.
*/
int legacy_aml_len =
pcmc->legacy_acpi_table_size +
ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
int legacy_table_size =
ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
ACPI_BUILD_ALIGN_SIZE);
if (tables_blob->len > legacy_table_size) {
/* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
error_report("Warning: migration may not work.");
}
g_array_set_size(tables_blob, legacy_table_size);
} else {
/* Make sure we have a buffer in case we need to resize the tables. */
if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
/* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
error_report("Warning: ACPI tables are larger than 64k.");
error_report("Warning: migration may not work.");
error_report("Warning: please remove CPUs, NUMA nodes, "
"memory slots or PCI bridges.");
}
acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
}
acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
| false | qemu | 5fe79386ba3cdc86fd808dde301bfc5bb7e9bded | void acpi_build(AcpiBuildTables *tables)
{
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
GArray *table_offsets;
unsigned facs, dsdt, rsdt, fadt;
AcpiCpuInfo cpu;
AcpiPmInfo pm;
AcpiMiscInfo misc;
AcpiMcfgInfo mcfg;
PcPciInfo pci;
uint8_t *u;
size_t aml_len = 0;
GArray *tables_blob = tables->table_data;
AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
acpi_get_cpu_info(&cpu);
acpi_get_pm_info(&pm);
acpi_get_misc_info(&misc);
acpi_get_pci_info(&pci);
acpi_get_slic_oem(&slic_oem);
table_offsets = g_array_new(false, true ,
sizeof(uint32_t));
ACPI_BUILD_DPRINTF("init ACPI tables\n");
bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
64 ,
false );
facs = tables_blob->len;
build_facs(tables_blob, tables->linker);
dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci);
aml_len += tables_blob->len - dsdt;
fadt = tables_blob->len;
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
slic_oem.id, slic_oem.table_id);
aml_len += tables_blob->len - fadt;
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, &cpu);
if (misc.has_hpet) {
acpi_add_table(table_offsets, tables_blob);
build_hpet(tables_blob, tables->linker);
}
if (misc.tpm_version != TPM_VERSION_UNSPEC) {
acpi_add_table(table_offsets, tables_blob);
build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
if (misc.tpm_version == TPM_VERSION_2_0) {
acpi_add_table(table_offsets, tables_blob);
build_tpm2(tables_blob, tables->linker);
}
}
if (pcms->numa_nodes) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker);
}
if (acpi_get_mcfg(&mcfg)) {
acpi_add_table(table_offsets, tables_blob);
build_mcfg_q35(tables_blob, tables->linker, &mcfg);
}
if (acpi_has_iommu()) {
acpi_add_table(table_offsets, tables_blob);
build_dmar_q35(tables_blob, tables->linker);
}
if (acpi_has_nvdimm()) {
nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
}
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
unsigned len = acpi_table_len(u);
acpi_add_table(table_offsets, tables_blob);
g_array_append_vals(tables_blob, u, len);
}
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets,
slic_oem.id, slic_oem.table_id);
build_rsdp(tables->rsdp, tables->linker, rsdt);
if (pcmc->legacy_acpi_table_size) {
int legacy_aml_len =
pcmc->legacy_acpi_table_size +
ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
int legacy_table_size =
ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
ACPI_BUILD_ALIGN_SIZE);
if (tables_blob->len > legacy_table_size) {
error_report("Warning: migration may not work.");
}
g_array_set_size(tables_blob, legacy_table_size);
} else {
if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
error_report("Warning: ACPI tables are larger than 64k.");
error_report("Warning: migration may not work.");
error_report("Warning: please remove CPUs, NUMA nodes, "
"memory slots or PCI bridges.");
}
acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
}
acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
g_array_free(table_offsets, true);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(AcpiBuildTables *VAR_0)
{
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
GArray *table_offsets;
unsigned VAR_1, VAR_2, VAR_3, VAR_4;
AcpiCpuInfo cpu;
AcpiPmInfo pm;
AcpiMiscInfo misc;
AcpiMcfgInfo mcfg;
PcPciInfo pci;
uint8_t *u;
size_t aml_len = 0;
GArray *tables_blob = VAR_0->table_data;
AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
acpi_get_cpu_info(&cpu);
acpi_get_pm_info(&pm);
acpi_get_misc_info(&misc);
acpi_get_pci_info(&pci);
acpi_get_slic_oem(&slic_oem);
table_offsets = g_array_new(false, true ,
sizeof(uint32_t));
ACPI_BUILD_DPRINTF("init ACPI VAR_0\n");
bios_linker_loader_alloc(VAR_0->linker, ACPI_BUILD_TABLE_FILE,
64 ,
false );
VAR_1 = tables_blob->len;
build_facs(tables_blob, VAR_0->linker);
VAR_2 = tables_blob->len;
build_dsdt(tables_blob, VAR_0->linker, &cpu, &pm, &misc, &pci);
aml_len += tables_blob->len - VAR_2;
VAR_4 = tables_blob->len;
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, VAR_0->linker, &pm, VAR_1, VAR_2,
slic_oem.id, slic_oem.table_id);
aml_len += tables_blob->len - VAR_4;
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, VAR_0->linker, &cpu);
if (misc.has_hpet) {
acpi_add_table(table_offsets, tables_blob);
build_hpet(tables_blob, VAR_0->linker);
}
if (misc.tpm_version != TPM_VERSION_UNSPEC) {
acpi_add_table(table_offsets, tables_blob);
build_tpm_tcpa(tables_blob, VAR_0->linker, VAR_0->tcpalog);
if (misc.tpm_version == TPM_VERSION_2_0) {
acpi_add_table(table_offsets, tables_blob);
build_tpm2(tables_blob, VAR_0->linker);
}
}
if (pcms->numa_nodes) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, VAR_0->linker);
}
if (acpi_get_mcfg(&mcfg)) {
acpi_add_table(table_offsets, tables_blob);
build_mcfg_q35(tables_blob, VAR_0->linker, &mcfg);
}
if (acpi_has_iommu()) {
acpi_add_table(table_offsets, tables_blob);
build_dmar_q35(tables_blob, VAR_0->linker);
}
if (acpi_has_nvdimm()) {
nvdimm_build_acpi(table_offsets, tables_blob, VAR_0->linker);
}
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
unsigned len = acpi_table_len(u);
acpi_add_table(table_offsets, tables_blob);
g_array_append_vals(tables_blob, u, len);
}
VAR_3 = tables_blob->len;
build_rsdt(tables_blob, VAR_0->linker, table_offsets,
slic_oem.id, slic_oem.table_id);
build_rsdp(VAR_0->rsdp, VAR_0->linker, VAR_3);
if (pcmc->legacy_acpi_table_size) {
int VAR_5 =
pcmc->legacy_acpi_table_size +
ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
int VAR_6 =
ROUND_UP(tables_blob->len - aml_len + VAR_5,
ACPI_BUILD_ALIGN_SIZE);
if (tables_blob->len > VAR_6) {
error_report("Warning: migration may not work.");
}
g_array_set_size(tables_blob, VAR_6);
} else {
if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
error_report("Warning: ACPI VAR_0 are larger than 64k.");
error_report("Warning: migration may not work.");
error_report("Warning: please remove CPUs, NUMA nodes, "
"memory slots or PCI bridges.");
}
acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
}
acpi_align_size(VAR_0->linker, ACPI_BUILD_ALIGN_SIZE);
g_array_free(table_offsets, true);
}
| [
"void FUNC_0(AcpiBuildTables *VAR_0)\n{",
"PCMachineState *pcms = PC_MACHINE(qdev_get_machine());",
"PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);",
"GArray *table_offsets;",
"unsigned VAR_1, VAR_2, VAR_3, VAR_4;",
"AcpiCpuInfo cpu;",
"AcpiPmInfo pm;",
"AcpiMiscInfo misc;",
"AcpiMcfgInfo mcfg;",
"PcPciInfo pci;",
"uint8_t *u;",
"size_t aml_len = 0;",
"GArray *tables_blob = VAR_0->table_data;",
"AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };",
"acpi_get_cpu_info(&cpu);",
"acpi_get_pm_info(&pm);",
"acpi_get_misc_info(&misc);",
"acpi_get_pci_info(&pci);",
"acpi_get_slic_oem(&slic_oem);",
"table_offsets = g_array_new(false, true ,\nsizeof(uint32_t));",
"ACPI_BUILD_DPRINTF(\"init ACPI VAR_0\\n\");",
"bios_linker_loader_alloc(VAR_0->linker, ACPI_BUILD_TABLE_FILE,\n64 ,\nfalse );",
"VAR_1 = tables_blob->len;",
"build_facs(tables_blob, VAR_0->linker);",
"VAR_2 = tables_blob->len;",
"build_dsdt(tables_blob, VAR_0->linker, &cpu, &pm, &misc, &pci);",
"aml_len += tables_blob->len - VAR_2;",
"VAR_4 = tables_blob->len;",
"acpi_add_table(table_offsets, tables_blob);",
"build_fadt(tables_blob, VAR_0->linker, &pm, VAR_1, VAR_2,\nslic_oem.id, slic_oem.table_id);",
"aml_len += tables_blob->len - VAR_4;",
"acpi_add_table(table_offsets, tables_blob);",
"build_madt(tables_blob, VAR_0->linker, &cpu);",
"if (misc.has_hpet) {",
"acpi_add_table(table_offsets, tables_blob);",
"build_hpet(tables_blob, VAR_0->linker);",
"}",
"if (misc.tpm_version != TPM_VERSION_UNSPEC) {",
"acpi_add_table(table_offsets, tables_blob);",
"build_tpm_tcpa(tables_blob, VAR_0->linker, VAR_0->tcpalog);",
"if (misc.tpm_version == TPM_VERSION_2_0) {",
"acpi_add_table(table_offsets, tables_blob);",
"build_tpm2(tables_blob, VAR_0->linker);",
"}",
"}",
"if (pcms->numa_nodes) {",
"acpi_add_table(table_offsets, tables_blob);",
"build_srat(tables_blob, VAR_0->linker);",
"}",
"if (acpi_get_mcfg(&mcfg)) {",
"acpi_add_table(table_offsets, tables_blob);",
"build_mcfg_q35(tables_blob, VAR_0->linker, &mcfg);",
"}",
"if (acpi_has_iommu()) {",
"acpi_add_table(table_offsets, tables_blob);",
"build_dmar_q35(tables_blob, VAR_0->linker);",
"}",
"if (acpi_has_nvdimm()) {",
"nvdimm_build_acpi(table_offsets, tables_blob, VAR_0->linker);",
"}",
"for (u = acpi_table_first(); u; u = acpi_table_next(u)) {",
"unsigned len = acpi_table_len(u);",
"acpi_add_table(table_offsets, tables_blob);",
"g_array_append_vals(tables_blob, u, len);",
"}",
"VAR_3 = tables_blob->len;",
"build_rsdt(tables_blob, VAR_0->linker, table_offsets,\nslic_oem.id, slic_oem.table_id);",
"build_rsdp(VAR_0->rsdp, VAR_0->linker, VAR_3);",
"if (pcmc->legacy_acpi_table_size) {",
"int VAR_5 =\npcmc->legacy_acpi_table_size +\nACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;",
"int VAR_6 =\nROUND_UP(tables_blob->len - aml_len + VAR_5,\nACPI_BUILD_ALIGN_SIZE);",
"if (tables_blob->len > VAR_6) {",
"error_report(\"Warning: migration may not work.\");",
"}",
"g_array_set_size(tables_blob, VAR_6);",
"} else {",
"if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {",
"error_report(\"Warning: ACPI VAR_0 are larger than 64k.\");",
"error_report(\"Warning: migration may not work.\");",
"error_report(\"Warning: please remove CPUs, NUMA nodes, \"\n\"memory slots or PCI bridges.\");",
"}",
"acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);",
"}",
"acpi_align_size(VAR_0->linker, ACPI_BUILD_ALIGN_SIZE);",
"g_array_free(table_offsets, true);",
"}"
]
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0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
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[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
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[
33
],
[
35
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[
37
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[
39
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[
41
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[
45,
47
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[
49
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[
53,
55,
57
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[
71
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[
73
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[
79
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[
81
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[
91
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[
97
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[
99
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[
101,
103
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[
105
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[
109
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[
111
],
[
115
],
[
117
],
[
119
],
[
121
],
[
123
],
[
125
],
[
127
],
[
131
],
[
133
],
[
135
],
[
137
],
[
139
],
[
141
],
[
143
],
[
145
],
[
147
],
[
149
],
[
151
],
[
153
],
[
155
],
[
157
],
[
159
],
[
161
],
[
163
],
[
167
],
[
169
],
[
171
],
[
177
],
[
179
],
[
183
],
[
185
],
[
187
],
[
193
],
[
195,
197
],
[
203
],
[
241
],
[
249,
251,
253
],
[
255,
257,
259
],
[
261
],
[
265
],
[
267
],
[
269
],
[
271
],
[
275
],
[
279
],
[
281
],
[
283,
285
],
[
287
],
[
289
],
[
291
],
[
295
],
[
301
],
[
303
]
]
|
10,231 | static void qnull_destroy_obj(QObject *obj)
{
assert(0);
}
| false | qemu | 55e1819c509b3d9c10a54678b9c585bbda13889e | static void qnull_destroy_obj(QObject *obj)
{
assert(0);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(QObject *VAR_0)
{
assert(0);
}
| [
"static void FUNC_0(QObject *VAR_0)\n{",
"assert(0);",
"}"
]
| [
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
]
]
|
10,234 | void hmp_info_snapshots(Monitor *mon, const QDict *qdict)
{
BlockDriverState *bs, *bs1;
QEMUSnapshotInfo *sn_tab, *sn, s, *sn_info = &s;
int nb_sns, i, ret, available;
int total;
int *available_snapshots;
bs = find_vmstate_bs();
if (!bs) {
monitor_printf(mon, "No available block device supports snapshots\n");
return;
}
nb_sns = bdrv_snapshot_list(bs, &sn_tab);
if (nb_sns < 0) {
monitor_printf(mon, "bdrv_snapshot_list: error %d\n", nb_sns);
return;
}
if (nb_sns == 0) {
monitor_printf(mon, "There is no snapshot available.\n");
return;
}
available_snapshots = g_new0(int, nb_sns);
total = 0;
for (i = 0; i < nb_sns; i++) {
sn = &sn_tab[i];
available = 1;
bs1 = NULL;
while ((bs1 = bdrv_next(bs1))) {
if (bdrv_can_snapshot(bs1) && bs1 != bs) {
ret = bdrv_snapshot_find(bs1, sn_info, sn->id_str);
if (ret < 0) {
available = 0;
break;
}
}
}
if (available) {
available_snapshots[total] = i;
total++;
}
}
if (total > 0) {
bdrv_snapshot_dump((fprintf_function)monitor_printf, mon, NULL);
monitor_printf(mon, "\n");
for (i = 0; i < total; i++) {
sn = &sn_tab[available_snapshots[i]];
bdrv_snapshot_dump((fprintf_function)monitor_printf, mon, sn);
monitor_printf(mon, "\n");
}
} else {
monitor_printf(mon, "There is no suitable snapshot available\n");
}
g_free(sn_tab);
g_free(available_snapshots);
}
| false | qemu | 723ccda1a0eecece8e70dbcdd35a603f6c41a475 | void hmp_info_snapshots(Monitor *mon, const QDict *qdict)
{
BlockDriverState *bs, *bs1;
QEMUSnapshotInfo *sn_tab, *sn, s, *sn_info = &s;
int nb_sns, i, ret, available;
int total;
int *available_snapshots;
bs = find_vmstate_bs();
if (!bs) {
monitor_printf(mon, "No available block device supports snapshots\n");
return;
}
nb_sns = bdrv_snapshot_list(bs, &sn_tab);
if (nb_sns < 0) {
monitor_printf(mon, "bdrv_snapshot_list: error %d\n", nb_sns);
return;
}
if (nb_sns == 0) {
monitor_printf(mon, "There is no snapshot available.\n");
return;
}
available_snapshots = g_new0(int, nb_sns);
total = 0;
for (i = 0; i < nb_sns; i++) {
sn = &sn_tab[i];
available = 1;
bs1 = NULL;
while ((bs1 = bdrv_next(bs1))) {
if (bdrv_can_snapshot(bs1) && bs1 != bs) {
ret = bdrv_snapshot_find(bs1, sn_info, sn->id_str);
if (ret < 0) {
available = 0;
break;
}
}
}
if (available) {
available_snapshots[total] = i;
total++;
}
}
if (total > 0) {
bdrv_snapshot_dump((fprintf_function)monitor_printf, mon, NULL);
monitor_printf(mon, "\n");
for (i = 0; i < total; i++) {
sn = &sn_tab[available_snapshots[i]];
bdrv_snapshot_dump((fprintf_function)monitor_printf, mon, sn);
monitor_printf(mon, "\n");
}
} else {
monitor_printf(mon, "There is no suitable snapshot available\n");
}
g_free(sn_tab);
g_free(available_snapshots);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(Monitor *VAR_0, const QDict *VAR_1)
{
BlockDriverState *bs, *bs1;
QEMUSnapshotInfo *sn_tab, *sn, s, *sn_info = &s;
int VAR_2, VAR_3, VAR_4, VAR_5;
int VAR_6;
int *VAR_7;
bs = find_vmstate_bs();
if (!bs) {
monitor_printf(VAR_0, "No VAR_5 block device supports snapshots\n");
return;
}
VAR_2 = bdrv_snapshot_list(bs, &sn_tab);
if (VAR_2 < 0) {
monitor_printf(VAR_0, "bdrv_snapshot_list: error %d\n", VAR_2);
return;
}
if (VAR_2 == 0) {
monitor_printf(VAR_0, "There is no snapshot VAR_5.\n");
return;
}
VAR_7 = g_new0(int, VAR_2);
VAR_6 = 0;
for (VAR_3 = 0; VAR_3 < VAR_2; VAR_3++) {
sn = &sn_tab[VAR_3];
VAR_5 = 1;
bs1 = NULL;
while ((bs1 = bdrv_next(bs1))) {
if (bdrv_can_snapshot(bs1) && bs1 != bs) {
VAR_4 = bdrv_snapshot_find(bs1, sn_info, sn->id_str);
if (VAR_4 < 0) {
VAR_5 = 0;
break;
}
}
}
if (VAR_5) {
VAR_7[VAR_6] = VAR_3;
VAR_6++;
}
}
if (VAR_6 > 0) {
bdrv_snapshot_dump((fprintf_function)monitor_printf, VAR_0, NULL);
monitor_printf(VAR_0, "\n");
for (VAR_3 = 0; VAR_3 < VAR_6; VAR_3++) {
sn = &sn_tab[VAR_7[VAR_3]];
bdrv_snapshot_dump((fprintf_function)monitor_printf, VAR_0, sn);
monitor_printf(VAR_0, "\n");
}
} else {
monitor_printf(VAR_0, "There is no suitable snapshot VAR_5\n");
}
g_free(sn_tab);
g_free(VAR_7);
}
| [
"void FUNC_0(Monitor *VAR_0, const QDict *VAR_1)\n{",
"BlockDriverState *bs, *bs1;",
"QEMUSnapshotInfo *sn_tab, *sn, s, *sn_info = &s;",
"int VAR_2, VAR_3, VAR_4, VAR_5;",
"int VAR_6;",
"int *VAR_7;",
"bs = find_vmstate_bs();",
"if (!bs) {",
"monitor_printf(VAR_0, \"No VAR_5 block device supports snapshots\\n\");",
"return;",
"}",
"VAR_2 = bdrv_snapshot_list(bs, &sn_tab);",
"if (VAR_2 < 0) {",
"monitor_printf(VAR_0, \"bdrv_snapshot_list: error %d\\n\", VAR_2);",
"return;",
"}",
"if (VAR_2 == 0) {",
"monitor_printf(VAR_0, \"There is no snapshot VAR_5.\\n\");",
"return;",
"}",
"VAR_7 = g_new0(int, VAR_2);",
"VAR_6 = 0;",
"for (VAR_3 = 0; VAR_3 < VAR_2; VAR_3++) {",
"sn = &sn_tab[VAR_3];",
"VAR_5 = 1;",
"bs1 = NULL;",
"while ((bs1 = bdrv_next(bs1))) {",
"if (bdrv_can_snapshot(bs1) && bs1 != bs) {",
"VAR_4 = bdrv_snapshot_find(bs1, sn_info, sn->id_str);",
"if (VAR_4 < 0) {",
"VAR_5 = 0;",
"break;",
"}",
"}",
"}",
"if (VAR_5) {",
"VAR_7[VAR_6] = VAR_3;",
"VAR_6++;",
"}",
"}",
"if (VAR_6 > 0) {",
"bdrv_snapshot_dump((fprintf_function)monitor_printf, VAR_0, NULL);",
"monitor_printf(VAR_0, \"\\n\");",
"for (VAR_3 = 0; VAR_3 < VAR_6; VAR_3++) {",
"sn = &sn_tab[VAR_7[VAR_3]];",
"bdrv_snapshot_dump((fprintf_function)monitor_printf, VAR_0, sn);",
"monitor_printf(VAR_0, \"\\n\");",
"}",
"} else {",
"monitor_printf(VAR_0, \"There is no suitable snapshot VAR_5\\n\");",
"}",
"g_free(sn_tab);",
"g_free(VAR_7);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
0,
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0,
0,
0,
0,
0,
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0,
0,
0,
0,
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0,
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0,
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0,
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0,
0,
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0,
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0,
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0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
29
],
[
31
],
[
33
],
[
35
],
[
37
],
[
41
],
[
43
],
[
45
],
[
47
],
[
51
],
[
53
],
[
55
],
[
57
],
[
59
],
[
61
],
[
65
],
[
67
],
[
69
],
[
71
],
[
73
],
[
75
],
[
77
],
[
79
],
[
81
],
[
85
],
[
87
],
[
89
],
[
91
],
[
93
],
[
97
],
[
99
],
[
101
],
[
103
],
[
105
],
[
107
],
[
109
],
[
111
],
[
113
],
[
115
],
[
117
],
[
121
],
[
123
],
[
127
]
]
|
10,235 | static void set_fifodepth(MSSSpiState *s)
{
unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
if (size <= 8) {
s->fifo_depth = 32;
} else if (size <= 16) {
s->fifo_depth = 16;
} else if (size <= 32) {
s->fifo_depth = 8;
} else {
s->fifo_depth = 4;
}
}
| false | qemu | cda607d5e0178d0268066d94dd06b89614304a7d | static void set_fifodepth(MSSSpiState *s)
{
unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
if (size <= 8) {
s->fifo_depth = 32;
} else if (size <= 16) {
s->fifo_depth = 16;
} else if (size <= 32) {
s->fifo_depth = 8;
} else {
s->fifo_depth = 4;
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(MSSSpiState *VAR_0)
{
unsigned int VAR_1 = VAR_0->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
if (VAR_1 <= 8) {
VAR_0->fifo_depth = 32;
} else if (VAR_1 <= 16) {
VAR_0->fifo_depth = 16;
} else if (VAR_1 <= 32) {
VAR_0->fifo_depth = 8;
} else {
VAR_0->fifo_depth = 4;
}
}
| [
"static void FUNC_0(MSSSpiState *VAR_0)\n{",
"unsigned int VAR_1 = VAR_0->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;",
"if (VAR_1 <= 8) {",
"VAR_0->fifo_depth = 32;",
"} else if (VAR_1 <= 16) {",
"VAR_0->fifo_depth = 16;",
"} else if (VAR_1 <= 32) {",
"VAR_0->fifo_depth = 8;",
"} else {",
"VAR_0->fifo_depth = 4;",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
]
]
|
10,236 | void qdev_unplug(DeviceState *dev, Error **errp)
{
DeviceClass *dc = DEVICE_GET_CLASS(dev);
if (!dev->parent_bus->allow_hotplug) {
error_set(errp, QERR_BUS_NO_HOTPLUG, dev->parent_bus->name);
return;
}
assert(dc->unplug != NULL);
qdev_hot_removed = true;
if (dc->unplug(dev) < 0) {
error_set(errp, QERR_UNDEFINED_ERROR);
return;
}
}
| false | qemu | 120dc38f6113b676ecef0a2c9e42fc08cace5bdb | void qdev_unplug(DeviceState *dev, Error **errp)
{
DeviceClass *dc = DEVICE_GET_CLASS(dev);
if (!dev->parent_bus->allow_hotplug) {
error_set(errp, QERR_BUS_NO_HOTPLUG, dev->parent_bus->name);
return;
}
assert(dc->unplug != NULL);
qdev_hot_removed = true;
if (dc->unplug(dev) < 0) {
error_set(errp, QERR_UNDEFINED_ERROR);
return;
}
}
| {
"code": [],
"line_no": []
} | void FUNC_0(DeviceState *VAR_0, Error **VAR_1)
{
DeviceClass *dc = DEVICE_GET_CLASS(VAR_0);
if (!VAR_0->parent_bus->allow_hotplug) {
error_set(VAR_1, QERR_BUS_NO_HOTPLUG, VAR_0->parent_bus->name);
return;
}
assert(dc->unplug != NULL);
qdev_hot_removed = true;
if (dc->unplug(VAR_0) < 0) {
error_set(VAR_1, QERR_UNDEFINED_ERROR);
return;
}
}
| [
"void FUNC_0(DeviceState *VAR_0, Error **VAR_1)\n{",
"DeviceClass *dc = DEVICE_GET_CLASS(VAR_0);",
"if (!VAR_0->parent_bus->allow_hotplug) {",
"error_set(VAR_1, QERR_BUS_NO_HOTPLUG, VAR_0->parent_bus->name);",
"return;",
"}",
"assert(dc->unplug != NULL);",
"qdev_hot_removed = true;",
"if (dc->unplug(VAR_0) < 0) {",
"error_set(VAR_1, QERR_UNDEFINED_ERROR);",
"return;",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33
]
]
|
10,237 | int rom_add_file(const char *file, const char *fw_dir, const char *fw_file,
target_phys_addr_t addr)
{
Rom *rom;
int rc, fd = -1;
rom = qemu_mallocz(sizeof(*rom));
rom->name = qemu_strdup(file);
rom->path = qemu_find_file(QEMU_FILE_TYPE_BIOS, rom->name);
if (rom->path == NULL) {
rom->path = qemu_strdup(file);
}
fd = open(rom->path, O_RDONLY | O_BINARY);
if (fd == -1) {
fprintf(stderr, "Could not open option rom '%s': %s\n",
rom->path, strerror(errno));
goto err;
}
rom->fw_dir = fw_dir ? qemu_strdup(fw_dir) : NULL;
rom->fw_file = fw_file ? qemu_strdup(fw_file) : NULL;
rom->addr = addr;
rom->romsize = lseek(fd, 0, SEEK_END);
rom->data = qemu_mallocz(rom->romsize);
lseek(fd, 0, SEEK_SET);
rc = read(fd, rom->data, rom->romsize);
if (rc != rom->romsize) {
fprintf(stderr, "rom: file %-20s: read error: rc=%d (expected %zd)\n",
rom->name, rc, rom->romsize);
goto err;
}
close(fd);
rom_insert(rom);
return 0;
err:
if (fd != -1)
close(fd);
qemu_free(rom->data);
qemu_free(rom->path);
qemu_free(rom->name);
qemu_free(rom);
return -1;
}
| false | qemu | bdb5ee3064d5ae786b0bcb6cf6ff4e3554a72990 | int rom_add_file(const char *file, const char *fw_dir, const char *fw_file,
target_phys_addr_t addr)
{
Rom *rom;
int rc, fd = -1;
rom = qemu_mallocz(sizeof(*rom));
rom->name = qemu_strdup(file);
rom->path = qemu_find_file(QEMU_FILE_TYPE_BIOS, rom->name);
if (rom->path == NULL) {
rom->path = qemu_strdup(file);
}
fd = open(rom->path, O_RDONLY | O_BINARY);
if (fd == -1) {
fprintf(stderr, "Could not open option rom '%s': %s\n",
rom->path, strerror(errno));
goto err;
}
rom->fw_dir = fw_dir ? qemu_strdup(fw_dir) : NULL;
rom->fw_file = fw_file ? qemu_strdup(fw_file) : NULL;
rom->addr = addr;
rom->romsize = lseek(fd, 0, SEEK_END);
rom->data = qemu_mallocz(rom->romsize);
lseek(fd, 0, SEEK_SET);
rc = read(fd, rom->data, rom->romsize);
if (rc != rom->romsize) {
fprintf(stderr, "rom: file %-20s: read error: rc=%d (expected %zd)\n",
rom->name, rc, rom->romsize);
goto err;
}
close(fd);
rom_insert(rom);
return 0;
err:
if (fd != -1)
close(fd);
qemu_free(rom->data);
qemu_free(rom->path);
qemu_free(rom->name);
qemu_free(rom);
return -1;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(const char *VAR_0, const char *VAR_1, const char *VAR_2,
target_phys_addr_t VAR_3)
{
Rom *rom;
int VAR_4, VAR_5 = -1;
rom = qemu_mallocz(sizeof(*rom));
rom->name = qemu_strdup(VAR_0);
rom->path = qemu_find_file(QEMU_FILE_TYPE_BIOS, rom->name);
if (rom->path == NULL) {
rom->path = qemu_strdup(VAR_0);
}
VAR_5 = open(rom->path, O_RDONLY | O_BINARY);
if (VAR_5 == -1) {
fprintf(stderr, "Could not open option rom '%s': %s\n",
rom->path, strerror(errno));
goto err;
}
rom->VAR_1 = VAR_1 ? qemu_strdup(VAR_1) : NULL;
rom->VAR_2 = VAR_2 ? qemu_strdup(VAR_2) : NULL;
rom->VAR_3 = VAR_3;
rom->romsize = lseek(VAR_5, 0, SEEK_END);
rom->data = qemu_mallocz(rom->romsize);
lseek(VAR_5, 0, SEEK_SET);
VAR_4 = read(VAR_5, rom->data, rom->romsize);
if (VAR_4 != rom->romsize) {
fprintf(stderr, "rom: VAR_0 %-20s: read error: VAR_4=%d (expected %zd)\n",
rom->name, VAR_4, rom->romsize);
goto err;
}
close(VAR_5);
rom_insert(rom);
return 0;
err:
if (VAR_5 != -1)
close(VAR_5);
qemu_free(rom->data);
qemu_free(rom->path);
qemu_free(rom->name);
qemu_free(rom);
return -1;
}
| [
"int FUNC_0(const char *VAR_0, const char *VAR_1, const char *VAR_2,\ntarget_phys_addr_t VAR_3)\n{",
"Rom *rom;",
"int VAR_4, VAR_5 = -1;",
"rom = qemu_mallocz(sizeof(*rom));",
"rom->name = qemu_strdup(VAR_0);",
"rom->path = qemu_find_file(QEMU_FILE_TYPE_BIOS, rom->name);",
"if (rom->path == NULL) {",
"rom->path = qemu_strdup(VAR_0);",
"}",
"VAR_5 = open(rom->path, O_RDONLY | O_BINARY);",
"if (VAR_5 == -1) {",
"fprintf(stderr, \"Could not open option rom '%s': %s\\n\",\nrom->path, strerror(errno));",
"goto err;",
"}",
"rom->VAR_1 = VAR_1 ? qemu_strdup(VAR_1) : NULL;",
"rom->VAR_2 = VAR_2 ? qemu_strdup(VAR_2) : NULL;",
"rom->VAR_3 = VAR_3;",
"rom->romsize = lseek(VAR_5, 0, SEEK_END);",
"rom->data = qemu_mallocz(rom->romsize);",
"lseek(VAR_5, 0, SEEK_SET);",
"VAR_4 = read(VAR_5, rom->data, rom->romsize);",
"if (VAR_4 != rom->romsize) {",
"fprintf(stderr, \"rom: VAR_0 %-20s: read error: VAR_4=%d (expected %zd)\\n\",\nrom->name, VAR_4, rom->romsize);",
"goto err;",
"}",
"close(VAR_5);",
"rom_insert(rom);",
"return 0;",
"err:\nif (VAR_5 != -1)\nclose(VAR_5);",
"qemu_free(rom->data);",
"qemu_free(rom->path);",
"qemu_free(rom->name);",
"qemu_free(rom);",
"return -1;",
"}"
]
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0,
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[
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[
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[
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[
15
],
[
17
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[
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21
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41
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[
43
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45
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[
47
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49
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[
61
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[
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65
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67
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77
],
[
79
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[
81
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[
83
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85
],
[
87
],
[
89
]
]
|
10,238 | static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEState *ide_if = opaque;
IDEState *s;
int unit, n;
int lba48 = 0;
#ifdef DEBUG_IDE
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
#endif
addr &= 7;
/* ignore writes to command block while busy with previous command */
if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))
return;
switch(addr) {
case 0:
break;
case 1:
ide_clear_hob(ide_if);
/* NOTE: data is written to the two drives */
ide_if[0].hob_feature = ide_if[0].feature;
ide_if[1].hob_feature = ide_if[1].feature;
ide_if[0].feature = val;
ide_if[1].feature = val;
break;
case 2:
ide_clear_hob(ide_if);
ide_if[0].hob_nsector = ide_if[0].nsector;
ide_if[1].hob_nsector = ide_if[1].nsector;
ide_if[0].nsector = val;
ide_if[1].nsector = val;
break;
case 3:
ide_clear_hob(ide_if);
ide_if[0].hob_sector = ide_if[0].sector;
ide_if[1].hob_sector = ide_if[1].sector;
ide_if[0].sector = val;
ide_if[1].sector = val;
break;
case 4:
ide_clear_hob(ide_if);
ide_if[0].hob_lcyl = ide_if[0].lcyl;
ide_if[1].hob_lcyl = ide_if[1].lcyl;
ide_if[0].lcyl = val;
ide_if[1].lcyl = val;
break;
case 5:
ide_clear_hob(ide_if);
ide_if[0].hob_hcyl = ide_if[0].hcyl;
ide_if[1].hob_hcyl = ide_if[1].hcyl;
ide_if[0].hcyl = val;
ide_if[1].hcyl = val;
break;
case 6:
/* FIXME: HOB readback uses bit 7 */
ide_if[0].select = (val & ~0x10) | 0xa0;
ide_if[1].select = (val | 0x10) | 0xa0;
/* select drive */
unit = (val >> 4) & 1;
s = ide_if + unit;
ide_if->cur_drive = s;
break;
default:
case 7:
/* command */
#if defined(DEBUG_IDE)
printf("ide: CMD=%02x\n", val);
#endif
s = ide_if->cur_drive;
/* ignore commands to non existant slave */
if (s != ide_if && !s->bs)
break;
/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
break;
switch(val) {
case WIN_IDENTIFY:
if (s->bs && !s->is_cdrom) {
if (!s->is_cf)
ide_identify(s);
else
ide_cfata_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
if (s->is_cdrom) {
ide_set_signature(s);
}
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_SPECIFY:
case WIN_RECAL:
s->error = 0;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_SETMULT:
if (s->is_cf && s->nsector == 0) {
/* Disable Read and Write Multiple */
s->mult_sectors = 0;
s->status = READY_STAT | SEEK_STAT;
} else if ((s->nsector & 0xff) != 0 &&
((s->nsector & 0xff) > MAX_MULT_SECTORS ||
(s->nsector & (s->nsector - 1)) != 0)) {
ide_abort_command(s);
} else {
s->mult_sectors = s->nsector & 0xff;
s->status = READY_STAT | SEEK_STAT;
}
ide_set_irq(s);
break;
case WIN_VERIFY_EXT:
lba48 = 1;
case WIN_VERIFY:
case WIN_VERIFY_ONCE:
/* do sector number check ? */
ide_cmd_lba48_transform(s, lba48);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_READ_EXT:
lba48 = 1;
case WIN_READ:
case WIN_READ_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->req_nb_sectors = 1;
ide_sector_read(s);
break;
case WIN_WRITE_EXT:
lba48 = 1;
case WIN_WRITE:
case WIN_WRITE_ONCE:
case CFA_WRITE_SECT_WO_ERASE:
case WIN_WRITE_VERIFY:
ide_cmd_lba48_transform(s, lba48);
s->error = 0;
s->status = SEEK_STAT | READY_STAT;
s->req_nb_sectors = 1;
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
s->media_changed = 1;
break;
case WIN_MULTREAD_EXT:
lba48 = 1;
case WIN_MULTREAD:
if (!s->mult_sectors)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->req_nb_sectors = s->mult_sectors;
ide_sector_read(s);
break;
case WIN_MULTWRITE_EXT:
lba48 = 1;
case WIN_MULTWRITE:
case CFA_WRITE_MULTI_WO_ERASE:
if (!s->mult_sectors)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->error = 0;
s->status = SEEK_STAT | READY_STAT;
s->req_nb_sectors = s->mult_sectors;
n = s->nsector;
if (n > s->req_nb_sectors)
n = s->req_nb_sectors;
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
s->media_changed = 1;
break;
case WIN_READDMA_EXT:
lba48 = 1;
case WIN_READDMA:
case WIN_READDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
ide_sector_read_dma(s);
break;
case WIN_WRITEDMA_EXT:
lba48 = 1;
case WIN_WRITEDMA:
case WIN_WRITEDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
ide_sector_write_dma(s);
s->media_changed = 1;
break;
case WIN_READ_NATIVE_MAX_EXT:
lba48 = 1;
case WIN_READ_NATIVE_MAX:
ide_cmd_lba48_transform(s, lba48);
ide_set_sector(s, s->nb_sectors - 1);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_CHECKPOWERMODE1:
case WIN_CHECKPOWERMODE2:
s->nsector = 0xff; /* device active or idle */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_SETFEATURES:
if (!s->bs)
goto abort_cmd;
/* XXX: valid for CDROM ? */
switch(s->feature) {
case 0xcc: /* reverting to power-on defaults enable */
case 0x66: /* reverting to power-on defaults disable */
case 0x02: /* write cache enable */
case 0x82: /* write cache disable */
case 0xaa: /* read look-ahead enable */
case 0x55: /* read look-ahead disable */
case 0x05: /* set advanced power management mode */
case 0x85: /* disable advanced power management mode */
case 0x69: /* NOP */
case 0x67: /* NOP */
case 0x96: /* NOP */
case 0x9a: /* NOP */
case 0x42: /* enable Automatic Acoustic Mode */
case 0xc2: /* disable Automatic Acoustic Mode */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case 0x03: { /* set transfer mode */
uint8_t val = s->nsector & 0x07;
switch (s->nsector >> 3) {
case 0x00: /* pio default */
case 0x01: /* pio mode */
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f);
break;
case 0x02: /* sigle word dma mode*/
put_le16(s->identify_data + 62,0x07 | (1 << (val + 8)));
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f);
break;
case 0x04: /* mdma mode */
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07 | (1 << (val + 8)));
put_le16(s->identify_data + 88,0x3f);
break;
case 0x08: /* udma mode */
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f | (1 << (val + 8)));
break;
default:
goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
}
default:
goto abort_cmd;
}
break;
case WIN_FLUSH_CACHE:
case WIN_FLUSH_CACHE_EXT:
if (s->bs)
bdrv_flush(s->bs);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_STANDBY:
case WIN_STANDBY2:
case WIN_STANDBYNOW1:
case WIN_STANDBYNOW2:
case WIN_IDLEIMMEDIATE:
case CFA_IDLEIMMEDIATE:
case WIN_SETIDLE1:
case WIN_SETIDLE2:
case WIN_SLEEPNOW1:
case WIN_SLEEPNOW2:
s->status = READY_STAT;
ide_set_irq(s);
break;
/* ATAPI commands */
case WIN_PIDENTIFY:
if (s->is_cdrom) {
ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_DIAGNOSE:
ide_set_signature(s);
s->status = READY_STAT | SEEK_STAT;
s->error = 0x01;
ide_set_irq(s);
break;
case WIN_SRST:
if (!s->is_cdrom)
goto abort_cmd;
ide_set_signature(s);
s->status = 0x00; /* NOTE: READY is _not_ set */
s->error = 0x01;
break;
case WIN_PACKETCMD:
if (!s->is_cdrom)
goto abort_cmd;
/* overlapping commands not supported */
if (s->feature & 0x02)
goto abort_cmd;
s->status = READY_STAT | SEEK_STAT;
s->atapi_dma = s->feature & 1;
s->nsector = 1;
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
ide_atapi_cmd);
break;
/* CF-ATA commands */
case CFA_REQ_EXT_ERROR_CODE:
if (!s->is_cf)
goto abort_cmd;
s->error = 0x09; /* miscellaneous error */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case CFA_ERASE_SECTORS:
case CFA_WEAR_LEVEL:
if (!s->is_cf)
goto abort_cmd;
if (val == CFA_WEAR_LEVEL)
s->nsector = 0;
if (val == CFA_ERASE_SECTORS)
s->media_changed = 1;
s->error = 0x00;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case CFA_TRANSLATE_SECTOR:
if (!s->is_cf)
goto abort_cmd;
s->error = 0x00;
s->status = READY_STAT | SEEK_STAT;
memset(s->io_buffer, 0, 0x200);
s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
s->io_buffer[0x02] = s->select; /* Head */
s->io_buffer[0x03] = s->sector; /* Sector */
s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
s->io_buffer[0x13] = 0x00; /* Erase flag */
s->io_buffer[0x18] = 0x00; /* Hot count */
s->io_buffer[0x19] = 0x00; /* Hot count */
s->io_buffer[0x1a] = 0x01; /* Hot count */
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s);
break;
case CFA_ACCESS_METADATA_STORAGE:
if (!s->is_cf)
goto abort_cmd;
switch (s->feature) {
case 0x02: /* Inquiry Metadata Storage */
ide_cfata_metadata_inquiry(s);
break;
case 0x03: /* Read Metadata Storage */
ide_cfata_metadata_read(s);
break;
case 0x04: /* Write Metadata Storage */
ide_cfata_metadata_write(s);
break;
default:
goto abort_cmd;
}
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
s->status = 0x00; /* NOTE: READY is _not_ set */
ide_set_irq(s);
break;
case IBM_SENSE_CONDITION:
if (!s->is_cf)
goto abort_cmd;
switch (s->feature) {
case 0x01: /* sense temperature in device */
s->nsector = 0x50; /* +20 C */
break;
default:
goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
default:
abort_cmd:
ide_abort_command(s);
ide_set_irq(s);
break;
}
}
}
| false | qemu | 33256a25b3b31915b9038eefe7923c68bb034118 | static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEState *ide_if = opaque;
IDEState *s;
int unit, n;
int lba48 = 0;
#ifdef DEBUG_IDE
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
#endif
addr &= 7;
if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))
return;
switch(addr) {
case 0:
break;
case 1:
ide_clear_hob(ide_if);
ide_if[0].hob_feature = ide_if[0].feature;
ide_if[1].hob_feature = ide_if[1].feature;
ide_if[0].feature = val;
ide_if[1].feature = val;
break;
case 2:
ide_clear_hob(ide_if);
ide_if[0].hob_nsector = ide_if[0].nsector;
ide_if[1].hob_nsector = ide_if[1].nsector;
ide_if[0].nsector = val;
ide_if[1].nsector = val;
break;
case 3:
ide_clear_hob(ide_if);
ide_if[0].hob_sector = ide_if[0].sector;
ide_if[1].hob_sector = ide_if[1].sector;
ide_if[0].sector = val;
ide_if[1].sector = val;
break;
case 4:
ide_clear_hob(ide_if);
ide_if[0].hob_lcyl = ide_if[0].lcyl;
ide_if[1].hob_lcyl = ide_if[1].lcyl;
ide_if[0].lcyl = val;
ide_if[1].lcyl = val;
break;
case 5:
ide_clear_hob(ide_if);
ide_if[0].hob_hcyl = ide_if[0].hcyl;
ide_if[1].hob_hcyl = ide_if[1].hcyl;
ide_if[0].hcyl = val;
ide_if[1].hcyl = val;
break;
case 6:
ide_if[0].select = (val & ~0x10) | 0xa0;
ide_if[1].select = (val | 0x10) | 0xa0;
unit = (val >> 4) & 1;
s = ide_if + unit;
ide_if->cur_drive = s;
break;
default:
case 7:
#if defined(DEBUG_IDE)
printf("ide: CMD=%02x\n", val);
#endif
s = ide_if->cur_drive;
if (s != ide_if && !s->bs)
break;
if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
break;
switch(val) {
case WIN_IDENTIFY:
if (s->bs && !s->is_cdrom) {
if (!s->is_cf)
ide_identify(s);
else
ide_cfata_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
if (s->is_cdrom) {
ide_set_signature(s);
}
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_SPECIFY:
case WIN_RECAL:
s->error = 0;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_SETMULT:
if (s->is_cf && s->nsector == 0) {
s->mult_sectors = 0;
s->status = READY_STAT | SEEK_STAT;
} else if ((s->nsector & 0xff) != 0 &&
((s->nsector & 0xff) > MAX_MULT_SECTORS ||
(s->nsector & (s->nsector - 1)) != 0)) {
ide_abort_command(s);
} else {
s->mult_sectors = s->nsector & 0xff;
s->status = READY_STAT | SEEK_STAT;
}
ide_set_irq(s);
break;
case WIN_VERIFY_EXT:
lba48 = 1;
case WIN_VERIFY:
case WIN_VERIFY_ONCE:
ide_cmd_lba48_transform(s, lba48);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_READ_EXT:
lba48 = 1;
case WIN_READ:
case WIN_READ_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->req_nb_sectors = 1;
ide_sector_read(s);
break;
case WIN_WRITE_EXT:
lba48 = 1;
case WIN_WRITE:
case WIN_WRITE_ONCE:
case CFA_WRITE_SECT_WO_ERASE:
case WIN_WRITE_VERIFY:
ide_cmd_lba48_transform(s, lba48);
s->error = 0;
s->status = SEEK_STAT | READY_STAT;
s->req_nb_sectors = 1;
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
s->media_changed = 1;
break;
case WIN_MULTREAD_EXT:
lba48 = 1;
case WIN_MULTREAD:
if (!s->mult_sectors)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->req_nb_sectors = s->mult_sectors;
ide_sector_read(s);
break;
case WIN_MULTWRITE_EXT:
lba48 = 1;
case WIN_MULTWRITE:
case CFA_WRITE_MULTI_WO_ERASE:
if (!s->mult_sectors)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->error = 0;
s->status = SEEK_STAT | READY_STAT;
s->req_nb_sectors = s->mult_sectors;
n = s->nsector;
if (n > s->req_nb_sectors)
n = s->req_nb_sectors;
ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
s->media_changed = 1;
break;
case WIN_READDMA_EXT:
lba48 = 1;
case WIN_READDMA:
case WIN_READDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
ide_sector_read_dma(s);
break;
case WIN_WRITEDMA_EXT:
lba48 = 1;
case WIN_WRITEDMA:
case WIN_WRITEDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
ide_sector_write_dma(s);
s->media_changed = 1;
break;
case WIN_READ_NATIVE_MAX_EXT:
lba48 = 1;
case WIN_READ_NATIVE_MAX:
ide_cmd_lba48_transform(s, lba48);
ide_set_sector(s, s->nb_sectors - 1);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_CHECKPOWERMODE1:
case WIN_CHECKPOWERMODE2:
s->nsector = 0xff;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_SETFEATURES:
if (!s->bs)
goto abort_cmd;
switch(s->feature) {
case 0xcc:
case 0x66:
case 0x02:
case 0x82:
case 0xaa:
case 0x55:
case 0x05:
case 0x85:
case 0x69:
case 0x67:
case 0x96:
case 0x9a:
case 0x42:
case 0xc2:
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case 0x03: {
uint8_t val = s->nsector & 0x07;
switch (s->nsector >> 3) {
case 0x00:
case 0x01:
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f);
break;
case 0x02:
put_le16(s->identify_data + 62,0x07 | (1 << (val + 8)));
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f);
break;
case 0x04:
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07 | (1 << (val + 8)));
put_le16(s->identify_data + 88,0x3f);
break;
case 0x08:
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f | (1 << (val + 8)));
break;
default:
goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
}
default:
goto abort_cmd;
}
break;
case WIN_FLUSH_CACHE:
case WIN_FLUSH_CACHE_EXT:
if (s->bs)
bdrv_flush(s->bs);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_STANDBY:
case WIN_STANDBY2:
case WIN_STANDBYNOW1:
case WIN_STANDBYNOW2:
case WIN_IDLEIMMEDIATE:
case CFA_IDLEIMMEDIATE:
case WIN_SETIDLE1:
case WIN_SETIDLE2:
case WIN_SLEEPNOW1:
case WIN_SLEEPNOW2:
s->status = READY_STAT;
ide_set_irq(s);
break;
case WIN_PIDENTIFY:
if (s->is_cdrom) {
ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_DIAGNOSE:
ide_set_signature(s);
s->status = READY_STAT | SEEK_STAT;
s->error = 0x01;
ide_set_irq(s);
break;
case WIN_SRST:
if (!s->is_cdrom)
goto abort_cmd;
ide_set_signature(s);
s->status = 0x00;
s->error = 0x01;
break;
case WIN_PACKETCMD:
if (!s->is_cdrom)
goto abort_cmd;
if (s->feature & 0x02)
goto abort_cmd;
s->status = READY_STAT | SEEK_STAT;
s->atapi_dma = s->feature & 1;
s->nsector = 1;
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
ide_atapi_cmd);
break;
case CFA_REQ_EXT_ERROR_CODE:
if (!s->is_cf)
goto abort_cmd;
s->error = 0x09;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case CFA_ERASE_SECTORS:
case CFA_WEAR_LEVEL:
if (!s->is_cf)
goto abort_cmd;
if (val == CFA_WEAR_LEVEL)
s->nsector = 0;
if (val == CFA_ERASE_SECTORS)
s->media_changed = 1;
s->error = 0x00;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case CFA_TRANSLATE_SECTOR:
if (!s->is_cf)
goto abort_cmd;
s->error = 0x00;
s->status = READY_STAT | SEEK_STAT;
memset(s->io_buffer, 0, 0x200);
s->io_buffer[0x00] = s->hcyl;
s->io_buffer[0x01] = s->lcyl;
s->io_buffer[0x02] = s->select;
s->io_buffer[0x03] = s->sector;
s->io_buffer[0x04] = ide_get_sector(s) >> 16;
s->io_buffer[0x05] = ide_get_sector(s) >> 8;
s->io_buffer[0x06] = ide_get_sector(s) >> 0;
s->io_buffer[0x13] = 0x00;
s->io_buffer[0x18] = 0x00;
s->io_buffer[0x19] = 0x00;
s->io_buffer[0x1a] = 0x01;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s);
break;
case CFA_ACCESS_METADATA_STORAGE:
if (!s->is_cf)
goto abort_cmd;
switch (s->feature) {
case 0x02:
ide_cfata_metadata_inquiry(s);
break;
case 0x03:
ide_cfata_metadata_read(s);
break;
case 0x04:
ide_cfata_metadata_write(s);
break;
default:
goto abort_cmd;
}
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
s->status = 0x00;
ide_set_irq(s);
break;
case IBM_SENSE_CONDITION:
if (!s->is_cf)
goto abort_cmd;
switch (s->feature) {
case 0x01:
s->nsector = 0x50;
break;
default:
goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
default:
abort_cmd:
ide_abort_command(s);
ide_set_irq(s);
break;
}
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void *VAR_0, uint32_t VAR_1, uint32_t VAR_2)
{
IDEState *ide_if = VAR_0;
IDEState *s;
int VAR_3, VAR_4;
int VAR_5 = 0;
#ifdef DEBUG_IDE
printf("IDE: write VAR_1=0x%x VAR_2=0x%02x\VAR_4", VAR_1, VAR_2);
#endif
VAR_1 &= 7;
if (VAR_1 != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))
return;
switch(VAR_1) {
case 0:
break;
case 1:
ide_clear_hob(ide_if);
ide_if[0].hob_feature = ide_if[0].feature;
ide_if[1].hob_feature = ide_if[1].feature;
ide_if[0].feature = VAR_2;
ide_if[1].feature = VAR_2;
break;
case 2:
ide_clear_hob(ide_if);
ide_if[0].hob_nsector = ide_if[0].nsector;
ide_if[1].hob_nsector = ide_if[1].nsector;
ide_if[0].nsector = VAR_2;
ide_if[1].nsector = VAR_2;
break;
case 3:
ide_clear_hob(ide_if);
ide_if[0].hob_sector = ide_if[0].sector;
ide_if[1].hob_sector = ide_if[1].sector;
ide_if[0].sector = VAR_2;
ide_if[1].sector = VAR_2;
break;
case 4:
ide_clear_hob(ide_if);
ide_if[0].hob_lcyl = ide_if[0].lcyl;
ide_if[1].hob_lcyl = ide_if[1].lcyl;
ide_if[0].lcyl = VAR_2;
ide_if[1].lcyl = VAR_2;
break;
case 5:
ide_clear_hob(ide_if);
ide_if[0].hob_hcyl = ide_if[0].hcyl;
ide_if[1].hob_hcyl = ide_if[1].hcyl;
ide_if[0].hcyl = VAR_2;
ide_if[1].hcyl = VAR_2;
break;
case 6:
ide_if[0].select = (VAR_2 & ~0x10) | 0xa0;
ide_if[1].select = (VAR_2 | 0x10) | 0xa0;
VAR_3 = (VAR_2 >> 4) & 1;
s = ide_if + VAR_3;
ide_if->cur_drive = s;
break;
default:
case 7:
#if defined(DEBUG_IDE)
printf("ide: CMD=%02x\VAR_4", VAR_2);
#endif
s = ide_if->cur_drive;
if (s != ide_if && !s->bs)
break;
if ((s->status & (BUSY_STAT|DRQ_STAT)) && VAR_2 != WIN_DEVICE_RESET)
break;
switch(VAR_2) {
case WIN_IDENTIFY:
if (s->bs && !s->is_cdrom) {
if (!s->is_cf)
ide_identify(s);
else
ide_cfata_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
if (s->is_cdrom) {
ide_set_signature(s);
}
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_SPECIFY:
case WIN_RECAL:
s->error = 0;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_SETMULT:
if (s->is_cf && s->nsector == 0) {
s->mult_sectors = 0;
s->status = READY_STAT | SEEK_STAT;
} else if ((s->nsector & 0xff) != 0 &&
((s->nsector & 0xff) > MAX_MULT_SECTORS ||
(s->nsector & (s->nsector - 1)) != 0)) {
ide_abort_command(s);
} else {
s->mult_sectors = s->nsector & 0xff;
s->status = READY_STAT | SEEK_STAT;
}
ide_set_irq(s);
break;
case WIN_VERIFY_EXT:
VAR_5 = 1;
case WIN_VERIFY:
case WIN_VERIFY_ONCE:
ide_cmd_lba48_transform(s, VAR_5);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_READ_EXT:
VAR_5 = 1;
case WIN_READ:
case WIN_READ_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, VAR_5);
s->req_nb_sectors = 1;
ide_sector_read(s);
break;
case WIN_WRITE_EXT:
VAR_5 = 1;
case WIN_WRITE:
case WIN_WRITE_ONCE:
case CFA_WRITE_SECT_WO_ERASE:
case WIN_WRITE_VERIFY:
ide_cmd_lba48_transform(s, VAR_5);
s->error = 0;
s->status = SEEK_STAT | READY_STAT;
s->req_nb_sectors = 1;
ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
s->media_changed = 1;
break;
case WIN_MULTREAD_EXT:
VAR_5 = 1;
case WIN_MULTREAD:
if (!s->mult_sectors)
goto abort_cmd;
ide_cmd_lba48_transform(s, VAR_5);
s->req_nb_sectors = s->mult_sectors;
ide_sector_read(s);
break;
case WIN_MULTWRITE_EXT:
VAR_5 = 1;
case WIN_MULTWRITE:
case CFA_WRITE_MULTI_WO_ERASE:
if (!s->mult_sectors)
goto abort_cmd;
ide_cmd_lba48_transform(s, VAR_5);
s->error = 0;
s->status = SEEK_STAT | READY_STAT;
s->req_nb_sectors = s->mult_sectors;
VAR_4 = s->nsector;
if (VAR_4 > s->req_nb_sectors)
VAR_4 = s->req_nb_sectors;
ide_transfer_start(s, s->io_buffer, 512 * VAR_4, ide_sector_write);
s->media_changed = 1;
break;
case WIN_READDMA_EXT:
VAR_5 = 1;
case WIN_READDMA:
case WIN_READDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, VAR_5);
ide_sector_read_dma(s);
break;
case WIN_WRITEDMA_EXT:
VAR_5 = 1;
case WIN_WRITEDMA:
case WIN_WRITEDMA_ONCE:
if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, VAR_5);
ide_sector_write_dma(s);
s->media_changed = 1;
break;
case WIN_READ_NATIVE_MAX_EXT:
VAR_5 = 1;
case WIN_READ_NATIVE_MAX:
ide_cmd_lba48_transform(s, VAR_5);
ide_set_sector(s, s->nb_sectors - 1);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_CHECKPOWERMODE1:
case WIN_CHECKPOWERMODE2:
s->nsector = 0xff;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_SETFEATURES:
if (!s->bs)
goto abort_cmd;
switch(s->feature) {
case 0xcc:
case 0x66:
case 0x02:
case 0x82:
case 0xaa:
case 0x55:
case 0x05:
case 0x85:
case 0x69:
case 0x67:
case 0x96:
case 0x9a:
case 0x42:
case 0xc2:
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case 0x03: {
uint8_t VAR_2 = s->nsector & 0x07;
switch (s->nsector >> 3) {
case 0x00:
case 0x01:
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f);
break;
case 0x02:
put_le16(s->identify_data + 62,0x07 | (1 << (VAR_2 + 8)));
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f);
break;
case 0x04:
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07 | (1 << (VAR_2 + 8)));
put_le16(s->identify_data + 88,0x3f);
break;
case 0x08:
put_le16(s->identify_data + 62,0x07);
put_le16(s->identify_data + 63,0x07);
put_le16(s->identify_data + 88,0x3f | (1 << (VAR_2 + 8)));
break;
default:
goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
}
default:
goto abort_cmd;
}
break;
case WIN_FLUSH_CACHE:
case WIN_FLUSH_CACHE_EXT:
if (s->bs)
bdrv_flush(s->bs);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case WIN_STANDBY:
case WIN_STANDBY2:
case WIN_STANDBYNOW1:
case WIN_STANDBYNOW2:
case WIN_IDLEIMMEDIATE:
case CFA_IDLEIMMEDIATE:
case WIN_SETIDLE1:
case WIN_SETIDLE2:
case WIN_SLEEPNOW1:
case WIN_SLEEPNOW2:
s->status = READY_STAT;
ide_set_irq(s);
break;
case WIN_PIDENTIFY:
if (s->is_cdrom) {
ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
} else {
ide_abort_command(s);
}
ide_set_irq(s);
break;
case WIN_DIAGNOSE:
ide_set_signature(s);
s->status = READY_STAT | SEEK_STAT;
s->error = 0x01;
ide_set_irq(s);
break;
case WIN_SRST:
if (!s->is_cdrom)
goto abort_cmd;
ide_set_signature(s);
s->status = 0x00;
s->error = 0x01;
break;
case WIN_PACKETCMD:
if (!s->is_cdrom)
goto abort_cmd;
if (s->feature & 0x02)
goto abort_cmd;
s->status = READY_STAT | SEEK_STAT;
s->atapi_dma = s->feature & 1;
s->nsector = 1;
ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
ide_atapi_cmd);
break;
case CFA_REQ_EXT_ERROR_CODE:
if (!s->is_cf)
goto abort_cmd;
s->error = 0x09;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case CFA_ERASE_SECTORS:
case CFA_WEAR_LEVEL:
if (!s->is_cf)
goto abort_cmd;
if (VAR_2 == CFA_WEAR_LEVEL)
s->nsector = 0;
if (VAR_2 == CFA_ERASE_SECTORS)
s->media_changed = 1;
s->error = 0x00;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
case CFA_TRANSLATE_SECTOR:
if (!s->is_cf)
goto abort_cmd;
s->error = 0x00;
s->status = READY_STAT | SEEK_STAT;
memset(s->io_buffer, 0, 0x200);
s->io_buffer[0x00] = s->hcyl;
s->io_buffer[0x01] = s->lcyl;
s->io_buffer[0x02] = s->select;
s->io_buffer[0x03] = s->sector;
s->io_buffer[0x04] = ide_get_sector(s) >> 16;
s->io_buffer[0x05] = ide_get_sector(s) >> 8;
s->io_buffer[0x06] = ide_get_sector(s) >> 0;
s->io_buffer[0x13] = 0x00;
s->io_buffer[0x18] = 0x00;
s->io_buffer[0x19] = 0x00;
s->io_buffer[0x1a] = 0x01;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s);
break;
case CFA_ACCESS_METADATA_STORAGE:
if (!s->is_cf)
goto abort_cmd;
switch (s->feature) {
case 0x02:
ide_cfata_metadata_inquiry(s);
break;
case 0x03:
ide_cfata_metadata_read(s);
break;
case 0x04:
ide_cfata_metadata_write(s);
break;
default:
goto abort_cmd;
}
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
s->status = 0x00;
ide_set_irq(s);
break;
case IBM_SENSE_CONDITION:
if (!s->is_cf)
goto abort_cmd;
switch (s->feature) {
case 0x01:
s->nsector = 0x50;
break;
default:
goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
default:
abort_cmd:
ide_abort_command(s);
ide_set_irq(s);
break;
}
}
}
| [
"static void FUNC_0(void *VAR_0, uint32_t VAR_1, uint32_t VAR_2)\n{",
"IDEState *ide_if = VAR_0;",
"IDEState *s;",
"int VAR_3, VAR_4;",
"int VAR_5 = 0;",
"#ifdef DEBUG_IDE\nprintf(\"IDE: write VAR_1=0x%x VAR_2=0x%02x\\VAR_4\", VAR_1, VAR_2);",
"#endif\nVAR_1 &= 7;",
"if (VAR_1 != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))\nreturn;",
"switch(VAR_1) {",
"case 0:\nbreak;",
"case 1:\nide_clear_hob(ide_if);",
"ide_if[0].hob_feature = ide_if[0].feature;",
"ide_if[1].hob_feature = ide_if[1].feature;",
"ide_if[0].feature = VAR_2;",
"ide_if[1].feature = VAR_2;",
"break;",
"case 2:\nide_clear_hob(ide_if);",
"ide_if[0].hob_nsector = ide_if[0].nsector;",
"ide_if[1].hob_nsector = ide_if[1].nsector;",
"ide_if[0].nsector = VAR_2;",
"ide_if[1].nsector = VAR_2;",
"break;",
"case 3:\nide_clear_hob(ide_if);",
"ide_if[0].hob_sector = ide_if[0].sector;",
"ide_if[1].hob_sector = ide_if[1].sector;",
"ide_if[0].sector = VAR_2;",
"ide_if[1].sector = VAR_2;",
"break;",
"case 4:\nide_clear_hob(ide_if);",
"ide_if[0].hob_lcyl = ide_if[0].lcyl;",
"ide_if[1].hob_lcyl = ide_if[1].lcyl;",
"ide_if[0].lcyl = VAR_2;",
"ide_if[1].lcyl = VAR_2;",
"break;",
"case 5:\nide_clear_hob(ide_if);",
"ide_if[0].hob_hcyl = ide_if[0].hcyl;",
"ide_if[1].hob_hcyl = ide_if[1].hcyl;",
"ide_if[0].hcyl = VAR_2;",
"ide_if[1].hcyl = VAR_2;",
"break;",
"case 6:\nide_if[0].select = (VAR_2 & ~0x10) | 0xa0;",
"ide_if[1].select = (VAR_2 | 0x10) | 0xa0;",
"VAR_3 = (VAR_2 >> 4) & 1;",
"s = ide_if + VAR_3;",
"ide_if->cur_drive = s;",
"break;",
"default:\ncase 7:\n#if defined(DEBUG_IDE)\nprintf(\"ide: CMD=%02x\\VAR_4\", VAR_2);",
"#endif\ns = ide_if->cur_drive;",
"if (s != ide_if && !s->bs)\nbreak;",
"if ((s->status & (BUSY_STAT|DRQ_STAT)) && VAR_2 != WIN_DEVICE_RESET)\nbreak;",
"switch(VAR_2) {",
"case WIN_IDENTIFY:\nif (s->bs && !s->is_cdrom) {",
"if (!s->is_cf)\nide_identify(s);",
"else\nide_cfata_identify(s);",
"s->status = READY_STAT | SEEK_STAT;",
"ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);",
"} else {",
"if (s->is_cdrom) {",
"ide_set_signature(s);",
"}",
"ide_abort_command(s);",
"}",
"ide_set_irq(s);",
"break;",
"case WIN_SPECIFY:\ncase WIN_RECAL:\ns->error = 0;",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case WIN_SETMULT:\nif (s->is_cf && s->nsector == 0) {",
"s->mult_sectors = 0;",
"s->status = READY_STAT | SEEK_STAT;",
"} else if ((s->nsector & 0xff) != 0 &&",
"((s->nsector & 0xff) > MAX_MULT_SECTORS ||\n(s->nsector & (s->nsector - 1)) != 0)) {",
"ide_abort_command(s);",
"} else {",
"s->mult_sectors = s->nsector & 0xff;",
"s->status = READY_STAT | SEEK_STAT;",
"}",
"ide_set_irq(s);",
"break;",
"case WIN_VERIFY_EXT:\nVAR_5 = 1;",
"case WIN_VERIFY:\ncase WIN_VERIFY_ONCE:\nide_cmd_lba48_transform(s, VAR_5);",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case WIN_READ_EXT:\nVAR_5 = 1;",
"case WIN_READ:\ncase WIN_READ_ONCE:\nif (!s->bs)\ngoto abort_cmd;",
"ide_cmd_lba48_transform(s, VAR_5);",
"s->req_nb_sectors = 1;",
"ide_sector_read(s);",
"break;",
"case WIN_WRITE_EXT:\nVAR_5 = 1;",
"case WIN_WRITE:\ncase WIN_WRITE_ONCE:\ncase CFA_WRITE_SECT_WO_ERASE:\ncase WIN_WRITE_VERIFY:\nide_cmd_lba48_transform(s, VAR_5);",
"s->error = 0;",
"s->status = SEEK_STAT | READY_STAT;",
"s->req_nb_sectors = 1;",
"ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);",
"s->media_changed = 1;",
"break;",
"case WIN_MULTREAD_EXT:\nVAR_5 = 1;",
"case WIN_MULTREAD:\nif (!s->mult_sectors)\ngoto abort_cmd;",
"ide_cmd_lba48_transform(s, VAR_5);",
"s->req_nb_sectors = s->mult_sectors;",
"ide_sector_read(s);",
"break;",
"case WIN_MULTWRITE_EXT:\nVAR_5 = 1;",
"case WIN_MULTWRITE:\ncase CFA_WRITE_MULTI_WO_ERASE:\nif (!s->mult_sectors)\ngoto abort_cmd;",
"ide_cmd_lba48_transform(s, VAR_5);",
"s->error = 0;",
"s->status = SEEK_STAT | READY_STAT;",
"s->req_nb_sectors = s->mult_sectors;",
"VAR_4 = s->nsector;",
"if (VAR_4 > s->req_nb_sectors)\nVAR_4 = s->req_nb_sectors;",
"ide_transfer_start(s, s->io_buffer, 512 * VAR_4, ide_sector_write);",
"s->media_changed = 1;",
"break;",
"case WIN_READDMA_EXT:\nVAR_5 = 1;",
"case WIN_READDMA:\ncase WIN_READDMA_ONCE:\nif (!s->bs)\ngoto abort_cmd;",
"ide_cmd_lba48_transform(s, VAR_5);",
"ide_sector_read_dma(s);",
"break;",
"case WIN_WRITEDMA_EXT:\nVAR_5 = 1;",
"case WIN_WRITEDMA:\ncase WIN_WRITEDMA_ONCE:\nif (!s->bs)\ngoto abort_cmd;",
"ide_cmd_lba48_transform(s, VAR_5);",
"ide_sector_write_dma(s);",
"s->media_changed = 1;",
"break;",
"case WIN_READ_NATIVE_MAX_EXT:\nVAR_5 = 1;",
"case WIN_READ_NATIVE_MAX:\nide_cmd_lba48_transform(s, VAR_5);",
"ide_set_sector(s, s->nb_sectors - 1);",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case WIN_CHECKPOWERMODE1:\ncase WIN_CHECKPOWERMODE2:\ns->nsector = 0xff;",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case WIN_SETFEATURES:\nif (!s->bs)\ngoto abort_cmd;",
"switch(s->feature) {",
"case 0xcc:\ncase 0x66:\ncase 0x02:\ncase 0x82:\ncase 0xaa:\ncase 0x55:\ncase 0x05:\ncase 0x85:\ncase 0x69:\ncase 0x67:\ncase 0x96:\ncase 0x9a:\ncase 0x42:\ncase 0xc2:\ns->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case 0x03: {",
"uint8_t VAR_2 = s->nsector & 0x07;",
"switch (s->nsector >> 3) {",
"case 0x00:\ncase 0x01:\nput_le16(s->identify_data + 62,0x07);",
"put_le16(s->identify_data + 63,0x07);",
"put_le16(s->identify_data + 88,0x3f);",
"break;",
"case 0x02:\nput_le16(s->identify_data + 62,0x07 | (1 << (VAR_2 + 8)));",
"put_le16(s->identify_data + 63,0x07);",
"put_le16(s->identify_data + 88,0x3f);",
"break;",
"case 0x04:\nput_le16(s->identify_data + 62,0x07);",
"put_le16(s->identify_data + 63,0x07 | (1 << (VAR_2 + 8)));",
"put_le16(s->identify_data + 88,0x3f);",
"break;",
"case 0x08:\nput_le16(s->identify_data + 62,0x07);",
"put_le16(s->identify_data + 63,0x07);",
"put_le16(s->identify_data + 88,0x3f | (1 << (VAR_2 + 8)));",
"break;",
"default:\ngoto abort_cmd;",
"}",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"}",
"default:\ngoto abort_cmd;",
"}",
"break;",
"case WIN_FLUSH_CACHE:\ncase WIN_FLUSH_CACHE_EXT:\nif (s->bs)\nbdrv_flush(s->bs);",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case WIN_STANDBY:\ncase WIN_STANDBY2:\ncase WIN_STANDBYNOW1:\ncase WIN_STANDBYNOW2:\ncase WIN_IDLEIMMEDIATE:\ncase CFA_IDLEIMMEDIATE:\ncase WIN_SETIDLE1:\ncase WIN_SETIDLE2:\ncase WIN_SLEEPNOW1:\ncase WIN_SLEEPNOW2:\ns->status = READY_STAT;",
"ide_set_irq(s);",
"break;",
"case WIN_PIDENTIFY:\nif (s->is_cdrom) {",
"ide_atapi_identify(s);",
"s->status = READY_STAT | SEEK_STAT;",
"ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);",
"} else {",
"ide_abort_command(s);",
"}",
"ide_set_irq(s);",
"break;",
"case WIN_DIAGNOSE:\nide_set_signature(s);",
"s->status = READY_STAT | SEEK_STAT;",
"s->error = 0x01;",
"ide_set_irq(s);",
"break;",
"case WIN_SRST:\nif (!s->is_cdrom)\ngoto abort_cmd;",
"ide_set_signature(s);",
"s->status = 0x00;",
"s->error = 0x01;",
"break;",
"case WIN_PACKETCMD:\nif (!s->is_cdrom)\ngoto abort_cmd;",
"if (s->feature & 0x02)\ngoto abort_cmd;",
"s->status = READY_STAT | SEEK_STAT;",
"s->atapi_dma = s->feature & 1;",
"s->nsector = 1;",
"ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,\nide_atapi_cmd);",
"break;",
"case CFA_REQ_EXT_ERROR_CODE:\nif (!s->is_cf)\ngoto abort_cmd;",
"s->error = 0x09;",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case CFA_ERASE_SECTORS:\ncase CFA_WEAR_LEVEL:\nif (!s->is_cf)\ngoto abort_cmd;",
"if (VAR_2 == CFA_WEAR_LEVEL)\ns->nsector = 0;",
"if (VAR_2 == CFA_ERASE_SECTORS)\ns->media_changed = 1;",
"s->error = 0x00;",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"case CFA_TRANSLATE_SECTOR:\nif (!s->is_cf)\ngoto abort_cmd;",
"s->error = 0x00;",
"s->status = READY_STAT | SEEK_STAT;",
"memset(s->io_buffer, 0, 0x200);",
"s->io_buffer[0x00] = s->hcyl;",
"s->io_buffer[0x01] = s->lcyl;",
"s->io_buffer[0x02] = s->select;",
"s->io_buffer[0x03] = s->sector;",
"s->io_buffer[0x04] = ide_get_sector(s) >> 16;",
"s->io_buffer[0x05] = ide_get_sector(s) >> 8;",
"s->io_buffer[0x06] = ide_get_sector(s) >> 0;",
"s->io_buffer[0x13] = 0x00;",
"s->io_buffer[0x18] = 0x00;",
"s->io_buffer[0x19] = 0x00;",
"s->io_buffer[0x1a] = 0x01;",
"ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);",
"ide_set_irq(s);",
"break;",
"case CFA_ACCESS_METADATA_STORAGE:\nif (!s->is_cf)\ngoto abort_cmd;",
"switch (s->feature) {",
"case 0x02:\nide_cfata_metadata_inquiry(s);",
"break;",
"case 0x03:\nide_cfata_metadata_read(s);",
"break;",
"case 0x04:\nide_cfata_metadata_write(s);",
"break;",
"default:\ngoto abort_cmd;",
"}",
"ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);",
"s->status = 0x00;",
"ide_set_irq(s);",
"break;",
"case IBM_SENSE_CONDITION:\nif (!s->is_cf)\ngoto abort_cmd;",
"switch (s->feature) {",
"case 0x01:\ns->nsector = 0x50;",
"break;",
"default:\ngoto abort_cmd;",
"}",
"s->status = READY_STAT | SEEK_STAT;",
"ide_set_irq(s);",
"break;",
"default:\nabort_cmd:\nide_abort_command(s);",
"ide_set_irq(s);",
"break;",
"}",
"}",
"}"
]
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|
10,241 | _syscall3(int,sys_faccessat,int,dirfd,const char *,pathname,int,mode)
#endif
#if defined(TARGET_NR_fchmodat) && defined(__NR_fchmodat)
_syscall3(int,sys_fchmodat,int,dirfd,const char *,pathname, mode_t,mode)
#endif
#if defined(TARGET_NR_fchownat) && defined(__NR_fchownat) && defined(USE_UID16)
_syscall5(int,sys_fchownat,int,dirfd,const char *,pathname,
uid_t,owner,gid_t,group,int,flags)
#endif
#if (defined(TARGET_NR_fstatat64) || defined(TARGET_NR_newfstatat)) && \
defined(__NR_fstatat64)
_syscall4(int,sys_fstatat64,int,dirfd,const char *,pathname,
struct stat *,buf,int,flags)
#endif
#if defined(TARGET_NR_futimesat) && defined(__NR_futimesat)
_syscall3(int,sys_futimesat,int,dirfd,const char *,pathname,
const struct timeval *,times)
#endif
#if (defined(TARGET_NR_newfstatat) || defined(TARGET_NR_fstatat64) ) && \
defined(__NR_newfstatat)
_syscall4(int,sys_newfstatat,int,dirfd,const char *,pathname,
struct stat *,buf,int,flags)
#endif
#if defined(TARGET_NR_linkat) && defined(__NR_linkat)
_syscall5(int,sys_linkat,int,olddirfd,const char *,oldpath,
int,newdirfd,const char *,newpath,int,flags)
#endif
#if defined(TARGET_NR_mkdirat) && defined(__NR_mkdirat)
_syscall3(int,sys_mkdirat,int,dirfd,const char *,pathname,mode_t,mode)
#endif
#if defined(TARGET_NR_mknodat) && defined(__NR_mknodat)
_syscall4(int,sys_mknodat,int,dirfd,const char *,pathname,
mode_t,mode,dev_t,dev)
#endif
#if defined(TARGET_NR_openat) && defined(__NR_openat)
_syscall4(int,sys_openat,int,dirfd,const char *,pathname,int,flags,mode_t,mode)
#endif
#if defined(TARGET_NR_readlinkat) && defined(__NR_readlinkat)
_syscall4(int,sys_readlinkat,int,dirfd,const char *,pathname,
char *,buf,size_t,bufsize)
#endif
#if defined(TARGET_NR_renameat) && defined(__NR_renameat)
_syscall4(int,sys_renameat,int,olddirfd,const char *,oldpath,
int,newdirfd,const char *,newpath)
#endif
#if defined(TARGET_NR_symlinkat) && defined(__NR_symlinkat)
_syscall3(int,sys_symlinkat,const char *,oldpath,
int,newdirfd,const char *,newpath)
#endif
#if defined(TARGET_NR_unlinkat) && defined(__NR_unlinkat)
_syscall3(int,sys_unlinkat,int,dirfd,const char *,pathname,int,flags)
#endif
#if defined(TARGET_NR_utimensat) && defined(__NR_utimensat)
_syscall4(int,sys_utimensat,int,dirfd,const char *,pathname,
const struct timespec *,tsp,int,flags)
#endif
#endif /* CONFIG_ATFILE */
#ifdef CONFIG_INOTIFY
#include <sys/inotify.h>
#if defined(TARGET_NR_inotify_init) && defined(__NR_inotify_init)
static int sys_inotify_init(void)
{
return (inotify_init());
}
| false | qemu | ebc996f3b13004e7272c462254522ba0102f09fe | _syscall3(int,sys_faccessat,int,dirfd,const char *,pathname,int,mode)
#endif
#if defined(TARGET_NR_fchmodat) && defined(__NR_fchmodat)
_syscall3(int,sys_fchmodat,int,dirfd,const char *,pathname, mode_t,mode)
#endif
#if defined(TARGET_NR_fchownat) && defined(__NR_fchownat) && defined(USE_UID16)
_syscall5(int,sys_fchownat,int,dirfd,const char *,pathname,
uid_t,owner,gid_t,group,int,flags)
#endif
#if (defined(TARGET_NR_fstatat64) || defined(TARGET_NR_newfstatat)) && \
defined(__NR_fstatat64)
_syscall4(int,sys_fstatat64,int,dirfd,const char *,pathname,
struct stat *,buf,int,flags)
#endif
#if defined(TARGET_NR_futimesat) && defined(__NR_futimesat)
_syscall3(int,sys_futimesat,int,dirfd,const char *,pathname,
const struct timeval *,times)
#endif
#if (defined(TARGET_NR_newfstatat) || defined(TARGET_NR_fstatat64) ) && \
defined(__NR_newfstatat)
_syscall4(int,sys_newfstatat,int,dirfd,const char *,pathname,
struct stat *,buf,int,flags)
#endif
#if defined(TARGET_NR_linkat) && defined(__NR_linkat)
_syscall5(int,sys_linkat,int,olddirfd,const char *,oldpath,
int,newdirfd,const char *,newpath,int,flags)
#endif
#if defined(TARGET_NR_mkdirat) && defined(__NR_mkdirat)
_syscall3(int,sys_mkdirat,int,dirfd,const char *,pathname,mode_t,mode)
#endif
#if defined(TARGET_NR_mknodat) && defined(__NR_mknodat)
_syscall4(int,sys_mknodat,int,dirfd,const char *,pathname,
mode_t,mode,dev_t,dev)
#endif
#if defined(TARGET_NR_openat) && defined(__NR_openat)
_syscall4(int,sys_openat,int,dirfd,const char *,pathname,int,flags,mode_t,mode)
#endif
#if defined(TARGET_NR_readlinkat) && defined(__NR_readlinkat)
_syscall4(int,sys_readlinkat,int,dirfd,const char *,pathname,
char *,buf,size_t,bufsize)
#endif
#if defined(TARGET_NR_renameat) && defined(__NR_renameat)
_syscall4(int,sys_renameat,int,olddirfd,const char *,oldpath,
int,newdirfd,const char *,newpath)
#endif
#if defined(TARGET_NR_symlinkat) && defined(__NR_symlinkat)
_syscall3(int,sys_symlinkat,const char *,oldpath,
int,newdirfd,const char *,newpath)
#endif
#if defined(TARGET_NR_unlinkat) && defined(__NR_unlinkat)
_syscall3(int,sys_unlinkat,int,dirfd,const char *,pathname,int,flags)
#endif
#if defined(TARGET_NR_utimensat) && defined(__NR_utimensat)
_syscall4(int,sys_utimensat,int,dirfd,const char *,pathname,
const struct timespec *,tsp,int,flags)
#endif
#endif
#ifdef CONFIG_INOTIFY
#include <sys/inotify.h>
#if defined(TARGET_NR_inotify_init) && defined(__NR_inotify_init)
static int sys_inotify_init(void)
{
return (inotify_init());
}
| {
"code": [],
"line_no": []
} | _syscall3(int,sys_faccessat,int,dirfd,const char *,pathname,int,mode)
#endif
#if defined(TARGET_NR_fchmodat) && defined(__NR_fchmodat)
_syscall3(int,sys_fchmodat,int,dirfd,const char *,pathname, mode_t,mode)
#endif
#if defined(TARGET_NR_fchownat) && defined(__NR_fchownat) && defined(USE_UID16)
_syscall5(int,sys_fchownat,int,dirfd,const char *,pathname,
uid_t,owner,gid_t,group,int,flags)
#endif
#if (defined(TARGET_NR_fstatat64) || defined(TARGET_NR_newfstatat)) && \
defined(__NR_fstatat64)
_syscall4(int,sys_fstatat64,int,dirfd,const char *,pathname,
struct stat *,buf,int,flags)
#endif
#if defined(TARGET_NR_futimesat) && defined(__NR_futimesat)
_syscall3(int,sys_futimesat,int,dirfd,const char *,pathname,
const struct timeval *,times)
#endif
#if (defined(TARGET_NR_newfstatat) || defined(TARGET_NR_fstatat64) ) && \
defined(__NR_newfstatat)
_syscall4(int,sys_newfstatat,int,dirfd,const char *,pathname,
struct stat *,buf,int,flags)
#endif
#if defined(TARGET_NR_linkat) && defined(__NR_linkat)
_syscall5(int,sys_linkat,int,olddirfd,const char *,oldpath,
int,newdirfd,const char *,newpath,int,flags)
#endif
#if defined(TARGET_NR_mkdirat) && defined(__NR_mkdirat)
_syscall3(int,sys_mkdirat,int,dirfd,const char *,pathname,mode_t,mode)
#endif
#if defined(TARGET_NR_mknodat) && defined(__NR_mknodat)
_syscall4(int,sys_mknodat,int,dirfd,const char *,pathname,
mode_t,mode,dev_t,dev)
#endif
#if defined(TARGET_NR_openat) && defined(__NR_openat)
_syscall4(int,sys_openat,int,dirfd,const char *,pathname,int,flags,mode_t,mode)
#endif
#if defined(TARGET_NR_readlinkat) && defined(__NR_readlinkat)
_syscall4(int,sys_readlinkat,int,dirfd,const char *,pathname,
char *,buf,size_t,bufsize)
#endif
#if defined(TARGET_NR_renameat) && defined(__NR_renameat)
_syscall4(int,sys_renameat,int,olddirfd,const char *,oldpath,
int,newdirfd,const char *,newpath)
#endif
#if defined(TARGET_NR_symlinkat) && defined(__NR_symlinkat)
_syscall3(int,sys_symlinkat,const char *,oldpath,
int,newdirfd,const char *,newpath)
#endif
#if defined(TARGET_NR_unlinkat) && defined(__NR_unlinkat)
_syscall3(int,sys_unlinkat,int,dirfd,const char *,pathname,int,flags)
#endif
#if defined(TARGET_NR_utimensat) && defined(__NR_utimensat)
_syscall4(int,sys_utimensat,int,dirfd,const char *,pathname,
const struct timespec *,tsp,int,flags)
#endif
#endif
#ifdef CONFIG_INOTIFY
#include <sys/inotify.h>
#if defined(TARGET_NR_inotify_init) && defined(__NR_inotify_init)
static int sys_inotify_init(void)
{
return (inotify_init());
}
| [
"_syscall3(int,sys_faccessat,int,dirfd,const char *,pathname,int,mode)\n#endif\n#if defined(TARGET_NR_fchmodat) && defined(__NR_fchmodat)\n_syscall3(int,sys_fchmodat,int,dirfd,const char *,pathname, mode_t,mode)\n#endif\n#if defined(TARGET_NR_fchownat) && defined(__NR_fchownat) && defined(USE_UID16)\n_syscall5(int,sys_fchownat,int,dirfd,const char *,pathname,\nuid_t,owner,gid_t,group,int,flags)\n#endif\n#if (defined(TARGET_NR_fstatat64) || defined(TARGET_NR_newfstatat)) && \\\ndefined(__NR_fstatat64)\n_syscall4(int,sys_fstatat64,int,dirfd,const char *,pathname,\nstruct stat *,buf,int,flags)\n#endif\n#if defined(TARGET_NR_futimesat) && defined(__NR_futimesat)\n_syscall3(int,sys_futimesat,int,dirfd,const char *,pathname,\nconst struct timeval *,times)\n#endif\n#if (defined(TARGET_NR_newfstatat) || defined(TARGET_NR_fstatat64) ) && \\\ndefined(__NR_newfstatat)\n_syscall4(int,sys_newfstatat,int,dirfd,const char *,pathname,\nstruct stat *,buf,int,flags)\n#endif\n#if defined(TARGET_NR_linkat) && defined(__NR_linkat)\n_syscall5(int,sys_linkat,int,olddirfd,const char *,oldpath,\nint,newdirfd,const char *,newpath,int,flags)\n#endif\n#if defined(TARGET_NR_mkdirat) && defined(__NR_mkdirat)\n_syscall3(int,sys_mkdirat,int,dirfd,const char *,pathname,mode_t,mode)\n#endif\n#if defined(TARGET_NR_mknodat) && defined(__NR_mknodat)\n_syscall4(int,sys_mknodat,int,dirfd,const char *,pathname,\nmode_t,mode,dev_t,dev)\n#endif\n#if defined(TARGET_NR_openat) && defined(__NR_openat)\n_syscall4(int,sys_openat,int,dirfd,const char *,pathname,int,flags,mode_t,mode)\n#endif\n#if defined(TARGET_NR_readlinkat) && defined(__NR_readlinkat)\n_syscall4(int,sys_readlinkat,int,dirfd,const char *,pathname,\nchar *,buf,size_t,bufsize)\n#endif\n#if defined(TARGET_NR_renameat) && defined(__NR_renameat)\n_syscall4(int,sys_renameat,int,olddirfd,const char *,oldpath,\nint,newdirfd,const char *,newpath)\n#endif\n#if defined(TARGET_NR_symlinkat) && defined(__NR_symlinkat)\n_syscall3(int,sys_symlinkat,const char *,oldpath,\nint,newdirfd,const char *,newpath)\n#endif\n#if defined(TARGET_NR_unlinkat) && defined(__NR_unlinkat)\n_syscall3(int,sys_unlinkat,int,dirfd,const char *,pathname,int,flags)\n#endif\n#if defined(TARGET_NR_utimensat) && defined(__NR_utimensat)\n_syscall4(int,sys_utimensat,int,dirfd,const char *,pathname,\nconst struct timespec *,tsp,int,flags)\n#endif\n#endif\n#ifdef CONFIG_INOTIFY\n#include <sys/inotify.h>\n#if defined(TARGET_NR_inotify_init) && defined(__NR_inotify_init)\nstatic int sys_inotify_init(void)\n{",
"return (inotify_init());",
"}"
]
| [
0,
0,
0
]
| [
[
1,
3,
5,
7,
9,
11,
13,
15,
17,
19,
21,
23,
25,
27,
29,
31,
33,
35,
37,
39,
41,
43,
45,
47,
49,
51,
53,
55,
57,
59,
61,
63,
65,
67,
69,
71,
73,
75,
77,
79,
81,
83,
85,
87,
89,
91,
93,
95,
97,
99,
101,
103,
105,
107,
109,
111,
115,
119,
121,
125,
127,
129
],
[
131
],
[
133
]
]
|
10,242 | static SocketAddress *sd_socket_address(const char *path,
const char *host, const char *port)
{
SocketAddress *addr = g_new0(SocketAddress, 1);
if (path) {
addr->type = SOCKET_ADDRESS_KIND_UNIX;
addr->u.q_unix.data = g_new0(UnixSocketAddress, 1);
addr->u.q_unix.data->path = g_strdup(path);
} else {
addr->type = SOCKET_ADDRESS_KIND_INET;
addr->u.inet.data = g_new0(InetSocketAddress, 1);
addr->u.inet.data->host = g_strdup(host ?: SD_DEFAULT_ADDR);
addr->u.inet.data->port = g_strdup(port ?: stringify(SD_DEFAULT_PORT));
}
return addr;
}
| false | qemu | dfd100f242370886bb6732f70f1f7cbd8eb9fedc | static SocketAddress *sd_socket_address(const char *path,
const char *host, const char *port)
{
SocketAddress *addr = g_new0(SocketAddress, 1);
if (path) {
addr->type = SOCKET_ADDRESS_KIND_UNIX;
addr->u.q_unix.data = g_new0(UnixSocketAddress, 1);
addr->u.q_unix.data->path = g_strdup(path);
} else {
addr->type = SOCKET_ADDRESS_KIND_INET;
addr->u.inet.data = g_new0(InetSocketAddress, 1);
addr->u.inet.data->host = g_strdup(host ?: SD_DEFAULT_ADDR);
addr->u.inet.data->port = g_strdup(port ?: stringify(SD_DEFAULT_PORT));
}
return addr;
}
| {
"code": [],
"line_no": []
} | static SocketAddress *FUNC_0(const char *path,
const char *host, const char *port)
{
SocketAddress *addr = g_new0(SocketAddress, 1);
if (path) {
addr->type = SOCKET_ADDRESS_KIND_UNIX;
addr->u.q_unix.data = g_new0(UnixSocketAddress, 1);
addr->u.q_unix.data->path = g_strdup(path);
} else {
addr->type = SOCKET_ADDRESS_KIND_INET;
addr->u.inet.data = g_new0(InetSocketAddress, 1);
addr->u.inet.data->host = g_strdup(host ?: SD_DEFAULT_ADDR);
addr->u.inet.data->port = g_strdup(port ?: stringify(SD_DEFAULT_PORT));
}
return addr;
}
| [
"static SocketAddress *FUNC_0(const char *path,\nconst char *host, const char *port)\n{",
"SocketAddress *addr = g_new0(SocketAddress, 1);",
"if (path) {",
"addr->type = SOCKET_ADDRESS_KIND_UNIX;",
"addr->u.q_unix.data = g_new0(UnixSocketAddress, 1);",
"addr->u.q_unix.data->path = g_strdup(path);",
"} else {",
"addr->type = SOCKET_ADDRESS_KIND_INET;",
"addr->u.inet.data = g_new0(InetSocketAddress, 1);",
"addr->u.inet.data->host = g_strdup(host ?: SD_DEFAULT_ADDR);",
"addr->u.inet.data->port = g_strdup(port ?: stringify(SD_DEFAULT_PORT));",
"}",
"return addr;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
33
],
[
35
]
]
|
10,243 | static void configure_alarms(char const *opt)
{
int i;
int cur = 0;
int count = (sizeof(alarm_timers) / sizeof(*alarm_timers)) - 1;
char *arg;
char *name;
if (!strcmp(opt, "help")) {
show_available_alarms();
exit(0);
}
arg = strdup(opt);
/* Reorder the array */
name = strtok(arg, ",");
while (name) {
struct qemu_alarm_timer tmp;
for (i = 0; i < count; i++) {
if (!strcmp(alarm_timers[i].name, name))
break;
}
if (i == count) {
fprintf(stderr, "Unknown clock %s\n", name);
goto next;
}
if (i < cur)
/* Ignore */
goto next;
/* Swap */
tmp = alarm_timers[i];
alarm_timers[i] = alarm_timers[cur];
alarm_timers[cur] = tmp;
cur++;
next:
name = strtok(NULL, ",");
}
free(arg);
if (cur) {
/* Disable remaining timers */
for (i = cur; i < count; i++)
alarm_timers[i].name = NULL;
}
/* debug */
show_available_alarms();
}
| false | qemu | e2b577e5e548b58740ed5b1d9d12015cb7b233ff | static void configure_alarms(char const *opt)
{
int i;
int cur = 0;
int count = (sizeof(alarm_timers) / sizeof(*alarm_timers)) - 1;
char *arg;
char *name;
if (!strcmp(opt, "help")) {
show_available_alarms();
exit(0);
}
arg = strdup(opt);
name = strtok(arg, ",");
while (name) {
struct qemu_alarm_timer tmp;
for (i = 0; i < count; i++) {
if (!strcmp(alarm_timers[i].name, name))
break;
}
if (i == count) {
fprintf(stderr, "Unknown clock %s\n", name);
goto next;
}
if (i < cur)
goto next;
tmp = alarm_timers[i];
alarm_timers[i] = alarm_timers[cur];
alarm_timers[cur] = tmp;
cur++;
next:
name = strtok(NULL, ",");
}
free(arg);
if (cur) {
for (i = cur; i < count; i++)
alarm_timers[i].name = NULL;
}
show_available_alarms();
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(char const *VAR_0)
{
int VAR_1;
int VAR_2 = 0;
int VAR_3 = (sizeof(alarm_timers) / sizeof(*alarm_timers)) - 1;
char *VAR_4;
char *VAR_5;
if (!strcmp(VAR_0, "help")) {
show_available_alarms();
exit(0);
}
VAR_4 = strdup(VAR_0);
VAR_5 = strtok(VAR_4, ",");
while (VAR_5) {
struct qemu_alarm_timer VAR_6;
for (VAR_1 = 0; VAR_1 < VAR_3; VAR_1++) {
if (!strcmp(alarm_timers[VAR_1].VAR_5, VAR_5))
break;
}
if (VAR_1 == VAR_3) {
fprintf(stderr, "Unknown clock %s\n", VAR_5);
goto next;
}
if (VAR_1 < VAR_2)
goto next;
VAR_6 = alarm_timers[VAR_1];
alarm_timers[VAR_1] = alarm_timers[VAR_2];
alarm_timers[VAR_2] = VAR_6;
VAR_2++;
next:
VAR_5 = strtok(NULL, ",");
}
free(VAR_4);
if (VAR_2) {
for (VAR_1 = VAR_2; VAR_1 < VAR_3; VAR_1++)
alarm_timers[VAR_1].VAR_5 = NULL;
}
show_available_alarms();
}
| [
"static void FUNC_0(char const *VAR_0)\n{",
"int VAR_1;",
"int VAR_2 = 0;",
"int VAR_3 = (sizeof(alarm_timers) / sizeof(*alarm_timers)) - 1;",
"char *VAR_4;",
"char *VAR_5;",
"if (!strcmp(VAR_0, \"help\")) {",
"show_available_alarms();",
"exit(0);",
"}",
"VAR_4 = strdup(VAR_0);",
"VAR_5 = strtok(VAR_4, \",\");",
"while (VAR_5) {",
"struct qemu_alarm_timer VAR_6;",
"for (VAR_1 = 0; VAR_1 < VAR_3; VAR_1++) {",
"if (!strcmp(alarm_timers[VAR_1].VAR_5, VAR_5))\nbreak;",
"}",
"if (VAR_1 == VAR_3) {",
"fprintf(stderr, \"Unknown clock %s\\n\", VAR_5);",
"goto next;",
"}",
"if (VAR_1 < VAR_2)\ngoto next;",
"VAR_6 = alarm_timers[VAR_1];",
"alarm_timers[VAR_1] = alarm_timers[VAR_2];",
"alarm_timers[VAR_2] = VAR_6;",
"VAR_2++;",
"next:\nVAR_5 = strtok(NULL, \",\");",
"}",
"free(VAR_4);",
"if (VAR_2) {",
"for (VAR_1 = VAR_2; VAR_1 < VAR_3; VAR_1++)",
"alarm_timers[VAR_1].VAR_5 = NULL;",
"}",
"show_available_alarms();",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
17
],
[
19
],
[
21
],
[
23
],
[
27
],
[
33
],
[
35
],
[
37
],
[
41
],
[
43,
45
],
[
47
],
[
51
],
[
53
],
[
55
],
[
57
],
[
61,
65
],
[
71
],
[
73
],
[
75
],
[
79
],
[
81,
83
],
[
85
],
[
89
],
[
93
],
[
97
],
[
99
],
[
101
],
[
107
],
[
109
]
]
|
10,245 | static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
target_ulong args,
uint32_t nret, target_ulong rets)
{
target_ulong parameter = rtas_ld(args, 0);
target_ulong buffer = rtas_ld(args, 1);
target_ulong length = rtas_ld(args, 2);
target_ulong ret;
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
char *param_val = g_strdup_printf("MaxEntCap=%d,"
"DesMem=%llu,"
"DesProcs=%d,"
"MaxPlatProcs=%d",
max_cpus,
current_machine->ram_size / M_BYTE,
smp_cpus,
max_cpus);
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
break;
}
case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {
uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED;
ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val));
break;
}
case RTAS_SYSPARM_UUID:
ret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
break;
default:
ret = RTAS_OUT_NOT_SUPPORTED;
}
rtas_st(rets, 0, ret);
}
| false | qemu | 9c5ce8db2e5c2769ed2fd3d91928dd1853b5ce7c | static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
target_ulong args,
uint32_t nret, target_ulong rets)
{
target_ulong parameter = rtas_ld(args, 0);
target_ulong buffer = rtas_ld(args, 1);
target_ulong length = rtas_ld(args, 2);
target_ulong ret;
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
char *param_val = g_strdup_printf("MaxEntCap=%d,"
"DesMem=%llu,"
"DesProcs=%d,"
"MaxPlatProcs=%d",
max_cpus,
current_machine->ram_size / M_BYTE,
smp_cpus,
max_cpus);
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
break;
}
case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {
uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED;
ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val));
break;
}
case RTAS_SYSPARM_UUID:
ret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
break;
default:
ret = RTAS_OUT_NOT_SUPPORTED;
}
rtas_st(rets, 0, ret);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(PowerPCCPU *VAR_0,
sPAPRMachineState *VAR_1,
uint32_t VAR_2, uint32_t VAR_3,
target_ulong VAR_4,
uint32_t VAR_5, target_ulong VAR_6)
{
target_ulong parameter = rtas_ld(VAR_4, 0);
target_ulong buffer = rtas_ld(VAR_4, 1);
target_ulong length = rtas_ld(VAR_4, 2);
target_ulong ret;
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
char *VAR_7 = g_strdup_printf("MaxEntCap=%d,"
"DesMem=%llu,"
"DesProcs=%d,"
"MaxPlatProcs=%d",
max_cpus,
current_machine->ram_size / M_BYTE,
smp_cpus,
max_cpus);
ret = sysparm_st(buffer, length, VAR_7, strlen(VAR_7) + 1);
g_free(VAR_7);
break;
}
case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {
uint8_t VAR_7 = DIAGNOSTICS_RUN_MODE_DISABLED;
ret = sysparm_st(buffer, length, &VAR_7, sizeof(VAR_7));
break;
}
case RTAS_SYSPARM_UUID:
ret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));
break;
default:
ret = RTAS_OUT_NOT_SUPPORTED;
}
rtas_st(VAR_6, 0, ret);
}
| [
"static void FUNC_0(PowerPCCPU *VAR_0,\nsPAPRMachineState *VAR_1,\nuint32_t VAR_2, uint32_t VAR_3,\ntarget_ulong VAR_4,\nuint32_t VAR_5, target_ulong VAR_6)\n{",
"target_ulong parameter = rtas_ld(VAR_4, 0);",
"target_ulong buffer = rtas_ld(VAR_4, 1);",
"target_ulong length = rtas_ld(VAR_4, 2);",
"target_ulong ret;",
"switch (parameter) {",
"case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {",
"char *VAR_7 = g_strdup_printf(\"MaxEntCap=%d,\"\n\"DesMem=%llu,\"\n\"DesProcs=%d,\"\n\"MaxPlatProcs=%d\",\nmax_cpus,\ncurrent_machine->ram_size / M_BYTE,\nsmp_cpus,\nmax_cpus);",
"ret = sysparm_st(buffer, length, VAR_7, strlen(VAR_7) + 1);",
"g_free(VAR_7);",
"break;",
"}",
"case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {",
"uint8_t VAR_7 = DIAGNOSTICS_RUN_MODE_DISABLED;",
"ret = sysparm_st(buffer, length, &VAR_7, sizeof(VAR_7));",
"break;",
"}",
"case RTAS_SYSPARM_UUID:\nret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0));",
"break;",
"default:\nret = RTAS_OUT_NOT_SUPPORTED;",
"}",
"rtas_st(VAR_6, 0, ret);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5,
7,
9,
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
23
],
[
25
],
[
27,
29,
31,
33,
35,
37,
39,
41
],
[
43
],
[
45
],
[
47
],
[
49
],
[
51
],
[
53
],
[
57
],
[
59
],
[
61
],
[
63,
65
],
[
67
],
[
69,
71
],
[
73
],
[
77
],
[
79
]
]
|
10,246 | static void test_qemu_strtoull_trailing(void)
{
const char *str = "123xxx";
char f = 'X';
const char *endptr = &f;
uint64_t res = 999;
int err;
err = qemu_strtoull(str, &endptr, 0, &res);
g_assert_cmpint(err, ==, 0);
g_assert_cmpint(res, ==, 123);
g_assert(endptr == str + 3);
}
| false | qemu | bc7c08a2c375acb7ae4d433054415588b176d34c | static void test_qemu_strtoull_trailing(void)
{
const char *str = "123xxx";
char f = 'X';
const char *endptr = &f;
uint64_t res = 999;
int err;
err = qemu_strtoull(str, &endptr, 0, &res);
g_assert_cmpint(err, ==, 0);
g_assert_cmpint(res, ==, 123);
g_assert(endptr == str + 3);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void)
{
const char *VAR_0 = "123xxx";
char VAR_1 = 'X';
const char *VAR_2 = &VAR_1;
uint64_t res = 999;
int VAR_3;
VAR_3 = qemu_strtoull(VAR_0, &VAR_2, 0, &res);
g_assert_cmpint(VAR_3, ==, 0);
g_assert_cmpint(res, ==, 123);
g_assert(VAR_2 == VAR_0 + 3);
}
| [
"static void FUNC_0(void)\n{",
"const char *VAR_0 = \"123xxx\";",
"char VAR_1 = 'X';",
"const char *VAR_2 = &VAR_1;",
"uint64_t res = 999;",
"int VAR_3;",
"VAR_3 = qemu_strtoull(VAR_0, &VAR_2, 0, &res);",
"g_assert_cmpint(VAR_3, ==, 0);",
"g_assert_cmpint(res, ==, 123);",
"g_assert(VAR_2 == VAR_0 + 3);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
17
],
[
21
],
[
23
],
[
25
],
[
27
]
]
|
10,247 | void bdrv_set_dirty_bitmap(BdrvDirtyBitmap *bitmap,
int64_t cur_sector, int64_t nr_sectors)
{
assert(bdrv_dirty_bitmap_enabled(bitmap));
hbitmap_set(bitmap->bitmap, cur_sector, nr_sectors);
}
| false | qemu | b64bd51efa9bbf30df1b2f91477d2805678d0b93 | void bdrv_set_dirty_bitmap(BdrvDirtyBitmap *bitmap,
int64_t cur_sector, int64_t nr_sectors)
{
assert(bdrv_dirty_bitmap_enabled(bitmap));
hbitmap_set(bitmap->bitmap, cur_sector, nr_sectors);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(BdrvDirtyBitmap *VAR_0,
int64_t VAR_1, int64_t VAR_2)
{
assert(bdrv_dirty_bitmap_enabled(VAR_0));
hbitmap_set(VAR_0->VAR_0, VAR_1, VAR_2);
}
| [
"void FUNC_0(BdrvDirtyBitmap *VAR_0,\nint64_t VAR_1, int64_t VAR_2)\n{",
"assert(bdrv_dirty_bitmap_enabled(VAR_0));",
"hbitmap_set(VAR_0->VAR_0, VAR_1, VAR_2);",
"}"
]
| [
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
11
]
]
|
10,248 | int kvm_has_xsave(void)
{
return kvm_state->xsave;
}
| false | qemu | 28143b409f698210d85165ca518235ac7e7c5ac5 | int kvm_has_xsave(void)
{
return kvm_state->xsave;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(void)
{
return kvm_state->xsave;
}
| [
"int FUNC_0(void)\n{",
"return kvm_state->xsave;",
"}"
]
| [
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
]
]
|
10,249 | static BlockDriverAIOCB *curl_aio_readv(BlockDriverState *bs,
int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
BlockDriverCompletionFunc *cb, void *opaque)
{
CURLAIOCB *acb;
acb = qemu_aio_get(&curl_aiocb_info, bs, cb, opaque);
acb->qiov = qiov;
acb->sector_num = sector_num;
acb->nb_sectors = nb_sectors;
acb->bh = qemu_bh_new(curl_readv_bh_cb, acb);
qemu_bh_schedule(acb->bh);
return &acb->common;
}
| false | qemu | 63f0f45f2e89b60ff8245fec81328ddfde42a303 | static BlockDriverAIOCB *curl_aio_readv(BlockDriverState *bs,
int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
BlockDriverCompletionFunc *cb, void *opaque)
{
CURLAIOCB *acb;
acb = qemu_aio_get(&curl_aiocb_info, bs, cb, opaque);
acb->qiov = qiov;
acb->sector_num = sector_num;
acb->nb_sectors = nb_sectors;
acb->bh = qemu_bh_new(curl_readv_bh_cb, acb);
qemu_bh_schedule(acb->bh);
return &acb->common;
}
| {
"code": [],
"line_no": []
} | static BlockDriverAIOCB *FUNC_0(BlockDriverState *bs,
int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
BlockDriverCompletionFunc *cb, void *opaque)
{
CURLAIOCB *acb;
acb = qemu_aio_get(&curl_aiocb_info, bs, cb, opaque);
acb->qiov = qiov;
acb->sector_num = sector_num;
acb->nb_sectors = nb_sectors;
acb->bh = qemu_bh_new(curl_readv_bh_cb, acb);
qemu_bh_schedule(acb->bh);
return &acb->common;
}
| [
"static BlockDriverAIOCB *FUNC_0(BlockDriverState *bs,\nint64_t sector_num, QEMUIOVector *qiov, int nb_sectors,\nBlockDriverCompletionFunc *cb, void *opaque)\n{",
"CURLAIOCB *acb;",
"acb = qemu_aio_get(&curl_aiocb_info, bs, cb, opaque);",
"acb->qiov = qiov;",
"acb->sector_num = sector_num;",
"acb->nb_sectors = nb_sectors;",
"acb->bh = qemu_bh_new(curl_readv_bh_cb, acb);",
"qemu_bh_schedule(acb->bh);",
"return &acb->common;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5,
7
],
[
9
],
[
13
],
[
17
],
[
19
],
[
21
],
[
25
],
[
27
],
[
29
],
[
31
]
]
|
10,250 | static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
target_ulong *pages, bool is_write)
{
bool lowprot = is_write && lowprot_enabled(&cpu->env);
uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
CPUS390XState *env = &cpu->env;
int ret, i, pflags;
for (i = 0; i < nr_pages; i++) {
/* Low-address protection? */
if (lowprot && (addr < 512 || (addr >= 4096 && addr < 4096 + 512))) {
trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
return -EACCES;
}
ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
if (ret) {
return ret;
}
if (!address_space_access_valid(&address_space_memory, pages[i],
TARGET_PAGE_SIZE, is_write)) {
program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO);
return -EFAULT;
}
addr += TARGET_PAGE_SIZE;
}
return 0;
}
| false | qemu | 2bcf018340cbf233f7145e643fc1bb367f23fd90 | static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
target_ulong *pages, bool is_write)
{
bool lowprot = is_write && lowprot_enabled(&cpu->env);
uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
CPUS390XState *env = &cpu->env;
int ret, i, pflags;
for (i = 0; i < nr_pages; i++) {
if (lowprot && (addr < 512 || (addr >= 4096 && addr < 4096 + 512))) {
trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
return -EACCES;
}
ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
if (ret) {
return ret;
}
if (!address_space_access_valid(&address_space_memory, pages[i],
TARGET_PAGE_SIZE, is_write)) {
program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO);
return -EFAULT;
}
addr += TARGET_PAGE_SIZE;
}
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(S390CPU *VAR_0, vaddr VAR_1, int VAR_2,
target_ulong *VAR_3, bool VAR_4)
{
bool lowprot = VAR_4 && lowprot_enabled(&VAR_0->env);
uint64_t asc = VAR_0->env.psw.mask & PSW_MASK_ASC;
CPUS390XState *env = &VAR_0->env;
int VAR_5, VAR_6, VAR_7;
for (VAR_6 = 0; VAR_6 < VAR_2; VAR_6++) {
if (lowprot && (VAR_1 < 512 || (VAR_1 >= 4096 && VAR_1 < 4096 + 512))) {
trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
return -EACCES;
}
VAR_5 = mmu_translate(env, VAR_1, VAR_4, asc, &VAR_3[VAR_6], &VAR_7, true);
if (VAR_5) {
return VAR_5;
}
if (!address_space_access_valid(&address_space_memory, VAR_3[VAR_6],
TARGET_PAGE_SIZE, VAR_4)) {
program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO);
return -EFAULT;
}
VAR_1 += TARGET_PAGE_SIZE;
}
return 0;
}
| [
"static int FUNC_0(S390CPU *VAR_0, vaddr VAR_1, int VAR_2,\ntarget_ulong *VAR_3, bool VAR_4)\n{",
"bool lowprot = VAR_4 && lowprot_enabled(&VAR_0->env);",
"uint64_t asc = VAR_0->env.psw.mask & PSW_MASK_ASC;",
"CPUS390XState *env = &VAR_0->env;",
"int VAR_5, VAR_6, VAR_7;",
"for (VAR_6 = 0; VAR_6 < VAR_2; VAR_6++) {",
"if (lowprot && (VAR_1 < 512 || (VAR_1 >= 4096 && VAR_1 < 4096 + 512))) {",
"trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);",
"return -EACCES;",
"}",
"VAR_5 = mmu_translate(env, VAR_1, VAR_4, asc, &VAR_3[VAR_6], &VAR_7, true);",
"if (VAR_5) {",
"return VAR_5;",
"}",
"if (!address_space_access_valid(&address_space_memory, VAR_3[VAR_6],\nTARGET_PAGE_SIZE, VAR_4)) {",
"program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO);",
"return -EFAULT;",
"}",
"VAR_1 += TARGET_PAGE_SIZE;",
"}",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
17
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33
],
[
35
],
[
37,
39
],
[
41
],
[
43
],
[
45
],
[
47
],
[
49
],
[
53
],
[
55
]
]
|
10,251 | static unsigned int dec_move_sr(DisasContext *dc)
{
DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
cris_cc_mask(dc, 0);
tcg_gen_helper_0_2(helper_movl_reg_sreg,
tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
return 2;
}
| false | qemu | a7812ae412311d7d47f8aa85656faadac9d64b56 | static unsigned int dec_move_sr(DisasContext *dc)
{
DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
cris_cc_mask(dc, 0);
tcg_gen_helper_0_2(helper_movl_reg_sreg,
tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
return 2;
}
| {
"code": [],
"line_no": []
} | static unsigned int FUNC_0(DisasContext *VAR_0)
{
DIS(fprintf (logfile, "move $s%u, $r%u\n", VAR_0->op2, VAR_0->op1));
cris_cc_mask(VAR_0, 0);
tcg_gen_helper_0_2(helper_movl_reg_sreg,
tcg_const_tl(VAR_0->op1), tcg_const_tl(VAR_0->op2));
return 2;
}
| [
"static unsigned int FUNC_0(DisasContext *VAR_0)\n{",
"DIS(fprintf (logfile, \"move $s%u, $r%u\\n\", VAR_0->op2, VAR_0->op1));",
"cris_cc_mask(VAR_0, 0);",
"tcg_gen_helper_0_2(helper_movl_reg_sreg,\ntcg_const_tl(VAR_0->op1), tcg_const_tl(VAR_0->op2));",
"return 2;",
"}"
]
| [
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9,
11
],
[
13
],
[
15
]
]
|
10,252 | static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
XenPTRegInfo *reg, uint32_t real_offset,
uint32_t *data)
{
PCIDevice *d = &s->dev;
uint16_t reg_field = 0;
/* use I/O device register's value as initial value */
reg_field = pci_get_word(d->config + real_offset);
if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
xen_host_pci_set_word(&s->real_device, real_offset,
reg_field & ~PCI_MSIX_FLAGS_ENABLE);
}
s->msix->ctrl_offset = real_offset;
*data = reg->init_val;
return 0;
}
| false | qemu | 54fd08136e4ac8b88b88b15c397010e3b0de379f | static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
XenPTRegInfo *reg, uint32_t real_offset,
uint32_t *data)
{
PCIDevice *d = &s->dev;
uint16_t reg_field = 0;
reg_field = pci_get_word(d->config + real_offset);
if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
xen_host_pci_set_word(&s->real_device, real_offset,
reg_field & ~PCI_MSIX_FLAGS_ENABLE);
}
s->msix->ctrl_offset = real_offset;
*data = reg->init_val;
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(XenPCIPassthroughState *VAR_0,
XenPTRegInfo *VAR_1, uint32_t VAR_2,
uint32_t *VAR_3)
{
PCIDevice *d = &VAR_0->dev;
uint16_t reg_field = 0;
reg_field = pci_get_word(d->config + VAR_2);
if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
xen_host_pci_set_word(&VAR_0->real_device, VAR_2,
reg_field & ~PCI_MSIX_FLAGS_ENABLE);
}
VAR_0->msix->ctrl_offset = VAR_2;
*VAR_3 = VAR_1->init_val;
return 0;
}
| [
"static int FUNC_0(XenPCIPassthroughState *VAR_0,\nXenPTRegInfo *VAR_1, uint32_t VAR_2,\nuint32_t *VAR_3)\n{",
"PCIDevice *d = &VAR_0->dev;",
"uint16_t reg_field = 0;",
"reg_field = pci_get_word(d->config + VAR_2);",
"if (reg_field & PCI_MSIX_FLAGS_ENABLE) {",
"XEN_PT_LOG(d, \"MSIX already enabled, disabling it first\\n\");",
"xen_host_pci_set_word(&VAR_0->real_device, VAR_2,\nreg_field & ~PCI_MSIX_FLAGS_ENABLE);",
"}",
"VAR_0->msix->ctrl_offset = VAR_2;",
"*VAR_3 = VAR_1->init_val;",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5,
7
],
[
9
],
[
11
],
[
17
],
[
21
],
[
23
],
[
25,
27
],
[
29
],
[
33
],
[
37
],
[
39
],
[
41
]
]
|
10,254 | static ssize_t v9fs_synth_readlink(FsContext *fs_ctx, V9fsPath *path,
char *buf, size_t bufsz)
{
errno = ENOSYS;
return -1;
}
| false | qemu | 364031f17932814484657e5551ba12957d993d7e | static ssize_t v9fs_synth_readlink(FsContext *fs_ctx, V9fsPath *path,
char *buf, size_t bufsz)
{
errno = ENOSYS;
return -1;
}
| {
"code": [],
"line_no": []
} | static ssize_t FUNC_0(FsContext *fs_ctx, V9fsPath *path,
char *buf, size_t bufsz)
{
errno = ENOSYS;
return -1;
}
| [
"static ssize_t FUNC_0(FsContext *fs_ctx, V9fsPath *path,\nchar *buf, size_t bufsz)\n{",
"errno = ENOSYS;",
"return -1;",
"}"
]
| [
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
11
]
]
|
10,255 | static bool cmd_read_dma(IDEState *s, uint8_t cmd)
{
bool lba48 = (cmd == WIN_READDMA_EXT);
if (!s->bs) {
ide_abort_command(s);
return true;
}
ide_cmd_lba48_transform(s, lba48);
ide_sector_start_dma(s, IDE_DMA_READ);
return false;
}
| false | qemu | 4be746345f13e99e468c60acbd3a355e8183e3ce | static bool cmd_read_dma(IDEState *s, uint8_t cmd)
{
bool lba48 = (cmd == WIN_READDMA_EXT);
if (!s->bs) {
ide_abort_command(s);
return true;
}
ide_cmd_lba48_transform(s, lba48);
ide_sector_start_dma(s, IDE_DMA_READ);
return false;
}
| {
"code": [],
"line_no": []
} | static bool FUNC_0(IDEState *s, uint8_t cmd)
{
bool lba48 = (cmd == WIN_READDMA_EXT);
if (!s->bs) {
ide_abort_command(s);
return true;
}
ide_cmd_lba48_transform(s, lba48);
ide_sector_start_dma(s, IDE_DMA_READ);
return false;
}
| [
"static bool FUNC_0(IDEState *s, uint8_t cmd)\n{",
"bool lba48 = (cmd == WIN_READDMA_EXT);",
"if (!s->bs) {",
"ide_abort_command(s);",
"return true;",
"}",
"ide_cmd_lba48_transform(s, lba48);",
"ide_sector_start_dma(s, IDE_DMA_READ);",
"return false;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
15
],
[
19
],
[
21
],
[
25
],
[
27
]
]
|
10,256 | static void timer_start(SpiceTimer *timer, uint32_t ms)
{
qemu_mod_timer(timer->timer, qemu_get_clock(rt_clock) + ms);
}
| false | qemu | 7bd427d801e1e3293a634d3c83beadaa90ffb911 | static void timer_start(SpiceTimer *timer, uint32_t ms)
{
qemu_mod_timer(timer->timer, qemu_get_clock(rt_clock) + ms);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(SpiceTimer *VAR_0, uint32_t VAR_1)
{
qemu_mod_timer(VAR_0->VAR_0, qemu_get_clock(rt_clock) + VAR_1);
}
| [
"static void FUNC_0(SpiceTimer *VAR_0, uint32_t VAR_1)\n{",
"qemu_mod_timer(VAR_0->VAR_0, qemu_get_clock(rt_clock) + VAR_1);",
"}"
]
| [
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
]
]
|
10,257 | static int pci_pbm_init_device(SysBusDevice *dev)
{
APBState *s;
int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
s = FROM_SYSBUS(APBState, dev);
/* apb_config */
apb_config = cpu_register_io_memory(apb_config_read,
apb_config_write, s);
sysbus_init_mmio(dev, 0x40ULL, apb_config);
/* pci_ioport */
pci_ioport = cpu_register_io_memory(pci_apb_ioread,
pci_apb_iowrite, s);
sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
/* mem_config */
pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
pci_apb_config_write, s);
sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
/* mem_data */
pci_mem_data = cpu_register_io_memory(pci_apb_read,
pci_apb_write, &s->host_state);
sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
return 0;
}
| false | qemu | 4f5e19e6c570459cd524b29b24374f03860f5149 | static int pci_pbm_init_device(SysBusDevice *dev)
{
APBState *s;
int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
s = FROM_SYSBUS(APBState, dev);
apb_config = cpu_register_io_memory(apb_config_read,
apb_config_write, s);
sysbus_init_mmio(dev, 0x40ULL, apb_config);
pci_ioport = cpu_register_io_memory(pci_apb_ioread,
pci_apb_iowrite, s);
sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
pci_apb_config_write, s);
sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
pci_mem_data = cpu_register_io_memory(pci_apb_read,
pci_apb_write, &s->host_state);
sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(SysBusDevice *VAR_0)
{
APBState *s;
int VAR_1, VAR_2, VAR_3, VAR_4;
s = FROM_SYSBUS(APBState, VAR_0);
VAR_3 = cpu_register_io_memory(apb_config_read,
apb_config_write, s);
sysbus_init_mmio(VAR_0, 0x40ULL, VAR_3);
VAR_4 = cpu_register_io_memory(pci_apb_ioread,
pci_apb_iowrite, s);
sysbus_init_mmio(VAR_0, 0x10000ULL, VAR_4);
VAR_1 = cpu_register_io_memory(pci_apb_config_read,
pci_apb_config_write, s);
sysbus_init_mmio(VAR_0, 0x10ULL, VAR_1);
VAR_2 = cpu_register_io_memory(pci_apb_read,
pci_apb_write, &s->host_state);
sysbus_init_mmio(VAR_0, 0x10000000ULL, VAR_2);
return 0;
}
| [
"static int FUNC_0(SysBusDevice *VAR_0)\n{",
"APBState *s;",
"int VAR_1, VAR_2, VAR_3, VAR_4;",
"s = FROM_SYSBUS(APBState, VAR_0);",
"VAR_3 = cpu_register_io_memory(apb_config_read,\napb_config_write, s);",
"sysbus_init_mmio(VAR_0, 0x40ULL, VAR_3);",
"VAR_4 = cpu_register_io_memory(pci_apb_ioread,\npci_apb_iowrite, s);",
"sysbus_init_mmio(VAR_0, 0x10000ULL, VAR_4);",
"VAR_1 = cpu_register_io_memory(pci_apb_config_read,\npci_apb_config_write, s);",
"sysbus_init_mmio(VAR_0, 0x10ULL, VAR_1);",
"VAR_2 = cpu_register_io_memory(pci_apb_read,\npci_apb_write, &s->host_state);",
"sysbus_init_mmio(VAR_0, 0x10000000ULL, VAR_2);",
"return 0;",
"}"
]
| [
0,
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0,
0,
0,
0,
0,
0,
0,
0,
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[
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[
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[
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[
17,
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[
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33,
35
],
[
37
],
[
41,
43
],
[
45
],
[
47
],
[
49
]
]
|
10,258 | void cpu_reset (CPUMIPSState *env)
{
memset(env, 0, offsetof(CPUMIPSState, breakpoints));
tlb_flush(env, 1);
/* Minimal init */
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
* come back to the jump. */
env->CP0_ErrorEPC = env->PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
env->CP0_ErrorEPC = env->PC;
}
env->PC = (int32_t)0xBFC00000;
#if defined (MIPS_USES_R4K_TLB)
env->CP0_Random = MIPS_TLB_NB - 1;
env->tlb_in_use = MIPS_TLB_NB;
#endif
env->CP0_Wired = 0;
/* SMP not implemented */
env->CP0_EBase = (int32_t)0x80000000;
env->CP0_Config0 = MIPS_CONFIG0;
env->CP0_Config1 = MIPS_CONFIG1;
env->CP0_Config2 = MIPS_CONFIG2;
env->CP0_Config3 = MIPS_CONFIG3;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
env->CP0_WatchLo = 0;
env->hflags = MIPS_HFLAG_ERL;
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
env->CP0_PRid = MIPS_CPU;
#endif
env->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
env->hflags |= MIPS_HFLAG_UM;
env->user_mode_only = 1;
#endif
#ifdef MIPS_USES_FPU
env->fcr0 = MIPS_FCR0;
#endif
/* XXX some guesswork here, values are CPU specific */
env->SYNCI_Step = 16;
env->CCRes = 2;
}
| false | qemu | b29a0341d7ed7e7df4bf77a41db8e614f1ddb645 | void cpu_reset (CPUMIPSState *env)
{
memset(env, 0, offsetof(CPUMIPSState, breakpoints));
tlb_flush(env, 1);
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & MIPS_HFLAG_BMASK) {
env->CP0_ErrorEPC = env->PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
env->CP0_ErrorEPC = env->PC;
}
env->PC = (int32_t)0xBFC00000;
#if defined (MIPS_USES_R4K_TLB)
env->CP0_Random = MIPS_TLB_NB - 1;
env->tlb_in_use = MIPS_TLB_NB;
#endif
env->CP0_Wired = 0;
env->CP0_EBase = (int32_t)0x80000000;
env->CP0_Config0 = MIPS_CONFIG0;
env->CP0_Config1 = MIPS_CONFIG1;
env->CP0_Config2 = MIPS_CONFIG2;
env->CP0_Config3 = MIPS_CONFIG3;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
env->CP0_WatchLo = 0;
env->hflags = MIPS_HFLAG_ERL;
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
env->CP0_PRid = MIPS_CPU;
#endif
env->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
env->hflags |= MIPS_HFLAG_UM;
env->user_mode_only = 1;
#endif
#ifdef MIPS_USES_FPU
env->fcr0 = MIPS_FCR0;
#endif
env->SYNCI_Step = 16;
env->CCRes = 2;
}
| {
"code": [],
"line_no": []
} | void FUNC_0 (CPUMIPSState *VAR_0)
{
memset(VAR_0, 0, offsetof(CPUMIPSState, breakpoints));
tlb_flush(VAR_0, 1);
#if !defined(CONFIG_USER_ONLY)
if (VAR_0->hflags & MIPS_HFLAG_BMASK) {
VAR_0->CP0_ErrorEPC = VAR_0->PC - 4;
VAR_0->hflags &= ~MIPS_HFLAG_BMASK;
} else {
VAR_0->CP0_ErrorEPC = VAR_0->PC;
}
VAR_0->PC = (int32_t)0xBFC00000;
#if defined (MIPS_USES_R4K_TLB)
VAR_0->CP0_Random = MIPS_TLB_NB - 1;
VAR_0->tlb_in_use = MIPS_TLB_NB;
#endif
VAR_0->CP0_Wired = 0;
VAR_0->CP0_EBase = (int32_t)0x80000000;
VAR_0->CP0_Config0 = MIPS_CONFIG0;
VAR_0->CP0_Config1 = MIPS_CONFIG1;
VAR_0->CP0_Config2 = MIPS_CONFIG2;
VAR_0->CP0_Config3 = MIPS_CONFIG3;
VAR_0->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
VAR_0->CP0_WatchLo = 0;
VAR_0->hflags = MIPS_HFLAG_ERL;
VAR_0->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
VAR_0->CP0_PRid = MIPS_CPU;
#endif
VAR_0->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
VAR_0->hflags |= MIPS_HFLAG_UM;
VAR_0->user_mode_only = 1;
#endif
#ifdef MIPS_USES_FPU
VAR_0->fcr0 = MIPS_FCR0;
#endif
VAR_0->SYNCI_Step = 16;
VAR_0->CCRes = 2;
}
| [
"void FUNC_0 (CPUMIPSState *VAR_0)\n{",
"memset(VAR_0, 0, offsetof(CPUMIPSState, breakpoints));",
"tlb_flush(VAR_0, 1);",
"#if !defined(CONFIG_USER_ONLY)\nif (VAR_0->hflags & MIPS_HFLAG_BMASK) {",
"VAR_0->CP0_ErrorEPC = VAR_0->PC - 4;",
"VAR_0->hflags &= ~MIPS_HFLAG_BMASK;",
"} else {",
"VAR_0->CP0_ErrorEPC = VAR_0->PC;",
"}",
"VAR_0->PC = (int32_t)0xBFC00000;",
"#if defined (MIPS_USES_R4K_TLB)\nVAR_0->CP0_Random = MIPS_TLB_NB - 1;",
"VAR_0->tlb_in_use = MIPS_TLB_NB;",
"#endif\nVAR_0->CP0_Wired = 0;",
"VAR_0->CP0_EBase = (int32_t)0x80000000;",
"VAR_0->CP0_Config0 = MIPS_CONFIG0;",
"VAR_0->CP0_Config1 = MIPS_CONFIG1;",
"VAR_0->CP0_Config2 = MIPS_CONFIG2;",
"VAR_0->CP0_Config3 = MIPS_CONFIG3;",
"VAR_0->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);",
"VAR_0->CP0_WatchLo = 0;",
"VAR_0->hflags = MIPS_HFLAG_ERL;",
"VAR_0->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);",
"VAR_0->CP0_PRid = MIPS_CPU;",
"#endif\nVAR_0->exception_index = EXCP_NONE;",
"#if defined(CONFIG_USER_ONLY)\nVAR_0->hflags |= MIPS_HFLAG_UM;",
"VAR_0->user_mode_only = 1;",
"#endif\n#ifdef MIPS_USES_FPU\nVAR_0->fcr0 = MIPS_FCR0;",
"#endif\nVAR_0->SYNCI_Step = 16;",
"VAR_0->CCRes = 2;",
"}"
]
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[
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[
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[
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[
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[
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[
35,
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[
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[
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[
51
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[
53
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[
55
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[
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[
61
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[
65
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[
67
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[
69,
71
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[
73,
75
],
[
77
],
[
79,
81,
83
],
[
85,
89
],
[
91
],
[
93
]
]
|
10,259 | static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
{
TCGv rd, rm, tmp;
rd = new_tmp();
rm = new_tmp();
tmp = new_tmp();
tcg_gen_andi_i32(rd, t0, 0xff);
tcg_gen_shri_i32(tmp, t0, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff00);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shli_i32(tmp, t1, 16);
tcg_gen_andi_i32(tmp, tmp, 0xff0000);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shli_i32(tmp, t1, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff000000);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shri_i32(rm, t0, 8);
tcg_gen_andi_i32(rm, rm, 0xff);
tcg_gen_shri_i32(tmp, t0, 16);
tcg_gen_andi_i32(tmp, tmp, 0xff00);
tcg_gen_or_i32(rm, rm, tmp);
tcg_gen_shli_i32(tmp, t1, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff0000);
tcg_gen_or_i32(rm, rm, tmp);
tcg_gen_andi_i32(tmp, t1, 0xff000000);
tcg_gen_or_i32(t1, rm, tmp);
tcg_gen_mov_i32(t0, rd);
dead_tmp(tmp);
dead_tmp(rm);
dead_tmp(rd);
}
| false | qemu | 02acedf93da420713a0c4bbeaf32ce9d734a4332 | static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
{
TCGv rd, rm, tmp;
rd = new_tmp();
rm = new_tmp();
tmp = new_tmp();
tcg_gen_andi_i32(rd, t0, 0xff);
tcg_gen_shri_i32(tmp, t0, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff00);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shli_i32(tmp, t1, 16);
tcg_gen_andi_i32(tmp, tmp, 0xff0000);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shli_i32(tmp, t1, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff000000);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shri_i32(rm, t0, 8);
tcg_gen_andi_i32(rm, rm, 0xff);
tcg_gen_shri_i32(tmp, t0, 16);
tcg_gen_andi_i32(tmp, tmp, 0xff00);
tcg_gen_or_i32(rm, rm, tmp);
tcg_gen_shli_i32(tmp, t1, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff0000);
tcg_gen_or_i32(rm, rm, tmp);
tcg_gen_andi_i32(tmp, t1, 0xff000000);
tcg_gen_or_i32(t1, rm, tmp);
tcg_gen_mov_i32(t0, rd);
dead_tmp(tmp);
dead_tmp(rm);
dead_tmp(rd);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(TCGv VAR_0, TCGv VAR_1)
{
TCGv rd, rm, tmp;
rd = new_tmp();
rm = new_tmp();
tmp = new_tmp();
tcg_gen_andi_i32(rd, VAR_0, 0xff);
tcg_gen_shri_i32(tmp, VAR_0, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff00);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shli_i32(tmp, VAR_1, 16);
tcg_gen_andi_i32(tmp, tmp, 0xff0000);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shli_i32(tmp, VAR_1, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff000000);
tcg_gen_or_i32(rd, rd, tmp);
tcg_gen_shri_i32(rm, VAR_0, 8);
tcg_gen_andi_i32(rm, rm, 0xff);
tcg_gen_shri_i32(tmp, VAR_0, 16);
tcg_gen_andi_i32(tmp, tmp, 0xff00);
tcg_gen_or_i32(rm, rm, tmp);
tcg_gen_shli_i32(tmp, VAR_1, 8);
tcg_gen_andi_i32(tmp, tmp, 0xff0000);
tcg_gen_or_i32(rm, rm, tmp);
tcg_gen_andi_i32(tmp, VAR_1, 0xff000000);
tcg_gen_or_i32(VAR_1, rm, tmp);
tcg_gen_mov_i32(VAR_0, rd);
dead_tmp(tmp);
dead_tmp(rm);
dead_tmp(rd);
}
| [
"static void FUNC_0(TCGv VAR_0, TCGv VAR_1)\n{",
"TCGv rd, rm, tmp;",
"rd = new_tmp();",
"rm = new_tmp();",
"tmp = new_tmp();",
"tcg_gen_andi_i32(rd, VAR_0, 0xff);",
"tcg_gen_shri_i32(tmp, VAR_0, 8);",
"tcg_gen_andi_i32(tmp, tmp, 0xff00);",
"tcg_gen_or_i32(rd, rd, tmp);",
"tcg_gen_shli_i32(tmp, VAR_1, 16);",
"tcg_gen_andi_i32(tmp, tmp, 0xff0000);",
"tcg_gen_or_i32(rd, rd, tmp);",
"tcg_gen_shli_i32(tmp, VAR_1, 8);",
"tcg_gen_andi_i32(tmp, tmp, 0xff000000);",
"tcg_gen_or_i32(rd, rd, tmp);",
"tcg_gen_shri_i32(rm, VAR_0, 8);",
"tcg_gen_andi_i32(rm, rm, 0xff);",
"tcg_gen_shri_i32(tmp, VAR_0, 16);",
"tcg_gen_andi_i32(tmp, tmp, 0xff00);",
"tcg_gen_or_i32(rm, rm, tmp);",
"tcg_gen_shli_i32(tmp, VAR_1, 8);",
"tcg_gen_andi_i32(tmp, tmp, 0xff0000);",
"tcg_gen_or_i32(rm, rm, tmp);",
"tcg_gen_andi_i32(tmp, VAR_1, 0xff000000);",
"tcg_gen_or_i32(VAR_1, rm, tmp);",
"tcg_gen_mov_i32(VAR_0, rd);",
"dead_tmp(tmp);",
"dead_tmp(rm);",
"dead_tmp(rd);",
"}"
]
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[
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[
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[
11
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[
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[
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[
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[
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[
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[
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[
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[
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[
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[
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57
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[
59
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[
63
],
[
65
],
[
67
],
[
69
]
]
|
10,260 | static int nic_can_receive(NetClientState *nc)
{
EEPRO100State *s = qemu_get_nic_opaque(nc);
TRACE(RXTX, logout("%p\n", s));
return get_ru_state(s) == ru_ready;
#if 0
return !eepro100_buffer_full(s);
#endif
}
| false | qemu | 363db4b249244f31d3c47fbd5a8b128c95ba8fe7 | static int nic_can_receive(NetClientState *nc)
{
EEPRO100State *s = qemu_get_nic_opaque(nc);
TRACE(RXTX, logout("%p\n", s));
return get_ru_state(s) == ru_ready;
#if 0
return !eepro100_buffer_full(s);
#endif
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(NetClientState *VAR_0)
{
EEPRO100State *s = qemu_get_nic_opaque(VAR_0);
TRACE(RXTX, logout("%p\n", s));
return get_ru_state(s) == ru_ready;
#if 0
return !eepro100_buffer_full(s);
#endif
}
| [
"static int FUNC_0(NetClientState *VAR_0)\n{",
"EEPRO100State *s = qemu_get_nic_opaque(VAR_0);",
"TRACE(RXTX, logout(\"%p\\n\", s));",
"return get_ru_state(s) == ru_ready;",
"#if 0\nreturn !eepro100_buffer_full(s);",
"#endif\n}"
]
| [
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11,
13
],
[
15,
17
]
]
|
10,261 | int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
{
return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
}
| false | qemu | b854bc196f5c4b4e3299c0b0ee63cf828ece9e77 | int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
target_phys_addr_t addr)
{
return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(struct omap_mpu_state_s *VAR_0,
target_phys_addr_t VAR_1)
{
return VAR_1 >= OMAP_EMIFF_BASE && VAR_1 < OMAP_EMIFF_BASE + VAR_0->sdram_size;
}
| [
"int FUNC_0(struct omap_mpu_state_s *VAR_0,\ntarget_phys_addr_t VAR_1)\n{",
"return VAR_1 >= OMAP_EMIFF_BASE && VAR_1 < OMAP_EMIFF_BASE + VAR_0->sdram_size;",
"}"
]
| [
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
]
]
|
10,262 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
const char *default_devaddr)
{
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
PCIBus *bus;
int devfn;
PCIDevice *pci_dev;
DeviceState *dev;
int i;
i = qemu_find_nic_model(nd, pci_nic_models, default_model);
if (i < 0)
return NULL;
bus = pci_get_bus_devfn(&devfn, devaddr);
if (!bus) {
error_report("Invalid PCI device address %s for device %s",
devaddr, pci_nic_names[i]);
return NULL;
}
pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
dev = &pci_dev->qdev;
if (nd->name)
dev->id = qemu_strdup(nd->name);
qdev_set_nic_properties(dev, nd);
if (qdev_init(dev) < 0)
return NULL;
return pci_dev;
}
| false | qemu | 1bb650420021ced718d550559034a5147c053068 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
const char *default_devaddr)
{
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
PCIBus *bus;
int devfn;
PCIDevice *pci_dev;
DeviceState *dev;
int i;
i = qemu_find_nic_model(nd, pci_nic_models, default_model);
if (i < 0)
return NULL;
bus = pci_get_bus_devfn(&devfn, devaddr);
if (!bus) {
error_report("Invalid PCI device address %s for device %s",
devaddr, pci_nic_names[i]);
return NULL;
}
pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
dev = &pci_dev->qdev;
if (nd->name)
dev->id = qemu_strdup(nd->name);
qdev_set_nic_properties(dev, nd);
if (qdev_init(dev) < 0)
return NULL;
return pci_dev;
}
| {
"code": [],
"line_no": []
} | PCIDevice *FUNC_0(NICInfo *nd, const char *default_model,
const char *default_devaddr)
{
const char *VAR_0 = nd->VAR_0 ? nd->VAR_0 : default_devaddr;
PCIBus *bus;
int VAR_1;
PCIDevice *pci_dev;
DeviceState *dev;
int VAR_2;
VAR_2 = qemu_find_nic_model(nd, pci_nic_models, default_model);
if (VAR_2 < 0)
return NULL;
bus = pci_get_bus_devfn(&VAR_1, VAR_0);
if (!bus) {
error_report("Invalid PCI device address %s for device %s",
VAR_0, pci_nic_names[VAR_2]);
return NULL;
}
pci_dev = pci_create(bus, VAR_1, pci_nic_names[VAR_2]);
dev = &pci_dev->qdev;
if (nd->name)
dev->id = qemu_strdup(nd->name);
qdev_set_nic_properties(dev, nd);
if (qdev_init(dev) < 0)
return NULL;
return pci_dev;
}
| [
"PCIDevice *FUNC_0(NICInfo *nd, const char *default_model,\nconst char *default_devaddr)\n{",
"const char *VAR_0 = nd->VAR_0 ? nd->VAR_0 : default_devaddr;",
"PCIBus *bus;",
"int VAR_1;",
"PCIDevice *pci_dev;",
"DeviceState *dev;",
"int VAR_2;",
"VAR_2 = qemu_find_nic_model(nd, pci_nic_models, default_model);",
"if (VAR_2 < 0)\nreturn NULL;",
"bus = pci_get_bus_devfn(&VAR_1, VAR_0);",
"if (!bus) {",
"error_report(\"Invalid PCI device address %s for device %s\",\nVAR_0, pci_nic_names[VAR_2]);",
"return NULL;",
"}",
"pci_dev = pci_create(bus, VAR_1, pci_nic_names[VAR_2]);",
"dev = &pci_dev->qdev;",
"if (nd->name)\ndev->id = qemu_strdup(nd->name);",
"qdev_set_nic_properties(dev, nd);",
"if (qdev_init(dev) < 0)\nreturn NULL;",
"return pci_dev;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23,
25
],
[
29
],
[
31
],
[
33,
35
],
[
37
],
[
39
],
[
43
],
[
45
],
[
47,
49
],
[
51
],
[
53,
55
],
[
57
],
[
59
]
]
|
10,263 | static const char *local_mapped_attr_path(FsContext *ctx,
const char *path, char *buffer)
{
char *dir_name;
char *tmp_path = g_strdup(path);
char *base_name = basename(tmp_path);
/* NULL terminate the directory */
dir_name = tmp_path;
*(base_name - 1) = '\0';
snprintf(buffer, PATH_MAX, "%s/%s/%s/%s",
ctx->fs_root, dir_name, VIRTFS_META_DIR, base_name);
g_free(tmp_path);
return buffer;
}
| false | qemu | 4fa4ce7107c6ec432f185307158c5df91ce54308 | static const char *local_mapped_attr_path(FsContext *ctx,
const char *path, char *buffer)
{
char *dir_name;
char *tmp_path = g_strdup(path);
char *base_name = basename(tmp_path);
dir_name = tmp_path;
*(base_name - 1) = '\0';
snprintf(buffer, PATH_MAX, "%s/%s/%s/%s",
ctx->fs_root, dir_name, VIRTFS_META_DIR, base_name);
g_free(tmp_path);
return buffer;
}
| {
"code": [],
"line_no": []
} | static const char *FUNC_0(FsContext *VAR_0,
const char *VAR_1, char *VAR_2)
{
char *VAR_3;
char *VAR_4 = g_strdup(VAR_1);
char *VAR_5 = basename(VAR_4);
VAR_3 = VAR_4;
*(VAR_5 - 1) = '\0';
snprintf(VAR_2, PATH_MAX, "%s/%s/%s/%s",
VAR_0->fs_root, VAR_3, VIRTFS_META_DIR, VAR_5);
g_free(VAR_4);
return VAR_2;
}
| [
"static const char *FUNC_0(FsContext *VAR_0,\nconst char *VAR_1, char *VAR_2)\n{",
"char *VAR_3;",
"char *VAR_4 = g_strdup(VAR_1);",
"char *VAR_5 = basename(VAR_4);",
"VAR_3 = VAR_4;",
"*(VAR_5 - 1) = '\\0';",
"snprintf(VAR_2, PATH_MAX, \"%s/%s/%s/%s\",\nVAR_0->fs_root, VAR_3, VIRTFS_META_DIR, VAR_5);",
"g_free(VAR_4);",
"return VAR_2;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
11
],
[
17
],
[
19
],
[
23,
25
],
[
27
],
[
29
],
[
31
]
]
|
10,265 | RxFilterInfoList *qmp_query_rx_filter(bool has_name, const char *name,
Error **errp)
{
NetClientState *nc;
RxFilterInfoList *filter_list = NULL, *last_entry = NULL;
QTAILQ_FOREACH(nc, &net_clients, next) {
RxFilterInfoList *entry;
RxFilterInfo *info;
if (has_name && strcmp(nc->name, name) != 0) {
continue;
}
/* only query rx-filter information of NIC */
if (nc->info->type != NET_CLIENT_OPTIONS_KIND_NIC) {
if (has_name) {
error_setg(errp, "net client(%s) isn't a NIC", name);
break;
}
continue;
}
if (nc->info->query_rx_filter) {
info = nc->info->query_rx_filter(nc);
entry = g_malloc0(sizeof(*entry));
entry->value = info;
if (!filter_list) {
filter_list = entry;
} else {
last_entry->next = entry;
}
last_entry = entry;
} else if (has_name) {
error_setg(errp, "net client(%s) doesn't support"
" rx-filter querying", name);
break;
}
if (has_name) {
break;
}
}
if (filter_list == NULL && !error_is_set(errp) && has_name) {
error_setg(errp, "invalid net client name: %s", name);
}
return filter_list;
}
| false | qemu | 9083da1d4c9dfff30d411f8c73ea494e9d78de1b | RxFilterInfoList *qmp_query_rx_filter(bool has_name, const char *name,
Error **errp)
{
NetClientState *nc;
RxFilterInfoList *filter_list = NULL, *last_entry = NULL;
QTAILQ_FOREACH(nc, &net_clients, next) {
RxFilterInfoList *entry;
RxFilterInfo *info;
if (has_name && strcmp(nc->name, name) != 0) {
continue;
}
if (nc->info->type != NET_CLIENT_OPTIONS_KIND_NIC) {
if (has_name) {
error_setg(errp, "net client(%s) isn't a NIC", name);
break;
}
continue;
}
if (nc->info->query_rx_filter) {
info = nc->info->query_rx_filter(nc);
entry = g_malloc0(sizeof(*entry));
entry->value = info;
if (!filter_list) {
filter_list = entry;
} else {
last_entry->next = entry;
}
last_entry = entry;
} else if (has_name) {
error_setg(errp, "net client(%s) doesn't support"
" rx-filter querying", name);
break;
}
if (has_name) {
break;
}
}
if (filter_list == NULL && !error_is_set(errp) && has_name) {
error_setg(errp, "invalid net client name: %s", name);
}
return filter_list;
}
| {
"code": [],
"line_no": []
} | RxFilterInfoList *FUNC_0(bool has_name, const char *name,
Error **errp)
{
NetClientState *nc;
RxFilterInfoList *filter_list = NULL, *last_entry = NULL;
QTAILQ_FOREACH(nc, &net_clients, next) {
RxFilterInfoList *entry;
RxFilterInfo *info;
if (has_name && strcmp(nc->name, name) != 0) {
continue;
}
if (nc->info->type != NET_CLIENT_OPTIONS_KIND_NIC) {
if (has_name) {
error_setg(errp, "net client(%s) isn't a NIC", name);
break;
}
continue;
}
if (nc->info->query_rx_filter) {
info = nc->info->query_rx_filter(nc);
entry = g_malloc0(sizeof(*entry));
entry->value = info;
if (!filter_list) {
filter_list = entry;
} else {
last_entry->next = entry;
}
last_entry = entry;
} else if (has_name) {
error_setg(errp, "net client(%s) doesn't support"
" rx-filter querying", name);
break;
}
if (has_name) {
break;
}
}
if (filter_list == NULL && !error_is_set(errp) && has_name) {
error_setg(errp, "invalid net client name: %s", name);
}
return filter_list;
}
| [
"RxFilterInfoList *FUNC_0(bool has_name, const char *name,\nError **errp)\n{",
"NetClientState *nc;",
"RxFilterInfoList *filter_list = NULL, *last_entry = NULL;",
"QTAILQ_FOREACH(nc, &net_clients, next) {",
"RxFilterInfoList *entry;",
"RxFilterInfo *info;",
"if (has_name && strcmp(nc->name, name) != 0) {",
"continue;",
"}",
"if (nc->info->type != NET_CLIENT_OPTIONS_KIND_NIC) {",
"if (has_name) {",
"error_setg(errp, \"net client(%s) isn't a NIC\", name);",
"break;",
"}",
"continue;",
"}",
"if (nc->info->query_rx_filter) {",
"info = nc->info->query_rx_filter(nc);",
"entry = g_malloc0(sizeof(*entry));",
"entry->value = info;",
"if (!filter_list) {",
"filter_list = entry;",
"} else {",
"last_entry->next = entry;",
"}",
"last_entry = entry;",
"} else if (has_name) {",
"error_setg(errp, \"net client(%s) doesn't support\"\n\" rx-filter querying\", name);",
"break;",
"}",
"if (has_name) {",
"break;",
"}",
"}",
"if (filter_list == NULL && !error_is_set(errp) && has_name) {",
"error_setg(errp, \"invalid net client name: %s\", name);",
"}",
"return filter_list;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7
],
[
9
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
31
],
[
33
],
[
35
],
[
37
],
[
39
],
[
41
],
[
43
],
[
47
],
[
49
],
[
51
],
[
53
],
[
57
],
[
59
],
[
61
],
[
63
],
[
65
],
[
67
],
[
69
],
[
71,
73
],
[
75
],
[
77
],
[
81
],
[
83
],
[
85
],
[
87
],
[
91
],
[
93
],
[
95
],
[
99
],
[
101
]
]
|
10,267 | write_f(int argc, char **argv)
{
struct timeval t1, t2;
int Cflag = 0, pflag = 0, qflag = 0, bflag = 0;
int c, cnt;
char *buf;
int64_t offset;
int count;
/* Some compilers get confused and warn if this is not initialized. */
int total = 0;
int pattern = 0xcd;
while ((c = getopt(argc, argv, "bCpP:q")) != EOF) {
switch (c) {
case 'b':
bflag = 1;
break;
case 'C':
Cflag = 1;
break;
case 'p':
pflag = 1;
break;
case 'P':
pattern = atoi(optarg);
break;
case 'q':
qflag = 1;
break;
default:
return command_usage(&write_cmd);
}
}
if (optind != argc - 2)
return command_usage(&write_cmd);
if (bflag && pflag) {
printf("-b and -p cannot be specified at the same time\n");
return 0;
}
offset = cvtnum(argv[optind]);
if (offset < 0) {
printf("non-numeric length argument -- %s\n", argv[optind]);
return 0;
}
optind++;
count = cvtnum(argv[optind]);
if (count < 0) {
printf("non-numeric length argument -- %s\n", argv[optind]);
return 0;
}
if (!pflag) {
if (offset & 0x1ff) {
printf("offset %lld is not sector aligned\n",
(long long)offset);
return 0;
}
if (count & 0x1ff) {
printf("count %d is not sector aligned\n",
count);
return 0;
}
}
buf = qemu_io_alloc(count, pattern);
gettimeofday(&t1, NULL);
if (pflag)
cnt = do_pwrite(buf, offset, count, &total);
else if (bflag)
cnt = do_save_vmstate(buf, offset, count, &total);
else
cnt = do_write(buf, offset, count, &total);
gettimeofday(&t2, NULL);
if (cnt < 0) {
printf("write failed: %s\n", strerror(-cnt));
goto out;
}
if (qflag)
goto out;
/* Finally, report back -- -C gives a parsable format */
t2 = tsub(t2, t1);
print_report("wrote", &t2, offset, count, total, cnt, Cflag);
out:
qemu_io_free(buf);
return 0;
}
| false | qemu | cf070d7ec0b8fb21faa9a630ed5cc66f90844a08 | write_f(int argc, char **argv)
{
struct timeval t1, t2;
int Cflag = 0, pflag = 0, qflag = 0, bflag = 0;
int c, cnt;
char *buf;
int64_t offset;
int count;
int total = 0;
int pattern = 0xcd;
while ((c = getopt(argc, argv, "bCpP:q")) != EOF) {
switch (c) {
case 'b':
bflag = 1;
break;
case 'C':
Cflag = 1;
break;
case 'p':
pflag = 1;
break;
case 'P':
pattern = atoi(optarg);
break;
case 'q':
qflag = 1;
break;
default:
return command_usage(&write_cmd);
}
}
if (optind != argc - 2)
return command_usage(&write_cmd);
if (bflag && pflag) {
printf("-b and -p cannot be specified at the same time\n");
return 0;
}
offset = cvtnum(argv[optind]);
if (offset < 0) {
printf("non-numeric length argument -- %s\n", argv[optind]);
return 0;
}
optind++;
count = cvtnum(argv[optind]);
if (count < 0) {
printf("non-numeric length argument -- %s\n", argv[optind]);
return 0;
}
if (!pflag) {
if (offset & 0x1ff) {
printf("offset %lld is not sector aligned\n",
(long long)offset);
return 0;
}
if (count & 0x1ff) {
printf("count %d is not sector aligned\n",
count);
return 0;
}
}
buf = qemu_io_alloc(count, pattern);
gettimeofday(&t1, NULL);
if (pflag)
cnt = do_pwrite(buf, offset, count, &total);
else if (bflag)
cnt = do_save_vmstate(buf, offset, count, &total);
else
cnt = do_write(buf, offset, count, &total);
gettimeofday(&t2, NULL);
if (cnt < 0) {
printf("write failed: %s\n", strerror(-cnt));
goto out;
}
if (qflag)
goto out;
t2 = tsub(t2, t1);
print_report("wrote", &t2, offset, count, total, cnt, Cflag);
out:
qemu_io_free(buf);
return 0;
}
| {
"code": [],
"line_no": []
} | FUNC_0(int VAR_0, char **VAR_1)
{
struct timeval VAR_2, VAR_3;
int VAR_4 = 0, VAR_5 = 0, VAR_6 = 0, VAR_7 = 0;
int VAR_8, VAR_9;
char *VAR_10;
int64_t offset;
int VAR_11;
int VAR_12 = 0;
int VAR_13 = 0xcd;
while ((VAR_8 = getopt(VAR_0, VAR_1, "bCpP:q")) != EOF) {
switch (VAR_8) {
case 'b':
VAR_7 = 1;
break;
case 'C':
VAR_4 = 1;
break;
case 'p':
VAR_5 = 1;
break;
case 'P':
VAR_13 = atoi(optarg);
break;
case 'q':
VAR_6 = 1;
break;
default:
return command_usage(&write_cmd);
}
}
if (optind != VAR_0 - 2)
return command_usage(&write_cmd);
if (VAR_7 && VAR_5) {
printf("-b and -p cannot be specified at the same time\n");
return 0;
}
offset = cvtnum(VAR_1[optind]);
if (offset < 0) {
printf("non-numeric length argument -- %s\n", VAR_1[optind]);
return 0;
}
optind++;
VAR_11 = cvtnum(VAR_1[optind]);
if (VAR_11 < 0) {
printf("non-numeric length argument -- %s\n", VAR_1[optind]);
return 0;
}
if (!VAR_5) {
if (offset & 0x1ff) {
printf("offset %lld is not sector aligned\n",
(long long)offset);
return 0;
}
if (VAR_11 & 0x1ff) {
printf("VAR_11 %d is not sector aligned\n",
VAR_11);
return 0;
}
}
VAR_10 = qemu_io_alloc(VAR_11, VAR_13);
gettimeofday(&VAR_2, NULL);
if (VAR_5)
VAR_9 = do_pwrite(VAR_10, offset, VAR_11, &VAR_12);
else if (VAR_7)
VAR_9 = do_save_vmstate(VAR_10, offset, VAR_11, &VAR_12);
else
VAR_9 = do_write(VAR_10, offset, VAR_11, &VAR_12);
gettimeofday(&VAR_3, NULL);
if (VAR_9 < 0) {
printf("write failed: %s\n", strerror(-VAR_9));
goto out;
}
if (VAR_6)
goto out;
VAR_3 = tsub(VAR_3, VAR_2);
print_report("wrote", &VAR_3, offset, VAR_11, VAR_12, VAR_9, VAR_4);
out:
qemu_io_free(VAR_10);
return 0;
}
| [
"FUNC_0(int VAR_0, char **VAR_1)\n{",
"struct timeval VAR_2, VAR_3;",
"int VAR_4 = 0, VAR_5 = 0, VAR_6 = 0, VAR_7 = 0;",
"int VAR_8, VAR_9;",
"char *VAR_10;",
"int64_t offset;",
"int VAR_11;",
"int VAR_12 = 0;",
"int VAR_13 = 0xcd;",
"while ((VAR_8 = getopt(VAR_0, VAR_1, \"bCpP:q\")) != EOF) {",
"switch (VAR_8) {",
"case 'b':\nVAR_7 = 1;",
"break;",
"case 'C':\nVAR_4 = 1;",
"break;",
"case 'p':\nVAR_5 = 1;",
"break;",
"case 'P':\nVAR_13 = atoi(optarg);",
"break;",
"case 'q':\nVAR_6 = 1;",
"break;",
"default:\nreturn command_usage(&write_cmd);",
"}",
"}",
"if (optind != VAR_0 - 2)\nreturn command_usage(&write_cmd);",
"if (VAR_7 && VAR_5) {",
"printf(\"-b and -p cannot be specified at the same time\\n\");",
"return 0;",
"}",
"offset = cvtnum(VAR_1[optind]);",
"if (offset < 0) {",
"printf(\"non-numeric length argument -- %s\\n\", VAR_1[optind]);",
"return 0;",
"}",
"optind++;",
"VAR_11 = cvtnum(VAR_1[optind]);",
"if (VAR_11 < 0) {",
"printf(\"non-numeric length argument -- %s\\n\", VAR_1[optind]);",
"return 0;",
"}",
"if (!VAR_5) {",
"if (offset & 0x1ff) {",
"printf(\"offset %lld is not sector aligned\\n\",\n(long long)offset);",
"return 0;",
"}",
"if (VAR_11 & 0x1ff) {",
"printf(\"VAR_11 %d is not sector aligned\\n\",\nVAR_11);",
"return 0;",
"}",
"}",
"VAR_10 = qemu_io_alloc(VAR_11, VAR_13);",
"gettimeofday(&VAR_2, NULL);",
"if (VAR_5)\nVAR_9 = do_pwrite(VAR_10, offset, VAR_11, &VAR_12);",
"else if (VAR_7)\nVAR_9 = do_save_vmstate(VAR_10, offset, VAR_11, &VAR_12);",
"else\nVAR_9 = do_write(VAR_10, offset, VAR_11, &VAR_12);",
"gettimeofday(&VAR_3, NULL);",
"if (VAR_9 < 0) {",
"printf(\"write failed: %s\\n\", strerror(-VAR_9));",
"goto out;",
"}",
"if (VAR_6)\ngoto out;",
"VAR_3 = tsub(VAR_3, VAR_2);",
"print_report(\"wrote\", &VAR_3, offset, VAR_11, VAR_12, VAR_9, VAR_4);",
"out:\nqemu_io_free(VAR_10);",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
15
],
[
19
],
[
21
],
[
25
],
[
27
],
[
29,
31
],
[
33
],
[
35,
37
],
[
39
],
[
41,
43
],
[
45
],
[
47,
49
],
[
51
],
[
53,
55
],
[
57
],
[
59,
61
],
[
63
],
[
65
],
[
69,
71
],
[
75
],
[
77
],
[
79
],
[
81
],
[
85
],
[
87
],
[
89
],
[
91
],
[
93
],
[
97
],
[
99
],
[
101
],
[
103
],
[
105
],
[
107
],
[
111
],
[
113
],
[
115,
117
],
[
119
],
[
121
],
[
125
],
[
127,
129
],
[
131
],
[
133
],
[
135
],
[
139
],
[
143
],
[
145,
147
],
[
149,
151
],
[
153,
155
],
[
157
],
[
161
],
[
163
],
[
165
],
[
167
],
[
171,
173
],
[
179
],
[
181
],
[
185,
187
],
[
191
],
[
193
]
]
|
10,270 | void framebuffer_update_display(
DisplaySurface *ds,
MemoryRegion *address_space,
hwaddr base,
int cols, /* Width in pixels. */
int rows, /* Height in pixels. */
int src_width, /* Length of source line, in bytes. */
int dest_row_pitch, /* Bytes between adjacent horizontal output pixels. */
int dest_col_pitch, /* Bytes between adjacent vertical output pixels. */
int invalidate, /* nonzero to redraw the whole image. */
drawfn fn,
void *opaque,
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
hwaddr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int first, last = 0;
int dirty;
int i;
ram_addr_t addr;
MemoryRegionSection mem_section;
MemoryRegion *mem;
i = *first_row;
*first_row = -1;
src_len = src_width * rows;
mem_section = memory_region_find(address_space, base, src_len);
if (int128_get64(mem_section.size) != src_len ||
!memory_region_is_ram(mem_section.mr)) {
return;
}
mem = mem_section.mr;
assert(mem);
assert(mem_section.offset_within_address_space == base);
memory_region_sync_dirty_bitmap(mem);
src_base = cpu_physical_memory_map(base, &src_len, 0);
/* If we can't map the framebuffer then bail. We could try harder,
but it's not really worth it as dirty flag tracking will probably
already have failed above. */
if (!src_base)
return;
if (src_len != src_width * rows) {
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
return;
}
src = src_base;
dest = surface_data(ds);
if (dest_col_pitch < 0)
dest -= dest_col_pitch * (cols - 1);
if (dest_row_pitch < 0) {
dest -= dest_row_pitch * (rows - 1);
}
first = -1;
addr = mem_section.offset_within_region;
addr += i * src_width;
src += i * src_width;
dest += i * dest_row_pitch;
for (; i < rows; i++) {
dirty = memory_region_get_dirty(mem, addr, src_width,
DIRTY_MEMORY_VGA);
if (dirty || invalidate) {
fn(opaque, dest, src, cols, dest_col_pitch);
if (first == -1)
first = i;
last = i;
}
addr += src_width;
src += src_width;
dest += dest_row_pitch;
}
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
if (first < 0) {
return;
}
memory_region_reset_dirty(mem, mem_section.offset_within_region, src_len,
DIRTY_MEMORY_VGA);
*first_row = first;
*last_row = last;
}
| false | qemu | dfde4e6e1a868f60033ece0590b1f75e6c57fa16 | void framebuffer_update_display(
DisplaySurface *ds,
MemoryRegion *address_space,
hwaddr base,
int cols,
int rows,
int src_width,
int dest_row_pitch,
int dest_col_pitch,
int invalidate,
drawfn fn,
void *opaque,
int *first_row,
int *last_row )
{
hwaddr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int first, last = 0;
int dirty;
int i;
ram_addr_t addr;
MemoryRegionSection mem_section;
MemoryRegion *mem;
i = *first_row;
*first_row = -1;
src_len = src_width * rows;
mem_section = memory_region_find(address_space, base, src_len);
if (int128_get64(mem_section.size) != src_len ||
!memory_region_is_ram(mem_section.mr)) {
return;
}
mem = mem_section.mr;
assert(mem);
assert(mem_section.offset_within_address_space == base);
memory_region_sync_dirty_bitmap(mem);
src_base = cpu_physical_memory_map(base, &src_len, 0);
if (!src_base)
return;
if (src_len != src_width * rows) {
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
return;
}
src = src_base;
dest = surface_data(ds);
if (dest_col_pitch < 0)
dest -= dest_col_pitch * (cols - 1);
if (dest_row_pitch < 0) {
dest -= dest_row_pitch * (rows - 1);
}
first = -1;
addr = mem_section.offset_within_region;
addr += i * src_width;
src += i * src_width;
dest += i * dest_row_pitch;
for (; i < rows; i++) {
dirty = memory_region_get_dirty(mem, addr, src_width,
DIRTY_MEMORY_VGA);
if (dirty || invalidate) {
fn(opaque, dest, src, cols, dest_col_pitch);
if (first == -1)
first = i;
last = i;
}
addr += src_width;
src += src_width;
dest += dest_row_pitch;
}
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
if (first < 0) {
return;
}
memory_region_reset_dirty(mem, mem_section.offset_within_region, src_len,
DIRTY_MEMORY_VGA);
*first_row = first;
*last_row = last;
}
| {
"code": [],
"line_no": []
} | void FUNC_0(
DisplaySurface *VAR_0,
MemoryRegion *VAR_1,
hwaddr VAR_2,
int VAR_3,
int VAR_4,
int VAR_5,
int VAR_6,
int VAR_7,
int VAR_8,
drawfn VAR_9,
void *VAR_10,
int *VAR_11,
int *VAR_12 )
{
hwaddr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int VAR_13, VAR_14 = 0;
int VAR_15;
int VAR_16;
ram_addr_t addr;
MemoryRegionSection mem_section;
MemoryRegion *mem;
VAR_16 = *VAR_11;
*VAR_11 = -1;
src_len = VAR_5 * VAR_4;
mem_section = memory_region_find(VAR_1, VAR_2, src_len);
if (int128_get64(mem_section.size) != src_len ||
!memory_region_is_ram(mem_section.mr)) {
return;
}
mem = mem_section.mr;
assert(mem);
assert(mem_section.offset_within_address_space == VAR_2);
memory_region_sync_dirty_bitmap(mem);
src_base = cpu_physical_memory_map(VAR_2, &src_len, 0);
if (!src_base)
return;
if (src_len != VAR_5 * VAR_4) {
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
return;
}
src = src_base;
dest = surface_data(VAR_0);
if (VAR_7 < 0)
dest -= VAR_7 * (VAR_3 - 1);
if (VAR_6 < 0) {
dest -= VAR_6 * (VAR_4 - 1);
}
VAR_13 = -1;
addr = mem_section.offset_within_region;
addr += VAR_16 * VAR_5;
src += VAR_16 * VAR_5;
dest += VAR_16 * VAR_6;
for (; VAR_16 < VAR_4; VAR_16++) {
VAR_15 = memory_region_get_dirty(mem, addr, VAR_5,
DIRTY_MEMORY_VGA);
if (VAR_15 || VAR_8) {
VAR_9(VAR_10, dest, src, VAR_3, VAR_7);
if (VAR_13 == -1)
VAR_13 = VAR_16;
VAR_14 = VAR_16;
}
addr += VAR_5;
src += VAR_5;
dest += VAR_6;
}
cpu_physical_memory_unmap(src_base, src_len, 0, 0);
if (VAR_13 < 0) {
return;
}
memory_region_reset_dirty(mem, mem_section.offset_within_region, src_len,
DIRTY_MEMORY_VGA);
*VAR_11 = VAR_13;
*VAR_12 = VAR_14;
}
| [
"void FUNC_0(\nDisplaySurface *VAR_0,\nMemoryRegion *VAR_1,\nhwaddr VAR_2,\nint VAR_3,\nint VAR_4,\nint VAR_5,\nint VAR_6,\nint VAR_7,\nint VAR_8,\ndrawfn VAR_9,\nvoid *VAR_10,\nint *VAR_11,\nint *VAR_12 )\n{",
"hwaddr src_len;",
"uint8_t *dest;",
"uint8_t *src;",
"uint8_t *src_base;",
"int VAR_13, VAR_14 = 0;",
"int VAR_15;",
"int VAR_16;",
"ram_addr_t addr;",
"MemoryRegionSection mem_section;",
"MemoryRegion *mem;",
"VAR_16 = *VAR_11;",
"*VAR_11 = -1;",
"src_len = VAR_5 * VAR_4;",
"mem_section = memory_region_find(VAR_1, VAR_2, src_len);",
"if (int128_get64(mem_section.size) != src_len ||\n!memory_region_is_ram(mem_section.mr)) {",
"return;",
"}",
"mem = mem_section.mr;",
"assert(mem);",
"assert(mem_section.offset_within_address_space == VAR_2);",
"memory_region_sync_dirty_bitmap(mem);",
"src_base = cpu_physical_memory_map(VAR_2, &src_len, 0);",
"if (!src_base)\nreturn;",
"if (src_len != VAR_5 * VAR_4) {",
"cpu_physical_memory_unmap(src_base, src_len, 0, 0);",
"return;",
"}",
"src = src_base;",
"dest = surface_data(VAR_0);",
"if (VAR_7 < 0)\ndest -= VAR_7 * (VAR_3 - 1);",
"if (VAR_6 < 0) {",
"dest -= VAR_6 * (VAR_4 - 1);",
"}",
"VAR_13 = -1;",
"addr = mem_section.offset_within_region;",
"addr += VAR_16 * VAR_5;",
"src += VAR_16 * VAR_5;",
"dest += VAR_16 * VAR_6;",
"for (; VAR_16 < VAR_4; VAR_16++) {",
"VAR_15 = memory_region_get_dirty(mem, addr, VAR_5,\nDIRTY_MEMORY_VGA);",
"if (VAR_15 || VAR_8) {",
"VAR_9(VAR_10, dest, src, VAR_3, VAR_7);",
"if (VAR_13 == -1)\nVAR_13 = VAR_16;",
"VAR_14 = VAR_16;",
"}",
"addr += VAR_5;",
"src += VAR_5;",
"dest += VAR_6;",
"}",
"cpu_physical_memory_unmap(src_base, src_len, 0, 0);",
"if (VAR_13 < 0) {",
"return;",
"}",
"memory_region_reset_dirty(mem, mem_section.offset_within_region, src_len,\nDIRTY_MEMORY_VGA);",
"*VAR_11 = VAR_13;",
"*VAR_12 = VAR_14;",
"}"
]
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[
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[
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[
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[
53
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[
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[
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[
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[
63,
65
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[
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[
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[
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[
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[
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[
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[
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[
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[
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[
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[
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[
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107
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[
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[
113
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[
115
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[
117
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[
121
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[
123
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[
125
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[
129
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[
131,
133
],
[
135
],
[
137
],
[
139,
141
],
[
143
],
[
145
],
[
147
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[
149
],
[
151
],
[
153
],
[
155
],
[
157
],
[
159
],
[
161
],
[
163,
165
],
[
167
],
[
169
],
[
171
]
]
|
10,271 | void tcg_region_reset_all(void)
{
unsigned int i;
qemu_mutex_lock(®ion.lock);
region.current = 0;
region.agg_size_full = 0;
for (i = 0; i < n_tcg_ctxs; i++) {
bool err = tcg_region_initial_alloc__locked(tcg_ctxs[i]);
g_assert(!err);
}
qemu_mutex_unlock(®ion.lock);
}
| false | qemu | 3468b59e18b179bc63c7ce934de912dfa9596122 | void tcg_region_reset_all(void)
{
unsigned int i;
qemu_mutex_lock(®ion.lock);
region.current = 0;
region.agg_size_full = 0;
for (i = 0; i < n_tcg_ctxs; i++) {
bool err = tcg_region_initial_alloc__locked(tcg_ctxs[i]);
g_assert(!err);
}
qemu_mutex_unlock(®ion.lock);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(void)
{
unsigned int VAR_0;
qemu_mutex_lock(®ion.lock);
region.current = 0;
region.agg_size_full = 0;
for (VAR_0 = 0; VAR_0 < n_tcg_ctxs; VAR_0++) {
bool err = tcg_region_initial_alloc__locked(tcg_ctxs[VAR_0]);
g_assert(!err);
}
qemu_mutex_unlock(®ion.lock);
}
| [
"void FUNC_0(void)\n{",
"unsigned int VAR_0;",
"qemu_mutex_lock(®ion.lock);",
"region.current = 0;",
"region.agg_size_full = 0;",
"for (VAR_0 = 0; VAR_0 < n_tcg_ctxs; VAR_0++) {",
"bool err = tcg_region_initial_alloc__locked(tcg_ctxs[VAR_0]);",
"g_assert(!err);",
"}",
"qemu_mutex_unlock(®ion.lock);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
17
],
[
19
],
[
23
],
[
25
],
[
27
],
[
29
]
]
|
10,272 | static int parse_args(int argc, char **argv)
{
const char *r;
int optind;
struct qemu_argument *arginfo;
for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
if (arginfo->env == NULL) {
continue;
}
r = getenv(arginfo->env);
if (r != NULL) {
arginfo->handle_opt(r);
}
}
optind = 1;
for (;;) {
if (optind >= argc) {
break;
}
r = argv[optind];
if (r[0] != '-') {
break;
}
optind++;
r++;
if (!strcmp(r, "-")) {
break;
}
for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
if (!strcmp(r, arginfo->argv)) {
if (optind >= argc) {
usage();
}
arginfo->handle_opt(argv[optind]);
if (arginfo->has_arg) {
optind++;
}
break;
}
}
/* no option matched the current argv */
if (arginfo->handle_opt == NULL) {
usage();
}
}
if (optind >= argc) {
usage();
}
filename = argv[optind];
exec_path = argv[optind];
return optind;
}
| false | qemu | 1386d4c0f5ce4c4391f2024a36c77eb8fb152e90 | static int parse_args(int argc, char **argv)
{
const char *r;
int optind;
struct qemu_argument *arginfo;
for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
if (arginfo->env == NULL) {
continue;
}
r = getenv(arginfo->env);
if (r != NULL) {
arginfo->handle_opt(r);
}
}
optind = 1;
for (;;) {
if (optind >= argc) {
break;
}
r = argv[optind];
if (r[0] != '-') {
break;
}
optind++;
r++;
if (!strcmp(r, "-")) {
break;
}
for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
if (!strcmp(r, arginfo->argv)) {
if (optind >= argc) {
usage();
}
arginfo->handle_opt(argv[optind]);
if (arginfo->has_arg) {
optind++;
}
break;
}
}
if (arginfo->handle_opt == NULL) {
usage();
}
}
if (optind >= argc) {
usage();
}
filename = argv[optind];
exec_path = argv[optind];
return optind;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(int VAR_0, char **VAR_1)
{
const char *VAR_2;
int VAR_3;
struct qemu_argument *VAR_4;
for (VAR_4 = arg_table; VAR_4->handle_opt != NULL; VAR_4++) {
if (VAR_4->env == NULL) {
continue;
}
VAR_2 = getenv(VAR_4->env);
if (VAR_2 != NULL) {
VAR_4->handle_opt(VAR_2);
}
}
VAR_3 = 1;
for (;;) {
if (VAR_3 >= VAR_0) {
break;
}
VAR_2 = VAR_1[VAR_3];
if (VAR_2[0] != '-') {
break;
}
VAR_3++;
VAR_2++;
if (!strcmp(VAR_2, "-")) {
break;
}
for (VAR_4 = arg_table; VAR_4->handle_opt != NULL; VAR_4++) {
if (!strcmp(VAR_2, VAR_4->VAR_1)) {
if (VAR_3 >= VAR_0) {
usage();
}
VAR_4->handle_opt(VAR_1[VAR_3]);
if (VAR_4->has_arg) {
VAR_3++;
}
break;
}
}
if (VAR_4->handle_opt == NULL) {
usage();
}
}
if (VAR_3 >= VAR_0) {
usage();
}
filename = VAR_1[VAR_3];
exec_path = VAR_1[VAR_3];
return VAR_3;
}
| [
"static int FUNC_0(int VAR_0, char **VAR_1)\n{",
"const char *VAR_2;",
"int VAR_3;",
"struct qemu_argument *VAR_4;",
"for (VAR_4 = arg_table; VAR_4->handle_opt != NULL; VAR_4++) {",
"if (VAR_4->env == NULL) {",
"continue;",
"}",
"VAR_2 = getenv(VAR_4->env);",
"if (VAR_2 != NULL) {",
"VAR_4->handle_opt(VAR_2);",
"}",
"}",
"VAR_3 = 1;",
"for (;;) {",
"if (VAR_3 >= VAR_0) {",
"break;",
"}",
"VAR_2 = VAR_1[VAR_3];",
"if (VAR_2[0] != '-') {",
"break;",
"}",
"VAR_3++;",
"VAR_2++;",
"if (!strcmp(VAR_2, \"-\")) {",
"break;",
"}",
"for (VAR_4 = arg_table; VAR_4->handle_opt != NULL; VAR_4++) {",
"if (!strcmp(VAR_2, VAR_4->VAR_1)) {",
"if (VAR_3 >= VAR_0) {",
"usage();",
"}",
"VAR_4->handle_opt(VAR_1[VAR_3]);",
"if (VAR_4->has_arg) {",
"VAR_3++;",
"}",
"break;",
"}",
"}",
"if (VAR_4->handle_opt == NULL) {",
"usage();",
"}",
"}",
"if (VAR_3 >= VAR_0) {",
"usage();",
"}",
"filename = VAR_1[VAR_3];",
"exec_path = VAR_1[VAR_3];",
"return VAR_3;",
"}"
]
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[
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[
85
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[
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[
103
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[
105
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[
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[
111
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[
113
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[
117
],
[
119
],
[
123
],
[
125
]
]
|
10,273 | void cpu_loop(CPUOpenRISCState *env)
{
CPUState *cs = CPU(openrisc_env_get_cpu(env));
int trapnr, gdbsig;
for (;;) {
cpu_exec_start(cs);
trapnr = cpu_openrisc_exec(cs);
cpu_exec_end(cs);
gdbsig = 0;
switch (trapnr) {
case EXCP_RESET:
qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
exit(EXIT_FAILURE);
break;
case EXCP_BUSERR:
qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
gdbsig = TARGET_SIGBUS;
break;
case EXCP_DPF:
case EXCP_IPF:
cpu_dump_state(cs, stderr, fprintf, 0);
gdbsig = TARGET_SIGSEGV;
break;
case EXCP_TICK:
qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
break;
case EXCP_ALIGN:
qemu_log("\nAlignment pc is %#x\n", env->pc);
gdbsig = TARGET_SIGBUS;
break;
case EXCP_ILLEGAL:
qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
gdbsig = TARGET_SIGILL;
break;
case EXCP_INT:
qemu_log("\nExternal interruptpc is %#x\n", env->pc);
break;
case EXCP_DTLBMISS:
case EXCP_ITLBMISS:
qemu_log("\nTLB miss\n");
break;
case EXCP_RANGE:
qemu_log("\nRange\n");
gdbsig = TARGET_SIGSEGV;
break;
case EXCP_SYSCALL:
env->pc += 4; /* 0xc00; */
env->gpr[11] = do_syscall(env,
env->gpr[11], /* return value */
env->gpr[3], /* r3 - r7 are params */
env->gpr[4],
env->gpr[5],
env->gpr[6],
env->gpr[7],
env->gpr[8], 0, 0);
break;
case EXCP_FPE:
qemu_log("\nFloating point error\n");
break;
case EXCP_TRAP:
qemu_log("\nTrap\n");
gdbsig = TARGET_SIGTRAP;
break;
case EXCP_NR:
qemu_log("\nNR\n");
break;
default:
qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
gdbsig = TARGET_SIGILL;
break;
}
if (gdbsig) {
gdb_handlesig(cs, gdbsig);
if (gdbsig != TARGET_SIGTRAP) {
exit(EXIT_FAILURE);
}
}
process_pending_signals(env);
}
}
| false | qemu | 120a9848c2f667bf8f1a06772dc9cde064d92a7d | void cpu_loop(CPUOpenRISCState *env)
{
CPUState *cs = CPU(openrisc_env_get_cpu(env));
int trapnr, gdbsig;
for (;;) {
cpu_exec_start(cs);
trapnr = cpu_openrisc_exec(cs);
cpu_exec_end(cs);
gdbsig = 0;
switch (trapnr) {
case EXCP_RESET:
qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
exit(EXIT_FAILURE);
break;
case EXCP_BUSERR:
qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
gdbsig = TARGET_SIGBUS;
break;
case EXCP_DPF:
case EXCP_IPF:
cpu_dump_state(cs, stderr, fprintf, 0);
gdbsig = TARGET_SIGSEGV;
break;
case EXCP_TICK:
qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
break;
case EXCP_ALIGN:
qemu_log("\nAlignment pc is %#x\n", env->pc);
gdbsig = TARGET_SIGBUS;
break;
case EXCP_ILLEGAL:
qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
gdbsig = TARGET_SIGILL;
break;
case EXCP_INT:
qemu_log("\nExternal interruptpc is %#x\n", env->pc);
break;
case EXCP_DTLBMISS:
case EXCP_ITLBMISS:
qemu_log("\nTLB miss\n");
break;
case EXCP_RANGE:
qemu_log("\nRange\n");
gdbsig = TARGET_SIGSEGV;
break;
case EXCP_SYSCALL:
env->pc += 4;
env->gpr[11] = do_syscall(env,
env->gpr[11],
env->gpr[3],
env->gpr[4],
env->gpr[5],
env->gpr[6],
env->gpr[7],
env->gpr[8], 0, 0);
break;
case EXCP_FPE:
qemu_log("\nFloating point error\n");
break;
case EXCP_TRAP:
qemu_log("\nTrap\n");
gdbsig = TARGET_SIGTRAP;
break;
case EXCP_NR:
qemu_log("\nNR\n");
break;
default:
qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
trapnr);
cpu_dump_state(cs, stderr, fprintf, 0);
gdbsig = TARGET_SIGILL;
break;
}
if (gdbsig) {
gdb_handlesig(cs, gdbsig);
if (gdbsig != TARGET_SIGTRAP) {
exit(EXIT_FAILURE);
}
}
process_pending_signals(env);
}
}
| {
"code": [],
"line_no": []
} | void FUNC_0(CPUOpenRISCState *VAR_0)
{
CPUState *cs = CPU(openrisc_env_get_cpu(VAR_0));
int VAR_1, VAR_2;
for (;;) {
cpu_exec_start(cs);
VAR_1 = cpu_openrisc_exec(cs);
cpu_exec_end(cs);
VAR_2 = 0;
switch (VAR_1) {
case EXCP_RESET:
qemu_log("\nReset request, exit, pc is %#x\n", VAR_0->pc);
exit(EXIT_FAILURE);
break;
case EXCP_BUSERR:
qemu_log("\nBus error, exit, pc is %#x\n", VAR_0->pc);
VAR_2 = TARGET_SIGBUS;
break;
case EXCP_DPF:
case EXCP_IPF:
cpu_dump_state(cs, stderr, fprintf, 0);
VAR_2 = TARGET_SIGSEGV;
break;
case EXCP_TICK:
qemu_log("\nTick time interrupt pc is %#x\n", VAR_0->pc);
break;
case EXCP_ALIGN:
qemu_log("\nAlignment pc is %#x\n", VAR_0->pc);
VAR_2 = TARGET_SIGBUS;
break;
case EXCP_ILLEGAL:
qemu_log("\nIllegal instructionpc is %#x\n", VAR_0->pc);
VAR_2 = TARGET_SIGILL;
break;
case EXCP_INT:
qemu_log("\nExternal interruptpc is %#x\n", VAR_0->pc);
break;
case EXCP_DTLBMISS:
case EXCP_ITLBMISS:
qemu_log("\nTLB miss\n");
break;
case EXCP_RANGE:
qemu_log("\nRange\n");
VAR_2 = TARGET_SIGSEGV;
break;
case EXCP_SYSCALL:
VAR_0->pc += 4;
VAR_0->gpr[11] = do_syscall(VAR_0,
VAR_0->gpr[11],
VAR_0->gpr[3],
VAR_0->gpr[4],
VAR_0->gpr[5],
VAR_0->gpr[6],
VAR_0->gpr[7],
VAR_0->gpr[8], 0, 0);
break;
case EXCP_FPE:
qemu_log("\nFloating point error\n");
break;
case EXCP_TRAP:
qemu_log("\nTrap\n");
VAR_2 = TARGET_SIGTRAP;
break;
case EXCP_NR:
qemu_log("\nNR\n");
break;
default:
qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
VAR_1);
cpu_dump_state(cs, stderr, fprintf, 0);
VAR_2 = TARGET_SIGILL;
break;
}
if (VAR_2) {
gdb_handlesig(cs, VAR_2);
if (VAR_2 != TARGET_SIGTRAP) {
exit(EXIT_FAILURE);
}
}
process_pending_signals(VAR_0);
}
}
| [
"void FUNC_0(CPUOpenRISCState *VAR_0)\n{",
"CPUState *cs = CPU(openrisc_env_get_cpu(VAR_0));",
"int VAR_1, VAR_2;",
"for (;;) {",
"cpu_exec_start(cs);",
"VAR_1 = cpu_openrisc_exec(cs);",
"cpu_exec_end(cs);",
"VAR_2 = 0;",
"switch (VAR_1) {",
"case EXCP_RESET:\nqemu_log(\"\\nReset request, exit, pc is %#x\\n\", VAR_0->pc);",
"exit(EXIT_FAILURE);",
"break;",
"case EXCP_BUSERR:\nqemu_log(\"\\nBus error, exit, pc is %#x\\n\", VAR_0->pc);",
"VAR_2 = TARGET_SIGBUS;",
"break;",
"case EXCP_DPF:\ncase EXCP_IPF:\ncpu_dump_state(cs, stderr, fprintf, 0);",
"VAR_2 = TARGET_SIGSEGV;",
"break;",
"case EXCP_TICK:\nqemu_log(\"\\nTick time interrupt pc is %#x\\n\", VAR_0->pc);",
"break;",
"case EXCP_ALIGN:\nqemu_log(\"\\nAlignment pc is %#x\\n\", VAR_0->pc);",
"VAR_2 = TARGET_SIGBUS;",
"break;",
"case EXCP_ILLEGAL:\nqemu_log(\"\\nIllegal instructionpc is %#x\\n\", VAR_0->pc);",
"VAR_2 = TARGET_SIGILL;",
"break;",
"case EXCP_INT:\nqemu_log(\"\\nExternal interruptpc is %#x\\n\", VAR_0->pc);",
"break;",
"case EXCP_DTLBMISS:\ncase EXCP_ITLBMISS:\nqemu_log(\"\\nTLB miss\\n\");",
"break;",
"case EXCP_RANGE:\nqemu_log(\"\\nRange\\n\");",
"VAR_2 = TARGET_SIGSEGV;",
"break;",
"case EXCP_SYSCALL:\nVAR_0->pc += 4;",
"VAR_0->gpr[11] = do_syscall(VAR_0,\nVAR_0->gpr[11],\nVAR_0->gpr[3],\nVAR_0->gpr[4],\nVAR_0->gpr[5],\nVAR_0->gpr[6],\nVAR_0->gpr[7],\nVAR_0->gpr[8], 0, 0);",
"break;",
"case EXCP_FPE:\nqemu_log(\"\\nFloating point error\\n\");",
"break;",
"case EXCP_TRAP:\nqemu_log(\"\\nTrap\\n\");",
"VAR_2 = TARGET_SIGTRAP;",
"break;",
"case EXCP_NR:\nqemu_log(\"\\nNR\\n\");",
"break;",
"default:\nqemu_log(\"\\nqemu: unhandled CPU exception %#x - aborting\\n\",\nVAR_1);",
"cpu_dump_state(cs, stderr, fprintf, 0);",
"VAR_2 = TARGET_SIGILL;",
"break;",
"}",
"if (VAR_2) {",
"gdb_handlesig(cs, VAR_2);",
"if (VAR_2 != TARGET_SIGTRAP) {",
"exit(EXIT_FAILURE);",
"}",
"}",
"process_pending_signals(VAR_0);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
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[
1,
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[
5
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[
7
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[
11
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[
13
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[
15
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[
17
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[
19
],
[
23
],
[
25,
27
],
[
29
],
[
31
],
[
33,
35
],
[
37
],
[
39
],
[
41,
43,
45
],
[
47
],
[
49
],
[
51,
53
],
[
55
],
[
57,
59
],
[
61
],
[
63
],
[
65,
67
],
[
69
],
[
71
],
[
73,
75
],
[
77
],
[
79,
81,
83
],
[
85
],
[
87,
89
],
[
91
],
[
93
],
[
95,
97
],
[
99,
101,
103,
105,
107,
109,
111,
113
],
[
115
],
[
117,
119
],
[
121
],
[
123,
125
],
[
127
],
[
129
],
[
131,
133
],
[
135
],
[
137,
139,
141
],
[
143
],
[
145
],
[
147
],
[
149
],
[
151
],
[
153
],
[
155
],
[
157
],
[
159
],
[
161
],
[
165
],
[
167
],
[
169
]
]
|
10,275 | void msix_save(PCIDevice *dev, QEMUFile *f)
{
unsigned n = dev->msix_entries_nr;
if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
return;
}
qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}
| false | qemu | 44701ab71ad854e6be567a6294f4665f36651076 | void msix_save(PCIDevice *dev, QEMUFile *f)
{
unsigned n = dev->msix_entries_nr;
if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
return;
}
qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(PCIDevice *VAR_0, QEMUFile *VAR_1)
{
unsigned VAR_2 = VAR_0->msix_entries_nr;
if (!(VAR_0->cap_present & QEMU_PCI_CAP_MSIX)) {
return;
}
qemu_put_buffer(VAR_1, VAR_0->msix_table_page, VAR_2 * PCI_MSIX_ENTRY_SIZE);
qemu_put_buffer(VAR_1, VAR_0->msix_table_page + MSIX_PAGE_PENDING, (VAR_2 + 7) / 8);
}
| [
"void FUNC_0(PCIDevice *VAR_0, QEMUFile *VAR_1)\n{",
"unsigned VAR_2 = VAR_0->msix_entries_nr;",
"if (!(VAR_0->cap_present & QEMU_PCI_CAP_MSIX)) {",
"return;",
"}",
"qemu_put_buffer(VAR_1, VAR_0->msix_table_page, VAR_2 * PCI_MSIX_ENTRY_SIZE);",
"qemu_put_buffer(VAR_1, VAR_0->msix_table_page + MSIX_PAGE_PENDING, (VAR_2 + 7) / 8);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
17
],
[
19
],
[
21
]
]
|
10,276 | int qsv_init(AVCodecContext *s)
{
InputStream *ist = s->opaque;
QSVContext *qsv = ist->hwaccel_ctx;
AVQSVContext *hwctx_dec;
int ret;
if (!qsv) {
av_log(NULL, AV_LOG_ERROR, "QSV transcoding is not initialized. "
"-hwaccel qsv should only be used for one-to-one QSV transcoding "
"with no filters.\n");
return AVERROR_BUG;
}
ret = init_opaque_surf(qsv);
if (ret < 0)
return ret;
hwctx_dec = av_qsv_alloc_context();
if (!hwctx_dec)
return AVERROR(ENOMEM);
hwctx_dec->session = qsv->session;
hwctx_dec->iopattern = MFX_IOPATTERN_OUT_OPAQUE_MEMORY;
hwctx_dec->ext_buffers = qsv->ext_buffers;
hwctx_dec->nb_ext_buffers = FF_ARRAY_ELEMS(qsv->ext_buffers);
av_freep(&s->hwaccel_context);
s->hwaccel_context = hwctx_dec;
ist->hwaccel_get_buffer = qsv_get_buffer;
ist->hwaccel_uninit = qsv_uninit;
return 0;
}
| false | FFmpeg | 03cef34aa66662e2ab3681d290e7c5a6634f4058 | int qsv_init(AVCodecContext *s)
{
InputStream *ist = s->opaque;
QSVContext *qsv = ist->hwaccel_ctx;
AVQSVContext *hwctx_dec;
int ret;
if (!qsv) {
av_log(NULL, AV_LOG_ERROR, "QSV transcoding is not initialized. "
"-hwaccel qsv should only be used for one-to-one QSV transcoding "
"with no filters.\n");
return AVERROR_BUG;
}
ret = init_opaque_surf(qsv);
if (ret < 0)
return ret;
hwctx_dec = av_qsv_alloc_context();
if (!hwctx_dec)
return AVERROR(ENOMEM);
hwctx_dec->session = qsv->session;
hwctx_dec->iopattern = MFX_IOPATTERN_OUT_OPAQUE_MEMORY;
hwctx_dec->ext_buffers = qsv->ext_buffers;
hwctx_dec->nb_ext_buffers = FF_ARRAY_ELEMS(qsv->ext_buffers);
av_freep(&s->hwaccel_context);
s->hwaccel_context = hwctx_dec;
ist->hwaccel_get_buffer = qsv_get_buffer;
ist->hwaccel_uninit = qsv_uninit;
return 0;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(AVCodecContext *VAR_0)
{
InputStream *ist = VAR_0->opaque;
QSVContext *qsv = ist->hwaccel_ctx;
AVQSVContext *hwctx_dec;
int VAR_1;
if (!qsv) {
av_log(NULL, AV_LOG_ERROR, "QSV transcoding is not initialized. "
"-hwaccel qsv should only be used for one-to-one QSV transcoding "
"with no filters.\n");
return AVERROR_BUG;
}
VAR_1 = init_opaque_surf(qsv);
if (VAR_1 < 0)
return VAR_1;
hwctx_dec = av_qsv_alloc_context();
if (!hwctx_dec)
return AVERROR(ENOMEM);
hwctx_dec->session = qsv->session;
hwctx_dec->iopattern = MFX_IOPATTERN_OUT_OPAQUE_MEMORY;
hwctx_dec->ext_buffers = qsv->ext_buffers;
hwctx_dec->nb_ext_buffers = FF_ARRAY_ELEMS(qsv->ext_buffers);
av_freep(&VAR_0->hwaccel_context);
VAR_0->hwaccel_context = hwctx_dec;
ist->hwaccel_get_buffer = qsv_get_buffer;
ist->hwaccel_uninit = qsv_uninit;
return 0;
}
| [
"int FUNC_0(AVCodecContext *VAR_0)\n{",
"InputStream *ist = VAR_0->opaque;",
"QSVContext *qsv = ist->hwaccel_ctx;",
"AVQSVContext *hwctx_dec;",
"int VAR_1;",
"if (!qsv) {",
"av_log(NULL, AV_LOG_ERROR, \"QSV transcoding is not initialized. \"\n\"-hwaccel qsv should only be used for one-to-one QSV transcoding \"\n\"with no filters.\\n\");",
"return AVERROR_BUG;",
"}",
"VAR_1 = init_opaque_surf(qsv);",
"if (VAR_1 < 0)\nreturn VAR_1;",
"hwctx_dec = av_qsv_alloc_context();",
"if (!hwctx_dec)\nreturn AVERROR(ENOMEM);",
"hwctx_dec->session = qsv->session;",
"hwctx_dec->iopattern = MFX_IOPATTERN_OUT_OPAQUE_MEMORY;",
"hwctx_dec->ext_buffers = qsv->ext_buffers;",
"hwctx_dec->nb_ext_buffers = FF_ARRAY_ELEMS(qsv->ext_buffers);",
"av_freep(&VAR_0->hwaccel_context);",
"VAR_0->hwaccel_context = hwctx_dec;",
"ist->hwaccel_get_buffer = qsv_get_buffer;",
"ist->hwaccel_uninit = qsv_uninit;",
"return 0;",
"}"
]
| [
0,
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0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17,
19,
21
],
[
23
],
[
25
],
[
29
],
[
31,
33
],
[
37
],
[
39,
41
],
[
45
],
[
47
],
[
49
],
[
51
],
[
55
],
[
57
],
[
61
],
[
63
],
[
67
],
[
69
]
]
|
10,277 | static void default_drive(int enable, int snapshot, int use_scsi,
BlockInterfaceType type, int index,
const char *optstr)
{
QemuOpts *opts;
if (type == IF_DEFAULT) {
type = use_scsi ? IF_SCSI : IF_IDE;
}
if (!enable || drive_get_by_index(type, index)) {
return;
}
opts = drive_add(type, index, NULL, optstr);
if (snapshot) {
drive_enable_snapshot(opts, NULL);
}
if (!drive_init(opts, use_scsi)) {
exit(1);
}
}
| false | qemu | 2d0d2837dcf786da415cf4165d37f4ddd684ff57 | static void default_drive(int enable, int snapshot, int use_scsi,
BlockInterfaceType type, int index,
const char *optstr)
{
QemuOpts *opts;
if (type == IF_DEFAULT) {
type = use_scsi ? IF_SCSI : IF_IDE;
}
if (!enable || drive_get_by_index(type, index)) {
return;
}
opts = drive_add(type, index, NULL, optstr);
if (snapshot) {
drive_enable_snapshot(opts, NULL);
}
if (!drive_init(opts, use_scsi)) {
exit(1);
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(int VAR_0, int VAR_1, int VAR_2,
BlockInterfaceType VAR_3, int VAR_4,
const char *VAR_5)
{
QemuOpts *opts;
if (VAR_3 == IF_DEFAULT) {
VAR_3 = VAR_2 ? IF_SCSI : IF_IDE;
}
if (!VAR_0 || drive_get_by_index(VAR_3, VAR_4)) {
return;
}
opts = drive_add(VAR_3, VAR_4, NULL, VAR_5);
if (VAR_1) {
drive_enable_snapshot(opts, NULL);
}
if (!drive_init(opts, VAR_2)) {
exit(1);
}
}
| [
"static void FUNC_0(int VAR_0, int VAR_1, int VAR_2,\nBlockInterfaceType VAR_3, int VAR_4,\nconst char *VAR_5)\n{",
"QemuOpts *opts;",
"if (VAR_3 == IF_DEFAULT) {",
"VAR_3 = VAR_2 ? IF_SCSI : IF_IDE;",
"}",
"if (!VAR_0 || drive_get_by_index(VAR_3, VAR_4)) {",
"return;",
"}",
"opts = drive_add(VAR_3, VAR_4, NULL, VAR_5);",
"if (VAR_1) {",
"drive_enable_snapshot(opts, NULL);",
"}",
"if (!drive_init(opts, VAR_2)) {",
"exit(1);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0
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| [
[
1,
3,
5,
7
],
[
9
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
29
],
[
31
],
[
33
],
[
35
],
[
37
],
[
39
],
[
41
],
[
43
]
]
|
10,279 | void css_generate_css_crws(uint8_t cssid)
{
if (!channel_subsys.sei_pending) {
css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, cssid);
}
channel_subsys.sei_pending = true;
}
| false | qemu | 5c8d6f008c0555b54cf10550fa86199a2cfabbca | void css_generate_css_crws(uint8_t cssid)
{
if (!channel_subsys.sei_pending) {
css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, cssid);
}
channel_subsys.sei_pending = true;
}
| {
"code": [],
"line_no": []
} | void FUNC_0(uint8_t VAR_0)
{
if (!channel_subsys.sei_pending) {
css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, VAR_0);
}
channel_subsys.sei_pending = true;
}
| [
"void FUNC_0(uint8_t VAR_0)\n{",
"if (!channel_subsys.sei_pending) {",
"css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, VAR_0);",
"}",
"channel_subsys.sei_pending = true;",
"}"
]
| [
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
]
]
|
10,280 | int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque)
{
WaitObjects *w = &wait_objects;
if (w->num >= MAXIMUM_WAIT_OBJECTS)
return -1;
w->events[w->num] = handle;
w->func[w->num] = func;
w->opaque[w->num] = opaque;
w->num++;
return 0;
}
| false | qemu | d3b12f5dec4b27ebab58fb5797cb67bacced773b | int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque)
{
WaitObjects *w = &wait_objects;
if (w->num >= MAXIMUM_WAIT_OBJECTS)
return -1;
w->events[w->num] = handle;
w->func[w->num] = func;
w->opaque[w->num] = opaque;
w->num++;
return 0;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(HANDLE VAR_0, WaitObjectFunc *VAR_1, void *VAR_2)
{
WaitObjects *w = &wait_objects;
if (w->num >= MAXIMUM_WAIT_OBJECTS)
return -1;
w->events[w->num] = VAR_0;
w->VAR_1[w->num] = VAR_1;
w->VAR_2[w->num] = VAR_2;
w->num++;
return 0;
}
| [
"int FUNC_0(HANDLE VAR_0, WaitObjectFunc *VAR_1, void *VAR_2)\n{",
"WaitObjects *w = &wait_objects;",
"if (w->num >= MAXIMUM_WAIT_OBJECTS)\nreturn -1;",
"w->events[w->num] = VAR_0;",
"w->VAR_1[w->num] = VAR_1;",
"w->VAR_2[w->num] = VAR_2;",
"w->num++;",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9,
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
]
]
|
10,281 | static void scsi_device_unrealize(SCSIDevice *s, Error **errp)
{
SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);
if (sc->unrealize) {
sc->unrealize(s, errp);
}
}
| false | qemu | fb7b5c0df6e3c501973ce4d57eb2b1d4344a519d | static void scsi_device_unrealize(SCSIDevice *s, Error **errp)
{
SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);
if (sc->unrealize) {
sc->unrealize(s, errp);
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(SCSIDevice *VAR_0, Error **VAR_1)
{
SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(VAR_0);
if (sc->unrealize) {
sc->unrealize(VAR_0, VAR_1);
}
}
| [
"static void FUNC_0(SCSIDevice *VAR_0, Error **VAR_1)\n{",
"SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(VAR_0);",
"if (sc->unrealize) {",
"sc->unrealize(VAR_0, VAR_1);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
]
]
|
10,284 | void disas(FILE *out, void *code, unsigned long size)
{
unsigned long pc;
int count;
struct disassemble_info disasm_info;
int (*print_insn)(bfd_vma pc, disassemble_info *info);
INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);
disasm_info.buffer = code;
disasm_info.buffer_vma = (unsigned long)code;
disasm_info.buffer_length = size;
#ifdef HOST_WORDS_BIGENDIAN
disasm_info.endian = BFD_ENDIAN_BIG;
#else
disasm_info.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(__i386__)
disasm_info.mach = bfd_mach_i386_i386;
print_insn = print_insn_i386;
#elif defined(__x86_64__)
disasm_info.mach = bfd_mach_x86_64;
print_insn = print_insn_i386;
#elif defined(_ARCH_PPC)
print_insn = print_insn_ppc;
#elif defined(__alpha__)
print_insn = print_insn_alpha;
#elif defined(__sparc__)
print_insn = print_insn_sparc;
#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
disasm_info.mach = bfd_mach_sparc_v9b;
#endif
#elif defined(__arm__)
print_insn = print_insn_arm;
#elif defined(__MIPSEB__)
print_insn = print_insn_big_mips;
#elif defined(__MIPSEL__)
print_insn = print_insn_little_mips;
#elif defined(__m68k__)
print_insn = print_insn_m68k;
#elif defined(__s390__)
print_insn = print_insn_s390;
#elif defined(__hppa__)
print_insn = print_insn_hppa;
#elif defined(__ia64__)
print_insn = print_insn_ia64;
#else
fprintf(out, "0x%lx: Asm output not supported on this arch\n",
(long) code);
return;
#endif
for (pc = (unsigned long)code; size > 0; pc += count, size -= count) {
fprintf(out, "0x%08lx: ", pc);
#ifdef __arm__
/* since data is included in the code, it is better to
display code data too */
fprintf(out, "%08x ", (int)bfd_getl32((const bfd_byte *)pc));
#endif
count = print_insn(pc, &disasm_info);
fprintf(out, "\n");
if (count < 0)
break;
}
}
| false | qemu | 0f136d9e060ad879d0b840274ddfd1955e24fc10 | void disas(FILE *out, void *code, unsigned long size)
{
unsigned long pc;
int count;
struct disassemble_info disasm_info;
int (*print_insn)(bfd_vma pc, disassemble_info *info);
INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);
disasm_info.buffer = code;
disasm_info.buffer_vma = (unsigned long)code;
disasm_info.buffer_length = size;
#ifdef HOST_WORDS_BIGENDIAN
disasm_info.endian = BFD_ENDIAN_BIG;
#else
disasm_info.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(__i386__)
disasm_info.mach = bfd_mach_i386_i386;
print_insn = print_insn_i386;
#elif defined(__x86_64__)
disasm_info.mach = bfd_mach_x86_64;
print_insn = print_insn_i386;
#elif defined(_ARCH_PPC)
print_insn = print_insn_ppc;
#elif defined(__alpha__)
print_insn = print_insn_alpha;
#elif defined(__sparc__)
print_insn = print_insn_sparc;
#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
disasm_info.mach = bfd_mach_sparc_v9b;
#endif
#elif defined(__arm__)
print_insn = print_insn_arm;
#elif defined(__MIPSEB__)
print_insn = print_insn_big_mips;
#elif defined(__MIPSEL__)
print_insn = print_insn_little_mips;
#elif defined(__m68k__)
print_insn = print_insn_m68k;
#elif defined(__s390__)
print_insn = print_insn_s390;
#elif defined(__hppa__)
print_insn = print_insn_hppa;
#elif defined(__ia64__)
print_insn = print_insn_ia64;
#else
fprintf(out, "0x%lx: Asm output not supported on this arch\n",
(long) code);
return;
#endif
for (pc = (unsigned long)code; size > 0; pc += count, size -= count) {
fprintf(out, "0x%08lx: ", pc);
#ifdef __arm__
fprintf(out, "%08x ", (int)bfd_getl32((const bfd_byte *)pc));
#endif
count = print_insn(pc, &disasm_info);
fprintf(out, "\n");
if (count < 0)
break;
}
}
| {
"code": [],
"line_no": []
} | void FUNC_0(FILE *VAR_0, void *VAR_1, unsigned long VAR_2)
{
unsigned long VAR_7;
int VAR_4;
struct disassemble_info VAR_5;
int (*VAR_6)(bfd_vma VAR_7, disassemble_info *VAR_7);
INIT_DISASSEMBLE_INFO(VAR_5, VAR_0, fprintf);
VAR_5.buffer = VAR_1;
VAR_5.buffer_vma = (unsigned long)VAR_1;
VAR_5.buffer_length = VAR_2;
#ifdef HOST_WORDS_BIGENDIAN
VAR_5.endian = BFD_ENDIAN_BIG;
#else
VAR_5.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(__i386__)
VAR_5.mach = bfd_mach_i386_i386;
VAR_6 = print_insn_i386;
#elif defined(__x86_64__)
VAR_5.mach = bfd_mach_x86_64;
VAR_6 = print_insn_i386;
#elif defined(_ARCH_PPC)
VAR_6 = print_insn_ppc;
#elif defined(__alpha__)
VAR_6 = print_insn_alpha;
#elif defined(__sparc__)
VAR_6 = print_insn_sparc;
#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
VAR_5.mach = bfd_mach_sparc_v9b;
#endif
#elif defined(__arm__)
VAR_6 = print_insn_arm;
#elif defined(__MIPSEB__)
VAR_6 = print_insn_big_mips;
#elif defined(__MIPSEL__)
VAR_6 = print_insn_little_mips;
#elif defined(__m68k__)
VAR_6 = print_insn_m68k;
#elif defined(__s390__)
VAR_6 = print_insn_s390;
#elif defined(__hppa__)
VAR_6 = print_insn_hppa;
#elif defined(__ia64__)
VAR_6 = print_insn_ia64;
#else
fprintf(VAR_0, "0x%lx: Asm output not supported on this arch\n",
(long) VAR_1);
return;
#endif
for (VAR_7 = (unsigned long)VAR_1; VAR_2 > 0; VAR_7 += VAR_4, VAR_2 -= VAR_4) {
fprintf(VAR_0, "0x%08lx: ", VAR_7);
#ifdef __arm__
fprintf(VAR_0, "%08x ", (int)bfd_getl32((const bfd_byte *)VAR_7));
#endif
VAR_4 = VAR_6(VAR_7, &VAR_5);
fprintf(VAR_0, "\n");
if (VAR_4 < 0)
break;
}
}
| [
"void FUNC_0(FILE *VAR_0, void *VAR_1, unsigned long VAR_2)\n{",
"unsigned long VAR_7;",
"int VAR_4;",
"struct disassemble_info VAR_5;",
"int (*VAR_6)(bfd_vma VAR_7, disassemble_info *VAR_7);",
"INIT_DISASSEMBLE_INFO(VAR_5, VAR_0, fprintf);",
"VAR_5.buffer = VAR_1;",
"VAR_5.buffer_vma = (unsigned long)VAR_1;",
"VAR_5.buffer_length = VAR_2;",
"#ifdef HOST_WORDS_BIGENDIAN\nVAR_5.endian = BFD_ENDIAN_BIG;",
"#else\nVAR_5.endian = BFD_ENDIAN_LITTLE;",
"#endif\n#if defined(__i386__)\nVAR_5.mach = bfd_mach_i386_i386;",
"VAR_6 = print_insn_i386;",
"#elif defined(__x86_64__)\nVAR_5.mach = bfd_mach_x86_64;",
"VAR_6 = print_insn_i386;",
"#elif defined(_ARCH_PPC)\nVAR_6 = print_insn_ppc;",
"#elif defined(__alpha__)\nVAR_6 = print_insn_alpha;",
"#elif defined(__sparc__)\nVAR_6 = print_insn_sparc;",
"#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)\nVAR_5.mach = bfd_mach_sparc_v9b;",
"#endif\n#elif defined(__arm__)\nVAR_6 = print_insn_arm;",
"#elif defined(__MIPSEB__)\nVAR_6 = print_insn_big_mips;",
"#elif defined(__MIPSEL__)\nVAR_6 = print_insn_little_mips;",
"#elif defined(__m68k__)\nVAR_6 = print_insn_m68k;",
"#elif defined(__s390__)\nVAR_6 = print_insn_s390;",
"#elif defined(__hppa__)\nVAR_6 = print_insn_hppa;",
"#elif defined(__ia64__)\nVAR_6 = print_insn_ia64;",
"#else\nfprintf(VAR_0, \"0x%lx: Asm output not supported on this arch\\n\",\n(long) VAR_1);",
"return;",
"#endif\nfor (VAR_7 = (unsigned long)VAR_1; VAR_2 > 0; VAR_7 += VAR_4, VAR_2 -= VAR_4) {",
"fprintf(VAR_0, \"0x%08lx: \", VAR_7);",
"#ifdef __arm__\nfprintf(VAR_0, \"%08x \", (int)bfd_getl32((const bfd_byte *)VAR_7));",
"#endif\nVAR_4 = VAR_6(VAR_7, &VAR_5);",
"fprintf(VAR_0, \"\\n\");",
"if (VAR_4 < 0)\nbreak;",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
19
],
[
21
],
[
23
],
[
27,
29
],
[
31,
33
],
[
35,
37,
39
],
[
41
],
[
43,
45
],
[
47
],
[
49,
51
],
[
53,
55
],
[
57,
59
],
[
61,
63
],
[
65,
67,
69
],
[
71,
73
],
[
75,
77
],
[
79,
81
],
[
83,
85
],
[
87,
89
],
[
91,
93
],
[
95,
97,
99
],
[
101
],
[
103,
105
],
[
107
],
[
109,
115
],
[
117,
119
],
[
121
],
[
123,
125
],
[
127
],
[
129
]
]
|
10,285 | void bdrv_add_key(BlockDriverState *bs, const char *key, Error **errp)
{
if (key) {
if (!bdrv_is_encrypted(bs)) {
error_setg(errp, "Node '%s' is not encrypted",
bdrv_get_device_or_node_name(bs));
} else if (bdrv_set_key(bs, key) < 0) {
error_set(errp, QERR_INVALID_PASSWORD);
}
} else {
if (bdrv_key_required(bs)) {
error_set(errp, ERROR_CLASS_DEVICE_ENCRYPTED,
"'%s' (%s) is encrypted",
bdrv_get_device_or_node_name(bs),
bdrv_get_encrypted_filename(bs));
}
}
}
| false | qemu | 61007b316cd71ee7333ff7a0a749a8949527575f | void bdrv_add_key(BlockDriverState *bs, const char *key, Error **errp)
{
if (key) {
if (!bdrv_is_encrypted(bs)) {
error_setg(errp, "Node '%s' is not encrypted",
bdrv_get_device_or_node_name(bs));
} else if (bdrv_set_key(bs, key) < 0) {
error_set(errp, QERR_INVALID_PASSWORD);
}
} else {
if (bdrv_key_required(bs)) {
error_set(errp, ERROR_CLASS_DEVICE_ENCRYPTED,
"'%s' (%s) is encrypted",
bdrv_get_device_or_node_name(bs),
bdrv_get_encrypted_filename(bs));
}
}
}
| {
"code": [],
"line_no": []
} | void FUNC_0(BlockDriverState *VAR_0, const char *VAR_1, Error **VAR_2)
{
if (VAR_1) {
if (!bdrv_is_encrypted(VAR_0)) {
error_setg(VAR_2, "Node '%s' is not encrypted",
bdrv_get_device_or_node_name(VAR_0));
} else if (bdrv_set_key(VAR_0, VAR_1) < 0) {
error_set(VAR_2, QERR_INVALID_PASSWORD);
}
} else {
if (bdrv_key_required(VAR_0)) {
error_set(VAR_2, ERROR_CLASS_DEVICE_ENCRYPTED,
"'%s' (%s) is encrypted",
bdrv_get_device_or_node_name(VAR_0),
bdrv_get_encrypted_filename(VAR_0));
}
}
}
| [
"void FUNC_0(BlockDriverState *VAR_0, const char *VAR_1, Error **VAR_2)\n{",
"if (VAR_1) {",
"if (!bdrv_is_encrypted(VAR_0)) {",
"error_setg(VAR_2, \"Node '%s' is not encrypted\",\nbdrv_get_device_or_node_name(VAR_0));",
"} else if (bdrv_set_key(VAR_0, VAR_1) < 0) {",
"error_set(VAR_2, QERR_INVALID_PASSWORD);",
"}",
"} else {",
"if (bdrv_key_required(VAR_0)) {",
"error_set(VAR_2, ERROR_CLASS_DEVICE_ENCRYPTED,\n\"'%s' (%s) is encrypted\",\nbdrv_get_device_or_node_name(VAR_0),\nbdrv_get_encrypted_filename(VAR_0));",
"}",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9,
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23,
25,
27,
29
],
[
31
],
[
33
],
[
35
]
]
|
10,286 | static void armv7m_nvic_reset(DeviceState *dev)
{
nvic_state *s = NVIC(dev);
NVICClass *nc = NVIC_GET_CLASS(s);
nc->parent_reset(dev);
/* Common GIC reset resets to disabled; the NVIC doesn't have
* per-CPU interfaces so mark our non-existent CPU interface
* as enabled by default, and with a priority mask which allows
* all interrupts through.
*/
s->gic.cpu_enabled[0] = true;
s->gic.priority_mask[0] = 0x100;
/* The NVIC as a whole is always enabled. */
s->gic.enabled = true;
systick_reset(s);
}
| false | qemu | 679aa175e84f5f80b32b307fce5a6b92729e0e61 | static void armv7m_nvic_reset(DeviceState *dev)
{
nvic_state *s = NVIC(dev);
NVICClass *nc = NVIC_GET_CLASS(s);
nc->parent_reset(dev);
s->gic.cpu_enabled[0] = true;
s->gic.priority_mask[0] = 0x100;
s->gic.enabled = true;
systick_reset(s);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(DeviceState *VAR_0)
{
nvic_state *s = NVIC(VAR_0);
NVICClass *nc = NVIC_GET_CLASS(s);
nc->parent_reset(VAR_0);
s->gic.cpu_enabled[0] = true;
s->gic.priority_mask[0] = 0x100;
s->gic.enabled = true;
systick_reset(s);
}
| [
"static void FUNC_0(DeviceState *VAR_0)\n{",
"nvic_state *s = NVIC(VAR_0);",
"NVICClass *nc = NVIC_GET_CLASS(s);",
"nc->parent_reset(VAR_0);",
"s->gic.cpu_enabled[0] = true;",
"s->gic.priority_mask[0] = 0x100;",
"s->gic.enabled = true;",
"systick_reset(s);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
21
],
[
23
],
[
27
],
[
29
],
[
31
]
]
|
10,287 | static void float_to_int16_sse(int16_t *dst, const float *src, long len){
int i;
for(i=0; i<len; i+=4) {
asm volatile(
"cvtps2pi %1, %%mm0 \n\t"
"cvtps2pi %2, %%mm1 \n\t"
"packssdw %%mm1, %%mm0 \n\t"
"movq %%mm0, %0 \n\t"
:"=m"(dst[i])
:"m"(src[i]), "m"(src[i+2])
);
}
asm volatile("emms");
}
| false | FFmpeg | 35ee72b1d72a4c8fc0ae4e76ad00a71e831b8dbe | static void float_to_int16_sse(int16_t *dst, const float *src, long len){
int i;
for(i=0; i<len; i+=4) {
asm volatile(
"cvtps2pi %1, %%mm0 \n\t"
"cvtps2pi %2, %%mm1 \n\t"
"packssdw %%mm1, %%mm0 \n\t"
"movq %%mm0, %0 \n\t"
:"=m"(dst[i])
:"m"(src[i]), "m"(src[i+2])
);
}
asm volatile("emms");
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(int16_t *VAR_0, const float *VAR_1, long VAR_2){
int VAR_3;
for(VAR_3=0; VAR_3<VAR_2; VAR_3+=4) {
asm volatile(
"cvtps2pi %1, %%mm0 \n\t"
"cvtps2pi %2, %%mm1 \n\t"
"packssdw %%mm1, %%mm0 \n\t"
"movq %%mm0, %0 \n\t"
:"=m"(VAR_0[VAR_3])
:"m"(VAR_1[VAR_3]), "m"(VAR_1[VAR_3+2])
);
}
asm volatile("emms");
}
| [
"static void FUNC_0(int16_t *VAR_0, const float *VAR_1, long VAR_2){",
"int VAR_3;",
"for(VAR_3=0; VAR_3<VAR_2; VAR_3+=4) {",
"asm volatile(\n\"cvtps2pi %1, %%mm0 \\n\\t\"\n\"cvtps2pi %2, %%mm1 \\n\\t\"\n\"packssdw %%mm1, %%mm0 \\n\\t\"\n\"movq %%mm0, %0 \\n\\t\"\n:\"=m\"(VAR_0[VAR_3])\n:\"m\"(VAR_1[VAR_3]), \"m\"(VAR_1[VAR_3+2])\n);",
"}",
"asm volatile(\"emms\");",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0
]
| [
[
1
],
[
3
],
[
5
],
[
7,
9,
11,
13,
15,
17,
19,
21
],
[
23
],
[
25
],
[
27
]
]
|
10,289 | static int migration_rate_limit(void *opaque)
{
MigrationState *s = opaque;
int ret;
ret = qemu_file_get_error(s->file);
if (ret) {
return ret;
}
if (s->bytes_xfer >= s->xfer_limit) {
return 1;
}
return 0;
}
| false | qemu | 1964a397063967acc5ce71a2a24ed26e74824ee1 | static int migration_rate_limit(void *opaque)
{
MigrationState *s = opaque;
int ret;
ret = qemu_file_get_error(s->file);
if (ret) {
return ret;
}
if (s->bytes_xfer >= s->xfer_limit) {
return 1;
}
return 0;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(void *VAR_0)
{
MigrationState *s = VAR_0;
int VAR_1;
VAR_1 = qemu_file_get_error(s->file);
if (VAR_1) {
return VAR_1;
}
if (s->bytes_xfer >= s->xfer_limit) {
return 1;
}
return 0;
}
| [
"static int FUNC_0(void *VAR_0)\n{",
"MigrationState *s = VAR_0;",
"int VAR_1;",
"VAR_1 = qemu_file_get_error(s->file);",
"if (VAR_1) {",
"return VAR_1;",
"}",
"if (s->bytes_xfer >= s->xfer_limit) {",
"return 1;",
"}",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
29
],
[
31
]
]
|
10,290 | void cpu_interrupt(CPUState *env, int mask)
{
int old_mask;
old_mask = env->interrupt_request;
env->interrupt_request |= mask;
#ifndef CONFIG_USER_ONLY
/*
* If called from iothread context, wake the target cpu in
* case its halted.
*/
if (!qemu_cpu_self(env)) {
qemu_cpu_kick(env);
return;
}
#endif
if (use_icount) {
env->icount_decr.u16.high = 0xffff;
#ifndef CONFIG_USER_ONLY
if (!can_do_io(env)
&& (mask & ~old_mask) != 0) {
cpu_abort(env, "Raised interrupt while not in I/O function");
}
#endif
} else {
cpu_unlink_tb(env);
}
}
| false | qemu | b7680cb6078bd7294a3dd86473d3f2fdee991dd0 | void cpu_interrupt(CPUState *env, int mask)
{
int old_mask;
old_mask = env->interrupt_request;
env->interrupt_request |= mask;
#ifndef CONFIG_USER_ONLY
if (!qemu_cpu_self(env)) {
qemu_cpu_kick(env);
return;
}
#endif
if (use_icount) {
env->icount_decr.u16.high = 0xffff;
#ifndef CONFIG_USER_ONLY
if (!can_do_io(env)
&& (mask & ~old_mask) != 0) {
cpu_abort(env, "Raised interrupt while not in I/O function");
}
#endif
} else {
cpu_unlink_tb(env);
}
}
| {
"code": [],
"line_no": []
} | void FUNC_0(CPUState *VAR_0, int VAR_1)
{
int VAR_2;
VAR_2 = VAR_0->interrupt_request;
VAR_0->interrupt_request |= VAR_1;
#ifndef CONFIG_USER_ONLY
if (!qemu_cpu_self(VAR_0)) {
qemu_cpu_kick(VAR_0);
return;
}
#endif
if (use_icount) {
VAR_0->icount_decr.u16.high = 0xffff;
#ifndef CONFIG_USER_ONLY
if (!can_do_io(VAR_0)
&& (VAR_1 & ~VAR_2) != 0) {
cpu_abort(VAR_0, "Raised interrupt while not in I/O function");
}
#endif
} else {
cpu_unlink_tb(VAR_0);
}
}
| [
"void FUNC_0(CPUState *VAR_0, int VAR_1)\n{",
"int VAR_2;",
"VAR_2 = VAR_0->interrupt_request;",
"VAR_0->interrupt_request |= VAR_1;",
"#ifndef CONFIG_USER_ONLY\nif (!qemu_cpu_self(VAR_0)) {",
"qemu_cpu_kick(VAR_0);",
"return;",
"}",
"#endif\nif (use_icount) {",
"VAR_0->icount_decr.u16.high = 0xffff;",
"#ifndef CONFIG_USER_ONLY\nif (!can_do_io(VAR_0)\n&& (VAR_1 & ~VAR_2) != 0) {",
"cpu_abort(VAR_0, \"Raised interrupt while not in I/O function\");",
"}",
"#endif\n} else {",
"cpu_unlink_tb(VAR_0);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
15,
25
],
[
27
],
[
29
],
[
31
],
[
33,
37
],
[
39
],
[
41,
43,
45
],
[
47
],
[
49
],
[
51,
53
],
[
55
],
[
57
],
[
59
]
]
|
10,292 | static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
int mem_index, TCGMemOp s_bits,
tcg_insn_unit **label_ptr, int which)
{
const TCGReg r0 = TCG_REG_L0;
const TCGReg r1 = TCG_REG_L1;
TCGType ttype = TCG_TYPE_I32;
TCGType htype = TCG_TYPE_I32;
int trexw = 0, hrexw = 0;
if (TCG_TARGET_REG_BITS == 64) {
if (TARGET_LONG_BITS == 64) {
ttype = TCG_TYPE_I64;
trexw = P_REXW;
}
if (TCG_TYPE_PTR == TCG_TYPE_I64) {
htype = TCG_TYPE_I64;
hrexw = P_REXW;
}
}
tcg_out_mov(s, htype, r0, addrlo);
tcg_out_mov(s, ttype, r1, addrlo);
tcg_out_shifti(s, SHIFT_SHR + hrexw, r0,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tgen_arithi(s, ARITH_AND + trexw, r1,
TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);
tgen_arithi(s, ARITH_AND + hrexw, r0,
(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
tcg_out_modrm_sib_offset(s, OPC_LEA + hrexw, r0, TCG_AREG0, r0, 0,
offsetof(CPUArchState, tlb_table[mem_index][0])
+ which);
/* cmp 0(r0), r1 */
tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0);
/* Prepare for both the fast path add of the tlb addend, and the slow
path function argument setup. There are two cases worth note:
For 32-bit guest and x86_64 host, MOVL zero-extends the guest address
before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ
copies the entire guest address for the slow path, while truncation
for the 32-bit host happens with the fastpath ADDL below. */
tcg_out_mov(s, ttype, r1, addrlo);
/* jne slow_path */
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
label_ptr[0] = s->code_ptr;
s->code_ptr += 4;
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
/* cmp 4(r0), addrhi */
tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4);
/* jne slow_path */
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
label_ptr[1] = s->code_ptr;
s->code_ptr += 4;
}
/* TLB Hit. */
/* add addend(r0), r1 */
tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,
offsetof(CPUTLBEntry, addend) - which);
}
| false | qemu | 8cc580f6a0d8c0e2f590c1472cf5cd8e51761760 | static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
int mem_index, TCGMemOp s_bits,
tcg_insn_unit **label_ptr, int which)
{
const TCGReg r0 = TCG_REG_L0;
const TCGReg r1 = TCG_REG_L1;
TCGType ttype = TCG_TYPE_I32;
TCGType htype = TCG_TYPE_I32;
int trexw = 0, hrexw = 0;
if (TCG_TARGET_REG_BITS == 64) {
if (TARGET_LONG_BITS == 64) {
ttype = TCG_TYPE_I64;
trexw = P_REXW;
}
if (TCG_TYPE_PTR == TCG_TYPE_I64) {
htype = TCG_TYPE_I64;
hrexw = P_REXW;
}
}
tcg_out_mov(s, htype, r0, addrlo);
tcg_out_mov(s, ttype, r1, addrlo);
tcg_out_shifti(s, SHIFT_SHR + hrexw, r0,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tgen_arithi(s, ARITH_AND + trexw, r1,
TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);
tgen_arithi(s, ARITH_AND + hrexw, r0,
(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
tcg_out_modrm_sib_offset(s, OPC_LEA + hrexw, r0, TCG_AREG0, r0, 0,
offsetof(CPUArchState, tlb_table[mem_index][0])
+ which);
tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0);
tcg_out_mov(s, ttype, r1, addrlo);
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
label_ptr[0] = s->code_ptr;
s->code_ptr += 4;
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4);
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
label_ptr[1] = s->code_ptr;
s->code_ptr += 4;
}
tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,
offsetof(CPUTLBEntry, addend) - which);
}
| {
"code": [],
"line_no": []
} | static inline void FUNC_0(TCGContext *VAR_0, TCGReg VAR_1, TCGReg VAR_2,
int VAR_3, TCGMemOp VAR_4,
tcg_insn_unit **VAR_5, int VAR_6)
{
const TCGReg VAR_7 = TCG_REG_L0;
const TCGReg VAR_8 = TCG_REG_L1;
TCGType ttype = TCG_TYPE_I32;
TCGType htype = TCG_TYPE_I32;
int VAR_9 = 0, VAR_10 = 0;
if (TCG_TARGET_REG_BITS == 64) {
if (TARGET_LONG_BITS == 64) {
ttype = TCG_TYPE_I64;
VAR_9 = P_REXW;
}
if (TCG_TYPE_PTR == TCG_TYPE_I64) {
htype = TCG_TYPE_I64;
VAR_10 = P_REXW;
}
}
tcg_out_mov(VAR_0, htype, VAR_7, VAR_1);
tcg_out_mov(VAR_0, ttype, VAR_8, VAR_1);
tcg_out_shifti(VAR_0, SHIFT_SHR + VAR_10, VAR_7,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tgen_arithi(VAR_0, ARITH_AND + VAR_9, VAR_8,
TARGET_PAGE_MASK | ((1 << VAR_4) - 1), 0);
tgen_arithi(VAR_0, ARITH_AND + VAR_10, VAR_7,
(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
tcg_out_modrm_sib_offset(VAR_0, OPC_LEA + VAR_10, VAR_7, TCG_AREG0, VAR_7, 0,
offsetof(CPUArchState, tlb_table[VAR_3][0])
+ VAR_6);
tcg_out_modrm_offset(VAR_0, OPC_CMP_GvEv + VAR_9, VAR_8, VAR_7, 0);
tcg_out_mov(VAR_0, ttype, VAR_8, VAR_1);
tcg_out_opc(VAR_0, OPC_JCC_long + JCC_JNE, 0, 0, 0);
VAR_5[0] = VAR_0->code_ptr;
VAR_0->code_ptr += 4;
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
tcg_out_modrm_offset(VAR_0, OPC_CMP_GvEv, VAR_2, VAR_7, 4);
tcg_out_opc(VAR_0, OPC_JCC_long + JCC_JNE, 0, 0, 0);
VAR_5[1] = VAR_0->code_ptr;
VAR_0->code_ptr += 4;
}
tcg_out_modrm_offset(VAR_0, OPC_ADD_GvEv + VAR_10, VAR_8, VAR_7,
offsetof(CPUTLBEntry, addend) - VAR_6);
}
| [
"static inline void FUNC_0(TCGContext *VAR_0, TCGReg VAR_1, TCGReg VAR_2,\nint VAR_3, TCGMemOp VAR_4,\ntcg_insn_unit **VAR_5, int VAR_6)\n{",
"const TCGReg VAR_7 = TCG_REG_L0;",
"const TCGReg VAR_8 = TCG_REG_L1;",
"TCGType ttype = TCG_TYPE_I32;",
"TCGType htype = TCG_TYPE_I32;",
"int VAR_9 = 0, VAR_10 = 0;",
"if (TCG_TARGET_REG_BITS == 64) {",
"if (TARGET_LONG_BITS == 64) {",
"ttype = TCG_TYPE_I64;",
"VAR_9 = P_REXW;",
"}",
"if (TCG_TYPE_PTR == TCG_TYPE_I64) {",
"htype = TCG_TYPE_I64;",
"VAR_10 = P_REXW;",
"}",
"}",
"tcg_out_mov(VAR_0, htype, VAR_7, VAR_1);",
"tcg_out_mov(VAR_0, ttype, VAR_8, VAR_1);",
"tcg_out_shifti(VAR_0, SHIFT_SHR + VAR_10, VAR_7,\nTARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);",
"tgen_arithi(VAR_0, ARITH_AND + VAR_9, VAR_8,\nTARGET_PAGE_MASK | ((1 << VAR_4) - 1), 0);",
"tgen_arithi(VAR_0, ARITH_AND + VAR_10, VAR_7,\n(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);",
"tcg_out_modrm_sib_offset(VAR_0, OPC_LEA + VAR_10, VAR_7, TCG_AREG0, VAR_7, 0,\noffsetof(CPUArchState, tlb_table[VAR_3][0])\n+ VAR_6);",
"tcg_out_modrm_offset(VAR_0, OPC_CMP_GvEv + VAR_9, VAR_8, VAR_7, 0);",
"tcg_out_mov(VAR_0, ttype, VAR_8, VAR_1);",
"tcg_out_opc(VAR_0, OPC_JCC_long + JCC_JNE, 0, 0, 0);",
"VAR_5[0] = VAR_0->code_ptr;",
"VAR_0->code_ptr += 4;",
"if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {",
"tcg_out_modrm_offset(VAR_0, OPC_CMP_GvEv, VAR_2, VAR_7, 4);",
"tcg_out_opc(VAR_0, OPC_JCC_long + JCC_JNE, 0, 0, 0);",
"VAR_5[1] = VAR_0->code_ptr;",
"VAR_0->code_ptr += 4;",
"}",
"tcg_out_modrm_offset(VAR_0, OPC_ADD_GvEv + VAR_10, VAR_8, VAR_7,\noffsetof(CPUTLBEntry, addend) - VAR_6);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5,
7
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33
],
[
35
],
[
37
],
[
39
],
[
43
],
[
45
],
[
49,
51
],
[
55,
57
],
[
59,
61
],
[
65,
67,
69
],
[
75
],
[
91
],
[
97
],
[
99
],
[
101
],
[
105
],
[
109
],
[
115
],
[
117
],
[
119
],
[
121
],
[
131,
133
],
[
135
]
]
|
10,294 | static inline void t_gen_sext(TCGv d, TCGv s, int size)
{
if (size == 1)
tcg_gen_ext8s_i32(d, s);
else if (size == 2)
tcg_gen_ext16s_i32(d, s);
else if(GET_TCGV(d) != GET_TCGV(s))
tcg_gen_mov_tl(d, s);
}
| false | qemu | a7812ae412311d7d47f8aa85656faadac9d64b56 | static inline void t_gen_sext(TCGv d, TCGv s, int size)
{
if (size == 1)
tcg_gen_ext8s_i32(d, s);
else if (size == 2)
tcg_gen_ext16s_i32(d, s);
else if(GET_TCGV(d) != GET_TCGV(s))
tcg_gen_mov_tl(d, s);
}
| {
"code": [],
"line_no": []
} | static inline void FUNC_0(TCGv VAR_0, TCGv VAR_1, int VAR_2)
{
if (VAR_2 == 1)
tcg_gen_ext8s_i32(VAR_0, VAR_1);
else if (VAR_2 == 2)
tcg_gen_ext16s_i32(VAR_0, VAR_1);
else if(GET_TCGV(VAR_0) != GET_TCGV(VAR_1))
tcg_gen_mov_tl(VAR_0, VAR_1);
}
| [
"static inline void FUNC_0(TCGv VAR_0, TCGv VAR_1, int VAR_2)\n{",
"if (VAR_2 == 1)\ntcg_gen_ext8s_i32(VAR_0, VAR_1);",
"else if (VAR_2 == 2)\ntcg_gen_ext16s_i32(VAR_0, VAR_1);",
"else if(GET_TCGV(VAR_0) != GET_TCGV(VAR_1))\ntcg_gen_mov_tl(VAR_0, VAR_1);",
"}"
]
| [
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5,
7
],
[
9,
11
],
[
13,
15
],
[
17
]
]
|
10,296 | static int vio_make_devnode(VIOsPAPRDevice *dev,
void *fdt)
{
VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&dev->qdev);
int vdevice_off, node_off, ret;
char *dt_name;
vdevice_off = fdt_path_offset(fdt, "/vdevice");
if (vdevice_off < 0) {
return vdevice_off;
}
dt_name = vio_format_dev_name(dev);
if (!dt_name) {
return -ENOMEM;
}
node_off = fdt_add_subnode(fdt, vdevice_off, dt_name);
free(dt_name);
if (node_off < 0) {
return node_off;
}
ret = fdt_setprop_cell(fdt, node_off, "reg", dev->reg);
if (ret < 0) {
return ret;
}
if (info->dt_type) {
ret = fdt_setprop_string(fdt, node_off, "device_type",
info->dt_type);
if (ret < 0) {
return ret;
}
}
if (info->dt_compatible) {
ret = fdt_setprop_string(fdt, node_off, "compatible",
info->dt_compatible);
if (ret < 0) {
return ret;
}
}
if (dev->qirq) {
uint32_t ints_prop[] = {cpu_to_be32(dev->vio_irq_num), 0};
ret = fdt_setprop(fdt, node_off, "interrupts", ints_prop,
sizeof(ints_prop));
if (ret < 0) {
return ret;
}
}
if (dev->rtce_window_size) {
uint32_t dma_prop[] = {cpu_to_be32(dev->reg),
0, 0,
0, cpu_to_be32(dev->rtce_window_size)};
ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
if (ret < 0) {
return ret;
}
ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
if (ret < 0) {
return ret;
}
ret = fdt_setprop(fdt, node_off, "ibm,my-dma-window", dma_prop,
sizeof(dma_prop));
if (ret < 0) {
return ret;
}
}
if (info->devnode) {
ret = (info->devnode)(dev, fdt, node_off);
if (ret < 0) {
return ret;
}
}
return node_off;
}
| false | qemu | 3954d33ab7f82f5a5fa0ced231849920265a5fec | static int vio_make_devnode(VIOsPAPRDevice *dev,
void *fdt)
{
VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&dev->qdev);
int vdevice_off, node_off, ret;
char *dt_name;
vdevice_off = fdt_path_offset(fdt, "/vdevice");
if (vdevice_off < 0) {
return vdevice_off;
}
dt_name = vio_format_dev_name(dev);
if (!dt_name) {
return -ENOMEM;
}
node_off = fdt_add_subnode(fdt, vdevice_off, dt_name);
free(dt_name);
if (node_off < 0) {
return node_off;
}
ret = fdt_setprop_cell(fdt, node_off, "reg", dev->reg);
if (ret < 0) {
return ret;
}
if (info->dt_type) {
ret = fdt_setprop_string(fdt, node_off, "device_type",
info->dt_type);
if (ret < 0) {
return ret;
}
}
if (info->dt_compatible) {
ret = fdt_setprop_string(fdt, node_off, "compatible",
info->dt_compatible);
if (ret < 0) {
return ret;
}
}
if (dev->qirq) {
uint32_t ints_prop[] = {cpu_to_be32(dev->vio_irq_num), 0};
ret = fdt_setprop(fdt, node_off, "interrupts", ints_prop,
sizeof(ints_prop));
if (ret < 0) {
return ret;
}
}
if (dev->rtce_window_size) {
uint32_t dma_prop[] = {cpu_to_be32(dev->reg),
0, 0,
0, cpu_to_be32(dev->rtce_window_size)};
ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
if (ret < 0) {
return ret;
}
ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
if (ret < 0) {
return ret;
}
ret = fdt_setprop(fdt, node_off, "ibm,my-dma-window", dma_prop,
sizeof(dma_prop));
if (ret < 0) {
return ret;
}
}
if (info->devnode) {
ret = (info->devnode)(dev, fdt, node_off);
if (ret < 0) {
return ret;
}
}
return node_off;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(VIOsPAPRDevice *VAR_0,
void *VAR_1)
{
VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&VAR_0->qdev);
int VAR_2, VAR_3, VAR_4;
char *VAR_5;
VAR_2 = fdt_path_offset(VAR_1, "/vdevice");
if (VAR_2 < 0) {
return VAR_2;
}
VAR_5 = vio_format_dev_name(VAR_0);
if (!VAR_5) {
return -ENOMEM;
}
VAR_3 = fdt_add_subnode(VAR_1, VAR_2, VAR_5);
free(VAR_5);
if (VAR_3 < 0) {
return VAR_3;
}
VAR_4 = fdt_setprop_cell(VAR_1, VAR_3, "reg", VAR_0->reg);
if (VAR_4 < 0) {
return VAR_4;
}
if (info->dt_type) {
VAR_4 = fdt_setprop_string(VAR_1, VAR_3, "device_type",
info->dt_type);
if (VAR_4 < 0) {
return VAR_4;
}
}
if (info->dt_compatible) {
VAR_4 = fdt_setprop_string(VAR_1, VAR_3, "compatible",
info->dt_compatible);
if (VAR_4 < 0) {
return VAR_4;
}
}
if (VAR_0->qirq) {
uint32_t ints_prop[] = {cpu_to_be32(VAR_0->vio_irq_num), 0};
VAR_4 = fdt_setprop(VAR_1, VAR_3, "interrupts", ints_prop,
sizeof(ints_prop));
if (VAR_4 < 0) {
return VAR_4;
}
}
if (VAR_0->rtce_window_size) {
uint32_t dma_prop[] = {cpu_to_be32(VAR_0->reg),
0, 0,
0, cpu_to_be32(VAR_0->rtce_window_size)};
VAR_4 = fdt_setprop_cell(VAR_1, VAR_3, "ibm,#dma-address-cells", 2);
if (VAR_4 < 0) {
return VAR_4;
}
VAR_4 = fdt_setprop_cell(VAR_1, VAR_3, "ibm,#dma-size-cells", 2);
if (VAR_4 < 0) {
return VAR_4;
}
VAR_4 = fdt_setprop(VAR_1, VAR_3, "ibm,my-dma-window", dma_prop,
sizeof(dma_prop));
if (VAR_4 < 0) {
return VAR_4;
}
}
if (info->devnode) {
VAR_4 = (info->devnode)(VAR_0, VAR_1, VAR_3);
if (VAR_4 < 0) {
return VAR_4;
}
}
return VAR_3;
}
| [
"static int FUNC_0(VIOsPAPRDevice *VAR_0,\nvoid *VAR_1)\n{",
"VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&VAR_0->qdev);",
"int VAR_2, VAR_3, VAR_4;",
"char *VAR_5;",
"VAR_2 = fdt_path_offset(VAR_1, \"/vdevice\");",
"if (VAR_2 < 0) {",
"return VAR_2;",
"}",
"VAR_5 = vio_format_dev_name(VAR_0);",
"if (!VAR_5) {",
"return -ENOMEM;",
"}",
"VAR_3 = fdt_add_subnode(VAR_1, VAR_2, VAR_5);",
"free(VAR_5);",
"if (VAR_3 < 0) {",
"return VAR_3;",
"}",
"VAR_4 = fdt_setprop_cell(VAR_1, VAR_3, \"reg\", VAR_0->reg);",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"if (info->dt_type) {",
"VAR_4 = fdt_setprop_string(VAR_1, VAR_3, \"device_type\",\ninfo->dt_type);",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"}",
"if (info->dt_compatible) {",
"VAR_4 = fdt_setprop_string(VAR_1, VAR_3, \"compatible\",\ninfo->dt_compatible);",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"}",
"if (VAR_0->qirq) {",
"uint32_t ints_prop[] = {cpu_to_be32(VAR_0->vio_irq_num), 0};",
"VAR_4 = fdt_setprop(VAR_1, VAR_3, \"interrupts\", ints_prop,\nsizeof(ints_prop));",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"}",
"if (VAR_0->rtce_window_size) {",
"uint32_t dma_prop[] = {cpu_to_be32(VAR_0->reg),",
"0, 0,\n0, cpu_to_be32(VAR_0->rtce_window_size)};",
"VAR_4 = fdt_setprop_cell(VAR_1, VAR_3, \"ibm,#dma-address-cells\", 2);",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"VAR_4 = fdt_setprop_cell(VAR_1, VAR_3, \"ibm,#dma-size-cells\", 2);",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"VAR_4 = fdt_setprop(VAR_1, VAR_3, \"ibm,my-dma-window\", dma_prop,\nsizeof(dma_prop));",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"}",
"if (info->devnode) {",
"VAR_4 = (info->devnode)(VAR_0, VAR_1, VAR_3);",
"if (VAR_4 < 0) {",
"return VAR_4;",
"}",
"}",
"return VAR_3;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
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| [
[
1,
3,
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17
],
[
19
],
[
21
],
[
25
],
[
27
],
[
29
],
[
31
],
[
35
],
[
37
],
[
39
],
[
41
],
[
43
],
[
47
],
[
49
],
[
51
],
[
53
],
[
57
],
[
59,
61
],
[
63
],
[
65
],
[
67
],
[
69
],
[
73
],
[
75,
77
],
[
79
],
[
81
],
[
83
],
[
85
],
[
89
],
[
91
],
[
95,
97
],
[
99
],
[
101
],
[
103
],
[
105
],
[
109
],
[
111
],
[
113,
115
],
[
119
],
[
121
],
[
123
],
[
125
],
[
129
],
[
131
],
[
133
],
[
135
],
[
139,
141
],
[
143
],
[
145
],
[
147
],
[
149
],
[
153
],
[
155
],
[
157
],
[
159
],
[
161
],
[
163
],
[
167
],
[
169
]
]
|
10,297 | void mkimg(const char *file, const char *fmt, unsigned size_mb)
{
gchar *cli;
bool ret;
int rc;
GError *err = NULL;
char *qemu_img_path;
gchar *out, *out2;
char *abs_path;
qemu_img_path = getenv("QTEST_QEMU_IMG");
abs_path = realpath(qemu_img_path, NULL);
assert(qemu_img_path);
cli = g_strdup_printf("%s create -f %s %s %uM", abs_path,
fmt, file, size_mb);
ret = g_spawn_command_line_sync(cli, &out, &out2, &rc, &err);
if (err) {
fprintf(stderr, "%s\n", err->message);
g_error_free(err);
}
g_assert(ret && !err);
/* In glib 2.34, we have g_spawn_check_exit_status. in 2.12, we don't.
* glib 2.43.91 implementation assumes that any non-zero is an error for
* windows, but uses extra precautions for Linux. However,
* 0 is only possible if the program exited normally, so that should be
* sufficient for our purposes on all platforms, here. */
if (rc) {
fprintf(stderr, "qemu-img returned status code %d\n", rc);
}
g_assert(!rc);
g_free(out);
g_free(out2);
g_free(cli);
free(abs_path);
}
| false | qemu | cb11e7b2f3878575f23d49454c02d8dce35c8d35 | void mkimg(const char *file, const char *fmt, unsigned size_mb)
{
gchar *cli;
bool ret;
int rc;
GError *err = NULL;
char *qemu_img_path;
gchar *out, *out2;
char *abs_path;
qemu_img_path = getenv("QTEST_QEMU_IMG");
abs_path = realpath(qemu_img_path, NULL);
assert(qemu_img_path);
cli = g_strdup_printf("%s create -f %s %s %uM", abs_path,
fmt, file, size_mb);
ret = g_spawn_command_line_sync(cli, &out, &out2, &rc, &err);
if (err) {
fprintf(stderr, "%s\n", err->message);
g_error_free(err);
}
g_assert(ret && !err);
if (rc) {
fprintf(stderr, "qemu-img returned status code %d\n", rc);
}
g_assert(!rc);
g_free(out);
g_free(out2);
g_free(cli);
free(abs_path);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(const char *VAR_0, const char *VAR_1, unsigned VAR_2)
{
gchar *cli;
bool ret;
int VAR_3;
GError *err = NULL;
char *VAR_4;
gchar *out, *out2;
char *VAR_5;
VAR_4 = getenv("QTEST_QEMU_IMG");
VAR_5 = realpath(VAR_4, NULL);
assert(VAR_4);
cli = g_strdup_printf("%s create -f %s %s %uM", VAR_5,
VAR_1, VAR_0, VAR_2);
ret = g_spawn_command_line_sync(cli, &out, &out2, &VAR_3, &err);
if (err) {
fprintf(stderr, "%s\n", err->message);
g_error_free(err);
}
g_assert(ret && !err);
if (VAR_3) {
fprintf(stderr, "qemu-img returned status code %d\n", VAR_3);
}
g_assert(!VAR_3);
g_free(out);
g_free(out2);
g_free(cli);
free(VAR_5);
}
| [
"void FUNC_0(const char *VAR_0, const char *VAR_1, unsigned VAR_2)\n{",
"gchar *cli;",
"bool ret;",
"int VAR_3;",
"GError *err = NULL;",
"char *VAR_4;",
"gchar *out, *out2;",
"char *VAR_5;",
"VAR_4 = getenv(\"QTEST_QEMU_IMG\");",
"VAR_5 = realpath(VAR_4, NULL);",
"assert(VAR_4);",
"cli = g_strdup_printf(\"%s create -f %s %s %uM\", VAR_5,\nVAR_1, VAR_0, VAR_2);",
"ret = g_spawn_command_line_sync(cli, &out, &out2, &VAR_3, &err);",
"if (err) {",
"fprintf(stderr, \"%s\\n\", err->message);",
"g_error_free(err);",
"}",
"g_assert(ret && !err);",
"if (VAR_3) {",
"fprintf(stderr, \"qemu-img returned status code %d\\n\", VAR_3);",
"}",
"g_assert(!VAR_3);",
"g_free(out);",
"g_free(out2);",
"g_free(cli);",
"free(VAR_5);",
"}"
]
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0,
0,
0,
0,
0,
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0,
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0,
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| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
29,
31
],
[
33
],
[
35
],
[
37
],
[
39
],
[
41
],
[
43
],
[
57
],
[
59
],
[
61
],
[
63
],
[
67
],
[
69
],
[
71
],
[
73
],
[
75
]
]
|
10,298 | static inline void RENAME(rgb32tobgr15)(const uint8_t *src, uint8_t *dst, long src_size)
{
const uint8_t *s = src;
const uint8_t *end;
#if COMPILE_TEMPLATE_MMX
const uint8_t *mm_end;
#endif
uint16_t *d = (uint16_t *)dst;
end = s + src_size;
#if COMPILE_TEMPLATE_MMX
__asm__ volatile(PREFETCH" %0"::"m"(*src):"memory");
__asm__ volatile(
"movq %0, %%mm7 \n\t"
"movq %1, %%mm6 \n\t"
::"m"(red_15mask),"m"(green_15mask));
mm_end = end - 15;
while (s < mm_end) {
__asm__ volatile(
PREFETCH" 32%1 \n\t"
"movd %1, %%mm0 \n\t"
"movd 4%1, %%mm3 \n\t"
"punpckldq 8%1, %%mm0 \n\t"
"punpckldq 12%1, %%mm3 \n\t"
"movq %%mm0, %%mm1 \n\t"
"movq %%mm0, %%mm2 \n\t"
"movq %%mm3, %%mm4 \n\t"
"movq %%mm3, %%mm5 \n\t"
"psllq $7, %%mm0 \n\t"
"psllq $7, %%mm3 \n\t"
"pand %%mm7, %%mm0 \n\t"
"pand %%mm7, %%mm3 \n\t"
"psrlq $6, %%mm1 \n\t"
"psrlq $6, %%mm4 \n\t"
"pand %%mm6, %%mm1 \n\t"
"pand %%mm6, %%mm4 \n\t"
"psrlq $19, %%mm2 \n\t"
"psrlq $19, %%mm5 \n\t"
"pand %2, %%mm2 \n\t"
"pand %2, %%mm5 \n\t"
"por %%mm1, %%mm0 \n\t"
"por %%mm4, %%mm3 \n\t"
"por %%mm2, %%mm0 \n\t"
"por %%mm5, %%mm3 \n\t"
"psllq $16, %%mm3 \n\t"
"por %%mm3, %%mm0 \n\t"
MOVNTQ" %%mm0, %0 \n\t"
:"=m"(*d):"m"(*s),"m"(blue_15mask):"memory");
d += 4;
s += 16;
}
__asm__ volatile(SFENCE:::"memory");
__asm__ volatile(EMMS:::"memory");
#endif
while (s < end) {
register int rgb = *(const uint32_t*)s; s += 4;
*d++ = ((rgb&0xF8)<<7) + ((rgb&0xF800)>>6) + ((rgb&0xF80000)>>19);
}
}
| false | FFmpeg | d1adad3cca407f493c3637e20ecd4f7124e69212 | static inline void RENAME(rgb32tobgr15)(const uint8_t *src, uint8_t *dst, long src_size)
{
const uint8_t *s = src;
const uint8_t *end;
#if COMPILE_TEMPLATE_MMX
const uint8_t *mm_end;
#endif
uint16_t *d = (uint16_t *)dst;
end = s + src_size;
#if COMPILE_TEMPLATE_MMX
__asm__ volatile(PREFETCH" %0"::"m"(*src):"memory");
__asm__ volatile(
"movq %0, %%mm7 \n\t"
"movq %1, %%mm6 \n\t"
::"m"(red_15mask),"m"(green_15mask));
mm_end = end - 15;
while (s < mm_end) {
__asm__ volatile(
PREFETCH" 32%1 \n\t"
"movd %1, %%mm0 \n\t"
"movd 4%1, %%mm3 \n\t"
"punpckldq 8%1, %%mm0 \n\t"
"punpckldq 12%1, %%mm3 \n\t"
"movq %%mm0, %%mm1 \n\t"
"movq %%mm0, %%mm2 \n\t"
"movq %%mm3, %%mm4 \n\t"
"movq %%mm3, %%mm5 \n\t"
"psllq $7, %%mm0 \n\t"
"psllq $7, %%mm3 \n\t"
"pand %%mm7, %%mm0 \n\t"
"pand %%mm7, %%mm3 \n\t"
"psrlq $6, %%mm1 \n\t"
"psrlq $6, %%mm4 \n\t"
"pand %%mm6, %%mm1 \n\t"
"pand %%mm6, %%mm4 \n\t"
"psrlq $19, %%mm2 \n\t"
"psrlq $19, %%mm5 \n\t"
"pand %2, %%mm2 \n\t"
"pand %2, %%mm5 \n\t"
"por %%mm1, %%mm0 \n\t"
"por %%mm4, %%mm3 \n\t"
"por %%mm2, %%mm0 \n\t"
"por %%mm5, %%mm3 \n\t"
"psllq $16, %%mm3 \n\t"
"por %%mm3, %%mm0 \n\t"
MOVNTQ" %%mm0, %0 \n\t"
:"=m"(*d):"m"(*s),"m"(blue_15mask):"memory");
d += 4;
s += 16;
}
__asm__ volatile(SFENCE:::"memory");
__asm__ volatile(EMMS:::"memory");
#endif
while (s < end) {
register int rgb = *(const uint32_t*)s; s += 4;
*d++ = ((rgb&0xF8)<<7) + ((rgb&0xF800)>>6) + ((rgb&0xF80000)>>19);
}
}
| {
"code": [],
"line_no": []
} | static inline void FUNC_0(rgb32tobgr15)(const uint8_t *src, uint8_t *dst, long src_size)
{
const uint8_t *VAR_0 = src;
const uint8_t *VAR_1;
#if COMPILE_TEMPLATE_MMX
const uint8_t *mm_end;
#endif
uint16_t *d = (uint16_t *)dst;
VAR_1 = VAR_0 + src_size;
#if COMPILE_TEMPLATE_MMX
__asm__ volatile(PREFETCH" %0"::"m"(*src):"memory");
__asm__ volatile(
"movq %0, %%mm7 \n\t"
"movq %1, %%mm6 \n\t"
::"m"(red_15mask),"m"(green_15mask));
mm_end = VAR_1 - 15;
while (VAR_0 < mm_end) {
__asm__ volatile(
PREFETCH" 32%1 \n\t"
"movd %1, %%mm0 \n\t"
"movd 4%1, %%mm3 \n\t"
"punpckldq 8%1, %%mm0 \n\t"
"punpckldq 12%1, %%mm3 \n\t"
"movq %%mm0, %%mm1 \n\t"
"movq %%mm0, %%mm2 \n\t"
"movq %%mm3, %%mm4 \n\t"
"movq %%mm3, %%mm5 \n\t"
"psllq $7, %%mm0 \n\t"
"psllq $7, %%mm3 \n\t"
"pand %%mm7, %%mm0 \n\t"
"pand %%mm7, %%mm3 \n\t"
"psrlq $6, %%mm1 \n\t"
"psrlq $6, %%mm4 \n\t"
"pand %%mm6, %%mm1 \n\t"
"pand %%mm6, %%mm4 \n\t"
"psrlq $19, %%mm2 \n\t"
"psrlq $19, %%mm5 \n\t"
"pand %2, %%mm2 \n\t"
"pand %2, %%mm5 \n\t"
"por %%mm1, %%mm0 \n\t"
"por %%mm4, %%mm3 \n\t"
"por %%mm2, %%mm0 \n\t"
"por %%mm5, %%mm3 \n\t"
"psllq $16, %%mm3 \n\t"
"por %%mm3, %%mm0 \n\t"
MOVNTQ" %%mm0, %0 \n\t"
:"=m"(*d):"m"(*VAR_0),"m"(blue_15mask):"memory");
d += 4;
VAR_0 += 16;
}
__asm__ volatile(SFENCE:::"memory");
__asm__ volatile(EMMS:::"memory");
#endif
while (VAR_0 < VAR_1) {
register int VAR_2 = *(const uint32_t*)VAR_0; VAR_0 += 4;
*d++ = ((VAR_2&0xF8)<<7) + ((VAR_2&0xF800)>>6) + ((VAR_2&0xF80000)>>19);
}
}
| [
"static inline void FUNC_0(rgb32tobgr15)(const uint8_t *src, uint8_t *dst, long src_size)\n{",
"const uint8_t *VAR_0 = src;",
"const uint8_t *VAR_1;",
"#if COMPILE_TEMPLATE_MMX\nconst uint8_t *mm_end;",
"#endif\nuint16_t *d = (uint16_t *)dst;",
"VAR_1 = VAR_0 + src_size;",
"#if COMPILE_TEMPLATE_MMX\n__asm__ volatile(PREFETCH\" %0\"::\"m\"(*src):\"memory\");",
"__asm__ volatile(\n\"movq %0, %%mm7 \\n\\t\"\n\"movq %1, %%mm6 \\n\\t\"\n::\"m\"(red_15mask),\"m\"(green_15mask));",
"mm_end = VAR_1 - 15;",
"while (VAR_0 < mm_end) {",
"__asm__ volatile(\nPREFETCH\" 32%1 \\n\\t\"\n\"movd %1, %%mm0 \\n\\t\"\n\"movd 4%1, %%mm3 \\n\\t\"\n\"punpckldq 8%1, %%mm0 \\n\\t\"\n\"punpckldq 12%1, %%mm3 \\n\\t\"\n\"movq %%mm0, %%mm1 \\n\\t\"\n\"movq %%mm0, %%mm2 \\n\\t\"\n\"movq %%mm3, %%mm4 \\n\\t\"\n\"movq %%mm3, %%mm5 \\n\\t\"\n\"psllq $7, %%mm0 \\n\\t\"\n\"psllq $7, %%mm3 \\n\\t\"\n\"pand %%mm7, %%mm0 \\n\\t\"\n\"pand %%mm7, %%mm3 \\n\\t\"\n\"psrlq $6, %%mm1 \\n\\t\"\n\"psrlq $6, %%mm4 \\n\\t\"\n\"pand %%mm6, %%mm1 \\n\\t\"\n\"pand %%mm6, %%mm4 \\n\\t\"\n\"psrlq $19, %%mm2 \\n\\t\"\n\"psrlq $19, %%mm5 \\n\\t\"\n\"pand %2, %%mm2 \\n\\t\"\n\"pand %2, %%mm5 \\n\\t\"\n\"por %%mm1, %%mm0 \\n\\t\"\n\"por %%mm4, %%mm3 \\n\\t\"\n\"por %%mm2, %%mm0 \\n\\t\"\n\"por %%mm5, %%mm3 \\n\\t\"\n\"psllq $16, %%mm3 \\n\\t\"\n\"por %%mm3, %%mm0 \\n\\t\"\nMOVNTQ\" %%mm0, %0 \\n\\t\"\n:\"=m\"(*d):\"m\"(*VAR_0),\"m\"(blue_15mask):\"memory\");",
"d += 4;",
"VAR_0 += 16;",
"}",
"__asm__ volatile(SFENCE:::\"memory\");",
"__asm__ volatile(EMMS:::\"memory\");",
"#endif\nwhile (VAR_0 < VAR_1) {",
"register int VAR_2 = *(const uint32_t*)VAR_0; VAR_0 += 4;",
"*d++ = ((VAR_2&0xF8)<<7) + ((VAR_2&0xF800)>>6) + ((VAR_2&0xF80000)>>19);",
"}",
"}"
]
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0,
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0
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[
1,
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[
5
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7
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[
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[
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],
[
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[
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[
23,
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[
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[
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[
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[
115
]
]
|
10,299 | static void cris_alu_op_exec(DisasContext *dc, int op,
TCGv dst, TCGv a, TCGv b, int size)
{
/* Emit the ALU insns. */
switch (op) {
case CC_OP_ADD:
tcg_gen_add_tl(dst, a, b);
/* Extended arithmetics. */
t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
tcg_gen_add_tl(dst, a, b);
t_gen_add_flag(dst, 0); /* C_FLAG. */
break;
case CC_OP_MCP:
tcg_gen_add_tl(dst, a, b);
t_gen_add_flag(dst, 8); /* R_FLAG. */
break;
case CC_OP_SUB:
tcg_gen_sub_tl(dst, a, b);
/* Extended arithmetics. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
tcg_gen_mov_tl(dst, b);
break;
case CC_OP_OR:
tcg_gen_or_tl(dst, a, b);
break;
case CC_OP_AND:
tcg_gen_and_tl(dst, a, b);
break;
case CC_OP_XOR:
tcg_gen_xor_tl(dst, a, b);
break;
case CC_OP_LSL:
t_gen_lsl(dst, a, b);
break;
case CC_OP_LSR:
t_gen_lsr(dst, a, b);
break;
case CC_OP_ASR:
t_gen_asr(dst, a, b);
break;
case CC_OP_NEG:
tcg_gen_neg_tl(dst, b);
/* Extended arithmetics. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
gen_helper_lz(dst, b);
break;
case CC_OP_MULS:
tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
break;
case CC_OP_MULU:
tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
break;
case CC_OP_DSTEP:
t_gen_cris_dstep(dst, a, b);
break;
case CC_OP_MSTEP:
t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
break;
case CC_OP_BOUND:
{
int l1;
l1 = gen_new_label();
tcg_gen_mov_tl(dst, a);
tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
tcg_gen_mov_tl(dst, b);
gen_set_label(l1);
}
break;
case CC_OP_CMP:
tcg_gen_sub_tl(dst, a, b);
/* Extended arithmetics. */
t_gen_subx_carry(dc, dst);
break;
default:
qemu_log("illegal ALU op.\n");
BUG();
break;
}
if (size == 1) {
tcg_gen_andi_tl(dst, dst, 0xff);
} else if (size == 2) {
tcg_gen_andi_tl(dst, dst, 0xffff);
}
}
| false | qemu | 42a268c241183877192c376d03bd9b6d527407c7 | static void cris_alu_op_exec(DisasContext *dc, int op,
TCGv dst, TCGv a, TCGv b, int size)
{
switch (op) {
case CC_OP_ADD:
tcg_gen_add_tl(dst, a, b);
t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
tcg_gen_add_tl(dst, a, b);
t_gen_add_flag(dst, 0);
break;
case CC_OP_MCP:
tcg_gen_add_tl(dst, a, b);
t_gen_add_flag(dst, 8);
break;
case CC_OP_SUB:
tcg_gen_sub_tl(dst, a, b);
t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
tcg_gen_mov_tl(dst, b);
break;
case CC_OP_OR:
tcg_gen_or_tl(dst, a, b);
break;
case CC_OP_AND:
tcg_gen_and_tl(dst, a, b);
break;
case CC_OP_XOR:
tcg_gen_xor_tl(dst, a, b);
break;
case CC_OP_LSL:
t_gen_lsl(dst, a, b);
break;
case CC_OP_LSR:
t_gen_lsr(dst, a, b);
break;
case CC_OP_ASR:
t_gen_asr(dst, a, b);
break;
case CC_OP_NEG:
tcg_gen_neg_tl(dst, b);
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
gen_helper_lz(dst, b);
break;
case CC_OP_MULS:
tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
break;
case CC_OP_MULU:
tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
break;
case CC_OP_DSTEP:
t_gen_cris_dstep(dst, a, b);
break;
case CC_OP_MSTEP:
t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
break;
case CC_OP_BOUND:
{
int l1;
l1 = gen_new_label();
tcg_gen_mov_tl(dst, a);
tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
tcg_gen_mov_tl(dst, b);
gen_set_label(l1);
}
break;
case CC_OP_CMP:
tcg_gen_sub_tl(dst, a, b);
t_gen_subx_carry(dc, dst);
break;
default:
qemu_log("illegal ALU op.\n");
BUG();
break;
}
if (size == 1) {
tcg_gen_andi_tl(dst, dst, 0xff);
} else if (size == 2) {
tcg_gen_andi_tl(dst, dst, 0xffff);
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(DisasContext *VAR_0, int VAR_1,
TCGv VAR_2, TCGv VAR_3, TCGv VAR_4, int VAR_5)
{
switch (VAR_1) {
case CC_OP_ADD:
tcg_gen_add_tl(VAR_2, VAR_3, VAR_4);
t_gen_addx_carry(VAR_0, VAR_2);
break;
case CC_OP_ADDC:
tcg_gen_add_tl(VAR_2, VAR_3, VAR_4);
t_gen_add_flag(VAR_2, 0);
break;
case CC_OP_MCP:
tcg_gen_add_tl(VAR_2, VAR_3, VAR_4);
t_gen_add_flag(VAR_2, 8);
break;
case CC_OP_SUB:
tcg_gen_sub_tl(VAR_2, VAR_3, VAR_4);
t_gen_subx_carry(VAR_0, VAR_2);
break;
case CC_OP_MOVE:
tcg_gen_mov_tl(VAR_2, VAR_4);
break;
case CC_OP_OR:
tcg_gen_or_tl(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_AND:
tcg_gen_and_tl(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_XOR:
tcg_gen_xor_tl(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_LSL:
t_gen_lsl(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_LSR:
t_gen_lsr(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_ASR:
t_gen_asr(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_NEG:
tcg_gen_neg_tl(VAR_2, VAR_4);
t_gen_subx_carry(VAR_0, VAR_2);
break;
case CC_OP_LZ:
gen_helper_lz(VAR_2, VAR_4);
break;
case CC_OP_MULS:
tcg_gen_muls2_tl(VAR_2, cpu_PR[PR_MOF], VAR_3, VAR_4);
break;
case CC_OP_MULU:
tcg_gen_mulu2_tl(VAR_2, cpu_PR[PR_MOF], VAR_3, VAR_4);
break;
case CC_OP_DSTEP:
t_gen_cris_dstep(VAR_2, VAR_3, VAR_4);
break;
case CC_OP_MSTEP:
t_gen_cris_mstep(VAR_2, VAR_3, VAR_4, cpu_PR[PR_CCS]);
break;
case CC_OP_BOUND:
{
int VAR_6;
VAR_6 = gen_new_label();
tcg_gen_mov_tl(VAR_2, VAR_3);
tcg_gen_brcond_tl(TCG_COND_LEU, VAR_3, VAR_4, VAR_6);
tcg_gen_mov_tl(VAR_2, VAR_4);
gen_set_label(VAR_6);
}
break;
case CC_OP_CMP:
tcg_gen_sub_tl(VAR_2, VAR_3, VAR_4);
t_gen_subx_carry(VAR_0, VAR_2);
break;
default:
qemu_log("illegal ALU VAR_1.\n");
BUG();
break;
}
if (VAR_5 == 1) {
tcg_gen_andi_tl(VAR_2, VAR_2, 0xff);
} else if (VAR_5 == 2) {
tcg_gen_andi_tl(VAR_2, VAR_2, 0xffff);
}
}
| [
"static void FUNC_0(DisasContext *VAR_0, int VAR_1,\nTCGv VAR_2, TCGv VAR_3, TCGv VAR_4, int VAR_5)\n{",
"switch (VAR_1) {",
"case CC_OP_ADD:\ntcg_gen_add_tl(VAR_2, VAR_3, VAR_4);",
"t_gen_addx_carry(VAR_0, VAR_2);",
"break;",
"case CC_OP_ADDC:\ntcg_gen_add_tl(VAR_2, VAR_3, VAR_4);",
"t_gen_add_flag(VAR_2, 0);",
"break;",
"case CC_OP_MCP:\ntcg_gen_add_tl(VAR_2, VAR_3, VAR_4);",
"t_gen_add_flag(VAR_2, 8);",
"break;",
"case CC_OP_SUB:\ntcg_gen_sub_tl(VAR_2, VAR_3, VAR_4);",
"t_gen_subx_carry(VAR_0, VAR_2);",
"break;",
"case CC_OP_MOVE:\ntcg_gen_mov_tl(VAR_2, VAR_4);",
"break;",
"case CC_OP_OR:\ntcg_gen_or_tl(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_AND:\ntcg_gen_and_tl(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_XOR:\ntcg_gen_xor_tl(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_LSL:\nt_gen_lsl(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_LSR:\nt_gen_lsr(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_ASR:\nt_gen_asr(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_NEG:\ntcg_gen_neg_tl(VAR_2, VAR_4);",
"t_gen_subx_carry(VAR_0, VAR_2);",
"break;",
"case CC_OP_LZ:\ngen_helper_lz(VAR_2, VAR_4);",
"break;",
"case CC_OP_MULS:\ntcg_gen_muls2_tl(VAR_2, cpu_PR[PR_MOF], VAR_3, VAR_4);",
"break;",
"case CC_OP_MULU:\ntcg_gen_mulu2_tl(VAR_2, cpu_PR[PR_MOF], VAR_3, VAR_4);",
"break;",
"case CC_OP_DSTEP:\nt_gen_cris_dstep(VAR_2, VAR_3, VAR_4);",
"break;",
"case CC_OP_MSTEP:\nt_gen_cris_mstep(VAR_2, VAR_3, VAR_4, cpu_PR[PR_CCS]);",
"break;",
"case CC_OP_BOUND:\n{",
"int VAR_6;",
"VAR_6 = gen_new_label();",
"tcg_gen_mov_tl(VAR_2, VAR_3);",
"tcg_gen_brcond_tl(TCG_COND_LEU, VAR_3, VAR_4, VAR_6);",
"tcg_gen_mov_tl(VAR_2, VAR_4);",
"gen_set_label(VAR_6);",
"}",
"break;",
"case CC_OP_CMP:\ntcg_gen_sub_tl(VAR_2, VAR_3, VAR_4);",
"t_gen_subx_carry(VAR_0, VAR_2);",
"break;",
"default:\nqemu_log(\"illegal ALU VAR_1.\\n\");",
"BUG();",
"break;",
"}",
"if (VAR_5 == 1) {",
"tcg_gen_andi_tl(VAR_2, VAR_2, 0xff);",
"} else if (VAR_5 == 2) {",
"tcg_gen_andi_tl(VAR_2, VAR_2, 0xffff);",
"}",
"}"
]
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[
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[
9
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[
11,
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],
[
17
],
[
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],
[
21,
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],
[
25
],
[
27
],
[
29,
31
],
[
33
],
[
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],
[
37,
39
],
[
43
],
[
45
],
[
47,
49
],
[
51
],
[
53,
55
],
[
57
],
[
59,
61
],
[
63
],
[
65,
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[
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],
[
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[
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],
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[
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],
[
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[
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],
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175
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177
],
[
179
],
[
181
]
]
|
10,300 | static void blockdev_backup_prepare(BlkTransactionState *common, Error **errp)
{
BlockdevBackupState *state = DO_UPCAST(BlockdevBackupState, common, common);
BlockdevBackup *backup;
BlockBackend *blk, *target;
Error *local_err = NULL;
assert(common->action->kind == TRANSACTION_ACTION_KIND_BLOCKDEV_BACKUP);
backup = common->action->blockdev_backup;
blk = blk_by_name(backup->device);
if (!blk) {
error_setg(errp, "Device '%s' not found", backup->device);
return;
}
if (!blk_is_available(blk)) {
error_setg(errp, QERR_DEVICE_HAS_NO_MEDIUM, backup->device);
return;
}
target = blk_by_name(backup->target);
if (!target) {
error_setg(errp, "Device '%s' not found", backup->target);
return;
}
/* AioContext is released in .clean() */
state->aio_context = blk_get_aio_context(blk);
if (state->aio_context != blk_get_aio_context(target)) {
state->aio_context = NULL;
error_setg(errp, "Backup between two IO threads is not implemented");
return;
}
aio_context_acquire(state->aio_context);
state->bs = blk_bs(blk);
bdrv_drained_begin(state->bs);
qmp_blockdev_backup(backup->device, backup->target,
backup->sync,
backup->has_speed, backup->speed,
backup->has_on_source_error, backup->on_source_error,
backup->has_on_target_error, backup->on_target_error,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
state->job = state->bs->job;
}
| false | qemu | 6a8f9661dc3c088ed0d2f5b41d940190407cbdc5 | static void blockdev_backup_prepare(BlkTransactionState *common, Error **errp)
{
BlockdevBackupState *state = DO_UPCAST(BlockdevBackupState, common, common);
BlockdevBackup *backup;
BlockBackend *blk, *target;
Error *local_err = NULL;
assert(common->action->kind == TRANSACTION_ACTION_KIND_BLOCKDEV_BACKUP);
backup = common->action->blockdev_backup;
blk = blk_by_name(backup->device);
if (!blk) {
error_setg(errp, "Device '%s' not found", backup->device);
return;
}
if (!blk_is_available(blk)) {
error_setg(errp, QERR_DEVICE_HAS_NO_MEDIUM, backup->device);
return;
}
target = blk_by_name(backup->target);
if (!target) {
error_setg(errp, "Device '%s' not found", backup->target);
return;
}
state->aio_context = blk_get_aio_context(blk);
if (state->aio_context != blk_get_aio_context(target)) {
state->aio_context = NULL;
error_setg(errp, "Backup between two IO threads is not implemented");
return;
}
aio_context_acquire(state->aio_context);
state->bs = blk_bs(blk);
bdrv_drained_begin(state->bs);
qmp_blockdev_backup(backup->device, backup->target,
backup->sync,
backup->has_speed, backup->speed,
backup->has_on_source_error, backup->on_source_error,
backup->has_on_target_error, backup->on_target_error,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
state->job = state->bs->job;
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(BlkTransactionState *VAR_0, Error **VAR_1)
{
BlockdevBackupState *state = DO_UPCAST(BlockdevBackupState, VAR_0, VAR_0);
BlockdevBackup *backup;
BlockBackend *blk, *target;
Error *local_err = NULL;
assert(VAR_0->action->kind == TRANSACTION_ACTION_KIND_BLOCKDEV_BACKUP);
backup = VAR_0->action->blockdev_backup;
blk = blk_by_name(backup->device);
if (!blk) {
error_setg(VAR_1, "Device '%s' not found", backup->device);
return;
}
if (!blk_is_available(blk)) {
error_setg(VAR_1, QERR_DEVICE_HAS_NO_MEDIUM, backup->device);
return;
}
target = blk_by_name(backup->target);
if (!target) {
error_setg(VAR_1, "Device '%s' not found", backup->target);
return;
}
state->aio_context = blk_get_aio_context(blk);
if (state->aio_context != blk_get_aio_context(target)) {
state->aio_context = NULL;
error_setg(VAR_1, "Backup between two IO threads is not implemented");
return;
}
aio_context_acquire(state->aio_context);
state->bs = blk_bs(blk);
bdrv_drained_begin(state->bs);
qmp_blockdev_backup(backup->device, backup->target,
backup->sync,
backup->has_speed, backup->speed,
backup->has_on_source_error, backup->on_source_error,
backup->has_on_target_error, backup->on_target_error,
&local_err);
if (local_err) {
error_propagate(VAR_1, local_err);
return;
}
state->job = state->bs->job;
}
| [
"static void FUNC_0(BlkTransactionState *VAR_0, Error **VAR_1)\n{",
"BlockdevBackupState *state = DO_UPCAST(BlockdevBackupState, VAR_0, VAR_0);",
"BlockdevBackup *backup;",
"BlockBackend *blk, *target;",
"Error *local_err = NULL;",
"assert(VAR_0->action->kind == TRANSACTION_ACTION_KIND_BLOCKDEV_BACKUP);",
"backup = VAR_0->action->blockdev_backup;",
"blk = blk_by_name(backup->device);",
"if (!blk) {",
"error_setg(VAR_1, \"Device '%s' not found\", backup->device);",
"return;",
"}",
"if (!blk_is_available(blk)) {",
"error_setg(VAR_1, QERR_DEVICE_HAS_NO_MEDIUM, backup->device);",
"return;",
"}",
"target = blk_by_name(backup->target);",
"if (!target) {",
"error_setg(VAR_1, \"Device '%s' not found\", backup->target);",
"return;",
"}",
"state->aio_context = blk_get_aio_context(blk);",
"if (state->aio_context != blk_get_aio_context(target)) {",
"state->aio_context = NULL;",
"error_setg(VAR_1, \"Backup between two IO threads is not implemented\");",
"return;",
"}",
"aio_context_acquire(state->aio_context);",
"state->bs = blk_bs(blk);",
"bdrv_drained_begin(state->bs);",
"qmp_blockdev_backup(backup->device, backup->target,\nbackup->sync,\nbackup->has_speed, backup->speed,\nbackup->has_on_source_error, backup->on_source_error,\nbackup->has_on_target_error, backup->on_target_error,\n&local_err);",
"if (local_err) {",
"error_propagate(VAR_1, local_err);",
"return;",
"}",
"state->job = state->bs->job;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
33
],
[
35
],
[
37
],
[
39
],
[
43
],
[
45
],
[
47
],
[
49
],
[
51
],
[
57
],
[
59
],
[
61
],
[
63
],
[
65
],
[
67
],
[
69
],
[
71
],
[
73
],
[
77,
79,
81,
83,
85,
87
],
[
89
],
[
91
],
[
93
],
[
95
],
[
99
],
[
101
]
]
|
10,301 | static int zipl_magic(uint8_t *ptr)
{
uint32_t *p = (void*)ptr;
uint32_t *z = (void*)ZIPL_MAGIC;
if (*p != *z) {
debug_print_int("invalid magic", *p);
virtio_panic("invalid magic");
}
return 1;
}
| false | qemu | abd696e4f74a9d30801c6ae2693efe4e5979c2f2 | static int zipl_magic(uint8_t *ptr)
{
uint32_t *p = (void*)ptr;
uint32_t *z = (void*)ZIPL_MAGIC;
if (*p != *z) {
debug_print_int("invalid magic", *p);
virtio_panic("invalid magic");
}
return 1;
}
| {
"code": [],
"line_no": []
} | static int FUNC_0(uint8_t *VAR_0)
{
uint32_t *p = (void*)VAR_0;
uint32_t *z = (void*)ZIPL_MAGIC;
if (*p != *z) {
debug_print_int("invalid magic", *p);
virtio_panic("invalid magic");
}
return 1;
}
| [
"static int FUNC_0(uint8_t *VAR_0)\n{",
"uint32_t *p = (void*)VAR_0;",
"uint32_t *z = (void*)ZIPL_MAGIC;",
"if (*p != *z) {",
"debug_print_int(\"invalid magic\", *p);",
"virtio_panic(\"invalid magic\");",
"}",
"return 1;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
]
]
|
10,302 | static void bt_hid_interrupt_sdu(void *opaque, const uint8_t *data, int len)
{
struct bt_hid_device_s *hid = opaque;
if (len > BT_HID_MTU || len < 1)
goto bad;
if ((data[0] & 3) != BT_DATA_OUTPUT)
goto bad;
if ((data[0] >> 4) == BT_DATA) {
if (hid->intr_state)
goto bad;
hid->data_type = BT_DATA_OUTPUT;
hid->intrdataout.len = 0;
} else if ((data[0] >> 4) == BT_DATC) {
if (!hid->intr_state)
goto bad;
} else
goto bad;
memcpy(hid->intrdataout.buffer + hid->intrdataout.len, data + 1, len - 1);
hid->intrdataout.len += len - 1;
hid->intr_state = (len == BT_HID_MTU);
if (!hid->intr_state) {
memcpy(hid->dataout.buffer, hid->intrdataout.buffer,
hid->dataout.len = hid->intrdataout.len);
bt_hid_out(hid);
}
return;
bad:
fprintf(stderr, "%s: bad transaction on Interrupt channel.\n",
__func__);
}
| false | qemu | bf937a7965c1d1a6dce4f615d0ead2e2ab505004 | static void bt_hid_interrupt_sdu(void *opaque, const uint8_t *data, int len)
{
struct bt_hid_device_s *hid = opaque;
if (len > BT_HID_MTU || len < 1)
goto bad;
if ((data[0] & 3) != BT_DATA_OUTPUT)
goto bad;
if ((data[0] >> 4) == BT_DATA) {
if (hid->intr_state)
goto bad;
hid->data_type = BT_DATA_OUTPUT;
hid->intrdataout.len = 0;
} else if ((data[0] >> 4) == BT_DATC) {
if (!hid->intr_state)
goto bad;
} else
goto bad;
memcpy(hid->intrdataout.buffer + hid->intrdataout.len, data + 1, len - 1);
hid->intrdataout.len += len - 1;
hid->intr_state = (len == BT_HID_MTU);
if (!hid->intr_state) {
memcpy(hid->dataout.buffer, hid->intrdataout.buffer,
hid->dataout.len = hid->intrdataout.len);
bt_hid_out(hid);
}
return;
bad:
fprintf(stderr, "%s: bad transaction on Interrupt channel.\n",
__func__);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void *VAR_0, const uint8_t *VAR_1, int VAR_2)
{
struct bt_hid_device_s *VAR_3 = VAR_0;
if (VAR_2 > BT_HID_MTU || VAR_2 < 1)
goto bad;
if ((VAR_1[0] & 3) != BT_DATA_OUTPUT)
goto bad;
if ((VAR_1[0] >> 4) == BT_DATA) {
if (VAR_3->intr_state)
goto bad;
VAR_3->data_type = BT_DATA_OUTPUT;
VAR_3->intrdataout.VAR_2 = 0;
} else if ((VAR_1[0] >> 4) == BT_DATC) {
if (!VAR_3->intr_state)
goto bad;
} else
goto bad;
memcpy(VAR_3->intrdataout.buffer + VAR_3->intrdataout.VAR_2, VAR_1 + 1, VAR_2 - 1);
VAR_3->intrdataout.VAR_2 += VAR_2 - 1;
VAR_3->intr_state = (VAR_2 == BT_HID_MTU);
if (!VAR_3->intr_state) {
memcpy(VAR_3->dataout.buffer, VAR_3->intrdataout.buffer,
VAR_3->dataout.VAR_2 = VAR_3->intrdataout.VAR_2);
bt_hid_out(VAR_3);
}
return;
bad:
fprintf(stderr, "%s: bad transaction on Interrupt channel.\n",
__func__);
}
| [
"static void FUNC_0(void *VAR_0, const uint8_t *VAR_1, int VAR_2)\n{",
"struct bt_hid_device_s *VAR_3 = VAR_0;",
"if (VAR_2 > BT_HID_MTU || VAR_2 < 1)\ngoto bad;",
"if ((VAR_1[0] & 3) != BT_DATA_OUTPUT)\ngoto bad;",
"if ((VAR_1[0] >> 4) == BT_DATA) {",
"if (VAR_3->intr_state)\ngoto bad;",
"VAR_3->data_type = BT_DATA_OUTPUT;",
"VAR_3->intrdataout.VAR_2 = 0;",
"} else if ((VAR_1[0] >> 4) == BT_DATC) {",
"if (!VAR_3->intr_state)\ngoto bad;",
"} else",
"goto bad;",
"memcpy(VAR_3->intrdataout.buffer + VAR_3->intrdataout.VAR_2, VAR_1 + 1, VAR_2 - 1);",
"VAR_3->intrdataout.VAR_2 += VAR_2 - 1;",
"VAR_3->intr_state = (VAR_2 == BT_HID_MTU);",
"if (!VAR_3->intr_state) {",
"memcpy(VAR_3->dataout.buffer, VAR_3->intrdataout.buffer,\nVAR_3->dataout.VAR_2 = VAR_3->intrdataout.VAR_2);",
"bt_hid_out(VAR_3);",
"}",
"return;",
"bad:\nfprintf(stderr, \"%s: bad transaction on Interrupt channel.\\n\",\n__func__);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9,
11
],
[
13,
15
],
[
17
],
[
19,
21
],
[
25
],
[
27
],
[
29
],
[
31,
33
],
[
35
],
[
37
],
[
41
],
[
43
],
[
45
],
[
47
],
[
49,
51
],
[
53
],
[
55
],
[
59
],
[
61,
63,
65
],
[
67
]
]
|
10,303 | static void decode_opc (CPUState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1, op2;
int16_t imm;
/* make sure instructions are on a word boundary */
if (ctx->pc & 0x3) {
env->CP0_BadVAddr = ctx->pc;
generate_exception(ctx, EXCP_AdEL);
return;
}
if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
int l1;
/* Handle blikely not taken case */
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
l1 = gen_new_label();
gen_op_jnz_T2(l1);
gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
}
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
sa = (ctx->opcode >> 6) & 0x1f;
imm = (int16_t)ctx->opcode;
switch (op) {
case OPC_SPECIAL:
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_SLL: /* Arithmetic with immediate */
case OPC_SRL ... OPC_SRA:
gen_arith_imm(env, ctx, op1, rd, rt, sa);
break;
case OPC_MOVZ ... OPC_MOVN:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
case OPC_SLLV: /* Arithmetic */
case OPC_SRLV ... OPC_SRAV:
case OPC_ADD ... OPC_NOR:
case OPC_SLT ... OPC_SLTU:
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_MULT ... OPC_DIVU:
gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_JR ... OPC_JALR:
gen_compute_branch(ctx, op1, rs, rd, sa);
return;
case OPC_TGE ... OPC_TEQ: /* Traps */
case OPC_TNE:
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_MFHI: /* Move from HI/LO */
case OPC_MFLO:
gen_HILO(ctx, op1, rd);
break;
case OPC_MTHI:
case OPC_MTLO: /* Move to HI/LO */
gen_HILO(ctx, op1, rs);
break;
case OPC_PMON: /* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
generate_exception(ctx, EXCP_RI);
#else
gen_op_pmon(sa);
#endif
break;
case OPC_SYSCALL:
generate_exception(ctx, EXCP_SYSCALL);
break;
case OPC_BREAK:
generate_exception(ctx, EXCP_BREAK);
break;
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
generate_exception(ctx, EXCP_RI);
#else
/* Implemented as RI exception for now. */
MIPS_INVAL("spim (unofficial)");
generate_exception(ctx, EXCP_RI);
#endif
break;
case OPC_SYNC:
/* Treat as NOP. */
break;
case OPC_MOVCI:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
(ctx->opcode >> 16) & 1);
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
case OPC_DSLL32:
case OPC_DSRL32 ... OPC_DSRA32:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith_imm(env, ctx, op1, rd, rt, sa);
break;
case OPC_DSLLV:
case OPC_DSRLV ... OPC_DSRAV:
case OPC_DADD ... OPC_DSUBU:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_DMULT ... OPC_DDIVU:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_muldiv(ctx, op1, rs, rt);
break;
#endif
default: /* Invalid */
MIPS_INVAL("special");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_SPECIAL2:
op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) {
case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
case OPC_MSUB ... OPC_MSUBU:
check_insn(env, ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_MUL:
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_CLZ ... OPC_CLO:
check_insn(env, ctx, ISA_MIPS32);
gen_cl(ctx, op1, rd, rs);
break;
case OPC_SDBBP:
/* XXX: not clear which exception should be raised
* when in debug mode...
*/
check_insn(env, ctx, ISA_MIPS32);
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
generate_exception(ctx, EXCP_DBp);
} else {
generate_exception(ctx, EXCP_DBp);
}
/* Treat as NOP. */
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO:
check_insn(env, ctx, ISA_MIPS64);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
#endif
default: /* Invalid */
MIPS_INVAL("special2");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_SPECIAL3:
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
case OPC_EXT:
case OPC_INS:
check_insn(env, ctx, ISA_MIPS32R2);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
check_insn(env, ctx, ISA_MIPS32R2);
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_WSBH:
GEN_LOAD_REG_TN(T1, rt);
gen_op_wsbh();
break;
case OPC_SEB:
GEN_LOAD_REG_TN(T1, rt);
gen_op_seb();
break;
case OPC_SEH:
GEN_LOAD_REG_TN(T1, rt);
gen_op_seh();
break;
default: /* Invalid */
MIPS_INVAL("bshfl");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rd, T0);
break;
case OPC_RDHWR:
check_insn(env, ctx, ISA_MIPS32R2);
switch (rd) {
case 0:
save_cpu_state(ctx, 1);
gen_op_rdhwr_cpunum();
break;
case 1:
save_cpu_state(ctx, 1);
gen_op_rdhwr_synci_step();
break;
case 2:
save_cpu_state(ctx, 1);
gen_op_rdhwr_cc();
break;
case 3:
save_cpu_state(ctx, 1);
gen_op_rdhwr_ccres();
break;
case 29:
#if defined (CONFIG_USER_ONLY)
gen_op_tls_value();
break;
#endif
default: /* Invalid */
MIPS_INVAL("rdhwr");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rt, T0);
break;
case OPC_FORK:
check_mips_mt(env, ctx);
GEN_LOAD_REG_TN(T0, rt);
GEN_LOAD_REG_TN(T1, rs);
gen_op_fork();
break;
case OPC_YIELD:
check_mips_mt(env, ctx);
GEN_LOAD_REG_TN(T0, rs);
gen_op_yield();
GEN_STORE_TN_REG(rd, T0);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_DBSHFL:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DSBH:
GEN_LOAD_REG_TN(T1, rt);
gen_op_dsbh();
break;
case OPC_DSHD:
GEN_LOAD_REG_TN(T1, rt);
gen_op_dshd();
break;
default: /* Invalid */
MIPS_INVAL("dbshfl");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rd, T0);
#endif
default: /* Invalid */
MIPS_INVAL("special3");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
switch (op1) {
case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
case OPC_BLTZAL ... OPC_BGEZALL:
gen_compute_branch(ctx, op1, rs, -1, imm << 2);
return;
case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
case OPC_TNEI:
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SYNCI:
check_insn(env, ctx, ISA_MIPS32R2);
/* Treat as NOP. */
break;
default: /* Invalid */
MIPS_INVAL("regimm");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_CP0:
check_cp0_enabled(ctx);
op1 = MASK_CP0(ctx->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
case OPC_MFTR:
case OPC_MTTR:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
gen_cp0(env, ctx, op1, rt, rd);
break;
case OPC_C0_FIRST ... OPC_C0_LAST:
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
break;
case OPC_MFMC0:
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_mips_mt(env, ctx);
gen_op_dmt();
break;
case OPC_EMT:
check_mips_mt(env, ctx);
gen_op_emt();
break;
case OPC_DVPE:
check_mips_mt(env, ctx);
gen_op_dvpe();
break;
case OPC_EVPE:
check_mips_mt(env, ctx);
gen_op_evpe();
break;
case OPC_DI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
gen_op_di();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case OPC_EI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
gen_op_ei();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rt, T0);
break;
case OPC_RDPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
GEN_LOAD_SRSREG_TN(T0, rt);
GEN_STORE_TN_REG(rd, T0);
break;
case OPC_WRPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
GEN_LOAD_REG_TN(T0, rt);
GEN_STORE_TN_SRSREG(rd, T0);
break;
default:
MIPS_INVAL("cp0");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */
gen_arith_imm(env, ctx, op, rt, rs, imm);
break;
case OPC_J ... OPC_JAL: /* Jump */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, rs, rt, offset);
return;
case OPC_BEQ ... OPC_BGTZ: /* Branch */
case OPC_BEQL ... OPC_BGTZL:
gen_compute_branch(ctx, op, rs, rt, imm << 2);
return;
case OPC_LB ... OPC_LWR: /* Load and stores */
case OPC_SB ... OPC_SW:
case OPC_SWR:
case OPC_LL:
case OPC_SC:
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
/* Treat as NOP. */
break;
case OPC_PREF:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
/* Treat as NOP. */
break;
/* Floating point (COP1). */
case OPC_LWC1:
case OPC_LDC1:
case OPC_SWC1:
case OPC_SDC1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
gen_flt_ldst(ctx, op, rt, rs, imm);
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
case OPC_CP1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
op1 = MASK_CP1(ctx->opcode);
switch (op1) {
case OPC_MFHC1:
case OPC_MTHC1:
check_insn(env, ctx, ISA_MIPS32R2);
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
case OPC_CTC1:
gen_cp1(ctx, op1, rt, rd);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
check_insn(env, ctx, ISA_MIPS3);
gen_cp1(ctx, op1, rt, rd);
break;
#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
check_cp1_3d(env, ctx);
/* fall through */
case OPC_BC1:
gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
return;
case OPC_S_FMT:
case OPC_D_FMT:
case OPC_W_FMT:
case OPC_L_FMT:
case OPC_PS_FMT:
gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
(imm >> 8) & 0x7);
break;
default:
MIPS_INVAL("cp1");
generate_exception (ctx, EXCP_RI);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
/* COP2. */
case OPC_LWC2:
case OPC_LDC2:
case OPC_SWC2:
case OPC_SDC2:
case OPC_CP2:
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
break;
case OPC_CP3:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
switch (op1) {
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_LUXC1:
case OPC_SWXC1:
case OPC_SDXC1:
case OPC_SUXC1:
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
/* Treat as NOP. */
break;
case OPC_ALNV_PS:
case OPC_MADD_S:
case OPC_MADD_D:
case OPC_MADD_PS:
case OPC_MSUB_S:
case OPC_MSUB_D:
case OPC_MSUB_PS:
case OPC_NMADD_S:
case OPC_NMADD_D:
case OPC_NMADD_PS:
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
MIPS_INVAL("cp3");
generate_exception (ctx, EXCP_RI);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
case OPC_SDL ... OPC_SDR:
case OPC_LLD:
case OPC_LD:
case OPC_SCD:
case OPC_SD:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_DADDI ... OPC_DADDIU:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith_imm(env, ctx, op, rt, rs, imm);
break;
#endif
case OPC_JALX:
check_insn(env, ctx, ASE_MIPS16);
/* MIPS16: Not implemented. */
case OPC_MDMX:
check_insn(env, ctx, ASE_MDMX);
/* MDMX: Not implemented. */
default: /* Invalid */
MIPS_INVAL("major opcode");
generate_exception(ctx, EXCP_RI);
break;
}
if (ctx->hflags & MIPS_HFLAG_BMASK) {
int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
/* Branches completion */
ctx->hflags &= ~MIPS_HFLAG_BMASK;
ctx->bstate = BS_BRANCH;
save_cpu_state(ctx, 0);
switch (hflags) {
case MIPS_HFLAG_B:
/* unconditional branch */
MIPS_DEBUG("unconditional branch");
gen_goto_tb(ctx, 0, ctx->btarget);
break;
case MIPS_HFLAG_BL:
/* blikely taken case */
MIPS_DEBUG("blikely branch taken");
gen_goto_tb(ctx, 0, ctx->btarget);
break;
case MIPS_HFLAG_BC:
/* Conditional branch */
MIPS_DEBUG("conditional branch");
{
int l1;
l1 = gen_new_label();
gen_op_jnz_T2(l1);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
gen_goto_tb(ctx, 0, ctx->btarget);
}
break;
case MIPS_HFLAG_BR:
/* unconditional branch to register */
MIPS_DEBUG("branch to register");
gen_op_breg();
gen_op_reset_T0();
gen_op_exit_tb();
break;
default:
MIPS_DEBUG("unknown branch");
break;
}
}
}
| false | qemu | 7385ac0ba2456159a52b9b2cbb5f6c71921d0c23 | static void decode_opc (CPUState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1, op2;
int16_t imm;
if (ctx->pc & 0x3) {
env->CP0_BadVAddr = ctx->pc;
generate_exception(ctx, EXCP_AdEL);
return;
}
if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
int l1;
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
l1 = gen_new_label();
gen_op_jnz_T2(l1);
gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
}
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
sa = (ctx->opcode >> 6) & 0x1f;
imm = (int16_t)ctx->opcode;
switch (op) {
case OPC_SPECIAL:
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_SLL:
case OPC_SRL ... OPC_SRA:
gen_arith_imm(env, ctx, op1, rd, rt, sa);
break;
case OPC_MOVZ ... OPC_MOVN:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
case OPC_SLLV:
case OPC_SRLV ... OPC_SRAV:
case OPC_ADD ... OPC_NOR:
case OPC_SLT ... OPC_SLTU:
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_MULT ... OPC_DIVU:
gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_JR ... OPC_JALR:
gen_compute_branch(ctx, op1, rs, rd, sa);
return;
case OPC_TGE ... OPC_TEQ:
case OPC_TNE:
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_MFHI:
case OPC_MFLO:
gen_HILO(ctx, op1, rd);
break;
case OPC_MTHI:
case OPC_MTLO:
gen_HILO(ctx, op1, rs);
break;
case OPC_PMON:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
generate_exception(ctx, EXCP_RI);
#else
gen_op_pmon(sa);
#endif
break;
case OPC_SYSCALL:
generate_exception(ctx, EXCP_SYSCALL);
break;
case OPC_BREAK:
generate_exception(ctx, EXCP_BREAK);
break;
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
generate_exception(ctx, EXCP_RI);
#else
MIPS_INVAL("spim (unofficial)");
generate_exception(ctx, EXCP_RI);
#endif
break;
case OPC_SYNC:
break;
case OPC_MOVCI:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
(ctx->opcode >> 16) & 1);
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
case OPC_DSLL32:
case OPC_DSRL32 ... OPC_DSRA32:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith_imm(env, ctx, op1, rd, rt, sa);
break;
case OPC_DSLLV:
case OPC_DSRLV ... OPC_DSRAV:
case OPC_DADD ... OPC_DSUBU:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_DMULT ... OPC_DDIVU:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_muldiv(ctx, op1, rs, rt);
break;
#endif
default:
MIPS_INVAL("special");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_SPECIAL2:
op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) {
case OPC_MADD ... OPC_MADDU:
case OPC_MSUB ... OPC_MSUBU:
check_insn(env, ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_MUL:
gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_CLZ ... OPC_CLO:
check_insn(env, ctx, ISA_MIPS32);
gen_cl(ctx, op1, rd, rs);
break;
case OPC_SDBBP:
check_insn(env, ctx, ISA_MIPS32);
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
generate_exception(ctx, EXCP_DBp);
} else {
generate_exception(ctx, EXCP_DBp);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO:
check_insn(env, ctx, ISA_MIPS64);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
#endif
default:
MIPS_INVAL("special2");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_SPECIAL3:
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
case OPC_EXT:
case OPC_INS:
check_insn(env, ctx, ISA_MIPS32R2);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
check_insn(env, ctx, ISA_MIPS32R2);
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_WSBH:
GEN_LOAD_REG_TN(T1, rt);
gen_op_wsbh();
break;
case OPC_SEB:
GEN_LOAD_REG_TN(T1, rt);
gen_op_seb();
break;
case OPC_SEH:
GEN_LOAD_REG_TN(T1, rt);
gen_op_seh();
break;
default:
MIPS_INVAL("bshfl");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rd, T0);
break;
case OPC_RDHWR:
check_insn(env, ctx, ISA_MIPS32R2);
switch (rd) {
case 0:
save_cpu_state(ctx, 1);
gen_op_rdhwr_cpunum();
break;
case 1:
save_cpu_state(ctx, 1);
gen_op_rdhwr_synci_step();
break;
case 2:
save_cpu_state(ctx, 1);
gen_op_rdhwr_cc();
break;
case 3:
save_cpu_state(ctx, 1);
gen_op_rdhwr_ccres();
break;
case 29:
#if defined (CONFIG_USER_ONLY)
gen_op_tls_value();
break;
#endif
default:
MIPS_INVAL("rdhwr");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rt, T0);
break;
case OPC_FORK:
check_mips_mt(env, ctx);
GEN_LOAD_REG_TN(T0, rt);
GEN_LOAD_REG_TN(T1, rs);
gen_op_fork();
break;
case OPC_YIELD:
check_mips_mt(env, ctx);
GEN_LOAD_REG_TN(T0, rs);
gen_op_yield();
GEN_STORE_TN_REG(rd, T0);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_DBSHFL:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DSBH:
GEN_LOAD_REG_TN(T1, rt);
gen_op_dsbh();
break;
case OPC_DSHD:
GEN_LOAD_REG_TN(T1, rt);
gen_op_dshd();
break;
default:
MIPS_INVAL("dbshfl");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rd, T0);
#endif
default:
MIPS_INVAL("special3");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
switch (op1) {
case OPC_BLTZ ... OPC_BGEZL:
case OPC_BLTZAL ... OPC_BGEZALL:
gen_compute_branch(ctx, op1, rs, -1, imm << 2);
return;
case OPC_TGEI ... OPC_TEQI:
case OPC_TNEI:
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SYNCI:
check_insn(env, ctx, ISA_MIPS32R2);
break;
default:
MIPS_INVAL("regimm");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_CP0:
check_cp0_enabled(ctx);
op1 = MASK_CP0(ctx->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
case OPC_MFTR:
case OPC_MTTR:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
gen_cp0(env, ctx, op1, rt, rd);
break;
case OPC_C0_FIRST ... OPC_C0_LAST:
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
break;
case OPC_MFMC0:
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_mips_mt(env, ctx);
gen_op_dmt();
break;
case OPC_EMT:
check_mips_mt(env, ctx);
gen_op_emt();
break;
case OPC_DVPE:
check_mips_mt(env, ctx);
gen_op_dvpe();
break;
case OPC_EVPE:
check_mips_mt(env, ctx);
gen_op_evpe();
break;
case OPC_DI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
gen_op_di();
ctx->bstate = BS_STOP;
break;
case OPC_EI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
gen_op_ei();
ctx->bstate = BS_STOP;
break;
default:
MIPS_INVAL("mfmc0");
generate_exception(ctx, EXCP_RI);
break;
}
GEN_STORE_TN_REG(rt, T0);
break;
case OPC_RDPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
GEN_LOAD_SRSREG_TN(T0, rt);
GEN_STORE_TN_REG(rd, T0);
break;
case OPC_WRPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
GEN_LOAD_REG_TN(T0, rt);
GEN_STORE_TN_SRSREG(rd, T0);
break;
default:
MIPS_INVAL("cp0");
generate_exception(ctx, EXCP_RI);
break;
}
break;
case OPC_ADDI ... OPC_LUI:
gen_arith_imm(env, ctx, op, rt, rs, imm);
break;
case OPC_J ... OPC_JAL:
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, rs, rt, offset);
return;
case OPC_BEQ ... OPC_BGTZ:
case OPC_BEQL ... OPC_BGTZL:
gen_compute_branch(ctx, op, rs, rt, imm << 2);
return;
case OPC_LB ... OPC_LWR:
case OPC_SB ... OPC_SW:
case OPC_SWR:
case OPC_LL:
case OPC_SC:
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
break;
case OPC_PREF:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
break;
case OPC_LWC1:
case OPC_LDC1:
case OPC_SWC1:
case OPC_SDC1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
gen_flt_ldst(ctx, op, rt, rs, imm);
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
case OPC_CP1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
op1 = MASK_CP1(ctx->opcode);
switch (op1) {
case OPC_MFHC1:
case OPC_MTHC1:
check_insn(env, ctx, ISA_MIPS32R2);
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
case OPC_CTC1:
gen_cp1(ctx, op1, rt, rd);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
check_insn(env, ctx, ISA_MIPS3);
gen_cp1(ctx, op1, rt, rd);
break;
#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
check_cp1_3d(env, ctx);
case OPC_BC1:
gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
return;
case OPC_S_FMT:
case OPC_D_FMT:
case OPC_W_FMT:
case OPC_L_FMT:
case OPC_PS_FMT:
gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
(imm >> 8) & 0x7);
break;
default:
MIPS_INVAL("cp1");
generate_exception (ctx, EXCP_RI);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
case OPC_LWC2:
case OPC_LDC2:
case OPC_SWC2:
case OPC_SDC2:
case OPC_CP2:
generate_exception_err(ctx, EXCP_CpU, 2);
break;
case OPC_CP3:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
switch (op1) {
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_LUXC1:
case OPC_SWXC1:
case OPC_SDXC1:
case OPC_SUXC1:
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
break;
case OPC_ALNV_PS:
case OPC_MADD_S:
case OPC_MADD_D:
case OPC_MADD_PS:
case OPC_MSUB_S:
case OPC_MSUB_D:
case OPC_MSUB_PS:
case OPC_NMADD_S:
case OPC_NMADD_D:
case OPC_NMADD_PS:
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
MIPS_INVAL("cp3");
generate_exception (ctx, EXCP_RI);
break;
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
case OPC_SDL ... OPC_SDR:
case OPC_LLD:
case OPC_LD:
case OPC_SCD:
case OPC_SD:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_DADDI ... OPC_DADDIU:
check_insn(env, ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith_imm(env, ctx, op, rt, rs, imm);
break;
#endif
case OPC_JALX:
check_insn(env, ctx, ASE_MIPS16);
case OPC_MDMX:
check_insn(env, ctx, ASE_MDMX);
default:
MIPS_INVAL("major opcode");
generate_exception(ctx, EXCP_RI);
break;
}
if (ctx->hflags & MIPS_HFLAG_BMASK) {
int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
ctx->hflags &= ~MIPS_HFLAG_BMASK;
ctx->bstate = BS_BRANCH;
save_cpu_state(ctx, 0);
switch (hflags) {
case MIPS_HFLAG_B:
MIPS_DEBUG("unconditional branch");
gen_goto_tb(ctx, 0, ctx->btarget);
break;
case MIPS_HFLAG_BL:
MIPS_DEBUG("blikely branch taken");
gen_goto_tb(ctx, 0, ctx->btarget);
break;
case MIPS_HFLAG_BC:
MIPS_DEBUG("conditional branch");
{
int l1;
l1 = gen_new_label();
gen_op_jnz_T2(l1);
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
gen_goto_tb(ctx, 0, ctx->btarget);
}
break;
case MIPS_HFLAG_BR:
MIPS_DEBUG("branch to register");
gen_op_breg();
gen_op_reset_T0();
gen_op_exit_tb();
break;
default:
MIPS_DEBUG("unknown branch");
break;
}
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0 (CPUState *VAR_0, DisasContext *VAR_1)
{
int32_t offset;
int VAR_2, VAR_3, VAR_4, VAR_5;
uint32_t op, op1, op2;
int16_t imm;
if (VAR_1->pc & 0x3) {
VAR_0->CP0_BadVAddr = VAR_1->pc;
generate_exception(VAR_1, EXCP_AdEL);
return;
}
if ((VAR_1->VAR_7 & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
int VAR_8;
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", VAR_1->pc + 4);
VAR_8 = gen_new_label();
gen_op_jnz_T2(VAR_8);
gen_op_save_state(VAR_1->VAR_7 & ~MIPS_HFLAG_BMASK);
gen_goto_tb(VAR_1, 1, VAR_1->pc + 4);
gen_set_label(VAR_8);
}
op = MASK_OP_MAJOR(VAR_1->opcode);
VAR_2 = (VAR_1->opcode >> 21) & 0x1f;
VAR_3 = (VAR_1->opcode >> 16) & 0x1f;
VAR_4 = (VAR_1->opcode >> 11) & 0x1f;
VAR_5 = (VAR_1->opcode >> 6) & 0x1f;
imm = (int16_t)VAR_1->opcode;
switch (op) {
case OPC_SPECIAL:
op1 = MASK_SPECIAL(VAR_1->opcode);
switch (op1) {
case OPC_SLL:
case OPC_SRL ... OPC_SRA:
gen_arith_imm(VAR_0, VAR_1, op1, VAR_4, VAR_3, VAR_5);
break;
case OPC_MOVZ ... OPC_MOVN:
check_insn(VAR_0, VAR_1, ISA_MIPS4 | ISA_MIPS32);
case OPC_SLLV:
case OPC_SRLV ... OPC_SRAV:
case OPC_ADD ... OPC_NOR:
case OPC_SLT ... OPC_SLTU:
gen_arith(VAR_0, VAR_1, op1, VAR_4, VAR_2, VAR_3);
break;
case OPC_MULT ... OPC_DIVU:
gen_muldiv(VAR_1, op1, VAR_2, VAR_3);
break;
case OPC_JR ... OPC_JALR:
gen_compute_branch(VAR_1, op1, VAR_2, VAR_4, VAR_5);
return;
case OPC_TGE ... OPC_TEQ:
case OPC_TNE:
gen_trap(VAR_1, op1, VAR_2, VAR_3, -1);
break;
case OPC_MFHI:
case OPC_MFLO:
gen_HILO(VAR_1, op1, VAR_4);
break;
case OPC_MTHI:
case OPC_MTLO:
gen_HILO(VAR_1, op1, VAR_2);
break;
case OPC_PMON:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
generate_exception(VAR_1, EXCP_RI);
#else
gen_op_pmon(VAR_5);
#endif
break;
case OPC_SYSCALL:
generate_exception(VAR_1, EXCP_SYSCALL);
break;
case OPC_BREAK:
generate_exception(VAR_1, EXCP_BREAK);
break;
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
generate_exception(VAR_1, EXCP_RI);
#else
MIPS_INVAL("spim (unofficial)");
generate_exception(VAR_1, EXCP_RI);
#endif
break;
case OPC_SYNC:
break;
case OPC_MOVCI:
check_insn(VAR_0, VAR_1, ISA_MIPS4 | ISA_MIPS32);
if (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(VAR_1, 1);
check_cp1_enabled(VAR_1);
gen_movci(VAR_1, VAR_4, VAR_2, (VAR_1->opcode >> 18) & 0x7,
(VAR_1->opcode >> 16) & 1);
} else {
generate_exception_err(VAR_1, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
case OPC_DSLL32:
case OPC_DSRL32 ... OPC_DSRA32:
check_insn(VAR_0, VAR_1, ISA_MIPS3);
check_mips_64(VAR_1);
gen_arith_imm(VAR_0, VAR_1, op1, VAR_4, VAR_3, VAR_5);
break;
case OPC_DSLLV:
case OPC_DSRLV ... OPC_DSRAV:
case OPC_DADD ... OPC_DSUBU:
check_insn(VAR_0, VAR_1, ISA_MIPS3);
check_mips_64(VAR_1);
gen_arith(VAR_0, VAR_1, op1, VAR_4, VAR_2, VAR_3);
break;
case OPC_DMULT ... OPC_DDIVU:
check_insn(VAR_0, VAR_1, ISA_MIPS3);
check_mips_64(VAR_1);
gen_muldiv(VAR_1, op1, VAR_2, VAR_3);
break;
#endif
default:
MIPS_INVAL("special");
generate_exception(VAR_1, EXCP_RI);
break;
}
break;
case OPC_SPECIAL2:
op1 = MASK_SPECIAL2(VAR_1->opcode);
switch (op1) {
case OPC_MADD ... OPC_MADDU:
case OPC_MSUB ... OPC_MSUBU:
check_insn(VAR_0, VAR_1, ISA_MIPS32);
gen_muldiv(VAR_1, op1, VAR_2, VAR_3);
break;
case OPC_MUL:
gen_arith(VAR_0, VAR_1, op1, VAR_4, VAR_2, VAR_3);
break;
case OPC_CLZ ... OPC_CLO:
check_insn(VAR_0, VAR_1, ISA_MIPS32);
gen_cl(VAR_1, op1, VAR_4, VAR_2);
break;
case OPC_SDBBP:
check_insn(VAR_0, VAR_1, ISA_MIPS32);
if (!(VAR_1->VAR_7 & MIPS_HFLAG_DM)) {
generate_exception(VAR_1, EXCP_DBp);
} else {
generate_exception(VAR_1, EXCP_DBp);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO:
check_insn(VAR_0, VAR_1, ISA_MIPS64);
check_mips_64(VAR_1);
gen_cl(VAR_1, op1, VAR_4, VAR_2);
break;
#endif
default:
MIPS_INVAL("special2");
generate_exception(VAR_1, EXCP_RI);
break;
}
break;
case OPC_SPECIAL3:
op1 = MASK_SPECIAL3(VAR_1->opcode);
switch (op1) {
case OPC_EXT:
case OPC_INS:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
gen_bitops(VAR_1, op1, VAR_3, VAR_2, VAR_5, VAR_4);
break;
case OPC_BSHFL:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
op2 = MASK_BSHFL(VAR_1->opcode);
switch (op2) {
case OPC_WSBH:
GEN_LOAD_REG_TN(T1, VAR_3);
gen_op_wsbh();
break;
case OPC_SEB:
GEN_LOAD_REG_TN(T1, VAR_3);
gen_op_seb();
break;
case OPC_SEH:
GEN_LOAD_REG_TN(T1, VAR_3);
gen_op_seh();
break;
default:
MIPS_INVAL("bshfl");
generate_exception(VAR_1, EXCP_RI);
break;
}
GEN_STORE_TN_REG(VAR_4, T0);
break;
case OPC_RDHWR:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
switch (VAR_4) {
case 0:
save_cpu_state(VAR_1, 1);
gen_op_rdhwr_cpunum();
break;
case 1:
save_cpu_state(VAR_1, 1);
gen_op_rdhwr_synci_step();
break;
case 2:
save_cpu_state(VAR_1, 1);
gen_op_rdhwr_cc();
break;
case 3:
save_cpu_state(VAR_1, 1);
gen_op_rdhwr_ccres();
break;
case 29:
#if defined (CONFIG_USER_ONLY)
gen_op_tls_value();
break;
#endif
default:
MIPS_INVAL("rdhwr");
generate_exception(VAR_1, EXCP_RI);
break;
}
GEN_STORE_TN_REG(VAR_3, T0);
break;
case OPC_FORK:
check_mips_mt(VAR_0, VAR_1);
GEN_LOAD_REG_TN(T0, VAR_3);
GEN_LOAD_REG_TN(T1, VAR_2);
gen_op_fork();
break;
case OPC_YIELD:
check_mips_mt(VAR_0, VAR_1);
GEN_LOAD_REG_TN(T0, VAR_2);
gen_op_yield();
GEN_STORE_TN_REG(VAR_4, T0);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
check_insn(VAR_0, VAR_1, ISA_MIPS64R2);
check_mips_64(VAR_1);
gen_bitops(VAR_1, op1, VAR_3, VAR_2, VAR_5, VAR_4);
break;
case OPC_DBSHFL:
check_insn(VAR_0, VAR_1, ISA_MIPS64R2);
check_mips_64(VAR_1);
op2 = MASK_DBSHFL(VAR_1->opcode);
switch (op2) {
case OPC_DSBH:
GEN_LOAD_REG_TN(T1, VAR_3);
gen_op_dsbh();
break;
case OPC_DSHD:
GEN_LOAD_REG_TN(T1, VAR_3);
gen_op_dshd();
break;
default:
MIPS_INVAL("dbshfl");
generate_exception(VAR_1, EXCP_RI);
break;
}
GEN_STORE_TN_REG(VAR_4, T0);
#endif
default:
MIPS_INVAL("special3");
generate_exception(VAR_1, EXCP_RI);
break;
}
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(VAR_1->opcode);
switch (op1) {
case OPC_BLTZ ... OPC_BGEZL:
case OPC_BLTZAL ... OPC_BGEZALL:
gen_compute_branch(VAR_1, op1, VAR_2, -1, imm << 2);
return;
case OPC_TGEI ... OPC_TEQI:
case OPC_TNEI:
gen_trap(VAR_1, op1, VAR_2, -1, imm);
break;
case OPC_SYNCI:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
break;
default:
MIPS_INVAL("regimm");
generate_exception(VAR_1, EXCP_RI);
break;
}
break;
case OPC_CP0:
check_cp0_enabled(VAR_1);
op1 = MASK_CP0(VAR_1->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
case OPC_MFTR:
case OPC_MTTR:
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
gen_cp0(VAR_0, VAR_1, op1, VAR_3, VAR_4);
break;
case OPC_C0_FIRST ... OPC_C0_LAST:
gen_cp0(VAR_0, VAR_1, MASK_C0(VAR_1->opcode), VAR_3, VAR_4);
break;
case OPC_MFMC0:
op2 = MASK_MFMC0(VAR_1->opcode);
switch (op2) {
case OPC_DMT:
check_mips_mt(VAR_0, VAR_1);
gen_op_dmt();
break;
case OPC_EMT:
check_mips_mt(VAR_0, VAR_1);
gen_op_emt();
break;
case OPC_DVPE:
check_mips_mt(VAR_0, VAR_1);
gen_op_dvpe();
break;
case OPC_EVPE:
check_mips_mt(VAR_0, VAR_1);
gen_op_evpe();
break;
case OPC_DI:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
save_cpu_state(VAR_1, 1);
gen_op_di();
VAR_1->bstate = BS_STOP;
break;
case OPC_EI:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
save_cpu_state(VAR_1, 1);
gen_op_ei();
VAR_1->bstate = BS_STOP;
break;
default:
MIPS_INVAL("mfmc0");
generate_exception(VAR_1, EXCP_RI);
break;
}
GEN_STORE_TN_REG(VAR_3, T0);
break;
case OPC_RDPGPR:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
GEN_LOAD_SRSREG_TN(T0, VAR_3);
GEN_STORE_TN_REG(VAR_4, T0);
break;
case OPC_WRPGPR:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
GEN_LOAD_REG_TN(T0, VAR_3);
GEN_STORE_TN_SRSREG(VAR_4, T0);
break;
default:
MIPS_INVAL("cp0");
generate_exception(VAR_1, EXCP_RI);
break;
}
break;
case OPC_ADDI ... OPC_LUI:
gen_arith_imm(VAR_0, VAR_1, op, VAR_3, VAR_2, imm);
break;
case OPC_J ... OPC_JAL:
offset = (int32_t)(VAR_1->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(VAR_1, op, VAR_2, VAR_3, offset);
return;
case OPC_BEQ ... OPC_BGTZ:
case OPC_BEQL ... OPC_BGTZL:
gen_compute_branch(VAR_1, op, VAR_2, VAR_3, imm << 2);
return;
case OPC_LB ... OPC_LWR:
case OPC_SB ... OPC_SW:
case OPC_SWR:
case OPC_LL:
case OPC_SC:
gen_ldst(VAR_1, op, VAR_3, VAR_2, imm);
break;
case OPC_CACHE:
check_insn(VAR_0, VAR_1, ISA_MIPS3 | ISA_MIPS32);
break;
case OPC_PREF:
check_insn(VAR_0, VAR_1, ISA_MIPS4 | ISA_MIPS32);
break;
case OPC_LWC1:
case OPC_LDC1:
case OPC_SWC1:
case OPC_SDC1:
if (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(VAR_1, 1);
check_cp1_enabled(VAR_1);
gen_flt_ldst(VAR_1, op, VAR_3, VAR_2, imm);
} else {
generate_exception_err(VAR_1, EXCP_CpU, 1);
}
break;
case OPC_CP1:
if (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(VAR_1, 1);
check_cp1_enabled(VAR_1);
op1 = MASK_CP1(VAR_1->opcode);
switch (op1) {
case OPC_MFHC1:
case OPC_MTHC1:
check_insn(VAR_0, VAR_1, ISA_MIPS32R2);
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
case OPC_CTC1:
gen_cp1(VAR_1, op1, VAR_3, VAR_4);
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
check_insn(VAR_0, VAR_1, ISA_MIPS3);
gen_cp1(VAR_1, op1, VAR_3, VAR_4);
break;
#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
check_cp1_3d(VAR_0, VAR_1);
case OPC_BC1:
gen_compute_branch1(VAR_0, VAR_1, MASK_BC1(VAR_1->opcode),
(VAR_3 >> 2) & 0x7, imm << 2);
return;
case OPC_S_FMT:
case OPC_D_FMT:
case OPC_W_FMT:
case OPC_L_FMT:
case OPC_PS_FMT:
gen_farith(VAR_1, MASK_CP1_FUNC(VAR_1->opcode), VAR_3, VAR_4, VAR_5,
(imm >> 8) & 0x7);
break;
default:
MIPS_INVAL("cp1");
generate_exception (VAR_1, EXCP_RI);
break;
}
} else {
generate_exception_err(VAR_1, EXCP_CpU, 1);
}
break;
case OPC_LWC2:
case OPC_LDC2:
case OPC_SWC2:
case OPC_SDC2:
case OPC_CP2:
generate_exception_err(VAR_1, EXCP_CpU, 2);
break;
case OPC_CP3:
if (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(VAR_1, 1);
check_cp1_enabled(VAR_1);
op1 = MASK_CP3(VAR_1->opcode);
switch (op1) {
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_LUXC1:
case OPC_SWXC1:
case OPC_SDXC1:
case OPC_SUXC1:
gen_flt3_ldst(VAR_1, op1, VAR_5, VAR_4, VAR_2, VAR_3);
break;
case OPC_PREFX:
break;
case OPC_ALNV_PS:
case OPC_MADD_S:
case OPC_MADD_D:
case OPC_MADD_PS:
case OPC_MSUB_S:
case OPC_MSUB_D:
case OPC_MSUB_PS:
case OPC_NMADD_S:
case OPC_NMADD_D:
case OPC_NMADD_PS:
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
gen_flt3_arith(VAR_1, op1, VAR_5, VAR_2, VAR_4, VAR_3);
break;
default:
MIPS_INVAL("cp3");
generate_exception (VAR_1, EXCP_RI);
break;
}
} else {
generate_exception_err(VAR_1, EXCP_CpU, 1);
}
break;
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
case OPC_SDL ... OPC_SDR:
case OPC_LLD:
case OPC_LD:
case OPC_SCD:
case OPC_SD:
check_insn(VAR_0, VAR_1, ISA_MIPS3);
check_mips_64(VAR_1);
gen_ldst(VAR_1, op, VAR_3, VAR_2, imm);
break;
case OPC_DADDI ... OPC_DADDIU:
check_insn(VAR_0, VAR_1, ISA_MIPS3);
check_mips_64(VAR_1);
gen_arith_imm(VAR_0, VAR_1, op, VAR_3, VAR_2, imm);
break;
#endif
case OPC_JALX:
check_insn(VAR_0, VAR_1, ASE_MIPS16);
case OPC_MDMX:
check_insn(VAR_0, VAR_1, ASE_MDMX);
default:
MIPS_INVAL("major opcode");
generate_exception(VAR_1, EXCP_RI);
break;
}
if (VAR_1->VAR_7 & MIPS_HFLAG_BMASK) {
int VAR_7 = VAR_1->VAR_7 & MIPS_HFLAG_BMASK;
VAR_1->VAR_7 &= ~MIPS_HFLAG_BMASK;
VAR_1->bstate = BS_BRANCH;
save_cpu_state(VAR_1, 0);
switch (VAR_7) {
case MIPS_HFLAG_B:
MIPS_DEBUG("unconditional branch");
gen_goto_tb(VAR_1, 0, VAR_1->btarget);
break;
case MIPS_HFLAG_BL:
MIPS_DEBUG("blikely branch taken");
gen_goto_tb(VAR_1, 0, VAR_1->btarget);
break;
case MIPS_HFLAG_BC:
MIPS_DEBUG("conditional branch");
{
int VAR_8;
VAR_8 = gen_new_label();
gen_op_jnz_T2(VAR_8);
gen_goto_tb(VAR_1, 1, VAR_1->pc + 4);
gen_set_label(VAR_8);
gen_goto_tb(VAR_1, 0, VAR_1->btarget);
}
break;
case MIPS_HFLAG_BR:
MIPS_DEBUG("branch to register");
gen_op_breg();
gen_op_reset_T0();
gen_op_exit_tb();
break;
default:
MIPS_DEBUG("unknown branch");
break;
}
}
}
| [
"static void FUNC_0 (CPUState *VAR_0, DisasContext *VAR_1)\n{",
"int32_t offset;",
"int VAR_2, VAR_3, VAR_4, VAR_5;",
"uint32_t op, op1, op2;",
"int16_t imm;",
"if (VAR_1->pc & 0x3) {",
"VAR_0->CP0_BadVAddr = VAR_1->pc;",
"generate_exception(VAR_1, EXCP_AdEL);",
"return;",
"}",
"if ((VAR_1->VAR_7 & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {",
"int VAR_8;",
"MIPS_DEBUG(\"blikely condition (\" TARGET_FMT_lx \")\", VAR_1->pc + 4);",
"VAR_8 = gen_new_label();",
"gen_op_jnz_T2(VAR_8);",
"gen_op_save_state(VAR_1->VAR_7 & ~MIPS_HFLAG_BMASK);",
"gen_goto_tb(VAR_1, 1, VAR_1->pc + 4);",
"gen_set_label(VAR_8);",
"}",
"op = MASK_OP_MAJOR(VAR_1->opcode);",
"VAR_2 = (VAR_1->opcode >> 21) & 0x1f;",
"VAR_3 = (VAR_1->opcode >> 16) & 0x1f;",
"VAR_4 = (VAR_1->opcode >> 11) & 0x1f;",
"VAR_5 = (VAR_1->opcode >> 6) & 0x1f;",
"imm = (int16_t)VAR_1->opcode;",
"switch (op) {",
"case OPC_SPECIAL:\nop1 = MASK_SPECIAL(VAR_1->opcode);",
"switch (op1) {",
"case OPC_SLL:\ncase OPC_SRL ... OPC_SRA:\ngen_arith_imm(VAR_0, VAR_1, op1, VAR_4, VAR_3, VAR_5);",
"break;",
"case OPC_MOVZ ... OPC_MOVN:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS4 | ISA_MIPS32);",
"case OPC_SLLV:\ncase OPC_SRLV ... OPC_SRAV:\ncase OPC_ADD ... OPC_NOR:\ncase OPC_SLT ... OPC_SLTU:\ngen_arith(VAR_0, VAR_1, op1, VAR_4, VAR_2, VAR_3);",
"break;",
"case OPC_MULT ... OPC_DIVU:\ngen_muldiv(VAR_1, op1, VAR_2, VAR_3);",
"break;",
"case OPC_JR ... OPC_JALR:\ngen_compute_branch(VAR_1, op1, VAR_2, VAR_4, VAR_5);",
"return;",
"case OPC_TGE ... OPC_TEQ:\ncase OPC_TNE:\ngen_trap(VAR_1, op1, VAR_2, VAR_3, -1);",
"break;",
"case OPC_MFHI:\ncase OPC_MFLO:\ngen_HILO(VAR_1, op1, VAR_4);",
"break;",
"case OPC_MTHI:\ncase OPC_MTLO:\ngen_HILO(VAR_1, op1, VAR_2);",
"break;",
"case OPC_PMON:\n#ifdef MIPS_STRICT_STANDARD\nMIPS_INVAL(\"PMON / selsl\");",
"generate_exception(VAR_1, EXCP_RI);",
"#else\ngen_op_pmon(VAR_5);",
"#endif\nbreak;",
"case OPC_SYSCALL:\ngenerate_exception(VAR_1, EXCP_SYSCALL);",
"break;",
"case OPC_BREAK:\ngenerate_exception(VAR_1, EXCP_BREAK);",
"break;",
"case OPC_SPIM:\n#ifdef MIPS_STRICT_STANDARD\nMIPS_INVAL(\"SPIM\");",
"generate_exception(VAR_1, EXCP_RI);",
"#else\nMIPS_INVAL(\"spim (unofficial)\");",
"generate_exception(VAR_1, EXCP_RI);",
"#endif\nbreak;",
"case OPC_SYNC:\nbreak;",
"case OPC_MOVCI:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS4 | ISA_MIPS32);",
"if (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {",
"save_cpu_state(VAR_1, 1);",
"check_cp1_enabled(VAR_1);",
"gen_movci(VAR_1, VAR_4, VAR_2, (VAR_1->opcode >> 18) & 0x7,\n(VAR_1->opcode >> 16) & 1);",
"} else {",
"generate_exception_err(VAR_1, EXCP_CpU, 1);",
"}",
"break;",
"#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)\ncase OPC_DSLL:\ncase OPC_DSRL ... OPC_DSRA:\ncase OPC_DSLL32:\ncase OPC_DSRL32 ... OPC_DSRA32:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3);",
"check_mips_64(VAR_1);",
"gen_arith_imm(VAR_0, VAR_1, op1, VAR_4, VAR_3, VAR_5);",
"break;",
"case OPC_DSLLV:\ncase OPC_DSRLV ... OPC_DSRAV:\ncase OPC_DADD ... OPC_DSUBU:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3);",
"check_mips_64(VAR_1);",
"gen_arith(VAR_0, VAR_1, op1, VAR_4, VAR_2, VAR_3);",
"break;",
"case OPC_DMULT ... OPC_DDIVU:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3);",
"check_mips_64(VAR_1);",
"gen_muldiv(VAR_1, op1, VAR_2, VAR_3);",
"break;",
"#endif\ndefault:\nMIPS_INVAL(\"special\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"break;",
"case OPC_SPECIAL2:\nop1 = MASK_SPECIAL2(VAR_1->opcode);",
"switch (op1) {",
"case OPC_MADD ... OPC_MADDU:\ncase OPC_MSUB ... OPC_MSUBU:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32);",
"gen_muldiv(VAR_1, op1, VAR_2, VAR_3);",
"break;",
"case OPC_MUL:\ngen_arith(VAR_0, VAR_1, op1, VAR_4, VAR_2, VAR_3);",
"break;",
"case OPC_CLZ ... OPC_CLO:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32);",
"gen_cl(VAR_1, op1, VAR_4, VAR_2);",
"break;",
"case OPC_SDBBP:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32);",
"if (!(VAR_1->VAR_7 & MIPS_HFLAG_DM)) {",
"generate_exception(VAR_1, EXCP_DBp);",
"} else {",
"generate_exception(VAR_1, EXCP_DBp);",
"}",
"break;",
"#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)\ncase OPC_DCLZ ... OPC_DCLO:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS64);",
"check_mips_64(VAR_1);",
"gen_cl(VAR_1, op1, VAR_4, VAR_2);",
"break;",
"#endif\ndefault:\nMIPS_INVAL(\"special2\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"break;",
"case OPC_SPECIAL3:\nop1 = MASK_SPECIAL3(VAR_1->opcode);",
"switch (op1) {",
"case OPC_EXT:\ncase OPC_INS:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"gen_bitops(VAR_1, op1, VAR_3, VAR_2, VAR_5, VAR_4);",
"break;",
"case OPC_BSHFL:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"op2 = MASK_BSHFL(VAR_1->opcode);",
"switch (op2) {",
"case OPC_WSBH:\nGEN_LOAD_REG_TN(T1, VAR_3);",
"gen_op_wsbh();",
"break;",
"case OPC_SEB:\nGEN_LOAD_REG_TN(T1, VAR_3);",
"gen_op_seb();",
"break;",
"case OPC_SEH:\nGEN_LOAD_REG_TN(T1, VAR_3);",
"gen_op_seh();",
"break;",
"default:\nMIPS_INVAL(\"bshfl\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"GEN_STORE_TN_REG(VAR_4, T0);",
"break;",
"case OPC_RDHWR:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"switch (VAR_4) {",
"case 0:\nsave_cpu_state(VAR_1, 1);",
"gen_op_rdhwr_cpunum();",
"break;",
"case 1:\nsave_cpu_state(VAR_1, 1);",
"gen_op_rdhwr_synci_step();",
"break;",
"case 2:\nsave_cpu_state(VAR_1, 1);",
"gen_op_rdhwr_cc();",
"break;",
"case 3:\nsave_cpu_state(VAR_1, 1);",
"gen_op_rdhwr_ccres();",
"break;",
"case 29:\n#if defined (CONFIG_USER_ONLY)\ngen_op_tls_value();",
"break;",
"#endif\ndefault:\nMIPS_INVAL(\"rdhwr\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"GEN_STORE_TN_REG(VAR_3, T0);",
"break;",
"case OPC_FORK:\ncheck_mips_mt(VAR_0, VAR_1);",
"GEN_LOAD_REG_TN(T0, VAR_3);",
"GEN_LOAD_REG_TN(T1, VAR_2);",
"gen_op_fork();",
"break;",
"case OPC_YIELD:\ncheck_mips_mt(VAR_0, VAR_1);",
"GEN_LOAD_REG_TN(T0, VAR_2);",
"gen_op_yield();",
"GEN_STORE_TN_REG(VAR_4, T0);",
"break;",
"#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)\ncase OPC_DEXTM ... OPC_DEXT:\ncase OPC_DINSM ... OPC_DINS:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS64R2);",
"check_mips_64(VAR_1);",
"gen_bitops(VAR_1, op1, VAR_3, VAR_2, VAR_5, VAR_4);",
"break;",
"case OPC_DBSHFL:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS64R2);",
"check_mips_64(VAR_1);",
"op2 = MASK_DBSHFL(VAR_1->opcode);",
"switch (op2) {",
"case OPC_DSBH:\nGEN_LOAD_REG_TN(T1, VAR_3);",
"gen_op_dsbh();",
"break;",
"case OPC_DSHD:\nGEN_LOAD_REG_TN(T1, VAR_3);",
"gen_op_dshd();",
"break;",
"default:\nMIPS_INVAL(\"dbshfl\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"GEN_STORE_TN_REG(VAR_4, T0);",
"#endif\ndefault:\nMIPS_INVAL(\"special3\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"break;",
"case OPC_REGIMM:\nop1 = MASK_REGIMM(VAR_1->opcode);",
"switch (op1) {",
"case OPC_BLTZ ... OPC_BGEZL:\ncase OPC_BLTZAL ... OPC_BGEZALL:\ngen_compute_branch(VAR_1, op1, VAR_2, -1, imm << 2);",
"return;",
"case OPC_TGEI ... OPC_TEQI:\ncase OPC_TNEI:\ngen_trap(VAR_1, op1, VAR_2, -1, imm);",
"break;",
"case OPC_SYNCI:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"break;",
"default:\nMIPS_INVAL(\"regimm\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"break;",
"case OPC_CP0:\ncheck_cp0_enabled(VAR_1);",
"op1 = MASK_CP0(VAR_1->opcode);",
"switch (op1) {",
"case OPC_MFC0:\ncase OPC_MTC0:\ncase OPC_MFTR:\ncase OPC_MTTR:\n#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)\ncase OPC_DMFC0:\ncase OPC_DMTC0:\n#endif\ngen_cp0(VAR_0, VAR_1, op1, VAR_3, VAR_4);",
"break;",
"case OPC_C0_FIRST ... OPC_C0_LAST:\ngen_cp0(VAR_0, VAR_1, MASK_C0(VAR_1->opcode), VAR_3, VAR_4);",
"break;",
"case OPC_MFMC0:\nop2 = MASK_MFMC0(VAR_1->opcode);",
"switch (op2) {",
"case OPC_DMT:\ncheck_mips_mt(VAR_0, VAR_1);",
"gen_op_dmt();",
"break;",
"case OPC_EMT:\ncheck_mips_mt(VAR_0, VAR_1);",
"gen_op_emt();",
"break;",
"case OPC_DVPE:\ncheck_mips_mt(VAR_0, VAR_1);",
"gen_op_dvpe();",
"break;",
"case OPC_EVPE:\ncheck_mips_mt(VAR_0, VAR_1);",
"gen_op_evpe();",
"break;",
"case OPC_DI:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"save_cpu_state(VAR_1, 1);",
"gen_op_di();",
"VAR_1->bstate = BS_STOP;",
"break;",
"case OPC_EI:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"save_cpu_state(VAR_1, 1);",
"gen_op_ei();",
"VAR_1->bstate = BS_STOP;",
"break;",
"default:\nMIPS_INVAL(\"mfmc0\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"GEN_STORE_TN_REG(VAR_3, T0);",
"break;",
"case OPC_RDPGPR:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"GEN_LOAD_SRSREG_TN(T0, VAR_3);",
"GEN_STORE_TN_REG(VAR_4, T0);",
"break;",
"case OPC_WRPGPR:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"GEN_LOAD_REG_TN(T0, VAR_3);",
"GEN_STORE_TN_SRSREG(VAR_4, T0);",
"break;",
"default:\nMIPS_INVAL(\"cp0\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"break;",
"case OPC_ADDI ... OPC_LUI:\ngen_arith_imm(VAR_0, VAR_1, op, VAR_3, VAR_2, imm);",
"break;",
"case OPC_J ... OPC_JAL:\noffset = (int32_t)(VAR_1->opcode & 0x3FFFFFF) << 2;",
"gen_compute_branch(VAR_1, op, VAR_2, VAR_3, offset);",
"return;",
"case OPC_BEQ ... OPC_BGTZ:\ncase OPC_BEQL ... OPC_BGTZL:\ngen_compute_branch(VAR_1, op, VAR_2, VAR_3, imm << 2);",
"return;",
"case OPC_LB ... OPC_LWR:\ncase OPC_SB ... OPC_SW:\ncase OPC_SWR:\ncase OPC_LL:\ncase OPC_SC:\ngen_ldst(VAR_1, op, VAR_3, VAR_2, imm);",
"break;",
"case OPC_CACHE:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3 | ISA_MIPS32);",
"break;",
"case OPC_PREF:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS4 | ISA_MIPS32);",
"break;",
"case OPC_LWC1:\ncase OPC_LDC1:\ncase OPC_SWC1:\ncase OPC_SDC1:\nif (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {",
"save_cpu_state(VAR_1, 1);",
"check_cp1_enabled(VAR_1);",
"gen_flt_ldst(VAR_1, op, VAR_3, VAR_2, imm);",
"} else {",
"generate_exception_err(VAR_1, EXCP_CpU, 1);",
"}",
"break;",
"case OPC_CP1:\nif (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {",
"save_cpu_state(VAR_1, 1);",
"check_cp1_enabled(VAR_1);",
"op1 = MASK_CP1(VAR_1->opcode);",
"switch (op1) {",
"case OPC_MFHC1:\ncase OPC_MTHC1:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS32R2);",
"case OPC_MFC1:\ncase OPC_CFC1:\ncase OPC_MTC1:\ncase OPC_CTC1:\ngen_cp1(VAR_1, op1, VAR_3, VAR_4);",
"break;",
"#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)\ncase OPC_DMFC1:\ncase OPC_DMTC1:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3);",
"gen_cp1(VAR_1, op1, VAR_3, VAR_4);",
"break;",
"#endif\ncase OPC_BC1ANY2:\ncase OPC_BC1ANY4:\ncheck_cp1_3d(VAR_0, VAR_1);",
"case OPC_BC1:\ngen_compute_branch1(VAR_0, VAR_1, MASK_BC1(VAR_1->opcode),\n(VAR_3 >> 2) & 0x7, imm << 2);",
"return;",
"case OPC_S_FMT:\ncase OPC_D_FMT:\ncase OPC_W_FMT:\ncase OPC_L_FMT:\ncase OPC_PS_FMT:\ngen_farith(VAR_1, MASK_CP1_FUNC(VAR_1->opcode), VAR_3, VAR_4, VAR_5,\n(imm >> 8) & 0x7);",
"break;",
"default:\nMIPS_INVAL(\"cp1\");",
"generate_exception (VAR_1, EXCP_RI);",
"break;",
"}",
"} else {",
"generate_exception_err(VAR_1, EXCP_CpU, 1);",
"}",
"break;",
"case OPC_LWC2:\ncase OPC_LDC2:\ncase OPC_SWC2:\ncase OPC_SDC2:\ncase OPC_CP2:\ngenerate_exception_err(VAR_1, EXCP_CpU, 2);",
"break;",
"case OPC_CP3:\nif (VAR_0->CP0_Config1 & (1 << CP0C1_FP)) {",
"save_cpu_state(VAR_1, 1);",
"check_cp1_enabled(VAR_1);",
"op1 = MASK_CP3(VAR_1->opcode);",
"switch (op1) {",
"case OPC_LWXC1:\ncase OPC_LDXC1:\ncase OPC_LUXC1:\ncase OPC_SWXC1:\ncase OPC_SDXC1:\ncase OPC_SUXC1:\ngen_flt3_ldst(VAR_1, op1, VAR_5, VAR_4, VAR_2, VAR_3);",
"break;",
"case OPC_PREFX:\nbreak;",
"case OPC_ALNV_PS:\ncase OPC_MADD_S:\ncase OPC_MADD_D:\ncase OPC_MADD_PS:\ncase OPC_MSUB_S:\ncase OPC_MSUB_D:\ncase OPC_MSUB_PS:\ncase OPC_NMADD_S:\ncase OPC_NMADD_D:\ncase OPC_NMADD_PS:\ncase OPC_NMSUB_S:\ncase OPC_NMSUB_D:\ncase OPC_NMSUB_PS:\ngen_flt3_arith(VAR_1, op1, VAR_5, VAR_2, VAR_4, VAR_3);",
"break;",
"default:\nMIPS_INVAL(\"cp3\");",
"generate_exception (VAR_1, EXCP_RI);",
"break;",
"}",
"} else {",
"generate_exception_err(VAR_1, EXCP_CpU, 1);",
"}",
"break;",
"#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)\ncase OPC_LWU:\ncase OPC_LDL ... OPC_LDR:\ncase OPC_SDL ... OPC_SDR:\ncase OPC_LLD:\ncase OPC_LD:\ncase OPC_SCD:\ncase OPC_SD:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3);",
"check_mips_64(VAR_1);",
"gen_ldst(VAR_1, op, VAR_3, VAR_2, imm);",
"break;",
"case OPC_DADDI ... OPC_DADDIU:\ncheck_insn(VAR_0, VAR_1, ISA_MIPS3);",
"check_mips_64(VAR_1);",
"gen_arith_imm(VAR_0, VAR_1, op, VAR_3, VAR_2, imm);",
"break;",
"#endif\ncase OPC_JALX:\ncheck_insn(VAR_0, VAR_1, ASE_MIPS16);",
"case OPC_MDMX:\ncheck_insn(VAR_0, VAR_1, ASE_MDMX);",
"default:\nMIPS_INVAL(\"major opcode\");",
"generate_exception(VAR_1, EXCP_RI);",
"break;",
"}",
"if (VAR_1->VAR_7 & MIPS_HFLAG_BMASK) {",
"int VAR_7 = VAR_1->VAR_7 & MIPS_HFLAG_BMASK;",
"VAR_1->VAR_7 &= ~MIPS_HFLAG_BMASK;",
"VAR_1->bstate = BS_BRANCH;",
"save_cpu_state(VAR_1, 0);",
"switch (VAR_7) {",
"case MIPS_HFLAG_B:\nMIPS_DEBUG(\"unconditional branch\");",
"gen_goto_tb(VAR_1, 0, VAR_1->btarget);",
"break;",
"case MIPS_HFLAG_BL:\nMIPS_DEBUG(\"blikely branch taken\");",
"gen_goto_tb(VAR_1, 0, VAR_1->btarget);",
"break;",
"case MIPS_HFLAG_BC:\nMIPS_DEBUG(\"conditional branch\");",
"{",
"int VAR_8;",
"VAR_8 = gen_new_label();",
"gen_op_jnz_T2(VAR_8);",
"gen_goto_tb(VAR_1, 1, VAR_1->pc + 4);",
"gen_set_label(VAR_8);",
"gen_goto_tb(VAR_1, 0, VAR_1->btarget);",
"}",
"break;",
"case MIPS_HFLAG_BR:\nMIPS_DEBUG(\"branch to register\");",
"gen_op_breg();",
"gen_op_reset_T0();",
"gen_op_exit_tb();",
"break;",
"default:\nMIPS_DEBUG(\"unknown branch\");",
"break;",
"}",
"}",
"}"
]
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|
10,304 | static void port92_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
Port92State *s = opaque;
int oldval = s->outport;
DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
s->outport = val;
qemu_set_irq(*s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request();
}
}
| false | qemu | d812b3d68ddf0efe91a088ecc8b177865b0bab8d | static void port92_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
Port92State *s = opaque;
int oldval = s->outport;
DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
s->outport = val;
qemu_set_irq(*s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request();
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{
Port92State *s = VAR_0;
int VAR_4 = s->outport;
DPRINTF("port92: write 0x%02" PRIx64 "\n", VAR_2);
s->outport = VAR_2;
qemu_set_irq(*s->a20_out, (VAR_2 >> 1) & 1);
if ((VAR_2 & 1) && !(VAR_4 & 1)) {
qemu_system_reset_request();
}
}
| [
"static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,\nunsigned VAR_3)\n{",
"Port92State *s = VAR_0;",
"int VAR_4 = s->outport;",
"DPRINTF(\"port92: write 0x%02\" PRIx64 \"\\n\", VAR_2);",
"s->outport = VAR_2;",
"qemu_set_irq(*s->a20_out, (VAR_2 >> 1) & 1);",
"if ((VAR_2 & 1) && !(VAR_4 & 1)) {",
"qemu_system_reset_request();",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
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[
13
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[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
]
]
|
10,305 | static uint64_t coroutine_fn mirror_iteration(MirrorBlockJob *s)
{
BlockDriverState *source = blk_bs(s->common.blk);
int64_t sector_num, first_chunk;
uint64_t delay_ns = 0;
/* At least the first dirty chunk is mirrored in one iteration. */
int nb_chunks = 1;
int64_t end = s->bdev_length / BDRV_SECTOR_SIZE;
int sectors_per_chunk = s->granularity >> BDRV_SECTOR_BITS;
bool write_zeroes_ok = bdrv_can_write_zeroes_with_unmap(blk_bs(s->target));
sector_num = hbitmap_iter_next(&s->hbi);
if (sector_num < 0) {
bdrv_dirty_iter_init(s->dirty_bitmap, &s->hbi);
sector_num = hbitmap_iter_next(&s->hbi);
trace_mirror_restart_iter(s, bdrv_get_dirty_count(s->dirty_bitmap));
assert(sector_num >= 0);
}
first_chunk = sector_num / sectors_per_chunk;
while (test_bit(first_chunk, s->in_flight_bitmap)) {
trace_mirror_yield_in_flight(s, sector_num, s->in_flight);
mirror_wait_for_io(s);
}
block_job_pause_point(&s->common);
/* Find the number of consective dirty chunks following the first dirty
* one, and wait for in flight requests in them. */
while (nb_chunks * sectors_per_chunk < (s->buf_size >> BDRV_SECTOR_BITS)) {
int64_t hbitmap_next;
int64_t next_sector = sector_num + nb_chunks * sectors_per_chunk;
int64_t next_chunk = next_sector / sectors_per_chunk;
if (next_sector >= end ||
!bdrv_get_dirty(source, s->dirty_bitmap, next_sector)) {
break;
}
if (test_bit(next_chunk, s->in_flight_bitmap)) {
break;
}
hbitmap_next = hbitmap_iter_next(&s->hbi);
if (hbitmap_next > next_sector || hbitmap_next < 0) {
/* The bitmap iterator's cache is stale, refresh it */
bdrv_set_dirty_iter(&s->hbi, next_sector);
hbitmap_next = hbitmap_iter_next(&s->hbi);
}
assert(hbitmap_next == next_sector);
nb_chunks++;
}
/* Clear dirty bits before querying the block status, because
* calling bdrv_get_block_status_above could yield - if some blocks are
* marked dirty in this window, we need to know.
*/
bdrv_reset_dirty_bitmap(s->dirty_bitmap, sector_num,
nb_chunks * sectors_per_chunk);
bitmap_set(s->in_flight_bitmap, sector_num / sectors_per_chunk, nb_chunks);
while (nb_chunks > 0 && sector_num < end) {
int ret;
int io_sectors, io_sectors_acct;
BlockDriverState *file;
enum MirrorMethod {
MIRROR_METHOD_COPY,
MIRROR_METHOD_ZERO,
MIRROR_METHOD_DISCARD
} mirror_method = MIRROR_METHOD_COPY;
assert(!(sector_num % sectors_per_chunk));
ret = bdrv_get_block_status_above(source, NULL, sector_num,
nb_chunks * sectors_per_chunk,
&io_sectors, &file);
if (ret < 0) {
io_sectors = nb_chunks * sectors_per_chunk;
}
io_sectors -= io_sectors % sectors_per_chunk;
if (io_sectors < sectors_per_chunk) {
io_sectors = sectors_per_chunk;
} else if (ret >= 0 && !(ret & BDRV_BLOCK_DATA)) {
int64_t target_sector_num;
int target_nb_sectors;
bdrv_round_sectors_to_clusters(blk_bs(s->target), sector_num,
io_sectors, &target_sector_num,
&target_nb_sectors);
if (target_sector_num == sector_num &&
target_nb_sectors == io_sectors) {
mirror_method = ret & BDRV_BLOCK_ZERO ?
MIRROR_METHOD_ZERO :
MIRROR_METHOD_DISCARD;
}
}
while (s->in_flight >= MAX_IN_FLIGHT) {
trace_mirror_yield_in_flight(s, sector_num, s->in_flight);
mirror_wait_for_io(s);
}
mirror_clip_sectors(s, sector_num, &io_sectors);
switch (mirror_method) {
case MIRROR_METHOD_COPY:
io_sectors = mirror_do_read(s, sector_num, io_sectors);
io_sectors_acct = io_sectors;
break;
case MIRROR_METHOD_ZERO:
case MIRROR_METHOD_DISCARD:
mirror_do_zero_or_discard(s, sector_num, io_sectors,
mirror_method == MIRROR_METHOD_DISCARD);
if (write_zeroes_ok) {
io_sectors_acct = 0;
} else {
io_sectors_acct = io_sectors;
}
break;
default:
abort();
}
assert(io_sectors);
sector_num += io_sectors;
nb_chunks -= DIV_ROUND_UP(io_sectors, sectors_per_chunk);
if (s->common.speed) {
delay_ns = ratelimit_calculate_delay(&s->limit, io_sectors_acct);
}
}
return delay_ns;
}
| false | qemu | 0965a41e998ab820b5d660c8abfc8c819c97bc1b | static uint64_t coroutine_fn mirror_iteration(MirrorBlockJob *s)
{
BlockDriverState *source = blk_bs(s->common.blk);
int64_t sector_num, first_chunk;
uint64_t delay_ns = 0;
int nb_chunks = 1;
int64_t end = s->bdev_length / BDRV_SECTOR_SIZE;
int sectors_per_chunk = s->granularity >> BDRV_SECTOR_BITS;
bool write_zeroes_ok = bdrv_can_write_zeroes_with_unmap(blk_bs(s->target));
sector_num = hbitmap_iter_next(&s->hbi);
if (sector_num < 0) {
bdrv_dirty_iter_init(s->dirty_bitmap, &s->hbi);
sector_num = hbitmap_iter_next(&s->hbi);
trace_mirror_restart_iter(s, bdrv_get_dirty_count(s->dirty_bitmap));
assert(sector_num >= 0);
}
first_chunk = sector_num / sectors_per_chunk;
while (test_bit(first_chunk, s->in_flight_bitmap)) {
trace_mirror_yield_in_flight(s, sector_num, s->in_flight);
mirror_wait_for_io(s);
}
block_job_pause_point(&s->common);
while (nb_chunks * sectors_per_chunk < (s->buf_size >> BDRV_SECTOR_BITS)) {
int64_t hbitmap_next;
int64_t next_sector = sector_num + nb_chunks * sectors_per_chunk;
int64_t next_chunk = next_sector / sectors_per_chunk;
if (next_sector >= end ||
!bdrv_get_dirty(source, s->dirty_bitmap, next_sector)) {
break;
}
if (test_bit(next_chunk, s->in_flight_bitmap)) {
break;
}
hbitmap_next = hbitmap_iter_next(&s->hbi);
if (hbitmap_next > next_sector || hbitmap_next < 0) {
bdrv_set_dirty_iter(&s->hbi, next_sector);
hbitmap_next = hbitmap_iter_next(&s->hbi);
}
assert(hbitmap_next == next_sector);
nb_chunks++;
}
bdrv_reset_dirty_bitmap(s->dirty_bitmap, sector_num,
nb_chunks * sectors_per_chunk);
bitmap_set(s->in_flight_bitmap, sector_num / sectors_per_chunk, nb_chunks);
while (nb_chunks > 0 && sector_num < end) {
int ret;
int io_sectors, io_sectors_acct;
BlockDriverState *file;
enum MirrorMethod {
MIRROR_METHOD_COPY,
MIRROR_METHOD_ZERO,
MIRROR_METHOD_DISCARD
} mirror_method = MIRROR_METHOD_COPY;
assert(!(sector_num % sectors_per_chunk));
ret = bdrv_get_block_status_above(source, NULL, sector_num,
nb_chunks * sectors_per_chunk,
&io_sectors, &file);
if (ret < 0) {
io_sectors = nb_chunks * sectors_per_chunk;
}
io_sectors -= io_sectors % sectors_per_chunk;
if (io_sectors < sectors_per_chunk) {
io_sectors = sectors_per_chunk;
} else if (ret >= 0 && !(ret & BDRV_BLOCK_DATA)) {
int64_t target_sector_num;
int target_nb_sectors;
bdrv_round_sectors_to_clusters(blk_bs(s->target), sector_num,
io_sectors, &target_sector_num,
&target_nb_sectors);
if (target_sector_num == sector_num &&
target_nb_sectors == io_sectors) {
mirror_method = ret & BDRV_BLOCK_ZERO ?
MIRROR_METHOD_ZERO :
MIRROR_METHOD_DISCARD;
}
}
while (s->in_flight >= MAX_IN_FLIGHT) {
trace_mirror_yield_in_flight(s, sector_num, s->in_flight);
mirror_wait_for_io(s);
}
mirror_clip_sectors(s, sector_num, &io_sectors);
switch (mirror_method) {
case MIRROR_METHOD_COPY:
io_sectors = mirror_do_read(s, sector_num, io_sectors);
io_sectors_acct = io_sectors;
break;
case MIRROR_METHOD_ZERO:
case MIRROR_METHOD_DISCARD:
mirror_do_zero_or_discard(s, sector_num, io_sectors,
mirror_method == MIRROR_METHOD_DISCARD);
if (write_zeroes_ok) {
io_sectors_acct = 0;
} else {
io_sectors_acct = io_sectors;
}
break;
default:
abort();
}
assert(io_sectors);
sector_num += io_sectors;
nb_chunks -= DIV_ROUND_UP(io_sectors, sectors_per_chunk);
if (s->common.speed) {
delay_ns = ratelimit_calculate_delay(&s->limit, io_sectors_acct);
}
}
return delay_ns;
}
| {
"code": [],
"line_no": []
} | static uint64_t VAR_0 mirror_iteration(MirrorBlockJob *s)
{
BlockDriverState *source = blk_bs(s->common.blk);
int64_t sector_num, first_chunk;
uint64_t delay_ns = 0;
int nb_chunks = 1;
int64_t end = s->bdev_length / BDRV_SECTOR_SIZE;
int sectors_per_chunk = s->granularity >> BDRV_SECTOR_BITS;
bool write_zeroes_ok = bdrv_can_write_zeroes_with_unmap(blk_bs(s->target));
sector_num = hbitmap_iter_next(&s->hbi);
if (sector_num < 0) {
bdrv_dirty_iter_init(s->dirty_bitmap, &s->hbi);
sector_num = hbitmap_iter_next(&s->hbi);
trace_mirror_restart_iter(s, bdrv_get_dirty_count(s->dirty_bitmap));
assert(sector_num >= 0);
}
first_chunk = sector_num / sectors_per_chunk;
while (test_bit(first_chunk, s->in_flight_bitmap)) {
trace_mirror_yield_in_flight(s, sector_num, s->in_flight);
mirror_wait_for_io(s);
}
block_job_pause_point(&s->common);
while (nb_chunks * sectors_per_chunk < (s->buf_size >> BDRV_SECTOR_BITS)) {
int64_t hbitmap_next;
int64_t next_sector = sector_num + nb_chunks * sectors_per_chunk;
int64_t next_chunk = next_sector / sectors_per_chunk;
if (next_sector >= end ||
!bdrv_get_dirty(source, s->dirty_bitmap, next_sector)) {
break;
}
if (test_bit(next_chunk, s->in_flight_bitmap)) {
break;
}
hbitmap_next = hbitmap_iter_next(&s->hbi);
if (hbitmap_next > next_sector || hbitmap_next < 0) {
bdrv_set_dirty_iter(&s->hbi, next_sector);
hbitmap_next = hbitmap_iter_next(&s->hbi);
}
assert(hbitmap_next == next_sector);
nb_chunks++;
}
bdrv_reset_dirty_bitmap(s->dirty_bitmap, sector_num,
nb_chunks * sectors_per_chunk);
bitmap_set(s->in_flight_bitmap, sector_num / sectors_per_chunk, nb_chunks);
while (nb_chunks > 0 && sector_num < end) {
int ret;
int io_sectors, io_sectors_acct;
BlockDriverState *file;
enum MirrorMethod {
MIRROR_METHOD_COPY,
MIRROR_METHOD_ZERO,
MIRROR_METHOD_DISCARD
} mirror_method = MIRROR_METHOD_COPY;
assert(!(sector_num % sectors_per_chunk));
ret = bdrv_get_block_status_above(source, NULL, sector_num,
nb_chunks * sectors_per_chunk,
&io_sectors, &file);
if (ret < 0) {
io_sectors = nb_chunks * sectors_per_chunk;
}
io_sectors -= io_sectors % sectors_per_chunk;
if (io_sectors < sectors_per_chunk) {
io_sectors = sectors_per_chunk;
} else if (ret >= 0 && !(ret & BDRV_BLOCK_DATA)) {
int64_t target_sector_num;
int target_nb_sectors;
bdrv_round_sectors_to_clusters(blk_bs(s->target), sector_num,
io_sectors, &target_sector_num,
&target_nb_sectors);
if (target_sector_num == sector_num &&
target_nb_sectors == io_sectors) {
mirror_method = ret & BDRV_BLOCK_ZERO ?
MIRROR_METHOD_ZERO :
MIRROR_METHOD_DISCARD;
}
}
while (s->in_flight >= MAX_IN_FLIGHT) {
trace_mirror_yield_in_flight(s, sector_num, s->in_flight);
mirror_wait_for_io(s);
}
mirror_clip_sectors(s, sector_num, &io_sectors);
switch (mirror_method) {
case MIRROR_METHOD_COPY:
io_sectors = mirror_do_read(s, sector_num, io_sectors);
io_sectors_acct = io_sectors;
break;
case MIRROR_METHOD_ZERO:
case MIRROR_METHOD_DISCARD:
mirror_do_zero_or_discard(s, sector_num, io_sectors,
mirror_method == MIRROR_METHOD_DISCARD);
if (write_zeroes_ok) {
io_sectors_acct = 0;
} else {
io_sectors_acct = io_sectors;
}
break;
default:
abort();
}
assert(io_sectors);
sector_num += io_sectors;
nb_chunks -= DIV_ROUND_UP(io_sectors, sectors_per_chunk);
if (s->common.speed) {
delay_ns = ratelimit_calculate_delay(&s->limit, io_sectors_acct);
}
}
return delay_ns;
}
| [
"static uint64_t VAR_0 mirror_iteration(MirrorBlockJob *s)\n{",
"BlockDriverState *source = blk_bs(s->common.blk);",
"int64_t sector_num, first_chunk;",
"uint64_t delay_ns = 0;",
"int nb_chunks = 1;",
"int64_t end = s->bdev_length / BDRV_SECTOR_SIZE;",
"int sectors_per_chunk = s->granularity >> BDRV_SECTOR_BITS;",
"bool write_zeroes_ok = bdrv_can_write_zeroes_with_unmap(blk_bs(s->target));",
"sector_num = hbitmap_iter_next(&s->hbi);",
"if (sector_num < 0) {",
"bdrv_dirty_iter_init(s->dirty_bitmap, &s->hbi);",
"sector_num = hbitmap_iter_next(&s->hbi);",
"trace_mirror_restart_iter(s, bdrv_get_dirty_count(s->dirty_bitmap));",
"assert(sector_num >= 0);",
"}",
"first_chunk = sector_num / sectors_per_chunk;",
"while (test_bit(first_chunk, s->in_flight_bitmap)) {",
"trace_mirror_yield_in_flight(s, sector_num, s->in_flight);",
"mirror_wait_for_io(s);",
"}",
"block_job_pause_point(&s->common);",
"while (nb_chunks * sectors_per_chunk < (s->buf_size >> BDRV_SECTOR_BITS)) {",
"int64_t hbitmap_next;",
"int64_t next_sector = sector_num + nb_chunks * sectors_per_chunk;",
"int64_t next_chunk = next_sector / sectors_per_chunk;",
"if (next_sector >= end ||\n!bdrv_get_dirty(source, s->dirty_bitmap, next_sector)) {",
"break;",
"}",
"if (test_bit(next_chunk, s->in_flight_bitmap)) {",
"break;",
"}",
"hbitmap_next = hbitmap_iter_next(&s->hbi);",
"if (hbitmap_next > next_sector || hbitmap_next < 0) {",
"bdrv_set_dirty_iter(&s->hbi, next_sector);",
"hbitmap_next = hbitmap_iter_next(&s->hbi);",
"}",
"assert(hbitmap_next == next_sector);",
"nb_chunks++;",
"}",
"bdrv_reset_dirty_bitmap(s->dirty_bitmap, sector_num,\nnb_chunks * sectors_per_chunk);",
"bitmap_set(s->in_flight_bitmap, sector_num / sectors_per_chunk, nb_chunks);",
"while (nb_chunks > 0 && sector_num < end) {",
"int ret;",
"int io_sectors, io_sectors_acct;",
"BlockDriverState *file;",
"enum MirrorMethod {",
"MIRROR_METHOD_COPY,\nMIRROR_METHOD_ZERO,\nMIRROR_METHOD_DISCARD\n} mirror_method = MIRROR_METHOD_COPY;",
"assert(!(sector_num % sectors_per_chunk));",
"ret = bdrv_get_block_status_above(source, NULL, sector_num,\nnb_chunks * sectors_per_chunk,\n&io_sectors, &file);",
"if (ret < 0) {",
"io_sectors = nb_chunks * sectors_per_chunk;",
"}",
"io_sectors -= io_sectors % sectors_per_chunk;",
"if (io_sectors < sectors_per_chunk) {",
"io_sectors = sectors_per_chunk;",
"} else if (ret >= 0 && !(ret & BDRV_BLOCK_DATA)) {",
"int64_t target_sector_num;",
"int target_nb_sectors;",
"bdrv_round_sectors_to_clusters(blk_bs(s->target), sector_num,\nio_sectors, &target_sector_num,\n&target_nb_sectors);",
"if (target_sector_num == sector_num &&\ntarget_nb_sectors == io_sectors) {",
"mirror_method = ret & BDRV_BLOCK_ZERO ?\nMIRROR_METHOD_ZERO :\nMIRROR_METHOD_DISCARD;",
"}",
"}",
"while (s->in_flight >= MAX_IN_FLIGHT) {",
"trace_mirror_yield_in_flight(s, sector_num, s->in_flight);",
"mirror_wait_for_io(s);",
"}",
"mirror_clip_sectors(s, sector_num, &io_sectors);",
"switch (mirror_method) {",
"case MIRROR_METHOD_COPY:\nio_sectors = mirror_do_read(s, sector_num, io_sectors);",
"io_sectors_acct = io_sectors;",
"break;",
"case MIRROR_METHOD_ZERO:\ncase MIRROR_METHOD_DISCARD:\nmirror_do_zero_or_discard(s, sector_num, io_sectors,\nmirror_method == MIRROR_METHOD_DISCARD);",
"if (write_zeroes_ok) {",
"io_sectors_acct = 0;",
"} else {",
"io_sectors_acct = io_sectors;",
"}",
"break;",
"default:\nabort();",
"}",
"assert(io_sectors);",
"sector_num += io_sectors;",
"nb_chunks -= DIV_ROUND_UP(io_sectors, sectors_per_chunk);",
"if (s->common.speed) {",
"delay_ns = ratelimit_calculate_delay(&s->limit, io_sectors_acct);",
"}",
"}",
"return delay_ns;",
"}"
]
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|
10,306 | static void flush_encoders(void)
{
int i, ret;
for (i = 0; i < nb_output_streams; i++) {
OutputStream *ost = output_streams[i];
AVCodecContext *enc = ost->enc_ctx;
AVFormatContext *os = output_files[ost->file_index]->ctx;
int stop_encoding = 0;
if (!ost->encoding_needed)
continue;
if (enc->codec_type == AVMEDIA_TYPE_AUDIO && enc->frame_size <= 1)
continue;
if (enc->codec_type != AVMEDIA_TYPE_VIDEO && enc->codec_type != AVMEDIA_TYPE_AUDIO)
continue;
avcodec_send_frame(enc, NULL);
for (;;) {
const char *desc = NULL;
switch (enc->codec_type) {
case AVMEDIA_TYPE_AUDIO:
desc = "Audio";
break;
case AVMEDIA_TYPE_VIDEO:
desc = "Video";
break;
default:
av_assert0(0);
}
if (1) {
AVPacket pkt;
av_init_packet(&pkt);
pkt.data = NULL;
pkt.size = 0;
ret = avcodec_receive_packet(enc, &pkt);
if (ret < 0 && ret != AVERROR_EOF) {
av_log(NULL, AV_LOG_FATAL, "%s encoding failed\n", desc);
exit_program(1);
}
if (ost->logfile && enc->stats_out) {
fprintf(ost->logfile, "%s", enc->stats_out);
}
if (ret == AVERROR_EOF) {
stop_encoding = 1;
break;
}
av_packet_rescale_ts(&pkt, enc->time_base, ost->st->time_base);
output_packet(os, &pkt, ost);
}
if (stop_encoding)
break;
}
}
}
| false | FFmpeg | 398f015f077c6a2406deffd9e37ff34b9c7bb3bc | static void flush_encoders(void)
{
int i, ret;
for (i = 0; i < nb_output_streams; i++) {
OutputStream *ost = output_streams[i];
AVCodecContext *enc = ost->enc_ctx;
AVFormatContext *os = output_files[ost->file_index]->ctx;
int stop_encoding = 0;
if (!ost->encoding_needed)
continue;
if (enc->codec_type == AVMEDIA_TYPE_AUDIO && enc->frame_size <= 1)
continue;
if (enc->codec_type != AVMEDIA_TYPE_VIDEO && enc->codec_type != AVMEDIA_TYPE_AUDIO)
continue;
avcodec_send_frame(enc, NULL);
for (;;) {
const char *desc = NULL;
switch (enc->codec_type) {
case AVMEDIA_TYPE_AUDIO:
desc = "Audio";
break;
case AVMEDIA_TYPE_VIDEO:
desc = "Video";
break;
default:
av_assert0(0);
}
if (1) {
AVPacket pkt;
av_init_packet(&pkt);
pkt.data = NULL;
pkt.size = 0;
ret = avcodec_receive_packet(enc, &pkt);
if (ret < 0 && ret != AVERROR_EOF) {
av_log(NULL, AV_LOG_FATAL, "%s encoding failed\n", desc);
exit_program(1);
}
if (ost->logfile && enc->stats_out) {
fprintf(ost->logfile, "%s", enc->stats_out);
}
if (ret == AVERROR_EOF) {
stop_encoding = 1;
break;
}
av_packet_rescale_ts(&pkt, enc->time_base, ost->st->time_base);
output_packet(os, &pkt, ost);
}
if (stop_encoding)
break;
}
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void)
{
int VAR_0, VAR_1;
for (VAR_0 = 0; VAR_0 < nb_output_streams; VAR_0++) {
OutputStream *ost = output_streams[VAR_0];
AVCodecContext *enc = ost->enc_ctx;
AVFormatContext *os = output_files[ost->file_index]->ctx;
int stop_encoding = 0;
if (!ost->encoding_needed)
continue;
if (enc->codec_type == AVMEDIA_TYPE_AUDIO && enc->frame_size <= 1)
continue;
if (enc->codec_type != AVMEDIA_TYPE_VIDEO && enc->codec_type != AVMEDIA_TYPE_AUDIO)
continue;
avcodec_send_frame(enc, NULL);
for (;;) {
const char *desc = NULL;
switch (enc->codec_type) {
case AVMEDIA_TYPE_AUDIO:
desc = "Audio";
break;
case AVMEDIA_TYPE_VIDEO:
desc = "Video";
break;
default:
av_assert0(0);
}
if (1) {
AVPacket pkt;
av_init_packet(&pkt);
pkt.data = NULL;
pkt.size = 0;
VAR_1 = avcodec_receive_packet(enc, &pkt);
if (VAR_1 < 0 && VAR_1 != AVERROR_EOF) {
av_log(NULL, AV_LOG_FATAL, "%s encoding failed\n", desc);
exit_program(1);
}
if (ost->logfile && enc->stats_out) {
fprintf(ost->logfile, "%s", enc->stats_out);
}
if (VAR_1 == AVERROR_EOF) {
stop_encoding = 1;
break;
}
av_packet_rescale_ts(&pkt, enc->time_base, ost->st->time_base);
output_packet(os, &pkt, ost);
}
if (stop_encoding)
break;
}
}
}
| [
"static void FUNC_0(void)\n{",
"int VAR_0, VAR_1;",
"for (VAR_0 = 0; VAR_0 < nb_output_streams; VAR_0++) {",
"OutputStream *ost = output_streams[VAR_0];",
"AVCodecContext *enc = ost->enc_ctx;",
"AVFormatContext *os = output_files[ost->file_index]->ctx;",
"int stop_encoding = 0;",
"if (!ost->encoding_needed)\ncontinue;",
"if (enc->codec_type == AVMEDIA_TYPE_AUDIO && enc->frame_size <= 1)\ncontinue;",
"if (enc->codec_type != AVMEDIA_TYPE_VIDEO && enc->codec_type != AVMEDIA_TYPE_AUDIO)\ncontinue;",
"avcodec_send_frame(enc, NULL);",
"for (;;) {",
"const char *desc = NULL;",
"switch (enc->codec_type) {",
"case AVMEDIA_TYPE_AUDIO:\ndesc = \"Audio\";",
"break;",
"case AVMEDIA_TYPE_VIDEO:\ndesc = \"Video\";",
"break;",
"default:\nav_assert0(0);",
"}",
"if (1) {",
"AVPacket pkt;",
"av_init_packet(&pkt);",
"pkt.data = NULL;",
"pkt.size = 0;",
"VAR_1 = avcodec_receive_packet(enc, &pkt);",
"if (VAR_1 < 0 && VAR_1 != AVERROR_EOF) {",
"av_log(NULL, AV_LOG_FATAL, \"%s encoding failed\\n\", desc);",
"exit_program(1);",
"}",
"if (ost->logfile && enc->stats_out) {",
"fprintf(ost->logfile, \"%s\", enc->stats_out);",
"}",
"if (VAR_1 == AVERROR_EOF) {",
"stop_encoding = 1;",
"break;",
"}",
"av_packet_rescale_ts(&pkt, enc->time_base, ost->st->time_base);",
"output_packet(os, &pkt, ost);",
"}",
"if (stop_encoding)\nbreak;",
"}",
"}",
"}"
]
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115,
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123
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|
10,307 | AVFormatContext *ff_rtp_chain_mux_open(AVFormatContext *s, AVStream *st,
URLContext *handle, int packet_size)
{
AVFormatContext *rtpctx;
int ret;
AVOutputFormat *rtp_format = av_guess_format("rtp", NULL, NULL);
if (!rtp_format)
return NULL;
/* Allocate an AVFormatContext for each output stream */
rtpctx = avformat_alloc_context();
if (!rtpctx)
return NULL;
rtpctx->oformat = rtp_format;
if (!av_new_stream(rtpctx, 0)) {
av_free(rtpctx);
return NULL;
}
/* Copy the max delay setting; the rtp muxer reads this. */
rtpctx->max_delay = s->max_delay;
/* Copy other stream parameters. */
rtpctx->streams[0]->sample_aspect_ratio = st->sample_aspect_ratio;
/* Set the synchronized start time. */
rtpctx->start_time_realtime = s->start_time_realtime;
avcodec_copy_context(rtpctx->streams[0]->codec, st->codec);
if (handle) {
url_fdopen(&rtpctx->pb, handle);
} else
url_open_dyn_packet_buf(&rtpctx->pb, packet_size);
ret = av_write_header(rtpctx);
if (ret) {
if (handle) {
avio_close(rtpctx->pb);
} else {
uint8_t *ptr;
avio_close_dyn_buf(rtpctx->pb, &ptr);
av_free(ptr);
}
avformat_free_context(rtpctx);
return NULL;
}
return rtpctx;
}
| false | FFmpeg | 403ee835e7913eb9536b22c2b22edfdd700166a9 | AVFormatContext *ff_rtp_chain_mux_open(AVFormatContext *s, AVStream *st,
URLContext *handle, int packet_size)
{
AVFormatContext *rtpctx;
int ret;
AVOutputFormat *rtp_format = av_guess_format("rtp", NULL, NULL);
if (!rtp_format)
return NULL;
rtpctx = avformat_alloc_context();
if (!rtpctx)
return NULL;
rtpctx->oformat = rtp_format;
if (!av_new_stream(rtpctx, 0)) {
av_free(rtpctx);
return NULL;
}
rtpctx->max_delay = s->max_delay;
rtpctx->streams[0]->sample_aspect_ratio = st->sample_aspect_ratio;
rtpctx->start_time_realtime = s->start_time_realtime;
avcodec_copy_context(rtpctx->streams[0]->codec, st->codec);
if (handle) {
url_fdopen(&rtpctx->pb, handle);
} else
url_open_dyn_packet_buf(&rtpctx->pb, packet_size);
ret = av_write_header(rtpctx);
if (ret) {
if (handle) {
avio_close(rtpctx->pb);
} else {
uint8_t *ptr;
avio_close_dyn_buf(rtpctx->pb, &ptr);
av_free(ptr);
}
avformat_free_context(rtpctx);
return NULL;
}
return rtpctx;
}
| {
"code": [],
"line_no": []
} | AVFormatContext *FUNC_0(AVFormatContext *s, AVStream *st,
URLContext *handle, int packet_size)
{
AVFormatContext *rtpctx;
int VAR_0;
AVOutputFormat *rtp_format = av_guess_format("rtp", NULL, NULL);
if (!rtp_format)
return NULL;
rtpctx = avformat_alloc_context();
if (!rtpctx)
return NULL;
rtpctx->oformat = rtp_format;
if (!av_new_stream(rtpctx, 0)) {
av_free(rtpctx);
return NULL;
}
rtpctx->max_delay = s->max_delay;
rtpctx->streams[0]->sample_aspect_ratio = st->sample_aspect_ratio;
rtpctx->start_time_realtime = s->start_time_realtime;
avcodec_copy_context(rtpctx->streams[0]->codec, st->codec);
if (handle) {
url_fdopen(&rtpctx->pb, handle);
} else
url_open_dyn_packet_buf(&rtpctx->pb, packet_size);
VAR_0 = av_write_header(rtpctx);
if (VAR_0) {
if (handle) {
avio_close(rtpctx->pb);
} else {
uint8_t *ptr;
avio_close_dyn_buf(rtpctx->pb, &ptr);
av_free(ptr);
}
avformat_free_context(rtpctx);
return NULL;
}
return rtpctx;
}
| [
"AVFormatContext *FUNC_0(AVFormatContext *s, AVStream *st,\nURLContext *handle, int packet_size)\n{",
"AVFormatContext *rtpctx;",
"int VAR_0;",
"AVOutputFormat *rtp_format = av_guess_format(\"rtp\", NULL, NULL);",
"if (!rtp_format)\nreturn NULL;",
"rtpctx = avformat_alloc_context();",
"if (!rtpctx)\nreturn NULL;",
"rtpctx->oformat = rtp_format;",
"if (!av_new_stream(rtpctx, 0)) {",
"av_free(rtpctx);",
"return NULL;",
"}",
"rtpctx->max_delay = s->max_delay;",
"rtpctx->streams[0]->sample_aspect_ratio = st->sample_aspect_ratio;",
"rtpctx->start_time_realtime = s->start_time_realtime;",
"avcodec_copy_context(rtpctx->streams[0]->codec, st->codec);",
"if (handle) {",
"url_fdopen(&rtpctx->pb, handle);",
"} else",
"url_open_dyn_packet_buf(&rtpctx->pb, packet_size);",
"VAR_0 = av_write_header(rtpctx);",
"if (VAR_0) {",
"if (handle) {",
"avio_close(rtpctx->pb);",
"} else {",
"uint8_t *ptr;",
"avio_close_dyn_buf(rtpctx->pb, &ptr);",
"av_free(ptr);",
"}",
"avformat_free_context(rtpctx);",
"return NULL;",
"}",
"return rtpctx;",
"}"
]
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],
[
77
],
[
79
],
[
81
],
[
83
],
[
85
],
[
87
],
[
89
],
[
91
],
[
93
],
[
97
],
[
99
]
]
|
10,309 | static av_cold int avs_decode_init(AVCodecContext * avctx)
{
AvsContext *s = avctx->priv_data;
s->frame = av_frame_alloc();
if (!s->frame)
return AVERROR(ENOMEM);
avctx->pix_fmt = AV_PIX_FMT_PAL8;
ff_set_dimensions(avctx, 318, 198);
return 0;
}
| false | FFmpeg | c7384664ba0cbb12d882effafbc6d321ae706cff | static av_cold int avs_decode_init(AVCodecContext * avctx)
{
AvsContext *s = avctx->priv_data;
s->frame = av_frame_alloc();
if (!s->frame)
return AVERROR(ENOMEM);
avctx->pix_fmt = AV_PIX_FMT_PAL8;
ff_set_dimensions(avctx, 318, 198);
return 0;
}
| {
"code": [],
"line_no": []
} | static av_cold int FUNC_0(AVCodecContext * avctx)
{
AvsContext *s = avctx->priv_data;
s->frame = av_frame_alloc();
if (!s->frame)
return AVERROR(ENOMEM);
avctx->pix_fmt = AV_PIX_FMT_PAL8;
ff_set_dimensions(avctx, 318, 198);
return 0;
}
| [
"static av_cold int FUNC_0(AVCodecContext * avctx)\n{",
"AvsContext *s = avctx->priv_data;",
"s->frame = av_frame_alloc();",
"if (!s->frame)\nreturn AVERROR(ENOMEM);",
"avctx->pix_fmt = AV_PIX_FMT_PAL8;",
"ff_set_dimensions(avctx, 318, 198);",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11,
13
],
[
17
],
[
19
],
[
23
],
[
25
]
]
|
10,310 | static av_cold int raw_encode_close(AVCodecContext *avctx)
{
av_frame_free(&avctx->coded_frame);
return 0;
}
| false | FFmpeg | d6604b29ef544793479d7fb4e05ef6622bb3e534 | static av_cold int raw_encode_close(AVCodecContext *avctx)
{
av_frame_free(&avctx->coded_frame);
return 0;
}
| {
"code": [],
"line_no": []
} | static av_cold int FUNC_0(AVCodecContext *avctx)
{
av_frame_free(&avctx->coded_frame);
return 0;
}
| [
"static av_cold int FUNC_0(AVCodecContext *avctx)\n{",
"av_frame_free(&avctx->coded_frame);",
"return 0;",
"}"
]
| [
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
]
]
|
10,311 | int avio_close_dyn_buf(AVIOContext *s, uint8_t **pbuffer)
{
DynBuffer *d;
int size;
static const char padbuf[AV_INPUT_BUFFER_PADDING_SIZE] = {0};
int padding = 0;
if (!s) {
*pbuffer = NULL;
return 0;
}
/* don't attempt to pad fixed-size packet buffers */
if (!s->max_packet_size) {
avio_write(s, padbuf, sizeof(padbuf));
padding = AV_INPUT_BUFFER_PADDING_SIZE;
}
avio_flush(s);
d = s->opaque;
*pbuffer = d->buffer;
size = d->size;
av_free(d);
av_free(s);
return size - padding;
}
| false | FFmpeg | b12e4d3bb8df994f042ff1216fb8de2b967aab9e | int avio_close_dyn_buf(AVIOContext *s, uint8_t **pbuffer)
{
DynBuffer *d;
int size;
static const char padbuf[AV_INPUT_BUFFER_PADDING_SIZE] = {0};
int padding = 0;
if (!s) {
*pbuffer = NULL;
return 0;
}
if (!s->max_packet_size) {
avio_write(s, padbuf, sizeof(padbuf));
padding = AV_INPUT_BUFFER_PADDING_SIZE;
}
avio_flush(s);
d = s->opaque;
*pbuffer = d->buffer;
size = d->size;
av_free(d);
av_free(s);
return size - padding;
}
| {
"code": [],
"line_no": []
} | int FUNC_0(AVIOContext *VAR_0, uint8_t **VAR_1)
{
DynBuffer *d;
int VAR_2;
static const char VAR_3[AV_INPUT_BUFFER_PADDING_SIZE] = {0};
int VAR_4 = 0;
if (!VAR_0) {
*VAR_1 = NULL;
return 0;
}
if (!VAR_0->max_packet_size) {
avio_write(VAR_0, VAR_3, sizeof(VAR_3));
VAR_4 = AV_INPUT_BUFFER_PADDING_SIZE;
}
avio_flush(VAR_0);
d = VAR_0->opaque;
*VAR_1 = d->buffer;
VAR_2 = d->VAR_2;
av_free(d);
av_free(VAR_0);
return VAR_2 - VAR_4;
}
| [
"int FUNC_0(AVIOContext *VAR_0, uint8_t **VAR_1)\n{",
"DynBuffer *d;",
"int VAR_2;",
"static const char VAR_3[AV_INPUT_BUFFER_PADDING_SIZE] = {0};",
"int VAR_4 = 0;",
"if (!VAR_0) {",
"*VAR_1 = NULL;",
"return 0;",
"}",
"if (!VAR_0->max_packet_size) {",
"avio_write(VAR_0, VAR_3, sizeof(VAR_3));",
"VAR_4 = AV_INPUT_BUFFER_PADDING_SIZE;",
"}",
"avio_flush(VAR_0);",
"d = VAR_0->opaque;",
"*VAR_1 = d->buffer;",
"VAR_2 = d->VAR_2;",
"av_free(d);",
"av_free(VAR_0);",
"return VAR_2 - VAR_4;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17
],
[
19
],
[
21
],
[
27
],
[
29
],
[
31
],
[
33
],
[
37
],
[
41
],
[
43
],
[
45
],
[
47
],
[
49
],
[
51
],
[
53
]
]
|
10,312 | void pcie_port_init_reg(PCIDevice *d)
{
/* Unlike pci bridge,
66MHz and fast back to back don't apply to pci express port. */
pci_set_word(d->config + PCI_STATUS, 0);
pci_set_word(d->config + PCI_SEC_STATUS, 0);
/* Unlike conventional pci bridge, some bits are hardwired to 0. */
#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_VGA_16BIT | /* Req, but no alias support yet */
PCI_BRIDGE_CTL_SERR |
PCI_BRIDGE_CTL_BUS_RESET);
}
| false | qemu | 45eb768c706d3a5fbe55224c589e8b4e252781d9 | void pcie_port_init_reg(PCIDevice *d)
{
pci_set_word(d->config + PCI_STATUS, 0);
pci_set_word(d->config + PCI_SEC_STATUS, 0);
#define PCI_BRIDGE_CTL_VGA_16BIT 0x10
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_VGA_16BIT |
PCI_BRIDGE_CTL_SERR |
PCI_BRIDGE_CTL_BUS_RESET);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(PCIDevice *VAR_0)
{
pci_set_word(VAR_0->config + PCI_STATUS, 0);
pci_set_word(VAR_0->config + PCI_SEC_STATUS, 0);
#define PCI_BRIDGE_CTL_VGA_16BIT 0x10
pci_set_word(VAR_0->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_VGA_16BIT |
PCI_BRIDGE_CTL_SERR |
PCI_BRIDGE_CTL_BUS_RESET);
}
| [
"void FUNC_0(PCIDevice *VAR_0)\n{",
"pci_set_word(VAR_0->config + PCI_STATUS, 0);",
"pci_set_word(VAR_0->config + PCI_SEC_STATUS, 0);",
"#define PCI_BRIDGE_CTL_VGA_16BIT 0x10\npci_set_word(VAR_0->wmask + PCI_BRIDGE_CONTROL,\nPCI_BRIDGE_CTL_PARITY |\nPCI_BRIDGE_CTL_ISA |\nPCI_BRIDGE_CTL_VGA |\nPCI_BRIDGE_CTL_VGA_16BIT |\nPCI_BRIDGE_CTL_SERR |\nPCI_BRIDGE_CTL_BUS_RESET);",
"}"
]
| [
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
9
],
[
11
],
[
17,
19,
21,
23,
25,
27,
29,
31
],
[
33
]
]
|
10,313 | static void get_slice_data(ProresContext *ctx, const uint16_t *src,
int linesize, int x, int y, int w, int h,
DCTELEM *blocks, uint16_t *emu_buf,
int mbs_per_slice, int blocks_per_mb, int is_chroma)
{
const uint16_t *esrc;
const int mb_width = 4 * blocks_per_mb;
int elinesize;
int i, j, k;
for (i = 0; i < mbs_per_slice; i++, src += mb_width) {
if (x >= w) {
memset(blocks, 0, 64 * (mbs_per_slice - i) * blocks_per_mb
* sizeof(*blocks));
return;
}
if (x + mb_width <= w && y + 16 <= h) {
esrc = src;
elinesize = linesize;
} else {
int bw, bh, pix;
esrc = emu_buf;
elinesize = 16 * sizeof(*emu_buf);
bw = FFMIN(w - x, mb_width);
bh = FFMIN(h - y, 16);
for (j = 0; j < bh; j++) {
memcpy(emu_buf + j * 16,
(const uint8_t*)src + j * linesize,
bw * sizeof(*src));
pix = emu_buf[j * 16 + bw - 1];
for (k = bw; k < mb_width; k++)
emu_buf[j * 16 + k] = pix;
}
for (; j < 16; j++)
memcpy(emu_buf + j * 16,
emu_buf + (bh - 1) * 16,
mb_width * sizeof(*emu_buf));
}
if (!is_chroma) {
ctx->dsp.fdct(esrc, elinesize, blocks);
blocks += 64;
if (blocks_per_mb > 2) {
ctx->dsp.fdct(src + 8, linesize, blocks);
blocks += 64;
}
ctx->dsp.fdct(src + linesize * 4, linesize, blocks);
blocks += 64;
if (blocks_per_mb > 2) {
ctx->dsp.fdct(src + linesize * 4 + 8, linesize, blocks);
blocks += 64;
}
} else {
ctx->dsp.fdct(esrc, elinesize, blocks);
blocks += 64;
ctx->dsp.fdct(src + linesize * 4, linesize, blocks);
blocks += 64;
if (blocks_per_mb > 2) {
ctx->dsp.fdct(src + 8, linesize, blocks);
blocks += 64;
ctx->dsp.fdct(src + linesize * 4 + 8, linesize, blocks);
blocks += 64;
}
}
x += mb_width;
}
}
| false | FFmpeg | cee03436e6f1e3d4893841698e73caa92f2a53c9 | static void get_slice_data(ProresContext *ctx, const uint16_t *src,
int linesize, int x, int y, int w, int h,
DCTELEM *blocks, uint16_t *emu_buf,
int mbs_per_slice, int blocks_per_mb, int is_chroma)
{
const uint16_t *esrc;
const int mb_width = 4 * blocks_per_mb;
int elinesize;
int i, j, k;
for (i = 0; i < mbs_per_slice; i++, src += mb_width) {
if (x >= w) {
memset(blocks, 0, 64 * (mbs_per_slice - i) * blocks_per_mb
* sizeof(*blocks));
return;
}
if (x + mb_width <= w && y + 16 <= h) {
esrc = src;
elinesize = linesize;
} else {
int bw, bh, pix;
esrc = emu_buf;
elinesize = 16 * sizeof(*emu_buf);
bw = FFMIN(w - x, mb_width);
bh = FFMIN(h - y, 16);
for (j = 0; j < bh; j++) {
memcpy(emu_buf + j * 16,
(const uint8_t*)src + j * linesize,
bw * sizeof(*src));
pix = emu_buf[j * 16 + bw - 1];
for (k = bw; k < mb_width; k++)
emu_buf[j * 16 + k] = pix;
}
for (; j < 16; j++)
memcpy(emu_buf + j * 16,
emu_buf + (bh - 1) * 16,
mb_width * sizeof(*emu_buf));
}
if (!is_chroma) {
ctx->dsp.fdct(esrc, elinesize, blocks);
blocks += 64;
if (blocks_per_mb > 2) {
ctx->dsp.fdct(src + 8, linesize, blocks);
blocks += 64;
}
ctx->dsp.fdct(src + linesize * 4, linesize, blocks);
blocks += 64;
if (blocks_per_mb > 2) {
ctx->dsp.fdct(src + linesize * 4 + 8, linesize, blocks);
blocks += 64;
}
} else {
ctx->dsp.fdct(esrc, elinesize, blocks);
blocks += 64;
ctx->dsp.fdct(src + linesize * 4, linesize, blocks);
blocks += 64;
if (blocks_per_mb > 2) {
ctx->dsp.fdct(src + 8, linesize, blocks);
blocks += 64;
ctx->dsp.fdct(src + linesize * 4 + 8, linesize, blocks);
blocks += 64;
}
}
x += mb_width;
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(ProresContext *VAR_0, const uint16_t *VAR_1,
int VAR_2, int VAR_3, int VAR_4, int VAR_5, int VAR_6,
DCTELEM *VAR_7, uint16_t *VAR_8,
int VAR_9, int VAR_10, int VAR_11)
{
const uint16_t *VAR_12;
const int VAR_13 = 4 * VAR_10;
int VAR_14;
int VAR_15, VAR_16, VAR_17;
for (VAR_15 = 0; VAR_15 < VAR_9; VAR_15++, VAR_1 += VAR_13) {
if (VAR_3 >= VAR_5) {
memset(VAR_7, 0, 64 * (VAR_9 - VAR_15) * VAR_10
* sizeof(*VAR_7));
return;
}
if (VAR_3 + VAR_13 <= VAR_5 && VAR_4 + 16 <= VAR_6) {
VAR_12 = VAR_1;
VAR_14 = VAR_2;
} else {
int VAR_18, VAR_19, VAR_20;
VAR_12 = VAR_8;
VAR_14 = 16 * sizeof(*VAR_8);
VAR_18 = FFMIN(VAR_5 - VAR_3, VAR_13);
VAR_19 = FFMIN(VAR_6 - VAR_4, 16);
for (VAR_16 = 0; VAR_16 < VAR_19; VAR_16++) {
memcpy(VAR_8 + VAR_16 * 16,
(const uint8_t*)VAR_1 + VAR_16 * VAR_2,
VAR_18 * sizeof(*VAR_1));
VAR_20 = VAR_8[VAR_16 * 16 + VAR_18 - 1];
for (VAR_17 = VAR_18; VAR_17 < VAR_13; VAR_17++)
VAR_8[VAR_16 * 16 + VAR_17] = VAR_20;
}
for (; VAR_16 < 16; VAR_16++)
memcpy(VAR_8 + VAR_16 * 16,
VAR_8 + (VAR_19 - 1) * 16,
VAR_13 * sizeof(*VAR_8));
}
if (!VAR_11) {
VAR_0->dsp.fdct(VAR_12, VAR_14, VAR_7);
VAR_7 += 64;
if (VAR_10 > 2) {
VAR_0->dsp.fdct(VAR_1 + 8, VAR_2, VAR_7);
VAR_7 += 64;
}
VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4, VAR_2, VAR_7);
VAR_7 += 64;
if (VAR_10 > 2) {
VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4 + 8, VAR_2, VAR_7);
VAR_7 += 64;
}
} else {
VAR_0->dsp.fdct(VAR_12, VAR_14, VAR_7);
VAR_7 += 64;
VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4, VAR_2, VAR_7);
VAR_7 += 64;
if (VAR_10 > 2) {
VAR_0->dsp.fdct(VAR_1 + 8, VAR_2, VAR_7);
VAR_7 += 64;
VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4 + 8, VAR_2, VAR_7);
VAR_7 += 64;
}
}
VAR_3 += VAR_13;
}
}
| [
"static void FUNC_0(ProresContext *VAR_0, const uint16_t *VAR_1,\nint VAR_2, int VAR_3, int VAR_4, int VAR_5, int VAR_6,\nDCTELEM *VAR_7, uint16_t *VAR_8,\nint VAR_9, int VAR_10, int VAR_11)\n{",
"const uint16_t *VAR_12;",
"const int VAR_13 = 4 * VAR_10;",
"int VAR_14;",
"int VAR_15, VAR_16, VAR_17;",
"for (VAR_15 = 0; VAR_15 < VAR_9; VAR_15++, VAR_1 += VAR_13) {",
"if (VAR_3 >= VAR_5) {",
"memset(VAR_7, 0, 64 * (VAR_9 - VAR_15) * VAR_10\n* sizeof(*VAR_7));",
"return;",
"}",
"if (VAR_3 + VAR_13 <= VAR_5 && VAR_4 + 16 <= VAR_6) {",
"VAR_12 = VAR_1;",
"VAR_14 = VAR_2;",
"} else {",
"int VAR_18, VAR_19, VAR_20;",
"VAR_12 = VAR_8;",
"VAR_14 = 16 * sizeof(*VAR_8);",
"VAR_18 = FFMIN(VAR_5 - VAR_3, VAR_13);",
"VAR_19 = FFMIN(VAR_6 - VAR_4, 16);",
"for (VAR_16 = 0; VAR_16 < VAR_19; VAR_16++) {",
"memcpy(VAR_8 + VAR_16 * 16,\n(const uint8_t*)VAR_1 + VAR_16 * VAR_2,\nVAR_18 * sizeof(*VAR_1));",
"VAR_20 = VAR_8[VAR_16 * 16 + VAR_18 - 1];",
"for (VAR_17 = VAR_18; VAR_17 < VAR_13; VAR_17++)",
"VAR_8[VAR_16 * 16 + VAR_17] = VAR_20;",
"}",
"for (; VAR_16 < 16; VAR_16++)",
"memcpy(VAR_8 + VAR_16 * 16,\nVAR_8 + (VAR_19 - 1) * 16,\nVAR_13 * sizeof(*VAR_8));",
"}",
"if (!VAR_11) {",
"VAR_0->dsp.fdct(VAR_12, VAR_14, VAR_7);",
"VAR_7 += 64;",
"if (VAR_10 > 2) {",
"VAR_0->dsp.fdct(VAR_1 + 8, VAR_2, VAR_7);",
"VAR_7 += 64;",
"}",
"VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4, VAR_2, VAR_7);",
"VAR_7 += 64;",
"if (VAR_10 > 2) {",
"VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4 + 8, VAR_2, VAR_7);",
"VAR_7 += 64;",
"}",
"} else {",
"VAR_0->dsp.fdct(VAR_12, VAR_14, VAR_7);",
"VAR_7 += 64;",
"VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4, VAR_2, VAR_7);",
"VAR_7 += 64;",
"if (VAR_10 > 2) {",
"VAR_0->dsp.fdct(VAR_1 + 8, VAR_2, VAR_7);",
"VAR_7 += 64;",
"VAR_0->dsp.fdct(VAR_1 + VAR_2 * 4 + 8, VAR_2, VAR_7);",
"VAR_7 += 64;",
"}",
"}",
"VAR_3 += VAR_13;",
"}",
"}"
]
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0,
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]
| [
[
1,
3,
5,
7,
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25,
27
],
[
29
],
[
31
],
[
33
],
[
35
],
[
37
],
[
39
],
[
41
],
[
45
],
[
47
],
[
51
],
[
53
],
[
57
],
[
59,
61,
63
],
[
65
],
[
67
],
[
69
],
[
71
],
[
73
],
[
75,
77,
79
],
[
81
],
[
83
],
[
85
],
[
87
],
[
89
],
[
91
],
[
93
],
[
95
],
[
97
],
[
99
],
[
101
],
[
103
],
[
105
],
[
107
],
[
109
],
[
111
],
[
113
],
[
115
],
[
117
],
[
119
],
[
121
],
[
123
],
[
125
],
[
127
],
[
129
],
[
131
],
[
135
],
[
137
],
[
139
]
]
|
10,314 | static always_inline void gen_farith3 (void *helper,
int ra, int rb, int rc)
{
if (unlikely(rc == 31))
return;
if (ra != 31) {
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]);
else {
TCGv tmp = tcg_const_i64(0);
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp);
tcg_temp_free(tmp);
}
} else {
TCGv tmp = tcg_const_i64(0);
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]);
else
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp);
tcg_temp_free(tmp);
}
}
| false | qemu | a7812ae412311d7d47f8aa85656faadac9d64b56 | static always_inline void gen_farith3 (void *helper,
int ra, int rb, int rc)
{
if (unlikely(rc == 31))
return;
if (ra != 31) {
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]);
else {
TCGv tmp = tcg_const_i64(0);
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp);
tcg_temp_free(tmp);
}
} else {
TCGv tmp = tcg_const_i64(0);
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]);
else
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp);
tcg_temp_free(tmp);
}
}
| {
"code": [],
"line_no": []
} | static always_inline void FUNC_0 (void *helper,
int ra, int rb, int rc)
{
if (unlikely(rc == 31))
return;
if (ra != 31) {
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]);
else {
TCGv tmp = tcg_const_i64(0);
tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp);
tcg_temp_free(tmp);
}
} else {
TCGv tmp = tcg_const_i64(0);
if (rb != 31)
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]);
else
tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp);
tcg_temp_free(tmp);
}
}
| [
"static always_inline void FUNC_0 (void *helper,\nint ra, int rb, int rc)\n{",
"if (unlikely(rc == 31))\nreturn;",
"if (ra != 31) {",
"if (rb != 31)\ntcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]);",
"else {",
"TCGv tmp = tcg_const_i64(0);",
"tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp);",
"tcg_temp_free(tmp);",
"}",
"} else {",
"TCGv tmp = tcg_const_i64(0);",
"if (rb != 31)\ntcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]);",
"else\ntcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp);",
"tcg_temp_free(tmp);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3,
5
],
[
7,
9
],
[
13
],
[
15,
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33,
35
],
[
37,
39
],
[
41
],
[
43
],
[
45
]
]
|
10,315 | static bool vfio_prereg_listener_skipped_section(MemoryRegionSection *section)
{
if (memory_region_is_iommu(section->mr)) {
hw_error("Cannot possibly preregister IOMMU memory");
}
return !memory_region_is_ram(section->mr) ||
memory_region_is_skip_dump(section->mr);
}
| false | qemu | 21e00fa55f3fdfcbb20da7c6876c91ef3609b387 | static bool vfio_prereg_listener_skipped_section(MemoryRegionSection *section)
{
if (memory_region_is_iommu(section->mr)) {
hw_error("Cannot possibly preregister IOMMU memory");
}
return !memory_region_is_ram(section->mr) ||
memory_region_is_skip_dump(section->mr);
}
| {
"code": [],
"line_no": []
} | static bool FUNC_0(MemoryRegionSection *section)
{
if (memory_region_is_iommu(section->mr)) {
hw_error("Cannot possibly preregister IOMMU memory");
}
return !memory_region_is_ram(section->mr) ||
memory_region_is_skip_dump(section->mr);
}
| [
"static bool FUNC_0(MemoryRegionSection *section)\n{",
"if (memory_region_is_iommu(section->mr)) {",
"hw_error(\"Cannot possibly preregister IOMMU memory\");",
"}",
"return !memory_region_is_ram(section->mr) ||\nmemory_region_is_skip_dump(section->mr);",
"}"
]
| [
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
13,
15
],
[
17
]
]
|
10,318 | static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
switch (reg) {
case 0:
switch (sel) {
case 0:
gen_op_mtc0_index();
rn = "Index";
break;
case 1:
// gen_op_mtc0_mvpcontrol(); /* MT ASE */
rn = "MVPControl";
// break;
case 2:
// gen_op_mtc0_mvpconf0(); /* MT ASE */
rn = "MVPConf0";
// break;
case 3:
// gen_op_mtc0_mvpconf1(); /* MT ASE */
rn = "MVPConf1";
// break;
default:
goto die;
}
break;
case 1:
switch (sel) {
case 0:
/* ignored */
rn = "Random";
break;
case 1:
// gen_op_mtc0_vpecontrol(); /* MT ASE */
rn = "VPEControl";
// break;
case 2:
// gen_op_mtc0_vpeconf0(); /* MT ASE */
rn = "VPEConf0";
// break;
case 3:
// gen_op_mtc0_vpeconf1(); /* MT ASE */
rn = "VPEConf1";
// break;
case 4:
// gen_op_mtc0_YQMask(); /* MT ASE */
rn = "YQMask";
// break;
case 5:
// gen_op_mtc0_vpeschedule(); /* MT ASE */
rn = "VPESchedule";
// break;
case 6:
// gen_op_mtc0_vpeschefback(); /* MT ASE */
rn = "VPEScheFBack";
// break;
case 7:
// gen_op_mtc0_vpeopt(); /* MT ASE */
rn = "VPEOpt";
// break;
default:
goto die;
}
break;
case 2:
switch (sel) {
case 0:
gen_op_mtc0_entrylo0();
rn = "EntryLo0";
break;
case 1:
// gen_op_mtc0_tcstatus(); /* MT ASE */
rn = "TCStatus";
// break;
case 2:
// gen_op_mtc0_tcbind(); /* MT ASE */
rn = "TCBind";
// break;
case 3:
// gen_op_mtc0_tcrestart(); /* MT ASE */
rn = "TCRestart";
// break;
case 4:
// gen_op_mtc0_tchalt(); /* MT ASE */
rn = "TCHalt";
// break;
case 5:
// gen_op_mtc0_tccontext(); /* MT ASE */
rn = "TCContext";
// break;
case 6:
// gen_op_mtc0_tcschedule(); /* MT ASE */
rn = "TCSchedule";
// break;
case 7:
// gen_op_mtc0_tcschefback(); /* MT ASE */
rn = "TCScheFBack";
// break;
default:
goto die;
}
break;
case 3:
switch (sel) {
case 0:
gen_op_mtc0_entrylo1();
rn = "EntryLo1";
break;
default:
goto die;
}
break;
case 4:
switch (sel) {
case 0:
gen_op_mtc0_context();
rn = "Context";
break;
case 1:
// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
goto die;
}
break;
case 5:
switch (sel) {
case 0:
gen_op_mtc0_pagemask();
rn = "PageMask";
break;
case 1:
gen_op_mtc0_pagegrain();
rn = "PageGrain";
break;
default:
goto die;
}
break;
case 6:
switch (sel) {
case 0:
gen_op_mtc0_wired();
rn = "Wired";
break;
case 1:
// gen_op_mtc0_srsconf0(); /* shadow registers */
rn = "SRSConf0";
// break;
case 2:
// gen_op_mtc0_srsconf1(); /* shadow registers */
rn = "SRSConf1";
// break;
case 3:
// gen_op_mtc0_srsconf2(); /* shadow registers */
rn = "SRSConf2";
// break;
case 4:
// gen_op_mtc0_srsconf3(); /* shadow registers */
rn = "SRSConf3";
// break;
case 5:
// gen_op_mtc0_srsconf4(); /* shadow registers */
rn = "SRSConf4";
// break;
default:
goto die;
}
break;
case 7:
switch (sel) {
case 0:
gen_op_mtc0_hwrena();
rn = "HWREna";
break;
default:
goto die;
}
break;
case 8:
/* ignored */
rn = "BadVaddr";
break;
case 9:
switch (sel) {
case 0:
gen_op_mtc0_count();
rn = "Count";
break;
/* 6,7 are implementation dependent */
default:
goto die;
}
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case 10:
switch (sel) {
case 0:
gen_op_mtc0_entryhi();
rn = "EntryHi";
break;
default:
goto die;
}
break;
case 11:
switch (sel) {
case 0:
gen_op_mtc0_compare();
rn = "Compare";
break;
/* 6,7 are implementation dependent */
default:
goto die;
}
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case 12:
switch (sel) {
case 0:
gen_op_mtc0_status();
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Status";
break;
case 1:
gen_op_mtc0_intctl();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
gen_op_mtc0_srsctl();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
break;
case 3:
gen_op_mtc0_srsmap();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
break;
default:
goto die;
}
break;
case 13:
switch (sel) {
case 0:
gen_op_mtc0_cause();
rn = "Cause";
break;
default:
goto die;
}
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case 14:
switch (sel) {
case 0:
gen_op_mtc0_epc();
rn = "EPC";
break;
default:
goto die;
}
break;
case 15:
switch (sel) {
case 0:
/* ignored */
rn = "PRid";
break;
case 1:
gen_op_mtc0_ebase();
rn = "EBase";
break;
default:
goto die;
}
break;
case 16:
switch (sel) {
case 0:
gen_op_mtc0_config0();
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case 1:
/* ignored, read only */
rn = "Config1";
break;
case 2:
gen_op_mtc0_config2();
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case 3:
/* ignored, read only */
rn = "Config3";
break;
/* 4,5 are reserved */
/* 6,7 are implementation dependent */
case 6:
/* ignored */
rn = "Config6";
break;
case 7:
/* ignored */
rn = "Config7";
break;
default:
rn = "Invalid config selector";
goto die;
}
break;
case 17:
switch (sel) {
case 0:
/* ignored */
rn = "LLAddr";
break;
default:
goto die;
}
break;
case 18:
switch (sel) {
case 0 ... 7:
gen_op_mtc0_watchlo(sel);
rn = "WatchLo";
break;
default:
goto die;
}
break;
case 19:
switch (sel) {
case 0 ... 7:
gen_op_mtc0_watchhi(sel);
rn = "WatchHi";
break;
default:
goto die;
}
break;
case 20:
switch (sel) {
case 0:
#ifdef TARGET_MIPS64
gen_op_mtc0_xcontext();
rn = "XContext";
break;
#endif
default:
goto die;
}
break;
case 21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
gen_op_mtc0_framemask();
rn = "Framemask";
break;
default:
goto die;
}
break;
case 22:
/* ignored */
rn = "Diagnostic"; /* implementation dependent */
break;
case 23:
switch (sel) {
case 0:
gen_op_mtc0_debug(); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
// gen_op_mtc0_tracecontrol(); /* PDtrace support */
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 2:
// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 3:
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// gen_op_mtc0_usertracedata(); /* PDtrace support */
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 4:
// gen_op_mtc0_debug(); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
// break;
default:
goto die;
}
break;
case 24:
switch (sel) {
case 0:
gen_op_mtc0_depc(); /* EJTAG support */
rn = "DEPC";
break;
default:
goto die;
}
break;
case 25:
switch (sel) {
case 0:
gen_op_mtc0_performance0();
rn = "Performance0";
break;
case 1:
// gen_op_mtc0_performance1();
rn = "Performance1";
// break;
case 2:
// gen_op_mtc0_performance2();
rn = "Performance2";
// break;
case 3:
// gen_op_mtc0_performance3();
rn = "Performance3";
// break;
case 4:
// gen_op_mtc0_performance4();
rn = "Performance4";
// break;
case 5:
// gen_op_mtc0_performance5();
rn = "Performance5";
// break;
case 6:
// gen_op_mtc0_performance6();
rn = "Performance6";
// break;
case 7:
// gen_op_mtc0_performance7();
rn = "Performance7";
// break;
default:
goto die;
}
break;
case 26:
/* ignored */
rn = "ECC";
break;
case 27:
switch (sel) {
case 0 ... 3:
/* ignored */
rn = "CacheErr";
break;
default:
goto die;
}
break;
case 28:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
gen_op_mtc0_taglo();
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_op_mtc0_datalo();
rn = "DataLo";
break;
default:
goto die;
}
break;
case 29:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
gen_op_mtc0_taghi();
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_op_mtc0_datahi();
rn = "DataHi";
break;
default:
rn = "invalid sel";
goto die;
}
break;
case 30:
switch (sel) {
case 0:
gen_op_mtc0_errorepc();
rn = "ErrorEPC";
break;
default:
goto die;
}
break;
case 31:
switch (sel) {
case 0:
gen_op_mtc0_desave(); /* EJTAG support */
rn = "DESAVE";
break;
default:
goto die;
}
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
generate_exception(ctx, EXCP_RI);
}
| false | qemu | 3a95e3a7d9a6fd7610fe483778ff7016d23be5ec | static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
switch (reg) {
case 0:
switch (sel) {
case 0:
gen_op_mtc0_index();
rn = "Index";
break;
case 1:
rn = "MVPControl";
case 2:
rn = "MVPConf0";
case 3:
rn = "MVPConf1";
default:
goto die;
}
break;
case 1:
switch (sel) {
case 0:
rn = "Random";
break;
case 1:
rn = "VPEControl";
case 2:
rn = "VPEConf0";
case 3:
rn = "VPEConf1";
case 4:
rn = "YQMask";
case 5:
rn = "VPESchedule";
case 6:
rn = "VPEScheFBack";
case 7:
rn = "VPEOpt";
default:
goto die;
}
break;
case 2:
switch (sel) {
case 0:
gen_op_mtc0_entrylo0();
rn = "EntryLo0";
break;
case 1:
rn = "TCStatus";
case 2:
rn = "TCBind";
case 3:
rn = "TCRestart";
case 4:
rn = "TCHalt";
case 5:
rn = "TCContext";
case 6:
rn = "TCSchedule";
case 7:
rn = "TCScheFBack";
default:
goto die;
}
break;
case 3:
switch (sel) {
case 0:
gen_op_mtc0_entrylo1();
rn = "EntryLo1";
break;
default:
goto die;
}
break;
case 4:
switch (sel) {
case 0:
gen_op_mtc0_context();
rn = "Context";
break;
case 1:
rn = "ContextConfig";
default:
goto die;
}
break;
case 5:
switch (sel) {
case 0:
gen_op_mtc0_pagemask();
rn = "PageMask";
break;
case 1:
gen_op_mtc0_pagegrain();
rn = "PageGrain";
break;
default:
goto die;
}
break;
case 6:
switch (sel) {
case 0:
gen_op_mtc0_wired();
rn = "Wired";
break;
case 1:
rn = "SRSConf0";
case 2:
rn = "SRSConf1";
case 3:
rn = "SRSConf2";
case 4:
rn = "SRSConf3";
case 5:
rn = "SRSConf4";
default:
goto die;
}
break;
case 7:
switch (sel) {
case 0:
gen_op_mtc0_hwrena();
rn = "HWREna";
break;
default:
goto die;
}
break;
case 8:
rn = "BadVaddr";
break;
case 9:
switch (sel) {
case 0:
gen_op_mtc0_count();
rn = "Count";
break;
default:
goto die;
}
ctx->bstate = BS_STOP;
break;
case 10:
switch (sel) {
case 0:
gen_op_mtc0_entryhi();
rn = "EntryHi";
break;
default:
goto die;
}
break;
case 11:
switch (sel) {
case 0:
gen_op_mtc0_compare();
rn = "Compare";
break;
default:
goto die;
}
ctx->bstate = BS_STOP;
break;
case 12:
switch (sel) {
case 0:
gen_op_mtc0_status();
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Status";
break;
case 1:
gen_op_mtc0_intctl();
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
gen_op_mtc0_srsctl();
ctx->bstate = BS_STOP;
rn = "SRSCtl";
break;
case 3:
gen_op_mtc0_srsmap();
ctx->bstate = BS_STOP;
rn = "SRSMap";
break;
default:
goto die;
}
break;
case 13:
switch (sel) {
case 0:
gen_op_mtc0_cause();
rn = "Cause";
break;
default:
goto die;
}
ctx->bstate = BS_STOP;
break;
case 14:
switch (sel) {
case 0:
gen_op_mtc0_epc();
rn = "EPC";
break;
default:
goto die;
}
break;
case 15:
switch (sel) {
case 0:
rn = "PRid";
break;
case 1:
gen_op_mtc0_ebase();
rn = "EBase";
break;
default:
goto die;
}
break;
case 16:
switch (sel) {
case 0:
gen_op_mtc0_config0();
rn = "Config";
ctx->bstate = BS_STOP;
break;
case 1:
rn = "Config1";
break;
case 2:
gen_op_mtc0_config2();
rn = "Config2";
ctx->bstate = BS_STOP;
break;
case 3:
rn = "Config3";
break;
case 6:
rn = "Config6";
break;
case 7:
rn = "Config7";
break;
default:
rn = "Invalid config selector";
goto die;
}
break;
case 17:
switch (sel) {
case 0:
rn = "LLAddr";
break;
default:
goto die;
}
break;
case 18:
switch (sel) {
case 0 ... 7:
gen_op_mtc0_watchlo(sel);
rn = "WatchLo";
break;
default:
goto die;
}
break;
case 19:
switch (sel) {
case 0 ... 7:
gen_op_mtc0_watchhi(sel);
rn = "WatchHi";
break;
default:
goto die;
}
break;
case 20:
switch (sel) {
case 0:
#ifdef TARGET_MIPS64
gen_op_mtc0_xcontext();
rn = "XContext";
break;
#endif
default:
goto die;
}
break;
case 21:
switch (sel) {
case 0:
gen_op_mtc0_framemask();
rn = "Framemask";
break;
default:
goto die;
}
break;
case 22:
rn = "Diagnostic";
break;
case 23:
switch (sel) {
case 0:
gen_op_mtc0_debug();
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
rn = "TraceControl";
ctx->bstate = BS_STOP;
case 2:
rn = "TraceControl2";
ctx->bstate = BS_STOP;
case 3:
ctx->bstate = BS_STOP;
rn = "UserTraceData";
ctx->bstate = BS_STOP;
case 4:
ctx->bstate = BS_STOP;
rn = "TraceBPC";
default:
goto die;
}
break;
case 24:
switch (sel) {
case 0:
gen_op_mtc0_depc();
rn = "DEPC";
break;
default:
goto die;
}
break;
case 25:
switch (sel) {
case 0:
gen_op_mtc0_performance0();
rn = "Performance0";
break;
case 1:
rn = "Performance1";
case 2:
rn = "Performance2";
case 3:
rn = "Performance3";
case 4:
rn = "Performance4";
case 5:
rn = "Performance5";
case 6:
rn = "Performance6";
case 7:
rn = "Performance7";
default:
goto die;
}
break;
case 26:
rn = "ECC";
break;
case 27:
switch (sel) {
case 0 ... 3:
rn = "CacheErr";
break;
default:
goto die;
}
break;
case 28:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
gen_op_mtc0_taglo();
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_op_mtc0_datalo();
rn = "DataLo";
break;
default:
goto die;
}
break;
case 29:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
gen_op_mtc0_taghi();
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_op_mtc0_datahi();
rn = "DataHi";
break;
default:
rn = "invalid sel";
goto die;
}
break;
case 30:
switch (sel) {
case 0:
gen_op_mtc0_errorepc();
rn = "ErrorEPC";
break;
default:
goto die;
}
break;
case 31:
switch (sel) {
case 0:
gen_op_mtc0_desave();
rn = "DESAVE";
break;
default:
goto die;
}
ctx->bstate = BS_STOP;
break;
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
generate_exception(ctx, EXCP_RI);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0 (DisasContext *VAR_0, int VAR_1, int VAR_2)
{
const char *VAR_3 = "invalid";
switch (VAR_1) {
case 0:
switch (VAR_2) {
case 0:
gen_op_mtc0_index();
VAR_3 = "Index";
break;
case 1:
VAR_3 = "MVPControl";
case 2:
VAR_3 = "MVPConf0";
case 3:
VAR_3 = "MVPConf1";
default:
goto die;
}
break;
case 1:
switch (VAR_2) {
case 0:
VAR_3 = "Random";
break;
case 1:
VAR_3 = "VPEControl";
case 2:
VAR_3 = "VPEConf0";
case 3:
VAR_3 = "VPEConf1";
case 4:
VAR_3 = "YQMask";
case 5:
VAR_3 = "VPESchedule";
case 6:
VAR_3 = "VPEScheFBack";
case 7:
VAR_3 = "VPEOpt";
default:
goto die;
}
break;
case 2:
switch (VAR_2) {
case 0:
gen_op_mtc0_entrylo0();
VAR_3 = "EntryLo0";
break;
case 1:
VAR_3 = "TCStatus";
case 2:
VAR_3 = "TCBind";
case 3:
VAR_3 = "TCRestart";
case 4:
VAR_3 = "TCHalt";
case 5:
VAR_3 = "TCContext";
case 6:
VAR_3 = "TCSchedule";
case 7:
VAR_3 = "TCScheFBack";
default:
goto die;
}
break;
case 3:
switch (VAR_2) {
case 0:
gen_op_mtc0_entrylo1();
VAR_3 = "EntryLo1";
break;
default:
goto die;
}
break;
case 4:
switch (VAR_2) {
case 0:
gen_op_mtc0_context();
VAR_3 = "Context";
break;
case 1:
VAR_3 = "ContextConfig";
default:
goto die;
}
break;
case 5:
switch (VAR_2) {
case 0:
gen_op_mtc0_pagemask();
VAR_3 = "PageMask";
break;
case 1:
gen_op_mtc0_pagegrain();
VAR_3 = "PageGrain";
break;
default:
goto die;
}
break;
case 6:
switch (VAR_2) {
case 0:
gen_op_mtc0_wired();
VAR_3 = "Wired";
break;
case 1:
VAR_3 = "SRSConf0";
case 2:
VAR_3 = "SRSConf1";
case 3:
VAR_3 = "SRSConf2";
case 4:
VAR_3 = "SRSConf3";
case 5:
VAR_3 = "SRSConf4";
default:
goto die;
}
break;
case 7:
switch (VAR_2) {
case 0:
gen_op_mtc0_hwrena();
VAR_3 = "HWREna";
break;
default:
goto die;
}
break;
case 8:
VAR_3 = "BadVaddr";
break;
case 9:
switch (VAR_2) {
case 0:
gen_op_mtc0_count();
VAR_3 = "Count";
break;
default:
goto die;
}
VAR_0->bstate = BS_STOP;
break;
case 10:
switch (VAR_2) {
case 0:
gen_op_mtc0_entryhi();
VAR_3 = "EntryHi";
break;
default:
goto die;
}
break;
case 11:
switch (VAR_2) {
case 0:
gen_op_mtc0_compare();
VAR_3 = "Compare";
break;
default:
goto die;
}
VAR_0->bstate = BS_STOP;
break;
case 12:
switch (VAR_2) {
case 0:
gen_op_mtc0_status();
gen_save_pc(VAR_0->pc + 4);
VAR_0->bstate = BS_EXCP;
VAR_3 = "Status";
break;
case 1:
gen_op_mtc0_intctl();
VAR_0->bstate = BS_STOP;
VAR_3 = "IntCtl";
break;
case 2:
gen_op_mtc0_srsctl();
VAR_0->bstate = BS_STOP;
VAR_3 = "SRSCtl";
break;
case 3:
gen_op_mtc0_srsmap();
VAR_0->bstate = BS_STOP;
VAR_3 = "SRSMap";
break;
default:
goto die;
}
break;
case 13:
switch (VAR_2) {
case 0:
gen_op_mtc0_cause();
VAR_3 = "Cause";
break;
default:
goto die;
}
VAR_0->bstate = BS_STOP;
break;
case 14:
switch (VAR_2) {
case 0:
gen_op_mtc0_epc();
VAR_3 = "EPC";
break;
default:
goto die;
}
break;
case 15:
switch (VAR_2) {
case 0:
VAR_3 = "PRid";
break;
case 1:
gen_op_mtc0_ebase();
VAR_3 = "EBase";
break;
default:
goto die;
}
break;
case 16:
switch (VAR_2) {
case 0:
gen_op_mtc0_config0();
VAR_3 = "Config";
VAR_0->bstate = BS_STOP;
break;
case 1:
VAR_3 = "Config1";
break;
case 2:
gen_op_mtc0_config2();
VAR_3 = "Config2";
VAR_0->bstate = BS_STOP;
break;
case 3:
VAR_3 = "Config3";
break;
case 6:
VAR_3 = "Config6";
break;
case 7:
VAR_3 = "Config7";
break;
default:
VAR_3 = "Invalid config selector";
goto die;
}
break;
case 17:
switch (VAR_2) {
case 0:
VAR_3 = "LLAddr";
break;
default:
goto die;
}
break;
case 18:
switch (VAR_2) {
case 0 ... 7:
gen_op_mtc0_watchlo(VAR_2);
VAR_3 = "WatchLo";
break;
default:
goto die;
}
break;
case 19:
switch (VAR_2) {
case 0 ... 7:
gen_op_mtc0_watchhi(VAR_2);
VAR_3 = "WatchHi";
break;
default:
goto die;
}
break;
case 20:
switch (VAR_2) {
case 0:
#ifdef TARGET_MIPS64
gen_op_mtc0_xcontext();
VAR_3 = "XContext";
break;
#endif
default:
goto die;
}
break;
case 21:
switch (VAR_2) {
case 0:
gen_op_mtc0_framemask();
VAR_3 = "Framemask";
break;
default:
goto die;
}
break;
case 22:
VAR_3 = "Diagnostic";
break;
case 23:
switch (VAR_2) {
case 0:
gen_op_mtc0_debug();
gen_save_pc(VAR_0->pc + 4);
VAR_0->bstate = BS_EXCP;
VAR_3 = "Debug";
break;
case 1:
VAR_3 = "TraceControl";
VAR_0->bstate = BS_STOP;
case 2:
VAR_3 = "TraceControl2";
VAR_0->bstate = BS_STOP;
case 3:
VAR_0->bstate = BS_STOP;
VAR_3 = "UserTraceData";
VAR_0->bstate = BS_STOP;
case 4:
VAR_0->bstate = BS_STOP;
VAR_3 = "TraceBPC";
default:
goto die;
}
break;
case 24:
switch (VAR_2) {
case 0:
gen_op_mtc0_depc();
VAR_3 = "DEPC";
break;
default:
goto die;
}
break;
case 25:
switch (VAR_2) {
case 0:
gen_op_mtc0_performance0();
VAR_3 = "Performance0";
break;
case 1:
VAR_3 = "Performance1";
case 2:
VAR_3 = "Performance2";
case 3:
VAR_3 = "Performance3";
case 4:
VAR_3 = "Performance4";
case 5:
VAR_3 = "Performance5";
case 6:
VAR_3 = "Performance6";
case 7:
VAR_3 = "Performance7";
default:
goto die;
}
break;
case 26:
VAR_3 = "ECC";
break;
case 27:
switch (VAR_2) {
case 0 ... 3:
VAR_3 = "CacheErr";
break;
default:
goto die;
}
break;
case 28:
switch (VAR_2) {
case 0:
case 2:
case 4:
case 6:
gen_op_mtc0_taglo();
VAR_3 = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
gen_op_mtc0_datalo();
VAR_3 = "DataLo";
break;
default:
goto die;
}
break;
case 29:
switch (VAR_2) {
case 0:
case 2:
case 4:
case 6:
gen_op_mtc0_taghi();
VAR_3 = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
gen_op_mtc0_datahi();
VAR_3 = "DataHi";
break;
default:
VAR_3 = "invalid VAR_2";
goto die;
}
break;
case 30:
switch (VAR_2) {
case 0:
gen_op_mtc0_errorepc();
VAR_3 = "ErrorEPC";
break;
default:
goto die;
}
break;
case 31:
switch (VAR_2) {
case 0:
gen_op_mtc0_desave();
VAR_3 = "DESAVE";
break;
default:
goto die;
}
VAR_0->bstate = BS_STOP;
break;
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (VAR_1 %d VAR_2 %d)\n",
VAR_3, VAR_1, VAR_2);
}
#endif
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (VAR_1 %d VAR_2 %d)\n",
VAR_3, VAR_1, VAR_2);
}
#endif
generate_exception(VAR_0, EXCP_RI);
}
| [
"static void FUNC_0 (DisasContext *VAR_0, int VAR_1, int VAR_2)\n{",
"const char *VAR_3 = \"invalid\";",
"switch (VAR_1) {",
"case 0:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_index();",
"VAR_3 = \"Index\";",
"break;",
"case 1:\nVAR_3 = \"MVPControl\";",
"case 2:\nVAR_3 = \"MVPConf0\";",
"case 3:\nVAR_3 = \"MVPConf1\";",
"default:\ngoto die;",
"}",
"break;",
"case 1:\nswitch (VAR_2) {",
"case 0:\nVAR_3 = \"Random\";",
"break;",
"case 1:\nVAR_3 = \"VPEControl\";",
"case 2:\nVAR_3 = \"VPEConf0\";",
"case 3:\nVAR_3 = \"VPEConf1\";",
"case 4:\nVAR_3 = \"YQMask\";",
"case 5:\nVAR_3 = \"VPESchedule\";",
"case 6:\nVAR_3 = \"VPEScheFBack\";",
"case 7:\nVAR_3 = \"VPEOpt\";",
"default:\ngoto die;",
"}",
"break;",
"case 2:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_entrylo0();",
"VAR_3 = \"EntryLo0\";",
"break;",
"case 1:\nVAR_3 = \"TCStatus\";",
"case 2:\nVAR_3 = \"TCBind\";",
"case 3:\nVAR_3 = \"TCRestart\";",
"case 4:\nVAR_3 = \"TCHalt\";",
"case 5:\nVAR_3 = \"TCContext\";",
"case 6:\nVAR_3 = \"TCSchedule\";",
"case 7:\nVAR_3 = \"TCScheFBack\";",
"default:\ngoto die;",
"}",
"break;",
"case 3:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_entrylo1();",
"VAR_3 = \"EntryLo1\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 4:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_context();",
"VAR_3 = \"Context\";",
"break;",
"case 1:\nVAR_3 = \"ContextConfig\";",
"default:\ngoto die;",
"}",
"break;",
"case 5:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_pagemask();",
"VAR_3 = \"PageMask\";",
"break;",
"case 1:\ngen_op_mtc0_pagegrain();",
"VAR_3 = \"PageGrain\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 6:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_wired();",
"VAR_3 = \"Wired\";",
"break;",
"case 1:\nVAR_3 = \"SRSConf0\";",
"case 2:\nVAR_3 = \"SRSConf1\";",
"case 3:\nVAR_3 = \"SRSConf2\";",
"case 4:\nVAR_3 = \"SRSConf3\";",
"case 5:\nVAR_3 = \"SRSConf4\";",
"default:\ngoto die;",
"}",
"break;",
"case 7:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_hwrena();",
"VAR_3 = \"HWREna\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 8:\nVAR_3 = \"BadVaddr\";",
"break;",
"case 9:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_count();",
"VAR_3 = \"Count\";",
"break;",
"default:\ngoto die;",
"}",
"VAR_0->bstate = BS_STOP;",
"break;",
"case 10:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_entryhi();",
"VAR_3 = \"EntryHi\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 11:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_compare();",
"VAR_3 = \"Compare\";",
"break;",
"default:\ngoto die;",
"}",
"VAR_0->bstate = BS_STOP;",
"break;",
"case 12:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_status();",
"gen_save_pc(VAR_0->pc + 4);",
"VAR_0->bstate = BS_EXCP;",
"VAR_3 = \"Status\";",
"break;",
"case 1:\ngen_op_mtc0_intctl();",
"VAR_0->bstate = BS_STOP;",
"VAR_3 = \"IntCtl\";",
"break;",
"case 2:\ngen_op_mtc0_srsctl();",
"VAR_0->bstate = BS_STOP;",
"VAR_3 = \"SRSCtl\";",
"break;",
"case 3:\ngen_op_mtc0_srsmap();",
"VAR_0->bstate = BS_STOP;",
"VAR_3 = \"SRSMap\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 13:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_cause();",
"VAR_3 = \"Cause\";",
"break;",
"default:\ngoto die;",
"}",
"VAR_0->bstate = BS_STOP;",
"break;",
"case 14:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_epc();",
"VAR_3 = \"EPC\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 15:\nswitch (VAR_2) {",
"case 0:\nVAR_3 = \"PRid\";",
"break;",
"case 1:\ngen_op_mtc0_ebase();",
"VAR_3 = \"EBase\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 16:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_config0();",
"VAR_3 = \"Config\";",
"VAR_0->bstate = BS_STOP;",
"break;",
"case 1:\nVAR_3 = \"Config1\";",
"break;",
"case 2:\ngen_op_mtc0_config2();",
"VAR_3 = \"Config2\";",
"VAR_0->bstate = BS_STOP;",
"break;",
"case 3:\nVAR_3 = \"Config3\";",
"break;",
"case 6:\nVAR_3 = \"Config6\";",
"break;",
"case 7:\nVAR_3 = \"Config7\";",
"break;",
"default:\nVAR_3 = \"Invalid config selector\";",
"goto die;",
"}",
"break;",
"case 17:\nswitch (VAR_2) {",
"case 0:\nVAR_3 = \"LLAddr\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 18:\nswitch (VAR_2) {",
"case 0 ... 7:\ngen_op_mtc0_watchlo(VAR_2);",
"VAR_3 = \"WatchLo\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 19:\nswitch (VAR_2) {",
"case 0 ... 7:\ngen_op_mtc0_watchhi(VAR_2);",
"VAR_3 = \"WatchHi\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 20:\nswitch (VAR_2) {",
"case 0:\n#ifdef TARGET_MIPS64\ngen_op_mtc0_xcontext();",
"VAR_3 = \"XContext\";",
"break;",
"#endif\ndefault:\ngoto die;",
"}",
"break;",
"case 21:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_framemask();",
"VAR_3 = \"Framemask\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 22:\nVAR_3 = \"Diagnostic\";",
"break;",
"case 23:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_debug();",
"gen_save_pc(VAR_0->pc + 4);",
"VAR_0->bstate = BS_EXCP;",
"VAR_3 = \"Debug\";",
"break;",
"case 1:\nVAR_3 = \"TraceControl\";",
"VAR_0->bstate = BS_STOP;",
"case 2:\nVAR_3 = \"TraceControl2\";",
"VAR_0->bstate = BS_STOP;",
"case 3:\nVAR_0->bstate = BS_STOP;",
"VAR_3 = \"UserTraceData\";",
"VAR_0->bstate = BS_STOP;",
"case 4:\nVAR_0->bstate = BS_STOP;",
"VAR_3 = \"TraceBPC\";",
"default:\ngoto die;",
"}",
"break;",
"case 24:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_depc();",
"VAR_3 = \"DEPC\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 25:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_performance0();",
"VAR_3 = \"Performance0\";",
"break;",
"case 1:\nVAR_3 = \"Performance1\";",
"case 2:\nVAR_3 = \"Performance2\";",
"case 3:\nVAR_3 = \"Performance3\";",
"case 4:\nVAR_3 = \"Performance4\";",
"case 5:\nVAR_3 = \"Performance5\";",
"case 6:\nVAR_3 = \"Performance6\";",
"case 7:\nVAR_3 = \"Performance7\";",
"default:\ngoto die;",
"}",
"break;",
"case 26:\nVAR_3 = \"ECC\";",
"break;",
"case 27:\nswitch (VAR_2) {",
"case 0 ... 3:\nVAR_3 = \"CacheErr\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 28:\nswitch (VAR_2) {",
"case 0:\ncase 2:\ncase 4:\ncase 6:\ngen_op_mtc0_taglo();",
"VAR_3 = \"TagLo\";",
"break;",
"case 1:\ncase 3:\ncase 5:\ncase 7:\ngen_op_mtc0_datalo();",
"VAR_3 = \"DataLo\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 29:\nswitch (VAR_2) {",
"case 0:\ncase 2:\ncase 4:\ncase 6:\ngen_op_mtc0_taghi();",
"VAR_3 = \"TagHi\";",
"break;",
"case 1:\ncase 3:\ncase 5:\ncase 7:\ngen_op_mtc0_datahi();",
"VAR_3 = \"DataHi\";",
"break;",
"default:\nVAR_3 = \"invalid VAR_2\";",
"goto die;",
"}",
"break;",
"case 30:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_errorepc();",
"VAR_3 = \"ErrorEPC\";",
"break;",
"default:\ngoto die;",
"}",
"break;",
"case 31:\nswitch (VAR_2) {",
"case 0:\ngen_op_mtc0_desave();",
"VAR_3 = \"DESAVE\";",
"break;",
"default:\ngoto die;",
"}",
"VAR_0->bstate = BS_STOP;",
"break;",
"default:\ngoto die;",
"}",
"#if defined MIPS_DEBUG_DISAS\nif (loglevel & CPU_LOG_TB_IN_ASM) {",
"fprintf(logfile, \"mtc0 %s (VAR_1 %d VAR_2 %d)\\n\",\nVAR_3, VAR_1, VAR_2);",
"}",
"#endif\nreturn;",
"die:\n#if defined MIPS_DEBUG_DISAS\nif (loglevel & CPU_LOG_TB_IN_ASM) {",
"fprintf(logfile, \"mtc0 %s (VAR_1 %d VAR_2 %d)\\n\",\nVAR_3, VAR_1, VAR_2);",
"}",
"#endif\ngenerate_exception(VAR_0, EXCP_RI);",
"}"
]
| [
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|
10,319 | static void test_native_list_integer_helper(TestInputVisitorData *data,
const void *unused,
UserDefNativeListUnionKind kind)
{
UserDefNativeListUnion *cvalue = NULL;
Visitor *v;
GString *gstr_list = g_string_new("");
GString *gstr_union = g_string_new("");
int i;
for (i = 0; i < 32; i++) {
g_string_append_printf(gstr_list, "%d", i);
if (i != 31) {
g_string_append(gstr_list, ", ");
}
}
g_string_append_printf(gstr_union, "{ 'type': '%s', 'data': [ %s ] }",
UserDefNativeListUnionKind_lookup[kind],
gstr_list->str);
v = visitor_input_test_init_raw(data, gstr_union->str);
visit_type_UserDefNativeListUnion(v, NULL, &cvalue, &error_abort);
g_assert(cvalue != NULL);
g_assert_cmpint(cvalue->type, ==, kind);
switch (kind) {
case USER_DEF_NATIVE_LIST_UNION_KIND_INTEGER: {
intList *elem = NULL;
for (i = 0, elem = cvalue->u.integer.data;
elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S8: {
int8List *elem = NULL;
for (i = 0, elem = cvalue->u.s8.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S16: {
int16List *elem = NULL;
for (i = 0, elem = cvalue->u.s16.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S32: {
int32List *elem = NULL;
for (i = 0, elem = cvalue->u.s32.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S64: {
int64List *elem = NULL;
for (i = 0, elem = cvalue->u.s64.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U8: {
uint8List *elem = NULL;
for (i = 0, elem = cvalue->u.u8.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U16: {
uint16List *elem = NULL;
for (i = 0, elem = cvalue->u.u16.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U32: {
uint32List *elem = NULL;
for (i = 0, elem = cvalue->u.u32.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U64: {
uint64List *elem = NULL;
for (i = 0, elem = cvalue->u.u64.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
default:
g_assert_not_reached();
}
g_string_free(gstr_union, true);
g_string_free(gstr_list, true);
qapi_free_UserDefNativeListUnion(cvalue);
}
| false | qemu | b3db211f3c80bb996a704d665fe275619f728bd4 | static void test_native_list_integer_helper(TestInputVisitorData *data,
const void *unused,
UserDefNativeListUnionKind kind)
{
UserDefNativeListUnion *cvalue = NULL;
Visitor *v;
GString *gstr_list = g_string_new("");
GString *gstr_union = g_string_new("");
int i;
for (i = 0; i < 32; i++) {
g_string_append_printf(gstr_list, "%d", i);
if (i != 31) {
g_string_append(gstr_list, ", ");
}
}
g_string_append_printf(gstr_union, "{ 'type': '%s', 'data': [ %s ] }",
UserDefNativeListUnionKind_lookup[kind],
gstr_list->str);
v = visitor_input_test_init_raw(data, gstr_union->str);
visit_type_UserDefNativeListUnion(v, NULL, &cvalue, &error_abort);
g_assert(cvalue != NULL);
g_assert_cmpint(cvalue->type, ==, kind);
switch (kind) {
case USER_DEF_NATIVE_LIST_UNION_KIND_INTEGER: {
intList *elem = NULL;
for (i = 0, elem = cvalue->u.integer.data;
elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S8: {
int8List *elem = NULL;
for (i = 0, elem = cvalue->u.s8.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S16: {
int16List *elem = NULL;
for (i = 0, elem = cvalue->u.s16.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S32: {
int32List *elem = NULL;
for (i = 0, elem = cvalue->u.s32.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S64: {
int64List *elem = NULL;
for (i = 0, elem = cvalue->u.s64.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U8: {
uint8List *elem = NULL;
for (i = 0, elem = cvalue->u.u8.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U16: {
uint16List *elem = NULL;
for (i = 0, elem = cvalue->u.u16.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U32: {
uint32List *elem = NULL;
for (i = 0, elem = cvalue->u.u32.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U64: {
uint64List *elem = NULL;
for (i = 0, elem = cvalue->u.u64.data; elem; elem = elem->next, i++) {
g_assert_cmpint(elem->value, ==, i);
}
break;
}
default:
g_assert_not_reached();
}
g_string_free(gstr_union, true);
g_string_free(gstr_list, true);
qapi_free_UserDefNativeListUnion(cvalue);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(TestInputVisitorData *VAR_0,
const void *VAR_1,
UserDefNativeListUnionKind VAR_2)
{
UserDefNativeListUnion *cvalue = NULL;
Visitor *v;
GString *gstr_list = g_string_new("");
GString *gstr_union = g_string_new("");
int VAR_3;
for (VAR_3 = 0; VAR_3 < 32; VAR_3++) {
g_string_append_printf(gstr_list, "%d", VAR_3);
if (VAR_3 != 31) {
g_string_append(gstr_list, ", ");
}
}
g_string_append_printf(gstr_union, "{ 'type': '%s', 'VAR_0': [ %s ] }",
UserDefNativeListUnionKind_lookup[VAR_2],
gstr_list->str);
v = visitor_input_test_init_raw(VAR_0, gstr_union->str);
visit_type_UserDefNativeListUnion(v, NULL, &cvalue, &error_abort);
g_assert(cvalue != NULL);
g_assert_cmpint(cvalue->type, ==, VAR_2);
switch (VAR_2) {
case USER_DEF_NATIVE_LIST_UNION_KIND_INTEGER: {
intList *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.integer.VAR_0;
elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S8: {
int8List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.s8.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S16: {
int16List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.s16.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S32: {
int32List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.s32.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_S64: {
int64List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.s64.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U8: {
uint8List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.u8.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U16: {
uint16List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.u16.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U32: {
uint32List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.u32.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
case USER_DEF_NATIVE_LIST_UNION_KIND_U64: {
uint64List *elem = NULL;
for (VAR_3 = 0, elem = cvalue->u.u64.VAR_0; elem; elem = elem->next, VAR_3++) {
g_assert_cmpint(elem->value, ==, VAR_3);
}
break;
}
default:
g_assert_not_reached();
}
g_string_free(gstr_union, true);
g_string_free(gstr_list, true);
qapi_free_UserDefNativeListUnion(cvalue);
}
| [
"static void FUNC_0(TestInputVisitorData *VAR_0,\nconst void *VAR_1,\nUserDefNativeListUnionKind VAR_2)\n{",
"UserDefNativeListUnion *cvalue = NULL;",
"Visitor *v;",
"GString *gstr_list = g_string_new(\"\");",
"GString *gstr_union = g_string_new(\"\");",
"int VAR_3;",
"for (VAR_3 = 0; VAR_3 < 32; VAR_3++) {",
"g_string_append_printf(gstr_list, \"%d\", VAR_3);",
"if (VAR_3 != 31) {",
"g_string_append(gstr_list, \", \");",
"}",
"}",
"g_string_append_printf(gstr_union, \"{ 'type': '%s', 'VAR_0': [ %s ] }\",",
"UserDefNativeListUnionKind_lookup[VAR_2],\ngstr_list->str);",
"v = visitor_input_test_init_raw(VAR_0, gstr_union->str);",
"visit_type_UserDefNativeListUnion(v, NULL, &cvalue, &error_abort);",
"g_assert(cvalue != NULL);",
"g_assert_cmpint(cvalue->type, ==, VAR_2);",
"switch (VAR_2) {",
"case USER_DEF_NATIVE_LIST_UNION_KIND_INTEGER: {",
"intList *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.integer.VAR_0;",
"elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_S8: {",
"int8List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.s8.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_S16: {",
"int16List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.s16.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_S32: {",
"int32List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.s32.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_S64: {",
"int64List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.s64.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_U8: {",
"uint8List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.u8.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_U16: {",
"uint16List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.u16.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_U32: {",
"uint32List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.u32.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"case USER_DEF_NATIVE_LIST_UNION_KIND_U64: {",
"uint64List *elem = NULL;",
"for (VAR_3 = 0, elem = cvalue->u.u64.VAR_0; elem; elem = elem->next, VAR_3++) {",
"g_assert_cmpint(elem->value, ==, VAR_3);",
"}",
"break;",
"}",
"default:\ng_assert_not_reached();",
"}",
"g_string_free(gstr_union, true);",
"g_string_free(gstr_list, true);",
"qapi_free_UserDefNativeListUnion(cvalue);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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]
| [
[
1,
3,
5,
7
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33
],
[
35,
37
],
[
39
],
[
43
],
[
45
],
[
47
],
[
51
],
[
53
],
[
55
],
[
57
],
[
59
],
[
61
],
[
63
],
[
65
],
[
67
],
[
69
],
[
71
],
[
73
],
[
75
],
[
77
],
[
79
],
[
81
],
[
83
],
[
85
],
[
87
],
[
89
],
[
91
],
[
93
],
[
95
],
[
97
],
[
99
],
[
101
],
[
103
],
[
105
],
[
107
],
[
109
],
[
111
],
[
113
],
[
115
],
[
117
],
[
119
],
[
121
],
[
123
],
[
125
],
[
127
],
[
129
],
[
131
],
[
133
],
[
135
],
[
137
],
[
139
],
[
141
],
[
143
],
[
145
],
[
147
],
[
149
],
[
151
],
[
153
],
[
155
],
[
157
],
[
159
],
[
161
],
[
163
],
[
165
],
[
167
],
[
169
],
[
171
],
[
173
],
[
175
],
[
177
],
[
179
],
[
181,
183
],
[
185
],
[
189
],
[
191
],
[
193
],
[
195
]
]
|
10,320 | pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
{
int i;
uint32_t txr_len_log2, rxr_len_log2;
uint32_t req_ring_size, cmp_ring_size;
m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
if ((ri->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)
|| (ri->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)) {
return -1;
}
req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
txr_len_log2 = pvscsi_log2(req_ring_size - 1);
rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
m->txr_len_mask = MASK(txr_len_log2);
m->rxr_len_mask = MASK(rxr_len_log2);
m->consumed_ptr = 0;
m->filled_cmp_ptr = 0;
for (i = 0; i < ri->reqRingNumPages; i++) {
m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
}
for (i = 0; i < ri->cmpRingNumPages; i++) {
m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
}
RS_SET_FIELD(m, reqProdIdx, 0);
RS_SET_FIELD(m, reqConsIdx, 0);
RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
RS_SET_FIELD(m, cmpProdIdx, 0);
RS_SET_FIELD(m, cmpConsIdx, 0);
RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
/* Flush ring state page changes */
smp_wmb();
return 0;
}
| false | qemu | 7f61f4690dd153be98900a2a508b88989e692753 | pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
{
int i;
uint32_t txr_len_log2, rxr_len_log2;
uint32_t req_ring_size, cmp_ring_size;
m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
if ((ri->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)
|| (ri->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)) {
return -1;
}
req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
txr_len_log2 = pvscsi_log2(req_ring_size - 1);
rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
m->txr_len_mask = MASK(txr_len_log2);
m->rxr_len_mask = MASK(rxr_len_log2);
m->consumed_ptr = 0;
m->filled_cmp_ptr = 0;
for (i = 0; i < ri->reqRingNumPages; i++) {
m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
}
for (i = 0; i < ri->cmpRingNumPages; i++) {
m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
}
RS_SET_FIELD(m, reqProdIdx, 0);
RS_SET_FIELD(m, reqConsIdx, 0);
RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
RS_SET_FIELD(m, cmpProdIdx, 0);
RS_SET_FIELD(m, cmpConsIdx, 0);
RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
smp_wmb();
return 0;
}
| {
"code": [],
"line_no": []
} | FUNC_0(PVSCSIRingInfo *VAR_0, PVSCSICmdDescSetupRings *VAR_1)
{
int VAR_2;
uint32_t txr_len_log2, rxr_len_log2;
uint32_t req_ring_size, cmp_ring_size;
VAR_0->rs_pa = VAR_1->ringsStatePPN << VMW_PAGE_SHIFT;
if ((VAR_1->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)
|| (VAR_1->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)) {
return -1;
}
req_ring_size = VAR_1->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
cmp_ring_size = VAR_1->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
txr_len_log2 = pvscsi_log2(req_ring_size - 1);
rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
VAR_0->txr_len_mask = MASK(txr_len_log2);
VAR_0->rxr_len_mask = MASK(rxr_len_log2);
VAR_0->consumed_ptr = 0;
VAR_0->filled_cmp_ptr = 0;
for (VAR_2 = 0; VAR_2 < VAR_1->reqRingNumPages; VAR_2++) {
VAR_0->req_ring_pages_pa[VAR_2] = VAR_1->reqRingPPNs[VAR_2] << VMW_PAGE_SHIFT;
}
for (VAR_2 = 0; VAR_2 < VAR_1->cmpRingNumPages; VAR_2++) {
VAR_0->cmp_ring_pages_pa[VAR_2] = VAR_1->cmpRingPPNs[VAR_2] << VMW_PAGE_SHIFT;
}
RS_SET_FIELD(VAR_0, reqProdIdx, 0);
RS_SET_FIELD(VAR_0, reqConsIdx, 0);
RS_SET_FIELD(VAR_0, reqNumEntriesLog2, txr_len_log2);
RS_SET_FIELD(VAR_0, cmpProdIdx, 0);
RS_SET_FIELD(VAR_0, cmpConsIdx, 0);
RS_SET_FIELD(VAR_0, cmpNumEntriesLog2, rxr_len_log2);
trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
smp_wmb();
return 0;
}
| [
"FUNC_0(PVSCSIRingInfo *VAR_0, PVSCSICmdDescSetupRings *VAR_1)\n{",
"int VAR_2;",
"uint32_t txr_len_log2, rxr_len_log2;",
"uint32_t req_ring_size, cmp_ring_size;",
"VAR_0->rs_pa = VAR_1->ringsStatePPN << VMW_PAGE_SHIFT;",
"if ((VAR_1->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)\n|| (VAR_1->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)) {",
"return -1;",
"}",
"req_ring_size = VAR_1->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;",
"cmp_ring_size = VAR_1->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;",
"txr_len_log2 = pvscsi_log2(req_ring_size - 1);",
"rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);",
"VAR_0->txr_len_mask = MASK(txr_len_log2);",
"VAR_0->rxr_len_mask = MASK(rxr_len_log2);",
"VAR_0->consumed_ptr = 0;",
"VAR_0->filled_cmp_ptr = 0;",
"for (VAR_2 = 0; VAR_2 < VAR_1->reqRingNumPages; VAR_2++) {",
"VAR_0->req_ring_pages_pa[VAR_2] = VAR_1->reqRingPPNs[VAR_2] << VMW_PAGE_SHIFT;",
"}",
"for (VAR_2 = 0; VAR_2 < VAR_1->cmpRingNumPages; VAR_2++) {",
"VAR_0->cmp_ring_pages_pa[VAR_2] = VAR_1->cmpRingPPNs[VAR_2] << VMW_PAGE_SHIFT;",
"}",
"RS_SET_FIELD(VAR_0, reqProdIdx, 0);",
"RS_SET_FIELD(VAR_0, reqConsIdx, 0);",
"RS_SET_FIELD(VAR_0, reqNumEntriesLog2, txr_len_log2);",
"RS_SET_FIELD(VAR_0, cmpProdIdx, 0);",
"RS_SET_FIELD(VAR_0, cmpConsIdx, 0);",
"RS_SET_FIELD(VAR_0, cmpNumEntriesLog2, rxr_len_log2);",
"trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);",
"smp_wmb();",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
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0,
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0,
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0,
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0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15,
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
33
],
[
35
],
[
39
],
[
41
],
[
45
],
[
47
],
[
49
],
[
53
],
[
55
],
[
57
],
[
61
],
[
63
],
[
65
],
[
69
],
[
71
],
[
73
],
[
77
],
[
83
],
[
87
],
[
89
]
]
|
10,321 | static bool check_overlapping_aiocb(BDRVSheepdogState *s, SheepdogAIOCB *aiocb)
{
SheepdogAIOCB *cb;
QLIST_FOREACH(cb, &s->inflight_aiocb_head, aiocb_siblings) {
if (AIOCBOverlapping(aiocb, cb)) {
return true;
}
}
QLIST_INSERT_HEAD(&s->inflight_aiocb_head, aiocb, aiocb_siblings);
return false;
}
| false | qemu | acf6e5f0962c4be670d4a93ede77423512521876 | static bool check_overlapping_aiocb(BDRVSheepdogState *s, SheepdogAIOCB *aiocb)
{
SheepdogAIOCB *cb;
QLIST_FOREACH(cb, &s->inflight_aiocb_head, aiocb_siblings) {
if (AIOCBOverlapping(aiocb, cb)) {
return true;
}
}
QLIST_INSERT_HEAD(&s->inflight_aiocb_head, aiocb, aiocb_siblings);
return false;
}
| {
"code": [],
"line_no": []
} | static bool FUNC_0(BDRVSheepdogState *s, SheepdogAIOCB *aiocb)
{
SheepdogAIOCB *cb;
QLIST_FOREACH(cb, &s->inflight_aiocb_head, aiocb_siblings) {
if (AIOCBOverlapping(aiocb, cb)) {
return true;
}
}
QLIST_INSERT_HEAD(&s->inflight_aiocb_head, aiocb, aiocb_siblings);
return false;
}
| [
"static bool FUNC_0(BDRVSheepdogState *s, SheepdogAIOCB *aiocb)\n{",
"SheepdogAIOCB *cb;",
"QLIST_FOREACH(cb, &s->inflight_aiocb_head, aiocb_siblings) {",
"if (AIOCBOverlapping(aiocb, cb)) {",
"return true;",
"}",
"}",
"QLIST_INSERT_HEAD(&s->inflight_aiocb_head, aiocb, aiocb_siblings);",
"return false;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
21
],
[
23
],
[
25
]
]
|
10,323 | static void qio_channel_websock_finalize(Object *obj)
{
QIOChannelWebsock *ioc = QIO_CHANNEL_WEBSOCK(obj);
buffer_free(&ioc->encinput);
buffer_free(&ioc->encoutput);
buffer_free(&ioc->rawinput);
buffer_free(&ioc->rawoutput);
object_unref(OBJECT(ioc->master));
if (ioc->io_tag) {
g_source_remove(ioc->io_tag);
}
if (ioc->io_err) {
error_free(ioc->io_err);
}
}
| false | qemu | 8dfd5f96515ca20c4eb109cb0ee28e2bb32fc505 | static void qio_channel_websock_finalize(Object *obj)
{
QIOChannelWebsock *ioc = QIO_CHANNEL_WEBSOCK(obj);
buffer_free(&ioc->encinput);
buffer_free(&ioc->encoutput);
buffer_free(&ioc->rawinput);
buffer_free(&ioc->rawoutput);
object_unref(OBJECT(ioc->master));
if (ioc->io_tag) {
g_source_remove(ioc->io_tag);
}
if (ioc->io_err) {
error_free(ioc->io_err);
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(Object *VAR_0)
{
QIOChannelWebsock *ioc = QIO_CHANNEL_WEBSOCK(VAR_0);
buffer_free(&ioc->encinput);
buffer_free(&ioc->encoutput);
buffer_free(&ioc->rawinput);
buffer_free(&ioc->rawoutput);
object_unref(OBJECT(ioc->master));
if (ioc->io_tag) {
g_source_remove(ioc->io_tag);
}
if (ioc->io_err) {
error_free(ioc->io_err);
}
}
| [
"static void FUNC_0(Object *VAR_0)\n{",
"QIOChannelWebsock *ioc = QIO_CHANNEL_WEBSOCK(VAR_0);",
"buffer_free(&ioc->encinput);",
"buffer_free(&ioc->encoutput);",
"buffer_free(&ioc->rawinput);",
"buffer_free(&ioc->rawoutput);",
"object_unref(OBJECT(ioc->master));",
"if (ioc->io_tag) {",
"g_source_remove(ioc->io_tag);",
"}",
"if (ioc->io_err) {",
"error_free(ioc->io_err);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
9
],
[
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
29
],
[
31
]
]
|
10,324 | static av_cold int vaapi_encode_h265_init_internal(AVCodecContext *avctx)
{
static const VAConfigAttrib default_config_attributes[] = {
{ .type = VAConfigAttribRTFormat,
.value = VA_RT_FORMAT_YUV420 },
{ .type = VAConfigAttribEncPackedHeaders,
.value = (VA_ENC_PACKED_HEADER_SEQUENCE |
VA_ENC_PACKED_HEADER_SLICE) },
};
VAAPIEncodeContext *ctx = avctx->priv_data;
VAAPIEncodeH265Context *priv = ctx->priv_data;
int i, err;
switch (avctx->profile) {
case FF_PROFILE_HEVC_MAIN:
case FF_PROFILE_UNKNOWN:
ctx->va_profile = VAProfileHEVCMain;
break;
case FF_PROFILE_HEVC_MAIN_10:
av_log(avctx, AV_LOG_ERROR, "H.265 main 10-bit profile "
"is not supported.\n");
return AVERROR_PATCHWELCOME;
default:
av_log(avctx, AV_LOG_ERROR, "Unknown H.265 profile %d.\n",
avctx->profile);
return AVERROR(EINVAL);
}
ctx->va_entrypoint = VAEntrypointEncSlice;
ctx->input_width = avctx->width;
ctx->input_height = avctx->height;
ctx->aligned_width = FFALIGN(ctx->input_width, 16);
ctx->aligned_height = FFALIGN(ctx->input_height, 16);
priv->ctu_width = FFALIGN(ctx->aligned_width, 32) / 32;
priv->ctu_height = FFALIGN(ctx->aligned_height, 32) / 32;
av_log(avctx, AV_LOG_VERBOSE, "Input %ux%u -> Aligned %ux%u -> CTU %ux%u.\n",
ctx->input_width, ctx->input_height, ctx->aligned_width,
ctx->aligned_height, priv->ctu_width, priv->ctu_height);
for (i = 0; i < FF_ARRAY_ELEMS(default_config_attributes); i++) {
ctx->config_attributes[ctx->nb_config_attributes++] =
default_config_attributes[i];
}
if (avctx->bit_rate > 0) {
ctx->va_rc_mode = VA_RC_CBR;
err = vaapi_encode_h265_init_constant_bitrate(avctx);
} else {
ctx->va_rc_mode = VA_RC_CQP;
err = vaapi_encode_h265_init_fixed_qp(avctx);
}
if (err < 0)
return err;
ctx->config_attributes[ctx->nb_config_attributes++] = (VAConfigAttrib) {
.type = VAConfigAttribRateControl,
.value = ctx->va_rc_mode,
};
ctx->nb_recon_frames = 20;
return 0;
}
| false | FFmpeg | c8241e730f116f1c9cfc0b34110aa7f052e05332 | static av_cold int vaapi_encode_h265_init_internal(AVCodecContext *avctx)
{
static const VAConfigAttrib default_config_attributes[] = {
{ .type = VAConfigAttribRTFormat,
.value = VA_RT_FORMAT_YUV420 },
{ .type = VAConfigAttribEncPackedHeaders,
.value = (VA_ENC_PACKED_HEADER_SEQUENCE |
VA_ENC_PACKED_HEADER_SLICE) },
};
VAAPIEncodeContext *ctx = avctx->priv_data;
VAAPIEncodeH265Context *priv = ctx->priv_data;
int i, err;
switch (avctx->profile) {
case FF_PROFILE_HEVC_MAIN:
case FF_PROFILE_UNKNOWN:
ctx->va_profile = VAProfileHEVCMain;
break;
case FF_PROFILE_HEVC_MAIN_10:
av_log(avctx, AV_LOG_ERROR, "H.265 main 10-bit profile "
"is not supported.\n");
return AVERROR_PATCHWELCOME;
default:
av_log(avctx, AV_LOG_ERROR, "Unknown H.265 profile %d.\n",
avctx->profile);
return AVERROR(EINVAL);
}
ctx->va_entrypoint = VAEntrypointEncSlice;
ctx->input_width = avctx->width;
ctx->input_height = avctx->height;
ctx->aligned_width = FFALIGN(ctx->input_width, 16);
ctx->aligned_height = FFALIGN(ctx->input_height, 16);
priv->ctu_width = FFALIGN(ctx->aligned_width, 32) / 32;
priv->ctu_height = FFALIGN(ctx->aligned_height, 32) / 32;
av_log(avctx, AV_LOG_VERBOSE, "Input %ux%u -> Aligned %ux%u -> CTU %ux%u.\n",
ctx->input_width, ctx->input_height, ctx->aligned_width,
ctx->aligned_height, priv->ctu_width, priv->ctu_height);
for (i = 0; i < FF_ARRAY_ELEMS(default_config_attributes); i++) {
ctx->config_attributes[ctx->nb_config_attributes++] =
default_config_attributes[i];
}
if (avctx->bit_rate > 0) {
ctx->va_rc_mode = VA_RC_CBR;
err = vaapi_encode_h265_init_constant_bitrate(avctx);
} else {
ctx->va_rc_mode = VA_RC_CQP;
err = vaapi_encode_h265_init_fixed_qp(avctx);
}
if (err < 0)
return err;
ctx->config_attributes[ctx->nb_config_attributes++] = (VAConfigAttrib) {
.type = VAConfigAttribRateControl,
.value = ctx->va_rc_mode,
};
ctx->nb_recon_frames = 20;
return 0;
}
| {
"code": [],
"line_no": []
} | static av_cold int FUNC_0(AVCodecContext *avctx)
{
static const VAConfigAttrib VAR_0[] = {
{ .type = VAConfigAttribRTFormat,
.value = VA_RT_FORMAT_YUV420 },
{ .type = VAConfigAttribEncPackedHeaders,
.value = (VA_ENC_PACKED_HEADER_SEQUENCE |
VA_ENC_PACKED_HEADER_SLICE) },
};
VAAPIEncodeContext *ctx = avctx->priv_data;
VAAPIEncodeH265Context *priv = ctx->priv_data;
int VAR_1, VAR_2;
switch (avctx->profile) {
case FF_PROFILE_HEVC_MAIN:
case FF_PROFILE_UNKNOWN:
ctx->va_profile = VAProfileHEVCMain;
break;
case FF_PROFILE_HEVC_MAIN_10:
av_log(avctx, AV_LOG_ERROR, "H.265 main 10-bit profile "
"is not supported.\n");
return AVERROR_PATCHWELCOME;
default:
av_log(avctx, AV_LOG_ERROR, "Unknown H.265 profile %d.\n",
avctx->profile);
return AVERROR(EINVAL);
}
ctx->va_entrypoint = VAEntrypointEncSlice;
ctx->input_width = avctx->width;
ctx->input_height = avctx->height;
ctx->aligned_width = FFALIGN(ctx->input_width, 16);
ctx->aligned_height = FFALIGN(ctx->input_height, 16);
priv->ctu_width = FFALIGN(ctx->aligned_width, 32) / 32;
priv->ctu_height = FFALIGN(ctx->aligned_height, 32) / 32;
av_log(avctx, AV_LOG_VERBOSE, "Input %ux%u -> Aligned %ux%u -> CTU %ux%u.\n",
ctx->input_width, ctx->input_height, ctx->aligned_width,
ctx->aligned_height, priv->ctu_width, priv->ctu_height);
for (VAR_1 = 0; VAR_1 < FF_ARRAY_ELEMS(VAR_0); VAR_1++) {
ctx->config_attributes[ctx->nb_config_attributes++] =
VAR_0[VAR_1];
}
if (avctx->bit_rate > 0) {
ctx->va_rc_mode = VA_RC_CBR;
VAR_2 = vaapi_encode_h265_init_constant_bitrate(avctx);
} else {
ctx->va_rc_mode = VA_RC_CQP;
VAR_2 = vaapi_encode_h265_init_fixed_qp(avctx);
}
if (VAR_2 < 0)
return VAR_2;
ctx->config_attributes[ctx->nb_config_attributes++] = (VAConfigAttrib) {
.type = VAConfigAttribRateControl,
.value = ctx->va_rc_mode,
};
ctx->nb_recon_frames = 20;
return 0;
}
| [
"static av_cold int FUNC_0(AVCodecContext *avctx)\n{",
"static const VAConfigAttrib VAR_0[] = {",
"{ .type = VAConfigAttribRTFormat,",
".value = VA_RT_FORMAT_YUV420 },",
"{ .type = VAConfigAttribEncPackedHeaders,",
".value = (VA_ENC_PACKED_HEADER_SEQUENCE |\nVA_ENC_PACKED_HEADER_SLICE) },",
"};",
"VAAPIEncodeContext *ctx = avctx->priv_data;",
"VAAPIEncodeH265Context *priv = ctx->priv_data;",
"int VAR_1, VAR_2;",
"switch (avctx->profile) {",
"case FF_PROFILE_HEVC_MAIN:\ncase FF_PROFILE_UNKNOWN:\nctx->va_profile = VAProfileHEVCMain;",
"break;",
"case FF_PROFILE_HEVC_MAIN_10:\nav_log(avctx, AV_LOG_ERROR, \"H.265 main 10-bit profile \"\n\"is not supported.\\n\");",
"return AVERROR_PATCHWELCOME;",
"default:\nav_log(avctx, AV_LOG_ERROR, \"Unknown H.265 profile %d.\\n\",\navctx->profile);",
"return AVERROR(EINVAL);",
"}",
"ctx->va_entrypoint = VAEntrypointEncSlice;",
"ctx->input_width = avctx->width;",
"ctx->input_height = avctx->height;",
"ctx->aligned_width = FFALIGN(ctx->input_width, 16);",
"ctx->aligned_height = FFALIGN(ctx->input_height, 16);",
"priv->ctu_width = FFALIGN(ctx->aligned_width, 32) / 32;",
"priv->ctu_height = FFALIGN(ctx->aligned_height, 32) / 32;",
"av_log(avctx, AV_LOG_VERBOSE, \"Input %ux%u -> Aligned %ux%u -> CTU %ux%u.\\n\",\nctx->input_width, ctx->input_height, ctx->aligned_width,\nctx->aligned_height, priv->ctu_width, priv->ctu_height);",
"for (VAR_1 = 0; VAR_1 < FF_ARRAY_ELEMS(VAR_0); VAR_1++) {",
"ctx->config_attributes[ctx->nb_config_attributes++] =\nVAR_0[VAR_1];",
"}",
"if (avctx->bit_rate > 0) {",
"ctx->va_rc_mode = VA_RC_CBR;",
"VAR_2 = vaapi_encode_h265_init_constant_bitrate(avctx);",
"} else {",
"ctx->va_rc_mode = VA_RC_CQP;",
"VAR_2 = vaapi_encode_h265_init_fixed_qp(avctx);",
"}",
"if (VAR_2 < 0)\nreturn VAR_2;",
"ctx->config_attributes[ctx->nb_config_attributes++] = (VAConfigAttrib) {",
".type = VAConfigAttribRateControl,\n.value = ctx->va_rc_mode,\n};",
"ctx->nb_recon_frames = 20;",
"return 0;",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
13,
15
],
[
17
],
[
21
],
[
23
],
[
25
],
[
29
],
[
31,
33,
35
],
[
37
],
[
39,
41,
43
],
[
45
],
[
47,
49,
51
],
[
53
],
[
55
],
[
57
],
[
61
],
[
63
],
[
65
],
[
67
],
[
69
],
[
71
],
[
75,
77,
79
],
[
83
],
[
85,
87
],
[
89
],
[
93
],
[
95
],
[
97
],
[
99
],
[
101
],
[
103
],
[
105
],
[
107,
109
],
[
113
],
[
115,
117,
119
],
[
123
],
[
127
],
[
129
]
]
|
10,325 | void qmp_migrate_set_downtime(double value, Error **errp)
{
value *= 1e9;
value = MAX(0, MIN(UINT64_MAX, value));
max_downtime = (uint64_t)value;
}
| false | qemu | 2ff30257974e19ebe2a97baad32ac29c06da5fb9 | void qmp_migrate_set_downtime(double value, Error **errp)
{
value *= 1e9;
value = MAX(0, MIN(UINT64_MAX, value));
max_downtime = (uint64_t)value;
}
| {
"code": [],
"line_no": []
} | void FUNC_0(double VAR_0, Error **VAR_1)
{
VAR_0 *= 1e9;
VAR_0 = MAX(0, MIN(UINT64_MAX, VAR_0));
max_downtime = (uint64_t)VAR_0;
}
| [
"void FUNC_0(double VAR_0, Error **VAR_1)\n{",
"VAR_0 *= 1e9;",
"VAR_0 = MAX(0, MIN(UINT64_MAX, VAR_0));",
"max_downtime = (uint64_t)VAR_0;",
"}"
]
| [
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
]
]
|
10,326 | static void qemu_cpu_kick_thread(CPUState *env)
{
#ifndef _WIN32
int err;
err = pthread_kill(env->thread->thread, SIG_IPI);
if (err) {
fprintf(stderr, "qemu:%s: %s", __func__, strerror(err));
exit(1);
}
#else /* _WIN32 */
if (!qemu_cpu_is_self(env)) {
SuspendThread(env->thread->thread);
cpu_signal(0);
ResumeThread(env->thread->thread);
}
#endif
}
| false | qemu | 1ecf47bf0a091700e45f1b7d1f5ad85abc0acd22 | static void qemu_cpu_kick_thread(CPUState *env)
{
#ifndef _WIN32
int err;
err = pthread_kill(env->thread->thread, SIG_IPI);
if (err) {
fprintf(stderr, "qemu:%s: %s", __func__, strerror(err));
exit(1);
}
#else
if (!qemu_cpu_is_self(env)) {
SuspendThread(env->thread->thread);
cpu_signal(0);
ResumeThread(env->thread->thread);
}
#endif
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(CPUState *VAR_0)
{
#ifndef _WIN32
int VAR_1;
VAR_1 = pthread_kill(VAR_0->thread->thread, SIG_IPI);
if (VAR_1) {
fprintf(stderr, "qemu:%s: %s", __func__, strerror(VAR_1));
exit(1);
}
#else
if (!qemu_cpu_is_self(VAR_0)) {
SuspendThread(VAR_0->thread->thread);
cpu_signal(0);
ResumeThread(VAR_0->thread->thread);
}
#endif
}
| [
"static void FUNC_0(CPUState *VAR_0)\n{",
"#ifndef _WIN32\nint VAR_1;",
"VAR_1 = pthread_kill(VAR_0->thread->thread, SIG_IPI);",
"if (VAR_1) {",
"fprintf(stderr, \"qemu:%s: %s\", __func__, strerror(VAR_1));",
"exit(1);",
"}",
"#else\nif (!qemu_cpu_is_self(VAR_0)) {",
"SuspendThread(VAR_0->thread->thread);",
"cpu_signal(0);",
"ResumeThread(VAR_0->thread->thread);",
"}",
"#endif\n}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5,
7
],
[
11
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21,
23
],
[
25
],
[
27
],
[
29
],
[
31
],
[
33,
35
]
]
|
10,328 | void helper_evaluate_flags_alu_4(void)
{
uint32_t src;
uint32_t dst;
uint32_t res;
uint32_t flags = 0;
src = env->cc_src;
dst = env->cc_dest;
/* Reconstruct the result. */
switch (env->cc_op)
{
case CC_OP_SUB:
res = dst - src;
break;
case CC_OP_ADD:
res = dst + src;
break;
default:
res = env->cc_result;
break;
}
if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
src = ~src;
if ((res & 0x80000000L) != 0L)
{
flags |= N_FLAG;
if (((src & 0x80000000L) == 0L)
&& ((dst & 0x80000000L) == 0L))
{
flags |= V_FLAG;
}
else if (((src & 0x80000000L) != 0L) &&
((dst & 0x80000000L) != 0L))
{
flags |= C_FLAG;
}
}
else
{
if (res == 0L)
flags |= Z_FLAG;
if (((src & 0x80000000L) != 0L)
&& ((dst & 0x80000000L) != 0L))
flags |= V_FLAG;
if ((dst & 0x80000000L) != 0L
|| (src & 0x80000000L) != 0L)
flags |= C_FLAG;
}
if (env->cc_op == CC_OP_SUB
|| env->cc_op == CC_OP_CMP) {
flags ^= C_FLAG;
}
evaluate_flags_writeback(flags);
}
| false | qemu | a8cf66bb393ff420d40ae172a4c817bf2752918a | void helper_evaluate_flags_alu_4(void)
{
uint32_t src;
uint32_t dst;
uint32_t res;
uint32_t flags = 0;
src = env->cc_src;
dst = env->cc_dest;
switch (env->cc_op)
{
case CC_OP_SUB:
res = dst - src;
break;
case CC_OP_ADD:
res = dst + src;
break;
default:
res = env->cc_result;
break;
}
if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
src = ~src;
if ((res & 0x80000000L) != 0L)
{
flags |= N_FLAG;
if (((src & 0x80000000L) == 0L)
&& ((dst & 0x80000000L) == 0L))
{
flags |= V_FLAG;
}
else if (((src & 0x80000000L) != 0L) &&
((dst & 0x80000000L) != 0L))
{
flags |= C_FLAG;
}
}
else
{
if (res == 0L)
flags |= Z_FLAG;
if (((src & 0x80000000L) != 0L)
&& ((dst & 0x80000000L) != 0L))
flags |= V_FLAG;
if ((dst & 0x80000000L) != 0L
|| (src & 0x80000000L) != 0L)
flags |= C_FLAG;
}
if (env->cc_op == CC_OP_SUB
|| env->cc_op == CC_OP_CMP) {
flags ^= C_FLAG;
}
evaluate_flags_writeback(flags);
}
| {
"code": [],
"line_no": []
} | void FUNC_0(void)
{
uint32_t src;
uint32_t dst;
uint32_t res;
uint32_t flags = 0;
src = env->cc_src;
dst = env->cc_dest;
switch (env->cc_op)
{
case CC_OP_SUB:
res = dst - src;
break;
case CC_OP_ADD:
res = dst + src;
break;
default:
res = env->cc_result;
break;
}
if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
src = ~src;
if ((res & 0x80000000L) != 0L)
{
flags |= N_FLAG;
if (((src & 0x80000000L) == 0L)
&& ((dst & 0x80000000L) == 0L))
{
flags |= V_FLAG;
}
else if (((src & 0x80000000L) != 0L) &&
((dst & 0x80000000L) != 0L))
{
flags |= C_FLAG;
}
}
else
{
if (res == 0L)
flags |= Z_FLAG;
if (((src & 0x80000000L) != 0L)
&& ((dst & 0x80000000L) != 0L))
flags |= V_FLAG;
if ((dst & 0x80000000L) != 0L
|| (src & 0x80000000L) != 0L)
flags |= C_FLAG;
}
if (env->cc_op == CC_OP_SUB
|| env->cc_op == CC_OP_CMP) {
flags ^= C_FLAG;
}
evaluate_flags_writeback(flags);
}
| [
"void FUNC_0(void)\n{",
"uint32_t src;",
"uint32_t dst;",
"uint32_t res;",
"uint32_t flags = 0;",
"src = env->cc_src;",
"dst = env->cc_dest;",
"switch (env->cc_op)\n{",
"case CC_OP_SUB:\nres = dst - src;",
"break;",
"case CC_OP_ADD:\nres = dst + src;",
"break;",
"default:\nres = env->cc_result;",
"break;",
"}",
"if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)\nsrc = ~src;",
"if ((res & 0x80000000L) != 0L)\n{",
"flags |= N_FLAG;",
"if (((src & 0x80000000L) == 0L)\n&& ((dst & 0x80000000L) == 0L))\n{",
"flags |= V_FLAG;",
"}",
"else if (((src & 0x80000000L) != 0L) &&\n((dst & 0x80000000L) != 0L))\n{",
"flags |= C_FLAG;",
"}",
"}",
"else\n{",
"if (res == 0L)\nflags |= Z_FLAG;",
"if (((src & 0x80000000L) != 0L)\n&& ((dst & 0x80000000L) != 0L))\nflags |= V_FLAG;",
"if ((dst & 0x80000000L) != 0L\n|| (src & 0x80000000L) != 0L)\nflags |= C_FLAG;",
"}",
"if (env->cc_op == CC_OP_SUB\n|| env->cc_op == CC_OP_CMP) {",
"flags ^= C_FLAG;",
"}",
"evaluate_flags_writeback(flags);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17
],
[
23,
25
],
[
27,
29
],
[
31
],
[
33,
35
],
[
37
],
[
39,
41
],
[
43
],
[
45
],
[
49,
51
],
[
55,
57
],
[
59
],
[
61,
63,
65
],
[
67
],
[
69
],
[
71,
73,
75
],
[
77
],
[
79
],
[
81
],
[
83,
85
],
[
87,
89
],
[
91,
93,
95
],
[
97,
99,
101
],
[
103
],
[
107,
109
],
[
111
],
[
113
],
[
115
],
[
117
]
]
|
10,329 | static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
int unaligned;
if (ret < 0) {
m->aiocb = NULL;
qemu_sglist_destroy(&s->sg);
ide_atapi_io_error(s, ret);
io->remainder_len = 0;
goto done;
}
if (!m->dma_active) {
MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
s->nsector, io->len, s->status);
/* data not ready yet, wait for the channel to get restarted */
io->processing = false;
return;
}
MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);
if (s->io_buffer_size > 0) {
m->aiocb = NULL;
qemu_sglist_destroy(&s->sg);
s->packet_transfer_size -= s->io_buffer_size;
s->io_buffer_index += s->io_buffer_size;
s->lba += s->io_buffer_index >> 11;
s->io_buffer_index &= 0x7ff;
}
s->io_buffer_size = MIN(io->len, s->packet_transfer_size);
MACIO_DPRINTF("remainder: %d io->len: %d size: %d\n", io->remainder_len,
io->len, s->packet_transfer_size);
if (io->remainder_len && io->len) {
/* guest wants the rest of its previous transfer */
int remainder_len = MIN(io->remainder_len, io->len);
MACIO_DPRINTF("copying remainder %d bytes\n", remainder_len);
cpu_physical_memory_write(io->addr, io->remainder + 0x200 -
remainder_len, remainder_len);
io->addr += remainder_len;
io->len -= remainder_len;
s->io_buffer_size = remainder_len;
io->remainder_len -= remainder_len;
/* treat remainder as individual transfer, start again */
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
&address_space_memory);
pmac_ide_atapi_transfer_cb(opaque, 0);
return;
}
if (!s->packet_transfer_size) {
MACIO_DPRINTF("end of transfer\n");
ide_atapi_cmd_ok(s);
m->dma_active = false;
}
if (io->len == 0) {
MACIO_DPRINTF("end of DMA\n");
goto done;
}
/* launch next transfer */
/* handle unaligned accesses first, get them over with and only do the
remaining bulk transfer using our async DMA helpers */
unaligned = io->len & 0x1ff;
if (unaligned) {
int sector_num = (s->lba << 2) + (s->io_buffer_index >> 9);
int nsector = io->len >> 9;
MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n",
unaligned, io->addr + io->len - unaligned);
bdrv_read(s->bs, sector_num + nsector, io->remainder, 1);
cpu_physical_memory_write(io->addr + io->len - unaligned,
io->remainder, unaligned);
io->len -= unaligned;
}
MACIO_DPRINTF("io->len = %#x\n", io->len);
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
&address_space_memory);
qemu_sglist_add(&s->sg, io->addr, io->len);
io->addr += s->io_buffer_size;
io->remainder_len = MIN(s->packet_transfer_size - s->io_buffer_size,
(0x200 - unaligned) & 0x1ff);
MACIO_DPRINTF("set remainder to: %d\n", io->remainder_len);
/* We would read no data from the block layer, thus not get a callback.
Just fake completion manually. */
if (!io->len) {
pmac_ide_atapi_transfer_cb(opaque, 0);
return;
}
io->len = 0;
MACIO_DPRINTF("sector_num=%d size=%d, cmd_cmd=%d\n",
(s->lba << 2) + (s->io_buffer_index >> 9),
s->packet_transfer_size, s->dma_cmd);
m->aiocb = dma_bdrv_read(s->bs, &s->sg,
(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
pmac_ide_atapi_transfer_cb, io);
return;
done:
MACIO_DPRINTF("done DMA\n");
block_acct_done(bdrv_get_stats(s->bs), &s->acct);
io->dma_end(opaque);
}
| false | qemu | 4be746345f13e99e468c60acbd3a355e8183e3ce | static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
int unaligned;
if (ret < 0) {
m->aiocb = NULL;
qemu_sglist_destroy(&s->sg);
ide_atapi_io_error(s, ret);
io->remainder_len = 0;
goto done;
}
if (!m->dma_active) {
MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
s->nsector, io->len, s->status);
io->processing = false;
return;
}
MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);
if (s->io_buffer_size > 0) {
m->aiocb = NULL;
qemu_sglist_destroy(&s->sg);
s->packet_transfer_size -= s->io_buffer_size;
s->io_buffer_index += s->io_buffer_size;
s->lba += s->io_buffer_index >> 11;
s->io_buffer_index &= 0x7ff;
}
s->io_buffer_size = MIN(io->len, s->packet_transfer_size);
MACIO_DPRINTF("remainder: %d io->len: %d size: %d\n", io->remainder_len,
io->len, s->packet_transfer_size);
if (io->remainder_len && io->len) {
int remainder_len = MIN(io->remainder_len, io->len);
MACIO_DPRINTF("copying remainder %d bytes\n", remainder_len);
cpu_physical_memory_write(io->addr, io->remainder + 0x200 -
remainder_len, remainder_len);
io->addr += remainder_len;
io->len -= remainder_len;
s->io_buffer_size = remainder_len;
io->remainder_len -= remainder_len;
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
&address_space_memory);
pmac_ide_atapi_transfer_cb(opaque, 0);
return;
}
if (!s->packet_transfer_size) {
MACIO_DPRINTF("end of transfer\n");
ide_atapi_cmd_ok(s);
m->dma_active = false;
}
if (io->len == 0) {
MACIO_DPRINTF("end of DMA\n");
goto done;
}
unaligned = io->len & 0x1ff;
if (unaligned) {
int sector_num = (s->lba << 2) + (s->io_buffer_index >> 9);
int nsector = io->len >> 9;
MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n",
unaligned, io->addr + io->len - unaligned);
bdrv_read(s->bs, sector_num + nsector, io->remainder, 1);
cpu_physical_memory_write(io->addr + io->len - unaligned,
io->remainder, unaligned);
io->len -= unaligned;
}
MACIO_DPRINTF("io->len = %#x\n", io->len);
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
&address_space_memory);
qemu_sglist_add(&s->sg, io->addr, io->len);
io->addr += s->io_buffer_size;
io->remainder_len = MIN(s->packet_transfer_size - s->io_buffer_size,
(0x200 - unaligned) & 0x1ff);
MACIO_DPRINTF("set remainder to: %d\n", io->remainder_len);
if (!io->len) {
pmac_ide_atapi_transfer_cb(opaque, 0);
return;
}
io->len = 0;
MACIO_DPRINTF("sector_num=%d size=%d, cmd_cmd=%d\n",
(s->lba << 2) + (s->io_buffer_index >> 9),
s->packet_transfer_size, s->dma_cmd);
m->aiocb = dma_bdrv_read(s->bs, &s->sg,
(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
pmac_ide_atapi_transfer_cb, io);
return;
done:
MACIO_DPRINTF("done DMA\n");
block_acct_done(bdrv_get_stats(s->bs), &s->acct);
io->dma_end(opaque);
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void *VAR_0, int VAR_1)
{
DBDMA_io *io = VAR_0;
MACIOIDEState *m = io->VAR_0;
IDEState *s = idebus_active_if(&m->bus);
int VAR_2;
if (VAR_1 < 0) {
m->aiocb = NULL;
qemu_sglist_destroy(&s->sg);
ide_atapi_io_error(s, VAR_1);
io->VAR_3 = 0;
goto done;
}
if (!m->dma_active) {
MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
s->VAR_5, io->len, s->status);
io->processing = false;
return;
}
MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);
if (s->io_buffer_size > 0) {
m->aiocb = NULL;
qemu_sglist_destroy(&s->sg);
s->packet_transfer_size -= s->io_buffer_size;
s->io_buffer_index += s->io_buffer_size;
s->lba += s->io_buffer_index >> 11;
s->io_buffer_index &= 0x7ff;
}
s->io_buffer_size = MIN(io->len, s->packet_transfer_size);
MACIO_DPRINTF("remainder: %d io->len: %d size: %d\n", io->VAR_3,
io->len, s->packet_transfer_size);
if (io->VAR_3 && io->len) {
int VAR_3 = MIN(io->VAR_3, io->len);
MACIO_DPRINTF("copying remainder %d bytes\n", VAR_3);
cpu_physical_memory_write(io->addr, io->remainder + 0x200 -
VAR_3, VAR_3);
io->addr += VAR_3;
io->len -= VAR_3;
s->io_buffer_size = VAR_3;
io->VAR_3 -= VAR_3;
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
&address_space_memory);
FUNC_0(VAR_0, 0);
return;
}
if (!s->packet_transfer_size) {
MACIO_DPRINTF("end of transfer\n");
ide_atapi_cmd_ok(s);
m->dma_active = false;
}
if (io->len == 0) {
MACIO_DPRINTF("end of DMA\n");
goto done;
}
VAR_2 = io->len & 0x1ff;
if (VAR_2) {
int VAR_4 = (s->lba << 2) + (s->io_buffer_index >> 9);
int VAR_5 = io->len >> 9;
MACIO_DPRINTF("precopying VAR_2 %d bytes to %#" HWADDR_PRIx "\n",
VAR_2, io->addr + io->len - VAR_2);
bdrv_read(s->bs, VAR_4 + VAR_5, io->remainder, 1);
cpu_physical_memory_write(io->addr + io->len - VAR_2,
io->remainder, VAR_2);
io->len -= VAR_2;
}
MACIO_DPRINTF("io->len = %#x\n", io->len);
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
&address_space_memory);
qemu_sglist_add(&s->sg, io->addr, io->len);
io->addr += s->io_buffer_size;
io->VAR_3 = MIN(s->packet_transfer_size - s->io_buffer_size,
(0x200 - VAR_2) & 0x1ff);
MACIO_DPRINTF("set remainder to: %d\n", io->VAR_3);
if (!io->len) {
FUNC_0(VAR_0, 0);
return;
}
io->len = 0;
MACIO_DPRINTF("VAR_4=%d size=%d, cmd_cmd=%d\n",
(s->lba << 2) + (s->io_buffer_index >> 9),
s->packet_transfer_size, s->dma_cmd);
m->aiocb = dma_bdrv_read(s->bs, &s->sg,
(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
FUNC_0, io);
return;
done:
MACIO_DPRINTF("done DMA\n");
block_acct_done(bdrv_get_stats(s->bs), &s->acct);
io->dma_end(VAR_0);
}
| [
"static void FUNC_0(void *VAR_0, int VAR_1)\n{",
"DBDMA_io *io = VAR_0;",
"MACIOIDEState *m = io->VAR_0;",
"IDEState *s = idebus_active_if(&m->bus);",
"int VAR_2;",
"if (VAR_1 < 0) {",
"m->aiocb = NULL;",
"qemu_sglist_destroy(&s->sg);",
"ide_atapi_io_error(s, VAR_1);",
"io->VAR_3 = 0;",
"goto done;",
"}",
"if (!m->dma_active) {",
"MACIO_DPRINTF(\"waiting for data (%#x - %#x - %x)\\n\",\ns->VAR_5, io->len, s->status);",
"io->processing = false;",
"return;",
"}",
"MACIO_DPRINTF(\"io_buffer_size = %#x\\n\", s->io_buffer_size);",
"if (s->io_buffer_size > 0) {",
"m->aiocb = NULL;",
"qemu_sglist_destroy(&s->sg);",
"s->packet_transfer_size -= s->io_buffer_size;",
"s->io_buffer_index += s->io_buffer_size;",
"s->lba += s->io_buffer_index >> 11;",
"s->io_buffer_index &= 0x7ff;",
"}",
"s->io_buffer_size = MIN(io->len, s->packet_transfer_size);",
"MACIO_DPRINTF(\"remainder: %d io->len: %d size: %d\\n\", io->VAR_3,\nio->len, s->packet_transfer_size);",
"if (io->VAR_3 && io->len) {",
"int VAR_3 = MIN(io->VAR_3, io->len);",
"MACIO_DPRINTF(\"copying remainder %d bytes\\n\", VAR_3);",
"cpu_physical_memory_write(io->addr, io->remainder + 0x200 -\nVAR_3, VAR_3);",
"io->addr += VAR_3;",
"io->len -= VAR_3;",
"s->io_buffer_size = VAR_3;",
"io->VAR_3 -= VAR_3;",
"qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,\n&address_space_memory);",
"FUNC_0(VAR_0, 0);",
"return;",
"}",
"if (!s->packet_transfer_size) {",
"MACIO_DPRINTF(\"end of transfer\\n\");",
"ide_atapi_cmd_ok(s);",
"m->dma_active = false;",
"}",
"if (io->len == 0) {",
"MACIO_DPRINTF(\"end of DMA\\n\");",
"goto done;",
"}",
"VAR_2 = io->len & 0x1ff;",
"if (VAR_2) {",
"int VAR_4 = (s->lba << 2) + (s->io_buffer_index >> 9);",
"int VAR_5 = io->len >> 9;",
"MACIO_DPRINTF(\"precopying VAR_2 %d bytes to %#\" HWADDR_PRIx \"\\n\",\nVAR_2, io->addr + io->len - VAR_2);",
"bdrv_read(s->bs, VAR_4 + VAR_5, io->remainder, 1);",
"cpu_physical_memory_write(io->addr + io->len - VAR_2,\nio->remainder, VAR_2);",
"io->len -= VAR_2;",
"}",
"MACIO_DPRINTF(\"io->len = %#x\\n\", io->len);",
"qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,\n&address_space_memory);",
"qemu_sglist_add(&s->sg, io->addr, io->len);",
"io->addr += s->io_buffer_size;",
"io->VAR_3 = MIN(s->packet_transfer_size - s->io_buffer_size,\n(0x200 - VAR_2) & 0x1ff);",
"MACIO_DPRINTF(\"set remainder to: %d\\n\", io->VAR_3);",
"if (!io->len) {",
"FUNC_0(VAR_0, 0);",
"return;",
"}",
"io->len = 0;",
"MACIO_DPRINTF(\"VAR_4=%d size=%d, cmd_cmd=%d\\n\",\n(s->lba << 2) + (s->io_buffer_index >> 9),\ns->packet_transfer_size, s->dma_cmd);",
"m->aiocb = dma_bdrv_read(s->bs, &s->sg,\n(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),\nFUNC_0, io);",
"return;",
"done:\nMACIO_DPRINTF(\"done DMA\\n\");",
"block_acct_done(bdrv_get_stats(s->bs), &s->acct);",
"io->dma_end(VAR_0);",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
11
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
],
[
27
],
[
31
],
[
33,
35
],
[
39
],
[
41
],
[
43
],
[
47
],
[
51
],
[
53
],
[
55
],
[
59
],
[
63
],
[
65
],
[
67
],
[
69
],
[
73
],
[
77,
79
],
[
81
],
[
85
],
[
89
],
[
93,
95
],
[
99
],
[
101
],
[
103
],
[
105
],
[
109,
111
],
[
113
],
[
115
],
[
117
],
[
121
],
[
123
],
[
125
],
[
127
],
[
129
],
[
133
],
[
135
],
[
137
],
[
139
],
[
151
],
[
153
],
[
155
],
[
157
],
[
161,
163
],
[
167
],
[
169,
171
],
[
175
],
[
177
],
[
181
],
[
185,
187
],
[
189
],
[
191
],
[
193,
195
],
[
197
],
[
205
],
[
207
],
[
209
],
[
211
],
[
215
],
[
219,
221,
223
],
[
227,
229,
231
],
[
233
],
[
237,
239
],
[
241
],
[
243
],
[
245
]
]
|
10,330 | static void pit_reset(void *opaque)
{
PITState *pit = opaque;
PITChannelState *s;
int i;
for(i = 0;i < 3; i++) {
s = &pit->channels[i];
s->mode = 3;
s->gate = (i != 2);
pit_load_count(s, 0);
}
}
| false | qemu | 64d7e9a421fea0ac50b44541f5521de455e7cd5d | static void pit_reset(void *opaque)
{
PITState *pit = opaque;
PITChannelState *s;
int i;
for(i = 0;i < 3; i++) {
s = &pit->channels[i];
s->mode = 3;
s->gate = (i != 2);
pit_load_count(s, 0);
}
}
| {
"code": [],
"line_no": []
} | static void FUNC_0(void *VAR_0)
{
PITState *pit = VAR_0;
PITChannelState *s;
int VAR_1;
for(VAR_1 = 0;VAR_1 < 3; VAR_1++) {
s = &pit->channels[VAR_1];
s->mode = 3;
s->gate = (VAR_1 != 2);
pit_load_count(s, 0);
}
}
| [
"static void FUNC_0(void *VAR_0)\n{",
"PITState *pit = VAR_0;",
"PITChannelState *s;",
"int VAR_1;",
"for(VAR_1 = 0;VAR_1 < 3; VAR_1++) {",
"s = &pit->channels[VAR_1];",
"s->mode = 3;",
"s->gate = (VAR_1 != 2);",
"pit_load_count(s, 0);",
"}",
"}"
]
| [
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
]
| [
[
1,
3
],
[
5
],
[
7
],
[
9
],
[
13
],
[
15
],
[
17
],
[
19
],
[
21
],
[
23
],
[
25
]
]
|
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