Split (1)

train · 2.1M rows

title stringlengths 1 149 ⌀	section stringlengths 1 1.9k ⌀	text stringlengths 13 73.5k
Slitherlink	Solution methods	Another useful notation when solving Slitherlink is a ninety degree arc between two adjacent lines, to indicate that exactly one of the two must be filled. A related notation is a double arc between adjacent lines, indicating that both or neither of the two must be filled. These notations are not necessary to the solution, but can be helpful in deriving it.
Slitherlink	Solution methods	Many of the methods below can be broken down into two simpler steps by use of arc notation.
Slitherlink	Solution methods	Exactly 2 or 0 lines at each point A key to many deductions in Slitherlink is that every point has either exactly two lines connected to it, or no lines. So if a point which is in the centre of the grid, not at an edge or corner, has three incoming lines which are X'd out, the fourth must also be X'd out. This is because the point cannot have just one line - it has no exit route from that point. Similarly, if a point on the edge of the grid, not at a corner, has two incoming lines which are X'd out, the third must also be X'd out. And if a corner of the grid has one incoming line which is X'd out, the other must also be X'd out. Application of this simple rule leads to increasingly complex deductions. Recognition of these simple patterns will help greatly in solving Slitherlink puzzles.
Slitherlink	Solution methods	Corners If a 1 is in a corner, the actual corner's lines may be X'd out, because a line that entered said corner could not leave it except by passing by the 1 again. This also applies if two lines leading into the 1-box at the same corner are X'd out.If a 3 is in a corner, the two outside edges of that box can be filled in because otherwise the rule above would have to be broken.If a 2 is in a corner, two lines must be going away from the 2 at the border.
Slitherlink	Solution methods	Rules for squares with 1 If a line comes into a corner of a 1 and if one of the three remaining directions that the line can continue, the one that is not a side of the 1 is a known blank, then the two sides of the 1 opposite that corner can be X'd out.This also applies in reverse. That is, if a line comes into the corner of a 1, and the two opposite edges of the 1 are already X'd out, the line cannot go away from the 1 since that would put Xs around all sides of the 1.If two 1s are diagonally adjacent, then of the eight segments around those two cells, either the "inner" set of four segments sharing a common endpoint (the point shared by the 1s) or the other "outer" set of four segments must all be X'd out. Thus if any two inner or outer segments in one 1 are X'd, the respective inner or outer segments of the other 1 must also be X'd.If two 1s are adjacent along the edge of the grid, the line between them can be X'd out, because there would be no direction for it to continue when it reached the edge.
Slitherlink	Solution methods	A rule for squares with 2 If a 2 has any surrounding line X’d, then a line coming into either of the two corners not adjacent to the X’d out line cannot immediately exit at right angles away from the 2, as then two lines around the 2 would be impossible, and can therefore be X’d. This means that the incoming line must continue on one side of the 2 or the other. This in turn means that the second line of the 2 must be on the only remaining free side, adjacent to the originally X’d line, so that can be filled in. Conversely, if a 2 has a line on one side, and an adjacent X’d out line, then the second line must be in one of the two remaining sides, and exit from the opposite corner (in either direction). If either of those two exits is X’d out, then it must take the other route.
Slitherlink	Solution methods	Rules for squares with 3 If a 3 is adjacent to a 0, either horizontally or vertically, then all edges of that 3 can be filled except for the one touching the 0. In addition, the two lines perpendicular to the adjacent boxes can be filled.If two 3s are adjacent to each other horizontally or vertically, their common edge must be filled in, because the only other option is a closed oval that is impossible to connect to any other line. Second, the two outer lines of the group (parallel to the common line) must be filled in. Thirdly, the line through the 3s will always wrap around in an "S" shape. Therefore, the line between the 3s cannot continue in a straight line, and those sides which are in a straight line from the middle line can be X'd out.If a 3 is adjacent to a 0 diagonally, both sides of the 3 that meet the 0's corner must be filled. This is because if either of those sides were open, the line ending in the corner of the 0 would have no place to go. This is similar to the 3-in-a-corner rule.Similarly, if a 3 has a corner with Xs in both directions going away from that corner, then both sides of the 3 that meet that corner must be filled. This is because if one of those two sides of the 3 were open, the other would have to be filled (because the 3 can only have one open side) but would meet 3 Xs at that corner, which is impossible because each point on the grid must have exactly 2 or 0 lines.
Slitherlink	Solution methods	If a line reaches a corner of a 3, there must be lines on both sides of the 3 that said corner is not adjacent to, because if the 3's sole empty space were not adjacent to it, the corner would have three lines connected to it. Furthermore, the segment leading away from the 3 at the corner reached by the line must be empty; if it were filled, neither of the remaining 2 undetermined sides of the 3 would be able to contain a line.
Slitherlink	Solution methods	Diagonals of 3s and 2s If two 3s are adjacent diagonally, the edges which do not run into the common point must be filled in.Similarly, if two 3s are in the same diagonal, but separated by any number of 2s (and only 2s) the outside edges of the 3s must be filled in, just as if they were adjacent diagonally.If there is a series of 2s in a diagonal line and an angled line meets the corner of the 2 at one end of the series, a matching angled line can be drawn all the way up the series.If a line reaches the starting point (A) of a diagonal that contains one or more 2s and ends with a 3, both sides of the far corner (farthest from A on the diagonal) of the 3 must be filled. If this were not true, it would imply that both sides of the near corner of the 3 must be filled, which would imply that the near corners of all the 2s must be filled, including the 2 at the start of the diagonal, which is impossible because it conflicts with the line that has reached the starting point (A).
Slitherlink	Solution methods	Diagonals of a 3 and 1 If a 1 and a 3 are adjacent diagonally and the outer two sides of the 1 are X'd out, then the outer two sides of the 3 must be filled in.The opposite is the same: if the outer two corners of the 3 are filled in, then the outer two corners of the 1 must be X'd out.
Slitherlink	Solution methods	Diagonals starting with a 2 If a line reaches a corner of a 2, and the line must continue through one of the two connecting sides of the 2, then exactly one of the other two sides of the 2 must be filled, and that line must continue through one of the two connecting sides of the diagonally adjacent square.
Slitherlink	Solution methods	A rule for closed regions If a region of the lattice is closed-off (such that no lines can "escape"), and is not empty, there must be a non-zero, even number of lines entering the region that begin outside the region. (An odd number of lines entering implies an odd number of segment ends inside the region, which makes it impossible for all the segment ends to connect. If there are no such lines, the lines inside the region cannot connect with the lines outside, making a solution impossible.) Often, this rule will eliminate one or more otherwise feasible options.
Slitherlink	Solution methods	In the figure below, the line at the top-left will close off the top-right region of the lattice whether it proceeds down or to the right. The line to the right (around two sides of the 3) has entered the closed region. To satisfy the rule, the first line must enter the region, and the second line must not enter the region a second time. (Since the boundary of any closed region also closes off the remainder of the puzzle, the rule can also be applied to the larger, bottom-left region. To apply the rule, it is only necessary to count the lines crossing the boundary.) Jordan curve theorem In an exceptionally difficult puzzle, one may use the Jordan curve theorem, which states that any open curve that starts and ends outside of a closed curve must intersect the closed curve an even number of times. In particular, this means that any row of the grid must have an even number of vertical lines and any column must have an even number of horizontal lines. When only one potential line segment in one of these groups is unknown, you can determine whether it is part of the loop or not with this theorem. This also means that if you mentally trace an arbitrary path from an outer edge of the grid, to another outer edge of the grid, the path will intersect the closed curve an even number of times. A simple strategy to assist in using this theorem is to "paint" (sometimes called "shade") the outside and the inside areas. When you see two outside cells, or two inside cells next to each other, then you know that there is not a line between them. The converse is also true: if you know there is no line between two cells, then those cells must be the same "color" (both inside or both outside). Similarly, if an outside cell and an inside cell are adjacent, you know there must be a filled line between them; and again the converse is true.
Slitherlink	Solution methods	Rules for puzzles that have only 1 solution If there are exactly two possible paths, A and B, between two points in the solution (two points that have been, or must be, reached by lines); and if a solution containing A must also work with B, and the reverse is not true; then B is the correct path, and the solution must pass through a point contained in A but not B.In the figure below, if a solution could pass through the top and right sides of the 2, then there must be another solution which is exactly the same except that it passes through the bottom and left sides of the 2, because the squares to the top and right of the 2 are unconstrained (do not contain numbers). Also, the solution must pass through the top-right corner of the 2, otherwise there must be another solution which is exactly the same except that it passes through the top and right sides of the 2.
Slitherlink	Solution methods	If there is a 2 in a corner, and the two non-diagonally adjacent squares are unconstrained, lines can be drawn as shown below. (In the figure, the question mark represents any number or blank, but the number will only be a 2 or 3. A puzzle with only one solution cannot have a 2 in a corner with two non-diagonally adjacent, unconstrained squares, and a diagonally adjacent 0 or 1.) If there are two paths between two points, such that a solution containing one must also work with the other, then both paths can be ruled out.In the figure below, the circled points can be connected by a line directly between them, and also by a line that traverses the other three sides of the square that extends to the left of the points. It should be clear (with the red line ignored) that for both paths the remainder of the solution can be the same – since the constraints for the remainder of the solution are the same – so both paths are ruled out.
Slitherlink	History	Slitherlink is an original puzzle of Nikoli; it first appeared in Puzzle Communication Nikoli #26 (June 1989). The editor combined two original puzzles contributed there. At first, every square contained a number and the edges did not have to form a loop.
Slitherlink	Video games	Slitherlink puzzles have been featured in video games on several platforms. A game titled Slither Link was published in Japan by Bandai for the Wonderswan portable console in 2000. Slitherlink puzzles were included alongside Sudoku and Nonogram puzzles in the Loppi Puzzle Magazine: Kangaeru Puzzle series of games from Success for the Game Boy Nintendo Power cartridge in 2001. Slitherlink games were also featured for the Nintendo DS handheld game console, with Hudson Soft releasing Puzzle Series Vol. 5: Slitherlink in Japan on November 16, 2006, and Agetec including Slitherlink in its Nikoli puzzle compilation, Brain Buster Puzzle Pak, released in North America on June 17, 2007.
Small-signal model	Small-signal model	Small-signal modeling is a common analysis technique in electronics engineering used to approximate the behavior of electronic circuits containing nonlinear devices with linear equations. It is applicable to electronic circuits in which the AC signals (i.e., the time-varying currents and voltages in the circuit) are small relative to the DC bias currents and voltages. A small-signal model is an AC equivalent circuit in which the nonlinear circuit elements are replaced by linear elements whose values are given by the first-order (linear) approximation of their characteristic curve near the bias point.
Small-signal model	Overview	Many of the electrical components used in simple electric circuits, such as resistors, inductors, and capacitors are linear. Circuits made with these components, called linear circuits, are governed by linear differential equations, and can be solved easily with powerful mathematical frequency domain methods such as the Laplace transform.In contrast, many of the components that make up electronic circuits, such as diodes, transistors, integrated circuits, and vacuum tubes are nonlinear; that is the current through them is not proportional to the voltage, and the output of two-port devices like transistors is not proportional to their input. The relationship between current and voltage in them is given by a curved line on a graph, their characteristic curve (I-V curve). In general these circuits don't have simple mathematical solutions. To calculate the current and voltage in them generally requires either graphical methods or simulation on computers using electronic circuit simulation programs like SPICE.
Small-signal model	Overview	However in some electronic circuits such as radio receivers, telecommunications, sensors, instrumentation and signal processing circuits, the AC signals are "small" compared to the DC voltages and currents in the circuit. In these, perturbation theory can be used to derive an approximate AC equivalent circuit which is linear, allowing the AC behavior of the circuit to be calculated easily. In these circuits a steady DC current or voltage from the power supply, called a bias, is applied to each nonlinear component such as a transistor and vacuum tube to set its operating point, and the time-varying AC current or voltage which represents the signal to be processed is added to it. The point on the graph representing the bias current and voltage is called the quiescent point (Q point). In the above circuits the AC signal is small compared to the bias, representing a small perturbation of the DC voltage or current in the circuit about the Q point. If the characteristic curve of the device is sufficiently flat over the region occupied by the signal, using a Taylor series expansion the nonlinear function can be approximated near the bias point by its first order partial derivative (this is equivalent to approximating the characteristic curve by a straight line tangent to it at the bias point). These partial derivatives represent the incremental capacitance, resistance, inductance and gain seen by the signal, and can be used to create a linear equivalent circuit giving the response of the real circuit to a small AC signal. This is called the "small-signal model". The small signal model is dependent on the DC bias currents and voltages in the circuit (the Q point). Changing the bias moves the operating point up or down on the curves, thus changing the equivalent small-signal AC resistance, gain, etc. seen by the signal. Any nonlinear component whose characteristics are given by a continuous, single-valued, smooth (differentiable) curve can be approximated by a linear small-signal model. Small-signal models exist for electron tubes, diodes, field-effect transistors (FET) and bipolar transistors, notably the hybrid-pi model and various two-port networks. Manufacturers often list the small-signal characteristics of such components at "typical" bias values on their data sheets.
Small-signal model	Variable notation	DC quantities (also known as bias), constant values with respect to time, are denoted by uppercase letters with uppercase subscripts. For example, the DC input bias voltage of a transistor would be denoted VIN . For example, one might say that VIN=5 Small-signal quantities, which have zero average value, are denoted using lowercase letters with lowercase subscripts. Small signals typically used for modeling are sinusoidal, or "AC", signals. For example, the input signal of a transistor would be denoted as vin . For example, one might say that 0.2 cos ⁡(2πt) Total quantities, combining both small-signal and large-signal quantities, are denoted using lower case letters and uppercase subscripts. For example, the total input voltage to the aforementioned transistor would be denoted as vIN(t) . The small-signal model of the total signal is then the sum of the DC component and the small-signal component of the total signal, or in algebraic notation, vIN(t)=VIN+vin(t) . For example, 0.2 cos ⁡(2πt)
Small-signal model	PN junction diodes	The (large-signal) Shockley equation for a diode can be linearized about the bias point or quiescent point (sometimes called Q-point) to find the small-signal conductance, capacitance and resistance of the diode. This procedure is described in more detail under diode modelling#Small-signal_modelling, which provides an example of the linearization procedure followed in small-signal models of semiconductor devices.
Small-signal model	Differences between small signal and large signal	A large signal is any signal having enough magnitude to reveal a circuit's nonlinear behavior. The signal may be a DC signal or an AC signal or indeed, any signal. How large a signal needs to be (in magnitude) before it is considered a large signal depends on the circuit and context in which the signal is being used. In some highly nonlinear circuits practically all signals need to be considered as large signals.
Small-signal model	Differences between small signal and large signal	A small signal is part of a model of a large signal. To avoid confusion, note that there is such a thing as a small signal (a part of a model) and a small-signal model (a model of a large signal). A small signal model consists of a small signal (having zero average value, for example a sinusoid, but any AC signal could be used) superimposed on a bias signal (or superimposed on a DC constant signal) such that the sum of the small signal plus the bias signal gives the total signal which is exactly equal to the original (large) signal to be modeled. This resolution of a signal into two components allows the technique of superposition to be used to simplify further analysis. (If superposition applies in the context.) In analysis of the small signal's contribution to the circuit, the nonlinear components, which would be the DC components, are analyzed separately taking into account nonlinearity.
Shikkui	Shikkui	Shikkui (漆喰) is an ecological nontoxic Japanese lime plaster primarily made out of hydrated lime and calcium carbonate coming from reprocessed eggshells. It is mainly used for surface coatings of walls and ceilings in housing construction. This material is reputed to achieve a notable range of traditional and modern finishes, including a full range of Venetian stucco and stone effects. Shikkui finishes allow a thin two-coat application, and their elasticity provides good stress-crack resistance. The color and texture of a finishing can be individually customized using a variety of diluted color pigments. The coatings are highly porous and naturally antiseptic, so indoor air quality is actively improved for healthier spaces. Shikkui coatings are also said to be humidity-regulating, fire-resistant, antistatic (preventing dust accumulation), hypoallergenic, antifungal and mold resistant.
Shikkui	Ecological characteristics	Limix, a Shikkui plaster-based material, has a low carbon footprint in production, and a low energy consumption in production (85% less compared to baked ceramic tiles). It absorbs VOC odors and CO2. It is also fully recyclable or decomposable.
Shikkui	Technical specifications	ASTM Test Data The Shikkui Surface Coatings have been tested in accordance with the ASTM International standards by accredited testing laboratories in the United States. • Fire Resistance (ASTM E84) Class A (Type I in other codes) • VOC Content (ASTM D3960) Zero-VOC material • Shore D Hardness (ASTM D2240) 61-85 (depending on product) • Mold/Fungal Resistance (ASTM D3273/D3274) Rating 10 (no fungal growth)
Backstitch	Backstitch	Backstitch or back stitch and its variants stem stitch, outline stitch and split stitch are a class of embroidery and sewing stitches in which individual stitches are made backward to the general direction of sewing. In embroidery, these stitches form lines and are most often used to outline shapes and to add fine detail to an embroidered picture. It is also used to embroider lettering. In hand sewing, it is a utility stitch which strongly and permanently attaches two pieces of fabric. The small stitches done back-and-forth makes the back stitch the strongest stitch among the basic stitches. Hence it can be used to sew strong seams by hand, without a sewing machine.
Backstitch	How to do it	A versatile stitch which is easy to work, backstitch is ideal for following both simple and intricate outlines and as a foundation row for more complex embroidery stitches such as herringbone ladder filling stitch. Although superficially similar to the Holbein stitch, which is commonly used in blackwork embroidery, backstitch differs in the way it is worked, requiring only a single journey to complete a line of stitching.
Backstitch	How to do it	Basic backstitch is the stitch used to outline shapes in modern cross-stitch, in Assisi embroidery and occasionally in blackwork.
Backstitch	How to do it	Stem stitch is an ancient technique; surviving mantles embroidered with stem stitch by the Paracas people of Peru are dated to the first century BCE. Stem stitch is used in the Bayeux Tapestry, an embroidered cloth probably dating to the later 1070s, for lettering and to outline areas filled with couching or laid-work.Split stitch in silk is characteristic of Opus Anglicanum, an embroidery style of Medieval England.
Backstitch	Description of the technique	Backstitch is most easily worked on an even-weave fabric, where the threads can be counted to ensure regularity, and is generally executed from right to left. The stitches are worked in a 'two steps forward, one step back' fashion, along the line to be filled, as shown in the diagram. Neatly worked in a straight line this stitch resembles chain stitching produced by a sewing machine. The back stitch can also be used as a hand sewing utility stitch to attach two pieces of fabric together.
Backstitch	Variants	Variants of backstitch include: Basic backstitch or point de sable. Threaded backstitch Pekinese stitch, a looped interlaced backstitch Stem stitch, in which each stitch overlaps the previous stitch to one side, forming a twisted line of stitching, with the thread passing below the needle. It is generally used for outlining shapes and for stitching flower stems and tendrils. Whipped back stitch using thread of a different color than the original stitch, the needle is passed under the stitch without piercing the fabric, repeated to create a colorful twisted effect Outline stitch, sometimes distinguished from stem stitch in that the thread passes above rather than below the needle. Split stitch, in which the needle pierces the thread rather than returning to one side. Ringed back stitch, back stitches are worked to create half rings, these are completed by a second row of stitches to form ring outlines Stitch gallery
Tonkatsu sauce	Tonkatsu sauce	Tonkatsu sauce or katsu sauce is a Japanese sauce served with tonkatsu (pork cutlet). It is a thick (viscosity over 2.0 pascal-second, per JAS Standard) Japanese Worcestershire-type sauce. It is similar to a brown sauce (British Isles), and can include a fish sauce, tomatoes, prunes, dates, apples, lemon juice, carrots, onions, and celery among its ingredients.
Tonkatsu sauce	History and varieties	The first tonkatsu sauce was made in 1948 by Oliver Sauce Co., Ltd. of Hyogo Prefecture. The Bull-Dog brand of tonkatsu sauce, for example, is made from malt vinegar, yeast, and vegetable and fruit purees, pastes, and extracts. In the United States, Kikkoman brand sells a fruity tonkatsu sauce with applesauce as the main ingredient.
Flip or Flop (franchise)	Flip or Flop (franchise)	Flip or Flop is a television franchise of television programs. With the exception of Flip or Flop: Follow Up, each series follows a format, with couples in different parts of the United States purchasing homes, flipping them, and reselling. As of December 29, 2017, 132 episodes of the Flip or Flop franchise have aired.
Flip or Flop (franchise)	Overview	Flip or Flop The El Moussas were both real estate agents prior to the crash in 2008, and later they began flipping homes, mostly in Orange County, California.In 2011, Tarek asked a friend to help him make an audition tape for HGTV. The friend filmed an entire episode of the process of house flipping from start to finish. The audition tape was sent to HGTV, and they were interested in talking to the couple. In 2012, HGTV signed the couple to a regular weekly program that shows the process of buying distressed property and renovating it.Christina's expertise is primarily in design, while Tarek finds and renovates homes. The show follows them as they buy homes, typically bank-owned, short sales or foreclosures, to renovate and resell.
Flip or Flop (franchise)	Overview	Flip or Flop Follow-Up Flip or Flop Follow-Up premiered July 14, 2015. The show revisits old house flips from previous Flip or Flop episodes. The series goes deeper into the issues with the individual flips, and shows previously unaired footage. The series also updates on houses that remained unsold at the time of the original production. These three stories include a successful flip, a flop, and a follow-up that ends with Tarek and Christina revisiting one of their house flips. This series did not return for a season 2 making it the first series in the franchise to end.
Flip or Flop (franchise)	Overview	Flip or Flop Vegas Flip or Flop Vegas is a television series airing on HGTV hosted by real estate agents Bristol and Aubrey Marunde. Filmed in Las Vegas, Nevada, it premiered on April 6, 2017. On June 5, 2017, HGTV announced Flip or Flop Vegas would be renewed for a second season, with 16 episodes.
Flip or Flop (franchise)	Overview	Flip or Flop Atlanta Flip or Flop Atlanta is a television series airing on HGTV hosted by real estate agent Anita Corsini and contractor husband Ken. Filmed in the metro Atlanta, Georgia area, it premiered on July 20, 2017. On August 21, 2017, HGTV announced Flip or Flop Atlanta would be renewed for a second season, with 14 episodes, which is expected to debut in 2018.
Flip or Flop (franchise)	Overview	Flip or Flop Nashville Flip or Flop Nashville will be a television series airing on HGTV hosted by real estate agents DeRon Jenkins and Page Turner. It will premiere on January 18, 2018 and will be filmed in Nashville, Tennessee. Flip or Flop Fort Worth Flip or Flop Fort Worth is a television series airing on HGTV hosted by real estate agents Andy and Ashley Williams. Filmed in Dallas, Texas, it premiered on November 2, 2017. Flip or Flop Chicago On March 1, 2017, HGTV announced that "Flip or Flop" would expand to Chicago, Illinois. The show featured a new couple, Mark and Liz Perez, flipping houses in Chicago, Illinois. It premiered as a pilot on March 23, 2017.
Flip or Flop (franchise)	Overview	Christina on the Coast In June 2018 it was announced that Christina would be receiving her own spin off show known as Christina on the Coast. The series premiere will focus on Christina renovating her new home following her divorce; with the remaining seven episodes focusing on her fixing up other people's homes. Filming began in fall 2018, for a spring 2019 premiere. On February 13, 2019, it was announced that the series will premiere on May 23, 2019.
Media multitasking	Media multitasking	Media multitasking is the concurrent use of multiple digital media streams. Media multitasking has been associated with depressive symptoms and social anxiety by a single study involving 318 participants. A 2018 review found that while the literature is sparse and inconclusive, people who do a heavy amount of media multitasking have poorer performance in several cognitive domains. One of the authors commented that while the data does not "unambiguously show that media multitasking causes a change in attention and memory," media multitasking is an inefficient practice that requires "task switching" costs.In many cases, media multitasking is made up of experiences that are not necessarily intended to be combined or coordinated. For example, a user may be browsing the Web, listening to music, playing video games, using e-mail, and/or talking on the phone while watching TV. More intentionally coordinated forms of media multitasking are emerging in the form of "co-active media" and particularly "co-active TV".
Media multitasking	Cognitive distraction	A touchstone 2009 study by Stanford University used experiments to compare heavy media multitaskers to light media multitaskers in terms of their cognitive control and ability to process information. Findings from the experiment include: When intentionally distracting elements were added to experiments, heavy media multitaskers were on average 0.08 seconds slower than their lighter media multitasking counterparts at identifying changes in patterns; In a longer-term memory test that invited participants to recall specific elements from earlier experiments, the high multitaskers more often falsely identified the elements that had been used most frequently as intentional distractors; In the presence of distracting elements, high multitaskers were 0.4 seconds slower than their counterparts to switch to new activities and 0.3 seconds slower to engage in a new section of the same activity.The researchers concluded that heavy media multitaskers are distracted by the multiple streams of media they are consuming, and that not multitasking can help with concentration. In the "bottleneck theory" of cognitive performance, the slowing down seen when people multitask is called "interference." According to this theory, people have only a limited amount of cognitive resources, which allow them to focus and complete one task at a time. When people try to do several things at once or multitask, their performance suffers a slowdown because of a "cognitive bottleneck," like a traffic jam in the brain.
Media multitasking	Cognitive distraction	Researchers tried to disprove this theory over several decades, and although they found a handful of activities that people can do simultaneously without slowing, these activities are relatively simple and so far removed from everyday human activities—that they cannot be used as support for people's ability to multitask. A team of researchers reviewed the extensive literature on multitasking and concluded that hundreds of studies show that slowing will happen when people try to multitask; in fact, many studies that were designed to show that people could multitask without interference in fact indicated the opposite. These researchers warned that when people attempt to multitask, especially when doing complex and potentially dangerous tasks (such as driving and using their cell phones to talk or text), they will always encounter the cognitive bottleneck, causing their performance to suffer in terms of speed or accuracy.A related article, "Breadth-biased versus focused cognitive control in media multitasking behaviors," notes that the prevalence of this phenomenon leads "to a question about the required skills and expertise to function in society. A society with its ever-increasing complexity appears to move people towards juggling among multiple tasks rather than focusing on one task for a long period." The study's author suggests that further research will be necessary as the effects on society become more pronounced: "The new technologies are gearing people, especially young people who grow up with digital technologies and wired networks, toward breadth-biased information processing behavior rather than linear in-depth study behavior. Long-term exposure to media multitasking is expected to produce both positive and negative outcomes on cognitive, emotional, and social development." By generation Despite the research, people from younger generations report that they feel multitasking is easy, even "a way of life." They perceive themselves as good at it and spend a substantial amount of their time engaged in one form of multitasking or another (for example, watching TV while doing homework, listening to music while doing homework, or even all three things at once). By contrast, members of older generations often openly admit that they are not very good at multitasking, finding it difficult, and therefore, do not do it as often as young people.
Media multitasking	Cognitive distraction	In the workforce Multitasking behavior in the workforce has been increasing steadily since the 1990s as people have easier, and therefore faster, access to information and communication through smart technologies that have become cheaper over time. Although multitasking behavior harms performance, the paradox is that organizational productivity is increasing at a high rate nonetheless. Concurrent with increased multitasking in the workforce and the subsequent rise in productivity and multitasking in general, literature has witnessed progressively more reports of increased stress, loss of focus, symptoms resembling attention deficit hyperactivity disorder (ADHD), and even a lowering of IQ.
Media multitasking	Cognitive distraction	While driving Research in media multitasking in real-world settings focused mostly on using cellphones while driving. There is an overwhelming amount of evidence to show that talking on a phone while driving is very dangerous, often leading to crashes, including those fatal to both drivers and pedestrians. Just one hour of talking on a cellphone per month while driving makes a person between four and nine times more likely to crash. Meanwhile, people who text while driving are 23 times more likely to be involved in some kind of accident. A large review of studies on driving while media multitasking showed that using a hands-free phone while driving is just as dangerous as using a hand-held version, and that both can result in many different driving mistakes including missing stop signs, forgetting to reduce speed when necessary, and following too closely, among many others. Also, media multitasking while driving with other technologies, including MP3 players, voice-based email, a car's music system, and even the GPS, is just as distracting as using a phone. Talking to a person on a cellphone while driving is not the same as having a conversation with a passenger, as adult passengers (but not children) often warn the driver of possible dangers, or at least stop talking when the driving conditions are tough, to let the driver focus on the road.
Media multitasking	Learning	Students commonly use multiple portable digital technologies, including laptops, tablets and smartphones with wireless access to the Internet.
Media multitasking	Learning	Students can use technologies in the classroom to multi-task in two specific ways when given the choice: For on-task purposes that supplement learning and ease the learning task, or for off-task purposes such as entertainment or social interaction. Overall, research shows that digital technologies can enhance learning when used as educational tools, as they are affordable and extremely portable. However, research consistently shows that inappropriate multitasking with digital technologies is harmful to student performance.
Media multitasking	Learning	On-task multitasking Students use technology for many diverse on-task purposes including taking notes, conducting literature searches, viewing video/audio files, creating and viewing spreadsheets and PowerPoint slides, completing online tests and assignments, and even texting friends to ask questions about course material. Outside of the classroom, students frequently use technology such as instant messaging to communicate with other students, coordinate group work, share important files and homework, and form peer support groups to vent and improve motivation.
Media multitasking	Learning	Students in grade school and high school benefit most from on-task use of technology. This is largely because at the grade school and high school levels, technology is integrated into the design of the course, and teachers provide the necessary structure and supervision. Such conditions allow students to process information more deeply and apply the newly learned information to new contexts, as well as improve collaboration among students.
Media multitasking	Learning	However, university students do not generally benefit from technology. The results of one study showed no benefits to using laptops for improving student GPA (grade point average) in comparison to students who did not use laptops. Two further studies showed that students who did not use laptops outperformed those who did use laptops. Overall, there is a pattern of decreasing the effectiveness of using technology for on-task purposes from the grade school level to the university level. This appears to be due to increased freedom of use of technology, combined with lower levels of integration of specific technology in the design of specific course material. Additionally, younger students and students from financially disadvantaged backgrounds who have high levels of Internet use are at an especially high risk of under-performing.
Media multitasking	Learning	Off-task multitasking A large portion of students use digital technologies for off-task purposes during classroom lectures, with social networking (especially Facebook), instant messaging, texting, emailing, and web-browsing being used most commonly Moreover, young adults multitask more than older adults and males multitask more than females for off-task purposes. The results of numerous studies show that high Internet use for off-task purposes is associated with lower GPA.
Media multitasking	Learning	One experimental study compared the impact of using 4 different technologies for off-task purposes including MSN, email, texting, and Facebook, to three control groups during real classroom lectures. The three control groups included one group of students who were free to use any amount of technologies as they wished including any on-task or off-task purposes. The other two groups were on-task note-takers who took notes either on paper, or on a laptop. The results showed that students in the MSN and Facebook conditions scored lower on a memory test than the paper notes control group. When examining the amount of multitasking instead of specific technologies, the results showed that greater levels of multitasking led to progressively lower grades.
Media multitasking	Learning	While all studies show that any kind of off-task multitasking lowers performance, some tasks impair performance more than others. Specifically, social networking is particularly bad for student performance as it leads to higher levels of unfinished assignments and lower GPAs. Moreover, off-task multitasking distracts not only the user but also neighboring students.
Media multitasking	Learning	Student multitasking An observational study of how students study at home examined their study habits and strategies. The results showed that most students prefer to task-switch a lot and focus for only approximately 6 minutes before reaching for their favorite digital device. Moreover, the students who enjoyed task-switching did so more often and with more technologies in comparison to students who preferred to focus on a single learning task, and who therefore did not have as many technologies readily available. Consistent with previous studies, students with a preference for focusing and those who used proper study strategies had higher GPAs than students who preferred to task-switch.
Media multitasking	Learning	Karpinski and colleagues (2013) compared multitasking behaviors of students from Europe to those of students from the U.S. They found that only the students from the U.S. were distracted by multitasking to the point that their GPA suffered. This was due to two main reasons: the U.S. students multitask more than European students and the European students, when engaging in multitasking, were more strategic in their multitasking behavior as they delayed replying to incoming messages. The concept of "digital meta cognition"—awareness of one's usage of and the effects of digital devices—has been proposed as a construct for providing a way to avoid problems with media multitasking while learning.
DEC Alpha	DEC Alpha	Alpha (original name Alpha AXP) is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets. Alpha is implemented in a series of microprocessors originally developed and fabricated by DEC. These microprocessors are most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, including PC form factor motherboards.
DEC Alpha	DEC Alpha	Operating systems that support Alpha included OpenVMS (formerly named OpenVMS AXP), Tru64 UNIX (formerly named DEC OSF/1 AXP and Digital UNIX), Windows NT (discontinued after NT 4.0; and prerelease Windows 2000 RC2), Linux (Debian, SUSE, Gentoo and Red Hat), BSD UNIX (NetBSD, OpenBSD and FreeBSD up to 6.x), Plan 9 from Bell Labs, and the L4Ka::Pistachio kernel. A port of Ultrix to Alpha was carried out during the initial development of the Alpha architecture, but was never released as a product.The Alpha architecture was sold, along with most parts of DEC, to Compaq in 1998. Compaq, already an Intel x86 customer, announced that they would phase out Alpha in favor of the forthcoming Hewlett-Packard/Intel Itanium architecture, and sold all Alpha intellectual property to Intel, in 2001, effectively killing the product. Hewlett-Packard purchased Compaq in 2002, continuing development of the existing product line until 2004, and selling Alpha-based systems, largely to the existing customer base, until April 2007.
DEC Alpha	History	PRISM Alpha emerged from an earlier RISC project named Parallel Reduced Instruction Set Machine (PRISM), itself the product of several earlier projects. PRISM was intended to be a flexible design, supporting Unix-like applications, and Digital's existing VAX/VMS software, after minor conversion. A new operating system named MICA would support both ULTRIX and VAX/VMS interfaces on a common kernel, allowing software for both platforms to be easily ported to the PRISM architecture.Started in 1985, the PRISM design was continually changed during its development in response to changes in the computer market, leading to lengthy delays in its introduction. It was not until the summer of 1987 that it was decided that it would be a 64-bit design, among the earliest such designs in a microprocessor format. In October 1987, Sun Microsystems introduced the Sun-4, their first workstation using their new SPARC processor. The Sun-4 runs about three to four times as fast as their latest Sun-3 designs using the Motorola 68020, and any Unix offering from DEC. The plans changed again; PRISM was realigned once again as a 32-bit part and aimed directly at the Unix market. This further delayed the design.Having watched the PRISM delivery date continue to slip, and facing the possibility of more delays, a team in the Palo Alto office decided to design their own workstation using another RISC processor. After due diligence, they selected the MIPS R2000 and built a working workstation running Ultrix in a period of 90 days. This sparked off an acrimonious debate within the company, which came to a head in a July 1988 management meeting. PRISM appeared to be faster than the R2000, but the R2000 machines could be in the market by January 1989, a year earlier than PRISM. When this proposal was accepted, one of the two original roles for PRISM disappeared. The decision to make a VMS PRISM had already ended by this point, so there was no remaining role. PRISM was cancelled at the meeting.
DEC Alpha	History	RISCy VAX As the meeting broke up, Bob Supnik was approached by Ken Olsen, who stated that the RISC chips appeared to be a future threat to their VAX line. He asked Supnik to consider what might be done with VAX to keep it competitive with future RISC systems.This led to the formation of the "RISCy VAX" team. They initially considered three concepts. One was a cut-down version of the VAX instruction set architecture (ISA) that would run on a RISC-like system and leave more complex VAX instructions to system subroutines. Another concept was a pure RISC system that would translate existing VAX code into its own ISA on-the-fly and store it in a CPU cache. Finally, there was still the possibility of a much faster CISC processor running the complete VAX ISA. Unfortunately, all of these approaches introduced overhead and would not be competitive with a pure-RISC machine running native RISC code.The group then considered hybrid systems that combined one of their existing VAX one-chip solution and a RISC chip as a coprocessor used for high-performance needs. These studies suggested that the system would inevitably be hamstrung by the lower-performance part and would offer no compelling advantage. It was at this point that Nancy Kronenberg pointed out that people ran VMS, not VAX, and that VMS only had a few hardware dependencies based on its modelling of interrupts and memory paging. There appeared to be no compelling reason why VMS could not be ported to a RISC chip as long as these small bits of the model were preserved. Further work on this concept suggested this was a workable approach.Supnik took the resulting report to the Strategy Task Force in February 1989. Two questions were raised: could the resulting RISC design also be a performance leader in the Unix market, and should the machine be an open standard? And with that, the decision was made to adopt the PRISM architecture with the appropriate modifications. This became the "EVAX" concept, a follow-on to the successful CMOS CVAX implementation. When management accepted the findings, they decided to give the project a more neutral name, removing "VAX", eventually settling on Alpha. Soon after, work began on a port of VMS to the new architecture.
DEC Alpha	History	Alpha The new design uses most of the basic PRISM concepts, but was re-tuned to allow VMS and VMS programs to run at reasonable speed with no conversion at all. The primary Alpha instruction set architects were Richard L. Sites and Richard T. Witek. The PRISM's Epicode was developed into the Alpha's PALcode, providing an abstracted interface to platform- and processor implementation-specific features.
DEC Alpha	History	The main contribution of Alpha to the microprocessor industry, and the main reason for its performance, is not so much the architecture but rather its implementation. At that time (as it is now), the microchip industry was dominated by automated design and layout tools. The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the complex VAX architecture. The Alpha chips show that manual circuit design applied to a simpler, cleaner architecture allows for much higher operating frequencies than those that are possible with the more automated design systems. These chips caused a renaissance of custom circuit design within the microprocessor design community.
DEC Alpha	History	Originally, the Alpha processors were designated the DECchip 21x64 series, with "DECchip" replaced in the mid-1990s with "Alpha". The first two digits, "21" signifies the 21st century, and the last two digits, "64" signifies 64 bits. The Alpha was designed as 64-bit from the start and there is no 32-bit version. The middle digit corresponds to the generation of the Alpha architecture. Internally, Alpha processors were also identified by EV numbers, EV officially standing for "Extended VAX" but having an alternative humorous meaning of "Electric Vlasic", giving homage to the Electric Pickle experiment at Western Research Lab.In May 1997, DEC sued Intel for allegedly infringing on its Alpha patents in designing the original Pentium, Pentium Pro, and Pentium II chips. As part of a settlement, much of DEC's chip design and fabrication business was sold to Intel. This included DEC's StrongARM implementation of the ARM computer architecture, which Intel marketed as the XScale processors commonly used in Pocket PCs. The core of Digital Semiconductor, the Alpha microprocessor group, remained with DEC, while the associated office buildings went to Intel as part of the Hudson fab.
DEC Alpha	History	Improved models The first few generations of the Alpha chips were some of the most innovative of their time. The first version, the Alpha 21064 or EV4, is the first CMOS microprocessor whose operating frequency rivalled higher-powered ECL minicomputers and mainframes. The second, 21164 or EV5, is the first microprocessor to place a large secondary cache on-chip. The third, 21264 or EV6, is the first microprocessor to combine both high operating frequency and the more complicated out-of-order execution microarchitecture. The 21364 or EV7 is the first high performance processor to have an on-chip memory controller.
DEC Alpha	History	The unproduced 21464 or EV8 would have been the first to include simultaneous multithreading, but this version was canceled after the sale of DEC to Compaq. The Tarantula research project, which most likely would have been called EV9, would have been the first Alpha processor to feature a vector processor unit.A persistent report attributed to DEC insiders suggests the choice of the AXP tag for the processor was made by DEC's legal department, which was still smarting from the VAX trademark fiasco. After a lengthy search the tag "AXP" was found to be entirely unencumbered. Within the computer industry, a joke got started that the acronym AXP meant "Almost eXactly PRISM".
DEC Alpha	Design principles	The Alpha architecture was intended to be a high-performance design. Digital intended the architecture to support a one-thousandfold increase in performance over twenty-five years. To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have: Branch delay slots Suppressed instructions Byte load or store instructions (later added with the Byte Word Extensions (BWX)) Condition codes The Alpha does not have condition codes for integer instructions to remove a potential bottleneck at the condition status register. Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 64 bits, write the 32 or 64 least significant bits to the destination register. The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand. If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition.
DEC Alpha	Registers	The architecture defines a set of 32 integer registers and a set of 32 floating-point registers in addition to a program counter, two lock registers and a floating-point control register (FPCR). It also defines registers that were optional, implemented only if the implementation required them. Lastly, registers for PALcode are defined.
DEC Alpha	Registers	The integer registers are denoted by R0 to R31 and floating-point registers are denoted by F0 to F31. The R31 and F31 registers are hardwired to zero and writes to those registers by instructions are ignored. Digital considered using a combined register file, but a split register file was determined to be better, as it enables two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating-point registers. A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports. The number of registers per register file was also considered, with 32 and 64 being contenders. Digital concluded that 32 registers was more suitable as it required less die space, which improves clock frequencies. This number of registers was deemed not to be a major issue in respect to performance and future growth, as thirty-two registers could support at least eight-way instruction issue.
DEC Alpha	Registers	The program counter is a 64-bit register which contains a longword-aligned virtual byte address, that is, the low two bits of the program counter are always zero. The PC is incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support. The floating-point control register (FPCR) is a 64-bit register defined by the architecture intended for use by Alpha implementations with IEEE 754-compliant floating-point hardware.
DEC Alpha	Data types	In the Alpha architecture, a byte is defined as an 8-bit datum (octet), a word as a 16-bit datum, a longword as a 32-bit datum, a quadword as a 64-bit datum, and an octaword as a 128-bit datum.
DEC Alpha	Data types	The Alpha architecture originally defined six data types: Quadword (64-bit) integer Longword (32-bit) integer IEEE T-floating-point (double precision, 64-bit) IEEE S-floating-point (single precision, 32-bit)To maintain a level of compatibility with the VAX, the 32-bit architecture that preceded the Alpha, two other floating-point data types are included: VAX G-floating point (double precision, 64-bit) VAX F-floating point (single precision, 32-bit) VAX H-floating point (quad precision, 128-bit) was not supported, but another 128-bit floating-point option, X-floating point, is available on Alpha, but not VAX.H and X have been described as similar, but not identical. Software emulation for H-floating is available from DEC, as is a source-code level converter named DECmigrate.
DEC Alpha	Memory	The Alpha has a 64-bit linear virtual address space with no memory segmentation. Implementations can implement a smaller virtual address space with a minimum size of 43 bits. Although the unused bits were not implemented in hardware such as TLBs, the architecture required implementations to check whether they are zero to ensure software compatibility with implementations with a larger (or full) virtual address space.
DEC Alpha	Instruction formats	The Alpha ISA has a fixed instruction length of 32 bits. It has six instruction formats.
DEC Alpha	Instruction formats	The integer operate format is used by integer instructions. It contains a 6-bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand. Next is a 3-bit field which is unused and reserved. A 1-bit field contains a "0", which distinguished this format from the integer literal format. A 7-bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to. The register fields are all 5 bits long, required to address 32 unique locations, the 32 integer registers.
DEC Alpha	Instruction formats	The integer literal format is used by integer instructions which use a literal as one of the operands. The format is the same as the integer operate format except for the replacement of the 5-bit Rb field and the 3 bits of unused space with an 8-bit literal field which is zero-extended to a 64-bit operand. The floating-point operate format is used by floating-point instructions. It is similar to the integer operate format, but has an 11-bit function field made possible by using the literal and unused bits which are reserved in integer operate format. The memory format is used mostly by load and store instructions. It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a 16-bit displacement field.
DEC Alpha	Instruction formats	Branch instructions have a 6-bit opcode field, a 5-bit Ra field and a 21-bit displacement field. The Ra field specifies a register to be tested by a conditional branch instruction, and if the condition is met, the program counter is updated by adding the contents of the displacement field with the program counter. The displacement field contains a signed integer and if the value of the integer is positive, if the branch is taken then the program counter is incremented. If the value of the integer is negative, then program counter is decremented if the branch is taken. The range of a branch thus is ±1 Mi instructions, or ±4 MiB. The Alpha Architecture was designed with a large range as part of the architecture's forward-looking goal.
DEC Alpha	Instruction formats	The CALL_PAL format is used by the CALL_PAL instruction, which is used to call PALcode subroutines. The format retains the opcode field but replaces the others with a 26-bit function field, which contains an integer specifying a PAL subroutine.
DEC Alpha	Instruction set	Control instructions The control instructions consist of conditional and unconditional branches, and jumps. The conditional and unconditional branch instructions use the branch instruction format, while the jump instructions use the memory instruction format.
DEC Alpha	Instruction set	Conditional branches test whether the least significant bit of a register is set or clear, or compare a register as a signed quadword to zero, and branch if the specified condition is true. The conditions available for comparing a register to zero are equality, inequality, less than, less than or equal to, greater than or equal to, and greater than. The new address is computed by longword aligning and sign extending the 21-bit displacement and adding it to the address of the instruction following the conditional branch.
DEC Alpha	Instruction set	Unconditional branches update the program counter with a new address computed in the same way as conditional branches. They also save the address of the instruction following the unconditional branch to a register. There are two such instructions, and they differ only in the hints provided for the branch prediction hardware. There are four jump instructions. These all perform the same operation, saving the address of the instruction following the jump, and providing the program counter with a new address from a register. They differ in the hints provided to the branch prediction hardware. The unused displacement field is used for this purpose.
DEC Alpha	Instruction set	Integer arithmetic The integer arithmetic instructions perform addition, multiplication, and subtraction on longwords and quadwords; and comparison on quadwords. There is no instruction(s) for division as the architects considered the implementation of division in hardware to be adverse to simplicity. In addition to the standard add and subtract instructions, there are scaled versions. These versions shift the second operand to the left by two or three bits before adding or subtracting. The Multiply Longword and Multiply Quadword instructions write the least significant 32 or 64 bits of a 64- or 128-bit result to the destination register, respectively. Since it is useful to obtain the most significant half, the Unsigned Multiply Quadword High (UMULH) instruction is provided. UMULH is used for implementing multi-precision arithmetic and division algorithms. The concept of a separate instruction for multiplication that returns the most significant half of a result was taken from PRISM.
DEC Alpha	Instruction set	The instructions that operate on longwords ignore the most significant half of the register and the 32-bit result is sign-extended before it is written to the destination register. By default, the add, multiply, and subtract instructions, with the exception of UMULH and scaled versions of add and subtract, do not trap on overflow. When such functionality is required, versions of these instructions that perform overflow detection and trap on overflow are provided.
DEC Alpha	Instruction set	The compare instructions compare two registers or a register and a literal and write '1' to the destination register if the specified condition is true or '0' if not. The conditions are equality, inequality, less than or equal to, and less than. With the exception of the instructions that specify the former two conditions, there are versions that perform signed and unsigned compares.
DEC Alpha	Instruction set	The integer arithmetic instructions use the integer operate instruction formats.
DEC Alpha	Instruction set	Logical and shift The logical instructions consist of those for performing bitwise logical operations and conditional moves on the integer registers. The bitwise logical instructions perform AND, NAND, NOR, OR, XNOR, and XOR between two registers or a register and literal. The conditional move instructions test a register as a signed quadword to zero and move if the specified condition is true. The specified conditions are equality, inequality, less than or equal to, less than, greater than or equal to, and greater than. The shift instructions perform arithmetic right shift, and logical left and right shifts. The shift amount is given by a register or literal. Logical and shift instructions use the integer operate instruction formats.
DEC Alpha	Extensions	Byte-Word Extensions (BWX) Later Alphas include byte-word extensions, a set of instructions to manipulate 8-bit and 16-bit data types. These instructions were first introduced in the 21164A (EV56) microprocessor and are present in all subsequent implementations. These instructions perform operations that formerly required multiple instructions to implement, which improves code density and the performance of certain applications. BWX also makes the emulation of x86 machine code and the writing of device drivers easier.
DEC Alpha	Extensions	Motion Video Instructions (MVI) Motion Video Instructions (MVI) was an instruction set extension to the Alpha ISA that added instructions for single instruction, multiple data (SIMD) operations. Alpha implementations that implement MVI, in chronological order, are the Alpha 21164PC (PCA56 and PCA57), Alpha 21264 (EV6) and Alpha 21364 (EV7). Unlike most other SIMD instruction sets of the same period, such as MIPS' MDMX or SPARC's Visual Instruction Set, but like PA-RISC's Multimedia Acceleration eXtensions (MAX-1, MAX-2), MVI was a simple instruction set composed of a few instructions that operate on integer data types stored in existing integer registers.
DEC Alpha	Extensions	MVI's simplicity is due to two reasons. Firstly, Digital had determined that the Alpha 21164 was already capable of performing DVD decoding through software, therefore not requiring hardware provisions for the purpose, but was inefficient in MPEG-2 encoding. The second reason is the requirement to retain the fast cycle times of implementations. Adding many instructions would have complicated and enlarged the instruction decode logic, reducing an implementation's clock frequency.
DEC Alpha	Extensions	MVI consists of 13 instructions: Floating-point Extensions (FIX) Floating-point extensions (FIX) are an extension to the Alpha Architecture. It introduces nine instructions for floating-point square-root and for transferring data to and from the integer registers and floating-point registers. The Alpha 21264 (EV6) is the first microprocessor to implement these instructions. Count Extensions (CIX) Count Extensions (CIX) is an extension to the architecture which introduces three instructions for counting bits. These instructions are categorized as integer arithmetic instructions. They were first implemented on the Alpha 21264A (EV67).
DEC Alpha	Implementations	At the time of its announcement, Alpha was heralded as an architecture for the next 25 years. While this was not to be, Alpha has nevertheless had a reasonably long life. The first version, the Alpha 21064 (otherwise named the EV4) was introduced in November 1992 running at up to 192 MHz; a slight shrink of the die (the EV4S, shrunk from 0.75 µm to 0.675 µm) ran at 200 MHz a few months later. The 64-bit processor was a superpipelined and superscalar design, like other RISC designs, but nevertheless outperformed them all and DEC touted it as the world's fastest processor. Careful attention to circuit design, a hallmark of the Hudson design team, like a huge centralized clock circuitry, allowed them to run the CPU at higher speeds, even though the microarchitecture was fairly similar to other RISC chips. In comparison, the less expensive Intel Pentium ran at 66 MHz when it was launched the following spring.
DEC Alpha	Implementations	The Alpha 21164 or EV5 became available in 1995 at processor frequencies of up to 333 MHz. In July 1996 the line was speed bumped to 500 MHz, in March 1998 to 666 MHz. Also in 1998 the Alpha 21264 (EV6) was released at 450 MHz, eventually reaching (in 2001 with the 21264C/EV68CB) 1.25 GHz. In 2003, the Alpha 21364 or EV7 Marvel was launched, essentially an EV68 core with four 1.6 GB/s inter-processor communication links for improved multiprocessor system performance, running at 1 or 1.15 GHz.
DEC Alpha	Implementations	In 1996, the production of Alpha chips was licensed to Samsung Electronics Company. Following the purchase of Digital by Compaq the majority of the Alpha products were placed with API NetWorks, Inc. (formerly Alpha Processor Inc.), a private company funded by Samsung and Compaq. In October 2001, Microway became the exclusive sales and service provider of API NetWorks' Alpha-based product line.
DEC Alpha	Implementations	On June 25, 2001, Compaq announced that Alpha would be phased out by 2004 in favor of Intel's Itanium, canceled the planned EV8 chip, and sold all Alpha intellectual property to Intel. Hewlett-Packard merged with Compaq in 2002; HP announced that development of the Alpha series would continue for a few more years, including the release of a 1.3 GHz EV7 variant named the EV7z. This would be the final iteration of Alpha, the 0.13 µm EV79 also being canceled.
DEC Alpha	Implementations	Alpha is also implemented in the Piranha, a research prototype developed by Compaq's Corporate Research and Nonstop Hardware Development groups at the Western Research Laboratory and Systems Research Center. Piranha is a multicore design for transaction processing workloads that contains eight simple cores. It was described at the 27th Annual International Symposium on Computer Architecture in June 2000.Early revisions of the Sunway architecture are claimed to be based on Alpha, however since the SW26010, Sunway uses a new instruction set architecture unrelated to Alpha.
DEC Alpha	Implementations	Model history ISA extensions R – Hardware support for rounding to infinity and negative infinity.
DEC Alpha	Implementations	B – BWX, the "Byte/Word Extension", adding instructions to allow 8- and 16-bit operations from memory and I/O M – MVI, "multimedia" instructions F – FIX, instructions to move data between integer and floating-point registers and for square root C – CIX, instructions for counting and finding bits T – support for prefetch with modify intent to improve the performance of the first attempt to acquire a lock
DEC Alpha	Performance	To illustrate the comparative performance of Alpha-based systems, some Standard Performance Evaluation Corporation (SPEC) performance numbers (SPECint95, SPECfp95) are listed below. Note that the SPEC results claim to report the measured performance of a whole computer system (CPU, bus, memory, compiler optimizer), not just the CPU. Also note that the benchmark and scale changed from 1992 to 1995. However, the figures give a rough impression of the performance of the Alpha architecture (64-bit), compared with the contemporary HP (64-bit) and Intel-based offerings (32-bit). Perhaps the most obvious trend is that while Intel could always get reasonably close to Alpha in integer performance, in floating-point performance the difference was considerable. On the other side, HP (PA-RISC) is also reasonably close to Alpha, but these CPUs are running at significantly lower clock rates (MHz). The tables lack two important values: the power consumption and the price of a CPU.
DEC Alpha	Alpha-based systems	The first generation of DEC Alpha-based systems comprise the DEC 3000 AXP series workstations and low-end servers, DEC 4000 AXP series mid-range servers, and DEC 7000 AXP and 10000 AXP series high-end servers. The DEC 3000 AXP systems use the same TURBOchannel bus as the prior MIPS-based DECstation models, whereas the 4000 is based on Futurebus+ and the 7000/10000 share an architecture with corresponding VAX models.
DEC Alpha	Alpha-based systems	DEC also produced a personal computer (PC) configuration Alpha workstation with an Extended Industry Standard Architecture (EISA) bus, the DECpc AXP 150 (codename Jensen, also named the DEC 2000 AXP). This is the first Alpha system to support Windows NT. DEC later produced Alpha versions of their Celebris XL and Digital Personal Workstation PC lines, with 21164 processors.

Subsets and Splits

No community queries yet

The top public SQL queries from the community will appear here once available.