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/*******************/
/* ram8x2048_sim.v */
/*******************/
`define SCAN_ASCII_ADDR 13'h0310
`define SCAN_ASCII_WEN 1'b1
// +----+
// clk->| |
// ram_addr[12:0]->| |
// ram_write_enable->| |->ram_read_data[31:0]
// ram_write_data[3... | |
//------------------------------------------------------------------
//-- Hello world example for the iCEstick board
//-- Turn on all the leds
//------------------------------------------------------------------
module leds(output wire D1,
output wire D2,
output wire D3,
out... | |
module clock_(clk, clk_, period);
input clk;
input[15:0] period;
output reg clk_;
reg[31:0] counter, p;
initial begin
counter = 0;
clk_ = 0;
p = 0;
end
always@(posedge clk) begin
if(!p) p <= 25000 * period;
else if(counter >= p) begin
counter <= 0;
clk_ <= ~clk_;
end
el... | |
`timescale 1ns/1ps
// IF/ID
module reg_if_id #(
parameter INIT_PC = 32'h0
)
(
input clk_i,
input rst_i,
input [31:0] inst_i,
input [31:0] current_pc_i,
input [31:0] return_pc_i,
input suspend_i,
input flush_i,
... |