content
stringlengths 7
1.05M
| fixed_cases
stringlengths 1
1.28M
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class Solution:
"""
@param A: An array of Integer
@return: an integer
"""
def longestIncreasingContinuousSubsequence(self, A):
n = len(A)
if n < 2:
return n
longest = 0
conti = 1
for i in range(1, n):
if A[i] > A[i - 1]:
conti += 1
else:
conti = 1
longest = max(longest, conti)
conti = 1
for i in range(1, n):
if A[i] < A[i - 1]:
conti += 1
else:
conti = 1
longest = max(longest, conti)
return longest
|
class Solution:
"""
@param A: An array of Integer
@return: an integer
"""
def longest_increasing_continuous_subsequence(self, A):
n = len(A)
if n < 2:
return n
longest = 0
conti = 1
for i in range(1, n):
if A[i] > A[i - 1]:
conti += 1
else:
conti = 1
longest = max(longest, conti)
conti = 1
for i in range(1, n):
if A[i] < A[i - 1]:
conti += 1
else:
conti = 1
longest = max(longest, conti)
return longest
|
LMS8001_REGDESC="""
REGBANK ChipConfig 0x000X
REGBANK BiasLDOConfig 0x001X
REGBANK Channel_A 0b00010000000XXXXX
REGBANK Channel_B 0b00010000001XXXXX
REGBANK Channel_C 0b00010000010XXXXX
REGBANK Channel_D 0b00010000011XXXXX
REGBANK HLMIXA 0x200X
REGBANK HLMIXB 0x201X
REGBANK HLMIXC 0x202X
REGBANK HLMIXD 0x203X
REGBANK PLL_CONFIGURATION 0b01000000000XXXXX
REGBANK PLL_PROFILE_0 0x410X
REGBANK PLL_PROFILE_1 0x411X
REGBANK PLL_PROFILE_2 0x412X
REGBANK PLL_PROFILE_3 0x413X
REGBANK PLL_PROFILE_4 0x414X
REGBANK PLL_PROFILE_5 0x415X
REGBANK PLL_PROFILE_6 0x416X
REGBANK PLL_PROFILE_7 0x417X
REGISTER SPIConfig 0x0000
BITFIELD SPI_SDIO_DS
POSITION=6
DEFAULT=0
MODE=RW
#! Driver strength of SPI_SDIO pad.
#! 0 - Driver strength is 4mA (default)
#! 1 - Driver strength is 8mA
ENDBITFIELD
BITFIELD SPI_SDO_DS
POSITION=5
DEFAULT=0
MODE=RW
#! Driver strength of SPI_SDO pad.
#! 0 - Driver strength is 4mA (default)
#! 1 - Driver strength is 8mA
ENDBITFIELD
BITFIELD SPI_SDIO_PE
POSITION=4
DEFAULT=1
MODE=RW
#! Pull up control of SPI_SDIO pad.
#! 0 - Pull up disengaged
#! 1 - Pull up engaged (default)
ENDBITFIELD
BITFIELD SPI_SDO_PE
POSITION=3
DEFAULT=1
MODE=RW
#! Pull up control of SPI_SDO pad.
#! 0 - Pull up disengaged
#! 1 - Pull up engaged (default)
ENDBITFIELD
BITFIELD SPI_SCLK_PE
POSITION=2
DEFAULT=1
MODE=RW
#! Pull up control of SPI_SCLK pad.
#! 0 - Pull up disengaged
#! 1 - Pull up engaged (default)
ENDBITFIELD
BITFIELD SPI_SEN_PE
POSITION=1
DEFAULT=1
MODE=RW
#! Pull up control of SPI_SEN pad.
#! 0 - Pull up disengaged
#! 1 - Pull up engaged (default)
ENDBITFIELD
BITFIELD SPIMODE
POSITION=0
DEFAULT=1
MODE=RWI
#! SPI communication mode.
#! 0 - 3 wire mode
#! 1 - 4 wire mode (default)
ENDBITFIELD
ENDREGISTER
REGISTER GPIOOutData 0x0004
BITFIELD GPIO_OUT_SPI<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
#! Output data for GPIO pads from SPI
ENDBITFIELD
ENDREGISTER
REGISTER GPIOOUT_SEL0 0x0005
BITFIELD GPIO4_SEL<2:0>
POSITION=<14:12>
DEFAULT=000
MODE=RWI
#! GPIO4 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO3_SEL<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! GPIO3 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO2_SEL<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! GPIO2 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO1_SEL<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! GPIO1 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO0_SEL<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! GPIO0 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
ENDREGISTER
REGISTER GPIOOUT_SEL1 0x0006
BITFIELD GPIO9_SEL<2:0>
POSITION=<14:12>
DEFAULT=000
MODE=RWI
#! GPIO9 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO8_SEL<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! GPIO8 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO7_SEL<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! GPIO7 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO6_SEL<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! GPIO6 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
BITFIELD GPIO5_SEL<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! GPIO5 source select
#! 000 - from SPI
#! 001 - PLL_LOCK
#! 010 - VTUNE_LOW
#! 011 - VTUNE_HIGH
#! 100 - Fast lock active
#! others - reserved
ENDBITFIELD
ENDREGISTER
REGISTER GPIOInData 0x0008
BITFIELD GPIO_IN<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=R
#! Data read from GPIO pads.
ENDBITFIELD
ENDREGISTER
REGISTER GPIOConfig_PE 0x0009
BITFIELD GPIO_PE<8:0>
POSITION=<8:0>
DEFAULT=111111111
MODE=RW
#! GPIO pull up control
#! 0 - Pull up disengaged
#! 1 - Pull up engaged (default)
ENDBITFIELD
ENDREGISTER
REGISTER GPIOConfig_DS 0x000A
BITFIELD GPIO_DS<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RW
#! GPIO drive strength
#! 0 - Driver strength is 4mA (default)
#! 1 - Driver strength is 8mA
ENDBITFIELD
ENDREGISTER
REGISTER GPIOConfig_IO 0x000B
BITFIELD GPIO_InO<8:0>
POSITION=<8:0>
DEFAULT=111111111
MODE=RW
#! GPIO input/output control
#! 0 - Pin is output
#! 1 - Pin is input (default)
ENDBITFIELD
ENDREGISTER
REGISTER TEMP_SENS 0x000C
BITFIELD TEMP_SENS_EN
POSITION=10
DEFAULT=0
MODE=RW
#! Enable the temperature sensor biasing.
ENDBITFIELD
BITFIELD TEMP_SENS_CLKEN
POSITION=9
DEFAULT=0
MODE=RW
#! Temperature sensor clock enable.
ENDBITFIELD
BITFIELD TEMP_START_CONV
POSITION=8
DEFAULT=0
MODE=STICKYBIT
#! Start the temperature conversion.
#! Bit is cleared when the conversion is complete.
ENDBITFIELD
BITFIELD TEMP_READ<7:0>
POSITION=<7:0>
DEFAULT=00000000
MODE=R
#! Readout of temperature sensor
ENDBITFIELD
ENDREGISTER
REGISTER ChipInfo 0x000F
BITFIELD VER<4:0>
POSITION=<15:11>
DEFAULT=01000
MODE=RI
#! Chip version.
#! 01000 - Chip version is 8.
ENDBITFIELD
BITFIELD REV<4:0>
POSITION=<10:6>
DEFAULT=00001
MODE=RI
#! Chip revision.
#! 00001 - Chip revision is 1.
ENDBITFIELD
BITFIELD MASK<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RI
#! Chip mask.
#! 000000 - Chip mask is 0.
ENDBITFIELD
ENDREGISTER
REGISTER BiasConfig 0x0010
BITFIELD PD_CALIB_COMP
POSITION=12
DEFAULT=1
MODE=RW
#! Calibration comparator power down.
#! 0 - Enabled
#! 1 - Powered down (default)
ENDBITFIELD
BITFIELD RP_CALIB_COMP
POSITION=11
DEFAULT=0
MODE=R
#! Comparator output. Used in rppolywo calibration algorithm.
ENDBITFIELD
BITFIELD RP_CALIB_BIAS<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RW
#! Calibration code for rppolywo. This code is set by calibration algorithm.
#! Default value : 10000 (16)
ENDBITFIELD
BITFIELD PD_FRP_BIAS
POSITION=4
DEFAULT=0
MODE=RW
#! Power down signal for Fix/RP
#! 0 - Enabled (default)
#! 1 - Powered down
ENDBITFIELD
BITFIELD PD_F_BIAS
POSITION=3
DEFAULT=0
MODE=RW
#! Power down signal for Fix
#! 0 - Enabled (default)
#! 1 - Powered down
ENDBITFIELD
BITFIELD PD_PTRP_BIAS
POSITION=2
DEFAULT=0
MODE=RW
#! Power down signal for PTAT/RP block
#! 0 - Enabled (default)
#! 1 - Powered down
ENDBITFIELD
BITFIELD PD_PT_BIAS
POSITION=1
DEFAULT=0
MODE=RW
#! Power down signal for PTAT block
#! 0 - Enabled (default)
#! 1 - Powered down
ENDBITFIELD
BITFIELD PD_BIAS
POSITION=0
DEFAULT=0
MODE=RW
#! Enable signal for central bias block
#! 0 - Sub blocks may be selectively powered down (default)
#! 1 - Poweres down all BIAS blocks
ENDBITFIELD
ENDREGISTER
REGISTER LOBUFA_LDO_Config 0x0011
BITFIELD EN_LOADIMP_LDO_LOBUFA
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_LOBUFA
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_LOBUFA
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_LOBUFA<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER LOBUFB_LDO_Config 0x0012
BITFIELD EN_LOADIMP_LDO_LOBUFB
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_LOBUFB
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_LOBUFB
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_LOBUFB<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER LOBUFC_LDO_Config 0x0013
BITFIELD EN_LOADIMP_LDO_LOBUFC
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_LOBUFC
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_LOBUFC
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_LOBUFC<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER LOBUFD_LDO_Config 0x0014
BITFIELD EN_LOADIMP_LDO_LOBUFD
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_LOBUFD
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_LOBUFD
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_LOBUFD<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER HFLNAA_LDO_Config 0x0015
BITFIELD EN_LOADIMP_LDO_HFLNAA
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_HFLNAA
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_HFLNAA
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_HFLNAA<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER HFLNAB_LDO_Config 0x0016
BITFIELD EN_LOADIMP_LDO_HFLNAB
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_HFLNAB
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_HFLNAB
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_HFLNAB<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER HFLNAC_LDO_Config 0x0017
BITFIELD EN_LOADIMP_LDO_HFLNAC
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_HFLNAC
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_HFLNAC
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_HFLNAC<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER HFLNAD_LDO_Config 0x0018
BITFIELD EN_LOADIMP_LDO_HFLNAD
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_HFLNAD
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_HFLNAD
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_HFLNAD<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER CLK_BUF_LDO_Config 0x001A
BITFIELD EN_LOADIMP_LDO_CLK_BUF
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_CLK_BUF
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_CLK_BUF
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the LO buffer LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_CLK_BUF<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER PLL_DIV_LDO_Config 0x001B
BITFIELD EN_LOADIMP_LDO_PLL_DIV
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_PLL_DIV
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_PLL_DIV
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the PLL divider LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_PLL_DIV<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the PLL divider LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_LDO_Config 0x001C
BITFIELD EN_LOADIMP_LDO_PLL_CP
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_PLL_CP
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD EN_LDO_PLL_CP
POSITION=8
DEFAULT=0
MODE=RW
#! Enables the PLL CP LDO
#! 0 - LDO powered down (default)
#! 1 - LDO enabled
ENDBITFIELD
BITFIELD RDIV_PLL_CP<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the PLL CP LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER DIG_CORE_LDO_Config 0x001F
BITFIELD EN_LOADIMP_LDO_DIG_CORE
POSITION=10
DEFAULT=0
MODE=RW
#! Enables the load dependent bias to optimize the load regulation
#! 0 - Constant bias (default)
#! 1 - Load dependant bias
ENDBITFIELD
BITFIELD SPDUP_LDO_DIG_CORE
POSITION=9
DEFAULT=0
MODE=RW
#! Short the noise filter resistor to speed up the settling time
#! 0 - Noise filter resistor in place (default)
#! 1 - Noise filter resistor bypassed
ENDBITFIELD
BITFIELD PD_LDO_DIG_CORE
POSITION=8
DEFAULT=0
MODE=RW
#! Power down the digital core and IO ring pre-drivers LDO
#! 0 - LDO on (default)
#! 1 - LDO powered down
ENDBITFIELD
BITFIELD RDIV_DIG_CORE<7:0>
POSITION=<7:0>
DEFAULT=01100101
MODE=RW
#! Controls the output voltage of the digital core and IO ring pre-drivers LDO by setting the resistive voltage divider ratio.
#! Vout = 860 mV + 3.92 mV * RDIV
#! Default : 01100101 (101) Vout = 1.25 V
ENDBITFIELD
ENDREGISTER
REGISTER CHA_MIX_ICT 0x1000
BITFIELD CHA_MIXB_ICT<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHA_MIXB_ICT/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_MIXA_ICT<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHA_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHA_HFPAD_ICT 0x1001
BITFIELD CHA_PA_ILIN2X
POSITION=10
DEFAULT=0
MODE=RW
#! Double the linearization bias current
#! 0 - Ilin * 1
#! 1 - Ilin * 2
#! Default : 0
ENDBITFIELD
BITFIELD CHA_PA_ICT_LIN<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of linearization section of HFPAD
#! I = Inom * CHA_PA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_PA_ICT_MAIN<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of main gm section of HFPAD
#! I = Inom * CHA_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD0 0x1004
BITFIELD CHA_PA_R50_EN0
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHA_PA_BYPASS0
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHA_PA_PD0
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_LOBUFF_PD0
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_BIAS_PD0
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_LOBUFF_PD0
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_LNA_PD0
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD1 0x1005
BITFIELD CHA_PA_R50_EN1
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHA_PA_BYPASS1
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHA_PA_PD1
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_LOBUFF_PD1
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_BIAS_PD1
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_LOBUFF_PD1
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_LNA_PD1
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD2 0x1006
BITFIELD CHA_PA_R50_EN2
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHA_PA_BYPASS2
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHA_PA_PD2
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_LOBUFF_PD2
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_BIAS_PD2
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_LOBUFF_PD2
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_LNA_PD2
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD3 0x1007
BITFIELD CHA_PA_R50_EN3
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHA_PA_BYPASS3
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHA_PA_PD3
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_LOBUFF_PD3
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXB_BIAS_PD3
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_LOBUFF_PD3
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_MIXA_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHA_LNA_PD3
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_CTRL0 0x1008
BITFIELD CHA_LNA_ICT_LIN0<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHA_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_ICT_MAIN0<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHA_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_CGSCTRL0<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_GCTRL0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_CTRL1 0x1009
BITFIELD CHA_LNA_ICT_LIN1<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHA_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_ICT_MAIN1<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHA_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_CGSCTRL1<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_GCTRL1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_CTRL2 0x100A
BITFIELD CHA_LNA_ICT_LIN2<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHA_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_ICT_MAIN2<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHA_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_CGSCTRL2<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_GCTRL2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_CTRL3 0x100B
BITFIELD CHA_LNA_ICT_LIN3<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHA_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_ICT_MAIN3<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHA_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHA_LNA_CGSCTRL3<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_GCTRL3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_CTRL0 0x100C
BITFIELD CHA_PA_LIN_LOSS0<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHA_PA_MAIN_LOSS0<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_CTRL1 0x100D
BITFIELD CHA_PA_LIN_LOSS1<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHA_PA_MAIN_LOSS1<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_CTRL2 0x100E
BITFIELD CHA_PA_LIN_LOSS2<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHA_PA_MAIN_LOSS2<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_CTRL3 0x100F
BITFIELD CHA_PA_LIN_LOSS3<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHA_PA_MAIN_LOSS3<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD_SEL0 0x1010
BITFIELD CHA_PD_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PD_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PD_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD_SEL1 0x1011
BITFIELD CHA_PD_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PD_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PD_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_SEL0 0x1012
BITFIELD CHA_LNA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_SEL1 0x1013
BITFIELD CHA_LNA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_SEL0 0x1014
BITFIELD CHA_PA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_SEL1 0x1015
BITFIELD CHA_PA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_INT_SEL 0x1016
BITFIELD CHA_PA_INT_SEL<1:0>
POSITION=<5:4>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHA_LNA_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHA_PD_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PD_RB 0x101D
BITFIELD CHA_PA_R50_EN_RB
POSITION=7
DEFAULT=CHA_PA_R50_EN0
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_PA_BYPASS_RB
POSITION=6
DEFAULT=CHA_PA_BYPASS
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_PA_PD_RB
POSITION=5
DEFAULT=CHA_PA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_MIXB_LOBUFF_PD_RB
POSITION=4
DEFAULT=CHA_MIXB_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_MIXB_BIAS_PD_RB
POSITION=3
DEFAULT=CHA_MIXB_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_MIXA_LOBUFF_PD_RB
POSITION=2
DEFAULT=CHA_MIXA_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_MIXA_BIAS_PD_RB
POSITION=1
DEFAULT=CHA_MIXA_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_LNA_PD_RB
POSITION=0
DEFAULT=CHA_LNA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHA_LNA_CTRL_RB 0x101E
BITFIELD CHA_LNA_ICT_LIN_RB<4:0>
POSITION=<15:11>
DEFAULT=CHA_LNA_ICT_LIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_LNA_ICT_MAIN_RB<4:0>
POSITION=<10:6>
DEFAULT=CHA_LNA_ICT_MAIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_LNA_CGSCTRL_RB<1:0>
POSITION=<5:4>
DEFAULT=CHA_LNA_CGSCTRL<1:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_LNA_GCTRL_RB<3:0>
POSITION=<3:0>
DEFAULT=CHA_LNA_GCTRL<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHA_PA_CTRL_RB 0x101F
BITFIELD CHA_PA_LIN_LOSS_RB<3:0>
POSITION=<7:4>
DEFAULT=CHA_PA_LIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHA_PA_MAIN_LOSS_RB<3:0>
POSITION=<3:0>
DEFAULT=CHA_PA_MAIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHB_MIX_ICT 0x1020
BITFIELD CHB_MIXB_ICT<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHB_MIXB_ICT/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_MIXA_ICT<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHB_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHB_HFPAD_ICT 0x1021
BITFIELD CHB_PA_ILIN2X
POSITION=10
DEFAULT=0
MODE=RW
#! Double the linearization bias current
#! 0 - Ilin * 1
#! 1 - Ilin * 2
#! Default : 0
ENDBITFIELD
BITFIELD CHB_PA_ICT_LIN<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of linearization section of HFPAD
#! I = Inom * CHB_PA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_PA_ICT_MAIN<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of main gm section of HFPAD
#! I = Inom * CHB_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD0 0x1024
BITFIELD CHB_PA_R50_EN0
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHB_PA_BYPASS0
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHB_PA_PD0
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_LOBUFF_PD0
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_BIAS_PD0
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_LOBUFF_PD0
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_LNA_PD0
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD1 0x1025
BITFIELD CHB_PA_R50_EN1
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHB_PA_BYPASS1
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHB_PA_PD1
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_LOBUFF_PD1
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_BIAS_PD1
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_LOBUFF_PD1
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_LNA_PD1
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD2 0x1026
BITFIELD CHB_PA_R50_EN2
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHB_PA_BYPASS2
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHB_PA_PD2
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_LOBUFF_PD2
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_BIAS_PD2
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_LOBUFF_PD2
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_LNA_PD2
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD3 0x1027
BITFIELD CHB_PA_R50_EN3
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHB_PA_BYPASS3
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHB_PA_PD3
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_LOBUFF_PD3
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXB_BIAS_PD3
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_LOBUFF_PD3
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_MIXA_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHB_LNA_PD3
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_CTRL0 0x1028
BITFIELD CHB_LNA_ICT_LIN0<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHB_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_ICT_MAIN0<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHB_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_CGSCTRL0<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_GCTRL0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_CTRL1 0x1029
BITFIELD CHB_LNA_ICT_LIN1<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHB_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_ICT_MAIN1<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHB_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_CGSCTRL1<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_GCTRL1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_CTRL2 0x102A
BITFIELD CHB_LNA_ICT_LIN2<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHB_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_ICT_MAIN2<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHB_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_CGSCTRL2<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_GCTRL2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_CTRL3 0x102B
BITFIELD CHB_LNA_ICT_LIN3<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHB_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_ICT_MAIN3<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHB_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHB_LNA_CGSCTRL3<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_GCTRL3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_CTRL0 0x102C
BITFIELD CHB_PA_LIN_LOSS0<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHB_PA_MAIN_LOSS0<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_CTRL1 0x102D
BITFIELD CHB_PA_LIN_LOSS1<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHB_PA_MAIN_LOSS1<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_CTRL2 0x102E
BITFIELD CHB_PA_LIN_LOSS2<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHB_PA_MAIN_LOSS2<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_CTRL3 0x102F
BITFIELD CHB_PA_LIN_LOSS3<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHB_PA_MAIN_LOSS3<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD_SEL0 0x1030
BITFIELD CHB_PD_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PD_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PD_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD_SEL1 0x1031
BITFIELD CHB_PD_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PD_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PD_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_SEL0 0x1032
BITFIELD CHB_LNA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_SEL1 0x1033
BITFIELD CHB_LNA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_SEL0 0x1034
BITFIELD CHB_PA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_SEL1 0x1035
BITFIELD CHB_PA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_INT_SEL 0x1036
BITFIELD CHB_PA_INT_SEL<1:0>
POSITION=<5:4>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHB_LNA_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHB_PD_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PD_RB 0x103D
BITFIELD CHB_PA_R50_EN_RB
POSITION=7
DEFAULT=CHB_PA_R50_EN0
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_PA_BYPASS_RB
POSITION=6
DEFAULT=CHB_PA_BYPASS
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_PA_PD_RB
POSITION=5
DEFAULT=CHB_PA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_MIXB_LOBUFF_PD_RB
POSITION=4
DEFAULT=CHB_MIXB_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_MIXB_BIAS_PD_RB
POSITION=3
DEFAULT=CHB_MIXB_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_MIXA_LOBUFF_PD_RB
POSITION=2
DEFAULT=CHB_MIXA_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_MIXA_BIAS_PD_RB
POSITION=1
DEFAULT=CHB_MIXA_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_LNA_PD_RB
POSITION=0
DEFAULT=CHB_LNA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHB_LNA_CTRL_RB 0x103E
BITFIELD CHB_LNA_ICT_LIN_RB<4:0>
POSITION=<15:11>
DEFAULT=CHB_LNA_ICT_LIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_LNA_ICT_MAIN_RB<4:0>
POSITION=<10:6>
DEFAULT=CHB_LNA_ICT_MAIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_LNA_CGSCTRL_RB<1:0>
POSITION=<5:4>
DEFAULT=CHB_LNA_CGSCTRL<1:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_LNA_GCTRL_RB<3:0>
POSITION=<3:0>
DEFAULT=CHB_LNA_GCTRL<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHB_PA_CTRL_RB 0x103F
BITFIELD CHB_PA_LIN_LOSS_RB<3:0>
POSITION=<7:4>
DEFAULT=CHB_PA_LIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHB_PA_MAIN_LOSS_RB<3:0>
POSITION=<3:0>
DEFAULT=CHB_PA_MAIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHC_MIX_ICT 0x1040
BITFIELD CHC_MIXB_ICT<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHC_MIXB_ICT/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_MIXA_ICT<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHC_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHC_HFPAD_ICT 0x1041
BITFIELD CHC_PA_ILIN2X
POSITION=10
DEFAULT=0
MODE=RW
#! Double the linearization bias current
#! 0 - Ilin * 1
#! 1 - Ilin * 2
#! Default : 0
ENDBITFIELD
BITFIELD CHC_PA_ICT_LIN<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of linearization section of HFPAD
#! I = Inom * CHC_PA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_PA_ICT_MAIN<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of main gm section of HFPAD
#! I = Inom * CHC_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD0 0x1044
BITFIELD CHC_PA_R50_EN0
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHC_PA_BYPASS0
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHC_PA_PD0
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_LOBUFF_PD0
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_BIAS_PD0
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_LOBUFF_PD0
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_LNA_PD0
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD1 0x1045
BITFIELD CHC_PA_R50_EN1
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHC_PA_BYPASS1
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHC_PA_PD1
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_LOBUFF_PD1
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_BIAS_PD1
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_LOBUFF_PD1
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_LNA_PD1
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD2 0x1046
BITFIELD CHC_PA_R50_EN2
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHC_PA_BYPASS2
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHC_PA_PD2
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_LOBUFF_PD2
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_BIAS_PD2
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_LOBUFF_PD2
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_LNA_PD2
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD3 0x1047
BITFIELD CHC_PA_R50_EN3
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHC_PA_BYPASS3
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHC_PA_PD3
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_LOBUFF_PD3
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXB_BIAS_PD3
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_LOBUFF_PD3
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_MIXA_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHC_LNA_PD3
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_CTRL0 0x1048
BITFIELD CHC_LNA_ICT_LIN0<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHC_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_ICT_MAIN0<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHC_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_CGSCTRL0<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_GCTRL0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_CTRL1 0x1049
BITFIELD CHC_LNA_ICT_LIN1<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHC_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_ICT_MAIN1<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHC_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_CGSCTRL1<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_GCTRL1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_CTRL2 0x104A
BITFIELD CHC_LNA_ICT_LIN2<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHC_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_ICT_MAIN2<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHC_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_CGSCTRL2<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_GCTRL2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_CTRL3 0x104B
BITFIELD CHC_LNA_ICT_LIN3<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHC_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_ICT_MAIN3<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHC_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHC_LNA_CGSCTRL3<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_GCTRL3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_CTRL0 0x104C
BITFIELD CHC_PA_LIN_LOSS0<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHC_PA_MAIN_LOSS0<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_CTRL1 0x104D
BITFIELD CHC_PA_LIN_LOSS1<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHC_PA_MAIN_LOSS1<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_CTRL2 0x104E
BITFIELD CHC_PA_LIN_LOSS2<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHC_PA_MAIN_LOSS2<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_CTRL3 0x104F
BITFIELD CHC_PA_LIN_LOSS3<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHC_PA_MAIN_LOSS3<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD_SEL0 0x1050
BITFIELD CHC_PD_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PD_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PD_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD_SEL1 0x1051
BITFIELD CHC_PD_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PD_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PD_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_SEL0 0x1052
BITFIELD CHC_LNA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_SEL1 0x1053
BITFIELD CHC_LNA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_SEL0 0x1054
BITFIELD CHC_PA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_SEL1 0x1055
BITFIELD CHC_PA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_INT_SEL 0x1056
BITFIELD CHC_PA_INT_SEL<1:0>
POSITION=<5:4>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHC_LNA_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHC_PD_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PD_RB 0x105D
BITFIELD CHC_PA_R50_EN_RB
POSITION=7
DEFAULT=CHC_PA_R50_EN0
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_PA_BYPASS_RB
POSITION=6
DEFAULT=CHC_PA_BYPASS
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_PA_PD_RB
POSITION=5
DEFAULT=CHC_PA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_MIXB_LOBUFF_PD_RB
POSITION=4
DEFAULT=CHC_MIXB_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_MIXB_BIAS_PD_RB
POSITION=3
DEFAULT=CHC_MIXB_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_MIXA_LOBUFF_PD_RB
POSITION=2
DEFAULT=CHC_MIXA_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_MIXA_BIAS_PD_RB
POSITION=1
DEFAULT=CHC_MIXA_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_LNA_PD_RB
POSITION=0
DEFAULT=CHC_LNA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHC_LNA_CTRL_RB 0x105E
BITFIELD CHC_LNA_ICT_LIN_RB<4:0>
POSITION=<15:11>
DEFAULT=CHC_LNA_ICT_LIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_LNA_ICT_MAIN_RB<4:0>
POSITION=<10:6>
DEFAULT=CHC_LNA_ICT_MAIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_LNA_CGSCTRL_RB<1:0>
POSITION=<5:4>
DEFAULT=CHC_LNA_CGSCTRL<1:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_LNA_GCTRL_RB<3:0>
POSITION=<3:0>
DEFAULT=CHC_LNA_GCTRL<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHC_PA_CTRL_RB 0x105F
BITFIELD CHC_PA_LIN_LOSS_RB<3:0>
POSITION=<7:4>
DEFAULT=CHC_PA_LIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHC_PA_MAIN_LOSS_RB<3:0>
POSITION=<3:0>
DEFAULT=CHC_PA_MAIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHD_MIX_ICT 0x1060
BITFIELD CHD_MIXB_ICT<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHD_MIXB_ICT/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_MIXA_ICT<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of polarization circuit
#! I = Inom * CHD_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHD_HFPAD_ICT 0x1061
BITFIELD CHD_PA_ILIN2X
POSITION=10
DEFAULT=0
MODE=RW
#! Double the linearization bias current
#! 0 - Ilin * 1
#! 1 - Ilin * 2
#! Default : 0
ENDBITFIELD
BITFIELD CHD_PA_ICT_LIN<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
#! Controls the bias current of linearization section of HFPAD
#! I = Inom * CHD_PA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_PA_ICT_MAIN<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
#! Controls the bias current of main gm section of HFPAD
#! I = Inom * CHD_MIXA_ICT/16
#! Default : 16
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD0 0x1064
BITFIELD CHD_PA_R50_EN0
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHD_PA_BYPASS0
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHD_PA_PD0
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_LOBUFF_PD0
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_BIAS_PD0
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_LOBUFF_PD0
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_LNA_PD0
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD1 0x1065
BITFIELD CHD_PA_R50_EN1
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHD_PA_BYPASS1
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHD_PA_PD1
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_LOBUFF_PD1
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_BIAS_PD1
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_LOBUFF_PD1
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_LNA_PD1
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD2 0x1066
BITFIELD CHD_PA_R50_EN2
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHD_PA_BYPASS2
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHD_PA_PD2
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_LOBUFF_PD2
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_BIAS_PD2
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_LOBUFF_PD2
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_LNA_PD2
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD3 0x1067
BITFIELD CHD_PA_R50_EN3
POSITION=7
DEFAULT=1
MODE=RWI
#! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.
#! 0 - Switch is open
#! 1 - Switch is closed
ENDBITFIELD
BITFIELD CHD_PA_BYPASS3
POSITION=6
DEFAULT=0
MODE=RWI
#! Controls the HFPAD bypass switches.
#! 0 - HFPAD in not bypassed
#! 1 - HFPAD is bypassed
#! Note : HFPAD must be manually disabled when bypassed.
ENDBITFIELD
BITFIELD CHD_PA_PD3
POSITION=5
DEFAULT=1
MODE=RWI
#! Power down for HFPAD
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_LOBUFF_PD3
POSITION=4
DEFAULT=1
MODE=RWI
#! Power down for MIXB LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXB_BIAS_PD3
POSITION=3
DEFAULT=1
MODE=RWI
#! Power down for MIXB bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_LOBUFF_PD3
POSITION=2
DEFAULT=1
MODE=RWI
#! Power down for MIXA LO buffer
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_MIXA_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
#! Power down for MIXA bias
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
BITFIELD CHD_LNA_PD3
POSITION=0
DEFAULT=1
MODE=RWI
#! Power down for LNA
#! 0 - Enabled
#! 1 - Powered down
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_CTRL0 0x1068
BITFIELD CHD_LNA_ICT_LIN0<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHD_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_ICT_MAIN0<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHD_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_CGSCTRL0<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_GCTRL0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_CTRL1 0x1069
BITFIELD CHD_LNA_ICT_LIN1<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHD_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_ICT_MAIN1<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHD_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_CGSCTRL1<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_GCTRL1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_CTRL2 0x106A
BITFIELD CHD_LNA_ICT_LIN2<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHD_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_ICT_MAIN2<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHD_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_CGSCTRL2<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_GCTRL2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_CTRL3 0x106B
BITFIELD CHD_LNA_ICT_LIN3<4:0>
POSITION=<15:11>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of linearization section of LNA
#! I = Inom * CHD_LNA_ICT_LIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_ICT_MAIN3<4:0>
POSITION=<10:6>
DEFAULT=10000
MODE=RWI
#! Controls the bias current of main gm section of LNA
#! I = Inom * CHD_LNA_ICT_MAIN/16
#! Default : 16
ENDBITFIELD
BITFIELD CHD_LNA_CGSCTRL3<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_GCTRL3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_CTRL0 0x106C
BITFIELD CHD_PA_LIN_LOSS0<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHD_PA_MAIN_LOSS0<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_CTRL1 0x106D
BITFIELD CHD_PA_LIN_LOSS1<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHD_PA_MAIN_LOSS1<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_CTRL2 0x106E
BITFIELD CHD_PA_LIN_LOSS2<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHD_PA_MAIN_LOSS2<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_CTRL3 0x106F
BITFIELD CHD_PA_LIN_LOSS3<3:0>
POSITION=<7:4>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD linearizing section
#! Pout = Pout_max - Loss
ENDBITFIELD
BITFIELD CHD_PA_MAIN_LOSS3<3:0>
POSITION=<3:0>
DEFAULT=0000
MODE=RWI
#! Controls the gain of HFPAD main section
#! Pout = Pout_max - Loss
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD_SEL0 0x1070
BITFIELD CHD_PD_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PD_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PD_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD_SEL1 0x1071
BITFIELD CHD_PD_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PD_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PD_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_SEL0 0x1072
BITFIELD CHD_LNA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_SEL1 0x1073
BITFIELD CHD_LNA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_SEL0 0x1074
BITFIELD CHD_PA_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PA_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PA_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_SEL1 0x1075
BITFIELD CHD_PA_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PA_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PA_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_INT_SEL 0x1076
BITFIELD CHD_PA_INT_SEL<1:0>
POSITION=<5:4>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHD_LNA_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD CHD_PD_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PD_RB 0x107D
BITFIELD CHD_PA_R50_EN_RB
POSITION=7
DEFAULT=CHD_PA_R50_EN0
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_PA_BYPASS_RB
POSITION=6
DEFAULT=CHD_PA_BYPASS
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_PA_PD_RB
POSITION=5
DEFAULT=CHD_PA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_MIXB_LOBUFF_PD_RB
POSITION=4
DEFAULT=CHD_MIXB_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_MIXB_BIAS_PD_RB
POSITION=3
DEFAULT=CHD_MIXB_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_MIXA_LOBUFF_PD_RB
POSITION=2
DEFAULT=CHD_MIXA_LOBUFF_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_MIXA_BIAS_PD_RB
POSITION=1
DEFAULT=CHD_MIXA_BIAS_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_LNA_PD_RB
POSITION=0
DEFAULT=CHD_LNA_PD
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHD_LNA_CTRL_RB 0x107E
BITFIELD CHD_LNA_ICT_LIN_RB<4:0>
POSITION=<15:11>
DEFAULT=CHD_LNA_ICT_LIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_LNA_ICT_MAIN_RB<4:0>
POSITION=<10:6>
DEFAULT=CHD_LNA_ICT_MAIN<4:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_LNA_CGSCTRL_RB<1:0>
POSITION=<5:4>
DEFAULT=CHD_LNA_CGSCTRL<1:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_LNA_GCTRL_RB<3:0>
POSITION=<3:0>
DEFAULT=CHD_LNA_GCTRL<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER CHD_PA_CTRL_RB 0x107F
BITFIELD CHD_PA_LIN_LOSS_RB<3:0>
POSITION=<7:4>
DEFAULT=CHD_PA_LIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
BITFIELD CHD_PA_MAIN_LOSS_RB<3:0>
POSITION=<3:0>
DEFAULT=CHD_PA_MAIN_LOSS<3:0>
MODE=RB
#! Readback the actual controlling value
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONFIG0 0x2000
BITFIELD HLMIXA_VGCAS0<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_ICT_BIAS0<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOBUF_PD0
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONFIG1 0x2001
BITFIELD HLMIXA_VGCAS1<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_ICT_BIAS1<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOBUF_PD1
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONFIG2 0x2002
BITFIELD HLMIXA_VGCAS2<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_ICT_BIAS2<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOBUF_PD2
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONFIG3 0x2003
BITFIELD HLMIXA_VGCAS3<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_ICT_BIAS3<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOBUF_PD3
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS0 0x2004
BITFIELD HLMIXA_MIXLOSS0<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_MIXLOSS_FINE0<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS1 0x2005
BITFIELD HLMIXA_MIXLOSS1<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_MIXLOSS_FINE1<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS2 0x2006
BITFIELD HLMIXA_MIXLOSS2<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_MIXLOSS_FINE2<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS3 0x2007
BITFIELD HLMIXA_MIXLOSS3<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_MIXLOSS_FINE3<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONF_SEL0 0x2008
BITFIELD HLMIXA_CONF_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_CONF_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_CONF_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONF_SEL1 0x2009
BITFIELD HLMIXA_CONF_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_CONF_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_CONF_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS_SEL0 0x200A
BITFIELD HLMIXA_LOSS_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOSS_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOSS_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS_SEL1 0x200B
BITFIELD HLMIXA_LOSS_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOSS_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_LOSS_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_INT_SEL 0x200C
BITFIELD HLMIXA_LOSS_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXA_CONF_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_CONFIG_RB 0x200E
BITFIELD HLMIXA_VGCAS_RB<6:0>
POSITION=<13:7>
DEFAULT=HLMIXA_VGCAS<6:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXA_ICT_BIAS_RB<4:0>
POSITION=<6:2>
DEFAULT=HLMIXA_ICT_BIAS<4:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXA_BIAS_PD_RB
POSITION=1
DEFAULT=HLMIXA_BIAS_PD
MODE=RB
ENDBITFIELD
BITFIELD HLMIXA_LOBUF_PD_RB
POSITION=0
DEFAULT=HLMIXA_LOBUF_PD
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXA_LOSS_RB 0x200F
BITFIELD HLMIXA_MIXLOSS_RB<3:0>
POSITION=<5:2>
DEFAULT=HLMIXA_MIXLOSS<3:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXA_MIXLOSS_FINE_RB<1:0>
POSITION=<1:0>
DEFAULT=HLMIXA_MIXLOSS_FINE<1:0>
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONFIG0 0x2010
BITFIELD HLMIXB_VGCAS0<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_ICT_BIAS0<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOBUF_PD0
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONFIG1 0x2011
BITFIELD HLMIXB_VGCAS1<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_ICT_BIAS1<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOBUF_PD1
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONFIG2 0x2012
BITFIELD HLMIXB_VGCAS2<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_ICT_BIAS2<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOBUF_PD2
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONFIG3 0x2013
BITFIELD HLMIXB_VGCAS3<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_ICT_BIAS3<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOBUF_PD3
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS0 0x2014
BITFIELD HLMIXB_MIXLOSS0<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_MIXLOSS_FINE0<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS1 0x2015
BITFIELD HLMIXB_MIXLOSS1<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_MIXLOSS_FINE1<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS2 0x2016
BITFIELD HLMIXB_MIXLOSS2<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_MIXLOSS_FINE2<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS3 0x2017
BITFIELD HLMIXB_MIXLOSS3<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_MIXLOSS_FINE3<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONF_SEL0 0x2018
BITFIELD HLMIXB_CONF_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_CONF_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_CONF_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONF_SEL1 0x2019
BITFIELD HLMIXB_CONF_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_CONF_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_CONF_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS_SEL0 0x201A
BITFIELD HLMIXB_LOSS_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOSS_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOSS_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS_SEL1 0x201B
BITFIELD HLMIXB_LOSS_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOSS_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_LOSS_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_INT_SEL 0x201C
BITFIELD HLMIXB_LOSS_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXB_CONF_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_CONFIG_RB 0x201E
BITFIELD HLMIXB_VGCAS_RB<6:0>
POSITION=<13:7>
DEFAULT=HLMIXB_VGCAS<6:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXB_ICT_BIAS_RB<4:0>
POSITION=<6:2>
DEFAULT=HLMIXB_ICT_BIAS<4:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXB_BIAS_PD_RB
POSITION=1
DEFAULT=HLMIXB_BIAS_PD
MODE=RB
ENDBITFIELD
BITFIELD HLMIXB_LOBUF_PD_RB
POSITION=0
DEFAULT=HLMIXB_LOBUF_PD
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXB_LOSS_RB 0x201F
BITFIELD HLMIXB_MIXLOSS_RB<3:0>
POSITION=<5:2>
DEFAULT=HLMIXB_MIXLOSS<3:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXB_MIXLOSS_FINE_RB<1:0>
POSITION=<1:0>
DEFAULT=HLMIXB_MIXLOSS_FINE<1:0>
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONFIG0 0x2020
BITFIELD HLMIXC_VGCAS0<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_ICT_BIAS0<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOBUF_PD0
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONFIG1 0x2021
BITFIELD HLMIXC_VGCAS1<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_ICT_BIAS1<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOBUF_PD1
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONFIG2 0x2022
BITFIELD HLMIXC_VGCAS2<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_ICT_BIAS2<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOBUF_PD2
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONFIG3 0x2023
BITFIELD HLMIXC_VGCAS3<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_ICT_BIAS3<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOBUF_PD3
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS0 0x2024
BITFIELD HLMIXC_MIXLOSS0<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_MIXLOSS_FINE0<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS1 0x2025
BITFIELD HLMIXC_MIXLOSS1<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_MIXLOSS_FINE1<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS2 0x2026
BITFIELD HLMIXC_MIXLOSS2<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_MIXLOSS_FINE2<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS3 0x2027
BITFIELD HLMIXC_MIXLOSS3<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_MIXLOSS_FINE3<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONF_SEL0 0x2028
BITFIELD HLMIXC_CONF_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_CONF_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_CONF_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONF_SEL1 0x2029
BITFIELD HLMIXC_CONF_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_CONF_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_CONF_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS_SEL0 0x202A
BITFIELD HLMIXC_LOSS_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOSS_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOSS_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS_SEL1 0x202B
BITFIELD HLMIXC_LOSS_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOSS_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_LOSS_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_INT_SEL 0x202C
BITFIELD HLMIXC_LOSS_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXC_CONF_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_CONFIG_RB 0x202E
BITFIELD HLMIXC_VGCAS_RB<6:0>
POSITION=<13:7>
DEFAULT=HLMIXC_VGCAS<6:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXC_ICT_BIAS_RB<4:0>
POSITION=<6:2>
DEFAULT=HLMIXC_ICT_BIAS<4:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXC_BIAS_PD_RB
POSITION=1
DEFAULT=HLMIXC_BIAS_PD
MODE=RB
ENDBITFIELD
BITFIELD HLMIXC_LOBUF_PD_RB
POSITION=0
DEFAULT=HLMIXC_LOBUF_PD
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXC_LOSS_RB 0x202F
BITFIELD HLMIXC_MIXLOSS_RB<3:0>
POSITION=<5:2>
DEFAULT=HLMIXC_MIXLOSS<3:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXC_MIXLOSS_FINE_RB<1:0>
POSITION=<1:0>
DEFAULT=HLMIXC_MIXLOSS_FINE<1:0>
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONFIG0 0x2030
BITFIELD HLMIXD_VGCAS0<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_ICT_BIAS0<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_BIAS_PD0
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOBUF_PD0
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONFIG1 0x2031
BITFIELD HLMIXD_VGCAS1<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_ICT_BIAS1<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_BIAS_PD1
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOBUF_PD1
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONFIG2 0x2032
BITFIELD HLMIXD_VGCAS2<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_ICT_BIAS2<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_BIAS_PD2
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOBUF_PD2
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONFIG3 0x2033
BITFIELD HLMIXD_VGCAS3<6:0>
POSITION=<13:7>
DEFAULT=1000000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_ICT_BIAS3<4:0>
POSITION=<6:2>
DEFAULT=10000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_BIAS_PD3
POSITION=1
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOBUF_PD3
POSITION=0
DEFAULT=1
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS0 0x2034
BITFIELD HLMIXD_MIXLOSS0<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_MIXLOSS_FINE0<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS1 0x2035
BITFIELD HLMIXD_MIXLOSS1<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_MIXLOSS_FINE1<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS2 0x2036
BITFIELD HLMIXD_MIXLOSS2<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_MIXLOSS_FINE2<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS3 0x2037
BITFIELD HLMIXD_MIXLOSS3<3:0>
POSITION=<5:2>
DEFAULT=0000
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_MIXLOSS_FINE3<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONF_SEL0 0x2038
BITFIELD HLMIXD_CONF_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_CONF_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_CONF_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONF_SEL1 0x2039
BITFIELD HLMIXD_CONF_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_CONF_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_CONF_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS_SEL0 0x203A
BITFIELD HLMIXD_LOSS_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOSS_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOSS_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS_SEL1 0x203B
BITFIELD HLMIXD_LOSS_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOSS_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_LOSS_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_INT_SEL 0x203C
BITFIELD HLMIXD_LOSS_INT_SEL<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
ENDBITFIELD
BITFIELD HLMIXD_CONF_INT_SEL<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_CONFIG_RB 0x203E
BITFIELD HLMIXD_VGCAS_RB<6:0>
POSITION=<13:7>
DEFAULT=HLMIXD_VGCAS<6:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXD_ICT_BIAS_RB<4:0>
POSITION=<6:2>
DEFAULT=HLMIXD_ICT_BIAS<4:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXD_BIAS_PD_RB
POSITION=1
DEFAULT=HLMIXD_BIAS_PD
MODE=RB
ENDBITFIELD
BITFIELD HLMIXD_LOBUF_PD_RB
POSITION=0
DEFAULT=HLMIXD_LOBUF_PD
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER HLMIXD_LOSS_RB 0x203F
BITFIELD HLMIXD_MIXLOSS_RB<3:0>
POSITION=<5:2>
DEFAULT=HLMIXD_MIXLOSS<3:0>
MODE=RB
ENDBITFIELD
BITFIELD HLMIXD_MIXLOSS_FINE_RB<1:0>
POSITION=<1:0>
DEFAULT=HLMIXD_MIXLOSS_FINE<1:0>
MODE=RB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VREG 0x4000
BITFIELD EN_VCOBIAS
POSITION=11
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD BYP_VCOREG
POSITION=10
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD CURLIM_VCOREG
POSITION=9
DEFAULT=1
MODE=RW
ENDBITFIELD
BITFIELD SPDUP_VCOREG
POSITION=8
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD VDIV_VCOREG<7:0>
POSITION=<7:0>
DEFAULT=00010000
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CFG_XBUF 0x4001
BITFIELD PLL_XBUF_SLFBEN
POSITION=2
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD PLL_XBUF_BYPEN
POSITION=1
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD PLL_XBUF_EN
POSITION=0
DEFAULT=0
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CAL_AUTO0 0x4002
BITFIELD FCAL_START
POSITION=12
DEFAULT=0
MODE=STICKYBIT
ENDBITFIELD
BITFIELD VCO_SEL_FINAL_VAL
POSITION=11
DEFAULT=0
MODE=R
ENDBITFIELD
BITFIELD VCO_SEL_FINAL<1:0>
POSITION=<10:9>
DEFAULT=00
MODE=R
ENDBITFIELD
BITFIELD FREQ_FINAL_VAL
POSITION=8
DEFAULT=0
MODE=R
ENDBITFIELD
BITFIELD FREQ_FINAL<7:0>
POSITION=<7:0>
DEFAULT=00000000
MODE=R
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CAL_AUTO1 0x4003
BITFIELD VCO_SEL_FORCE
POSITION=13
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD VCO_SEL_INIT<1:0>
POSITION=<12:11>
DEFAULT=10
MODE=RW
ENDBITFIELD
BITFIELD FREQ_INIT_POS<2:0>
POSITION=<10:8>
DEFAULT=111
MODE=RW
ENDBITFIELD
BITFIELD FREQ_INIT<7:0>
POSITION=<7:0>
DEFAULT=00000000
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CAL_AUTO2 0x4004
BITFIELD FREQ_SETTLING_N<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RW
ENDBITFIELD
BITFIELD VTUNE_WAIT_N<7:0>
POSITION=<7:0>
DEFAULT=01000000
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CAL_AUTO3 0x4005
BITFIELD VCO_SEL_FREQ_MAX<7:0>
POSITION=<15:8>
DEFAULT=11111010
MODE=RW
ENDBITFIELD
BITFIELD VCO_SEL_FREQ_MIN<7:0>
POSITION=<7:0>
DEFAULT=00000101
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CAL_MAN 0x4006
BITFIELD VCO_FREQ_MAN<7:0>
POSITION=<15:8>
DEFAULT=10000000
MODE=RW
ENDBITFIELD
BITFIELD VCO_SEL_MAN<1:0>
POSITION=<7:6>
DEFAULT=10
MODE=RW
ENDBITFIELD
BITFIELD FREQ_HIGH
POSITION=5
DEFAULT=0
MODE=R
ENDBITFIELD
BITFIELD FREQ_EQUAL
POSITION=4
DEFAULT=0
MODE=R
ENDBITFIELD
BITFIELD FREQ_LOW
POSITION=3
DEFAULT=0
MODE=R
ENDBITFIELD
BITFIELD CTUNE_STEP_DONE
POSITION=2
DEFAULT=0
MODE=R
ENDBITFIELD
BITFIELD CTUNE_START
POSITION=1
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD CTUNE_EN
POSITION=0
DEFAULT=0
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CFG_SEL0 0x4008
BITFIELD PLL_CFG_SEL0_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD PLL_CFG_SEL0_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD PLL_CFG_SEL0_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CFG_SEL1 0x4009
BITFIELD PLL_CFG_SEL1_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD PLL_CFG_SEL1_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD PLL_CFG_SEL1_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CFG_SEL2 0x400A
BITFIELD PLL_CFG_SEL2_INTERNAL
POSITION=11
DEFAULT=1
MODE=RWI
ENDBITFIELD
BITFIELD PLL_CFG_SEL2_INVERT
POSITION=10
DEFAULT=0
MODE=RWI
ENDBITFIELD
BITFIELD PLL_CFG_SEL2_MASK<8:0>
POSITION=<8:0>
DEFAULT=000000000
MODE=RWI
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CFG 0x400B
BITFIELD PLL_RSTN
POSITION=9
DEFAULT=0
MODE=RW
#! PLL reset, active low.
ENDBITFIELD
BITFIELD CTUNE_RES<1:0>
POSITION=<8:7>
DEFAULT=01
MODE=RW
#! PLL capacitor bank tuning resolution.
ENDBITFIELD
BITFIELD PLL_CALIBRATION_MODE
POSITION=6
DEFAULT=0
MODE=RW
#! PLL calibration mode.
#! 0 - Automatic calibration (default)
#! 1 - Manual calibration
ENDBITFIELD
BITFIELD PLL_CALIBRATION_EN
POSITION=5
DEFAULT=0
MODE=RW
#! Activate PLL calibration.
#! 0 - Normal mode (default)
#! 1 - Calibration mode
ENDBITFIELD
BITFIELD PLL_FLOCK_INTERNAL
POSITION=4
DEFAULT=0
MODE=RWI
#! Fast lock control.
#! 0 - Normal operation. Fast lock select signal comes from fast lock state machine. (default)
#! 1 - Debug mode. Fast lock select signal is forced by PLL_FLOCK_INTVAL
ENDBITFIELD
BITFIELD PLL_FLOCK_INTVAL
POSITION=3
DEFAULT=0
MODE=RWI
#! Fast lock control internal select value.
ENDBITFIELD
BITFIELD PLL_CFG_INT_SEL<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! Internal PLL profile control.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CFG_STATUS 0x400C
BITFIELD VTUNE_HIGH
POSITION=2
DEFAULT=0
MODE=R
#! Tuning voltage high.
ENDBITFIELD
BITFIELD VTUNE_LOW
POSITION=1
DEFAULT=0
MODE=R
#! Tuning voltage low.
ENDBITFIELD
BITFIELD PLL_LOCK
POSITION=0
DEFAULT=0
MODE=R
#! PLL lock detect.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG1 0x400E
BITFIELD SEL_BIAS_CORE
POSITION=10
DEFAULT=0
MODE=RW
ENDBITFIELD
BITFIELD PLL_LODIST_ICT_CORE<4:0>
POSITION=<9:5>
DEFAULT=10000
MODE=RW
ENDBITFIELD
BITFIELD PLL_LODIST_ICT_BUF<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG2 0x400F
BITFIELD PLL_ICT_OUT3<1:0>
POSITION=<7:6>
DEFAULT=10
MODE=RW
ENDBITFIELD
BITFIELD PLL_ICT_OUT2<1:0>
POSITION=<5:4>
DEFAULT=10
MODE=RW
ENDBITFIELD
BITFIELD PLL_ICT_OUT1<1:0>
POSITION=<3:2>
DEFAULT=10
MODE=RW
ENDBITFIELD
BITFIELD PLL_ICT_OUT0<1:0>
POSITION=<1:0>
DEFAULT=10
MODE=RW
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_BIST1 0x4010
BITFIELD BSIGL<6:0>
POSITION=<15:9>
DEFAULT=0000000
MODE=RI
#! BIST signature. Read only.
ENDBITFIELD
BITFIELD BSTATE
POSITION=8
DEFAULT=0
MODE=RI
#! BIST state indicator
#! 0 - BIST not running (default)
#! 1 - BIST running
ENDBITFIELD
BITFIELD EN_SDM_TSTO
POSITION=4
DEFAULT=0
MODE=RW
#! Enable test buffer output
ENDBITFIELD
BITFIELD BEN
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable BIST
ENDBITFIELD
BITFIELD BSTART
POSITION=0
DEFAULT=0
MODE=RWI
#! Starts BIST
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_BIST2 0x4011
BITFIELD BSIGH<15:0>
POSITION=<15:0>
DEFAULT=0000000000000000
MODE=RI
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_0 0x4100
BITFIELD PLL_LODIST_EN_BIAS_0
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_0
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_0
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_0
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_0
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_0
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_0
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_0
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_0
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_0
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_0
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_0
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_0
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_0 0x4101
BITFIELD R3_0<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_0<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_0<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_0 0x4102
BITFIELD VTUNE_VCT_0<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_0
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_0 0x4103
BITFIELD FLIP_0
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_0<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_0<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_0<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_0 0x4104
BITFIELD LD_VCT_0<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_0<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_0 0x4105
BITFIELD VCO_FREQ_0<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_0 0x4106
BITFIELD SPDUP_VCO_0
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_0
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_0<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_0<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_0<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_0 0x4107
BITFIELD FFDIV_SEL_0
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_0<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_0<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_0 0x4108
BITFIELD INTMOD_EN_0
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_0
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_0
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_0
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_0<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_0 0x4109
BITFIELD FRACMODL_0<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_0 0x410A
BITFIELD FRACMODH_0<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_0 0x410B
BITFIELD PLL_LODIST_EN_OUT_0<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_0<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_0<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_0<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_0<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_0 0x410C
BITFIELD FLOCK_R3_0<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_0<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_0<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_0<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_0 0x410D
BITFIELD FLOCK_C3_0<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_0<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_0<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_0 0x410E
BITFIELD FLOCK_LODIST_EN_OUT_0<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_0
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_0<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_1 0x4110
BITFIELD PLL_LODIST_EN_BIAS_1
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_1
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_1
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_1
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_1
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_1
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_1
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_1
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_1
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_1
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_1
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_1
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_1
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_1 0x4111
BITFIELD R3_1<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_1<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_1<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_1 0x4112
BITFIELD VTUNE_VCT_1<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_1
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_1 0x4113
BITFIELD FLIP_1
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_1<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_1<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_1<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_1 0x4114
BITFIELD LD_VCT_1<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_1<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_1 0x4115
BITFIELD VCO_FREQ_1<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_1 0x4116
BITFIELD SPDUP_VCO_1
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_1
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_1<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_1<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_1<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_1 0x4117
BITFIELD FFDIV_SEL_1
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_1<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_1<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_1 0x4118
BITFIELD INTMOD_EN_1
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_1
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_1
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_1
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_1<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_1 0x4119
BITFIELD FRACMODL_1<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_1 0x411A
BITFIELD FRACMODH_1<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_1 0x411B
BITFIELD PLL_LODIST_EN_OUT_1<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_1<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_1<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_1<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_1<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_1 0x411C
BITFIELD FLOCK_R3_1<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_1<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_1<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_1<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_1 0x411D
BITFIELD FLOCK_C3_1<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_1<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_1<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_1 0x411E
BITFIELD FLOCK_LODIST_EN_OUT_1<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_1
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_1<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_2 0x4120
BITFIELD PLL_LODIST_EN_BIAS_2
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_2
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_2
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_2
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_2
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_2
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_2
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_2
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_2
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_2
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_2
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_2
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_2
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_2 0x4121
BITFIELD R3_2<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_2<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_2<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_2 0x4122
BITFIELD VTUNE_VCT_2<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_2
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_2 0x4123
BITFIELD FLIP_2
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_2<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_2<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_2<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_2 0x4124
BITFIELD LD_VCT_2<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_2<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_2 0x4125
BITFIELD VCO_FREQ_2<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_2 0x4126
BITFIELD SPDUP_VCO_2
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_2
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_2<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_2<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_2<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_2 0x4127
BITFIELD FFDIV_SEL_2
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_2<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_2<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_2 0x4128
BITFIELD INTMOD_EN_2
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_2
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_2
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_2
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_2<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_2 0x4129
BITFIELD FRACMODL_2<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_2 0x412A
BITFIELD FRACMODH_2<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_2 0x412B
BITFIELD PLL_LODIST_EN_OUT_2<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_2<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_2<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_2<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_2<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_2 0x412C
BITFIELD FLOCK_R3_2<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_2<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_2<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_2<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_2 0x412D
BITFIELD FLOCK_C3_2<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_2<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_2<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_2 0x412E
BITFIELD FLOCK_LODIST_EN_OUT_2<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_2
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_2<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_3 0x4130
BITFIELD PLL_LODIST_EN_BIAS_3
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_3
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_3
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_3
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_3
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_3
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_3
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_3
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_3
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_3
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_3
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_3
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_3
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_3 0x4131
BITFIELD R3_3<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_3<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_3<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_3 0x4132
BITFIELD VTUNE_VCT_3<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_3
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_3 0x4133
BITFIELD FLIP_3
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_3<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_3<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_3<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_3 0x4134
BITFIELD LD_VCT_3<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_3<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_3 0x4135
BITFIELD VCO_FREQ_3<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_3 0x4136
BITFIELD SPDUP_VCO_3
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_3
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_3<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_3<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_3<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_3 0x4137
BITFIELD FFDIV_SEL_3
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_3<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_3<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_3 0x4138
BITFIELD INTMOD_EN_3
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_3
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_3
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_3
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_3<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_3 0x4139
BITFIELD FRACMODL_3<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_3 0x413A
BITFIELD FRACMODH_3<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_3 0x413B
BITFIELD PLL_LODIST_EN_OUT_3<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_3<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_3<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_3<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_3<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_3 0x413C
BITFIELD FLOCK_R3_3<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_3<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_3<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_3<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_3 0x413D
BITFIELD FLOCK_C3_3<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_3<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_3<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_3 0x413E
BITFIELD FLOCK_LODIST_EN_OUT_3<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_3
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_3<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_4 0x4140
BITFIELD PLL_LODIST_EN_BIAS_4
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_4
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_4
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_4
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_4
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_4
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_4
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_4
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_4
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_4
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_4
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_4
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_4
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_4 0x4141
BITFIELD R3_4<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_4<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_4<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_4<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_4 0x4142
BITFIELD VTUNE_VCT_4<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_4
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_4<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_4 0x4143
BITFIELD FLIP_4
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_4<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_4<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_4<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_4 0x4144
BITFIELD LD_VCT_4<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_4<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_4 0x4145
BITFIELD VCO_FREQ_4<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_4 0x4146
BITFIELD SPDUP_VCO_4
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_4
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_4<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_4<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_4<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_4 0x4147
BITFIELD FFDIV_SEL_4
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_4<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_4<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_4 0x4148
BITFIELD INTMOD_EN_4
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_4
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_4
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_4
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_4<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_4 0x4149
BITFIELD FRACMODL_4<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_4 0x414A
BITFIELD FRACMODH_4<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_4 0x414B
BITFIELD PLL_LODIST_EN_OUT_4<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_4<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_4<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_4<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_4<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_4 0x414C
BITFIELD FLOCK_R3_4<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_4<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_4<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_4<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_4 0x414D
BITFIELD FLOCK_C3_4<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_4<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_4<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_4 0x414E
BITFIELD FLOCK_LODIST_EN_OUT_4<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_4
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_4<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_5 0x4150
BITFIELD PLL_LODIST_EN_BIAS_5
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_5
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_5
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_5
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_5
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_5
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_5
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_5
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_5
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_5
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_5
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_5
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_5
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_5 0x4151
BITFIELD R3_5<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_5<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_5<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_5<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_5 0x4152
BITFIELD VTUNE_VCT_5<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_5
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_5<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_5 0x4153
BITFIELD FLIP_5
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_5<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_5<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_5<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_5 0x4154
BITFIELD LD_VCT_5<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_5<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_5 0x4155
BITFIELD VCO_FREQ_5<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_5 0x4156
BITFIELD SPDUP_VCO_5
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_5
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_5<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_5<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_5<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_5 0x4157
BITFIELD FFDIV_SEL_5
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_5<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_5<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_5 0x4158
BITFIELD INTMOD_EN_5
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_5
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_5
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_5
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_5<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_5 0x4159
BITFIELD FRACMODL_5<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_5 0x415A
BITFIELD FRACMODH_5<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_5 0x415B
BITFIELD PLL_LODIST_EN_OUT_5<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_5<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_5<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_5<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_5<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_5 0x415C
BITFIELD FLOCK_R3_5<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_5<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_5<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_5<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_5 0x415D
BITFIELD FLOCK_C3_5<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_5<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_5<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_5 0x415E
BITFIELD FLOCK_LODIST_EN_OUT_5<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_5
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_5<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_6 0x4160
BITFIELD PLL_LODIST_EN_BIAS_6
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_6
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_6
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_6
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_6
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_6
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_6
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_6
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_6
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_6
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_6
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_6
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_6
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_6 0x4161
BITFIELD R3_6<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_6<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_6<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_6<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_6 0x4162
BITFIELD VTUNE_VCT_6<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_6
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_6<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_6 0x4163
BITFIELD FLIP_6
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_6<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_6<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_6<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_6 0x4164
BITFIELD LD_VCT_6<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_6<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_6 0x4165
BITFIELD VCO_FREQ_6<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_6 0x4166
BITFIELD SPDUP_VCO_6
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_6
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_6<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_6<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_6<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_6 0x4167
BITFIELD FFDIV_SEL_6
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_6<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_6<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_6 0x4168
BITFIELD INTMOD_EN_6
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_6
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_6
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_6
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_6<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_6 0x4169
BITFIELD FRACMODL_6<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_6 0x416A
BITFIELD FRACMODH_6<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_6 0x416B
BITFIELD PLL_LODIST_EN_OUT_6<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_6<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_6<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_6<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_6<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_6 0x416C
BITFIELD FLOCK_R3_6<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_6<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_6<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_6<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_6 0x416D
BITFIELD FLOCK_C3_6<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_6<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_6<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_6 0x416E
BITFIELD FLOCK_LODIST_EN_OUT_6<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_6
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_6<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_ENABLE_7 0x4170
BITFIELD PLL_LODIST_EN_BIAS_7
POSITION=12
DEFAULT=0
MODE=RWI
#! Enable for LO distribution bias.
ENDBITFIELD
BITFIELD PLL_LODIST_EN_DIV2IQ_7
POSITION=11
DEFAULT=0
MODE=RWI
#! Enable for IQ generator in LO distribution.
#! 0 - Clock is not divided by 2
#! 1 - Clock is divided by 2, I and Q are generated
ENDBITFIELD
BITFIELD PLL_EN_VTUNE_COMP_7
POSITION=10
DEFAULT=0
MODE=RWI
#! Enable for tuning voltage comparator in PLL.
ENDBITFIELD
BITFIELD PLL_EN_LD_7
POSITION=9
DEFAULT=0
MODE=RWI
#! Lock detector enable.
ENDBITFIELD
BITFIELD PLL_EN_PFD_7
POSITION=8
DEFAULT=0
MODE=RWI
#! Enable for PFD in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CP_7
POSITION=7
DEFAULT=0
MODE=RWI
#! Enable for charge pump in PLL.
ENDBITFIELD
BITFIELD PLL_EN_CPOFS_7
POSITION=6
DEFAULT=0
MODE=RWI
#! Enable for offset (bleeding) current in charge pump.
ENDBITFIELD
BITFIELD PLL_EN_VCO_7
POSITION=5
DEFAULT=0
MODE=RWI
#! Enable for VCO.
ENDBITFIELD
BITFIELD PLL_EN_FFDIV_7
POSITION=4
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider in PLL.
#! 0 - Output clock is not divided
ENDBITFIELD
BITFIELD PLL_EN_FB_PDIV2_7
POSITION=3
DEFAULT=0
MODE=RWI
#! Enable for feedback pre-divider.
#! 0 - Output clock is directly fed to feedback divider
ENDBITFIELD
BITFIELD PLL_EN_FFCORE_7
POSITION=2
DEFAULT=0
MODE=RWI
#! Enable for feed-forward divider core
ENDBITFIELD
BITFIELD PLL_EN_FBDIV_7
POSITION=1
DEFAULT=0
MODE=RWI
#! Enable for feedback divider core
ENDBITFIELD
BITFIELD PLL_SDM_CLK_EN_7
POSITION=0
DEFAULT=0
MODE=RWI
#! Enable for sigma-delta modulator
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG1_7 0x4171
BITFIELD R3_7<3:0>
POSITION=<15:12>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R3_val = 9 kOhm/R3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD R2_7<3:0>
POSITION=<11:8>
DEFAULT=0001
MODE=RWI
#! Control word for loop filter.
#! R2_val = 15.6 kOhm/R2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C2_7<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Control word for C2 in PLL loop filter.
#! C2_val = 300 pF+7.5 pF * C2<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
BITFIELD C1_7<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C1 in PLL loop filter.
#! C1_val = 1.8 pF*C1<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LPF_CFG2_7 0x4172
BITFIELD VTUNE_VCT_7<1:0>
POSITION=<6:5>
DEFAULT=01
MODE=RWI
#! Tuning voltage control word during coarse tuning (LPFSW=1).
#! 00 - 300 mV,
#! 01 - 600 mV,
#! 10 - 750 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD LPFSW_7
POSITION=4
DEFAULT=0
MODE=RWI
#! Loop filter control.
#! 0 - PLL loop is closed,
#! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.
#! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.
ENDBITFIELD
BITFIELD C3_7<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Control word for C3 in PLL loop filter.
#! C3_val = 3 pF * C3<3:0>
#! When fast lock mode is enabled, this is the final value.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG0_7 0x4173
BITFIELD FLIP_7
POSITION=14
DEFAULT=0
MODE=RWI
#! Flip for PFD inputs
#! 0 - Normal operation,
#! 1 - Inputs are interchanged
ENDBITFIELD
BITFIELD DEL_7<1:0>
POSITION=<13:12>
DEFAULT=00
MODE=RWI
#! Reset path delay
ENDBITFIELD
BITFIELD PULSE_7<5:0>
POSITION=<11:6>
DEFAULT=000100
MODE=RWI
#! Charge pump pulse current
#! I = 25 uA * PULSE<5:0>
ENDBITFIELD
BITFIELD OFS_7<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current
#! I = 6.25 uA * OFS<5:0>
ENDBITFIELD
ENDREGISTER
REGISTER PLL_CP_CFG1_7 0x4174
BITFIELD LD_VCT_7<1:0>
POSITION=<6:5>
DEFAULT=10
MODE=RWI
#! Threshold voltage for lock detector
#! 00 - 600 mV,
#! 01 - 700 mV,
#! 10 - 800 mV,
#! 11 - 900 mV.
ENDBITFIELD
BITFIELD ICT_CP_7<4:0>
POSITION=<4:0>
DEFAULT=10000
MODE=RWI
#! Charge pump bias current.
#! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_FREQ_7 0x4175
BITFIELD VCO_FREQ_7<7:0>
POSITION=<7:0>
DEFAULT=10000000
MODE=RWI
#! VCO cap bank code.
#! 00000000 - lowest frequency
#! 11111111 - highest frequency
ENDBITFIELD
ENDREGISTER
REGISTER PLL_VCO_CFG_7 0x4176
BITFIELD SPDUP_VCO_7
POSITION=12
DEFAULT=0
MODE=RWI
#! Speed-up VCO core by bypassing the noise filter
ENDBITFIELD
BITFIELD VCO_AAC_EN_7
POSITION=11
DEFAULT=1
MODE=RWI
#! Enable for automatic VCO amplitude control.
ENDBITFIELD
BITFIELD VDIV_SWVDD_7<1:0>
POSITION=<10:9>
DEFAULT=10
MODE=RWI
#! Capacitor bank switches bias voltage
#! 00 - 600 mV,
#! 01 - 800 mV,
#! 10 - 1000 mV,
#! 11 - 1200 mV.
ENDBITFIELD
BITFIELD VCO_SEL_7<1:0>
POSITION=<8:7>
DEFAULT=11
MODE=RWI
#! VCO core selection
#! 00 - External VCO,
#! 01 - Low-frequency band VCO (4 - 6 GHz),
#! 10 - Mid-frequency band VCO (6 - 8 GHz),
#! 11 - High-frequency band VCO (8 - 10 GHz).
ENDBITFIELD
BITFIELD VCO_AMP_7<6:0>
POSITION=<6:0>
DEFAULT=0000001
MODE=RWI
#! VCO amplitude control word.
#! 0000000 - minimum amplitude
#! Lowest two bits control the VCO core current.
#! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FF_CFG_7 0x4177
BITFIELD FFDIV_SEL_7
POSITION=4
DEFAULT=0
MODE=RWI
#! Feed-forward divider multiplexer select bit
#! 0 - No division,
#! 1 - Input frequency is divided
ENDBITFIELD
BITFIELD FFCORE_MOD_7<1:0>
POSITION=<3:2>
DEFAULT=00
MODE=RWI
#! Feed-forward divider core modulus
#! 00 - No division
#! 01 - Div by 2
#! 10 - Div by 4
#! 11 - Div by 8
ENDBITFIELD
BITFIELD FF_MOD_7<1:0>
POSITION=<1:0>
DEFAULT=00
MODE=RWI
#! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_SDM_CFG_7 0x4178
BITFIELD INTMOD_EN_7
POSITION=14
DEFAULT=0
MODE=RWI
#! Integer mode enable
ENDBITFIELD
BITFIELD DITHER_EN_7
POSITION=13
DEFAULT=0
MODE=RWI
#! Enable dithering in SDM
#! 0 - Disabled
#! 1 - Enabled
ENDBITFIELD
BITFIELD SEL_SDMCLK_7
POSITION=12
DEFAULT=0
MODE=RWI
#! Selects between the feedback divider output and FREF for SDM
#! 0 - CLK CLK_DIV
#! 1 - CLK CLK_REF
ENDBITFIELD
BITFIELD REV_SDMCLK_7
POSITION=11
DEFAULT=0
MODE=RWI
#! Reverses the SDM clock
#! 0 - Normal
#! 1 - Reversed (after INV)
ENDBITFIELD
BITFIELD INTMOD_7<9:0>
POSITION=<9:0>
DEFAULT=0011011000
MODE=RWI
#! Integer section of division ratio.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODL_7 0x4179
BITFIELD FRACMODL_7<15:0>
POSITION=<15:0>
DEFAULT=0101011100110000
MODE=RWI
#! Fractional control of the division ratio LSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FRACMODH_7 0x417A
BITFIELD FRACMODH_7<3:0>
POSITION=<3:0>
DEFAULT=0101
MODE=RWI
#! Fractional control of the division ratio MSB
ENDBITFIELD
ENDREGISTER
REGISTER PLL_LODIST_CFG_7 0x417B
BITFIELD PLL_LODIST_EN_OUT_7<3:0>
POSITION=<15:12>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals.
#! Each bit is an enable for individual channel.
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT3_7<2:0>
POSITION=<11:9>
DEFAULT=000
MODE=RWI
#! LO distribution channel 3 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT2_7<2:0>
POSITION=<8:6>
DEFAULT=000
MODE=RWI
#! LO distribution channel 2 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT1_7<2:0>
POSITION=<5:3>
DEFAULT=000
MODE=RWI
#! LO distribution channel 1 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
BITFIELD PLL_LODIST_FSP_OUT0_7<2:0>
POSITION=<2:0>
DEFAULT=000
MODE=RWI
#! LO distribution channel 0 frequency, sign and phase control.
#! FSP_OUT<2> - Frequency division control
#! 0 - LO is divided by 2,
#! 1 - LO is not divided.
#! FSP_OUT<1> - LO sign
#! 0 - LO is not inverted
#! 1 - LO is inverted
#! FSP_OUT<0> - LO phase
#! 0 - LO phase 0 deg (I)
#! 1 - LO phase 90 deg (Q)
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG1_7 0x417C
BITFIELD FLOCK_R3_7<3:0>
POSITION=<15:12>
DEFAULT=0100
MODE=RWI
#! Loop filter R3 used during fact lock.
ENDBITFIELD
BITFIELD FLOCK_R2_7<3:0>
POSITION=<11:8>
DEFAULT=0100
MODE=RWI
#! Loop filter R2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C2_7<3:0>
POSITION=<7:4>
DEFAULT=1000
MODE=RWI
#! Loop filter C2 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_C1_7<3:0>
POSITION=<3:0>
DEFAULT=1000
MODE=RWI
#! Loop filter C1 used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG2_7 0x417D
BITFIELD FLOCK_C3_7<3:0>
POSITION=<15:12>
DEFAULT=1000
MODE=RWI
#! Loop filter C3 used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_PULSE_7<5:0>
POSITION=<11:6>
DEFAULT=111111
MODE=RWI
#! Charge pump pulse current used during fast lock.
ENDBITFIELD
BITFIELD FLOCK_OFS_7<5:0>
POSITION=<5:0>
DEFAULT=000000
MODE=RWI
#! Charge pump offset (bleeding) current used during fast lock.
ENDBITFIELD
ENDREGISTER
REGISTER PLL_FLOCK_CFG3_7 0x417E
BITFIELD FLOCK_LODIST_EN_OUT_7<3:0>
POSITION=<14:11>
DEFAULT=0000
MODE=RWI
#! LO distribution enable signals used during fast lock
ENDBITFIELD
BITFIELD FLOCK_VCO_SPDUP_7
POSITION=10
DEFAULT=0
MODE=RWI
#! VCO speedup used during fast lock
ENDBITFIELD
BITFIELD FLOCK_N_7<9:0>
POSITION=<9:0>
DEFAULT=0110010000
MODE=RWI
#! Duration of fast lock in PLL reference frequency clock cycles.
ENDBITFIELD
ENDREGISTER
"""
|
lms8001_regdesc = '\n\nREGBANK ChipConfig 0x000X\nREGBANK BiasLDOConfig 0x001X\nREGBANK Channel_A 0b00010000000XXXXX\nREGBANK Channel_B 0b00010000001XXXXX\nREGBANK Channel_C 0b00010000010XXXXX\nREGBANK Channel_D 0b00010000011XXXXX\nREGBANK HLMIXA 0x200X\nREGBANK HLMIXB 0x201X\nREGBANK HLMIXC 0x202X\nREGBANK HLMIXD 0x203X\nREGBANK PLL_CONFIGURATION 0b01000000000XXXXX\nREGBANK PLL_PROFILE_0 0x410X\nREGBANK PLL_PROFILE_1 0x411X\nREGBANK PLL_PROFILE_2 0x412X\nREGBANK PLL_PROFILE_3 0x413X\nREGBANK PLL_PROFILE_4 0x414X\nREGBANK PLL_PROFILE_5 0x415X\nREGBANK PLL_PROFILE_6 0x416X\nREGBANK PLL_PROFILE_7 0x417X\nREGISTER SPIConfig 0x0000\n BITFIELD SPI_SDIO_DS\n POSITION=6\n DEFAULT=0\n MODE=RW\n #! Driver strength of SPI_SDIO pad.\n #! 0 - Driver strength is 4mA (default)\n #! 1 - Driver strength is 8mA\n ENDBITFIELD\n BITFIELD SPI_SDO_DS\n POSITION=5\n DEFAULT=0\n MODE=RW\n #! Driver strength of SPI_SDO pad.\n #! 0 - Driver strength is 4mA (default)\n #! 1 - Driver strength is 8mA\n ENDBITFIELD\n BITFIELD SPI_SDIO_PE\n POSITION=4\n DEFAULT=1\n MODE=RW\n #! Pull up control of SPI_SDIO pad.\n #! 0 - Pull up disengaged\n #! 1 - Pull up engaged (default)\n ENDBITFIELD\n BITFIELD SPI_SDO_PE\n POSITION=3\n DEFAULT=1\n MODE=RW\n #! Pull up control of SPI_SDO pad.\n #! 0 - Pull up disengaged\n #! 1 - Pull up engaged (default)\n ENDBITFIELD\n BITFIELD SPI_SCLK_PE\n POSITION=2\n DEFAULT=1\n MODE=RW\n #! Pull up control of SPI_SCLK pad.\n #! 0 - Pull up disengaged\n #! 1 - Pull up engaged (default)\n ENDBITFIELD\n BITFIELD SPI_SEN_PE\n POSITION=1\n DEFAULT=1\n MODE=RW\n #! Pull up control of SPI_SEN pad.\n #! 0 - Pull up disengaged\n #! 1 - Pull up engaged (default)\n ENDBITFIELD\n BITFIELD SPIMODE\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! SPI communication mode.\n #! 0 - 3 wire mode\n #! 1 - 4 wire mode (default)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOOutData 0x0004\n BITFIELD GPIO_OUT_SPI<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n #! Output data for GPIO pads from SPI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOOUT_SEL0 0x0005\n BITFIELD GPIO4_SEL<2:0>\n POSITION=<14:12>\n DEFAULT=000\n MODE=RWI\n #! GPIO4 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO3_SEL<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! GPIO3 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO2_SEL<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! GPIO2 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO1_SEL<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! GPIO1 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO0_SEL<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! GPIO0 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOOUT_SEL1 0x0006\n BITFIELD GPIO9_SEL<2:0>\n POSITION=<14:12>\n DEFAULT=000\n MODE=RWI\n #! GPIO9 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO8_SEL<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! GPIO8 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO7_SEL<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! GPIO7 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO6_SEL<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! GPIO6 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\n BITFIELD GPIO5_SEL<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! GPIO5 source select\n #! 000 - from SPI\n #! 001 - PLL_LOCK\n #! 010 - VTUNE_LOW\n #! 011 - VTUNE_HIGH\n #! 100 - Fast lock active\n #! others - reserved\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOInData 0x0008\n BITFIELD GPIO_IN<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=R\n #! Data read from GPIO pads.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOConfig_PE 0x0009\n BITFIELD GPIO_PE<8:0>\n POSITION=<8:0>\n DEFAULT=111111111\n MODE=RW\n #! GPIO pull up control\n #! 0 - Pull up disengaged\n #! 1 - Pull up engaged (default)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOConfig_DS 0x000A\n BITFIELD GPIO_DS<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RW\n #! GPIO drive strength\n #! 0 - Driver strength is 4mA (default)\n #! 1 - Driver strength is 8mA\n ENDBITFIELD\nENDREGISTER\n\nREGISTER GPIOConfig_IO 0x000B\n BITFIELD GPIO_InO<8:0>\n POSITION=<8:0>\n DEFAULT=111111111\n MODE=RW\n #! GPIO input/output control\n #! 0 - Pin is output\n #! 1 - Pin is input (default)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER TEMP_SENS 0x000C\n BITFIELD TEMP_SENS_EN\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enable the temperature sensor biasing.\n ENDBITFIELD\n BITFIELD TEMP_SENS_CLKEN\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Temperature sensor clock enable.\n ENDBITFIELD\n BITFIELD TEMP_START_CONV\n POSITION=8\n DEFAULT=0\n MODE=STICKYBIT\n #! Start the temperature conversion.\n #! Bit is cleared when the conversion is complete.\n ENDBITFIELD\n BITFIELD TEMP_READ<7:0>\n POSITION=<7:0>\n DEFAULT=00000000\n MODE=R\n #! Readout of temperature sensor\n ENDBITFIELD\nENDREGISTER\n\nREGISTER ChipInfo 0x000F\n BITFIELD VER<4:0>\n POSITION=<15:11>\n DEFAULT=01000\n MODE=RI\n #! Chip version.\n #! 01000 - Chip version is 8.\n ENDBITFIELD\n BITFIELD REV<4:0>\n POSITION=<10:6>\n DEFAULT=00001\n MODE=RI\n #! Chip revision.\n #! 00001 - Chip revision is 1.\n ENDBITFIELD\n BITFIELD MASK<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RI\n #! Chip mask.\n #! 000000 - Chip mask is 0.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER BiasConfig 0x0010\n BITFIELD PD_CALIB_COMP\n POSITION=12\n DEFAULT=1\n MODE=RW\n #! Calibration comparator power down.\n #! 0 - Enabled\n #! 1 - Powered down (default)\n ENDBITFIELD\n BITFIELD RP_CALIB_COMP\n POSITION=11\n DEFAULT=0\n MODE=R\n #! Comparator output. Used in rppolywo calibration algorithm.\n ENDBITFIELD\n BITFIELD RP_CALIB_BIAS<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RW\n #! Calibration code for rppolywo. This code is set by calibration algorithm.\n #! Default value : 10000 (16)\n ENDBITFIELD\n BITFIELD PD_FRP_BIAS\n POSITION=4\n DEFAULT=0\n MODE=RW\n #! Power down signal for Fix/RP\n #! 0 - Enabled (default)\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD PD_F_BIAS\n POSITION=3\n DEFAULT=0\n MODE=RW\n #! Power down signal for Fix\n #! 0 - Enabled (default)\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD PD_PTRP_BIAS\n POSITION=2\n DEFAULT=0\n MODE=RW\n #! Power down signal for PTAT/RP block\n #! 0 - Enabled (default)\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD PD_PT_BIAS\n POSITION=1\n DEFAULT=0\n MODE=RW\n #! Power down signal for PTAT block\n #! 0 - Enabled (default)\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD PD_BIAS\n POSITION=0\n DEFAULT=0\n MODE=RW\n #! Enable signal for central bias block\n #! 0 - Sub blocks may be selectively powered down (default)\n #! 1 - Poweres down all BIAS blocks\n ENDBITFIELD\nENDREGISTER\n\nREGISTER LOBUFA_LDO_Config 0x0011\n BITFIELD EN_LOADIMP_LDO_LOBUFA\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_LOBUFA\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_LOBUFA\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_LOBUFA<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER LOBUFB_LDO_Config 0x0012\n BITFIELD EN_LOADIMP_LDO_LOBUFB\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_LOBUFB\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_LOBUFB\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_LOBUFB<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER LOBUFC_LDO_Config 0x0013\n BITFIELD EN_LOADIMP_LDO_LOBUFC\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_LOBUFC\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_LOBUFC\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_LOBUFC<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER LOBUFD_LDO_Config 0x0014\n BITFIELD EN_LOADIMP_LDO_LOBUFD\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_LOBUFD\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_LOBUFD\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_LOBUFD<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HFLNAA_LDO_Config 0x0015\n BITFIELD EN_LOADIMP_LDO_HFLNAA\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_HFLNAA\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_HFLNAA\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_HFLNAA<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HFLNAB_LDO_Config 0x0016\n BITFIELD EN_LOADIMP_LDO_HFLNAB\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_HFLNAB\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_HFLNAB\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_HFLNAB<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HFLNAC_LDO_Config 0x0017\n BITFIELD EN_LOADIMP_LDO_HFLNAC\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_HFLNAC\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_HFLNAC\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_HFLNAC<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HFLNAD_LDO_Config 0x0018\n BITFIELD EN_LOADIMP_LDO_HFLNAD\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_HFLNAD\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_HFLNAD\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_HFLNAD<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CLK_BUF_LDO_Config 0x001A\n BITFIELD EN_LOADIMP_LDO_CLK_BUF\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_CLK_BUF\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_CLK_BUF\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the LO buffer LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_CLK_BUF<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_DIV_LDO_Config 0x001B\n BITFIELD EN_LOADIMP_LDO_PLL_DIV\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_PLL_DIV\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_PLL_DIV\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the PLL divider LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_PLL_DIV<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the PLL divider LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_LDO_Config 0x001C\n BITFIELD EN_LOADIMP_LDO_PLL_CP\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_PLL_CP\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD EN_LDO_PLL_CP\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Enables the PLL CP LDO\n #! 0 - LDO powered down (default)\n #! 1 - LDO enabled\n ENDBITFIELD\n BITFIELD RDIV_PLL_CP<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the PLL CP LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER DIG_CORE_LDO_Config 0x001F\n BITFIELD EN_LOADIMP_LDO_DIG_CORE\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Enables the load dependent bias to optimize the load regulation\n #! 0 - Constant bias (default)\n #! 1 - Load dependant bias\n ENDBITFIELD\n BITFIELD SPDUP_LDO_DIG_CORE\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! Short the noise filter resistor to speed up the settling time\n #! 0 - Noise filter resistor in place (default)\n #! 1 - Noise filter resistor bypassed\n ENDBITFIELD\n BITFIELD PD_LDO_DIG_CORE\n POSITION=8\n DEFAULT=0\n MODE=RW\n #! Power down the digital core and IO ring pre-drivers LDO\n #! 0 - LDO on (default)\n #! 1 - LDO powered down\n ENDBITFIELD\n BITFIELD RDIV_DIG_CORE<7:0>\n POSITION=<7:0>\n DEFAULT=01100101\n MODE=RW\n #! Controls the output voltage of the digital core and IO ring pre-drivers LDO by setting the resistive voltage divider ratio.\n #! Vout = 860 mV + 3.92 mV * RDIV\n #! Default : 01100101 (101) Vout = 1.25 V\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_MIX_ICT 0x1000\n BITFIELD CHA_MIXB_ICT<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHA_MIXB_ICT/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_MIXA_ICT<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHA_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_HFPAD_ICT 0x1001\n BITFIELD CHA_PA_ILIN2X\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Double the linearization bias current\n #! 0 - Ilin * 1\n #! 1 - Ilin * 2\n #! Default : 0\n ENDBITFIELD\n BITFIELD CHA_PA_ICT_LIN<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of linearization section of HFPAD\n #! I = Inom * CHA_PA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_PA_ICT_MAIN<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of main gm section of HFPAD\n #! I = Inom * CHA_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD0 0x1004\n BITFIELD CHA_PA_R50_EN0\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHA_PA_BYPASS0\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHA_PA_PD0\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_LOBUFF_PD0\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_BIAS_PD0\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_LOBUFF_PD0\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_LNA_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD1 0x1005\n BITFIELD CHA_PA_R50_EN1\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHA_PA_BYPASS1\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHA_PA_PD1\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_LOBUFF_PD1\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_BIAS_PD1\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_LOBUFF_PD1\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_LNA_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD2 0x1006\n BITFIELD CHA_PA_R50_EN2\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHA_PA_BYPASS2\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHA_PA_PD2\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_LOBUFF_PD2\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_BIAS_PD2\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_LOBUFF_PD2\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_LNA_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD3 0x1007\n BITFIELD CHA_PA_R50_EN3\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHA_PA_BYPASS3\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHA_PA_PD3\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_LOBUFF_PD3\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXB_BIAS_PD3\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_LOBUFF_PD3\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_MIXA_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHA_LNA_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_CTRL0 0x1008\n BITFIELD CHA_LNA_ICT_LIN0<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHA_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_ICT_MAIN0<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHA_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_CGSCTRL0<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_GCTRL0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_CTRL1 0x1009\n BITFIELD CHA_LNA_ICT_LIN1<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHA_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_ICT_MAIN1<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHA_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_CGSCTRL1<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_GCTRL1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_CTRL2 0x100A\n BITFIELD CHA_LNA_ICT_LIN2<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHA_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_ICT_MAIN2<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHA_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_CGSCTRL2<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_GCTRL2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_CTRL3 0x100B\n BITFIELD CHA_LNA_ICT_LIN3<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHA_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_ICT_MAIN3<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHA_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHA_LNA_CGSCTRL3<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_GCTRL3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_CTRL0 0x100C\n BITFIELD CHA_PA_LIN_LOSS0<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHA_PA_MAIN_LOSS0<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_CTRL1 0x100D\n BITFIELD CHA_PA_LIN_LOSS1<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHA_PA_MAIN_LOSS1<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_CTRL2 0x100E\n BITFIELD CHA_PA_LIN_LOSS2<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHA_PA_MAIN_LOSS2<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_CTRL3 0x100F\n BITFIELD CHA_PA_LIN_LOSS3<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHA_PA_MAIN_LOSS3<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD_SEL0 0x1010\n BITFIELD CHA_PD_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PD_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PD_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD_SEL1 0x1011\n BITFIELD CHA_PD_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PD_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PD_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_SEL0 0x1012\n BITFIELD CHA_LNA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_SEL1 0x1013\n BITFIELD CHA_LNA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_SEL0 0x1014\n BITFIELD CHA_PA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_SEL1 0x1015\n BITFIELD CHA_PA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_INT_SEL 0x1016\n BITFIELD CHA_PA_INT_SEL<1:0>\n POSITION=<5:4>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_LNA_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHA_PD_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PD_RB 0x101D\n BITFIELD CHA_PA_R50_EN_RB\n POSITION=7\n DEFAULT=CHA_PA_R50_EN0\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_PA_BYPASS_RB\n POSITION=6\n DEFAULT=CHA_PA_BYPASS\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_PA_PD_RB\n POSITION=5\n DEFAULT=CHA_PA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_MIXB_LOBUFF_PD_RB\n POSITION=4\n DEFAULT=CHA_MIXB_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_MIXB_BIAS_PD_RB\n POSITION=3\n DEFAULT=CHA_MIXB_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_MIXA_LOBUFF_PD_RB\n POSITION=2\n DEFAULT=CHA_MIXA_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_MIXA_BIAS_PD_RB\n POSITION=1\n DEFAULT=CHA_MIXA_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_LNA_PD_RB\n POSITION=0\n DEFAULT=CHA_LNA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_LNA_CTRL_RB 0x101E\n BITFIELD CHA_LNA_ICT_LIN_RB<4:0>\n POSITION=<15:11>\n DEFAULT=CHA_LNA_ICT_LIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_LNA_ICT_MAIN_RB<4:0>\n POSITION=<10:6>\n DEFAULT=CHA_LNA_ICT_MAIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_LNA_CGSCTRL_RB<1:0>\n POSITION=<5:4>\n DEFAULT=CHA_LNA_CGSCTRL<1:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_LNA_GCTRL_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHA_LNA_GCTRL<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHA_PA_CTRL_RB 0x101F\n BITFIELD CHA_PA_LIN_LOSS_RB<3:0>\n POSITION=<7:4>\n DEFAULT=CHA_PA_LIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHA_PA_MAIN_LOSS_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHA_PA_MAIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_MIX_ICT 0x1020\n BITFIELD CHB_MIXB_ICT<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHB_MIXB_ICT/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_MIXA_ICT<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHB_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_HFPAD_ICT 0x1021\n BITFIELD CHB_PA_ILIN2X\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Double the linearization bias current\n #! 0 - Ilin * 1\n #! 1 - Ilin * 2\n #! Default : 0\n ENDBITFIELD\n BITFIELD CHB_PA_ICT_LIN<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of linearization section of HFPAD\n #! I = Inom * CHB_PA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_PA_ICT_MAIN<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of main gm section of HFPAD\n #! I = Inom * CHB_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD0 0x1024\n BITFIELD CHB_PA_R50_EN0\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHB_PA_BYPASS0\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHB_PA_PD0\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_LOBUFF_PD0\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_BIAS_PD0\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_LOBUFF_PD0\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_LNA_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD1 0x1025\n BITFIELD CHB_PA_R50_EN1\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHB_PA_BYPASS1\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHB_PA_PD1\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_LOBUFF_PD1\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_BIAS_PD1\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_LOBUFF_PD1\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_LNA_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD2 0x1026\n BITFIELD CHB_PA_R50_EN2\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHB_PA_BYPASS2\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHB_PA_PD2\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_LOBUFF_PD2\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_BIAS_PD2\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_LOBUFF_PD2\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_LNA_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD3 0x1027\n BITFIELD CHB_PA_R50_EN3\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHB_PA_BYPASS3\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHB_PA_PD3\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_LOBUFF_PD3\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXB_BIAS_PD3\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_LOBUFF_PD3\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_MIXA_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHB_LNA_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_CTRL0 0x1028\n BITFIELD CHB_LNA_ICT_LIN0<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHB_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_ICT_MAIN0<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHB_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_CGSCTRL0<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_GCTRL0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_CTRL1 0x1029\n BITFIELD CHB_LNA_ICT_LIN1<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHB_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_ICT_MAIN1<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHB_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_CGSCTRL1<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_GCTRL1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_CTRL2 0x102A\n BITFIELD CHB_LNA_ICT_LIN2<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHB_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_ICT_MAIN2<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHB_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_CGSCTRL2<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_GCTRL2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_CTRL3 0x102B\n BITFIELD CHB_LNA_ICT_LIN3<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHB_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_ICT_MAIN3<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHB_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHB_LNA_CGSCTRL3<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_GCTRL3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_CTRL0 0x102C\n BITFIELD CHB_PA_LIN_LOSS0<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHB_PA_MAIN_LOSS0<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_CTRL1 0x102D\n BITFIELD CHB_PA_LIN_LOSS1<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHB_PA_MAIN_LOSS1<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_CTRL2 0x102E\n BITFIELD CHB_PA_LIN_LOSS2<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHB_PA_MAIN_LOSS2<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_CTRL3 0x102F\n BITFIELD CHB_PA_LIN_LOSS3<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHB_PA_MAIN_LOSS3<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD_SEL0 0x1030\n BITFIELD CHB_PD_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PD_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PD_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD_SEL1 0x1031\n BITFIELD CHB_PD_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PD_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PD_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_SEL0 0x1032\n BITFIELD CHB_LNA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_SEL1 0x1033\n BITFIELD CHB_LNA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_SEL0 0x1034\n BITFIELD CHB_PA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_SEL1 0x1035\n BITFIELD CHB_PA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_INT_SEL 0x1036\n BITFIELD CHB_PA_INT_SEL<1:0>\n POSITION=<5:4>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_LNA_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHB_PD_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PD_RB 0x103D\n BITFIELD CHB_PA_R50_EN_RB\n POSITION=7\n DEFAULT=CHB_PA_R50_EN0\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_PA_BYPASS_RB\n POSITION=6\n DEFAULT=CHB_PA_BYPASS\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_PA_PD_RB\n POSITION=5\n DEFAULT=CHB_PA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_MIXB_LOBUFF_PD_RB\n POSITION=4\n DEFAULT=CHB_MIXB_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_MIXB_BIAS_PD_RB\n POSITION=3\n DEFAULT=CHB_MIXB_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_MIXA_LOBUFF_PD_RB\n POSITION=2\n DEFAULT=CHB_MIXA_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_MIXA_BIAS_PD_RB\n POSITION=1\n DEFAULT=CHB_MIXA_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_LNA_PD_RB\n POSITION=0\n DEFAULT=CHB_LNA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_LNA_CTRL_RB 0x103E\n BITFIELD CHB_LNA_ICT_LIN_RB<4:0>\n POSITION=<15:11>\n DEFAULT=CHB_LNA_ICT_LIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_LNA_ICT_MAIN_RB<4:0>\n POSITION=<10:6>\n DEFAULT=CHB_LNA_ICT_MAIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_LNA_CGSCTRL_RB<1:0>\n POSITION=<5:4>\n DEFAULT=CHB_LNA_CGSCTRL<1:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_LNA_GCTRL_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHB_LNA_GCTRL<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHB_PA_CTRL_RB 0x103F\n BITFIELD CHB_PA_LIN_LOSS_RB<3:0>\n POSITION=<7:4>\n DEFAULT=CHB_PA_LIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHB_PA_MAIN_LOSS_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHB_PA_MAIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_MIX_ICT 0x1040\n BITFIELD CHC_MIXB_ICT<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHC_MIXB_ICT/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_MIXA_ICT<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHC_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_HFPAD_ICT 0x1041\n BITFIELD CHC_PA_ILIN2X\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Double the linearization bias current\n #! 0 - Ilin * 1\n #! 1 - Ilin * 2\n #! Default : 0\n ENDBITFIELD\n BITFIELD CHC_PA_ICT_LIN<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of linearization section of HFPAD\n #! I = Inom * CHC_PA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_PA_ICT_MAIN<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of main gm section of HFPAD\n #! I = Inom * CHC_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD0 0x1044\n BITFIELD CHC_PA_R50_EN0\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHC_PA_BYPASS0\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHC_PA_PD0\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_LOBUFF_PD0\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_BIAS_PD0\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_LOBUFF_PD0\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_LNA_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD1 0x1045\n BITFIELD CHC_PA_R50_EN1\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHC_PA_BYPASS1\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHC_PA_PD1\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_LOBUFF_PD1\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_BIAS_PD1\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_LOBUFF_PD1\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_LNA_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD2 0x1046\n BITFIELD CHC_PA_R50_EN2\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHC_PA_BYPASS2\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHC_PA_PD2\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_LOBUFF_PD2\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_BIAS_PD2\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_LOBUFF_PD2\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_LNA_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD3 0x1047\n BITFIELD CHC_PA_R50_EN3\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHC_PA_BYPASS3\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHC_PA_PD3\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_LOBUFF_PD3\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXB_BIAS_PD3\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_LOBUFF_PD3\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_MIXA_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHC_LNA_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_CTRL0 0x1048\n BITFIELD CHC_LNA_ICT_LIN0<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHC_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_ICT_MAIN0<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHC_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_CGSCTRL0<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_GCTRL0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_CTRL1 0x1049\n BITFIELD CHC_LNA_ICT_LIN1<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHC_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_ICT_MAIN1<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHC_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_CGSCTRL1<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_GCTRL1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_CTRL2 0x104A\n BITFIELD CHC_LNA_ICT_LIN2<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHC_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_ICT_MAIN2<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHC_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_CGSCTRL2<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_GCTRL2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_CTRL3 0x104B\n BITFIELD CHC_LNA_ICT_LIN3<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHC_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_ICT_MAIN3<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHC_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHC_LNA_CGSCTRL3<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_GCTRL3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_CTRL0 0x104C\n BITFIELD CHC_PA_LIN_LOSS0<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHC_PA_MAIN_LOSS0<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_CTRL1 0x104D\n BITFIELD CHC_PA_LIN_LOSS1<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHC_PA_MAIN_LOSS1<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_CTRL2 0x104E\n BITFIELD CHC_PA_LIN_LOSS2<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHC_PA_MAIN_LOSS2<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_CTRL3 0x104F\n BITFIELD CHC_PA_LIN_LOSS3<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHC_PA_MAIN_LOSS3<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD_SEL0 0x1050\n BITFIELD CHC_PD_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PD_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PD_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD_SEL1 0x1051\n BITFIELD CHC_PD_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PD_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PD_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_SEL0 0x1052\n BITFIELD CHC_LNA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_SEL1 0x1053\n BITFIELD CHC_LNA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_SEL0 0x1054\n BITFIELD CHC_PA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_SEL1 0x1055\n BITFIELD CHC_PA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_INT_SEL 0x1056\n BITFIELD CHC_PA_INT_SEL<1:0>\n POSITION=<5:4>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_LNA_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHC_PD_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PD_RB 0x105D\n BITFIELD CHC_PA_R50_EN_RB\n POSITION=7\n DEFAULT=CHC_PA_R50_EN0\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_PA_BYPASS_RB\n POSITION=6\n DEFAULT=CHC_PA_BYPASS\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_PA_PD_RB\n POSITION=5\n DEFAULT=CHC_PA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_MIXB_LOBUFF_PD_RB\n POSITION=4\n DEFAULT=CHC_MIXB_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_MIXB_BIAS_PD_RB\n POSITION=3\n DEFAULT=CHC_MIXB_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_MIXA_LOBUFF_PD_RB\n POSITION=2\n DEFAULT=CHC_MIXA_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_MIXA_BIAS_PD_RB\n POSITION=1\n DEFAULT=CHC_MIXA_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_LNA_PD_RB\n POSITION=0\n DEFAULT=CHC_LNA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_LNA_CTRL_RB 0x105E\n BITFIELD CHC_LNA_ICT_LIN_RB<4:0>\n POSITION=<15:11>\n DEFAULT=CHC_LNA_ICT_LIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_LNA_ICT_MAIN_RB<4:0>\n POSITION=<10:6>\n DEFAULT=CHC_LNA_ICT_MAIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_LNA_CGSCTRL_RB<1:0>\n POSITION=<5:4>\n DEFAULT=CHC_LNA_CGSCTRL<1:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_LNA_GCTRL_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHC_LNA_GCTRL<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHC_PA_CTRL_RB 0x105F\n BITFIELD CHC_PA_LIN_LOSS_RB<3:0>\n POSITION=<7:4>\n DEFAULT=CHC_PA_LIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHC_PA_MAIN_LOSS_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHC_PA_MAIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_MIX_ICT 0x1060\n BITFIELD CHD_MIXB_ICT<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHD_MIXB_ICT/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_MIXA_ICT<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of polarization circuit\n #! I = Inom * CHD_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_HFPAD_ICT 0x1061\n BITFIELD CHD_PA_ILIN2X\n POSITION=10\n DEFAULT=0\n MODE=RW\n #! Double the linearization bias current\n #! 0 - Ilin * 1\n #! 1 - Ilin * 2\n #! Default : 0\n ENDBITFIELD\n BITFIELD CHD_PA_ICT_LIN<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of linearization section of HFPAD\n #! I = Inom * CHD_PA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_PA_ICT_MAIN<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n #! Controls the bias current of main gm section of HFPAD\n #! I = Inom * CHD_MIXA_ICT/16\n #! Default : 16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD0 0x1064\n BITFIELD CHD_PA_R50_EN0\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHD_PA_BYPASS0\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHD_PA_PD0\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_LOBUFF_PD0\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_BIAS_PD0\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_LOBUFF_PD0\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_LNA_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD1 0x1065\n BITFIELD CHD_PA_R50_EN1\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHD_PA_BYPASS1\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHD_PA_PD1\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_LOBUFF_PD1\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_BIAS_PD1\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_LOBUFF_PD1\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_LNA_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD2 0x1066\n BITFIELD CHD_PA_R50_EN2\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHD_PA_BYPASS2\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHD_PA_PD2\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_LOBUFF_PD2\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_BIAS_PD2\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_LOBUFF_PD2\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_LNA_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD3 0x1067\n BITFIELD CHD_PA_R50_EN3\n POSITION=7\n DEFAULT=1\n MODE=RWI\n #! Controls the switch in series with 50 Ohm resistor to ground at HFPAD input.\n #! 0 - Switch is open\n #! 1 - Switch is closed\n ENDBITFIELD\n BITFIELD CHD_PA_BYPASS3\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Controls the HFPAD bypass switches.\n #! 0 - HFPAD in not bypassed\n #! 1 - HFPAD is bypassed\n #! Note : HFPAD must be manually disabled when bypassed.\n ENDBITFIELD\n BITFIELD CHD_PA_PD3\n POSITION=5\n DEFAULT=1\n MODE=RWI\n #! Power down for HFPAD\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_LOBUFF_PD3\n POSITION=4\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXB_BIAS_PD3\n POSITION=3\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXB bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_LOBUFF_PD3\n POSITION=2\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA LO buffer\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_MIXA_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n #! Power down for MIXA bias\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\n BITFIELD CHD_LNA_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n #! Power down for LNA\n #! 0 - Enabled\n #! 1 - Powered down\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_CTRL0 0x1068\n BITFIELD CHD_LNA_ICT_LIN0<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHD_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_ICT_MAIN0<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHD_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_CGSCTRL0<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_GCTRL0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_CTRL1 0x1069\n BITFIELD CHD_LNA_ICT_LIN1<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHD_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_ICT_MAIN1<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHD_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_CGSCTRL1<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_GCTRL1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_CTRL2 0x106A\n BITFIELD CHD_LNA_ICT_LIN2<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHD_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_ICT_MAIN2<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHD_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_CGSCTRL2<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_GCTRL2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_CTRL3 0x106B\n BITFIELD CHD_LNA_ICT_LIN3<4:0>\n POSITION=<15:11>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of linearization section of LNA\n #! I = Inom * CHD_LNA_ICT_LIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_ICT_MAIN3<4:0>\n POSITION=<10:6>\n DEFAULT=10000\n MODE=RWI\n #! Controls the bias current of main gm section of LNA\n #! I = Inom * CHD_LNA_ICT_MAIN/16\n #! Default : 16\n ENDBITFIELD\n BITFIELD CHD_LNA_CGSCTRL3<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_GCTRL3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_CTRL0 0x106C\n BITFIELD CHD_PA_LIN_LOSS0<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHD_PA_MAIN_LOSS0<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_CTRL1 0x106D\n BITFIELD CHD_PA_LIN_LOSS1<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHD_PA_MAIN_LOSS1<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_CTRL2 0x106E\n BITFIELD CHD_PA_LIN_LOSS2<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHD_PA_MAIN_LOSS2<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_CTRL3 0x106F\n BITFIELD CHD_PA_LIN_LOSS3<3:0>\n POSITION=<7:4>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD linearizing section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\n BITFIELD CHD_PA_MAIN_LOSS3<3:0>\n POSITION=<3:0>\n DEFAULT=0000\n MODE=RWI\n #! Controls the gain of HFPAD main section\n #! Pout = Pout_max - Loss\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD_SEL0 0x1070\n BITFIELD CHD_PD_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PD_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PD_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD_SEL1 0x1071\n BITFIELD CHD_PD_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PD_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PD_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_SEL0 0x1072\n BITFIELD CHD_LNA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_SEL1 0x1073\n BITFIELD CHD_LNA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_SEL0 0x1074\n BITFIELD CHD_PA_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PA_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PA_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_SEL1 0x1075\n BITFIELD CHD_PA_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PA_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PA_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_INT_SEL 0x1076\n BITFIELD CHD_PA_INT_SEL<1:0>\n POSITION=<5:4>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_LNA_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD CHD_PD_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PD_RB 0x107D\n BITFIELD CHD_PA_R50_EN_RB\n POSITION=7\n DEFAULT=CHD_PA_R50_EN0\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_PA_BYPASS_RB\n POSITION=6\n DEFAULT=CHD_PA_BYPASS\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_PA_PD_RB\n POSITION=5\n DEFAULT=CHD_PA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_MIXB_LOBUFF_PD_RB\n POSITION=4\n DEFAULT=CHD_MIXB_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_MIXB_BIAS_PD_RB\n POSITION=3\n DEFAULT=CHD_MIXB_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_MIXA_LOBUFF_PD_RB\n POSITION=2\n DEFAULT=CHD_MIXA_LOBUFF_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_MIXA_BIAS_PD_RB\n POSITION=1\n DEFAULT=CHD_MIXA_BIAS_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_LNA_PD_RB\n POSITION=0\n DEFAULT=CHD_LNA_PD\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_LNA_CTRL_RB 0x107E\n BITFIELD CHD_LNA_ICT_LIN_RB<4:0>\n POSITION=<15:11>\n DEFAULT=CHD_LNA_ICT_LIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_LNA_ICT_MAIN_RB<4:0>\n POSITION=<10:6>\n DEFAULT=CHD_LNA_ICT_MAIN<4:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_LNA_CGSCTRL_RB<1:0>\n POSITION=<5:4>\n DEFAULT=CHD_LNA_CGSCTRL<1:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_LNA_GCTRL_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHD_LNA_GCTRL<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER CHD_PA_CTRL_RB 0x107F\n BITFIELD CHD_PA_LIN_LOSS_RB<3:0>\n POSITION=<7:4>\n DEFAULT=CHD_PA_LIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\n BITFIELD CHD_PA_MAIN_LOSS_RB<3:0>\n POSITION=<3:0>\n DEFAULT=CHD_PA_MAIN_LOSS<3:0>\n MODE=RB\n #! Readback the actual controlling value\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONFIG0 0x2000\n BITFIELD HLMIXA_VGCAS0<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_ICT_BIAS0<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOBUF_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONFIG1 0x2001\n BITFIELD HLMIXA_VGCAS1<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_ICT_BIAS1<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOBUF_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONFIG2 0x2002\n BITFIELD HLMIXA_VGCAS2<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_ICT_BIAS2<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOBUF_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONFIG3 0x2003\n BITFIELD HLMIXA_VGCAS3<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_ICT_BIAS3<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOBUF_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS0 0x2004\n BITFIELD HLMIXA_MIXLOSS0<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_MIXLOSS_FINE0<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS1 0x2005\n BITFIELD HLMIXA_MIXLOSS1<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_MIXLOSS_FINE1<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS2 0x2006\n BITFIELD HLMIXA_MIXLOSS2<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_MIXLOSS_FINE2<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS3 0x2007\n BITFIELD HLMIXA_MIXLOSS3<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_MIXLOSS_FINE3<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONF_SEL0 0x2008\n BITFIELD HLMIXA_CONF_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_CONF_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_CONF_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONF_SEL1 0x2009\n BITFIELD HLMIXA_CONF_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_CONF_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_CONF_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS_SEL0 0x200A\n BITFIELD HLMIXA_LOSS_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOSS_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOSS_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS_SEL1 0x200B\n BITFIELD HLMIXA_LOSS_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOSS_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_LOSS_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_INT_SEL 0x200C\n BITFIELD HLMIXA_LOSS_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXA_CONF_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_CONFIG_RB 0x200E\n BITFIELD HLMIXA_VGCAS_RB<6:0>\n POSITION=<13:7>\n DEFAULT=HLMIXA_VGCAS<6:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXA_ICT_BIAS_RB<4:0>\n POSITION=<6:2>\n DEFAULT=HLMIXA_ICT_BIAS<4:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXA_BIAS_PD_RB\n POSITION=1\n DEFAULT=HLMIXA_BIAS_PD\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXA_LOBUF_PD_RB\n POSITION=0\n DEFAULT=HLMIXA_LOBUF_PD\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXA_LOSS_RB 0x200F\n BITFIELD HLMIXA_MIXLOSS_RB<3:0>\n POSITION=<5:2>\n DEFAULT=HLMIXA_MIXLOSS<3:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXA_MIXLOSS_FINE_RB<1:0>\n POSITION=<1:0>\n DEFAULT=HLMIXA_MIXLOSS_FINE<1:0>\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONFIG0 0x2010\n BITFIELD HLMIXB_VGCAS0<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_ICT_BIAS0<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOBUF_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONFIG1 0x2011\n BITFIELD HLMIXB_VGCAS1<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_ICT_BIAS1<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOBUF_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONFIG2 0x2012\n BITFIELD HLMIXB_VGCAS2<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_ICT_BIAS2<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOBUF_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONFIG3 0x2013\n BITFIELD HLMIXB_VGCAS3<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_ICT_BIAS3<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOBUF_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS0 0x2014\n BITFIELD HLMIXB_MIXLOSS0<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_MIXLOSS_FINE0<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS1 0x2015\n BITFIELD HLMIXB_MIXLOSS1<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_MIXLOSS_FINE1<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS2 0x2016\n BITFIELD HLMIXB_MIXLOSS2<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_MIXLOSS_FINE2<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS3 0x2017\n BITFIELD HLMIXB_MIXLOSS3<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_MIXLOSS_FINE3<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONF_SEL0 0x2018\n BITFIELD HLMIXB_CONF_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_CONF_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_CONF_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONF_SEL1 0x2019\n BITFIELD HLMIXB_CONF_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_CONF_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_CONF_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS_SEL0 0x201A\n BITFIELD HLMIXB_LOSS_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOSS_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOSS_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS_SEL1 0x201B\n BITFIELD HLMIXB_LOSS_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOSS_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_LOSS_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_INT_SEL 0x201C\n BITFIELD HLMIXB_LOSS_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXB_CONF_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_CONFIG_RB 0x201E\n BITFIELD HLMIXB_VGCAS_RB<6:0>\n POSITION=<13:7>\n DEFAULT=HLMIXB_VGCAS<6:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXB_ICT_BIAS_RB<4:0>\n POSITION=<6:2>\n DEFAULT=HLMIXB_ICT_BIAS<4:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXB_BIAS_PD_RB\n POSITION=1\n DEFAULT=HLMIXB_BIAS_PD\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXB_LOBUF_PD_RB\n POSITION=0\n DEFAULT=HLMIXB_LOBUF_PD\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXB_LOSS_RB 0x201F\n BITFIELD HLMIXB_MIXLOSS_RB<3:0>\n POSITION=<5:2>\n DEFAULT=HLMIXB_MIXLOSS<3:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXB_MIXLOSS_FINE_RB<1:0>\n POSITION=<1:0>\n DEFAULT=HLMIXB_MIXLOSS_FINE<1:0>\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONFIG0 0x2020\n BITFIELD HLMIXC_VGCAS0<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_ICT_BIAS0<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOBUF_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONFIG1 0x2021\n BITFIELD HLMIXC_VGCAS1<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_ICT_BIAS1<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOBUF_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONFIG2 0x2022\n BITFIELD HLMIXC_VGCAS2<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_ICT_BIAS2<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOBUF_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONFIG3 0x2023\n BITFIELD HLMIXC_VGCAS3<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_ICT_BIAS3<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOBUF_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS0 0x2024\n BITFIELD HLMIXC_MIXLOSS0<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_MIXLOSS_FINE0<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS1 0x2025\n BITFIELD HLMIXC_MIXLOSS1<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_MIXLOSS_FINE1<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS2 0x2026\n BITFIELD HLMIXC_MIXLOSS2<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_MIXLOSS_FINE2<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS3 0x2027\n BITFIELD HLMIXC_MIXLOSS3<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_MIXLOSS_FINE3<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONF_SEL0 0x2028\n BITFIELD HLMIXC_CONF_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_CONF_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_CONF_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONF_SEL1 0x2029\n BITFIELD HLMIXC_CONF_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_CONF_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_CONF_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS_SEL0 0x202A\n BITFIELD HLMIXC_LOSS_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOSS_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOSS_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS_SEL1 0x202B\n BITFIELD HLMIXC_LOSS_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOSS_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_LOSS_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_INT_SEL 0x202C\n BITFIELD HLMIXC_LOSS_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXC_CONF_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_CONFIG_RB 0x202E\n BITFIELD HLMIXC_VGCAS_RB<6:0>\n POSITION=<13:7>\n DEFAULT=HLMIXC_VGCAS<6:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXC_ICT_BIAS_RB<4:0>\n POSITION=<6:2>\n DEFAULT=HLMIXC_ICT_BIAS<4:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXC_BIAS_PD_RB\n POSITION=1\n DEFAULT=HLMIXC_BIAS_PD\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXC_LOBUF_PD_RB\n POSITION=0\n DEFAULT=HLMIXC_LOBUF_PD\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXC_LOSS_RB 0x202F\n BITFIELD HLMIXC_MIXLOSS_RB<3:0>\n POSITION=<5:2>\n DEFAULT=HLMIXC_MIXLOSS<3:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXC_MIXLOSS_FINE_RB<1:0>\n POSITION=<1:0>\n DEFAULT=HLMIXC_MIXLOSS_FINE<1:0>\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONFIG0 0x2030\n BITFIELD HLMIXD_VGCAS0<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_ICT_BIAS0<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_BIAS_PD0\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOBUF_PD0\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONFIG1 0x2031\n BITFIELD HLMIXD_VGCAS1<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_ICT_BIAS1<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_BIAS_PD1\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOBUF_PD1\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONFIG2 0x2032\n BITFIELD HLMIXD_VGCAS2<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_ICT_BIAS2<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_BIAS_PD2\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOBUF_PD2\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONFIG3 0x2033\n BITFIELD HLMIXD_VGCAS3<6:0>\n POSITION=<13:7>\n DEFAULT=1000000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_ICT_BIAS3<4:0>\n POSITION=<6:2>\n DEFAULT=10000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_BIAS_PD3\n POSITION=1\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOBUF_PD3\n POSITION=0\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS0 0x2034\n BITFIELD HLMIXD_MIXLOSS0<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_MIXLOSS_FINE0<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS1 0x2035\n BITFIELD HLMIXD_MIXLOSS1<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_MIXLOSS_FINE1<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS2 0x2036\n BITFIELD HLMIXD_MIXLOSS2<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_MIXLOSS_FINE2<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS3 0x2037\n BITFIELD HLMIXD_MIXLOSS3<3:0>\n POSITION=<5:2>\n DEFAULT=0000\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_MIXLOSS_FINE3<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONF_SEL0 0x2038\n BITFIELD HLMIXD_CONF_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_CONF_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_CONF_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONF_SEL1 0x2039\n BITFIELD HLMIXD_CONF_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_CONF_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_CONF_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS_SEL0 0x203A\n BITFIELD HLMIXD_LOSS_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOSS_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOSS_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS_SEL1 0x203B\n BITFIELD HLMIXD_LOSS_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOSS_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_LOSS_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_INT_SEL 0x203C\n BITFIELD HLMIXD_LOSS_INT_SEL<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\n BITFIELD HLMIXD_CONF_INT_SEL<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_CONFIG_RB 0x203E\n BITFIELD HLMIXD_VGCAS_RB<6:0>\n POSITION=<13:7>\n DEFAULT=HLMIXD_VGCAS<6:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXD_ICT_BIAS_RB<4:0>\n POSITION=<6:2>\n DEFAULT=HLMIXD_ICT_BIAS<4:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXD_BIAS_PD_RB\n POSITION=1\n DEFAULT=HLMIXD_BIAS_PD\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXD_LOBUF_PD_RB\n POSITION=0\n DEFAULT=HLMIXD_LOBUF_PD\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER HLMIXD_LOSS_RB 0x203F\n BITFIELD HLMIXD_MIXLOSS_RB<3:0>\n POSITION=<5:2>\n DEFAULT=HLMIXD_MIXLOSS<3:0>\n MODE=RB\n ENDBITFIELD\n BITFIELD HLMIXD_MIXLOSS_FINE_RB<1:0>\n POSITION=<1:0>\n DEFAULT=HLMIXD_MIXLOSS_FINE<1:0>\n MODE=RB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VREG 0x4000\n BITFIELD EN_VCOBIAS\n POSITION=11\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD BYP_VCOREG\n POSITION=10\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD CURLIM_VCOREG\n POSITION=9\n DEFAULT=1\n MODE=RW\n ENDBITFIELD\n BITFIELD SPDUP_VCOREG\n POSITION=8\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD VDIV_VCOREG<7:0>\n POSITION=<7:0>\n DEFAULT=00010000\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CFG_XBUF 0x4001\n BITFIELD PLL_XBUF_SLFBEN\n POSITION=2\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_XBUF_BYPEN\n POSITION=1\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_XBUF_EN\n POSITION=0\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CAL_AUTO0 0x4002\n BITFIELD FCAL_START\n POSITION=12\n DEFAULT=0\n MODE=STICKYBIT\n ENDBITFIELD\n BITFIELD VCO_SEL_FINAL_VAL\n POSITION=11\n DEFAULT=0\n MODE=R\n ENDBITFIELD\n BITFIELD VCO_SEL_FINAL<1:0>\n POSITION=<10:9>\n DEFAULT=00\n MODE=R\n ENDBITFIELD\n BITFIELD FREQ_FINAL_VAL\n POSITION=8\n DEFAULT=0\n MODE=R\n ENDBITFIELD\n BITFIELD FREQ_FINAL<7:0>\n POSITION=<7:0>\n DEFAULT=00000000\n MODE=R\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CAL_AUTO1 0x4003\n BITFIELD VCO_SEL_FORCE\n POSITION=13\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD VCO_SEL_INIT<1:0>\n POSITION=<12:11>\n DEFAULT=10\n MODE=RW\n ENDBITFIELD\n BITFIELD FREQ_INIT_POS<2:0>\n POSITION=<10:8>\n DEFAULT=111\n MODE=RW\n ENDBITFIELD\n BITFIELD FREQ_INIT<7:0>\n POSITION=<7:0>\n DEFAULT=00000000\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CAL_AUTO2 0x4004\n BITFIELD FREQ_SETTLING_N<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RW\n ENDBITFIELD\n BITFIELD VTUNE_WAIT_N<7:0>\n POSITION=<7:0>\n DEFAULT=01000000\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CAL_AUTO3 0x4005\n BITFIELD VCO_SEL_FREQ_MAX<7:0>\n POSITION=<15:8>\n DEFAULT=11111010\n MODE=RW\n ENDBITFIELD\n BITFIELD VCO_SEL_FREQ_MIN<7:0>\n POSITION=<7:0>\n DEFAULT=00000101\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CAL_MAN 0x4006\n BITFIELD VCO_FREQ_MAN<7:0>\n POSITION=<15:8>\n DEFAULT=10000000\n MODE=RW\n ENDBITFIELD\n BITFIELD VCO_SEL_MAN<1:0>\n POSITION=<7:6>\n DEFAULT=10\n MODE=RW\n ENDBITFIELD\n BITFIELD FREQ_HIGH\n POSITION=5\n DEFAULT=0\n MODE=R\n ENDBITFIELD\n BITFIELD FREQ_EQUAL\n POSITION=4\n DEFAULT=0\n MODE=R\n ENDBITFIELD\n BITFIELD FREQ_LOW\n POSITION=3\n DEFAULT=0\n MODE=R\n ENDBITFIELD\n BITFIELD CTUNE_STEP_DONE\n POSITION=2\n DEFAULT=0\n MODE=R\n ENDBITFIELD\n BITFIELD CTUNE_START\n POSITION=1\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD CTUNE_EN\n POSITION=0\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CFG_SEL0 0x4008\n BITFIELD PLL_CFG_SEL0_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD PLL_CFG_SEL0_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD PLL_CFG_SEL0_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CFG_SEL1 0x4009\n BITFIELD PLL_CFG_SEL1_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD PLL_CFG_SEL1_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD PLL_CFG_SEL1_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CFG_SEL2 0x400A\n BITFIELD PLL_CFG_SEL2_INTERNAL\n POSITION=11\n DEFAULT=1\n MODE=RWI\n ENDBITFIELD\n BITFIELD PLL_CFG_SEL2_INVERT\n POSITION=10\n DEFAULT=0\n MODE=RWI\n ENDBITFIELD\n BITFIELD PLL_CFG_SEL2_MASK<8:0>\n POSITION=<8:0>\n DEFAULT=000000000\n MODE=RWI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CFG 0x400B\n BITFIELD PLL_RSTN\n POSITION=9\n DEFAULT=0\n MODE=RW\n #! PLL reset, active low.\n ENDBITFIELD\n BITFIELD CTUNE_RES<1:0>\n POSITION=<8:7>\n DEFAULT=01\n MODE=RW\n #! PLL capacitor bank tuning resolution.\n ENDBITFIELD\n BITFIELD PLL_CALIBRATION_MODE\n POSITION=6\n DEFAULT=0\n MODE=RW\n #! PLL calibration mode.\n #! 0 - Automatic calibration (default)\n #! 1 - Manual calibration\n ENDBITFIELD\n BITFIELD PLL_CALIBRATION_EN\n POSITION=5\n DEFAULT=0\n MODE=RW\n #! Activate PLL calibration.\n #! 0 - Normal mode (default)\n #! 1 - Calibration mode\n ENDBITFIELD\n BITFIELD PLL_FLOCK_INTERNAL\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Fast lock control.\n #! 0 - Normal operation. Fast lock select signal comes from fast lock state machine. (default)\n #! 1 - Debug mode. Fast lock select signal is forced by PLL_FLOCK_INTVAL\n ENDBITFIELD\n BITFIELD PLL_FLOCK_INTVAL\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Fast lock control internal select value.\n ENDBITFIELD\n BITFIELD PLL_CFG_INT_SEL<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! Internal PLL profile control.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CFG_STATUS 0x400C\n BITFIELD VTUNE_HIGH\n POSITION=2\n DEFAULT=0\n MODE=R\n #! Tuning voltage high.\n ENDBITFIELD\n BITFIELD VTUNE_LOW\n POSITION=1\n DEFAULT=0\n MODE=R\n #! Tuning voltage low.\n ENDBITFIELD\n BITFIELD PLL_LOCK\n POSITION=0\n DEFAULT=0\n MODE=R\n #! PLL lock detect.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG1 0x400E\n BITFIELD SEL_BIAS_CORE\n POSITION=10\n DEFAULT=0\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_LODIST_ICT_CORE<4:0>\n POSITION=<9:5>\n DEFAULT=10000\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_LODIST_ICT_BUF<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG2 0x400F\n BITFIELD PLL_ICT_OUT3<1:0>\n POSITION=<7:6>\n DEFAULT=10\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_ICT_OUT2<1:0>\n POSITION=<5:4>\n DEFAULT=10\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_ICT_OUT1<1:0>\n POSITION=<3:2>\n DEFAULT=10\n MODE=RW\n ENDBITFIELD\n BITFIELD PLL_ICT_OUT0<1:0>\n POSITION=<1:0>\n DEFAULT=10\n MODE=RW\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_BIST1 0x4010\n BITFIELD BSIGL<6:0>\n POSITION=<15:9>\n DEFAULT=0000000\n MODE=RI\n #! BIST signature. Read only.\n ENDBITFIELD\n BITFIELD BSTATE\n POSITION=8\n DEFAULT=0\n MODE=RI\n #! BIST state indicator\n #! 0 - BIST not running (default)\n #! 1 - BIST running\n ENDBITFIELD\n BITFIELD EN_SDM_TSTO\n POSITION=4\n DEFAULT=0\n MODE=RW\n #! Enable test buffer output\n ENDBITFIELD\n BITFIELD BEN\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable BIST\n ENDBITFIELD\n BITFIELD BSTART\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Starts BIST\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_BIST2 0x4011\n BITFIELD BSIGH<15:0>\n POSITION=<15:0>\n DEFAULT=0000000000000000\n MODE=RI\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_0 0x4100\n BITFIELD PLL_LODIST_EN_BIAS_0\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_0\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_0\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_0\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_0\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_0\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_0\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_0\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_0\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_0\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_0\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_0\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_0\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_0 0x4101\n BITFIELD R3_0<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_0<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_0<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_0 0x4102\n BITFIELD VTUNE_VCT_0<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_0\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_0 0x4103\n BITFIELD FLIP_0\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_0<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_0<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_0<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_0 0x4104\n BITFIELD LD_VCT_0<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_0<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_0 0x4105\n BITFIELD VCO_FREQ_0<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_0 0x4106\n BITFIELD SPDUP_VCO_0\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_0\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_0<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_0<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_0<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_0 0x4107\n BITFIELD FFDIV_SEL_0\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_0<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_0<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_0 0x4108\n BITFIELD INTMOD_EN_0\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_0\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_0\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_0\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_0<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_0 0x4109\n BITFIELD FRACMODL_0<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_0 0x410A\n BITFIELD FRACMODH_0<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_0 0x410B\n BITFIELD PLL_LODIST_EN_OUT_0<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_0<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_0<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_0<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_0<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_0 0x410C\n BITFIELD FLOCK_R3_0<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_0<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_0<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_0<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_0 0x410D\n BITFIELD FLOCK_C3_0<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_0<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_0<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_0 0x410E\n BITFIELD FLOCK_LODIST_EN_OUT_0<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_0\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_0<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_1 0x4110\n BITFIELD PLL_LODIST_EN_BIAS_1\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_1\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_1\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_1\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_1\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_1\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_1\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_1\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_1\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_1\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_1\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_1\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_1\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_1 0x4111\n BITFIELD R3_1<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_1<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_1<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_1 0x4112\n BITFIELD VTUNE_VCT_1<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_1\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_1 0x4113\n BITFIELD FLIP_1\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_1<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_1<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_1<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_1 0x4114\n BITFIELD LD_VCT_1<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_1<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_1 0x4115\n BITFIELD VCO_FREQ_1<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_1 0x4116\n BITFIELD SPDUP_VCO_1\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_1\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_1<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_1<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_1<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_1 0x4117\n BITFIELD FFDIV_SEL_1\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_1<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_1<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_1 0x4118\n BITFIELD INTMOD_EN_1\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_1\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_1\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_1\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_1<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_1 0x4119\n BITFIELD FRACMODL_1<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_1 0x411A\n BITFIELD FRACMODH_1<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_1 0x411B\n BITFIELD PLL_LODIST_EN_OUT_1<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_1<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_1<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_1<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_1<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_1 0x411C\n BITFIELD FLOCK_R3_1<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_1<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_1<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_1<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_1 0x411D\n BITFIELD FLOCK_C3_1<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_1<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_1<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_1 0x411E\n BITFIELD FLOCK_LODIST_EN_OUT_1<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_1\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_1<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_2 0x4120\n BITFIELD PLL_LODIST_EN_BIAS_2\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_2\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_2\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_2\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_2\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_2\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_2\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_2\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_2\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_2\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_2\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_2\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_2\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_2 0x4121\n BITFIELD R3_2<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_2<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_2<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_2 0x4122\n BITFIELD VTUNE_VCT_2<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_2\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_2 0x4123\n BITFIELD FLIP_2\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_2<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_2<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_2<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_2 0x4124\n BITFIELD LD_VCT_2<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_2<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_2 0x4125\n BITFIELD VCO_FREQ_2<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_2 0x4126\n BITFIELD SPDUP_VCO_2\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_2\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_2<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_2<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_2<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_2 0x4127\n BITFIELD FFDIV_SEL_2\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_2<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_2<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_2 0x4128\n BITFIELD INTMOD_EN_2\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_2\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_2\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_2\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_2<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_2 0x4129\n BITFIELD FRACMODL_2<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_2 0x412A\n BITFIELD FRACMODH_2<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_2 0x412B\n BITFIELD PLL_LODIST_EN_OUT_2<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_2<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_2<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_2<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_2<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_2 0x412C\n BITFIELD FLOCK_R3_2<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_2<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_2<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_2<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_2 0x412D\n BITFIELD FLOCK_C3_2<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_2<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_2<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_2 0x412E\n BITFIELD FLOCK_LODIST_EN_OUT_2<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_2\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_2<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_3 0x4130\n BITFIELD PLL_LODIST_EN_BIAS_3\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_3\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_3\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_3\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_3\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_3\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_3\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_3\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_3\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_3\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_3\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_3\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_3\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_3 0x4131\n BITFIELD R3_3<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_3<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_3<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_3 0x4132\n BITFIELD VTUNE_VCT_3<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_3\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_3 0x4133\n BITFIELD FLIP_3\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_3<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_3<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_3<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_3 0x4134\n BITFIELD LD_VCT_3<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_3<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_3 0x4135\n BITFIELD VCO_FREQ_3<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_3 0x4136\n BITFIELD SPDUP_VCO_3\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_3\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_3<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_3<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_3<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_3 0x4137\n BITFIELD FFDIV_SEL_3\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_3<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_3<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_3 0x4138\n BITFIELD INTMOD_EN_3\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_3\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_3\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_3\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_3<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_3 0x4139\n BITFIELD FRACMODL_3<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_3 0x413A\n BITFIELD FRACMODH_3<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_3 0x413B\n BITFIELD PLL_LODIST_EN_OUT_3<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_3<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_3<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_3<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_3<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_3 0x413C\n BITFIELD FLOCK_R3_3<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_3<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_3<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_3<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_3 0x413D\n BITFIELD FLOCK_C3_3<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_3<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_3<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_3 0x413E\n BITFIELD FLOCK_LODIST_EN_OUT_3<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_3\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_3<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_4 0x4140\n BITFIELD PLL_LODIST_EN_BIAS_4\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_4\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_4\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_4\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_4\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_4\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_4\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_4\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_4\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_4\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_4\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_4\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_4\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_4 0x4141\n BITFIELD R3_4<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_4<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_4<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_4<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_4 0x4142\n BITFIELD VTUNE_VCT_4<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_4\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_4<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_4 0x4143\n BITFIELD FLIP_4\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_4<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_4<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_4<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_4 0x4144\n BITFIELD LD_VCT_4<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_4<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_4 0x4145\n BITFIELD VCO_FREQ_4<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_4 0x4146\n BITFIELD SPDUP_VCO_4\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_4\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_4<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_4<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_4<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_4 0x4147\n BITFIELD FFDIV_SEL_4\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_4<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_4<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_4 0x4148\n BITFIELD INTMOD_EN_4\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_4\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_4\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_4\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_4<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_4 0x4149\n BITFIELD FRACMODL_4<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_4 0x414A\n BITFIELD FRACMODH_4<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_4 0x414B\n BITFIELD PLL_LODIST_EN_OUT_4<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_4<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_4<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_4<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_4<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_4 0x414C\n BITFIELD FLOCK_R3_4<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_4<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_4<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_4<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_4 0x414D\n BITFIELD FLOCK_C3_4<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_4<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_4<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_4 0x414E\n BITFIELD FLOCK_LODIST_EN_OUT_4<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_4\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_4<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_5 0x4150\n BITFIELD PLL_LODIST_EN_BIAS_5\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_5\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_5\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_5\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_5\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_5\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_5\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_5\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_5\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_5\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_5\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_5\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_5\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_5 0x4151\n BITFIELD R3_5<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_5<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_5<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_5<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_5 0x4152\n BITFIELD VTUNE_VCT_5<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_5\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_5<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_5 0x4153\n BITFIELD FLIP_5\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_5<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_5<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_5<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_5 0x4154\n BITFIELD LD_VCT_5<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_5<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_5 0x4155\n BITFIELD VCO_FREQ_5<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_5 0x4156\n BITFIELD SPDUP_VCO_5\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_5\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_5<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_5<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_5<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_5 0x4157\n BITFIELD FFDIV_SEL_5\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_5<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_5<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_5 0x4158\n BITFIELD INTMOD_EN_5\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_5\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_5\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_5\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_5<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_5 0x4159\n BITFIELD FRACMODL_5<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_5 0x415A\n BITFIELD FRACMODH_5<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_5 0x415B\n BITFIELD PLL_LODIST_EN_OUT_5<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_5<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_5<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_5<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_5<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_5 0x415C\n BITFIELD FLOCK_R3_5<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_5<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_5<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_5<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_5 0x415D\n BITFIELD FLOCK_C3_5<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_5<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_5<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_5 0x415E\n BITFIELD FLOCK_LODIST_EN_OUT_5<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_5\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_5<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_6 0x4160\n BITFIELD PLL_LODIST_EN_BIAS_6\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_6\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_6\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_6\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_6\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_6\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_6\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_6\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_6\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_6\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_6\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_6\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_6\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_6 0x4161\n BITFIELD R3_6<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_6<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_6<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_6<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_6 0x4162\n BITFIELD VTUNE_VCT_6<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_6\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_6<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_6 0x4163\n BITFIELD FLIP_6\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_6<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_6<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_6<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_6 0x4164\n BITFIELD LD_VCT_6<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_6<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_6 0x4165\n BITFIELD VCO_FREQ_6<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_6 0x4166\n BITFIELD SPDUP_VCO_6\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_6\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_6<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_6<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_6<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_6 0x4167\n BITFIELD FFDIV_SEL_6\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_6<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_6<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_6 0x4168\n BITFIELD INTMOD_EN_6\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_6\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_6\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_6\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_6<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_6 0x4169\n BITFIELD FRACMODL_6<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_6 0x416A\n BITFIELD FRACMODH_6<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_6 0x416B\n BITFIELD PLL_LODIST_EN_OUT_6<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_6<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_6<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_6<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_6<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_6 0x416C\n BITFIELD FLOCK_R3_6<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_6<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_6<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_6<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_6 0x416D\n BITFIELD FLOCK_C3_6<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_6<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_6<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_6 0x416E\n BITFIELD FLOCK_LODIST_EN_OUT_6<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_6\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_6<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_ENABLE_7 0x4170\n BITFIELD PLL_LODIST_EN_BIAS_7\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Enable for LO distribution bias.\n ENDBITFIELD\n BITFIELD PLL_LODIST_EN_DIV2IQ_7\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Enable for IQ generator in LO distribution.\n #! 0 - Clock is not divided by 2\n #! 1 - Clock is divided by 2, I and Q are generated\n ENDBITFIELD\n BITFIELD PLL_EN_VTUNE_COMP_7\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! Enable for tuning voltage comparator in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_LD_7\n POSITION=9\n DEFAULT=0\n MODE=RWI\n #! Lock detector enable.\n ENDBITFIELD\n BITFIELD PLL_EN_PFD_7\n POSITION=8\n DEFAULT=0\n MODE=RWI\n #! Enable for PFD in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CP_7\n POSITION=7\n DEFAULT=0\n MODE=RWI\n #! Enable for charge pump in PLL.\n ENDBITFIELD\n BITFIELD PLL_EN_CPOFS_7\n POSITION=6\n DEFAULT=0\n MODE=RWI\n #! Enable for offset (bleeding) current in charge pump.\n ENDBITFIELD\n BITFIELD PLL_EN_VCO_7\n POSITION=5\n DEFAULT=0\n MODE=RWI\n #! Enable for VCO.\n ENDBITFIELD\n BITFIELD PLL_EN_FFDIV_7\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider in PLL.\n #! 0 - Output clock is not divided\n ENDBITFIELD\n BITFIELD PLL_EN_FB_PDIV2_7\n POSITION=3\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback pre-divider.\n #! 0 - Output clock is directly fed to feedback divider\n ENDBITFIELD\n BITFIELD PLL_EN_FFCORE_7\n POSITION=2\n DEFAULT=0\n MODE=RWI\n #! Enable for feed-forward divider core\n ENDBITFIELD\n BITFIELD PLL_EN_FBDIV_7\n POSITION=1\n DEFAULT=0\n MODE=RWI\n #! Enable for feedback divider core\n ENDBITFIELD\n BITFIELD PLL_SDM_CLK_EN_7\n POSITION=0\n DEFAULT=0\n MODE=RWI\n #! Enable for sigma-delta modulator\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG1_7 0x4171\n BITFIELD R3_7<3:0>\n POSITION=<15:12>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R3_val = 9 kOhm/R3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD R2_7<3:0>\n POSITION=<11:8>\n DEFAULT=0001\n MODE=RWI\n #! Control word for loop filter.\n #! R2_val = 15.6 kOhm/R2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C2_7<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C2 in PLL loop filter.\n #! C2_val = 300 pF+7.5 pF * C2<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\n BITFIELD C1_7<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C1 in PLL loop filter.\n #! C1_val = 1.8 pF*C1<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LPF_CFG2_7 0x4172\n BITFIELD VTUNE_VCT_7<1:0>\n POSITION=<6:5>\n DEFAULT=01\n MODE=RWI\n #! Tuning voltage control word during coarse tuning (LPFSW=1).\n #! 00 - 300 mV,\n #! 01 - 600 mV,\n #! 10 - 750 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD LPFSW_7\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Loop filter control.\n #! 0 - PLL loop is closed,\n #! 1 - PLL loop is open and tuning voltage is set to value specified by VTUNE_VCT<1:0>.\n #! When LFPSW=1 PLL is in open-loop configuration for coarse tuning.\n ENDBITFIELD\n BITFIELD C3_7<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Control word for C3 in PLL loop filter.\n #! C3_val = 3 pF * C3<3:0>\n #! When fast lock mode is enabled, this is the final value.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG0_7 0x4173\n BITFIELD FLIP_7\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Flip for PFD inputs\n #! 0 - Normal operation,\n #! 1 - Inputs are interchanged\n ENDBITFIELD\n BITFIELD DEL_7<1:0>\n POSITION=<13:12>\n DEFAULT=00\n MODE=RWI\n #! Reset path delay\n ENDBITFIELD\n BITFIELD PULSE_7<5:0>\n POSITION=<11:6>\n DEFAULT=000100\n MODE=RWI\n #! Charge pump pulse current\n #! I = 25 uA * PULSE<5:0>\n ENDBITFIELD\n BITFIELD OFS_7<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current\n #! I = 6.25 uA * OFS<5:0>\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_CP_CFG1_7 0x4174\n BITFIELD LD_VCT_7<1:0>\n POSITION=<6:5>\n DEFAULT=10\n MODE=RWI\n #! Threshold voltage for lock detector\n #! 00 - 600 mV,\n #! 01 - 700 mV,\n #! 10 - 800 mV,\n #! 11 - 900 mV.\n ENDBITFIELD\n BITFIELD ICT_CP_7<4:0>\n POSITION=<4:0>\n DEFAULT=10000\n MODE=RWI\n #! Charge pump bias current.\n #! ICP_BIAS = ICP_BIAS_NOM * ICT_CP<4:0>/16\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_FREQ_7 0x4175\n BITFIELD VCO_FREQ_7<7:0>\n POSITION=<7:0>\n DEFAULT=10000000\n MODE=RWI\n #! VCO cap bank code.\n #! 00000000 - lowest frequency\n #! 11111111 - highest frequency\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_VCO_CFG_7 0x4176\n BITFIELD SPDUP_VCO_7\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Speed-up VCO core by bypassing the noise filter\n ENDBITFIELD\n BITFIELD VCO_AAC_EN_7\n POSITION=11\n DEFAULT=1\n MODE=RWI\n #! Enable for automatic VCO amplitude control.\n ENDBITFIELD\n BITFIELD VDIV_SWVDD_7<1:0>\n POSITION=<10:9>\n DEFAULT=10\n MODE=RWI\n #! Capacitor bank switches bias voltage\n #! 00 - 600 mV,\n #! 01 - 800 mV,\n #! 10 - 1000 mV,\n #! 11 - 1200 mV.\n ENDBITFIELD\n BITFIELD VCO_SEL_7<1:0>\n POSITION=<8:7>\n DEFAULT=11\n MODE=RWI\n #! VCO core selection\n #! 00 - External VCO,\n #! 01 - Low-frequency band VCO (4 - 6 GHz),\n #! 10 - Mid-frequency band VCO (6 - 8 GHz),\n #! 11 - High-frequency band VCO (8 - 10 GHz).\n ENDBITFIELD\n BITFIELD VCO_AMP_7<6:0>\n POSITION=<6:0>\n DEFAULT=0000001\n MODE=RWI\n #! VCO amplitude control word.\n #! 0000000 - minimum amplitude\n #! Lowest two bits control the VCO core current.\n #! Other bits are used for fine amplitude control, automatically determined when VCO_AAC_EN=1\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FF_CFG_7 0x4177\n BITFIELD FFDIV_SEL_7\n POSITION=4\n DEFAULT=0\n MODE=RWI\n #! Feed-forward divider multiplexer select bit\n #! 0 - No division,\n #! 1 - Input frequency is divided\n ENDBITFIELD\n BITFIELD FFCORE_MOD_7<1:0>\n POSITION=<3:2>\n DEFAULT=00\n MODE=RWI\n #! Feed-forward divider core modulus\n #! 00 - No division\n #! 01 - Div by 2\n #! 10 - Div by 4\n #! 11 - Div by 8\n ENDBITFIELD\n BITFIELD FF_MOD_7<1:0>\n POSITION=<1:0>\n DEFAULT=00\n MODE=RWI\n #! Multiplexer for divider outputs. In normal operation FF_MOD should be equal to FFCORE_MOD.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_SDM_CFG_7 0x4178\n BITFIELD INTMOD_EN_7\n POSITION=14\n DEFAULT=0\n MODE=RWI\n #! Integer mode enable\n ENDBITFIELD\n BITFIELD DITHER_EN_7\n POSITION=13\n DEFAULT=0\n MODE=RWI\n #! Enable dithering in SDM\n #! 0 - Disabled\n #! 1 - Enabled\n ENDBITFIELD\n BITFIELD SEL_SDMCLK_7\n POSITION=12\n DEFAULT=0\n MODE=RWI\n #! Selects between the feedback divider output and FREF for SDM\n #! 0 - CLK CLK_DIV\n #! 1 - CLK CLK_REF\n ENDBITFIELD\n BITFIELD REV_SDMCLK_7\n POSITION=11\n DEFAULT=0\n MODE=RWI\n #! Reverses the SDM clock\n #! 0 - Normal\n #! 1 - Reversed (after INV)\n ENDBITFIELD\n BITFIELD INTMOD_7<9:0>\n POSITION=<9:0>\n DEFAULT=0011011000\n MODE=RWI\n #! Integer section of division ratio.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODL_7 0x4179\n BITFIELD FRACMODL_7<15:0>\n POSITION=<15:0>\n DEFAULT=0101011100110000\n MODE=RWI\n #! Fractional control of the division ratio LSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FRACMODH_7 0x417A\n BITFIELD FRACMODH_7<3:0>\n POSITION=<3:0>\n DEFAULT=0101\n MODE=RWI\n #! Fractional control of the division ratio MSB\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_LODIST_CFG_7 0x417B\n BITFIELD PLL_LODIST_EN_OUT_7<3:0>\n POSITION=<15:12>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals.\n #! Each bit is an enable for individual channel.\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT3_7<2:0>\n POSITION=<11:9>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 3 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT2_7<2:0>\n POSITION=<8:6>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 2 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT1_7<2:0>\n POSITION=<5:3>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 1 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\n BITFIELD PLL_LODIST_FSP_OUT0_7<2:0>\n POSITION=<2:0>\n DEFAULT=000\n MODE=RWI\n #! LO distribution channel 0 frequency, sign and phase control.\n #! FSP_OUT<2> - Frequency division control\n #! 0 - LO is divided by 2,\n #! 1 - LO is not divided.\n #! FSP_OUT<1> - LO sign\n #! 0 - LO is not inverted\n #! 1 - LO is inverted\n #! FSP_OUT<0> - LO phase\n #! 0 - LO phase 0 deg (I)\n #! 1 - LO phase 90 deg (Q)\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG1_7 0x417C\n BITFIELD FLOCK_R3_7<3:0>\n POSITION=<15:12>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R3 used during fact lock.\n ENDBITFIELD\n BITFIELD FLOCK_R2_7<3:0>\n POSITION=<11:8>\n DEFAULT=0100\n MODE=RWI\n #! Loop filter R2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C2_7<3:0>\n POSITION=<7:4>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C2 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_C1_7<3:0>\n POSITION=<3:0>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C1 used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG2_7 0x417D\n BITFIELD FLOCK_C3_7<3:0>\n POSITION=<15:12>\n DEFAULT=1000\n MODE=RWI\n #! Loop filter C3 used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_PULSE_7<5:0>\n POSITION=<11:6>\n DEFAULT=111111\n MODE=RWI\n #! Charge pump pulse current used during fast lock.\n ENDBITFIELD\n BITFIELD FLOCK_OFS_7<5:0>\n POSITION=<5:0>\n DEFAULT=000000\n MODE=RWI\n #! Charge pump offset (bleeding) current used during fast lock.\n ENDBITFIELD\nENDREGISTER\n\nREGISTER PLL_FLOCK_CFG3_7 0x417E\n BITFIELD FLOCK_LODIST_EN_OUT_7<3:0>\n POSITION=<14:11>\n DEFAULT=0000\n MODE=RWI\n #! LO distribution enable signals used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_VCO_SPDUP_7\n POSITION=10\n DEFAULT=0\n MODE=RWI\n #! VCO speedup used during fast lock\n ENDBITFIELD\n BITFIELD FLOCK_N_7<9:0>\n POSITION=<9:0>\n DEFAULT=0110010000\n MODE=RWI\n #! Duration of fast lock in PLL reference frequency clock cycles.\n ENDBITFIELD\nENDREGISTER\n\n'
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km=float(input('Quantos km percorridos: '))
d = float(input('Quantos dias alugado: '))
pago = (d * 60) + (km * 0.15)
print('o total a pagar: r$ {} '.format(pago))
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km = float(input('Quantos km percorridos: '))
d = float(input('Quantos dias alugado: '))
pago = d * 60 + km * 0.15
print('o total a pagar: r$ {} '.format(pago))
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username ="username" #your reddit username
password = "password" #your reddit password
client_id = "personal use script" #your personal use script
client_secret = "secret" #your secret
|
username = 'username'
password = 'password'
client_id = 'personal use script'
client_secret = 'secret'
|
# Solution for day2 of advent of code
origValues = list(map(int, open('day2/input.txt').readline().rstrip().split(',')))
print(origValues)
def getOpCode(values, codeAndArgumentWidth, numberOfCodesEvaluated):
currentOpCodeIndex = getCurrentOpCodeIndex(values, codeAndArgumentWidth, numberOfCodesEvaluated)
return int(values[currentOpCodeIndex])
def addOperation(values, opCodeIndex):
operant1 = int(values[values[opCodeIndex+1]])
operant2 = int(values[values[opCodeIndex+2]])
values[values[opCodeIndex+3]] = operant1 + operant2
def multiplyOperation(values, opCodeIndex):
operant1 = int(values[valuesPart1[opCodeIndex+1]])
operant2 = int(values[valuesPart1[opCodeIndex+2]])
values[values[opCodeIndex+3]] = operant1 * operant2
def getCurrentOpCodeIndex(values, codeAndArgumentWidth, numberOfCodesEvaluated):
"""Computes the current opCode index"""
return codeAndArgumentWidth * numberOfCodesEvaluated
def getResult(values):
"""Calculates the result for the memory operations"""
numberOfCodesEvaluated = 0
codeAndArgumentWidth = 4
haltCodeFound = False
while not haltCodeFound:
opCode = getOpCode(values, codeAndArgumentWidth, numberOfCodesEvaluated)
#print("Current opCode: " + str(opCode))
if(opCode == 1):
#print("add operation")
addOperation(values, getCurrentOpCodeIndex(values, codeAndArgumentWidth, numberOfCodesEvaluated))
elif(opCode == 2):
#print("multiply operation")
multiplyOperation(values, getCurrentOpCodeIndex(values, codeAndArgumentWidth,numberOfCodesEvaluated))
elif(opCode == 99):
#print("HALT found")
haltCodeFound = True
else:
print("ERROR unknown opcode found: " + str(opCode) + " for opCodeIndex: " + str(getCurrentOpCodeIndex(values, codeAndArgumentWidth, numberOfCodesEvaluated)))
return -1
numberOfCodesEvaluated += 1
return values[0]
valuesPart1 = origValues.copy()
valuesPart1[1] = 12
valuesPart1[2] = 2
resultPart1 = getResult(valuesPart1)
print("Result of part1: " + str(valuesPart1[0]))
assert 5098658 == resultPart1
# part2
# Initialize
valuesPart2 = origValues.copy()
noun = 0
verb = 0
desiredOutput = 19690720
desiredOutputFound = False
while not desiredOutputFound:
# print("Noun: " + str(noun) + " -- Verb: " + str(verb))
valuesPart2[1] = noun
valuesPart2[2] = verb
currentResult = getResult(valuesPart2)
if(currentResult < 0):
print("Found unknown opcode ==> FAIL")
break
if currentResult == desiredOutput:
desiredOutputFound = True
else:
# keep guessing the verb & noun
if verb >= 99:
noun += 1
verb = 0
else:
verb += 1
# reset the "memory"
valuesPart2 = origValues.copy()
print("Result part2: " + str(100 * valuesPart2[1] + valuesPart2[2]))
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orig_values = list(map(int, open('day2/input.txt').readline().rstrip().split(',')))
print(origValues)
def get_op_code(values, codeAndArgumentWidth, numberOfCodesEvaluated):
current_op_code_index = get_current_op_code_index(values, codeAndArgumentWidth, numberOfCodesEvaluated)
return int(values[currentOpCodeIndex])
def add_operation(values, opCodeIndex):
operant1 = int(values[values[opCodeIndex + 1]])
operant2 = int(values[values[opCodeIndex + 2]])
values[values[opCodeIndex + 3]] = operant1 + operant2
def multiply_operation(values, opCodeIndex):
operant1 = int(values[valuesPart1[opCodeIndex + 1]])
operant2 = int(values[valuesPart1[opCodeIndex + 2]])
values[values[opCodeIndex + 3]] = operant1 * operant2
def get_current_op_code_index(values, codeAndArgumentWidth, numberOfCodesEvaluated):
"""Computes the current opCode index"""
return codeAndArgumentWidth * numberOfCodesEvaluated
def get_result(values):
"""Calculates the result for the memory operations"""
number_of_codes_evaluated = 0
code_and_argument_width = 4
halt_code_found = False
while not haltCodeFound:
op_code = get_op_code(values, codeAndArgumentWidth, numberOfCodesEvaluated)
if opCode == 1:
add_operation(values, get_current_op_code_index(values, codeAndArgumentWidth, numberOfCodesEvaluated))
elif opCode == 2:
multiply_operation(values, get_current_op_code_index(values, codeAndArgumentWidth, numberOfCodesEvaluated))
elif opCode == 99:
halt_code_found = True
else:
print('ERROR unknown opcode found: ' + str(opCode) + ' for opCodeIndex: ' + str(get_current_op_code_index(values, codeAndArgumentWidth, numberOfCodesEvaluated)))
return -1
number_of_codes_evaluated += 1
return values[0]
values_part1 = origValues.copy()
valuesPart1[1] = 12
valuesPart1[2] = 2
result_part1 = get_result(valuesPart1)
print('Result of part1: ' + str(valuesPart1[0]))
assert 5098658 == resultPart1
values_part2 = origValues.copy()
noun = 0
verb = 0
desired_output = 19690720
desired_output_found = False
while not desiredOutputFound:
valuesPart2[1] = noun
valuesPart2[2] = verb
current_result = get_result(valuesPart2)
if currentResult < 0:
print('Found unknown opcode ==> FAIL')
break
if currentResult == desiredOutput:
desired_output_found = True
else:
if verb >= 99:
noun += 1
verb = 0
else:
verb += 1
values_part2 = origValues.copy()
print('Result part2: ' + str(100 * valuesPart2[1] + valuesPart2[2]))
|
site = 'ftp.skilldrick.co.uk'
webRoot = '/public_html'
localDir = '.' #by default use current directory
remoteDir = 'tmpl'
ignoreDirs = ['.git', 'fancybox', 'safeinc']
ignoreFileSuffixes = ['.py', '.pyc', '~', '#', '.swp',
'.gitignore', '.lastrun',
'Makefile', '.bat', 'Thumbs.db', 'README.markdown']
|
site = 'ftp.skilldrick.co.uk'
web_root = '/public_html'
local_dir = '.'
remote_dir = 'tmpl'
ignore_dirs = ['.git', 'fancybox', 'safeinc']
ignore_file_suffixes = ['.py', '.pyc', '~', '#', '.swp', '.gitignore', '.lastrun', 'Makefile', '.bat', 'Thumbs.db', 'README.markdown']
|
async def m001_initial(db):
"""
Initial lnurlpos table.
"""
await db.execute(
f"""
CREATE TABLE lnurlpos.lnurlposs (
id TEXT NOT NULL PRIMARY KEY,
key TEXT NOT NULL,
title TEXT NOT NULL,
wallet TEXT NOT NULL,
currency TEXT NOT NULL,
timestamp TIMESTAMP NOT NULL DEFAULT {db.timestamp_now}
);
"""
)
await db.execute(
f"""
CREATE TABLE lnurlpos.lnurlpospayment (
id TEXT NOT NULL PRIMARY KEY,
posid TEXT NOT NULL,
payhash TEXT,
payload TEXT NOT NULL,
pin INT,
sats INT,
timestamp TIMESTAMP NOT NULL DEFAULT {db.timestamp_now}
);
"""
)
|
async def m001_initial(db):
"""
Initial lnurlpos table.
"""
await db.execute(f'\n CREATE TABLE lnurlpos.lnurlposs (\n id TEXT NOT NULL PRIMARY KEY,\n key TEXT NOT NULL,\n title TEXT NOT NULL,\n wallet TEXT NOT NULL,\n currency TEXT NOT NULL,\n timestamp TIMESTAMP NOT NULL DEFAULT {db.timestamp_now}\n );\n ')
await db.execute(f'\n CREATE TABLE lnurlpos.lnurlpospayment (\n id TEXT NOT NULL PRIMARY KEY,\n posid TEXT NOT NULL,\n payhash TEXT,\n payload TEXT NOT NULL,\n pin INT,\n sats INT, \n timestamp TIMESTAMP NOT NULL DEFAULT {db.timestamp_now}\n );\n ')
|
class Node:
def __init__(self, data):
self.data = data
self.next = None
class CircularLinkedList:
def __init__(self):
self.head = None
self.tail = None
self.length = 0
def append(self, data):
new_node = Node(data)
if not self.head:
self.head = new_node
self.head.next = self.head
else:
curr_node = self.head
while curr_node.next != self.head:
curr_node = curr_node.next
curr_node.next = new_node;
new_node.next = self.head
def prepend(self, data):
new_node = Node(data)
curr_node = self.head
new_node.next = self.head
if not self.head:
new_node.next = self.head
else:
while curr_node.next != self.head:
curr_node = curr_node.next
curr_node.next = new_node
self.head = new_node
def delete(self, key):
if self.head is None:
return
if self.head.next == self.head and self.head.data == key:
self.head = None
elif self.head.data == key:
curr_node = self.head
while curr_node.next != self.head:
curr_node = curr_node.next
curr_node.next = self.head.next
self.head = self.head.next
else:
curr_node = self.head
prev = None
while curr_node.next != self.head:
prev = curr_node
curr_node = curr_node.next
# print('ss',curr_node.data)
if curr_node.data == key:
prev.next = curr_node.next
curr_node = curr_node.next
def lookup(self):
curr_node = self.head
while curr_node:
print(curr_node.data)
curr_node = curr_node.next
if curr_node == self.head:
break
circularLls = CircularLinkedList()
# circularLls.append(1)
# circularLls.append(2)
# circularLls.append(3)
# circularLls.append(4)
# circularLls.prepend(0)
# circularLls.prepend(-1)
circularLls.delete(1)
circularLls.lookup()
|
class Node:
def __init__(self, data):
self.data = data
self.next = None
class Circularlinkedlist:
def __init__(self):
self.head = None
self.tail = None
self.length = 0
def append(self, data):
new_node = node(data)
if not self.head:
self.head = new_node
self.head.next = self.head
else:
curr_node = self.head
while curr_node.next != self.head:
curr_node = curr_node.next
curr_node.next = new_node
new_node.next = self.head
def prepend(self, data):
new_node = node(data)
curr_node = self.head
new_node.next = self.head
if not self.head:
new_node.next = self.head
else:
while curr_node.next != self.head:
curr_node = curr_node.next
curr_node.next = new_node
self.head = new_node
def delete(self, key):
if self.head is None:
return
if self.head.next == self.head and self.head.data == key:
self.head = None
elif self.head.data == key:
curr_node = self.head
while curr_node.next != self.head:
curr_node = curr_node.next
curr_node.next = self.head.next
self.head = self.head.next
else:
curr_node = self.head
prev = None
while curr_node.next != self.head:
prev = curr_node
curr_node = curr_node.next
if curr_node.data == key:
prev.next = curr_node.next
curr_node = curr_node.next
def lookup(self):
curr_node = self.head
while curr_node:
print(curr_node.data)
curr_node = curr_node.next
if curr_node == self.head:
break
circular_lls = circular_linked_list()
circularLls.delete(1)
circularLls.lookup()
|
n = 8
if n%2==0 and (n in range(2,6) or n>20 ):
print ("Not Weird")
else:
print ("Weird")
|
n = 8
if n % 2 == 0 and (n in range(2, 6) or n > 20):
print('Not Weird')
else:
print('Weird')
|
routes = Blueprint("routes", __name__, template_folder="templates")
if not os.path.exists(os.path.dirname(recipyGui.config.get("tinydb"))):
os.mkdir(os.path.dirname(recipyGui.config.get("tinydb")))
@recipyGui.route("/")
def index():
form = SearchForm()
query = request.args.get("query", "").strip()
escaped_query = re.escape(query) if query else query
db = utils.open_or_create_db()
runs = search_database(db, query=escaped_query)
runs = [_change_date(r) for r in runs]
runs = sorted(runs, key=lambda x: x["date"], reverse=True)
run_ids = []
for run in runs:
if "notes" in run.keys():
run["notes"] = str(escape(run["notes"]))
run_ids.append(run.eid)
db.close()
return render_template("list.html", runs=runs, query=escaped_query, search_bar_query=query, form=form, run_ids=str(run_ids), dbfile=recipyGui.config.get("tinydb"))
@recipyGui.route("/run_details")
def run_details():
form = SearchForm()
annotateRunForm = AnnotateRunForm()
query = request.args.get("query", "")
run_id = int(request.args.get("id"))
db = utils.open_or_create_db()
r = db.get(eid=run_id)
if r is not None:
diffs = db.table("filediffs").search(Query().run_id == run_id)
else:
flash("Run not found.", "danger")
diffs = []
r = _change_date(r)
db.close()
return render_template("details.html", query=query, form=form, annotateRunForm=annotateRunForm, run=r, dbfile=recipyGui.config.get("tinydb"), diffs=diffs)
@recipyGui.route("/latest_run")
def latest_run():
form = SearchForm()
annotateRunForm = AnnotateRunForm()
db = utils.open_or_create_db()
r = get_latest_run()
if r is not None:
diffs = db.table("filediffs").search(Query().run_id == r.eid)
else:
flash("No latest run (database is empty).", "danger")
diffs = []
r = _change_date(r)
db.close()
return render_template("details.html", query="", form=form, run=r, annotateRunForm=annotateRunForm, dbfile=recipyGui.config.get("tinydb"), diffs=diffs, active_page="latest_run")
@recipyGui.route("/annotate", methods=["POST"])
def annotate():
notes = request.form["notes"]
run_id = int(request.form["run_id"])
query = request.args.get("query", "")
db = utils.open_or_create_db()
db.update({"notes": notes}, eids=[run_id])
db.close()
return redirect(url_for("run_details", id=run_id, query=query))
@recipyGui.route("/runs2json", methods=["POST"])
def runs2json():
run_ids = literal_eval(request.form["run_ids"])
db = db = utils.open_or_create_db()
runs = [db.get(eid=run_id) for run_id in run_ids]
db.close()
response = make_response(dumps(runs, indent=2, sort_keys=True, default=unicode))
response.headers["content-type"] = "application/json"
response.headers["Content-Disposition"] = "attachment; filename=runs.json"
return response
@recipyGui.route("/patched_modules")
def patched_modules():
db = utils.open_or_create_db()
modules = db.table("patches").all()
db.close()
form = SearchForm()
return render_template("patched_modules.html", form=form, active_page="patched_modules", modules=modules, dbfile=recipyGui.config.get("tinydb"))
|
routes = blueprint('routes', __name__, template_folder='templates')
if not os.path.exists(os.path.dirname(recipyGui.config.get('tinydb'))):
os.mkdir(os.path.dirname(recipyGui.config.get('tinydb')))
@recipyGui.route('/')
def index():
form = search_form()
query = request.args.get('query', '').strip()
escaped_query = re.escape(query) if query else query
db = utils.open_or_create_db()
runs = search_database(db, query=escaped_query)
runs = [_change_date(r) for r in runs]
runs = sorted(runs, key=lambda x: x['date'], reverse=True)
run_ids = []
for run in runs:
if 'notes' in run.keys():
run['notes'] = str(escape(run['notes']))
run_ids.append(run.eid)
db.close()
return render_template('list.html', runs=runs, query=escaped_query, search_bar_query=query, form=form, run_ids=str(run_ids), dbfile=recipyGui.config.get('tinydb'))
@recipyGui.route('/run_details')
def run_details():
form = search_form()
annotate_run_form = annotate_run_form()
query = request.args.get('query', '')
run_id = int(request.args.get('id'))
db = utils.open_or_create_db()
r = db.get(eid=run_id)
if r is not None:
diffs = db.table('filediffs').search(query().run_id == run_id)
else:
flash('Run not found.', 'danger')
diffs = []
r = _change_date(r)
db.close()
return render_template('details.html', query=query, form=form, annotateRunForm=annotateRunForm, run=r, dbfile=recipyGui.config.get('tinydb'), diffs=diffs)
@recipyGui.route('/latest_run')
def latest_run():
form = search_form()
annotate_run_form = annotate_run_form()
db = utils.open_or_create_db()
r = get_latest_run()
if r is not None:
diffs = db.table('filediffs').search(query().run_id == r.eid)
else:
flash('No latest run (database is empty).', 'danger')
diffs = []
r = _change_date(r)
db.close()
return render_template('details.html', query='', form=form, run=r, annotateRunForm=annotateRunForm, dbfile=recipyGui.config.get('tinydb'), diffs=diffs, active_page='latest_run')
@recipyGui.route('/annotate', methods=['POST'])
def annotate():
notes = request.form['notes']
run_id = int(request.form['run_id'])
query = request.args.get('query', '')
db = utils.open_or_create_db()
db.update({'notes': notes}, eids=[run_id])
db.close()
return redirect(url_for('run_details', id=run_id, query=query))
@recipyGui.route('/runs2json', methods=['POST'])
def runs2json():
run_ids = literal_eval(request.form['run_ids'])
db = db = utils.open_or_create_db()
runs = [db.get(eid=run_id) for run_id in run_ids]
db.close()
response = make_response(dumps(runs, indent=2, sort_keys=True, default=unicode))
response.headers['content-type'] = 'application/json'
response.headers['Content-Disposition'] = 'attachment; filename=runs.json'
return response
@recipyGui.route('/patched_modules')
def patched_modules():
db = utils.open_or_create_db()
modules = db.table('patches').all()
db.close()
form = search_form()
return render_template('patched_modules.html', form=form, active_page='patched_modules', modules=modules, dbfile=recipyGui.config.get('tinydb'))
|
class Solution:
def getIntersectionNode(self, headA: ListNode, headB: ListNode) -> Optional[ListNode]:
a = headA
b = headB
while a != b:
if a: a = a.next
else: a = headB
if b: b = b.next
else: b = headA
return a
|
class Solution:
def get_intersection_node(self, headA: ListNode, headB: ListNode) -> Optional[ListNode]:
a = headA
b = headB
while a != b:
if a:
a = a.next
else:
a = headB
if b:
b = b.next
else:
b = headA
return a
|
def reformat(string):
string = string.replace('-', '').replace('(', '').replace(')', '')
return string[-10:] if len(string) > 7 else '495' + string[-7:]
n = 4
notes = [input() for i in range(n)]
for note in notes[1:]:
print('YES' if reformat(notes[0]) == reformat(note) else 'NO')
|
def reformat(string):
string = string.replace('-', '').replace('(', '').replace(')', '')
return string[-10:] if len(string) > 7 else '495' + string[-7:]
n = 4
notes = [input() for i in range(n)]
for note in notes[1:]:
print('YES' if reformat(notes[0]) == reformat(note) else 'NO')
|
class SQLiteQueryResultSpy(object):
def __init__(self, row_count, lazy_result):
self.row_count = row_count
self.number_of_elements = row_count
self.lazy_result = lazy_result
@property
def rowcount(self):
return self.row_count
def fetchone(self):
self.number_of_elements -= 1
if self.number_of_elements < 0:
return None
return self.lazy_result()
|
class Sqlitequeryresultspy(object):
def __init__(self, row_count, lazy_result):
self.row_count = row_count
self.number_of_elements = row_count
self.lazy_result = lazy_result
@property
def rowcount(self):
return self.row_count
def fetchone(self):
self.number_of_elements -= 1
if self.number_of_elements < 0:
return None
return self.lazy_result()
|
def odeeuler(F,x0,y0,h,N):
x = x0
y = y0
for i in range(1,N+1):
y += h*F(x,y)
x += h
return y
|
def odeeuler(F, x0, y0, h, N):
x = x0
y = y0
for i in range(1, N + 1):
y += h * f(x, y)
x += h
return y
|
"""Functions to get all the book's information."""
def get_title(soup_object: object) -> str:
"""Return book title."""
return soup_object.find("h1").text
def get_universal_product_code(product_information_table: list) -> str:
"""Return book UPC."""
return product_information_table[0].text
def get_price_including_tax(product_information_table: list) -> str:
"""Return book price including tax."""
return product_information_table[3].text
def get_price_excluding_tax(product_information_table: list) -> str:
"""Return book price excluding tax."""
return product_information_table[2].text
def get_number_available(product_information_table: list) -> str:
"""Return number of books available."""
number = product_information_table[5].text
return "".join([character for character in number if character.isdigit()])
def get_product_description(soup_object: object) -> str:
"""Return book description."""
if soup_object.find("div", {"id": "product_description"}) != None:
description = (
soup_object.find("article", {"class": "product_page"}).findAll("p")[3].text
)
else:
description = "No description yet."
return description.replace(";", ",")
def get_category(soup_object: object) -> str:
"""Return book category."""
return soup_object.find("ul", {"class": "breadcrumb"}).findAll("a")[2].text
def get_review_rating(soup_object: object) -> str:
"""Return book review rating."""
return soup_object.find("p", {"class": "star-rating"})["class"][1]
def get_image_url(soup_object: object) -> str:
"""Return book image url."""
image_url = soup_object.find("img")["src"]
return image_url.replace("../..", "https://books.toscrape.com/")
|
"""Functions to get all the book's information."""
def get_title(soup_object: object) -> str:
"""Return book title."""
return soup_object.find('h1').text
def get_universal_product_code(product_information_table: list) -> str:
"""Return book UPC."""
return product_information_table[0].text
def get_price_including_tax(product_information_table: list) -> str:
"""Return book price including tax."""
return product_information_table[3].text
def get_price_excluding_tax(product_information_table: list) -> str:
"""Return book price excluding tax."""
return product_information_table[2].text
def get_number_available(product_information_table: list) -> str:
"""Return number of books available."""
number = product_information_table[5].text
return ''.join([character for character in number if character.isdigit()])
def get_product_description(soup_object: object) -> str:
"""Return book description."""
if soup_object.find('div', {'id': 'product_description'}) != None:
description = soup_object.find('article', {'class': 'product_page'}).findAll('p')[3].text
else:
description = 'No description yet.'
return description.replace(';', ',')
def get_category(soup_object: object) -> str:
"""Return book category."""
return soup_object.find('ul', {'class': 'breadcrumb'}).findAll('a')[2].text
def get_review_rating(soup_object: object) -> str:
"""Return book review rating."""
return soup_object.find('p', {'class': 'star-rating'})['class'][1]
def get_image_url(soup_object: object) -> str:
"""Return book image url."""
image_url = soup_object.find('img')['src']
return image_url.replace('../..', 'https://books.toscrape.com/')
|
REQUEST_LAUNCH_MSG = "Hello, I'm Otto Investment bot, I' here to inform you about your investments. Do you want me to tell you a report on your portfolio? Or maybe information about specific stock? "
REQUEST_LAUNCH_REPROMPT = "Go on, tell me what can I do for you."
REQUEST_END_MSG = "Bye bye. "
# General
INTENT_GENERAL_OK = "Ok then."
INTENT_GENERAL_REPROMPT = "Is there something else I can help you with?"
# Help
INTENT_HELP = "Looks like you are confused. You can ask about a stock price, market cap of a company, add and remove stocks from virtual portfolio. Get a performance report on your portfolio. You can also get an investing term explained or a investing strategy. You can even ask bout the news regarding a traded company. What would like to do?"
# Price
INTENT_STOCK_PRICE_MSG = "The price of {0} is ${1}."
INTENT_STOCK_PRICE_MSG_FAIL = "Sorry, there was a problem getting data for {}"
# Market Cap
INTENT_MARKET_CAP_MSG = "The Market Cap of {0} is ${1}."
INTENT_MARKET_CAP_MSG_FAIL = "Sorry, there was a problem getting market capitalization for {}"
# Investing Strategy
INTENT_INVEST_STRAT_MSG = "Here is a example of investing strategy, this one is called {}. {}"
# Watchlist
INTENT_WATCHLIST_REPORT_TOP_STOCK = "The best performing stock is {} which is {} {:.2f}%. "
INTENT_WATCHLIST_REPORT_WORST_STOCK = "The worst performing stock is {} which is {} {:.2f}%. "
INTENT_WATCHLIST_REPORT_MSG_INTRO = "Here is your watchlist:"
INTENT_WATCHLIST_REPORT_MSG_BODY = " Stock {} is {} {:.2f}%. "
INTENT_WATCHLIST_EMPTY_MSG = "Your watchlist is empty. "
INTENT_ADD_TO_WATCHLIST_ASK_CONFIRMATION = "Should I add stock {}? "
INTENT_ADD_TO_WATCHLIST_DENIED = "Ok, not adding it. "
INTENT_ADD_TO_WATCHLIST_CONFIRMED = "Ok, adding {} to watchlist. "
INTENT_ADDED_TO_WATCHLIST = "Stock {} was added to watchlist. "
INTENT_ADDED_TO_WATCHLIST_EXISTS = "Stock {} is already in your watchlist. "
INTENT_ADDED_TO_WATCHLIST_FAIL = "Couldn't add stock to watchlist. "
INTENT_REMOVE_FROM_WATCHLIST_ASK_CONFIRMATION = "Should I remove {}? "
INTENT_REMOVE_FROM_WATCHLIST_DENIED = "Ok, not removing it. "
INTENT_REMOVE_FROM_WATCHLIST_CONFIRMED = "Ok, removing {} from watchlist. "
INTENT_REMOVE_FROM_WATCHLIST_NOT_THERE = "There is no stock {} in your watchlist. "
INTENT_REMOVE_FROM_WATCHLIST_FAIL = "Couldn't remove stock from watchlist. "
# Education
INTENT_EDU_IN_CONSTRUCTION = "Can't explain {} right now."
# News
INTENT_NEWS_ABOUT_COMPANY_INTRO = "Here are some articles mentioning {}: "
INTENT_NEWS_ABOUT_COMPANY_ASK_MORE_INFO = "Should I send you a link to one of the articles? "
INTENT_NEWS_ABOUT_COMPANY_ASK_ARTICLE_NO = "Which one? "
INTENT_NEWS_ABOUT_COMPANY_FAIL_ARTICLE_NOT_FOUND = "Sorry, couldn't find this article. "
INTENT_NEWS_ABOUT_COMPANY_ARTICLE_SENT = "Article was sent to your device. "
INTENT_NEWS_ABOUT_COMPANY_ARTICLE_CARD_TITLE = "Article about {}"
INTENT_NEWS_ABOUT_COMPANY_ARTICLE_CARD_CONTENT = "{}"
# Analytics recommendation
INTENT_RCMD_NO_RCMD = "There is no analyst recommendation for this stock."
INTENT_RCMD_STRONG_BUY = "The analysts are strongly suggesting to buy this stock."
INTENT_RCMD_BUY = "The analysts are suggesting to consider buying this stock."
INTENT_RCMD_OPT_HOLD = "The analysts are somewhat optimistic, they are torn between holding or even buying this stock."
INTENT_RCMD_HOLD = "The analysts suggest not making any decisions just yet, you should hold to this stock."
INTENT_RCMD_PES_HOLD = "The analysts are worried about this one, they suggest holding, whit some intentions to selling."
INTENT_RCMD_SELL = "The stock has been underperforming, analysts suggest considering selling."
INTENT_RCMD_STRONG_SELL = "The analysts strongly suggest selling this stock."
# Error states
ERROR_NOT_AUTHENTICATED = "First you need to authenticate in the Alexa App."
ERROR_NOT_AUTHENTICATED_REPROMPT = "Please go to the Alexa App and link your Facebook account to use this feature."
ERROR_CANT_ADD_TO_WATCHLIST = "Sorry, I wasn't able to add stock {} to watchlist."
ERROR_NEWS_BAD_TICKER = "Sorry it is not possible to get news for this company."
ERROR_NEWS_NO_NEWS = "Sorry, there are now news for company {}"
|
request_launch_msg = "Hello, I'm Otto Investment bot, I' here to inform you about your investments. Do you want me to tell you a report on your portfolio? Or maybe information about specific stock? "
request_launch_reprompt = 'Go on, tell me what can I do for you.'
request_end_msg = 'Bye bye. '
intent_general_ok = 'Ok then.'
intent_general_reprompt = 'Is there something else I can help you with?'
intent_help = 'Looks like you are confused. You can ask about a stock price, market cap of a company, add and remove stocks from virtual portfolio. Get a performance report on your portfolio. You can also get an investing term explained or a investing strategy. You can even ask bout the news regarding a traded company. What would like to do?'
intent_stock_price_msg = 'The price of {0} is ${1}.'
intent_stock_price_msg_fail = 'Sorry, there was a problem getting data for {}'
intent_market_cap_msg = 'The Market Cap of {0} is ${1}.'
intent_market_cap_msg_fail = 'Sorry, there was a problem getting market capitalization for {}'
intent_invest_strat_msg = 'Here is a example of investing strategy, this one is called {}. {}'
intent_watchlist_report_top_stock = 'The best performing stock is {} which is {} {:.2f}%. '
intent_watchlist_report_worst_stock = 'The worst performing stock is {} which is {} {:.2f}%. '
intent_watchlist_report_msg_intro = 'Here is your watchlist:'
intent_watchlist_report_msg_body = ' Stock {} is {} {:.2f}%. '
intent_watchlist_empty_msg = 'Your watchlist is empty. '
intent_add_to_watchlist_ask_confirmation = 'Should I add stock {}? '
intent_add_to_watchlist_denied = 'Ok, not adding it. '
intent_add_to_watchlist_confirmed = 'Ok, adding {} to watchlist. '
intent_added_to_watchlist = 'Stock {} was added to watchlist. '
intent_added_to_watchlist_exists = 'Stock {} is already in your watchlist. '
intent_added_to_watchlist_fail = "Couldn't add stock to watchlist. "
intent_remove_from_watchlist_ask_confirmation = 'Should I remove {}? '
intent_remove_from_watchlist_denied = 'Ok, not removing it. '
intent_remove_from_watchlist_confirmed = 'Ok, removing {} from watchlist. '
intent_remove_from_watchlist_not_there = 'There is no stock {} in your watchlist. '
intent_remove_from_watchlist_fail = "Couldn't remove stock from watchlist. "
intent_edu_in_construction = "Can't explain {} right now."
intent_news_about_company_intro = 'Here are some articles mentioning {}: '
intent_news_about_company_ask_more_info = 'Should I send you a link to one of the articles? '
intent_news_about_company_ask_article_no = 'Which one? '
intent_news_about_company_fail_article_not_found = "Sorry, couldn't find this article. "
intent_news_about_company_article_sent = 'Article was sent to your device. '
intent_news_about_company_article_card_title = 'Article about {}'
intent_news_about_company_article_card_content = '{}'
intent_rcmd_no_rcmd = 'There is no analyst recommendation for this stock.'
intent_rcmd_strong_buy = 'The analysts are strongly suggesting to buy this stock.'
intent_rcmd_buy = 'The analysts are suggesting to consider buying this stock.'
intent_rcmd_opt_hold = 'The analysts are somewhat optimistic, they are torn between holding or even buying this stock.'
intent_rcmd_hold = 'The analysts suggest not making any decisions just yet, you should hold to this stock.'
intent_rcmd_pes_hold = 'The analysts are worried about this one, they suggest holding, whit some intentions to selling.'
intent_rcmd_sell = 'The stock has been underperforming, analysts suggest considering selling.'
intent_rcmd_strong_sell = 'The analysts strongly suggest selling this stock.'
error_not_authenticated = 'First you need to authenticate in the Alexa App.'
error_not_authenticated_reprompt = 'Please go to the Alexa App and link your Facebook account to use this feature.'
error_cant_add_to_watchlist = "Sorry, I wasn't able to add stock {} to watchlist."
error_news_bad_ticker = 'Sorry it is not possible to get news for this company.'
error_news_no_news = 'Sorry, there are now news for company {}'
|
# -*- coding: utf-8 -*-
"""
Created on Sat Feb 13 20:04:51 2021
@author: Charissa
"""
'''
==================================
Queue
==================================
'''
class QNode:
def __init__(self, data):
self.data = data
self.next = None
class Queue:
def __init__(self):
self.front = None
self.rear = None
self.size = 0
def enqueue(self, data):
'''
enqueue elements at the rear of the list
Parameters
----------
element :
element that is to be added at the rear of the queue
'''
newNode = QNode(data)
if self.front == None and self.rear == None:
self.front=newNode
self.rear=newNode
else:
self.rear.next = newNode
self.rear = newNode
self.size += 1
def dequeue(self):
'''
dequeues the front element
Returns
-------
Error message only if there is None elements in the queue
data:
data that was removed
'''
if (self.front == None) and (self.rear == None):
return print("Error Occurred, no element in queue to dequeue please try again.")
else:
data = self.front.data
self.front = self.front.next
if self.front == None:
self.rear = None
self.size -= 1
return data
def printQueue(self):
queuelist = []
curr = self.front
while curr:
queuelist.append(curr.data)
curr = curr.next
print(queuelist)
'''
================================================
Binary Search Tree
================================================
'''
class BSTNode:
def __init__(self,data):
self.data = data
self.leftchild = None
self.rightchild = None
class BinarySearchTree:
def __init__(self):
self.root = None
self.size = 0
def insert(self, data):
'''
Parameters
----------
data : float
the float to be added to the binary search tree
Returns
-------
self.data: bst
returns the updated bst
'''
newNode = BSTNode(data)
if self.root == None:
self.root = newNode
self.size +=1
return
else:
curr = self.root
while curr:
if newNode.data == curr.data:
return
elif newNode.data > curr.data:
if curr.rightchild != None:
curr = curr.rightchild
else:
curr.rightchild = newNode
else:
if curr.leftchild != None:
curr = curr.leftchild
else:
curr.leftchild = newNode
self.size+=1
return
def inordertraversal(self,root):
'''
generates inorder traversal of binary search tree
Parameters
----------
root : Nodes
Nodes of binary search tree
Returns
-------
root : Node
return inorder traversal of binary search tree
'''
if root != None:
self.inordertraversal(root.leftchild)
print(root.data)
self.inordertraversal(root.rightchild)
else:
return self.root
def minval(node):
'''
Find the current reference to node of minimum value
Parameters
----------
node : Node
Returns
-------
curr : reference
current reference to node of minimum value
'''
curr = node
while curr.leftchild != None:
curr = curr.leftchild
return curr
def search(self,key):
'''
binary search for an element
Parameters
----------
root : Nodes of BST
key : Integer
intgere to be found in BST
Returns
-------
key :Integer
returns key if found
'''
if self.root.data == None or self.root.data == key:
return self.root.data
if self.root.data < key:
return self.search(self.root.rightchild,key)
else:
return self.search(self.root.leftchild,key)
def delete(self,root,node):
'''
delete an element form BST
Parameters
----------
root : Nodes of bst
node : Node
Node for which to be deleted
Returns
-------
root
BST excluding deleted element
'''
if self.root.data != None:
if self.root.data > node:
self.root.leftchild = self.delete(self.root.leftchild,node)
elif self.root.data < node:
self.root.rightchild = self.delete(self.root.rightchild,node)
else:
if self.root.leftchild == None:
temp = self.root.rightchild
self.root.data = None
return temp
elif self.root.rightchild == None:
temp = self.root.leftchild
self.root.node = None
return temp
temp = self.minval(self.root.rightchild)
self.root.rightchild = self.delete(self.root.rightchild,temp.data)
return self.root
def levelorderTraversal(self):
'''
generates level order traversal of binary search tree
Returns
-------
result :
generates level order traversal of binary search tree
'''
result = []
myqueue = Queue()
curr = self.root
if curr != None:
myqueue.enqueue(curr)
while myqueue.front:
curr = myqueue.dequeue()
result.append(curr.data)
if curr.leftchild != None:
myqueue.enqueue(curr.leftchild)
if curr.rightchild != None:
myqueue.enqueue(curr.rightchild)
return result
BST = BinarySearchTree()
for i in range(10):
BST.insert(2*i)
print(BST.levelorderTraversal())
print()
print(BST.inordertraversal(BST.root))
|
"""
Created on Sat Feb 13 20:04:51 2021
@author: Charissa
"""
'\n==================================\nQueue\n==================================\n'
class Qnode:
def __init__(self, data):
self.data = data
self.next = None
class Queue:
def __init__(self):
self.front = None
self.rear = None
self.size = 0
def enqueue(self, data):
"""
enqueue elements at the rear of the list
Parameters
----------
element :
element that is to be added at the rear of the queue
"""
new_node = q_node(data)
if self.front == None and self.rear == None:
self.front = newNode
self.rear = newNode
else:
self.rear.next = newNode
self.rear = newNode
self.size += 1
def dequeue(self):
"""
dequeues the front element
Returns
-------
Error message only if there is None elements in the queue
data:
data that was removed
"""
if self.front == None and self.rear == None:
return print('Error Occurred, no element in queue to dequeue please try again.')
else:
data = self.front.data
self.front = self.front.next
if self.front == None:
self.rear = None
self.size -= 1
return data
def print_queue(self):
queuelist = []
curr = self.front
while curr:
queuelist.append(curr.data)
curr = curr.next
print(queuelist)
'\n================================================\nBinary Search Tree\n================================================\n'
class Bstnode:
def __init__(self, data):
self.data = data
self.leftchild = None
self.rightchild = None
class Binarysearchtree:
def __init__(self):
self.root = None
self.size = 0
def insert(self, data):
"""
Parameters
----------
data : float
the float to be added to the binary search tree
Returns
-------
self.data: bst
returns the updated bst
"""
new_node = bst_node(data)
if self.root == None:
self.root = newNode
self.size += 1
return
else:
curr = self.root
while curr:
if newNode.data == curr.data:
return
elif newNode.data > curr.data:
if curr.rightchild != None:
curr = curr.rightchild
else:
curr.rightchild = newNode
elif curr.leftchild != None:
curr = curr.leftchild
else:
curr.leftchild = newNode
self.size += 1
return
def inordertraversal(self, root):
"""
generates inorder traversal of binary search tree
Parameters
----------
root : Nodes
Nodes of binary search tree
Returns
-------
root : Node
return inorder traversal of binary search tree
"""
if root != None:
self.inordertraversal(root.leftchild)
print(root.data)
self.inordertraversal(root.rightchild)
else:
return self.root
def minval(node):
"""
Find the current reference to node of minimum value
Parameters
----------
node : Node
Returns
-------
curr : reference
current reference to node of minimum value
"""
curr = node
while curr.leftchild != None:
curr = curr.leftchild
return curr
def search(self, key):
"""
binary search for an element
Parameters
----------
root : Nodes of BST
key : Integer
intgere to be found in BST
Returns
-------
key :Integer
returns key if found
"""
if self.root.data == None or self.root.data == key:
return self.root.data
if self.root.data < key:
return self.search(self.root.rightchild, key)
else:
return self.search(self.root.leftchild, key)
def delete(self, root, node):
"""
delete an element form BST
Parameters
----------
root : Nodes of bst
node : Node
Node for which to be deleted
Returns
-------
root
BST excluding deleted element
"""
if self.root.data != None:
if self.root.data > node:
self.root.leftchild = self.delete(self.root.leftchild, node)
elif self.root.data < node:
self.root.rightchild = self.delete(self.root.rightchild, node)
else:
if self.root.leftchild == None:
temp = self.root.rightchild
self.root.data = None
return temp
elif self.root.rightchild == None:
temp = self.root.leftchild
self.root.node = None
return temp
temp = self.minval(self.root.rightchild)
self.root.rightchild = self.delete(self.root.rightchild, temp.data)
return self.root
def levelorder_traversal(self):
"""
generates level order traversal of binary search tree
Returns
-------
result :
generates level order traversal of binary search tree
"""
result = []
myqueue = queue()
curr = self.root
if curr != None:
myqueue.enqueue(curr)
while myqueue.front:
curr = myqueue.dequeue()
result.append(curr.data)
if curr.leftchild != None:
myqueue.enqueue(curr.leftchild)
if curr.rightchild != None:
myqueue.enqueue(curr.rightchild)
return result
bst = binary_search_tree()
for i in range(10):
BST.insert(2 * i)
print(BST.levelorderTraversal())
print()
print(BST.inordertraversal(BST.root))
|
# A string index should always be within range
s = "Hello"
print(s[5]) # Syntax error - valid indices for s are 0-4
|
s = 'Hello'
print(s[5])
|
#!/anaconda3/bin/python3.6
# coding=utf-8
if __name__ == "__main__":
print("suppliermgr package")
|
if __name__ == '__main__':
print('suppliermgr package')
|
# encoding: utf-8
# Copyright 2008 California Institute of Technology. ALL RIGHTS
# RESERVED. U.S. Government Sponsorship acknowledged.
'''
EDRN RDF Service: unit and functional tests.
'''
|
"""
EDRN RDF Service: unit and functional tests.
"""
|
with open("input.txt") as input_file:
lines = input_file.readlines()
fish = [int(n) for n in lines[0].split(",")]
print(fish)
for _ in range(80):
fish = [f-1 for f in fish]
zeroes = fish.count(-1)
for i, f in enumerate(fish):
if f == -1:
fish[i] = 6
fish.extend([8]*zeroes)
print(len(fish))
|
with open('input.txt') as input_file:
lines = input_file.readlines()
fish = [int(n) for n in lines[0].split(',')]
print(fish)
for _ in range(80):
fish = [f - 1 for f in fish]
zeroes = fish.count(-1)
for (i, f) in enumerate(fish):
if f == -1:
fish[i] = 6
fish.extend([8] * zeroes)
print(len(fish))
|
def test_first(setup_teardown):
text_logo = setup_teardown.find_element_by_id('logo').text
assert text_logo == 'Your Store'
|
def test_first(setup_teardown):
text_logo = setup_teardown.find_element_by_id('logo').text
assert text_logo == 'Your Store'
|
def calculaMulta (velocidade):
if velocidade > 50 and velocidade < 55:
return 230
elif velocidade > 55 and velocidade <= 60:
return 340
elif velocidade > 60:
valor = (velocidade-50) * 19.28
return valor
else:
return 0
vel = int(input("Informe a velocidade :"))
print(calculaMulta(vel))
|
def calcula_multa(velocidade):
if velocidade > 50 and velocidade < 55:
return 230
elif velocidade > 55 and velocidade <= 60:
return 340
elif velocidade > 60:
valor = (velocidade - 50) * 19.28
return valor
else:
return 0
vel = int(input('Informe a velocidade :'))
print(calcula_multa(vel))
|
class Solution:
def removeElement(self, nums: List[int], val: int) -> int:
for numbers in range(len(nums)):
if val not in nums:
break
if len(nums) == 0:
return 0
else:
nums.remove(val)
print(len(nums))
print ("nums = ",nums)
|
class Solution:
def remove_element(self, nums: List[int], val: int) -> int:
for numbers in range(len(nums)):
if val not in nums:
break
if len(nums) == 0:
return 0
else:
nums.remove(val)
print(len(nums))
print('nums = ', nums)
|
"""
The RequestSupplement object that will get injected on marketplace requests
"""
class RequestSupplement(object):
# adding some duplicate fields keyed to more consistent python naming and
# more understandable naming in some cases. You're free to use whichever
# you want.
EXTRAS = {
'portal_id': 'hub_id',
'app_pageUrl': 'local_url',
'app_callbackUrl': 'local_base_url',
'app_canvasUrl': 'base_url',
}
def __init__(self, request):
super(RequestSupplement,self).__init__()
self.process(request)
def process(self, request):
for k in request.REQUEST:
if k.startswith('hubspot.marketplace.'):
attr = '_'.join(k.split('.')[2:])
val = request.REQUEST.get(k)
if attr.endswith('_id'):
val = long(val)
elif attr.startswith('is_'):
val = val.lower()=='true'
setattr(self, attr, val)
for k in self.__class__.EXTRAS:
if getattr(self,k,None): # they're not all necessarily here (uninstall hook only gives secret and portal_id)
setattr(self,self.__class__.EXTRAS[k],getattr(self,k))
|
"""
The RequestSupplement object that will get injected on marketplace requests
"""
class Requestsupplement(object):
extras = {'portal_id': 'hub_id', 'app_pageUrl': 'local_url', 'app_callbackUrl': 'local_base_url', 'app_canvasUrl': 'base_url'}
def __init__(self, request):
super(RequestSupplement, self).__init__()
self.process(request)
def process(self, request):
for k in request.REQUEST:
if k.startswith('hubspot.marketplace.'):
attr = '_'.join(k.split('.')[2:])
val = request.REQUEST.get(k)
if attr.endswith('_id'):
val = long(val)
elif attr.startswith('is_'):
val = val.lower() == 'true'
setattr(self, attr, val)
for k in self.__class__.EXTRAS:
if getattr(self, k, None):
setattr(self, self.__class__.EXTRAS[k], getattr(self, k))
|
# import matplotlib.pyplot as plt
# Menge an Werten
zahlen = "1203456708948673516874354531568764645"
# Initialisieren der Histogramm Variable
histogramm = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
for index in range(len(zahlen)):
histogramm[int(zahlen[index])] += 1
# plt.hist(histogramm, bins = 9)
# plt.show()
for i in range(0,10):
print("Die Zahl", i, "kommt", histogramm[i], "Mal vor.")
|
zahlen = '1203456708948673516874354531568764645'
histogramm = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
for index in range(len(zahlen)):
histogramm[int(zahlen[index])] += 1
for i in range(0, 10):
print('Die Zahl', i, 'kommt', histogramm[i], 'Mal vor.')
|
#!/usr/bin/env pytho
codigo = {
'A': '.-', 'B': '-...', 'C': '-.-.',
'D': '-..', 'E': '.', 'F': '..-.',
'G': '--.', 'H': '....', 'I': '..',
'J': '.---', 'K': '-.-', 'L': '.-..',
'M': '--', 'N': '-.', 'O': '---',
'P': '.--.', 'Q': '--.-', 'R': '.-.',
'S': '...', 'T': '-', 'U': '..-',
'V': '...-', 'W': '.--', 'X': '-..-',
'Y': '-.--', 'Z': '--..', '1': '.----',
'2': '..---', '3': '...--', '4': '....-',
'5': '.....', '6': '-....', '7': '--...',
'8': '---..', '9': '----.', '0': '-----',
'.': '.-.-.-', ',': '--..--', ':': '---...',
';': '-.-.-.', '?': '..--..', '!': '-.-.--',
'"': '.-..-.', "'": '.----.', '+': '.-.-.',
'-': '-....-', '/': '-..-.', '=': '-...-',
'_': '..--.-', '$': '...-..-', '@': '.--.-.',
'&': '.-...', '(': '-.--.', ')': '-.--.-'
}
palabra = input("Palabra:")
lista_codigos = []
for caracter in palabra:
if caracter.islower():
caracter=caracter.upper()
lista_codigos.append(codigo[caracter])
print (" ".join(lista_codigos))
morse=input("Morse:")
lista_morse=morse.split(" ")
palabra = ""
for cod in lista_morse:
#letra=[key for key,valor in codigo.items() if valor==cod][0]
for key,valor in codigo.items():
if valor == cod:
letra = key
palabra=palabra+letra
print (palabra)
|
codigo = {'A': '.-', 'B': '-...', 'C': '-.-.', 'D': '-..', 'E': '.', 'F': '..-.', 'G': '--.', 'H': '....', 'I': '..', 'J': '.---', 'K': '-.-', 'L': '.-..', 'M': '--', 'N': '-.', 'O': '---', 'P': '.--.', 'Q': '--.-', 'R': '.-.', 'S': '...', 'T': '-', 'U': '..-', 'V': '...-', 'W': '.--', 'X': '-..-', 'Y': '-.--', 'Z': '--..', '1': '.----', '2': '..---', '3': '...--', '4': '....-', '5': '.....', '6': '-....', '7': '--...', '8': '---..', '9': '----.', '0': '-----', '.': '.-.-.-', ',': '--..--', ':': '---...', ';': '-.-.-.', '?': '..--..', '!': '-.-.--', '"': '.-..-.', "'": '.----.', '+': '.-.-.', '-': '-....-', '/': '-..-.', '=': '-...-', '_': '..--.-', '$': '...-..-', '@': '.--.-.', '&': '.-...', '(': '-.--.', ')': '-.--.-'}
palabra = input('Palabra:')
lista_codigos = []
for caracter in palabra:
if caracter.islower():
caracter = caracter.upper()
lista_codigos.append(codigo[caracter])
print(' '.join(lista_codigos))
morse = input('Morse:')
lista_morse = morse.split(' ')
palabra = ''
for cod in lista_morse:
for (key, valor) in codigo.items():
if valor == cod:
letra = key
palabra = palabra + letra
print(palabra)
|
class Cloth:
def __init__(self, name, shop_url, available, brand_logo, price, img_url):
self.name = name
self.shop_url = shop_url
self.available = available
self.brand_logo = brand_logo
self.price = price
self.img_url = img_url
def __str__(self):
print('Name: {0}\nBrand: {1}\nPrice: {2}\nAvailable: {3}, Link to the shop: {4}'.format(self.name, self.brand,
self.price,
self.available,
self.shop_url))
|
class Cloth:
def __init__(self, name, shop_url, available, brand_logo, price, img_url):
self.name = name
self.shop_url = shop_url
self.available = available
self.brand_logo = brand_logo
self.price = price
self.img_url = img_url
def __str__(self):
print('Name: {0}\nBrand: {1}\nPrice: {2}\nAvailable: {3}, Link to the shop: {4}'.format(self.name, self.brand, self.price, self.available, self.shop_url))
|
#!/usr/bin/env python3
"""
The marketing team is spending way too much time typing in hashtags.
Let's help them with our own Hashtag Generator!
Here's the deal:
It must start with a hashtag (#).
All words must have their first letter capitalized.
If the final result is longer than 140 chars it must return false.
If the input or the result is an empty string it must return false.
Examples
" Hello there thanks for trying my Kata" => "#HelloThereThanksForTryingMyKata"
" Hello World " => "#HelloWorld"
"" => false
"""
def execute(s):
s = s.rstrip()
r = False
if 0 == len(s) or 140 < len(s):
return r
r = "#%s" % s.title().replace(' ','')
return r
|
"""
The marketing team is spending way too much time typing in hashtags.
Let's help them with our own Hashtag Generator!
Here's the deal:
It must start with a hashtag (#).
All words must have their first letter capitalized.
If the final result is longer than 140 chars it must return false.
If the input or the result is an empty string it must return false.
Examples
" Hello there thanks for trying my Kata" => "#HelloThereThanksForTryingMyKata"
" Hello World " => "#HelloWorld"
"" => false
"""
def execute(s):
s = s.rstrip()
r = False
if 0 == len(s) or 140 < len(s):
return r
r = '#%s' % s.title().replace(' ', '')
return r
|
def pickingNumbers(a):
solution = 0
for num1 in a:
if a.count(num1) + a.count(num1 + 1) > solution:
solution = a.count(num1) + a.count(num1 + 1)
return solution
|
def picking_numbers(a):
solution = 0
for num1 in a:
if a.count(num1) + a.count(num1 + 1) > solution:
solution = a.count(num1) + a.count(num1 + 1)
return solution
|
# while loops
def nearest_square(limit):
number = 0
while (number+1) ** 2 < limit:
number += 1
return number ** 2
test1 = nearest_square(40)
print("expected result: 36, actual result: {}".format(test1))
# black jack
card_deck = [4, 11, 8, 5, 13, 2, 8, 10]
hand = []
while sum(hand) <= 21:
hand.append(card_deck.pop()) #removes from deck
print(hand)
# headline ticker for news, up to 140 chars
headlines = ["Local Bear Eaten by Man",
"Legislature Announces New Laws",
"Peasant Discovers Violence Inherent in System",
"Cat Rescues Fireman Stuck in Tree",
"Brave Knight Runs Away",
"Papperbok Review: Totally Triffic"]
news_ticker = ""
for headline in headlines:
if len(news_ticker) + len(headline) <= 140:
news_ticker += headline + " "
else:
for letter in headline:
if len(news_ticker) < 140:
news_ticker += letter
else:
break;
print(news_ticker)
# alternative for above, shorter
news_ticker = ""
for headline in headlines:
news_ticker += headline + " "
if len(news_ticker) >= 140: # just take first 140 after creating full
news_ticker = news_ticker[:140]
break;
print(news_ticker)
|
def nearest_square(limit):
number = 0
while (number + 1) ** 2 < limit:
number += 1
return number ** 2
test1 = nearest_square(40)
print('expected result: 36, actual result: {}'.format(test1))
card_deck = [4, 11, 8, 5, 13, 2, 8, 10]
hand = []
while sum(hand) <= 21:
hand.append(card_deck.pop())
print(hand)
headlines = ['Local Bear Eaten by Man', 'Legislature Announces New Laws', 'Peasant Discovers Violence Inherent in System', 'Cat Rescues Fireman Stuck in Tree', 'Brave Knight Runs Away', 'Papperbok Review: Totally Triffic']
news_ticker = ''
for headline in headlines:
if len(news_ticker) + len(headline) <= 140:
news_ticker += headline + ' '
else:
for letter in headline:
if len(news_ticker) < 140:
news_ticker += letter
else:
break
print(news_ticker)
news_ticker = ''
for headline in headlines:
news_ticker += headline + ' '
if len(news_ticker) >= 140:
news_ticker = news_ticker[:140]
break
print(news_ticker)
|
A_1,B_1 = input().split(" ")
a = int(A_1)
b = int(B_1)
if a > b:
horas = (24-a) + b
print("O JOGO DUROU %i HORA(S)"%(horas))
elif a == b:
print("O JOGO DUROU 24 HORA(S)")
else:
horas = b - a
print("O JOGO DUROU %i HORA(S)"%(horas))
|
(a_1, b_1) = input().split(' ')
a = int(A_1)
b = int(B_1)
if a > b:
horas = 24 - a + b
print('O JOGO DUROU %i HORA(S)' % horas)
elif a == b:
print('O JOGO DUROU 24 HORA(S)')
else:
horas = b - a
print('O JOGO DUROU %i HORA(S)' % horas)
|
"""Example of comments within the Hello World package
This is a further elaboration of the docstring. Here, you can
define the details and steps appropriate for the situation.
Code tells you how. Comments tell you why.
args:
name (int): a description of the parameter
name (str): a description of the parameter
returns:
type: a description of what is being returned of type
"""
# Comment preceding a simple print statement to show how the hash works
print("Hello, World!")
|
"""Example of comments within the Hello World package
This is a further elaboration of the docstring. Here, you can
define the details and steps appropriate for the situation.
Code tells you how. Comments tell you why.
args:
name (int): a description of the parameter
name (str): a description of the parameter
returns:
type: a description of what is being returned of type
"""
print('Hello, World!')
|
# https://app.codesignal.com/arcade/code-arcade/well-of-integration/QmK8kHTyKqh8xDoZk
def threeSplit(numbers):
# From a list of numbers, cut into three pieces such that each
# piece contains an integer, and the sum of integers in each
# piece is the same.
# We know that the total sum of elements in the array is divisible by 3.
# So any 3 segments it can be divided into must have sum total/3.
total = sum(numbers)
third = total / 3
# The count of starts, this is, places where it adds to a third.
start_count = 0
# Acum so far of values in the array.
acum_sum = 0
# Result which will hold the amount of ways the array can be split into 3 equally.
result = 0
for idx in range(len(numbers) - 1):
# Keep accumulating values.
acum_sum += numbers[idx]
# A second splitting point is if up to this point it adds to two thirds.
# Checked before the start point for the case in which a third of the total
# is equal to two thirds, because the total added up to 0. Also for a second
# splitting point to be valid, there has to be at least one starting point.
if acum_sum == 2 * third and start_count > 0:
# Any "second splitting point" found will work with any of the previously
# found "starting splitting points", so add up the amount of such points
# found until the current one.
result += start_count
# A starting splitting point is if up to this point it adds up to a third.
if acum_sum == third:
start_count += 1
return result
|
def three_split(numbers):
total = sum(numbers)
third = total / 3
start_count = 0
acum_sum = 0
result = 0
for idx in range(len(numbers) - 1):
acum_sum += numbers[idx]
if acum_sum == 2 * third and start_count > 0:
result += start_count
if acum_sum == third:
start_count += 1
return result
|
def comparator(predicate):
"""Makes a comparator function out of a function that reports whether the first
element is less than the second"""
return lambda a, b: predicate(a, b) * -1 + predicate(b, a) * 1
|
def comparator(predicate):
"""Makes a comparator function out of a function that reports whether the first
element is less than the second"""
return lambda a, b: predicate(a, b) * -1 + predicate(b, a) * 1
|
# https://stackoverflow.com/questions/14485255/vertical-sum-in-a-given-binary-tree
# https://codereview.stackexchange.com/questions/151208/vertical-sum-in-a-given-binary-tree
d = {}
def traverse(node, hd):
if not node:
return
if not hd in d:
d[hd] = 0
d[hd] = d[hd] + node.value
traverse(node.left, hd - 1)
traverse(node.right, hd + 1)
class Node:
def __init__(self, value, left=None, right=None):
self.value = value
self.left = left
self.right = right
"""
1
/ \
2 3
/ \ / \
4 5 6 7
"""
node7 = Node(70)
node6 = Node(60)
node5 = Node(50)
node4 = Node(40)
node3 = Node(3)
node2 = Node(2)
root = Node(1)
root.left = node2
root.right = node3
node2.left = node4
node2.right = node5
node3.left = node6
node3.right = node7
traverse(root, 0)
print(sorted(d.items()))
|
d = {}
def traverse(node, hd):
if not node:
return
if not hd in d:
d[hd] = 0
d[hd] = d[hd] + node.value
traverse(node.left, hd - 1)
traverse(node.right, hd + 1)
class Node:
def __init__(self, value, left=None, right=None):
self.value = value
self.left = left
self.right = right
'\n 1\n / 2 3\n/ \\ / 4 5 6 7\n'
node7 = node(70)
node6 = node(60)
node5 = node(50)
node4 = node(40)
node3 = node(3)
node2 = node(2)
root = node(1)
root.left = node2
root.right = node3
node2.left = node4
node2.right = node5
node3.left = node6
node3.right = node7
traverse(root, 0)
print(sorted(d.items()))
|
conf_my_cnf_xenial = """[mysqld]
bind-address = 0.0.0.0
default-storage-engine = innodb
innodb_file_per_table
max_connections = 4096
collation-server = utf8_general_ci
character-set-server = utf8
innodb_autoinc_lock_mode=2
innodb_flush_log_at_trx_commit=0
innodb_buffer_pool_size=122M
# MariaDB Galera Cluster in Xenial
wsrep_cluster_name="galera_cluster"
wsrep_cluster_address="{{ wsrep_cluster_address }}"
wsrep_node_name="{{ wsrep_node_name }}"
wsrep_node_address="{{ wsrep_node_address }}"
wsrep_provider=/usr/lib/libgalera_smm.so
wsrep_provider_options="pc.recovery=TRUE;gcache.size=300M"
wsrep_sst_method=rsync
binlog_format=ROW
"""
|
conf_my_cnf_xenial = '[mysqld]\nbind-address = 0.0.0.0\ndefault-storage-engine = innodb\ninnodb_file_per_table\nmax_connections = 4096\ncollation-server = utf8_general_ci\ncharacter-set-server = utf8\ninnodb_autoinc_lock_mode=2\ninnodb_flush_log_at_trx_commit=0\ninnodb_buffer_pool_size=122M\n\n# MariaDB Galera Cluster in Xenial\nwsrep_cluster_name="galera_cluster"\nwsrep_cluster_address="{{ wsrep_cluster_address }}"\nwsrep_node_name="{{ wsrep_node_name }}"\nwsrep_node_address="{{ wsrep_node_address }}"\nwsrep_provider=/usr/lib/libgalera_smm.so\nwsrep_provider_options="pc.recovery=TRUE;gcache.size=300M"\nwsrep_sst_method=rsync\nbinlog_format=ROW\n'
|
def elevadorLotado(paradas, capacidade):
energiaGasta = 0
while paradas:
ultimo = paradas[-1]
energiaGasta += 2*ultimo
paradas = paradas[:-capacidade]
return energiaGasta
testes = int(input())
for x in range(testes):
NCM = input().split()
capacidade = int(NCM[1])
destinhos = list(map(int,input().split()))
destinhos.sort()
s = elevadorLotado(destinhos, capacidade)
print(s)
|
def elevador_lotado(paradas, capacidade):
energia_gasta = 0
while paradas:
ultimo = paradas[-1]
energia_gasta += 2 * ultimo
paradas = paradas[:-capacidade]
return energiaGasta
testes = int(input())
for x in range(testes):
ncm = input().split()
capacidade = int(NCM[1])
destinhos = list(map(int, input().split()))
destinhos.sort()
s = elevador_lotado(destinhos, capacidade)
print(s)
|
with open('EN_op_1_57X32A15_31.csv','r') as csvfile:
reader = csv.reader(csvfile)
for row in reader:
print(row[1])
|
with open('EN_op_1_57X32A15_31.csv', 'r') as csvfile:
reader = csv.reader(csvfile)
for row in reader:
print(row[1])
|
class Blosum62:
"""Score matrix BLOSUM62"""
def __init__(self):
self.blosum62 = {
'A': {'A': 4, 'R':-1, 'N':-2, 'D':-2, 'C': 0, 'Q':-1, 'E':-1, 'G': 0, 'H':-2, 'I':-1, 'L':-1, 'K':-1, 'M':-1, 'F':-2, 'P':-1, 'S': 1, 'T': 0, 'W':-3, 'Y':-2, 'V': 0, 'B':-2, 'Z':-1, 'X': 0, '-':-4},
'R': {'A':-1, 'R': 5, 'N': 0, 'D':-2, 'C':-3, 'Q': 1, 'E': 0, 'G':-2, 'H': 0, 'I':-3, 'L':-2, 'K': 2, 'M':-1, 'F':-3, 'P':-2, 'S':-1, 'T':-1, 'W':-3, 'Y':-2, 'V':-3, 'B':-1, 'Z': 0, 'X':-1, '-':-4},
'N': {'A':-2, 'R': 0, 'N': 6, 'D': 1, 'C':-3, 'Q': 0, 'E': 0, 'G': 0, 'H': 1, 'I':-3, 'L':-3, 'K': 0, 'M':-2, 'F':-3, 'P':-2, 'S': 1, 'T': 0, 'W':-4, 'Y':-2, 'V':-3, 'B': 3, 'Z': 0, 'X':-1, '-':-4},
'D': {'A':-2, 'R':-2, 'N': 1, 'D': 6, 'C':-3, 'Q': 0, 'E': 2, 'G':-1, 'H':-1, 'I':-3, 'L':-4, 'K':-1, 'M':-3, 'F':-3, 'P':-1, 'S': 0, 'T':-1, 'W':-4, 'Y':-3, 'V':-3, 'B': 4, 'Z': 1, 'X':-1, '-':-4},
'C': {'A': 0, 'R':-3, 'N':-3, 'D':-3, 'C': 9, 'Q':-3, 'E':-4, 'G':-3, 'H':-3, 'I':-1, 'L':-1, 'K':-3, 'M':-1, 'F':-2, 'P':-3, 'S':-1, 'T':-1, 'W':-2, 'Y':-2, 'V':-1, 'B':-3, 'Z':-3, 'X':-2, '-':-4},
'Q': {'A':-1, 'R': 1, 'N': 0, 'D': 0, 'C':-3, 'Q': 5, 'E': 2, 'G':-2, 'H': 0, 'I':-3, 'L':-2, 'K': 1, 'M': 0, 'F':-3, 'P':-1, 'S': 0, 'T':-1, 'W':-2, 'Y':-1, 'V':-2, 'B': 0, 'Z': 3, 'X':-1, '-':-4},
'E': {'A':-1, 'R': 0, 'N': 0, 'D': 2, 'C':-4, 'Q': 2, 'E': 5, 'G':-2, 'H': 0, 'I':-3, 'L':-3, 'K': 1, 'M':-2, 'F':-3, 'P':-1, 'S': 0, 'T':-1, 'W':-3, 'Y':-2, 'V':-2, 'B': 1, 'Z': 4, 'X':-1, '-':-4},
'G': {'A': 0, 'R':-2, 'N': 0, 'D':-1, 'C':-3, 'Q':-2, 'E':-2, 'G': 6, 'H':-2, 'I':-4, 'L':-4, 'K':-2, 'M':-3, 'F':-3, 'P':-2, 'S': 0, 'T':-2, 'W':-2, 'Y':-3, 'V':-3, 'B':-1, 'Z':-2, 'X':-1, '-':-4},
'H': {'A':-2, 'R': 0, 'N': 1, 'D':-1, 'C':-3, 'Q': 0, 'E': 0, 'G':-2, 'H': 8, 'I':-3, 'L':-3, 'K':-1, 'M':-2, 'F':-1, 'P':-2, 'S':-1, 'T':-2, 'W':-2, 'Y': 2, 'V':-3, 'B': 0, 'Z': 0, 'X':-1, '-':-4},
'I': {'A':-1, 'R':-3, 'N':-3, 'D':-3, 'C':-1, 'Q':-3, 'E':-3, 'G':-4, 'H':-3, 'I': 4, 'L': 2, 'K':-3, 'M': 1, 'F': 0, 'P':-3, 'S':-2, 'T':-1, 'W':-3, 'Y':-1, 'V': 3, 'B':-3, 'Z':-3, 'X':-1, '-':-4},
'L': {'A':-1, 'R':-2, 'N':-3, 'D':-4, 'C':-1, 'Q':-2, 'E':-3, 'G':-4, 'H':-3, 'I': 2, 'L': 4, 'K':-2, 'M': 2, 'F': 0, 'P':-3, 'S':-2, 'T':-1, 'W':-2, 'Y':-1, 'V': 1, 'B':-4, 'Z':-3, 'X':-1, '-':-4},
'K': {'A':-1, 'R': 2, 'N': 0, 'D':-1, 'C':-3, 'Q': 1, 'E': 1, 'G':-2, 'H':-1, 'I':-3, 'L':-2, 'K': 5, 'M':-1, 'F':-3, 'P':-1, 'S': 0, 'T':-1, 'W':-3, 'Y':-2, 'V':-2, 'B': 0, 'Z': 1, 'X':-1, '-':-4},
'M': {'A':-1, 'R':-1, 'N':-2, 'D':-3, 'C':-1, 'Q': 0, 'E':-2, 'G':-3, 'H':-2, 'I': 1, 'L': 2, 'K':-1, 'M': 5, 'F': 0, 'P':-2, 'S':-1, 'T':-1, 'W':-1, 'Y':-1, 'V': 1, 'B':-3, 'Z':-1, 'X':-1, '-':-4},
'F': {'A':-2, 'R':-3, 'N':-3, 'D':-3, 'C':-2, 'Q':-3, 'E':-3, 'G':-3, 'H':-1, 'I': 0, 'L': 0, 'K':-3, 'M': 0, 'F': 6, 'P':-4, 'S':-2, 'T':-2, 'W': 1, 'Y': 3, 'V':-1, 'B':-3, 'Z':-3, 'X':-1, '-':-4},
'P': {'A':-1, 'R':-2, 'N':-2, 'D':-1, 'C':-3, 'Q':-1, 'E':-1, 'G':-2, 'H':-2, 'I':-3, 'L':-3, 'K':-1, 'M':-2, 'F':-4, 'P': 7, 'S':-1, 'T':-1, 'W':-4, 'Y':-3, 'V':-2, 'B':-2, 'Z':-1, 'X':-2, '-':-4},
'S': {'A': 1, 'R':-1, 'N': 1, 'D': 0, 'C':-1, 'Q': 0, 'E': 0, 'G': 0, 'H':-1, 'I':-2, 'L':-2, 'K': 0, 'M':-1, 'F':-2, 'P':-1, 'S': 4, 'T': 1, 'W':-3, 'Y':-2, 'V':-2, 'B': 0, 'Z': 0, 'X': 0, '-':-4},
'T': {'A': 0, 'R':-1, 'N': 0, 'D':-1, 'C':-1, 'Q':-1, 'E':-1, 'G':-2, 'H':-2, 'I':-1, 'L':-1, 'K':-1, 'M':-1, 'F':-2, 'P':-1, 'S': 1, 'T': 5, 'W':-2, 'Y':-2, 'V': 0, 'B':-1, 'Z':-1, 'X': 0, '-':-4},
'W': {'A':-3, 'R':-3, 'N':-4, 'D':-4, 'C':-2, 'Q':-2, 'E':-3, 'G':-2, 'H':-2, 'I':-3, 'L':-2, 'K':-3, 'M':-1, 'F': 1, 'P':-4, 'S':-3, 'T':-2, 'W':11, 'Y': 2, 'V':-3, 'B':-4, 'Z':-3, 'X':-2, '-':-4},
'Y': {'A':-2, 'R':-2, 'N':-2, 'D':-3, 'C':-2, 'Q':-1, 'E':-2, 'G':-3, 'H': 2, 'I':-1, 'L':-1, 'K':-2, 'M':-1, 'F': 3, 'P':-3, 'S':-2, 'T':-2, 'W': 2, 'Y': 7, 'V':-1, 'B':-3, 'Z':-2, 'X':-1, '-':-4},
'V': {'A': 0, 'R':-3, 'N':-3, 'D':-3, 'C':-1, 'Q':-2, 'E':-2, 'G':-3, 'H':-3, 'I': 3, 'L': 1, 'K':-2, 'M': 1, 'F':-1, 'P':-2, 'S':-2, 'T': 0, 'W':-3, 'Y':-1, 'V': 4, 'B':-3, 'Z':-2, 'X':-1, '-':-4},
'B': {'A':-2, 'R':-1, 'N': 3, 'D': 4, 'C':-3, 'Q': 0, 'E': 1, 'G':-1, 'H': 0, 'I':-3, 'L':-4, 'K': 0, 'M':-3, 'F':-3, 'P':-2, 'S': 0, 'T':-1, 'W':-4, 'Y':-3, 'V':-3, 'B': 4, 'Z': 1, 'X':-1, '-':-4},
'Z': {'A':-1, 'R': 0, 'N': 0, 'D': 1, 'C':-3, 'Q': 3, 'E': 4, 'G':-2, 'H': 0, 'I':-3, 'L':-3, 'K': 1, 'M':-1, 'F':-3, 'P':-1, 'S': 0, 'T':-1, 'W':-3, 'Y':-2, 'V':-2, 'B': 1, 'Z': 4, 'X':-1, '-':-4},
'X': {'A': 0, 'R':-1, 'N':-1, 'D':-1, 'C':-2, 'Q':-1, 'E':-1, 'G':-1, 'H':-1, 'I':-1, 'L':-1, 'K':-1, 'M':-1, 'F':-1, 'P':-2, 'S': 0, 'T': 0, 'W':-2, 'Y':-1, 'V':-1, 'B':-1, 'Z':-1, 'X':-1, '-':-4},
'-': {'A':-4, 'R':-4, 'N':-4, 'D':-4, 'C':-4, 'Q':-4, 'E':-4, 'G':-4, 'H':-4, 'I':-4, 'L':-4, 'K':-4, 'M':-4, 'F':-4, 'P':-4, 'S':-4, 'T':-4, 'W':-4, 'Y':-4, 'V':-4, 'B':-4, 'Z':-4, 'X':-4, '-': 1}
}
def score(self, c1, c2):
return(self.blosum62[c1][c2])
def calc_score(self, s1, s2):
if len(s1) != len(s2):
return(-1)
score = 0
for i in range(len(s1)):
score += self.blosum62[s1[i]][s2[i]]
return(score)
class SM_Nucleotide:
"""Score matrix Nucleotide"""
def __init__(self):
self.sm = {
'A': {'A': 2, 'T':-1, 'G':-1, 'C':-1, '*':-2},
'T': {'A':-1, 'T': 2, 'G':-1, 'C':-1, '*':-2},
'G': {'A':-1, 'T':-1, 'G': 2, 'C':-1, '*':-2},
'C': {'A':-1, 'T':-1, 'G':-1, 'C': 2, '*':-2},
'*': {'A':-2, 'T':-2, 'G':-2, 'C':-2, '*':-1}
}
def score(self, c1, c2):
return(self.sm[c1][c2])
def calc_score(self, s1, s2):
if len(s1) != len(s2):
return(-1)
score = 0
for i in range(len(s1)):
score += self.sm[s1[i]][s2[i]]
return(score)
|
class Blosum62:
"""Score matrix BLOSUM62"""
def __init__(self):
self.blosum62 = {'A': {'A': 4, 'R': -1, 'N': -2, 'D': -2, 'C': 0, 'Q': -1, 'E': -1, 'G': 0, 'H': -2, 'I': -1, 'L': -1, 'K': -1, 'M': -1, 'F': -2, 'P': -1, 'S': 1, 'T': 0, 'W': -3, 'Y': -2, 'V': 0, 'B': -2, 'Z': -1, 'X': 0, '-': -4}, 'R': {'A': -1, 'R': 5, 'N': 0, 'D': -2, 'C': -3, 'Q': 1, 'E': 0, 'G': -2, 'H': 0, 'I': -3, 'L': -2, 'K': 2, 'M': -1, 'F': -3, 'P': -2, 'S': -1, 'T': -1, 'W': -3, 'Y': -2, 'V': -3, 'B': -1, 'Z': 0, 'X': -1, '-': -4}, 'N': {'A': -2, 'R': 0, 'N': 6, 'D': 1, 'C': -3, 'Q': 0, 'E': 0, 'G': 0, 'H': 1, 'I': -3, 'L': -3, 'K': 0, 'M': -2, 'F': -3, 'P': -2, 'S': 1, 'T': 0, 'W': -4, 'Y': -2, 'V': -3, 'B': 3, 'Z': 0, 'X': -1, '-': -4}, 'D': {'A': -2, 'R': -2, 'N': 1, 'D': 6, 'C': -3, 'Q': 0, 'E': 2, 'G': -1, 'H': -1, 'I': -3, 'L': -4, 'K': -1, 'M': -3, 'F': -3, 'P': -1, 'S': 0, 'T': -1, 'W': -4, 'Y': -3, 'V': -3, 'B': 4, 'Z': 1, 'X': -1, '-': -4}, 'C': {'A': 0, 'R': -3, 'N': -3, 'D': -3, 'C': 9, 'Q': -3, 'E': -4, 'G': -3, 'H': -3, 'I': -1, 'L': -1, 'K': -3, 'M': -1, 'F': -2, 'P': -3, 'S': -1, 'T': -1, 'W': -2, 'Y': -2, 'V': -1, 'B': -3, 'Z': -3, 'X': -2, '-': -4}, 'Q': {'A': -1, 'R': 1, 'N': 0, 'D': 0, 'C': -3, 'Q': 5, 'E': 2, 'G': -2, 'H': 0, 'I': -3, 'L': -2, 'K': 1, 'M': 0, 'F': -3, 'P': -1, 'S': 0, 'T': -1, 'W': -2, 'Y': -1, 'V': -2, 'B': 0, 'Z': 3, 'X': -1, '-': -4}, 'E': {'A': -1, 'R': 0, 'N': 0, 'D': 2, 'C': -4, 'Q': 2, 'E': 5, 'G': -2, 'H': 0, 'I': -3, 'L': -3, 'K': 1, 'M': -2, 'F': -3, 'P': -1, 'S': 0, 'T': -1, 'W': -3, 'Y': -2, 'V': -2, 'B': 1, 'Z': 4, 'X': -1, '-': -4}, 'G': {'A': 0, 'R': -2, 'N': 0, 'D': -1, 'C': -3, 'Q': -2, 'E': -2, 'G': 6, 'H': -2, 'I': -4, 'L': -4, 'K': -2, 'M': -3, 'F': -3, 'P': -2, 'S': 0, 'T': -2, 'W': -2, 'Y': -3, 'V': -3, 'B': -1, 'Z': -2, 'X': -1, '-': -4}, 'H': {'A': -2, 'R': 0, 'N': 1, 'D': -1, 'C': -3, 'Q': 0, 'E': 0, 'G': -2, 'H': 8, 'I': -3, 'L': -3, 'K': -1, 'M': -2, 'F': -1, 'P': -2, 'S': -1, 'T': -2, 'W': -2, 'Y': 2, 'V': -3, 'B': 0, 'Z': 0, 'X': -1, '-': -4}, 'I': {'A': -1, 'R': -3, 'N': -3, 'D': -3, 'C': -1, 'Q': -3, 'E': -3, 'G': -4, 'H': -3, 'I': 4, 'L': 2, 'K': -3, 'M': 1, 'F': 0, 'P': -3, 'S': -2, 'T': -1, 'W': -3, 'Y': -1, 'V': 3, 'B': -3, 'Z': -3, 'X': -1, '-': -4}, 'L': {'A': -1, 'R': -2, 'N': -3, 'D': -4, 'C': -1, 'Q': -2, 'E': -3, 'G': -4, 'H': -3, 'I': 2, 'L': 4, 'K': -2, 'M': 2, 'F': 0, 'P': -3, 'S': -2, 'T': -1, 'W': -2, 'Y': -1, 'V': 1, 'B': -4, 'Z': -3, 'X': -1, '-': -4}, 'K': {'A': -1, 'R': 2, 'N': 0, 'D': -1, 'C': -3, 'Q': 1, 'E': 1, 'G': -2, 'H': -1, 'I': -3, 'L': -2, 'K': 5, 'M': -1, 'F': -3, 'P': -1, 'S': 0, 'T': -1, 'W': -3, 'Y': -2, 'V': -2, 'B': 0, 'Z': 1, 'X': -1, '-': -4}, 'M': {'A': -1, 'R': -1, 'N': -2, 'D': -3, 'C': -1, 'Q': 0, 'E': -2, 'G': -3, 'H': -2, 'I': 1, 'L': 2, 'K': -1, 'M': 5, 'F': 0, 'P': -2, 'S': -1, 'T': -1, 'W': -1, 'Y': -1, 'V': 1, 'B': -3, 'Z': -1, 'X': -1, '-': -4}, 'F': {'A': -2, 'R': -3, 'N': -3, 'D': -3, 'C': -2, 'Q': -3, 'E': -3, 'G': -3, 'H': -1, 'I': 0, 'L': 0, 'K': -3, 'M': 0, 'F': 6, 'P': -4, 'S': -2, 'T': -2, 'W': 1, 'Y': 3, 'V': -1, 'B': -3, 'Z': -3, 'X': -1, '-': -4}, 'P': {'A': -1, 'R': -2, 'N': -2, 'D': -1, 'C': -3, 'Q': -1, 'E': -1, 'G': -2, 'H': -2, 'I': -3, 'L': -3, 'K': -1, 'M': -2, 'F': -4, 'P': 7, 'S': -1, 'T': -1, 'W': -4, 'Y': -3, 'V': -2, 'B': -2, 'Z': -1, 'X': -2, '-': -4}, 'S': {'A': 1, 'R': -1, 'N': 1, 'D': 0, 'C': -1, 'Q': 0, 'E': 0, 'G': 0, 'H': -1, 'I': -2, 'L': -2, 'K': 0, 'M': -1, 'F': -2, 'P': -1, 'S': 4, 'T': 1, 'W': -3, 'Y': -2, 'V': -2, 'B': 0, 'Z': 0, 'X': 0, '-': -4}, 'T': {'A': 0, 'R': -1, 'N': 0, 'D': -1, 'C': -1, 'Q': -1, 'E': -1, 'G': -2, 'H': -2, 'I': -1, 'L': -1, 'K': -1, 'M': -1, 'F': -2, 'P': -1, 'S': 1, 'T': 5, 'W': -2, 'Y': -2, 'V': 0, 'B': -1, 'Z': -1, 'X': 0, '-': -4}, 'W': {'A': -3, 'R': -3, 'N': -4, 'D': -4, 'C': -2, 'Q': -2, 'E': -3, 'G': -2, 'H': -2, 'I': -3, 'L': -2, 'K': -3, 'M': -1, 'F': 1, 'P': -4, 'S': -3, 'T': -2, 'W': 11, 'Y': 2, 'V': -3, 'B': -4, 'Z': -3, 'X': -2, '-': -4}, 'Y': {'A': -2, 'R': -2, 'N': -2, 'D': -3, 'C': -2, 'Q': -1, 'E': -2, 'G': -3, 'H': 2, 'I': -1, 'L': -1, 'K': -2, 'M': -1, 'F': 3, 'P': -3, 'S': -2, 'T': -2, 'W': 2, 'Y': 7, 'V': -1, 'B': -3, 'Z': -2, 'X': -1, '-': -4}, 'V': {'A': 0, 'R': -3, 'N': -3, 'D': -3, 'C': -1, 'Q': -2, 'E': -2, 'G': -3, 'H': -3, 'I': 3, 'L': 1, 'K': -2, 'M': 1, 'F': -1, 'P': -2, 'S': -2, 'T': 0, 'W': -3, 'Y': -1, 'V': 4, 'B': -3, 'Z': -2, 'X': -1, '-': -4}, 'B': {'A': -2, 'R': -1, 'N': 3, 'D': 4, 'C': -3, 'Q': 0, 'E': 1, 'G': -1, 'H': 0, 'I': -3, 'L': -4, 'K': 0, 'M': -3, 'F': -3, 'P': -2, 'S': 0, 'T': -1, 'W': -4, 'Y': -3, 'V': -3, 'B': 4, 'Z': 1, 'X': -1, '-': -4}, 'Z': {'A': -1, 'R': 0, 'N': 0, 'D': 1, 'C': -3, 'Q': 3, 'E': 4, 'G': -2, 'H': 0, 'I': -3, 'L': -3, 'K': 1, 'M': -1, 'F': -3, 'P': -1, 'S': 0, 'T': -1, 'W': -3, 'Y': -2, 'V': -2, 'B': 1, 'Z': 4, 'X': -1, '-': -4}, 'X': {'A': 0, 'R': -1, 'N': -1, 'D': -1, 'C': -2, 'Q': -1, 'E': -1, 'G': -1, 'H': -1, 'I': -1, 'L': -1, 'K': -1, 'M': -1, 'F': -1, 'P': -2, 'S': 0, 'T': 0, 'W': -2, 'Y': -1, 'V': -1, 'B': -1, 'Z': -1, 'X': -1, '-': -4}, '-': {'A': -4, 'R': -4, 'N': -4, 'D': -4, 'C': -4, 'Q': -4, 'E': -4, 'G': -4, 'H': -4, 'I': -4, 'L': -4, 'K': -4, 'M': -4, 'F': -4, 'P': -4, 'S': -4, 'T': -4, 'W': -4, 'Y': -4, 'V': -4, 'B': -4, 'Z': -4, 'X': -4, '-': 1}}
def score(self, c1, c2):
return self.blosum62[c1][c2]
def calc_score(self, s1, s2):
if len(s1) != len(s2):
return -1
score = 0
for i in range(len(s1)):
score += self.blosum62[s1[i]][s2[i]]
return score
class Sm_Nucleotide:
"""Score matrix Nucleotide"""
def __init__(self):
self.sm = {'A': {'A': 2, 'T': -1, 'G': -1, 'C': -1, '*': -2}, 'T': {'A': -1, 'T': 2, 'G': -1, 'C': -1, '*': -2}, 'G': {'A': -1, 'T': -1, 'G': 2, 'C': -1, '*': -2}, 'C': {'A': -1, 'T': -1, 'G': -1, 'C': 2, '*': -2}, '*': {'A': -2, 'T': -2, 'G': -2, 'C': -2, '*': -1}}
def score(self, c1, c2):
return self.sm[c1][c2]
def calc_score(self, s1, s2):
if len(s1) != len(s2):
return -1
score = 0
for i in range(len(s1)):
score += self.sm[s1[i]][s2[i]]
return score
|
chars = {
'A': ['010',
'101',
'111',
'101',
'101'],
'B': ['110',
'101',
'111',
'101',
'110'],
'C': ['011',
'100',
'100',
'100',
'011'],
'D': ['110',
'101',
'101',
'101',
'110'],
'E': ['111',
'100',
'111',
'100',
'111'],
'F': ['111',
'100',
'111',
'100',
'100'],
'G': ['0111',
'1000',
'1011',
'1001',
'0110'],
'H': ['101',
'101',
'111',
'101',
'101'],
'I': ['111',
'010',
'010',
'010',
'111'],
'J': ['111',
'010',
'010',
'010',
'110'],
'K': ['1001',
'1010',
'1100',
'1010',
'1001'],
'L': ['100',
'100',
'100',
'100',
'111'],
'M': ['10001',
'11011',
'10101',
'10001',
'10001'],
'N': ['1001',
'1101',
'1111',
'1011',
'1001'],
'O': ['010',
'101',
'101',
'101',
'010'],
'P': ['110',
'101',
'110',
'100',
'100'],
'Q': ['0110',
'1001',
'1001',
'1011',
'0111'],
'R': ['110',
'101',
'110',
'101',
'101'],
'S': ['011',
'100',
'011',
'001',
'110'],
'T': ['111',
'010',
'010',
'010',
'010'],
'U': ['101',
'101',
'101',
'101',
'010'],
'V': ['10001',
'10001',
'10001',
'01010',
'00100'],
'W': ['10001',
'10001',
'10101',
'11011',
'10001'],
'X': ['1001',
'0110',
'0110',
'0110',
'1001'],
'Y': ['101',
'101',
'010',
'010',
'010'],
'Z': ['1111',
'0010',
'0100',
'1000',
'1111'],
'.': ['0',
'0',
'0',
'0',
'1'],
':': ['0',
'1',
'0',
'1',
'0'],
'!': ['1',
'1',
'1',
'0',
'1'],
'?': ['01110',
'10001',
'00110',
'00000',
'00100'],
'\'': ['11',
'11',
'00',
'00',
'00'],
'\"': ['11',
'00',
'00',
'00',
'00'],
' ': ['0',
'0',
'0',
'0',
'0'],
',': ['00',
'00',
'00',
'01',
'11'],
'/': ['001',
'011',
'010',
'110',
'100'],
'\\': ['100',
'110',
'010',
'011',
'001'],
'0': ['010',
'101',
'101',
'101',
'010'],
'1': ['010',
'110',
'010',
'010',
'111'],
'2': ['011',
'101',
'010',
'100',
'111'],
'3': ['111',
'001',
'111',
'001',
'111'],
'4': ['011',
'101',
'111',
'001',
'001'],
'5': ['111',
'100',
'111',
'001',
'111'],
'6': ['111',
'100',
'111',
'101',
'111'],
'7': ['111',
'001',
'010',
'100',
'100'],
'8': ['111',
'101',
'111',
'101',
'111'],
'9': ['111',
'101',
'111',
'001',
'111']
}
def get_mapping(string):
global chars
mapping = ['','','','','']
string = string.upper()
for char in string:
if char in chars:
char_mapping = chars[char]
else:
char_mapping = ['0','0','0','0','0']
mapping = [
mapping[0] + char_mapping[0] + '0',
mapping[1] + char_mapping[1] + '0',
mapping[2] + char_mapping[2] + '0',
mapping[3] + char_mapping[3] + '0',
mapping[4] + char_mapping[4] + '0'
]
return mapping
|
chars = {'A': ['010', '101', '111', '101', '101'], 'B': ['110', '101', '111', '101', '110'], 'C': ['011', '100', '100', '100', '011'], 'D': ['110', '101', '101', '101', '110'], 'E': ['111', '100', '111', '100', '111'], 'F': ['111', '100', '111', '100', '100'], 'G': ['0111', '1000', '1011', '1001', '0110'], 'H': ['101', '101', '111', '101', '101'], 'I': ['111', '010', '010', '010', '111'], 'J': ['111', '010', '010', '010', '110'], 'K': ['1001', '1010', '1100', '1010', '1001'], 'L': ['100', '100', '100', '100', '111'], 'M': ['10001', '11011', '10101', '10001', '10001'], 'N': ['1001', '1101', '1111', '1011', '1001'], 'O': ['010', '101', '101', '101', '010'], 'P': ['110', '101', '110', '100', '100'], 'Q': ['0110', '1001', '1001', '1011', '0111'], 'R': ['110', '101', '110', '101', '101'], 'S': ['011', '100', '011', '001', '110'], 'T': ['111', '010', '010', '010', '010'], 'U': ['101', '101', '101', '101', '010'], 'V': ['10001', '10001', '10001', '01010', '00100'], 'W': ['10001', '10001', '10101', '11011', '10001'], 'X': ['1001', '0110', '0110', '0110', '1001'], 'Y': ['101', '101', '010', '010', '010'], 'Z': ['1111', '0010', '0100', '1000', '1111'], '.': ['0', '0', '0', '0', '1'], ':': ['0', '1', '0', '1', '0'], '!': ['1', '1', '1', '0', '1'], '?': ['01110', '10001', '00110', '00000', '00100'], "'": ['11', '11', '00', '00', '00'], '"': ['11', '00', '00', '00', '00'], ' ': ['0', '0', '0', '0', '0'], ',': ['00', '00', '00', '01', '11'], '/': ['001', '011', '010', '110', '100'], '\\': ['100', '110', '010', '011', '001'], '0': ['010', '101', '101', '101', '010'], '1': ['010', '110', '010', '010', '111'], '2': ['011', '101', '010', '100', '111'], '3': ['111', '001', '111', '001', '111'], '4': ['011', '101', '111', '001', '001'], '5': ['111', '100', '111', '001', '111'], '6': ['111', '100', '111', '101', '111'], '7': ['111', '001', '010', '100', '100'], '8': ['111', '101', '111', '101', '111'], '9': ['111', '101', '111', '001', '111']}
def get_mapping(string):
global chars
mapping = ['', '', '', '', '']
string = string.upper()
for char in string:
if char in chars:
char_mapping = chars[char]
else:
char_mapping = ['0', '0', '0', '0', '0']
mapping = [mapping[0] + char_mapping[0] + '0', mapping[1] + char_mapping[1] + '0', mapping[2] + char_mapping[2] + '0', mapping[3] + char_mapping[3] + '0', mapping[4] + char_mapping[4] + '0']
return mapping
|
SAGA_ENABLED = 1
MIN_DETECTED_FACE_WIDTH = 20
MIN_DETECTED_FACE_HEIGHT = 20
PICKLE_FILES_DIR = "/app/facenet/resources/output"
MODEL_FILES_DIR = "/app/facenet/resources/model"
UPLOAD_DIR = "/app/resources/images/"
# PICKLE_FILES_DIR = '/Users/ashishgupta/git/uPresent/face-recognition/resources/output'
# MODEL_FILES_DIR = '/Users/ashishgupta/git/uPresent/face-recognition/resources/model'
# UPLOAD_DIR = '/Users/ashishgupta/git/uPresent/face-recognition/resources/images/'
# DATASET_PATH = '/Users/anchitseth/Desktop/facenet-data-vol/dataset'
# PICKLE_FILES_DIR = '/Users/anchitseth/Desktop/facenet-data-vol/output'
# MODEL_FILES_DIR = '/Users/anchitseth/Desktop/facenet-data-vol/model'
|
saga_enabled = 1
min_detected_face_width = 20
min_detected_face_height = 20
pickle_files_dir = '/app/facenet/resources/output'
model_files_dir = '/app/facenet/resources/model'
upload_dir = '/app/resources/images/'
|
"""
VIS_LR
Visualization tools for learning rate stuff
Stefan Wong 2019
"""
def plot_lr_vs_acc(ax, lr_data, acc_data, **kwargs):
title = kwargs.pop('title', 'Learning Rate vs. Accuracy')
if len(lr_data) != len(acc_data):
plot_len = min([len(lr_data), len(acc_data)])
else:
plot_len = len(lr_data)
ax.plot(lr_data[:plot_len], acc_data[:plot_len])
#ax.set_xlim([lr_data[0], lr_data[plot_len]])
#ax.set_ylim([acc_data[0], acc_data[plot_len]])
ax.set_xlabel('Accuracy')
ax.set_ylabel('Learning Rate')
ax.set_title(title)
|
"""
VIS_LR
Visualization tools for learning rate stuff
Stefan Wong 2019
"""
def plot_lr_vs_acc(ax, lr_data, acc_data, **kwargs):
title = kwargs.pop('title', 'Learning Rate vs. Accuracy')
if len(lr_data) != len(acc_data):
plot_len = min([len(lr_data), len(acc_data)])
else:
plot_len = len(lr_data)
ax.plot(lr_data[:plot_len], acc_data[:plot_len])
ax.set_xlabel('Accuracy')
ax.set_ylabel('Learning Rate')
ax.set_title(title)
|
class Contact:
def __init__(self, first_name: str, second_name: str, phone_number: str):
self._first_name = first_name
self._second_name = second_name
self._phone_number = phone_number
@property
def first_name(self):
return self._first_name
@property
def second_name(self):
return self._second_name
@property
def phone_number(self):
return self._phone_number
@first_name.setter
def first_name(self, name: str):
self._first_name = name
@second_name.setter
def second_name(self, surname: str):
self._second_name = surname
@phone_number.setter
def phone_number(self, number: str):
self._phone_number = number
|
class Contact:
def __init__(self, first_name: str, second_name: str, phone_number: str):
self._first_name = first_name
self._second_name = second_name
self._phone_number = phone_number
@property
def first_name(self):
return self._first_name
@property
def second_name(self):
return self._second_name
@property
def phone_number(self):
return self._phone_number
@first_name.setter
def first_name(self, name: str):
self._first_name = name
@second_name.setter
def second_name(self, surname: str):
self._second_name = surname
@phone_number.setter
def phone_number(self, number: str):
self._phone_number = number
|
def answer(l):
res = 0
length = len(l)
for x in xrange(length):
left = 0
right = 0
for i in xrange(x):
if not (l[x] % l[i]):
left = left + 1
for i in xrange(x + 1, length):
if not (l[i] % l[x]):
right = right + 1
res = res + left * right
return res
# Provided test cases.
assert(answer([1, 1, 1]) == 1)
assert(answer([1, 2, 3, 4, 5, 6]) == 3)
# Custom test cases.
assert(answer([1]) == 0)
assert(answer([1, 2]) == 0)
assert(answer([2, 4]) == 0)
assert(answer([1, 1, 1, 1]) == 4)
assert(answer([1, 1, 1, 1, 1]) == 10)
assert(answer([1, 1, 1, 1, 1, 1]) == 20)
assert(answer([1, 1, 1, 1, 1, 1, 1]) == 35)
assert(answer([1, 1, 2]) == 1)
assert(answer([1, 1, 2, 2]) == 4)
assert(answer([1, 1, 2, 2, 2]) == 10)
assert(answer([1, 1, 2, 2, 2, 3]) == 11)
assert(answer([1, 2, 4, 8, 16]) == 10)
assert(answer([2, 4, 5, 9, 12, 34, 45]) == 1)
assert(answer([2, 2, 2, 2, 4, 4, 5, 6, 8, 8, 8]) == 90)
assert(answer([2, 4, 8]) == 1)
assert(answer([2, 4, 8, 16]) == 4)
assert(answer([3, 4, 2, 7]) == 0)
assert(answer([6, 5, 4, 3, 2, 1]) == 0)
assert(answer([4, 7, 14]) == 0)
assert(answer([4, 21, 7, 14, 8, 56, 56, 42]) == 9)
assert(answer([4, 21, 7, 14, 56, 8, 56, 4, 42]) == 7)
assert(answer([4, 7, 14, 8, 21, 56, 42]) == 4)
assert(answer([4, 8, 4, 16]) == 2)
|
def answer(l):
res = 0
length = len(l)
for x in xrange(length):
left = 0
right = 0
for i in xrange(x):
if not l[x] % l[i]:
left = left + 1
for i in xrange(x + 1, length):
if not l[i] % l[x]:
right = right + 1
res = res + left * right
return res
assert answer([1, 1, 1]) == 1
assert answer([1, 2, 3, 4, 5, 6]) == 3
assert answer([1]) == 0
assert answer([1, 2]) == 0
assert answer([2, 4]) == 0
assert answer([1, 1, 1, 1]) == 4
assert answer([1, 1, 1, 1, 1]) == 10
assert answer([1, 1, 1, 1, 1, 1]) == 20
assert answer([1, 1, 1, 1, 1, 1, 1]) == 35
assert answer([1, 1, 2]) == 1
assert answer([1, 1, 2, 2]) == 4
assert answer([1, 1, 2, 2, 2]) == 10
assert answer([1, 1, 2, 2, 2, 3]) == 11
assert answer([1, 2, 4, 8, 16]) == 10
assert answer([2, 4, 5, 9, 12, 34, 45]) == 1
assert answer([2, 2, 2, 2, 4, 4, 5, 6, 8, 8, 8]) == 90
assert answer([2, 4, 8]) == 1
assert answer([2, 4, 8, 16]) == 4
assert answer([3, 4, 2, 7]) == 0
assert answer([6, 5, 4, 3, 2, 1]) == 0
assert answer([4, 7, 14]) == 0
assert answer([4, 21, 7, 14, 8, 56, 56, 42]) == 9
assert answer([4, 21, 7, 14, 56, 8, 56, 4, 42]) == 7
assert answer([4, 7, 14, 8, 21, 56, 42]) == 4
assert answer([4, 8, 4, 16]) == 2
|
# NOTE: The sitename and dataname corresponding to the observation are 'y' by default
# Any latents that are not population level
model_constants = {
'arm.anova_radon_nopred': {
'population_effects':{'mu_a', 'sigma_a', 'sigma_y'},
'ylims':(1000, 5000),
'ylims_zoomed':(1000, 1200)
},
'arm.anova_radon_nopred_chr': {
'population_effects':{'sigma_a', 'sigma_y', 'mu_a'},
'ylims':(1000, 5000),
'ylims_zoomed':(1000, 1200)
},
'arm.congress': {
'population_effects':{'beta', 'sigma'},
'sitename':'vote_88',
'dataname':'vote_88',
'ylims':(1000, 5000), # CHANGE!
'ylims_zoomed':(1000, 1200) # CHANGE!
},
'arm.earnings_latin_square': {
'population_effects':{"sigma_a1", "sigma_a2", "sigma_b1", "sigma_b2", "sigma_c", "sigma_d", "sigma_y", 'mu_a1', 'mu_a2', 'mu_b1', 'mu_b2', 'mu_c', 'mu_d'},
'ylims':(800, 5000),
'ylims_zoomed':(800, 5000)
},
'arm.earnings_latin_square_chr': {
'population_effects':{"sigma_a1", "sigma_a2", "sigma_b1", "sigma_b2", "sigma_c", "sigma_d", "sigma_y", 'mu_a1', 'mu_a2', 'mu_b1', 'mu_b2', 'mu_c', 'mu_d'},
'ylims':(800, 5000),
'ylims_zoomed':(800, 5000)
},
'arm.earnings_vary_si': {
'population_effects':{"sigma_a1", "sigma_a2", "sigma_y", "mu_a1", "mu_a2"},
'sitename':'log_earn',
'dataname':'log_earn',
'ylims':(800, 5000), # CHANGE!
'ylims_zoomed':(800, 5000) # CHANGE!
},
'arm.earnings_vary_si_chr': {
'population_effects':{"sigma_a1", "sigma_a2", "sigma_y", "mu_a1", "mu_a2"},
'sitename':'log_earn',
'dataname':'log_earn',
'ylims':(800, 5000), # CHANGE!
'ylims_zoomed':(800, 5000) # CHANGE!
},
'arm.earnings1': {
'population_effects':{"sigma", "beta"},
'sitename':'earn_pos',
'dataname':'earn_pos',
'ylims':(800, 5000), # CHANGE!
'ylims_zoomed':(800, 5000) # CHANGE!
},
'arm.earnings2': {
'population_effects':{"sigma", "beta"},
'sitename':'log_earnings',
'dataname':'log_earnings',
'ylims':(800, 5000), # CHANGE!
'ylims_zoomed':(800, 5000) # CHANGE!
},
'arm.election88_ch14': {
'population_effects':{'mu_a', 'sigma_a', 'b'},
'ylims':(1200, 2000),
'ylims_zoomed':(1200, 1400)
},
'arm.election88_ch19': {
'population_effects':{'beta', 'mu_age', 'sigma_age', 'mu_edu', 'sigma_edu', 'mu_age_edu', 'sigma_age_edu', 'mu_region', 'sigma_region', 'b_v_prev'},
'ylims':(1200, 2000), # CHANGE!
'ylims_zoomed':(1200, 1400) # CHANGE!
},
'arm.electric': {
'population_effects':{'beta', 'mu_a', 'sigma_a', 'sigma_y'},
'ylims':(1200, 2000), # CHANGE!
'ylims_zoomed':(1200, 1400) # CHANGE!
},
'arm.electric_1a': {
'population_effects':set(),
'ylims':(1200, 2000), # CHANGE!
'ylims_zoomed':(1200, 1400) # CHANGE!
},
'arm.hiv': {
'population_effects':{'mu_a1', 'sigma_a1', 'mu_a2', 'sigma_a2', 'sigma_y'},
'ylims':(1200, 2000), # CHANGE!
'ylims_zoomed':(1200, 1400) # CHANGE!
},
'arm.wells_dist': {
'population_effects':{'beta'},
'sitename':'switched',
'dataname':'switched',
'ylims':(2000, 7500),
'ylims_zoomed':(2000, 2500)
},
'arm.wells_dae_inter_c': {
'population_effects':{'beta'},
'sitename':'switched',
'dataname':'switched',
'ylims':(1800, 4000),
'ylims_zoomed':(1800, 2200)
},
'arm.radon_complete_pool': {
'population_effects':{'beta', 'sigma'},
'ylims':(1000, 4000),
'ylims_zoomed':(1000, 1400)
},
'arm.radon_group': {
'population_effects':{'beta', 'sigma', 'mu_alpha', 'sigma_alpha', 'mu_beta', 'sigma_beta'},
'ylims':(1000, 4000),
'ylims_zoomed':(1000, 1200),
},
'arm.radon_inter_vary': {
'population_effects':{'beta', 'sigma_y', 'sigma_a', 'sigma_b', 'sigma_beta', 'mu_a', 'mu_b', 'mu_beta'},
'ylims':(1000, 5000),
'ylims_zoomed':(1000, 1300)
},
}
|
model_constants = {'arm.anova_radon_nopred': {'population_effects': {'mu_a', 'sigma_a', 'sigma_y'}, 'ylims': (1000, 5000), 'ylims_zoomed': (1000, 1200)}, 'arm.anova_radon_nopred_chr': {'population_effects': {'sigma_a', 'sigma_y', 'mu_a'}, 'ylims': (1000, 5000), 'ylims_zoomed': (1000, 1200)}, 'arm.congress': {'population_effects': {'beta', 'sigma'}, 'sitename': 'vote_88', 'dataname': 'vote_88', 'ylims': (1000, 5000), 'ylims_zoomed': (1000, 1200)}, 'arm.earnings_latin_square': {'population_effects': {'sigma_a1', 'sigma_a2', 'sigma_b1', 'sigma_b2', 'sigma_c', 'sigma_d', 'sigma_y', 'mu_a1', 'mu_a2', 'mu_b1', 'mu_b2', 'mu_c', 'mu_d'}, 'ylims': (800, 5000), 'ylims_zoomed': (800, 5000)}, 'arm.earnings_latin_square_chr': {'population_effects': {'sigma_a1', 'sigma_a2', 'sigma_b1', 'sigma_b2', 'sigma_c', 'sigma_d', 'sigma_y', 'mu_a1', 'mu_a2', 'mu_b1', 'mu_b2', 'mu_c', 'mu_d'}, 'ylims': (800, 5000), 'ylims_zoomed': (800, 5000)}, 'arm.earnings_vary_si': {'population_effects': {'sigma_a1', 'sigma_a2', 'sigma_y', 'mu_a1', 'mu_a2'}, 'sitename': 'log_earn', 'dataname': 'log_earn', 'ylims': (800, 5000), 'ylims_zoomed': (800, 5000)}, 'arm.earnings_vary_si_chr': {'population_effects': {'sigma_a1', 'sigma_a2', 'sigma_y', 'mu_a1', 'mu_a2'}, 'sitename': 'log_earn', 'dataname': 'log_earn', 'ylims': (800, 5000), 'ylims_zoomed': (800, 5000)}, 'arm.earnings1': {'population_effects': {'sigma', 'beta'}, 'sitename': 'earn_pos', 'dataname': 'earn_pos', 'ylims': (800, 5000), 'ylims_zoomed': (800, 5000)}, 'arm.earnings2': {'population_effects': {'sigma', 'beta'}, 'sitename': 'log_earnings', 'dataname': 'log_earnings', 'ylims': (800, 5000), 'ylims_zoomed': (800, 5000)}, 'arm.election88_ch14': {'population_effects': {'mu_a', 'sigma_a', 'b'}, 'ylims': (1200, 2000), 'ylims_zoomed': (1200, 1400)}, 'arm.election88_ch19': {'population_effects': {'beta', 'mu_age', 'sigma_age', 'mu_edu', 'sigma_edu', 'mu_age_edu', 'sigma_age_edu', 'mu_region', 'sigma_region', 'b_v_prev'}, 'ylims': (1200, 2000), 'ylims_zoomed': (1200, 1400)}, 'arm.electric': {'population_effects': {'beta', 'mu_a', 'sigma_a', 'sigma_y'}, 'ylims': (1200, 2000), 'ylims_zoomed': (1200, 1400)}, 'arm.electric_1a': {'population_effects': set(), 'ylims': (1200, 2000), 'ylims_zoomed': (1200, 1400)}, 'arm.hiv': {'population_effects': {'mu_a1', 'sigma_a1', 'mu_a2', 'sigma_a2', 'sigma_y'}, 'ylims': (1200, 2000), 'ylims_zoomed': (1200, 1400)}, 'arm.wells_dist': {'population_effects': {'beta'}, 'sitename': 'switched', 'dataname': 'switched', 'ylims': (2000, 7500), 'ylims_zoomed': (2000, 2500)}, 'arm.wells_dae_inter_c': {'population_effects': {'beta'}, 'sitename': 'switched', 'dataname': 'switched', 'ylims': (1800, 4000), 'ylims_zoomed': (1800, 2200)}, 'arm.radon_complete_pool': {'population_effects': {'beta', 'sigma'}, 'ylims': (1000, 4000), 'ylims_zoomed': (1000, 1400)}, 'arm.radon_group': {'population_effects': {'beta', 'sigma', 'mu_alpha', 'sigma_alpha', 'mu_beta', 'sigma_beta'}, 'ylims': (1000, 4000), 'ylims_zoomed': (1000, 1200)}, 'arm.radon_inter_vary': {'population_effects': {'beta', 'sigma_y', 'sigma_a', 'sigma_b', 'sigma_beta', 'mu_a', 'mu_b', 'mu_beta'}, 'ylims': (1000, 5000), 'ylims_zoomed': (1000, 1300)}}
|
def addStrings(num1: str, num2: str) -> str:
i, j = len(num1) - 1, len(num2) - 1
tmp = 0
result = ""
while i >= 0 or j >= 0:
if i >= 0:
tmp += int(num1[i])
i -= 1
if j >= 0:
tmp += int(num2[j])
j -= 1
result = str(tmp % 10) + result
tmp //= 10
if tmp != 0:
result = str(tmp) + result
return result
if __name__ == "__main__":
num1 = "999999"
num2 = "99"
result = addStrings(num1, num2)
print(result)
|
def add_strings(num1: str, num2: str) -> str:
(i, j) = (len(num1) - 1, len(num2) - 1)
tmp = 0
result = ''
while i >= 0 or j >= 0:
if i >= 0:
tmp += int(num1[i])
i -= 1
if j >= 0:
tmp += int(num2[j])
j -= 1
result = str(tmp % 10) + result
tmp //= 10
if tmp != 0:
result = str(tmp) + result
return result
if __name__ == '__main__':
num1 = '999999'
num2 = '99'
result = add_strings(num1, num2)
print(result)
|
"""
Definition of TreeNode:
class TreeNode:
def __init__(self, val):
self.val = val
self.left, self.right = None, None
"""
class Solution:
"""
@param A: a list of integer
@return: a tree node
"""
def sortedArrayToBST(self, A):
# write your code here
if len(A) == 0:
return None
mid = len(A) / 2
node = TreeNode(A[mid])
node.left = self.sortedArrayToBST(A[:mid])
node.right = self.sortedArrayToBST(A[(mid+1):])
return node
|
"""
Definition of TreeNode:
class TreeNode:
def __init__(self, val):
self.val = val
self.left, self.right = None, None
"""
class Solution:
"""
@param A: a list of integer
@return: a tree node
"""
def sorted_array_to_bst(self, A):
if len(A) == 0:
return None
mid = len(A) / 2
node = tree_node(A[mid])
node.left = self.sortedArrayToBST(A[:mid])
node.right = self.sortedArrayToBST(A[mid + 1:])
return node
|
intin = int(input())
if intin == 2:
print("NO")
elif intin%2==0:
if intin%4==0:
print("YES")
elif (intin-2)%4==0:
print("YES")
else:
print("NO")
else:
print("NO")
|
intin = int(input())
if intin == 2:
print('NO')
elif intin % 2 == 0:
if intin % 4 == 0:
print('YES')
elif (intin - 2) % 4 == 0:
print('YES')
else:
print('NO')
else:
print('NO')
|
def rgb(r, g, b):
s=""
if r>255:
r=255
elif g>255:
g=255
elif b>255:
b=255
if r<0:
r=0
elif g<0:
g=0
elif b<0:
b=0
r='{0:x}'.format(r)
g='{0:x}'.format(g)
b='{0:x}'.format(b)
if int(r,16)<=15 and int(r,16)>=0:
r='0'+r
if int(g,16)<=15 and int(g,16)>=0:
g='0'+g
if int(b,16)<=15 and int(b,16)>=0:
b='0'+b
s+=r+g+b
return s.upper()
|
def rgb(r, g, b):
s = ''
if r > 255:
r = 255
elif g > 255:
g = 255
elif b > 255:
b = 255
if r < 0:
r = 0
elif g < 0:
g = 0
elif b < 0:
b = 0
r = '{0:x}'.format(r)
g = '{0:x}'.format(g)
b = '{0:x}'.format(b)
if int(r, 16) <= 15 and int(r, 16) >= 0:
r = '0' + r
if int(g, 16) <= 15 and int(g, 16) >= 0:
g = '0' + g
if int(b, 16) <= 15 and int(b, 16) >= 0:
b = '0' + b
s += r + g + b
return s.upper()
|
# https://www.reddit.com/r/dailyprogrammer/comments/1ystvb/022414_challenge_149_easy_disemvoweler/
def disem(str):
result = ''
rem_vowels = ''
vowels = 'aeiou'
for c in str:
if c not in vowels and not c.isspace():
result += c
elif not c.isspace():
rem_vowels += c
print(result + '\n' + rem_vowels)
def main():
phrase = input('\nPlease enter a line: ')
disem(phrase)
choice = input('\nAgain? ')
if choice != 'n':
main()
quit()
main() # Need to actually call the main() method!
|
def disem(str):
result = ''
rem_vowels = ''
vowels = 'aeiou'
for c in str:
if c not in vowels and (not c.isspace()):
result += c
elif not c.isspace():
rem_vowels += c
print(result + '\n' + rem_vowels)
def main():
phrase = input('\nPlease enter a line: ')
disem(phrase)
choice = input('\nAgain? ')
if choice != 'n':
main()
quit()
main()
|
'''
@description 2019/09/22 20:53
'''
|
"""
@description 2019/09/22 20:53
"""
|
def setup():
size (500,500)
background (100)
smooth()
noLoop()
strokeWeight(15)
str(100)
def draw ():
fill (250)
rect (100,100, 100,100)
fill (50)
rect (200,200, 50,100)
|
def setup():
size(500, 500)
background(100)
smooth()
no_loop()
stroke_weight(15)
str(100)
def draw():
fill(250)
rect(100, 100, 100, 100)
fill(50)
rect(200, 200, 50, 100)
|
#Write a function that accepts a 2D list of integers and returns the maximum EVEN value for the entire list.
#You can assume that the number of columns in each row is the same.
#Your function should return None if the list is empty or all the numbers in the 2D list are odd.
#Do NOT use python's built in max() function.
def even_empty_odd(list2d):
len_list = 0
even_numbers = []
odd_numbers = []
count = 0
#if the list is empty
for list_number in list2d:
len_list += len(list_number)
if len_list == 0:
return None
#if the list is gretaer than zero
else:
for list_number in list2d:
for number in list_number:
#find the even numbers
if number % 2 == 0:
even_numbers.append(number) #append all the even numbers in the even_numbers list
else:
#find the odd numbers
odd_numbers.append(number) #append all the odd numbers in the odd_numbers list
count += 1
#Compare if the len of the odd_numbers list is equal to count
#if True that means that all the numbers are odds
if len(odd_numbers) == count:
return "All the numbers in the list are odds"
#if not it means that at least there is onw even number
else:
even_numbers.sort()
return even_numbers[len(even_numbers)-1]
print(even_empty_odd([[1,8],[3,2]]))
|
def even_empty_odd(list2d):
len_list = 0
even_numbers = []
odd_numbers = []
count = 0
for list_number in list2d:
len_list += len(list_number)
if len_list == 0:
return None
else:
for list_number in list2d:
for number in list_number:
if number % 2 == 0:
even_numbers.append(number)
else:
odd_numbers.append(number)
count += 1
if len(odd_numbers) == count:
return 'All the numbers in the list are odds'
else:
even_numbers.sort()
return even_numbers[len(even_numbers) - 1]
print(even_empty_odd([[1, 8], [3, 2]]))
|
class PolicyOwner(basestring):
"""
cluster-admin|vserver-admin
Possible values:
<ul>
<li> "cluster_admin" ,
<li> "vserver_admin"
</ul>
"""
@staticmethod
def get_api_name():
return "policy-owner"
|
class Policyowner(basestring):
"""
cluster-admin|vserver-admin
Possible values:
<ul>
<li> "cluster_admin" ,
<li> "vserver_admin"
</ul>
"""
@staticmethod
def get_api_name():
return 'policy-owner'
|
""" HealthDES - A python library to support discrete event simulation in health and social care """
class ResourceBase:
# TODO: Build out the do and query functions for person, activity and resource objects.
# Need to create dictionary of actions and parameters.
# Subclassing allows dictionary of actions/ activities to be extended.
# Need to provide error checking if actions/ parameters not in dictionary.
def do(self, action, **kwargs):
""" Perform an action on the person """
pass
def query(self, param):
""" Get a parameter from the person."""
pass
|
""" HealthDES - A python library to support discrete event simulation in health and social care """
class Resourcebase:
def do(self, action, **kwargs):
""" Perform an action on the person """
pass
def query(self, param):
""" Get a parameter from the person."""
pass
|
### assuming you have Google Chrome installed...
## remember `pip3 install -r setup.py` before trying any scrapers in this dir
# have a nice day
selenium
chromedriver
requests
|
selenium
chromedriver
requests
|
class Power:
def __init__(self, power_id, name, amount):
self.power_id = power_id
self.power_name = name
self.amount = amount
@classmethod
def from_json(cls, json_object):
return cls(json_object["id"], json_object["name"], json_object["amount"])
def __eq__(self, other):
return self.power_id == other.power_id and self.amount == other.amount
|
class Power:
def __init__(self, power_id, name, amount):
self.power_id = power_id
self.power_name = name
self.amount = amount
@classmethod
def from_json(cls, json_object):
return cls(json_object['id'], json_object['name'], json_object['amount'])
def __eq__(self, other):
return self.power_id == other.power_id and self.amount == other.amount
|
DB_PORT=5432
DB_USERNAME="postgres"
DB_PASSWORD="password"
DB_HOST="127.0.0.1"
DB_DATABASE="eventtriggertest"
|
db_port = 5432
db_username = 'postgres'
db_password = 'password'
db_host = '127.0.0.1'
db_database = 'eventtriggertest'
|
# -*- coding: utf-8 -*-
"""
Created on Wed Mar 14 20:07:55 2018
@author: vegetto
"""
# Local versus Global
def local():
# m doesn't belong to the scope defined by the local function so Python will keep looking into the next enclosing scope. m is finally found in the global scope
print(m, 'printing from the local scope')
m = 5
print(m, 'printing from the global scope')
local()
|
"""
Created on Wed Mar 14 20:07:55 2018
@author: vegetto
"""
def local():
print(m, 'printing from the local scope')
m = 5
print(m, 'printing from the global scope')
local()
|
class WindowNeighbor:
"""The window class for finding the
neighbor pixels around the center"""
def __init__(self, width, center, image):
# center is a list of [row, col, Y_intensity]
self.center = [center[0], center[1], image[center][0]]
self.width = width
self.neighbors = None
self.find_neighbors(image)
self.mean = None
self.var = None
def find_neighbors(self, image):
self.neighbors = []
ix_r_min = max(0, self.center[0] - self.width)
ix_r_max = min(image.shape[0], self.center[0] + self.width + 1)
ix_c_min = max(0, self.center[1] - self.width)
ix_c_max = min(image.shape[1], self.center[1] + self.width + 1)
for r in range(ix_r_min, ix_r_max):
for c in range(ix_c_min, ix_c_max):
if r == self.center[0] and c == self.center[1]:
continue
self.neighbors.append([r, c, image[r, c, 0]])
def __str__(self):
return 'windows c=(%d, %d, %f) size: %d' % (
self.center[0], self.center[1],
self.center[2], len(self.neighbors)
)
|
class Windowneighbor:
"""The window class for finding the
neighbor pixels around the center"""
def __init__(self, width, center, image):
self.center = [center[0], center[1], image[center][0]]
self.width = width
self.neighbors = None
self.find_neighbors(image)
self.mean = None
self.var = None
def find_neighbors(self, image):
self.neighbors = []
ix_r_min = max(0, self.center[0] - self.width)
ix_r_max = min(image.shape[0], self.center[0] + self.width + 1)
ix_c_min = max(0, self.center[1] - self.width)
ix_c_max = min(image.shape[1], self.center[1] + self.width + 1)
for r in range(ix_r_min, ix_r_max):
for c in range(ix_c_min, ix_c_max):
if r == self.center[0] and c == self.center[1]:
continue
self.neighbors.append([r, c, image[r, c, 0]])
def __str__(self):
return 'windows c=(%d, %d, %f) size: %d' % (self.center[0], self.center[1], self.center[2], len(self.neighbors))
|
class Solution(object):
def findLengthOfLCIS(self, nums):
"""
:type nums: List[int]
:rtype: int
"""
start = 0
prev = None
m = 0
for i, n in enumerate(nums):
if prev is not None:
if n <= prev:
start = i
m = max(m, i - start + 1)
prev = n
return m
|
class Solution(object):
def find_length_of_lcis(self, nums):
"""
:type nums: List[int]
:rtype: int
"""
start = 0
prev = None
m = 0
for (i, n) in enumerate(nums):
if prev is not None:
if n <= prev:
start = i
m = max(m, i - start + 1)
prev = n
return m
|
setting = {
'file': './data/crime2010_2018.csv',
'limit': 10000,
'source': [0,1,2,3,7,8,10,11,14,16,23,5,25],
'vars': {
0 : 'num',
1 : 'date_reported',
2:'date_occured',
3:'time_occured',
7:'crime_code',
8:'crime_desc',
10:'victim_age',
11:'victim_sex',
14:'premise_desc',
16:'weapon',
23:'address',
5:'area',25:'location'
}
}
|
setting = {'file': './data/crime2010_2018.csv', 'limit': 10000, 'source': [0, 1, 2, 3, 7, 8, 10, 11, 14, 16, 23, 5, 25], 'vars': {0: 'num', 1: 'date_reported', 2: 'date_occured', 3: 'time_occured', 7: 'crime_code', 8: 'crime_desc', 10: 'victim_age', 11: 'victim_sex', 14: 'premise_desc', 16: 'weapon', 23: 'address', 5: 'area', 25: 'location'}}
|
'''from axju.core.tools import SmartCLI
from axju.worker.git import GitWorker
def main():
cli = SmartCLI(GitWorker)
cli.run()
if __name__ == '__main__':
main()
'''
|
"""from axju.core.tools import SmartCLI
from axju.worker.git import GitWorker
def main():
cli = SmartCLI(GitWorker)
cli.run()
if __name__ == '__main__':
main()
"""
|
# -*- coding: utf-8 -*-
class PaytabsApiError(Exception):
"""Exception raised when an a RequestHandler indicates the request failed.
Attributes:
code -- the error code returned from the API
msg_english -- explanation of the error
"""
def __init__(self, code, message):
self.code = code
self.massage = message
super(PaytabsApiError, self).__init__(message, )
|
class Paytabsapierror(Exception):
"""Exception raised when an a RequestHandler indicates the request failed.
Attributes:
code -- the error code returned from the API
msg_english -- explanation of the error
"""
def __init__(self, code, message):
self.code = code
self.massage = message
super(PaytabsApiError, self).__init__(message)
|
#!/usr/bin/python
# -*- coding: utf-8 -*-
# (c) 2017, Michael Eaton <[email protected]>
#
# This file is part of Ansible
#
# Ansible is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Ansible is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Ansible. If not, see <http://www.gnu.org/licenses/>.
# this is a windows documentation stub. actual code lives in the .ps1
# file of the same name
ANSIBLE_METADATA = {'metadata_version': '1.1',
'status': ['preview'],
'supported_by': 'community'}
DOCUMENTATION = r'''
---
module: win_firewall
version_added: '2.4'
short_description: Enable or disable the Windows Firewall
description:
- Enable or Disable Windows Firewall profiles.
options:
profiles:
description:
- Specify one or more profiles to change.
choices:
- Domain
- Private
- Public
default: [Domain, Private, Public]
state:
description:
- Set state of firewall for given profile.
choices:
- enabled
- disabled
requirements:
- This module requires Windows Management Framework 5 or later.
author: Michael Eaton (@MichaelEaton83)
'''
EXAMPLES = r'''
- name: Enable firewall for Domain, Public and Private profiles
win_firewall:
state: enabled
profiles:
- Domain
- Private
- Public
tags: enable_firewall
- name: Disable Domain firewall
win_firewall:
state: disabled
profiles:
- Domain
tags: disable_firewall
'''
RETURN = r'''
enabled:
description: current firewall status for chosen profile (after any potential change)
returned: always
type: bool
sample: true
profiles:
description: chosen profile
returned: always
type: string
sample: Domain
state:
description: desired state of the given firewall profile(s)
returned: always
type: list
sample: enabled
'''
|
ansible_metadata = {'metadata_version': '1.1', 'status': ['preview'], 'supported_by': 'community'}
documentation = "\n---\nmodule: win_firewall\nversion_added: '2.4'\nshort_description: Enable or disable the Windows Firewall\ndescription:\n- Enable or Disable Windows Firewall profiles.\noptions:\n profiles:\n description:\n - Specify one or more profiles to change.\n choices:\n - Domain\n - Private\n - Public\n default: [Domain, Private, Public]\n state:\n description:\n - Set state of firewall for given profile.\n choices:\n - enabled\n - disabled\nrequirements:\n - This module requires Windows Management Framework 5 or later.\nauthor: Michael Eaton (@MichaelEaton83)\n"
examples = '\n- name: Enable firewall for Domain, Public and Private profiles\n win_firewall:\n state: enabled\n profiles:\n - Domain\n - Private\n - Public\n tags: enable_firewall\n\n- name: Disable Domain firewall\n win_firewall:\n state: disabled\n profiles:\n - Domain\n tags: disable_firewall\n'
return = '\nenabled:\n description: current firewall status for chosen profile (after any potential change)\n returned: always\n type: bool\n sample: true\nprofiles:\n description: chosen profile\n returned: always\n type: string\n sample: Domain\nstate:\n description: desired state of the given firewall profile(s)\n returned: always\n type: list\n sample: enabled\n'
|
"""Top-level package for siphr."""
__author__ = """Shamindra Shrotriya"""
__email__ = "[email protected]"
__version__ = "0.1.0"
|
"""Top-level package for siphr."""
__author__ = 'Shamindra Shrotriya'
__email__ = '[email protected]'
__version__ = '0.1.0'
|
class ActivityBar:
"""
Content settings for the activity bar.
"""
def __init__(self, id: str, title: str, icon: str) -> None:
self.id = id
self.title = title
self.icon = icon
class StaticWebview:
"""
Content settings for a Static Webview.
"""
def __init__(self, id: str, html: str, title: str = None) -> None:
self.id = id
self.html = html
self.title = title
class InputBoxOptions:
"""
Options to configure the behavior of the input box UI.
"""
def __init__(
self,
title: str = None,
password: bool = None,
ignore_focus_out: bool = None,
prompt: str = None,
place_holder: str = None,
value: str = None,
) -> None:
self.title = title
self.password = password
self.ignoreFocusOut = ignore_focus_out
self.prompt = prompt
self.placeHolder = place_holder
self.value = value
class QuickPickOptions:
"""
Options to configure the behavior of the quick pick UI.
"""
def __init__(
self,
title: str = None,
can_pick_many: bool = None,
ignore_focus_out: bool = None,
match_on_description: bool = None,
place_holder: str = None,
match_on_detail: bool = None,
) -> None:
self.title = title
self.canPickMany = can_pick_many
self.ignoreFocusOut = ignore_focus_out
self.matchOnDescription = match_on_description
self.placeHolder = place_holder
self.matchOnDetail = match_on_detail
class QuickPickItem:
"""
Content settings for a Quick Pick Item.
"""
def __init__(self, label: str = None, detail: str = None, description: str = None, **options) -> None:
self.label = label
self.detail = detail
self.description = description
self.__dict__.update(options)
class Undefined:
"""
An instance of this class is returned everytime javascript returns undefined.
"""
def __str__(self):
return "undefined"
def __bool__(self):
return False
def __eq__(self, other):
return isinstance(other, self.__class__)
undefined = Undefined()
class Disposable:
"""
Represents a type which can release resources, such as event listening or a timer.
"""
def __init__(self, id):
self.id = id
def dispose(self):
print(f'DI: {self.id}', flush=True, end='')
|
class Activitybar:
"""
Content settings for the activity bar.
"""
def __init__(self, id: str, title: str, icon: str) -> None:
self.id = id
self.title = title
self.icon = icon
class Staticwebview:
"""
Content settings for a Static Webview.
"""
def __init__(self, id: str, html: str, title: str=None) -> None:
self.id = id
self.html = html
self.title = title
class Inputboxoptions:
"""
Options to configure the behavior of the input box UI.
"""
def __init__(self, title: str=None, password: bool=None, ignore_focus_out: bool=None, prompt: str=None, place_holder: str=None, value: str=None) -> None:
self.title = title
self.password = password
self.ignoreFocusOut = ignore_focus_out
self.prompt = prompt
self.placeHolder = place_holder
self.value = value
class Quickpickoptions:
"""
Options to configure the behavior of the quick pick UI.
"""
def __init__(self, title: str=None, can_pick_many: bool=None, ignore_focus_out: bool=None, match_on_description: bool=None, place_holder: str=None, match_on_detail: bool=None) -> None:
self.title = title
self.canPickMany = can_pick_many
self.ignoreFocusOut = ignore_focus_out
self.matchOnDescription = match_on_description
self.placeHolder = place_holder
self.matchOnDetail = match_on_detail
class Quickpickitem:
"""
Content settings for a Quick Pick Item.
"""
def __init__(self, label: str=None, detail: str=None, description: str=None, **options) -> None:
self.label = label
self.detail = detail
self.description = description
self.__dict__.update(options)
class Undefined:
"""
An instance of this class is returned everytime javascript returns undefined.
"""
def __str__(self):
return 'undefined'
def __bool__(self):
return False
def __eq__(self, other):
return isinstance(other, self.__class__)
undefined = undefined()
class Disposable:
"""
Represents a type which can release resources, such as event listening or a timer.
"""
def __init__(self, id):
self.id = id
def dispose(self):
print(f'DI: {self.id}', flush=True, end='')
|
load("//webgen:webgen.bzl", "erb_file", "js_file", "scss_file", "website")
def page(name, file, out=None, data=False, math=False, plot=False):
extra_templates = []
if data: extra_templates.append("template/data.html")
if math: extra_templates.append("template/mathjax.html")
if plot: extra_templates.append("template/plot.html")
if plot == "tape": extra_templates.append("template/plot_tape.html")
erb_file(
name = name,
srcs = [file, "template/default.html"] + extra_templates,
out = out if out else file,
bootstrap = True,
)
def script(name, file=None, files=[], out=None, plot=False):
extra_sources = []
if plot: extra_sources.append("vis/js/plot.js")
if plot == "prog" or plot == "tape": extra_sources.append("vis/js/plot_prog.js")
if plot == "tape": extra_sources.append("vis/js/plot_tape.js")
js_file(
name = name,
srcs = extra_sources + ([file] if file else []) + files,
out = out if out else file,
)
|
load('//webgen:webgen.bzl', 'erb_file', 'js_file', 'scss_file', 'website')
def page(name, file, out=None, data=False, math=False, plot=False):
extra_templates = []
if data:
extra_templates.append('template/data.html')
if math:
extra_templates.append('template/mathjax.html')
if plot:
extra_templates.append('template/plot.html')
if plot == 'tape':
extra_templates.append('template/plot_tape.html')
erb_file(name=name, srcs=[file, 'template/default.html'] + extra_templates, out=out if out else file, bootstrap=True)
def script(name, file=None, files=[], out=None, plot=False):
extra_sources = []
if plot:
extra_sources.append('vis/js/plot.js')
if plot == 'prog' or plot == 'tape':
extra_sources.append('vis/js/plot_prog.js')
if plot == 'tape':
extra_sources.append('vis/js/plot_tape.js')
js_file(name=name, srcs=extra_sources + ([file] if file else []) + files, out=out if out else file)
|
class Solution:
def uniquePaths(self, m, n):
"""
:type m: int
:type n: int
:rtype: int
"""
return int(math.factorial(m+n-2)/ (math.factorial(m-1)* math.factorial(n-1)))
|
class Solution:
def unique_paths(self, m, n):
"""
:type m: int
:type n: int
:rtype: int
"""
return int(math.factorial(m + n - 2) / (math.factorial(m - 1) * math.factorial(n - 1)))
|
def two_finger_sort(arr, brr):
"""
The two_finger_sort() is a function that takes two sorted lists as input
parameters and returns a single sorted list.
Its time complexity is O(n), but it also needs extra space to store the new
sorted list.
Explanation : arr = [1, 2, 34, 56], brr = [3, 5], crr = []
^ ^
1. Compare the elements that are at the beginning i.e. arr[0] and brr[0].
2. Choose the smaller element and copy it to a new list i.e. arr[0] in this case.
3. Move the pointer to the next element i.e. arr[1] in this case.
4. Compare again and then move to step 2.
5. Complete the comparison till one of the lists is exhausted with the elements
and then copy the rest of the elements in the other list to the list crr.
6. Return the crr list.
crr = [1, 2, 3, 5, 34, 56]
"""
if arr == sorted(arr) and brr == sorted(brr):
i = 0
j = 0
crr = []
while i < len(arr) and j < len(brr):
if arr[i] > brr[j]:
crr.append(brr[j])
j = j + 1
elif arr[i] == brr[j]:
crr.append(arr[i])
crr.append(brr[j])
i = i + 1
j = j + 1
else :
crr.append(arr[i])
i = i + 1
if i == len(arr):
while j < len(brr):
crr.append(brr[j])
j = j + 1
else :
while i < len(arr):
crr.append(arr[i])
i = i + 1
return crr
else :
return "Error : The input lists should be sorted."
#For Debugging
#print(two_finger_sort([1, 2, 3, 4, 56], [3, 5]))
"""
INPUT
arr = [1, 2, 34, 56]
brr = [3, 5]
OUTPUT
[1, 2, 3, 5, 34, 56]
INPUT
arr = [1, 2, 4, 3, 56]
brr = [3, 5]
OUTPUT
Error : The input lists should be sorted.
"""
|
def two_finger_sort(arr, brr):
"""
The two_finger_sort() is a function that takes two sorted lists as input
parameters and returns a single sorted list.
Its time complexity is O(n), but it also needs extra space to store the new
sorted list.
Explanation : arr = [1, 2, 34, 56], brr = [3, 5], crr = []
^ ^
1. Compare the elements that are at the beginning i.e. arr[0] and brr[0].
2. Choose the smaller element and copy it to a new list i.e. arr[0] in this case.
3. Move the pointer to the next element i.e. arr[1] in this case.
4. Compare again and then move to step 2.
5. Complete the comparison till one of the lists is exhausted with the elements
and then copy the rest of the elements in the other list to the list crr.
6. Return the crr list.
crr = [1, 2, 3, 5, 34, 56]
"""
if arr == sorted(arr) and brr == sorted(brr):
i = 0
j = 0
crr = []
while i < len(arr) and j < len(brr):
if arr[i] > brr[j]:
crr.append(brr[j])
j = j + 1
elif arr[i] == brr[j]:
crr.append(arr[i])
crr.append(brr[j])
i = i + 1
j = j + 1
else:
crr.append(arr[i])
i = i + 1
if i == len(arr):
while j < len(brr):
crr.append(brr[j])
j = j + 1
else:
while i < len(arr):
crr.append(arr[i])
i = i + 1
return crr
else:
return 'Error : The input lists should be sorted.'
'\nINPUT\n\narr = [1, 2, 34, 56]\nbrr = [3, 5]\n\nOUTPUT\n\n[1, 2, 3, 5, 34, 56]\n\n\nINPUT\n\narr = [1, 2, 4, 3, 56]\nbrr = [3, 5]\n\nOUTPUT\n\nError : The input lists should be sorted.\n'
|
#data kualitatif
a = "the dogis hungry. The cat is bored. the snack is awake."
s = a.split(".")
print(s)
print(s[0])
print(s[1])
print(s[2])
|
a = 'the dogis hungry. The cat is bored. the snack is awake.'
s = a.split('.')
print(s)
print(s[0])
print(s[1])
print(s[2])
|
'''
Completion sample module
'''
def func_module_level(i, a='foo'):
'some docu'
return i * a
class ModClass:
''' some inner namespace class'''
@classmethod
def class_level_func(cls, boolean=True):
return boolean
class NestedClass:
''' some inner namespace class'''
@classmethod
def class_level_func(cls, a_str='foo', boolean=True):
return boolean or a_str
@classmethod
def a_really_really_loooo_path_to_func(i=23, j='str'):
'''## Some documentation
over `multiple` lines
- list1
- list2
'''
return i
|
"""
Completion sample module
"""
def func_module_level(i, a='foo'):
"""some docu"""
return i * a
class Modclass:
""" some inner namespace class"""
@classmethod
def class_level_func(cls, boolean=True):
return boolean
class Nestedclass:
""" some inner namespace class"""
@classmethod
def class_level_func(cls, a_str='foo', boolean=True):
return boolean or a_str
@classmethod
def a_really_really_loooo_path_to_func(i=23, j='str'):
"""## Some documentation
over `multiple` lines
- list1
- list2
"""
return i
|
N = int(input())
A = int(input())
for a in range(A+1):
for j in range(21):
if a + 500 * j == N:
print("Yes")
exit()
print("No")
|
n = int(input())
a = int(input())
for a in range(A + 1):
for j in range(21):
if a + 500 * j == N:
print('Yes')
exit()
print('No')
|
# ----------------------------------------------------------------
# Copyright 2016 Cisco Systems
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ------------------------------------------------------------------
""" service.py
The base Service class.
"""
class Service(object):
""" Base service class which can be extended for different ways of communicating to remote server """
def operate_on_object_or_dictionary(self, entity, function, args):
result=None
if isinstance(entity, dict):
result = {}
for module, child in entity.items():
result[module] = function(child, *args)
else:
result = function(entity, *args)
return result
def execute_payload(self, provider, payload, operation):
reply = provider.execute(payload, operation)
return reply
|
""" service.py
The base Service class.
"""
class Service(object):
""" Base service class which can be extended for different ways of communicating to remote server """
def operate_on_object_or_dictionary(self, entity, function, args):
result = None
if isinstance(entity, dict):
result = {}
for (module, child) in entity.items():
result[module] = function(child, *args)
else:
result = function(entity, *args)
return result
def execute_payload(self, provider, payload, operation):
reply = provider.execute(payload, operation)
return reply
|
# Scrapy settings for uefispider project
#
# For simplicity, this file contains only the most important settings by
# default. All the other settings are documented here:
#
# http://doc.scrapy.org/en/latest/topics/settings.html
#
BOT_NAME = 'uefispider'
SPIDER_MODULES = ['uefispider.spiders']
NEWSPIDER_MODULE = 'uefispider.spiders'
# Crawl responsibly by identifying yourself (and your website) on the user-agent
USER_AGENT = 'uefispider (+https://github.com/theopolis/uefi-spider)'
ITEM_PIPELINES = {
'uefispider.pipelines.UefispiderPipeline': 1
}
COOKIES_DEBUG = True
|
bot_name = 'uefispider'
spider_modules = ['uefispider.spiders']
newspider_module = 'uefispider.spiders'
user_agent = 'uefispider (+https://github.com/theopolis/uefi-spider)'
item_pipelines = {'uefispider.pipelines.UefispiderPipeline': 1}
cookies_debug = True
|
class Solution:
def baseNeg2(self, N: int) -> str:
if N == 0:
return "0"
nums = []
while N != 0:
r = N % (-2)
N //= (-2)
if r < 0:
r += 2
N += 1
nums.append(r)
return ''.join(map(str, nums[::-1]))
|
class Solution:
def base_neg2(self, N: int) -> str:
if N == 0:
return '0'
nums = []
while N != 0:
r = N % -2
n //= -2
if r < 0:
r += 2
n += 1
nums.append(r)
return ''.join(map(str, nums[::-1]))
|
# This file contains the different states of the api
class Config(object):
DEBUG = False
SQLALCHEMY_DATABASE_URI = 'sqlite:///database.db'
SQLALCHEMY_TRACK_MODIFICATIONS = False
class Production(Config):
DEBUG = False
class DevelopmentConfig(Config):
DEBUG = True
|
class Config(object):
debug = False
sqlalchemy_database_uri = 'sqlite:///database.db'
sqlalchemy_track_modifications = False
class Production(Config):
debug = False
class Developmentconfig(Config):
debug = True
|
class Node(object):
def __init__(self, item):
self.data = item
self.left = None
self.right = None
def BTToDLLUtil(root):
if root is None:
return root
if root.left:
left = BTToDLLUtil(root.left)
while left.right:
left = left.right
left.right = root
root.left = left
if root.right:
right = BTToDLLUtil(root.right)
while right.left:
right = right.left
right.left = root
root.right = right
return root
def BTToDLL(root):
if root is None:
return root
root = BTToDLLUtil(root)
while root.left:
root = root.left
return root
def method1(head):
if head is None:
return
while head:
print(head.data, end=" ")
head = head.right
if __name__ == "__main__":
"""
from timeit import timeit
root = Node(10)
root.left = Node(12)
root.right = Node(15)
root.left.left = Node(25)
root.left.right = Node(30)
root.right.left = Node(36)
head = BTToDLL(root)
print(timeit(lambda: method1(head), number=10000)) # 0.05323586200393038
"""
|
class Node(object):
def __init__(self, item):
self.data = item
self.left = None
self.right = None
def bt_to_dll_util(root):
if root is None:
return root
if root.left:
left = bt_to_dll_util(root.left)
while left.right:
left = left.right
left.right = root
root.left = left
if root.right:
right = bt_to_dll_util(root.right)
while right.left:
right = right.left
right.left = root
root.right = right
return root
def bt_to_dll(root):
if root is None:
return root
root = bt_to_dll_util(root)
while root.left:
root = root.left
return root
def method1(head):
if head is None:
return
while head:
print(head.data, end=' ')
head = head.right
if __name__ == '__main__':
'\n from timeit import timeit\n\n root = Node(10)\n root.left = Node(12)\n root.right = Node(15)\n root.left.left = Node(25)\n root.left.right = Node(30)\n root.right.left = Node(36)\n\n head = BTToDLL(root)\n print(timeit(lambda: method1(head), number=10000)) # 0.05323586200393038\n '
|
#!/usr/bin/env python
print('nihao')
|
print('nihao')
|
def friend_find(line):
check=[i for i,j in enumerate(line) if j=="red"]
total=0
for i in check:
if i>=2 and line[i-1]=="blue" and line[i-2]=="blue":
total+=1
elif (i>=1 and i<=len(line)-2) and line[i-1]=="blue" and line[i+1]=="blue":
total+=1
elif (i<=len(line)-3) and line[i+1]=="blue" and line[i+2]=="blue":
total+=1
return total
|
def friend_find(line):
check = [i for (i, j) in enumerate(line) if j == 'red']
total = 0
for i in check:
if i >= 2 and line[i - 1] == 'blue' and (line[i - 2] == 'blue'):
total += 1
elif (i >= 1 and i <= len(line) - 2) and line[i - 1] == 'blue' and (line[i + 1] == 'blue'):
total += 1
elif i <= len(line) - 3 and line[i + 1] == 'blue' and (line[i + 2] == 'blue'):
total += 1
return total
|
# _*_ coding: utf-8 _*_
#
# Package: bookstore.src.core.validator
__all__ = ["validators"]
|
__all__ = ['validators']
|
sanitizedLines = []
with open("diff.txt") as f:
for line in f:
sanitizedLines.append("https://interclip.app/" + line.strip())
print(str(sanitizedLines))
|
sanitized_lines = []
with open('diff.txt') as f:
for line in f:
sanitizedLines.append('https://interclip.app/' + line.strip())
print(str(sanitizedLines))
|
#
# chmod this file securely and be sure to remove the default users
#
users = {
"frodo" : "1ring",
"yossarian" : "catch22",
"ayla" : "jondalar",
}
|
users = {'frodo': '1ring', 'yossarian': 'catch22', 'ayla': 'jondalar'}
|
def calcMul(items):
mulTotal = 1
for i in items:
mulTotal *= i
return mulTotal
print("The multiple is: ",calcMul([10,20,30]))
|
def calc_mul(items):
mul_total = 1
for i in items:
mul_total *= i
return mulTotal
print('The multiple is: ', calc_mul([10, 20, 30]))
|
def validate_contract_create(request, **kwargs):
if request.validated['auction'].status not in ['active.qualification', 'active.awarded']:
request.errors.add('body', 'data',
'Can\'t add contract in current ({}) auction status'.format(request.validated['auction'].status))
request.errors.status = 403
return
def validate_contract_update(request, **kwargs):
if request.validated['auction_status'] not in ['active.qualification', 'active.awarded']:
request.errors.add('body', 'data', 'Can\'t update contract in current ({}) auction status'.format(
request.validated['auction_status']))
request.errors.status = 403
return
if any([i.status != 'active' for i in request.validated['auction'].lots if
i.id in [a.lotID for a in request.validated['auction'].awards if a.id == request.context.awardID]]):
request.errors.add('body', 'data', 'Can update contract only in active lot status')
request.errors.status = 403
return
|
def validate_contract_create(request, **kwargs):
if request.validated['auction'].status not in ['active.qualification', 'active.awarded']:
request.errors.add('body', 'data', "Can't add contract in current ({}) auction status".format(request.validated['auction'].status))
request.errors.status = 403
return
def validate_contract_update(request, **kwargs):
if request.validated['auction_status'] not in ['active.qualification', 'active.awarded']:
request.errors.add('body', 'data', "Can't update contract in current ({}) auction status".format(request.validated['auction_status']))
request.errors.status = 403
return
if any([i.status != 'active' for i in request.validated['auction'].lots if i.id in [a.lotID for a in request.validated['auction'].awards if a.id == request.context.awardID]]):
request.errors.add('body', 'data', 'Can update contract only in active lot status')
request.errors.status = 403
return
|
"""Constants for Skoda Connect library."""
BASE_SESSION = 'https://msg.volkswagen.de'
BASE_AUTH = 'https://identity.vwgroup.io'
BRAND = 'VW'
COUNTRY = 'DE'
# Data used in communication
CLIENT = {
'Legacy': {
'CLIENT_ID': '9496332b-ea03-4091-a224-8c746b885068%40apps_vw-dilab_com', # client id for VWG API, legacy Skoda Connect/MySkoda
'SCOPE': 'openid mbb profile cars address email birthdate nickname phone',
# 'SCOPE': 'openid mbb profile cars address email birthdate badge phone driversLicense dealers profession vin',
'TOKEN_TYPES': 'code id_token token'
},
'New': {
'CLIENT_ID': 'f9a2359a-b776-46d9-bd0c-db1904343117@apps_vw-dilab_com', # Provides access to new API? tokentype=IDK_TECHNICAL..
'SCOPE': 'openid mbb profile',
'TOKEN_TYPES': 'code id_token'
},
'Unknown': {
'CLIENT_ID': '72f9d29d-aa2b-40c1-bebe-4c7683681d4c@apps_vw-dilab_com', # gives tokentype=IDK_SMARTLINK ?
'SCOPE': 'openid dealers profile email cars address',
'TOKEN_TYPES': 'code id_token'
},
}
XCLIENT_ID = '85fa2187-5b5c-4c35-adba-1471d0c4ea60'
XAPPVERSION = '5.3.2'
XAPPNAME = 'We Connect'
USER_AGENT = 'okhttp/3.14.7'
APP_URI = 'carnet://identity-kit/login'
# Used when fetching data
HEADERS_SESSION = {
'Connection': 'keep-alive',
'Content-Type': 'application/json',
'Accept-charset': 'UTF-8',
'Accept': 'application/json',
'X-Client-Id': XCLIENT_ID,
'X-App-Version': XAPPVERSION,
'X-App-Name': XAPPNAME,
'User-Agent': USER_AGENT,
'tokentype': 'IDK_TECHNICAL'
}
# Used for authentication
HEADERS_AUTH = {
'Connection': 'keep-alive',
'Accept': 'text/html,application/xhtml+xml,application/xml;q=0.9,image/avif,image/webp,image/apng,*/*;q=0.8,application/signed-exchange;v=b3;q=0.9',
'Accept-Encoding': 'gzip, deflate',
'Content-Type': 'application/x-www-form-urlencoded',
'x-requested-with': XAPPNAME,
'User-Agent': USER_AGENT,
'X-App-Name': XAPPNAME
}
|
"""Constants for Skoda Connect library."""
base_session = 'https://msg.volkswagen.de'
base_auth = 'https://identity.vwgroup.io'
brand = 'VW'
country = 'DE'
client = {'Legacy': {'CLIENT_ID': '9496332b-ea03-4091-a224-8c746b885068%40apps_vw-dilab_com', 'SCOPE': 'openid mbb profile cars address email birthdate nickname phone', 'TOKEN_TYPES': 'code id_token token'}, 'New': {'CLIENT_ID': 'f9a2359a-b776-46d9-bd0c-db1904343117@apps_vw-dilab_com', 'SCOPE': 'openid mbb profile', 'TOKEN_TYPES': 'code id_token'}, 'Unknown': {'CLIENT_ID': '72f9d29d-aa2b-40c1-bebe-4c7683681d4c@apps_vw-dilab_com', 'SCOPE': 'openid dealers profile email cars address', 'TOKEN_TYPES': 'code id_token'}}
xclient_id = '85fa2187-5b5c-4c35-adba-1471d0c4ea60'
xappversion = '5.3.2'
xappname = 'We Connect'
user_agent = 'okhttp/3.14.7'
app_uri = 'carnet://identity-kit/login'
headers_session = {'Connection': 'keep-alive', 'Content-Type': 'application/json', 'Accept-charset': 'UTF-8', 'Accept': 'application/json', 'X-Client-Id': XCLIENT_ID, 'X-App-Version': XAPPVERSION, 'X-App-Name': XAPPNAME, 'User-Agent': USER_AGENT, 'tokentype': 'IDK_TECHNICAL'}
headers_auth = {'Connection': 'keep-alive', 'Accept': 'text/html,application/xhtml+xml,application/xml;q=0.9,image/avif,image/webp,image/apng,*/*;q=0.8,application/signed-exchange;v=b3;q=0.9', 'Accept-Encoding': 'gzip, deflate', 'Content-Type': 'application/x-www-form-urlencoded', 'x-requested-with': XAPPNAME, 'User-Agent': USER_AGENT, 'X-App-Name': XAPPNAME}
|
class User:
def __init__(self, userName, firstName, lastName, passportNumber, address1, address2, zipCode):
self.userName = userName
self.firstName = firstName
self.lastName = lastName
self.passportNumber = passportNumber
self.address1 = address1
self.address2 = address2
self.zipCode = zipCode
def toString(self):
return "[userName: " + self.userName + ", firstName: " + self.firstName + ", lastName: " + self.lastName + ", passportNumber: " + self.passportNumber +\
", address1: " + self.address1 + ", address2: " + self.address2 + ", zipCode: " + self.zipCode + "]"
|
class User:
def __init__(self, userName, firstName, lastName, passportNumber, address1, address2, zipCode):
self.userName = userName
self.firstName = firstName
self.lastName = lastName
self.passportNumber = passportNumber
self.address1 = address1
self.address2 = address2
self.zipCode = zipCode
def to_string(self):
return '[userName: ' + self.userName + ', firstName: ' + self.firstName + ', lastName: ' + self.lastName + ', passportNumber: ' + self.passportNumber + ', address1: ' + self.address1 + ', address2: ' + self.address2 + ', zipCode: ' + self.zipCode + ']'
|
# pylint: skip-file
# pylint: disable=too-many-instance-attributes
class VMInstance(GCPResource):
'''Object to represent a gcp instance'''
resource_type = "compute.v1.instance"
# pylint: disable=too-many-arguments
def __init__(self,
rname,
project,
zone,
machine_type,
metadata,
tags,
disks,
network_interfaces,
service_accounts=None,
):
'''constructor for gcp resource'''
super(VMInstance, self).__init__(rname, VMInstance.resource_type, project, zone)
self._machine_type = machine_type
self._service_accounts = service_accounts
self._machine_type_url = None
self._tags = tags
self._metadata = []
if metadata and isinstance(metadata, dict):
self._metadata = {'items': [{'key': key, 'value': value} for key, value in metadata.items()]}
elif metadata and isinstance(metadata, list):
self._metadata = [{'key': label['key'], 'value': label['value']} for label in metadata]
self._disks = disks
self._network_interfaces = network_interfaces
self._properties = None
@property
def service_accounts(self):
'''property for resource service accounts '''
return self._service_accounts
@property
def network_interfaces(self):
'''property for resource machine network_interfaces '''
return self._network_interfaces
@property
def machine_type(self):
'''property for resource machine type '''
return self._machine_type
@property
def machine_type_url(self):
'''property for resource machine type url'''
if self._machine_type_url == None:
self._machine_type_url = Utils.zonal_compute_url(self.project, self.zone, 'machineTypes', self.machine_type)
return self._machine_type_url
@property
def tags(self):
'''property for resource tags '''
return self._tags
@property
def metadata(self):
'''property for resource metadata'''
return self._metadata
@property
def disks(self):
'''property for resource disks'''
return self._disks
@property
def properties(self):
'''property for holding the properties'''
if self._properties == None:
self._properties = {'zone': self.zone,
'machineType': self.machine_type_url,
'metadata': self.metadata,
'tags': self.tags,
'disks': self.disks,
'networkInterfaces': self.network_interfaces,
}
if self.service_accounts:
self._properties['serviceAccounts'] = self.service_accounts
return self._properties
def to_resource(self):
'''return the resource representation'''
return {'name': self.name,
'type': VMInstance.resource_type,
'properties': self.properties,
}
|
class Vminstance(GCPResource):
"""Object to represent a gcp instance"""
resource_type = 'compute.v1.instance'
def __init__(self, rname, project, zone, machine_type, metadata, tags, disks, network_interfaces, service_accounts=None):
"""constructor for gcp resource"""
super(VMInstance, self).__init__(rname, VMInstance.resource_type, project, zone)
self._machine_type = machine_type
self._service_accounts = service_accounts
self._machine_type_url = None
self._tags = tags
self._metadata = []
if metadata and isinstance(metadata, dict):
self._metadata = {'items': [{'key': key, 'value': value} for (key, value) in metadata.items()]}
elif metadata and isinstance(metadata, list):
self._metadata = [{'key': label['key'], 'value': label['value']} for label in metadata]
self._disks = disks
self._network_interfaces = network_interfaces
self._properties = None
@property
def service_accounts(self):
"""property for resource service accounts """
return self._service_accounts
@property
def network_interfaces(self):
"""property for resource machine network_interfaces """
return self._network_interfaces
@property
def machine_type(self):
"""property for resource machine type """
return self._machine_type
@property
def machine_type_url(self):
"""property for resource machine type url"""
if self._machine_type_url == None:
self._machine_type_url = Utils.zonal_compute_url(self.project, self.zone, 'machineTypes', self.machine_type)
return self._machine_type_url
@property
def tags(self):
"""property for resource tags """
return self._tags
@property
def metadata(self):
"""property for resource metadata"""
return self._metadata
@property
def disks(self):
"""property for resource disks"""
return self._disks
@property
def properties(self):
"""property for holding the properties"""
if self._properties == None:
self._properties = {'zone': self.zone, 'machineType': self.machine_type_url, 'metadata': self.metadata, 'tags': self.tags, 'disks': self.disks, 'networkInterfaces': self.network_interfaces}
if self.service_accounts:
self._properties['serviceAccounts'] = self.service_accounts
return self._properties
def to_resource(self):
"""return the resource representation"""
return {'name': self.name, 'type': VMInstance.resource_type, 'properties': self.properties}
|
#
# Variables:
# - Surname: String
# - SurnameLength, NextCodeNumber, CustomerID, i: Integer
# - NextChar: Char
#
Surname = input("Enter your surname: ")
SurnameLength = len(Surname)
CustomerID = 0
for i in range(0, SurnameLength):
NextChar = Surname[i]
NextCodeNumber = ord(NextChar)
CustomerID = CustomerID + NextCodeNumber
print("Customer ID is ", CustomerID)
|
surname = input('Enter your surname: ')
surname_length = len(Surname)
customer_id = 0
for i in range(0, SurnameLength):
next_char = Surname[i]
next_code_number = ord(NextChar)
customer_id = CustomerID + NextCodeNumber
print('Customer ID is ', CustomerID)
|
class EmptyType(object):
"""A sentinel value when nothing is returned from the database"""
def __new__(cls):
return Empty
def __reduce__(self):
return EmptyType, ()
def __bool__(self):
return False
def __repr__(self):
return 'Empty'
Empty = object.__new__(EmptyType)
|
class Emptytype(object):
"""A sentinel value when nothing is returned from the database"""
def __new__(cls):
return Empty
def __reduce__(self):
return (EmptyType, ())
def __bool__(self):
return False
def __repr__(self):
return 'Empty'
empty = object.__new__(EmptyType)
|
class classproperty(object):
'''Implements both @property and @classmethod behavior.'''
def __init__(self, getter):
self.getter = getter
def __get__(self, instance, owner):
return self.getter(instance) if instance else self.getter(owner)
|
class Classproperty(object):
"""Implements both @property and @classmethod behavior."""
def __init__(self, getter):
self.getter = getter
def __get__(self, instance, owner):
return self.getter(instance) if instance else self.getter(owner)
|
def is_empty(text):
if text in [None,'']:
return True
return False
|
def is_empty(text):
if text in [None, '']:
return True
return False
|
mysql_config = {
'user': 'USER',
'password': 'PASSWORD',
'host': 'HOST',
'port': 3306,
'charset': 'utf8mb4',
'database': 'DATABASE',
'raise_on_warnings': False,
'use_pure': False,
}
|
mysql_config = {'user': 'USER', 'password': 'PASSWORD', 'host': 'HOST', 'port': 3306, 'charset': 'utf8mb4', 'database': 'DATABASE', 'raise_on_warnings': False, 'use_pure': False}
|
class Preprocess_Data:
"""this class converts the integer date time values to the python datetime string format"""
def __init__(self, data_dict):
self.data_dict = data_dict
def preprocess(self):
from_year = self.data_dict["fromYr"]
from_month = self.data_dict["fromMth"]
to_year = self.data_dict["toYr"]
to_month = self.data_dict["toMth"]
from_date = str(from_year) + "-" + str(from_month)
to_date = str(to_year) + "-" + str(to_month)
return from_date, to_date
|
class Preprocess_Data:
"""this class converts the integer date time values to the python datetime string format"""
def __init__(self, data_dict):
self.data_dict = data_dict
def preprocess(self):
from_year = self.data_dict['fromYr']
from_month = self.data_dict['fromMth']
to_year = self.data_dict['toYr']
to_month = self.data_dict['toMth']
from_date = str(from_year) + '-' + str(from_month)
to_date = str(to_year) + '-' + str(to_month)
return (from_date, to_date)
|
#!/usr/bin/env python3
"""Global color definitions.
"""
BLUE_BACKGROUND: int = 20
GREEN_BACKGROUND: int = 30
RED_BACKGROUND: int = 5
WHITE: int = 0
YELLOW_BACKGROUND: int = 186
|
"""Global color definitions.
"""
blue_background: int = 20
green_background: int = 30
red_background: int = 5
white: int = 0
yellow_background: int = 186
|
movie = {"title": "padmavati", "director": "Bhansali","year": "2018", "rating": "4.5"}
print(movie)
print(movie['year'])
movie['year'] = 2019 #update data.
print(movie['year'])
print('-' * 20)
for x in movie:
print(x) #this print key.
print(movie[x]) #this print value at key.
print('-' * 20)
movie = {}
movie['title'] = 'Manikarnika'
movie['Director'] = 'kangana Ranut'
movie['year'] = '2015'
print(movie)
movie['actor'] = ['kangana Ranut', 'Khilge','Pelge'] #defining a list within dictionary.
movie['other_detail'] = {'language': 'Hindi', 'runtime': '180min'} #defining a dictinary witnin dictionay.
print(movie)
print('\n...........new example........')
orders = {'apple': 2, 'banana': 5 , 'orange': 10}
print(orders.values())
print(list(orders))
print(list(orders.values()))
for tuple in list(orders.items()): #iterate in dictionary , converting in tuple by using items() method.
print(tuple)
|
movie = {'title': 'padmavati', 'director': 'Bhansali', 'year': '2018', 'rating': '4.5'}
print(movie)
print(movie['year'])
movie['year'] = 2019
print(movie['year'])
print('-' * 20)
for x in movie:
print(x)
print(movie[x])
print('-' * 20)
movie = {}
movie['title'] = 'Manikarnika'
movie['Director'] = 'kangana Ranut'
movie['year'] = '2015'
print(movie)
movie['actor'] = ['kangana Ranut', 'Khilge', 'Pelge']
movie['other_detail'] = {'language': 'Hindi', 'runtime': '180min'}
print(movie)
print('\n...........new example........')
orders = {'apple': 2, 'banana': 5, 'orange': 10}
print(orders.values())
print(list(orders))
print(list(orders.values()))
for tuple in list(orders.items()):
print(tuple)
|
def comb(m, s):
if m == 1: return [[x] for x in s]
if m == len(s): return [s]
return [s[:1] + a for a in comb(m-1, s[1:])] + comb(m, s[1:])
|
def comb(m, s):
if m == 1:
return [[x] for x in s]
if m == len(s):
return [s]
return [s[:1] + a for a in comb(m - 1, s[1:])] + comb(m, s[1:])
|
n, x = map(int, input().split())
mark_sheet = []
for _ in range(x):
mark_sheet.append( map(float, input().split()) )
for i in zip(*mark_sheet):
print( sum(i)/len(i) )
|
(n, x) = map(int, input().split())
mark_sheet = []
for _ in range(x):
mark_sheet.append(map(float, input().split()))
for i in zip(*mark_sheet):
print(sum(i) / len(i))
|
__name__ = "lbry"
__version__ = "0.42.1"
version = tuple(__version__.split('.'))
|
__name__ = 'lbry'
__version__ = '0.42.1'
version = tuple(__version__.split('.'))
|
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