id
int32 0
27.3k
| func
stringlengths 26
142k
| target
bool 2
classes | project
stringclasses 2
values | commit_id
stringlengths 40
40
|
|---|---|---|---|---|
9,064 | DISAS_INSN(scc)
{
int l1;
int cond;
TCGv reg;
l1 = gen_new_label();
cond = (insn >> 8) & 0xf;
reg = DREG(insn, 0);
tcg_gen_andi_i32(reg, reg, 0xffffff00);
/* This is safe because we modify the reg directly, with no other values
live. */
gen_jmpcc(s, cond ^ 1, l1);
tcg_gen_ori_i32(reg, reg, 0xff);
gen_set_label(l1);
}
| false | qemu | 42a268c241183877192c376d03bd9b6d527407c7 |
9,065 | static int usb_host_scan(void *opaque, USBScanFunc *func)
{
Monitor *mon = cur_mon;
FILE *f = NULL;
DIR *dir = NULL;
int ret = 0;
const char *fs_type[] = {"unknown", "proc", "dev", "sys"};
char devpath[PATH_MAX];
/* only check the host once */
if (!usb_fs_type) {
dir = opendir(USBSYSBUS_PATH "/devices");
if (dir) {
/* devices found in /dev/bus/usb/ (yes - not a mistake!) */
strcpy(devpath, USBDEVBUS_PATH);
usb_fs_type = USB_FS_SYS;
closedir(dir);
dprintf(USBDBG_DEVOPENED, USBSYSBUS_PATH);
goto found_devices;
}
f = fopen(USBPROCBUS_PATH "/devices", "r");
if (f) {
/* devices found in /proc/bus/usb/ */
strcpy(devpath, USBPROCBUS_PATH);
usb_fs_type = USB_FS_PROC;
fclose(f);
dprintf(USBDBG_DEVOPENED, USBPROCBUS_PATH);
goto found_devices;
}
/* try additional methods if an access method hasn't been found yet */
f = fopen(USBDEVBUS_PATH "/devices", "r");
if (f) {
/* devices found in /dev/bus/usb/ */
strcpy(devpath, USBDEVBUS_PATH);
usb_fs_type = USB_FS_DEV;
fclose(f);
dprintf(USBDBG_DEVOPENED, USBDEVBUS_PATH);
goto found_devices;
}
found_devices:
if (!usb_fs_type) {
monitor_printf(mon, "husb: unable to access USB devices\n");
return -ENOENT;
}
/* the module setting (used later for opening devices) */
usb_host_device_path = qemu_mallocz(strlen(devpath)+1);
strcpy(usb_host_device_path, devpath);
monitor_printf(mon, "husb: using %s file-system with %s\n",
fs_type[usb_fs_type], usb_host_device_path);
}
switch (usb_fs_type) {
case USB_FS_PROC:
case USB_FS_DEV:
ret = usb_host_scan_dev(opaque, func);
break;
case USB_FS_SYS:
ret = usb_host_scan_sys(opaque, func);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
| false | qemu | eba6fe8732cb5109b6fcf6a973d8959827eb7af4 |
9,066 | static int scsi_cd_initfn(SCSIDevice *dev)
{
SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, dev);
s->qdev.blocksize = 2048;
s->qdev.type = TYPE_ROM;
s->features |= 1 << SCSI_DISK_F_REMOVABLE;
if (!s->product) {
s->product = g_strdup("QEMU CD-ROM");
}
return scsi_initfn(&s->qdev);
}
| false | qemu | a818a4b69d47ca3826dee36878074395aeac2083 |
9,068 | static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
PCIDevice *dev = opaque;
int vector = addr / PCI_MSIX_ENTRY_SIZE;
bool was_masked;
was_masked = msix_is_masked(dev, vector);
pci_set_long(dev->msix_table + addr, val);
msix_handle_mask_update(dev, vector, was_masked);
}
| false | qemu | a8170e5e97ad17ca169c64ba87ae2f53850dab4c |
9,069 | static void encrypted_bdrv_it(void *opaque, BlockDriverState *bs)
{
Error **errp = opaque;
if (!error_is_set(errp) && bdrv_key_required(bs)) {
error_set(errp, QERR_DEVICE_ENCRYPTED, bdrv_get_device_name(bs),
bdrv_get_encrypted_filename(bs));
}
}
| false | qemu | ab31979a7e835832605f8425d0eaa5c74d1e6375 |
9,070 | void virtio_scsi_dataplane_stop(VirtIOSCSI *s)
{
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(s)));
VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(s);
int i;
/* Better luck next time. */
if (s->dataplane_fenced) {
s->dataplane_fenced = false;
return;
}
if (!s->dataplane_started || s->dataplane_stopping) {
return;
}
s->dataplane_stopping = true;
assert(s->ctx == iothread_get_aio_context(vs->conf.iothread));
aio_context_acquire(s->ctx);
aio_set_event_notifier(s->ctx, &s->ctrl_vring->host_notifier,
false, NULL);
aio_set_event_notifier(s->ctx, &s->event_vring->host_notifier,
false, NULL);
for (i = 0; i < vs->conf.num_queues; i++) {
aio_set_event_notifier(s->ctx, &s->cmd_vrings[i]->host_notifier,
false, NULL);
}
blk_drain_all(); /* ensure there are no in-flight requests */
aio_context_release(s->ctx);
/* Sync vring state back to virtqueue so that non-dataplane request
* processing can continue when we disable the host notifier below.
*/
virtio_scsi_vring_teardown(s);
for (i = 0; i < vs->conf.num_queues + 2; i++) {
k->set_host_notifier(qbus->parent, i, false);
}
/* Clean up guest notifier (irq) */
k->set_guest_notifiers(qbus->parent, vs->conf.num_queues + 2, false);
s->dataplane_stopping = false;
s->dataplane_started = false;
}
| false | qemu | 3a1e8074d74ad2acbcedf28d35aebedc3573f19e |
9,071 | static void spitz_common_init(int ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
enum spitz_model_e model, int arm_id)
{
uint32_t spitz_ram = 0x04000000;
uint32_t spitz_rom = 0x00800000;
struct pxa2xx_state_s *cpu;
struct scoop_info_s *scp;
cpu = pxa270_init(ds, (model == terrier) ? "c5" : "c0");
/* Setup memory */
if (ram_size < spitz_ram + spitz_rom) {
fprintf(stderr, "This platform requires %i bytes of memory\n",
spitz_ram + spitz_rom);
exit(1);
}
cpu_register_physical_memory(PXA2XX_RAM_BASE, spitz_ram, IO_MEM_RAM);
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
cpu_register_physical_memory(0, spitz_rom, spitz_ram | IO_MEM_ROM);
/* Setup peripherals */
spitz_keyboard_register(cpu);
spitz_ssp_attach(cpu);
scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
if (model == terrier)
/* A 6.0 GB microdrive is permanently sitting in CF slot 0. */
spitz_microdrive_attach(cpu);
else if (model != akita)
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
spitz_microdrive_attach(cpu);
/* Setup initial (reset) machine state */
cpu->env->regs[15] = PXA2XX_RAM_BASE;
arm_load_kernel(cpu->env, ram_size, kernel_filename, kernel_cmdline,
initrd_filename, arm_id, PXA2XX_RAM_BASE);
sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_RAM_BASE);
}
| false | qemu | 4207117c93357347500235952ce7891688089cb1 |
9,073 | static void run_test(void)
{
unsigned int remaining;
int i;
while (atomic_read(&n_ready_threads) != n_rw_threads + n_rz_threads) {
cpu_relax();
}
atomic_mb_set(&test_start, true);
do {
remaining = sleep(duration);
} while (remaining);
atomic_mb_set(&test_stop, true);
for (i = 0; i < n_rw_threads; i++) {
qemu_thread_join(&rw_threads[i]);
}
for (i = 0; i < n_rz_threads; i++) {
qemu_thread_join(&rz_threads[i]);
}
}
| false | qemu | 977ec47de06bdcb24f01c93bc125b7c6c221a1c5 |
9,074 | static void leon3_generic_hw_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
SPARCCPU *cpu;
CPUSPARCState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *prom = g_new(MemoryRegion, 1);
int ret;
char *filename;
qemu_irq *cpu_irqs = NULL;
int bios_size;
int prom_size;
ResetData *reset_info;
/* Init CPU */
if (!cpu_model) {
cpu_model = "LEON3";
}
cpu = cpu_sparc_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);
}
env = &cpu->env;
cpu_sparc_set_id(env, 0);
/* Reset data */
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
reset_info->sp = 0x40000000 + ram_size;
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate IRQ manager */
grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
env->qemu_irq_ack = leon3_irq_manager;
/* Allocate RAM */
if ((uint64_t)ram_size > (1UL << 30)) {
fprintf(stderr,
"qemu: Too much memory for this machine: %d, maximum 1G\n",
(unsigned int)(ram_size / (1024 * 1024)));
exit(1);
}
memory_region_init_ram(ram, NULL, "leon3.ram", ram_size, &error_abort);
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_abort);
vmstate_register_ram_global(prom);
memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom);
/* Load boot prom */
if (bios_name == NULL) {
bios_name = PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
bios_size = get_image_size(filename);
if (bios_size > prom_size) {
fprintf(stderr, "qemu: could not load prom '%s': file too big\n",
filename);
exit(1);
}
if (bios_size > 0) {
ret = load_image_targphys(filename, 0x00000000, bios_size);
if (ret < 0 || ret > prom_size) {
fprintf(stderr, "qemu: could not load prom '%s'\n", filename);
exit(1);
}
} else if (kernel_filename == NULL && !qtest_enabled()) {
fprintf(stderr, "Can't read bios image %s\n", filename);
exit(1);
}
/* Can directly load an application. */
if (kernel_filename != NULL) {
long kernel_size;
uint64_t entry;
kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
1 /* big endian */, ELF_MACHINE, 0);
if (kernel_size < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
if (bios_size <= 0) {
/* If there is no bios/monitor, start the application. */
env->pc = entry;
env->npc = entry + 4;
reset_info->entry = entry;
}
}
/* Allocate timers */
grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6);
/* Allocate uart */
if (serial_hds[0]) {
grlib_apbuart_create(0x80000100, serial_hds[0], cpu_irqs[3]);
}
} | true | qemu | d71cdbfd540d91a6ae0005e59abfd782c424b07a |
9,075 | static int assign_intx(AssignedDevice *dev, Error **errp)
{
AssignedIRQType new_type;
PCIINTxRoute intx_route;
bool intx_host_msi;
int r;
Error *local_err = NULL;
/* Interrupt PIN 0 means don't use INTx */
if (assigned_dev_pci_read_byte(&dev->dev, PCI_INTERRUPT_PIN) == 0) {
pci_device_set_intx_routing_notifier(&dev->dev, NULL);
return 0;
}
verify_irqchip_in_kernel(&local_err);
if (local_err) {
error_propagate(errp, local_err);
return -ENOTSUP;
}
pci_device_set_intx_routing_notifier(&dev->dev,
assigned_dev_update_irq_routing);
intx_route = pci_device_route_intx_to_irq(&dev->dev, dev->intpin);
assert(intx_route.mode != PCI_INTX_INVERTED);
if (!pci_intx_route_changed(&dev->intx_route, &intx_route)) {
return 0;
}
switch (dev->assigned_irq_type) {
case ASSIGNED_IRQ_INTX_HOST_INTX:
case ASSIGNED_IRQ_INTX_HOST_MSI:
intx_host_msi = dev->assigned_irq_type == ASSIGNED_IRQ_INTX_HOST_MSI;
r = kvm_device_intx_deassign(kvm_state, dev->dev_id, intx_host_msi);
break;
case ASSIGNED_IRQ_MSI:
r = kvm_device_msi_deassign(kvm_state, dev->dev_id);
break;
case ASSIGNED_IRQ_MSIX:
r = kvm_device_msix_deassign(kvm_state, dev->dev_id);
break;
default:
r = 0;
break;
}
if (r) {
perror("assign_intx: deassignment of previous interrupt failed");
}
dev->assigned_irq_type = ASSIGNED_IRQ_NONE;
if (intx_route.mode == PCI_INTX_DISABLED) {
dev->intx_route = intx_route;
return 0;
}
retry:
if (dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK &&
dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
intx_host_msi = true;
new_type = ASSIGNED_IRQ_INTX_HOST_MSI;
} else {
intx_host_msi = false;
new_type = ASSIGNED_IRQ_INTX_HOST_INTX;
}
r = kvm_device_intx_assign(kvm_state, dev->dev_id, intx_host_msi,
intx_route.irq);
if (r < 0) {
if (r == -EIO && !(dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK) &&
dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
/* Retry with host-side MSI. There might be an IRQ conflict and
* either the kernel or the device doesn't support sharing. */
error_report("Host-side INTx sharing not supported, "
"using MSI instead");
error_printf("Some devices do not work properly in this mode.\n");
dev->features |= ASSIGNED_DEVICE_PREFER_MSI_MASK;
goto retry;
}
error_setg_errno(errp, -r, "Failed to assign irq for \"%s\"",
dev->dev.qdev.id);
error_append_hint(errp, "Perhaps you are assigning a device "
"that shares an IRQ with another device?\n");
return r;
}
dev->intx_route = intx_route;
dev->assigned_irq_type = new_type;
return r;
}
| true | qemu | 6b728b31163bbd0788fe7d537931c4624cd24215 |
9,076 | static void gen_tlbwe_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
#else
if (unlikely(ctx->pr)) {
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
return;
}
switch (rB(ctx->opcode)) {
case 0:
gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
break;
case 1:
gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
break;
default:
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
break;
}
#endif
}
| true | qemu | 9b2fadda3e0196ffd485adde4fe9cdd6fae35300 |
9,077 | void do_sraw (void)
{
int32_t ret;
if (likely(!(T1 & 0x20UL))) {
if (likely((uint32_t)T1 != 0)) {
ret = (int32_t)T0 >> (T1 & 0x1fUL);
if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
xer_ca = 0;
} else {
xer_ca = 1;
}
} else {
ret = T0;
xer_ca = 0;
}
} else {
ret = (-1) * ((uint32_t)T0 >> 31);
if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
xer_ca = 0;
} else {
xer_ca = 1;
}
}
T0 = ret;
}
| true | qemu | 6f2d8978728c48ca46f5c01835438508aace5c64 |
9,078 | int qemu_sem_timedwait(QemuSemaphore *sem, int ms)
{
int rc;
struct timespec ts;
#if defined(__APPLE__) || defined(__NetBSD__)
compute_abs_deadline(&ts, ms);
pthread_mutex_lock(&sem->lock);
--sem->count;
while (sem->count < 0) {
rc = pthread_cond_timedwait(&sem->cond, &sem->lock, &ts);
if (rc == ETIMEDOUT) {
break;
}
if (rc != 0) {
error_exit(rc, __func__);
}
}
pthread_mutex_unlock(&sem->lock);
return (rc == ETIMEDOUT ? -1 : 0);
#else
if (ms <= 0) {
/* This is cheaper than sem_timedwait. */
do {
rc = sem_trywait(&sem->sem);
} while (rc == -1 && errno == EINTR);
if (rc == -1 && errno == EAGAIN) {
return -1;
}
} else {
compute_abs_deadline(&ts, ms);
do {
rc = sem_timedwait(&sem->sem, &ts);
} while (rc == -1 && errno == EINTR);
if (rc == -1 && errno == ETIMEDOUT) {
return -1;
}
}
if (rc < 0) {
error_exit(errno, __func__);
}
return 0;
#endif
} | true | qemu | a795ef8dcb8cbadffc996c41ff38927a97645234 |
9,080 | static void spatial_compose97i_dy(dwt_compose_t *cs, DWTELEM *buffer, int width, int height, int stride){
int y = cs->y;
DWTELEM *b0= cs->b0;
DWTELEM *b1= cs->b1;
DWTELEM *b2= cs->b2;
DWTELEM *b3= cs->b3;
DWTELEM *b4= buffer + mirror(y+3, height-1)*stride;
DWTELEM *b5= buffer + mirror(y+4, height-1)*stride;
if(stride == width && y+4 < height && 0){
int x;
for(x=0; x<width/2; x++)
b5[x] += 64*2;
for(; x<width; x++)
b5[x] += 169*2;
}
{START_TIMER
if(b3 <= b5) vertical_compose97iL1(b3, b4, b5, width);
if(b2 <= b4) vertical_compose97iH1(b2, b3, b4, width);
if(b1 <= b3) vertical_compose97iL0(b1, b2, b3, width);
if(b0 <= b2) vertical_compose97iH0(b0, b1, b2, width);
if(width>400){
STOP_TIMER("vertical_compose97i")}}
{START_TIMER
if(y-1>= 0) horizontal_compose97i(b0, width);
if(b0 <= b2) horizontal_compose97i(b1, width);
if(width>400 && b0 <= b2){
STOP_TIMER("horizontal_compose97i")}}
cs->b0=b2;
cs->b1=b3;
cs->b2=b4;
cs->b3=b5;
cs->y += 2;
}
| true | FFmpeg | 13705b69ebe9e375fdb52469760a0fbb5f593cc1 |
9,081 | static int nbd_co_receive_request(NBDRequestData *req, NBDRequest *request,
Error **errp)
{
NBDClient *client = req->client;
int valid_flags;
g_assert(qemu_in_coroutine());
assert(client->recv_coroutine == qemu_coroutine_self());
if (nbd_receive_request(client->ioc, request, errp) < 0) {
return -EIO;
}
trace_nbd_co_receive_request_decode_type(request->handle, request->type,
nbd_cmd_lookup(request->type));
if (request->type != NBD_CMD_WRITE) {
/* No payload, we are ready to read the next request. */
req->complete = true;
}
if (request->type == NBD_CMD_DISC) {
/* Special case: we're going to disconnect without a reply,
* whether or not flags, from, or len are bogus */
return -EIO;
}
/* Check for sanity in the parameters, part 1. Defer as many
* checks as possible until after reading any NBD_CMD_WRITE
* payload, so we can try and keep the connection alive. */
if ((request->from + request->len) < request->from) {
error_setg(errp,
"integer overflow detected, you're probably being attacked");
return -EINVAL;
}
if (request->type == NBD_CMD_READ || request->type == NBD_CMD_WRITE) {
if (request->len > NBD_MAX_BUFFER_SIZE) {
error_setg(errp, "len (%" PRIu32" ) is larger than max len (%u)",
request->len, NBD_MAX_BUFFER_SIZE);
return -EINVAL;
}
req->data = blk_try_blockalign(client->exp->blk, request->len);
if (req->data == NULL) {
error_setg(errp, "No memory");
return -ENOMEM;
}
}
if (request->type == NBD_CMD_WRITE) {
if (nbd_read(client->ioc, req->data, request->len, errp) < 0) {
error_prepend(errp, "reading from socket failed: ");
return -EIO;
}
req->complete = true;
trace_nbd_co_receive_request_payload_received(request->handle,
request->len);
}
/* Sanity checks, part 2. */
if (request->from + request->len > client->exp->size) {
error_setg(errp, "operation past EOF; From: %" PRIu64 ", Len: %" PRIu32
", Size: %" PRIu64, request->from, request->len,
(uint64_t)client->exp->size);
return request->type == NBD_CMD_WRITE ? -ENOSPC : -EINVAL;
}
valid_flags = NBD_CMD_FLAG_FUA;
if (request->type == NBD_CMD_READ && client->structured_reply) {
valid_flags |= NBD_CMD_FLAG_DF;
} else if (request->type == NBD_CMD_WRITE_ZEROES) {
valid_flags |= NBD_CMD_FLAG_NO_HOLE;
}
if (request->flags & ~valid_flags) {
error_setg(errp, "unsupported flags for command %s (got 0x%x)",
nbd_cmd_lookup(request->type), request->flags);
return -EINVAL;
}
return 0;
}
| true | qemu | fed5f8f82056c9f222433c41aeb9fca50c89f297 |
9,084 | void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
CPUARMState *env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_M)) {
/* M profile has no coprocessor registers */
return;
}
define_arm_cp_regs(cpu, cp_reginfo);
if (!arm_feature(env, ARM_FEATURE_V8)) {
/* Must go early as it is full of wildcards that may be
* overridden by later definitions.
*/
define_arm_cp_regs(cpu, not_v8_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V6)) {
/* The ID registers all have impdef reset values */
ARMCPRegInfo v6_idregs[] = {
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_pfr0 },
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_pfr1 },
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_dfr0 },
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_afr0 },
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr0 },
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr1 },
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr2 },
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr3 },
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_isar0 },
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_isar1 },
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_isar2 },
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_isar3 },
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_isar4 },
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_isar5 },
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr4 },
/* 7 is as yet unallocated and must RAZ */
{ .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, v6_idregs);
define_arm_cp_regs(cpu, v6_cp_reginfo);
} else {
define_arm_cp_regs(cpu, not_v6_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V6K)) {
define_arm_cp_regs(cpu, v6k_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7MP) &&
!arm_feature(env, ARM_FEATURE_PMSA)) {
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement only the cycle
* count register.
*/
#ifndef CONFIG_USER_ONLY
ARMCPRegInfo pmcr = {
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
.access = PL0_RW,
.type = ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
.accessfn = pmreg_access, .writefn = pmcr_write,
.raw_writefn = raw_write,
};
ARMCPRegInfo pmcr64 = {
.name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
.resetvalue = cpu->midr & 0xff000000,
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64);
#endif
ARMCPRegInfo clidr = {
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
};
define_one_arm_cp_reg(cpu, &clidr);
define_arm_cp_regs(cpu, v7_cp_reginfo);
define_debug_regs(cpu);
} else {
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V8)) {
/* AArch64 ID registers, which all have impdef reset values.
* Note that within the ID register ranges the unused slots
* must all RAZ, not UNDEF; future architecture versions may
* define new registers here.
*/
ARMCPRegInfo v8_idregs[] = {
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64pfr0 },
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64pfr1},
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64dfr0 },
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64dfr1 },
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64afr0 },
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64afr1 },
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64isar0 },
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64isar1 },
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64mmfr0 },
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_aa64mmfr1 },
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->mvfr0 },
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->mvfr1 },
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->mvfr2 },
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.resetvalue = cpu->pmceid0 },
{ .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.resetvalue = cpu->pmceid0 },
{ .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.resetvalue = cpu->pmceid1 },
{ .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.resetvalue = cpu->pmceid1 },
REGINFO_SENTINEL
};
/* RVBAR_EL1 is only implemented if EL1 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2)) {
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
}
define_arm_cp_regs(cpu, v8_idregs);
define_arm_cp_regs(cpu, v8_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_EL2)) {
uint64_t vmpidr_def = mpidr_read_val(env);
ARMCPRegInfo vpidr_regs[] = {
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
.resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL2_RW, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
.resetvalue = vmpidr_def,
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
.access = PL2_RW,
.resetvalue = vmpidr_def,
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vpidr_regs);
define_arm_cp_regs(cpu, el2_cp_reginfo);
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3)) {
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
}
} else {
/* If EL2 is missing but higher ELs are enabled, we need to
* register the no_el2 reginfos.
*/
if (arm_feature(env, ARM_FEATURE_EL3)) {
/* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
* of MIDR_EL1 and MPIDR_EL1.
*/
ARMCPRegInfo vpidr_regs[] = {
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
.type = ARM_CP_CONST, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
.type = ARM_CP_NO_RAW,
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vpidr_regs);
define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
}
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, el3_cp_reginfo);
ARMCPRegInfo el3_regs[] = {
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW,
.raw_writefn = raw_write, .writefn = sctlr_write,
.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
.resetvalue = cpu->reset_sctlr },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, el3_regs);
}
/* The behaviour of NSACR is sufficiently various that we don't
* try to describe it in a single reginfo:
* if EL3 is 64 bit, then trap to EL3 from S EL1,
* reads as constant 0xc00 from NS EL1 and NS EL2
* if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
* if v7 without EL3, register doesn't exist
* if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
*/
if (arm_feature(env, ARM_FEATURE_EL3)) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
ARMCPRegInfo nsacr = {
.name = "NSACR", .type = ARM_CP_CONST,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL1_RW, .accessfn = nsacr_access,
.resetvalue = 0xc00
};
define_one_arm_cp_reg(cpu, &nsacr);
} else {
ARMCPRegInfo nsacr = {
.name = "NSACR",
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL3_RW | PL1_R,
.resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.nsacr)
};
define_one_arm_cp_reg(cpu, &nsacr);
}
} else {
if (arm_feature(env, ARM_FEATURE_V8)) {
ARMCPRegInfo nsacr = {
.name = "NSACR", .type = ARM_CP_CONST,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL1_R,
.resetvalue = 0xc00
};
define_one_arm_cp_reg(cpu, &nsacr);
}
}
if (arm_feature(env, ARM_FEATURE_PMSA)) {
if (arm_feature(env, ARM_FEATURE_V6)) {
/* PMSAv6 not implemented */
assert(arm_feature(env, ARM_FEATURE_V7));
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
} else {
define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
}
} else {
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_VAPA)) {
define_arm_cp_regs(cpu, vapa_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
define_arm_cp_regs(cpu, omap_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
define_arm_cp_regs(cpu, strongarm_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
define_arm_cp_regs(cpu, xscale_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_LPAE)) {
define_arm_cp_regs(cpu, lpae_cp_reginfo);
}
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
* be read-only (ie write causes UNDEF exception).
*/
{
ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
/* Pre-v8 MIDR space.
* Note that the MIDR isn't a simple constant register because
* of the TI925 behaviour where writes to another register can
* cause the MIDR value to change.
*
* Unimplemented registers in the c15 0 0 0 space default to
* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
* and friends override accordingly.
*/
{ .name = "MIDR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .resetvalue = cpu->midr,
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
.readfn = midr_read,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.type = ARM_CP_OVERRIDE },
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
{ .name = "DUMMY",
.cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "DUMMY",
.cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "DUMMY",
.cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "DUMMY",
.cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "DUMMY",
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.readfn = midr_read },
/* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
.access = PL1_R, .resetvalue = cpu->midr },
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
.access = PL1_R, .resetvalue = cpu->midr },
{ .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
REGINFO_SENTINEL
};
ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */
{ .name = "CTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
{ .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
.access = PL0_R, .accessfn = ctr_el0_access,
.type = ARM_CP_CONST, .resetvalue = cpu->ctr },
/* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
{ .name = "TCMTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
/* TLBTR is specific to VMSA */
ARMCPRegInfo id_tlbtr_reginfo = {
.name = "TLBTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
};
/* MPUIR is specific to PMSA V6+ */
ARMCPRegInfo id_mpuir_reginfo = {
.name = "MPUIR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->pmsav7_dregion << 8
};
ARMCPRegInfo crn0_wi_reginfo = {
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
.type = ARM_CP_NOP | ARM_CP_OVERRIDE
};
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
arm_feature(env, ARM_FEATURE_STRONGARM)) {
ARMCPRegInfo *r;
/* Register the blanket "writes ignored" value first to cover the
* whole space. Then update the specific ID registers to allow write
* access, so that they ignore writes rather than causing them to
* UNDEF.
*/
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
for (r = id_pre_v8_midr_cp_reginfo;
r->type != ARM_CP_SENTINEL; r++) {
r->access = PL1_RW;
}
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
r->access = PL1_RW;
}
id_tlbtr_reginfo.access = PL1_RW;
id_tlbtr_reginfo.access = PL1_RW;
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
} else {
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
}
define_arm_cp_regs(cpu, id_cp_reginfo);
if (!arm_feature(env, ARM_FEATURE_PMSA)) {
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
}
}
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
define_arm_cp_regs(cpu, mpidr_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
ARMCPRegInfo auxcr_reginfo[] = {
{ .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST,
.resetvalue = cpu->reset_auxcr },
{ .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
{ .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL3_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, auxcr_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CBAR)) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
/* 32 bit view is [31:18] 0...0 [43:32]. */
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
| extract64(cpu->reset_cbar, 32, 12);
ARMCPRegInfo cbar_reginfo[] = {
{ .name = "CBAR",
.type = ARM_CP_CONST,
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
.access = PL1_R, .resetvalue = cpu->reset_cbar },
{ .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_CONST,
.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
.access = PL1_R, .resetvalue = cbar32 },
REGINFO_SENTINEL
};
/* We don't implement a r/w 64 bit CBAR currently */
assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
define_arm_cp_regs(cpu, cbar_reginfo);
} else {
ARMCPRegInfo cbar = {
.name = "CBAR",
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
.access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
.fieldoffset = offsetof(CPUARMState,
cp15.c15_config_base_address)
};
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
cbar.access = PL1_R;
cbar.fieldoffset = 0;
cbar.type = ARM_CP_CONST;
}
define_one_arm_cp_reg(cpu, &cbar);
}
}
if (arm_feature(env, ARM_FEATURE_VBAR)) {
ARMCPRegInfo vbar_cp_reginfo[] = {
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
offsetof(CPUARMState, cp15.vbar_ns) },
.resetvalue = 0 },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vbar_cp_reginfo);
}
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
.name = "SCTLR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL1_RW,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
offsetof(CPUARMState, cp15.sctlr_ns) },
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
.raw_writefn = raw_write,
};
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
/* Normally we would always end the TB on an SCTLR write, but Linux
* arch/arm/mach-pxa/sleep.S expects two instructions following
* an MMU enable to execute from cache. Imitate this behaviour.
*/
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
}
define_one_arm_cp_reg(cpu, &sctlr);
}
}
| true | qemu | 96a8b92ed8f02d5e86ad380d3299d9f41f99b072 |
9,085 | static void pci_nic_uninit(PCIDevice *pci_dev)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
eeprom93xx_free(&pci_dev->qdev, s->eeprom);
qemu_del_nic(s->nic);
} | true | qemu | 2634ab7fe29b3f75d0865b719caf8f310d634aae |
9,086 | void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
uint32_t val, old;
uint32_t mask = env->CP0_Status_rw_bitmask;
if (env->insn_flags & ISA_MIPS32R6) {
if (extract32(env->CP0_Status, CP0St_KSU, 2) == 0x3) {
mask &= ~(3 << CP0St_KSU);
}
mask &= ~(0x00180000 & arg1);
}
val = arg1 & mask;
old = env->CP0_Status;
env->CP0_Status = (env->CP0_Status & ~mask) | val;
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
sync_c0_status(env, env, env->current_tc);
} else {
compute_hflags(env);
}
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
old, old & env->CP0_Cause & CP0Ca_IP_mask,
val, val & env->CP0_Cause & CP0Ca_IP_mask,
env->CP0_Cause);
switch (env->hflags & MIPS_HFLAG_KSU) {
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
default:
cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
break;
}
}
}
| true | qemu | f88f79ec9df06d26d84e1d2e0c02d2634b4d8583 |
9,088 | void av_register_all(void)
{
static int initialized;
if (initialized)
return;
initialized = 1;
avcodec_init();
avcodec_register_all();
/* (de)muxers */
REGISTER_DEMUXER (AAC, aac);
REGISTER_MUXDEMUX (AC3, ac3);
REGISTER_MUXER (ADTS, adts);
REGISTER_MUXDEMUX (AIFF, aiff);
REGISTER_MUXDEMUX (AMR, amr);
REGISTER_DEMUXER (APC, apc);
REGISTER_DEMUXER (APE, ape);
REGISTER_MUXDEMUX (ASF, asf);
REGISTER_MUXER (ASF_STREAM, asf_stream);
REGISTER_MUXDEMUX (AU, au);
REGISTER_MUXDEMUX (AVI, avi);
REGISTER_DEMUXER (AVISYNTH, avisynth);
REGISTER_MUXER (AVM2, avm2);
REGISTER_DEMUXER (AVS, avs);
REGISTER_DEMUXER (BETHSOFTVID, bethsoftvid);
REGISTER_DEMUXER (BFI, bfi);
REGISTER_DEMUXER (C93, c93);
REGISTER_MUXER (CRC, crc);
REGISTER_DEMUXER (DAUD, daud);
REGISTER_MUXDEMUX (DIRAC, dirac);
REGISTER_DEMUXER (DSICIN, dsicin);
REGISTER_MUXDEMUX (DTS, dts);
REGISTER_MUXDEMUX (DV, dv);
REGISTER_DEMUXER (DXA, dxa);
REGISTER_DEMUXER (EA, ea);
REGISTER_DEMUXER (EA_CDATA, ea_cdata);
REGISTER_MUXDEMUX (FFM, ffm);
REGISTER_MUXDEMUX (FLAC, flac);
REGISTER_DEMUXER (FLIC, flic);
REGISTER_MUXDEMUX (FLV, flv);
REGISTER_DEMUXER (FOURXM, fourxm);
REGISTER_MUXER (FRAMECRC, framecrc);
REGISTER_MUXDEMUX (GIF, gif);
REGISTER_DEMUXER (GSM, gsm);
REGISTER_MUXDEMUX (GXF, gxf);
REGISTER_MUXDEMUX (H261, h261);
REGISTER_MUXDEMUX (H263, h263);
REGISTER_MUXDEMUX (H264, h264);
REGISTER_DEMUXER (IDCIN, idcin);
REGISTER_DEMUXER (IFF, iff);
REGISTER_MUXDEMUX (IMAGE2, image2);
REGISTER_MUXDEMUX (IMAGE2PIPE, image2pipe);
REGISTER_DEMUXER (INGENIENT, ingenient);
REGISTER_DEMUXER (IPMOVIE, ipmovie);
REGISTER_MUXER (IPOD, ipod);
REGISTER_DEMUXER (LMLM4, lmlm4);
REGISTER_MUXDEMUX (M4V, m4v);
REGISTER_MUXDEMUX (MATROSKA, matroska);
REGISTER_MUXER (MATROSKA_AUDIO, matroska_audio);
REGISTER_MUXDEMUX (MJPEG, mjpeg);
REGISTER_DEMUXER (MLP, mlp);
REGISTER_DEMUXER (MM, mm);
REGISTER_MUXDEMUX (MMF, mmf);
REGISTER_MUXDEMUX (MOV, mov);
REGISTER_MUXER (MP2, mp2);
REGISTER_MUXDEMUX (MP3, mp3);
REGISTER_MUXER (MP4, mp4);
REGISTER_DEMUXER (MPC, mpc);
REGISTER_DEMUXER (MPC8, mpc8);
REGISTER_MUXER (MPEG1SYSTEM, mpeg1system);
REGISTER_MUXER (MPEG1VCD, mpeg1vcd);
REGISTER_MUXER (MPEG1VIDEO, mpeg1video);
REGISTER_MUXER (MPEG2DVD, mpeg2dvd);
REGISTER_MUXER (MPEG2SVCD, mpeg2svcd);
REGISTER_MUXER (MPEG2VIDEO, mpeg2video);
REGISTER_MUXER (MPEG2VOB, mpeg2vob);
REGISTER_DEMUXER (MPEGPS, mpegps);
REGISTER_MUXDEMUX (MPEGTS, mpegts);
REGISTER_DEMUXER (MPEGTSRAW, mpegtsraw);
REGISTER_DEMUXER (MPEGVIDEO, mpegvideo);
REGISTER_MUXER (MPJPEG, mpjpeg);
REGISTER_DEMUXER (MSNWC_TCP, msnwc_tcp);
REGISTER_DEMUXER (MTV, mtv);
REGISTER_DEMUXER (MVI, mvi);
REGISTER_DEMUXER (MXF, mxf);
REGISTER_DEMUXER (NSV, nsv);
REGISTER_MUXER (NULL, null);
REGISTER_MUXDEMUX (NUT, nut);
REGISTER_DEMUXER (NUV, nuv);
REGISTER_MUXDEMUX (OGG, ogg);
REGISTER_DEMUXER (OMA, oma);
REGISTER_MUXDEMUX (PCM_ALAW, pcm_alaw);
REGISTER_MUXDEMUX (PCM_MULAW, pcm_mulaw);
REGISTER_MUXDEMUX (PCM_S16BE, pcm_s16be);
REGISTER_MUXDEMUX (PCM_S16LE, pcm_s16le);
REGISTER_MUXDEMUX (PCM_S8, pcm_s8);
REGISTER_MUXDEMUX (PCM_U16BE, pcm_u16be);
REGISTER_MUXDEMUX (PCM_U16LE, pcm_u16le);
REGISTER_MUXDEMUX (PCM_U8, pcm_u8);
REGISTER_MUXER (PSP, psp);
REGISTER_DEMUXER (PVA, pva);
REGISTER_MUXDEMUX (RAWVIDEO, rawvideo);
REGISTER_DEMUXER (REDIR, redir);
REGISTER_DEMUXER (RL2, rl2);
REGISTER_MUXDEMUX (RM, rm);
REGISTER_MUXDEMUX (ROQ, roq);
REGISTER_DEMUXER (RPL, rpl);
REGISTER_MUXER (RTP, rtp);
REGISTER_DEMUXER (RTSP, rtsp);
REGISTER_DEMUXER (SDP, sdp);
#ifdef CONFIG_SDP_DEMUXER
av_register_rtp_dynamic_payload_handlers();
#endif
REGISTER_DEMUXER (SEGAFILM, segafilm);
REGISTER_DEMUXER (SHORTEN, shorten);
REGISTER_DEMUXER (SIFF, siff);
REGISTER_DEMUXER (SMACKER, smacker);
REGISTER_DEMUXER (SOL, sol);
REGISTER_DEMUXER (STR, str);
REGISTER_MUXDEMUX (SWF, swf);
REGISTER_MUXER (TG2, tg2);
REGISTER_MUXER (TGP, tgp);
REGISTER_DEMUXER (THP, thp);
REGISTER_DEMUXER (TIERTEXSEQ, tiertexseq);
REGISTER_DEMUXER (TTA, tta);
REGISTER_DEMUXER (TXD, txd);
REGISTER_DEMUXER (VC1, vc1);
REGISTER_DEMUXER (VC1T, vc1t);
REGISTER_DEMUXER (VMD, vmd);
REGISTER_MUXDEMUX (VOC, voc);
REGISTER_MUXDEMUX (WAV, wav);
REGISTER_DEMUXER (WC3, wc3);
REGISTER_DEMUXER (WSAUD, wsaud);
REGISTER_DEMUXER (WSVQA, wsvqa);
REGISTER_DEMUXER (WV, wv);
REGISTER_DEMUXER (XA, xa);
REGISTER_MUXDEMUX (YUV4MPEGPIPE, yuv4mpegpipe);
/* external libraries */
REGISTER_MUXDEMUX (LIBNUT, libnut);
/* protocols */
REGISTER_PROTOCOL (FILE, file);
REGISTER_PROTOCOL (HTTP, http);
REGISTER_PROTOCOL (PIPE, pipe);
REGISTER_PROTOCOL (RTP, rtp);
REGISTER_PROTOCOL (TCP, tcp);
REGISTER_PROTOCOL (UDP, udp);
}
| true | FFmpeg | 0b54f3c0878a3acaa9142e4f24942e762d97e350 |
9,090 | static void vfio_pci_size_rom(VFIODevice *vdev)
{
uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK);
off_t offset = vdev->config_offset + PCI_ROM_ADDRESS;
char name[32];
if (vdev->pdev.romfile || !vdev->pdev.rom_bar) {
return;
}
/*
* Use the same size ROM BAR as the physical device. The contents
* will get filled in later when the guest tries to read it.
*/
if (pread(vdev->fd, &orig, 4, offset) != 4 ||
pwrite(vdev->fd, &size, 4, offset) != 4 ||
pread(vdev->fd, &size, 4, offset) != 4 ||
pwrite(vdev->fd, &orig, 4, offset) != 4) {
error_report("%s(%04x:%02x:%02x.%x) failed: %m",
__func__, vdev->host.domain, vdev->host.bus,
vdev->host.slot, vdev->host.function);
return;
}
size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1;
if (!size) {
return;
}
DPRINTF("%04x:%02x:%02x.%x ROM size 0x%x\n", vdev->host.domain,
vdev->host.bus, vdev->host.slot, vdev->host.function, size);
snprintf(name, sizeof(name), "vfio[%04x:%02x:%02x.%x].rom",
vdev->host.domain, vdev->host.bus, vdev->host.slot,
vdev->host.function);
memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev),
&vfio_rom_ops, vdev, name, size);
pci_register_bar(&vdev->pdev, PCI_ROM_SLOT,
PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom);
vdev->pdev.has_rom = true;
} | true | qemu | e638073c569e801ce9def2016a84f955cbbca779 |
9,092 | void OPPROTO op_POWER_sraq (void)
{
env->spr[SPR_MQ] = rotl32(T0, 32 - (T1 & 0x1FUL));
if (T1 & 0x20UL)
T0 = -1L;
else
T0 = Ts0 >> T1;
RETURN();
}
| true | qemu | d9bce9d99f4656ae0b0127f7472db9067b8f84ab |
9,093 | static int shorten_decode_frame(AVCodecContext *avctx,
void *data, int *data_size,
AVPacket *avpkt)
{
const uint8_t *buf = avpkt->data;
int buf_size = avpkt->size;
ShortenContext *s = avctx->priv_data;
int i, input_buf_size = 0;
int16_t *samples = data;
int ret;
/* allocate internal bitstream buffer */
if(s->max_framesize == 0){
void *tmp_ptr;
s->max_framesize= 1024; // should hopefully be enough for the first header
tmp_ptr = av_fast_realloc(s->bitstream, &s->allocated_bitstream_size,
s->max_framesize);
if (!tmp_ptr) {
av_log(avctx, AV_LOG_ERROR, "error allocating bitstream buffer\n");
return AVERROR(ENOMEM);
}
s->bitstream = tmp_ptr;
}
/* append current packet data to bitstream buffer */
if(1 && s->max_framesize){//FIXME truncated
buf_size= FFMIN(buf_size, s->max_framesize - s->bitstream_size);
input_buf_size= buf_size;
if(s->bitstream_index + s->bitstream_size + buf_size > s->allocated_bitstream_size){
memmove(s->bitstream, &s->bitstream[s->bitstream_index], s->bitstream_size);
s->bitstream_index=0;
}
memcpy(&s->bitstream[s->bitstream_index + s->bitstream_size], buf, buf_size);
buf= &s->bitstream[s->bitstream_index];
buf_size += s->bitstream_size;
s->bitstream_size= buf_size;
/* do not decode until buffer has at least max_framesize bytes */
if(buf_size < s->max_framesize){
*data_size = 0;
return input_buf_size;
}
}
/* init and position bitstream reader */
init_get_bits(&s->gb, buf, buf_size*8);
skip_bits(&s->gb, s->bitindex);
/* process header or next subblock */
if (!s->blocksize)
{
if ((ret = read_header(s)) < 0)
return ret;
*data_size = 0;
}
else
{
int cmd;
int len;
cmd = get_ur_golomb_shorten(&s->gb, FNSIZE);
if (cmd > FN_VERBATIM) {
av_log(avctx, AV_LOG_ERROR, "unknown shorten function %d\n", cmd);
if (s->bitstream_size > 0) {
s->bitstream_index++;
s->bitstream_size--;
}
return -1;
}
if (!is_audio_command[cmd]) {
/* process non-audio command */
switch (cmd) {
case FN_VERBATIM:
len = get_ur_golomb_shorten(&s->gb, VERBATIM_CKSIZE_SIZE);
while (len--) {
get_ur_golomb_shorten(&s->gb, VERBATIM_BYTE_SIZE);
}
break;
case FN_BITSHIFT:
s->bitshift = get_ur_golomb_shorten(&s->gb, BITSHIFTSIZE);
break;
case FN_BLOCKSIZE: {
int blocksize = get_uint(s, av_log2(s->blocksize));
if (blocksize > s->blocksize) {
av_log(avctx, AV_LOG_ERROR, "Increasing block size is not supported\n");
return AVERROR_PATCHWELCOME;
}
if (!blocksize || blocksize > MAX_BLOCKSIZE) {
av_log(avctx, AV_LOG_ERROR, "invalid or unsupported "
"block size: %d\n", blocksize);
return AVERROR(EINVAL);
}
s->blocksize = blocksize;
break;
}
case FN_QUIT:
break;
}
*data_size = 0;
} else {
/* process audio command */
int residual_size = 0;
int channel = s->cur_chan;
int32_t coffset;
/* get Rice code for residual decoding */
if (cmd != FN_ZERO) {
residual_size = get_ur_golomb_shorten(&s->gb, ENERGYSIZE);
/* this is a hack as version 0 differed in defintion of get_sr_golomb_shorten */
if (s->version == 0)
residual_size--;
}
/* calculate sample offset using means from previous blocks */
if (s->nmean == 0)
coffset = s->offset[channel][0];
else {
int32_t sum = (s->version < 2) ? 0 : s->nmean / 2;
for (i=0; i<s->nmean; i++)
sum += s->offset[channel][i];
coffset = sum / s->nmean;
if (s->version >= 2)
coffset >>= FFMIN(1, s->bitshift);
}
/* decode samples for this channel */
if (cmd == FN_ZERO) {
for (i=0; i<s->blocksize; i++)
s->decoded[channel][i] = 0;
} else {
if ((ret = decode_subframe_lpc(s, cmd, channel, residual_size, coffset)) < 0)
return ret;
}
/* update means with info from the current block */
if (s->nmean > 0) {
int32_t sum = (s->version < 2) ? 0 : s->blocksize / 2;
for (i=0; i<s->blocksize; i++)
sum += s->decoded[channel][i];
for (i=1; i<s->nmean; i++)
s->offset[channel][i-1] = s->offset[channel][i];
if (s->version < 2)
s->offset[channel][s->nmean - 1] = sum / s->blocksize;
else
s->offset[channel][s->nmean - 1] = (sum / s->blocksize) << s->bitshift;
}
/* copy wrap samples for use with next block */
for (i=-s->nwrap; i<0; i++)
s->decoded[channel][i] = s->decoded[channel][i + s->blocksize];
/* shift samples to add in unused zero bits which were removed
during encoding */
fix_bitshift(s, s->decoded[channel]);
/* if this is the last channel in the block, output the samples */
s->cur_chan++;
if (s->cur_chan == s->channels) {
samples = interleave_buffer(samples, s->channels, s->blocksize, s->decoded);
s->cur_chan = 0;
*data_size = (int8_t *)samples - (int8_t *)data;
} else {
*data_size = 0;
}
}
}
s->bitindex = get_bits_count(&s->gb) - 8*((get_bits_count(&s->gb))/8);
i= (get_bits_count(&s->gb))/8;
if (i > buf_size) {
av_log(s->avctx, AV_LOG_ERROR, "overread: %d\n", i - buf_size);
s->bitstream_size=0;
s->bitstream_index=0;
return -1;
}
if (s->bitstream_size) {
s->bitstream_index += i;
s->bitstream_size -= i;
return input_buf_size;
} else
return i;
}
| false | FFmpeg | 882dafe9b666a7333d1b256fafe63e35dc582e3f |
9,096 | void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
int secondary_ide_enabled)
{
PCIDevice *dev;
dev = pci_create(bus, -1, "CMD646 IDE");
qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
qdev_init(&dev->qdev);
pci_ide_create_devs(dev, hd_table);
}
| true | qemu | e23a1b33b53d25510320b26d9f154e19c6c99725 |
9,097 | static av_cold int avisynth_load_library(void) {
avs_library = av_mallocz(sizeof(AviSynthLibrary));
if (!avs_library)
return AVERROR_UNKNOWN;
avs_library->library = LoadLibrary(AVISYNTH_LIB);
if (!avs_library->library)
goto init_fail;
#define LOAD_AVS_FUNC(name, continue_on_fail) \
{ \
avs_library->name = (void*)GetProcAddress(avs_library->library, #name); \
if(!continue_on_fail && !avs_library->name) \
goto fail; \
}
LOAD_AVS_FUNC(avs_bit_blt, 0);
LOAD_AVS_FUNC(avs_clip_get_error, 0);
LOAD_AVS_FUNC(avs_create_script_environment, 0);
LOAD_AVS_FUNC(avs_delete_script_environment, 0);
LOAD_AVS_FUNC(avs_get_audio, 0);
LOAD_AVS_FUNC(avs_get_error, 1); // New to AviSynth 2.6
LOAD_AVS_FUNC(avs_get_frame, 0);
LOAD_AVS_FUNC(avs_get_video_info, 0);
LOAD_AVS_FUNC(avs_invoke, 0);
LOAD_AVS_FUNC(avs_release_clip, 0);
LOAD_AVS_FUNC(avs_release_value, 0);
LOAD_AVS_FUNC(avs_release_video_frame, 0);
LOAD_AVS_FUNC(avs_take_clip, 0);
#undef LOAD_AVS_FUNC
atexit(avisynth_atexit_handler);
return 0;
fail:
FreeLibrary(avs_library->library);
init_fail:
av_freep(&avs_library);
return AVERROR_UNKNOWN;
} | true | FFmpeg | 9db353bc4727d2a184778c110cf4ea0b9d1616cb |
9,098 | static int mjpegb_decode_frame(AVCodecContext *avctx,
void *data, int *data_size,
uint8_t *buf, int buf_size)
{
MJpegDecodeContext *s = avctx->priv_data;
uint8_t *buf_end, *buf_ptr;
AVFrame *picture = data;
GetBitContext hgb; /* for the header */
uint32_t dqt_offs, dht_offs, sof_offs, sos_offs, second_field_offs;
uint32_t field_size, sod_offs;
buf_ptr = buf;
buf_end = buf + buf_size;
read_header:
/* reset on every SOI */
s->restart_interval = 0;
s->restart_count = 0;
s->mjpb_skiptosod = 0;
init_get_bits(&hgb, buf_ptr, /*buf_size*/(buf_end - buf_ptr)*8);
skip_bits(&hgb, 32); /* reserved zeros */
if (get_bits_long(&hgb, 32) != MKBETAG('m','j','p','g'))
{
av_log(avctx, AV_LOG_WARNING, "not mjpeg-b (bad fourcc)\n");
return 0;
}
field_size = get_bits_long(&hgb, 32); /* field size */
av_log(avctx, AV_LOG_DEBUG, "field size: 0x%x\n", field_size);
skip_bits(&hgb, 32); /* padded field size */
second_field_offs = get_bits_long(&hgb, 32);
av_log(avctx, AV_LOG_DEBUG, "second field offs: 0x%x\n", second_field_offs);
if (second_field_offs)
s->interlaced = 1;
dqt_offs = get_bits_long(&hgb, 32);
av_log(avctx, AV_LOG_DEBUG, "dqt offs: 0x%x\n", dqt_offs);
if (dqt_offs)
{
init_get_bits(&s->gb, buf+dqt_offs, (buf_end - (buf+dqt_offs))*8);
s->start_code = DQT;
mjpeg_decode_dqt(s);
}
dht_offs = get_bits_long(&hgb, 32);
av_log(avctx, AV_LOG_DEBUG, "dht offs: 0x%x\n", dht_offs);
if (dht_offs)
{
init_get_bits(&s->gb, buf+dht_offs, (buf_end - (buf+dht_offs))*8);
s->start_code = DHT;
mjpeg_decode_dht(s);
}
sof_offs = get_bits_long(&hgb, 32);
av_log(avctx, AV_LOG_DEBUG, "sof offs: 0x%x\n", sof_offs);
if (sof_offs)
{
init_get_bits(&s->gb, buf+sof_offs, (buf_end - (buf+sof_offs))*8);
s->start_code = SOF0;
if (mjpeg_decode_sof(s) < 0)
return -1;
}
sos_offs = get_bits_long(&hgb, 32);
av_log(avctx, AV_LOG_DEBUG, "sos offs: 0x%x\n", sos_offs);
sod_offs = get_bits_long(&hgb, 32);
av_log(avctx, AV_LOG_DEBUG, "sod offs: 0x%x\n", sod_offs);
if (sos_offs)
{
// init_get_bits(&s->gb, buf+sos_offs, (buf_end - (buf+sos_offs))*8);
init_get_bits(&s->gb, buf+sos_offs, field_size*8);
s->mjpb_skiptosod = (sod_offs - sos_offs - show_bits(&s->gb, 16));
s->start_code = SOS;
mjpeg_decode_sos(s);
}
if (s->interlaced) {
s->bottom_field ^= 1;
/* if not bottom field, do not output image yet */
if (s->bottom_field && second_field_offs)
{
buf_ptr = buf + second_field_offs;
second_field_offs = 0;
goto read_header;
}
}
//XXX FIXME factorize, this looks very similar to the EOI code
*picture= s->picture;
*data_size = sizeof(AVFrame);
if(!s->lossless){
picture->quality= FFMAX(FFMAX(s->qscale[0], s->qscale[1]), s->qscale[2]);
picture->qstride= 0;
picture->qscale_table= s->qscale_table;
memset(picture->qscale_table, picture->quality, (s->width+15)/16);
if(avctx->debug & FF_DEBUG_QP)
av_log(avctx, AV_LOG_DEBUG, "QP: %d\n", picture->quality);
picture->quality*= FF_QP2LAMBDA;
}
return buf_ptr - buf;
}
| true | FFmpeg | 6c3dba5760a18dff23213d0c4de7f57065a4648c |
9,099 | static int dv_write_header(AVFormatContext *s)
{
s->priv_data = dv_init_mux(s);
if (!s->priv_data) {
av_log(s, AV_LOG_ERROR, "Can't initialize DV format!\n"
"Make sure that you supply exactly two streams:\n"
" video: 25fps or 29.97fps, audio: 2ch/48Khz/PCM\n"
" (50Mbps allows an optional second audio stream)\n");
return -1;
}
return 0;
}
| true | FFmpeg | 0008afc59c240271827d8a0fc747179da905050f |
9,100 | static void print_type_size(Visitor *v, uint64_t *obj, const char *name,
Error **errp)
{
StringOutputVisitor *sov = DO_UPCAST(StringOutputVisitor, visitor, v);
static const char suffixes[] = { 'B', 'K', 'M', 'G', 'T' };
uint64_t div, val;
char *out;
int i;
if (!sov->human) {
out = g_strdup_printf("%llu", (long long) *obj);
string_output_set(sov, out);
return;
}
val = *obj;
/* Compute floor(log2(val)). */
i = 64 - clz64(val);
/* Find the power of 1024 that we'll display as the units. */
i /= 10;
if (i >= ARRAY_SIZE(suffixes)) {
i = ARRAY_SIZE(suffixes) - 1;
}
div = 1ULL << (i * 10);
out = g_strdup_printf("%0.03f%c", (double)val/div, suffixes[i]);
string_output_set(sov, out);
}
| true | qemu | e41b509d68afb1f329c8558b6edfe2fcbac88e66 |
9,102 | static void avc_h_loop_filter_chroma422_msa(uint8_t *src,
int32_t stride,
int32_t alpha_in,
int32_t beta_in,
int8_t *tc0)
{
int32_t col, tc_val;
int16_t out0, out1, out2, out3;
v16u8 alpha, beta, res;
alpha = (v16u8) __msa_fill_b(alpha_in);
beta = (v16u8) __msa_fill_b(beta_in);
for (col = 0; col < 4; col++) {
tc_val = (tc0[col] - 1) + 1;
if (tc_val <= 0) {
src += (4 * stride);
continue;
}
AVC_LPF_H_CHROMA_422(src, stride, tc_val, alpha, beta, res);
out0 = __msa_copy_s_h((v8i16) res, 0);
out1 = __msa_copy_s_h((v8i16) res, 1);
out2 = __msa_copy_s_h((v8i16) res, 2);
out3 = __msa_copy_s_h((v8i16) res, 3);
STORE_HWORD((src - 1), out0);
src += stride;
STORE_HWORD((src - 1), out1);
src += stride;
STORE_HWORD((src - 1), out2);
src += stride;
STORE_HWORD((src - 1), out3);
src += stride;
}
}
| false | FFmpeg | bcd7bf7eeb09a395cc01698842d1b8be9af483fc |
9,103 | static int test_vector_dmac_scalar(AVFloatDSPContext *fdsp, AVFloatDSPContext *cdsp,
const double *v1, const double *src0, double scale)
{
LOCAL_ALIGNED(32, double, cdst, [LEN]);
LOCAL_ALIGNED(32, double, odst, [LEN]);
int ret;
memcpy(cdst, v1, LEN * sizeof(*v1));
memcpy(odst, v1, LEN * sizeof(*v1));
cdsp->vector_dmac_scalar(cdst, src0, scale, LEN);
fdsp->vector_dmac_scalar(odst, src0, scale, LEN);
if (ret = compare_doubles(cdst, odst, LEN, ARBITRARY_DMAC_SCALAR_CONST))
av_log(NULL, AV_LOG_ERROR, "vector_dmac_scalar failed\n");
return ret;
}
| false | FFmpeg | e53c9065ca08a9153ecc73a6a8940bcc6d667e58 |
9,104 | static av_always_inline int cmp_inline(MpegEncContext *s, const int x, const int y, const int subx, const int suby,
const int size, const int h, int ref_index, int src_index,
me_cmp_func cmp_func, me_cmp_func chroma_cmp_func, int qpel, int chroma){
MotionEstContext * const c= &s->me;
const int stride= c->stride;
const int uvstride= c->uvstride;
const int dxy= subx + (suby<<(1+qpel)); //FIXME log2_subpel?
const int hx= subx + (x<<(1+qpel));
const int hy= suby + (y<<(1+qpel));
uint8_t * const * const ref= c->ref[ref_index];
uint8_t * const * const src= c->src[src_index];
int d;
//FIXME check chroma 4mv, (no crashes ...)
int uvdxy; /* no, it might not be used uninitialized */
if(dxy){
if(qpel){
c->qpel_put[size][dxy](c->temp, ref[0] + x + y*stride, stride); //FIXME prototype (add h)
if(chroma){
int cx= hx/2;
int cy= hy/2;
cx= (cx>>1)|(cx&1);
cy= (cy>>1)|(cy&1);
uvdxy= (cx&1) + 2*(cy&1);
//FIXME x/y wrong, but mpeg4 qpel is sick anyway, we should drop as much of it as possible in favor for h264
}
}else{
c->hpel_put[size][dxy](c->temp, ref[0] + x + y*stride, stride, h);
if(chroma)
uvdxy= dxy | (x&1) | (2*(y&1));
}
d = cmp_func(s, c->temp, src[0], stride, h);
}else{
d = cmp_func(s, src[0], ref[0] + x + y*stride, stride, h);
if(chroma)
uvdxy= (x&1) + 2*(y&1);
}
if(chroma){
uint8_t * const uvtemp= c->temp + 16*stride;
c->hpel_put[size+1][uvdxy](uvtemp , ref[1] + (x>>1) + (y>>1)*uvstride, uvstride, h>>1);
c->hpel_put[size+1][uvdxy](uvtemp+8, ref[2] + (x>>1) + (y>>1)*uvstride, uvstride, h>>1);
d += chroma_cmp_func(s, uvtemp , src[1], uvstride, h>>1);
d += chroma_cmp_func(s, uvtemp+8, src[2], uvstride, h>>1);
}
return d;
}
| false | FFmpeg | b50e003e1cb6a215df44ffa3354603bf600b4aa3 |
9,105 | static void do_video_out(AVFormatContext *s, OutputStream *ost,
InputStream *ist, AVFrame *in_picture)
{
int nb_frames, i, ret, format_video_sync;
AVFrame *final_picture;
AVCodecContext *enc;
double sync_ipts;
double duration = 0;
int frame_size = 0;
float quality = same_quant ? in_picture->quality
: ost->st->codec->global_quality;
enc = ost->st->codec;
if (ist->st->start_time != AV_NOPTS_VALUE && ist->st->first_dts != AV_NOPTS_VALUE) {
duration = FFMAX(av_q2d(ist->st->time_base), av_q2d(ist->st->codec->time_base));
if(ist->st->avg_frame_rate.num)
duration= FFMAX(duration, 1/av_q2d(ist->st->avg_frame_rate));
duration /= av_q2d(enc->time_base);
}
sync_ipts = get_sync_ipts(ost, in_picture->pts) / av_q2d(enc->time_base);
/* by default, we output a single frame */
nb_frames = 1;
format_video_sync = video_sync_method;
if (format_video_sync == VSYNC_AUTO)
format_video_sync = (s->oformat->flags & AVFMT_VARIABLE_FPS) ? ((s->oformat->flags & AVFMT_NOTIMESTAMPS) ? VSYNC_PASSTHROUGH : VSYNC_VFR) : 1;
if (format_video_sync != VSYNC_PASSTHROUGH && format_video_sync != VSYNC_DROP) {
double vdelta = sync_ipts - ost->sync_opts + duration;
// FIXME set to 0.5 after we fix some dts/pts bugs like in avidec.c
if (vdelta < -1.1)
nb_frames = 0;
else if (format_video_sync == VSYNC_VFR) {
if (vdelta <= -0.6) {
nb_frames = 0;
} else if (vdelta > 0.6)
ost->sync_opts = lrintf(sync_ipts);
} else if (vdelta > 1.1)
nb_frames = lrintf(vdelta);
if (nb_frames == 0) {
++nb_frames_drop;
av_log(NULL, AV_LOG_VERBOSE, "*** drop!\n");
} else if (nb_frames > 1) {
nb_frames_dup += nb_frames - 1;
av_log(NULL, AV_LOG_VERBOSE, "*** %d dup!\n", nb_frames - 1);
}
} else
ost->sync_opts = lrintf(sync_ipts);
nb_frames = FFMIN(nb_frames, ost->max_frames - ost->frame_number);
if (nb_frames <= 0)
return;
do_video_resample(ost, ist, in_picture, &final_picture);
/* duplicates frame if needed */
for (i = 0; i < nb_frames; i++) {
AVPacket pkt;
av_init_packet(&pkt);
pkt.data = NULL;
pkt.size = 0;
if (s->oformat->flags & AVFMT_RAWPICTURE &&
enc->codec->id == CODEC_ID_RAWVIDEO) {
/* raw pictures are written as AVPicture structure to
avoid any copies. We support temporarily the older
method. */
enc->coded_frame->interlaced_frame = in_picture->interlaced_frame;
enc->coded_frame->top_field_first = in_picture->top_field_first;
pkt.data = (uint8_t *)final_picture;
pkt.size = sizeof(AVPicture);
pkt.pts = av_rescale_q(ost->sync_opts, enc->time_base, ost->st->time_base);
pkt.flags |= AV_PKT_FLAG_KEY;
write_frame(s, &pkt, ost);
} else {
int got_packet;
AVFrame big_picture;
big_picture = *final_picture;
/* better than nothing: use input picture interlaced
settings */
big_picture.interlaced_frame = in_picture->interlaced_frame;
if (ost->st->codec->flags & (CODEC_FLAG_INTERLACED_DCT|CODEC_FLAG_INTERLACED_ME)) {
if (ost->top_field_first == -1)
big_picture.top_field_first = in_picture->top_field_first;
else
big_picture.top_field_first = !!ost->top_field_first;
}
/* handles same_quant here. This is not correct because it may
not be a global option */
big_picture.quality = quality;
if (!enc->me_threshold)
big_picture.pict_type = 0;
big_picture.pts = ost->sync_opts;
if (ost->forced_kf_index < ost->forced_kf_count &&
big_picture.pts >= ost->forced_kf_pts[ost->forced_kf_index]) {
big_picture.pict_type = AV_PICTURE_TYPE_I;
ost->forced_kf_index++;
}
ret = avcodec_encode_video2(enc, &pkt, &big_picture, &got_packet);
if (ret < 0) {
av_log(NULL, AV_LOG_FATAL, "Video encoding failed\n");
exit_program(1);
}
if (got_packet) {
if (pkt.pts == AV_NOPTS_VALUE && !(enc->codec->capabilities & CODEC_CAP_DELAY))
pkt.pts = ost->sync_opts;
if (pkt.pts != AV_NOPTS_VALUE)
pkt.pts = av_rescale_q(pkt.pts, enc->time_base, ost->st->time_base);
if (pkt.dts != AV_NOPTS_VALUE)
pkt.dts = av_rescale_q(pkt.dts, enc->time_base, ost->st->time_base);
if (debug_ts) {
av_log(NULL, AV_LOG_INFO, "encoder -> type:video "
"pkt_pts:%s pkt_pts_time:%s pkt_dts:%s pkt_dts_time:%s\n",
av_ts2str(pkt.pts), av_ts2timestr(pkt.pts, &ost->st->time_base),
av_ts2str(pkt.dts), av_ts2timestr(pkt.dts, &ost->st->time_base));
}
if (format_video_sync == VSYNC_DROP)
pkt.pts = pkt.dts = AV_NOPTS_VALUE;
write_frame(s, &pkt, ost);
frame_size = pkt.size;
video_size += pkt.size;
/* if two pass, output log */
if (ost->logfile && enc->stats_out) {
fprintf(ost->logfile, "%s", enc->stats_out);
}
}
}
ost->sync_opts++;
/*
* For video, number of frames in == number of packets out.
* But there may be reordering, so we can't throw away frames on encoder
* flush, we need to limit them here, before they go into encoder.
*/
ost->frame_number++;
}
if (vstats_filename && frame_size)
do_video_stats(output_files[ost->file_index].ctx, ost, frame_size);
} | true | FFmpeg | 6a3f1726af914183ee9b735b6b28e79f0383058d |
9,107 | ssize_t migrate_fd_put_buffer(void *opaque, const void *data, size_t size)
{
FdMigrationState *s = opaque;
ssize_t ret;
do {
ret = s->write(s, data, size);
} while (ret == -1 && ((s->get_error(s)) == EINTR));
if (ret == -1)
ret = -(s->get_error(s));
if (ret == -EAGAIN) {
qemu_set_fd_handler2(s->fd, NULL, NULL, migrate_fd_put_notify, s);
} else if (ret < 0) {
s->state = MIG_STATE_ERROR;
notifier_list_notify(&migration_state_notifiers, NULL);
}
return ret;
}
| true | qemu | 2350e13c93c28f717e2ba1b31560b49ac6f81d4d |
9,108 | static void do_sdl_resize(int new_width, int new_height, int bpp)
{
int flags;
// printf("resizing to %d %d\n", w, h);
flags = SDL_HWSURFACE|SDL_ASYNCBLIT|SDL_HWACCEL|SDL_RESIZABLE;
if (gui_fullscreen)
flags |= SDL_FULLSCREEN;
if (gui_noframe)
flags |= SDL_NOFRAME;
width = new_width;
height = new_height;
real_screen = SDL_SetVideoMode(width, height, bpp, flags);
if (!real_screen) {
fprintf(stderr, "Could not open SDL display (%dx%dx%d): %s\n", width,
height, bpp, SDL_GetError());
exit(1);
}
}
| true | qemu | 91ada9808408fcad818ced7309f47c5fb91c6075 |
9,111 | static int wavpack_decode_block(AVCodecContext *avctx, int block_no,
AVFrame *frame, const uint8_t *buf, int buf_size)
{
WavpackContext *wc = avctx->priv_data;
ThreadFrame tframe = { .f = frame };
WavpackFrameContext *s;
GetByteContext gb;
void *samples_l = NULL, *samples_r = NULL;
int ret;
int got_terms = 0, got_weights = 0, got_samples = 0,
got_entropy = 0, got_bs = 0, got_float = 0, got_hybrid = 0;
int i, j, id, size, ssize, weights, t;
int bpp, chan = 0, chmask = 0, orig_bpp, sample_rate = 0;
int multiblock;
if (block_no >= wc->fdec_num && wv_alloc_frame_context(wc) < 0) {
av_log(avctx, AV_LOG_ERROR, "Error creating frame decode context\n");
return AVERROR_INVALIDDATA;
}
s = wc->fdec[block_no];
if (!s) {
av_log(avctx, AV_LOG_ERROR, "Context for block %d is not present\n",
block_no);
return AVERROR_INVALIDDATA;
}
memset(s->decorr, 0, MAX_TERMS * sizeof(Decorr));
memset(s->ch, 0, sizeof(s->ch));
s->extra_bits = 0;
s->and = s->or = s->shift = 0;
s->got_extra_bits = 0;
bytestream2_init(&gb, buf, buf_size);
s->samples = bytestream2_get_le32(&gb);
if (s->samples != wc->samples) {
av_log(avctx, AV_LOG_ERROR, "Mismatching number of samples in "
"a sequence: %d and %d\n", wc->samples, s->samples);
return AVERROR_INVALIDDATA;
}
s->frame_flags = bytestream2_get_le32(&gb);
bpp = av_get_bytes_per_sample(avctx->sample_fmt);
orig_bpp = ((s->frame_flags & 0x03) + 1) << 3;
multiblock = (s->frame_flags & WV_SINGLE_BLOCK) != WV_SINGLE_BLOCK;
s->stereo = !(s->frame_flags & WV_MONO);
s->stereo_in = (s->frame_flags & WV_FALSE_STEREO) ? 0 : s->stereo;
s->joint = s->frame_flags & WV_JOINT_STEREO;
s->hybrid = s->frame_flags & WV_HYBRID_MODE;
s->hybrid_bitrate = s->frame_flags & WV_HYBRID_BITRATE;
s->post_shift = bpp * 8 - orig_bpp + ((s->frame_flags >> 13) & 0x1f);
s->hybrid_maxclip = ((1LL << (orig_bpp - 1)) - 1);
s->hybrid_minclip = ((-1LL << (orig_bpp - 1)));
s->CRC = bytestream2_get_le32(&gb);
// parse metadata blocks
while (bytestream2_get_bytes_left(&gb)) {
id = bytestream2_get_byte(&gb);
size = bytestream2_get_byte(&gb);
if (id & WP_IDF_LONG) {
size |= (bytestream2_get_byte(&gb)) << 8;
size |= (bytestream2_get_byte(&gb)) << 16;
}
size <<= 1; // size is specified in words
ssize = size;
if (id & WP_IDF_ODD)
size--;
if (size < 0) {
av_log(avctx, AV_LOG_ERROR,
"Got incorrect block %02X with size %i\n", id, size);
break;
}
if (bytestream2_get_bytes_left(&gb) < ssize) {
av_log(avctx, AV_LOG_ERROR,
"Block size %i is out of bounds\n", size);
break;
}
switch (id & WP_IDF_MASK) {
case WP_ID_DECTERMS:
if (size > MAX_TERMS) {
av_log(avctx, AV_LOG_ERROR, "Too many decorrelation terms\n");
s->terms = 0;
bytestream2_skip(&gb, ssize);
continue;
}
s->terms = size;
for (i = 0; i < s->terms; i++) {
uint8_t val = bytestream2_get_byte(&gb);
s->decorr[s->terms - i - 1].value = (val & 0x1F) - 5;
s->decorr[s->terms - i - 1].delta = val >> 5;
}
got_terms = 1;
break;
case WP_ID_DECWEIGHTS:
if (!got_terms) {
av_log(avctx, AV_LOG_ERROR, "No decorrelation terms met\n");
continue;
}
weights = size >> s->stereo_in;
if (weights > MAX_TERMS || weights > s->terms) {
av_log(avctx, AV_LOG_ERROR, "Too many decorrelation weights\n");
bytestream2_skip(&gb, ssize);
continue;
}
for (i = 0; i < weights; i++) {
t = (int8_t)bytestream2_get_byte(&gb);
s->decorr[s->terms - i - 1].weightA = t << 3;
if (s->decorr[s->terms - i - 1].weightA > 0)
s->decorr[s->terms - i - 1].weightA +=
(s->decorr[s->terms - i - 1].weightA + 64) >> 7;
if (s->stereo_in) {
t = (int8_t)bytestream2_get_byte(&gb);
s->decorr[s->terms - i - 1].weightB = t << 3;
if (s->decorr[s->terms - i - 1].weightB > 0)
s->decorr[s->terms - i - 1].weightB +=
(s->decorr[s->terms - i - 1].weightB + 64) >> 7;
}
}
got_weights = 1;
break;
case WP_ID_DECSAMPLES:
if (!got_terms) {
av_log(avctx, AV_LOG_ERROR, "No decorrelation terms met\n");
continue;
}
t = 0;
for (i = s->terms - 1; (i >= 0) && (t < size); i--) {
if (s->decorr[i].value > 8) {
s->decorr[i].samplesA[0] =
wp_exp2(bytestream2_get_le16(&gb));
s->decorr[i].samplesA[1] =
wp_exp2(bytestream2_get_le16(&gb));
if (s->stereo_in) {
s->decorr[i].samplesB[0] =
wp_exp2(bytestream2_get_le16(&gb));
s->decorr[i].samplesB[1] =
wp_exp2(bytestream2_get_le16(&gb));
t += 4;
}
t += 4;
} else if (s->decorr[i].value < 0) {
s->decorr[i].samplesA[0] =
wp_exp2(bytestream2_get_le16(&gb));
s->decorr[i].samplesB[0] =
wp_exp2(bytestream2_get_le16(&gb));
t += 4;
} else {
for (j = 0; j < s->decorr[i].value; j++) {
s->decorr[i].samplesA[j] =
wp_exp2(bytestream2_get_le16(&gb));
if (s->stereo_in) {
s->decorr[i].samplesB[j] =
wp_exp2(bytestream2_get_le16(&gb));
}
}
t += s->decorr[i].value * 2 * (s->stereo_in + 1);
}
}
got_samples = 1;
break;
case WP_ID_ENTROPY:
if (size != 6 * (s->stereo_in + 1)) {
av_log(avctx, AV_LOG_ERROR,
"Entropy vars size should be %i, got %i.\n",
6 * (s->stereo_in + 1), size);
bytestream2_skip(&gb, ssize);
continue;
}
for (j = 0; j <= s->stereo_in; j++)
for (i = 0; i < 3; i++) {
s->ch[j].median[i] = wp_exp2(bytestream2_get_le16(&gb));
}
got_entropy = 1;
break;
case WP_ID_HYBRID:
if (s->hybrid_bitrate) {
for (i = 0; i <= s->stereo_in; i++) {
s->ch[i].slow_level = wp_exp2(bytestream2_get_le16(&gb));
size -= 2;
}
}
for (i = 0; i < (s->stereo_in + 1); i++) {
s->ch[i].bitrate_acc = bytestream2_get_le16(&gb) << 16;
size -= 2;
}
if (size > 0) {
for (i = 0; i < (s->stereo_in + 1); i++) {
s->ch[i].bitrate_delta =
wp_exp2((int16_t)bytestream2_get_le16(&gb));
}
} else {
for (i = 0; i < (s->stereo_in + 1); i++)
s->ch[i].bitrate_delta = 0;
}
got_hybrid = 1;
break;
case WP_ID_INT32INFO: {
uint8_t val[4];
if (size != 4) {
av_log(avctx, AV_LOG_ERROR,
"Invalid INT32INFO, size = %i\n",
size);
bytestream2_skip(&gb, ssize - 4);
continue;
}
bytestream2_get_buffer(&gb, val, 4);
if (val[0] > 32) {
av_log(avctx, AV_LOG_ERROR,
"Invalid INT32INFO, extra_bits = %d (> 32)\n", val[0]);
continue;
} else if (val[0]) {
s->extra_bits = val[0];
} else if (val[1]) {
s->shift = val[1];
} else if (val[2]) {
s->and = s->or = 1;
s->shift = val[2];
} else if (val[3]) {
s->and = 1;
s->shift = val[3];
}
/* original WavPack decoder forces 32-bit lossy sound to be treated
* as 24-bit one in order to have proper clipping */
if (s->hybrid && bpp == 4 && s->post_shift < 8 && s->shift > 8) {
s->post_shift += 8;
s->shift -= 8;
s->hybrid_maxclip >>= 8;
s->hybrid_minclip >>= 8;
}
break;
}
case WP_ID_FLOATINFO:
if (size != 4) {
av_log(avctx, AV_LOG_ERROR,
"Invalid FLOATINFO, size = %i\n", size);
bytestream2_skip(&gb, ssize);
continue;
}
s->float_flag = bytestream2_get_byte(&gb);
s->float_shift = bytestream2_get_byte(&gb);
s->float_max_exp = bytestream2_get_byte(&gb);
got_float = 1;
bytestream2_skip(&gb, 1);
break;
case WP_ID_DATA:
s->sc.offset = bytestream2_tell(&gb);
s->sc.size = size * 8;
if ((ret = init_get_bits8(&s->gb, gb.buffer, size)) < 0)
return ret;
s->data_size = size * 8;
bytestream2_skip(&gb, size);
got_bs = 1;
break;
case WP_ID_EXTRABITS:
if (size <= 4) {
av_log(avctx, AV_LOG_ERROR, "Invalid EXTRABITS, size = %i\n",
size);
bytestream2_skip(&gb, size);
continue;
}
s->extra_sc.offset = bytestream2_tell(&gb);
s->extra_sc.size = size * 8;
if ((ret = init_get_bits8(&s->gb_extra_bits, gb.buffer, size)) < 0)
return ret;
s->crc_extra_bits = get_bits_long(&s->gb_extra_bits, 32);
bytestream2_skip(&gb, size);
s->got_extra_bits = 1;
break;
case WP_ID_CHANINFO:
if (size <= 1) {
av_log(avctx, AV_LOG_ERROR,
"Insufficient channel information\n");
return AVERROR_INVALIDDATA;
}
chan = bytestream2_get_byte(&gb);
switch (size - 2) {
case 0:
chmask = bytestream2_get_byte(&gb);
break;
case 1:
chmask = bytestream2_get_le16(&gb);
break;
case 2:
chmask = bytestream2_get_le24(&gb);
break;
case 3:
chmask = bytestream2_get_le32(&gb);
break;
case 5:
size = bytestream2_get_byte(&gb);
if (avctx->channels != size)
av_log(avctx, AV_LOG_WARNING, "%i channels signalled"
" instead of %i.\n", size, avctx->channels);
chan |= (bytestream2_get_byte(&gb) & 0xF) << 8;
chmask = bytestream2_get_le16(&gb);
break;
default:
av_log(avctx, AV_LOG_ERROR, "Invalid channel info size %d\n",
size);
chan = avctx->channels;
chmask = avctx->channel_layout;
}
break;
case WP_ID_SAMPLE_RATE:
if (size != 3) {
av_log(avctx, AV_LOG_ERROR, "Invalid custom sample rate.\n");
return AVERROR_INVALIDDATA;
}
sample_rate = bytestream2_get_le24(&gb);
break;
default:
bytestream2_skip(&gb, size);
}
if (id & WP_IDF_ODD)
bytestream2_skip(&gb, 1);
}
if (!got_terms) {
av_log(avctx, AV_LOG_ERROR, "No block with decorrelation terms\n");
return AVERROR_INVALIDDATA;
}
if (!got_weights) {
av_log(avctx, AV_LOG_ERROR, "No block with decorrelation weights\n");
return AVERROR_INVALIDDATA;
}
if (!got_samples) {
av_log(avctx, AV_LOG_ERROR, "No block with decorrelation samples\n");
return AVERROR_INVALIDDATA;
}
if (!got_entropy) {
av_log(avctx, AV_LOG_ERROR, "No block with entropy info\n");
return AVERROR_INVALIDDATA;
}
if (s->hybrid && !got_hybrid) {
av_log(avctx, AV_LOG_ERROR, "Hybrid config not found\n");
return AVERROR_INVALIDDATA;
}
if (!got_bs) {
av_log(avctx, AV_LOG_ERROR, "Packed samples not found\n");
return AVERROR_INVALIDDATA;
}
if (!got_float && avctx->sample_fmt == AV_SAMPLE_FMT_FLTP) {
av_log(avctx, AV_LOG_ERROR, "Float information not found\n");
return AVERROR_INVALIDDATA;
}
if (s->got_extra_bits && avctx->sample_fmt != AV_SAMPLE_FMT_FLTP) {
const int size = get_bits_left(&s->gb_extra_bits);
const int wanted = s->samples * s->extra_bits << s->stereo_in;
if (size < wanted) {
av_log(avctx, AV_LOG_ERROR, "Too small EXTRABITS\n");
s->got_extra_bits = 0;
}
}
if (!wc->ch_offset) {
int sr = (s->frame_flags >> 23) & 0xf;
if (sr == 0xf) {
if (!sample_rate) {
av_log(avctx, AV_LOG_ERROR, "Custom sample rate missing.\n");
return AVERROR_INVALIDDATA;
}
avctx->sample_rate = sample_rate;
} else
avctx->sample_rate = wv_rates[sr];
if (multiblock) {
if (chan)
avctx->channels = chan;
if (chmask)
avctx->channel_layout = chmask;
} else {
avctx->channels = s->stereo ? 2 : 1;
avctx->channel_layout = s->stereo ? AV_CH_LAYOUT_STEREO :
AV_CH_LAYOUT_MONO;
}
/* get output buffer */
frame->nb_samples = s->samples + 1;
if ((ret = ff_thread_get_buffer(avctx, &tframe, 0)) < 0)
return ret;
frame->nb_samples = s->samples;
}
if (wc->ch_offset + s->stereo >= avctx->channels) {
av_log(avctx, AV_LOG_WARNING, "Too many channels coded in a packet.\n");
return (avctx->err_recognition & AV_EF_EXPLODE) ? AVERROR_INVALIDDATA : 0;
}
samples_l = frame->extended_data[wc->ch_offset];
if (s->stereo)
samples_r = frame->extended_data[wc->ch_offset + 1];
wc->ch_offset += 1 + s->stereo;
if (s->stereo_in) {
ret = wv_unpack_stereo(s, &s->gb, samples_l, samples_r, avctx->sample_fmt);
if (ret < 0)
return ret;
} else {
ret = wv_unpack_mono(s, &s->gb, samples_l, avctx->sample_fmt);
if (ret < 0)
return ret;
if (s->stereo)
memcpy(samples_r, samples_l, bpp * s->samples);
}
return 0;
}
| true | FFmpeg | c188f358aaee5800af5a5d699dd657cef3fb43a6 |
9,112 | static int http_connect(URLContext *h, const char *path, const char *hoststr)
{
HTTPContext *s = h->priv_data;
int post, err, ch;
char line[1024], *q;
/* send http header */
post = h->flags & URL_WRONLY;
snprintf(s->buffer, sizeof(s->buffer),
"%s %s HTTP/1.0\r\n"
"User-Agent: %s\r\n"
"Accept: */*\r\n"
"Host: %s\r\n"
"\r\n",
post ? "POST" : "GET",
path,
LIBAVFORMAT_IDENT,
hoststr);
if (http_write(h, s->buffer, strlen(s->buffer)) < 0)
return AVERROR_IO;
/* init input buffer */
s->buf_ptr = s->buffer;
s->buf_end = s->buffer;
s->line_count = 0;
s->location[0] = '\0';
if (post) {
sleep(1);
return 0;
}
/* wait for header */
q = line;
for(;;) {
ch = http_getc(s);
if (ch < 0)
return AVERROR_IO;
if (ch == '\n') {
/* process line */
if (q > line && q[-1] == '\r')
q--;
*q = '\0';
#ifdef DEBUG
printf("header='%s'\n", line);
#endif
err = process_line(s, line, s->line_count);
if (err < 0)
return err;
if (err == 0)
return 0;
s->line_count++;
q = line;
} else {
if ((q - line) < sizeof(line) - 1)
*q++ = ch;
}
}
}
| false | FFmpeg | 6ba5cbc699e77cae66bb719354fa142114b64eab |
9,113 | static void decodeplane8(uint8_t *dst, const uint8_t *const buf, int buf_size, int bps, int plane)
{
GetBitContext gb;
int i, b;
init_get_bits(&gb, buf, buf_size * 8);
for(i = 0; i < (buf_size * 8 + bps - 1) / bps; i++) {
for (b = 0; b < bps; b++) {
dst[ i*bps + b ] |= get_bits1(&gb) << plane;
}
}
}
| false | FFmpeg | 473147bed01c0c6c82d85fd79d3e1c1d65542663 |
9,114 | static void mpeg_decode_sequence_extension(MpegEncContext *s)
{
int horiz_size_ext, vert_size_ext;
int bit_rate_ext;
int level, profile;
skip_bits(&s->gb, 1); /* profil and level esc*/
profile= get_bits(&s->gb, 3);
level= get_bits(&s->gb, 4);
s->progressive_sequence = get_bits1(&s->gb); /* progressive_sequence */
s->chroma_format = get_bits(&s->gb, 2); /* chroma_format 1=420, 2=422, 3=444 */
horiz_size_ext = get_bits(&s->gb, 2);
vert_size_ext = get_bits(&s->gb, 2);
s->width |= (horiz_size_ext << 12);
s->height |= (vert_size_ext << 12);
bit_rate_ext = get_bits(&s->gb, 12); /* XXX: handle it */
s->bit_rate += (bit_rate_ext << 12) * 400;
skip_bits1(&s->gb); /* marker */
s->avctx->rc_buffer_size += get_bits(&s->gb, 8)*1024*16<<10;
s->low_delay = get_bits1(&s->gb);
if(s->flags & CODEC_FLAG_LOW_DELAY) s->low_delay=1;
s->frame_rate_ext_n = get_bits(&s->gb, 2);
s->frame_rate_ext_d = get_bits(&s->gb, 5);
dprintf("sequence extension\n");
s->codec_id= s->avctx->codec_id= CODEC_ID_MPEG2VIDEO;
s->avctx->sub_id = 2; /* indicates mpeg2 found */
if(s->avctx->debug & FF_DEBUG_PICT_INFO)
av_log(s->avctx, AV_LOG_DEBUG, "profile: %d, level: %d vbv buffer: %d, bitrate:%d\n",
profile, level, s->avctx->rc_buffer_size, s->bit_rate);
}
| false | FFmpeg | baced9f5986a466c957456f5cf32a722d8b35512 |
9,115 | static int init(AVFilterContext *ctx, const char *args)
{
EvalContext *eval = ctx->priv;
char *args1 = av_strdup(eval->exprs);
char *expr, *buf;
int ret, i;
if (!args1) {
av_log(ctx, AV_LOG_ERROR, "Channels expressions list is empty\n");
ret = args ? AVERROR(ENOMEM) : AVERROR(EINVAL);
goto end;
}
/* parse expressions */
buf = args1;
i = 0;
while (i < FF_ARRAY_ELEMS(eval->expr) && (expr = av_strtok(buf, "|", &buf))) {
ret = av_expr_parse(&eval->expr[i], expr, var_names,
NULL, NULL, NULL, NULL, 0, ctx);
if (ret < 0)
goto end;
i++;
}
eval->nb_channels = i;
if (eval->chlayout_str) {
int n;
ret = ff_parse_channel_layout(&eval->chlayout, eval->chlayout_str, ctx);
if (ret < 0)
goto end;
n = av_get_channel_layout_nb_channels(eval->chlayout);
if (n != eval->nb_channels) {
av_log(ctx, AV_LOG_ERROR,
"Mismatch between the specified number of channels '%d' "
"and the number of channels '%d' in the specified channel layout '%s'\n",
eval->nb_channels, n, eval->chlayout_str);
ret = AVERROR(EINVAL);
goto end;
}
} else {
/* guess channel layout from nb expressions/channels */
eval->chlayout = av_get_default_channel_layout(eval->nb_channels);
if (!eval->chlayout) {
av_log(ctx, AV_LOG_ERROR, "Invalid number of channels '%d' provided\n",
eval->nb_channels);
ret = AVERROR(EINVAL);
goto end;
}
}
if ((ret = ff_parse_sample_rate(&eval->sample_rate, eval->sample_rate_str, ctx)))
goto end;
eval->duration = -1;
if (eval->duration_str) {
int64_t us = -1;
if ((ret = av_parse_time(&us, eval->duration_str, 1)) < 0) {
av_log(ctx, AV_LOG_ERROR, "Invalid duration: '%s'\n", eval->duration_str);
goto end;
}
eval->duration = (double)us / 1000000;
}
eval->n = 0;
end:
av_free(args1);
return ret;
}
| false | FFmpeg | 491d261adecec619a3c7b92249133fb3ef0f5044 |
9,116 | static void vc1_loop_filter_iblk(MpegEncContext *s, int pq)
{
int i, j;
if(!s->first_slice_line)
s->dsp.vc1_loop_filter(s->dest[0], 1, s->linesize, 16, pq);
s->dsp.vc1_loop_filter(s->dest[0] + 8*s->linesize, 1, s->linesize, 16, pq);
for(i = !s->mb_x*8; i < 16; i += 8)
s->dsp.vc1_loop_filter(s->dest[0] + i, s->linesize, 1, 16, pq);
for(j = 0; j < 2; j++){
if(!s->first_slice_line)
s->dsp.vc1_loop_filter(s->dest[j+1], 1, s->uvlinesize, 8, pq);
if(s->mb_x)
s->dsp.vc1_loop_filter(s->dest[j+1], s->uvlinesize, 1, 8, pq);
}
}
| false | FFmpeg | 3992526b3c43278945d00fac6e2ba5cb8f810ef3 |
9,117 | static int dnxhd_decode_dct_block_10(const DNXHDContext *ctx,
RowContext *row, int n)
{
return dnxhd_decode_dct_block(ctx, row, n, 6, 8, 4);
}
| false | FFmpeg | 6f1ccca4ae3b93b6a2a820a7a0e72081ab35767c |
9,118 | static inline void RENAME(hScale)(int16_t *dst, int dstW, const uint8_t *src, int srcW, int xInc,
const int16_t *filter, const int16_t *filterPos, long filterSize)
{
#if COMPILE_TEMPLATE_MMX
assert(filterSize % 4 == 0 && filterSize>0);
if (filterSize==4) { // Always true for upscaling, sometimes for down, too.
x86_reg counter= -2*dstW;
filter-= counter*2;
filterPos-= counter/2;
dst-= counter/2;
__asm__ volatile(
#if defined(PIC)
"push %%"REG_b" \n\t"
#endif
"pxor %%mm7, %%mm7 \n\t"
"push %%"REG_BP" \n\t" // we use 7 regs here ...
"mov %%"REG_a", %%"REG_BP" \n\t"
".p2align 4 \n\t"
"1: \n\t"
"movzwl (%2, %%"REG_BP"), %%eax \n\t"
"movzwl 2(%2, %%"REG_BP"), %%ebx \n\t"
"movq (%1, %%"REG_BP", 4), %%mm1 \n\t"
"movq 8(%1, %%"REG_BP", 4), %%mm3 \n\t"
"movd (%3, %%"REG_a"), %%mm0 \n\t"
"movd (%3, %%"REG_b"), %%mm2 \n\t"
"punpcklbw %%mm7, %%mm0 \n\t"
"punpcklbw %%mm7, %%mm2 \n\t"
"pmaddwd %%mm1, %%mm0 \n\t"
"pmaddwd %%mm2, %%mm3 \n\t"
"movq %%mm0, %%mm4 \n\t"
"punpckldq %%mm3, %%mm0 \n\t"
"punpckhdq %%mm3, %%mm4 \n\t"
"paddd %%mm4, %%mm0 \n\t"
"psrad $7, %%mm0 \n\t"
"packssdw %%mm0, %%mm0 \n\t"
"movd %%mm0, (%4, %%"REG_BP") \n\t"
"add $4, %%"REG_BP" \n\t"
" jnc 1b \n\t"
"pop %%"REG_BP" \n\t"
#if defined(PIC)
"pop %%"REG_b" \n\t"
#endif
: "+a" (counter)
: "c" (filter), "d" (filterPos), "S" (src), "D" (dst)
#if !defined(PIC)
: "%"REG_b
#endif
);
} else if (filterSize==8) {
x86_reg counter= -2*dstW;
filter-= counter*4;
filterPos-= counter/2;
dst-= counter/2;
__asm__ volatile(
#if defined(PIC)
"push %%"REG_b" \n\t"
#endif
"pxor %%mm7, %%mm7 \n\t"
"push %%"REG_BP" \n\t" // we use 7 regs here ...
"mov %%"REG_a", %%"REG_BP" \n\t"
".p2align 4 \n\t"
"1: \n\t"
"movzwl (%2, %%"REG_BP"), %%eax \n\t"
"movzwl 2(%2, %%"REG_BP"), %%ebx \n\t"
"movq (%1, %%"REG_BP", 8), %%mm1 \n\t"
"movq 16(%1, %%"REG_BP", 8), %%mm3 \n\t"
"movd (%3, %%"REG_a"), %%mm0 \n\t"
"movd (%3, %%"REG_b"), %%mm2 \n\t"
"punpcklbw %%mm7, %%mm0 \n\t"
"punpcklbw %%mm7, %%mm2 \n\t"
"pmaddwd %%mm1, %%mm0 \n\t"
"pmaddwd %%mm2, %%mm3 \n\t"
"movq 8(%1, %%"REG_BP", 8), %%mm1 \n\t"
"movq 24(%1, %%"REG_BP", 8), %%mm5 \n\t"
"movd 4(%3, %%"REG_a"), %%mm4 \n\t"
"movd 4(%3, %%"REG_b"), %%mm2 \n\t"
"punpcklbw %%mm7, %%mm4 \n\t"
"punpcklbw %%mm7, %%mm2 \n\t"
"pmaddwd %%mm1, %%mm4 \n\t"
"pmaddwd %%mm2, %%mm5 \n\t"
"paddd %%mm4, %%mm0 \n\t"
"paddd %%mm5, %%mm3 \n\t"
"movq %%mm0, %%mm4 \n\t"
"punpckldq %%mm3, %%mm0 \n\t"
"punpckhdq %%mm3, %%mm4 \n\t"
"paddd %%mm4, %%mm0 \n\t"
"psrad $7, %%mm0 \n\t"
"packssdw %%mm0, %%mm0 \n\t"
"movd %%mm0, (%4, %%"REG_BP") \n\t"
"add $4, %%"REG_BP" \n\t"
" jnc 1b \n\t"
"pop %%"REG_BP" \n\t"
#if defined(PIC)
"pop %%"REG_b" \n\t"
#endif
: "+a" (counter)
: "c" (filter), "d" (filterPos), "S" (src), "D" (dst)
#if !defined(PIC)
: "%"REG_b
#endif
);
} else {
const uint8_t *offset = src+filterSize;
x86_reg counter= -2*dstW;
//filter-= counter*filterSize/2;
filterPos-= counter/2;
dst-= counter/2;
__asm__ volatile(
"pxor %%mm7, %%mm7 \n\t"
".p2align 4 \n\t"
"1: \n\t"
"mov %2, %%"REG_c" \n\t"
"movzwl (%%"REG_c", %0), %%eax \n\t"
"movzwl 2(%%"REG_c", %0), %%edx \n\t"
"mov %5, %%"REG_c" \n\t"
"pxor %%mm4, %%mm4 \n\t"
"pxor %%mm5, %%mm5 \n\t"
"2: \n\t"
"movq (%1), %%mm1 \n\t"
"movq (%1, %6), %%mm3 \n\t"
"movd (%%"REG_c", %%"REG_a"), %%mm0 \n\t"
"movd (%%"REG_c", %%"REG_d"), %%mm2 \n\t"
"punpcklbw %%mm7, %%mm0 \n\t"
"punpcklbw %%mm7, %%mm2 \n\t"
"pmaddwd %%mm1, %%mm0 \n\t"
"pmaddwd %%mm2, %%mm3 \n\t"
"paddd %%mm3, %%mm5 \n\t"
"paddd %%mm0, %%mm4 \n\t"
"add $8, %1 \n\t"
"add $4, %%"REG_c" \n\t"
"cmp %4, %%"REG_c" \n\t"
" jb 2b \n\t"
"add %6, %1 \n\t"
"movq %%mm4, %%mm0 \n\t"
"punpckldq %%mm5, %%mm4 \n\t"
"punpckhdq %%mm5, %%mm0 \n\t"
"paddd %%mm0, %%mm4 \n\t"
"psrad $7, %%mm4 \n\t"
"packssdw %%mm4, %%mm4 \n\t"
"mov %3, %%"REG_a" \n\t"
"movd %%mm4, (%%"REG_a", %0) \n\t"
"add $4, %0 \n\t"
" jnc 1b \n\t"
: "+r" (counter), "+r" (filter)
: "m" (filterPos), "m" (dst), "m"(offset),
"m" (src), "r" ((x86_reg)filterSize*2)
: "%"REG_a, "%"REG_c, "%"REG_d
);
}
#else
#if COMPILE_TEMPLATE_ALTIVEC
hScale_altivec_real(dst, dstW, src, srcW, xInc, filter, filterPos, filterSize);
#else
int i;
for (i=0; i<dstW; i++) {
int j;
int srcPos= filterPos[i];
int val=0;
//printf("filterPos: %d\n", filterPos[i]);
for (j=0; j<filterSize; j++) {
//printf("filter: %d, src: %d\n", filter[i], src[srcPos + j]);
val += ((int)src[srcPos + j])*filter[filterSize*i + j];
}
//filter += hFilterSize;
dst[i] = FFMIN(val>>7, (1<<15)-1); // the cubic equation does overflow ...
//dst[i] = val>>7;
}
#endif /* COMPILE_TEMPLATE_ALTIVEC */
#endif /* COMPILE_MMX */
}
| false | FFmpeg | d1adad3cca407f493c3637e20ecd4f7124e69212 |
9,119 | static void draw_curves(AVFilterContext *ctx, AVFilterLink *inlink, AVFrame *out)
{
AudioNEqualizerContext *s = ctx->priv;
char *colors, *color, *saveptr = NULL;
int ch, i, n;
colors = av_strdup(s->colors);
if (!colors)
return;
memset(out->data[0], 0, s->h * out->linesize[0]);
for (ch = 0; ch < inlink->channels; ch++) {
uint8_t fg[4] = { 0xff, 0xff, 0xff, 0xff };
int prev_v = -1;
double f;
color = av_strtok(ch == 0 ? colors : NULL, " |", &saveptr);
if (color)
av_parse_color(fg, color, -1, ctx);
for (f = 0; f < s->w; f++) {
double complex z;
double complex H = 1;
double w;
int v, y, x;
w = M_PI * (s->fscale ? pow(s->w - 1, f / s->w) : f) / (s->w - 1);
z = 1. / cexp(I * w);
for (n = 0; n < s->nb_filters; n++) {
if (s->filters[n].channel != ch ||
s->filters[n].ignore)
continue;
for (i = 0; i < FILTER_ORDER / 2; i++) {
FoSection *S = &s->filters[n].section[i];
H *= (((((S->b4 * z + S->b3) * z + S->b2) * z + S->b1) * z + S->b0) /
((((S->a4 * z + S->a3) * z + S->a2) * z + S->a1) * z + S->a0));
}
}
v = av_clip((1. + -20 * log10(cabs(H)) / s->mag) * s->h / 2, 0, s->h - 1);
x = lrint(f);
if (prev_v == -1)
prev_v = v;
if (v <= prev_v) {
for (y = v; y <= prev_v; y++)
AV_WL32(out->data[0] + y * out->linesize[0] + x * 4, AV_RL32(fg));
} else {
for (y = prev_v; y <= v; y++)
AV_WL32(out->data[0] + y * out->linesize[0] + x * 4, AV_RL32(fg));
}
prev_v = v;
}
}
av_free(colors);
}
| false | FFmpeg | 63702014fa4e4bb812fa984ca748f3178bd1174f |
9,120 | static void set_sar(TiffContext *s, unsigned tag, unsigned num, unsigned den)
{
int offset = tag == TIFF_YRES ? 2 : 0;
s->res[offset++] = num;
s->res[offset] = den;
if (s->res[0] && s->res[1] && s->res[2] && s->res[3])
av_reduce(&s->avctx->sample_aspect_ratio.num, &s->avctx->sample_aspect_ratio.den,
s->res[2] * (uint64_t)s->res[1], s->res[0] * (uint64_t)s->res[3], INT32_MAX);
}
| true | FFmpeg | ed412d285078c167a3a5326bcb16b2169b488943 |
9,121 | CPUX86State *cpu_x86_init(const char *cpu_model)
{
X86CPU *cpu;
CPUX86State *env;
static int inited;
cpu = X86_CPU(object_new(TYPE_X86_CPU));
env = &cpu->env;
env->cpu_model_str = cpu_model;
/* init various static tables used in TCG mode */
if (tcg_enabled() && !inited) {
inited = 1;
optimize_flags_init();
#ifndef CONFIG_USER_ONLY
prev_debug_excp_handler =
cpu_set_debug_excp_handler(breakpoint_handler);
#endif
}
if (cpu_x86_register(cpu, cpu_model) < 0) {
object_delete(OBJECT(cpu));
return NULL;
}
qemu_init_vcpu(env);
return env;
}
| true | qemu | 7a05995361a7b4376dffb3c7f04a95644251d29f |
9,123 | static int glyph_enu_free(void *opaque, void *elem)
{
av_free(elem);
return 0;
} | true | FFmpeg | 423047ea3167db5dc7d7b69165e1930710adb878 |
9,124 | static void encode_scale_factors(AVCodecContext *avctx, AACEncContext *s,
SingleChannelElement *sce)
{
int off = sce->sf_idx[0], diff;
int i, w;
for (w = 0; w < sce->ics.num_windows; w += sce->ics.group_len[w]) {
for (i = 0; i < sce->ics.max_sfb; i++) {
if (!sce->zeroes[w*16 + i]) {
diff = sce->sf_idx[w*16 + i] - off + SCALE_DIFF_ZERO;
if (diff < 0 || diff > 120)
av_log(avctx, AV_LOG_ERROR, "Scalefactor difference is too big to be coded\n");
off = sce->sf_idx[w*16 + i];
put_bits(&s->pb, ff_aac_scalefactor_bits[diff], ff_aac_scalefactor_code[diff]);
}
}
}
}
| true | FFmpeg | f69f9b387624bb5e3749e74c180bd092e0dcd20c |
9,125 | static void mpegts_close_filter(MpegTSContext *ts, MpegTSFilter *filter)
{
int pid;
pid = filter->pid;
if (filter->type == MPEGTS_SECTION)
av_freep(&filter->u.section_filter.section_buf);
av_free(filter);
ts->pids[pid] = NULL;
| true | FFmpeg | dcd913d9ed6c15ea53882894baa343695575abcd |
9,126 | static void blk_mig_reset_dirty_cursor(void)
{
BlkMigDevState *bmds;
QSIMPLEQ_FOREACH(bmds, &block_mig_state.bmds_list, entry) {
bmds->cur_dirty = 0;
}
}
| true | qemu | 60fe637bf0e4d7989e21e50f52526444765c63b4 |
9,127 | void ppc_tlb_invalidate_all (CPUPPCState *env)
{
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
ppc6xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_REAL_4xx:
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
case POWERPC_MMU_BOOKE_FSL:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
case POWERPC_MMU_601:
/* XXX: TODO */
cpu_abort(env, "MMU model not implemented\n");
break;
case POWERPC_MMU_32B:
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
case POWERPC_MMU_64BRIDGE:
#endif /* defined(TARGET_PPC64) */
tlb_flush(env, 1);
break;
default:
/* XXX: TODO */
cpu_abort(env, "Unknown MMU model %d\n", env->mmu_model);
break;
}
}
| true | qemu | 12de9a396acbc95e25c5d60ed097cc55777eaaed |
9,128 | static int ffm_is_avail_data(AVFormatContext *s, int size)
{
FFMContext *ffm = s->priv_data;
int64_t pos, avail_size;
int len;
len = ffm->packet_end - ffm->packet_ptr;
if (size <= len)
return 1;
pos = url_ftell(s->pb);
if (!ffm->write_index) {
if (pos == ffm->file_size);
return AVERROR_EOF;
avail_size = ffm->file_size - pos;
} else {
if (pos == ffm->write_index) {
/* exactly at the end of stream */
return AVERROR(EAGAIN);
} else if (pos < ffm->write_index) {
avail_size = ffm->write_index - pos;
} else {
avail_size = (ffm->file_size - pos) + (ffm->write_index - FFM_PACKET_SIZE);
}
}
avail_size = (avail_size / ffm->packet_size) * (ffm->packet_size - FFM_HEADER_SIZE) + len;
if (size <= avail_size)
return 1;
else
return AVERROR(EAGAIN);
}
| false | FFmpeg | 21c6438f2c353b4e0a5bb16bb5861fb8a799e121 |
9,129 | static int mov_read_stsc(MOVContext *c, ByteIOContext *pb, MOVAtom atom)
{
AVStream *st = c->fc->streams[c->fc->nb_streams-1];
MOVStreamContext *sc = st->priv_data;
unsigned int i, entries;
get_byte(pb); /* version */
get_be24(pb); /* flags */
entries = get_be32(pb);
dprintf(c->fc, "track[%i].stsc.entries = %i\n", c->fc->nb_streams-1, entries);
if(entries >= UINT_MAX / sizeof(*sc->stsc_data))
return -1;
sc->stsc_data = av_malloc(entries * sizeof(*sc->stsc_data));
if (!sc->stsc_data)
return AVERROR(ENOMEM);
sc->stsc_count = entries;
for(i=0; i<entries; i++) {
sc->stsc_data[i].first = get_be32(pb);
sc->stsc_data[i].count = get_be32(pb);
sc->stsc_data[i].id = get_be32(pb);
}
return 0;
}
| false | FFmpeg | 6a63ff19b6a7fe3bc32c7fb4a62fca8f65786432 |
9,131 | static int siff_read_packet(AVFormatContext *s, AVPacket *pkt)
{
SIFFContext *c = s->priv_data;
if (c->has_video) {
unsigned int size;
if (c->cur_frame >= c->frames)
return AVERROR_EOF;
if (c->curstrm == -1) {
c->pktsize = avio_rl32(s->pb) - 4;
c->flags = avio_rl16(s->pb);
c->gmcsize = (c->flags & VB_HAS_GMC) ? 4 : 0;
if (c->gmcsize)
avio_read(s->pb, c->gmc, c->gmcsize);
c->sndsize = (c->flags & VB_HAS_AUDIO) ? avio_rl32(s->pb) : 0;
c->curstrm = !!(c->flags & VB_HAS_AUDIO);
}
if (!c->curstrm) {
size = c->pktsize - c->sndsize - c->gmcsize - 2;
size = ffio_limit(s->pb, size);
if (size < 0 || c->pktsize < c->sndsize)
return AVERROR_INVALIDDATA;
if (av_new_packet(pkt, size + c->gmcsize + 2) < 0)
return AVERROR(ENOMEM);
AV_WL16(pkt->data, c->flags);
if (c->gmcsize)
memcpy(pkt->data + 2, c->gmc, c->gmcsize);
if (avio_read(s->pb, pkt->data + 2 + c->gmcsize, size) != size) {
av_free_packet(pkt);
return AVERROR_INVALIDDATA;
}
pkt->stream_index = 0;
c->curstrm = -1;
} else {
int pktsize = av_get_packet(s->pb, pkt, c->sndsize - 4);
if (pktsize < 0)
return AVERROR(EIO);
pkt->stream_index = 1;
pkt->duration = pktsize;
c->curstrm = 0;
}
if (!c->cur_frame || c->curstrm)
pkt->flags |= AV_PKT_FLAG_KEY;
if (c->curstrm == -1)
c->cur_frame++;
} else {
int pktsize = av_get_packet(s->pb, pkt, c->block_align);
if (!pktsize)
return AVERROR_EOF;
if (pktsize <= 0)
return AVERROR(EIO);
pkt->duration = pktsize;
}
return pkt->size;
}
| false | FFmpeg | e71dce5769b2282824da7cfd6f7e4ce0d1985876 |
9,132 | static int packed_vscale(SwsContext *c, SwsFilterDescriptor *desc, int sliceY, int sliceH)
{
VScalerContext *inst = desc->instance;
int dstW = desc->dst->width;
int chrSliceY = sliceY >> desc->dst->v_chr_sub_sample;
int lum_fsize = inst[0].filter_size;
int chr_fsize = inst[1].filter_size;
uint16_t *lum_filter = inst[0].filter[0];
uint16_t *chr_filter = inst[1].filter[0];
int firstLum = FFMAX(1-lum_fsize, inst[0].filter_pos[chrSliceY]);
int firstChr = FFMAX(1-chr_fsize, inst[1].filter_pos[chrSliceY]);
int sp0 = firstLum - desc->src->plane[0].sliceY;
int sp1 = firstChr - desc->src->plane[1].sliceY;
int sp2 = firstChr - desc->src->plane[2].sliceY;
int sp3 = firstLum - desc->src->plane[3].sliceY;
int dp = sliceY - desc->dst->plane[0].sliceY;
uint8_t **src0 = desc->src->plane[0].line + sp0;
uint8_t **src1 = desc->src->plane[1].line + sp1;
uint8_t **src2 = desc->src->plane[2].line + sp2;
uint8_t **src3 = desc->alpha ? desc->src->plane[3].line + sp3 : NULL;
uint8_t **dst = desc->dst->plane[0].line + dp;
if (c->yuv2packed1 && lum_fsize == 1 && chr_fsize <= 2) { // unscaled RGB
int chrAlpha = chr_fsize == 1 ? 0 : chr_filter[2 * sliceY + 1];
((yuv2packed1_fn)inst->pfn)(c, (const int16_t*)*src0, (const int16_t**)src1, (const int16_t**)src2, (const int16_t*)(desc->alpha ? *src3 : NULL), *dst, dstW, chrAlpha, sliceY);
} else if (c->yuv2packed2 && lum_fsize == 2 && chr_fsize == 2) { // bilinear upscale RGB
int lumAlpha = lum_filter[2 * sliceY + 1];
int chrAlpha = chr_filter[2 * sliceY + 1];
c->lumMmxFilter[2] =
c->lumMmxFilter[3] = lum_filter[2 * sliceY] * 0x10001;
c->chrMmxFilter[2] =
c->chrMmxFilter[3] = chr_filter[2 * chrSliceY] * 0x10001;
((yuv2packed2_fn)inst->pfn)(c, (const int16_t**)src0, (const int16_t**)src1, (const int16_t**)src2, (const int16_t**)src3,
*dst, dstW, lumAlpha, chrAlpha, sliceY);
} else { // general RGB
((yuv2packedX_fn)inst->pfn)(c, lum_filter + sliceY * lum_fsize,
(const int16_t**)src0, lum_fsize, chr_filter + sliceY * chr_fsize,
(const int16_t**)src1, (const int16_t**)src2, chr_fsize, (const int16_t**)src3, *dst, dstW, sliceY);
}
return 1;
}
| false | FFmpeg | eb7802afefb7af4da50bc56818cdab9da07de7d0 |
9,133 | WINDOW_FUNC(eight_short)
{
const float *swindow = sce->ics.use_kb_window[0] ? ff_aac_kbd_short_128 : ff_sine_128;
const float *pwindow = sce->ics.use_kb_window[1] ? ff_aac_kbd_short_128 : ff_sine_128;
const float *in = audio + 448;
float *out = sce->ret;
for (int w = 0; w < 8; w++) {
dsp->vector_fmul (out, in, w ? pwindow : swindow, 128);
out += 128;
in += 128;
dsp->vector_fmul_reverse(out, in, swindow, 128);
out += 128;
}
}
| false | FFmpeg | 3715d841a619f1cbc4776d9b00575dae6fb6534a |
9,135 | static int udp_read_packet(AVFormatContext *s,
AVPacket *pkt)
{
AVFormatContext *ic;
AVStream *st;
RTSPStream *rtsp_st;
fd_set rfds;
int fd1, fd2, fd_max, n, i, ret;
char buf[RTP_MAX_PACKET_LENGTH];
struct timeval tv;
for(;;) {
if (rtsp_abort_req)
return -EIO;
FD_ZERO(&rfds);
fd_max = -1;
for(i = 0; i < s->nb_streams; i++) {
st = s->streams[i];
rtsp_st = st->priv_data;
ic = rtsp_st->ic;
/* currently, we cannot probe RTCP handle because of blocking restrictions */
rtp_get_file_handles(url_fileno(&ic->pb), &fd1, &fd2);
if (fd1 > fd_max)
fd_max = fd1;
FD_SET(fd1, &rfds);
}
/* XXX: also add proper API to abort */
tv.tv_sec = 0;
tv.tv_usec = 500000;
n = select(fd_max + 1, &rfds, NULL, NULL, &tv);
if (n > 0) {
for(i = 0; i < s->nb_streams; i++) {
st = s->streams[i];
rtsp_st = st->priv_data;
ic = rtsp_st->ic;
rtp_get_file_handles(url_fileno(&ic->pb), &fd1, &fd2);
if (FD_ISSET(fd1, &rfds)) {
ret = url_read(url_fileno(&ic->pb), buf, sizeof(buf));
if (ret >= 0 &&
rtp_parse_packet(ic, pkt, buf, ret) == 0) {
pkt->stream_index = i;
return ret;
}
}
}
}
}
}
| false | FFmpeg | b7b8fc340632d15cb3b26a57915ebea84f37d03e |
9,136 | static void apply_unsharp( uint8_t *dst, int dst_stride,
const uint8_t *src, int src_stride,
int width, int height, FilterParam *fp)
{
uint32_t **sc = fp->sc;
uint32_t sr[MAX_MATRIX_SIZE - 1], tmp1, tmp2;
int32_t res;
int x, y, z;
const uint8_t *src2 = NULL; //silence a warning
if (!fp->amount) {
if (dst_stride == src_stride)
memcpy(dst, src, src_stride * height);
else
for (y = 0; y < height; y++, dst += dst_stride, src += src_stride)
memcpy(dst, src, width);
return;
}
for (y = 0; y < 2 * fp->steps_y; y++)
memset(sc[y], 0, sizeof(sc[y][0]) * (width + 2 * fp->steps_x));
for (y = -fp->steps_y; y < height + fp->steps_y; y++) {
if (y < height)
src2 = src;
memset(sr, 0, sizeof(sr[0]) * (2 * fp->steps_x - 1));
for (x = -fp->steps_x; x < width + fp->steps_x; x++) {
tmp1 = x <= 0 ? src2[0] : x >= width ? src2[width-1] : src2[x];
for (z = 0; z < fp->steps_x * 2; z += 2) {
tmp2 = sr[z + 0] + tmp1; sr[z + 0] = tmp1;
tmp1 = sr[z + 1] + tmp2; sr[z + 1] = tmp2;
}
for (z = 0; z < fp->steps_y * 2; z += 2) {
tmp2 = sc[z + 0][x + fp->steps_x] + tmp1; sc[z + 0][x + fp->steps_x] = tmp1;
tmp1 = sc[z + 1][x + fp->steps_x] + tmp2; sc[z + 1][x + fp->steps_x] = tmp2;
}
if (x >= fp->steps_x && y >= fp->steps_y) {
const uint8_t *srx = src - fp->steps_y * src_stride + x - fp->steps_x;
uint8_t *dsx = dst - fp->steps_y * dst_stride + x - fp->steps_x;
res = (int32_t)*srx + ((((int32_t) * srx - (int32_t)((tmp1 + fp->halfscale) >> fp->scalebits)) * fp->amount) >> 16);
*dsx = av_clip_uint8(res);
}
}
if (y >= 0) {
dst += dst_stride;
src += src_stride;
}
}
}
| false | FFmpeg | d2cadea3f0856bb6d278f24cb657ad4b877ba081 |
9,137 | static off_t read_uint32(BlockDriverState *bs, int64_t offset)
{
uint32_t buffer;
if (bdrv_pread(bs->file, offset, &buffer, 4) < 4)
return 0;
return be32_to_cpu(buffer);
}
| true | qemu | 69d34a360dfe773e17e72c76d15931c9b9d190f6 |
9,138 | static void gen_tlbre_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
#else
if (unlikely(ctx->pr)) {
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
return;
}
switch (rB(ctx->opcode)) {
case 0:
gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
cpu_gpr[rA(ctx->opcode)]);
break;
case 1:
gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
cpu_gpr[rA(ctx->opcode)]);
break;
default:
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
break;
}
#endif
}
| true | qemu | 9b2fadda3e0196ffd485adde4fe9cdd6fae35300 |
9,139 | int aio_bh_poll(AioContext *ctx)
{
QEMUBH *bh, **bhp, *next;
int ret;
ctx->walking_bh++;
ret = 0;
for (bh = ctx->first_bh; bh; bh = next) {
/* Make sure that fetching bh happens before accessing its members */
smp_read_barrier_depends();
next = bh->next;
/* The atomic_xchg is paired with the one in qemu_bh_schedule. The
* implicit memory barrier ensures that the callback sees all writes
* done by the scheduling thread. It also ensures that the scheduling
* thread sees the zero before bh->cb has run, and thus will call
* aio_notify again if necessary.
*/
if (!bh->deleted && atomic_xchg(&bh->scheduled, 0)) {
if (!bh->idle)
ret = 1;
bh->idle = 0;
bh->cb(bh->opaque);
}
}
ctx->walking_bh--;
/* remove deleted bhs */
if (!ctx->walking_bh) {
qemu_mutex_lock(&ctx->bh_lock);
bhp = &ctx->first_bh;
while (*bhp) {
bh = *bhp;
if (bh->deleted) {
*bhp = bh->next;
g_free(bh);
} else {
bhp = &bh->next;
}
}
qemu_mutex_unlock(&ctx->bh_lock);
}
return ret;
}
| true | qemu | ca96ac44dcd290566090b2435bc828fded356ad9 |
9,140 | static void libschroedinger_handle_first_access_unit(AVCodecContext *avctx)
{
SchroDecoderParams *p_schro_params = avctx->priv_data;
SchroDecoder *decoder = p_schro_params->decoder;
p_schro_params->format = schro_decoder_get_video_format(decoder);
/* Tell FFmpeg about sequence details. */
if (av_image_check_size(p_schro_params->format->width,
p_schro_params->format->height, 0, avctx) < 0) {
av_log(avctx, AV_LOG_ERROR, "invalid dimensions (%dx%d)\n",
p_schro_params->format->width, p_schro_params->format->height);
avctx->height = avctx->width = 0;
return;
}
avctx->height = p_schro_params->format->height;
avctx->width = p_schro_params->format->width;
avctx->pix_fmt = get_chroma_format(p_schro_params->format->chroma_format);
if (ff_get_schro_frame_format(p_schro_params->format->chroma_format,
&p_schro_params->frame_format) == -1) {
av_log(avctx, AV_LOG_ERROR,
"This codec currently only supports planar YUV 4:2:0, 4:2:2 "
"and 4:4:4 formats.\n");
return;
}
avctx->framerate.num = p_schro_params->format->frame_rate_numerator;
avctx->framerate.den = p_schro_params->format->frame_rate_denominator;
}
| true | FFmpeg | 220b24c7c97dc033ceab1510549f66d0e7b52ef1 |
9,141 | static av_cold int atrac1_decode_end(AVCodecContext * avctx) {
AT1Ctx *q = avctx->priv_data;
av_freep(&q->out_samples[0]);
ff_mdct_end(&q->mdct_ctx[0]);
ff_mdct_end(&q->mdct_ctx[1]);
ff_mdct_end(&q->mdct_ctx[2]);
return 0;
}
| true | FFmpeg | 6dc7dd7af45aa1e341b471fd054f85ae2747775b |
9,143 | static double block_angle(int x, int y, int cx, int cy, MotionVector *shift)
{
double a1, a2, diff;
a1 = atan2(y - cy, x - cx);
a2 = atan2(y - cy + shift->y, x - cx + shift->x);
diff = a2 - a1;
return (diff > M_PI) ? diff - 2 * M_PI :
(diff < -M_PI) ? diff + 2 * M_PI :
diff;
}
| true | FFmpeg | 7cbb32e461cdbe8b745d560c1700c711ba5933cc |
9,144 | static void panicked_mon_event(const char *action)
{
QObject *data;
data = qobject_from_jsonf("{ 'action': %s }", action);
monitor_protocol_event(QEVENT_GUEST_PANICKED, data);
qobject_decref(data);
}
| true | qemu | 3a4496903795e05c1e8367bb4c9862d5670f48d7 |
9,145 | int inet_aton (const char * str, struct in_addr * add)
{
const char * pch = str;
unsigned int add1 = 0, add2 = 0, add3 = 0, add4 = 0;
add1 = atoi(pch);
pch = strpbrk(pch,".");
if (pch == 0 || ++pch == 0) return 0;
add2 = atoi(pch);
pch = strpbrk(pch,".");
if (pch == 0 || ++pch == 0) return 0;
add3 = atoi(pch);
pch = strpbrk(pch,".");
if (pch == 0 || ++pch == 0) return 0;
add4 = atoi(pch);
if (!add1 || (add1|add2|add3|add4) > 255) return 0;
add->s_addr=(add4<<24)+(add3<<16)+(add2<<8)+add1;
return 1;
}
| false | FFmpeg | 109d30e9f1fbe4de416fcdbcc1442aaf43f85d00 |
9,147 | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
{
return cirrus_bitblt_common_patterncopy(s,
s->vram_ptr +
(s->cirrus_blt_srcaddr & ~7));
}
| true | qemu | b2eb849d4b1fdb6f35d5c46958c7f703cf64cfef |
9,148 | static void cdg_load_palette(CDGraphicsContext *cc, uint8_t *data, int low)
{
uint8_t r, g, b;
uint16_t color;
int i;
int array_offset = low ? 0 : 8;
uint32_t *palette = (uint32_t *) cc->frame.data[1];
for (i = 0; i < 8; i++) {
color = (data[2 * i] << 6) + (data[2 * i + 1] & 0x3F);
r = ((color >> 8) & 0x000F) * 17;
g = ((color >> 4) & 0x000F) * 17;
b = ((color ) & 0x000F) * 17;
palette[i + array_offset] = 0xFF << 24 | r << 16 | g << 8 | b;
}
cc->frame.palette_has_changed = 1;
}
| true | FFmpeg | b12d92efd6c0d48665383a9baecc13e7ebbd8a22 |
9,149 | static void load_elf_image(const char *image_name, int image_fd,
struct image_info *info, char **pinterp_name,
char bprm_buf[BPRM_BUF_SIZE])
{
struct elfhdr *ehdr = (struct elfhdr *)bprm_buf;
struct elf_phdr *phdr;
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
int i, retval;
const char *errmsg;
/* First of all, some simple consistency checks */
errmsg = "Invalid ELF image for this architecture";
if (!elf_check_ident(ehdr)) {
goto exit_errmsg;
}
bswap_ehdr(ehdr);
if (!elf_check_ehdr(ehdr)) {
goto exit_errmsg;
}
i = ehdr->e_phnum * sizeof(struct elf_phdr);
if (ehdr->e_phoff + i <= BPRM_BUF_SIZE) {
phdr = (struct elf_phdr *)(bprm_buf + ehdr->e_phoff);
} else {
phdr = (struct elf_phdr *) alloca(i);
retval = pread(image_fd, phdr, i, ehdr->e_phoff);
if (retval != i) {
goto exit_read;
}
}
bswap_phdr(phdr, ehdr->e_phnum);
#ifdef CONFIG_USE_FDPIC
info->nsegs = 0;
info->pt_dynamic_addr = 0;
#endif
/* Find the maximum size of the image and allocate an appropriate
amount of memory to handle that. */
loaddr = -1, hiaddr = 0;
for (i = 0; i < ehdr->e_phnum; ++i) {
if (phdr[i].p_type == PT_LOAD) {
abi_ulong a = phdr[i].p_vaddr;
if (a < loaddr) {
loaddr = a;
}
a += phdr[i].p_memsz;
if (a > hiaddr) {
hiaddr = a;
}
#ifdef CONFIG_USE_FDPIC
++info->nsegs;
#endif
}
}
load_addr = loaddr;
if (ehdr->e_type == ET_DYN) {
/* The image indicates that it can be loaded anywhere. Find a
location that can hold the memory space required. If the
image is pre-linked, LOADDR will be non-zero. Since we do
not supply MAP_FIXED here we'll use that address if and
only if it remains available. */
load_addr = target_mmap(loaddr, hiaddr - loaddr, PROT_NONE,
MAP_PRIVATE | MAP_ANON | MAP_NORESERVE,
-1, 0);
if (load_addr == -1) {
goto exit_perror;
}
} else if (pinterp_name != NULL) {
/* This is the main executable. Make sure that the low
address does not conflict with MMAP_MIN_ADDR or the
QEMU application itself. */
probe_guest_base(image_name, loaddr, hiaddr);
}
load_bias = load_addr - loaddr;
#ifdef CONFIG_USE_FDPIC
{
struct elf32_fdpic_loadseg *loadsegs = info->loadsegs =
g_malloc(sizeof(*loadsegs) * info->nsegs);
for (i = 0; i < ehdr->e_phnum; ++i) {
switch (phdr[i].p_type) {
case PT_DYNAMIC:
info->pt_dynamic_addr = phdr[i].p_vaddr + load_bias;
break;
case PT_LOAD:
loadsegs->addr = phdr[i].p_vaddr + load_bias;
loadsegs->p_vaddr = phdr[i].p_vaddr;
loadsegs->p_memsz = phdr[i].p_memsz;
++loadsegs;
break;
}
}
}
#endif
info->load_bias = load_bias;
info->load_addr = load_addr;
info->entry = ehdr->e_entry + load_bias;
info->start_code = -1;
info->end_code = 0;
info->start_data = -1;
info->end_data = 0;
info->brk = 0;
for (i = 0; i < ehdr->e_phnum; i++) {
struct elf_phdr *eppnt = phdr + i;
if (eppnt->p_type == PT_LOAD) {
abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em;
int elf_prot = 0;
if (eppnt->p_flags & PF_R) elf_prot = PROT_READ;
if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE;
if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC;
vaddr = load_bias + eppnt->p_vaddr;
vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
vaddr_ps = TARGET_ELF_PAGESTART(vaddr);
error = target_mmap(vaddr_ps, eppnt->p_filesz + vaddr_po,
elf_prot, MAP_PRIVATE | MAP_FIXED,
image_fd, eppnt->p_offset - vaddr_po);
if (error == -1) {
goto exit_perror;
}
vaddr_ef = vaddr + eppnt->p_filesz;
vaddr_em = vaddr + eppnt->p_memsz;
/* If the load segment requests extra zeros (e.g. bss), map it. */
if (vaddr_ef < vaddr_em) {
zero_bss(vaddr_ef, vaddr_em, elf_prot);
}
/* Find the full program boundaries. */
if (elf_prot & PROT_EXEC) {
if (vaddr < info->start_code) {
info->start_code = vaddr;
}
if (vaddr_ef > info->end_code) {
info->end_code = vaddr_ef;
}
}
if (elf_prot & PROT_WRITE) {
if (vaddr < info->start_data) {
info->start_data = vaddr;
}
if (vaddr_ef > info->end_data) {
info->end_data = vaddr_ef;
}
if (vaddr_em > info->brk) {
info->brk = vaddr_em;
}
}
} else if (eppnt->p_type == PT_INTERP && pinterp_name) {
char *interp_name;
if (*pinterp_name) {
errmsg = "Multiple PT_INTERP entries";
goto exit_errmsg;
}
interp_name = malloc(eppnt->p_filesz);
if (!interp_name) {
goto exit_perror;
}
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
memcpy(interp_name, bprm_buf + eppnt->p_offset,
eppnt->p_filesz);
} else {
retval = pread(image_fd, interp_name, eppnt->p_filesz,
eppnt->p_offset);
if (retval != eppnt->p_filesz) {
goto exit_perror;
}
}
if (interp_name[eppnt->p_filesz - 1] != 0) {
errmsg = "Invalid PT_INTERP entry";
goto exit_errmsg;
}
*pinterp_name = interp_name;
}
}
if (info->end_data == 0) {
info->start_data = info->end_code;
info->end_data = info->end_code;
info->brk = info->end_code;
}
if (qemu_log_enabled()) {
load_symbols(ehdr, image_fd, load_bias);
}
close(image_fd);
return;
exit_read:
if (retval >= 0) {
errmsg = "Incomplete read of file header";
goto exit_errmsg;
}
exit_perror:
errmsg = strerror(errno);
exit_errmsg:
fprintf(stderr, "%s: %s\n", image_name, errmsg);
exit(-1);
} | true | qemu | d8fd2954996255ba6ad610917e7849832d0120b7 |
9,151 | void omap_clk_init(struct omap_mpu_state_s *mpu)
{
struct clk **i, *j, *k;
int count;
int flag;
if (cpu_is_omap310(mpu))
flag = CLOCK_IN_OMAP310;
else if (cpu_is_omap1510(mpu))
flag = CLOCK_IN_OMAP1510;
else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
flag = CLOCK_IN_OMAP242X;
else if (cpu_is_omap2430(mpu))
flag = CLOCK_IN_OMAP243X;
else if (cpu_is_omap3430(mpu))
flag = CLOCK_IN_OMAP243X;
else
return;
for (i = onchip_clks, count = 0; *i; i ++)
if ((*i)->flags & flag)
count ++;
mpu->clks = (struct clk *) g_malloc0(sizeof(struct clk) * (count + 1));
for (i = onchip_clks, j = mpu->clks; *i; i ++)
if ((*i)->flags & flag) {
memcpy(j, *i, sizeof(struct clk));
for (k = mpu->clks; k < j; k ++)
if (j->parent && !strcmp(j->parent->name, k->name)) {
j->parent = k;
j->sibling = k->child1;
k->child1 = j;
} else if (k->parent && !strcmp(k->parent->name, j->name)) {
k->parent = j;
k->sibling = j->child1;
j->child1 = k;
}
j->divisor = j->divisor ?: 1;
j->multiplier = j->multiplier ?: 1;
j ++;
}
for (j = mpu->clks; count --; j ++) {
omap_clk_update(j);
omap_clk_rate_update(j);
}
}
| true | qemu | b45c03f585ea9bb1af76c73e82195418c294919d |
9,152 | static void ohci_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = usb_ohci_initfn_pci;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
k->class_id = PCI_CLASS_SERIAL_USB;
dc->desc = "Apple USB Controller";
dc->props = ohci_pci_properties;
} | true | qemu | 6c2d1c32d084320081b0cd047f8cacd6e722d03a |
9,153 | int av_opt_set(void *obj, const char *name, const char *val, int search_flags)
{
int ret;
void *dst, *target_obj;
const AVOption *o = av_opt_find2(obj, name, NULL, 0, search_flags, &target_obj);
if (!o || !target_obj)
return AVERROR_OPTION_NOT_FOUND;
if (!val && (o->type != AV_OPT_TYPE_STRING &&
o->type != AV_OPT_TYPE_PIXEL_FMT && o->type != AV_OPT_TYPE_SAMPLE_FMT &&
o->type != AV_OPT_TYPE_IMAGE_SIZE && o->type != AV_OPT_TYPE_VIDEO_RATE &&
o->type != AV_OPT_TYPE_DURATION && o->type != AV_OPT_TYPE_COLOR &&
o->type != AV_OPT_TYPE_CHANNEL_LAYOUT))
return AVERROR(EINVAL);
dst = ((uint8_t*)target_obj) + o->offset;
switch (o->type) {
case AV_OPT_TYPE_STRING: return set_string(obj, o, val, dst);
case AV_OPT_TYPE_BINARY: return set_string_binary(obj, o, val, dst);
case AV_OPT_TYPE_FLAGS:
case AV_OPT_TYPE_INT:
case AV_OPT_TYPE_INT64:
case AV_OPT_TYPE_FLOAT:
case AV_OPT_TYPE_DOUBLE:
case AV_OPT_TYPE_RATIONAL: return set_string_number(obj, target_obj, o, val, dst);
case AV_OPT_TYPE_IMAGE_SIZE:
if (!val || !strcmp(val, "none")) {
*(int *)dst = *((int *)dst + 1) = 0;
return 0;
}
ret = av_parse_video_size(dst, ((int *)dst) + 1, val);
if (ret < 0)
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as image size\n", val);
return ret;
case AV_OPT_TYPE_VIDEO_RATE:
if (!val) {
ret = AVERROR(EINVAL);
} else {
ret = av_parse_video_rate(dst, val);
}
if (ret < 0)
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as video rate\n", val);
return ret;
case AV_OPT_TYPE_PIXEL_FMT:
if (!val || !strcmp(val, "none")) {
ret = AV_PIX_FMT_NONE;
} else {
ret = av_get_pix_fmt(val);
if (ret == AV_PIX_FMT_NONE) {
char *tail;
ret = strtol(val, &tail, 0);
if (*tail || (unsigned)ret >= AV_PIX_FMT_NB) {
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as pixel format\n", val);
return AVERROR(EINVAL);
}
}
}
*(enum AVPixelFormat *)dst = ret;
return 0;
case AV_OPT_TYPE_SAMPLE_FMT:
if (!val || !strcmp(val, "none")) {
ret = AV_SAMPLE_FMT_NONE;
} else {
ret = av_get_sample_fmt(val);
if (ret == AV_SAMPLE_FMT_NONE) {
char *tail;
ret = strtol(val, &tail, 0);
if (*tail || (unsigned)ret >= AV_SAMPLE_FMT_NB) {
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as sample format\n", val);
return AVERROR(EINVAL);
}
}
}
*(enum AVSampleFormat *)dst = ret;
return 0;
case AV_OPT_TYPE_DURATION:
if (!val) {
*(int64_t *)dst = 0;
return 0;
} else {
if ((ret = av_parse_time(dst, val, 1)) < 0)
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as duration\n", val);
return ret;
}
break;
case AV_OPT_TYPE_COLOR:
if (!val) {
return 0;
} else {
ret = av_parse_color(dst, val, -1, obj);
if (ret < 0)
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as color\n", val);
return ret;
}
break;
case AV_OPT_TYPE_CHANNEL_LAYOUT:
if (!val || !strcmp(val, "none")) {
*(int64_t *)dst = 0;
} else {
#if FF_API_GET_CHANNEL_LAYOUT_COMPAT
int64_t cl = ff_get_channel_layout(val, 0);
#else
int64_t cl = av_get_channel_layout(val);
#endif
if (!cl) {
av_log(obj, AV_LOG_ERROR, "Unable to parse option value \"%s\" as channel layout\n", val);
ret = AVERROR(EINVAL);
}
*(int64_t *)dst = cl;
return ret;
}
break;
}
av_log(obj, AV_LOG_ERROR, "Invalid option type.\n");
return AVERROR(EINVAL);
}
| true | FFmpeg | 2d8ccf0adcae09cb9e14b01cfe20e4d77c3bbf5d |
9,154 | static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
hwaddr base, omap_clk clk)
{
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
omap_lpg_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
return s;
}
| true | qemu | f3c7d0389fe8a2792fd4c1cf151b885de03c8f62 |
9,155 | static void pred4x4_horizontal_vp8_c(uint8_t *src, const uint8_t *topright, int stride){
const int lt= src[-1-1*stride];
LOAD_LEFT_EDGE
AV_WN32A(src+0*stride, ((lt + 2*l0 + l1 + 2) >> 2)*0x01010101);
AV_WN32A(src+1*stride, ((l0 + 2*l1 + l2 + 2) >> 2)*0x01010101);
AV_WN32A(src+2*stride, ((l1 + 2*l2 + l3 + 2) >> 2)*0x01010101);
AV_WN32A(src+3*stride, ((l2 + 2*l3 + l3 + 2) >> 2)*0x01010101);
}
| true | FFmpeg | 60f10e0ad37418cc697765d85b0bc22db70f726a |
9,156 | static void restart_coroutine(void *opaque)
{
Coroutine *co = opaque;
DPRINTF("co=%p", co);
qemu_coroutine_enter(co, NULL);
}
| true | qemu | 0b8b8753e4d94901627b3e86431230f2319215c4 |
9,157 | PPC_OP(test_ctrz_false)
{
T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0);
RETURN();
}
| true | qemu | d9bce9d99f4656ae0b0127f7472db9067b8f84ab |
9,158 | static int packed_16bpc_bswap(SwsContext *c, const uint8_t *src[],
int srcStride[], int srcSliceY, int srcSliceH,
uint8_t *dst[], int dstStride[])
{
int i, j;
int srcstr = srcStride[0] >> 1;
int dststr = dstStride[0] >> 1;
uint16_t *dstPtr = (uint16_t *) dst[0];
const uint16_t *srcPtr = (const uint16_t *) src[0];
for (i = 0; i < srcSliceH; i++) {
for (j = 0; j < srcstr; j++) {
dstPtr[j] = av_bswap16(srcPtr[j]);
}
srcPtr += srcstr;
dstPtr += dststr;
}
return srcSliceH;
}
| true | FFmpeg | 6e9bb5aa3ed0b56c484ba96bf1bb3bdd8a9741f3 |
9,159 | int monitor_read_bdrv_key_start(Monitor *mon, BlockDriverState *bs,
BlockCompletionFunc *completion_cb,
void *opaque)
{
Error *local_err = NULL;
int err;
bdrv_add_key(bs, NULL, &local_err);
if (!local_err) {
if (completion_cb)
completion_cb(opaque, 0);
return 0;
}
/* Need a key for @bs */
if (monitor_ctrl_mode(mon)) {
qerror_report_err(local_err);
return -1;
}
monitor_printf(mon, "%s (%s) is encrypted.\n", bdrv_get_device_name(bs),
bdrv_get_encrypted_filename(bs));
mon->password_completion_cb = completion_cb;
mon->password_opaque = opaque;
err = monitor_read_password(mon, bdrv_password_cb, bs);
if (err && completion_cb)
completion_cb(opaque, err);
return err;
} | true | qemu | 988e0f06621fde11ec0d319a6fd0ab3ccef0602f |
9,160 | static void slavio_timer_get_out(SLAVIO_TIMERState *s)
{
int out;
int64_t diff, ticks, count;
uint32_t limit;
// There are three clock tick units: CPU ticks, register units
// (nanoseconds), and counter ticks (500 ns).
if (s->mode == 1 && s->stopped)
ticks = s->stop_time;
else
ticks = qemu_get_clock(vm_clock) - s->tick_offset;
out = (ticks > s->expire_time);
if (out)
s->reached = 0x80000000;
if (!s->limit)
limit = 0x7fffffff;
else
limit = s->limit;
// Convert register units to counter ticks
limit = limit >> 9;
// Convert cpu ticks to counter ticks
diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);
// Calculate what the counter should be, convert to register
// units
count = diff % limit;
s->count = count << 9;
s->counthigh = count >> 22;
// Expire time: CPU ticks left to next interrupt
// Convert remaining counter ticks to CPU ticks
s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);
DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
if (s->mode != 1)
pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
}
| true | qemu | 31ade715088fa40976cdaf7bd4c01345ea8fda26 |
9,161 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = x86_env_get_cpu(env);
CPUState *cs = CPU(cpu);
/* test if maximum index reached */
if (index & 0x80000000) {
if (index > env->cpuid_xlevel) {
if (env->cpuid_xlevel2 > 0) {
/* Handle the Centaur's CPUID instruction. */
if (index > env->cpuid_xlevel2) {
index = env->cpuid_xlevel2;
} else if (index < 0xC0000000) {
index = env->cpuid_xlevel;
} else {
/* Intel documentation states that invalid EAX input will
* return the same information as EAX=cpuid_level
* (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
*/
index = env->cpuid_level;
} else {
if (index > env->cpuid_level)
index = env->cpuid_level;
switch(index) {
case 0:
*eax = env->cpuid_level;
get_cpuid_vendor(env, ebx, ecx, edx);
case 1:
*eax = env->cpuid_version;
*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
*ecx = env->features[FEAT_1_ECX];
*edx = env->features[FEAT_1_EDX];
if (cs->nr_cores * cs->nr_threads > 1) {
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
*edx |= 1 << 28; /* HTT bit */
case 2:
/* cache info: needed for Pentium Pro compatibility */
host_cpuid(index, 0, eax, ebx, ecx, edx);
*eax = 1; /* Number of CPUID[EAX=2] calls required */
*ebx = 0;
*ecx = 0;
*edx = (L1D_DESCRIPTOR << 16) | \
(L1I_DESCRIPTOR << 8) | \
(L2_DESCRIPTOR);
case 4:
/* cache info: needed for Core compatibility */
if (cs->nr_cores > 1) {
*eax = (cs->nr_cores - 1) << 26;
} else {
*eax = 0;
switch (count) {
case 0: /* L1 dcache info */
*eax |= CPUID_4_TYPE_DCACHE | \
CPUID_4_LEVEL(1) | \
CPUID_4_SELF_INIT_LEVEL;
*ebx = (L1D_LINE_SIZE - 1) | \
((L1D_PARTITIONS - 1) << 12) | \
((L1D_ASSOCIATIVITY - 1) << 22);
*ecx = L1D_SETS - 1;
*edx = CPUID_4_NO_INVD_SHARING;
case 1: /* L1 icache info */
*eax |= CPUID_4_TYPE_ICACHE | \
CPUID_4_LEVEL(1) | \
CPUID_4_SELF_INIT_LEVEL;
*ebx = (L1I_LINE_SIZE - 1) | \
((L1I_PARTITIONS - 1) << 12) | \
((L1I_ASSOCIATIVITY - 1) << 22);
*ecx = L1I_SETS - 1;
*edx = CPUID_4_NO_INVD_SHARING;
case 2: /* L2 cache info */
*eax |= CPUID_4_TYPE_UNIFIED | \
CPUID_4_LEVEL(2) | \
CPUID_4_SELF_INIT_LEVEL;
if (cs->nr_threads > 1) {
*eax |= (cs->nr_threads - 1) << 14;
*ebx = (L2_LINE_SIZE - 1) | \
((L2_PARTITIONS - 1) << 12) | \
((L2_ASSOCIATIVITY - 1) << 22);
*ecx = L2_SETS - 1;
*edx = CPUID_4_NO_INVD_SHARING;
default: /* end of info */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 5:
/* mwait info: needed for Core compatibility */
*eax = 0; /* Smallest monitor-line size in bytes */
*ebx = 0; /* Largest monitor-line size in bytes */
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
*edx = 0;
case 6:
/* Thermal and Power Leaf */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 7:
/* Structured Extended Feature Flags Enumeration Leaf */
if (count == 0) {
*eax = 0; /* Maximum ECX value for sub-leaves */
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
*ecx = 0; /* Reserved */
*edx = 0; /* Reserved */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 9:
/* Direct Cache Access Information Leaf */
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */
*ebx = 0;
*ecx = 0;
*edx = 0;
case 0xA:
/* Architectural Performance Monitoring Leaf */
if (kvm_enabled() && cpu->enable_pmu) {
KVMState *s = cs->kvm_state;
*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 0xD:
/* Processor Extended State */
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
if (kvm_enabled()) {
KVMState *s = cs->kvm_state;
*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 0x80000000:
*eax = env->cpuid_xlevel;
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
case 0x80000001:
*eax = env->cpuid_version;
*ebx = 0;
*ecx = env->features[FEAT_8000_0001_ECX];
*edx = env->features[FEAT_8000_0001_EDX];
/* The Linux kernel checks for the CMPLegacy bit and
* discards multiple thread information if it is set.
* So dont set it here for Intel to make Linux guests happy.
*/
if (cs->nr_cores * cs->nr_threads > 1) {
uint32_t tebx, tecx, tedx;
get_cpuid_vendor(env, &tebx, &tecx, &tedx);
if (tebx != CPUID_VENDOR_INTEL_1 ||
tedx != CPUID_VENDOR_INTEL_2 ||
tecx != CPUID_VENDOR_INTEL_3) {
*ecx |= 1 << 1; /* CmpLegacy bit */
case 0x80000002:
case 0x80000003:
case 0x80000004:
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
case 0x80000005:
/* cache info (L1 cache) */
host_cpuid(index, 0, eax, ebx, ecx, edx);
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
*ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
(L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
*edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
(L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
case 0x80000006:
/* cache info (L2 cache) */
host_cpuid(index, 0, eax, ebx, ecx, edx);
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
(L2_DTLB_2M_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
(L2_ITLB_2M_ENTRIES);
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
(L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES);
*ecx = (L2_SIZE_KB_AMD << 16) | \
(AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
(L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
*edx = ((L3_SIZE_KB/512) << 18) | \
(AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
(L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
/* XXX: This value must match the one used in the MMU code. */
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
/* 64 bit processor */
/* XXX: The physical address space is limited to 42 bits in exec.c. */
*eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
} else {
if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
*eax = 0x00000024; /* 36 bits physical */
} else {
*eax = 0x00000020; /* 32 bits physical */
*ebx = 0;
*ecx = 0;
*edx = 0;
if (cs->nr_cores * cs->nr_threads > 1) {
*ecx |= (cs->nr_cores * cs->nr_threads) - 1;
case 0x8000000A:
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
*eax = 0x00000001; /* SVM Revision */
*ebx = 0x00000010; /* nr of ASIDs */
*ecx = 0;
*edx = env->features[FEAT_SVM]; /* optional features */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
*ecx = 0;
*edx = 0;
case 0xC0000001:
/* Support for VIA CPU's CPUID instruction */
*eax = env->cpuid_version;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_C000_0001_EDX];
case 0xC0000002:
case 0xC0000003:
case 0xC0000004:
/* Reserved for the future, and now filled with zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
default:
/* reserved values: zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
| true | qemu | 787aaf5703a702094f395db6795e74230282cd62 |
9,163 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
{
pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
QXLMode *mode = d->modes->modes + modenr;
uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
QXLMemSlot slot = {
.mem_start = start,
.mem_end = end
};
QXLSurfaceCreate surface = {
.width = mode->x_res,
.height = mode->y_res,
.stride = -mode->x_res * 4,
.format = SPICE_SURFACE_FMT_32_xRGB,
.flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
.mouse_mode = true,
.mem = devmem + d->shadow_rom.draw_area_offset,
};
trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
devmem);
if (!loadvm) {
qxl_hard_reset(d, 0);
}
d->guest_slots[0].slot = slot;
qxl_add_memslot(d, 0, devmem, QXL_SYNC);
d->guest_primary.surface = surface;
qxl_create_guest_primary(d, 0, QXL_SYNC);
d->mode = QXL_MODE_COMPAT;
d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
if (mode->bits == 16) {
d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
}
#endif
d->shadow_rom.mode = cpu_to_le32(modenr);
d->rom->mode = cpu_to_le32(modenr);
qxl_rom_set_dirty(d);
}
| true | qemu | e954ea2873fd6621d199d4a1a012fc0bc0292924 |
9,164 | static int aac_parse_packet(AVFormatContext *ctx, PayloadContext *data,
AVStream *st, AVPacket *pkt, uint32_t *timestamp,
const uint8_t *buf, int len, uint16_t seq,
int flags)
{
int ret;
if (rtp_parse_mp4_au(data, buf))
return -1;
buf += data->au_headers_length_bytes + 2;
len -= data->au_headers_length_bytes + 2;
/* XXX: Fixme we only handle the case where rtp_parse_mp4_au define
one au_header */
if ((ret = av_new_packet(pkt, data->au_headers[0].size)) < 0)
return ret;
memcpy(pkt->data, buf, data->au_headers[0].size);
pkt->stream_index = st->index;
return 0;
}
| true | FFmpeg | a7ba3244131d96d9ab7a99ef30dc7276efd05cc7 |
9,165 | static int decode_header(SnowContext *s){
int plane_index, tmp;
uint8_t kstate[32];
memset(kstate, MID_STATE, sizeof(kstate));
s->keyframe= get_rac(&s->c, kstate);
if(s->keyframe || s->always_reset){
ff_snow_reset_contexts(s);
s->spatial_decomposition_type=
s->qlog=
s->qbias=
s->mv_scale=
s->block_max_depth= 0;
}
if(s->keyframe){
GET_S(s->version, tmp <= 0U)
s->always_reset= get_rac(&s->c, s->header_state);
s->temporal_decomposition_type= get_symbol(&s->c, s->header_state, 0);
s->temporal_decomposition_count= get_symbol(&s->c, s->header_state, 0);
GET_S(s->spatial_decomposition_count, 0 < tmp && tmp <= MAX_DECOMPOSITIONS)
s->colorspace_type= get_symbol(&s->c, s->header_state, 0);
if (s->colorspace_type == 1) {
s->avctx->pix_fmt= AV_PIX_FMT_GRAY8;
s->nb_planes = 1;
} else if(s->colorspace_type == 0) {
s->chroma_h_shift= get_symbol(&s->c, s->header_state, 0);
s->chroma_v_shift= get_symbol(&s->c, s->header_state, 0);
if(s->chroma_h_shift == 1 && s->chroma_v_shift==1){
s->avctx->pix_fmt= AV_PIX_FMT_YUV420P;
}else if(s->chroma_h_shift == 0 && s->chroma_v_shift==0){
s->avctx->pix_fmt= AV_PIX_FMT_YUV444P;
}else if(s->chroma_h_shift == 2 && s->chroma_v_shift==2){
s->avctx->pix_fmt= AV_PIX_FMT_YUV410P;
} else {
av_log(s, AV_LOG_ERROR, "unsupported color subsample mode %d %d\n", s->chroma_h_shift, s->chroma_v_shift);
s->chroma_h_shift = s->chroma_v_shift = 1;
s->avctx->pix_fmt= AV_PIX_FMT_YUV420P;
return AVERROR_INVALIDDATA;
}
s->nb_planes = 3;
} else {
av_log(s, AV_LOG_ERROR, "unsupported color space\n");
s->chroma_h_shift = s->chroma_v_shift = 1;
s->avctx->pix_fmt= AV_PIX_FMT_YUV420P;
return AVERROR_INVALIDDATA;
}
s->spatial_scalability= get_rac(&s->c, s->header_state);
// s->rate_scalability= get_rac(&s->c, s->header_state);
GET_S(s->max_ref_frames, tmp < (unsigned)MAX_REF_FRAMES)
s->max_ref_frames++;
decode_qlogs(s);
}
if(!s->keyframe){
if(get_rac(&s->c, s->header_state)){
for(plane_index=0; plane_index<FFMIN(s->nb_planes, 2); plane_index++){
int htaps, i, sum=0;
Plane *p= &s->plane[plane_index];
p->diag_mc= get_rac(&s->c, s->header_state);
htaps= get_symbol(&s->c, s->header_state, 0)*2 + 2;
if((unsigned)htaps >= HTAPS_MAX || htaps==0)
return AVERROR_INVALIDDATA;
p->htaps= htaps;
for(i= htaps/2; i; i--){
p->hcoeff[i]= get_symbol(&s->c, s->header_state, 0) * (1-2*(i&1));
sum += p->hcoeff[i];
}
p->hcoeff[0]= 32-sum;
}
s->plane[2].diag_mc= s->plane[1].diag_mc;
s->plane[2].htaps = s->plane[1].htaps;
memcpy(s->plane[2].hcoeff, s->plane[1].hcoeff, sizeof(s->plane[1].hcoeff));
}
if(get_rac(&s->c, s->header_state)){
GET_S(s->spatial_decomposition_count, 0 < tmp && tmp <= MAX_DECOMPOSITIONS)
decode_qlogs(s);
}
}
s->spatial_decomposition_type+= get_symbol(&s->c, s->header_state, 1);
if(s->spatial_decomposition_type > 1U){
av_log(s->avctx, AV_LOG_ERROR, "spatial_decomposition_type %d not supported\n", s->spatial_decomposition_type);
return AVERROR_INVALIDDATA;
}
if(FFMIN(s->avctx-> width>>s->chroma_h_shift,
s->avctx->height>>s->chroma_v_shift) >> (s->spatial_decomposition_count-1) <= 1){
av_log(s->avctx, AV_LOG_ERROR, "spatial_decomposition_count %d too large for size\n", s->spatial_decomposition_count);
return AVERROR_INVALIDDATA;
}
if (s->avctx->width > 65536-4) {
av_log(s->avctx, AV_LOG_ERROR, "Width %d is too large\n", s->avctx->width);
return AVERROR_INVALIDDATA;
}
s->qlog += get_symbol(&s->c, s->header_state, 1);
s->mv_scale += get_symbol(&s->c, s->header_state, 1);
s->qbias += get_symbol(&s->c, s->header_state, 1);
s->block_max_depth+= get_symbol(&s->c, s->header_state, 1);
if(s->block_max_depth > 1 || s->block_max_depth < 0 || s->mv_scale > 256U){
av_log(s->avctx, AV_LOG_ERROR, "block_max_depth= %d is too large\n", s->block_max_depth);
s->block_max_depth= 0;
s->mv_scale = 0;
return AVERROR_INVALIDDATA;
}
if (FFABS(s->qbias) > 127) {
av_log(s->avctx, AV_LOG_ERROR, "qbias %d is too large\n", s->qbias);
s->qbias = 0;
return AVERROR_INVALIDDATA;
}
return 0;
}
| true | FFmpeg | c897a9285846b6a072b9650976afd4f091b7a71f |
9,166 | void alpha_translate_init(void)
{
#define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUAlphaState, V) }
typedef struct { TCGv *var; const char *name; int ofs; } GlobalVar;
static const GlobalVar vars[] = {
DEF_VAR(pc),
DEF_VAR(lock_addr),
DEF_VAR(lock_st_addr),
DEF_VAR(lock_value),
DEF_VAR(unique),
#ifndef CONFIG_USER_ONLY
DEF_VAR(sysval),
DEF_VAR(usp),
#endif
};
#undef DEF_VAR
/* Use the symbolic register names that match the disassembler. */
static const char greg_names[31][4] = {
"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
"t10", "t11", "ra", "t12", "at", "gp", "sp"
};
static const char freg_names[31][4] = {
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30"
};
static bool done_init = 0;
int i;
if (done_init) {
return;
}
done_init = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
for (i = 0; i < 31; i++) {
cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUAlphaState, ir[i]),
greg_names[i]);
}
for (i = 0; i < 31; i++) {
cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUAlphaState, fir[i]),
freg_names[i]);
}
for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i];
*v->var = tcg_global_mem_new_i64(TCG_AREG0, v->ofs, v->name);
}
}
| true | qemu | 06ef8604e92964cbf30084b7d31091aa7cbbb62f |
9,167 | static void RENAME(mix6to2)(SAMPLE **out, const SAMPLE **in, COEFF *coeffp, integer len){
int i;
for(i=0; i<len; i++) {
INTER t = in[2][i]*coeffp[0*6+2] + in[3][i]*coeffp[0*6+3];
out[0][i] = R(t + in[0][i]*(INTER)coeffp[0*6+0] + in[4][i]*(INTER)coeffp[0*6+4]);
out[1][i] = R(t + in[1][i]*(INTER)coeffp[1*6+1] + in[5][i]*(INTER)coeffp[1*6+5]);
}
}
| true | FFmpeg | b04bbe6b869581d572fe6b1dc351a2fd8e134cc1 |
9,168 | static QPCIDevice *get_device(void)
{
QPCIDevice *dev;
QPCIBus *pcibus;
pcibus = qpci_init_pc();
dev = NULL;
qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
g_assert(dev != NULL);
return dev;
}
| true | qemu | 1760048a5d21bacf0e4838da2f61b2d8db7d2866 |
9,169 | void do_nego (void)
{
if (likely(T0 != INT32_MIN)) {
xer_ov = 0;
T0 = -Ts0;
} else {
xer_ov = 1;
xer_so = 1;
}
}
| true | qemu | d9bce9d99f4656ae0b0127f7472db9067b8f84ab |
9,170 | static int nbd_co_writev_1(NbdClientSession *client, int64_t sector_num,
int nb_sectors, QEMUIOVector *qiov,
int offset)
{
struct nbd_request request;
struct nbd_reply reply;
ssize_t ret;
request.type = NBD_CMD_WRITE;
if (!bdrv_enable_write_cache(client->bs) &&
(client->nbdflags & NBD_FLAG_SEND_FUA)) {
request.type |= NBD_CMD_FLAG_FUA;
}
request.from = sector_num * 512;
request.len = nb_sectors * 512;
nbd_coroutine_start(client, &request);
ret = nbd_co_send_request(client, &request, qiov, offset);
if (ret < 0) {
reply.error = -ret;
} else {
nbd_co_receive_reply(client, &request, &reply, NULL, 0);
}
nbd_coroutine_end(client, &request);
return -reply.error;
}
| true | qemu | b1b27b64262fdace45e5ab134c4438338076cb98 |
9,171 | void qemu_input_event_send_key(QemuConsole *src, KeyValue *key, bool down)
{
InputEvent *evt;
evt = qemu_input_event_new_key(key, down);
if (QTAILQ_EMPTY(&kbd_queue)) {
qemu_input_event_send(src, evt);
qemu_input_event_sync();
qapi_free_InputEvent(evt);
} else {
qemu_input_queue_event(&kbd_queue, src, evt);
qemu_input_queue_sync(&kbd_queue);
}
}
| true | qemu | fa18f36a461984eae50ab957e47ec78dae3c14fc |
9,173 | int av_strerror(int errnum, char *errbuf, size_t errbuf_size)
{
int ret = 0, i;
struct error_entry *entry = NULL;
for (i = 0; i < FF_ARRAY_ELEMS(error_entries); i++) {
if (errnum == error_entries[i].num) {
entry = &error_entries[i];
break;
}
}
if (entry) {
av_strlcpy(errbuf, entry->str, errbuf_size);
} else {
#if HAVE_STRERROR_R
ret = strerror_r(AVUNERROR(errnum), errbuf, errbuf_size);
#else
ret = -1;
#endif
if (ret < 0)
snprintf(errbuf, errbuf_size, "Error number %d occurred", errnum);
}
return ret;
}
| true | FFmpeg | 5683de00e99e4be87419a97d521887f94acc937a |
9,175 | int blk_insert_bs(BlockBackend *blk, BlockDriverState *bs, Error **errp)
{
blk->root = bdrv_root_attach_child(bs, "root", &child_root,
blk->perm, blk->shared_perm, blk, errp);
if (blk->root == NULL) {
return -EPERM;
}
bdrv_ref(bs);
notifier_list_notify(&blk->insert_bs_notifiers, blk);
if (blk->public.throttle_group_member.throttle_state) {
throttle_timers_attach_aio_context(
&blk->public.throttle_group_member.throttle_timers,
bdrv_get_aio_context(bs));
}
return 0;
}
| true | qemu | c89bcf3af01e7a8834cca5344e098bf879e99999 |
9,177 | void rgb15tobgr24(const uint8_t *src, uint8_t *dst, long src_size)
{
const uint16_t *end;
uint8_t *d = (uint8_t *)dst;
const uint16_t *s = (uint16_t *)src;
end = s + src_size/2;
while(s < end)
{
register uint16_t bgr;
bgr = *s++;
*d++ = (bgr&0x7C00)>>7;
*d++ = (bgr&0x3E0)>>2;
*d++ = (bgr&0x1F)<<3;
}
}
| true | FFmpeg | 6e42e6c4b410dbef8b593c2d796a5dad95f89ee4 |
9,179 | int ff_xvmc_field_start(MpegEncContext *s, AVCodecContext *avctx)
{
struct xvmc_pix_fmt *last, *next, *render = (struct xvmc_pix_fmt*)s->current_picture.f.data[2];
const int mb_block_count = 4 + (1 << s->chroma_format);
assert(avctx);
if (!render || render->xvmc_id != AV_XVMC_ID ||
!render->data_blocks || !render->mv_blocks ||
(unsigned int)render->allocated_mv_blocks > INT_MAX/(64*6) ||
(unsigned int)render->allocated_data_blocks > INT_MAX/64 ||
!render->p_surface) {
av_log(avctx, AV_LOG_ERROR,
"Render token doesn't look as expected.\n");
return -1; // make sure that this is a render packet
}
if (render->filled_mv_blocks_num) {
av_log(avctx, AV_LOG_ERROR,
"Rendering surface contains %i unprocessed blocks.\n",
render->filled_mv_blocks_num);
return -1;
}
if (render->allocated_mv_blocks < 1 ||
render->allocated_data_blocks < render->allocated_mv_blocks*mb_block_count ||
render->start_mv_blocks_num >= render->allocated_mv_blocks ||
render->next_free_data_block_num >
render->allocated_data_blocks -
mb_block_count*(render->allocated_mv_blocks-render->start_mv_blocks_num)) {
av_log(avctx, AV_LOG_ERROR,
"Rendering surface doesn't provide enough block structures to work with.\n");
return -1;
}
render->picture_structure = s->picture_structure;
render->flags = s->first_field ? 0 : XVMC_SECOND_FIELD;
render->p_future_surface = NULL;
render->p_past_surface = NULL;
switch(s->pict_type) {
case AV_PICTURE_TYPE_I:
return 0; // no prediction from other frames
case AV_PICTURE_TYPE_B:
next = (struct xvmc_pix_fmt*)s->next_picture.f.data[2];
if (!next)
return -1;
if (next->xvmc_id != AV_XVMC_ID)
return -1;
render->p_future_surface = next->p_surface;
// no return here, going to set forward prediction
case AV_PICTURE_TYPE_P:
last = (struct xvmc_pix_fmt*)s->last_picture.f.data[2];
if (!last)
last = render; // predict second field from the first
if (last->xvmc_id != AV_XVMC_ID)
return -1;
render->p_past_surface = last->p_surface;
return 0;
}
return -1;
}
| true | FFmpeg | f6774f905fb3cfdc319523ac640be30b14c1bc55 |
9,180 | static int handle_dependencies(BlockDriverState *bs, uint64_t guest_offset,
uint64_t *cur_bytes)
{
BDRVQcowState *s = bs->opaque;
QCowL2Meta *old_alloc;
uint64_t bytes = *cur_bytes;
QLIST_FOREACH(old_alloc, &s->cluster_allocs, next_in_flight) {
uint64_t start = guest_offset;
uint64_t end = start + bytes;
uint64_t old_start = l2meta_cow_start(old_alloc);
uint64_t old_end = l2meta_cow_end(old_alloc);
if (end <= old_start || start >= old_end) {
/* No intersection */
} else {
if (start < old_start) {
/* Stop at the start of a running allocation */
bytes = old_start - start;
} else {
bytes = 0;
}
if (bytes == 0) {
/* Wait for the dependency to complete. We need to recheck
* the free/allocated clusters when we continue. */
qemu_co_mutex_unlock(&s->lock);
qemu_co_queue_wait(&old_alloc->dependent_requests);
qemu_co_mutex_lock(&s->lock);
return -EAGAIN;
}
}
}
/* Make sure that existing clusters and new allocations are only used up to
* the next dependency if we shortened the request above */
*cur_bytes = bytes;
return 0;
}
| true | qemu | ecdd5333ab9ed3f2b848066aaaef02c027b25e36 |
9,181 | void scsi_req_data(SCSIRequest *req, int len)
{
trace_scsi_req_data(req->dev->id, req->lun, req->tag, len);
req->bus->ops->complete(req->bus, SCSI_REASON_DATA, req->tag, len);
}
| true | qemu | 5c6c0e513600ba57c3e73b7151d3c0664438f7b5 |
9,182 | static int compute_mask(int step, uint32_t *mask)
{
int i, z, ret = 0;
int counter_size = sizeof(uint32_t) * (2 * step + 1);
uint32_t *temp1_counter, *temp2_counter, **counter;
temp1_counter = av_mallocz(counter_size);
if (!temp1_counter) {
ret = AVERROR(ENOMEM);
goto end;
}
temp2_counter = av_mallocz(counter_size);
if (!temp2_counter) {
ret = AVERROR(ENOMEM);
goto end;
}
counter = av_mallocz_array(2 * step + 1, sizeof(uint32_t *));
if (!counter) {
ret = AVERROR(ENOMEM);
goto end;
}
for (i = 0; i < 2 * step + 1; i++) {
counter[i] = av_mallocz(counter_size);
if (!counter[i]) {
ret = AVERROR(ENOMEM);
goto end;
}
}
for (i = 0; i < 2 * step + 1; i++) {
memset(temp1_counter, 0, counter_size);
temp1_counter[i] = 1;
for (z = 0; z < step * 2; z += 2) {
add_mask_counter(temp2_counter, counter[z], temp1_counter, step * 2);
memcpy(counter[z], temp1_counter, counter_size);
add_mask_counter(temp1_counter, counter[z + 1], temp2_counter, step * 2);
memcpy(counter[z + 1], temp2_counter, counter_size);
}
}
memcpy(mask, temp1_counter, counter_size);
end:
av_freep(&temp1_counter);
av_freep(&temp2_counter);
for (i = 0; i < 2 * step + 1; i++) {
av_freep(&counter[i]);
}
av_freep(&counter);
return ret;
}
| true | FFmpeg | 21583e936a06fa0c9dca99436c21d441d04e57f4 |
9,183 | static int encode_end(AVCodecContext *avctx)
{
FFV1Context *s = avctx->priv_data;
common_end(s);
return 0;
}
| true | FFmpeg | 0c2aaa882d124f05b7bf0a4a4abba3293f4d6d84 |
9,184 | static void vga_isa_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
ISAVGAState *d = ISA_VGA(dev);
VGACommonState *s = &d->state;
MemoryRegion *vga_io_memory;
const MemoryRegionPortio *vga_ports, *vbe_ports;
vga_common_init(s, OBJECT(dev), true);
s->legacy_address_space = isa_address_space(isadev);
vga_io_memory = vga_init_io(s, OBJECT(dev), &vga_ports, &vbe_ports);
isa_register_portio_list(isadev, 0x3b0, vga_ports, s, "vga");
if (vbe_ports) {
isa_register_portio_list(isadev, 0x1ce, vbe_ports, s, "vbe");
}
memory_region_add_subregion_overlap(isa_address_space(isadev),
0x000a0000,
vga_io_memory, 1);
memory_region_set_coalescing(vga_io_memory);
s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
vga_init_vbe(s, OBJECT(dev), isa_address_space(isadev));
/* ROM BIOS */
rom_add_vga(VGABIOS_FILENAME);
}
| true | qemu | e305a16510afa74eec20390479e349402e55ef4c |
9,185 | static int read_matrix_params(MLPDecodeContext *m, unsigned int substr, GetBitContext *gbp)
{
SubStream *s = &m->substream[substr];
unsigned int mat, ch;
const int max_primitive_matrices = m->avctx->codec_id == AV_CODEC_ID_MLP
? MAX_MATRICES_MLP
: MAX_MATRICES_TRUEHD;
if (m->matrix_changed++ > 1) {
av_log(m->avctx, AV_LOG_ERROR, "Matrices may change only once per access unit.\n");
return AVERROR_INVALIDDATA;
}
s->num_primitive_matrices = get_bits(gbp, 4);
if (s->num_primitive_matrices > max_primitive_matrices) {
av_log(m->avctx, AV_LOG_ERROR,
"Number of primitive matrices cannot be greater than %d.\n",
max_primitive_matrices);
return AVERROR_INVALIDDATA;
}
for (mat = 0; mat < s->num_primitive_matrices; mat++) {
int frac_bits, max_chan;
s->matrix_out_ch[mat] = get_bits(gbp, 4);
frac_bits = get_bits(gbp, 4);
s->lsb_bypass [mat] = get_bits1(gbp);
if (s->matrix_out_ch[mat] > s->max_matrix_channel) {
av_log(m->avctx, AV_LOG_ERROR,
"Invalid channel %d specified as output from matrix.\n",
s->matrix_out_ch[mat]);
return AVERROR_INVALIDDATA;
}
if (frac_bits > 14) {
av_log(m->avctx, AV_LOG_ERROR,
"Too many fractional bits specified.\n");
return AVERROR_INVALIDDATA;
}
max_chan = s->max_matrix_channel;
if (!s->noise_type)
max_chan+=2;
for (ch = 0; ch <= max_chan; ch++) {
int coeff_val = 0;
if (get_bits1(gbp))
coeff_val = get_sbits(gbp, frac_bits + 2);
s->matrix_coeff[mat][ch] = coeff_val * (1 << (14 - frac_bits));
}
if (s->noise_type)
s->matrix_noise_shift[mat] = get_bits(gbp, 4);
else
s->matrix_noise_shift[mat] = 0;
}
return 0;
} | true | FFmpeg | 64ea4d102a070b95832ae4a751688f87da7760a2 |
9,186 | int spapr_tce_dma_write(VIOsPAPRDevice *dev, uint64_t taddr, const void *buf,
uint32_t size)
{
#ifdef DEBUG_TCE
fprintf(stderr, "spapr_tce_dma_write taddr=0x%llx size=0x%x\n",
(unsigned long long)taddr, size);
#endif
/* Check for bypass */
if (dev->flags & VIO_PAPR_FLAG_DMA_BYPASS) {
cpu_physical_memory_write(taddr, buf, size);
return 0;
}
while (size) {
uint64_t tce;
uint32_t lsize;
uint64_t txaddr;
/* Check if we are in bound */
if (taddr >= dev->rtce_window_size) {
#ifdef DEBUG_TCE
fprintf(stderr, "spapr_tce_dma_write out of bounds\n");
#endif
return H_DEST_PARM;
}
tce = dev->rtce_table[taddr >> SPAPR_VIO_TCE_PAGE_SHIFT].tce;
/* How much til end of page ? */
lsize = MIN(size, ((~taddr) & SPAPR_VIO_TCE_PAGE_MASK) + 1);
/* Check TCE */
if (!(tce & 2)) {
return H_DEST_PARM;
}
/* Translate */
txaddr = (tce & ~SPAPR_VIO_TCE_PAGE_MASK) |
(taddr & SPAPR_VIO_TCE_PAGE_MASK);
#ifdef DEBUG_TCE
fprintf(stderr, " -> write to txaddr=0x%llx, size=0x%x\n",
(unsigned long long)txaddr, lsize);
#endif
/* Do it */
cpu_physical_memory_write(txaddr, buf, lsize);
buf += lsize;
taddr += lsize;
size -= lsize;
}
return 0;
}
| true | qemu | ad0ebb91cd8b5fdc4a583b03645677771f420a46 |
9,187 | static void compare_refcounts(BlockDriverState *bs, BdrvCheckResult *res,
BdrvCheckMode fix, int64_t *highest_cluster,
uint16_t *refcount_table, int64_t nb_clusters)
{
BDRVQcowState *s = bs->opaque;
int64_t i;
int refcount1, refcount2, ret;
for (i = 0, *highest_cluster = 0; i < nb_clusters; i++) {
refcount1 = get_refcount(bs, i);
if (refcount1 < 0) {
fprintf(stderr, "Can't get refcount for cluster %" PRId64 ": %s\n",
i, strerror(-refcount1));
res->check_errors++;
continue;
}
refcount2 = refcount_table[i];
if (refcount1 > 0 || refcount2 > 0) {
*highest_cluster = i;
}
if (refcount1 != refcount2) {
/* Check if we're allowed to fix the mismatch */
int *num_fixed = NULL;
if (refcount1 > refcount2 && (fix & BDRV_FIX_LEAKS)) {
num_fixed = &res->leaks_fixed;
} else if (refcount1 < refcount2 && (fix & BDRV_FIX_ERRORS)) {
num_fixed = &res->corruptions_fixed;
}
fprintf(stderr, "%s cluster %" PRId64 " refcount=%d reference=%d\n",
num_fixed != NULL ? "Repairing" :
refcount1 < refcount2 ? "ERROR" :
"Leaked",
i, refcount1, refcount2);
if (num_fixed) {
ret = update_refcount(bs, i << s->cluster_bits, 1,
refcount2 - refcount1,
QCOW2_DISCARD_ALWAYS);
if (ret >= 0) {
(*num_fixed)++;
continue;
}
}
/* And if we couldn't, print an error */
if (refcount1 < refcount2) {
res->corruptions++;
} else {
res->leaks++;
}
}
}
}
| true | qemu | f307b2558f61e068ce514f2dde2cad74c62036d6 |
9,188 | int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
{
uint32_t *hc = (uint32_t*)buf;
struct kvm_ppc_pvinfo pvinfo;
if (!kvmppc_get_pvinfo(env, &pvinfo)) {
memcpy(buf, pvinfo.hcall, buf_len);
return 0;
}
/*
* Fallback to always fail hypercalls regardless of endianness:
*
* tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
* li r3, -1
* b .+8 (becomes nop in wrong endian)
* bswap32(li r3, -1)
*/
hc[0] = cpu_to_be32(0x08000048);
hc[1] = cpu_to_be32(0x3860ffff);
hc[2] = cpu_to_be32(0x48000008);
hc[3] = cpu_to_be32(bswap32(0x3860ffff));
return 0;
}
| true | qemu | 0ddbd0536296f5a36c8f225edd4d14441be6b153 |
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