README.md

metadata

dataset_info:
  features:
    - name: instruction
      dtype: string
    - name: input
      dtype: string
    - name: output
      dtype: string
    - name: metadata
      dtype: string
task_categories:
  - text-generation
language:
  - en
tags:
  - verilog
  - hardware-design
  - hdl
  - fpga
  - asic
size_categories:
  - 1K<n<10K

Verilog and hardware design training data collection

Contents

• cvdp_expert_problems.json: CVDP expert-level problems
• cvdp_memory_problems.json: CVDP memory-focused problems
• cvdp_processor_problems.json: CVDP processor design problems

Usage

from datasets import load_dataset

dataset = load_dataset('AbiralArch/verilog-training-data')

Statistics

• Files: 3
• Total Size: 10.1 MB
• Uploaded: 2025-07-31 20:40:12

Files Available

• cvdp_expert_problems.json
• cvdp_memory_problems.json
• cvdp_processor_problems.json