Hugging Face
Models
Datasets
Spaces
Community
Docs
Enterprise
Pricing
Log In
Sign Up
Datasets:
AbiralArch
/
verilog-training-data
like
1
Tasks:
Text Generation
Languages:
English
Size:
1K<n<10K
Tags:
verilog
hardware-design
hdl
fpga
asic
Dataset card
Files
Files and versions
xet
Community
main
verilog-training-data
1 contributor
History:
5 commits
AbiralArch
Upload README.md with huggingface_hub
2ac7363
verified
10 days ago
.gitattributes
Safe
2.46 kB
initial commit
10 days ago
README.md
Safe
897 Bytes
Upload README.md with huggingface_hub
10 days ago
cvdp_expert_problems.json
Safe
704 kB
Upload cvdp_expert_problems.json with huggingface_hub
10 days ago
cvdp_memory_problems.json
Safe
4.82 MB
Upload cvdp_memory_problems.json with huggingface_hub
10 days ago
cvdp_processor_problems.json
Safe
5.06 MB
Upload cvdp_processor_problems.json with huggingface_hub
10 days ago
