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H: Three stage amplifier with third transistor connected to emitter of second
My question is that for voltage gain, is it correct if I take voltage gain of each transistor and then multiplying, to get gain of whole circuit?
AI: The used expressions for the 2nd stage is wrong. The gain must be positive and below unity (emitter follower).
The product of the individual gains for the 3 stages - when correctly calculated - gives the so-called "loop gain" (A_loop). This is the gain of the complete feedback loop when it is opened at a "suitable" node.
What means "suitable"? One should find a node where a small output resistance is conncted at a high input resistance so that opening at this node will not drastically change the loading conditions. Such a node could be the emitter of Q2.
So you would start the analysis of the three stages with a test voltage at the base of Q3 (open the loop at this point before!). The collector of Q3 is connected via Rf to the emitter of Q1 (common base principle)....output of the 3-stage chain now is the emitter of Q3.
When you have the loop gain A_loop you can find the gain of the closed-loop Acl using the well-known formula
Acl=Aol/(1+A_loop) with Aol being the gain without negative feedback.
For calculating Aol the feedback loop must be opened and the path inluding Rf must be considered as an additional load at the collector of Q3.
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H: UCC25800 PSpice model
I downloaded the PSpice model of the UCC25800 from here. I then tried to create a model for LTspice by opening the .lib file within the folder and then creating a symbol in LTspice.
But, when I opened the .lib file in LTspice, it seemed to be corrupt; there are random numbers in the file. It doesn't make sense and doesn't work after symbol creation. Is the .lib file corrupt? Or is it an error on my part?
Note: the model is from TI.com and not from any third party.
AI: Look at the very top line: -
**$ENCRYPTED_LIB
**$INTERFACE
*$
* UCC25800-Q1
*****************************************************************************
* (C) Copyright 2022 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
Do you see that the file is encrypted. This means that all the random numbers you see are in fact the encrypted spice file data. You have to use features in LTspice to unencrypt the data. You still won't be able to see the unencrypted information but, it should run on LTspice.
Don't ask me how to do this because I don't use LTspice. If you can't get it to run on LTspice there's a chance that it will work with Micro-cap. I say this because I've used encrypted files from ON semi with Micro-cap.
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H: Are there mux/demux chips that will enable N-signals to be connected in arbitrary configurations?
Would like to be able to configure a small number of signals, in this case 3 signals, A, B, and C, for testing, with arbitrary connections.
Not looking for a CPLD or FPGA, would prefer an IC.
Use case is to be able to things like A->B, A->C for one test, or C->A, C->B for another test, or B->A, B->C for another test.
AI: The component type you're looking for is a crosspoint switch IC.
They connect a number of A-side pins to a number of B-side pins in a programmable arrangement.
Analogue and digital versions exist, you can research them further on the Internet. The site's not for individual part recommendations but this is a technology.
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H: Electronically activated circuit breaker
I want to be able to disconnect the load from a circuit, which may be of variable amperage, possibly up in the hundreds.
I guess what a normal person would do is probably use a contactor of some sort. But then there will be constant consumption in the case of NO, and it will not work with NC because the control unit is part of the load that is to be stopped, so it will just bounce on and off.
It would be best if there was a device such as an automatic circuit breaker that could get triggered with an electronic signal just like it can with that small lever physically. I searched around but I could not find one.
I got a crazy idea of modifying an RCD to add a transistor in the place of the test button, but then remembered that it wouldn't work with DC. I'm just mentioning this to paint you a better picture of what I'm looking for.
Is there such a device?
AI: You already have a circuit breaker, right?
They make various types of actuators for these. They're basically an electromagnet that moves a little lever that flips the breaker down. There are also models that flip the breaker up, just in case. Here's one that will flip a breaker in case of fire. It should be connected to a fire detection system.
(pic source is a random Yandex search)
Here's another (pic source) that will also flip your breaker down.
No matter what country you live in, breakers need to be flipped automatically in case of fire, so you'll probably find a compatible local product.
Note AC circuit breakers don't work on DC. With AC, it's difficult for an arc to sustain itself because current stops flowing 100-120 times per second. However with DC, the breaker needs to actively extinguish the arc, for example by using magnets to bend it or other special measures. That's why an AC circuit breaker or switch rated for 250VAC may have an absurdly low rating of 50VDC. If it is used on a DC circuit (and especially on high voltage DC like photovoltaic) it will catch fire and/or explode on first use.
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H: Calculating a gain of a PWM Modulator with triangle carrier
I'd like to ask for help with calculating a gain of a PWM modulator using a triangle wave.
I know how to calculate a gain in case with a sawtooth carrier with turning-on at the start of cycle.
and
The DC gain equals:
and the AC gain is the same:
Where is an amplitude of the sawtooth wave and these realtions are valid for .
Next, I would like to calculate the gain for the same configuration but with triangle carrier instead of the sawtooth.
And here is my first question. Can I assume that the control signal is much slower than the carrier? I mean that I assume that the control signal has the same level at the beginning of the pulse and at the end? It can simplify a lot calculating the gain cuz it will be symetrical around the peak of carrier.
Could you help me with the calculations? I'm really confused how to start...
AI: I ran a few simulations with different types of artificial ramps to check the transfer function of the pulse-width modulator (PWM) block. First, we start with the naturally sampled modulator, driven by a classical sawtooth, here is with a 2-V peak amplitude:
SIMPLIS is well suited for extracting the transfer function of this switching circuit. The small-signal gain is 0.5 or -6 dB.
The second circuit is a leading-edge modulator (the previous was a trailing edge type) and the attenuation remains the same at 6 dB:
Then I used two triangular waveforms, one starting from 0 to 2 V and another one from -1 to 1 V:
Finally, I have added a low-pass filter and did replace the ac source by a 1-kHz sinewave. The demodulated signal has been plotted with the 4 different ramp voltages and the peak-to-peak values for the 4 resulting output voltages are identical:
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H: TC4420 MOSFET Driver Output Latching Behavior
The TC4420 push-pull MOSFET driver seems to latch its output on if the low input signal isn’t pulled to ground. The signal I am using for the input is purely an on-off signal where the off part of the signal isn’t pulled to ground.
Is there a way I could force the driver to (quickly to minimize switching losses) pull its output low when the input signal is in its off stage? A way that I found to work is by adding a 10k resistor on the input and ground pins, essentially acting as a pull-down resistor for the internal MOSFETs, but I don’t know if this is the right/best way to do it.
TC4420 Diagram:
AI: This device has extensive anti-latch-up circuitry, so will not latch-up.
Since the device input is high impedance, the output can be driven high or low depending on external factors associated with the input. Leakage through your high impedance source or leakage through the protection diodes, could be driving the input high or low depending on the source circuitry.
According to the data sheet, the input signal requires short transition times to prevent double-pulsing of the output.
A resistive pull-down will work as long as the fall time meets the requirements from the data sheet.
I could not find in the data sheet what is meant by "slow rise and fall times", but the switching tests were done with input switching times <10ns (Figure 4.1).
The effective input capacitance is 38pF. To first order, the rise/fall time is about 2 time constants. Using 10ns fall time, the time constant is 5ns. So the pull down value is:
$$
R_{pd}=\frac{\tau}{C_{eff}}=\frac{5ns}{38pF}\approx 132\Omega
$$
Higher resistance values may work, but experimantation is required.
Is there a way I could force the driver to (quickly to minimize switching losses) pull its output low when the input signal is in its off stage?
Using a pull-down resistor will minimize the switching losses of the TC4420, but will increase the losses while there is current through the resistor. Much higher power dissipation.
To achieve both reduced power consumption and meet the data sheet specification, a buffer (like the 74LVC1G17) is required between the high impedance source and the TC4420 input. Then a 10kΩ resistor may be sufficient. Of course it will also consume power but maybe less than the resistor pull-down.
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H: Finding the reflection coefficient for a wave incident from the left into the first transmission line?
I am having a hard time dealing with lumped impedance in problems related to traveling waves.
How can I handle problems where both characteristic impedance and lumped impedance are present, as in the example below?
A series lumped inductor L is inserted into a transmission line section as shown in the picture. The characteristic impedance of the transmission line is Z_0. The line is terminated to the right so that there is no reflection off the end of the line.
Is it correct to solve it as below?
AI: Your case as redrawn:
You think that line section A has load impedance Zin and that's right. Then you wrote the next calculation for the complex reflection factor at the right end of section A (judgement added):
You should see that Zo-Zo=0 and Zo+Zo=2Zo. I must admit that I do not have a slightest idea how you got the result =1.
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H: What is this 2-pin motherboard component and is it broken?
I own a ASUS FX505DT Notebook and the fans stopped spinning so I wanted to check the voltage with a multimeter. I accidentally slipped of one of the terminals and released some "magic smoke" next to the M.2 Slot. I shorted 5v and GND. I am not 100% sure of the origin of the smoke but since both fans are note spinning anymore I kept looking for unusual spots. This component catched my eyesight:
In the red square you can see the damage I assume is broken. My assumption is based on the dot next to the number two, where I guess the magic smoke left from. The Notebook has two fans, so I looked up the other side and found the component labeled R2. I browsed around and found it to be a Schottky Diode but I am unsure what exact model. I guess it might be a MBR0520-TP.
I measured it to be around 150 Ohm, no matter which way I probe it.
AI: It would seem your assumption is correct, (SMT Schottky Barrier Diode MBR0520).
Here is the datasheet.
On page 1 and at the top right of page 3 it shows the marking is R2.
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H: µA723 output Zener diode: why is it as high as 6.2 V?
The µA723 voltage regulator has a 6.2 V Zener diode on its output. I am trying to understand why the Zener voltage is as high as 6.2 V. (LM723 or LM723C are more or less equivalent parts, raising the same question.)
Here is the block diagram from the µA723 datasheet (\$V_z\$ is the Zener voltage, which is specified as 6.2 V later in the datasheet):
The Zener is used in circuits for a negative regulated voltage, or for a general floating regulated voltage. To make things more concrete, here is the negative voltage regulator circuit from the datasheet (\$V_I\$ is some fairly negative voltage):
Without the Zener diode, the regulated output would be only a diode drop (2N5001 base to emitter) above \$V_{CC-}\$. I can see this being a problem for at least the error amplifier, which might need a bit more space between its negative rail (\$V_{CC-}\$) and output. But I don't understand why it needs 6.2 V. In the standard low-voltage positive supply circuit in the datasheet, for example, the output voltage may be as low as 2 V above ground, when \$V_{CC-}\$ is also ground.
There is a very old application note which has a couple of tantalising mentions of the Zener diode, but it doesn't really indicate why 6.2 V is the correct value:
Diode \$D_2\$ used to shift the \$V_{OUT}\$ terminal of the \$\mu\$A723 up to provide sufficient operating voltage to \$Q_{12}\$. \$D_2\$ can be eliminated when using the DIP package by using the \$V_{Z}\$ terminal instead of the \$V_{OUT}\$ terminal. [page 2.10]
The zener provides the necessary level shifting required to maintain biasing of the regulator. (\$\mu\$A723's in the metal can package do not have a \$V_{zener}\$ output. When using these devices, it would be necessary to add an external 6.2 volt zener between \$V_{out}\$ and the switch transistors). [page 4.6]
I know this is an old part and newer, shinier options are available. Nevertheless, I'm trying to understand this one.
AI: Because of physics. Turns out that around 6-7 V is the voltage for which the temperature coefficient of Zener diodes is minimized. Much lower voltage Zener diodes also operate on a different principle and have very soft 'knees', so the regulation as well as the temperature coefficient is inferior.
Discrete ~6.2 V Zener references were once popular, for example, the 1N829. They're still available, but not inexpensive.
Modern circuits tend to use bandgap references, which require lower minimum operating voltage but are noisier and perhaps not as stable. They're very cheap and good enough for many applications. There are also some references that operate on the principle of a floating gate with a charge applied at the factory.
The best available Zener references (and some of the finest voltage references available, period) are 'buried' ovenized Zener diodes in the 6-7 V range. The crystal-looking cans in the image are ultra-precision resistors.
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H: Audio Power Amplifier Layout clarifications
I am using LM4670SD/NOPB in my design. The IC is working at 5 V supply.
This IC requires an 8 Ω speaker.
My first question is,
In that case do the lines Vo1 and Vo2 needs a differential impedance of 8 Ω (each line 4 Ω Single ended).
May I know my assumption is correct or not.
My second question about the current carrying capacity of Vo1 and Vo2 lines. In the datasheet page no 4 you can see the power specification as given below.
Considering the maximum power as 3 W from the 5 V rail, I calculated the current carrying capacity of Vo1 and Vo2 as 0.6 A.
May I know is this correct?
AI: No. Differential impedance is unimportant at audio frequency. Actually this is switching so there will likely be signal at gigher frequencies, maybe 100kHz or so, but still - you don't need to worry about differential impedance until dealing with signals at least in the MHz range at normal track lengths.
If you are running 5V into an 8 ohm load, the absolute maximum current possible is 5/8 or 0.625A. This would only really happen in a fault condition, the real working RMS current under normal operation would be rather less, but if the circuit failed you don't want the board burning so I would personally design for something like 1A minimum. It costs nothing to run thick tracks.
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H: Using two supply rails (on supply and output pins) with 74HC595
I have a 74HC595 connected to an STM32 to drive a bunch of LEDs using fewer GPIO pins.
I want to reduce the current flowing through the 3.3V regulator IC which supplies the controller, and want the LEDs to be on the 5V power rail.
Can connecting 5V supply to the SR output pins lead to any complications, considering that the SR is powered from the 3.3V supply rail? The datasheet mentions that "input and output voltage ratings may be exceeded if the input and output current ratings are observed."
The current ratings can be observed by using appropriate current limiting resistors. Is this enough to get the job done?
I can't provide 5V to the IC supply, cause the controller uses 3.3V logic levels, and 3.3V is not guaranteed to be interpreted as logic HIGH.
EDIT: The current carrying resistor values were from my design which used 3.3V supply, and I hadn't updated it in the schematic.
AI: That's not a good way of doing it.
This is even said in the data sheet; outputs should not be pulled above VCC, and 70mA total current should not be exceeded, and you are doing both.
If 5V supply powers on first, it will push current through LEDs and into the IC outputs which pushes current to the 3.3V node.
And as an output, the safe range for voltage on output is up to the 3.3V supply.
The assumption is that LEDs drop 5V down but they might not drop the voltage down to 3.3V, as that would be 1.7V over the LED, and LEDs will require at least some amount of current to drop 1.7V. So the LEDs could still be on even if 74HC595 output is high.
Assuming the LEDs drop 2V, the total current adds up to more than 70mA. The IC has an absolute maximum rating of 70mA, so first of all, the chip does not need to work because it is being used outside nominal operating conditions, and second, the chip is being used beyond absolute maximum ratings so it can cause permanent damage to the chip.
And you didn't ask but you could simply switch to a 74HCT595 which allows 3.3V IO signals while being powered at 5V.
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H: Isolated flybacks in series to generate high-voltage
I'm considering placing isolated flyback converters secondaries in series such as the image below. I want to drive the transformers individually using synced clocks (such each transformer has its own IC driver and opto-feedback) such that across each transformer is 50 V, and they are in series up to 600 V (12 converters total). I want to locally float circuits across each 50 V step and draw around 50 mA. The load across each 50 V rail will be the same as the circuits are duplicates. All of the primary drives would be fed off the same DC rail. I think a better solution would be by having a transformer with a single primary and 12 secondaries but I don't have the knowledge/capability to design such a thing so I am looking at this design with off-the-shelf parts.
Would this solution be feasible? I am looking at using transformers with 100 V secondary voltage rating and 2 kV+ pri-sec rating to provide sufficient isolation.
AI: My general advice is to never connect anything but resistors in series.
If you do need 12 individual outputs, spanning from 0 to 600 V DC, there are some benefits of stacking the outputs of 12 converters in series:
Cross regulation
Downsides would include:
DC stress on the topmost transformers
Dynamic behavior at startup and faults
Your other option would be to make just one converter with 12 outputs, at which point you have more control over the DC stress in the transformer. 600 V isn't that high, but your average enamel wire may only be rated for 300 V working voltage. With tape or insulated wire, you could have the last windings have ample voltage rating. Downside would be cross regulation with just one feedback. Without for example post regulation in the form of an LDO, you're down to how well the secondaries in your transformer are coupled to each other and how much load imbalance you have.
Assuming the transformer isn't a limitation, you need to consider fault cases. The foremost I can think of is either if one of the converters would stop operating by some fault or just an overload from whatever is connected downstream of it. If there are any loads from for example +600 V to ground (across all converters), depending on how much it behaves like an ideal current sink and how much inductance you have, will try to force the converter not supplying any current to go negative. The situation is identical to a series battery pack where one cell is depleted before the others. If the load across them keeps pulling current, the depleted cell will eventually go negative voltage. BMSes are used to prevent this very situation.
I would recommend you to put a Schottky diode across each output to prevent it from going too negative to damage anything (capacitors, feedback) and ideally, a power good signal from each converter, probably via optocoupler down to some central MCU or similar to shut down the other converters if this happens. A BMS of sorts.
The schematic below is very simplified. As it stands, it won't allow the converters to boot. You need to inhibit the power good function for some time until they are expected to be up and running. It's just to give you an idea on how to catch problems. D4 and D14 are Schottky diodes. It may be possible to hook into the existing feedback loops and determine if a converter has lost regulation, but it's the same startup behavior you need to catch as they all start from zero yet there is nothing wrong.
simulate this circuit – Schematic created using CircuitLab
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H: Connecting another Arduino to RX pin, bypasses first Arduino.,
I've got two Arduinos. One connected via USB to a PC, then another with its RX connected to the RX of the first Arduino. Both have a common ground through through the USB and another wire connecting the two grounds together.
Basically I want to send serial via one USB connection, but have two Arduinos receive the the same message.
I thought I could connect both RX pins together, meaning the FTDI chip sends the data to both Arduinos.
But when I connect the two RX together, only the second Arduino gets the message, like it absorbs the signal.
Question: Is there a simple way to get one usb cable to talk to 2 Arduinos without modifying the firmware of the first Arduino?
Edit: Both are Arduino UNO
AI: If you look at the circuit diagram of the Uno and strip out everything except the portion connecting the serial output of U3 (another ATMega, actually, not a FTDI chip) to the RXD of the CPU ZIC1, you have the circuit shown below. With your link between the two RXD lines.
You see that you have two outputs (PD3 of the two U3s) joined by 2K resistance; you can't have two outputs joined together. They then feed the two PD0 inputs (aka RXD).
Fundamentally, you have to avoid the two-outputs-joined situation.
Your choices, without changing the firmware of Arduino A:
Disconnect: Cut the track on Arduino B so its U3-PD3 isn't connected to anything (which means you won't be able to program it through the bootloader, only the ISP socket)
Avoid Use software serial on Arduino B (ie, a different pin, not PD0), which requires changing the software of B, and would have a limit on the baud rate.
Not an Output Hold Arduino B's U3 in reset, which will make all its outputs high-impedance. You could do this by holding RESET2 to GND, such as by shorting pins 5 and 6 of ISP1, perhaps with a removable connector.
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H: Understanding max output voltage of a solar cell data sheet
For the following solar cell datasheet values, what would be the max output voltage of the solar cell?
Would it be the open circuit voltage typical or the max operating one? What exactly is the open circuit voltage?
Referenced from AM-8701 Datasheet(PDF) - Sanyo Semicon Device (alldatasheet.com)
AI: Would it be the open circuit voltage typical or the max operating one?
Open circuit voltage is the voltage the solar cell will output at the conditions provided.
The table you have there shows that the Open circuit voltage is 6V typ. (on average) at a luminance of 50,000 Lx (Lux)
There may be a graph on that datasheet that provides the change in voltage in relation to the change in light intensity.
What exactly is the open circuit voltage
Open circuit voltage is the voltage between the terminals of your solar cell with no load attached.
Short circuit current is the current through a wire when the two terminals are shorted. A shorted connection ideally has a voltage of zero, while an open connection ideally has a current of zero.
what would be the max output voltage of the solar cell
The voltage will depend on the luminance on the area of the photovoltaics inside and maximum output voltage will depend on temperature (colder environments increase the maximum voltage) of the solar cell. There is no maximum listed in the table you provided.
The Maximum Output section on the table provided shows your maximum wattage at a specific luminance. With solar cells, there is no "maximum" per say, it comes down to how many photons you can get to hit the photovoltaics inside.
It is best to take some measurements in the primary environment your project will be in and work with those values.
To further read this table, some key definitions:
AM-1.5 is your Air Mass rating (wiki here, scroll down some)
100mW/cm^2 is your intensity (wiki here)
All measurements given on a datasheet will have a specific condition they were measured under. You can expect different values if measured under different conditions.
Update: Look at Figure 1 of this paper (doi 10.1016). It has information on the relationship between illumination intensity, short circuit current, and open circuit voltage. In the paper you will see that short circuit voltage increases logarithmically, while short circuit current increases linearly. It's an interesting relationship to say the least!
Note: for future questions include sources for images such as the datasheet to help us answer your questions on the EE.SE.
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H: How to truncate an expression bit width in Verilog in 2023?
I have the same question as here:
How to truncate an expression bit width in Verilog?
But I was hoping that in 2023, there would be more interesting answers that in 2013!
My specific use-case:
localparam logic [31:0] BAR0_OFFSET_MASK = {32{1'b1}} << (10);
Some tools complains that LHS is 32 whereas RHS is 42, and I would like to select part of the result of the shift operation without creating a temporary variable or a function.
AI: Tools that complain that the RHS of the assignment width is 42 bits are incorrect. The width of a shift operation is determined by the width of its left operand.
Regardless, SystemVerilog added a select in a concatenation
localparam logic [31:0] BAR0_OFFSET_MASK = { {32{1'b1}} << (10) }[31:0];
You could also use casts
localparam logic [31:0] BAR0_OFFSET_MASK = 32'( 32'('1) << (10)) ;
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H: Switch to handle two inputs and switch between two sets of two outputs (guitar amp send and return switch)
I am looking to build a simple box, for fun, to switch the send and return signals from a guitar amplifier effects loop between two different amplifiers, depending on which amp I am using at the time.
The box would have two 1/4 inch TS input jacks (one for send one for return; these would be connected to the guitar pedals).
It would then have four total output jacks (send and return to amp A, send and return for amp B; these would be connected to the amplifiers' effects loops).
The external connections would be made with standard 1/4 inch instrument cables.
Hopefully that all makes sense - I am obviously new to this.
I would like to be able to have a single switch that would route the input signals to either output A or output B.
What kind of switch can manage this? Or do I need to do something with multiple switches to turn each output on/off?
Any tips appreciated!
AI: You will need a double pole (switch both signal and the return), double throw (1 input to 2 outputs) switch. Usually, These are shortened to DPDT.
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H: Cannot isolate Raspberry Pi from the other circuit using optocoupler. Why not?
I'm sending data (Tx1-D) and command (Tx2-C) communication from Raspberry Pi 3 at baud rate 115200. I tried to isolate the RPi from the other circuits by using optocoupler as in the diagram but it doesn't work. I tried different values for R2, R3, R4 and R5 (ranges from 200 ohm to 100k) but all failed. Why?
Note: The whole system is common grounded. Vcc on the right hand side is the power supply of the RPi and the Vcc on the left hand side is the power supply of the rest of the circuit (both 5VDC.)
Tx1 and Tx2 is the input data for two serial bus drivers (MAX485).
Without isolation (direct wiring for data and command, and using one power supply for both RPi and the circuit), the system works fine.
AI: At 115200 baud you have about 8us low and 8us high. From a datasheet:
You would be better off to use a digital output optoisolator such as 6N137 if you really need that high a baud rate.
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H: FTDI FT234XD not recognized
I designed a PCB that incorporates FT234XD (Datasheet) USB-UART converter but no matter what I tried, I couldn't get it working. Host computers does not even react let alone give an error so it's probably not a driver issue. The IC is connected to STM32F030 MCU.
What I tried so far, removing DM,DP 47pF caps, shorting 22Ω resistors, shorting filter inductor, reversing DP and DM, testing several Type-B cables as wells as direct header connection.
I see 3.3V and 2.5V on RX/TX pins, DP is pulled up to 3.3V. So IC regulator is working. I'm using the IC in bus powered configuration. My filter inductor is Sunlord GZ2012D601TF
AI: The diodes are completely unsuitable for high speed data lines such as 12Mbps USB. They are also unidirectional so they don't protect from negative ESD.
The diodes seem to have capacitance beyond 1000pF. If it was only 1000pF, it would form an RC filter with the 27 ohm resistors that has a cut-off below 6 MHz, so a 12 Mbps signal has no chance of working.
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H: What happens if an MCU boosts its own supply voltage while running?
I'm designing a low-power, battery-powered sensor node using an ATtiny1626 microcontroller (1.8V~5.5V supply with low clock speed), powered directly from 2x AAA batteries (various chemistry, let's say 2V up to 3V over usable life).
For providing supply for other parts of circuit, a hi-efficiency boost converter XC9141B/42B is used. The chosen version with B suffix, bypasses the input voltage to the VOUT pin when the CE pin is low and the VOUT would be more or less equal to VBATT in that case. When the CE goes up, VOUT also goes up from VBATT to 3.3V.
In order to get rid of level translations, I thought about supplying the MCU from the VOUT pin itself; so the MCU (still powered from pass-through capability) holds the supply voltage at VBATT and when needed, turns the boost converter on, and the supply of MCU and the other part of circuit jumps to 3.3V.
The other parts have their own sleep modes, so it's not a problem if they still get powered by VBATT or when the voltage jumps between values.
The idea is to boost voltage when the battery level is low and unable to power other parts sufficiently, and maybe for better TX power of LoRA (SX1278 module.
What kind of problems would arise from this sudden switch of voltage for the MCU itself?
AI: I've done that with an ATtiny84 with no problems.
When in sleep mode parts of the circuit (such as the analog section) are powered down and the supply voltage is dropped from 5V to 1.8V with only the MCU running.
When the processor periodically comes out of sleep from a timer interrupt it sets the supply to 5V, enables power to the analog sections then waits an appropriate time for the supply to stabilize before using the analog section.
This is in a device powered from solar photovoltaic cells that charge a single NiMH cell to power the circuitry through a boost converter controllable to output either 1.8V or 5V. A MCU GPIO controls the output voltage. Energy is very limited although instantaneous power is not so much as the battery can provide that power.
You need to watch out for sneak paths in the sleep state. For example the I/O pins often have ESD diodes to VCC. You also may need to put the MCU GPIOs into tri-state mode, high or low as needed.
If the voltage is too low for the peripherals in the sleep state they may need to be power-switched to avoid operating out of guaranteed operating range. If you power down a peripheral the MCU GPIOs to that peripheral will probably need to be put to low.
Buses like I2C can be tricky or there may be leakage into the peripheral or you may need to power-switch the pull-up resistors.
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H: Unity Gain Buffer Output Impedance
First time here. I'm not an engineer so please pardon my lack of technical expertise. Thanks in advance for your help!
Here's is the circuit in question:
I've been told that R5 (10K) sets the output impedance of the buffer. However, there are two other resistors connected to ground when the buffer is connected to a tube amplifier.
Question 1: Wouldn't the output impedance be set by the 25K pot and the 10K R5 in parallel (7.15K)?
Question 2: Would it be a better design to put R5 before C3 to set the output impedance at 10K?
AI: I've been told that R5 (10K) sets the output impedance of the buffer.
The only indication in your schematic of where the buffer output is here: -
And, that node could be described as the output of the buffer hence, R5 (10 kΩ) plays a role but, the impedance at that node is mainly determined by R4 (100 Ω) and C3 (2.2 μF).
Question 1: Wouldn't the output impedance be set by the 25K pot and
the 10K R5 in parallel (7.15K)?
Your question seems to assume that the output node of the buffer is at some other point than the node marked "OUT" so, I have to disagree.
Question 2: Would it be a better design to put R5 before C3 to set the
output impedance at 10K?
R5 is there to stop a DC voltage accumulating on the "OUT" node when nothing is connected hence it must be placed where it is.
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H: Circuit that outputs signal A when AC sine is positive and signal B when AC sine is negative
I need help designing a circuit that outputs Signal A high when AC sine wave is positive and Signal B high when the sine wave is negative. It's part of a larger project that cycles power in a transformer.
I have the below circuit working but it's not accurate enough. Signal A and B don't start/stop exactly at the zero-cross of the input sine wave. Any help appreciated!
AI: Op-amp precision rectifiers are the likely turn-to solution. Here's an example circuit: -
When the input is positive, the op-amp is prevented from creating an inverted (negative) output by D1 but, when the input is negative, the natural situation is for a positive output to be produced and, of course, D1 allows this. D2 prevents output saturation of the op-amp when the input is positive i.e. keeps it in the linear region.
The circuit produces a positive half wave rectified output.
If the diodes are reversed then you get a half-wave rectified output when the input is positive and 0 volts when the input is negative. You can then add another inverting stage after this so that you get the polarity you require.
So, two precision op-amp circuits are needed and both are fed from \$V_{IN}\$. If you need to have a decent square wave output, add comparators to both output channels.
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H: MAX7221 with multiple LEDs per point
I am using a MAX7219/MAX7221 chip in a keyboard design in order to light up the individual keys. The keyboard is going to have exactly 64 keys so with the 8x8 matrix the chip handles I will be able to put one led under every key.
However, I think the space bar is too wide to be lit by a single led, I think 3 would be more appropriate but then how can I connect 3 leds to the same matrix point? Is it enough to put them in series? Do I need some helper circuit? Of course a key requirement is that these 3 leds are as bright as the other ones.
Thanks in advance!
AI: You can't put 3 in series, the voltage drop will be too high. If you put 3 in parallel, even if you solve the voltage matching issue, you will only get 1/3 the current in each.
The left circuit is how the IC is intended to be used, there is one LED at each SEG and DIG intersection.
The right circuit is a potential solution. Unfortunately, when you use a non-standard connection, the parameters you need are not always specified. It is difficult to know how predictable the current source will be in this circuit. Without a sufficient load, it won't be able to put out the specified current. It should put out a voltage near 5V as it attempts to put out the specified current, but you may need to run some experiments.
If you are only building one, an experiment would be sufficient. If you are designing a product, this would be risky. They could change the design while still meeting the datasheet; but affecting your non-standard design.
You will need to select the resistor value to match the current in the other LEDs.
simulate this circuit – Schematic created using CircuitLab
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H: How to write the equation for the input side of a JFET?
I have been reading about the voltage gain of JFET, but I am unable to understand how to write the equation for the input side. Can somebody explain the method to write the equation for the input side?
The text has provided \$V_i=V_{gs}+V_{Rs}\$ but I do not understand how this equation came up.
AI: I do not understand how this equation came up
It's as easy as this: what ever voltage you have at the input with respect to 0 volts (\$V_i\$) must equal the voltage between gate and source (\$V_{GS}\$) plus the voltage between source and 0 volts (the voltage across \$R_S\$).
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H: BJT Amplifier simulated gain is only around 80% of calculated gain. Why is this and how to improve calculation vs simulation accuracy?
I'm trying to design a CE BJT amplifier in Multisim with 100mVp 1kHz input, and target gain of around -208.8. Starting from my choice of Vcc = 50V and Ic(DC) = 15mA, here is the design I came up with:
The Ic(DC) during simulation looked close enough to my expected value:
So I calculated gain using -Rc/(Re'+Rsw) = -1613/(1.725+6) = -208.8, everything was looking reasonable.
Then I simulated the circuit with virtually no load (1Tohm load) as seen in the first screenshot. For 200mVpk-pk I'm expecting 41.76Vpk-pk, however the output is only 42.03 - 8.31 = 33.72Vpk-pk, ~20% drop from expected output. I'm quite certain the output is not clipping, but what is causing this drop, and is it possible to improve the gain accuracy as close to 100% as possible? I've looked around the Internet and found no similar situations so I'm perplexed and don't know where to start looking for design issues.
I'm very, very new to circuit design and would appreciate a detailed explanation.
AI: When you try and make a single stage BJT have a gain that is realistically pushing the limits, you have to factor in the miller capacitance feedback effect due to collector-base capacitance. It may only be a few picofarads but, at unfeasibly large anticipated gains, it will bite you.
BJTs are so cheap that it makes no financial sense to use a single transistor to provide the whole gain. As a rule of thumb, I stick with a voltage gain per stage of no-more than 50.
how to improve simulation accuracy?
The simulation accuracy is far-far better than your hand calculations for gain.
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H: What is the direct coupling problem which differential amplifiers help avert?
The discussion below comes from Chapter 3.5 of Analysis and Design of Analog Integrated Circuits by Gray, Hurst, Meyer, and Lewis.
In particular, I do not follow what is meant when they write
This property allows direct coupling of cascaded stages without offsets.
I understand the property, but I do not understand why the property allows direct coupling of consecutive stages. Perhaps someone can provide an example that might show how a regular (?) stage does not allow for direct coupling but a differential stage does?
AI: Because a decently designed differential amplifier will have very little (or near-zero) common-mode gain (irrespective of a high differential gain), you can attach the differential outputs from one stage to another differential stage's inputs without great worries of the 2nd stage transistors becoming saturated.
This can only happen with differential stages because the common-mode gain is near-zero. A non-differential input has only gain and cannot benefit from any common-mode cancellation.
For instance, imagine a single-ended amplifier with a gain of ten having a nominal output voltage of half the supply rails when the input is 0 volts. You could not connect this directly to another similar stage because that extra stage wants to see 0 volts as a neutral input but, the first stage is supplying it with 6 volts. In other words it would hit the end-stops.
On the other hand you could engineer a single-ended input that produced 0 volts out with 0 volts in then, you could cascade multiple stages but, you then introduce a problem hidden in the first example; your common 0 volt line is likely subject to all sorts of noise currents from other parts of the circuit and, the final result would be a noisy output.
Not so with differential (and impedance balanced) circuits; using differential signal lines means no shared noise with other system components and, any noise that does come along (such as EMI) would affect both simultaneously and, because the CM gain is near-zero, that noise would hardly influence the output differential voltage.
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H: I2C BME688 Read Request Sent, but no data received
As the title suggests, im interfacing with the BME688 using I2C. The signal I captured using my logic analyzer is shown below. The slave address is 0x76 and register address im trying to read is 0xD0. The slave should return 0x61 but no data is returned by the slave whatsoever.
The master code is running on one of the AM335X Programmable Real-Time Units (PRUs) on a Beaglebone Black. The code is written in PASM and quite long, though the sections of code that matter are linked below:
.macro I2C_WAIT_BY_STOP
.mparam reg
_CHECK:
LBCO reg.w0, C_I2C1, I2C_CON, 2
QBBS _CHECK, reg.t1
.endm
.macro I2C_READ_INIT
.mparam reg, busaddr, regaddr
//slave address
MOV reg.w0, busaddr
SBCO reg.w0, C_I2C1, I2C_SA, 2
//number of bytes to send
MOV reg.b0, 1
SBCO reg.b0, C_I2C1, I2C_CNT, 1
//fill the FIFO
MOV reg, regaddr
SBCO reg.b0, C_I2C1, I2C_DATA, 1
_I2C1_WAIT_BUS_FREE:
LBCO reg, C_I2C1, I2C_STAT_RAW, 4
QBBS _I2C1_WAIT_BUS_FREE, reg.t12
MOV reg.w0, I2C_CMD_ENABLE | I2C_CMD_TX | I2C_CMD_START | I2C_CMD_MST | I2C_CMD_STOP
SBCO reg.w0, C_I2C1, I2C_CON, 2
I2C_WAIT_BY_STOP reg
.endm
Here I2C_XX are bitmasks or register offsets and C_I2C1 is the I2C1 control register. The Techinal Reference Manual can be found here with I2C registers starting from Page 4601. The linked code writes the slave address to the appropriate register, followed by the number of bytes to send (just 1, the register address). Then the register address is added to the FIFO. When the bus is free, the control register is set with the appropriate bits. These bits enable the module, go into transmission mode, set a start condition, set the module as master, and set a stop condition. Then I2C_WAIT_BY_STOP loops until a new stop condition is received.
What am I doing wrong here?
EDIT:
I added the I2C read diagram of the BME688 . I was of the understanding that after sending the slave addr + reg addr the device should respond with the register value in the form of a data packet?
AI: Okay, I was just being silly. I forgot to set the I2C module in receiver mode after transmitting the message. The updated PASM code is:
.macro I2C_WAIT_BY_STOP
.mparam reg
_CHECK:
LBCO reg.w0, C_I2C1, I2C_CON, 2
QBBS _CHECK, reg.t1
.endm
.macro I2C_READ_INIT
.mparam reg, busaddr, regaddr
//slave address
MOV reg.w0, busaddr
SBCO reg.w0, C_I2C1, I2C_SA, 2
//number of bytes to send
MOV reg.b0, 1
SBCO reg.b0, C_I2C1, I2C_CNT, 1
//fill the FIFO
MOV reg, regaddr
SBCO reg.b0, C_I2C1, I2C_DATA, 1
_I2C1_WAIT_BUS_FREE:
LBCO reg, C_I2C1, I2C_STAT_RAW, 4
QBBS _I2C1_WAIT_BUS_FREE, reg.t12
MOV reg.w0, I2C_CMD_ENABLE | I2C_CMD_TX | I2C_CMD_START | I2C_CMD_MST | I2C_CMD_STOP
SBCO reg.w0, C_I2C1, I2C_CON, 2
I2C_WAIT_BY_STOP reg
// Put device in receiver mode
MOV reg.w0, I2C_CMD_ENABLE | I2C_CMD_RX | I2C_CMD_START | I2C_CMD_MST | I2C_CMD_STOP
SBCO reg.w0, C_I2C1, I2C_CON, 2
I2C_WAIT_BY_STOP reg
.endm
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H: Multisim simulation insight
I want to simulate an AC circuit in multisim. I would like hints or articles on how to simulate complex-valued impedance, for example this circuit:
I don't have an option in multisim 12.0 , to have a complex-value for the inductance or capacitor, how can i do that?
also for the analysis of this circuit to find \$V_o \$ im going with the superposition theorem:
first im turning off the voltage-dependent source replacing it with a short-circuit, turining into this circuit :
so we have in the upper-most left mesh by KVL :
\$ -4V + \frac{V_A - V_B}{1j \Omega} + \frac{V_B - V_c}{1 \Omega} = 0 \$
I'm very confused on how to extract the two more equations to solve for to find \$V_o\$ for this first superposition.
AI: If "j * omega" ... is an inductance ...
And 4*V is a "step generator" ...
Then I could write these equations: Made with Maple ...
i1 (left-high loop), i2 (left low loop), i3 (right loop) are the internal currents loops.
Confirmed with simulator microcap v12.
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H: How do I split and isolate a digital signal?
I am working on a circuit that needs to observe when VAC is at zero cross. I have a photostransistor whose anode and cathode are connected to VAC line and neutral. I've connected 3.3VDC to the collector side of the transistor. My logic chip watches the emitter side of the phototransistor with an internal pulldown GPIO. When the emitter reads a digital false, I know VAC is briefly at zero cross.
I want to use the output from the emitter to power a VAC status indicator LED, but I don't want to interfere with the zero cross monitor (since the signal is being pulled down). Is there a device that is commonly used to split a signal into two isolated signals? So the GPIO PD doesn't interfere with the LED.
AI: It is unclear why you you ask about how to split a signal, maybe because you think splitting a signal is a solution to your original problem, about pull-down interfering a LED, but you don't need to split the signal to begin with because pull-down isn't a problem.
The pull down is in the order of 50k, and it pulls down. A 50k pull-down won't interfere with the LED.
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H: Analogue Read in ESP8266 WEMOS D1 MINI is fluctuating
I am trying to read the current consumption of a light bulb (160 W) using a current transformer (5A/5mA) connected to the ESP8266 WEMOS D1 MINI analog pin.
I have put a 240 ohms burden resistor in parallel with the pins of the current transformer. I used this formula to get the resistor: Burden Resistor (ohms) = (AREF * CT TURNS) / (2√2 * max primary current)
I then used a voltage divider to get the mid-point voltage, I inputted the voltage divider to the 3.3V source of the WEMOS. A 10uF capacitor is used at the pin of the current transformer and the ground.
You can check below my installations:
Note that the schematic is from this link. Thanks to it, I was able to install my circuit.
I wrote a very simple program to display the result in volts, but what is being displayed when turning on the light bulb is very confusing. The result is fluctuating from 2.1 ish to 1.4 ish (1.65 being 0V which means the light bulb is off, and 2.10 being the light bulb is on.) 2.1 volts is fair enough because if 3.3 volts is displayed, it means that there is 5A passing, and the light bulb is 160 watts meaning approx. 0.7A, so it means that 2.1 volts should be displayed. You can also check below the printed result.
What does this fluctuation mean?
The below program is added after some hints given by answers.
void setup() {
Serial.begin(9600);
}
void loop() {
float mean;
float sensorValue[21];
for (int i = 0; i <= 21; i++) {
sensorValue[i] = ((analogRead(A0)) * ((3.3) / (1023)));
mean += sensorValue[i];
delay(1); //wait 1ms
}
mean = mean / 21;
float sum;
for (int i = 0; i <= 21; i++) {
sum += pow((sensorValue[i] - mean), 2);
}
sum = sqrt(sum);
delay(500);
Serial.printf("%.10f", sum);
Serial.println(" ");
}
AI: Take under interrupt (every 1 ms for 50 Hz mains) 21 samples.
Calculate the "mean" measure.
When done, you can calculate the RMS value of the current.
As in this file for ATmega328N under Arduino. Don't know if it can work for ESP8266 (seems no).
Compiled with version Arduino 1.8.19. Note that some comments are in french.
Take 21 samples under interrupt (every 1ms, change this value if the main is 60 Hz)
verify that samples are on a "sinusoid" ...
verify that extreme samples (the 1st and the 21st are the "same" value)
If they are not on a sinusoid, then the current is distorded.
Verify also that samples are not just as "saturated" (high or low)
You should then change the "sensitivity" ... change the "burden" resistor ( must be lower).
calculate the mean of all samples
calculate the distance between every sample and "mean"
square these distances
Sum the distances
square root of the sum
calibrate this value with the current measured with an RMS ammeter
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H: High pass filter after TIA is not behaving as expected in LTspice
I have the following schematics to amplify a current signal modulated at 10 kHz. The first stage is a transimpedance amplifier with a -3dB bandwidth of 72 kHz. The second stage is a high pass filter with a -3dB bandwidth of 0.13 Hz. The purpose of the high pass filter is to eliminate a possible unwanted offset in the input signal.
However, when I simulate this in LTspice, I obtain an unexpected behavior, as shown in the following image:
The green plot here is the signal before the high pass filter stage, which in this case is centered at zero, as expected. However, the blue plot, which is the voltage after the high pass filter, acquires a negative offset. Why does this happen? Is there an intuitive explanation on why this is the case?
Note: U28 is OPA828 and U31 is NE5532
AI: The NE5532 isn't good for these types of low-offset output voltage applications. There are several pointers in data data sheet: -
Input offset voltage
At your maximum gain (set by R169) of about 20, a typical input offset voltage of 0.5 mV will produce an output offset error of 10 mV. Far, far worse if the offset is not close to typical. I mean it could be as high as 4 mV at ambient temperature.
Input bias current
Input bias current will flow into R138 and typically, will produce an effective input offset voltage of 2 volts. This gets amplified and too bad, the op-amp output hits the end stops.
Input offset current
The data sheet gives you this figure to help you decide the final error due to bias currents. Input bias currents can be largely cancelled in many BJT op-amp circuits by using matching resistors in both inputs but, offset current tells you how far this can work. With a typical offset current of 10 nA and a resistor of 1 MΩ (R138), the effective error voltage at the input could still be 10 mV and, with your gain at a max level of 20, the output offset would be 200 mV.
What you should consider doing about offset/bias currents
Maybe try using a capacitor in series with R134; this makes the DC gain of the final stage unity. Of course, the capacitor has to be big enough so as not to reduce gains at low frequencies. If 20 Hz is your lower range you would need a capacitor of 2.2 μF in series with R134.
Recommended power supply minimal value
You are running it at +/- 4.5 volts but, the minimum recommended supply is +/- 5 volts: -
How to determine what's a suitable op-amp
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H: Is it good to equalize input impedances in cascade active opamp filters?
In my design, I designed a first 2nd order high pass filter with a Sallen key cut-off frequency of 0.2Hz and an input impedance of 250kohm. Then, I designed a second-order Multiple-Feedback low pass filter with a cut-off frequency of 100 khz and its input impedance is 15kohm. Thus, I have a bandpass filter. I wonder if it is good to equalize the input impedance of both filters? What effects can different filter input impedances have?
AI: I wonder if it is good to equalize the input impedance of both
filters? What effects can different filter input impedances have?
For the frequencies you are talking about (100 kHz maximum), impedance matching (if that's what you mean) is pointless. You only impedance match when you are trying to: -
Maximize power transfer (you aren't)
Avoid disruptive signal reflections (you won't be at 100 kHz or probably even up to 10 MHz)
If you mean "make equal" the input impedances for both stages, that also doesn't matter because both those circuits are unrelated to each other in that respect.
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H: From the perspective of a progressive wave, what is lumped impedance?
This question asks about the meaning of lumped impedance in traveling wave theory.
Should lumped impedance be viewed as something like a point charge, a point mass, or a direct delta function?
When a traveling wave enters the interface between Z_0 and Z_1, the traveling wave knows the characteristic impedance Z_2 behind the lumped impedance
Z_1.
How can a traveling wave know in advance the existence of Z_2?
How should lumped impedance be viewed in the analysis of traveling waves?
Is lumped impedance lengthless?
Even if it is a very short length, it will have a non-zero length.
If so, isn't it the same as characteristic impedance?
Therefore, the traveling wave cannot know in advance Z_2 behind Z_1, right?
AI: Is lumped impedance lengthless?
Yes it is regarded as length-less. This means it doesn't behave like a transmission line. If its length is non zero then it wouldn't be a lumped impedance but, would be regarded as a transmission line.
But, the trick is knowing when to regard a real non-ideal component as an ideal lumped component and, not a transmission line.
Should lumped impedance be viewed as something like a point charge, a
point mass, or a direct delta function?
You regard it as an ideal component that has no transmission-line properties i.e. it has zero dimensions and cannot create reflections.
Even if it is a very short length, it will have a non-zero length
You are confusing a lumped impedance with a non-ideal lumped impedance. With a non-ideal lumped impedance you may choose to regard it as a transmission line at higher frequencies.
How can a traveling wave know in advance the existence of Z_2?
Because the lumped impedance introduces no transmission-line delays.
How should lumped impedance be viewed in the analysis of traveling
waves?
By definition, it must be regarded as a zero-dimensioned ideal component thus, introducing no transmission-line delays.
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H: Why is core resistance modeled to be parallel to the primary winding of ideal part of a real transformer?
When a real transformer is modeled to a simpler circuit, it is shown that the core resistance or a resistance model which basically describes eddy current and hysteresis loss is in parallel with the ideal primary winding part. Why is that resistance considered in parallel instead of series? I know that the hysteresis loss and eddy current depends on the flux of the primary winding but what does it have to do with the parallel orientation?
AI: Why is that resistance considered in parallel instead of series? I
know that the hysteresis loss and eddy current depends on the flux of
the primary winding but what does it have to do with the parallel
orientation?
Both eddy currents and core flux are proportional to the applied voltage and, are \$\text{not-at-all}^1\$ dependent on the secondary load currents or the primary referred secondary load currents hence, there is absolutely no alternative other than to model them as parallel components (so that they get worse with a bigger primary voltage and, are largely unaffected by primary or secondary load currents).
\$\text{not-at-all}^1\$ is a little to convenient to say when it comes to core flux and associated components. In fact, as the load current increases, the voltage appearing on the components \$R_C\$ and \$L_M\$ slightly reduces and, this slightly alleviates the problems associated with core saturation and eddy currents. Equivalent circuit from my basic website: -
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H: Why does MD13S JST have an NC pin?
This is about the 4-pin JST connector that links the driver to a microcontroller. It seems that the only important pins are GND, PWM (speed), and DIR (direction). Clearly, when Cytron has designed the driver from the ground up, why would they add an NC (which I assume is "no connect") to the driver (instead of using a 3-pin JST)? Isn't it a waste?
I am using one of these motor drivers for a college project. The people worked on it before me had kindly soldered a 3-pin JST header to it, so I never gave this much thought before.
Motor driver product page, for reference: https://www.cytron.io/c-motor-driver/p-13amp-6v-30v-dc-motor-driver
AI: They claim it is "Grove compatible", which refers to a hobbyist ecosystem using connectors with pins 3 and 4 devoted to Vcc and GND respectively. The English is a bit painful but:
**Interface of Grove modules**
You may notice that there're 4 color of the Grove cable.
pin 1 - Yellow (for example, SCL on I2C Grove Connectors)
pin 2 - White (for example, SDA on I2C Grove Connectors)
pin 3 - Red - VCC on all Grove Connectors
pin 4 - Black - GND on all Grove Connectors
That allows the use of common mass-produced cables and standard breakout boards to connect to something like an Arduino Uno. I don't see a schematic, but this particular module probably draws its power from the motor power supply.
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H: SDA has to wait around one second to go high when reading hex is 0xF8
When I was trying to read 0xF8 from slave, the SDA is still low.
b"0111_0000", -- 38 slave address (write)
b"0000_0000", -- 00 register address
b"1000_1111", -- 8F data
b"0111_0000", -- 38 slave address (write)
b"1010_0100", -- A4 register address
b"0000_0000", -- 00 data (enable interrupt to host)
b"0111_0000", -- 38 slave address (write)
b"1000_0000", -- 80 register address (describe valid touching detect threshold)
b"0000_1111", -- 0F data
b"0111_0000", -- 38 slave address (write)
b"1000_1000", -- 88 register address (describe valid touching detect threshold)
b"0000_1100", -- 0C data
b"0111_0000", -- 38 slave address (write)
b"1010_0001", -- A1 register address
b"0111_0001", -- 38 slave address (read)
b"0111_0000", -- 38 slave address (write)
b"1010_0010", -- A2 register address
b"0111_0001", -- 38 slave address (read)
Whole code initialization used by the master is above.
Datasheet of the slave chip is here (https://threefivedisplays.com/wp-content/uploads/datasheets/touch_driver_datasheets/FT5206_REV_0_4_%20APP.pdf)
As you can see from the datasheet, this IC is used by touch screen to read touch value.
You can see that from the first picture that the SDA is low even though SCL is high for quite a while. The message I am trying to send is a stop according to IIC protocol.
You can see from 2nd picture when I was trying to read 0x30 from slave, the slave is high.
The 3rd picture shows that SDA goes high anyway after one second (very long time) when read value is 0xF8.
Scope diagram of the IIC is here.
Second oscilloscope diagram is here.
Can anyone explain what happened here?
AI: When you have transferred the last byte you want to read, you ACK the byte.
That is incorrect, you must NAK the last byte.
If you ACK the byte, the slave IC thinks you want to receive a next byte too and starts transmitting it out. So that is why SDA is low and you can't send out a stop, because you can't release the SDA after setting SCL high if the slave is keeping the SDA low.
If you NAK the byte, the slave will no longer drive any data out after the NAK, leaves the SDA floating high, and the FPGA is free to pull SDA down, release SCL high, and release SDA.
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H: Acceptable PCB practice for pad routing and vias
Two questions on beginner PCB design:
For integrated chips on PCB design, can you draw routes from the side of the contact pad, or is it standard practice to go head-on straight to the pad entry?
For large capacitors that have an output to GND, on a board that has a GND plane, can you put a via directly to the GND plane? Does this help dissipate heat?
AI: You can route your signals to whatever point of the pad that is convenient for you, it does not matter (at least not until you go into very high frequencies). So both options on your image are equally valid (you can even connect with a diagonal line, or on the "inside" side).
What you are drawing on your second image is called a "via in pad": it is perfectly allowed, but requires the via to be filled (epoxy or metal) before soldering the capacitor (otherwise the solder paste will flow into the via, with a great risk of getting a bad solder joint). Most PCB manufacturers can do via in pad. But usually, they charge extra for it (so if you can avoid using via in pad for your design, it's cheaper).
For thermal dissipation, all depends from where to where you want to dissipate heat (from the capacitor itself to the ground plane?). Often, the best solution if you can, is to add a ground "plane" as big as you can on the top layer. If you need additional transfer to ground plane on an internal/bottom ground plane, then add as many vias as you can (if heat comes from the capacitor, one via beneath the capacitor is probably slightly better than one next to it, but vias all around would be even better is you have enough space.
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H: Exploding/superhot capacitor in XT AC-DC PSU
I have a commercial replacement PSU that I am using for a vintage XT class computer which has 4 DC lines (5v, 12v, -12v and -5v). On fitting the PSU however, the PC operated but after a while under load one of the capacitors E7 within the 5V DC section got very hot and vented, followed by a second E13 within a different line. The seller has given me some advice and kindly sent me a schematic. From this I have replaced the caps with rubycon 35V versions and E7 gets to about 50c tops from my testing, E13 barely get's warm. I will fit a fan. I wondered if anyone here from the schematic could please give me there thoughts on if there is a reason one failure led to the other? Many thanks
The specs for the replacement are approximately correct. The PSU can supply
+5v @6A,
+12v @ 3A,
-12v @ .8A,
-5v @ .8A
My PC is needing (tested via shunt resistor)
+5v @ 2.1A
+12v @ .34A
-12v @ .02A
-5v @ 0A
AI: The power supply schematic indicates this is a flyback converter, total output power rating = 80W (sum of output power rating of all rails), which is quite modest by today's standards. Your load, however, is only about 12.6W.
Failure of E7 (on the +5V rail) is quite understandable, as it was subjected to the most stress (ripple current). Even more understandable if this capacitor was several decades old - it would likely to have suffered "drying out" and its capacitance and ripple current withstand would have suffered as a result.
Failure of E13 (on the -5V rail) is less understandable, since there was no load on it, however, once E7 failed then E13 may have been subjected to higher ripple current and/or ripple voltage (and possibly DC voltage) than normal since E7 would have been providing the majority of the voltage clamping - details would depend on the magnetic coupling between each of the secondary winding pairs.
You mentioned that the replacement for E7 got to 50C - that is of some concern since it is not necessarily the temperature per se that does the damage, it is the temperature rise above local ambient. Check the datasheet of the capacitor used, which will provide guidance on the effect of (a) ambient temperature, and (b) temperature rise.
I would be tempted to replace E7 with two or possibly three capacitors in parallel, to get the ripple current stress down - ripple current is what casues most of the internal heating. Reducing ripple current by factor of 2 reduces the power loss by a factor of 4 (power = I^2 * R). Look up electrolytic capacitor datasheets to ensure the ripple current stays within manufacturer specifications. For these applications, the value of the capacitance is not as important as the ripple current withstand. There is a second filter after E7, E7 is intended to filter the flyback ripple current and get +5V supply voltage ripple to an acceptable level that is then cleaned up by L2 & C8.
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H: LTSpice (Berkeley Spice) Files. WHERE?
I am working on importing spice files into Fusion 360 Electrical. It accepts original spice files. Is this something common, where can I find it, etc. I am used to finding the footprint, symbol, 3d model through samacsys ECAD libraries. Is it contained in that folder menu for a similar software? I see that autodesk posts "As long as its a pure Spice model, change it to .mdl" I cant find any pure spice models. Do you guys generally do circuit analysis through fusion or through another way? Is there a circuit analysis like kicad that will have the model included in the ECAD files? For instance I need SMAJ58A. How can I get one of those spice models into a simulator?
AI: You get the models from either the manufacturer or another party that has modeled the device.
It is possible in LTspice IV to create a new symbol from scratch for a
third-party model but who has the time? Follow these easy steps to
generate a new symbol for a third-party model defined in a subcircuit
(.SUBCKT statement).
Open the netlist file that contains the subcircuit definitions in LTspice (File > Open or drag file into LTspice)
Right-click the line containing the name of the subcircuit, and select Create
To use the new symbol (and associated third party model) in a schematic, select the symbol from the AutoGenerated directory in the
component library (F2) and place it in your schematic:
Select Component Symbol
By using the automatic symbol generation you can focus on your
simulations, not creating new symbols. For a more information on how
to import third party models that use intrinsic SPICE device (.MODEL
statement) see the video at www.linear.com/solutions/1083.
Source:
https://www.analog.com/en/technical-articles/ltspice-simple-steps-to-import-third-party-models.html
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H: Why does compiler optimization flag cause function definitions other than main() to break program in AVR ATMega C code?
I am using avr-gcc and avrdude to write programs onto an ATMega8515 micro-controller. I have got the blinking LED program working without a hitch. However, when I started to use interrupts and introduce functions other than main() to the code, I came across bugs. Though I could compile the program and write it onto the chip, it did not run as expected - the LEDs that should have been blinking were completely unresponsive. With tweaking I found out that the introduction of any function, not just an interrupt service routine, caused this issue.
I came across near identical issues here:
https://stackoverflow.com/questions/65427371/why-does-my-isr-declaration-break-my-program
"Now, none of the LEDs blink. Even weirder, none of them blink when I remove the sei(). The only way I've found to make the first LED blink again is to comment out the ISR declaration"
And here:
AVR ATmega32 - C - Gets stuck in function call
"it's just the same statements as before, moved to the pulse_init() function. When I upload this code the timer is set up correctly and the output pulse is OK, but the program never starts blinking the LEDs on PC0..1."
To be clear, these are the commands I am using to compile and write the code to the ATMega:
avr-gcc main.c -O2 -o main.elf
avr-objcopy main.elf -O ihex main.hex
avrdude -c usbasp -p m8515 -U flash:w:"main.hex":a
And this is a sample code snippet that does not work:
#ifndef F_CPU
#define F_CPU 1000000UL // 16 MHz clock speed
#endif
#define __AVR_ATmega8515__
#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
volatile uint8_t toggle_blinking = 1;
int main()
{
sei(); /* set global interrupt enable */
MCUCR = 0b00000100; /* Set the INT1 to trigger on any logic change*/
GICR = 0b10000000;
DDRC = 0xFF; // Makes PORTC as output
DDRD=0xe0;
while(1)
{
if(toggle_blinking)
{
PORTC = 0xFF; //Turns ON All LEDs
// _delay_ms(500); //1 second delay
// _delay_ms(500); //1 second delay
}
else
{
PORTC= 0x00; //Turns OFF All LEDs
}
}
}
ISR(INT1_vect)
{
toggle_blinking ^= 1;
}
The common denominator between all of these programs (mine, and the two linked above) is the use of the avr-gcc optimization flag (-O) which is there to ensure that the util/delay.h functions run correctly. I compiled a program which did not work with the optimization flag again, this time without the optimization flag. And sure enough, the program worked.
To clarify, I am not sure whether other function definitions are "breaking" the program, or if they are just being run instead of main(). Here is the object dump when running running avr-objdump -d main.elf on the .elf file that was generated by compiling the above program with optimization enabled:
00000000 <__ctors_end>:
0: 10 e0 ldi r17, 0x00 ; 0
2: a0 e6 ldi r26, 0x60 ; 96
4: b0 e0 ldi r27, 0x00 ; 0
6: ea e6 ldi r30, 0x6A ; 106
8: f0 e0 ldi r31, 0x00 ; 0
a: 03 c0 rjmp .+6 ; 0x12 <__zero_reg__+0x11>
c: c8 95 lpm
e: 31 96 adiw r30, 0x01 ; 1
10: 0d 92 st X+, r0
12: a2 36 cpi r26, 0x62 ; 98
14: b1 07 cpc r27, r17
16: d1 f7 brne .-12 ; 0xc <__zero_reg__+0xb>
00000018 <__vector_2>:
18: 1f 92 push r1
1a: 0f 92 push r0
1c: 0f b6 in r0, 0x3f ; 63
1e: 0f 92 push r0
20: 11 24 eor r1, r1
22: 8f 93 push r24
24: 9f 93 push r25
26: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <__data_start>
2a: 91 e0 ldi r25, 0x01 ; 1
2c: 89 27 eor r24, r25
2e: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__data_start>
32: 9f 91 pop r25
34: 8f 91 pop r24
36: 0f 90 pop r0
38: 0f be out 0x3f, r0 ; 63
3a: 0f 90 pop r0
3c: 1f 90 pop r1
3e: 18 95 reti
00000040 <main>:
40: 78 94 sei
42: 84 e0 ldi r24, 0x04 ; 4
44: 85 bf out 0x35, r24 ; 53
46: 80 e8 ldi r24, 0x80 ; 128
48: 8b bf out 0x3b, r24 ; 59
4a: 8f ef ldi r24, 0xFF ; 255
4c: 84 bb out 0x14, r24 ; 20
4e: 80 ee ldi r24, 0xE0 ; 224
50: 81 bb out 0x11, r24 ; 17
52: 9f ef ldi r25, 0xFF ; 255
54: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <__data_start>
58: 88 23 and r24, r24
5a: 29 f0 breq .+10 ; 0x66 <main+0x26>
5c: 95 bb out 0x15, r25 ; 21
5e: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <__data_start>
62: 81 11 cpse r24, r1
64: fb cf rjmp .-10 ; 0x5c <main+0x1c>
66: 15 ba out 0x15, r1 ; 21
68: f5 cf rjmp .-22 ; 0x54 <main+0x14>
And here is the dump from the compiled program without optimization enabled:
00000000 <__ctors_end>:
0: 10 e0 ldi r17, 0x00 ; 0
2: a0 e6 ldi r26, 0x60 ; 96
4: b0 e0 ldi r27, 0x00 ; 0
6: ea ea ldi r30, 0xAA ; 170
8: f0 e0 ldi r31, 0x00 ; 0
a: 03 c0 rjmp .+6 ; 0x12 <__zero_reg__+0x11>
c: c8 95 lpm
e: 31 96 adiw r30, 0x01 ; 1
10: 0d 92 st X+, r0
12: a2 36 cpi r26, 0x62 ; 98
14: b1 07 cpc r27, r17
16: d1 f7 brne .-12 ; 0xc <__zero_reg__+0xb>
00000018 <main>:
18: cf 93 push r28
1a: df 93 push r29
1c: cd b7 in r28, 0x3d ; 61
1e: de b7 in r29, 0x3e ; 62
20: 78 94 sei
22: 85 e5 ldi r24, 0x55 ; 85
24: 90 e0 ldi r25, 0x00 ; 0
26: 24 e0 ldi r18, 0x04 ; 4
28: e8 2f mov r30, r24
2a: f9 2f mov r31, r25
2c: 20 83 st Z, r18
2e: 8b e5 ldi r24, 0x5B ; 91
30: 90 e0 ldi r25, 0x00 ; 0
32: 20 e8 ldi r18, 0x80 ; 128
34: e8 2f mov r30, r24
36: f9 2f mov r31, r25
38: 20 83 st Z, r18
3a: 84 e3 ldi r24, 0x34 ; 52
3c: 90 e0 ldi r25, 0x00 ; 0
3e: 2f ef ldi r18, 0xFF ; 255
40: e8 2f mov r30, r24
42: f9 2f mov r31, r25
44: 20 83 st Z, r18
46: 81 e3 ldi r24, 0x31 ; 49
48: 90 e0 ldi r25, 0x00 ; 0
4a: 20 ee ldi r18, 0xE0 ; 224
4c: e8 2f mov r30, r24
4e: f9 2f mov r31, r25
50: 20 83 st Z, r18
52: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <__data_start>
56: 88 23 and r24, r24
58: 39 f0 breq .+14 ; 0x68 <__SREG__+0x29>
5a: 85 e3 ldi r24, 0x35 ; 53
5c: 90 e0 ldi r25, 0x00 ; 0
5e: 2f ef ldi r18, 0xFF ; 255
60: e8 2f mov r30, r24
62: f9 2f mov r31, r25
64: 20 83 st Z, r18
66: f5 cf rjmp .-22 ; 0x52 <__SREG__+0x13>
68: 85 e3 ldi r24, 0x35 ; 53
6a: 90 e0 ldi r25, 0x00 ; 0
6c: e8 2f mov r30, r24
6e: f9 2f mov r31, r25
70: 10 82 st Z, r1
72: ef cf rjmp .-34 ; 0x52 <__SREG__+0x13>
00000074 <__vector_2>:
74: 1f 92 push r1
76: 0f 92 push r0
78: 0f b6 in r0, 0x3f ; 63
7a: 0f 92 push r0
7c: 11 24 eor r1, r1
7e: 8f 93 push r24
80: 9f 93 push r25
82: cf 93 push r28
84: df 93 push r29
86: cd b7 in r28, 0x3d ; 61
88: de b7 in r29, 0x3e ; 62
8a: 90 91 60 00 lds r25, 0x0060 ; 0x800060 <__data_start>
8e: 81 e0 ldi r24, 0x01 ; 1
90: 89 27 eor r24, r25
92: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__data_start>
96: 00 00 nop
98: df 91 pop r29
9a: cf 91 pop r28
9c: 9f 91 pop r25
9e: 8f 91 pop r24
a0: 0f 90 pop r0
a2: 0f be out 0x3f, r0 ; 63
a4: 0f 90 pop r0
a6: 1f 90 pop r1
a8: 18 95 reti
It seems as though the memory address location of main() is being affected by compiler optimizations which is causing the issues. Does anyone have a proper explanation for this and/or a fix that would allow me to use compiler optimizations with interrupt routines?
AI: These are not bugs that you are encountering. The problem goes deeper than just compiler optimization flags. It is a pure coincidence it happens to work at all.
The code isn't compiled properly according to instructions and examples of avr-libc/avr-gcc. Reading the manual will solve the issue.
The command used to compile the code will not work and generates something you can't use, at least not on a Mega8515.
You haven't told to the compiler and the linker which MCU you are using, so that the compiler could pick the right architecture, right startup code, and right libraries to use when compiling and linking code, as there are about 15-20 possible variants of things called AVR.
By default the compiler generates code for "avr2" architecture and Mega8515 is an "avr4" architecture chip.
Also the way you are defining the IC you use in the code for the io header is not the intended way of defining the MCU.
All this is explained on avr-libc website and there are also example projects and more importantly, examples how to compile them properly.
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H: Drawing a Visual Hardware Representation for VHDL Code
The following code is given. My task involves drawing a visual hardware representation that outlines the modules, their associated ports, and the interconnecting signals. Check out my solution below. Am I on the right track?
flipflop.vhdl:
library ieee;
use ieee.std_logic_1164.all;
entity Clocked_Logic is
port (i_Clk : in std_logic;
i_Switch_1 : in std_logic;
o_LED_1 : out std_logic);
end entity Clocked_Logic;
architecture RTL of Clocked_Logic is
signal r_Switch_1 : std_logic := '0';
signal r_LED_1 : std_logic := '0';
begin
-- this clocked-sequential process starts when i_Clk state change
-- the sensitivity list contains only i_Clk
p_Register: process (i_Clk) is
begin
if rising_edge(i_Clk) then
r_Switch_1 <= i_Switch_1;
if i_Switch_1 = '0' and r_Switch_1 = '1' then
r_LED_1 <= not r_LED_1;
end if;
end if;
end process p_Register;
o_LED_1 <= r_LED_1;
end architecture RTL;
My solution:
AI: Your design has 2 flipflops. The first flipflop is needed to store r_switch_1. The second flipflop is needed to store r_LED_1. The second flipflop will toogle as soon as there is a falling edge at i_Switch_1. A toogle flipflop can be build by a multiplexer which leads the q-output of the flipflop back to the d-input of the flipflop, in one case as a inverted signal and in the other case as a not inverted signal. This results in a schematic like this:
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H: How to create a PWM source with fixed frequency and decreasing duty cycle (at some interval) in LTspice?
I'm trying to simulate a PWM signal whose duty cycle decreases by a fixed amount over a given interval from 100% to 0. For example, if the PWM frequency is 2 MHz, I want to ramp down the on-time from 100% to 0 in 11 equal steps (9.1% each) and I want each duty cycle step to "dwell" for 10 cycles of the 2 MHz clock, or 5usecs. So, the 2MHz clocks duty cycle starts at 100%, then after 5usecs, changes the 91%, then after another 5usecs, changes to 82%, etc.
I haven't figured out how to do this. I think I should be able to do it with BV-type devices, but I can't figure out how to have a 2 MHz square wave source, and somehow use it in conjunction with a BV source to set the switching frequency, and then change the duty cycle perhaps based on yet another source with some sort of ramp for which I could "look" for levels to trigger the changes in duty cycle.
In real life, I will be setting the PWM duty cycle digitally (in an FPGA), so I can easily change the duty cycle in steps after x-number of microseconds. But, for the purposes of simulating the analog circuity interfacing with this PWM signal, I would like to be able to create this "stimulus" in the simulation, to verify, among other things, what the dwelling-for-5usecs on each step looks like at the output of the RC filter (i.e., to ensure the filter's time constant is fast enough to settle in time).
I appreciate any suggestions, and will post my solution if I figure it out in the meantime.
AI: Probably brute-forcing a solution using a PWL source is the quickest way to a solution. It's very useful for weird and/or complex sources. Once you dabble in generating your own PWLs using a programming language (or even Excel), you can also use what you learned to import CSV files from real-life oscilloscope data as PWL sources in LTspice.
However, one big downside to PWL sources is that each PWL point overrides SPICE's internal timestep control algorithm and forces the simulator to calculate a solution for the entire circuit at each point. So if you can manage a solution uniquely using LTspice primitives, you can get a significant speed boost.
Below is one such method I've used before for a similar problem as yours. It uses a sample&hold (sample found under the category [SpecialFunctions]) and a diffschmtbuf (found under [Digital]) used as an ideal comparator...along with a bunch of ramps and clocks.
The sample&hold takes a ramp input and generates a stair-step pattern which holds the duty cycle constant for 10 clock cycles of your 2MHz clock before stepping down to the next step which translates to a different duty cycle. This stair-step output goes into a comparator which compares against a 2MHz ramp to generate the PWM output. Vhigh should be the VCCIO of your FPGA bank and the Vt and Vh help set the comparator up to work how we need it to.
Below are the contents of the .asc LTspice schematic file. Copy/paste it into a text file with a .asc extension and you can open the schematic on your machine and play around with it.
Version 4
SHEET 1 1028 680
WIRE -336 0 -384 0
WIRE -160 0 -336 0
WIRE -384 32 -384 0
WIRE -160 32 -288 32
WIRE 80 48 16 48
WIRE 256 48 80 48
WIRE -288 64 -288 32
WIRE -192 64 -240 64
WIRE -160 64 -192 64
WIRE 592 64 320 64
WIRE 656 64 592 64
WIRE 208 80 176 80
WIRE 256 80 208 80
WIRE 592 96 592 64
WIRE 176 128 176 80
WIRE -384 160 -384 112
WIRE -240 160 -240 64
WIRE 592 208 592 176
WIRE 176 256 176 208
WIRE -240 288 -240 240
FLAG -384 160 0
FLAG -240 288 0
FLAG -288 64 0
FLAG 176 256 0
FLAG 592 208 0
FLAG 656 64 out
FLAG -192 64 clk
FLAG 80 48 stair
FLAG 208 80 ramp2
FLAG -336 0 ramp1
SYMBOL voltage -384 16 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(1 0 0 55u 5u 1p 55u)
SYMBOL voltage -240 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 1p 1p 2.5u 5u)
SYMBOL SpecialFunctions\\sample -80 32 R0
SYMATTR InstName A1
SYMBOL voltage 176 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(1 0 0 500n 1p 1p 500n)
SYMBOL Digital\\diffschmtbuf 256 0 R0
WINDOW 3 39 89 Left 2
WINDOW 123 41 120 Left 2
SYMATTR InstName A2
SYMATTR Value Vhigh=3.3
SYMATTR Value2 Vt=0 Vh=0.01
SYMBOL res 576 80 R0
SYMATTR InstName R1
SYMATTR Value 100k
TEXT -554 256 Left 2 !.tran 120u
I just wanted to mention that regardless of what method you use to generate the waveform, it would probably be a good idea to find the IBIS models for your FPGA so you can create a proper Thevenin equivalent of your FPGA output pin instead of assuming zero source resistance. This is particularly useful if you're interfacing into RC circuits. There is more information regarding how to do this in this answer:
https://electronics.stackexchange.com/a/573907
Lastly, there is a new SPICE program that just came out several months ago called QSPICE. It is written by the same author of LTspice (the actual person, not the company), so you'll notice many similarities in the interface. One of the most advertised features of QSPICE is the ability to create custom C++ or Verilog modules which can run much faster since everything inside a module is isolated from the rest of the SPICE circuit matrix. I'm still struggling to find good use cases for these "DLL modules", but one I did find is being able to generate arbitrary sources directly using code. You can try using this feature to create your waveform programmatically within the actual SPICE simulator software, and also without a performance hit.
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H: What is the meaning of "e" in this timing diagram?
https://hdlbits.01xz.net/wiki/Edgecapture
What is the meaning of "e" in this timing diagram?
AI: e is a numeric value displayed in hexadecimal format. It is the same as 14 in decimal. It means that bits in[3:1] are set to 1, and the other 29 bits of in are 0.
It is common for Verilog simulation waveform viewers to display bus signals (like the 32-bit in signal) in hex format, also in shortest form (no prefix, no leading 0's). For example, e represents the 32-bit value in Verilog syntax:
32'h0000_000e
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H: How can you protect exposed ground pins from ESD?
If I have a DC powered PCB that is floating (not tied to earth ground), and a human touches the ground plane causing an ESD event to occur, what can be done in terms of design to prevent damage to the ground pins of IC's and other sensitive components?
As an example I've drawn a circuit where there are two exposed pins which power an LED. Consider C1, IC, and TVS to be part of the PCB, and the DC power supply to be connected externally. The boxed in portion is the exposed area of the circuit which a human can touch.
If the system is powered and the PSU (or battery) is connected to the circuit, then I would assume that the ESD current would flow back into the power supply negative. But what if the system is unplugged? Are the GND pins at risk of damage here?
simulate this circuit – Schematic created using CircuitLab
AI: You're supposed to have a separate chassis ground that maximizes free space capacitance such as a large area conductive plate (can be very thin) or enclosure. You then ESD shunt everything to that, including your circuit ground. The large free space capacitance reduces the accumulated voltage on the device when your body capacitance equalizes charge with it.
Obviously signals must be shunted to the chassis ground through devices like TVS diodes, but I recall that shunting circuit ground to chassis ground can be done directly or through TVS diodes. I am unclear which is more effective. It would seem that direct shunting is the lower impedance more expedient path but relies solely on the equalization of charge to reduce the voltage spike on the circuit ground, whereas the TVS diode is less ideal path but has an energy dissipation mechanism to hard limit the accumulated voltage on the circuit ground. I suppose the higher the free space capacitance of the chassis ground, the more you would prefer direct shunting.
Care must be taken when shunting to this chassis ground so that the impedance is low enough that the fast ESD transients at the entry points you are designing for favour going to the chassis ground over your circuit board. This can sometimes involve a mini split-plane on your PCB that nearby connectors shunts to which then connects to your chassis ground. This mini-plane will need to be connected via a bridge to the real ground plane and signals entering the connectors need to be routed over the bridge accordingly to prevent EMC problems regarding discontinuities or unecessarily large loops for the return currents.
You can't effectively shunt ESD that can enter everywhere and anywhere on the board. You need to identify the ESD entry points you want to protect against and prevent contact everywhere else.
Taken from Electromagnetic Compatibility, 2009, Henry Ott R.I.P.
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H: Peak current limit and valley current limit of inverting buck-boost converter
I am trying to understand, in a inverting buck-boost converter, why the peak current in the inductor should be smaller than the high-side current limit and valley current in the inductor should be smaller than the low-side current limit.
My understanding:
During high-side switch ON and low-side switch OFF, the current goes up until peak current and during low-side switch ON and high-side switch OFF the current goes down. So this peak current should be smaller than both low-side current limit or high-side current limit, whichever is smaller. But when I read this artical for TI (page 14), it seems it's just OK if Ipeak < high-side current limit (4.2A<4.8A) and Ivalley < low-side current limit (3.7A<3.9A). So why? During low-side switch ON and high-side switch OFF, the current passing throug low-side MOSFET goes down from Ipeak to Ivalley, so if Ipeak > low-side current limit (4.2A > 3.9A), it shouldn't work!
Can anyone explai it?
Thanks
AI: so if Ipeak > low-side current limit (4.2A > 3.9A), it shouldn't work!
You haven't read the information on page 6 correctly: -
The typical current limit value for the high-side is 5.5 amps but, could be as high as 6.2 amps. For the low-side the current limit could be as high as 5 amps or as low as 3.9 amps and, 4.2 amps seems reasonable to me and within data sheet expectations.
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H: Diode and bipolar NPN transistors orientation not correct, says JLCPCB
JLCPCB is telling me 4 components are incorrect but when I look over it and the datasheet it all seems correct to me.
My original | JLCPCB corrected:
This is what my current board looks like:
My schematic:
To me that looks correct.
1N4148WS (Datasheet, JLCPCB, Footprint, Symbol & 3D Model)
PMBT3904 (Datasheet, JLCPCB, Footprint, Symbol & 3D Model)
AI: I guess what causes the populated view to show up inverted, is that the pick and place file generated from KiCad ends up 180° rotated for polarized components *. Therefore, they fix this to adjust the components to the orientation of their component feeder.
Let them resolve this. They usually know what you intend and how to realize it on their fab machines.
* It doesn't mean that KiCad is wrong, or that they are wrong. It just means that they use different conventions, or rather that there doesn't seem to be a convention.
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H: Electromagnet design and powering it up? (Fault prevention of DC supply for a small coiled Electromagnet)
I want to create an array of multiple electromagnet which I will be controlling using a microcontroller.
I will have around 100 such magnets lined in a squared grid 10x10. Only three or five at a time will be turned on.
This array of electromagnets will be responsilbe for driving a smaller natural magnet above it.
There will be a small glass sheet sepearting them.
I tried to setup a basic test, creating a very proto-typical model for the desired magnet. As shown in the image below:
Now since it's an 18gauge copper wire, it draws a lot of current which is a good thing for generating powerful magnetic force.
But it only works if we hook this contraption with any battery made of electrolytes.
As soon as I hook the make-do model of electromagnet with a 12v DC supply, the power-supply does what it supposed to do.
That is to protecte itself from the exessive current draw, and its fault prvention circuitry cut the power altogether.
How to make it work?
Should I opt for a higher voltage supply, since I have very low resistance because of the short length copper wire and its wide gauge?
Should I opt for a higher gauge wire and go with more turns in the coil?
Or Should I add some resistors in series to control the excessive current draw?
Here's my dimensions of magnets which I "cannot" change.
5mm core
10mm overall diameter of the electormagnet.
25mm length of the electromagnet.
AI: With your poor magnetic circuit - the iron core only halves the length of air that your H-field has to push flux through - you are going to need all the Ampere.Turns you can get, as it only doubles the field compared to an air core.
To get maximum strength from the magnet, you need to (a) wind as much copper on there as possible and (b) dissipate as much power in it as it will allow. This is independent of voltage, current, turns or wire gauge - they are related as we shall see, but only the mass of copper and the power dissipated actually affect the magnetic field independently.
The maximum power you can use is governed by the maximum temperature it can reach, and the magnet duty cycle. If you want to operate it continuously, then you are limited by its cooling. If you want to apply a single pulse, then you are limited by its heat capacity. Needless to say, most realistic use cases fall between these two simple extremes. It's safest to design for the continuous case. If you can plan for, let's say, a 10% duty cycle, then you can use three times more current than the continuous limit. However, if you operate at 30% or 100% for too long, it will overheat. It's quite easy to operate at 100% if your software crashes - you may want to implement a watchdog to shut the magnet supply down if the software fails.
Once you have decided what power you can use, you change the turns and wire gauge to match your power supply. More turns of thinner wire - higher voltage lower current. Fewer turns of thick wire - lower voltage higher current. But in each case, it's the same total power.
A series resistor will simply increase the voltage needed at the power supply for any given magnet current, so avoid it in the final design. It can be a useful way of limiting the current while you are experimenting though.
To answer your actual questions
Should I opt for a higher voltage supply, since I have very low resistance because of the short length copper wire and its wide gauge?
No, that will only make things worse, you need a lower voltage higher current power supply.
Should I opt for a higher gauge wire and go with more turns in the coil?
That would help with your present supply.
Or Should I add some resistors in series to control the excessive current draw?
To experiment with, yes, but don't design them into the final version.
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H: The condition of linear operation of the transistor Dipole in small signal mode
How small should the base-emitter voltage changes of the transistor be so that the relationship between the base-emitter voltage changes and the collector current changes can be considered linear?
AI: For a BJT, the voltage scale is the thermal voltage, about 26 mV at room temperature. The base voltage change must be substantially smaller than that to approach linearity.
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H: Repurpose adjustable standing desk linear actuator for a project on my truck
Disclaimer: fairly limited experience with electrical engineering.
I'm currently making a deck for my snowmobile that will sit in my truck bed -
a 'Sled deck'. Nice sled decks have telescopic sides so the sides expand to facilitate two snowmobiles side by side. I would like to make the sides telescope out electrically using linear actuators, will be simple to put together and easy to wire into the trailer power in my truck bed.
I have been looking on progressive automation's website and found some actuators that would work and a control panel that will allow presets - having presets is something I never thought of but now really want... however, it's coming in pretty expensive.
It dawned on me that maybe I could repurpose the control panel and actuators from a standing deck (there is one for sale on Facebook marketplace locally for one fourth the price of getting everything new).
However the standing desk has a household AC plug on and I need them to work with DC. Is there any way I could do that?
Alternatively, is there cheaper way anyone knows of setting presets than the $150 control from progressive?
AI: You’d need to have a close look at the circuitry; it’s quite possible that the actuators run on low-voltage DC and the control circuit certainly will. If you’re lucky you’ll find that there’s an AC to DC power module, so you could essentially remove that and operate the whole thing from DC (if you’re really lucky it will be 12V).
It’s also possible that the power conversion circuit is built into the control board, in which case you’d need to do some surgery to feed in DC at the right point. You may need more than one supply voltage, which could get more complicated.
Another approach, which might work well for you, would be to use an inverter to generate AC and then run from that.
Be aware though that a desk is designed for indoor use, so consider what will happen when it gets wet.
Good luck!
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H: Sampling gain effect in buck converter
I recently learned that there is a phenomena called sampling gain effect in dc-dc converter and I am struggling to understand what this phenomena really is. Could someone enlighten me?
And I have seen a document where they are saying that using average current mode control (with a filter inside the feedback loop of the current) help to get rid of this effect. Is it true? How is it possible?
AI: Let me try to give a simple answer to this question. Current-mode-controlled converters are made of two loops: an inner current loop and an outer loop which ensures voltage regulation. The error or control voltage \$v_c\$ does not set the duty ratio \$d\$ (as in voltage-mode control) but programs the inductor peak current \$i_L\$ and, indirectly, the duty ratio. It is the inner loop which does this job.
It is possible to model the current loop with the below illustration that I drawn for the article I published in How2Power some years ago:
This model is coming from Dr. Ray Ridley's work carried in 1990 and documented in his thesis available online.
In this model, you see a block \$H_e(s)\$ and it is describing the sampling operation: the inductor peak current is a discrete value updated cycle-by-cycle and that is the reason why Ridley used sampled-data analysis to model the loop. He did approximate \$H_e(s)\$ with a 2nd-order polynomial form featuring two right-half-plane zeroes. These two zeroes are located at half the switching frequency. It then becomes possible to visualize the control-to-inductor-peak-current transfer function which looks like this:
Unlike what people believe, there is no peaking in this inner current loop but its gain moves in relationship with the sense resistance, the various inductor slopes and the amount of injected compensation ramp via parameter \$m_c=1+\frac{S_e}{S_n}\$ with \$S_e\$ the external compensation ramp slope and \$S_n\$, the on-time slope. As the loop phase does not depend on the gain, at some point, if the gain is too strong (no compensation ramp and duty ratio approaching 50% in CCM), you have conditions for oscillations. Injecting an external ramp will force a crossover at a lower frequency, naturally building phase margin and stabilizing the current loop.
It is when the current loop is embedded into the outer voltage loop that the two RHP zeroes turn into double poles - the sub-harmonic poles - located at \$\frac{F_{SW}}{2}\$ and affected by a peaking you need to damp:
I have shown in the article how I built a digital modulator to measure the current loop transfer function in SIMPLIS and it perfectly confirms Ridley approach who also used a digital modulator on the bench for his experiments. As additional information, I looked at a way to differently model the current loop with a delay line here and the final theoretical results exactly match the power stage control-to-output transfer function obtained in SIMPLIS.
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H: Capacitance equation understanding
Does anyone know where the bottom equation is derived from?
Why is it 8V/9V?
Source: Mouser - Everything for Capacitive Power Supplies by TDK
AI: Those are the minimum and maximum output voltages, given 1 Vp-p of permissible ripple.
The capacitor discharges exponentially, following the curve
$$V(t) = V_0 e^{-\frac{t}{RC}}$$
Solving for C gives:
$$\frac{V(t)}{V_0} = e^{-\frac{t}{RC}}$$
$$\ln\left(\frac{V(t)}{V_0}\right) = -\frac{t}{RC}$$
$$C = -\frac{t}{R\ln\left(\frac{V(t)}{V_0}\right)}$$
This isn't how I normally do this computation, however.
A power supply is usually designed for a particular load current, not resistance, so there's simpler formula you can use to size the capacitor:
$$\Delta V = \frac{\Delta Q}{C} = \frac{I \Delta t}{C}$$
Solving for C:
$$C = \frac{I \Delta t}{\Delta V}$$
and given a load current of 9 V / 600 Ω = 15 mA, plugging in values:
$$C = \frac{15 mA \cdot 10 ms}{1 V} = 150 \mu F$$
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H: Using VOUT to Power Up a DC-DC Switching Regulator
I am trying to use LM5117 to convert 36V (VIN) to 32V (VOUT) for constant current constant voltage application. It seems the datasheet is saying if the VIN > 14.5V I can use VOUT with a Zener diode (see the attached picture) to power up the DC-DC chip as well. How is this possible since you need the VCC (VCC has to be between 5.5V and 14V) to first power up the chip first. It almost feels like the "chicken or the egg" paradox.
My question was can you use VOUT as the supply voltage for a voltage regulator?
AI: No, the zener diode is for a reference for the HB pin, Vcc in this part is an output not an input. Vin is the input.
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H: How do I select and use a BJT in a simple LED circuit?
I am trying to understand how to use a transistor in a simple LED circuit.
The LED (blue) has a forward voltage of 3V, and I'd like to provide it with 19-20mA. VCC on the circuit is 3.3V. I was thinking I could connect VCC to the collector terminal, and the cathode of the LED to the emitter terminal. I have a 3.3V signal with a maximum current of 10mA. I want to connect this signal to the base terminal of the transistor to illuminate the blue LED.
From what I have heard, an NPN might be a good fit for this application. However, I am struggling to understand how an NPN BJT works, and how to confirm that it meets the circuit requirements.
I have a few questions:
How do I determine if a transistor will operate at a given voltage (3.3V)? I see maximum voltages listed, but not minimums.
How do I determine the required current on the base terminal to “close / enable” the transistor?
How do I determine at what voltage on the base terminal will the transistor be “open / disabled?”
Do I use DC Current Gain to calculate how the ratio of current on the base terminal to the current through the collector to emitter terminals? If so, how?
Is VCE the voltage drop over the device?
Is VCCSAT the voltage drop over the device when the device is saturated?
I am new to EE; any help would be much appreciated.
Edit:
I was asked to include the transistor part number and a link to the datasheet. This is the one I am looking at, but I'm not sure it is correct for my application: BC847BLT3G
AI: Transistors don't have minimum voltage requirements per se, the limiting factor is generally the base emitter voltage \$V_{BE}\$ which is around 0.6 V for a silicon transistor.
For saturation, you'll want something like 1/10th the collector
current.
The transistor will be 'on' when the voltage from base to emitter is at least the \$V_{BE}\$ for the transistor.
You don't use the DC current gain when working with transistors in saturation, that will underestimate the needed base current. Usually you use the \$I_C/10\$ rule of thumb to ensure plenty of base current.
\$V_{CE}\$ is the voltage from collector to emitter, so yes, the voltage across the device.
I believe you mean \$V_{CE_{sat}}\$ which is the voltage from collector to emitter when the transistor is in saturation. This is basically the minimum voltage drop you can expect the transistor to have.
Running a blue LED on 3.3V and keeping the current at a given point is going to be iffy, you don't have much headroom on the voltage, and the LED's forward voltage can vary from device to device and with temperature.
Let's say you wanted to get 20 mA through an LED with a \$V_F\$ of 3.0 V from a 3.3 V source. You would calculate the current limiting resistor to drop the extra 0.3 V, so $$\frac{0.3 V}{20 mA} = 15\Omega$$
Now say that \$V_F\$ changes due to temperature or device variability and it's now 3.1 V. With a 15\$\Omega\$ resistor you would have $$\frac{0.2V}{15\Omega} = 13.333 mA$$ not quite the 20 mA you were expecting. Adding in the \$V_{CE_{sat}}\$ of a transistor gives you even less leeway.
Running from a higher voltage makes LED \$V_F\$ changes less critical,let's say you used a 5 V supply for the LED. To get 20 mA you would need $$\frac{2 V}{20 mA} = 100\Omega$$
If \$V_F\$ increases to 3.1 V it's now $$\frac{1.9 V}{100\Omega} = 19 mA$$
much better than the 13.333 mA in the previous example.
Using a transistor you can run the LED on a higher voltage than the I/O voltage, like this
simulate this circuit – Schematic created using CircuitLab
If you already have a higher voltage supply available you can use that, if not you can use a DC-DC converter to boost the 3.3 V to obtain the higher voltage for the LED.
If you just want the LED to light, and it's a one-off project you can try running it at 3.3 V, same basic circuit. Instead of the 100\$\Omega\$ a 10 to 15\$\Omega\$ limiting resistor in series with the LED should be about right. It might work well enough for your purposes.
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H: LM393’s LOW shows high Ohm to GND
In LM393 datasheet it’s connected to GND on LOW, and disconnected of everything on HIGH.
But on my tester I see on LOW:
100 Ohm when no load’s GND connected to Out pin. (No load at all).
850 Ohm when 12V led’d GND lead connected to LM393 out pin.
When I connect the GND of my (comparator-gated) PCB to the out pin nothing 12V fires up, only some 5V leds light up
Why? I expected zero Ohm on LOW.
LM393 usage:
Big picture:
Fix (black):
Edit: @justme, I had to use the comparator as a gate driver, was forced to invert the inputs as the MOSFET was always on in the original setup. Driving the gate with 4V; 0.1mA
Thanks for the help!
AI: You can't test the output of a LM393 with an ohmmeter.
Or you can, but the results are meaningless, because, the path between LM393 output and ground is not a resistance.
So you get an incorrect measurement because you told your multimeter to measure a resistance but you did not give it a resistance to measure.
You are also trying to power a circuit through the LM393 output.
It's not strong enough for that.
When the output drives a 4mA load, the output is guaranteed to be below 0.7V over full temperature range, typically 0.13V and max 0.4V at room temperature. If the voltage is allowed to rise up to 1.5V, it is guaranteed to pull at least 6mA.
The maximum allowed current before it damages is 20mA. It cannot drive your 200mA load.
So yes, the output is not a resistor and not 0 ohm short circuit. You can't measure it with multimeter in resistance mode for meaningful reasults. It's not a power relay intended to drive loads directly.
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H: Transistor works with just base connected
Currently I am trying to self learn electronics. After the diode I moved to the transistor.
I understood the transistor as an “electronic” switch with no moving parts. When the base is connected, then the current can flow from the collector to the emitter. Otherwise it cannot.
Though, when I put 5v across the base, with no voltage across collector nor emitter, an LED, connected to the emitter through a resistor, lights up. Is this normal? Am I missing something on the functions of a transistor?
AI: Yes, it's normal, current into base flows out from emitter, regardless of what connections, if any, you have on the collector.
The base current controls the collector current. Both base and collector current come out of emitter.
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H: Why can't I divide the total number of bytes of a .BMP file by the color depth?
I have a .BMP file resize.bmp.
The total number of bytes that encode pixels in this file is 320 bytes.
The color depth in this file is 3 bytes.
0x176 total number of bytes including Header
0x140 Total number of bytes without Header
AI: Each row of pixel data is padded up to a multiple of 4 bytes.
Specifications for .BMP format are widely available, the original ones made by Microsoft and there is good enough reference even at Wikipedia. Keep the specifications at hand for reference when writing code to handle .BMP files.
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H: When using USB CDC to interface a USB2CAN controller, do I have to set the serial baudrate explicitly and if so, what rate?
I connect a USB to CAN controller via CDC as a virtual port to my computer and interface it via slcan from the can-utils package. So far so good.
What I would like to understand is, why the elinux suggests to use in general 3Mbit/s for the (virtual) serial interface
sudo slcand -o -s8 -t hw -S 3000000 /dev/ttyUSB0
by writing -S 3000000, while the CAN bus speed is set with -s8 to the maximum CAN bus speed of 1 Mbit/s. It describes how the CAN baudrate may be adjusted, but there is no info about the UART baudrate.
The article does not explain, why 3 Mbit/s are selected and I am used to baudrates not being "smooth" (as also seen there: Standard UART rates electronics stackexchange
When I look at the slcand --help
I wonder why the UART speed is not listed in the examples at all. What is the default rate?
Can you please help me to understand this?
AI: That depends which CAN controller it is and how it is made.
For a device that does not have an actual UART which you could communicate with, such as a MCU enumerating itself as USB CDC, the baud rate is irrelevant and unused so it does not matter if it is set to any value or not.
In such a case the MCU simply wants to show itself as virtual COM port for sending and receiving data bytes.
So the communicated bytes don't go out on any UART at any baud rate. They are being used to configure and operate a CAN interface to send and receive packets of data.
If you really do implement an actual serial port using a UART of an MCU that enumerates as USB CDC, then you can use the baud rate setting of the VCP to set the baud rate of the MCU UART to be able to select it from the PC. But if you know it must only communicate at for example 9600 BPS for a GPS receiver, then your MCU must ignore the VCP baud rate and keep communicating always at 9600 BPS no matter what baud rate the PC selects.
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H: HIP4081 Full Bridge FET driver peak pull up/down current
The datasheet for the HIP4081A bridge driver references a limit of 2.5 A "pull up"/"down" current.
I thought the maximum load current in a bridge is limited by the FETs themselves, and not the driver.
What am I misunderstanding?
The reason I ask, is that I need to drive a 12 VDC motor with a 10 A stall current with a PWM.
I confirmed the 10 A stall current by connecting it directly to a car battery with a meter, and a vice-grip to stall the axle.
When I put the 4081a circuit in between, it stalls at a peak 4 A (which is way above the 2.5 A spec). Note that I built the reference circuit in the datasheet (page 3), but pull DISABLE low so that it is 100% duty cycle.
I'm using IRF530 FETs which can handle 10 A, 88 W, so they should at least get me to 10 A @ 12 VDC before smoking. (I'll replace these later with something > 120 W.)
Is there a better full-bridge driver I should be using? I waded through DigiKey but had trouble finding a DIP package driver with that level current.
AI: In the datasheet, the current limits you refer to are in the "GATE DRIVER OUTPUT PINS" section. They therefore refer to the gate drive capacities (i.e. ability to source/sink current to the gate), not the "load" current in the drain-source channels of the FETs.
The drive currents are relevant when working out the switching speed of your FETs, given their gate capacitances.
In general slower switching will lead to greater resistive losses in the FET during transitions, and depending on the PWM rate, these losses could lead to significant FET heating.
However, if you are only running at 100% duty cycle, then you will only have an occasional ON/OFF transition, so 2A of gate drive will almost certainly be more than enough for your application.
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H: Could you use millions of small watch batteries in parallel to start a car?
This is an xkcd style question I grant
Assume you didn't care if the batteries exploded, that this is clearly not practical or sensible etc
But theoretically, it's the end of the world, you have access to unlimited numbers of watch batteries and infinite time, could it theoretically work?
AI: If one CR2032 can supply 2mA at 2.4V @-10°C, to get 250A CCA (cold cranking amperes) at 7.2V (a reasonable, but not generous, rating for a car battery) you'd need 3 sets in series and 125,000 parallel in each set, so 375,000 total.
So not quite millions, at least for the common CR2032 coin cell. If the engine is warm and other conditions favorable, then fewer cells would be required. Of course you'd have to finish wiring them before the batteries self-discharged too much.
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H: Eliminating a weird pulse when switching a valve actuator using a low-side MOSFET
The circuit is connected as drawn below:
MOSFET IC = MAX14919A
Valve actuator = MHE2-MS1H-3/2G-M7-K
Schottky Diode = SS16HL-TP
The pulse happens when the low-side MOSFET opens (disconnecting the valve actuator from ground) before slowly increasing to 24V from 0V.
The yellow line represents the MOSFET gate input signal (5V = on, 0V = off)
The green line represents the applied output voltage (24V)
The waveforms are shown below:
I believe this phenomenon is not an inductive spike because if it was, the Schottky diode would have minimised or eliminate the spike. I have tried the same setup with two other MOSFET ICs, BTS3410G and Si83014BF‐IT. Both of these MOSFET are slower than the MAX14919A (with the BTS3410G being the slowest) and both of them show this pulse once the MOSFET is open.
BTS3410G:
Si83014BF‐IT:
AI: The delayed return to the 24 V level may be due to an RC snubber circuit already within the assembly. Note that in the valve's datasheet there is this entry: "Additional functions - Spark arresting, Holding current reduction, Protective circuit". So there are likely a few other components within the assembly.
The extra pulse could be due to a long cable (as hinted by Tim W). Might there be excess cable length coiled up? On your next to last plot following the first pulse there even seems to be a bit of suppressed oscillation (ringing), potentially caused by cable inductance. If there are additional components internal to the valve perhaps these are helping to suppress some but not all of the ringing action.
If the extra pulse is causing a problem (beyond just a curiosity), a moderate size cap located near the valve may eliminate ringing due to a long cable length.
Below is a sample circuit and Vin/Vout plots showing the results with an RC snubber placed across the valve coil and a small amount of extra inductance on the in-coming cable side.
If the extra cable inductance were to increase to 3 uH the pulse (ringing) will increase considerably.
By adding a relatively small cap (C5 10 uF) onto the cable just ahead of the valve coil the pulse(s) can be eliminated.
A final note: The RC snubber values used were not optimized at all, they were selected in an attempt to duplicate the original plots. The coil inductance, resistance, and self capacitance are also just guesses.
.
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H: Derive values from a graph
I want to get accurate values from this graph when the input voltage (mV) is 0mV what should the output voltage(V) be? I can guess by saying it's 2.55V but I need accurate values to make my circuit more accurate.
I plotted the graph on Excel but it was no good. I had never done anything like this before, and I would appreciate it if someone could point me in the correct direction to figure out how to solve something like this. I had another idea that I draw this graph but I really don't want to.
This graph is from an isolated amplifier: https://datasheet.lcsc.com/lcsc/1809300216_Texas-Instruments-AMC1200BDWVR_C79905.pdf
AI: The graph only shows typical values. You cannot depend on those values being accurate for any given sample of the chip. If you read the datasheet you linked, you will find this line:
So for a 4.5V to 5.5V supply the output common mode voltage will be somewhere between 2.4V and 2.7V, with 2.55V being "typical" at 25°C & at 5.0V supply.
Note that you should not have any expectation of the common mode voltage being stable with respect to temperature or power supply voltage (or even time) unless it's guaranteed by the datasheet in some way. In fact, it's implied it varies considerably with power supply voltage.
Generally speaking, you should use it in such a way that the common mode voltage (within the guaranteed range) has minimal effect on your circuit. Your circuit should respond to the differential output voltage and reject the common mode output voltage.
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H: Closed-loop differential-input JFET amplifier
I am unsure how a differential-input JFET amplifier in a closed-loop can be built. A very simple amplifier with differential inputs and differential outputs can look like this:
As far as I understand, the disadvantage is a gain that depends on the transconductance of the transistors which is not well defined.
To form an amplifier with a well-defined gain one could form such a closed-loop structure:
However, in that case one of the differential inputs is used for the loop feedback such that an amplifier with a single-ended input results.
I am looking for a closed-loop amplifier structure based on a pair of two JFETs with a real differential input.
AI: Think about how this would be done with just an op-amp, you have the differential inputs and an output and when you want to close the loop you connect the output to one of the inputs through a network that determines the gain. The gain isn't well defined until you define it. The FET differential amp is the same as the input stage of an op-amp so you would close the loop the same way, add some gain after the differential stage and feed the output back to the inverting input.
simulate this circuit – Schematic created using CircuitLab
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H: Is negative voltage going to cause trouble?
I'm trying to design a circuit that will allow me to set and reset an SR-latch with a single input.
My idea is that when the input is driven high, the latch immediately resets, and if it persists for longer than t milliseconds then it is set.
So when I want to reset I supply the input with duration less than t and when I want to set - greater than t.
simulate this circuit – Schematic created using CircuitLab
I tried simulating it in falstad - check it out
It seems to work, when the input is held for around 10 ms the latch is set, but when released I notice a voltage drop below 0 on R:
This makes me a little uncomfortable because I don't fully understand what is happening. I understand that negative voltage means that ground is at higher potential than R, but that just raises so many questions in my mind...
Is charge taken from ground through R3 to bring R to 0V?
How does it work?
Is it going to cause damage to a battery?
Can it disrupt the reference voltage of a buck converter if that's the power source?
Could it cause damage to the latch as it will also see negative voltage on it's R input?
AI: If this exactly happens with a real circuit, too (not just simulation), it means the "NOT gate" does not have a clamping diode in the input. It's very common for a gate to have this in the input (source):
If the chip has these diodes, the voltage of the signal will be clamped to the diode voltage.
It's not a good idea to let this happen. It's better to add a diode with low Vf in your circuit so that diode would dissipate that energy from the capacitor. The connection is the same as the bottom diode in the picture (cathode to the input and anode to GND).
To answer your questions:
The current will go through the bottom 1k resistor (R3 in the first schematic) from GND to discharge the capacitor.
It's a high-pass RC filter characteristic.
UPDATE:
As explained by a comment, the question is how we can draw current from GND. The GND in your circuit is not a single node. It's connected to the chip, output load, etc. When this capacitor is drawing some current from GND, the return current to the battery will be reduced (for a very short period of time) as long as this current is not going to be bigger than the return current to the battery (It's not possible and the current drawn to the capacitor will be limited by that current); meaning the battery will source current from the negative node. Kirchhoff's law can explain what happens there. You need to create a complete network of the components to be able to see where the current goes. In very simple terms, when this capacitor is drawing current from the GND, the return current to the battery will be reduced (during capacitor discharging). Because the battery has only two terminals, by reducing the return current from GND, the source from positive will be reduced at the same time. This means, the stored energy in the capacitor from the previous charge (higher current drawn from the battery in the charging phase), is being discharged to supply rail if you have a diode there. In case of discharging through the resistor, the energy will be dissipated through the R3 resistor and you will see less ripple in the return current.
No. It will create a small ripple in GND, though.
Usually, the effect is negligible. Unless you decide to go for higher capacitors. In that case, the design and placement of the components are important. Usually, to prevent any noise from going back to the rest of the circuits, a T or Pi filter is used on supply lines.
Yes. Add an external diode to prevent any potential damage.
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H: What sort of transistor is this?
I come back to ask for the help of the community in order to identify a device which was given to me several years ago by an electronics component dealer. This time I know something more, precisely
it seems a PNP transistor since it appears as a two junction device with a common terminal which leads to a N-doped regions (it may be a double diode, but in this case it would be extremely uncommon device),
the (gold plated) base terminal is the center one (see pictures below),
the (gold plated) body, including the mounting screw, is isolated from the terminals
the producer is ST Microelectronics (i.e. SGS-Thomson) (see pictures below),
the body is marked with the following alphanumerical codes: 520400501C and 8828 (between these codes lies the ST logo) (again, see pictures below).
What I'd like to know: a data sheet would be perfect (as usual) but even a summary of the basic characteristics will suffice.
For explanation and completeness I add the following pictures of the device.
AI: It can't be really old since ST isn't that old. Mid to late 1980s at the earliest. You can look up when SGS and Thomson got together. Perhaps 1988 is the year of manufacture.
So probably silicon (you can tell from the diode voltage and also identify collector from emitter if it's a BJT- the symmetry and voltage you measure point towards it being silicon diodes).
You can measure the gain if it's a BJT with many multimeters- using the hFE function. If there is no gain, then it's a dual diode.
This kind of case was typically used with thyristors, however they generally had only two lugs and the case was the third connection. If it's a transistor it would not be suprising if the case is also connected to the collector.
Might be some house numbered device for some military or space application- literally a gold-plated design.
2N5005 seems like a plausible part number. There is a listing here for an identically marked part which the seller claims is a 2N5005:
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H: ESD protection: connect wrist strap to ESD mat or directly to grounding point
For our workshop, I'm thinking about buying a big ESD mat to cover the whole workbench (5.5 m), so it won't be a "ready to use" one, but a roll to cut to the right dimensions, and to which I need to add the connector(s) to ground.
Now the question is: where should I connect the wrist strips:
directly to the earthing point? (it's what we do currently with our small mats, that have a single connector)
or to the mat? (it would be cheaper, and probably more convenient to use)
Is one solution safer (for the user and/or the electronics) than the other?
If it matters, for now, the cables we use all have built in 1 MΩ resistors, and some of our grounding points also include a 1 MΩ resistors (but not all of them). Anyway, we will buy new grounding point plus and cables for this workbench, so we can use something else if better suited.
AI: Now the question is : where should I connect the wrist strips
I'd connect wrist band to the mat and the mat to earth: -
Image from here.
Is one solution safer (for the user and/or the electronics) than the
other?
Either are just as safe but, my preference is to be able to visually see that a wrist band is connected to the mat because, sometimes, the wall socket cannot be readily seen and, if it's removed it's not the end of the world in terms of protecting the sensitive electronics. Reason: it's static discharge picked up by the user that needs to be equalized to the electronics (via the mat) and, not necessarily hard earth.
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H: Relationship Between Current and Power in a Refrigerator
I have a refrigerator with the following characteristics:
Condensing Unit Size 1/2 H.P.
Voltage (International) 115/60/1
Total Amps (International) 7.7
Defrost Amps (International) 4.4
What generates doubt for me is that: The power is 1/2 HP, which is equal to 372 W, but if I calculate it:
120 V x 7.7 A = 924 W
So, why does the specification sheet say 1/2 HP?
AI: "Defrost Amps: 4.4" means that up to 4.4A are used by the defrost heater, which is a separate thing from the compressor.
7.7A - 4.4A = 3.3A.
3.3A * 115V = 379W, which is quite a nice match for 1/2 HP.
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H: Grounding in power electronics
I'm designing a three-phase inverter and have been looking up information online with respect to grounding, which led me to a somewhat misapprehension.
In my system I firstly planned on separating the ground of microcontrollers (PWM, digital signals etc..) and sensors (analog signals such as current/voltage measurements) from the power ground, which is the one in the 400 V DC LINK of the three-phase legs. I intend to do that with optocouplers and hall sensors.
However, I'm still confused as to why there's a need to isolate these grounds. Can I not simply be careful with pcb routing not to create dangerous return paths and I'm good to go?
Is there really a specific need to isolate grounds that PCB routing cannot solve?
For instance, this design from ST uses a shared ground for both MCU and power transistors : https://www.st.com/resource/en/data_brief/steval-esc001v1.pdf
AI: Based on the information you provided, i'd recommend the following system layout. This only isolates the CAN-Interface for external use.
simulate this circuit – Schematic created using CircuitLab
(1) Your CAN interface is isolated from your main MCU with a digital Isolator. I'm not aware (From the top of my head), that i used isolators intended for CAN specifically. We usually use a "Communications Co-Processor" connected to the main MCU via SPI.
(2) You main MCU is on the same ground as your entire power circuit. The gate-drives, the ADC to sample phase voltage and current, and what-not.
(3) Your main circuit needs a "helper power-supply" to bootstrap the circuit from the AC-Input. The gate-drivers can require a significant ammount of power, so do your calculations.
(4) Programming/Updating the device in the Field is done via a e.g. USB interface. The data is routed through the Co-Processor and updates the main MCU. Make sure, the power circuit is in a safe state per design while the main MCU is in reset.
(5) The Co-Processors flash image is stored in the main controllers flash image. It is "updated" every-time the device boots. This way, the Co-Processor can't suffer from firmware inconsistency issues after the main processor was updated.
(6) Power is supplied to your communcation side via the external interfaces (USB for updating, CAN for data exchange). This is extremly common. Take care of EMI/TVS protection on the CAN interface if intended for industrial use.
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H: Sizing an CMOS StrongArm Latch comparator on Virtuoso from scratch
I'm currently designing an CMOS comparator and I'm a little bit lost regarding sizing the transistors. I was taught to use the Id formula, but for that to work I need to have muCox, and I do not. Can't calculate muCox either because I don't have W/L ratio, since it's what I'm trying to calculate.
Is there any other way to get the W/L ratio for each NMOS/PMOS knowing Id, Vgs and Vds?
For now I want all transistors in saturation, I'll change that once I find a solid method to size everything. Below is the topology I'm trying to size.
AI: If you know Id, Vgs, and Vds, and a Virtuoso device model, you have enough information to solve for an approximate shape ratio under a few assumptions (namely, no body effect, if applicable you've decided between nominal/low-Vt/native/RF transistors and chosen a specific one, etc)
Even though you don't have a muCox, your spice/spectre models will include a vast number of process-specific parameters that will provide the same unknown as muCox does, just with a much higher degree of precision.
You can pick a length based on your speed and approximate R_out requirement(1), bias a transistor with a constant Vgs and Vds, and sweep the width ratio until the correct drain current is achieved. This will get you a solution at one corner (probably the nominal one), and you may need to iterate on both length and width if you aren't hitting all specs, and will set your inversion coefficient (2) for you.
You'll also want to note that the performance will vary outside the typical corner - presumably your Vgs, Vds, and headroom will change a bit as long as you're feeding a constant current
Notes:
(1) - Higher length makes for a slower transistor, but with better output impedance and intrinsic gain.
(2) - At low inversion coefficient (weak inversion) transconductance efficiency (gm/Id) is high, but speed is low. At high inversion coefficient gm/Id is low, but speed is higher. I give plots in this answer I wrote a few years back. As further reading, if you want a methodology that relates gm/id to high-speed small-signal performance, you may want to consider gm/Id based design, I have written up a past answer here. I don't know enough about your current topology and criteria to know whether it is applicable (and this question is not a duplicate).
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H: Verilog: only run an edge triggered always loop once per edge change
I'm currently working on a simple up counter triggered by the negative edge of a push button. If the button is held while pressed down, the counter gets stuck in the always block and increments by more than 1. Is there any way to only execute the always block only once per negative edge?
always @(negedge button) begin
count <= count + 1;
end
AI: A better design is to use a double-rank flip flop to synchronize the push-button to the system clock.
The always block is then clocked from the system clock and includes a simple state-machine to detect the push-button falling edge that is then used to synchronously increment your counter (which is also operated from the system clock).
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H: Optocoupler as a switch for composite video sources
I want to switch between 2 video sources (cameras) to a common video receiver. Is general purpose optocoupler suitable for that?
Here is the schematics:
In more details, the video switch is controlled by a 3.3v MCU. It will select input video source before turning on the video receiver, so there will be no question regarding video synchronization. The cameras are of standard composite NTSC video type, have 12V power supply and 2 video wires (plus and minus, where minus is actually the common ground).
So, the question is if optocouplers work well passing analog signal.
AI: No. An optocoupler is not a broadband signal switch. That will not work.
It's not clear what you'd need optical isolation for in such low-voltage signals, anyways.
Either way, you will have to use a broadband analog switch. There's dedicated video switch ICs (e.g., the TS3V330), but any analog switch IC with sufficiently high bandwidth (anything above ca. 6 MHz should do, but doesn't really hurt to go to say 20 or 50 MHz, really) and low insertion loss should do.
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H: High voltage at the Schottky's anode terminal (Hobby Li-Po charger circuit)
I'm pretty new at hardware side of things and trying to teach myself circuit and PCB design just as a hobby, so. bear with me if I'm annoyingly noob for you.
As a relatively simple first task, I decided to design a USB powered Li-Po charging - 3V3 LDO circuit. It looks like a pretty common hot-plug type design. basically when the USB cable is connected it cuts the Li-Po from the load and charges the LI-PO while powering the circuit from USB power. When USB isn't connected it uses LI-PO power. Here's how it looks:
The problem(?) is with the Schottky diode (D5) which is supposed to block the current from Li-Po to USB (and the MOSFET gate) when the USB cable isn't connected.
I used the following diode for my prototype:
https://datasheet.lcsc.com/lcsc/2303141100_MDD-Microdiode-Electronics--SS54_C22452.pdf
Anyway, after getting 5 prototype boards I noticed:
When I unplug my USB and plug in a LI-PO Battery (when the Li-Po is at around 4 V) I see 2.55 V at the Schottky's anode terminal. Now I know you're supposed to have reverse leakage with a Schottky diode and it can be high. The unit functions correctly, but that 2.55 V is giving me an itch. Is this normal for this diode? At first I thought the diode may be faulty but all 5 prototypes consistently have the same voltage at that terminal with that 4 V Li-Po.
If this is normal, is this a problem in general? (let's say I will power a MCU board with this)
I'm not sure if it's relevant, but the input impedance of the multi-meter I use is 1 MΩ.
AI: Look at Fig.2 in the Diode's Datasheet (Typical reverse Characteristics).
25µA reverse leakage are exactly in spec for the Diode.
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H: How to format data properly before using CDC_Transmit_FS?
I am using STM32CubeIDE to program 12 bit ADC(P/N = ADC128s102) which has 8 bit of control register and return 12 bit in MISO. Following is scope result. I am able to return some data which I think it is correct.. however, when I try to send these data to the terminal application using CDC_Transmit feature but i am definitely getting wrong value. I am trying to read in decimal and I am expecting value bewteen 1600~1700(ADC reference voltage is 5V). I am currently using only one channel and others grounded.
Could anyone provide me some guideline..? it's very simple thing but I've been struggling so long.. I think the way im reconstructing data is wrong.. thanks in advance
SCOPE
Yellow = MOSI
BLUE = CLK
GREEN = MISO
MAIN LOOP
SPI INITILIZATION
Result on terminal
32774
40710
29190
25094
37638
37126
32774
33798
41478
35590
45318
48134
40710
41222
47366
.....
Edition 1
while (1)
{
//Put CS Low
HAL_GPIO_WritePin(GPIOA, SPI1_CS_Pin, GPIO_PIN_RESET);
HAL_SPI_TransmitReceive(&hspi1, tx_data, rx_data, 1, 10);
//Put CS High
HAL_GPIO_WritePin(GPIOA, SPI1_CS_Pin, GPIO_PIN_SET);
//Reconstruction
uint16_t adcval = (((uint16_t)rx_data[1]) << 8) | rx_data[0];
sprintf(txBuf, "0x%X\t%d\r\n", adcval, adcval);
CDC_Transmit_FS((uint8_t*)txBuf, strlen(txBuf));
HAL_Delay(100);
}
In terminal app,
0x649 1609
0x5F2 1522
0x5FD 1533
0x611 1553
0x632 1586
0x617 1559
0x61B 1563
0x643 1603
0x5FF 1535
0x62D 1581
0x64E 1614
0x62C 1580
0x5FB 1531
0x63D 1597
0x603 1539
0x5F9 1529
0x663 1635
0x61F 1567
0x5EB 1515
0x60C 1548
0x5F1 1521
0x629 1577
0x647 1607
AI: Look closer at your scope shot, the control signals are in the wr0ng byte.
Your are sampling channel 0x00 and not the one you tried to select with the 0x08 value.
Fix is simple: Put it in the other byte, which is the MSB for a 16-bit value.
The ADC expects the control signals to be present in the first byte (MSB) sent on the wire.
EDIT:
Thuis is also why you see those funny values, the SPI peripherial/DMA corrects the byte order to little endian already for you and thus you combined the values the wrong way around. That would be much simpler to see if you printed the values in hex.
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H: Finding the ideal parameters for a homemade electromagnet
I am making an electromagnet and I was watching some videos on designing one. I just have some misunderstanding about power calculations of electromagnets and I have some questions about it.
Q1)
1.1) In terms of power ratings some pre-made electromagnets for example, it says 3W at 5V, my guess would be that they took the nominal current as 0.6A in their magnetic calculations and decided on 5V to be the operating voltage thus giving the 3W rating but when I use a multimeter on both ends it gives me a resistance reading of 6Ω, does this mean that actually the current flowing is 0.83A at 5V or is it that they designed it so that their turns of wire give them the 6Ω of resistance and 0.6A, but rated it as 5V due to losses not allowing the current to actually get to that 0.83A mark?
1.2)
Say I connect a 9V battery to the 5V rated electromagnet, would it be safe to assume that the current will increase making the magnet stronger but get hotter in exchange, obviously the current will be limited and not actually be 1.5A through such a battery but would the magnet still function normally just abit more hotter? If so, is it correct to assume operating at a higher voltage than the rated voltage is ok if I'm planning on using it for a minute or two at a time?
Q2)
Lastly, I want to power my electromagnet with a 9V battery. From research, these 9V batteries can provide from 100 mA and 500 mA, the issue is from my calculations I got resistance to be 1.5Ω so using 9V battery this would give 6A, but that wouldn't actually be the current so what would actually happen if this was connected up? This is what I have a hard time visualizing.
I just want to understand the principles and not just have a single specific solution for my case so I have the questions in a more open/ambiguous manner. I hope you understand, thanks!
Calculator link
AI: The force is proportional to the magnetic flux, which is proportional to the current multiplied by the number of turns.
So, bigger is better, you can have more turns and/or larger wire without overheating.
For a given mechanical cavity size, there will be wasted space between the wires and the insulation itself. I don't know which wire size has the most efficient packing density, but that isn't the most important factor.
The most important factor is to match the wire size and number of turns to your power source. Batteries have internal resistance and this power will be wasted. You want this loss to be minimal.
9V batteries have a lot of internal resistance and are therefore a poor choice. If you must use a 9V battery, you want a lot of turns with fine wire.
There are no standards for determining the wattage for a magnet, especially for those on ebay. Obviously if you put too much power into the coil it will overheat. The continuous power will of course be less than intermittent power.
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H: SATA to USB conversion: is it complex?
Recently I purchased a SATA to USB adapter. To be able to access 2.5-inch (laptop) and 3.5-inch (desktop) hard drives.
To my surprise, there is a board to do the conversion.
Question
Why there should be a board to do the conversion? Why the conversion process is so complex that a board is required?
Update
As pointed out by @Justme the above device has a USB socket problem. A proper device-side USB socket would look like a well-designed external HDD:
AI: Yes, without going to details, it's complex, and it's because USB and SATA are completely different protocols, intended for completely different applications. They use different electrical signaling, different line coding, different packet structure, everything.
You need a chip that can do the conversion.
The chip needs to be placed somewhere, and it needs connections to USB connector and power supply connector, and internally to SATA connector.
The chip, connectors, and components that do the required power supply conversion are best done with a PCB.
Also, it is clearly a poor quality design. They did not even bother to put the correct USB connector there.
They put a host-side socket to a device that should obviously have a device side socket. You now possess a possibly dangerous USB cable which allows you to make connections between devices that you are not supposed to make and can damage the devices.
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H: How to select a handshake and code examples in verilog
I'm new to Verilog, and I was taking a look into the ready-valid handshake. I saw that this is the most used handshake, as it is simple to understand. However, I couldn't find the disadvantages of this handshake. So my first question is:
Are there any cases when the ready-valid is not well-suited for specific scenarios?
Do any specific rules exist to keep in mind when implementing handshakes?
Are there any repository where I can find a simple implementation of a ready-valid example in Verilog?
AI: Ready-valid is very good in a synchronous design, because it allows high bandwidth (transfer on every clock cycle) and precise flow control. That's why it's used in the AXI interface, which is the basis for much vendor IP -- and also my own IP.
For example, here's a module from my own library. The "v" on the input and output ports comes from the fact that much of my work is with video transferred on AXI streams.
/* axi_one_stage_fifo.v */
/* This module is the simplest possible AXI FIFO. It demonstrates the basics of
* the AXI handshake, and can also be used as the output stage of more complex
* processing modules.
*
* This is a fall-though FIFO -- the data appears on the output pins regardless
* of the state of vout_tready.
*
* The disadvantage compared to the two-stage FIFO is that the flow control path
* (TREADY) is combinatorial, which can create long timing paths.
*/
module axi_one_stage_fifo #(
parameter TDATA_WIDTH = 1,
parameter TUSER_WIDTH = 1
) (
/* AXI in */
output vin_tready,
input vin_tvalid,
input [TDATA_WIDTH-1:0] vin_tdata,
input [TUSER_WIDTH-1:0] vin_tuser,
input vin_tlast,
/* AXI out */
input vout_tready,
output reg vout_tvalid,
output reg [TDATA_WIDTH-1:0] vout_tdata,
output reg [TUSER_WIDTH-1:0] vout_tuser,
output reg vout_tlast,
/* clock, reset */
input clock,
input reset
);
wire xfer_in = vin_tready & vin_tvalid;
wire xfer_out = vout_tready & vout_tvalid;
assign vin_tready = vout_tready | !vout_tvalid;
always @(posedge clock) begin
if (reset) begin
vout_tvalid <= 0;
end else begin
if (xfer_in) begin
vout_tvalid <= 1;
vout_tdata <= vin_tdata;
vout_tuser <= vin_tuser;
vout_tlast <= vin_tlast;
end else if (xfer_out) begin
vout_tvalid <= 0;
end
end
end
endmodule
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H: How do you turn on an LED when the input voltage is less than 12V?
I am designing a device that will check whether a fuse box motherboard is outputting 12V or not. I first considered diodes as they each have a 2V drop so I had 6 in series and functioned well but having 6 LEDs is not efficient. I then considered a npn BJT and had no luck and now I have designed a differential OP Amp that turns on the LED if the Voltage is not 12V. I chose R1=R2 to be 10k ohms and R3=R4=20k ohms giving a gain of 2 I believe. This means that the 2V LED should turn on when the input is 11V or less. Will this work in turning the LED on if the voltage is not 12V(Greater than 11V)? V1 will be the voltage from the output voltage from the fuse box needing to be measured and V2 is the 12V reference. I am also worried if it does work that the current through the diode will be strong enough as it is required that it is bright. Image sourced from ElectronicsTutorials https://www.electronics-tutorials.ws/opamp/opamp_5.html
AI: Riffing on Dave's answer, here's the low component way to turn an LED off when the sense voltage exceeds some threshold. Not for battery operation due to the continuous power drain, but 'fuse box' did sound like wall power was being used.
simulate this circuit – Schematic created using CircuitLab
Depending on the accuracy required, the 431 could be replaced by a simple N-BJT.
We don't know how low a plain 431 will pull its cathode down below its nominal 2.5 V, but a TLV431 will get to just below 1 V. Alternatively, add one or more diodes in the D2 position to increase the LED voltage above the on voltage of the LM431. Note that a white or blue LED will have well above the 431 on voltage.
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H: Fixed-increment adjustment of constant-current source
I am using the LM317 as a constant-current source according to Figure 22 on the ON-Semi datasheet here.
I would like to control the current in fixed increments rather than the continuous provided by a pot, however I am unsure how to go about it.
For fixed-increment voltage regulation, you could just have a multi-select switch/knob and have different resistors connected to each pin as Voltage Adjust is a variable resistor. But because Current Limit Adjust is a potentiometer, this doesn't work. How do I go about this?
AI: If you only need a few points, and are happy with a rotary switch, you could replace the two resistors in the feedback divider with a chain of resistors, then use the switch to tap the desired ratio.
For failsafe behaviour during switching of a voltage regulator, it is normally better to use the switch to short out one of more resistors (rather than just swapping tap points) because that always leaves a well defined minimum feedback path.
In the case of the potentiometer used in the current limit circuit, using the resistor chain suggested above with a make before break switch would probably suffice.
More generally, for full computerized control, you can use a DAC to inject an additional current into the feedback pin of the regulator. This then adds an additional variable control term into the feedback equation.
The specifics are covered in a number of other answers, with this one Adjusting buck regulator with DAC being one of the best.
(The answer and above circuit is actually for an adjustable voltage regulator, but as you already know, this is easy to convert into an adjustable current source.)
You could also consider using a digitally controlled potentiometer (pure silicon, not motorized physical), but you will need to look carefully at the control loop bandwidth and voltage ranges.
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H: Current Consumption of multiplexed 7 segment
I have a display with an one digit 7 segment , I want to use a multiplexed seven-segment and my regulator can just support 150ma of current .
Now my question is that.
Is the current that the regulator must supply the same for both modes? Does it mean that whether it provides for one or for matrixed segment is the same?
Because practically every moment a digit is lit?
AI: You need enough average current per 'on' segment for it to be adequately bright. So if you have 4 digits multiplexed you'd need around 4x the current for a single digit that is driven statically.
The average current required for a display to be adequately bright depends on the LED dice, the display design, optical filters, operating conditions etc. Multiplexing generally does not affect the total required current much. In other words, if 5mA per segment is adequate there will not be much visual difference between a statically driven display showing 8.8.8.8. and drawing 160mA and one driven with 20mA per segment and 25% duty cycle (also 160mA from the power supply).
|
H: What do these 2 NOR gates do in this wind turbine charge controller?
I have the schematic for a wind turbine charge controller from here.
What is the purpose of the two interconnected NOR gates in the middle of the schematic?
AI: S-R Latch
The two NOR gates form an S-R ("Set"-"Reset") latch.
(Symbol from linked source.)
The two outputs 3 (Q) & 4 (not Q) are intended to be complements of each other.
Whilst input 1 (RESET) & 6 (SET) are both low, the state of Q & not-Q will not change (i.e. they are "latched"). This is due to the feedback from each output to the input of the other gate.
If 6 (SET) goes high, 3 (Q) goes high, and 4 (not Q) goes low.
If 1 (RESET) goes high, 3 (Q) goes low, and 4 (not Q) goes high.
If 1 & 6 are both high (SET and RESET at the same time), the Q / not-Q complementary state breaks down, with both outputs being low.
(The "S-R latch" is also known as an "S-R flip-flop".)
Operational significance
In the full schematic, we can see an op-amp/comparator implementing an upper "dump" threshold on the turbine output (which the "dump" button can force) and another op-amp/comparator implementing a lower "charge" threshold (which the charge button can force).
One would expect the two thresholds to be set so there is a dead zone in the middle, and as such only one will be active at once (meeting the input requirements for the S-R latch).
The latch means the current state is held until the opposite threshold is hit. This provides latching of the "Dump"/"Charge" relay state, only switching from one state to the other either when the buttons are manually pressed, or when the turbine voltages hits the opposite threshold.
You would normally expect the two thresholds to be significantly different, to provide hysteresis and prevent "chatter" of the relay.
The two complementary outputs are also used to drive the "Charge" & "Dump" leds.
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H: SRIX4K Emulator - ASK transceiver
I'm trying to build a simple SRIX4K emulator using an ATMEGA328p, I found this circuit on the internet, and it should work as a simple ASK transceiver, using the MCU to transfer data using the SRIX4K protocol:
I tried to both simulating (using this website: https://www.falstad.com/circuit/) and building it with no luck, I'm unable to get the antenna to resonate with the circuit.
The POC containing this circuit: https://github.com/Ptr-srix4k/SRIX4K-Emulator/blob/master/Manual.pdf
How SRIX4K protocol works: https://media.digikey.com/pdf/Data%20Sheets/ST%20Microelectronics%20PDFS/SRIX4K.pdf
Any help or suggestions would be highly appreciated.
AI: I'm unable to get the antenna to resonate with the circuit.
Where's the power transferring transmitter situated? – Andy aka
there isn't one, the circuit is powered by a battery – Giovanni Visentin
You need an externally generated AC magnetic field that drives the coil: -
So, when you say this: -
I'm unable to get the antenna to resonate with the circuit
It gives me the impression that you expect your circuit (as shown in your question) to oscillate happily on its own. That won't happen. The lower circuitry attached to the coil is an envelope detector for receiving AM data that is embedded into the externally generated magnetic field. The upper part of your circuit (Q3) can modulate the received externally generated field and, this modulation can be received by a sensitive detector within the external generator.
Any help or suggestions would be highly appreciated.
You need an external field generator to make this work.
|
H: Is my PFET Orientation Correct for Reverse Voltage Protection?
Do I have the P MOSFET orientation in the attached circuit correct?
AI: Is my PFET Orientation Correct for Reverse Voltage Protection?
No it has drain and source connected incorrectly.
The easiest way to remember is that the MOSFET's bulk diode would not be reverse biased when the polarity is correct. Yours would be reverse biased as it currently stands. This is how it should be done especially if the input voltage can rise beyond 20 volts although the 100 Ω resistor can be significantly higher in value: -
Source: PMOS MOSFET for Reverse Voltage Protection but, as with any circuit on the web, there are many examples that are wrong.
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H: How can prevent the source voltage from dropping when using a 555 timer
I am trying to use a 555 timer in my circuit to produce a signal (rather generally) above 100kHz. I have been successful with this goal, but have had an issue where the voltage measured on my positive and GND rails drops significantly whenever there is a change.
I am using a bench supply that is set to supply 9v at a maximum of 80mA, but the whole circuit only draws 19mA when operational.
This photo shows the 555 timer, with a 470Ω resistor connected to pins 7 and 8, a 10kΩ resistor connected to pins 6 and 7, a 330pF capacitor from pin 6 to GND, and a 1nF capacitor from 5 to GND.
The image above shows the measurement of the supply voltage in yellow and the 555 timer output voltage in blue.
Here is a zoomed in version of the second photo.
This voltage drop is causing the other ICs in my circuit to not work properly.
My guesses is that there is a capacitor somewhere that is too large or small, that this is a property of the power supply or 555 timer, or that the sudden change of voltage requires a lot of current to drive that I somehow cannot detect with my power supply.
Is there any way that I can minimize the voltage drop of my source?
AI: The problem is most likely the lack of a power supply decoupling capacitor. When using a breadboard to prototype analog circuits I always put a 10uF capacitor on the supply rail.
|
H: Arduino's impedance in breadboard circuit
(Warning, as this is a long question, asked by students that don't know what they're doing. Perhaps our questions are too general and can't be answered but at this point we'll take all the help we can get)
As a project in first year engineering, we have to send a laser to be reflected off of a mirror that is placed on a box. In this box is a speaker, making the mirror vibrate. We must collect the data from the laser with a photodiode and send it into a Python and C++ program.
We faced many, MANY problems but one of them is that we do not understand is what happens when we send the signal into the Arduino. Absolutely nothing goes through and we don't know why.
Our circuit:
One of our hypotheses is that the impedance of the Arduino is killing the signal before it can even be analysed.
We switched to another circuit with which we flashed a DEL directly onto the photodiode, omitting the laser and the mirror completely. It gave us something that looks like this:
The other problem we encountered is the translation into audio files. When we eventually had a circuit that worked properly with a laser and the mirror oscillating with the music, the audio files were weirdly cropped.
Our question is: at what sampling rate should we have set our Python program in order to translate the data into audio files that we can actually listen to? Because in order for the time of the audio file to match the time of the sample of the song, the sampling frequency of the photodiode must be identical to the sampling frequency within our Python script (or so we were told).
AI: When you are overwhelmed with a project, you need to break it into smaller pieces.
Test your ADC path with a simpler setup. Play some music and try to capture it directly with the Arduino. You need to bias the signal to the center of the ADC.
Note that the ADC output will be a number from 0 to the maximum value of the ADC (4095 for a 12-bit ADC, not sure what the Arduino has).
Audio files are generally 2's complement numbers. You may need to convert the data before the Arduino can play it. https://en.wikipedia.org/wiki/Two%27s_complement
simulate this circuit – Schematic created using CircuitLab
Once you are confident in the ADC, work on the other blocks. These are the blocks that you probably need.
This is a difficult problem for first year students. I didn't learn any circuits in my first year. This is more like a senior level project. Has your professor actually made a working version of this?
The laser will put a large bias on the signal. Since this is only a demonstration, you can adjust the gain until the transimpedance amplifier output is near 2 V. If this was a real application, you would need some type of automatic operation point adjustment (as BitLauncher discussed in their comment).
You will likely need a large amount of amplification. But, you need to remove the bias first. All of this will be simpler if your opamps have bipolar supplies.
After the amp, you need to add bias again for the ADC. This is the circuit in the first part of my answer.
The laser output probably has a gaussian distribution vs angle. Do you know if the photodiode sensor is smaller than the laser spot? Most photodiodes have a crude lens attached, this may be a detriment.
The mechanical configuration may make or break this project. If you assume that the mirror is a piston, you may not get enough deflection (left diagram).
If you fix the mirror on one end and cantilever the other end, you will get more deflection (right diagram).
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H: What is a solution to handle multiple same capacity lipo cells in parallel?
It seems that BMS's are for batteries in series...
If I have 3 x 1200mAh lipo cells to get pretty much a large 3600mAh 1S pack...
I believe I know that I can't just parallel wire single-cell BMS's together...
So I'm not sure, I was looking around and I could not find a BMS for parallel/1S configuration.
We pretty much just want a "giant" capacity battery pack but in smaller pieces.
I want a single charging input port... and then while in use if a cell is too low it turns off, others keep going, until they all fail or you charge before this scenario happens.
I know there are balancing chargers... we could just do that, but then our cells would be pulled without a protection board/hopefully they drain evenly.
I'm not sure if this is how RC planes do it, where there isn't a smart board on board (most batteries) but the charger deals with balancing.
Thanks for any ideas, looking for off the shelf/small approach.
AI: If you put cells in parallel, all of them will be discharged evenly, and they will all go flat at exactly the same time. There's no need for a special BMS. Two batteries in parallel are electrically identical to a single, larger battery. You can connect your large, 1-S-many-P battery to a single-cell BMS with an appropriate current rating.
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H: Replace One Centre-Tapped Resistor with Two Resistors
I have just started research and design on a small tube guitar amp and have hit the first of what is probably many uncertainties. The idea is to reuse the transformers, 7C5 power tube and 7Y4 rectification tube from an old 1950s Philco 1224 Gramophone Radio. For additional context, I'd also like to use a couple of 7F7 tubes in the preamp section, but you obviously won't see those in the schematic.
The full schematic of the original gramophone is available at the link above, but my specific question relates to (what I think is) a 1500 ohm, 10 watt resistor in the power filter section:
If my understanding is correct, then the resistor is centre tapped, from which one of the two B+ lines is taken.
I'm struggling to find a resistor (within budget) which matches this description, so my plan is to replace it with two 750 ohm resistors in series, and this same B+ line could then be taken from the intersection between them.
What I'm not sure of, if this is indeed possible, is what the power rating of these two resistors ought to be. My very sketchy understanding of Ohm's law makes me think that I need to increase their rating, but my gut wants me to cut them both to 5W.
What would you suggest?
AI: To answer this properly, we would need to know the DC current drawn from each of the 270V and 250V lines. In the absence of that information we can make educated guesses.
If we assume that after the capacitors have all charged up to their operating voltages, average current in those capacitors from then on will be zero, and we can treat all resistor currents as an average over time, DC, ignoring the capacitors. From the power rating of the 100Ω resistor, which is 1W:
$$
\begin{aligned}
P &= I^2R \\ \\
I &= \sqrt{\frac{P}{R}} \\ \\
&= \sqrt{\frac{1W}{100\Omega}} \\ \\
&= 100mA \\ \\
\end{aligned}
$$
That's an absolute maximum, and I would expect the designer to choose a 1W device if current were considerably less than this, which I'll address below.
If that current were to pass through 750Ω this would dissipate
$$P=I^2R = 0.1^2\times 750 = 7.5W$$
justifying the 10W second/third resistors. This is not really in agreement with the DC voltages shown, which imply certain voltages across the resistors, from which we can derive expected power in each resistor. For the left 750Ω:
$$
\begin{aligned}
P &= \frac{V^2}{R} \\ \\
&= \frac{{(310V - 270V)}^2}{750\Omega} \\ \\
&= 2.1W
\end{aligned}
$$
The right-hand 750Ω:
$$
\begin{aligned}
&= \frac{{(270V - 250V)}^2}{750\Omega} \\ \\
&= 0.53W
\end{aligned}
$$
That's a total of 2.6W, well below the 10W rating of the centre-tapped 1.5kΩ unit, so I suspect those marked DC voltages are no-load test values, with motor off and no input signal, for instance.
The voltages across those two half-resistors, under full load, will no doubt be significantly greater than the shown values, and I'd rather trust the 100mA maximum current estimate. Guessing that the designer would want a 75% safety margin on power, current through the 1W, 100Ω resistor would be:
$$
\begin{aligned}
P &= I^2R \\ \\
0.75 \times 1W &= I^2 \times 100\Omega \\ \\
I &= \sqrt{\frac{0.75 \times 1W}{100\Omega}} \\ \\
&= 87mA
\end{aligned}
$$
This current will all pass through the first of the 750Ω resistors, but only a fraction of that will pass through the second one, a fact which is clear from Kirchhoff's current law:
simulate this circuit – Schematic created using CircuitLab
For R2, its power dissipation while passing 87mA is:
$$
\begin{aligned}
P &= I^2R \\ \\
&= (87mA)^2 \times 750 \\ \\
&= 5.7W \\ \\
\end{aligned}
$$
Again assuming a 75% power margin, this leaves \$(0.75\times 10W) - 5.7W = 1.8W\$ for the right half of the 1.5kΩ. Just to know, this corresponds to a current drawn from the 250V rail of:
$$
\begin{aligned}
P &= I^2R \\ \\
1.8W &= I^2 \times 750\Omega \\ \\
I &= \sqrt{\frac{1.8W}{750\Omega}} \\ \\
&= 49mA
\end{aligned}
$$
By making a lot of assumptions, I am estimating:
$$ P_{R2} = 6W $$
$$ P_{R3} = 2W $$
I would advise to use a 10W device for R2, and at least 3W for R3.
Of course, all this will be made easier if you used those values provisionally, and actually measure the current through R3. That way you could know for sure.
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H: Practical example of controlled voltage and current sources
In text books some controlled or dependent voltage and current sources are shown. What are they really? Can someone explain them with real examples?
AI: Short answer
The difference between the ordinary constant sources and dependent sources is that the former have only output (the input is implicit, constant) while the latter have both input and output (actually they are converters). So:
VCVS is a voltage-to-voltage converter or voltage amplifier, follower or attenuator.
VCCS is a voltage-to-current converter or transconductance amplifier.
CCCS is a current-to-current converter or current amplifier.
CCVS is a current-to-voltage converter or transimpedance amplifier.
So the independent sources can be thought as "dependent sources with constant input quantity", and dependent sources as "independent sources with variable input quantity".
How to present circuits
In text books some controlled or dependent voltage and current sources are shown...
The problem of these textbooks is that they only show these circuit building blocks but do not explain what is inside them; so let's fill that gap. The best way to do this is by building the circuit step by step showing what the idea is at each step. Let's illustrate it by reinventing some of these famous circuits - the basic current-to-voltage converter, the dual "voltage-to-current converter", and the composite voltage-to-voltage converter.
Building a current-to-voltage converter
The main idea underlying the building of these active circuits is that they are improved passive circuits. So let’s start building the current-to-voltage converter with its simplest passive version - the resistor.
Non-inverting configuration
Passive current-to-voltage converter unloaded: In this arrangement, the input current source Iin passes its current through the resistor R thus creating, according to Ohm's law, the output voltage Vout = Iin.R.
simulate this circuit – Schematic created using CircuitLab
As you can see from the graph below, the relationship between the current and voltage is linear.
Passive current-to-voltage converter loaded: The problem with the passive I-to-V converter, as with any passive circuit, is that the input (current) source supplies the load. Let's test it by loading the circuit with the same 1 kΩ resistance as the resistor R; hence the figurative name RL1k. The easiest way to do this is to go into the voltmeter parameters window and reduce its resistance to 1 kΩ. Now it will serve as a “voltage-visualized load”.
simulate this circuit
The result of this intervention is that the total resistance R||RL1k and accordingly the output voltage drop twice. Let’s investigate it graphically for three load resistances - 100 Ω, 1 kΩ and 10 kΩ. As you can see, the impact of the load is significant.
Active current-to-voltage converter: The trick we can use to solve this problem is known as negative feedback (I prefer to call it active copying). It means to supply the load RL1k from another voltage source Vout that copies the voltage VR across the resistor R. We can do it by comparing VR and Vout with a floating null indicator NI (a sensitive voltmeter) and adjusting Vout so that to keep a zero voltage difference across NI.
simulate this circuit
Now the RL1k load is supplied by the Vout voltage source instead of Iin; so it can be low resistive enough.
Op-amp buffered current-to-voltage converter: Of course, an op-amp would do this tedious job much better than we do; so let us entrust it to the op-amp. Now it will compare its output voltage with the input one and will adjust it so that to zero the voltage difference. The name of this circuit is op-amp follower.
simulate this circuit
Inverting configuration
In the circuit of the non-inverting I-to-V converter, the input current source was perfect ("ideal"), and we have solved the problem caused by the load.
Imperfect current source short circuited: But the input source can be imperfect (made by a voltage source Vin and a resistor Rin in series as in the schematic below). It is of course expected to be short-circuited by an "ideal current load" ("piece of wire" or "ideal" ammeter). Then the current would be exactly Iout = Vin/Rin.
simulate this circuit
Imperfect current source R loaded: But we have connected a resistor R = 1 kΩ, so the current has decreased twice - Iout = Vin/(Rin+R), and the output voltage is also decreased twice.
simulate this circuit
Active I-to-V converter without negative feedback: Now we can take one more trick out of our "bag of circuit tricks" :-) In fact, it is not only electrical, but widely used in life, and it says the following: If a harmful quantity appears, we destroy it with a useful quantity of equal value. In our case, the voltage drop across the resistor is harmful; therefore we should destroy it with an equal value voltage. This means connecting an additional source -VR in series so that its voltage is added to the input voltage Vin (i.e, it must be negative to ground). In this CircuitLab simulation, this source is implemented as "behavioral" with voltage -VR.
simulate this circuit
As a result, the "undesired" voltage drop is neutralized, and the imperfect input voltage is virtually short circuited. The upper rail has zero voltage; that is why it is called virtual ground.
Active I-to-V converter with negative feedback: In life and circuits, we prefer to produce the compensating quantity by the negative feedback principle. We can do it as above, by comparing Vout = -VR and VR with a grounded null indicator NI (a sensitive voltmeter) and adjusting Vout so that to keep a zero voltage difference across NI. An interesting fact is that we use the compensating voltage -VR as an output voltage.
simulate this circuit
Op-amp I-to-V converter with negative feedback: As above, we make an op-amp to do this boring job. It "observes" the voltage of its inverting input (virtual ground), and adjusts its (negative) output voltage to keep the virtual ground.
simulate this circuit
Perfect current source: Of course, we can drive the I-to-V converter with a perfect current source Iin.
simulate this circuit
The result is the same.
Voltage-to-current converter
Passive voltage-to-current converter
We have seen above in the Schematic 1.1 how the humble resistor R can convert, according to Ohm's law, the current Iin flowing through it to a voltage drop Vout = Iin.R across it. Conversely, the same resistor can convert, according to Ohm's law, the voltage Vin applied across it to a current Iout = Vin/Iin flowing through it (see Schematic 2.1).
Active voltage-to-current converter
To eliminate the harmful voltage drop across the load (imperfect ammeter) connected in series to the resistor, we can apply the same clever trick as above - adding the same voltage in series. When we change the load resistance RL, this voltage will vary keeping up a constant current. Lets investigate it for three load resistances.
RL = 0 Ω: If the ammeter is "ideal", there is no disturbing voltage drop across it; so there is nothing to compensate and the op-amp output voltage VOA is zero. The output current is Iout = Vin/R = 1 mA.
simulate this circuit
RL = 1 kΩ: Now let's set the ammeter's resistance to 1 kΩ. A 1 V disturbing voltage drop appears across it, and to compensate it, the op-amp output voltage becomes -1 V. The output current is Iout = (Vin - VRL + VRL)/Rin = 1 - 1 + 1 = 1 mA.
simulate this circuit
RL = 10 kΩ: Finally, let's increase the disturbing ammeter's resistance to 10 kΩ. A 10 V disturbing voltage drop appears across it, and to compensate it, the op-amp output voltage becomes -10 V. So the output current is Iout = (Vin - VRL + VRL)/Rin = 1 - 10 + 10 = 1 mA again.
simulate this circuit
Voltage-to-voltage converter
Passive voltage-to-voltage converter
When we load the passive voltage-to-current converter (a resistor R1) with another resistor R2 acting as a current-to-voltage converter (see Schematic 2.2), a simple voltage-to-voltage converter (aka voltage divider) is formed.
Active voltage-to-voltage converter
As above, we can remove the voltage drop across R2, and use the compensating voltage as an output (see Schematic 2.5). Thus we obtain the famous inverting configuration. Depending on the R2 value, three versions can be obtained.
R2 = 1 kΩ: If R2 = R1, this inverting configuration acts as an inverter (inverting amplifier with a gain of -1).
simulate this circuit
R2 = 10 kΩ: If R2 > R1, this voltage-to-voltage converter acts as an inverting amplifier.
simulate this circuit
R2 = 100 Ω: And when R2 < R1, the circuit acts as an inverting attenuator.
simulate this circuit
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H: MOSFET ring oscillator LT SPICE
I am designing a ring oscillator using MOSFETS to create the inverters however, I am encountering problems with the output. Please check my understanding. Here is what I understand: the oscillating frequency should be:
$$F_{osc} = \frac{1}{2NT_{p}}$$
This is the most general case. To change the propagation delay, you can add load capacitors between each inverter stage and the frequency of oscillation can be calculated if you know the current through the transistor and the load capacitor. The frequency of oscillation becomes:
$$SlewRate = \frac{I_{ss}}{C_{L}}$$
$$T_{propagation} = \frac{V_{sw}}{SlewRate}$$
where $$V_{sw}$$ is the switching voltage of the inverter. And the equation for the oscillation frequency becomes:
$$F_{osc}=\frac{I_{ss}}{2NV_{sw}C_{L}}$$
And the inverter propagation delay is the average of the low to high and high to low propagation delay:
$$T_{prop} = \frac{T_{PLtoH}+T_{PHtoL}}2$$
So with all of this information, what I understood was that you can change the oscillation frequency by changing the supply voltage, the load capacitor, or by changing the size of the transistors. The supply voltage will change Iss. The load capacitor will change the slew rate which will change the propagation delay. Changing the size of the transistors will change the Iss current which will also change the slew rate which will change the propagation delay. Let me know if I messed up anywhere.
The next part is that if I want the output to swing from VCC/2 to VCC (I chose this arbitrarily not for any specific reason but to observe behavior), then I need to set W and L the same for both transistors. I did this and simulated the oscillator. The output is a flat line that doesn't oscillate. Here is the simulated output:
Here is the schematic:
I set w=50nm and L =1u. Can someone please explain why my inverter isn't oscillating and check if I made any errors with my understanding? I appreciate the effort. If any additional information is needed, please let me know and I will provide this information. The MOSFET models I am using are nmos4 and pmos4.
update: I added a pulse source on the feedback network and got this result
here is the schematic.
The circuit did not oscillate after adding a disturbance siganl. The disturbance signal was a pulse.
AI: Of course, you are not seeing any oscillations, as you use a default N/PMOS model, and this model is the Shichman-Hodges model, threshold-based model, which does not model device capacitances.
You can introduce device capacitances into consideration by specifying the model level parameter. Setting LEVEL=14, like in a statement '.model NL14 NMOS LEVEL=14' below, gives you the BSIM4.6.1 model:
The other directives to notice are '.ic V(inout)=0.3' -- without this directive the oscillation start is delayed; and length/width parameters of the transistors. To bring MOSFET length/width parameter to the screen, right-click on the device symbol with ctrl key pressed and mark the Vis field. The parameter values are in the field 'Value2'.
You can experiment with different model level parameter values, like 9 or 12 -- see LTspice help, only do not forget to read messages appearing in the SPICE Error Log.
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H: AC and DC inputs to a Power Supply
I am studying about power supplies and I need some help with the following. I have a power supply with a 12 V DC output to power the lower power controller electronics. This power supply has two inputs as seen in the figure below. What components do I need to put in the box to make sure that the AC source is the main primary input and the DC source is only used when the AC source is not available?
Will a diode-based ORing circuit help for such high power levels? Or are there alternate ways that are better than the diode-based ORing circuit?
Updated: Thank you everyone for your valuable comments. I tried something on MATLAB (see following pictures) and I would like to know if this is practical and can actually be implemented.
I used a breaker which will look at the ac voltage and determine if the 400 V DC should be used or not. If the AC voltage is close to zero, the breaker will close and 400 V will be injected into the system from the DC source.
Output Voltage waveform when ac voltage is turned off and the 400 V DC input voltage supplies power to the 12 V buck converter.
AI: I suggest buying an off-the-shelf PSU to generate an isolated 420VDC from the AC supply (assuming the 12V PSU can handle 420V at its input). I suggest this because the power level is up to 1kW, which is well in the range where sinusoidal line current is required on the AC supply, which is non-trivial to design and build as a one-off, and more cost-effective to just buy an existing commercial product.
Connect the 420VDC negative to the 400VDC negative, and connect the 400VDC positive to the 420VDC positive via a diode, refer schematic below:
Alternatively, get a second +12V PSU, so that each main supply feeds just one +12V PSU, and use diodes to OR the outputs of these +12V PSUs to the load. Set the output voltage of one PSU a little higher than the other to select which power source is used by default.
Edited: Update After OP Added Change-Over Contactor to Original Question
The solution suggested by the OP adds a mechanical device (called a "circuit breaker", but I suspect the correct term is "contactor") that is controlled by a comparator. Both of these devices introduce some risk of failure from various mechanisms, for example:
The contactor has "contact bounce", which can last up to 20 milliseconds, see refs below.
The voltage comparator requires its own control power supply, and means of measuring the voltage it is monitoring.
There will be a time delay from when the AC voltage fails, to when input to the 12V PSU is switched over to the DC voltage source. Does the +12V output have sufficient "hold-up time" to "ride-through" this power loss?
Switching from the DC source to the AC source requires a contactor that can safely break the DC current, before making contact with the supply from the AC source.
I would suggest the simple solution as presented in my answer here, introduces far less risk of failure, with far less complexity.
References for Contact Bounce:
Physics behind switch bounce when opening?
http://www.ganssle.com/debouncing.htm
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H: Circuit analysis of a halfwave rectifier
I want to verify whether my calculations are correct. Additionally, there are two questions related to this circuit: 'What is the purpose of R1 and R2 in the given circuit?' and 'What is the intended application of this circuit?' I am unable to think of any specific reasons or applications for this circuit type, can you please enlighten me. Thank you.
circuit
waveform
question
answer
AI: Here is my simple analysis:
When Vin is positive: D2 conducts. R2 (1k1) is connected directly across Vin, and plays no part in setting Vout (assuming Vin has zero internal impedance). So, Vout is determined by the resistive divider formed by RL(2k2) and R1(3k3).
So Vout peak = 0.40 x 40V = +16.00V ==> 11.31V RMS (divide by sqrt 2 to get RMS).
On the scope, Vout will appear as a positive half-sine with a peak = 16.0V.
When Vin is negative: D1 conducts. R1 (3k3) is connected directly across Vin, and plays no part in setting Vout. Vout is determined by the resistive divider formed by RL(2k2) and R2(1k1).
So Vout peak = 0.667 x 40V = +26.67V ==> 18.86V RMS.
On the scope, Vout will appear as a positive half-sine with a peak = 26.67V.
Assuming the frequency of Vin is much faster than the display update rate of the meter, and assuming the meter reads true RMS at the frequency of Vin, the meter reading will be the average of these two values, so:
Meter reading = 0.5 x (11.31V + 18.86V) = +15.09V.
As for practical application: I am stumped by the frequency of 0.7958Hz. Never seen this frequency used in real life, I guess it is just set by the angular frequency of sin(5t), 5 rads/sec ==> 0.7958Hz. At such a low frequency, the assumption that the meter will display the average value may no longer hold, so in reality you may see the meter display alternating between 11.31V & 18.86V - and that is assuming the meter is still reading true RMS at this very low frequency.
As for the purpose of R1 & R2: These set the other half of the resistive divider formed with the load resistor, depending on the polarity of the input voltage. Vout is higher for negative Vin than for positive Vin. I am not really sure if this circuit with these resistor values has a practical, real-world application.
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H: AM-Receiver circuit, problems with saturation?
I have a question about this specific circuit. I marked the potential-point I have "problems" with. I think there will be saturation in this point at some time. This point doesn't look to be able to discharge, because the diode is blocking, so how will you pass a signal after a while. I have a strong feeling that I miss something, maybe there is somebody who can help me out.
OA91 datasheet here
https://www.circuits-diy.com/simple-am-receiver-circuit/
AI: I think there will be saturation in this point at some time. This
point doesn't look to be able to discharge, because the diode is
blocking, so how will you pass a signal after a while.
I believe that the OA91 germanium diode will have significant leakage and therefore alleviate the problem you mentioned but, if you were thinking about building one of these then, I'd be considering adding a 10 kΩ resistor across the 100 nF capacitor with the red dot attached.
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H: Multimeter Range and Resolution
I'm confused as to how my multimeter takes readings, especially since its not an auto-range multimeter. I have to switch to the desired range to carry out measurements. Unfortunately, the resolution part is what confuses me. How do I know my exact reading?
AI: Your meter uses a DVM, digital voltmeter, module with a range of -199.9 mV to +199.9 mV (or ±0.2 V in round numbers). These are known as 3½-digit displays, the leading '1' being the ½ digit.
simulate this circuit – Schematic created using CircuitLab
Figure 1. Simplified switching diagram for current measurement ranges. Only one switch closed at a time but make-before-break contacts are likely to be used to prevent high voltages being applied to the DVM during range switching. Fuses and input protection not shown.
The current measurement ranges connect the digital display inputs across a current shunt resistor whose value will generate a 200 mV drop at the rated current. So, most sensitive range on your meter, 2 mA full-scale, will need a resistor of \$ R = \frac V I = \frac {0.2}{0.002} = 100\ \Omega\$ for the current shunt. The resolution of the display is the smallest increment it can display on that range.
Range: 2.000 mA 20.00 mA 200.0 mA 2.000 A
| | | |
Resolution: 1 μA 10 μA 100 μA 1 mA
As Andy has noted the accuracy depends on the stack-up of all the errors.
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H: I need help understanding the envelope detector part
I started reading "Build Your Own Transistor Radios" by Ronald Quan and I don't get how the envelope detector works in his TRF radio.
I know that a "classic" envelope detector looks like this:
But in the first example the D3, C7 and R7 looks like they have been "reversed" and I don't understand the way current flows and why it works. Why didn't the author choose the "classic" representation where D3 faces the C7 and R7?
AI: It doesn't matter which polarity half of the modulated waveform you choose to rectify in order to detect the audio. It works just fine for both but, in the particular case of your circuit, the author chose to rectify the portion of the carrier that was more negative at the collector of Q. It makes no difference at all in reality: -
Image from here and, as you can see, the upper envelope and the lower envelope are mirror images of each other but, they will sound exactly the same when processed into audio.
If I'd have shown the detector circuit using two diodes like this would you have been confused: -
Maybe this circuit won't confuse you: -
They can all be made to work as envelope detectors.
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H: Tiny Switch TNY289 current limit and di/dt question
I want to ask about how the Integrated circuit decides the proper (di/dt) for next cycle , the voltage across an inductor/transformer is L*(di/dt) the Integrated circuit TNY289 as I understand
it ramps up current so that (di/dt) is constant and consequently the voltage across an inductor/transformer is constant during ramp up (on time) , my question does the decision about (di/dt) for next cycle is to maintain constant Voltage on drain constant (Vsupply - L(di/dt)) ?
On what criteria this decision is taken ? to maintain what constant at what value ?
I understand also that the slope should be (di/dt)= Ilimit/Ton , to change (di/dt) does Ilimit only change or Ton also ?
I know the following figures in the datasheet are relevant but I couldn't interpret them properly to answer my questions :
One last question also concerning the following figure :
During ramp as I interpreted before (di/dt) is constant which means that voltage across the inductor is constant , while the supply voltage is constant , the result of their subtraction (Vds) should be constant but according to last figure the voltage change linearly with current , so during ramp the voltage should ramp also (not constant) according to the last figure , I feel that is contradictory ... so what am I misunderstanding / not interpreting ?
Thanks
AI: how the Integrated circuit decides the proper (di/dt) for next cycle,
the voltage across an inductor/transformer is L(di/dt) the Integrated
circuit TNY289 as I understand it ramps up current so that (di/dt) is
constant and consequently the voltage across an inductor/transformer
is constant during ramp up (on time)*
It doesn't; it contains a MOSFET that when activated puts the DC supply voltage across the transformer's primary magnetization inductance. It is V and L that determine di/dt. It's just the simple inductor equation.
to change (di/dt) does Ilimit only change or Ton also?
No, di/dt is fixed by the inductor equation. The only thing the IC can do is control \$t_{ON}\$. By controlling \$t_{ON}\$ it controls the energy delivered to the secondary of the flyback transformer. That energy is limited by the IC's ability to terminate the \$t_{ON}\$ cycle by measuring the current ramped-up to.
but according to last figure the voltage change linearly with current, so during ramp the voltage should ramp also (not constant) according
to the last figure , I feel that is contradictory ... so what am I
misunderstanding / not interpreting?
You can assume that the voltage dropped across the MOSFET (internal to the IC) is a very small fraction of the supply voltage so, in effect, we don't care if this rises a couple of volts. Ideally, we assume it always to be 0 volts and, I recommend you adopt that approach when trying to understand this type of circuit.
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H: Why do these MCU voltage dividers have +, -, and S on the output?
I'm looking at voltage divider modules like these to eventually measure a DC battery voltage with the range of ~10-15V:
https://www.amazon.com/dp/B07L81QJ75/
https://www.amazon.com/dp/B01HTC4XKY
I see the input side has VCC and GND for the voltage source. On the output side I see +, -, and S. I assume S goes to an analog pin on the MCU, but what are +, and - for? Are they drawing power from the MCU? Is the GND on the output connect to the input GND? That seems like it might cause a problem if it ends up connected to the MCU GND.
AI: If I was going to guess I would say that it's probably backward-compatible with modules that once had a buffer amplifier on board.
With cost-cutting the circuit has been reduced to two resistors and the amplifier is gone, so the vestigial power supply pin remains, but is N.C.
The circuit looks like this:
simulate this circuit – Schematic created using CircuitLab
So the measured voltage must have a common ground with the MCU ground.
The division ratio is 5:1 so a 25 input yields a 5V output (and a 16.5V input yields a 3.3V output).
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H: Why would a low-pass filter be connected to +5V on an RS422 differential line?
I am interested in a datasheet's schematic for my own PCB design of a similar system.
In my system, I am receiving an RS-422 differential line, and would simply be tempted to put a 100 Ohm terminating resistor between the differential data lines and then send them directly to the line receiver.
However, in addition to this terminating resistor (82.5 Ohms in their case), they included 147 Ohm resistors on each line to ground. What is the purpose of these?
Moreover, they seem to have put a low pass filter with a 8.25Kohm and 2.2pF capacitor, which corresponds to a cut-off frequency of 8.7MHz which is reasonable for the use case but they connected the capacitor to +5V instead of GND which I would have assumed. Why did they connect these capacitors to +5V instead of GND?
Here is their circuit
AI: In a multi-node network, the RS422 drivers each have tri-state outputs that can go into a high-impedance state to allow other drivers to drive the bus. When all of the nodes are in this state, the lines can float, possibly out of the common-mode range of the receivers. The resistance to ground is meant to prevent this.
Since RS422 was designed for long cable lengths, the two ends of a long cable often each have their own local, independent power supply even though they have connected grounds. In your circuit, the 2.2 pF capacitors are connected to the local power supply voltage on the "receive" end, which may be separate from the "drive" end of the cable.
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H: RS485 Wiring and Enables
I have an sensor with an RS485 interface that has a pinout with labels V, GND, A and B. In my system context, there will just be this one sensor and an ESP32 microcontroller running on 3.3V to communicate with it. Nothing else on the RS485 bus, it's a self-contained system. So I'm designing a little interface circuit to connect them together. I'm looking at using the SP3485EN-L chip to do the job.
The pinout of that chip has signal pins for A, B, RO, /RE, DI, DE. Does that mean that my microcontroller code needs to manage /RE and DE such that /RE is low and DE is low when expecting to receive data, and /RE is high and DE is high before sending data? I guess separate signals are available even though DE and /RE track each other, to allow for a neutral state between active states? I'm thinking I just hook up RO to a UART RX pin on the ESP32 and DI to a UART TX pin on the ESP32. Then throw a 120 ohm resistor across the A <-> B pins.
Something like this:
simulate this circuit – Schematic created using CircuitLab
I take it as obvious / given that all of these components have their GNDs connected together. Do I have the right idea? Anything I have omitted / need to watch out for?
Additional Information #1
In my application the Sensor is on the end of a 1.25 meter cable and the other end of that cable will be permanently attached (soldered) to the PCB on which the SP3485EN-L is mounted.
Additional Information #2
The datasheet indicates that the sensor adopts the Modbus-RTU communication protocol. And it appears to be a request / response prototcol.
AI: Nothing that is known wrong so far but your block design may or may not omit things on purpose.
First of all, RS-485 is not a 2-wire bus. Sure, there's two wires for differential data, but you must connect the grounds of the RS-485 interfaces together. You don't show that, but if you power the sensor and MCU from the same power supply, they might already be connected together. If you use two separate power supplies, their outputs may share a common reference (e.g. mains earth at inlet connected to supply output negative), or it may do damage (two floating power supplies).
You are correct that the bus must be terminated. But you need to be sure both ends of the bus is terminated. The sensor may or may not have a 120 ohm resistor built-in. Make sure you know that if there is an internal or or if it requires an external termination resiator you need to apply yourself. For a very short bus it might work wigh a single terminator.
You have selected an RS485 chip with 3.3V supply. RS-485 is nominally meant to be driven with 5V chips. Generally, this might not be an issue with short bus and only two devices, but you should carefully analyze or at least test the system if it will properly work with only 3.3V driven to the bus.
You can tie RE and DE together if you don't need to control them separately.
And finally what the have already said. Supply voltage connections to chips and the bypass caps are omitted. Fail-safe bias might be good to be prepared for if you need it, but also that's why the sensor may have provisions for it, if the V is a 5V output for biasing. And yes there is no protection but it may not be a problem for a short bus.
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H: Esp32 INPUT-pullup
I have an enable pin that i want to drive high always except when a limit switch is closed, and at the same time I want to monitor the state of the limit switch So is that possible with input_pull-up mode on esp32 pins?
AI: For the question, is it possible, it certainly is possible and that's why internal pull-ups exist, to keep a pin high if nothing is driving it.
However, for your specific application, we can't know if a pull-up will work in your case.
Pull-ups are quite weak, and if there is a long cable between a limit switch and the MCU, the pull-up resistance may be too weak. It might be that if you touch the IO pin even with a finger, the MCU may detect the pin toggling at mains frequency.
Flipping a light switch nearby could also cause the MCU to see a pulse.
So preparing with a real external pull-up which is much lower in resistance could be a good idea.
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H: Circuit theory basic problem
What approach do I have to take to find Vs. I don't really want an answer to this question but I want to know how to solve these circuits.
I'll first tell the approach I tried. I took KVL for all the loops, and then I was quite confused with the current directions I assumed. Please help me in figuring out the approach.
AI: I don't really want an answer to this question but I want to know how to solve these circuits.
List the information that you have. For starters, this is the schematic and this data point:
3A current source produces 12W
See if the information you have allows you to determine some voltage or currents on the schematic. via Ohm's law, KCL, KVL, etc
3A current source produces 12W, P=VI, therefore it has 4V across it (mind the polarity of the voltage, which is given by the mention it is producing power and not consuming).
3A current source is in series with 4 ohm resistor, V=RI, therefore there's 12V across the resistor.
5 ohm resistor is in parallel with 10V source, so there's 2A current through it.
Add the new information to your list and repeat until you solved the circuit.
Two voltages on top are in series, so we get voltage on the 4 ohm resistor
Thus we get current in the 4 ohm resistor
Now we know currents in 2 wires to the 3 wire node on top of the 10V source, apply KCL to get current through the third wire.
3 components form a loop and 2 voltages are known, so apply KVL to get voltage on the third
etc
Basically, write everything on the schematic and every time you spot: known voltages in series, known currents in a branch, nodes with current known in all wires except one, loops with voltage known in all elements except one, etc... then apply the corresponding rule, and every time you do so you get a new piece of information.
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H: How do the comparators in this circuit work? Do they compare the voltages between themselves? How do comparators generally work?
This is the schematic of the circuit my question references. I understand that the potentiometers are set at 2 different levels and the comparators then send out signals based on whether its above or below the charge levels, but I'm wondering exactly how they know?
AI: The two 3.3K resistors form a fixed voltage divider across the battery, producing half the battery voltage.
Meanwhile, the LM7808 provices a constant 8V, that won't change (unless the battery is really flat). This is then divided down using two more voltage dividers in the form of 10K potentiometers. But each comparator has its own potentiometer, and they can be adjusted differently.
A comparator compares its + and - inputs. If the + input is at a higher voltage than the -, then the comparator output goes high. If the - input is at a higher voltage than the +, then the output goes low. Notice how the two comparators' inputs are wired opposite ways round.
The comparators don't talk to each other, but they do both feed into the SR latch formed by IC2a and IC2b.
If you set the 10K potentiometers correctly, one comparator signals when the battery voltage is getting too high, and needs to stop charging. the other signals when it is too low and needs to start charging.
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H: FET turn-on time in DC-DC converter
I am selecting a GaN FET for a buck-boost DC-DC converter application. The Vgs of the part I'm looking at combined with the gate charge and gate resistance lets me switch the FET on in about 5.3 ns. This would be 0.53% of the period with 1MHz switching frequency. Is this fast enough for 1MHz? This is a sensitive application and the converter efficiency has to be as high as possible.
Here's the schematic of the buck-boost converter (Fig. 1. from H-Bridge Buck-Boost Converter with Dual Feedforward Control)
Source: K. Muro, T. Nabeshima, T. Sato, K. Nishijima and S. Yoshida, "H-Bridge Buck-Boost Converter with Dual Feedforward Control", 2009 International Conference on Power Electronics and Drive Systems (PEDS), Taipei, Taiwan, 2009, pp. 1002-1007, doi: 10.1109/PEDS.2009.5385893
AI: the gate charge and gate resistance lets me switch the FET on in about 5.3 ns. This would be 0.53% of the period with 1MHz switching frequency. Is this fast enough for 1MHz?
Short answer: yes.
However, the speed of the gate drive is just one of many factors that influence the overall efficiency of a power converter, and in many cases, it would have a minor effect compared to other power loss mechanisms. I would expect that power loss in the FET, which is comprised of conduction loss, and switching loss (including internal diode turn-off loss), would be much larger than losses caused by a gate drive of 5.3ns. Other components having significant power loss will be the magnetic components (inductors, power transformers), and the capacitors.
Switching loss can be reduced by implementing "soft-switching", which can greatly reduce energy lost per switching cycle. This usually comes at a cost of increased conduction loss in the FET and other components (the degree of increase depends on the method used to achieve soft-switching), however the switching power loss saving is usually greater than the extra conduction loss, thus giving an overall net benefit. Soft-switching also reduces EMI, particularly if diode turn-off loss is greatly reduced.
An introduction to the two main types of soft-switching, Zero-Voltage-Switching (ZVS) and Zero-Current-Switching (ZCS), is provided here:
https://patents.google.com/patent/US5742495A/
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H: How Should I Model Eddy Currents in a Magnetic Core?
simulate this circuit – Schematic created using CircuitLab
I'm primarily a VHDL and DSP guy, so I apologize in advance if this question is dumb.
I have wire wrapped around a magnetic core. The coil is connected to an AC source.
I want to calculate the extent to which eddy currents in that core will decrease the net flux seen by the core.
In the transformer, only the primary winding is a physical object. It is the wire wrapped around the core. The secondary side of the transformer and everything connected to it is nothing more than a model of eddy currents inside the core.
I'm hoping I can reflect the secondary circuit over to the primary side.
I have 2 questions:
1.) Should there be a capacitor in the secondary circuit?
2.) How should I estimate the parameters of the secondary circuit?
AI: In general, it will be a distributed RL network, with an overall \$|Z| \sim \sqrt{F}\$ characteristic, at least over the range of interest. This is due to the skin effect, a diffusion mechanism, which therefore has this impedance slope, or equivalently, a phase of 45°, or equal real and imaginary (reactive) components.
That fixes the slope of the function, but calculating the offset is nontrivial, and most generally will require a field simulation. Whether enough assumptions and approximations can be made to justify such a value, depends.
For practical purposes, I would suggest starting with an empirical or semi-empirical model. For example, laminated iron cores can be modeled with the generalized Steinmetz equation, \$p = C F^\alpha B^\beta\$ for some constants C, α and β, where p is the power density (usually mass density for transformer iron, volumetric (specific) density for high-frequency materials). These parameters are usually tabulated by the manufacturer and given in the datasheet.
Given core parameters, one can calculate the loss tangent of magnetizing current, or whatever equivalent core loss resistance, as reflected at the winding of interest, and extrapolate from there assuming skin effect is known and in play at the given frequency/range. (Preferably/hopefully, the loss equation is valid over the frequency range of interest, and so the loss resistance can be solved in terms of it, without having to make further assumptions at all. Mind that values may not be fit over a broad range, but only those relevant to mains frequencies, 50-400Hz for example.)
You may find the discussion here of interest,
Discussion | Calculators: Coilcraft SPICE Model Converter | Seven Transistor Labs
in many real cases (core loss and wire skin effect), we can approximate frequency-dependent resistance as a Warburg (diffusion) element, which in turn can be expressed with a circuit such as:
where the R and L values are in a geometric series.
Another example can be seen in this equivalent model,
Source: my site, CurveFit3.png
L5-L7 and R4, R6, R7 approximate the shallow-rising impedance in the 20-400 kHz range. The part uses a very thin strip-type core material (nanocrystalline), which therefore exhibits skin effect, which dominates its impedance in this range.
As for flux:
Skin effect is a self-shielding effect, preventing magnetic field from reaching the center of the conductor. Cross-sectional area therefore drops at a corresponding rate (hence this curve manifests for both conductor and core losses). This might cause less flux to be seen by the core overall, or the remaining cross-section is driven more strongly (i.e., the same given magnetic field strength, but \$A_e\$ is smaller), and thus driven closer to saturation, which acts to further increase core losses.
For solid materials, I'm not aware of a simple calculation, even for common geometries such as a cylinder inside a solenoid coil. Further reading might be found in texts on induction heating; though I don't have any recommendations handy unfortunately.
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