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H: Changing gate turn off voltage of SiC MOSFET from 0V to -4V The design of sic gate driver circuit is designed to work at 0 V as gate turn off voltage. Due to some undamped ringing at turn off, I want to change the gate turn off voltage at -2 or -4V which is generally recommended by all manufacturers to avoid false turn on due to low gate source threshold voltage. I wanted to ask how I can achieve that? Turning in the Rgon and Rgoff does not have any effect on this so option left is tuning in capacitor value but in this gate drive circuit, the only external capacitor added is between gate and source so should I tune that to achieve negative turn off voltage? Thanks AI: Simple approach is to drive gate through series capacitor C1 with capacitance so with R1 the Vx voltage at the end of Ton falls to about half. During Toff you see the Vx voltage goes negative and would reach the 0V for very long time (much longer then Toff). So Vx stays in safety negative zone. Note: The voltage levels in diagram are for standard mosfets so for SiC use datasheet values.
H: H11L1M optocoupler is inverting I'd like to protect a serial connection with a H11L1M (I can easily get some at work and it works from 3 to 16 V). The problem is this optocoupler is inverting and has the following truth table: Input Output H L L H Is it possible to drive the LED from the anode? I mean when the device is not emitting on TX, the LED is high (so the output is low) and when TX is high, the LED is not grounded so the output is high. Would that work? Do I need to add a pull-down resistor? AI: The optoisolator is not inverting, it works like all other optoisolators basically. Of course it may depend on your viewpoint but it does not change how it or all other optoisolators work. There is no logic input to LED so you can define how it works. There is no definition of high input, but it means LED being on. When there is current through LED, there is also current through output on normal optoisolator, and typically this is wired so that a normal opto will pull a wire low for a data line. This just has logic level output instead of open collector, but very weak, so you need a pull-up anyway. If you want output to be low when input is low, you connect the LED so that when TX is low, it will turn on the LED, which will pull output low and your RX is low. That's exactly how your schematic already works. The turn-on time and turn-off time max of 4us can limit your baud rate severely. It does say typically 1us and 1 Mbps with NRZ coding, but max is still 4us. The pull-up resistor is from datasheet examples so it should work fine. As 115200 bps has 8.68 us per bit, it might not be a good idea to use an optocoupler that can skew the signal by about 46% of the bit length. For example, in MIDI, the requirement is much stricter, 2us max skew with only 31.25 kbps, but in that system, the signal could go through multiple optoisolators.
H: Design Suggestions for an Optocoupler Relay Module I have designed this module to operate with input voltages of 5V and 3.3V (common in most MCUs). Additionally, I have equipped it with an optocoupler to isolate the MCU from the power section of the circuit. I wanted to know if you have any design or optimization suggestions? AI: The optocoupler fills no purpose, get rid of it. And as already noted by @Spehro, the MOSFET is completely overkill. It's rated for 49A(!). The only components you need: The relay of whatever coil voltage that makes sense - not important. A simple SOT23 N-channel with decent VGS characteristics that can handle 3.3V logic. For example SSM3K339R. The flyback diode. 1N4148 will do fine. (optional) Two resistors for the gate, for example 10k series + 10k pull-down. 10k series will protect the MCU, pull down will keep the MOSFET stable while the MCU is booting.
H: Reading 4-20 mA industrial pressure sensor I am trying to read an industrial pressure sensor (datasheet) with range 0-10 bar and output 4-20 mA, with an Arduino Opta RS485, powered from an external 12 VDC source. Leaving the sensor in the air, not connected in any process pipe (-> 1 bar) and using a 470 Ω resistor in order to convert 4-20 mA into a 0-10 V signal that the Opta can handle, I expected a reading of ~2.6 V (-> 5.6 mA.) I am instead seeing a reading of ~ 1.6 V which would land below the 4-20 mA range. Is expecting 1 bar out of the pressure sensor in plain air wrong, or is there a problem with the connections? Does anyone have experience with reading 4-20 mA pressure sensors and had similar problem? AI: According to the data sheet, your load resistor must be \$R\le(\text{V}_{\text{CC}} - 8 \text{ V})\cdot 0.02\text{ A}\$, which in your case would be 200 Ω.
H: Name of this 4-pin fan connector I have a 40mm fan with a connector that has standard breadboard pin spacing. I would like to connect it to what I thought was a relatively standard fan connector that has wider spacing (and thicker pins). In the image below, the fan is wired to the connector on top; I'd like to connect it to the connector on the bottom: What is the name of the larger connector? That would make it easier to find an appropriate adapter. AI: They are both: single-wall wire-to-board connectors. But ... Top: CPU fan connector female plug. 2.54 mm pitch, unlatched, compatible with 3 and 4-circuit PCB headers. (my site) Bottom: JST VH male PCB header: 3.96 mm pitch, latched. (my site) Note: even if you have the matching plug, that doesn't mean that it will work. We don't know whether the PCB male header is intended for a fan, and, if it is, what its pinout and signaling is.
H: Monopole antenna with coil design (Note: I'm a beginner in antenna theory) When browsing for low cost antennas online, there seems to be class of monopole antennas that have a coil or two built into the monopole, and are advertised to be suitable for operation in the GHz range despite being 200~300 mm in length. For example: Quectel YXH001AA with a real datasheet Generic aliexpress antenna From my understanding, the coil is meant to be a loading coil that adds inductance to the circuit to cancel out capacitive reactance from a shorter length antenna (e.g., when the monopole is shorter than a ¼ wave). But in this case, the antenna is a lot longer than a ¼ wave for its operating frequencies (~75 mm for 1 GHz), which usually means the antenna is inductive rather than capacitive? How does the loading coil work in this case? Is it even a loading coil at all? There's also a few other components in the monopole whose purpose isn't clear to me: Small cap at the tip of the antenna. I assume this is purely for mechanical reasons, and doesn't have any significant electrical role? Thicker section of the antenna. No idea what this is for. Maybe mechanical for wind-loading reasons? Loading coil-like helix as mentioned above Pedestal which I assume acts like the ground plane, but it sure is tiny Image adapted from: AliExpress - OpenSourceSDRLab Store - 700MHz-2700MHz SMA Antenna for HackRF One Overall, my questions are: What are the highlighted components of this monopole, and what are their functions? How does such a long monopole operate in the GHz range efficiently? Are there any general design rules for such an antenna, such that I can tell the antenna's operating frequencies/gain/etc from a few quick measurements, or build one for a specific frequency? AI: advertised to be suitable for operation in the GHz range Marketing will literally claim anything to sell an antenna; that's very much their job. An antenna that doesn't come without a plot of efficiency over the relevant frequency ranges (or S11 or VSWR whatever sensible measurement relevant to you) should simply not get bought, no matter how cheap – anyone can sell you a piece of wet wood and claim it's an antenna for the 50 Hz – 12 GHz range. Promise! Notice how even the reputable quectel antenna is sold as an antenna for frequencies up to 5 GHz – in whole bands this thing never gets better than 30% efficiency, see the image from the datasheet you linked to below. It's an antenna in these bands, alright, but is it a great antenna? No. Might a much smaller antenna have worked better, at least one band in isolation? Yes. The radiation patterns, even for the lower bands, are surprisingly anisotropic, considering the device's symmetry. My bet is on "used a rectangular ground (10 × 15 cm) plane sufficiently smaller than a wavelength for it to have effect on the antenna pattern"; that of course raises questions on the qualification of the tester. From my understanding, the coil is meant to be a loading coil that adds inductance to the circuit to cancel out capacitive reactance from a shorter length antenna (e.g., when the monopole is shorter than a ¼ wave). Let's look at the one band that the quectel antenna is actually good in (VSWR < 2): ca 1.8 GHz to ca. 2.3 GHz. Wavelength at 2 GHz is 15 cm, quarter-wave monopole would hence be 3.75cm long. This antenna is much longer than the wavelength it works well at. So, for that band, the coil can't be used to electrically enlarge the antenna. OK, so let's look at the lowest frequency they advertise, 700 MHz. Wavelength would be 42.9 cm, quarter of that would be roughly 10.7 cm. So, the antenna, being 28.5 cm long, is still much longer than that. So, no. This is not an electrically short antenna. The coil might be a mechanical element – to make this outdoor (and probably automotive-mounted) antenna resilient to wind load and vibrations. Of course, the coil affects the behaviour of the antenna, and thus the electrical design was done around it. Or maybe it wasn't; after all, the antennna really isn't that great for a lot of the bands it gets advertised for. But I think it was – the antenna doesn't behave really badly anywhere in the intended band, and achieving that is also not easy. So I think what happened here was a design process where the coil was included for mechanical reasons, and to make the antenna have different electrical lengths for different frequencies, and then the number of turns and the position of the coil was optimized to give an acceptable performance over the whole frequency range. Small cap at the tip of the antenna. I assume this is purely for mechanical reasons, and doesn't have any significant electrical role? yeah Thicker section of the antenna. No idea what this is for. Maybe mechanical for wind-loading reasons? that, or maybe some higher-\$\mu_r\$ material to, like the coil, make the antenna seem shorter for high frequencies, in order to achieve some "generally acceptable" design. Pedestal which I assume acts like the ground plane, but it sure is tiny The pedestal goes onto the ground plane, which the user has to supply, e.g. in the form of a metal car roof. (typically, the outer conductor of the coax feed is slightly coupled capacitively to that ground plane, but that makes surprisingly little difference in practice, in my experience). How does such a long monopole operate in the GHz range efficiently? It doesn't, aside from that one range, where the frequency-dependent behaviour of coil, "???" component and the monopole rod kind of compensate each other well. Are there any general design rules for such an antenna, such that I can tell the antenna's operating frequencies/gain/etc from a few quick measurements, or build one for a specific frequency? Since you have very few parameters to optimize: length of antenna turns of coil position of coil position of ??? component you'd probably just go into your microwave design tool of choice, set it up to run a simulation over a few hundred sensible combinations of these parameters (VSWR of a single rod is not going to take extremely long to simulate in e.g. CST), come back the next morning, pick one or two of the best results, and if you feel like it, optimize that a bit finer. Note that it's not easy to rule out that specific parameters where given in a non-electrical manner. For example, this being an automotive antenna, there might be end-user preferences for an antenna that looks like a high-quality antenna to someone who's not studied electrical engineering, i.e. a long rod, with something that looks like a coil.
H: How to determine voltage level of the ultrasonic transducer? I am designing the generator for an ultrasonic transducer for a cleaning system and I am not sure how to set the output voltage level. I measured the voltage level of the existing products, peak voltage was around 150V ~ 200V. When I searched for information about the ultrasonic transducer, there is no specific output voltage level. It does not show output voltage like this. What I'm confused about now is this: If the output power of the 20kHz transducer is 100W, does that mean the output power at the resonance frequency of 20kHz? If 1. is right, then if the impedance of the transducer is 25ohm at resonance, the output voltage should be 50V (from P=V^2/R.) In fact, 50V is too small for what I'm used to seeing. What am I missing? AI: In your output power to drive voltage equation, you are not allowing for the conversion efficiency of the transducer. A quick review of the literature suggests conversion efficiencies of 20-40%, with the normal for typical systems being at the lower end of the range. Thus if you are seeking 100W of ultrasonic power, you should expect to put in around 300-500W, and given a 25R load this equates to around 85V-115V RMS drive.
H: Op-amp - Lead compensator design I would be very happy if anyone can help me find answer regarding to questions below: The lead compensator is added to the system to increase the phase margin. 1'st picture is related to the uncompensated loop gain-phase graph. 2'nd picture is the summary of the lead compensator. Poles and zeros are calculated to be added to our uncompensated transfer function. 3'rd picture is the bode plot of lead compensator calculated to be added to the system. My question is how did they calculate the compensator dc gain stated at the bottom of the 2'nd picture as Gc0= (fc/fo)*2x(1/Tco)x sqrt(fz/fp). I could not undestand that. Source : Indus Electric Offical - Power Electronic 3 4 6 Design Example - https://www.youtube.com/watch?v=ABY43mX7UQo Source : Indus Electric Offical - Power Electronic 3 4 6 Design Example - https://www.youtube.com/watch?v=ABY43mX7UQo Source : Indus Electric Offical - Power Electronic 3 4 6 Design Example - https://www.youtube.com/watch?v=ABY43mX7UQo AI: You need to design your active filter - the compensator - so that it exhibits a gain of 20.6 dB at 5 kHz. Calculate the magnitude of the filter with the selected pole-zero pair. This pair is positioned to meet the targeted phase boost: \$\|G(f_c)\|=G_0\frac{\sqrt{1+(\frac{f_c}{f_z})^2}}{\sqrt{1+(\frac{f_c}{f_p})^2}}\$. You know that this magnitude should compensate for the 20.6-dB attenuation at 5 kHz. Knowing the pole and zero selected for boosting the phase by 52°, what should \$G_0\$ be so that \$\|G(5\;\mathrm{kHz)}\|=20.6\;\mathrm{dB}\$: You can also have a look at my free 90+ ready-made templates running on the demo of SIMPLIS for most of them. There are plenty of converters with an automated compensation procedure and the buck in VM and CM is there. The expression used by Pr. Erickson in the 2nd picture, considers the high-frequency response asymptotes of the power stage \$H\$ and the compensator \$G\$. We know that the loop gain magnitude \$\|T\|\$ must be equal to one (or 0 dB) at the selected crossover frequency \$f_c=5\;\mathrm{kHz}\$. The power stage transfer function is \$H(s)=H_0\frac{1}{1+\frac{s}{Q\omega_0}+(\frac{s}{\omega_0})^2}\$. If you consider that the crossover frequency is after the resonance \$f_0\$ - which is the case for proper compensation of a VM buck converter - then, you can write \$H(s)\approx H_0\frac{1}{(\frac{s}{\omega_0})^2}\$. In magnitude, you thus have \$\|H(f_c)\| \approx H_0(\frac{f_0}{f_c})^2\$. Same goes with the compensator: \$\|G(f_c)\|\approx G_0\frac{\sqrt{(\frac{f_c}{f_z})^2}}{\sqrt{(\frac{f_c}{f_p})^2}}\approx G_0 \sqrt{\frac{f_p}{f_z}}\$. Now, if you write the complete loop gain magnitude observed at crossover, you have: \$(\frac{f_0}{f_c})^2H_0\sqrt{\frac{f_p}{f_z}}G_0=1\$. Solving for \$G_0\$ which is the dc gain of the compensator, you have \$G_0=(\frac{f_c}{f_0})^2\frac{1}{H_0}\sqrt{\frac{f_z}{f_p}}=3.67\$.
H: Determining current magnitude Here is problem 3.9 from Hayt "Engineering Circuit Analysis". I reduced it to single voltage source, keeping direction of current the same as indicated by arrow. simulate this circuit – Schematic created using CircuitLab Solving it gives me current of 54A, while answer is -54A.What am I missing? AI: Add your voltage sources again. Have you got your V1 correct?
H: Which power source is good for my project? I want to create an inverter LED light source. I would be using 2 COB LED lights rated at 4 volt DC, 8 watt. My idea is that when the phase is connected, I want the light to glow and at the same time charge the battery. When the phase is not available I want the bulb to use battery back up and glow. For an I AC to DC converter, I have two options: Option 1: transformerless power supply: simulate this circuit – Schematic created using CircuitLab Is the circuit diagram is correct? Option 2: transformer power supply: simulate this circuit Is this circuit diagram correct? Which one is beginner friendly? AI: The first circuit - capacitive dropper - is totally unsafe, it has a direct connection to the mains. I'm not going to comment on that circuit further, except to note that several important component specifications for mains connection are not shown on the diagram. The second circuit is much safer, with its isolation from the mains, meaning only the L/N transformer terminals are unsafe. It's a reasonable circuit for a 5 V supply, though the specified transformer output voltage might be a tad low for the regulator dropout voltage, given silicon diodes and C1 droop when supplying nearly 2 A to fully light your LEDs. However, if you had to ask the question, I'd guess your electronic skill and awareness level is not really up to keeping you properly safe from ANY DIY thing connected to the mains. I would advise you to buy a plug-in wall-wart type of power supply delivering 5 V.
H: Why are smoothing capacitors useful/why do they work Okay so from my understanding and looking at the equation for the impedance a capacitor has, the high frequency signals would be relatively easy to be sunk to ground (if the capacitor was grounded) and hence the decoupling caps near ICs. So (I think) from that perspective I'm okay. But it's the big capacitors, say for example on some ESCs, power supplies or super caps for car subwoofers that I don't understand. From my understanding, the discharge and charge rate are both equivalent assuming the resistance on the charge side is the same as the discharge side. People I ask say it's because it supplies charge when there's like a surge of power needed and eases load from the supply, but surely when there's a say high demand (say bass from the sub), then the second the bass has done, the capacitor would need to equally recharge the same amount (and the same current), hence I can't see what benefit this has to the supply. Even then, my mind would be telling me it's also trying to charge the cap up equally during a power requirement to keep the voltages the same as its parallel to the load (the cap). I suppose on the case for the car, there would be long wire from the battery to the rear sub and inductance, so it would be advantageous since the charge rate would be slower than the discharge rate if the cap was right next to the speaker, but there's many times when I see the bigger caps on circuitry where I doubt it's the case. Hope my question makes sense, AI: How to explain concepts The OP's question is conceptual and requires a conceptual answer. But how do we explain concepts? Concepts are basic ideas that are generally non-electrical. Therefore, the first means we can use associations with well-known life phenomena (analogies). The next means by which we can make the transition to specific electrical circuits are equivalent electrical circuits. They are cleared of details that only make it difficult to understand the idea. "Dynamic self-buffering" When something (such as money, food, water, etc.) is lacking at some point in life, we need help. It can be external (we find a sponsor) but we can also help ourselves (as we have saved it in advance). In the first case we consume else's funds and in the second our own. In electronic circuits this is called buffering. Because the circuit buffers itself, and only for a short time, hence this figurative "dynamic self-buffering" name (fabricated by me:-) "Dynamic self-buffered voltage divider" The OP's configuration can be thought as a voltage divider where the wire and source resistance form the upper resistor R1, and the load is the bottom resistor R2. Also, a big (decoupling) capacitor is connected in parallel to the divider output (R2). This technique is widely used in circuits. To understand at the lowest level how the concept is implemented, let's build the circuit and explore its operation by the help of the CircuitLab DC Live Simulation in a few steps. To do this, we must "get rid of the tyranny of time" by replacing (emulating) the charged capacitor with a voltage source. Imperfect voltage source loaded R2 = 1 kΩ: Initially imagine a 1 kΩ constant load resistance R2 so the output voltage is half the input voltage. simulate this circuit – Schematic created using CircuitLab R2 decreases twice: If, for example, we connect another 1 kΩ resistor (load) in parallel to R2, Vout decreases. simulate this circuit R2 increases twice: Conversely, if we connect the 1 kΩ resistor in series to R2, Vout increases. simulate this circuit Imperfect voltage source buffered Slowly changing load: Now let's connect a big "capacitor" (a behavioral voltage source C copying the voltage drop across R2) in parallel to the divider output (R2). Also, connect an ammeter to monitor the current I through the "capacitor". The ammeter has to have some minimum resistance (1 Ω set in its parameters window) to decouple Vc from VR2; otherwise a vicious circle results (Vc is a copy of itself) and CircuitLab reports an error. If R2 slowly decreases, the "capacitor" slowly discharges, and Vc follows Vout. No current flows through C, and the load is entirely supplied by Vin. This technique is known as "bootstrapping" and is used to virtually increase resistance. simulate this circuit If R2 slowly increases, the "capacitor" slowly charges, and Vc follows Vout. No current flows through C again, and the load is entirely supplied by Vin. simulate this circuit Rapidly changing load: To imitate it, we have to replace the following behavioral voltage source with a constant voltage source, and repeat the experiments above. If R2 rapidly decreases, the "capacitor" does not change its voltage and supplies the load (in cooperation with Vin). simulate this circuit If R2 rapidly increases, the "capacitor" does not change its voltage as above and sinks the load current (like a Zener diode). simulate this circuit Practical circuits Let's finally investigate two practical circuits of imperfect 10 V voltage sources with 10 Ω internal resistance R (including the wire resistance) - first without, and then with backup capacitor C. They are loaded by a 100 mA pulse current source IL that "pulls down" for one second the output at the 50th and 100th second (it is implemented as a programmable so-called CSV current source from the CircuitLab library). Unbuffered imperfect voltage source First let's disconnect the capacitor. The result is obvious... simulate this circuit ... the output voltage drops to ground... ... when the load current "jumps" to 100 mA. Buffered imperfect voltage source Then let's restore the capacitor. simulate this circuit Now the output voltage slightly drops... when the load current "jumps" to 100 mA. Conclusions A capacitor connected in parallel to the load acts as a "backup battery" that can dump short load changes. The larger the capacitance, the longer the load voltage drops can be, but the time to recover the charge (the time between two adjacent drops) will be longer.
H: MOSFETs stabilizing current in coils keeps burning, how to protect them? I am trying to stabilize the current in coils in my experiment. For that I am using a circuit as in the picture: First section is a fast switch. It is also galvanically isolated from the TTL signal with opto-coupler (not in the picture) Second section is fast discharging of the coils. When we suddenly stop the current from the supply, the coils respond in reverse voltage build-up opening the diode. Then in quarter of a cycle of the LC circuit the energy flows from the coils to the capacitor and the diode closes. Then it slowly discharges through the resistor. Coils inductance is 350 uH. Third section is linearized MOSFET. I am using OPA277 here. It linearizes the response of the MOSFET by comparing the voltage on the sense resistor with the input and adjusting the gate voltage. 10R resistor is added to reduce gate ringing of the MOSFET. It is connected to the PID control (I am currently using RedPitaya for that). Current measurement for the PID is done independently with a current transducer. In the circuit there are 4 such sections connected in parallel to lower the power dissipation. What my problem is, that when I am sending larger currents (a few amps) after some time the MOSFET responsible for current stabilization burns. Firstly I thought that it is due to heating up, but it is placed on a water cooled aluminum casing and its temperature doesn't rise. Then I added additional clamping Shottky diodes bypassing the body diode of the MOSFETs (each transistor got one, directly on the terminals of their casings) because I thought it is due to high reverse voltage. The fast discharging setup lets the current discharge in around 100 us and thus large reverse voltage is generated (I calculated it to be around 414 V at 70 A - largest current I want to use). I have run out of ideas what could be the problem. I would be glad for some explanation what can cause the burning of the MOSFETs and possibly how to protect them. AI: The thermal resistance of the MOSFET junction-case interface, compared with the thermal capacity, coupled with thermal runaway, makes it very easy to burn out these device before the case even gets warm. Here's an excellent app note on the challenges of MOSFETs in linear mode. You may well be better using an IGBT for this kind of control. There are some very high current modules with excellent thermal bonding to avoid exactly these kind of problems, but same gate drive as your existing MOSFETs. Datasheet for a Vishay example of similar physical size here, but for more money they can be had all the way up to 7200A! Note most IGBT are not designed for linear use, but are more stable in this mode than equivalently rated MOSFETs. As noted in the linked app note, older generation devices (which tend to have bigger dies) and higher voltage ratings (which also tend to have bigger dies) are generally better in linear mode.
H: Buck Converter - C_OSS charging up loss Consider the following synchronous buck converter: where Q1 is the high-side and Q2 the low-side (https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/buck_converter_efficiency_app-e.pdf) When the high side Q1 device turns on, it will charge up the C_OSS of the low-side Q2 device. In the app note above, it states that this charge is usually ignored because eventually that charge on the C_OSS of Q2 will flow to the load and hence not be wasted. However, and this is my question, when C_OSS of Q2 is being charged up in the first place (i.e. when Q1 high-side turns on), that is essentially a voltage source Vin charging a capacitor C_OSS of Q2 which is inherently a lossy operation (Is the 50% loss of energy when charging a cap from a battery a set rule in stone?) The discharging of Q2 C_OSS is loseless due to the inductor discharging it, however the charging up of Q2 C_OSS is not via the inductor, it is via the Vin and hence it should be lossy. Why is the loss associated with the initial C_OSS charging of Q2 (low-side) when Q1 (high-side) turned on being ignored here? AI: Is the 50% loss of energy when charging a cap from a battery a set rule in stone? Yes it is. Why is the loss associated with the initial C_OSS charging of Q2 (low-side) when Q1 (high-side) turned on being ignored here? It shouldn't be ignored; it's a real loss.
H: Earth for custom POE+ board design after getting the center tap pins for poe, I have an example schematic to design an EARTH ground. I have the understanding that that would be our Earth in AC over cabinet. That would remove our value for doing this entire poe design, as we only want the ethernet line coming into the design. How can I provide "Earth" in this case. Can I just share it with ground on the pcb? The reality is that our design will utilize a pse with poe+ type B, but that isn't the scope of our PD. We want this to be 802.3 at compliant. So we must rectify, regardless if our pse is DC constant. With that in mind, what engineering technique should I follow to provide ground/ Earth in this image? AI: That's not "Earth" literally, but it could be. It depends on your exact scenario, but if your RJ45 socket has a metal shell, it connects to that, as it might be Earth if you are using an STP cable whose shielding connects the metal shells of connectors together. If you have a metal enclosure, the RJ45 metal shell should in general connect to the metal enclosure. For example a generic desktop PC will have RJ45 metal shell connected to metal chassis, and the metal chassis connects to PE via mains plug, so it will be earthed. And that's what you need to do whether or not your design uses PoE. These are unrelated. If you are doing a PD, it depends if it must be isolated or not. If there are no other connections then the innards can be non-isolated, but if there is a possibility for someone to connect something so that the PD cannot be non-isolated, then you need an isolated PoE converter.
H: Buck Converter - Coss Loss From: https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/buck_converter_efficiency_app-e.pdf Can someone explain why the high-side MOSFET causes a loss due to its C_OSS. The charge from the C_OSS flows to the load, so why is it considered a loss? In a sense, the C_OSS charge from the high-side does not flow to ground, it flows to the output, so it is useful charge being supplied to the load. AI: Assuming IL is positive when you turn your high side switch on (Minimum inductor current >0), VSW will start at about -0.7V due to low side diode conduction during the dead time. Because of this, the current you put into VSW will initially have a return path through ground, since it has to conduct at least ILmin amount of current before the low side diode can turn on and allow VSW to start slewing high. Edit: Think of Coss as a capacitor between VSW and IN. Right before you turn on your high side switch, this capacitor has V(IN) plus a diode across it. When you turn on your high side switch, you are discharging this capacitor. The current loop is local; it's just from the top of the capacitor, through the switch, then back into the bottom of the capacitor. This does not go to OUT.
H: Will capacitors that are connected between GND and Vcc to a CPU impact the capacitance between the same pins on other components? I am working on a pcb that has to have a CPU with capacitors between its gnd and vcc pins, other components like sensors also have to have capacitors connected to them for whatever reason indicated in the datasheet, and these capacitors are also connected between gnd and vcc, but capacitors between the 2 pins will impact the overall capacitances on the entire board. For example, if I need a 10pF capacitor between vcc-gnd pins of a CPU, and another one between vcc-gnd pins of a sensor, the equivalent capacitance will become 20pF, and if these kind of connections are too frequent, I will end up with a huge equivalent capacitance that may not work well for those components. AI: Yes, but. Decoupling capacitors work best when they're as close as possible to the pins of the IC (some ICs even have internal decoupling capacitors placed directly on top of the silicon die itself). A capacitor providing decoupling to one chip will not necessarily be adequate decoupling for another chip a few inches away, even if it's nominally enough capacitance for them both. At low frequencies (e.g. when measured with a multimeter), two capacitors associated with different chips will indeed measure as the sum of their capacitances. But at higher frequencies the impedance of the connecting traces (which is most of the reason these capacitors are used!) will become significant. Outside of the outputs of amplifiers, it's unusual for too much capacitance to cause a problem, especially if it has significant series impedance (due to being halfway across the board). Note that linear regulators are amplifiers and can exhibit this type of instability, though modern ones are typically more tolerant of large output capacitances. Switching converters, as long as they use some form of soft-start, are unlikely to go unstable, though the cheapest ones might have issues starting up into a 10 mF load. Decoupling capacitors halfway across the board are not generally something you will need to worry about for any chips other than your PMICs, and then only in fairly extreme cases. Also, you're extremely unlikely to be using 10 pF capacitors for decoupling. It's usually 100 nF for most chips, a few to a few dozen μF for regulators, and probably somewhere in the 1 to 100 nF range for complex CPUs and FPGAs (times a lot, for the dozens of power supply pins that need decoupling).
H: Problem with the output of a synchronous non-inverting buck-boost converter I found this electronic circuit in an old research, along with the code necessary to operate it. When I applied it in the laboratory, the results were not the same as in the original research, not even close. The voltage on the capacitor is equal to the battery voltage, and this is what I do not want. This "synchronous non-inverting buck-boost converter" must output a voltage higher than approximately 13.5 to charge the 12 V 7 Ah battery. The primary source for this circuit is a 50 W solar panel. I have checked all the parts, connections, and even the code, and I still do not know the reason. If this converter does not work, I suspect the reason may be the MOSFET gate driver connections. I tried to contact the person who did this research, but unfortunately, I did not find any email for him. What are your suggestions? I fixed the position of the capacitors and I made my power supply "solar panel" at 17 V, and it started giving me 13-14.5 V at the output of the converter but it's not stable and the input of gates for left MOSFETs "buck leg" will be like the picture below, how can I fix it? The Arduino code is generating 10 kHz signals. AI: You are correct, it can't work because the gate driver schematics have an error. Capacitors C2 and C4 are not correctly connected. Please fix it by reading the IR2104 data sheet for examples.
H: Inverting opamp amplifier: frequency response not compatible with LTspice simulation I have a simple inverting opamp amplifier and I want to study the frequency response of the circuit and finally calculate the frequency band (or cutoff frequency). Unfortunately the model created in LTspice gives very different output from the data I collected doing the circuit manually in laboratory. What I get is a very different cutoff frequency, but the amplification is okay. I'm gonna link to you the pictures of our frequency response with our data, and then also the circuit we use in LTspice and the output. As you can see in the LTspice simulation cutoff frequency is something like 1MHz but in our data we estimated it to be 200kHz more or less. AI: Looks like you are using a behavioural opamp model. If so, you need to adjust the gain-bandwidth (GBW) of the model to match the GBW of the TL082 which is typically 3 MHz. Depending on the breadboard system you are using, the contact capacitance can alter the operation of the actual circuit. In the simulation below, the UniversalOpamp model GBW is set to 3 MHz and 3 pF was added to the feedback capacitor which mimics the breadboard capacitance which gives a -3 dB frequency around 200 kHz. It is better to use the SPICE model for the actual part. You can download the model from the manufacturer which is on Texas Instruments web site for the TL082. This is a PSpice model which is normally compatible with LTspice.
H: Should two different DC power supply GNDs be connected to each other on a PCB? I'm making a small project that drives a few DC motors with H-bridges. +12V DC will come from one DC power supply (regulated to 10V for motors,) and then +5V will come from another (different) DC power supply for some logic controls. Since these are two separate power supplies, should the GNDs be connected or isolated from one another? If so, how? Should I just connect the GND of both DC power supplies to the GND plane on the PCB, or should I bring in the +5V and not connect the +5V GND at ALL, and just reference the GND from the +12V on all the ICs? AI: You would usually connect all the supplies on a single board together back to one GND. Some would suggest you seperate digital and analog grounds in sensitive systems but I don't think this applies here (and I wouldn't recommend it personally anyway.) I presume at the point of the H-bridges, the logic part of your circuit that's powered from 5V, will need to controll the flow of the 12V for your motors. At this point, if your two supplies are isolated (GNDs unconnected) this part of the circuit might not work at all, or as expected. In this application, you should connect the two GNDs with a strong connection (ideally a GND pour) and ideally have the two connectors mounted reasonably close together.
H: Pulling pin low through PNP BJT? I'm using a battery charger/buck regulator IC that turns on if the pin named "shphld" is momentarily pulled low, and turns off if the pin named "shpact" is momentarily pulled high. When the IC is on, it outputs regulated voltage on VOUTB. VBAT is always connected to the battery, the 100K resistor is specified by the datasheet to ensure shphld is not floating while the system is off. I was wondering if I could use some sort of transistor to allow one button to control both powering the circuit on and off, depending on if VOUTB is outputting or not. I mocked up a schematic with a P-channel mosfet that I think should work, however I do not have a PMOS to test with. I tested the same circuit wih a BJT (PNP) in place of the PMOS, but that did not work for some reason. Pulling SHPACT high trough the 100k resistor worked fine, but pulling SHPHLD low through the transistor did not. Since it did not work with the PNP, will it or will it not work with the PMOS? AI: I think what's happening is that when the regulator is off (floating output) and the switch is pressed, there is a potential divider chain formed from the 100k resistor, Vbe (of the pnp transistor), R1 and the LED which results in SHPHLD not being pulled down far enough (maybe down to 1.5 V) Try adding a 1k resistor between the base of the pnp transistor (VOUTB) and ground. This should result in SHPHLD being pulled to a lower voltage when the switch is pressed (maybe down to 0.5 V). The drawback of this is higher current drain. If this is the cause of the problem then a pfet may also cause problems because of the Vgs voltage not letting the fet pull the source close enough to ground even though the gate is being held at 0 V by R1 and the LED. THEORY 2 It looks to me like the regulator's output will cycle on and off whilst the switch is being pressed so, to slow down the cycling try splitting the 100k resistor into two separate series resistors (say two 51k resistors) and add a capacitor (say 10uF) connected from the junction of the two resistors to ground. Now when you press the switch the regulator's output should change state (on to off or off to on) after a short delay but then the switch must be released before the regulator's output changes state again. You can adjust the size of the capacitor and the ratio of the two resistors to adjust the timing to suit. If my theory is correct this should work with a pnp bjt in place of the pfet.
H: Pulling Receiver Enable Low for RS-485 Transceiver is being transmitted as a byte in Modbus packet I am running into an issue where pulling RE low on my Max3441EESA is appearing as an extra byte in my Modbus message. I am currently testing the Modbus capability of my PIC32 MCU with a Modbus slave program on my PC, and even though I am transmitting an additional byte, the software still interprets and returns a message. However, when communicating with a Modbus sensor, the communication fails, and I believe it might be due to the extra byte. (Rx is what my MCU is sending and 00 is the extra byte) Below is a picture of my schematic. It is important to note that I am not using the dedicated RTS for my chosen UART. Unfortunately, I had to add a peripheral board to an existing design so I did not have the luxury of re-purposing the RTS pin; I had to choose a separate GPIO pin and try to use it as RE. I can communicate between my MCU and the Windows Program, and between the Program and the Modbus sensor, so I know both my MCU and Modbus sensor can interface through Modbus. For specifics, I am using Modbus RTU with a 38400 Baud Rate Any ideas on how I can resolve this in hardware or software would be appreciated. I have messed around with when I pull RE low, and I soldered up some solutions to try using different pins for RE to no avail. AI: The A and B are biased incorrectly, they should be biased the other way. A-B must be positive for idle logic 1 state. In your case, A-B is negative, logic 0.
H: Less than minimum charge voltage for NiMH battery and extra parts in a "simple" circuit I was given the job of duplicating a "simple" box that monitors air flow in a duct. It seemed simple. I dabble in electronics (I design and build industrial control panels, starts, PLCs, HMI, etc.) I knew the guy who designed and built the originals about 25 or 30 years ago. He has long since retired and passed I found an old drawing we had, but it does not match the circuit. I traced the board. R7 (drawn in red) is a 1.2K resistor not on the drawing but on the board. It is not something added in later as it even has artwork on the board for it. I don't understand what it is for, it just adds load. Maybe it is needed as the relay only draws 30mA. I don't understand D6. D7 is for voltage foldback (flyback diode) but why D6? R2 says optional but is installed on all boards. I don't see what it does as it bypasses D5, which is a problem as it backfeeds the yellow LED (glows on even when power fails.) "see note 2" - no note 2. Now my big question: Reading the data sheets, I see the LM317 (REG 2) is fed from the 12 volt regulator REG 1. The LM317 requires 3 volt differential to operate properly. This means I can get 9 volts at best out of REG 2. After going through the diode D5, maybe 8.5 volts. The battery is a 9 volt NiMH, 8.4 V rated voltage. 7V drop off, 10.5 V maximum charging. I checked the units and found 7.24 volts at the regulator. After sitting a while (put in a new battery) the same voltage at the battery! I know these are working and I know they have been used for years, but how is the battery charging at only 7.24 volts? The beeper is a sonalarm 6-28 volts at 6-26 mA. Maybe if you charge the battery at only 7.24 volts it will still have say 10% of it's capacity. A 280 mA battery will still have maybe 28mA, enough to keep the buzzer going for an hour (which is probably fine.) I never heard of "under charging." The boss just wants me to duplicate this. Am I missing something? AI: Update & Supplement #2: I found other information here in the EESE site and in Linsen’s great “Handbook of Batteries” that supports my original answer, but I felt the need to clarify and update some points: 9V NiMH Battery, internal construction - photo I have an old 9V NiCd battery from GP of 150 mAh, now leaky and defective, that I opened for a comparative view of its internals. That opened GP’s battery is compared side by side with 2 Panasonic ones of 120 mAh (still so-so) and a couple of newer NiMH 9V from Elgin, marketed as 250 mAh, where the actual capacity seems to be about half of it, so “1XX” mAh. We can then say that most “9V” Nickel-based rechargeable batteries with 8.4 V nominal voltage are made of a stack of 7 NiMH (NiCd) cells. Initial & Final discharge voltages of 9V NiMH An excellent and benchmark source of information is the Handbook of Batteries by Linden & Reddy, which Chapter 29 lectures about NiMH. Its “Figure 29.6.a” reports the discharge profile of the 9V NiMH battery, whose data was provided by GP batteries. The points to highlight here are: Initial discharge battery voltage is 10.0V for lower current drains (i < 0.2C). Discharging cut-off voltage 8.0V delivers 100%C at drain current of 0.2C (30~50 mA) and +90%C at 0.5C (75~125 mA). Final discharge voltage is set at 7.0V, regardless of discharging current, as an absolute cut-off limit. Recommended Charging & Discharging for O.P.’s 9V NiMH application: Adjust “REG2” to deliver 10.0V measured at the cathode of D5 (not at the battery) and with a battery installed, or using a 8.2V Zener diode as test jig (dummy 9V battery load). This will be the practical final voltage for the battery, assuming a Vdrop = 0.8~0.9 V of voltage drop on D5 (1N4148) for 20~30 mA, lowering to Vdrop ~0.6 V for 1 mA. D5, R4 and REG2 will provide the charging profile for a kind of “floating” charge for the NiMH, with 10.0 V in real charging situations and up to 10.2~10.3 V if residual charging current is really small (~1 mA). I suggest R4 = 100R (1W) to limit charging current to less than 30 mA (~0.2C) if V_bat = 7.0 V. At Vbat = 9V, Icharge = 10 mA (0.04C~0.07C). For a residual charging current of 1 mA, R4_drop = 0.1 V; at this current level, such voltage drop will be more than compensated by the increased cathode voltage in D5. Upgrades: REG2’s supply & Discharging cut-off: you would redesign or modernize the PCB, I would feed the LM317 from the larger capacitor, C1, as I originally said at the end. I also would consider a cut-off circuit, even something based on the TL431 and a bipolar or mosfet transistor would be enough to protect the 9V battery from overdischarge below 7.0 V. Other NiMH related links, from EESE: What does it mean that NiMH batteries do not have a "float voltage"? Can I indefinitely "trickle" charge NiMH batteries with a constant current? Russell McMahon’s answer to “How fast may I trickle charge a full LSD NiMH battery?” Original post: “And now my big question ...” (and concerns) Let’s address them by parts: About the “REG2” as LM317: The LM317 requires 3 volt differential to operate properly. Not exactly, as it is dependent of the load current (and temperature), as seen on Onsemi’s LM317 the dropout will be lower than 2V at charging currents of ~20mA, as this “Figure 10”, extracted and highlighted in Blue marker shows: . Because of that, you could maintain the “REG2” connected to the +12V from REG1, as it could provide up to ~10.0V of regulated output to charge the 9V battery, depending also of the output tolerances (typ. 5%) of the LM340T-12. However, to have more freedom of voltage regulating, I would suggest you to connect the LM317 directly to the unregulated voltage at C1 - see above in Onsemi’s “Figure 8” that the LM317 could provide up to 500mA with a voltage differential of 30V - and in your case, running at 20~30 mA, and Vin-Vout < 20V, dissipating P < 0.5W, it will not need a heatsink for that. About the 9V NiMH battery: “ The battery is a 9 volt NiMH ... 8.4 rated voltage... 7 drop off ...10.5 max charging” It seems the modern NiMH batteries are a stack of 7 element-cells of NiMH, as: 7 * 1.2 = 8.4V nominal voltage; 7 * 1.0 = 7.0V discharge termination voltage; 7 * 1.5 = 10.5V charge termination voltage. This can be seen for the following manufacturers Energizer, Varta, Ansmann, Tenergy, and some less worldwide-known brands as Elgin could have their customer service providing data with variable degree of detail: and here this one brings further detail of charging voltage curves, in the highlighted Blue box. The key point here is that the recommended charging voltage should be between 9.1V and 10.0V, otherwise the electrode will not be fully charged - see discussion below. NiMH - Undercharging, Overcharging and Overdischarging This Energizer Handbook and Application Manual for NiMH brings further details about the battery chemistry and there are 3 pictures I would like to base my comments: Nominal voltage = 1.2V is at ~50% State of Discharge and 1.0V is already at knee, voltage termination: State of NiMH electrodes at fully-discharged, fully-charged and overcharging states: NiMH voltages and electrode polarization states where I marked the Nominal (1.2V), your application (1.03 ~= 1.0V) and polarization reversal on the first electrode at 0V, not your case in theory, but could happen in 1 cell, in real life situations discharge of a 7 stack of NiMH cells. Main Conclusion: Recommended charging voltage and current: From the above information, we can say that current/modern 9V NiMH should be charged a with a termination voltage of 9.1~9.5V to 10.0V, depending of ambient temperature, and with a floating charging current of 3%C to 5%C to minimize damages due to eventual overcharge of one of the cells, allowing the Oxygen recombination mechanism to happen safely. The suggested change on the supply voltage of the LM317 would allow better assurance this (essential) higher voltage level is achieved in your charging circuit. You mentioned charging at 7.24V and this is way too low. In this case, the battery electrodes might be close to polarity reversal potentials and one of the 7 cells could reverse potential and be irremediably damaged. ’Mind the Gap’ for Board compatibility interchange: Some changes should be made on the new boards, especially about voltage and current floating-charge values, and they will not affect interchangeability between ‘old’ and ‘updated’ boards. However, one should keep in mind that further changes are to be evaluated carefully, as they could alter the features in terms of the alarm sensor and LED indications, for instance, eventually impacting the operational experience. Supplement #1 - Other questions within: R2 ‘optional’, but always present on all boards: It seems its main function is to provide a low (very low) current above 7.24V, if the battery stand-by charging current is lower than 0.7 mA (voltage drop on R2 with diode D5 as 0.7V), but in real life 0.7 mA means for a 150mAh battery just 0.4%C, well below usual floating current levels. D7 and relay: It is used to avoid inductive voltage spikes when an inductive load (relay coil) is switched-off. Must be maintained. D6 and Alarm detection: It seems it is used to establish the supply voltage only to the relay through the High-Low alarm switch loop, but not directly to the relay. R7 and possibly delayed alarm: When operation = Normal, alarm switch is not triggered, so its position is Closed, and the relay coil this energized. However when on Alarm status, and depending on how this switch is used inside the sensor, the switch response could be seen as faulty or have a large capacitor still charged, delaying relay response. Possibly R7 is used to avoid false alarms, working as a load, speeding the Alarm response.
H: How to calculate capacitor size? I'll apologize in advance as I'm sure this answer is already somewhere on the site. I don't have enough of an electrical background to know the proper terms to search for so I came up empty. I'm looking to install a diesel heater that draws 15A at 12V for about 2 minutes before dropping to 2A. The power pack I was hoping to use can supply 10A at 12V. I was wondering if a big audio capacitor could handle the startup but I have no idea how to calculate what I'd need or how to go about wiring it. I'm guessing the capacitor would need to be stupid big but now that I'm thinking about it I'd really like to know how stupid big it would need to be. Thanks in advance. AI: No. Capacitors aren't directly suited to this kind of application, because they don't hold a steady voltage (or anything even close to it) as they charge/discharge. To put a capacitor in parallel with a constant-voltage source for a meaningful "current boost" you would need a bunch of regulation circuitry that would be more complicated than the thing you already have. If you wired it up without that, it would basically not help at all (and would create some new problems). Even being generous with the numbers, yes, you need "stupid big". 5 A * 12 V * 120 s = 7200 J (aka 2 watt-hours), just to serve the "over 10 amps" portion of your load. The capacitors we work with most of the time are a millionth of that. A "reasonable" car audio capacitor is, say, 1 to 5 Farad @ 16V, which works out to between 256 and 1280 J (if you had a way to charge and discharge it with nonexistent 100%-efficient converters). There are a few products that claim to be in the 30F range, which would theoretically do the job, but their specs are pretty likely to be lies. Delivering power over long periods of time is a job for a battery, not a capacitor, and what you really need is a battery box that's rated for your load current in the first place. 15A isn't asking that much.
H: Can an output voltage of a simple comparator be higher than the input voltage? This is a simple comparator circuit that I have built for a school project. However, for some reason, the output voltage tends to be higher than the input voltage of 12 volts(accidentally cut out in the picture, so it looks like 2V). It comes out as 15V, which I have no clue why. Is there a reason for this, and is there a way to fix this? AI: You don't show the opamp supply, but when used as a comparator with no negative feedback, the op-amp output will go from one extreme (the negative supply or ground if single supply) to the other (the positive supply) depending on which input is the most positive. Exact output voltage and current drive levels depend on the op-amp model, with some supporting rail-to-rail drive, with others only getting within a diode drop at decent currents. True comparators (as opposed to opamps) are optimizer for the extreme to extreme switching, and speced in terms of speed, whereas opamps are normally designed to operate in between the supply voltages and are defined in terms of gain-bandwidth. When a opamp is used as a comparator it may take significant time to recover from drive to the rails.
H: Inductor of twisted pair cable and of a wire I found two calculators on internet for calculating the self inductance of a wire and an other calculator for calculating the inductance of twisted pair. Here are the results for the following parameters : Diameter of wire: 0.2 cm Length of wire: 100  cm Distance between wires: 0.3 cm Here are the results : Wire self inductance = 1.37  μH Twisted pair inductance = 441 nH What I am not sure about is what is really the twisted pair inductance given by the calculator? I said that the length of the cable was 1 meter but in a twisted pair cable there are two conductors, so the inductance of the twisted pair represent the "return" path and also the "going" path? So what I really calculate is the inductance for a cable of 2 meters and not for only one meter? I mean to make the comparison between the two kinds of cable I should take 2 meters of the wire self inductance and 1 meter for the twisted pair inductance. And so we got the following results : Wire self inductance 200 cm = 2,74 μH Twisted pair inductance 100 cm (+100 cm) = 441 nH And so twisting pair reduce the inductance by a factor of 6! It appears to me a lot and I am not sure that it is correct. Did I make a mistake? AI: Twisted pair is not meant to transport a current and the return current to convey information - the information travels as the energy between the two conductors, and always in one direction. So, the value you're being presented with us the inductance per unit length of the twisted pair cable understood as transmission line. It answers the question of "if I suddenly changed the differential current I use to excite this transmission line, what happens?". So, you wouldn't compare these numbers altogether. They are not describing the same thing. You can feed a common-mode current into both conductors of a twisted pair cable and calculate something that is comparable to what you've got for the single conductor. But I wouldn't know what that would be useful for.
H: Reading different CAN bus protocols with one interface We have a system with multiple CAN bus protocols. All are running at 250 kbit/s. These are NMEA 2000, J1939, and CANopen. These systems do not have to communicate with each other, but I would like to read all their data. Is it possible to link all these together for easy cable management and to have a CAN controller with just one interface, or will these systems interfere with each other? AI: Yes. As long as the bitrate is the same, there should be no problem. The whole idea of having a bus is the easy integration. The CAN controller manages the bus access. If two or more nodes try to take control of the bus, the one with the lower ID will win the race. Having CAN Open is a software layer on top of the CAN Controller to make it more manageable to handle the messages. In your case, it seems you have one master and multiple devices. It's a normal configuration, and the data reading is usually started by the master. This is called the pooling method. However, in CAN Open, you can have multiple masters too. It makes it a little complicated, but you can have more than one master if you need to. The only consideration here is to make sure to make it a bus. It should not have any branches. The bus must start from one node, go to the next nodes one by one, and be terminated by a 120R resistor in the first and last nodes (image source).
H: Is pad against pad enough for a good connection? I have two PCBs that I need to connect together with holes or notched pins that I have to solder by hand. In order to reduce soldering time, I've placed a few 2mm square pads on the bottom PCB and I'm thinking of placing another one on the top PCB, then after connecting the PCBs together, I hope these pads will be connected without having to solder them. Illustration: Is that good practice? Does it logically have a success rate of at least 98%? AI: No, absolutely not. The soldermask alone is not perfectly flat, so that will prevent the pads from coming into direct contact with each other. If the board finish is HASL, it's possible that it could be thick enough that the pads come into contact, but not guaranteed. This would not be a gas-tight connection, however, meaning that the finish would oxidize and the connection worsen over time. You could do this if you applied some solder paste, just like soldering any LGA part, however. You'd need to reflow it with either a reflow oven or a hot-air station, though. Castellated holes are popular for this style of direct board-to-board attachment with a conventional soldering iron (and you can even use castellated holes to fit into some PLCC sockets for a solderless connection). If you need to make repeated connections between boards like this without soldering (this is very common in my work as a test engineer, to attach a DUT to a test fixture), you need some kind of connector. Standard pin headers can be used if you don't mind having a connector on both sides of the connection, or you can attach pins to give your PCB the same pin size and layout of common through-hole packages (e.g. TO-220, TO-247, DIP) and then use a test socket for that package. Alternatively, and probably most usefully, you can use pogo pins to avoid having to solder anything to your movable boards. In the latter case, the movable boards should have a gold-plated finish (ENIG/ENEPIG or hard gold) to ensure connectivity, unless you know you'll be testing the boards very shortly after they're manufactured (before they've had time to oxidize). You should also ensure that there's some good way of holding the movable board in position, so that the pins are properly aligned with the pads; this can be as simple as two or three posts on the test fixture that go through mounting holes on the DUT, or as involved as a 3D-printed clamping mechanism. A card-edge connector is also an option; your movable board would need to have an appropriate pattern on one of its sides (which should be plated with hard gold if intended for repeated connection and disconnection, or ENIG/ENEPIG for one-time use. Many fabs offer selective hard gold plating ("gold fingers"), which is cheaper than full-board hard gold, specifically for this purpose.), which can then be inserted into a card-edge connector on the other board.
H: Non-Schottky SiC diodes Hopefully this isn't too much of a shopping question. I am looking for off-the-shelf silicon carbide P-N junction diodes, but all I can find are Schottky ones. Do P-N version ones even exist commercially? AI: SiC pn diodes are not commercially manufactured for one simple reason: They have a forward voltage of about 3 to 4 volts. For almost any purpose, either a silicon pn diode or a SiC schottky is a better choice. Despite the famous leakiness of schottky diodes, SiC ones (due to the properties of silicon carbide) tend to have leakage currents more in line with the leakage of a silicon pn diode than a silicon schottky. If, for some reason, you truly need a SiC pn diode, it may be possible to use the the body diode of a SiC MOSFET where you've tied gate to source. The gate-drain junction of a SiC JFET might work as well, though these are not usually rated for much if any forward current.
H: Identify this connector and 2.5 mm pin type Can you identify the connector type, and more important the pins? I was able to find NPP 2.5 mm pins that look the same, but apparently they are smaller than what I need... I'm attaching some photos for reference, the one on the left is the one I need (bigger one). AI: My Identiconn utility identifies it as a JST VH connector. Female plug housing: JST VHR-8N Female crimp socket contact: SVH-21T-P1.1, SVH-41T-P1.1, or SVH-21GH-P1.1, depending on wire gauge and plating {Source: Digikey]
H: Do we need differential routing TX and RX in Ethernet RMII MAC to MAC Connection I am implementing an Ethernet mac to mac connection between SAMA5D27C-D1G-CU and FS32K148UJT0VLQT micro-controller. In MAC to MAC communication PHY TX is connected to RX of MAC and vice versa as shown below. In Ethernet,the RX and TX are differential signals with characteristic impedance of 100 Ohm. My Question is ,Do we need to follow differential routing for RX and TX in this MAC to MAC communication? AI: While the Ethernet copper MDI signals are differential, the MII/RMII are not. The signals are not differential so they do not require differential routing. It would even be wrong to route them as differential pairs as they are not differential signals but unrelated signals.
H: Are 24/12 V automotive ECUs 3.3 V under the hood? My understanding is that MCUs (especially 32 bit ones) typically operate at 3.3 V. I have a 24/12 V, 32 bit automotive ECU (Bosch Rexroth Series 40). I've provided them as an example, but I'm asking generally about all automotive ECUs. Their datasheet includes a block diagram as follows: This leads to my questions: Does the "Voltage supplies and watchdog" block step-down the supply voltage to 3.3 V for the μC block? Do the ECU input conditioning blocks step down the voltage before feeding into a 3.3 V ADC? I've included another diagram to visualize what I mean. Conversely, are outputs stepped up from 0-3.3 V to the appropriate 0-12/24 V using amplifiers? Edit: Thanks for the comments. For context, I'm specifically asking about the internals of the ECU (MCU block and peripherals,,) not about external sensors and their supplies. Below is an application that I'm using this controller for. It monitors the supply voltage for undervoltage and uses the supply voltage for calibrating parameters in firmware. As you can see, it does not rely on the sensor supply outputs. It is purely reading the supply voltage. AI: It’s impossible to make a blanket statement about what voltages the MCU will actually use - you need to consult the MCU datasheet. That said, 5V and/or 3.3V are common for logic I/O voltages, it's highly likely that the MCU has at least this voltage rail. The MCU core voltage for a newer, more advanced MCU could be lower, such as 1.2V or even lower than that. This is compatible with more advanced process nodes. As for what voltage range the MCU’s ADC supports, again you’d need to consult the data sheet. In any event the sensed voltages will need to be scaled to what the ADC can accept. If you are looking to use a power rail for the voltage reference, it would seem prudent to instead provide a dedicated reference that is stable and also qualified for automotive.
H: Are all ESP32 GPIO available for use? After watching many videos I would like to try to make my own ESP32 driven christmas LED display. But a few things aren't clear: Are all GPIO pins available to me to drive LED's ? (Many video's/articles talk about alternate labels / roles for these pins). How many LED's can one ESP32 control? Do I need to put inline resistors with each LED ? There seems to be lots of ESP32 board variations, is there such a think as an LED specific board with resistors already soldered on the board? (Trying to avoid too much learning) AI: A blanket statement of "No", because some pins are reserved for bootstraps, i.e. configuring from where the MCU boots and how. These may need to be pulled up or down during the MCU reset so an incorrect load on them makes the MCU to boot incorrectly by trying to boot from some place you don't want it to. Different models have different amount of GPIO pins, but this is largely irrelevant for many reasons. First is that you seem to be trying to connect all free IO pins to LEDs, so you likely have too much load on the IO pins and you can't have that much load. Second reason is, don't try to run one LED per IO pin to begin with. Using an addressable LED strip, a single IO pin can send data to hundreds of RGB LEDs in chain. I once analyzed some RGB controller that came with a cheap PC case and it tried to control 600 LEDs. Yes, a resistor is always needed between an IO pin and a LED, to prevent overcurrent from damaging and burning out either the IO pin or the LED. I have not seen a board made for the purpose of directly connecting to LEDs by having onboard resistors, but such a thing could exist. I just don't see why anyone would have made one for such a specific purpose, but as I mentioned already, it may not be a good idea to load all IO pins with LEDs.
H: What happens if a 5 V 2.4 A supply is connected to a 21 gauge nichromium wire of 0.79 ohms/ft? If I connect a USB power supply, rated for 2.4 A max. at 5 V, to a 1 ft 21 gauge nichrome hot wire (resistance 0.79 ohms/ft), what would happen? Would the wire still heat up, but not much, or will my power supply fail? AI: Current is voltage divided by resistance, so if 1 foot of wire has a resistance of 0.79\$\Omega\$ then the current at 5 V will be $$\frac{5 V}{0.79\Omega} = 6.33 A $$ Your supply will not handle this so either the fuse will blow, current limiting will kick in (if the supply has this feature), or the supply will overheat and probably fail. To keep the current within the limits of the supply the resistance would need to be more than $$\frac{5V}{2.4A} = 2.08\Omega $$ Which would be $$\frac{2.08\Omega}{0.79\Omega/ft} = 2.64 ft $$ Mind you, this is the maximum current, so you'd want to leave some breathing room, maybe run it at 80 % which would be around 3.3 ft.
H: Automotive MOSFET active clamping circuit - LC ringing between coil load and MOSFET gate? I'm trying to design a circuit equivavlent to fully clamped automotive MOSFETs (like the STP62NS04Z) using discreet, cheap and readily available IRFZxx MOSFETS. The goal is to drive a high impedance fuel injector which is equivalent to a resistor and a inductor in series. The inductance is about 8.5mH and the resistance is about 12 Ohms. I designed this circuit: The automotive fuel injector is supplied with a 14.4V constant supply and is switched to ground. When the load switches off, the zener clamps the output voltage to ~Vds - 10V and the MOSFET turns on, bleeding this potential energy to ground. What I'm experiencing is ringing between some components of the circuit: The red line is the microcontroller output, the blue line is the injector (load) current and the green line is the MOSFET gate voltage supplied via the zener. The voltage at the gate is oscillating for ~0.5ms after the inductor is bled of energy. Is this ringing caused by a LC ringing circtuit between the MOSFET gate capacitance and the inductance of the injector? Will this cause any issues with MOSFET gate drivers like the generic TC4424 (COS4427 and similar)? There is a small AC current on the circuit input: Can this damage the MOSFET drivers? AI: Try an R+C from drain to source. Exact values depend on cable length, solenoid impedance, etc., but typical values would be \$C \ge 3 C_\textrm{oss}\$ and \$R = \sqrt{L \,/\, C_\textrm{oss}}\$, or about 3k and 1nF here. Larger snubber C can be used to slow the free rise / ringdown time, which may help with EMI. Different resistor values will apply for different rates/capacitors, or for different purposes. There can even be reason to use multiple R+Cs. A more dramatic illustration of this comes from switching converters, where the load is inductive (e.g. flyback transformer), and the clamp diode is secondary-referred; thus the primary experiences an initial ringdown on top of the turn-off edge (Coss ringing with transformer leakage), followed by a slower free-ringdown after the flyback pulse terminates (Coss + diode CJ ringing with magnetizing inductance). The nearest application of this, for automotive use, would probably be if the wiring is long enough that its transmission line impedance is relevant (i.e., R ~ 100Ω, C several times the line equivalent capacitance), and then a different value (larger R and C?) to snub the load itself. But mostly, in this context, switching times can be made slow enough that transmission line effects don't matter. In any case, the gate driver is more than capable of handling mere ~mA of backflow. A fancy gate driver is hardly required at all; 12V gate drive into 1k resistor is only 12mA, even a CD4000 series gate can deliver on that. The main annoyance is that, there's no TTL-input CD4000 gate, and you'll probably end up with some discrete transistors to do the level shifting instead, and it's a big pain in the [component count], especially if you need a lot of output channels. Also mind that there's not really any good substitute for the integrated thermal protection, or current limiting or fault detection, that the protected MOS devices can provide; they can be constructed from discrete components even, if you like, but the component count isn't going to be at all competitive, at least anywhere most commodity ICs are available. There are some eFuse and hot-plug / load-switch controllers available that provide, or approximate, this functionality (e.g., sensing and limiting current, and calculating dissipated power, as a stand-in for on-die temperature sensing), that would be most beneficial here. Or, to put it another way -- what you've done so far is provide load clamping, and potentially transient protection (I don't like the idea of ESD or surge going directly into the gate, but the MOSFET may well act fast enough to protect itself here; I'd want to test it extensively before committing to production!), but no short-circuit or cross-wiring fault protection or current limiting or anything. (Maybe those are next on the list or something, I don't know. This, more just to make it clear to any readers looking for such alternatives.)
H: ATX power supply's "Power Good" measurement using oscilloscope I want to measure the power good time of ATX PSU using an oscilloscope. As far as I know, normal time for power good is between 100ms to 500ms. and it is measured according to the picture below, starting from PS_ON command. So I measured PS_ON and power good signals using oscilloscope and got the following image [I forgot to get the original piscture, so I drew it] I think the power good should the time between PS_ON falling edge and PG rising edge. which is 180ms. But when i connected power supply to an ATX power supply tester (i borrowed cheap one with no brand name), it displays 280-320ms as PG. Which measurement is correct. mine, or power supply tester? Any advice to correct measurement is appreciated. Thanks. AI: Both your measurement and the tester may be correct. And actually your numbers for pass criteria are a bit wrong. T1 is specified less than 500ms. T2 is specified more than 100ms and less than 500ms. T4 is specified less than 10ms. So reading the diagram you posted, the absolute minimum allowed time from driving PS_ON# low to PG high is 100ms like you say, but even T2 is defined 0.1ms to 20ms. Then for slowest possible supply, the PG is allowed to stay low 1000ms before it starts rising, and then must have risen within 1010ms. The rate how fast all the outputs are stable depends on if you start the PSU with no or full load resistively, or with no or full load capacitively. The power supply tester may have resistors and capacitors as load. How you did your test is unknown, but I bet you did not apply the exact same load as the tester. Different loads produce different time between PS_ON# and PG. Since you have the tester, you can use the oscilloscope to verify if the tester measures the time properly, by measurint PS_ON# and PG with scope and tester.
H: What is the definition of DDR memory latency? On Corsair's web site, they define memory latency with an equation: (Real Latency) = CAS Latency x 2000 / Data-rate My question is what that means in practice. Is this the delay from the time the address is put on the DDR's bus until the first read comes back? From the CPU point of view, intra-chip, registers are available in under a clock cycle, but the RAM value still has to propagate through the cache, the buffers at pins. What is the latency for Intel or AMD processors of current generation after the value. There is latency from the chipset, and presumably from the CPU itself. AI: CAS latency stands for Column Access Strobe latency. It’s a timing parameter that measures the delay between the memory controller sending a command to read data from a specific column in the memory module and the module responding with the requested data. CAS latency is measured in clock cycles, which are determined by the memory module’s frequency. Source: https://www.globalonetechnology.com/blog/what-is-cas-latency-for-memory-modules/ The total time it will take to make a memory operation will be determined by the time it takes for the data to get to/from the memory, which will be determined by the memory clock. The memory has to process that operation and then sends the data back. I think they have this wrong because for the read operation to complete it should take the CAS time plus the time it takes to send the data (which would be the bus clock length * amount of data in the read operation)
H: SPICE Error in LM5117 Model in Microcap-12 I am trying to simulate SNVA829 (constant current constant voltage) schematic given in the application report from TI. I downloaded the spice model from TI site and imported it to microcap. When I tried to run the transient analysis I get the following error (seems it's a warning but it doesn't start or complete the simulation due to the warning); Warning: Extra Text 'TC=0,0' found. Part: X4.C_C1 File: Any idea on how to fix it? Is the model not correct? AI: According to the manual page 556, Microcap does not use temperature coefficients for capacitors like it does for resistors. Removing "TC=0,0" will fix the problem
H: What type of surface mount diode is SOT-23 marked "JY L"? What type of surface mount diode is this, SOT-23 marked "JY L" AI: The part is most likely a BAV199L dual diode, datasheet here. The key marking is JY, with L probably being a date code. There are several manufacturers who make this part with a JY code including Nexperia and OnSemi. The date coding and exact locations are a good match for the OnSemi part (as noted by nanash1 in comments), as is the "dot". However, whilst I'm pretty confident of the part id, specific manufacturer typically remains uncertain on SOT23 parts unless you see the specific logo (which we don't have in this case). Here's a photo from an eBay advert for the onsemi part.
H: Do LEDs turn on because of heat? I was watching one of my seniors soldering a few SMD LEDs on one of his power converters. He touched the iron on the anode of one of the LEDs and it glowed. I think it is because of thermal generation. Later, I heard him talking about the LED not glowing if a current limiting resistor is present. Am I correct in thinking that thermal generation of electrons might be the cause here? Also, I probably saw one of the LEDs glowing when the iron was touched on its cathode. Is this possible? AI: Yes it is possible but unlikely from thermal generation. Much more likely cause is having mains leakage current via soldering iron, or the iron just closing a circuit for current to flow. The circuit has to complete via some route so simply the soldering iron itself does not explain the phenomenon. The soldering iron may be the terminal for providing the leakage or providing the ground for leakage, the other terminal is unknown.
H: Why do I get shocked from my laptop? How do I stop it in my own designs? Recently, I noticed my MacBook gave me a small shock when it was plugged in and I only touched the very corner of it with my palm. It was fine if I gave it enough contact by resting both palms on the shell. Intrigued, I went to investigate this issue and with my multimeter, I am measuring 80 V AC between my hand and the laptop cover: This seems a bit concerning. I also remembered that my USB power source also gives me a similar shock. It's a bit annoying as I get shocked every time I touch either the 5 V or the ground. I can light an LED by connecting any one lead to either rail and simply holding the other side, but the LED turns off if I jump off the floor. (I made a cool circuit that lights the LED when I touch the handle on my desk:) simulate this circuit – Schematic created using CircuitLab I also remembered that our iMac would give you a nasty Jolt whenever you touched the cover, making it inconvenient to use the power button on the back. I imagine this is all linked to how the house is grounded. I live in India, and I don't imagine the ground prong of the sockets is actually grounded; i.e. connected to a metal bar in the ground. Also, we don't have any of these problems in North America. So my question is this: What is this effect, and how can I stop it? [Edit:] There were some comments that were very helpful in understanding the problem: The main cause due to power supply design ("Y-Capacitor issue"). Can anyone explain how this problem arises and how to counter-act it in my own designs? AI: Many 2 prong USB chargers and other 2 prong power supplies may give shocks due to their internal design. It has nothing to do with grounding in your house. These adapters couple mains to low voltage side capacitively. Either intentionally with an Y cap or unintentionally via transformer winding capacitance. If the laptop charger has a an earthed mains plug and it is connected to properly earthed wall socket, it should not give a shock. But if the laptop has an earthed mains plug and it is connected to an 2-prong unearthed wall socket, or the 3-prong wall socket has missing grounding, then the laptop supply may show high values such as 80 VAC on output and may give shocks. The mains input filter has Y caps from live and neutral to ground so it floats at half mains if wall socket does not provide ground. So two pronged laptop chargers tend to give shocks anyway due to their internal design. Three pronged usually don't when connected to 3 pronged outlet as intended, but will shock if wall socket does not give the required ground. As an example, a very big and expensive top of the line model flat TV from a very known brand has a black anodized metal frame and two prong plug. I don't want to touch the metal frame or do any connections to the TV unless it is unplugged or has connections through another device to mains earth so TV frame stays at earth potential.
H: Resistivity: related to V/I or dV/dI? The resistivity of Tungsten is given by \$\rho(T) \propto T^{1.209}\$ (from Paul Gluck's Physics Project Lab). Let's assume that we can ignore the changes in the geometry of the wire due to temperature change. Does that mean that for a Tungsten filament with applied voltage \$V\$ and current \$I\$, we have \$V/I\propto T^{1.209}\$ or \$dV/dI\propto T^{1.209}\$? Note that \$V(I)\$ is not linear, so the distinction is relevant. As I understand it, the former is resistance, and the latter is differential-resistance. Which one of them is related to temperature as given above? AI: The resistivity, \$\rho(T)\$, is temperature-dependent. \$T\$ is the material temperature here. Which one of them is related to temperature as given above? Neither. Resistance is $$ R=\rho \ \frac{l}{A} $$ where \$l\$ and \$A\$ are length and cross-sectional area, respectively. The only clear thing is \$\rho(T)\propto T^{1.209}\$. But it's unclear if the physical dimensions are temperature-dependent as well. So we may not say \$R(T)\propto T^{1.209}\$ instantly. If you apply a voltage of \$V\$ across a temperature-dependent resistance of \$R(T)\$, a current of \$I\$ flows. $$ V/I=R(T)=\rho(T) \ \frac{l}{A} $$ If we assume the physical dimensions remains unchanged with temperature then we can write \$R(T)\propto T^{1.209}\$ so \$V/I\propto T^{1.209}\$. But this is a result of some assumptions. The relation between the dissipation of \$P=V \ I\$ and the final material temperature is not given, or not clear, or not included. So if you increase the applied voltage by \$dV\$ the resistance change due to the dissipation increase may or may not be proportional to \$T^{1.209}\$.
H: Why memory cell basis is typically "paired inverters" and not "paired forwarders", revisited I asked over a year ago (link) about why memory cells typically use paired inverters instead of paired buffers. The answer mentioned gain, "this is basically because it's hard to make non-inverting gain elements and easy to make inverting gain elements". I now considered a simple example to demonstrate to myself why and how that might be the case. In a simple NPN transistor inverter, the input-to-output voltage ratio is close to one (inverted, but, the voltage levels for zero and one have a gain of nearly 1). But in an "emitter follower" configuration (I will refer to them as "forwarders"), the input-to-output voltage ratio has to be at least (x-0.7)/x (or whatever the base-emitter voltage drop is). If two inverters are paired in a loop, it seems they'll sustain the signal. But if two "forwarders" are looped, the output should always be 0.7 V below the input, so the signal will gradually decay? And if I am right on this, is that the main problem with using "buffers" instead of "inverters", that the signal tends to decay? Someone also mentioned in an answer that buffers are typically made with inverters, but, I feel like that might be secondary in why memory cell basis is paired inverters and not paired "forwarders". buffer inverting buffer Both above images from: HyperPhysics - Inverting and Non-inverting Buffers AI: Exactly right. The voltage gain in a memory cell must be greater than unity in order to get the positive feedback that sustains the data. As you say, the voltage gain of a "forwarder" cannot be greater than unity. Furthermore, the output of one forwarder cannot directly drive the input of a second forwarder without incurring additional losses. Additional discussion on these points here.
H: ELC AL-901 Bench power supply what is the role of ic-1A, and D2-D3, if the voltage variation is made by R11-R12, and the current regulation is made by ic-1B thanks in advance AI: This is a power supply manufactured by ELC, a French company, still in business in Haute-Savoie. The data-sheet is here. The part that they used is a µA723, supposedly designed by the legendary Bob Widlar (see this site). SGS did release its own version, the L123 (low voltage) and the L146 (high voltage). You can find the specs of these old components - plus that of the µA723 - in the pages of this scanned data-book. I ran a quick simulation of this circuit and it is not exactly a constant-current regulator but more a kind of two-step current-limit which reduces the bias current of the external series-pass Darlington: When the current increases and exceeds the 4-A limit, the power supply starts breaking by biasing the internal bipolar inside the 723. This is the one connected between pins 2 and 3 which, when it conducts, squeezes the Darlington base-emitter bias. It is IC1A who features a higher gain than 1B who increases quickly but in a delayed way so that if there is a transient load, it does not collapse the output prematurely. Because of the two 1N4148 clamping diodes, the action of IC1A is kind of limited in amplitude: it starts biasing the transistor but not completely. Then, if the current keeps increasing, it is 1B that finishes the job and further biases the internal bipolar to block the Darlington bias. Without these two diodes, 1A would immediately clamp the output current. This is my interpretation and I might be wrong of course but it looks like a kind of 2-step current break where a first one gently limits the current (IC1A with its clamping diodes) whereas the second op-amp (IC1B) truly hard-brakes if a short circuit happens. Let me know what you think.
H: Auxiliary mechanical anti-ESD measures If a PCBA within a plastic enclosure is prone to malfunctioning due to ESD air discharge in proximity of enclosure seams and openings, but changing the hardware or plastic design is not an option, what could then be steps to minimize the problem? The typical system refered to here is a battery powered one but with buttons, overlays or seams that are poorly designed in terms of keeping ESD discharge arc from reaching the PCBA. No on-board protective components can be assumed. One solution I have come across is ESD protection tape (not the packaging type, but rather Kapton) that can be applied to specific PCBA areas to add protection. Are there other mechanical means to achieve the same goal? AI: Depending on the need for future servicing / repair, and the system thermals, you could consider either potting or a conformal coating (the conformal coating being less "final"). Have a look here and here for some guidance on different types of conformal coating. Most of them will provide good insulation, and it is the secondary characteristics (temp, shrinkage, chemical resistance, humidity tolerance, removability) that will dominate selection.
H: Energy reservoir capacitor How to calculate the appriopriate capacitance for an energy reservoir capacitor that would serve as an alternative IC power supply in case of main power supply failure. Is there a specific formula or a method to identify the right capacitor for the application? The datasheet specifies a minimum capacitance value but I am curious about the general process of identifying the exact or the most appropriate capacitance for the application. AI: A capacitor stores a certain charge. Per charge added, the voltage rises. Per charge removed, the voltage drops. A charge is a certain current flowing for a certain time. Circuits require not only current, but also a minimum voltage to operate. Therefore, the formula is: $$C=\frac{Q}{V}$$ which can be rewritten as: $$C=\frac{I\Delta T}{\Delta V}$$ For your application this means: $$C=\frac{I_{max}T_{min}}{V_{nom} - V_{min}}$$ with I_max = Maximum current draw (Amperes) of the circuit to be kept alive T_min = Minimum time (Seconds) to keep the circuit alive after power fail V_nom = Nominal voltage (Volts) the capacitor is charged too V_min = Minimum operating voltage (Volts) for the circuit to be kept alive can operate from But: Be aware of the significant inrush-currents big capacitors with low ESR can cause. You should have a look at slew-rate controllers, hot-plug controllers, inrush-limiters, soft-starters - many names for a family of ICs targeted at this problem. Also: Make sure your capacitor does not "pump" its charge towards the power supply, once it failed. LDOs usually don't really like that. And: If your capacitor is charged to a significant Voltage V>48V you should rethink your overall approach. Touching high charge reservoirs at high voltages is ... not so nice. Also you should incorporate some sort of bleeding if your circuit to be kept alive does not draw current any more (e.g MCU flushed its memory and goes to sleep).
H: Changing a negatively switch circuit to a positively switched circuit with a PNP transitor I believe I am trying to do something relatively simple, but I am not versed in this sort of thing. Please forgive any error in terms or diagrams. I have a turn signal circuit for a motorcycle. There is one positive and one ground. The positive is constantly hot. The ground is switched on and off to engage the turn signal. I want to convert this to a positively switched system. I believe I can use a PNP transistor to do this. If I connect the PNP base to ground and the PNP emitter to positive, the PNP collector would be a positively switched circuit? I included the diagram below, but I may have used the wrong symbols. simulate this circuit – Schematic created using CircuitLab AI: Controlling some load using “Switched Gnd” can be done using circuit bellow. When “Switched Gnd” is at Gnd the Led is glowing. Edit: Switching with positive signal
H: How can I remove DC from an audio signal? I am trying to "isolate" an audio signal that is transmitted on top of a 24V (DC) power supply voltage. This construct is used in door intercom systems from TCS. The audio signal is the speech between the outdoor station/bell and the indoor terminal. Can some one point me into the right direction how I can remove the DC? I read that a simple capacitor can be used to block the DC part: Would the schematic above give me the "pure" analog audio signal without the (24V) DC part? I have no clue about the level/voltage of the audio signal. I guess/assume phono/microphone level. The goal with the signal in the Arduino is to capture/sample it and transfer it over the serial interface as "raw bytes" to the computer where I can convert it into an into a audio file with FFmpeg. If the above schematic is right, I need to learn about sampling and buffering. AI: If you connect your MCU GND to one of the door intercom lines you may introduce a massive hum noise in this system or even a short cut. So I recommend to use some kind of isolation in such a context. The turn on voltage gradient of the intercom system is unknown and there may exist voltage spikes from lightning or other artefacts. To clamp these voltages, that have a much larger amplitude than the audio signal, I added 3.3 V zener diodes D1 and D2 and a resistor R1 to limit the current of such impacts. The DC part of the line voltage is removed by C1. The 1:1 audio transformer provides isolation and D3 clamps inductive kick backs from large DC line voltage changes to protect the ADC input. R2 and R2 set the analog mid point voltage here and an ADC ref voltage of 3.3 V is assumed. The DC input resistance of the typical ADC input is above 1 MΩ and has no large impact on the voltage divider. R4 adds additional protection for the ADC input because D3 clamps the negative voltage only to -0.5 V, which is close to the typical limit. R4 and C3 form a low pass filter of about 7 kHz to avoid conversion alias and RF artefacts from cell phones. C2 separates the transformer from the DC midpoint voltage and forms a high pass filter in combination with R2 and R3, here around 70 Hz. C3 also holds the voltage during the ADC sampling phase, where the internal sampling capacitors are charged. I added a step voltage V1 to simulate the intercom line turn on and to see, how the circuit deals with that. simulate this circuit – Schematic created using CircuitLab
H: I have built a tube amp but the voltage drop doesn't work as expected The original schematic had 180 V before the diode rectifier. Multiplied with 1.4 that makes 252 V. I could only get a transformer with 200 V, so I added a voltage drop after the rectifier. I calculated to get from (measured) 286 V to 252 V(0,085 A) by using a 0,4kOhm (3 *1,2kOhm parallel) resistor, but the measured result after the voltage drop is 278 V. I don't understand why this value is different than calculated. Can someone help me understand the difference in the measured vs calculated values. AI: You are dropping 8 V over 400\$\Omega\$ which means the amp is drawing 20 mA. This is going to be the idle current, when you put in a signal it's going to draw more. If you figure on dropping 34 V at idle that will take a 1700\$\Omega\$ resistor. The thing then is that when the amp draws more current the voltage will drop more. Let's say you hook up a guitar and play loud, maybe the draw is now 50 mA, and the drop would be 85 V. This variation of the supply voltage is going to affect the sound of the amp. Some people like a bit of 'softness' in their amps because this is one of the things that happens with tube rectifiers, the voltage sags a bit on volume peaks. You probably don't need to get the voltage down to exactly what it was in the original, the tubes should probably handle some extra voltage. So you might try some different resistance values between the 400\$\Omega\$ up to the 1700\$\Omega\$ to see how it sounds with different amounts of voltage sag. You could get some idea of how much current is drawn at higher volume by measuring the drop with some signal into the amp. If you want the voltage to remain relatively constant you would need to use some type of regulator, or a load that will draw enough current to keep the voltage drop within a narrower range.
H: Using AC/DC transformer to step down voltage or as antenna balun You can get an AC/DC step-down transformer like this from many electronic items. There are two things I want to do with it: Convert 6V or 12V DC to 3V or 4.5V DC, but it's not doing it. With the one I have, the input leads measure 133 ohms, that's nice so the power source doesn't short itself out and catch on fire; the output leads have no resistance. So I connect a 6V battery to the input, and the output leads have zero volts. Am I doing something wrong or how do you do it? Use as a unun or balun for antenna. Popular examples are 1:9, 1:4, etc. made with separate wires wrapped through/around a toroid. Why isn't this done with a transformer? Can it be done, or why not? AI: Welcome to EE.SE. Convert 6V or 12V DC to 3V or 4.5V DC, but it's not doing it. It won't. While it's common for the general public to loosely call a DC power supply a transformer an actual transformer, as you pictured, only works on AC, not DC. It takes in AC and outputs AC. To take in a DC supply and output a lower DC voltage you require a buck convertor. (You can google that term for explanations with less equations than that Wikipedia article.) You can buy them ready-made; you'll need to know the current requirement of your load to choose a suitable one. Use as a unun or balun for antenna. Popular examples are 1:9, 1:4, etc. made with separate wires wrapped through/around a toroid. Why isn't this done with a transformer? Transformers are only suitable for specific frequency ranges. The pictured transformer is labelled on the top as being suitable for 50 to 60 Hz operation. It is suitable for AC mains/grid supplies but can't be used as a radio balun. You need a transformer design suited for the radio frequencies you intend to use it for. A device with wires wrapped round a toroidal core is a transformer design suitable for short wave radio frequencies. This is a common way of making ununs or baluns for HF. (Other types of balun are possible at VHF and higher frequencies.)
H: How does this circuit work? BAV99 (3.3V for an ADC) I'm having serious difficulties understanding how this circuit works. It's supposed to be around 10V at my test point with the voltage divider, but when I measure it, I get around 3.3V. It's not clear to me how a diode can consistently reduce my voltage from 10.5V to 3.3V, even when I increase my VBATT voltage. If someone could explain it to me in the simplest way possible, or in the most engineering terms, I would be happy. Thank you very much. AI: D2 is clamping the voltage at around 3.3V by dumping current into the 3.3V source. This is a common configuration for input protection on integrated circuits where the diodes can provide limited over- and under-voltage protection.
H: How to reduce 24V to 0V-5V variable through a pot with an output current of 3amp? I want to build a 5v variable PSU. I found one on ebay but the output current is not good for my application, 10mA. AI: Getting generic variable supply to go down to 0V on the output is tricky, this is because the feedback is referenced against a fixed voltage, so to get zero out you need to feed the fixed voltage in to the feedback. so to do this you need to offset the feedback signal by some offset without dominating it. simulate this circuit – Schematic created using CircuitLab here I'm using an LM317 to make a voltage slightly higher than the output voltage so that it can be fed back allowing selection of voltages below 1.25v . R2 limits the selectable output range to about 0-5.1V on a generic adjustable DC-DC module the feedback pin is connected to the middle pin ot the adjustment potentiometer, so rip the potentiometer off (trying to unsolder is hard) the de-solder the pins and connect a circuit like above to where the middle pin was. The LM317 won't be making much heat so a TO92 model can be used (like LM317LZ) this way you'll be able to use $1 XL4015 buck modules as the DC-DC converters and still get the full 0-5V potentiometer adjustment range.
H: What does it mean when device needs a voltage drop to function? Sorry if this is a badly worded question, still learning electronics and don't know specifically what to ask yet. I'm new to electronics and working on a problem that requires me to find resistor values so that a fan will work with a voltage drop of 5V. I've attached a picture of the circuit as well. I'm not sure quite what it exactly means by a voltage drop. To me the only logical answer is that when the voltage passes through the fan the voltage would just drop by 5V. But I'm struggling to understand this concept and how it can be used to help design and analyze circuit diagrams. Is it the resistor that makes the voltage drop or the fan itself? This idea has confused me and tends to get me stuck on a lot of problems like this. Thank you This is the full context of the question: Then the sub part asks to find the values of the resistors R1 and R2 so that the fan works with a 5V voltage drop. Edit: I don't have a characteristic curve of the fan but I have one of the transistor. Shown below Circuit diagram Edit 2: My bad the curve was on a different page, thank you all for being patient AI: voltage drop = potential difference Your fan needs at least 5V between the red terminal and the black terminal to operate. A typical PC case fan could be damaged by 24V (most are designed to operate from 12V). This is the reason for the resistor in series with the fan.
H: ATSAMD21E18A - Atmel ICE programming error Recently I have designed my custom PCB board, which includes a SAMD21E18A. Unfortunately, I am having trouble with programming. I am enclosing the schematic (please ignore the quality of the schematic, it is still a work in progress). It should also be noted that all other active components on the board were desoldered and only MCU, LDO, programming header, and a couple of passive components are present. For programming, I am using the Microchip Studio with ATMEL ICE programmer. My problem is as follows: SOMETIMES, I am unable to read the device signature. However, the target voltage is stable at 3.3V. It seems to read the signature just sometimes, usually the signature is read a couple of times after the MCU is powered, and then it suddenly stops responding. Since I could not resolve this problem (I am unfortunately unable to test the programmer on a different board), I tried to conduct some measurements. One unexpected thing I could measure is a voltage of 0.6-0.7V at the RESET line while the ATMEL ICE is connected. To conclude, I would like to ask if anyone has ever experienced similar behavior (the MCU is clearly not dead since I am able to read the signature once in a while). Do you think there is a chance my programmer/debugger ATMEL ICE may be faulty? AI: The manual can be found from the manufacturer https://www.microchip.com/en-us/product/ATsamd21g18 - download complete datasheet. (If you have the old Atmel datasheet like I did, it uses different chapter enumeration...) Your design is quite different from manufacturer recommendations, chapter 45. VDDCORE should have a 1uF cap (45.2.1 power supply connections) SWCLK has internal pull-up - the external one may interfere(?) (13.6.2) /Reset should have a 100nF cap (45.4 external reset circuit) External pull-up on /reset typically recommended for high integrity applications (45.4 external reset circuit) If you use external quartz then the layout + schematic of that is highly relevant to the question. See 45.5.2 for recommendations. The VDDCORE and /reset caps are likely to be particularly critical.
H: DC-DC Converter output: 6.21 V instead of 5.5 V I am using a MGDSK10H5,5 in my design for generating 5.5 V. The MGDSK10H5,5 is an isolated DC-DC converter, but I am using it as a non-isolated DC-DC converter; I have shorted input and output grounds of this DC-DC converter. When I measure the output it's showing 6.21 V instead 5.5 V. I am using FBMJ2125HM330-T ferrite bead at the output between two 22μF capacitors. I have attached the circuit diagram I am using currently. Can someone tell me why I am getting 6.21 V instead of 5.5 V? Is something wrong with my circuit? AI: If you're measuring the output voltage with no load, don't do that. The datasheet for this regulator says that the load regulation spec is ±2.5% when the load is between 25% and 100% of rated (450mA - 1.8A), and -2.5% to +20% when the load is less than 25%. 5.5V + 20% = 6.6V, so you're well inside that. It also says "Minimum 10% load is recommended, operation with no load during more than 1s may partially damage the converter output." so it's really not designed for no-load safety.
H: USB-C camera wired for USB 2.0 in circuit layout I'm a bit confused about the USB 2.0 portion of a USB-C pinout. We have two cameras that operate over USB-C, but they are also compatible with USB 2.0 because we can use them successfully through USB 2.0 when plugged into our laptop. Our actual flight board will be connected to our embedded OS through some traces on the circuit board in the image below, so I'm trying to figure out if I need to put the USB 2.0 traces on pins A6&7 or B6&7, based on the standard USB-C pinout. The cameras seem to be reversible because I flipped them around in the USB-C cable and they still work over USB 2.0 on our laptop. What I'm not sure about is if it's the camera that is hardwired to be reversible, or is it something in the USB-C cable itself that is making it reversible? If the camera is hardwired to be reversible then it doesn't matter which side I put the traces on, but if it's the cable itself I'm not sure how I can know for sure which side to put the traces on on my surface mount USB-C connector. I reached out to the company and they haven't been very helpful. The cameras are: DFM 37UX178-ML and DMM 37UX178-ML Embedded system is: Toradex Colibri iMX6 256MB IT AI: With USB C 2.0, on the receptacle side, both the A and B sides are wires up. This creates small stubs, which aren't an issue with the low speeds of USB 2.0. You also need to wire up A5 to a 5.1k resistor to ground, and B5 to another 5.1K resistor to ground. This is required for the connection detection part (without this, an dual role device won't communicate) With an plug, you only wire up the A side, and wire up A5 to an 5.1K resistor to ground (Note that on the source instead of sink side, the resistors to A5 and B5 (A5 only in the plug) need to be 56K to 5V) For understanding the differences between the term sink a source, a sink is like a keyboard/mouse, it consumes power from the USB it is attached to. It also obeys command from the device connected to the cable. A source is like a desktop PC. It sends power and USB commands though the cable. When using an C to C cable, It first sends limited current though the CC wire, and it detects a valid connection with the A5 and B5 resistors. Once it detects a valid connection, it will apply 5V. This process makes USB C immune to wrong connections like charger to charger or desktop pc to desktop pc
H: Cascode BJT amplifier DC analysis assumption simulate this circuit – Schematic created using CircuitLab I am working on the DC analysis of a cascode amplifier. If I assume base current is negligible I get the following equations: From voltage divider: Vb1 = (Rb1/Rb1+Rb2+Rb3) * Vcc, Vb2 = (Rb1+Rb2/Rb1+Rb2+Rb3) * Vcc From Kirchhoff: Vb1 - Vbeon - Ie1Re = 0 from which I calculate Ie1 therefore Ic1=(β/β+1)Ιe1 = Ie2 and Ic2 = (β/β+1)Ιe2 So finally: Vo = Vcc - Ic2Rc my output voltage gain My question is: what will change in my analysis if I don't assume zero base currents ? AI: Initial Answer I won't perform the solution (yet.) But I can suggest a process for analyzing the circuit when the base currents aren't assumed to be zero. Let's look at the annotated schematic: simulate this circuit – Schematic created using CircuitLab Before I begin, just a few notes about the above schematic: I'm assuming that both BJTs will be in their active mode. If, for any reason, your analysis finds that either one of them is not in active mode then what I present here fails. This is a normal way to proceed, though. Start with this assumption, perform the calculations, apply them to the schematic and see if the results confirm the assumption. There are two base-emitter voltages indicated in the schematic. But, for analysis, you don't actually need the one for \$Q_2\$. (Except when testing to see if the results confirm the assumptions in #1 above.) You will need the base-emitter voltage for \$Q_1\$. You can either supply it as an assumption you make or, if you want a closed solution, you can develop it using the Shockley diode equation. However, I don't recommend going that direction as it requires you to have some experience with one of the branches of the product-log function (LambertW) and that's unlikely unless you study mathematics outside the typical undergrad curriculum. You will have to supply some assumed values for \$\beta_1\$ and \$\beta_2\$ for their respective BJTs. You can apply KCL to nodes \$V_1\$ and \$V_2\$. That should be pretty easy to lay out. You can apply KVL to two loops: (1) From \$V_{_{\text{CC}}}\$, through \$R_{_{\text{B}_3}}\$, through \$R_{_{\text{B}_2}}\$, via \$V_{_{\text{BE}_1}}\$, then finally through \$R_{_{\text{E}}}\$. (2) From \$V_{_{\text{CC}}}\$, through \$R_{_{\text{B}_3}}\$, through \$R_{_{\text{B}_2}}\$, then finally through \$R_{_{\text{B}_1}}\$. You should carefully note that there are clear, definite relationships between a number of the unknowns shown in the schematic. Two of these unknowns that you will need to find directly are obviously \$V_1\$ and \$V_2\$. But you can select exactly two currents as your additional unknowns to find and then take note of the quantitative relationships that all the remaining currents have to these two. I'd recommend that one of the currents should be either of the two base currents, with the other one pretty much any one of the five resistor currents. After substitutions, this provides four equations in four unknowns and it is easily solvable. Added for Autodidacts A day's gone by, now. And I may as well work through the problem (before I move on in life) for those interested in seeing how a solution may develop from the above discussion. This is added for those kindred self-educators. Let's first re-state the schematic with some added information. We'll need this when developing the equations. simulate this circuit Be sure to carefully trace out the additions I've added above. As you may well see, now all of the currents are dependent upon exactly two unknown currents, \$I_{_{\text{B}_1}}\$ and \$I_{\text{R}_{\text{B}_1}}\$. With that in hand, the KVL equations can be developed shortly. But first, the easiest part is the KCL for the nodes associated with \$V_1\$ and \$V_2\$. $$\begin{align} \frac{V_1}{R_{_{\text{B}_1}}}+\frac{V_1}{R_{_{\text{B}_2}}} +I_{_{\text{B}_1}} &=\frac{V_2}{R_{_{\text{B}_2}}} \\\\ \frac{V_2}{R_{_{\text{B}_2}}}+\frac{V_2}{R_{_{\text{B}_3}}}+\left(I_{_{\text{B}_2}}=I_{_{\text{B}_1}}\cdot\frac{\beta_1}{\beta_2+1}\right) &=\frac{V_1}{R_{_{\text{B}_2}}}+\frac{V_{_{\text{CC}}}}{R_{_{\text{B}_3}}} \end{align}$$ I've used a technique above that I've developed (and discuss in the KCL Addendum below) for quickly and accurately writing out the particular form of the above equations. The results are exactly the same as other forms. I just prefer these. I've found I make far fewer mistakes that way. But feel free to re-arrange the above equations into any form that feels more comfortable. They will be mathematically equivalent, as you'll see if you try it. The above two equations have three unknowns: \$V_1\$, \$V_2\$, and \$I_{_{\text{B}_1}}\$. The KVL below follows through with my earlier discussion and in the order I listed them: $$\begin{align} V_{_{\text{CC}}} - R_{_{\text{B}_3}}\cdot I_{\text{R}_{\text{B}_3}} - R_{_{\text{B}_2}}\cdot I_{\text{R}_{\text{B}_2}} - V_{_{\text{BE}_1}} - R_{_{\text{E}}}\cdot I_{_{\text{E}_1}} &= 0\:\text{V} \\\\ V_{_{\text{CC}}} - R_{_{\text{B}_3}}\cdot I_{\text{R}_{\text{B}_3}} - R_{_{\text{B}_2}}\cdot I_{\text{R}_{\text{B}_2}} - R_{_{\text{B}_1}}\cdot I_{_{\text{B}_1}} &= 0\:\text{V} \end{align}$$ Using the annotations in the latest schematic above we can make some substitutions and reduce the unknowns: $$\begin{align} V_{_{\text{CC}}} - R_{_{\text{B}_3}}\cdot \left(I_{\text{R}_{\text{B}_1}}+I_{_{\text{B}_1}}\!\!\left[1+\frac{\beta_1}{\beta_2+1}\right]\right) - R_{_{\text{B}_2}}\cdot \left(I_{\text{R}_{\text{B}_1}}+I_{_{\text{B}_1}}\right) - V_{_{\text{BE}_1}} - R_{_{\text{E}}}\cdot I_{_{\text{B}_1}}\cdot\left(\beta_1+1\right) &= 0\:\text{V} \\\\ V_{_{\text{CC}}} - R_{_{\text{B}_3}}\cdot \left(I_{\text{R}_{\text{B}_1}}+I_{_{\text{B}_1}}\!\!\left[1+\frac{\beta_1}{\beta_2+1}\right]\right) - R_{_{\text{B}_2}}\cdot \left(I_{\text{R}_{\text{B}_1}}+I_{_{\text{B}_1}}\right) - R_{_{\text{B}_1}}\cdot I_{\text{R}_{\text{B}_1}} &= 0\:\text{V} \end{align}$$ This only adds one more unknown: \$I_{\text{R}_{\text{B}_1}}\$. So now there are just four unknowns and four equations to solve. Using the freely available SymPy: eq1 = Eq( v1/rb1 + v1/rb2 + ib1, v2/rb2 ) eq2 = Eq( v2/rb2 + v2/rb3 + ib1beta_1/(beta_2+1), v1/rb2 + vcc/rb3 ) eq3 = Eq( vcc - rb3(irb1+ib1(1+beta_1/(beta_2+1))) - rb2(irb1+ib1) - vbe - reib1(beta_1+1), 0 ) eq4 = Eq( vcc - rb3(irb1+ib1(1+beta_1/(beta_2+1))) - rb2(irb1+ib1) - rb1irb1, 0 ) ans = solve( [ eq1, eq2, eq3, eq4 ], [ v1, v2, ib1, irb1 ] ) This is a symbolic solution, not numerical. So to get numerical results we will need to specify numerical inputs for each known variable. To achieve this, I need a starting place to generate values for the circuit. Here are some assumptions I'll use: Quiescent \$I_{_{\text{E}_1}}=1\:\text{mA}\$. \$R_{_{\text{E}}}=1\:\text{k}\Omega\$ to set \$V_{_{\text{E}_1}}=1\:\text{V}\$. \$V_{_{\text{BE}_1}}=660\:\text{mV}\$ @ \$I_{_{\text{E}_1}}=1\:\text{mA}\$. \$Q_1\$ is LTspice model for 2N3904, except \$\beta_1=150\$. \$Q_2\$ is LTspice model for 2N3904, except \$\beta_2=250\$. Biasing stiffness: \$I_{\text{R}_{\text{B}_1}}\approx 100\:\mu\text{A}\$. \$R_{_{\text{C}}}=4.7\:\text{k}\Omega\$ (some modest voltage gain.) \$V_{_{\text{CC}}}=15\:\text{V}\$. From the above, add this: Quiescent \$V_{_{\text{C}_2}}\approx V_{_{\text{CC}}}-R_{_{\text{C}}}\cdot I_{_{\text{E}_1}} = 10.3\:\text{V}\$. Allowing room for \$\pm 2\:\text{V}\$ swing, this means as low as about \$8\:\text{V}\$, when active. I like another \$2\:\text{V}\$ of margin to keep \$Q_2\$ well out of saturation, so I'll assign \$V_2=6\:\text{V}\$ as a design goal. Now I can compute the rest: \$V_1=V_{_{\text{E}_1}}+V_{_{\text{BE}_1}}=1\:\text{V}+660\:\text{mV}=1.66\:\text{V}\$ \$I_{_{\text{B}_1}}=\frac{1}{\beta_1+1}\cdot I_{_{\text{E}_1}}=\frac{1\:\text{mA}}{150+1}\approx 6.6\:\mu\text{A}\$ \$I_{_{\text{B}_2}}=\frac{\beta_1}{\beta_1+1}\cdot \frac{1}{\beta_2+1}\cdot I_{_{\text{E}_1}}\approx 4.0\:\mu\text{A}\$ \$I_{\text{R}_{\text{B}_2}}=I_{\text{R}_{\text{B}_1}}+I_{_{\text{B}_1}}\approx 107\:\mu\text{A}\$ \$I_{\text{R}_{\text{B}_3}}=I_{\text{R}_{\text{B}_2}}+I_{_{\text{B}_2}}\approx 111\:\mu\text{A}\$ \$R_{_{\text{B}_1}}=\frac{V_1}{I_{\text{R}_{\text{B}_1}}}=\frac{1.66\:\text{V}}{100\:\mu\text{A}}=16.6\:\text{k}\Omega\$ \$R_{_{\text{B}_2}}=\frac{V_2-V_1}{I_{\text{R}_{\text{B}_2}}}=\frac{1\:\text{V}+660\:\text{mV}}{107\:\mu\text{A}}\approx 41\:\text{k}\Omega\$ \$R_{_{\text{B}_3}}=\frac{V_{_{\text{CC}}}-V_2}{I_{\text{R}_{\text{B}_3}}}=\frac{15\:\text{V}-6\:\text{V}}{111\:\mu\text{A}}\approx 81\:\text{k}\Omega\$ I'll round the resistor values using E24 series values. simulate this circuit Now to make predictions using SymPy's solution: for y in ans: y, ans[y].subs({rb1:18e3,rb2:39e3,rb3:82e3,vbe:.66,beta_1:150,beta_2:250,vcc:15,re:1e3}) (v1, 1.77926399160283) (v2, 5.92341740170372) (ib1, 7.41234431525051e-6) (irb1, 9.88479995334904e-5) And finally, to now run LTspice: In good agreement. As another double-check, both BJTs are in active mode according to LTspice. I'd designed it that way. But it's nice to see that the design didn't go astray from my intent. Let's now flip the \$\beta\$ values for the two BJTs and see if SymPy's results still match the modified LTspice run. The circuit wasn't designed using those values. But it should survive the run, I think. SymPy says: for y in ans: y, ans[y].subs({rb1:18e3,rb2:39e3,rb3:82e3,vbe:.66,beta_1:250,beta_2:150,vcc:15,re:1e3}) (v1, 1.79243375213728) (v2, 5.85199605706693) (ib1, 4.51168825552700e-6) (irb1, 9.95796528965154e-5) LTspice says: Again, looks reasonably close. We could also change resistor values and so on. But I think there's some confidence already that the analysis was soundly reasoned. Some final notes about the above. We made an assumption (and I got lucky) about the base-emitter voltage of \$Q_1\$. LTspice didn't make that assumption. It uses a fairly detailed model and an iterative process in order to compute it. Far beyond what we are likely to ever manage without such a program to help. However, we can use a tool like LTspice to inform us better, in simulation, and we can then use that better value in our manual computations to verify that we'd get still closer. That's a additional small test about our thinking processes that could be made. But we've already many other ways of testing ourselves (such as changing the \$\beta\$ values as done once above, for example, to see if our analytical result continues to stay close to SPICE computations.) Also, SPICE should be used to help confirm your analytical thinking. It should not be a source of 'hunt-and-peck' design, where you keep plugging in values hoping that something useful comes out in the end. You don't evolve a circuit through mutation and selection. That's a different subject called evolutionary biology. Not electronics design. You should have enough of the process to follow that SPICE tends to confirm your thinking. KCL Addendum The KCL equations may appear to treat node voltages as if they don't have to be differences, but can be absolute values. However, that's not really the case here. In fact, I'm just using superposition (which is easily seen once you've really had the concepts deepened into you.) This is, in fact, the same technique used within Spice programs (those where I've directly looked over the code used to generate these.) Perhaps the easiest way to imagine is that absolute voltage at a node spills away from that node through the available paths. But also that absolute voltages spill into that node from surrounding nodes through those same paths. So long as you treat them all as absolute values, the result is the application of a simple superposition concept that results in, effectively, the potential differences controlling the result. You can test this, easily, by rearranging the resulting equation(s), moving the right side over to the left side and then combining terms. You'll then see the usual potential differences that you expect. So it really is the same result. The reason I very much prefer this method is that it is simple to visualize and very difficult to make mistakes. You can easily orient yourself to a node and then work out the terms for out-flowing currents for the left side of the equation. Then all you have to do is position yourself at each surrounding node and work out the terms for in-flowing currents for the right side. It's almost impossible to screw that up. Conversely, when you are instead struggling to work out the potential differences in your mind (using the more traditionally taught method) and just write those terms, you often find yourself not entirely sure if you have the sign right as you try and add them up, correctly. I find, time and time again that not only others wind up messing up somewhere and making an uncaught mistake.. but that I also make those mistakes, as well. Even with lots of experience, you just aren't 100% sure and you often find yourself double and triple checking your work, just in case. That doesn't ever happen, once you start using the superposition method. It just works. It just works right. It just works right each and every time. I've never, not once, screwed up. (I make typos. But not sign errors.) It's too easy to use. So voltage spills away from a node via available paths and voltage spills into a node from nearby nodes via the same available paths. The only caveat is that a current source or sink can only flow in, or flow out, but not both directions. It's one way. So it will either appear on the out-flowing side or on the in-flowing side -- but not both sides. This also works perfectly well with capacitors and inductors. It does turn the equation into a differential/integral equation. But that's just a technicality. It's still correct.
H: What happen when we parallel or series ferrite bead? If I use ferrite with capacitor as pi network. What happen when I series or parallel the ferrite bead? Which one reject emi better? I known the ferrite bead is not inductance. It act like resistor at high frequency why dissipate energy as heat. But think about series and parallel really confuse me. AI: If you parallel two the same then the impedance (complex number) will be half, and if you put two the same in series then it will double. The DC current capacity should be higher with two in parallel (ideally it would be doubled, but that may not be a safe assumption in practice). Ferrite beads are inductive at lower frequencies, and capacitive at very high frequencies. It’s possible that using a combination of two different types might be preferable in some particular situation. I can’t recall seeing that used in practice. Anyway, in a pi circuit (2 caps to ground and one series ferrite bead), two beads in series will increase the attenuation.
H: How to determine an equivalent RC circuit of a black box? I've been given information about a "black box" device that I know is made of a simple combination of resistors and capacitors, and I've been asked to determine an equivalent circuit. I took an "Electrical Engineering for Non-EE Engineering Majors" class many years ago, but the skills and knowledge that I learned back then are quite rusty, and I could use some help. Here's what I know: when an RLC bridge is connected to the black box and set to measure the equivalent parallel circuit, then the measurement is 140 pF. The dissipation factor is 0.16. The measurement frequency is 1 kHz. I don't have access to the device, I just have specifications. I've shared all that I know, although I strongly suspect that the device uses a minimum number of components. What has me confused is that when I looked up Dissipation Factor, the Wikipedia article talks about an equivalent circuit of a capacitor in series with a resistor. That seems simple enough; I could easily calculate the component values if I knew that the black box were such a series circuit. But when I looked up "RLC bridge" I quickly ended up at the Wien bridge Wikipedia article, which talks about an equivalent circuit of a capacitor in parallel with a resistor. Let me guess that a black box circuit made from resistors and capacitors can have an equivalent circuit of either a resistor in series with a capacitor, or a resistor in parallel with a capacitor. Is that right? And would someone please point me in the right direction to understand how to calculate the component values? If they can't be directly calculated, or if my learning curve would be too steep in the time I have available, could I arrive at the component values by simulating a circuit in LTspice and adjusting component values until the calculated results are sufficiently close to the numbers I was given? I'd be grateful for any help. By the way, this isn't a homework question, although it does sound like one. This is a project my boss assigned to me. AI: a black box circuit made from resistors and capacitors can have an equivalent circuit of either a resistor in series with a capacitor, or a resistor in parallel with a capacitor. At a given frequency, a resistor in parallel with capacitor has the same impedance as a different resistor in series with a different capacitor. Call \$-jX_p\$ the impedance of the parallel capacitor, \$R_p\$ the resistance of the parallel resistor, \$-jX_s\$ the impedance of the series capacitor, \$R_s\$ the resistance of the series resistor, then $$R_s -jX_s = R_p \|\| - jX_p$$ $$R_s - jX_s = \frac{-jX_pR_p}{R_p-jX_p} = \frac{(-jX_pR_p)(R_p+jX_p)}{(R_p-jX_p)(R_p+jX_p)}$$ $$R_s - jX_s =\frac{-jX_pR_p^2-j^2X_p^2R_p}{R_p^2-j^2X_p^2}$$ $$R_s - jX_s =\frac{-jX_pR_p^2+X_p^2R_p}{R_p^2+X_p^2}$$ \$\therefore\$ $$R_s = \frac{X_p^2R_p}{R_p^2+X_p^2}$$ $$X_s = \frac{X_pR_p^2}{R_p^2+X_p^2}$$
H: Leaving the plug attached to the socket It would be really helpful for me to leave the USB plug (the "brick") plugged into the power socket. I would not connect the cable, which could potentially short if it touched a conductor, but only the brick itself, so I would plug the cable in each time I need to charge my phone: Does this consume energy? Is this any dangerous (as it is said about leaving the cable plugged in)? Thanks in advance, SP P.S. I do not really know which site to ask on, so sorry in case I am in the wrong place. AI: Does this consume energy? Yes. Although not enough to make a difference in your electric bill. Is this any dangerous? We tend not to leave electronics plugged in if not in use just in case. Perhaps a better solution would be to use a power strip. Turn it on when phone is charging, then turn off when not charging phone. You can leave the cable connected and out of the way so no one trips on it.
H: Is it possible for this kind of solid state relay to drive high side? I require a solid state relay to be able to switch high side, but also has low on-resistance. G3VM has low on-resistance but it's application diagram shows exclusively low-side switch. Question: what is this configuration of FETs called ? Since it's isolated, why it cannot be used as high side switches ? AI: Connection C is the high side switch to the load, if DC negative terminal = pins 6,7 as shown. Gnd is where you decide is 0V. The Nch FETs are just ganged in parallel in "C" as a common-source mode switch (common to input and output) and switched drain.
H: I don't understand dimming on 3 quadrant TRIACs Can someone help me understand how dimming works on 3-quadrant triacs? I understand they are great because they have higher reliability and don't need snubbers. What I don't understand is how 0-100% dimming can work if you can never operate in quadrant IV. Ok so on a standard TRIAC if I want 50% dimming I would fire the TRIAC at the peak and trough of the sine wave, the start of quadrant II and quadrant IV. If I want 40%, I would fire even further into quadrant II and quadrant IV, and so on down to 0% dimming, otherwise known as off. But if I can't fire in quadrant IV, how am I able to achieve dimming of 50% or less? Seems I would only be able to fire in quadrant II. I have looked for waveform diagrams and other learning resources to try and understand how it is done but I haven't been able to find anything. Can anyone offer some insight here? What am I missing? AI: Quadrants refer to the polarity of the gate current vs. the polarity of MT2 vs. MT1. Image from here. Polarity of gate current is more-or-less irrelevant to what current goes through the load. Simple dimmers and opto-isolated switches derive the trigger current from the voltage across the triac so they always trigger in quadrant I or III. Triacs that are only rated to operate in three quadrants don't work well in quadrant IV so we use a negative gate current to trigger them, say if an MCU is being used to generate the timed pulses. So they are used in quadrants II and III. Even triacs that are guaranteed to trigger in all four quadrants generally have inferior sensitivity in quadrant IV. In each case, you generally can get the whole AC waveform across the load (give or take a bit of losses). Or none (give or take some leakage).
H: Why do speed sensors fail so often? The typical vehicle speed sensor (variable reluctance sensor) is a very basic device which essentially amounts to a coil of wire wrapped around a permanent magnet. Simple, yes, but very reliable? Apparently not so these days... Years ago, I worked on some ancient airport CAT (cash-audit terminals) which would read a magnetic stripe printed on a length of a thick paper card. When the motorist provided the cashier with the card, the machine would read the stripe, calculate the parking fee and using a rather unique printing mechanism, hammer out the text of the charges onto the card as a receipt. The machines were made by a company in San Diego known as 'Electron' - they went out of business in the late 80's. I bring up the CAT units because of their interesting printing mechanism - an electric motor would turn on, and a round metal disc (platen) with numbers and letters embossed around the perimeter was attached to the motor using a specially made rubber band. As the wheel spun, an ink wheel rolled over the characters on the outside of the wheel. As the card passed through a channel, a cantilevered solenoid with a little hammer-like head would strike - pressing the passing thick paper receipt against the spinning print wheel as a stepper motor positioned the receipt for the next character to be printed. The timing, speed and precision were amazing - I used to fix them and marveled at how well engineered and reliable they were. I bring that up because there was a hall-effect sensor that sensed an index mark on the spinning wheel. This signal was sent back to the circuit to adjust the timing of the stepper and hammer strikes. In the 7 years that I worked on those machines, I only recall a very rare few times when we had to replace the printer sensor - maybe less than 5 times in 7 years across about 50 units. Just about every car I've owned has had wheel speed sensors go out. Now, based on my limited understanding of the manufacture of these items, and of their basic design, I have to wonder what could possibly go bad with a wire coil and permanent magnet encased in epoxy? What am I missing? AI: The variable reluctance pickup coils are wound of fine wire, and located in an engine compartment with temperature that cycles from hot to cold. Often they are potted which can increase forces on the wires if it is not done very carefully. That was not necessarily well understood in the early days so you'd see a lot of open coils, at least on American cars. Edit: For more information you can read this patent which points to the encapsulation and subsequent temperature cycling as the major source of reliability issues.
H: Can I divide a MIPI Clock between two MIPI CSI Cameras? So, I'm facing this problem I have encountered while building a pcb. I need to mount two MIPI CSI cameras (2 data lanes each) onto a chip that has 4 MIPI data lanes. The thing is, the chip only has 1 MIPI-Clock and each camera need its own Clock, how could I feed both cameras with just the chip's clock. The chip is a Tibbo's Plus1. AI: This is new to both of us and you have a lot more reading to do than I will. But this is where I started. ref ref MIPI D-PHY components are current-mode binary Bi-phase differential, not much different than ethernet, HDMI and USB but not the same. It can use LVDS technology for your 800 MHz clock, but they seem to be using SMB RF connectors with thin 50 Ohm coax cables (braid or semi-rigid copper) for each 100 ohm, differential channel, rather than CAT4e or CAT5 approach, which might work, but D-PHY experts would say it is not compliant. side-comment: I believe it is because of the evolution to the newer more advanced MIPI C-PHY that uses 3 coax wires per HS Gbps lane for the highest speed data in a three-phase modulation of 3 levels for future 22 Megapixel video imaging, that is new and different than the other protocols. This allows the receiver can operate a lower bandwidth for higher bit-rate data with simpler Rx designs and lower latency than ethernet RLL protocols.. There are several sources of current mode-clock drivers TI's clock splitters or equiv., They also gang the current mode drivers to increase voltage levels and margin for the faster than 800 MHz rates. This is for the "eye" data pattern windows from impedance imperfections and stray noise from adjacent lanes CPU clocks, SMPS power switching harmonics, AC grid, and other gnd noises. A tiny SMT Common-Mode choke is a good part to have to raise the differential impedance and lessen the stray current noise that can be coupled. See low-voltage differential signals (LVDS). See page 3-10 These can be controlled-impedance paths 100 to 120 ohms differential. The detailed MIPI specs are limited to the members of the group of OEMs only but the recommended physical interfaces must exist to be purchased, yet Tibbo "a la cart" modules are rather pricey didn't show any to me. I suspect the clock drivers may need the option to be ganged to boost the current for best signal integrity. So plan on at least 4 outputs combined to 2 ports. Look for existing IoT package designs and signals, as the chips will be a supply issue and a major design learning curve for you, to enable the best integrity on your 1st go. These interfaces can go much faster, but these cams are limited in resolution Four PinMuxable capture modules MIPI-CSI camera interface for up to two cameras supporting resolutions up to 1328x864 @ 60 fps MIPI video interface supporting resolutions up to 1366x768 and 1312x816 HDMI 1.4 video interface for connecting monitors with up to 720p resolution The specs for the MIPI-CSI camera port are: Supports up to two cameras Compliant with; MIPI CSI-2 Specification, rev. 1.01 MIPI D-PHY interface Specification, v1.1 Supported modes High-speed (HS) mode 1.0 Gbps per lane ( and LS low speed mode 10MHz ) REF Doc: https://mixel.com/publications/ https://mixel.com/mipi-d-phy-rx-an-optimized-test-configuration/ And this is where I stopped (Xilinx)
H: How enable for latch converts to clock in flip flop Latch has enable signal and we cascade latches to make flip flops. How enable for latch converts to clock in flip flop. I mean how and why enable driven latches form edge triggered flip flops. Why Flip flops are not enable driven, but are edge triggered? AI: The latches in a D flop (or JK for that matter) operate on opposite clock levels. At the ‘active’ edge (rising, say), the first latch is closed as the second latch is open, allowing the first latch data to flow through. So despite the ‘edge trigger’ name, the pair of latches still work on levels. There’s a variant D or JK flop design that uses just a latch and a pulse generated from rising clock that opens the latch briefly on the rising edge. This could be said to be truly ‘edge-triggered’. This kind of design, although simpler, isn’t favored in modern logic.
H: Why is it not possible to measure PCB trace characteristic impedance using a multimeter? I was looking into StackExchange posts for PCB trace impedance measurement. How to measure trace impedance? This posts clearly explains what the methods to be used for trace impedance measurement are. I searched in many places to find out why we can't use a multimeter for trace impedance measurement, but I did not find a proper answer. Can you please explain why multimeters are not used for trace impedance measurements? AI: You are confusing impedance and resistance. A multimeter measures resistance: it puts a known voltage and measure the current (the other way works, too) and gives you the resistance i.e. the DC impedance For measuring impedance the method is more or less the same but you do it with an AC signal (a sinusoid); what you measure is the amplitude and the phase of the current so it's a complex quantity. It is also varying with frequency: in fact the equipment used for low frequencies (impedance meters/analyzers) are quite different that those for high frequencies. For PCB measurement you are usually interested in impedance at high frequencies (since at low frequency a PCB is small enough to not pose a problem). You need a VNA for that which is probably the single most expensive piece of electronic test equipment (I've seen whole rooms built for that kind of testing).
H: How to configure / construct a CMOS sensor to act on changing signals only? You all probably know how a CMOS sensor works, at least in general. In short, it consists of a lot of pixels (photodiode plus amplifier and so on), and each pixel is read out individually (different to CCD). I have two questions now, a main and a minor one: The minor: A pixel generates a signal only when the signal is above a certain threshold. Physically speaking, this is when a certain amount of light particles hit the pixel aka the photodiode. So, when it is dark, the pixel is not generating any signal (roughly phrased), right? The main one: How could a CMOS sensor be adjusted such that a pixel is read out only when a change in the signal is significant? With the help of a simple resistor, one could change the threshold for the necessary light intensity but this would ignore a signal change from, e.g., very bright to very dark. Would it already work with a capacitor? It would be charged when it is bright and when it changes to dark, the capacitor would be discharged. And when it is bright again, the capacitor would be charged again. Here are two images to help with visualization. Though one cannot ignore physics, I'm more interested in the electronics/engineering part. But here you can already see even three transistors and, for me, it seems like T_1 is already doing this job? AI: There has been a lot of work (research and commercial) done on this subject, so you will be able to find answers in the literature. What you're describing is generally known as an event camera. The advantages compared to reading out whole frames and computing changes digitally are the following: vastly increased temporal resolution and dynamic range low power consumption sparse (low-bandwidth) output. In an event camera each pixel independently tracks changes in light intensity with a differencing circuit. Whenever the change is greater than a certain threshold the comparators in the pixel emits an event, which is sent out as the pixel address, timestamp and sometimes the polarity of the change. You may want to have a look at one of the seminal papers for details of a possible implementation in a custom CMOS sensor: P. Lichtsteiner, C. Posch and T. Delbruck, "A 128 x 128 120 dB 15 μs Latency Asynchronous Temporal Contrast Vision Sensor," in IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 566-576, Feb. 2008, doi: 10.1109/JSSC.2007.914337. https://www.researchgate.net/publication/2983746_A_128_128_120_dB_15_ms_Latency_Asynchronous_Temporal_Contrast_Vision_Sensor
H: Inductive kick back I have simulated two circuits, the switches are open in the beginning and closed and opened after that, because of back EMF the FET has high voltage on VDS for a moment. But one config has 63V as max voltage but the other one is just 6.8V. Why does this happen? AI: So the plots show Vds. When the FET turns off, inductor current won't go to zero immediately. Instead, the inductor will increase voltage between its pin until something in the circuit creates a path for current to flow and dissipate the energy stored in the magnetic field. In both cases, current in the inductor flows left to right, but a different pin on the inductor is switched, and that makes all the difference. In the left schematic, when the FET turns off, current keeps flowing in the inductor from left to right, which increases Vds until the FET avalanches and limits the voltage. Thus you get a large voltage spike. In the right schematic, when the FET turns off, current also keeps flowing in the inductor from left to right. But the right pin of the inductor is grounded, which means this time the left pin of the inductor drops to a negative voltage. Since the FET's gate is biased at 0V through the resistor, it gets enough Vgs to turn, and it does. So its source sets the voltage on the left pin of the inductor (and resistor), and you'll get a few negative volts there.
H: Which flyback diode for magnetic buzzer I am a novice, and I'm playing around with SMD magnetic buzzers. For instance, the CUI CMT-322-65-SMT-TR. In the datasheet they recommend something like this: After some Googling I learnt the diode is a flyback diode, which prevents the transistor from being damaged when power is cut. My question is: how do I know which diode to use? In this case, the +VDC powering the buzzer would be 3V. Do I need a regular, Zener or Schottky diode? Regardless of the type, what kind of characteristics should I then be looking for in this specific configuration? This is an SMD project, but since I'm just experimenting I can also play around with through-hole diodes if you have any suggestions. AI: Take a look at the data sheet: - So what this tells you is: - It's a magnetic device and not a piezo device The rated voltage is 3 volts p-p typically At the rated voltage the current consumption is 120 mA Doublechecking the numbers, 50% of 3 volts divided by the typical coil resistance (12 Ω) is 125 mA peak current. Not far off so believable. how do I know which diode to use? Use a diode that is rated at a forward current of at least 125 mA. Maybe go for the inexpensive 1N400x series of diode. There isn't anything particularly onerous in this circuit that requires anything other than a standard diode but, if you have a Schottky diode to hand, that wouldn't be a problem either. You should not attempt to run the +Vdc supply any higher than 4 volts for this type of buzzer hence, don't employ a 5 volt supply unless you put a resistor in series with the buzzer to limit that peak current to below ~120 mA.
H: ESC's Brushless Motor PSU and Maximum Torque I am looking to purchase DC 12V 83.3A 1000W Power Supply and will use 4 brushless motors A2212 1400KV Brushless Motor. I have checked the Motors and they require 11.1 V and Load Current: 19.0A Power:210W. The ESC's will be 30a bi directional. From my understanding the power supply I am looking to purchase would meet the requirements to run the motors at full torque at the same time. My questions is theoretically will the PSU be sufficient to power the 4 brushless motors at max torque at the same time - although I probably would not want to make them work at 100% probably at 80% but I am just interested to know if I am correct. AI: Yes 1000W will power four 210W loads. There is also more to consider, and that is the efficiency of the power supply. Most SMPS power supplies have an efficiency somewhere in the range of 95 to 80 percent. But the 1000W is at the output of this supply because 12V83.3A is 1000W, so the efficiency doesn't need to be considered. But the supply could draw more than 1000W on the input. Another thing to check is the current, four motors will draw 19A4=76A so the 83.3A will be more than sufficient to run the motors. Also make sure you have good cabling as amps of current will cause a noticeable voltage drop on the cables if smaller wire gauges are used.
H: Switch to ground using transistor I am building an AVR-based diagnostic device for my old Mitsubishi car. To perform diagnostics you must short pin 1 (diag) with pin 4 (ground) on the car diagnostics connector to start a session; no problem with a paper clip. But do I do this with a transistor controlled by an AVR output pin? A pseudo circuit: simulate this circuit – Schematic created using CircuitLab AI: I recommend that you use an N-Channel MOSFET instead, with a logic level gate threshold. simulate this circuit – Schematic created using CircuitLab But, if you wish to use an NPN BJT, as you show, then add a 1 kOhm resistor between the AVR and the base of the transistor. simulate this circuit
H: Are two 2oz copper layers the same thing as one 4oz copper layer? Let's say I want to use 4oz copper, but the PCB fabrication house does not have that capability. Can I just use two 2oz copper layers, and route both of them to the same place? Edit: I am discharging a capacitor, and I expect very brief current spikes of ~20A AI: You might be surprised to find out what you can get away with on short PCB traces that are only 2 oz copper or less. Clearly though, you have to be aware of track inductance if the current change is very fast because this can produce a large \$L\dfrac{di}{dt}\$ that can cause noise (or worse) in other connected components. Another general point is that a discharge path should really try and avoid passing currents across a plane; it's better to star-point such connections as much as you can. So, it's a fine line between having a plane that has a very low inductance and small \$L\dfrac{di}{dt}\$ (at the expense of disturbing other connected circuits) AND using a start pointed connection to ground that will have significantly more inductance but far less chance of directly disturbing other circuits. In my recent experience, I was pulsing up to 165 amps at a frequency of around 100 kHz and I opted for star-pointing. I also wanted 4 oz copper but, due to supply problems could not get it. In the end my tracks were 3 oz copper and about 7 mm wide duplicated on another layer with plenty of connecting vias. I had no problems. Do the math based on this example maybe. 20 amps peak current sounds pretty trivial really. Can I just use two 2oz copper layers, and route both of them to the same place? That's effectively what I did and it didn't cause a problem. Clearly my current was much higher (165 amps peak, 40 amps valley) but, 7 mm wide tracks on 3 oz copper on two layers worked for me so, maybe scale it down to see what you might get away with.
H: Common Mode Noise Attenuation The question is below: Your raw sensor signal is 6.5 mV, and you are using an instrumentation amplifier to process it. The amplifier has a CMRR of 80 dB and a differential mode gain of 40 dB. If the RF noise on the leads from the thermocouple sensor to the data logger is 79 mV, what will the noise level be on the amplified signal in mV? (Type in a two-decimal number.) I tried the following steps: Find common-mode gain from CMRR = 20log(Ad/Acm) Multiply 79 mV with Acm to find the noise at the output But it turns out that I was wrong. I would appreciate if anyone could help me with this. AI: If the RF noise on the leads from the thermocouple sensor to the data logger is 79 mV, what will the noise level be on the amplified signal in mV? Here's where the question isn't tied down enough - does it mean that the RF noise on both leads is simultaneously 79 mV i.e. the common-mode interfering noise is truly 79mV or is it trying to tease out something else? I say this because noise induced on one lead wont be the same as the noise on the other lead; it might be close and, it will be close if the sending end device (raw sensor signal) has a balanced output impedance to ground. But the details in the question don't cover this. Anyway, to get you out of jail as best i can I've had to assume the 79 mV noise is truly common mode. Given that the CMRR is 80 dB, that means that the 79 mV is reduced by 80 dB into a purely differential signal at the inputs. That differential noise signal is then amplified by 40 dB hence, the 79 mV common mode noise appears at the output of the InAmp amplified by a gain of -40 dB i.e. it is 79 mV divided by 100 or 0.79 mV.
H: When behavioral simulation of RTL works but synthesis/implimentation do not I wrote a UART receiver similar to Nandland's example. To verify that I am receiving and processing data (coming from my PC through Putty), I wrote a design that would correspond certain LEDs to certain keyboard letters based on their ASCII character. When I simulate the design, it works as intended. Problem: When I synthesize and then implement the design, no timing report shows up which leads me to believe Vivado is not creating a clock (or isn't connecting it). Why does the elaborated design show expected connectivity while the synthesized and implemented design do not? Elaborated schematic: To clarify, the design is supposed to store the data byte from the PC in a flip flop before going to 3 different LEDs on the board (Arty S7). Synthesized schematic: Implimentation schematic (literally): And yes, I've used the same xdc file to make simple designs like a flashing LED to verify my constraint naming of the clock is correct (which is obviously taken from the manufacturer's github). I would post my code but that seems irrelevant since the tools are not even creating a gate level version of my code (regardless of whether it's correctly for my goal). EDIT: here is the elaborated schematic of the UART AI: I found the resolution in my code and decided I'd leave it here as a warning to anyone who gets good behavioral simulation results (using VHDL) but incorrect synthesis and implimentation results. It all has to do with VHDL's wonderful integer range command in which you can specify the decimal size of the integer. Behavioral simulation ignores this command and will allow that integer to be larger than the range you gave it but synthesis and implimentation do not. My example: signal byte_index : integer range 0 to 7 := 0; then, later on within a FSM I have a state which compares a value to byte_index: if byte_index < 8 then... The problem here is that I defined byte_index as going up to 7 which means a 3-bit register but I want to compare it to a number that is in decimal 8 which needs a 4-bit register. Because behavioral simulation ignores the specified range, this may go undetected in behavioral simulation but in synthesis, the integer is truncated to match the maximum decimal size you specified. This caused my FSM to be stuck on this state because it was waiting for byte_index to be greater than 7 and as a result, synthesis eliminated the FSM. Why did I make this mistake? Simply because I'm used to using one less than the maximum bit size I want (eg. I want 4 bits so that means I need something [0:3] not [0:4] ). so I wrote range 0 to 7 when I should have written range 0 to 8. NOTE: you can compare this to Nandland's UART example I linked in the question to get a sense of what this integer's role was (it is his r_Bit_Index) but be aware my code uses an integer which goes up to 8 and his uses an integer which goes up to 7.
H: Frequency Modulation - Why don't we modulate the carrier by multiplying message signal m(t) directly with f_car? I am master student of computer science and I have got a problem/question from the domain of communication engineering. So: I'm listening to a lecture that's about Layer 1 stuff, and recently we discussed how exactly FM radio works. At one point we discussed how a frequency modulated signal s(t) can be obtain a from a message signal m(t). Therefore our lecturer derived the following formula using the instantaneous frequency: The derivation was done similar to the derivation presented in: FM modulation derivation source - SpringerLink From my understanding, this formula modulates the frequency by introducing a "changing phase offset"., because our equation introduces another summand, which normally represents a phase. However, I thought I can point out the obvious and asked my lecture: "why don't we just modulate by directly multiplying our message stream onto the carrier frequency term?" (Which would look like this:) And my lecturer couldn't really come up with an answer for this, as it looks kind of intuitive to do it like this. So I plotted both approaches using matlab. The resulting plot shows that my intuitive approach doesn't work. However, I am struggling to come up with an explanation, why my approach didn't work. So I thought, maybe someone with a deeper understanding of the mathematics behind the frequency modulation can help me out on this one. The corresponding m(t) signal was: Best Regards AI: I don't know why you think your proposed method of frequency modulation is intuitive. In any case, consider what happens if the modulating signal is 0. In the correct expression for an FM signal, as given in your question, the result reduces to just the carrier as one would expect. However, with your proposed implementation, the result reduces to cos(0) which is a constant value of 1 since m(t) = 0. This is obviously not how FM signals are supposed to work so your expression is incorrect. Note that the correct expression for an FM signal is derived directly from the definition of FM: a signal with a fixed carrier frequency whose instantaneous frequency is shifted from the carrier in proportion to a modulating signal (m(t)). Intuition does not play a role in engineering.
H: How can water create a good ground reference? In the 240V Single Phase panel in my home the ground bus is tied to a water line. My concern is water flows via a non-metallic pipe from the artesian well to a holding tank. A copper line connects the tank to a plastic housed membrane filter. After the filter begins a new run of copper pipe that feeds the fixtures within the house. This section of copper pipe is where the panel ground is attached. How can flowing water create a sufficient ground for the appliances within the house? AI: It doesn't. The water isn't a significant conductor. Most likely your panel is providing a ground connection to the water pipe (as required by NEC 250.104(A) in the US), not "getting its ground" from the water pipe (which it could have done if it was a metal pipe running underground for at least 10 feet), although it is possible that someone screwed up while installing the electrical service or modifying the plumbing. If you've been looking for your ground rod, and concerned that you can't find it, seeing as how you seem to live in Arizona (I checked your callsign), it's a reasonable bet that you have an Ufer ground within your foundation.
H: Passivity and Causality of PCB channel We use S parameters to analyze a PCB channel. Once the S parameters are extracted, what I have seen is SI engineers will check the S parameters obtained are passive and casual. I have some questions about it. A PCB channel consists of copper traces. The trace has some resistance, capacitance and inductance. May I know in any case will this trace become an active element. Will this channel become non-causal at any time. AI: Such a channel will always be passive and causal (not casual). What they are checking for is not that the channel is passive/causal, they know that, it's that the measurements of the channel show it to be passive/causal. A measurement showing it to be otherwise would demonstrate that the measurement was wrong.
H: Does the negative voltage regulator emit noise into ground I am designing an inverting voltage regulator using a LT3758 controller to generate -15 V from a 12 V / 5 V input. This is a non-isolated regulator. My biggest concern implementing the design is if the regulator is going to inject any noise into GND because that can cause many other issues on the board. I had a thought of providing a pi filter or LC filter using a ferrite bead between my board's GND and the regulator's GND (just like how we provide a filter to Vin in a positive voltage regulator). But in TI's document SNVA559 it is shown that inductance between GNDs can cause ground bounces, which is what I want to avoid. What is a proper solution to avoid switching noise in the negative voltage regulator? AI: One does not simply "inject noise into ground", because there is no "ground" . There is a ground plane (hopefully) and it has an impedance, therefore if current flows through it, a voltage drop will appear between different points on the ground plane. This common impedance coupling means every chip or other device that has a "GND" pin will get a different 0V reference from the others, and then noise is introduced into your signal. Your converter has two current loops: the hot loop (in red), with HF square wave currents ; the warm loop (blue), with sawtooth currents. The most noxious is the hot one, because square waves have much more HF harmonics than sawtooth. The most important things are: Make sure the currents from both loops do not flow in your ground plane, by connecting the GND pins of input cap, output cap, Rsense, and L1B together on the same spot, or on a small copper island on toplayer which is then connected to the ground plane with a cluster of vias. You can also put it in a corner and not in the middle of the board, and if you don't like common mode noise, don't put it between two connectors, but on the side. Minimize the area of the hot loop first, then the warm loop second, which will reduce EM field emissions in proportion. For the hot loop, you can put D1 and Cout very close to M1. For the warm loop, forget about "laying it out like the schematic" with the input on one side and the output on the other side. If you put the input and output on the same side, with the GND pins of Cin and Cout next to each other, it will be much easier. A separate via to ground plane for the feedback's ground reference, so it is not contaminated by switching noise. The datasheet layout doesn't fulfill all these conditions, but the placement of the ground vias is excellent. Note the GND reference of the chip is its own GND pin, and it will regulate in reference to this, so it's good to place the ground vias under the chip too. Also the feedback sense point is taken after Cout, which is important since it avoids spikes on your feedback voltage. Further reading.
H: How to design an EMI Filter for AC/DC PSU I am designing a single phase MIL-STD-461 AC/DC PSU. I have the following requirements to the PSU: It needs to operate with an input voltage from 100Vrms up to 310Vrms. Operating frequency 45-65 Hz Current rating of at least 3 Arms (important for choosing inductors and CM choke) Compliant to MIL-STD-461G conducted emissions I have chosen a PFC AC/DC module that works as intended. However, the accompanying filter is only rated up to 264Vrms (the PFC AC/DC module has sufficient rating). The filter rating is mainly due to the use of X2 X7R safety capacitors in the filter. The fundamental circuit diagram of the filter is shown in this schematic from the filter datasheet (component values not specified and damping resistors not included). The CM and DM attenuation performance of the filter with 50 Ohm source and load impedance is shown in this plot: It seems that most commercial and military filters are rated up to 250-264Vrms, and commercial filters also have unspecified attenuation for frequencies under 150 kHz. This is why I am looking into designing my own filter, where I plan to use class 1 safety rated capacitors in order to increase the voltage rating. I think that I have two options for specifying the needed attenuation of the filter. Measure the spectrum of the PSU without any filter and see at which frequencies and how much I am over the limit. Specifying the same attenuation as in the plot shown above (given that the manufacturer of the PSU has tested the PSU/filter combination against the standard). I would prefer option 1, but unfortunately I am unable to measure the spectrum of the PSU at this point in time, because our LISN filters and analyzer is out for calibration. Even if I was able to measure the spectrum of the PSU, the question remains the same: "How do I design an EMI filter that meets a specified attention performance"? I am not aware of an analytical approach to multi-stage filter design, and from the differential-mode attenuation plot, I can identify three different cut-off frequencies. I would think that the design of EMI filters to meet a specified attentuation would be something that was "standardized" to some degree, given that almost all electronic products require a filter, but during my research I haven't been able to find this approach. So, to summarize, these are my main questions: Given the required attenuation for a given frequency band, how should I design the EMI filter? How to choose topology? How to choose component values? Are there any SW packages available for filter synthesis and/or simulation to aid the design? (I am comfortable with spice simulation, but without a methodical way to choose topology and component values this becomes hit and miss). AI: Given the required attenuation for a given frequency band, how should I design the EMI filter? You design the filter based on the required attenuation needed for the frequency bands in question. You appear to be asking for a general solution but, I'm saying that for a particular requirement, you design the filter to suit that requirement. I'm sorry that you might think this isn't helpful but, sat where I am, that's how I do it. To try and gives rules and options for an unspecified requirement is unreasonable and impractical. For the specific filter design shown in your question, here's what it does generally: - Breakdown each one in turn if you want to learn about them - using a simulation package to mimic the behaviour is something I highly recommend. Without a good data sheet for that filter, I wouldn't begin this process. Collect the information, understand it then simulate. How to choose topology? You study the requirements for the filter and figure out what topology is likely to be most successful. This may mean a fairly standard filter as per the one shown in your question or, it might mean doubling up on those filters to cover overlapping bands to obtain maximum spectrum-wide performance. Note here that I'm suggesting that a single simple EMI filter can easily run-out-of-steam in the higher spectrum but be perfectly good in the lower part of the spectrum. Sometimes, it's necessary to put different inductors in series so that one inductor (that is good for the lower spectrum) is supplemented by another series inductor that is good for the higher part of the spectrum. I'm talking about problems of self-resonant frequency and how this factor can morph an inductor into a capacitor and therefore let higher frequency interference through at ease. How to choose component values? I use a simulation package (as do most pros) and that means starting off from a blank sheet and developing ideas that eventually yield component values. It's a suck-it-and-see approach. Sure, the experienced guy will have something in mind as a starting point so, as you gain experience, this process becomes easier but, for the 1st time designer, it's a daunting process that rapidly gets easier as you start to believe in yourself. Are there any SW packages available for filter synthesis and/or simulation to aid the design? Absolutely yes. I use micro-cap 12 - that's a download link. Many people use LTSpice and there are others but, I'm an experienced micro-cap user and wouldn't bother with other sims. But, the biggest mistake is not understanding the real characteristics of inductors IMHO. Make you models with great care and you'll get good results. Also, you might be surprised to find how relatively easily you can model the differential current waveforms that you design produces. You don't need a great degree of precision here; if your current waveform is roughly mimicked to within 10% of actual that will be good enough for use in a simulator. You must also model your LISNs too - that's really easy so don't skimp on the simulation is my advice. I am comfortable with spice simulation, but without a methodical way to choose topology and component values this becomes hit and miss Yeah, for sure it's hit and miss but, so is any design process and I'm not just talking EE designs. That's what design is all about. That's what makes design so interesting (and frustrating). Get used to it. I mentioned the "suck-it-and-see approach" approach earlier. I am not aware of an analytical approach to multi-stage filter design There are many, many analytical approaches; you just haven't found them or not recognized them yet. The main one that springs to mind is cascading pi filters to get massive differential-mode attenuation above certain frequencies but, as with any theoretical approach, the devil isn't in the theory but in component selection and understanding component limitations. From comments, this arose: - my intention was to ask how I could go about mimicking the attenuation as plotted in the graph, using the circuit topology as shown The data sheet says this: - Total Common-Mode Capacitance 2 x 9.4 nF Total Differential-Mode Capacitance 336 nF This tells me that you can assume this: - C3 = C4 = 4.7 nF C1 + C2 = 332 nF (336 nF minus C3 in series with C4) The data sheet also says this: - Tcase = 25ºC 230 mΩ (series resistance of filter) Zero Load, 115 Vrms 60 Hz 0.1 W Zero Load, 115 Vrms 400 Hz 0.6 W Hence, you can start to figure out the values of series resistance especially in those inductors that I've marked L1 above. From the attenuation graph you can see that at about 1 kHz the DM attenuation is about 7 dB so you can double check the numbers and, because this is such a low frequency you can assume that the inductors are not playing a significant role in opposing currents. The front page of the data sheet says this: - Differential & Common-mode Output Attenuation >40dB @ 250kHz But, if you are choosing values, it should be more like 40 dB attenuation at 120 kHz: - Then, just keep plugging away at it covering every little hint in the data sheet you can find. Cross-check the numbers and you're good to go. It'd probably take me 4 hours but, it might take you 2 days. That's the way it is unfortunately; experience trumps inexperience!
H: Filter noise using MATLAB to include in LTspice I have measured a voltage, and I need to include the .txt file in my LTSpice simulation. Before doing that, I first want to filter the noise I ended up measuring (see figure below). How can I do that using MATLAB? AI: So what you are after is filtering. However, you are in a really good position as you have the complete set of data and do not need to perform "real time" filtering. "real time" filtering using FIR and IIR are good but introduce errors as they are causal and these errors are typically gain and phase related. With the complete dataset a range of "offline" post-processing methods are available to you which you would not be able to fully realise in real-time. filtfilt. This type of filtering filters forward and reverse to mitigate the phase shift that filters typically introduce: https://www.mathworks.com/help/signal/ref/filtfilt.html Savitzky-Golay Filters An advanced weighted least squares tracking filter which is extremely effective at extracting the underlying characteristics by providing lower significant on transient type effects. https://www.mathworks.com/help/signal/ref/sgolayfilt.html Kalman filter an acausal type filter using "look ahead" to extract the true underlying trend https://www.mathworks.com/help/control/ug/kalman-filtering.html perfect Sinc filter A sinc waveform which matches the length of the complete data is a true "brick wall" filter https://www.mathworks.com/matlabcentral/fileexchange/42956-sinc-filter My personal favorite is the SavGol filter t= linspace(0,1e-3,10000); y = zeros(10000,1); y(t> 100e-6 & t < 300e-6) = 10; y = y + rand(10000,1); Ysav = sgolayfilt(y, 5, 9); Y1stord = lowpass(y,1000,1/t(2)); figure; plot(t,y); hold; plot(t,Ysav); plot(t,Y1stord) legend('raw data','SavGol filter','1st order LPF'); Basically you want filtering but you do not need to restrict yourself to the classic LPF (FIR,IIRC, R-C type filtering) as you have the complete dataset and thus more opportunities available
H: How to remove floating teardrops after removing the object they were attached to in Altium Designer? I removed a via and the tracks connected to it after removing the associated net and this left the teardrops in place; impossible to select, and not getting removed with "remove all" in the teardrop tool. I also found another one that was left when using "delete/all" and exhibits identical behavior despite the objects it was attached to still existing. How do I get rid of them? AI: After closing and reopening the file the teardrops were possible to select and delete using the "Regions" selection filter.
H: Why do I have a sudden current peak when PWMing a valve? I am driving a proportional solenoid valve with PWM from an MCU as follows: The voltage of the MCU is 3.3 V. The gain of the amplifier is set to 20 V/V. Because the valve consumes 170 mA when fully opened, the maximum ADC voltage is 1.7 V with a 0.5 ohm resistor. TSC103 datasheet. Datasheet of the valve Here are the curves at low frequency (100 Hz): Red is the voltage between ADC input and GND. Yellow is the voltage between the gate of the MOSFET and GND (Vgs) It seems normal, but if I zoom in on the curves at the switching moment, here is what we can see: (The frequency is now 40 kHz but this behavior is present whatever the frequency.) As you can see there is a decreasing current for some μs when the transistor switches. At a higher duty cycle (90%), this is what I get: (You can ignore the blue curve, it is the voltage between the anode of the diode and GND) I do not understand what's causing this issue. The problem is that I need to measure the current passing through the valve when the PWM is 40 kHz, and at this frequency, the peak really becomes a problem. Do you know the cause of this? What solution could I implement to solve it? AI: The first trace is OK. Next of them are not. Possibly the issue is the gate driving circuit - you didn't measured the Vds, I don't believe you can drive the MOSFET at 40kHz without appropriate gate driver. Next thing is the CMRR of the sense amplifier. You don't have any low pass filter on the input of the opamp. As you can see the red trace is flat with some spikes, sure something is wrong. EDIT: How to filter the input of a high-side current sensing At 100Hz Vgs VS IL At 40kHz DT=50% IL Vgs VS. IL You should get a flat response at 40kHz. Try to connect two probes on Rshunt and then use scope math to subtract. Note that GPIO current is very high, assumed that ON/OFF resistance is 50 Ohm, but can be even higher. So you should group several GPIOs parallel and add external gate resistor. Then you turn ON/OFF GPIOs synchronously (not with digitalWrite() or similar command).
H: What are the advantages of an instrumentation amplifier over a single op amp amplifier? Basically, strain gauges are going to be connected to a Wheatstone bridge and the output from the bridge will be amplified by an instrumentation amplifier. But what are the advantages of this over a single op-amp amplifier? AI: With a bridge there are two inputs which are both similar source impedance, so an instrumentation amplifier may make sense to measure the difference in voltage. The high impedances on both inputs mean that the gain is isolated from any changes in the absolute value of the resistances. Downsides include more complicated saturation characteristics, (all other things being equal) more front end noise by (ideally) about 40%, more complexity etc.
H: STM32 PDR_ON Pin Internal Power Supervisor Explanation I want to implement STM32F746NG on my PCB - the one from the STM32F746-DISCO with display and SDRAM, Flash and other peripherals. The MCU has a PDR_ON pin, which I have never met before. I searched for it and found different threads and STMicroelectronics documents, but ST documents are usually very cryptic when you read them for the first time and not familiar with topic yet. So I would want someone to make sure I understand stuff correctly and, if possible or necessary, "dumbify" it a bit. What I understood about PDR_ON/Internal Power Supervisor PDR_ON controls internal power supervisor, which is an internal device(if that word is applicable?) that basically makes sure the voltage on VDD is sufficient and stable, and only then it releases reset and lets MCU start. Tying PDR_ON to VDD turns it on, tying it to VSS turns if off. If the internal supervisor is off, then some external circuit should release reset with a little pause after the voltage is above minimal threshold. Did I understand it correct? About power supplies in my specific project In my project the MCU will get a regulated 3.3V supply (via buck-boost from battery); Same supply goes to VDDUSB, VBAT (not expecting to use USB or RTC) and via ferrite bead is fed into AVDD and VREF+ (will use ADC/DAC). I will have a 10k from 3.3V to Reset pin (although I hear it's not mandatory due to internal pull-up, but it won't hurt anything anyway; I can always leave pads unpopulated) and the reset pin will have an external 0.1uF cap. All of this, I believe, will give sufficient pause for reset release. PDR_ON state selection Quote from the document attached above AN4938, page 18: The supply ranges which never go below 1.71 V minimum should be better managed by the internal circuitry (no additional component needed, thanks to the fully embedded reset controller). Does it mean I just connect PDR_ON to VDD and I'm done? AI: If you do not wish to do anything special, just tie PDR_ON to Vdd and the MCU will work just like any other which does not have the PDR_ON pin. See chapter 2.17.1 in the Datasheet: On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled.
H: Asymmetric sine wave I've got a signal generator sending a sine wave to a PCB (X3). I closed jumper 19 so I measure D10, a GF1M diode. I measured the voltage over test point 16 (TP16) and the voltage over TP18. I get the following image on an oscilloscope. As expected we see that the voltage over TP16 is rectified (red CH2). The voltage over TP18 is an asymmetric sine wave (blue CH1). The width of the parts under 0 is smaller than the width of the parts above 0, but I don't understand why this is the case. AI: Think of the diode as conducting fully after the voltage across it exceeds 0,7V. This will then connect the "load" with the generator source and the voltage divider (resulting from the generator source impedance with the load impedance) will gradually kick-in for the positive part of the cycle (but with a diode exponential type gradual increase). Then for the negative going cycle, the diode is switched off and there is nothing loading the source, and the sine wave looks all perfect and symmetrical during the negative cycle, as one would expect.
H: How can I make this kind of hole or drill in Altium? I'm trying to add this component to my design in Altium but I don't understand this kind of "holes" (I suppose it can't be drilled properly.) I can't find any tool in Altium to design this hole. Is there a way to do it? I have tried to do 2 holes and put on one over the other but on 3D view it can be seen this (i'm trying to d this from footprint editor): AI: Two possible ways: Combine two slot holes: Draw both hole and annular ring with lines, convert it to the board cutout (Tools - Convert - Create board cutout) and copper region (Tools - Convert - Create region) In both cases, you'll need to override DRC rules. The situation will be easier for a first case because it's just one rule - hole-to-hole clearance. Also, it'll be a good idea to warn your PCB house about this stuff because it doesn't quite fit into "standard" PCB features. If the PCB house won't know what you want to achieve - there is a possibility to receive manufactured PCB without slot plating.
H: Will a synchronous circuit have a race condition if not all inputs arrive before the clock rising edge? Suppose that the circuit has several inputs from an external circuit which do not have an effect until the clock next rise edge due to using synchronous flip-flops. If the external circuit sends several inputs and because there is a different propagation delay for each line one or two inputs arrive late after the clock has rise and after other inputs were activated will the circuit encounter a hazard? AI: If the delays are constant and those inputs always arrive after the clock edge, there is no race condition, there is a pipeline error. You can solve this by (for example) delaying the faster input by a clock period to match the other inputs : this Q&A illustrates a pipeline error and its resolution. If the delays are variable (or the input is completely unsynchronised) there is a race condition, and several bad things can happen when the input arrives at approximately the same time as the clock edge. Very rarely, this results in metastability, where the two (data and clock) arrive at precisely the same instant so that the changing data cannot be resolved as either '0' or '1'. This can result in an intermediate output state which takes a long time (worst case, more than a clock period) to resolve into a valid logic level. (In modern FPGA technology, "very rarely" translates into "maybe once or twice before the heat death of the universe" though in the early 2000s it was a more significant problem. Much more commonly, (and often confused with metastability) the input signal arrives at two or more destinations within the circuit, before the clock edge at one register, and after it at another, and is thus seen as both '0' and '1' by different parts of the circuit.
H: How to derive the transfer function of this op-amp? For the 1st question, is this a Sallen-Key filter? What criteria must a circuit possess in order for it to classified as a Sallen-Key filter? I searched the internet but found no clear answer. For finding the frequency: my attempt, see below, defines node voltages Va and Vb and uses nodal analysis to find the transfer function, treating vo = vb since the opamp will regulate the voltage at the inverting input the same as the non-inverting input. After finding the transfer function, I differentiated with respect to f to find the value in terms of R and C. $$\frac{v_i-v_a}{R}=\frac{v_a-v_b}{R}+\frac{v_a-v_b}{\frac{1}{jwc}}$$ $$\frac{v_a-v_b}{\frac{1}{jwc}}=\frac{v_b}{R\|\|\frac{1}{jwc}}$$ After substituting Va in terms of Vb,A = Vb/Vi, I got the equation below: $$gain=\frac{jwc}{3+w^2Rc-j(6wRc+wc)}$$ This is as far as I got, I am stuck on how I can get the above answer. Is the nodal analysis equation I derived correct? AI: Nodal analysis is the way to go. You can work on s-domain to make the life easier. According to your schematic, \$\mathrm{v_b=V_o}\$. Using the properties of a closed loop operational amplifier, you'll get $$ \mathrm{ V_i+(1+s\ RC)V_o=(2+s\ RC)V_a } $$ where $$ \mathrm{ V_a=V_o\frac{1+2s\ RC}{sRC} } $$ So the gain function can be written as $$ \mathrm{ G=\frac{V_o}{V_i}=\frac{u-1}{u^2+2u-1} } $$ where $$ \mathrm{ u=1+s\ RC } $$ Before you ask, this \$u\$ comes from using the paralleled impedances R and C across \$\mathrm{v_b}\$ and GND. After the substitution, you'll get $$ \mathrm{ G=\frac{s/(RC)}{s^2+\frac{4}{RC}s+\frac{2}{R^2C^2}} } $$ It's obvious that this is a transfer function of a second order system which has a transfer function of $$ \mathrm{ G=A\frac{\omega_n^2}{s^2+2\zeta \omega_n+\omega_n^2} } $$ but with an extra zero. So, re-arranging the final equation so that it forms like the one above gave me $$ \mathrm{ G=\frac{s\ RC}{2}\cdot \frac{\frac{2}{R^2C^2}}{s^2+\frac{4}{RC}s+\frac{2}{R^2C^2}} } $$ From here, you can go for either substituting \$s\$ with \$j\omega\$, or differentiating, or any other technique. But eventually, you'll find that the maximum gain occurs at \$\mathrm{\omega=\sqrt{2/(R^2C^2)}=\sqrt2/(RC)}\$.
H: Impact of Bandwidth Increase on Shannon Capacity What is the impact of doubling of bandwidth on Shannon Capacity, assuming noise power spectral density and signal power remain the same? AI: Recall the statement of the Shannon-Hartley Theorem, which gives a theoretical bound on the channel capacity1: $$C = B \log_2\left(1+\frac{S}{N}\right)$$ Under your assumptions, the bandwidth doubles, while the noise PSD stays the same. This means that the noise power roughly doubles (in practice the performance of the bandpass filter is also relevant here). Because you're dealing with an unchanged signal power, you're now looking at: $$C^\prime = 2B \log_2\left(1+\frac{S}{2N}\right)$$ Note that for all possible (i.e. positive real) SNR values, \$C^\prime \geq C\$. However, note that \$C' \neq 2C\$ (see interactive graph). However, \$C'/C\$ does approach 2 as SNR increases, very slowly (e.g. at 90 dB SNR, the ratio is 1.933). 1 A practical realization of a communication channel may not necessarily realize the theoretical bound, or may only realize it asymptotically.
H: Arduino NANO heating issue I am trying use a HMI display with arduino NANO. I am powering arduino and hmi display ( topway 5 inch smart display ) with 9 volt adaptor. everyting works fine. but if I plugin the Tx, Rx pins which are coming from rs232 ttl converter (this device) to arduino nano's Rx and Tx pins, arduino nano is starting heating. I have waited one day heating was not to much but there was a heating issue. Also there is no problem communication between arduino nano and hmi display. If I plug out the rx and tx pins, there was no heating even after one day waiting. everythings looks fine. I guess that heating will make a problem in future within long term usage. also if I powering rs232 converter with 5 volt, this time rs232 converter heating too much and broken. Therefore, I am powering rs232 converter with 3.3 volt. if I powering 3.3 volt there is no heating on rs232 converter. this is my circuit diagram, sorry about my paint skill. well, I didnt understand why arduino nano heating and how to fix that. Can you help me AI: The Nano uses a 5V MCU (ATMega328). If you are going to connect it directly with the SP3232 then it should operate from the same supply or have a voltage translator between. The SP3232, if it is genuine (doubt) should withstand up to 5.5V. That's not a lot of margin between that and 5V and you have routed the 500mA max current from the display through the RS-232 adapter board, which is bad. Run the ground wire from the display back to the supply directly. You don't need another ground wire to the adapter, there is enough noise margin in the RS-232. I have seen similar genuine chips fail from minor disturbances in the supply, they are not as robust as the old 5V-only MAX232 chips.
H: How important is a PCIE_PEG_TXN pin on a motherboard? I managed to break the PCIE_PEG_TXN 2 pin on my motherboard according to this pin layout: https://sector.biz.ua/docs/lga-775-1150-1151-1156-1155-1366-2011-pinouts/s1200_1.png I am curious if it is wise to start the computer without this pin. I assume it is for sending data to the first PCIE slot on the second PCIE lane. The positive is still there, but I guess without this negative pin it is not possible to close the circuit. Maybe it is not a big deal and I will just lose a PCIE lane, maybe it is a big issue and the CPU, motherboard, video card will burn down and it will cause meltdown in the near nuclear reactor. What do you think? AI: I'll assume by "broken" you mean physically snapped the pin off (i.e. didn't short it out etc.). In this case theoretically nothing catastrophic will happen. It is reasonably safe to boot the computer in such a state and for the most part it will work ok. What you will find however is that your graphics card will not link up at the full x16 width (or if bifurcation is being used the first port won't link at x8). This is because without both the _P and the _N part of a lane, the lane will be dead. Fortunately, the PCIe spec mandates that all PCIe devices must be able to support x1 mode. This means your graphics card will in all likelihood work just fine. During the link training process it will detect that one of the lanes is non-functional, and so fail back to x1 mode (). Thus it will still work, just slower. Some PCIe devices also support intermediate widths. If supported your graphics card may actually link up at x2 width, but there is no requirement to support that, so in all likelihood it will remain at x1 width. It will not link at a partial width (e.g. x15, or x8) because all lanes must be consecutive starting with Lane 0. () If it had been Lane 0 that you broke, no link could be established as that is the one lane required to establish a link.
H: Exporting LTSpice waveform data from Monte Carlo simulation and manipulate it in MATLAB So I am doing a Monte Carlo Simulation on LTSpice. Then I want to export my data and manipulate it in MATLAB. Here is a working example file, just with 2 decades each one with 11 points and 6 iterations of Monte Carlo: Freq. V(vout) Step Information: X=0 (Run: 1/6) 1.00000000000000e-002 (-6.26777881841443e+000dB,-2.45632080921360e+001°) 1.25892541179417e-002 (-6.36861181114449e+000dB,-3.06433832660851e+001°) 1.58489319246111e-002 (-6.50874601655850e+000dB,-3.80698128918313e+001°) 1.99526231496888e-002 (-6.68840252431672e+000dB,-4.70502691728284e+001°) 2.51188643150958e-002 (-6.88767600648017e+000dB,-5.78295465358373e+001°) 3.16227766016838e-002 (-7.04662306199209e+000dB,-7.08121145050537e+001°) 3.98107170553497e-002 (-7.04613385608013e+000dB,-8.69037556678446e+001°) 5.01187233627273e-002 (-6.73302774870351e+000dB,-1.08291925528466e+002°) 6.30957344480194e-002 (-6.17898060206205e+000dB,-1.39490624870074e+002°) 7.94328234724282e-002 (-6.29156027893901e+000dB,1.76371893719709e+002°) 1.00000000000000e-001 (-7.00343610611535e+000dB,1.25917428931445e+002°) 1.25892541179417e-001 (-6.07744581972252e+000dB,4.88363107428150e+001°) 1.58489319246111e-001 (-6.92190787935448e+000dB,-1.05087106512531e+002°) 1.99526231496888e-001 (-3.64476579715909e+001dB,1.50248213268233e+002°) 2.51188643150958e-001 (-5.65563441261771e+001dB,1.30679615367055e+002°) 3.16227766016838e-001 (-7.35748460393752e+001dB,1.19998987277993e+002°) 3.98107170553498e-001 (-8.92621053142513e+001dB,1.12887963014667e+002°) 5.01187233627273e-001 (-1.04257065089212e+002dB,1.07760106447624e+002°) 6.30957344480194e-001 (-1.18860319936777e+002dB,1.03910331684806e+002°) 7.94328234724282e-001 (-1.33231869456083e+002dB,1.00954550855709e+002°) 1.00000000000000e+000 (-1.47462843245236e+002dB,9.86551571694855e+001°) Step Information: X=1 (Run: 2/6) 1.00000000000000e-002 (-6.16672256403144e+000dB,-2.44850335449979e+001°) 1.25892541179417e-002 (-6.26639121158446e+000dB,-3.05477574094463e+001°) 1.58489319246111e-002 (-6.40485695767013e+000dB,-3.79544592941995e+001°) 1.99526231496888e-002 (-6.58222673567182e+000dB,-4.69137543618026e+001°) 2.51188643150958e-002 (-6.77853960525347e+000dB,-5.76720745778276e+001°) 3.16227766016838e-002 (-6.93392757217094e+000dB,-7.06368382452438e+001°) 3.98107170553497e-002 (-6.92972272669119e+000dB,-8.67198835897928e+001°) 5.01187233627273e-002 (-6.61488302611489e+000dB,-1.08121876478984e+002°) 6.30957344480194e-002 (-6.07070535374054e+000dB,-1.39362050183132e+002°) 7.94328234724282e-002 (-6.21965984211102e+000dB,1.76590682774648e+002°) 1.00000000000000e-001 (-6.95327975730355e+000dB,1.26605975615689e+002°) 1.25892541179417e-001 (-5.98464834532776e+000dB,4.97190587873480e+001°) 1.58489319246111e-001 (-6.40417682367860e+000dB,-9.75145351869804e+001°) 1.99526231496888e-001 (-3.60323515588510e+001dB,1.49599381516468e+002°) 2.51188643150958e-001 (-5.62806798193614e+001dB,1.30188107624632e+002°) 3.16227766016838e-001 (-7.33429304420458e+001dB,1.19642264129678e+002°) 3.98107170553498e-001 (-8.90496342710569e+001dB,1.12621087528093e+002°) 5.01187233627273e-001 (-1.04054663427162e+002dB,1.07555972526800e+002°) 6.30957344480194e-001 (-1.18663568970525e+002dB,1.03751971633780e+002°) 7.94328234724282e-001 (-1.33038438305737e+002dB,1.00830612529090e+002°) 1.00000000000000e+000 (-1.47271416461901e+002dB,9.85576222906644e+001°) Step Information: X=2 (Run: 3/6) 1.00000000000000e-002 (-6.21225990393714e+000dB,-2.42398271464396e+001°) 1.25892541179417e-002 (-6.30909308389625e+000dB,-3.02474562172609e+001°) 1.58489319246111e-002 (-6.44368675411592e+000dB,-3.75911929919443e+001°) 1.99526231496888e-002 (-6.61617014498940e+000dB,-4.64809809162114e+001°) 2.51188643150958e-002 (-6.80702103232767e+000dB,-5.71648578399885e+001°) 3.16227766016838e-002 (-6.95744340949862e+000dB,-7.00503088335492e+001°) 3.98107170553497e-002 (-6.95058694718676e+000dB,-8.60451477040284e+001°) 5.01187233627273e-002 (-6.63826350750918e+000dB,-1.07340680147192e+002°) 6.30957344480194e-002 (-6.10854527731718e+000dB,-1.38439087101438e+002°) 7.94328234724282e-002 (-6.30362830475549e+000dB,1.77802087261242e+002°) 1.00000000000000e-001 (-7.12172801096167e+000dB,1.28771964802357e+002°) 1.25892541179417e-001 (-6.03607855680839e+000dB,5.40055044059610e+001°) 1.58489319246111e-001 (-6.09076329776158e+000dB,-7.96416809130710e+001°) 1.99526231496888e-001 (-3.50723893849773e+001dB,1.49324548669222e+002°) 2.51188643150958e-001 (-5.56565653180954e+001dB,1.29763151240751e+002°) 3.16227766016838e-001 (-7.28297203350366e+001dB,1.19299898524730e+002°) 3.98107170553498e-001 (-8.85876592266688e+001dB,1.12354271502988e+002°) 5.01187233627273e-001 (-1.03619895627022e+002dB,1.07347693711844e+002°) 6.30957344480194e-001 (-1.18244315768821e+002dB,1.03588572559094e+002°) 7.94328234724282e-001 (-1.32628393065329e+002dB,1.00701890827225e+002°) 1.00000000000000e+000 (-1.46866966442567e+002dB,9.84559235597901e+001°) Step Information: X=3 (Run: 4/6) 1.00000000000000e-002 (-6.22331279803977e+000dB,-2.46332673587796e+001°) 1.25892541179417e-002 (-6.32504917213284e+000dB,-3.07272672560921e+001°) 1.58489319246111e-002 (-6.46623144544338e+000dB,-3.81680557698355e+001°) 1.99526231496888e-002 (-6.64677864154134e+000dB,-4.71624573226846e+001°) 2.51188643150958e-002 (-6.84606579338628e+000dB,-5.79553475142998e+001°) 3.16227766016838e-002 (-7.00283755937839e+000dB,-7.09556477273628e+001°) 3.98107170553497e-002 (-6.99627249573579e+000dB,-8.70859007405126e+001°) 5.01187233627273e-002 (-6.67343602866177e+000dB,-1.08579125550146e+002°) 6.30957344480194e-002 (-6.12030688950781e+000dB,-1.40015647535145e+002°) 7.94328234724282e-002 (-6.27478190951681e+000dB,1.75681713302692e+002°) 1.00000000000000e-001 (-6.99206525364281e+000dB,1.25430995493748e+002°) 1.25892541179417e-001 (-6.03691617350726e+000dB,4.75748098362317e+001°) 1.58489319246111e-001 (-6.78167767121785e+000dB,-1.05705064001918e+002°) 1.99526231496888e-001 (-3.66017286534973e+001dB,1.49104719709746e+002°) 2.51188643150958e-001 (-5.67225468275595e+001dB,1.29982261243041e+002°) 3.16227766016838e-001 (-7.37401305848446e+001dB,1.19514081606539e+002°) 3.98107170553498e-001 (-8.94256387901318e+001dB,1.12530467253416e+002°) 5.01187233627273e-001 (-1.04419241358117e+002dB,1.07488355447641e+002°) 6.30957344480194e-001 (-1.19021571859160e+002dB,1.03700150338241e+002°) 7.94328234724282e-001 (-1.33392517159571e+002dB,1.00790315794714e+002°) 1.00000000000000e+000 (-1.47623102632076e+002dB,9.85260246778205e+001°) Step Information: X=4 (Run: 5/6) 1.00000000000000e-002 (-6.23268747704643e+000dB,-2.50410800230128e+001°) 1.25892541179417e-002 (-6.33917575843080e+000dB,-3.12217854974529e+001°) 1.58489319246111e-002 (-6.48629042886293e+000dB,-3.87581607866792e+001°) 1.99526231496888e-002 (-6.67304499854865e+000dB,-4.78538422903985e+001°) 2.51188643150958e-002 (-6.87639806629557e+000dB,-5.87536116429439e+001°) 3.16227766016838e-002 (-7.03051544993454e+000dB,-7.18804940213071e+001°) 3.98107170553497e-002 (-7.00828150775649e+000dB,-8.82104246417903e+001°) 5.01187233627273e-002 (-6.65530648891537e+000dB,-1.10119730420866e+002°) 6.30957344480194e-002 (-6.09469920219503e+000dB,-1.42405205514390e+002°) 7.94328234724282e-002 (-6.34016880658946e+000dB,1.72505719420889e+002°) 1.00000000000000e-001 (-7.04017166605841e+000dB,1.21990674426408e+002°) 1.25892541179417e-001 (-6.07437235545994e+000dB,4.12337724162087e+001°) 1.58489319246111e-001 (-8.18869568325135e+000dB,-1.25105992577795e+002°) 1.99526231496888e-001 (-3.80083248976535e+001dB,1.47144346294457e+002°) 2.51188643150958e-001 (-5.78497981809793e+001dB,1.28956714532505e+002°) 3.16227766016838e-001 (-7.47637582348090e+001dB,1.18825272338581e+002°) 3.98107170553498e-001 (-9.03986136722447e+001dB,1.12028380207313e+002°) 5.01187233627273e-001 (-1.05364437014045e+002dB,1.07108394410606e+002°) 6.30957344480194e-001 (-1.19950616999652e+002dB,1.03406857883888e+002°) 7.94328234724282e-001 (-1.34311862227457e+002dB,1.00561359030665e+002°) 1.00000000000000e+000 (-1.48536509737044e+002dB,9.83460945944903e+001°) Step Information: X=5 (Run: 6/6) 1.00000000000000e-002 (-6.25082744156451e+000dB,-2.47181947915387e+001°) 1.25892541179417e-002 (-6.35355099949484e+000dB,-3.08297344200067e+001°) 1.58489319246111e-002 (-6.49590256038996e+000dB,-3.82894691652311e+001°) 1.99526231496888e-002 (-6.67751099794831e+000dB,-4.73034739546178e+001°) 2.51188643150958e-002 (-6.87704700139995e+000dB,-5.81169846727973e+001°) 3.16227766016838e-002 (-7.03196827194024e+000dB,-7.11437980905331e+001°) 3.98107170553497e-002 (-7.01979302428447e+000dB,-8.73238848974908e+001°) 5.01187233627273e-002 (-6.68796414576871e+000dB,-1.08936886014197e+002°) 6.30957344480194e-002 (-6.13713289323238e+000dB,-1.40629994073302e+002°) 7.94328234724282e-002 (-6.33523944865220e+000dB,1.74880767731570e+002°) 1.00000000000000e-001 (-7.06204694631925e+000dB,1.24795188737801e+002°) 1.25892541179417e-001 (-6.07176510225266e+000dB,4.62141099523223e+001°) 1.58489319246111e-001 (-6.94683355469541e+000dB,-1.07596087699931e+002°) 1.99526231496888e-001 (-3.68700051939526e+001dB,1.48337323013288e+002°) 2.51188643150958e-001 (-5.69761930020967e+001dB,1.29501884676301e+002°) 3.16227766016838e-001 (-7.39858496501359e+001dB,1.19174614947729e+002°) 3.98107170553498e-001 (-8.96667862090866e+001dB,1.12277917628911e+002°) 5.01187233627273e-001 (-1.04657656100839e+002dB,1.07295362073189e+002°) 6.30957344480194e-001 (-1.19258318601153e+002dB,1.03550408363673e+002°) 7.94328234724282e-001 (-1.33628232853353e+002dB,1.00673080554496e+002°) 1.00000000000000e+000 (-1.47858176057854e+002dB,9.84337357907819e+001°) So I already have a code that works with in case of a plot with just 1 iteration (it doesn't have the "Step Information: X=0 (Run: 1/6)" line . I've adapted this from another code I've seen. clc; close all; clear all; filename = 'FrequencyResponse.txt'; filetoread = fopen(filename, 'rt'); Dummy= textscan(filetoread, 'Freq. V(vout)', 'CollectOutput', 1); DataScanned = textscan(filetoread, '%f(%fdB,%f°)', 'CollectOutput',1); fclose(filetoread); D = cell2mat(DataScanned); D(:,1)=D(:,1)2pi; figure subplot(2,1,1) semilogx(D(:,1), D(:,2)) title('Amplitude (dB)') grid subplot(2,1,2) semilogx(D(:,1), D(:,3)) title('Phase (°)') grid xlabel('Frequency') So yeah this code works for just a normal simulation. Now for Monte Carlo there are a lot of challenges that I am facing. For instance: 1 - How should I read the "Step Information yada yada" and then read all the values and then stop at the next step information. 2 - How to read the number of iterations? 3 - How should I store the info of each interation? I'm thinking of a matrix, each column for each Monte Carlo iteration (frequency, voltage magnitude, voltage phase). But I already have a 3 column matrix... Some help would be appreciated. I have little experience with MATLAB and I always struggled with reading files in C. So this is really confusing for me. AI: Something along the lines of this: fn = "test_dat.txt"; % Filename variable - no trailing carriage return S = readlines(fn); % read all lines into an array STEP=0; % initialise counter results = struct.empty; % initialise result structure rx = '[+-.e0-9]' % create regex pattern to match exponent numbers for i=2:length(S) % loop over every line BUT skip the 1st if startsWith(S(i),'Step') % check if the line starts with the word "step", if so use this as a marker for a new step group STEP = STEP+1; % increment the STEP counter results(STEP).data = [0 0 0]; % seed a new results array else num = str2double(regexp(S(i),rx,'match')) % match the three exponential numbers in a line based upon regex pattern results(STEP).data = [results(STEP).data ; num(1) num(2) num(3)]; % create an row and append to the results table associated with this STEP end end figure; % create a figure subplot(2,1,1); % select 1st subplot ylabel('Amplitude (dB)'); % set y label xlabel('Frequency'); % set xlabel set(gca, 'XScale', 'log'); % change xaxis to log hold; % hold plot to permit multiple plots in one axis grid; % turn on grid subplot(2,1,2) % same steps for 2nd subplot ylabel('Phase (°)') xlabel('Frequency') set(gca, 'XScale', 'log'); hold; grid; for i = 1:numel(results) % start looping over all entries in the results struct subplot(2,1,1) % select upper subplot plot(results(i).data(:,1)2pi, results(i).data(:,2)); % plot freq (1st column) and mag (2nd column) subplot(2,1,2) % select lower subplot plot(results(i).data(:,1)2*pi, results(i).data(:,3)); % plot freq (1st column) and angle (3rd) end
H: How to safely temporarily wire 120v? I am wondering if there is any device to safely create a wire connection? More specifically, here is my most recent situation: troubleshooting a noisy 120V electric motor (fireplace blower). The motor had a proprietary 2-wire plug which connected to the fireplace wiring, but using that wasn't an option when I was in the garage trying to give it power. I ended up hooking up two small alligator clips to the two prongs inside the connector and then hooking the other end of the alligator clips to an electrical cord which I had cut open and exposed the two wire ends. I would plug the electrical cord into my power strip, switch on the power strip, and run the motor. The alligator clips just hanging of loose wiring made me nervous, and indeed at one point I somehow bumped the assembly, the wires touched and boom I flipped the circuit breaker and was in the darkness. Ugh. Trying to figure out if I can do something a bit more foolproof next time... My approach seems great for automotive 12V, but doing the same 'just use some nails/twist the wires together' seems like a bad idea with 120V! I saw something of this sort on amazon: I am thinking that could be an easy way to connect wires together. This device could permanently sit on my power cord and I could plug raw wires from whatever I'm testing into it? AI: These connectors are designed for quickly and safely connecting power to a unterminated mains cable for testing purposes - This example has a datasheet available here Power is only applied once the cover has been closed.
H: Find RL circuit average power when no AC amplitude is given I am asked to find the average power of this RL circuit, assuming that \$R\$, \$L\$ and the frequency (\$\omega\$) and phase (\$\phi\$, can be zero) are given. But nothing is said about the amplitude \$A\$ of the alternating current source. I can calculate the voltage across the \$R\$ and \$L\$ using Ohm's law and phasors, but I will get the amplitude \$A\$ in my expression. Then I can use the following formula of average power, depending on the phasors of voltage and current: $$P_{\text{avg}} = \dfrac{V_m \cdot A \cdot \cos(\theta_I - \theta_V)}{2}$$ And here the \$A\$ will be squared. So we can't throw it away. Maybe there is another (unknown to me) way to solve this specific problem, or it is impossible to solve this question without the amplitude \$A\$. In fact, it seems weird to get a power value when the amplitude \$A\$ can be zero. AI: In your problem, you are not given numerical values of R, L frequency and phase (at least you have not shown them in your question). Why are you concerned that a numerical value for amplitude is not given? You simply solve the problem using symbols for all of the parameters. If values are given later, then you substitute them in your answer. Its not weird to have the power be 0 if the input amplitude is 0. That is to be expected and, in fact, is a quick check on your symbolic answer.
H: Efficiency of green High Power LED compared to efficient white Whenever I see color High Power LEDs (for example green 3W on Star) I see disappointing efficiencies: For 520 nm the theoretical efficiency is 683 lm/W * 0.88 (green) = 601 lm/W. But most are described with 110 lm / 3W (Example)= 37 lm/W which is a conversion of electricity to light of 6%. There aren't phosphor losses and we talk about the efficiency of the LED without power converters. I wonder why they are so inefficient while white LEDs (not necessarily High Power) with phosphors often have a efficiency of 100 lm/W? AI: Due to the high demand in consumer electronics - especially lighting applications - both "blue" semiconductors (mainly GaN) and phosphor coatings have been developed further and further in recent years. Green LEDs are only used in niches. This is especially true for green high-power LEDs, because efficiency is much less important in low-power applications like LED displays or signalling. Some time ago I developed a framework that allows me to convert all various photo- and radiometric units into each other based on the corresponding spectra. I can confirm that your conversions between luminous and radiant/electrical efficiency are correct. However, I don't agree that green LEDs are as inefficient as you say. The LED you refer to is simply an example of a particularly bad LED. For the famous LM301B white LED (operated at 100mA, which is half abs max), I get a radiant efficiency of ~70% and a luminous efficiency of 220 lm/W. According to my framework, the GT QSSPA 1.13 (521nm) by Osram has a radiant efficiency of ~30% (140 lm/W) at Imax/2. Even though this is obviously much worse than the LM301, it's still much better than what you assumed. One should not forget that LEDs have improved greatly in the last years and the efficiency of less important colors is simply still at the level that was common a decade ago. When I look at the other LEDs I deal with, there is clearly a correlation between the efficiency of an LED and its demand on the global market. For example, the efficiency of red LEDs, which play a role in the automotive market (tail and brake lights) or in plant lighting, has improved greatly as well. On the other side: if you take a look at how other colors like yellow, far-red or UV perform, you'll see they are all more or less at the level of green ones. So the simple answer is: a lot of effort has gone into improving certain LEDs. Another point is, that cheap no-name LEDs generally perform much worse than those you get from reputable manufacturers which are specialized in LED manufacturing. A comparison is simply not fair.
H: PCB clearance/creepage with dead metal I have PCB design where there are two pads the may be shorted (manually in assembly) or left as is, depending on the product model. The through hole circular pad is actually for a terminal block. I wanted to maintain ~3mm clearance between CN3 and CN8 since there is at least on case wherein: CN3 is connected (via leadwire) to a 2nd relay's common (COM) pin and CN8 is connected to 1st relay's normally closed pin (NC). I want to isolate the contact lines of two different relays. However, I also want to make it easier for the worker who will short CN3 and CN8. There is a case wherein CN3 and CN8 are shorted because: In one product model, there is only one relay. In one-relay model, there are "submodels" wherein the NC of relay is accessible to user or not (User access is via CN3 since it is connected to terminal block). So for NC-accessible type, CN3 and CN8 should be shorted by a vertical solder bridge. We find it hard to do this with a leadfree solder. Our two options: User a wire or a resistor leg to make shorting CN3 and CN8 easier. Add a dead metal between CN3 and CN8 to make shorting easier. I am curious about 2. Will adding dead metal affect the designed 3mm clearance/creepage between CN3 and CN8? I am more inclined that the answer is no, because of how clearance (pt-pt distance between the two copper in question) and creepage (distance between the two copper along an insulator) is defined. But I also know that some high voltage can cause "arcing" when two conductors are close to each other. Addition note: Relay loads are: 250VAC or 30VDC, both 5A max AI: The metal would (at best) subtract from the clearance by its width. It may be worse than that as deemed by safety agencies. I suggest a through-hole zero-ohm resistor as an option.
H: How to handle the DC charge input on the PCB for a symmetrical 5V magnetic charger cable? I'm working on a low voltage DC consumer product that specifies using a specific magnetic charge cable on the 5V input instead of a regular USB connector. See image: We started out assuming the cable wasn't symmetrical and there must be a positive and ground that could only fit one way, so we planned to just use a corresponding positive and ground pin on the PCB power input. See image: But later we found the cable is in fact symmetrical, so the user could attach it in an orientation where the positive and ground connections could be swapped. So, we can't just assume to have a static positive and ground pin as shown in the pictures, it seems we need a way to sense upon connection, which pin is positive and which pin is ground and design our circuit to handle it either way. Are there IC's we could use to help handle this? Some other approaches to the circuit design? Thank you! Note: all the images here are my own. AI: Seems the below two circuits are two ways to handle this, using either four MOSFETS or four diodes, with the MOSFET solution preferred as it results in a lower voltage drop.
H: Is it possible to use two DC-DC boost converters in series from separate DC sources? I was wondering if I could put two DC-DC boost converters in series. Each of these converters is fed from a DC source which is basically a USB charger of 230VAC to 5VDC/1A. The voltage output of these converters should have some fixed ratio (i.e. 2.) AI: Yes. As long as the 5Vdc supply is electrically isolated from the mains and the dc supplies do not share a common ground, this should work without a problem.
H: LTspice diode bridge rectifier input oscillating I've made a LTspice model of a diode bridge rectifier, but when I simulate my circuit, the input voltage is oscillating. Here is my schematic, along with the simulation result of the voltage at node 3 (marked with an arrow.) When I zoom in on these weird parts, I can see that it is definitely some kind of oscillation: I've already tried changing the position of the ground, changing the solver to an alternate solver, and introducing ESR to the capacitor. The problem seems to be correlated with the capacitor, since when I set a lower capacitance, the output gets better. The output also gets better when I set the capacitor ESR to a few ohms, but that is not very realistic. I also tried with different diode models, and the problem persists. Does anyone have an idea what could be the problem? AI: You're getting ringing from the diodes switching off in conjunction with the line inductance (and resonating with the diode capacitance when blocking- maybe 50pF or so). If you add a snubber like 100\$\Omega\$ in series with 47nF across the bridge rectifier input it should go away, mostly or entirely. It's probably unrealistic to have 200uH with zero parallel capacitance as that component of the line impedance but if that is your model, maybe you need to use it. Frequently, in audio equipment, the diodes are paralleled with a small capacitor to prevent the EMI from showing up as a nasty 100Hz/120Hz buzz in the sound.
H: Problem with the simulation of two different low-pass filters I am trying to simulate the circuit below. Why do both low-pass filters show the same behaviour, even though their component values are different? Edit: How stupid of me. I used the label "In" for the both circuit. That is the why I got same result. AI: I think that you'll find that this is "a" definite problem: -
H: Does CT act as a constant current source for a specific primary current? I connected several resistors (1, 10, 100, 560 Ω) at the output of a 1000:1 CT (0-100 A measurement). I saw that the secondary current doesn't change for different resistors for a constant primary current. If the current is constant, then I2R will be very low for a tiny sampling resistor. Is it good to use a tiny (say 1 Ω) sampling resistor? Or I am getting the whole concept wrong? AI: Is it good to use a tiny (say 1 ohm) sampling resistor? Firstly, proper names; it's a burden resistor and not a sampling resistor. So... It's best to use the lowest value burden resistor you can because it does improve the accuracy of the CT over its full range of input currents. In effect the burden resistor can be referred to the primary and "placed" in parallel with the fat input wire. That fat input wire might have 10 μH inductance as it passes through the core and, at 50 Hz, that's an impedance of 3.14 mΩ. Not much you might think and, damn right it shouldn't be much. But, the referred burden resistor of 1 Ω becomes 1000² times smaller (turns ratio squared) at 1 μΩ on the primary and, this takes the vast majority of the current that flows through the cable (rather than letting it flow through the 10 μH magnetization inductance of the cable). If your burden resistor was 560 Ω, the referred resistance on the input winding would now be 0.56 mΩ and, as you can possibly see, the vast majority of the input current does not now flow in that referred resistor hence, you start to get errors AND you start to cause core saturation problems. Does CT act as a constant current source for a specific primary current? It does in the main; that's what it's supposed to do but, don't make the burden resistor too high.

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