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H: why are there unused vias in eagle design
I have this design I grabbed online, and when I load it up in eagle and run a DRC, it gives me a bunch of airwire errors on vias that appear to serve no function. Are they just ones the designer left on there and don't care about? Is there any other possible reason why they still exist?
Here's one where there's one directly under IC1.
AI: First, airwires are not errors. They show connections specified in the schematic but that have not been realized in the board. They represent work not done yet, not mistakes necessarily.
In this case, unless you are not showing us all the copper layers, the via under IC1 makes no sense. If it is not a deliberate thru-hole pad for some purpose (not in the schematic), and it is not part of a larger structure in additional hidden layers, then it serves no purpose.
If the above is really the case, then the routing is a mess. Run away. I see several other vias that appear to serve no purpose from what you show. If this really is the case, then you should rip up the whole mess and route the board properly yourself.
Added
Just for entertainment, I looked at the board and schematic files. Yikes! What a mess!
Run away. This tiny board and schematic would be far easier to generate from scratch properly that it would take to fix this disaster. Whoever designed this was incompetent. Some obvious problems:
There are several pads too close to the edge of the board for most ordinary board house processes. I loaded my own standard DRC settings for a two layer board, and it found 10 such cases.
One of the pads is too close to a hole. This is in the upper right-ish area of the board. The pad is connected to ground.
Many of the pads are partially covered with stuff from the tDocu layer. This makes the board difficult to work with in routing, and it serves no useful purpose. For example, every pad of the 44 pin package seems to have a deliberate tDocu rectangle covering the inner ⅔ or of each pad. This makes no sense, and prevents using tDocu for legitimate purposes during routing.
The gratuitous vias that you are actually asking about are apparently due to a misguided attempt to put a partial ground plane on both sides of the board. The vias are to stich the two sides together. A much better strategy is to try to use one side, in this case the bottom, for a ground plane as much as possible.
The board is offset to some strange value from the origin. There is no point to that.
I didn't really look at the circuit, but that single 100 nF bypass cap for all four power pins of the microcontroller is a joke. Even worse, it's not even placed by any of the power pins. And then it's right in the middle of the densest part of the board, getting in the way of other routing.
As a quick challenge, I took the board you provided, ripped up all the routing, and defined the bottom layer as a ground polygon. I then connected most ground pads directly to the ground plane with their own vias. That freed up a lot of routing complexity on the top layer.
I also moved the single lone bypass cap to the top power and ground pin pair of the micro, and connected the other three power pins to that in a star as much as possible. This is not the right way to do this, but I was just trying to get past that to see what routing of the whole board would look like.
After manually routing the ground, and the microcontroller power connections, I let the auto-router do the rest. Here is the result:
The next step would be to clean that up a little, minimize the size of islands, etc. There is certainly obvious opportunity for some cleanups.
Anyway, the point is that the board you have was incompetently designed. I didn't really look at the circuit, but the schematic is also messy. Given the messy schematic and downright irresponsibly designed board, there is little confidence in the circuit.
Find out who made this mess and avoid anything else by the same person. Run away! |
H: Why don't ICs include bypass capacitors?
I'm a newbie to electronics, so apart from the obvious physical size issues there may be a clear reason as to why this is a dumb question, but if the general rule of thumb is to use a bypass capacitor for all ICs on a board, why not just build capacitors right into the components? Is there a reason this never became a standard feature?
Sure, there's a size issue on smaller ICs (especially SMD chips and the like), but in a lot of applications vertical height doesn't seem to be an issue and it would simplify circuitry and BOMs etc.
AI: The last time I got a quote to add capacitors or resistors to a chip it was about $0.01 per part to be added plus the cost of the part. Parts like say an Intel/Altera/Xilinx FPGA, or a processor usually have decoupling capacitors built in and then also require some on the PCB as well. It's a complex question that depends on the part and application.
If you're making a $1.00 microcontroller and you've added $0.10 worth of capacitors that is going to put you at a price disadvantage at the negotiating table (despite your competitor needing $0.10 of parts on the board!). Additionally there is a constant push now for smaller and smaller packages. Adding large 0201 01005 parts is not helping. Then also adding parts lends itself to packages that have a substrate board. Lots of cheap little parts are using leadframes with no good way to solder parts to it. Some parts are now coming in CSP packaging which is essentially just the die. No place for external decoupling caps there (more on that later).
The other thing is your part may not need it, but sometimes it will. The connection between the die and the board could be many things, a bond wire to a substrate, flip chip to substrate, leadframe, etc. This path has an impedance (and inductance) that resists your die's desire to pull current through it. When you're a big power sucking chip with high frequency current demands like an FPGA or CPU you may not be able to pull the kind of current you want without significant voltage drop. Placing capacitors on your substrate and bypassing that impedance is more about robust functionality at your operating frequencies than it is about convenience for the pcb designer.
Finally chips do actually include bypass capacitance right on the die. A lot of things wouldn't work if we didn't. Now those structures are small of course and not the 1uF you can get with a discrete part. However they all work together to provide a stable voltage where it matters at the actual circuit on the die. Your on die capacitance is the first line of defense, followed by your on package, followed by your pcb board. But you can see that by the time you reach the board you've already gone through quite a bit of impedance so your 1uF 0402 may not be effective enough for that highspeed bit of logic. So then you need some die capacitance maybe, but oh maybe you can't get enough without blowing up the area (and thus the cost) so then you start thinking about putting in some on package caps. Then you start obsessing about lowering the package impedance (inductance again) so maybe you don't need quite so many on die parts...
Long story short it's a tradeoff like everything else we do. |
H: Sine Wave Generator Circuit - Bipolar
I have this sine wave generating circuit working. It is based on an application note from TI (http://www.ti.com/lit/wp/snoa839/snoa839.pdf).
we are driving an inductive sensor with a 2KHz sine wave, and right now I am putting a filter and amplifier to make the the generated signal have zero DC offset, and have the amplitude we need. I was wondering what changes to the circuit would be needed to change this circuit to a bipolar (+-5V), or is there an alternative layout that would be better for bipolar?
AI: I was wondering what changes to the circuit would be needed to change
this circuit to a bipolar (+-5V)
I'd start by powering both op-amps with bipolar supplies, something like +/- 9 volts. This gives enough supply overhead to produce a sensible output level of a 5 volt peak sine wave. The split bipolar supply also naturally gives you a centre point of 0 volts (desireable). R4 would also need to connect to the negative rail.
Next I would ensure that the output from the first stage (the relaxation oscillator) fed the 2nd stage (a 2nd order low pass filter) via a decoupling capacitor and resistor to ground. Those two components are there to remove any DC offset from the oscillator because that sort of oscillator is going to produce an offset that is generally undesireable due to asymmetries in the output limiting.
I might also consider that to give a reasonably constant output amplitude, the output from the oscillator is limited by precision voltage shunts (possibly LT1389 or SPX4040) to restrict the output to +/- 2.5 volts. This would then mean that the 2nd stage filter will need a gain of 2 to obtain +/- 5 volts peak to peak. That gain can be tweaked to set the output precisely at +/- 5 volts.
If you choose rail to rail op-amps and have a stable + and - 5 volt rails then you can probably rely on the square wave output's amplitude from the first stage. |
H: Led strip turning on dimly when touched
I have a 12V led strip connected to a (cheap) 12V 5A switching mode supply.
The supply is connected to a remote control switch.
The supply does not have earth connection (only neutral and live)
The supply have an European plug ( Live and neutral can be switched by turning the plug 180°)
Since the remote control switch only cuts one connection (I think) if I connect the plug in a certain way the live or the neutral wire still reaches the power supply even if the "return path" is blocked.
In one of the 2 cases I noticed that if I touch the led strip some of the leds near the point that I touch turn on very dimly. I have no body->earth connection except for the body capacitance.
The questions:
Is this caused by me working as an antenna or by me working as a
capacitor for some low current AC signal on the output of the power supply?
Is this safe?
Is the power supply working properly?
Is the remote control switch working properly?
AI: Is this caused by me working as an antenna or by me working as a capacitor for some low current AC signal on the output of the power supply?
Forget Antenna, indeed it is mostly capacitive coupling and leakage of your body to all the mains wiring and mains connected devices in your house.
Is this safe?
Yes, assuming a properly designed power supply, the current will be so small that it cannot harm a human. Even if you'd touch the LED strip and touch a grounded conductor with your other hand.
Is the power supply working properly?
Yes, there will always be some capacitive coupling to the mains lines through a power supply. It cannot be avoided. As long as it is not too much (meaning a harmful (to humans) current can flow) this is OK.
Is the remote control switch working properly?
Yes, switching off only one line is OK as there should be enough isolation in the powers supply to safely touch the supply's output even if it only is connected to the live wire. |
H: Toggle between two colors in a common-cathode RGB LED using a SPST switch
I'm working on a switching circuit for a guitar amplifier that uses one DPDT relay which is powered by 12V DC supply. A SPST switch (panel mount or footswitch) will power the relay and switch to a second amplifier channel.
Is it possible to wire a common-cathode RGB LED to glow one color (red) when relay is off and other color (blue) when relay is on?
The closest circuit I could find is this Alternating between two LEDS using BJTs
but it has common anodes.
Is it possible to rework the circuit to use common cathodes?
If that's possible, I could bring a positive voltage to R4 when I turn the relay on.
AI: If you switch high side you can use a P-MOSFET as shown below.
simulate this circuit – Schematic created using CircuitLab
As others have mentioned, a simpler solution is simply to mix the colours.
simulate this circuit |
H: Does the Low State in NE555 go to GND?
Here is the first schematic that I created : .
The Vcc is at 5.1V and I a self made using the LM317, Works Fine.
When I checked the Output with the Multi-meter I use., I was getting a high state of around 3.9V(Which I guess was fair enough.), but the Low was was giving an out of 2.5 ~ 2.6V, which to me seems a concern because the NE555 datasheet shows low state going to 0V in one of the .
I even tried simulating the circuit afterwards and this is what it looks like in simulation and even in the hardware set up :
.
And what am I supposed to make out of this?
So now I am getting a High state of 3.6V(seems fine), but the low state is still around 2.6V.
How do I find out the root of the Issue and how should I debug it?
AI: With that particular circuit yes the output should go close to ground.
If it is not, either
the 555 is sick or
you MUST be pulling current from somewhere else... or
perhaps the oscillator is still oscillating at some higher frequency, or,
Your 5V supply is not flat DC.
Using a scope would help a lot.
You could try lifting the output pin and see if it still does it and measure what the voltage is at the top of the LED to eliminate item 2. |
H: How would you size the transistors in this problem?
I know that whenever you have series transistors multiply the equivalent W/L of the inverter by the number of series transistors. In the parallel case W/L remains the same. I don't know how to apply those two rules to this problem. All of the examples I can find are far simpler than this and more symmetric.
How do I apply parallel and series rules to transistors?
AI: If you have already sketched out the transistor diagrams take the worst case N path (4 transistors if I am not mistaken) and size these to give you the required overall w/l. The other transistors on the N side can be smaller, you have a set of three one of which is already sized from the above. Size the other two to match the needed overall W/L. Finally you have one which acts on its own size that one accordingly.
Repeat the exercise for the P side transistors and you are done. |
H: How to reliably switch a DC analog signal that can vary from 10mV to 12V, and 1mA to 100mA
Preface: I'm a Controls Engineer, not an EE.
I currently have a system that tests resistance through a Device Under Test using voltage drop. I am using 12 Phoneix Contact PLC-RSC relays to alter the test circuit to perform various tests. I have had some periodic false failures and bizarre test values. I believe I have isolated this problem to inconsistent contact resistance in the relays. I also previously replaced one relay that was reading consistently high across the contacts (around 1 Ohm).
So to my question, is there a type of transistor/SSR/MOSFET etc that can switch a voltage this low and a voltage range this wide (10mV - 12V), and a current this low 1mA to 100mA?
I have been googling for a while but I am really not sure what terms to be searching for.
AI: You can try to find the best relays, etc. But the proper engineering way to measure resistance accurately and also detect contactor faults is to use a 4-wire (aka Kelvin) resistance measurement.
Here's a diagram from this website:
You run your test current through one set of contacts and then measure the voltage through another set of contacts. By contacts I mean separate relays, switches, and separate wire connections.
Let's say your test current is set to 100 mA and can hit a high of say up to 10 Volts, and your DUT is 1 Ohm. So you would expect 100 mV across your DUT.
If your relay is bad and adds an extra 1 Ohm, your current source voltage will go up 0.1V to maintain the exact 100 mA you set it to, so that extra resistance will not affect how much current is running through your DUT.
Let's say a bad relay connecting the voltage sense also has 1 Ohm extra resistance, well the current through the voltage sense is 0 so that extra resistance is ignored also.
Let's say your relay is super bad and cannot flow current. Then your current source will try to push 100 mA through the DUT and it will hit its upper limit of 10 Volts. We can set our 4-wire meter to give a fault indication when it cannot supply the test current we have set it to.
So basically, with a 4-wire measurement circuit, you can:
1) Ignore resistance in test probes, cabling, and switch contacts.
2) Determine when there is a gross fault in the measurement system.
3) Obtain very accurate resistance readings of your DUT.
Keep in mind you don't need a separate current source and voltage meter; there are plenty of bench meters that do this 4-wire sense.
This webpage has a very thorough explanation of 4-wire measurements.
https://www.cirris.com/learning-center/general-testing/special-topics/40-4-wire-kelvin-testing |
H: Did the cold front cause usability issues with the batteries in electric cars?
This may be more of a motor vehicle question, but since I'm asking about batteries, I think it may be more suited here.
As we know, electronics don't like the cold.
As we also know, last week was real cold.
Now, I've had my fair share of phone troubles in the cold before. For a short while, I lived in the north, and in extreme cold my phone would arbitrarily turn off if I held it out too long. I was wondering if electric cars suffered the same effect at all.
As I understand it Teslas use (in part) Li-ion batteries, like my phone does, and these are the kinds I've heard have the most problems in extreme temperatures. Assuming they follow the same principles as my phone, then driving out of a warm garage may mean your car will arbitrarily turn off on the road. I imagine that's undesirable behavior for a car.
Did this front affect electric cars at all? If not, what measures have the manufactures taken to protect their electrics against this?
Note: I'm not asking about these cars having trouble starting; that's an issue in all cars. But where gas-powered cars primarily rely on batteries to start, electric cars rely on them to keep moving. I am asking if the cold affected the batteries of already-running electric cars.
AI: Telsa Owner's Manual, page 83
"Temperature limits:
Do not expose Model S to ambient temperatures above 140F (60C) or below -22F (-30C) for more than 24 hours at a time."
It's an explicit warning from the manufacturer, who knows that the batteries and electronics will be affected in sub zero weather. So yes, they are affected.
Of course, batteries in use will experience self heating, so they will not be exposed to the same temperature as ambient weather, so should not see as much as a performance hit as inactive batteries. |
H: Capacitor charging/discharging waveform confusion
This is the circuit:
At t=0s, switch is moved to position 1 and the time constant= 1ms
At t=10ms, switch is moved to position 2, it is assumed there is no leakage current
At t=20ms, switch is moved to position 3 and the time constant is 1.5ms
The waveforms of position 1 and 3:
So I understand what's going on before 10ms but what's confusing me is after it, so if the time constant after 10ms(position 3) is 1.5ms then after five time constant where the capacitor is supposed to be fully discharged then must be at 1.5x5 = 17.5ms but on the waveform it looks like it's saying after five time constant, the capacitor is fully discharged at 22.5ms, so what's going on ?
AI: The 22.5ms label is wrong, but the rest of the graph is right. There's equal horizontal spacing between 0ms, 5ms, 10ms, and 15ms, with about half as much space between 15ms and the final +5τ' tick. This suggests that the +5τ' tick is actually at 17.5ms, which is the correct answer.
Textbooks sometimes have errata on the publisher's web site. You can check there to see if they've already noticed this error. If not, they should have a way for you to report it. |
H: Getting the Thévenin equivalent resistance for a max power problem
The given question :
I went on to get Rth by adding a voltage of 1v to control the dependent source from which I obtain the current in the branches and get the total current , as follow then later decide it by 1 since 1/I =v by ohms law to get Rth:
But in the the answer of the text book I’m using ((fundamentals of electric circuits 5th ed chapter 4 practical problem 13)) , no 1v voltage (or current ) were introduced and he solved as :
Which I found very confusing.
So the bottom line is :
When and when not are voltage sources introduced in the analysis to get Rth when there’s a dependent source ?
AI: So the bottom line is : When and when not are voltage sources introduced in the analysis to get Rth when there’s a dependent source ?
Both should work. As a summary, you can find the \$R_{TH}\$ by doing one of the following:
Option 1: If all the sources in your circuit are independent (not in this case since there is a dependent one), you just deactivate them and find the equivalent resistance of the network you are left with. By deactivating, voltage sources become shorts, and current sources become open circuits.
Option 2: You can find the short circuit current, (\$I_{sc}\$), flowing through the terminals of interest and to find \$R_{TH}\$, you compute \$R_{TH}=\dfrac{V_{TH}}{I_{sc}}\$. In this case, you don't deactivate any of the sources.
Option 3: This is what you are doing, but you are making a mistake. You add a test source across the terminals of interest, but you have to deactivate the independent sources, and leave the dependent ones untouched. So, in your method, you need to make the 9V source a short circuit (0V).
Both option 2 and 3 should give you the right result. |
H: Is it possible to power STM32 Nucleo Boards from a 3.7 Lithium Ion battery?
I have a Lithium Ion Battery that produces 3.7 volts and i would like to use it to power my STM32L476RG Nucleo board to collect data on the ADC and push the data to SD Card.
I understand that i can power the Nucleo from external 5 volts but is there a way to power it on 3.7 Volts without needing a boost converter?
AI: STM32 Nucleo boards use an LD39030 to drop the 5V power input to 3.3V. This regulator has a typical dropout voltage of 0.2V at 500mA (proportionally less at lower current), so the Li-ion battery would have to stay above 3.5V at maximum board current.
Provided you use a suitably sized battery it should work fine, though the effective battery capacity may be reduced. Most li-ion cells can produce over 3.5V for ~70% of their actual capacity at low current draw.
Example: Sanyo/Panasonic NCR18650GA 3500mAh
For battery health you should avoid using more than 80% anyway, so 70% is not bad. |
H: Impact of increased pad length in PCB
I was wondering why I cannot edit footprint of LED 1206 to take care of LED 0805 as well so that I can mount one of them depending on the availability. To do this, I have to increase the pad size of 1206 footprint on the inner side to give a clearance of around 1.2 mm between two pads. I want to know the impact of increased pad length in the PCB.
AI: If you increase the pad, you will probably increase the amount of paste too. Too much paste will increase the possibility of the component tombstoning as the solder melts. |
H: Electrical Charisteristics of PIC24FJ1024GB610
I am reading the Electrical characteristics of PIC24FJ1024GB610 from it's Datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/30010074e.pdf
(Page 419/468).
it mentions:
Maximum output current sunk by any I/O pin 25 mA
Maximum output current sourced by any I/O pin 25 mA
Maximum current sunk by all ports 200 mA
Maximum current sourced by all ports 200 mA
Does it mean that the maximum operational current sourced/sunk to/by the PIC24 is 25 mA, and the max current allowed to/from the I/O pins is 200mA
Thank you in advance
AI: It means that the maximum that can be sunk / sourced by any one pin is 25mA and that the maximum that the chip can sink / source simultaneously across all pins is 200mA. |
H: A basic question about the meaning of dB of an antenna radiation pattern
I know that dB is always a power ratio. And to obtain dB there must be a reference power or voltage measured with respect to another.
Below is an antenna pattern which shows a -3dB point for instance:
What does that mean literally? Can it be explained clearly? -3dB obtained by dividing which units? And what is relative to what? Basically I'm asking the idea of antenna pattern and the dB associations. And how is that obtained.
Edit:
Edit 2:
I marked two points A and B in X, Y, Z coordinates. A is on the plot surface B is not. Red and pink share the same XY point and different Z. Are the powers at A and B same? If not is the power pattern only valid for that plotted surface? How about the rest of the sapce?
AI: See the point at the end of the lobe - it's called the "peak output power point". The point called "-3 dB from peak" tells me that at this point, if there was an RF power density of (say) 100 watts per sq metre at the peak point then there will only be 50 watts per sq metre at the -3 dB point.
-3 dB when converted to a power ratio is \$10^{-3/10}\$ = 0.50119 (or basically a half if pin-point accuracy isn't required). |
H: Why does re-seating the battery work to fix a device?
I have a wireless mouse that is powered by standard AA batteries. Periodically I will go to use the mouse and there's no response. Every time when this happens all I need to do is open up the mouse, re-seat the battery, and then everything works fine again. I want to emphasize that this is NOT simply because I am cycling power. There is a power switch on the back as well, and turning the power off and then on does not fix the mouse.
Why would re-seating the battery make a device work again when simply cycling power does not?
AI: Sometimes the contacts of the battery oxidize and/or corrode slightly, sometimes just enough to cause an intermittent or no connection to the battery contacts. Re-seating the battery (or sometimes even just spinning the batteries in the holder) can scrape off this oxidization and make the electrical connection again. |
H: Embedded system task scheduling for data aquisition on a CAN network
I'm struggling with the concept of how to schedule my tasks.
My Setup:
STM32F103 hooked up on CAN. Taking measurements with a Lidar V3 module comms via I2C, then distributing that measurement on the CAN
Interrupt 1 is a 1ms timer interrupt to initiate message send on CAN
interrupt 2 is active upon receiving CAN message
I also have to poll a register via I2C on the LIDAR unit to ensure that measurement has finished before I can then use I2C to read the distance register, code snippet shown below
status = CheckLidarStatus();
while ((status & LIDAR_BUSY) == LIDAR_BUSY)
{
status = CheckLidarStatus();
}
What I believe is the correct flow that my program should take is shown below:
My main concerns are:
Does the flow seem a logical way in which to approach this?
If I prioritise the timer interrupt (rather than RX int) for CAN transmission, will this affect the CAN network negatively i.e. not dealing with the received CAN messages promptly enough?
If either of the interrupts are active during I2C comms, will it cause the I2C comms to "fall over"?
Is it acceptable to sit in a while loop waiting for the Checklidar status to come back as not busy, or is there a better way to do this?
AI: Yes, it seems logical to me. Although, what's the maximum amount of time that the lidar peripheral could be busy? If that is more than 1 millisecond then you could miss a transmit opportunity. Maybe the busy case should just skip over the data read rather than looping back to poll the status.
Yes, the lower priority interrupt handler will be held off while the higher priority interrupt handler runs. If the higher priority timer interrupt handler runs longer than it takes for the CAN peripheral to receive enough messages to overflow then you would lose messages. That's why it's a good rule of thumb to keep interrupt handlers short. And if all your timer interrupt does is set a flag then I doubt whether you're going to have a problem.
Another way to consider this is what is the penalty when either interrupt handler is delayed by the other. When the CAN interrupt is delayed by the timer interrupt then you would add lag to CAN response or worst case drop a message. When the timer interrupt is delayed by the CAN interrupt then you would add jitter to the timer interrupt. Worst case would be dropping a millisecond but the CAN interrupt would have to run for more than a millisecond for that to happen. So what is less desirable for your application, a little lag or a little jitter?
It's doubtful that either interrupt would break I2C communications. You're probably using an I2C controller peripheral that transmits/receives bits mostly independently from the CPU. The I2C controller will continue to clock in and out bits as necessary without affect from the interrupts. (If you were bit-banging each bit then there would be more of an impact because individual clocks could get stretched out by an unrelated interrupt. But even that is not necessarily a problem because of the synchronous nature of I2C. The slave device shouldn't care if the I2C clock pulses get stretched out.)
It may be acceptable to poll the lidar status. If you don't have anything else for the CPU to do then what's the harm? But if the lidar peripheral has a "data ready" interrupt of some sort then you could enable that interrupt and wait for the interrupt rather then poll for status. |
H: Depletion MOSFET inverter
I know that if both transistors in a CMOS inverter are enhancement then the output will be as shown in the figure:
But I wonder, what if one of them is enhancement and the other is depletion?
AI: If one transistor is of the depletion type, then that transistor will never switch off. That transistor is then effectively a variable resistor.
In the case that the NMOS is a depletion type and the PMOS is an enhancement type mosfet, the output voltage can still easily reach 0V at an input of VDD. The PMOS is still able to completely shut off current, leaving just a conductance to ground.
Reaching VDD with the output at an input of 0V however will not be possible anymore. You get into a situation where the NMOS and the PMOS will "fight" over the output voltage using their currents. If the NMOS is conducting more than the PMOS then the NMOS will "win" and be able to pull the output downwards. If the PMOS has a very high transconductance, then it will "win" and the output will be pulled more upwards. |
H: Uart for Atmega32
Can manchester encoding be implemented using UART?
If not what kind of modulation can I use, using UART on the Atmega32. I am making a Visible Light Comm system. If I use the UART as normal I get flickering of the LED, because there are long strings of zero's and one's. I want to use UART because Im finding it hard to design my own communication protocol. But I need to find a way to modulate my data using UART.
AI: If I use the UART as normal I get flickering of the LED
If data rate isn't an issue and you're just trying to deal with visible flickering, you could consider sending two bytes instead of one.
That is, instead of
transmitbyte(x)
Do
transmitbyte(lo(x));
transmitbyte(hi(x));
Where lo(x) interleaves the bottom 4 bits with their inverses, like Manchester. So bits hgfedcba => DdCcBbAa, where A is inverse of bit a; hi(x) takes hgfedcba => HhGgFfEe. Thus you'll get a transition every bit time. If the receiver feels like it, it could check the consistency of each byte.
If you don't have any other way to stay in sync, send lo(x)&0x7f and hi(x)|0x80.
You'll see that if you transmit back-to-back at 8N1, taking account of the start and stop bits, you'll have the same number of 1s and 0s in the output, one of the main benefits of Manchester encoding. Additionally you have a guaranteed transition within two bits.
0DdCcBbAa10HhGgFfEe1
Or if you use the high bit to say which nibble this is, then you still have equal 1s and 0s, and a transition guaranteed within three bits.
00dCcBbAa101hGgFfEe1 |
H: How to introduce delay to a signal
I need to introduce a delay to the output of an astable, it needs to be in the order of 10 micro seconds.
I have read that optical cable is good for delays, which makes sense for small delays, but I have no access to optical cable for the project I am working on. The ideal solution would be some components / IC's. I am working with a square wave, so the signal can be assumed to be digital
AI: simulate this circuit – Schematic created using CircuitLab
There is a tolerance on Vt+ and Vt- that shifts withtemperature that will make the delays asymmetric.
Also if the waveform is not repetitive, it will take 20% longer for the 1st edge.
This is my approach if the delay tolerance is adequate.
Since the Schmitt trigger thresholds are 1/3 to 2/3 each delay is 2/3 of V+ which is very close to linear approximation of the RC exponential decay. |
H: Connecting a supply voltage from linear encoder to camera IO board with a current limiter
I have a TTL output from an incremental linear encoder which also supplies a 5V output at 140 mA. I would like to use this 5V output voltage to power a camera IO board with RS422 Interface which has a specification of 5V/50mA.
How do I reduce the current from 140mA to 50mA. Can I just use a 150 Ohm resistor or have you got any suggestions ?
simulate this circuit – Schematic created using CircuitLab
Please find the camera IO board specifications below :
Pin......Level.............Description..........Default
1........RS422.............GPIO_P0(input).......Incremental encoder(high)
2........RS422.............GPIO_P1(input).......Lightbarrier(high)
3........LVCMOS............GPIO_P4..............Can be used for lightbarriers
4........LVCMOS............GPIO_P2..............Reserved
5........3.3Vover100Ohm....Power................Output
6........LVCMOS............GPIO_P3..............Master/Slave-interface
7........0V................Ground...............-
8........LVCMOS............GPIO_N4..............Master/Slave-interface
9........RS422.............GPIO_N0(input).......Incremental encoder(low)
10.......RS422.............GPIO_N1(input).......Lightbarrier(low)
11.......0V................Ground...............-
12.......LVCMOS............GPIO_N2..............Reserved
13.......0V................Ground...............-
14.......LVCMOS............GPIO_N3..............Reserved
15.......5Vover100Ohm......Powersupply..........Output
AI: If the camera needs 5 volts and takes up to 50 mA then supply it with 5 volts and even if the supply is capable of proviging 140 mA (or more) it doesn't matter because the camera will take only the current it needs to operate. I expect that the 140 mA figure is a maximum rating for the device i.e. it is capable of supplying 5 volts to a load than can take up to 140 mA.
Regards your comment, this contradicts what your main question body appears to say so please provide a link to the camera interface card data sheet so this contradiction can be resolved. |
H: How do I calculate period of synchronous counter?
So how do I calculate maximum frequency if this values are given:
\$T_{Hold-ff}=0.2ns\$,
\$T_{Delay-ff}=2ns\$,
\$T_{Delay-nor}=0.3ns\$,\$T_{Delay-nand}=0.4ns\$,\$T_{Setup-ff}=0.5ns\$.
I thought about: \$T_{Delay-ff}=2ns\$+\$T_{Delay-nor}=0.3ns\$+\$T_{Setup-ff}=0.5ns\$
Is that good?
Also how could I calculate Response time (time from the clock edge on the clock until output A, B, C)?
AI: The data launched by the third flip-flop has to be captured by the first flip-flop in the next clock cycle for correct functionality. The path is Q out-> NOR -> AND -> J in . Also it is the critical path here. So the maximum frequency of operation would have to satisfy:
$$T_{Delay-FF}+T_{Delay-Nor}+T_{Delay-Nand}+T_{Setup-FF} < T_{clk}$$ |
H: How do I implement a communications interface to an Altera FPGA?
I have a DE1-SoC with some data coming in through an A-D Card.
After digital processing I want to transmit data to a host PC for records.
I'm trying to figure out the easiest way to go about this. I've never used the HSP side of this hardware before, so am treading carefully.
I think the following options are available, but I may be ignorant of more.
USB Blaster
Perhaps using the Nios ii processor to communicate across USB-Blaster. I am not sure how to save data sets through the nios interface though.
Similar transmission to Signal-Tap?
Using the HPS module (Linux) transmit data over the Ethernet module. Setting up a receiver in python would be quite accessible?
How do I implement a communications interface to an Altera FPGA?
AI: It depends on how much bandwidth you need, because you will need to write software on the other side to collect your data. You will probably also want to minimize the IP or HDL code you have to write on the FPGA side.
The easiest thing would be to use a uart to USB as most software has compatibility for serial ports but you are limited on bandwidth. On the FPGA side there is an RS232 UART core under the university program.
USB is going to be more complicated as you will need to write a driver on the PC side and on the FPGA side you will need to have a USB core. Both of which have a significant time investment to implement.
You can also use the USB blaster to send information over JTAG into a quartus debug terminal, and I believe that you can also use the uart over this interface, but if you already have an RS232 to usb on the board, that would be easier to use.
I don't need the bandwidth so I implement an RS232 port on the boards I use, if I need more bandwidth, I use a quad spi interface to usb by FTDI. |
H: How to solve this. Multiple op amps circuits in series
The question is. What value for R1 is correct if we want the total power amplification to become 30 dB
My calculations. 30dB is amplification of 1000 times.
Last circuit got amp of 15/1,5=10 times. 1000/10=100
We therefor need amp of first circuit to be 100 times.
10/R1=100
R1=0.1kohm
We could tick in 100 ohm but according to solutions manual the correct answer is 3.2kohm and I do not understand why.
AI: 30 dB amplification as a voltage ratio is \$10^{30/20}\$ = 31.62.
Given that the 2nd stage has a gain of 10 the first stage has a gain of 3.16 hence, R1 approximately equals 3.162 kohm.
30dB is amplification of 1000 times
30 dB is a power ratio of 1000 and a voltage ratio of \$\sqrt{1000}\$ |
H: Gradually ramping voltage on button press
I have a circuit with a button and a motor. How would I make the motor gradually ramp up speed over 1-3 seconds when the button is pressed and gradually slow down over 0.5-1 seconds when the button is released, instead of the motor going full speed immediately? The circuit may be either 12V or -12V depending on the desired turning direction.
This is a simplified version of an old electric desk control circuit. The desk moves too suddenly when the button is pressed and I need to slow it down.
As a programmer, my go-to solution for stuff like this is often a microcontroller, but I'd like to try using analog components if possible.
Even though I've had education in electronics back in the day, I don't know if there is a name for what I'm trying to do and how to search for more information about it. I'm stuck googling with too broad keywords. If the analog solution isn't too much more complex than a microcontroller one, please point me to the right direction.
AI: Generically you may be able to do this by controlling a DC motor with PWM using and ramping the duty cycle from 0% to 100% over some time, and that will probably solve your problem.
The details are heavily dependent on the type and size (current/voltage) of motor- it may not be practical if the motor is of certain AC types for example.
I have retrofitted something that this and it worked well in the application (it happened to be gently lifting many millions of dollars worth of equipment rather than a desk top).
I used a cheap little microcontroller (PIC18F14K22) with a few lines of assembly code (less than 200 including comments and blank lines) to generate the timed 7.8kHz PWM signal to drive several large MOSFETs. A hardware overcurrent cutoff was included (probably why I picked that particular chip). I was able to leave all the original safety and other interlocks in place, just interrupting what was already present. |
H: 2 x 8-channel multiplexers with with linked outputs
I have only one input to measure 16 channels, my intention is to use this circuit below based on the LTC1380 MULTIPLEXER:
The multiplexers have different addresses (AO A1). The output of both is linked to the same output buffer. Therein lies my confusion how to deal with both outputs connected together
My questions is
Will I have to close top multiplexer off, while I take a reading from bottom multiplexer and vice versa. (I would assume that this is the case, which leads to the next question...
What would happen if I have both S0 lines open on each multiplexer
AI: You are correct in your statement about having to toggle between the two multiplexers to take a proper reading of any single input. You do this by setting or resetting the Enable bit which is included in the SMBus-delivered configuration word ( Page 8 of the Linear Tech data sheet). You must select one or the other of the two multiplexers. So, there are a few precautions.
A. You must avoid enabling both multiplexers at the same time as this will effectively connect two of your inputs together. Since these inputs are sourced by some entitiy, you would effectively be shorting these two sources together. Maybe OK, maybe not, depending on their source impedances and electrical composition. So, best to avoid this situation entirely.
B. When switching between two inputs on opposite multiplexers, always go to the "both off" state first, then select the appropriate multiplexer in a subsequent SMB transaction. (See "C" below, as this is a transient floating condition.) This is essentially a "break-before-make" strategy. Not to worry when you are switching between inputs on a single multiplexer because the LTC1380 has "Guaranteed Break-Before-Make" (Page 1 of data sheet).
C. If you disable both 1380's simultaneously, the NI input of your unity-gain buffer will be left floating - maybe OK, maybe not, depends on a number of factors. Unless you leave both MUX's disabled for an extended period of time ( say more than 100 milli-secs ), I wouldn't worry about it. You could connect a high value resistor ( 1 meg or greater) from the NI input to DC Common to eliminate this floating situation, but that could create accuracy issues, depending on the source impedances of the input signals and a few other factors. As a practical precaution you should probably assign one of the inputs as a "parking" position. Always select this input when you are not actively utilizing any of the other inputs. |
H: Replacements for mica capacitors?
I realize that there is along history to mica capacitors; however, I've been unable to determine if there any modern equivalents that have the same static electronic characteristics. The short list of types that seem like they'd have similar behavior and properties over time are silicon capacitors, ceramic capacitors, film capacitors; however, I've not found a rigorous comparison anywhere.
I'm trying to redo an old amplifier with modern parts as the original parts are no longer available.
AI: Don't worry about the internal makeup of the capacitor. Instead, figure out what you really need the capacitor to do. Once you have such a spec, then just look around for a cap that meets them. If you've specified it properly, then you won't really care if the dielectric is mylar, polypropylene, mica, or something else.
The two most important specs are the capacitance and the voltage. Those alone will push you towards certain technologies.
Since you mentioned audio, you need to get more specific for anything in the signal path. Many types of ceramic have some piezo effect, so aren't good for audio. Vibrations and mechanical shock on the device can end up in the signal. High-capacitance ceramics are also non-linear.
If you only need up to 10 nF or so, but have to stand off high voltage (like in old tube amplifiers), then mylar or even old paper types would work fine.
If this is just to filter out noise, like across a power supply, then the cheaper and smaller ceramics might be fine.
In short, this process starts with good specs. Without them, you're just poking around in the dark. |
H: Transient analysis with Laplace and nodal analysis error
Have the schematic:
Solving using MathCAD:
There is an error in my equations with nodal analysis but I can't find where? May anyone help me?
I also add the solution using approach of series RLC circuit:
But it seems to be A1 and A2 constant sign is incorrect comparing my result with that in textbook.
I also tried to solve with Laplace but using Mesh Current Method, my equations are (I1 - left mesh current, I2 - right):
But same thing - I can't get properly result, may be something wrong but I can't understand what!
AI: Thevenin Equiv circuit for v1 goes from 60V to 40% or 24V with Rs=30//20=12 ohms. The steady state v(t) across cap is then +24-30= -6Vdc
Then we know resonance ω= √(L/C)= v(0.5) = 0.707 and Q=XL/R = 2 π 0.5/12 which is <1 and thus overdamped and the initial voltage across cap will be 0V.
Does this method make it easier than Laplace? |
H: Which particular transistor types represent triode and pentode vacuum tubes best?
If you encounter an old text which uses tubes instead of transistors, and if you are not familiar with the tubes, which one of the transistor from the following transistor tree would you think of to understand the circuit?
I sometimes encounter an ancient text but when I see tubes in the diagram I used to skip reading. Should I instead think of it as an NPN transistor or a particular type of MOSFET? Which particular transistor in the above tree makes most sense for a tube circuit?
AI: None of the above. They are voltage-controlled, like FETs, but their characteristics are not so similar. Perhaps JFETs are closest, since a more negative voltage on the grid turns them 'off'.
You should just look at the I-V curves of vacuum tubes for a basic understanding.
Consider that if the anode current is fixed at 1.5mA and the grid voltage goes from -1V to -2V, the anode voltage goes from 160V to 260V - a gain of -100! |
H: Flatness vs Frequency parameter in RF zero bias detectors
I require the measurement of RF power from a port, and I am considering using a zero-bias RF detector in order the measure the power being delivered through the port.
These devices give a voltage output which is roughly linear to the logarithm of the power being received at the port, ie., power in dBm.
All these detectors have a parameter known as Flatness vs. Frequency, and they mention the values in dB. I think that this may be referring to the amount of change of the output voltage as the RF frequency of the input power is changed, but I am unable to figure out how it works quantitatively, and whether the deviation is sufficient for my application.
For example, one of the detectors which I am considering shows a flatness vs. Frequency of (+/-)0.5 dB max. What does this mean, and how can I make sense of these numbers?
AI: When a Schottky diode is used as an RF peak detector to measure mV/mW or RF power with some high impedance like 100k on the diode detected over a 50 Ohm load.
Sensitivity is usually rated in mV/mW of RF power over a frequency range such as 10MHz to 4GHz.
Since Power is 10 log (Pd/Pr) where Pr reference 1mW = 0dBm
and -10dBm = 0.1mW
and +10dBm = 10 mW
Tolerance 0.5 dB for power = ten to the power of 0.5dB/10
10^0.05=1.12 thus +12% voltage out
10^-0.05=0.89 thus -11% voltage out |
H: Fan PWM driver - design question
I've been working on crating a simple PWM fan driver for my Raspberry Pi. To simply explain idea - I get 3 pin input (1 - PWM, 2 - 5V, 3 - GND), then using RC filter I turn PWM signal into voltage and feed it into positive side of OpAmp. Then output drives MOSFET which in turn works essentially as variable resistor controling fan speed (M1 motor on schematic).
My (newbie) questions are:
PWM signal is 3.3V, is there a way to make OpAmp output do full 0-5V without adding additional OpAmp to scale it up?
How should I protect circuit from effects that fan might have? It's an inductive load after all.
And probably most important - am I missing something obvious to people who know what they are doing?
On the side note, speciafic OpAmp and MOSFET I will choose later, but I was thinking about rail to rail opamp that works in 0-5V range and for MOSFET I will use some TTL level one.
Also, C1 is planned to be 1uF
AI: I'm confused why you would want to convert your PWM signal into a very inefficient linear driver. PWM divers are used to efficiently modulate the power directly to the motor with minimal losses in the switch gear.
The following circuit would be typical..
simulate this circuit – Schematic created using CircuitLab
PWM motor drivers of this type do the integration you performed with R1 and C1 using the inductance and inertia of the motor itself.
If you need tighter speed control you can, with appropriate timing, you can feed back the voltage at the top of the MOSFET, suitable scaled, to the micro and have the latter measure the back-EMF and hence the motor speed.
EDIT:
Switching a BDLC fan at high frequencies can however be problematic, and as you have indicated, and can be noisier that a linear drive.
In that case the principal of your circuit is ok as long a the time constants of the integrator is sufficient.
However: The way you have the MOSFET connected means you can never drive the fan with anything greater than Vcc - Vth (The threshold voltage of the MOSFET.)
As such it would be more appropriate to invert the amplifier and use a P-MOSFET instead. Something like the schematic below.
Notice I also changed the feedback on the op-amp to change it from a voltage follower into to a positive gain amplifier to convert your 3.3V signal to a full 5V signal.
BE AWARE: The OP-AMP needs to be rail-to-rail on inputs and outputs.
simulate this circuit |
H: Replacement of Tantalum Capacitor
We are using some tantalum capacitors for some products. for two purpose:
Bulk Capacitor
Low ESR for MCU power
Recently, we are suffering to get tantalum capacitors. Our supplier is saying that Chinese electric vehicle companies are using huge amount of these. So it makes the shortage of tantalum capacitors
So we need to replace the tantalum capacitors with another type of capacitors.
I think that the characteristics of the replace capacitors for Bulk is not important. So we have only to meet the its capacity, voltage and dimension.
Which types of capacitors will meet for the replacement of bulk tantalum capacitor?
Which types of capacitors will meet for the replacement of low ESR tantalum capacitors?
FYI, I can't change my PCB so the the 2D dimension should be same. (We are using A type and D type tantalum capacitors)
AI: About the only possible form fit and function equivalent maybe possible are 1206 ceramics for D size.
Cost, Values and pad / stencil size will need review.
https://www.johansondielectrics.com/downloads/JDI-Tanceram.pdf |
H: Does changing wire gauge change output of a thermocouple?
So I've been experimenting creating thermocouples with copper and constantan wire, just by twisting them together at one end and heating the junction with a candle and using a voltmeter to measure the emf at the other end. I thought that changing the gauge of the copper wire might change the emf output, and it appears that the smaller the diameter of the wire the larger the voltage is, but I'm not sure why this is. From research, it looks like the thermoelectric efficiency is determined by the Seebeck coefficient, the thermal conductivity, and the electrical conductivity, as well as the temperature difference.
Since the conductivities are intrinsic properties of the copper and I'm keeping the temperature constant, I'm not sure why the output of the thermocouple is changing. I thought that I might be changing the conductivity in some way by changing the gauge, but is this possible?
AI: Thicker wires mean you are heating the 'cold' end more (and, as in the comment) drawing more heat from the hot end. To a rough approximation the no-load voltage is proportional to the temperature difference between the ends.
A long thick wire (long enough the cold end does not heat appreciably) should not be any different from a long thin wire pair if the alloys are similar and negligible current is drawn.
Think of a heat engine, if that makes sense, when you start drawing current the resistance figures into it as well as the heat flow down the wires.
To get a good reading you have to have both ends at controlled temperatures. For a rough measurement (maybe within 2-3 degrees C) you can put one end (the junction) in boiling water and the other (transition junction(s) to copper on both sides) into an ice-water slurry. |
H: Burned ST LINK by connecting it to the board
I have a PCB that is getting powered from mains and is connected to a Hi Link component (HLK-5M05 with 5V output). At the moment it is connected to an extensions with a button, a little bit like this one. When I power it on and start measuring I get the 5V output, 3v3 output, I can see that some components are working accordingly (voltage monitor) and then I went to load my firmware into the st microcontroller.
I disconnected eveything since I don't want to accidentally get shocked, I connect all the pins (gnd to gnd, 3v3 to Vapp, TMS -> TMS, etc). After I connected this I connected the board to the extension and turned on the button. Immediately I heard a loud noise and I noticed the st link wasn't ON anymore (a capacitor exploded) and the circuit breaker activated. Then I went to measure the board and I notice that there is a3v3 short to ground.
I have revised my entire layout and there is no connection between mains and GND in my circuit. The closest to it is the analog circuitry for measuring the voltage, but still, they are not connected. From what I can see everything is connected as it should be according to datasheets, but it still didn't work.
After that I tried connecting and programming my board via the bootloader. I did the required connections and tested my board and everything was working properly. Again I disconnected everything and connected the USB-serial board to my board (GND, TX and RX ... very simple and straight forward). When I connected everything the circuit breaker still activated but fortunately this time it didn't destroy my PCB.
Very distraught I turned off the button and went to disconnect the USB-serial board and got shocked. After that I measured the voltage between the USB connector and my PCB ground and there was 220Vac ... when the extension was turned off and the extension is not grounded (not USA .. incompatibility between different types of plugs ... old everything), but there is 0V when I measure the voltage between them when the extension is powered on.
What could I be doing wrong? I measured other devices (USB chargers and similar) and they all had the same behaviour ... 0V when ON and 220V when OFF. I have compared my schematic to others, such as open energy monitor and many other projects you can find online and I'm not doing anything crazy here (in terms of schematics and connections). Could there be something wrong with my installation? Or is it a PEBKAC (more like between PCB and chair [PEBPAC])?
EDIT:
Adding schematics, just the important part, the rest is all decoupling capacitors, oscillators, etc.
AI: The accidental mains-earth short. Don't we all make those one day.
You switched extension cord probably only switches one line.
That way you do not know whether it switched Line of Neutral unless you explicitly measure it relative to mains earth.
I'd recommend getting an isolator switch, an appropriate contactor, or just unplug.
Relays don't have enough distance and might get stuck on faults.
Your circuit does have a path from mains to earth when you connect the programmer. But we don't know the impedance of this connection.
Inside your PC the USB GND is connected to mains earth, and that's what has blown your ST Link.
The slightest current this way may upset power supplies. Or blow inputs if you do not connect ground first. Which is why typical connectors always connect ground first. eg: USB, HDMI, VGA, DVI, SATA, PCI. Except audio, which you've probably noticed one day will create a loud humm when not inserted correctly yet.
I'd recommend getting an ST-LINK/V2-ISOL if you plan to work with circuit like this further. But beware, your oscilloscope has the same problem! You can use a differential probe with your scope.
Or buy an isolation transformer, that would remove the sparks on a fault. But can still result in strange behavior and shock hazards with a fault.
In the future, be aware of what potentials you connect.
In a comment you state that resistors r4, r5 and r6 are 200k and r7, r8, r9 are 820 Ohm. This means there was a short trough r7,r8 and r9 to earth.
I'd recommend making these two resistor strings identical:
simulate this circuit – Schematic created using CircuitLab
But you will have to take common mode noise into account. |
H: Which diff eq is used in electronic engineering?
Its a projectthat our teacher gave us . To find which diff eq is used in this field .please help me.
(By diff eq i mean the diff eq like legendre or riccati that are famous and known by a special name )
AI: Assuming your only components are
resistors (V-I-relationship: \$v=Ri\$),
capacitors (V-I-relationship: \$v=\frac{1}{C}\int{i})dt\$ and
inductors (V-I-relationship: \$v=-L\frac{di}{dt}\$) and of course
voltage and/or current sources (\$v(t)\$, \$i(t)\$)
your circuit (i.e. all currents and voltages vs. time) can be described by a
system of max. 2nd order linear ordinary diffential equations with constant coefficients.
If you allow also active components (e.g. OpAmps) you can build an analog computer for any ordinary differential equation you can imagine. |
H: Latching relay not working
I'm pretty new to electronics. I've however recently used mechanical and solid state relays successfully. Now, I am just started trying to use latching relays. I am currently trying to create a set up whereby my raspberry pi would trigger the latching relay to both set and reset positions, thereby switching the main circuit on and off. However, I am encountering some problems as the relay does not seem to latch when the appropriate current is applied to set and reset coils. The schematic of my relay is:
The datasheet can be found here: http://docs-asia.electrocomponents.com/webdocs/1398/0900766b8139805d.pdf
Pins 1 and 6 will be connected to GPIO pins of my raspberry pi, while the main circuit that will be switched on and off will be connected across pin 10 and 3. Since I read that the operate voltage of a latching relay is 3.75V (based on nominal voltage of 5V), I used an adjustable voltage regulator to convert my 9V power supply to around 3.75V. I applied this 3.75V voltage to pins 1 and 6, one at a time, and the GND of pins 12 and 7 to the emitter pin of my transistor which drains to my raspberry pi GND. I also applied 9V across pins 10 and 3, where pin 3 leads to GND of the circuit. When I ran my looping raspberry pi script to cease the voltage across pins 12 and 1, I verified with my multimeter that the voltage dropped to zero from around 3.75V before rising back up again after a few seconds. I expected that current will pass from pin 10 to pin 3. However, the latching relay did not work and I confirmed with my multimeter that no current passed from pin 10 to 3 when set voltage is applied, and I did not hear any expected clicking noise during operation. I then activated the reset coil instead and find that there is still no current passing from pin 10 to 3, or any latching sounds produced. Could any advise me on this issue?
I've also drew a schematic as well. The schematic for the relay is not the exact one I used, since there are limited options on the circuit lab sketch, but this diagram should otherwise be about the same as my current set up with one GPIO pin used.
simulate this circuit – Schematic created using CircuitLab
AI: Just to be sure we're on the same page, relay coils are between pins 1-12 and 6-7, not between 3-10. Also note that Q2 has some voltage drop even when turned on, so if you set the PSU to the latching voltage, the relay will see a smaller voltage and may not activate. Set the PSU to "rated" voltage, i.e. 5V. You could even leave it at 9V, since the relay is guaranteed to withstand up to 10.9V, though that's getting pretty close to the limit which is OK for a prototype but not advised for long-term usage. |
H: Can i connect something else to programming pins in STM32 (SWD)?
As in the topic: Can i connect something else to programming pins in STM32 (SWD)?
For example a single LED with current limiting resistor connected to SWDIO and SWCLK pins. Will this load affect programming via this interface (SWD)? Should I use a buffer?
AI: Yes, you can use STM32 SWD pins as GPIO, and yes, you need to think about the impact of doing so on the SWD functionality.
Likely you want anything else driven by those lines to be behind a buffer with a high impedance input, and you want anything that could drive those lines to be behind a specific enable.
But there's also a risk in re-purposing those lines, especially as GPIO output. If you do so, you will not be able to connect an SWD probe to the running system.
With a full capability SWD adapter, you should be able to perform a coordinated "connect under reset" where the CPU core is reset and the SWD connection is used to suspend operation before the program can re-purpose the pins and disable SWD. However, this can be difficult with some setups.
So generally, if you are going to re-purpose the pins, it's best for a program to provide a second or two of delay upon reset before doing so.
You probably also want to make doing so at all dependent on a macro definition, perhaps one passed on the compiler command line. That way, if you decide you want to use a breakpoint debugger, you can build the code with alternate settings that do not re-purpose the SWD pins (maybe something like arm-non-eabi-gcc -DNO_REPURPOSE_SWD), and so leave them operating in SWD mode to permit the debugger to function.
And of course whatever you connect to those pins needs to not problematically mis-operate if it sees SWD traffic rather than the intended signals. So things like motor drives are a very bad idea; but status LEDs, or serial advisory message outputs might be okay. |
H: Size of a non-plated throughole (NPTH) for a spacer
I am designing a PCB. For spacer, I would like to use this part:
http://www.keyelco.com/product-pdf.cfm?p=4805
The diameter of this spacer is 0.25 inches.
What should be the size of hole on the PCB? should I use the same dia 0.25 inches for the NPTH holes?
AI: The inside diameter of the spacer is 0.144 inch. I would make the hole in the board 0.144 inch as well - or big enough to pass the fastener you will be using.
The outside diameter of the spacer is 0.25 inch - if you make the hole in the board that size, the spacer will fall through the board. |
H: Calculate electromagnetic torque of synchronous motor?
I usually use this formula $$P=Tω=Τ\frac{2π}{60}n$$
where n is revolutions per minute and P is the power depending on the occasion.
Since we have to deal with a synchronous motor we have to use the synchronous speed Ns. My big problem is what power should I use. I have everything, power input, power output, all the losses. How should I replace P to find the 'electromagnetic' torque.
AI: The electromagnetic torque is the torque applied to the rotor through the interaction of electromagnetic fields. The power used to calculate it is the mechanical output power plus the mechanical losses. The mechanical losses are bearing friction and aerodynamic drag also known as windage. It is also the input power minus the electrical losses in the stator consisting of copper losses and iron losses. This assumes that the excitation power is considered separately from the input power. |
H: Sensitive photosensor
I'm looking for an extremely sensitive photosensor. I have a setup where a beam of light of some sort (weak laser, or something else) will be shining into the photosensor. Every now and then, a molecule with a diameter of about 1.0 - 1.3 nanometers will pass between the light source and the photosensor, and the photosensor must be able to detect the difference. Does such a photosensor exist, and if so, where could I get one? (The cheaper, the better.)
AI: No, that doesn't exist. Visible light has a wavelength much larger than your particles, so the waves will go right around them unimpeded |
H: Current source driving capacitor in LTspice
A circuit is given (see the figure).
simulate this circuit – Schematic created using CircuitLab
where
$$I= \left\{\begin{matrix}
0, & t < 0\\
I_0 sin(\omega t), & t \geqslant 0
\end{matrix}\right.
$$
and the capacitor stores no energy at \$t = 0\$
So, the capacitor voltage can be calculated as
$$V(t) = \frac{1}{C}\int_{\infty}^{t}I(x)dx = -\left. \frac{I_0}{\omega C}cos(\omega t)\right|_0^t$$
This, in particular, gives a DC offset equal to \$\frac{I_0}{\omega C}\$.
Let's the parameters values be: \$I_0 = 1A, C = 1\mu F\$ and \$\omega = 1kHz\$. Then the DC offset should be equal to \$1kV\$. But using LTspice I had just about \$150V\$.
Moreover, this offset goes down with time to the value of \$0\$ (looks like capasitor discharge curve in response to a voltage step in an RC circuit).
Does it mean that LTspice models the components imperfections (internal resistances, for example)? Or my calculations are wrong? If the former is true, how to model ideal behavior?
Thanks
AI: I'm posting the answer since it is instructive to see what can happen with the default timestep when the simulation spans too big an interval.
This is the circuit in LTSpice.
A minimum time step of 50us is more than adequate to give a stable solution on 200 ms interval:
But take it to 60us with .tran 0 200m 0 60u startup and you will see the solution drifting toward the time axis:
With 100us timestep we get shape similar - but only similar - to an exponential decay of the mean value |
H: Compute loss/inch for (differential) T-line from s-parameters?
I have the 4-port s-parameters of 2 PCB boards, where each board consists of a differential transmission-line with SMA connectors on either end.
The only difference between the boards is their trace length is different.
Can I accurately compute the insertion loss of the PCB trace in dB/inch? If so, how?
AI: S11 is input return loss. S22 is output return loss (output driven and reflected energy measured). S21 is forward gain, input driven and output power measured. S12 is reverse gain, output driven and input power measured.
You have various measurements, including S21 for 2 different lengths, for various frequencies. Did you normalize the S-param measurements, before measuring the PCBs? Normalization allows de-embedding the item-under-test from the cables and SMA connectors. If you did "normalize", can you tell the difference?
Suppose at 1GHz, for 1 meter the S21 is -0.5dB, and for 2 meters the S21 is -1.2dB. Does this mean that PCB, at 1GHz, has 0.7dB loss per meter? I think so.
[EDIT Read Mike's discussion below, in the comment. ] |
H: USB plug in detection for charging port
Is there a way to detect if there is a USB cable physically inserted into a USB receptacle, even if it is just a cable (with nothing attached to it).
I am designing a USB charging port (short D+ and D- together styles) and would like to be able to disable the buck converter if there is nothing plugged into the USB receptacle (which will be >99% of the time).
I can't rely on the devices that will be drawing power from the receptacle to have any specific protocol in terms of negotiating charging current etc (i.e. can't use serially transmitted data from device X as a detection mechanism).
I think what I'm asking for is if there are USB-A receptacles with mechanical plug-in detection (along the lines of what is available for SIM cards and SD cards), or if there is a way of "sensing" a plug-in event transient (less inclined to go this route as it sounds pricey).
What say you?
_
_
EDIT:
Found a receptacle with a "contact sense pin" feature that was referenced in another post:
Special USB Port With "Sensor" Contact
AI: Yes, special USB receptacles have been defined within Power Delivery specifications. In version 2.0 an extra special contact was defined, for both USB 2.0 and USB 3.0/3.1 Type-A connectors. They were called "PD Standard A Connector", and there some protocol is defined as well.
In Power Delivery Rev 3.0 all Type-A and Type-B connectors are "depreciated", and the focus now is on Type-C connector.
Going forward, it might be challenging to find the original "PD Standard A Connector" with extra insertion detect contact. Wurth Electronics makes one for USB3, and Assmann, both are still available at Digi-Key. |
H: Which STM32 is best for logging a CAN network?
I would like to build a project based on STM32 that interfaces with a CAN network. The CAN network has a 250 kbit/s baud rate.
On this network I have to:
Log messages from 127 nodes with IDs between 0x381 and 0x3FF (each node transmits one message per second).
Transmit messages to nodes with ID between 0x581 and 0x5FF.
Receive responses to these messages that will have IDs between 0x601 and 0x67F.
I was thinking of using an STM32 with two CAN channels. My intention is to set up two different filters on IDs and limit interruptions. Is that a good choice? Can it be done with only one CAN?
I have doubts about the kind and the speed of processor to use. Can an STM32F1 be sufficient? Or do I need an F4?
AI: The shortest CAN frame is 55 bit times, so in the very worst case situation with a completely saturated bus consisting of one data byte frames (which is not really realistic for a CAN bus with any sort of useful performance) you will be receiving a frame every 220 µS (55 / 250000). The cheapest ST microcontroller that has a CAN controller is the STM32F042 ($1), and this has a maximum CPU frequency of 48 MHz. So with this device, you would have approximately 10560 (48 * 220) instructions per message in the worst case.
In terms of dealing with the CAN controller and processing CAN messages, this is a considerable amount of processing power - enough to dump the messages into an EEPROM or SD card with a lot of post processing done on them if required. If that is really all your device is doing then I wouldn't worry about it too much and any of the STM32 devices will be fine. If anything, RAM is probably going to be more of an issue if you need to buffer messages, etc.
In practice I doubt the bus is running anywhere near full capacity (though only you know this) and if you can use the hardware filters to ignore a portion of the messages, then you just gain more and more instruction cycles per message. |
H: full wave rectifier resistor place
Where is the best to place resistor in full wave rectifier circuit?
What is the difference in usage of the resistors in these two
circuits?
(values are not precise)
Three side questions:
what about removing one resistor and replacing the left one with bigger value in the first circuit?
is there any disadvantage of relatively big capacitance of the cap (instead of size) or the wave will be just smoother?
when there is the DC fan, do you recommend any snubber or flyback diode in this circuit?
simulate this circuit – Schematic created using CircuitLab
simulate this circuit
Thank you!
AI: The answer depends on what the purpose of the resistor is. Most of the time, you use none at all.
Note that in both cases, the resistor is in series with the load, so will dissipate power proportional to the square of the load current. Gratuitously dissipating power is a bad idea. If you're going to spend the power, you need to have a good reason. You have not provided any.
In the top case, the resistors will limit the inrush current a bit when the cap is first charged up. Sometimes it is necessary to avoid large inrush currents.
However, R1 and R2 are in series. Electrically, you'd have the same thing by replacing one of them with a 40 Ω resistor and getting rid of the other. Using two resistors in series can be a legitimate way to get a higher power resistor. If you're already stocking the two smaller resistors, it can be all around cheaper to use them instead of stocking a whole new power resistor for a low volume product. In that case putting one in each leg may be useful too, but only to put them physically distant enough from each other so that they don't mutually heat. Electrically there is no advantage.
If it is really necessary to limit inrush cheaply, the usual solution is a negative temperature coefficient thermistor. You size it to limit inrush at room temperature. It will heat up a bit and have lower resistance during normal operation. That still eats power during operation, but not as much as a fixed resistor.
More sophisticated circuits turn on a FET slowly across the inrush limiter. After a few line cycles, the FET is fully on and there is very little resistance in series with the power feed.
The bottom circuit is just plain silly. The resistor doesn't limit inrush at all, just gets in the way of providing power. You haven't told us of any problem it is intended to solve. |
H: Bus isolation circuit
I got a question about BUS isolation circuits.
Is this a correct design?
Looks not to me.
The book said that if POWOK is high, two SMBUS will connect together.
But I think it's wrong, the NMOS should be turned on when POWOK is low.....
The other circuits is like shown below.
I think its purpose is to isolate two power plane of the BUS.
When no power, the MOS is off to prevent the current from the outside ( to the SOC), and when power on and R/W data, if the data is high, the MOS will be off, and the other side will be pulled-up to the level as its power. and when data is low, it can pass through the NMOS to the other side.
Please correct if anything wrong here.
AI: For the first schematic if the POWOK is low it will turn off the NPN transistor allowing the collector resistor to pull the two FET gates to the positive voltage and thus allow the SMBus isolator to function between the VCC3 and the 3VSB power domains.
The second schematic is used to allow SMBus level conversion for the IPMB interface between the 3V3SB domain and the 5VSB domain. No particular power gating is intended by this circuit. It is just that typical off board interface for IPMB has been 5V signalling levels since legacy times and most modern on-board controllers (SOC, chipset or BMC) will be using 3.3V signalling for SMBus. |
H: How does this IF alignment procedure work?
Simple question (I hope!) I've been looking at AM radio alignment techniques recently and IF alignment in particular. The "generic" approach in a valve(tube) radio is to feed the IF frequency into the control grid of the mixer/frequency changer valve and monitor for peak output at the speaker whilst tuning the IF transformers. I would imagine the same technique is generally applicable in transistor radios also.
The control grid of the frequency changer is the RF input with the LO signal arriving on a separate grid. What I don't understand is how the LO signal doesn't interfere with the generated test IF signal fed into the control grid?
The general consensus says that you can perform an IF alignment leaving the LO signal in-place and changing the LO shouldn't affect the IFT output. But doesn't the mixer valve hetrodyne the two signals to produce the IF products (subsequently tuned by the IFTs). So, if you leave the LO signal as an input won't you get variable products and won't it affect the output?
AI: Any real mixer is not perfect; in addition to the sum and difference signals, you'll also get significant amounts of the original RF and LO signals as well. The key is to look at the frequencies of all four output signals.
In normal operation, you feed in RF and LO, and you get RF, LO, RF+LO and RF-LO at the input of the IF amplifier. Only one of these will be anywhere near the passband of the amplifier, and the rest will be strongly attenuated. The goal of IF alignment is to maximize the gain of the amplifier at that frequency.
During alignment, you feed in IF and LO, and you get IF, LO, IF+LO and IF-LO out. Again, only one of these will be close to the amplifier's passband, and it can be used for alignment purposes. While it's theoretically possible to align the IF amplifier to one of those other signals, in practice, the limited tuning range of the transformers makes it extremely unlikely. And in any case, you can make sure that you aren't aligning on a spurious signal by verifying that the indication doesn't change if you vary the LO.
The fact that those other signals are present does not interfere with the alignment process itself. First of all, they're strongly attenuated relative to the IF signal. Second, you're generally looking at relative changes in level at the output anyway. A constant offset caused by those other signals does not affect this. |
H: How to distinguish between Thermistor, Varistor and disk capacitor?
How to distinguish between Thermistor, Varistor and disk capacitor they usually look the same.
Is there any way to distinguish between the three? What are some ways I could do that?
AI: APPEARANCE
Start by visiting Google Images (images.google.com) and study the differences in appearance.
I think varistors are often bright blue or red, and usually glossy, though I don't know if that is a standard. I often notice one of the leads showing through the case for varistors.
Thermistors on google images are often black.
Disk capacitors are often a dull tan/orange with no gloss.
MARKINGS
Capacitors usually start with a 3-digit number like "104" (100nf or 0.1uF), but might have some other markings that indicate other characteristics.
Common kinds of thermistor are "NTC" (negative temperature coefficient) and "PTC" ("positive temperature coefficient) types. I notice that many of the images on google have NTC at the top of the markings. It might be the same with PTC's.
You can try googling markings that you don't understand; you might find what they mean.
MEASUREMENT
A disk capacitor can be measured on a DMM that has a capacitance range.
Thermistors can be measured on a resistance range. Measure it, apply heat, and measure again; the resistance should change.
Varistors often have a very high resistance and may show up as "open circuit" or "over range".
You can google on varistor or thermistor testing or measuring to learn more about what they should look when measured. Understanding the different purposes and constructions of the components will help, too. |
H: I2C Slave address
What is the best way to discover if the I2C slave address is given in the 8bit or 7bit format in datasheet?
As I can see from programming guide for ADV7511 page 16:
The SDA/SCL programming address for the Main Register Map is 0x72 or 0x7A,
based on whether PD/AD is pulled high (10KΩ resistor to power supply = 0x7A) or pulled low (10KΩ resistor to GND =
0x72) when power is applied to the supplies.
I have 10k pull-down resistor on PD/AD, so the address should be 0x72.
But if that is 7 bit format address, that means that I have to add one more bit for R/W at LSB and shift this 7 bit address to the left for one position, and that is 0xE4 for write or 0xE5 for read.
When I send that value over the I2C SDA, only I can read for the address from the osciloscope is value 0x64 (higher 7 bits in byte), so I am assuming that this is not correct, because what is sent and what I see on scope is not the same. Does something limiting that 7 bit slave address, or is it too high? Am I missing something?
AI: It is not stated in ADV7511W Programming Guide PDF that the address which is given is in 8-bit format, so if you're using Zynq7002 you need to write address of slave in 7-bit format to I2C peripheral address register, which is 0x72 >> 1 = 0x39 (PD/AD is pulled down to the ground with the 10k resistor).
Before transfer initiating byte is sent, value (0x39) you wrote in address register will be shifted left for one position to the upper 7 bits and R\W bit will be inserted to LSB of that transfer initiating byte.
Now slave acknowledges every byte, and I have the possibility to read its revision number correctly.
Solution found at https://ez.analog.com/thread/82668 |
H: EAGLE PCB Delete all nets in a selected area
I have a section in my schematic which is full of shenanigans. I want to delete all the nets in the selected box with a single command. Is it possible? I mean only delete nets and not anything else:
If I have to do it manually I have to click 1 million times.
AI: Due to That different nets have different names you cannot delete all of them in one command.
You can use the group function to select the unwanted group of nets, and select the delete command then right click on your schematic page and select delete group. |
H: Snubber circuit
The circuit is a Single phase motor(120V runs 4.7amps running amps), and a relay to trigger the motor on/off.
I'm looking to use a snubber circuit to protect the relay contacts for prolonged use. The motor shouldn't be switching on/off very often but to be safe.
According to this page:
http://www.farnell.com/datasheets/303558.pdf
It says .5 to 1 ohm per volt so 120 v = 120ohms
For amps it says about 1uf per amp. The motor runs 4.7 after startup.
For running current I would be looking for a 120ohm resistor and a 5uf capacitor.
Should the snubber circuit be valued for the running current? I also have a varistor rated for 120V, would this be a equal alternative? The varistor is rated for 1 watt of current.
AI: The best practice for selecting a relay to start and stop a motor is to select a relay or contractor that is designed for that purpose. For areas of the world where motors are rated in horsepower, relays and contactors that have a horsepower rating are available. For areas where IEC standards are used, relays and contactors have IEC utilization categories. Such devices are designed to start and stop motor safely without using either a snubber circuit or varistor to protect the contacts.
Since using a general purpose relay or contactor for motor control is not the generally accepted practice, it may be difficult to find guidelines for doing that. However, very small motors, smaller than about 1/4 Hp or 200 watts, might be suitably controlled by a general purpose relay. Applicable electrical codes are likely to prohibit using devices for other than their intended purpose.
Here are some similar questions:
Max allowed inductive load (pump) for a given relay
switching device for motor
Switching a 220VAC/20A Load with a 5VDC Coil Voltage? |
H: How to identify the loops to apply Kirchhoff's voltage law in these circuits?
Here is what I know so far regarding KVL. To apply KVL to a circuit, the nodes of the circuit must be identified. Then we identify loops in the circuit (a loop starts at a node, travels along one or more branches and ends at the start node). Then apply KVL to the loop.
My problem is with circuits such as a the following
I am having some difficulty in finding the loops in the circuits to apply KVL.
In schematic on the left, because Vcc and ground are drawn as single lines not connected to anything, I don't understand how to form loops to include Vcc and the wire from the transistor's emitter to apply KVL.
Similarly, in the schematic on the right, I don't understand how to include the 10V source in a loop.
I am able to solve circuit analysis questions using Kirchhoff's laws when there are "closed" connections in a circuit. But components like the ones in the above schematics confuse me.
Can someone please help me understand these schematics?
AI: For the first circuit
simulate this circuit – Schematic created using CircuitLab
First loop (Blue)
$$V_{CC} - I_BR_B+Vbe = 0$$
Second loop (Red)
$$V_{CC} - I_CR_C - V_{CE}$$
And for the second circuit with voltage divider:
simulate this circuit
Input loops
(Blue)
$$V_{CC} - (I_B+I_2)R_1 - I_2R_2=0$$
(Green)
$$ I_2R_2 = V_{BE}+I_ER_E$$
And the output loop
(Red)
$$V_{CC} - I_CR_C - V_{CE} -I_ER_E $$ |
H: What is the tolerance level of SMD resistors?
As in normal ceramic and carbon film resistors we can calculate by color codes but nothing mention over the smd components so how to get it? As nothing is ideal so I believe there will be some tolerance level in it also.
please help :)
AI: You can't tell without the datasheet, though there are some hints- usually precision resistors are thin film and look a bit different from thick film. Most consumer products use 5% resistors, some use 1% or better. There are similar size resistors that are 0.1% or even 0.01%, with commensurately better stability and stunningly high price tags (at the low end they are almost free, a reel of 10,000 costing less than a decent lunch, about the cost of a single high precision resistor).
You may be able to tell something from the resistance marking (if any, many smaller parts are not marked at all). If it's made to an E96 series value it's 1% or better, but it's also possible a 2.7K resistor could be 1% tolerance. If it is marked with the 3 character alphanumeric code it's 1% or better.
There are a lot of other things you don't know without a part number, manufacturer and datasheet/manual- the rated power dissipation, the maximum voltage, the temperature coefficient, the rated stability and so on. Tolerance is just one more unknown. |
H: Correct definition of transition in line coding
Hello I have following question and it says:
I basically cannot understand this solution.
My questions:
isn't it a sequence of 4 0s followed by 4 1s? (answer says 4 1s followed by 4 0s) since retangle below the middle line represent 0 in NRZ?
if you see the middle of those rectangle block, I think there is one transition (from what I learned, definition of transition is something that happens when there exists 0->1 or 1->0) at circled area shown in following picture:
But why is answer saying that there are no transitions?
Also above figure looks like polar NRZ but not NRZ. is that really correct drawing?
Thank you very much.
AI: A -1 represents a logic 1 and +1 represents a logic 0 -read the question (in your question) and think about it a bit more.
Yes you are correct
The answer is saying that NRZ can produce long sequences where there are no transistions. That doesn't necessarily apply to the picture in your question but it all depends on what happened before and afterwards.
. |
H: LED Lighting PWM Dimming (LM3404)
The LM3404 is a "Constant Current Buck Regulator for Driving High Power LEDs." One of the features the datasheet boasts is "LED dimming using pulse width modulation (PWM)." My question is, using this chip (and its associated support ciruitry), which of the following accurately reflects the nature of the current delivered to the LEDs?
the LEDs are actually switched on and off (chopped current) at the configured constant current in relation to the PWM input signal
the LED current is proportionately (i.e. in accordance with PWM duty cycle) reduced from the nominal fully bright constant current, but still driven by constant current (i.e. unmodulated).
Something else, if so please explain
AI: The datasheet (http://www.ti.com/lit/ds/symlink/lm3404hv.pdf) describes the DIM pin as follows:
Input for PWM dimming. Connect a logic-level PWM signal to this pin to enable and disable the power MOSFET and reduce the average light output of the LED array
Therefore, the LEDs are dimmed by turning on and off along with the PWM input. There is no analog dimming. |
H: How to represent binary for differential and Manchester coding?
I have some questions with solution provided from random material, but I can't understand well.
Question 1:
I tried to represent binary for each block according to description in the picture above, is this correct? (where you see "? 1 1 1 0 0 0 0 ?") in terms of location I placed and the value of binary.
And also for 2 of "?"'s I drew at the end of each side, what would be good value to be in there? (i simply put "?" mark because I do not know binary for those 2 blocks)
================= END of Q1 =================
Question 2:
Similar question as question 1. I tried to represent binary for each block according to description in the picture above, is this correct? (where you see "0 0 0 ? 1 1 1 1") in terms of location I placed and the value of binary.
And also for "?" I drew around the mid point, what would be good value to be in there? (i simply put ? because I do not know binary for that block)
================= END of Q2 =================
Here are original images without my drawing in case if you need them to answer above questions:
AI: The signal is either at +1 or -1, except when there is no communication. Additional protocols/conventions are needed to detect starts and ends of messages.
For Q1, the two extreme values have no real value, it can be a convention as "messages start with a rising or falling edge..."
For Q2, your ? is a 0.
For the Manchester format exposed, a synchronization method or external clock is needed for determining the phase, else all 1's and 0's are inverted.
For example, with the old 10Mbps Ethernet, frames start with a known header (named "Preamble/Start Of Frame"). For the MIL-STD 1553 bus, frames begin with a high-low or low-high transition with lengthened bit times.... |
H: How to increase current output of an electromagnet controller?
I am modifying a Grove electromagnet controller (schematic below) to output more current with the same inputs. The controller unmodified takes in a 5V power input and a signal of 0-5V with 0-20mA. The output is 0-5V with 0-400mA. So its basically a current amplifier. What I am trying to do is redesign the controller by changing or adding components for the controller to output the same voltage with 0-1A current.
I know the desired current can be reached by changing the components and making sure they have the right power rating but I don't know which components to change and what specific components to replace them with.
The product is open source so I can modify it as needed. I know the electromagnet itself that comes with the controller can't handle that current but I am using different electromagnets for my project. Also, I know adding a transistor and an external power source is more logical to get the needed current output but I am using 32 electromagnets for my project and it's not possible to have a power source for each coil.
AI: There is nothing on there that limits the current, it's just acting as a switch. The only limiting factor in the output current will be the failure of the FET.
The FET claims a maximum continuous drain current of 2.1A, so it should already be capable of switching a 1A electromagnet with no changes.
In the assembly as-sold, the factor that limits the current is the electromagnet itself. |
H: Current kills, but is voltage important?
We always say that a low current can kill. However my knowledge of current is the amount of Coulomb. When that is explained, there is no mention of voltage level...
However, shouldn't voltage be important too? Do we consider a voltage of 120V because this is the voltage in common wire?
Let's make an extreme supposition.
Would 1A with 1 pV still be dangerous?
If so why? Coulomb are like particle as far as I understand, so if they have no energy, why would they be so dangerous?
AI: It is the level of current that determines how dangerous electricity is when it flows into the human body. The level of current is determined by the voltage and the resistance of the path that the electricity is using to enter the body. Thus both voltage and current are important. Assuming the body's resistance is fixed, the current is proportional to the voltage. Low voltages (say below 40 volts) are usually considered reasonably safe because the resistance of the human body is high enough so that dangerous currents will not flow. House mains voltage (usually 120 or 240) is high enough that dangerous currents can flow. Your example of 1 pV and 1A would require a resistance so low as to be impossible given that wire resistances and the range of body resistances are orders of magnitude higher. As far as energy goes, again consider how much energy is being supplied by your mains voltage which is just a flow of current. By the way, a coulomb is a measure of charge and is not a particle. |
H: Turn-on resistance - IGBTs
I would like to find out the internal resistance Ron of this IGBT device :
http://www.infineon.com/dgdl/Infineon-IHW50N65R5-DS-v02_04-EN.pdf?fileId=5546d461464245d30146ae23713f0115
The Ron resistance is not included in the datasheet.
Is there a way to export Ron from the charts that are included ?
Thanks in advance
AI: It's not a MOSFET, it is an IGBT, so doesn't have an Ron resistance in the way a MOSFET does.
An IGBT functions like a combined device with a low power MOSFET driving a bipolar transistor. Because the operating current density for bipolar transistors is higher than FETs an IGBT can carry higher currents than the same size FET.
The data sheet gives the voltage drop at specific currents and has a curve in figure 5 on page 8 that could be used to determine the voltage drop at various currents. Notice that it does not intersect at zero as a MOSFET would and requires about 0.5v to start conducting.
The Simulink model treats the IGBT DC output characteristic as having two segments:
Vf - The voltage at which conduction starts
Ron - The slope of the conduction after that point
From the curve the Vf is 0.5V.
To calculate Ron draw a straight line through the curve from 0.5v to 2.5v. The current increases by ~140Amps over this 2V range. This is equivalent to a resistance of 2/140 = ~14mOhm (0.014 Ohms). |
H: Charging 6 NiMH batteries in series via solar
I'm currently working on a project in which a Atmega328 is powered by 6AA NiMH batteries in series (7.5v, 2000MaH). It is in sleep mode most of the time, except to turn a servo a couple times a day, for a couple of seconds (Hence the need for the high voltage).
I have a solar panel at 12V and 1.8W, so maximum of 150mA. After doing a lot of research, and looking at this post: Charging NiMH batteries with 1W solar panel, charge controller needed? .
The maximum output for my solar panel is within the c/10 -> c/40 range that is safe for the NiMH batteries to be charged at.
My question is, none of the resources I could find explicitly say if what I am attempting is OK for multiple cells like I have.. Due to the remote nature of my device, charging each cell individually, or using a LiPo, is not an option.
Thank you very much.
EDIT: Below is a PCB design for this circuit. According to @BruceAbbott The voltage of the panel would be fine, but since my servo can only handle a max of 8v, would the batteries still be able to lower to voltage to not damage my servo?
I believe the reason it is safe is due to how the current and voltage is controlled from a solar panel, for example, this IV curve (NOT the panel i'm using, just an example.)
This should ensure that the voltage never exceeds the dangerous limit?
AI: The panel will automatically limit the current to a safe 'trickle' charge, so all you have to do is connect it directly to the battery.
If the panel has high dark current then a small Schottky diode in series will block the reverse current. Your panel probably has pretty low dark current so the diode may not be necessary, though it could be a good safety feature if the panel is wired remotely (a short in the panel leads won't short out the battery). |
H: X-acto knife with soldering iron (Durable?)
I know many people who like to use an x-acto knife on their soldering iron. They use it to cut through plastic enclosures for their products. But the question is, how long will the x-acto knife last with the heat?
AI: Given that the blade is made from Steel, and Steel melts at around 1400°C, heating it up to a mere 350°C is not likely to do anything to it other than perhaps tarnish the surface.
Given also that it's not the blade that's "cutting" through the plastic but rather the heat of the soldering iron melting the plastic, it is probably somewhat irrelevant how sharp the blade remains, or whether or not it tarnishes.
I'd be more concerned about the soldering iron. Cutting through plastic leaves a nasty hard to clean residue. While it doesn't really matter if this gets on the blade, if it gets on your soldering iron tip you'll likely never be able to use the tip again for soldering. If you remove the tip and it gets on the heating element then it will degrade performance next time you try to put on a new tip by reducing heat transfer. |
H: What is the use of 'import' in SystemVerilog?
Once a package is included, the file is compiled. Then why it is required to import the same package?
AI: There is an interesting article here regarding the difference between import and `include when it comes to packages. I'm going to attempt to summarise it here.
When you `include a file, it is basically saying take the contents of that file and paste it at the location of the include statement. This is effectively the same behaviour as #include in C/C++.
Great you are thinking, now we have everything in the file, why can't we just use it? Imagine the case though where you are declaring a package in SV. If you `include a file containing a class A into two different packages P and Q, you are basically making a different copy of it in each package, which because of the way SV handles types will be incompatible (you now have one class called P::A and another called Q::A).
This is where import comes in. Unlike `include, the import statement does not copy the definitions being brought in to the file, instead it simply makes them visible. This is similar to the way the using namespace works in C++. Lets say you still `include the class A in package P as before. But now, rather than including A directly in package Q, you import P::A instead, both P and Q now contain the same class P::A instead of having two different ones.
So in summary:
`include copies the contents of the file in making a local copy of any classes/types/etc.
import doesn't copy but rather makes the existing package declarations visible in the current file. |
H: CAN bus signal integrity
The channels are CAN_H (red), CAN_L (blue), and CAN_H-CAN_L (brown).
It can be observed in the diagram below that CAN_H-CAN_L has an acceptable signal shape. However, both CAN_H and CAN_L look poorly to me. And actually the device is not running in a noisy environment. I have two questions:
Do you think signal integrity is an issue here?
CAN_H-CAN_L sometimes has high voltage level of 1.65 V (left side part), while sometimes it has a high level of 2.06 V (right side part). Do you think this is a problem?
AI: No. The differential signalling is performing as intended.
No. As long as the "common mode voltage" does not exceed the ratings of the transceiver. And the maximum DC ratings, which for a CAN transceiver like the MCP2551 is -42 V to +42 V.
The twisted pair cable and the differential signalling mode make the single-end signals look like gibberish while the differential signal is not affected by the noise. You will have the occasional corrupt frame, but CAN has several features to ensure only correct frames are accepted and bad ones are re-transmitted.
CRC to detect bit errors.
Error frames. When one node detects an error, it sends an error frame, and this frame forces the bus dominant longer than the bit stuffing rule. All nodes see this.
Automatic re-transmit until the error limit.
I have one of these images as well. These are textbook images on differential signalling. This kind of noise is inevitable in systems with electromechanical or high power switching components. |
H: where can I found STM32L4 DSP and standard peripherals library?
I want to use standard peripherals library for stm32l476rg(stm32-nucleo). But I could not find it. I dont want to use HAL Library. Do you any suggestion?
AI: ST doesn't have a "standard perhiperals library" for L4 as they used to have for other chips, but was discontinued and replaced by STMCube. STM32CubeL4.
However, ST does have Low-Level API. This is new, and is more similar to the old "std periph". These start with: stm32l4xx_ll_.
All of which are found in the STMCubeMX tool.
DSP library is found in CMSIS, not from ST, but from ARM. This is included in ST's library package though. |
H: Are flags strictly related to interrupts or not?
If we want to some flag to be set when true (for example FIFO is full), does that mean that we have to enable the interrupts?
Whether it will be set if interrupts are not enabled?
Are that flags always triggered, but it is on us to chose the way how we want to handle those events (polling or interrupt way)?
AI: They are not strictly mapped to interrupts. Usually a peripheral (let's say an UART), has some flags like transmit complete, receive complete etc.
In the ARM world a peripheral can have one or two (or many vectors). For example the Kinetis has a single vector for UART (no matter if it is RX/TX, the ISR has to check the flags to find out why the interrupt happened), but dual vectors for CAN (MSCAN - separate TX and RX vectors), so the mapping varies from part to part.
Flags can also be used for triggering DMA without any sort of interrupts or for triggering event systems (like the "peripheral reflex system" in EFM32 or "event system" in XMEGA). For example on the EFM32 you can use the LESENSE peripheral to control the ADC and DAC, when some threshold is reached the "reflex" is fired, which tells a timer to count a pulse. |
H: How to interface AMBE-4020 vocoder chip to Ti CC2640R2F Microcontroller?
How to interface AMBE-4020 vocoder chip to Ti CC2640R2F Microcontroller?
The user manual of AMBE-4020 has not given any detail about this.
AI: The general procedure for connecting another chip to a microcontroller is:
Read the microcontroller datasheet.
Read the other chip datasheet.
Assuming a appropriate microcontroller was picked in the first place, think about what I/O you want to use on the micro.
Wire it all up.
Write the code.
I don't see any reason for this process to be different in your case. |
H: PCB design, Ground plane and power plane issues
This is the first time I am designing a 4 layer PCB. The circuit will work on multiple frequencies: Signal acquisition part works on few Hz to 200 Hz(max), but one portion of the circuit will generate 13.56MHz. Power supply is 3.3V from a Lipo battery. I am planning to stack the layers as follows:
Signal
Ground Plane
Power Plane
Signal
I am using KiCad. I have already created ground plane and power plane. I have connected the negative terminal of battery to the ground plane by via. The schematic has a lot of ICs which require ground. I am just connecting those pads to the ground plane by vias too.
My question is: Do I have to route the connections in ground plane layer(all of them together, I mean do I have to connect them together again in ground plane-2nd layer of my PCB) or will the vias from the IC pads (supposed to be connected to ground as schematics) to ground plane will do? My understanding is, ground plane is full of copper unless I route any signal through them.
AI: In KiCad, to create a GND plane you have to use the "Add Filled Zones" button from the toolbar normally visible on the right side of the screen. Select the layer you want this zone to be at and draw your plane. You would usually want to cover the whole layer with this zone / GND plane.
After doing this, every normal GND via that you add it will automatically go through all layers and will automatically be connected to the GND plane as well. I mentioned normal via, since there are the blind and burried vias, which wouldn't necessary mean that they would be automatically connected to your GND vias.
In the end, you can anyway control if there is a connection or not. If your via is shown to have a thin white line attached to it, that seems to be connected to an IC GND pin or some other GND point on your board, then you know that the intended connection to the GND is not done. |
H: Optimal design choices for mosfet driver for DC-DC step-down converter
I'm dealing with an application in which a DC-DC converter is used to transform an input voltage of 15V DC into lower voltages.
The current configuration makes use of an LM27222 with two mosfets in push-pull configuration. The output voltage is linearized into an LC filter.
Here's a picture of the general schematic used.
The LM27222 is driven by a PWM signal with a carrier frequency of 65 KHz. The mosfets used are of type FDMS86101DC. The logic level voltage is 5V.
The output current to design the system is 10A. The load is resistive.
The system works fine, but some concerns have been raised to avoid collisions between the two mosfets (both transistors ON), especially during start-up/turn-off sequence. This happened a couple of times during testing of new firmwares, but, most probably, the problem was related to the testing engineer which not so carefully "touched" the output leads generating a destructive shortcut.
According to one of the new engineers we have been working with, we should:
Substitute the LM27222 with another driver, the L6388E, which should be much more stable than the LM27222 and avoid any change of collision, even in transition sequences.
Add a diode in series with the low-side mosfet. This diode should add additional protection during transient
Add a complex filter to the Vin line. The filter should have a common-mode and a differential mode inductor, together with a large electrolytic capacitor and several small ceramic capacitors. According to the engineer this filter should limit the demand of pulsed power from the power supply, and result in a more "compliance-friendly" design to meet the EMC (electromagnetic compatibility) regulations. The Vin comes from a AC-DC desktop power adapter and he is concerned that the connection cable from the power supply to the electronic card could radiate frequencies because of the required pulsed power. Besides, since several of these power supplies got broken during tests, the engineer is also suspecting that we are throwing some important noise back into the power supply, leading to failures.
Here's a picture of the L6388E internal schematic.
I would like to ask two questions:
Is it necessary to carry out all the steps suggested by the engineer? The change of LM27222 is particularly painful and I would avoid that if it does not give clear advantages.
If we decide to keep the current configuration with the LM27222, how can we drive the LEN signal to avoid problems at start-up and turn-off of the system?
AI: The L6388E doesn't look at all that good in the data sheet for your application. For instance (and this worries me) they say recommended max operating frequency is 400 kHz and that shoot through dead-time is nominally 320 ns. That means dead-time can be 13% of the overall switching cycle. They don't appear to recommend nominal operating conditions and neither do they offer a "typical" circuit in their data sheet.
Minimum Vcc for the part appears to be 9.1 volts and this well below the 4 volts to 6.85 volts in your default schematic.
Adding the diode in series with the lower MOSFET is a bizarre thing to recommend and defeats the efficiency gained by using a synchronization MOSFET. |
H: Where does the power supply current return?
I am a bit confused about return currents on a ground plane. I try explain it based on drawing. Let be a PCB with ground plane that is powered by external power supply through a connector. An LDO regulates appropriate voltage for component on board.
Does the current of this component return to the LDO ground or to the main ground connection? (Which of 2 arrows does the return current follow?)
simulate this circuit – Schematic created using CircuitLab
This confusion stems from uncertainty in my head, how to treat the power connection. If it should be treated like a signal, the the current returns to the LDO. On the other hand an LDO doesn't "produce" current, but simply dissipates excessive external power. It itself returns current to the ground connecter. Thus, it ground pin serves double purpose: return current to the ground connector and receive return currents from the component(s), which seem odd to me. Rather it seems to me that the true surce of current is the main power connector and that's where the current return.
Understanding this problem is important for how I place LDO and components, that it powers, relative to each other.
AI: Primary current flow is from the component to the connector. A secondary (usually smaller) current flows from the ground of the 7805 to the connector. This secondary current is the current drawn by the 7805 in operation, and can be found in the data sheet. (And, as a comment, a 7805 is nobody's idea of an LDO, which stands for Low Drop Out - the minimum voltage difference between the input and output).
At this level of performance, there is no need to worry about the effects of ground currents, although if you ever get to dealing with amps or 10's of amps, or mixing high-speed logic with sensitive analog functions, controlling the return paths of ground currents can become quite important. |
H: Why would electrons cross a cross section when there is no potential difference?
There is a cross section , it's said that electrons move from left to right and vice versa, and the total sum of the electrons crossing this section from left to right is equal to the ones crossing from right to left.
When we have potential energy (a battery connected to 2 sides of this section) electrons going from left to right are more than the ones going from right to left, and then there will be electrical current.
My question is, why would electrons move when there is no difference of potential?
Edit :
electrons that move are free electrons.
AI: First, there is a small change you need to make.
electrons going from left to right are more than the ones going from
right to left, and then there will be NET NON-ZERO electrical current.
With that done, you should be aware that free electrons, like any particle, are incapable of being perfectly at rest (except at absolute zero). That is, they will exhibit random motion, usually called thermal motion. With no potential applied, the average overall, or net, motion will be zero, and so will the current. |
H: Are oil-filled transformers ever run at a vacuum?
Larger oil-filled transformers are sometimes dehydrated by removing the oil and pulling a vacuum inside the chassis for an extended time. That requires that the chassis must be rated to hold a vacuum. If I read correctly, the dielectric strength of a vacuum is greater than that of the insulating oil. Given that, why not just run such a transformer at a vacuum all the time? Do the thermal benefits of the oil overwhelm the benefits of the insulation being perfectly dry all the time? If so, could you design a transformer that wouldn't have that property? Are there, in fact, transformers designed for vacuum operation?
AI: Large oil-filled transformers use the oil as a thermal transfer medium as well as a dielectric. That's why the cooling fins are on the outside.
If there was a vacuum inside the coils would run very hot and would require massive derating to protect the wire insulation. There would still be heat loss through the wires to the outside world and also by conduction through the mounting means, and by radiation to the housing. Transformer oil is essential to minimizing the size and cost of large transformers. Pure water would be vastly thermally superior to oil, but the slightest ionic contamination would be an issue.
There is no particular trick in making a transformer operate in a vacuum, it just has to be designed so the heat produced can get out of the innards. If it's for space use you may have to specify materials that don't outgas excessively. |
H: LDO Regulator TPS737xx, connecting Enable to VIN and avoid damage when removing VIN
I'm designing a PCB that is powered by this solar charger using a 3.7V LiPo battery (maybe I'll have to move up to a 4.2 battery). I want to regulate that voltage to 3.3V for feeding a microcontroller and I've selected a TPS73633DBVT, this is a LDO voltage regulator with fixed 3.3V output and 75 to 200mV dropout voltage.
The datasheet says that I can connect the enable to vin if I don't need it but it also says that stuff could happen if I remove the battery from Vin, which is what I can't understand. It says:
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power-up.
Could someone please explain me what this means and how can I avoid damage when the battery is removed?
AI: It basically tells you that when EN is connected to VIN, it may happen that current flows from the output towards the input, after VIN has been removed. Or/and that upon power-up the ramp up time of the output may be faster than usual.
This is due to the fact that the gate of the MOSFET that is the switching element (in broad terms it is inserted in-series between the input and the output) may maintain some charge, with the result that the MOSFET is still conducting. That's why this reverse current may be observed and the ramp up time may be faster.
The correct way to do it in order to avoid such a case, if you had the EN connected separately from VIN, would be to first drive the EN low to discharge the gate capacitance of the MOSFET and then remove VIN.
There is actually no real risk for the LDO itself or your battery, since it is anyway removed. It's just something they mention because it could be undesirable for some applications. I believe you shouldn't worry about this. |
H: How does the Miller effect affect a JFET-amplifier stage with tuned-circuit input?
I'm trying to build a simple JFET amplifier of MW signals (500kHz-1.5MHz) using a ferrite antenna and a variable capacitor to tune the desired station. The schematics is pretty obvious, as seen in the following figure:
While designing it, I wondered if Miller effect has any impact here, as it will lead to a capacitance between JFET's gate and source and, with source grounded at AC due to \$C_s\$, Miller capacitance will appear in parallel with tuning capacitor \$C_t\$ so, apart of modifying the tuning range (which I can compensate adjusting the self-made coil) I don't see any other obvious harm here. Am I right?
AI: I wondered if Miller effect has any impact here, as it will lead to a
capacitance between JFET's gate and source
Miller capacitance is between drain and gate but for JFETs you can usually find types with about 1 pF so go for something like an 2N5486. 1 pF multiplied by voltage gain could be somewhat troublesome at 30 MHz but not at 1 MHz because Ct is going to be several tens of pF to hundreds of pF.
Try it and see and also compare your design with one on the internet using JFETs. |
H: PIC16F877A PORTA RA4 not working as ouput
I have used RB state change interruption to turn on two LED connected to portA (pin4 and 5). The probem is when interruption occurs LED on pin5 turn on, but not LED on pin4. When I change pin4 to pin3 it works normally, but I can't use this pin, because my circuit is already printed.
I've read the datasheet, and I understand that PORTA pin4 is multiplexed with Timer0, is that causing the problem? How do I disable that?
XC8 compiler code:
#define _XTAL_FREQ 20000000
#include <xc.h>
// BEGIN CONFIG
#pragma config FOSC = HS // Oscillator Selection bits (HS oscillator)
#pragma config WDTE = OFF // Watchdog Timer Enable bit (WDT enabled)
#pragma config PWRTE = ON // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = ON // Brown-out Reset Enable bit (BOR enabled)
#pragma config LVP = OFF // Low-Voltage (Single-Supply) In-Circuit Serial
Programming Enable bit (RB3 is digital I/O, HV
on MCLR must be used for programming)
#pragma config CPD = OFF // Data EEPROM Memory Code Protection bit (Data
EEPROM code protection off)
#pragma config WRT = OFF // Flash Program Memory Write Enable bits (Write
protection off; all program memory may be
written to by EECON control)
#pragma config CP = OFF // Flash Program Memory Code Protection bit (Code
protection off)
//END CONFIG
int main()
{
TRISA = 0x00; //set portA as output
TRISB = 0xFF; //set portB as input
TRISD = 0xFF; //set portD as input
TRISC = 0xFF; //set portC as input
ADCON0 = 0x00; //disable AD converter
ADCON1 = 0b10000110; //disable AD converter
OPTION_REG = 0b00000000; //disable AD converter
INTCON = 0b11001000; //enable port b pullups
PORTA = 0x00; //turn off LEDs
while(1)
{
}
return 0;
}
void interrupt isr(void)
{
if (INTCONbits.RBIF) {
if (PORTB) {
asm("nop");
}
INTCONbits.RBIF = 0; //clear interrupt flag
PORTAbits.RA4 = 1; // turn on bottom LED
PORTAbits.RA5 = 1; // turn on top LED
}
}
AI: RA4 on that microcontroller is an open drain output. This means that when you set it as low, the output will be low; but when you set it high the output will be tristated (high impedance).
You will need to change your LED configuration to turn it on with an open drain. |
H: busted WS2811 LED strip by overpowering, totally useless now?
Powered a 5V WS2811 LED strip with 12V by accident. It turned on for a split second, it fried a microcontroller, I noticed the smell and turned everything off as fast as I could.
When i tried powering the LED strip again with 5V (also exchanging for a new microcontroller of course) only the 2nd LED in row turned on. I cut off the first 3 LEDs and soldered the wires on again, but now nothing turns on.
Does that mean the whole 5m LED strip is busted or is it possible some LED+ics further down the line could be salvaged?
AI: All the ICs in the strip are powered in parallel. It is entirely possible that every chip in the strip is now broken. |
H: Repurpose a MagSafe 2 Charger for USB-C
Hi Mac Owner here that is now dealing with cable hell...
I have an inexpensive 60W MagSafe 2 charger that I was wondering if I was able to rewire the connector for USB-C. I have experience with electronics from a repair stand point, but almost zero electrical theory.
Is this possible? Where do I start?
AI: Charging over USB C uses "USB power delivery" to negotiate the voltage and current, starting at a "safe" 5V.
So no you can't really convert a generic power brick to a USB C laptop power brick without significant extra electronics. |
H: Audio amplifier provides the capability to drive 660Ω loads directly without buffering
From PGA2311 datasheet we can read this sentence.
Does that mean if I drive a 660ohm load at power P, in order to drive a 100ohm load with same power, PGA2311 won't be able to source enough current? So a buffer is needed?
How can I determine load values range from datasheet? Is it related to output buffer short circuit current?
AI: The output of the PGA2311 is a voltage source that, if powered with a +/- 5 volt supply, has an output range of -3.75 volts to +3.75 volts. The output can drive up to 50 mA of current.
This means that if you connect a 100 ohm load, your worst case current will be 37.5 mA, well within the rated output current. You should perform a thermal dissipation calculation, however, to make certain you do not require a heatsink since the device power dissipation has gone up by a factor of 6.6 from their reference design.
The device is designed for a 660 ohm load and unfortunately they do not specify the effect on THD based on load impedance. You can call an application engineer at TI if you are concerned about this parameter. |
H: Butterworth filter with non arbitrary component
How do I design a filter with certain cutoff frequency and as flat pass-band as possible, given that:
one of the filter components is non arbitrary, and
that filter component does not match the corresponding Butterworth prototype (i.e., the impedance conditions and cutoff frequency)?
For this question, I understand that performance will be degraded compared to real Butterworth filter. Still, is there known analytical or numerical method for designing this to match the Butterworth filter as closely as possible?
As you see in the schematic below, I can arbitrarily choose values for \$L_{1}\$ and \$C_{2}\$. However, I cannot change the source or load impedances (since they do not change with frequency), nor can I change \$C_{fixed}\$.
simulate this circuit – Schematic created using CircuitLab
AI: Like the Butterworth itself, this is an optimization problem.
Pick a way to parametrize "flatness in the Pass Band" as an error term (call it E) -- maybe rms deviation from flat, or some such -- figure out the closed form solution E in terms of your fixed and floating parameters, and minimize it. |
H: What is the difference or relation between Rd and Rf in a diode?
For the small signal impedance of a forward diode we usually write:
$$r_d = \frac{n\cdot V_T}{I_D}$$
However, in datasheets one usually finds a specified forward resistance: \$r_f\$
Can anyone explain the difference and or relation between the two?
AI: You have an equation for the DC dynamic resistance- the Shockley equation, minus the ideality factor (Edit: it has now been added in). And it's valid- at a few hundred Hz, certainly.
However to, quote from this app note, "The DC dynamic resistance point is not, however, valid in PIN diodes at frequencies above which the period is shorter than the transit time of the I (intrinsic) region. The frequency at which this occurs, fT , is called transit time frequency".
Above fT, the resistance is still inversely proportional to applied current, but is significantly lower. The proportionality factor depends on the physical parameters (Intrinsic region width and electron and hole mobilities and carrier lifetime).
\$R_S = \frac{ W^2}{(\mu_n + \mu_p) \tau I_F}\$
Where W is the intrinsic region width, \$\mu_n\$ and \$\mu_p\$ are electron and hole mobilities and \$\tau\$ is the carrier recombination time.
We can predict fT as follows:
\$f_T = \frac{1300}{W^2}\$ with W in microns and fT in MHz, so in the case of the Infineon diodes W = 4.5\$\mu m\$ so fT = 64MHz. |
H: Arduino Controllable Digital Pot for Motor Controller
I have an analog motor controller that has a B10K potentiometer on it. I'd like to be able to swap out the analog potentiometer for a digital one, but I'm not exactly sure what voltage is being sent to the original potentiometer as I don't have the spec sheets for it.
My current specifications, which work as a prototype, are:
- Power supply: 48V 4A transformer, connected to...
- Variable speed DC PWM Motor Controller which controls...
- A 130V 1A max DC motor.
I'm fine with the power and speed that 48V gives me, but do I need to specifically look for a digital potentiometer that can handle high voltages, or would a standard 10K digital pot work?
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. Analog input on motor controller.
Many industrial motor controllers are designed to work from a 0 - 10 V signal. To provide flexibility they usually provide a reference voltage - typically 10 V - so that a pot can be used if an analog control signal is not available. If this is the case on your controller then you may be in luck.
With a multimeter check to see if the potentiometer low-speed end is connected to the controller common. If so ...
Check the voltage between Node1 and common.
Check the control voltage between the wiper and common.
These measurements should give you enough information to decipher how the analog input works. If all is good you can control directly from an amplified analog signal with no need for a digital pot. |
H: Mbed LPC1768 Too Slow for Virtual Methods
I've written an OOP program which calculates the position of an object following a Trapezoidal motion trajectory - accelerate up to max speed, coast until decel point, decelerate to target position.
The trajectory code is based around a state machine using virtual methods.
When I run the code on my Macbook, the program completes in a few seconds. On the mbed LPC1768 dev board, the program takes minutes to complete (far too long for my needs).
Is there anything in my code which could be slowing down the program? Should I upgrade to a more powerful chip? I'd really like to keep the OOP state machine if possible.
Perhaps somebody could also run the program on other mbed boards and see whether it completes in less time.
AI: I suggest learning about your microcontroller.
Cortex-M4F has single-precision FPU.
Cortex-M4 has no FPU.
Cortex-M3 also has no FPU.
Manipulating double-precision floating point numbers without FPU is horrendously slow.
Now, the question is, if the code is about fast double-precision FP performance, why did you select a micro without a double precision FPU? (or any FPU at all...)
(Note: I'm not aware of any micro with a double precision FPU).
EDIT
@peufeu, Essentially, yes. The position will be compared with an encoder count, subjected to a PID loop and the result outputted to a DAC.
OK, so why not do just that? That's 1-2 pages of C code, maybe a tiny state machine... quite simple. No need for classes and Movers/Managers/Bloat. Implement your state machine using switch/case, obviously. "State" pattern has no place here.
@peufeu, In what way am I abusing C++, if you don't mind me asking?
Why do it in one page of code when you can fill in a Mover class, one class for acceleration and deceleration and whatnot, and 13 source files?..... the result of which is you have no idea what the program is actually doing, and thus you wonder why it is slow.
The purpose of C++ is to have clear, readable code, which is also high-performance as the compiler can optimize it. If you want a dynamic language, use Python. If you want to turn a motor, use C.
Since a motor is slow by microcontroller standards, you can't possibly need more than, say, 1k updates/s on your PID. Using an ARM Cortex is fine, you can even use floats if you want... even without FPU and in software emulation...
I mean, a PIC16 can do it...
You can use float (or double) if you like safety, since your micro has plenty of power to spare.
Fixed point would only be useful performance-wise on a tiny micro. However it has other advantages, for example if you use a 32 bit value to encode your turns, with say 8 bits for the degrees from your encoder, then counting turns and doing modulos and stuff like that is very simple, but of course you got to guard against wrap around bugs.
Floating point allows you not to care about wraparound bugs.
As-is? It seems to hide a few dozen lines of maths in a thousand lines of abstraction. There are apps written this way, e.g. Eclipse, but this style really only makes sense in huge componentised apps.
pj_50 -> Eeeeexactly, well said. |
H: Possible to run MCP2003 on 3.3v?
I'm planning on connecting a MCP2003 to a ESP8266.
The voltage levels of the uart (and any io) on the ESP8266 is 3.3v.
As far as I understand the datasheet, the MCP2003 needs to be powered by 6-30v, and it's io (out) levels on the uart side match the power voltage.
So:
Is it common that the 6v is the absolute minimum for these kind of chips, or do I have a chance that it'll run at 3.3v?
Am I missing or misunderstanding something in the datasheet that could help me do what I want? (For example, is there another way to get a lower output signal? Or is there so little power behind the signals that the ESP would be fine fine with them?)
If neither of the previous questions give me a way to do what I want, what would be the easiest or least component alternative?
Some background information:
What I want to do is to control a AXA Remote 2.0 device with an ESP over wifi. This device uses a LIN bus, and the MCP2003 converts from UART to LIN.
The voltage on the LIN bus is higher as I understand it, but this shouldn't be a problem, as the MCP2003 can handle that (I think). I haven't quite figured out how the LIN 'output' from the MCP2003 works, can't find a easy description of LIN, but I'm guessing it the bus get's pulled down similar to onewire? In which case there's no output voltage to the LIN bus to worry about.
The AXA Remote 2.0 device sadly isn't very well documented, basically this is it: http://files.domoticaforum.eu/uploads/Axa/AXA%20Remote%202%20domotica%20English%202012nov_V2.pdf It shows how to solder a MCP2003 to a 5v TTL USB serial dongle :)
Any helps or insights would be greatly appreciated! :)
AI: The MCP2003 uses TTL inputs and Open Drain outputs for communicating with your MCU.
That means that the TXD pin needs a HIGH signal that is between 2v and 5.3v and the RXD pin swings between 0v and whatever voltage you pull it up to with the required external pull-up resistor.
All of those are what an ESP8266 can work with. Of course you still need to provide the minimum 6v supply to the chip for it to work.
All this is shown in the datasheet both in the form of a simple schematic and a table of voltages:
(Green annotations are mine)
R1 is a pullup resistor for the Open Drain output of the \$R_{XD}\$ pin. It should pull up to the logic level of the receiving device (ESP8266; 3.3V).
(Reduced to only show the two logic voltages of interest) |
H: Reset circuit for D-flip flop?
I need to capture the posedge of a signal (ONSWA) and output another signal (PSHOLD) high until I see another posedge of ONSWA. My solution is to use a DFF with an inverted output with ONSWA as the clock and D <= !Q. Now my question is how to properly ensure this circuit is reset when powered up. My solution is to use a RC circuit on both D and CLK but I want to know if there is a better/simpler way. My main concern the power usage--the circuit should not use too much power while in the "off" state (since it's battery powered). I also would like to avoid having PSHOLD high for a small period during reset if possible. If there's a better solution than a DFF or a better part, I would like to know that as well.
EDIT: Okay I've updated the design to use a DFF with (re)set.
AI: The classic POR (Power On Reset) circuit with a 74HC74 looks like
simulate this circuit – Schematic created using CircuitLab
The R1/C1 time constant is set to be significantly longer than the rise time of the power line, typically 10's of milliseconds. The two inverters are Schmitt triggers because the capacitor voltage rises relatively slowly, and CMOS does not handle slow transients gracefully. The transform the exponential waveform to a nice clean logic signal. The diode protects the first inverter in the event of a fast drop in power voltage by discharging the cap rather than letting the current flow through the inverter.
If you're feeling lucky and/or cheap, you can eliminate the inverters, especially if you can guarantee that the clock input will be inactive during the transition period. And you only need one of these POR circuits to provide a power-on signal for an entire logic system, so the added complexity is usually lost in the wash for larger systems.
Alternatively, you can use a dedicated power supervisor chip such as the TL7705 and others of its ilk. |
H: -5V to 5V DAC Design
I am trying to design a 10 bit DAC using an R-2R ladder. I hope to achieve a signal that can vary from -5V to 5V.
In the circuit provided, I am showing my design for 5 inputs. I have used Mosfets instead of directly connecting the MCU I/O pins to the DAC because their resistance varies a lot with the temp.
My question is, does this seem like a viable circuit in terms of generating the desired output signal.
This is my first time on this site so if I violated any of the posting rules, I apologize.
Thank you for your time!
*Update: I have adjusted the requirement of the DAC to produce a 0 to 1V signal which I will adjust using an opamp.
Based on the replies, I believe this circuit should do the trick!
AI: Won't work. You need to drive the ends of the 2R resistors push-pull from +5 to -5, not just to +5, so you need something like complementary MOSFETs and level shifters.
Edit after 2nd schematic added- since Vdd is 3.3V you need a more complex level shifter. Maybe something like this:
R2/Q2 could be replaced with a logic level MOSFET- 2N7000 is a bit marginal at 3.3V.
simulate this circuit – Schematic created using CircuitLab
Unless you are doing this for educational purposes it may be better to just buy a DAC. Of course you could also use a high-Z R2R ladder off the MCU and use an op-amp to shift the 0-3.3V output to +/-5V. Plenty of answers here on that sort of thing. |
H: Calculating CRC for bootloader firmware
I am using PIC32MZ2048EFH064, MPLABx3.40, XC32 V1.42, Harmony V2.01b. And my PC app is using MS Visual C++ 2010 Express.
Instead of using microchip's Pic32 downloader I want to build my own downloader and, I want to download my custom encrypted firmware using PC host application. Now problem is, I am able to connect and download the bootloader firmware using my custom app, but CRC verification (i.e. program verification) is failed. Because the CRC calculated (and sent) by firmware doesn't matches to the CRC calculated by my custom app for the hex file. Now my observations are :
Both are using same address range and same program length over which CRC is calcuated.
Address range is : 0x9FC00000 - 0x9FC0FFF4.
Both are using same CRC table, CRC routine to calculate CRC.
I want to ask that, whether calculating CRC should include config register area also?
AI: Usually your program image would only have its verification CRC computed across the image and not any of the configuration registers in the MCU. But be aware that CRC calculations can have many variables even with the same CRC acceleration table. Some of these factors:
Are the CRC bytes locations in the image itself included in the calculation?
Do you start the CRC calculation loop with a seed of 0x0000 or 0xFFFF?
The order you store the CRC bytes in the image needs to be comprehended.
The CRC table is typically 16-bits wide for MCU type application. It makes a difference if you take the high table byte first into the computation loop or the low byte.
Sometimes the final computed CRC is logically inverted before having its value stuffed into the image.
It is strongly recommended that you prototype your CRC generator and checker routines in a PC C language environment to ensure the algorithms encode and decode the same way. If you are trying to put your own algorithm up against that generated/decoded by another tool it is especially important to test it thoroughly before you ever try to make it work on a live embedded system where it can be more difficult to test and debug. |
H: USB 3.0 RX&TX Connection
Sorry for the inexperience. This will be quick.
I have two Texas Instrument ICs, one is a device, the other is a hub.
I'm looking at a USB 3.0 device that has the TX and RX lines. When connecting directly to the hub, I should be switching those lines right?
TX (Device) <--> RX (Hub)
RX (Device) <--> TX (Hub)
This breaks down further...
TX+ (Device) <--> RX+ (Hub)
TX- (Device) <--> RX- (Hub)
Is this correct? I'm looking at USB connectors to try and get an idea but it seems like the pinouts that are labeled in pictures match up the TX+ and the TX+ on each side and that doesn't make sense!
AI: You are correct in that high speed transceivers are unidirectional, so in much the same way as UART you must connect transmit at one end to receive at the other.
Typically this crossover is done in the cable. What that means is that on the PCB you would wire the TX of a USB controller to the TX of a USB socket, and the RX of the USB controller to the RX of the socket. You would not cross them over on the board.
However, as you are not using a cable (missed that initially, sorry), they you will need to cross the signals over. The RX of one device must always connected to the TX of the other device and vice versa.
For the D+/D- lines, they shouldn't be swapped at all, simply connect with the corresponding D+/D- on the other end.
TL;DR Yes, you should connect the TX of your hub to the RX of your device. |
H: Need help adding gain overdrive/control to my tube guitar amp design
I'm new to analog electronics, so bear with me. Consider my guitar amp design:
What we have is a 12AX7 feeding into a cathode follower, going into a James tonestack, through another 12AX7 gain phase, then through another cathode follower.
So I'm kinda doing something cool here... I'm splitting the plate load resistors and adding the feedback in between the split resistors. According to Designing Tube Preamps for Guitar, this makes the net A/C across R5 and R13 near 0, making the gain of the stage very very high.
So problem #1: I'm unsure how to actually calculate the gain of those stages, and what my output Vac will be. My limited understanding calculations say 1Vrms coming in will be about 20Vac going out for the first stage... I think.
Problem #2: I want to be able to switch the amplifier from Carlos Santana mode to Hank Marvin mode. So if there is excess gain leftover from after the tone stack, I want to shunt it to clean up the amp. Normally a voltage divider pot does this between stages... but I'm trying to figure out how do that in this case. My thought is to put the voltage divider after C2, but I'm not sure how that'll affect the tonality of the stack.
Finally, bonus round... I want to use a dual gang pot between wherever I put the gain control and have RV3 be the inverse of the gain control. Any thoughts on that? So as I turn my gain control up, RV3 shunts more to ground, reducing the output signal. I couldn't find and designs using this type of idea, but I'm wondering if it's been done before.
Many thanks!
AI: The first tube is an anode gain stage bootstrapped with the signal taken on the cathode of the next stage. This is a positive feedback that tries to keep the current flowing trough R5 constant. This turns R5 to a virtually huge impedance load as seen by U1A. This is good because the ECC83 has a high internal impedance (rounded to 60k) so it needs a high load not to loose gain.
Since the current flowing through the tube becomes nearly constant, it compensates the fact R3 is not decoupled which results in a dramatic raise of the stage amplification. Using this bootstrap method you can bet it will give a gain between 80 and 100.
The direct coupling between the anode gain stage and the cathode follower is also a good thing in a guitar amp since, depending on the bias of the cathode follower, its grid may steal current from its neighbour causing nice H2 distortion.
Maybe a solution for being able to switch between high gain and low gain, would be a switch in the bootstrap loop of the second pair of ECC83. The filters behind the first couple of triodes will decide the output level of the amplifier. |
H: Rectifier for two phases (220 V 50 Hz)
I have a switch circuit which works with two phases. I need a flyback SMPS power supply for my logic circuit. I want my control circuit to be alive if any or both phases are receiving power. This can be achieved if my bulk DC capacitor receives power from both phases simultaneously. Currently, my power circuit receives power from a single phase like this:
To add the second phase, I am planning to do this:
Will it work? I think it should because the capacitor's voltage will block any voltage lower than it's voltage right behind the diode itself, at any point of time.
Or, am I wrong? At the bulk capacitor, will there be two voltages fighting each other?
In case it works, can I do something like this:
I have removed the redundant neutral supply in the bottom rectifier, thereby saving me two diodes.
Besides this, is there anything else that I am missing out? Will the voltage on capacitor remain same whether single or both phases are supplying power or will it differ?
EDIT:
After looking at the answers, I realize that if I use full bridge rectifiers as I shown in previous images, peak output on bulk capacitor will increase significantly depending upon the phase difference of the voltages. This increase will create difficulty due to these two reasons:
1) Higher voltage means a higher voltage rated capacitor
2) It might get difficult to find a flyback IC which operates at this high voltage.
3) Even if capacitor and IC are available, it might be costlier as compared to what I can use with a lower voltage which I get in 1 phase design.
As such, I can think of another option. Using half bridge rectifiers to rectify each phase and use Neutral line as my reference:
Since my output power requirement is less than 5 watts (1-2 watts typical), I feel that half bridge will work even when only a single phase is available. This also ensures that my bulk capacitor will not see a voltage higher than sqrt(2)*220 V = 311 V peak. In worst case where Vrms = 270V, it will give 382 V peak. Thus I don't need to modify my existing single phase power supply circuit after the bulk capacitor.
Am I right in thinking so? Is there any better way to do this?
AI: You're almost there, but not quite thinking about the problem enough in a generalized way.
If you have N leads with arbitrary AC voltage between them, then you need 2N diodes to make a full wave rectifier. Each lead is connected to one diode going to the positive DC output, and one diode coming from the negative DC output.
Note that your bottom circuit is like that, only that you've drawn it to make it not immediately obvious.
Here is a generalized full wave rectifier for N AC inputs:
You have 3 AC inputs. Your mental block seems to be thinking about the neutral line as special in that regard. It's no worse than just another AC input line, so you can make a full wave rectifier with 3 pairs of diodes.
Rectifying two of three AC phases and neutral is a odd thing to do, but is no special case for the general circuit above. Here is a plot of the voltages:
This example uses 120 V AC at 60 Hz and assumes ideal diodes.
The rectifier output is the greatest difference between any two AC inputs at any one instance. To make this easier to see, the max of all the AC inputs is shown in red, and the min in blue. The resulting difference is the green trace, which is the instantaneous output of the rectifier. This is the voltage the cap smoothes out, and is what you'd get if there was no cap and you put a small resistive load on the output.
Note that the green trace is NOT relative to the same reference as the AC inputs. It is showing the DC output when that is taken in isolation. The individual DC outputs with respect to the same reference as the AC voltages are the red and blue traces.
For contrast, here is what full 3 phase rectification looks like:
Note that this has much less ripple, and that ripple is at 6x of the AC frequency. Your two out of three phase rectification results in ripple at only 2x the AC frequency. |
H: Will placing a strong magnet near my electric skateboard Li-Ion Battery pack damage or discharge it?
The original clips securing my battery cover are broken and i thought of devising an alternate way to keep the cover shut involving a hard drive magnet and a hinge
the battery pack would sit in proximity (3-5 cm away) to the magnet while in use (1-2 hours/day), but I would remove it when the session ends.
Here's a rough plan. If you can make any sense of my drawing skills, the battery pack sits right under the cover. The hard drive magnet would be inside the battery case (dashed trait)
Before refining this idea I just wanna make sure this setup would not be harmful to my battery pack or other electronics (bluetooth remote receiver, ESC, ...).
What if I decide to switch to a LiPo battery pack later?
AI: As far as I know is there no direct harm to a lipo battery if you place a magnet next to it.
I have put magnets ofthen next to electronics to see what happens and never had some problems with that.
Also in the brushless motors you are going to use there are also fairly strong magnets inside of them, so don't worry.
I'm aware that this sin't a very scientific answer, but I'm not a lipo or ESC specialist.
I'm just an experienced electronics guy. But I'm 99.99% sure nothing bad will hapen if you do this. |
H: 74181 ALU not working properly cascaded to add 8 bit numbers
I'm trying to make a homebrew CPU but having problems with the 74LS181 ALU, which I'm simulating in Logisim software before diving into real ICs and breadboards.
I've cascaded two 74181 following instructions found in many sites such as this.
This works fine with most of addings I tried, but some don't work.
For example:
0010 0111 (39 in decimal)
+
0000 0001 (1)
leads to a 0010 0000 (32) result.
I know it should have something to do with the fact that 74181 uses signed numbers represented in two's complement. The least significant nibble in the example (0111) represents the max positive number with 4 bits, so when incremented by one goes to zero...
Is there any way to make 74181 work with only positive numbers? Or solve this issue in any other way.
I'm frustrated because with this problem the ALU is completelly usesless.
link for 74181 datasheet
link for project (has image of error on simulated ALU) - link on comment bellow
AI: All the answers helped me in finding the bug. Actually the error was in the implementation of 74181 ALU in Logisim, as I supposed. There are 3 file versions of the chip, but the right one is (strangelly) the v2 not the v3. I will put a comment on the author's page to warn others in the future.
Besides this the Carry output/input connection was inverted, should be from the ALU of Low nibble (4 least significant bits) to the High nibble. I made the opposite. My mistake.
Thanks everyone. |
H: Why are there two diodes in series in this test circuit?
Look at Figure 2 in the following datasheet:
http://www.onsemi.com/pub/Collateral/MMBT3904LT1-D.PDF
Why are there two diodes and not just one?
Thanks.
AI: The circuit includes two diodes to set the negative bias at the base during the turn-off phase of the measurement.
A single diode would only give about 0.7v reverse, two give twice that.
If they didn't have any diodes at all the voltage would exceed the reverse breakdown of the base-emitter junction that is in the region of 7v with silicon planar transistors.
I agree that it is somewhat unusual way to do the test rather than defining the voltage from the pulse generator. |
H: Maximum power transfer for unknown resistance
simulate this circuit – Schematic created using CircuitLab
Hi,
I am trying to find out what should be the value of resistor connected across node 'ab' for maximum power transfer. So far I have tried working out by hand and I don't think I have got the right values. I have shorted out voltage source to find thevenin resistance and considered R1 parallel with (R2+R3) and (R4+R5). Can anyone please help me to find out equivalent thevenin circuit.
AI: In order to find out Thevenize circuit, you want to do following things.
Temporary remove the load resistance(which is temoved here) whose current is required.
Find out the open circuit voltage Voc which appears across the 2 terminals from where resistance has been removed. It is called Thevenin voltage Ath.
Compute the Thevenin resistance, Rth of whole network as looked into from these 2 terminals(a and b) after all voltage sources have been removed leaving behind their internal resistances(if any) and current sources have been replaced by open circuit ie. infinite resistance.
Replace the entire network by a single Thevenin source, whose voltage is Vth or Voc and whose internal resistance is Rth or Ri.
Connect load resistance back to its terminals from where it was removed.
Finally calculate current flowing through load resistance Rl using equation,
I= Vth/(Rth+Rl) or
I= Voc/(Ri+Rl).
Maximum power transfer
According to maximum power transfer theorem, the maximum power Pmax=((V^2)/4Rl)=((V^2)/4Ri)
Or
We can simply say that when internal resistance of source,Ri= load resistance Rl, then the maximum power transfer happens...
According to me you want to put Thevenin's resistance, Rth across ab. Since the question is not providing information about internal resistance of V1, we can consider internal resistance zero while Thevenizing circuit (Some articles also saying we can make this consideration theoretically). But the system do not exists practically since there is no voltage source with zero internal resistance.
Sorry for typos. This answer may be false. Please critically think. |
H: Track vs sample-and-hold
This is the output of both track-and-hold and sample-and-hold.
But when I searched for its circuit I am getting the circuit I have shown below for both.
So my question is: if the circuit for sample-and-hold and track-and-hold are the same then how is the difference between the two getting reflected in the circuit? Is the control signal input different for both, and if it is, then how is it different?
AI: There is no difference. The two terms are used interchangeably:
Track-and-Hold
Track-and-hold, often called 'sample-and-hold,' refers to the input-sampling circuitry of an ADC. The most basic representation of a track-and-hold input is an analog switch and a capacitor. (See figure.) The circuit is in 'track' mode when the switch is closed. When the switch opens, the last instantaneous value of the input is held on the sampling capacitor, and the circuit is in 'hold' mode.
-- Maxim ADC Glossary
A capacitor takes time to charge or discharge to the level of the incoming signal. This time is the track time (aka the sample time). The amount of time taken depends to a large extent on both the size of the hold capacitor and the output impedance of the device you are sampling.
Note the word "ideal" in the description of your waveform a. Ideal never exists in the real world, so you have to add the "tracking" period to be able to sample the waveform.
That is why there is only one circuit shown for the input, because they are both the same thing. |
H: Should it be expected that some shielded wire is not good at data transmission?
I have recently purchased a reel of this specification screened wire from RS Components to use in I2C communications, expecting it to be very well suited to purpose. I am running at approximately 400 kHz clock on the wire and did not think for a second that the choice of cable might limit the speed I could run at. However on oscilloscope inspection, the bus signals are extremely dulled by the connection of a 3m length of this wire.
Is the problem with the I2C master not having a sufficient pullup resistor say, or is the wire genuinely at fault? Is there a significantly better wire specification I could use for this application?
Further Information:
It is true this wire is listed as 95pF/m. I have found a different spec of wire (for microphone use) that seems potentially impossible based on the physics discussed, but here it is, 55-105pF/km.
AI: Interestingly I was replacing some solid core ethernet cable I'd
hacked in to do the job, moving up to a wire type I assumed would be
far superior. Turned out it wasn't to my surprise.
Cable that has a characteristic impedance of 50 ohms tends to fall into the 100 pF per metre region and if you look at the formula for impedance above several hundreds of kHz it is approximately this: -
\$\sqrt{\dfrac{L}{C}}\$
This means that the inductance is about 250 nH per metre (with a touch of hand waving). For the impedance to double to 100 ohms, something has to give and clearly the ratio L/C has to increase 4 times. This usually (and again with a bit of hand waving) means L doubles and C halves.
I have dropped it from 400 kHz to 200 kHz as I can see the waveforms
are just about good enough to get the job done. It works for now.
This might easily be enough of a reason for things not to work at 400 kHz clock but become workable at 200 kHz. |
H: Electrical System Harmonics
I'm a mechanical engineer so I don't know much about electric circuits and power generation to begin with. Can somebody explain what a harmonic is in the power grid and what is the reason why it is bad? I understand it comes from non-linear electric loads but what does that mean?
AI: A particular reason why the electricity companies think harmonics are bad is that they have to supply them (which means a generally slightly thicker cable on average) AND they can't usually bill the user for them. There are exceptions of course (for higher energy users) and they are encouraged (by the cost of their bill) to keep harmonics low and power factor as close to unity as possible.
A harmonic is a term that nearly always applies to a non-linear load distorting the normally sineusoidal load current. Basically it's not a higher power consumption but it does mean the infrastructure has to be able to cope with the basic billable currents and the generally non-billable harmonics: - |
H: RLC voltage at resonance
I did a small simulation for a RLC circuit as here :
How does one compute the maximal voltage attained for this resonance?
AI: At resonance, the final voltage on the resistor is precisely what the input sinewave amplitude is. This is because inductive and capacitive reactances totally cancel to zero in an AC analysis.
This then tells you the current flowing through all series components so, use ohms law (for impedances) to calculate the voltage on L and C individually. At resonance they will be the same amplitude and, if their individual reactances are greater than the resistor, you will see that the voltages are larger than the incoming sinewave.
In an off-resonance scenario you calculate the net impedance of the capacitor and inductor (zero at resonance as previously mentioned) and use Pythagoras to determine the voltage across the resistor then proceed as above. |
H: How does the IC design process work?
Particularly for highly complex, digital ICs. Is it bottom up or top down? In particular, for top-down design designs the actual logic gates?
AI: Actual logic gates are designed at manufacturer's foundry. They design various gates and other logic elements within their node capabilities, "qualify" their gates, and offer several variants of libraries, for different grade of silicons, low-power, normal, high-performance, etc. So one can say this is "bottom-up".
A customer of a fab (a fabless IC company) designs top-down, from marketing specifications, down to desired functions, integrating various IPs (frequently acquired from big design houses as Synopsis), using an hierarchy of design languages (C#, System Verilog, down to Verilog and VHDL). Then they translate the RTL into offered libraries of a particular FAB.
I hope this answers the original OP question |
H: building a minimalistic rf circuit (as simple as possible just for OOK)
I have been recently interrested in rf transmission. I would like to create a small circuit to generate à 125kHz signal at about 10-15 meters. I am very newbie for these kind of things. When I look on the internet for some schematics they all seem very complicated. I would need to have a minimalistic circuitry to to just OOK (On Off Keying) in this frequency. What would be the minimalistic circuit (you could just point to some schematics) that I could use in practice, that would be operationnal?
AI: I'm going to answer the "minimalistic rf circuit" bit. As the comments note, 125kHz is a tall order. I'll assume that 433MHz, being unlicensed, practical and popular, will suffice.
A big caveat up front: RF is not simple! I'm assuming this is a learning exercise for you. In that case, carry on! If instead you just want to use rf, then just buy one of the many, many dirt cheap RF transmitter/receiver modules.
With that out of the way, here is the simplest RF transmitter circuit I know of:
simulate this circuit – Schematic created using CircuitLab
V2 is your OOK signal, V1 is your power supply (approx 5V), L1 is your antenna and the "SAW" component is a 1-Port SAW Resonator. The critical values are C2, C3 and L1 - the values I've provided are just starting points. They are highly unlikely to work for you! They depend a great deal on your layout, PCB materials and component variation. It will take some experimentation to get it right. Just make sure the series combination of C2, C3 and L1 resonate at the frequency you want (433Mhz is a good target).
L1 will be the most difficult to control - try a coil of wire whose dimensions you can adjust as you go. The rest of the components should be SMD and mounted close together. |
H: Antenna concept, is it a passive device but how about gain?
Cisco antenna explanation
Here it says that antenna is passive device which doesn't offer any added power to the signal. But at same time it says that antenna is responsible for increasing the amount of energy to a radio frequency (RF) signal.
So I don't get aren't they opposite things? How can it be a passive device and increase the amount of energy to a RF signal?
AI: An antenna is a passive device.
The gain of an antenna refers to its directivity times efficiency compared to an isotropic antenna.
An isotropic antenna is a theoretical antenna that radiates equally in all directions. If this antenna were encapsulated in the center of a sphere, it would illuminate all parts of the sphere equally and uniformly.
All other real world antennas do not illuminate a sphere equally. Some areas of the surface have more power than other areas. As a result of the antenna favoring some areas of the surface compared to others, the antenna is said to have gain when compared to an evenly illuminated sphere. The area or direction with the most power is considered to be the major lobe of the radiation.
While radiation has been used in this description, due to the theory of reciprocity, it applies equally to a receiving antenna.
You can also think of this in the context of a flashlight/torch bulb. If you illuminate the bulb without its reflector, it does not appear to be very bright. But if you now place a very narrow beam reflector behind it, you can shine it at someone's eyes with nearly blinding results. The energy emitted by the bulb has not changed, but to the observer it is as if the bulb is many times brighter. This is analogous to antenna gain. |
H: Combined series and parallel resistors -- adding resistors
Sorry for the poorly worded question, I wasn't sure how to make it clear
If I have a 100ohm resistor with two 100ohm resistors coming off of it (in parallel), is the total resistance 200ohms?
simulate this circuit – Schematic created using CircuitLab
AI: If R2 and R3 were in parallel, their combined resistance would be 50 ohms. This in series with the R1 100 ohm resistor would make a combined resistance of 150 ohms. But this is not what is happening.
R2 and R3 are each in series with an LED. These resistors, in combination with R1 are limiting the current through the LEDs. So the usual series/parallel resistor analysis is not applicable due to the presence of the LEDs. |
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