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H: The Conjugate Match
I've been deriving transmission line theory from scratch, out of curiosity, and I'm a bit hung up on one seemingly insignificant point.
When determining the real power drop on a reactive load with a reactive transmission line attached (and supplied by a voltage source), it is commonly accepted that the current amplitude in the loop should be multiplied by only the real part of the load impedance. This does not make sense to me. I think the current amplitude in the loop should be multiplied by the magnitude of the load impedance (r^2 + x^2)^(0.5).
What the hell is going on here!?
AI: This does not make sense to me
Go back to the time domain and see that, for the real part of the load impedance, power is always absorbed. The average power is, thus, non-zero.
However, for the imaginary (reactive) part of the impedance, power is alternately absorbed and then delivered (the power alternates from positive to negative). For the reactive part, the average power is, thus, zero. |
H: How to calculate the address fields for a cache?
I've a homework question about 32-bit cache memories:
For a cache memory that has size 16kB (16384 byte) and blocksize 2
words, state the names and the sizes of each field of the address that
comes from the CPU.
My answer is: 3 bits block offset since 2³=8 and 14 bits for the address tag since 2¹⁴=16384. The rest, 15 bits are for the index of the cache. Is my answer correct?
AI: Assuming that the memory is byte addressable, and words are 32 bits, then each cache line is 8 bytes wide, thus requiring a 3 bit byte address.
The next fields cannot be determined without assuming a cache organization, and so the homework problem is indeterminate.
The cache has 2048 lines, but how are they used?
If the cache is direct-mapped, then of the next 29 bits, 11 bits are an index into the cache, and the remaining 18 bits are address tag.
If the cache is fully associative, then all 29 bits are tag.
And everything in between: four-way set associative means there are 11 - 2 = 9 set index bits, and the tag is 18 + 2 = 20 bits. Each set associativity choice divides the 29 bits between tag and index. |
H: JTAG Design for altera cyclone 3
I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file (http://www.mediafire.com/?0gt55eyperbm385)
Or just a snapshot here:
Would you please having a look for me?
I have some doubts:
Should I connect nCE of JTAG directly in to nCE of the FPGA, or nCE from FPGA is connected to ground?
About the clock: I see that there are 16 clocks (clk0 t clk15). To which clock I should connect the output from oscillator to?
In my board, I only use 3.3V (the label VCC means 3.3V). Is that ok?
By the way, would you please showing me how to add a flashing LED to indicate the JTAG is working?
AI: Should I connect nCE of JTAG directly in to nCE of the FPGA, or nCE from FPGA is connected to ground?
I'm not sure what you mean by "nCE" of "JTAG", but the nCE pin of the FPGA should be tied low. It is only used in multi-device configuration scenarios, where you daisy chain devices by connecting nCEO of one device to nCE of the next.
About the clock: I see that there are 16 clocks (clk0 t clk15). To which clock I should connect the output from oscillator to?
It doesn't matter, choose whichever is easier for you to route.
In my board, I only use 3.3V (the label VCC means 3.3V). Is that ok?
I doubt it. Doesn't the device require 1.2V for core logic and 2.5V for PLL?
By the way, would you please showing me how to add a flashing LED to indicate the JTAG is working?
You can just connect a LED via resistor between 3.3V and TMS. The pin is driven by the programmer and will be low most of the time during the programming. |
H: IAR errors about extern and global vriables
I want to get values of a global array in a c file. the print screen of code is shown below:
'data' is the global array and 'slave_buffer_rx' is another global array defined in this file to get values of 'data'.each red cross has two errors:
Error[Pe094]: the size of an array must be greater than zero
Error[Pe028]: expression must have a constant value
I know how to get rid of errors: make assignments in a local function. the code without errors
is shown below:
But I do not known the exact reasons and how can IAR consider it as an array with zero length. Can anyone give me some ideas?
AI: There are a few problems, take the first line for example:
__IO uint8_t Slave_Buffer_Rx[0]=data[0];
This is trying to declare a zero length array and also assign a non-constant value to it. The first [0] is specifying the length of the array as zero. What you're attempting above is a static inialization so using data[0] doesn't make much sense at that point because during program initialization the pointer value won't be known.
Because you're using pointers and the values will be one and the same I don't see an immediate reason to use any different variables. If your ISR routine needs to write data to your global buffer you could use something like the following for example:
INTERRUPT_HANDLER(I2C_IRQHandler, 19)
{
data[0] = I2C_read();
data[1] = I2C_read();
data[2] = I2C_read();
}
If you really do need a seperate copy of the data (for example to modify without changing the main buffer) then what you've done in the second example is perfectly fine. You'll need to copy the contents of the buffer on each ISR call in case the data has changed between calls. |
H: 0V LDO Adjustable Regulator
I'm currently researching LDO adjustable regulators to make an adjustable supply that runs from 5V. I want my supply to be capable of supplying down to 0V.
I've found the LT3083, which can adjust down to 0V, however has a 310mV drop out voltage. I would prefer to have a smaller drop out voltage than this. Does anyone know of a similar regulator that meets my 0V requirement, but has a smaller drop out voltage? I am seeking a smaller drop out voltage so that my supply's upper range will be closer to 5V.
Thanks
AI: The LT3083 is a good device and your limitations on drop-out can be improved by considering the following: -
As can be seen, the drop-out at 3A load is just a bit over 300mV but at 1.5A it is about 170mV. Given that devices can be paralleled (diagram on right), maybe you should reconsider this device. Also note the larger words at the bottom - to truly get down to 0V you will need to generate a small negative voltage that is still "removing" 1mA from the device. |
H: IGBT vs. Power MOSFET for switching applications. Where to draw the line?
For lower breakdown voltages, a power MOSFET is clearly the device to go for, in view of its higher efficiency, higher commutation speed and lower price.
Where should the line be drawn, upwards of which IGBTs take over as the preferable solution? What are the relevant decision criteria?
AI: The main criteria in choosing either IGBT or MOSFET are voltage rating, power losses (efficiency of the whole system) and of course the cost of the whole system. Choosing one over other may impact not only losses in the transistors but also the weight and cost of cooling, size of the complete product and also reliability so sometimes e.g. a weight constrain may force you to use MOSFET instead of IGBT.
If you look at this graph, you will see different areas, where each type of switch are typically used:
Choosing a particular device type depends on specific application and its requirements.
MOSFETs dominate in high frequency and low current applications because they can switch extremely fast and act as resistance when on.
Fast switching means they are used when the device has to be small as when you increase switching frequency you can reduce the size of passive filters.
The conduction losses are proportional to the square of drain current and therefore you cannot pass huge current through the structure.
They also have limited breakdown voltage and are typically used up to 600V.
IGBTs have higher breakdown voltage and conduction losses are approximately equal to Vf*Ic therefore you can use them in high current applications. They have limited switching speed therefore they are typically used in industrial applications where low switching frequency is not a problem (acoustical noise). |
H: Damped Oscillations Start with a Delay
I feel like a total newb here, because I've built resonant tank circuits plenty of times before, but somehow I'm stumped on this one. I've run into a bizarre problem I can't figure out.
See scope shot:
The top channel is my signal to the gate of a mosfet. The mosfet is driving a tank circuit that contains a large coil wrapped on ferrite with a 5uF capacitor. The coil is large enough that the frequency is near 100Hz.
The bottom channel shows the positive side of the tank capacitor where the mosfet source is connected to drive the circuit. What I'm confused as heck about is the low voltage delay after the input turns off and before the initial oscillation begins. I don't recall ever running into something like this before. I've traced my circuit leads and double checked everything and I just don't know what's going on. Anyone else ever seen something like this in a tank circuit?
Ok here's a circuit diagram. I should have posted before, but I doubt this is going to help:
AI: Since you didn't post a circuit diagram, most of what follows is speculation, but your waveform is very similar to what you see in any switching regulator that's operating in discontinuous mode.
When you turn on your MOSFET, you are "charging" the coil with a certain amount of current. At the moment when you turn off the MOSFET, this current still needs to flow. Since the current can't flow through the (smallish) capacitor, it is forced to flow through the "body" diode of the MOSFET (or some other diode you have in the circuit?), at least until it drops to a value that allows the voltage of that node to rise above zero volts. At that point, the diode stops conducting. Now the MOSFET is truly "open circuit" and you see the oscillations you expect.
OK, now that you've posted a diagram, I can see what's going on. When the gate signal goes high, this enables current to flow through the MOSFET, because the source is essentially tied to ground through the diode and the coil. Current builds up in the coil as described above, because it has a positive bias across it. When the gate signal goes low, the inductance of the coil pulls the source terminal low enough (a negative voltage) so that the MOSFET is still on, but now the magnitude of the current is decreasing instead of increasing, because the coil now has a negative bias across it. Once the current decays sufficiently to allow the MOSFET to cut off, the remaining residual current drives the oscillation you see in the latter part of each cycle. |
H: Surface Mount vs. PTH Components For Production
I'm a hobbyist who has developed a product which uses ~20 PTH components. The device is essentially an Arduino UNO with some extra driver ICs and LEDs. I have had quite a lot of positive feedback on the product and am considering re-designing it so that I can put it into production.
I was wondering what technology was best for automated/volume production? I've noticed that several companies use both surface mount and PTH components on their boards, Arduino being an example. How do the board designers make a decision on what technology to use? Size isn't really an issue for this product, the existing board using PTH components is a quarter of the size of it's container.
AI: I'd recommend you check out the excellent EEVblog tutorial videos part one and part two covering PCB design for manufacturing. You'll not only find the answers to your component selection questions above, you'll get a ton of suggestions and advice about a half-dozen other critical issues you might not have thought of yet.
They're a long stream at about an hour apiece, but totally worth it! |
H: Creating an LED array light box
I'm wanting to make a light box of sorts from LEDs and wanted to run it by you to confirm I have the right idea...
I have ordered 500 super bright LEDs off eBay and want to wire loads of them together. The forward voltage on the specs says 3V and my supply voltage is 12V (max 2A). I want to provide 20mA of current to the LEDs for a nice brightness.
I have calculated that if I wire 3 LEDs in series with a 150 Ohm resistor, I will get the desired 20mA of current. Is this correct?
Resistor = (12V - (3*3V)) = 3/0.02A = 150 Ohm
Now I have 3 LEDs using 20mA of current, can this be up-scaled to the full 2A power by simply duplicating the circuit as shown in the picture? So in theory I could run 300 LEDs from the power?
One last thing, If the LED's forward voltage is 3V, does that mean I can used 4 in series without a resistor with a 12V supply?
Thanks
IMAGE IS SUPPOSED TO SAY 12V NOT 5V - I've been working with Arduino for the last while
AI: You might find, that at 20mA, the LED forward voltage is slightly less than 3V and will increase the current a bit so go for a slightly higher value resistor with 3 LEDs.
Upscaling to several strings of LEDs should not be a problem.
You can't put 4 in series because there is nothing to limit the current thru them and, if all four were dropping 2.9V at 20mA, you'd be applying 12V across something that expects 11.6V and this may take a lot more current than 20mA. |
H: Using on and off switches and logic gates
So I have 2 switches Representing:
Bit A
Bit B
And then I have :
AND gate
OR gate
Not gate
Some other gates like adder and comparator
I used the method described here because the Adder & comparator gates always get the input as 1 however the switch is on or off here. Which is connecting the switch between input to gates and the ground , connect the led between the vcc and the output from gates and it works fine for those 2 gates.
But 3 probems occur now :
For the AND gate nearly work as an OR gate:
- When the 2 switches off: the led is nearly off though I can still see very
very low illumination
- When either switch is on: led illuminate with full power
For the NOT gate the output is weak and it kinda go and come (like the LED is vibrating but with light effect)
For the OR gate inputs are always seen as 1
-when switches are closed: lead illuminate nearly with third of its potential
- when both are opened: led illuminate with full power.
So is there a way to use those switches correctly ?! I know it is wrong with the switches connection as when i try the input with either with Vcc for 1 or Ground for 0, they work just fine.
AI: It sounds to me that when a switch is open, you have a floating logic input. Logic chips, in general, do not like to have floating inputs and this can produce results like you see (gates half-way on).
Try adding pull-down resistors to your inputs, for example 4.7K between the input and ground. This guarantees that an input always sees a valid logic state. |
H: What is the metal sheath surrounding a USB connector, and is it commonly connected?
I was tearing apart a mouse for repairs and noticed that the small plug for the USB connection had a fifth connection. This connection had a much thicker wire than the other four.
I assume it is connected to the metal sheath on the male end of the connector, but what does it actually do?
AI: It's a shielding ground, usually made of copper braid. It stops stray signals from leaking in or out of the cable.
It should usually be connected at at least one end. I've seen conflicting advice over exactly how it should be connected to minimise noise and avoid ground loops. |
H: Transistor Toggle Not Working
I'm trying to learn about how transistors work. As a simple test I created the following circuit:
My idea is that when the second transistor will keep the first one active after I click the button for the first time, but it isn't. What am I doing wrong?
AI: What you are trying to create is a thyristor and it is slightly different.
simulate this circuit – Schematic created using CircuitLab
To sustain a transistor on you need current through the gate, in this design the two transistors are feeding output through each other. |
H: Splitting a power supply between two circuits
I have two separate circuit boards (clock & radio) that I'd like to place within the same enclosure. One takes 12V, and the other needs 3V. How can I utilize one AC adapter to power both boards appropriately?
AI: Use a 12V DC output AC Adapter to power the 12V module directly. You will then need a voltage regulator or DC to DC converter to reduce the 12V down to the 3V required for your other module. If the current requirement for the 3V module is low you could build a linear regulator out of an LM317, two resistors, two capacitors and a heatsink.
If your current requirement is more than a small number of mA the LM317 style design will get very hot and so a switching type DC-DC converter module would be required. You can find these for sale on eBay. Building your own switching regulator requires a certain amount of experience with such designs. Here is a sample type thing from eBay that could suit your needs.
(image from above linked eBay auction page)
Here is a diagram of how the power lines from the 12V wall adapter would connect into your two modules. |
H: Adjustable clock in HDL
I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). I came up with a solution which uses a counter and a comparator, the output of the comparator being the new clock but this idea creates a very ugly clock (spike) and I was wondering if there is a better solution to this.
On some fpgas (stratix) it is possible to use a reconfigurable pll but this doesn't apply to cyclone II unfortunately.
Thanks for your help
edit: Input clock 24 Mhz. Output clock 1khz - 10Mhz, clock is used for transceiver and receiver blocks, which are simply sending bytes between each other.
AI: If you can tolerate 42 ns of peak-to-peak jitter (the period of your 24 MHz clock) in your synthesized clock, a direct-digital-synthesis (DDS) approach would probably be viable. This simply requires an accumulator register and an adder of the same width. The MSB of the accumulator becomes your synthesized clock.
You didn't say how much frequency resolution you need. To generate a 1 kHz output would require at least 15 bits in your accumulator; this would allow you to generate any frequency that's a multiple of 24 MHz / 215 = 732.42 Hz. If you add more bits, you can get finer resolution. If you want ~1 Hz resolution, you'll need 25 bits, which would give you steps of 0.715 Hz.
For any particular DDS design, the number of bits in the frequency-setting value is the same as the number of bits in the adder and the accumulator. To change the frequency, even on the fly, just requires changing that value (but not its width). |
H: Easy resource to learn solving counter problems?
Could anybody please point me some direction on where I can learn to solve simple counter problems like counting in a given sequence using a given flip-flop? For example:
Create a counter counting in a sequence 3-1-4-7-2 and again from the
beginning using the D-type flip-flops
I'm not asking for help in this particular problem - rather, it'd be great to know how to solve this class of problems. I know how to design counters in a series to count from n to n+k or the reverse but how to do this thing?
AI: Think of your special counter as a state machine. Then assign the state the coded value of the count sequence that you want. In this case the states would be as following with the next state showing.
State Next State
3 -> 1
1 -> 4
4 -> 7
7 -> 2
2 -> 3
Each state can be encoded into three binary bits so your design will require three D type flipflops. You need to make up a set of three karnough maps, one for each flipflop that, shows the next bit value for the flop flop (D input) based upon the three current state (Q outputs).
Use the k-maps to simplify the logic down to the minimal required. Finally you can code the minimal logic up in a series of AND gates driving OR gates into each FF D-input.
Here I show the k-map for the lowest ordered bit of the "counter" to get you started with the idea. |
H: How do I buffer a high Frequency clock on a Spartan 6?
I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to generate a higher speed clock.
Things work fine as long as my clock frequencies are below 400MHz. If I try to run the output clocks any faster, I see the warning -
"CLK_OUT1 frequency requires that this output clock must drive a BUFFPLL"
The datasheet of the clocking wizard states that
If a clock output requires special buffers like BUFPLL which the wizard does
not generate in the design, alert messages are flagged to the user. Feedback for the
primitive can be user-controlled or left to the wizard to automatically connect. If automatic
feedback is selected, the feedback path is matched to timing for CLK_OUT1.
The Spartan 6 clocking guide mentions BUFPLL as a primitive. I have never done any such designs. How do I proceed. How do I create a BUFPLL in my design? Is this simply beyond the capability of a Spartan 6 or my board?
AI: I haven't used Spartan6 specifically, but you should be able to instantiate a BUFPLL (page 52) primitive and feed the output of whatever is generated by the wizard into that.
Page 80 of Xilinx Spartan-6 Libraries Guide for HDL Designs will have the info you need on instantiation. |
H: RC circuit and tone
Can I generate a tone on an 8-ohm speaker using a 5VDC power source, resistor and capacitor? For example if I want to generate a 440 Hz tone, could I use resistor capacitor values such that RC = 1/440?
EDIT: power source
AI: Everything has some resonance, so certainly you might be able to wrangle a capacitor value that, with the inductance in the rest of the circuit (chiefly to be found in your speaker), you could hit a given frequency.
But the problem here is, you have nothing to excite that resonance into action. If you fully charged the capacitor and slapped it onto the speaker, you'd get nothing more than a damped oscillation. And by damped, we're not talking about anything you could experience. Odds are it would all be over in microseconds.
The usual way to 'generate a tone' is to use an amplifier (read: more parts) to sample that natural oscillation, take power from your DC supply and provide gain, and then feed the amplified signal back to the resonant section in order to sustain the oscillation.
Short answer: no. |
H: Does anyone remember this article about the Euclidean Algorithm?
In the 70's I had a stack of old Amateur Radio magazines (50s-60s), and for a long time I saved an article about using the Euclidian Algorithm to combine a number of resistors to achieve a specific value. Does anyone recall and have a copy of this article, or know how the Euclidean algorithm is applied to solve this problem?
AI: It's actually based on the theory of continued fractions, which is closely related to Euclid's method for finding the GCD between two numbers.
Here's an example: Suppose you have a bunch of 10K precision resistors, and you need a resistance value of 27K for your project. You need some combination of the 10K resistors in series and/or parallel to produce that resistance.
Start by writing the ratio of the two resistances:
27K / 10K = 2.7
This means you need two resistors in series with some combination that gives 0.7 of a resistor.
Using the concept of continued fractions, you can rewrite the number 2.7 as 2 + 1/1.42857. Furthermore, you can break up the number 1.42587 into 1 + 1/2.3333.
Now, if you look at the first fraction again, it can be written as
$$\frac{1}{1.42857} = \frac{1}{\frac{1}{1}+\frac{1}{2.3333}}$$
Note that this happens to be the expression for two resistors in parallel; in this case, one resistor in parallel with 2.3333 resistors.
How do you come up with 2.333 resistors? You could iterate through the algorithm again, but it should be obvious by inspection that you need two resistors in series with the parallel combination of three more resistors.
The final network ends up looking like this, and it has a resistance of exactly 27K.
simulate this circuit – Schematic created using CircuitLab
Obviously, not all examples will work out this nicely. In general, you have to decide when to stop iterating based on when the precision of the network you have so far is "close enough".
The generalized form of the algorithm goes like this: Determine the ratio X = Rdesired / Ravailable. Write X as a continued fraction, where A, B, C, D, E, etc. are all integers:
$$X = A + \frac{1}{B + \frac{1}{C + \frac{1}{D + \frac{1}{E + \frac{1}{...}}}}}$$
Build your network with
A resistors in series with ...
B resistors in parallel with ...
C resistors in series with ...
D resistors in parallel with ...
E resistors in series with ...
... and so on, until you either get a sub-expression that has no fractional part, or you get "close enough" to the desired result.
Note that if X is less than one to begin with, then A will be zero, which simply means that you're starting out with a parallel combination of resistors and proceeding from there. Note also that as long as X is a rational number, the sequence of continued fractions will be finite. |
H: What is the difference between a PLL and a DLL?
Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what applications they might be used, the comparison between the two circuits and why one should be used vs. the other.
AI: A PLL controls a voltage-controlled oscillator in order to bring its frequency (or some derivative of it) into phase (and frequency) lock with a reference signal.
PLLs have many applications, from creating a "clean" replica of a noisy reference signal (with amplitude and phase variations removed), to creating new frequencies through multiplication and division, to demodulating phase- and frequency-modulated communications signals. The input-to-output transfer characteristics of a PLL can be controlled through the design of its feedback network.
A DLL controls a voltage-controlled delay line, which typically has many taps, in order to bring one of those taps into phase alignment with a reference signal. The input to the delay line is usually also the reference signal, so the various taps provide additional signals that are interpolated and/or extrapolated from the period of the reference signal.
DLLs are commonly used in high-speed communications among chips on a board (e.g., between a memory controller and its SDRAM chips) in order to "cancel out" things like input and output buffer delays as well as wiring delays, allowing very tight control over setup and hold times relative to the clock signal. This allows data rates to be much higher than would otherwise be possible.
With suitably-designed phase detectors, both PLLs and DLLs can work with nonperiodic reference signals; a common application involves aligning data signal transitions with a reference clock.
While the mentioned above (i.e. clean version of signal -> PLL) a key aspect of where PLLs/DLLs differ is that PLL's filter and effectively block jitter in the source from affecting the VCO output, whereas DLL's propagate jitter. At first this may appear to be a negative aspect of DLL's but it can be used to great effect. In some cases you need to pull the main sampling point from the signal that is arriving and ignore the jitter in the signal, you would use a PLL. In other cases, say when a signal and clock signal are subjected to the same jitter inducing effects either at the source or in the communications channel. You can use a DLL and multiple sampling delay times to reduce/eliminate the relative jitter between the two signals (because they have the very similar jitter) and use the delayed clock to align to an ultimate sampling point. |
H: Continous rotary input?
I need something to work as an input for a rotary device. It must be able to rotate continously, accurate to a degree of rotation, and so that any extra full rotation will have no effect on the input, a+360 is the same as a. With no limit of rotations as well.
So I have found no potentiometer that does that. And rotary encoders never have so many levels. I thought about doing it mechanically, and the using something kind of pressure potentiometer like this one https://www.sparkfun.com/products/8678 to transmit any rotation of my mechanical device to the surface of the potentiometer. This is the best I could come with, but if I could find something better, and specially less expensive, it would be great. Is there any standard device to do this?
Thanks in advance.
EDIT: Ok, so found, thank you to the answers, the rotary encoders that seem to be what I'm looking for. My doubt is: what I will be using as the input is the global position of the encoder, the degrees to which it's rotated, and not how it's being rotated, left or right, which is what the incremental that I've seen do. Are there any more types of these things? Or does an incremental one tell you how much it's rotating?
AI: I am surprised that you cannot find a rotary encoder good to one degree, but I do not know a whole lot about them. A 10 to 1 gear train can improve the resolution by a factor of 10. Or a stepper motor can be used as a rotary encoder with 360/(steps per rotation) accuracy. A 1.8 degree stepper is almost there. |
H: Programming ATMega48 with Arduino Uno
I'm trying to build a circuit that uses an ATMega48 PDIP-style chip and an ATTiny26. I'm stuck on loading code onto the ATMega48 using an Arduino Uno.
I've been following these instructions. I got all the way to step 4 when I got this error:
>avrdude -P COM3 -b 19200 -c avrisp -p m48 -n
[...]
avrdude: Device signature = 0x1e920a
avrdude: Expected signature for ATMEGA48 is 1E 92 05
Double-check chip, or use -F to override this check.
[...]
I did the easy thing and added the -F option, and everything seemed to work out. Then I added the hexfile (following the format specified in the guide) and got this:
>avrdude -P COM3 -b 19200 -c avrisp -p m328p -u -U flash:
w:"[...]\build2681525234531849420.tmp\Blink.cpp.hex":i -F
avrdude: AVR device initialized and ready to accept instructions
Reading | ################################################## | 100% 0.07s
avrdude: Device signature = 0x1e920a
avrdude: Expected signature for ATMEGA328P is 1E 95 0F
avrdude: NOTE: FLASH memory has been specified, an erase cycle will be performed
To disable this feature, specify the -D option.
avrdude: erasing chip
avrdude: reading input file "[...]\build2681525234531849420.tmp\Blink.cpp.hex"
avrdude: writing flash (1084 bytes):
Writing | ################################################## | 100% 1.34s
avrdude: 1084 bytes of flash written
avrdude: verifying flash memory against [...]\build2681525234531849420.tmp\Blink.cpp.hex:
avrdude: load data flash data from input file [...]\build2681525234531849420.tmp\Blink.cpp.hex:
avrdude: input file [...]\build2681525234531849420.tmp\Blink.cpp.hex contains 1084 bytes
avrdude: reading on-chip flash data:
Reading | ################################################## | 100% 0.98s
avrdude: verifying ...
avrdude: verification error, first mismatch at byte 0x0002
0x61 != 0x01
avrdude: verification error; content mismatch
avrdude done. Thank you.
How do I go about fixing this?
For the record, I'm using the "minimal" configuration specified here:
Arduino -> Mega48
10 -> 1
11 -> 17
12 -> 18
13 -> 19
AI: You have an ATmega48p, judging from the signature, so use -p m48p to get rid of the signature error.
I don’t know whether that alone will fix things, but the ATmega328 has a different flash page size and doubtlessly other differences from the mega48, so ignoring the signature was unlikely to work (I think -F for anything but diagnostic purposes is a bad move). |
H: How was the first programmable microchip made
Microchips have to be programmed to function. But if programmers (computers) are needed to program it, and they use microchips, how was the first one made?
AI: The first microchips were designed to fetch their code from an external memory chip, whether that be RAM, ROM, EPROM, core memory or a few other exotic technologies. The computers used in the day were made out of 100's of not 1000's of simple logic chips such as gates, latches, multiplexers, registers, buffers, counters and bus driver chips. These computers were leveraged with cross assemblers and compilers that could used to produce the target machine code for the first microchip computers. As microchips became more powerful a natural progression of bootstrap type activities allowed systems built around these computer chips to host much of their own development software - and of course support for the tools of the next following microchip technology. A process that continues on even today as technology keeps marching forward. |
H: Why does CPLD has four clock sources?
Altera CPLD EPM570 series have four global clocks(GCLK0-GCLK3)，I want to assign two clock sources to CPLD: one from oscillator and one from a MCU. From "GLOBAL SIGNAL" part of "MAX II Architecture"MAX II Architecture, i get confused.the structure is shown below:
why does CPLD have four clock output? I think it should only have one output connecting one of four global clocks. Does it mean that four clock output will serve different logicals? and is it safe to assign different clock sources to different GCLKx?
AI: Multiple clocks are often needed because several parts of the CPLD (or FPGA for that matter) will be programmed with separate functionality that operates asynchronously from other parts using separated clock domains.
Other times some clocks will be generated from an external clock source using one of the specialty clock generator chips that created different clocks that have defined phase relationships. These can be leveraged in different parts of the CPLD/FPGA in a way to optimize the operational behavior of the chip programming.
It is perfectly safe to have different parts of the CPLD / FPGA using different clocks. Your challenge as the designer is to use extreme care to keep each circuit confined to its own clock domain. And if it turns out to be necessary for some logic to make a crossing from one clock domain to another that you apply the necessary design rigor to apply the necessary clock synchronization circuits to the crossing paths to ensure that the resulting logic is stable and not subject to metastability problems. |
H: Driving a laser module from 5V supply
I've got a cheapo 5mW red laser module (datasheet), it looks like its got an internal regulator, probably a thermal cutoff too. I've been having problems driving it.
First thing I tried is I connected it to 5V via a resistor of varying value, (1k down to something like 200r) and the results are plain weird.
The module starts to lase at about 470r, but would be very erratic and would go off at some point. Driving it with a 200r i get a bright enough spot, but the current measures between 17mA and 21mA, voltage across the laser is 2.7v, but after a while it just cuts off like its been blown. The resistance of the laser module drops to couple of Ohms, regardless of polarity. Leaving it to "cool down" also does nothing.
Fooling around I then just tapped it on the 5V rail with no resistor, and it blinked with bright light, and started working with 470r and 200r resistors again.
Am I hitting some sort of a thermal cutoff or does the module need that minimum current/voltage to just lase, and could probably take higher voltage/current combination?
I'd like to drive it so its at its brightest point, within its rated spec.
AI: You linked to the datasheet, but apparently didn't read it. It's not very good, but enough basic information is there. The typical operating point is 3.0 V at 25 mA. If you are using a 5 V supply with a resistor, then the resistor will drop 2 V. 2V / 25mA = 80Ω. How you came up with 1 kΩ, 470 Ω, and 200 Ω as series resistors is completely beyond me.
Directly connecting this laser to a 5 V supply is a really bad idea. The datasheet only lists the typical voltage, which is 3.0 V. It does show the typical current as 25 mA and the maximum as 35 mA. How is directly connecting this thing to a 5 V supply going to ensure 35 mA is not exceeded? You may have damaged the device, even if it appears to operate.
Try the common value of 82 Ω in series with the 5 V supply and measure the voltage accross the module. It should be about 3 V. To not exceed 35 mA, the voltage accross the resistor must not exceed 35mA * 82Ω = 2.87 V, which also means the voltage accross the module when powered thru this resistor and a 5 V supply should be at least 2.13 V. |
H: Redefining Slave-Reset-Pin in MegaISP on ATmega2560
I want to make a Arduino ISP-Shield universal exchangeable between Arduino models. For this purpose I want to use the ISP-Header in combination with Pin 10 (like the Arduino Ethernet-Shield does). The reason for this is the different pin out on UNO, Leonardo and Mega boards.
At the moment I'm breadboarding to test using pin 10 on ATmega2560 as Slave-Reset. On the Mega I put the default ISP-Sketch (you can found it on GitHub) and changing the following line:
#define RESET SS
(which is PB0 broken out on PIN 53 of ArduinoMega2560) to
#define RESET 10
(PB4 of the ATmega2560)
With this change the board could later use the same layout for UNO and Mega Arduinos.
The RESET constant is used for "slave-select" which, in my knowledge does not need to be on any special pin as the other pins that should use hardware SPI pins. But when changing to pin 10 it does not work. It's driving me crazy. Here's the avrdude verbose output:
Binary sketch size: 826 bytes (of a 8,192 byte maximum)
/Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr/bin/avrdude -C/Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr/etc/avrdude.conf -v -v -v -v -pattiny85 -cstk500v1 -P/dev/tty.usbmodemfa131 -b19200 -Uflash:w:/var/folders/yp/trpfnkdn75zfzpl33tyw0tpm0000gn/T/build385603139236268699.tmp/Blink.cpp.hex:i
avrdude: Version 5.11, compiled on Sep 2 2011 at 18:52:52
Copyright (c) 2000-2005 Brian Dean, http://www.bdmicro.com/
Copyright (c) 2007-2009 Joerg Wunsch
System wide configuration file is "/Applications/Arduino.app/Contents/Resources/Java/hardware/tools/avr/etc/avrdude.conf"
User configuration file is "/Users/mose/.avrduderc"
User configuration file does not exist or is not a regular file, skipping
Using Port : /dev/tty.usbmodemfa131
Using Programmer : stk500v1
Overriding Baud Rate : 19200
avrdude: Send: 0 [30] [20]
avrdude: Send: 0 [30] [20]
avrdude: Send: 0 [30] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [10]
AVR Part : ATtiny85
Chip Erase delay : 4500 us
PAGEL : P00
BS2 : P00
RESET disposition : possible i/o
RETRY pulse : SCK
serial program mode : yes
parallel program mode : yes
Timeout : 200
StabDelay : 100
CmdexeDelay : 25
SyncLoops : 32
ByteDelay : 0
PollIndex : 3
PollValue : 0x53
Memory Detail :
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
eeprom 65 6 4 0 no 512 4 0 4000 4500 0xff 0xff
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
flash 65 6 32 0 yes 8192 64 128 4500 4500 0xff 0xff
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
signature 0 0 0 0 no 3 0 0 0 0 0x00 0x00
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
lock 0 0 0 0 no 1 0 0 9000 9000 0x00 0x00
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
lfuse 0 0 0 0 no 1 0 0 9000 9000 0x00 0x00
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
hfuse 0 0 0 0 no 1 0 0 9000 9000 0x00 0x00
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
efuse 0 0 0 0 no 1 0 0 9000 9000 0x00 0x00
Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
calibration 0 0 0 0 no 2 0 0 0 0 0x00 0x00
Programmer Type : STK500
Description : Atmel STK500 Version 1.x firmware
avrdude: Send: A [41] . [80] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [02]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [81] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [01]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [82] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [12]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [98] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [00]
avrdude: Recv: . [10]
Hardware Version: 2
Firmware Version: 1.18
Topcard : Unknown
avrdude: Send: A [41] . [84] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [00]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [85] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [00]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [86] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [00]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [87] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [00]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [89] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [00]
avrdude: Recv: . [10]
Vtarget : 0.0 V
Varef : 0.0 V
Oscillator : Off
SCK period : 0.1 us
avrdude: Send: A [41] . [81] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [01]
avrdude: Recv: . [10]
avrdude: Send: A [41] . [82] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [12]
avrdude: Recv: . [10]
avrdude: Send: B [42] . [14] . [00] . [00] . [01] . [01] . [01] . [01] . [03] . [ff] . [ff] . [ff] . [ff] . [00] @ [40] . [02] . [00] . [00] . [00] [20] . [00] [20]
avrdude: Recv: . [14]
avrdude: Recv: . [10]
avrdude: please define PAGEL and BS2 signals in the configuration file for part ATtiny85
avrdude: Send: P [50] [20]
avrdude: ser_recv(): programmer is not responding
avrdude: stk500_recv(): programmer is not responding
To check my wiring, I tried using the default pin 53 instead of 10 and with this simple change everything works just fine. What is wrong here? How do I get it working with pin 10? I even tried using another Mega2560 board with the same results :-(
It's clear to me that the program stops at the point where it avrdude tells to start program mode and call start_pmode();. In void start_pmode() the constant RESET is used, but I can not see anything wrong there...
AI: I’m pretty sure you CAN use a different output pin as as the slave select, but you have to take care of the original SS pin to avoid becoming accidentally enslaved yourself. Either set pin 53 as an output, or pull it high.
See section 21.1.2 in the 2560 data sheet for details.
By adding
pinMode(53,OUTPUT);
in void setup() it should work. |
H: what is the effect of a current-carrying wire through a solenoid?
The solenoid coil concentrates the magnetic field lines through the interior when the solenoid wire carries a current.
I am curious about a different case, however. If a (separate) straight wire went through the center of an unpowered solenoid coil, and this wire carried current, what would the induced effect be on the solenoid coil (say the solenoid is either grounded or left open)? Would any induced effect fight the current on the wire through the center?
AI: No, a wire fed axially through the centreline of a solenoid would not induce anything into the solenoid coil. The magnetic fields (if both are energized) will be at right angles. There would be no transformer action.
At much higher frequencies there will be circulating eddy currents induced in the solenoid winding (from the straight wire) but these won't be significant below tens or hundreds of kHz |
H: Current sense magnetics with critical/boundary conduction PFC chips
I was thinking of using a critical/boundary conduction PFC controller in a boost PFC.
I'm not sure how convenient it is to find an inductor with an auxiliary winding.
I can find lots of choke type inductors in the inductance and current range I need. I do not know much about chokes. Is it feasible to use 1 winding of a choke as my inductor, and the other as a current sense winding?
If I use a choke or inductor without an aux winding, have I removed the opportunity for designing a critical/boundary conduction PFC?
AI: Most of the BCM controllers out there expect a voltage input from the supplemental PFC choke winding to tell it when to start the next cycle. You could somewhat reproduce this signal with a current transformer between the inductor and the boost diode. Rectify the secondary side signal and apply it to the control pin, and see what happens.
That being said, you probably should consider spinning your own magnetics for this powertrain. That way you know exactly what you're getting and won't end up paying extra for some feature or capability you don't need. The design process is fairly straightforward as well, especially if you design with distributed-gap toroidal inductor cores (just add turns!) |
H: Measuring transistor beta (hFE) - Ib anomalies explanation needed
I've been struggling with details of building accurate (\$\pm1\%\$ tolerance maximum) beta meter. The simplest idea I came with went to a diagram as shown below, with R set to a value providing a \$0.01\ \mathrm{mA}\$ current and a digital ICL7107 meter put to measure \$I_C\$. Obviously, with \$I_B\$ set to a constant value, \$I_C\$ could be easily transposed as a beta meter...
BUT
After building this simple circuit in a simulator, I've noticed that the actual \$I_B\$ shifts a little bit as a function of given beta, with about \$10\%\$ difference between \$\beta \rightarrow 0\$ and \$\beta \rightarrow \infty\$; I provided actual test case betas below (\$\beta=10\$ for a low-current transistor and \$\beta=1\mathrm{M}\$ for a high-current Darlington pair, the difference below goes to approximately \${}8\%\$). Of course, I could say this shift is small enough to be ignored - sadly, it's not (at least not in my case).
What is the source of this difference?
Do actual transistors behave similarly (possibly with recalling actual test results)?
And yes, I'm coming to a conclusion that in this case \$V_{CC}+R\$ can't be treated as a stable base current source. And I'm aware that \$V_{drop}\$ on \$R\$ changes with \$\beta\$, and that \$V_{BE} \mathbin{/} V_{BC}\$ distribution changes as well... but I don't understand how this affects \$I_B\$.
The circuit simulator I used.
AI: If I understand the data provided by Danny & Kaz correctly, the strict beta measurement by simple current/voltage measurement is neither possible nor sensible due to changes in operating conditions (thermal emissions etc), reverse current gain and other variables related to specific transistors. Ib itself is varied based on the Vbe/Vbc voltages and although the coefficient of change is low, higher precision is not actually possible by simple, one-point measurement.
To sum up, I'll stick with approximations and up the error tolerance by one order of magnitude, to +-10%, leaving a simple bias with known Vcc/R values as a base of beta calculation.
By the way, it seems that increasing Vcc actually makes Ib(beta) more constant. With Vcc in orders of tens of V, Ib ~ const. The actual drift occurs heavily on low (<5V) voltages though, at least in the sim; I suppose that thermal emission on higher voltages would cancel this const-ness though. |
H: What is this relay symbol?
I have never seen a relay depicted as below:
from here (pdf)
Can someone explain what is going on for terminals 6, 7, and 8?
AI: Terminal 7 is the common point between a normally closed contact (terminal 6) and a normally open contact (terminal 8).
When the device is not powered, terminals 6 and 7 are connected. When the device activates terminals 6 and 7 open and terminals 7 and 8 close. |
H: How to wire a Normally Open Button to a BeagleBone Black?
This one should be simple, but I'm fairly new to this.
The button has a COM and an NO terminal. Beaglebone pins can only take 6mA, so I don't have much room for error. My question is, how do I wire this and does it need voltage?
More information:
This button only has NO, COM. It doesn't have NC.
Here is the button.
http://www.adafruit.com/products/1185#Technical%20Details
There isn't any technical info listed that seems helpful.
Here are the pins:
AI: Your button can be a pull-up or pull-down on a GPIO. You take on of the GPIO lines (configured as an input in software) and connect it to one of the button terminals. You place a resistor (say 10K) between that line and the 3.3V rail.
You then take the other terminal and connect it to ground.
When the button is open (i.e. not pressed) the GPIO line is pulled to +3.3V via the resistor and the input will read 1. When the button is pressed the line will be connected to ground and it will read 0. You can do "de-bouncing" in software by not reading the button after the first 1 to 0 transition, for small period, say 200 ms.
The point of the resistor is to pull the line back up to +3.3V when the button is released again, otherwise it would "float" at some indeterminate value. Hence it is called a "pull-up" resistor.
Here are a couple of examples. The left shows an active high switch with an external pull-down resistor. The right is an active low switch with an external pull-up resistor. The Beagleboard also has internal pull-up and pull-down resistors which can be enabled for this purpose. It may also be a good idea to put a small resistance (100 - 1k) in between the switch and the pin to protect it.
simulate this circuit – Schematic created using CircuitLab |
H: PWM Motor Speed Control
I recently bought one of these:
When i hooked it up to my 24v power supply and a voltmeter, it was either 0 or 24v with the POT. Nowhere in between. Why is this? Is it becasue this is a PWM device and needs a PWM signal? If so, why did they even include a POT with it...?
AI: Put a load on it.
From what I can see (given the lack of datasheet), it should generate a PWM w/ the duty cycle proportional to the value of the pot. |
H: Boosting a Lithium Coin Cell
I made a board recently and just started checking it out yesterday. I used a typical lithium coin cell and a boost converter (Microchip MCP1640). With a battery plugged in I get no voltage out of the boost converter (i.e. 5V to GND measures 0V). Worse yet, I measure very nearly 0V from BATT_PWR to GND with the battery in circuit.
So I removed the battery and fed 3V from a benchtop power supply into the FTDI_PWR net and sure enough was able to measure 5V. The PSU indicated I was drawing about 50mA. I experimented with lowering the voltage, and the booster held 5V, but current draw increased as input voltage decreased (which I believe is expected).
So, is the peculiar battery behavior described above due to the battery current limiting? Is there likely to be some more insidious problem at work here - how might I determine that? If this is the wrong way to boost a coin cell to 5V, what's a better way?
AI: Schottky diodes don't make great blocking diodes for the purpose of power rails. They have often have high reverse leakage currents.
Your initial in-rush current is probably high causing the battery voltage to dip below the part's UVLO. To verify this put a scope on your battery and set it to trigger on it dipping more than 100mV below it's nominal value. Make sure you are looking at things at micro-second resolution (like 10 us/div). Post your results here.
Also, if your current requirements are low (<150mA) you can get away w/ a charge-pump. |
H: ATTINY 84 Aref pin?
I want to program an ATTINY84 microcontroller using Arduino UNO as an ISP. In my program I need to use the AREF pin that is located at pin P0 on ATTINY84. I know that I can call analogReference() on Arduino UNO ATMEGA328, but what about the ATTINY84? Do I have to program the IC with some fuses?
AI: For reference, here's a link to the ATTiny84 datasheet.
Section 16.13 specifies the ADC-related registers for controlling the ADC peripheral.
16.13.1 specifies the ADMUX register:
Bit 7 6 5 4 3 2 1 0
0x07 (0x27) REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
If REFS1=0 and REFS0=1, the ADC will use the external reference on pin PA0.
These registers can be modified in code, here's an example using AVR-C:
ADMUX = 0x40;
Note that this will mess up the MUX settings, there are other ways to do this if you don't want to mess up the mux settings using bitwise operands:
ADMUX = (ADMUX & 0x7F) | 0x40; |
H: How can I safely power two 3v motors from a 9v battery?
I'm making a Sumo Bot from scratch and I had purchased two 1.5-3v DC motors from Radio Shack to run with my Arduino Uno v3. I'm using a 9v battery to power my Arduino alongside an RF receiver, Quad Half-H driver, and the two motors. However, 9v is probably too much to directly power two 3v motors.
How could I reduce 9v to a safer voltage to power my two motors?
Thanks!
AI: Do you specifically need (or want) to use a 9V battery? They are not good choices for anything under a lot of load, such as motors. They do not store that much charge, and thus will die very quickly. Regardless of what you do, ensure that you have decoupling capacitors at the power pin of every IC in use, and you have a couple of bulk caps at the power feed for the motors to help with the immediate draw. Sometimes, a motor turning on can drop the line voltage enough that the other circuitry will reset. This is, of course, undesirable!
Option 1 - Dual Battery Banks
You could use two battery banks: 9V for your circuitry, and 3V (2 x 1.5V alkaline or 3 x 1.2V rechargeable batteries). If using the rechargeable batteries, note that 3 of them in series will produce at least 3.6V, so you should use a maximum duty of 80% in a PWM speed controller, so the maximum average voltage is around 3V.
Using two battery banks is rather common in robotics, but not ideal since you have two different charge levels to worry about. For things to work smoothly, the ground terminals of the two batteries (and any power components) should be shared.
Option 2 - Regulating the Voltage for the Motors
The most common thing to do in this situation would be to regulate the 9V down to 3V for use with the motors. This can be done with a linear regulator, but it would be very inefficient since most of the power would be wasted:
Wasted Power = (V_Source - V_Motor) * (I_Motor(s) + I_Regulator)
Using a switching regulator is a better choice, but it is still going to waste at least 10% of the battery power.
Option 3 - Boost the Voltage for the circuitry
I would recommend using a smaller power source suitable for the motors (around 3V DC) and then boosting that voltage level up with a switching regulator to power the Arduino and any other circuitry. A lot less power will be wasted because the circuitry will be drawing a lot less current than the motors.
On top of that, the circuitry itself may be able to run from a lower voltage source, such as 3V DC. The Arduino has an on board voltage regulator to create a stable 5V level for the microcontroller and other parts, but the AVR chip will work fine at 3V DC if you bypass the on board regulator. I don't know what other components are on the Arduino board or what other circuitry / sensors you plan to use that might actually need that 5V to work.
Edit: I neglected the fact that this AVR based Arduino board is using an external 16MHz crystal which does require the higher voltage (5V) to operate. The AVR chip will only operate up to 10MHz with less than 4.5V.
Option 4 - Use 5V Motors
If you were to get different motors that operated at a higher voltage, you could use a 5V (or 4.8V) battery pack. With this, you could bypass the voltage regulator on the Arduino board, as I mentioned at the end of Option 3. In all actuality, the 3V motors might be OK at this voltage anyway, just so long as you do not exceed a PWM duty of 60% when driving them. |
H: LM13700 VCA circuit
I'm trying to build a VCA from the LM137000's datasheet.
The original circuit is with +-15V while I only have a 9V supply. I wonder how the resistor values should be changed so the OTA works with 9V (split supply)? Thank you for your help in advance!
AI: If your 9V supply is actually a split supply, you will probably be fine. Use caution if you intend to make more than one of these.
As far as changes, you won't need to make many.
Put voltage dividers on + and - pins to scale their voltage to \$\pm20mV_{max}\$. You will get a more linear response this way. If you do this, eliminate the diode bias resistor. It won't be necessary.
The gain control is where you need to pay attention. The maximum amplifier bias current (\$I_{ABC}\$) is 2mA. It is calculated as follows: \$I_{ABC}=\dfrac{V_{control_{max}}-(-V_s+1.3V)}{R_{ABC}}\$. Keep in mind that 2mA is an absolute maximum rating. \$R_{ABC}\$ must be chosen to stay under it.
The output current is given as \$I_{out}=\frac{17}{V}I_{ABC}(V_+-V_-)\$ Since the output is a current source, you can chose any \$R_L\$ value that will give you the output voltage you need. Regardless of your choice, I recommend using an op amp buffer instead of the Darlington pair that is built into the part. |
H: Cell phone battery with solar shield, arduino
I was looking for your opinion on this product: http://www.seeedstudio.com/wiki/Solar_Charger_Shield_v2.0b
Do you think I could use a cell phone battery (3.7v 1000mA) with this? I have a standard Li-Ion battery with these specs that seems to work fine with this product, but I'm not sure if there is anything special about a cell phone battery that would cause it to explode or act differently if hooked up to this solar shield.
I was looking at a cell phone battery like this one: http://www.amazon.com/LG-1100mAh-Standard-Battery-manufactured/dp/B000IBRSIS
I was thinking I would just epoxy (not solder) on some leads to a JST connector.
Can I just leave the third terminal empty? I think it is usually to sense heat or charge or something, right?
Thanks!
AI: That circuit uses the CN3083 LiIon charger IC <- datasheet.
It can work with batteries with or without temperature sensors.
If the IC specs suit your need the circuit will work as well as the CN3083 does.
Horrendously drawn Charger shield cct diagram here |
H: Mathematical rigour in Signal and Systems
I'm an electronics engineering student with high inclination to analysis and pure mathematics ( abstract algebra/linear algebra ... ). I was just wondering if there was any book ( or any resource ) that treats signal and systems and signal processing with a lot of mathematics rigour ( actually doing proper complex analysis, using functional analysis and linear algebra rigorously to explain convolution, fourier, laplace and z transforms for example ).
I'm very disapointed with the books i've read ( Oppenhein, Lathi and related ) because it actually throws a lot of the beauty of analysis and algebra away, focusing on the computational side.
Thanks a lot
AI: This xkcd comic comes to mind.
EE is some kind of hybrid of applied physics and mathematics. It's easy for a mathematician to pick up an electronics book and move to the left. It is not as easy for a EE to pick up an advanced mathematics book and move to the right.
For most practical things, the the math is well understood. For example, filters are commonly developed from canned topologies, and most practicing EEs let MATLAB or other software do the number crunching. It's just not worth the time it would take to work through all of the transforms manually to get the transfer function, especially for filters higher than second order. If the filter is going to be implemented digitally, all it takes is a z transform and some algebra to get to a difference equation.
The majority of the guys that care about the math at the level you're interested in are researchers. You might look at the Proakis signal processing and communications books. They have quite a bit of math in them, but your expectations aren't clear enough to me to say whether you'll be satisfied with them. You would probably be better served to look for straight math books that cover the topics of interest. Unfortunately, I cannot provide any recommendations there. That question may be better suited for Math.SE |
H: Could someone help me understand this simple circuit?
This is a single-wire earth-return telephone system used in cave rescue communications.
simulate this circuit – Schematic created using CircuitLab
The ground is a metal casing to make contact with the users hand. Line is clipped to an exposed section of a wire that runs through the cave.
The circuit is shown in receive mode, PTT switches to transmit, the speaker serves as a microphone and speaker. All systems I've seen use a Rocking Armature Transducer for the speaker. There is no base station or similar - you can just connect two or more of these to the same wire and use them.
My electronics knowledge is not good enough to fully understand this. Here's what (I think) I do understand.
C3 and C4 are audio coupling (block direct current flow.)
R1 and R2 hold + of the op-amp at 4.5v.
Earth-return is a misnomer - it actually works off the capacitance of your body.
When receiving
R3 is shorted and therefore does absolutely nothing.
The op-amp is working as a buffer and does not amplify the input.
I'm guessing C1, C2 and R4 are serving to filter the input - perhaps suppress high frequency noise.
When transmitting (this is where I really get lost)
C2 is now shorted and does nothing.
What's R3 doing - is the op-amp now amplifying?
Are C1 and R4 still performing some function?
Am I right so far? Can someone please help me understand the rest?
My goal is to be able to alter the circuit to try out different speaker setups.
Thanks
AI: Maybe look at it like this: -
I've removed components that get shorted or open circuited by the PTT switch contacts
In transmit mode, the speaker becomes the mic and the op-amp has a large gain determined by R3 (100k) and the small impedance of the speaker. The Rocking Armature's impedance is 150 ohm so for a rough estimate, the gain is 100,000 ÷ 150 = 666. This means that a 10mVp-p signal on your "mike" gets amplified to 6.67Vp-p.
In transmit mode R4 is superfluous but I left it in because it wasn't exactly open circuited or short-circuited by the PTT switch. C1 in transmit mode is just stabilizing the non-inverting input of the amp. |
H: Minimum tolerable signal to noise ratio in modern communication systems
What is the minimum tolerable SNR in today's (digital) communication systems for successful recovery of the message? I've heard that regular commercial systems can recover the message with a SNR as small as -60 dB (using robust coding techniques). Is it correct? And if yes, how can you observe and distinguish even the presence of a signal when it's burden in a noise with 106X more power?
AI: What your professor is almost certainly referring to is SSDS (Spread Spectrum Direct Sequence) encoding technicals (yes they are convolutional) and they trade off data rate for a given bandwidth for the ability to recover signal in deep noise. CDMA systems from Qualcomm use CDMA but not so much for signal in noise recovery but for code diversity in band, meaning multiple independent transmissions overlapped in band.
CDMA uses the concept of process gain to reflect the ability to recover from noise and it counts on the fact that the "pseudo noise" (aka PN) has a distinct matched filter. When the matched filter is applied any noise in band will be mapped out of band and any PN will be mapped to a modulated signal. the process gain (measured in dB) tells you how much excess that you can have in S/N.
However, 60dB is trivial in context to the the NASA PN codes that are used in it's deep space network. These codes can have repeat lengths of 1000's of chips. A chip is s sub-unit of modulation, it is the ratio of chips to bits that determines the process gain.
An excellent book on this subject is "spread spectrum systems" by Dixon.
GPS is also based upon CDMA.
This work was first developed by Claude shannon and was top secret for many years post war. |
H: Problem on output compliance?
What is exactly meant by output compliance of a current source? I've read that it's the range of voltage over which the current source behaves well. What exactly does behaving well mean?
I've got a little problem based on this concept, but Im not sure how to go about it.
You have +5 and +15 volt regulated supplies available in a circuit. Design a 5mA npn circuit source(sink) using the +5 volts on the base. What is the output compliance?
How would you do this?
AI: A well behaved (ideal) current source keeps the current constant no matter what its voltage is.
There are of course lots of different topologies for making current sources, just like there are lots of ways of making voltage sources. However, what this question is referring to is a special property of BJTs that can be exploited to make simple current sources.
Consider these characteristic curves of a common NPN transistor (swiped from here):
Each curve is the collector current as a function of the collector to emitter voltage for a particular base current. Note how the curves are pretty flat after 1/2 a volt or so accross C-E. That means that the current changes little despite large changes in voltage. Sound familiar? Now see if you can exploit this in a circuit to make a well behaved current sink. |
H: What does "6 V stop-start applications" mean?
I read the following in the NXP TDF8530 leaflet:
this ultra-efficient device supports 6 V stop-start applications and delivers
audiophile sound quality
What does that "6 V stop-start applications" mean?
AI: What it actually says is "... is an ultra-efficient, quad-channel Class-D audio amplifier that supports the 6 V requirement for start-stop vehicles."
Vehicles that stop and restart their engines for short periods of time (e.g., at stoplights) can experience power bus sags. What this brochure is saying is that this chip will be well-behaved even if the power supply sags as low as 6V. |
H: Electrical properties of keyboard keys
I'm looking to hack together a keyboard by taking an existing keyboard and connecting it to switches that I'll assemble separately.
What I want to know: What should be the electrical properties of the switches that I'll buy? I'm new to this so I'm not sure whether I need "mom off", "mom on", SPST, SPDT... Please tell me which one should be used for a keyboard.
AI: Keyboard keys conduct electricity when you press them down so you want normally open momentary press switch. To find where a button that you press is (for instance the letter "C", try to follow the lines where the switch goes and then check for electrical conductance with a multimeter (or a battery with an LED) when you press the button down. When you press it, the resistance of the leads should go from infinite ohms to close to 0 ohms. |
H: How does less cable impedance, source/termination impedance, lead to longer cable length for higher data rates?
This question is about high speed digital transmission on a transmission line,
I need to know about how does the
(1) impedance of the transmission line and the
(2) source impedance and
(3) termination impedance,
effect the (1) cable length when we want to transmit a fixed high data rate,
and also
(2) effect data rate for a fixed length cable.
AI: I understand you asking these sort of questions and I've tried to answer in the format that you presented the questions. Please forgive if I have misconstrued something.
Q1 - cable length when transmitting high data rate: -
(1) Impedance of the transmission line is independent of cable length
(2) Source impedance is independent of cable length
(3) Termination impedance is independent of cable length
Q2 - data rate for a fixed length cable: -
(1) Impedance of the transmission line is generally higher for better data success
(2) Source impedance can be zero for improved results providing the receiver has good terminator
(3) Termination impedance needs to be the correct value for the cable to minimize reflections corrupting the data |
H: How to know whether a potentiometer is a linear potentiometer or audio potentiometer?
In general, how can you tell?
As a specific example, how would I know from looking at the following datasheet? http://www.alps.com/products/WebObjects/catalog.woa/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K1130AV7.html
AI: The relationship between the angle of the knob and the resistance is the "taper". That datasheet says this pot's taper is "1B".
Finding information on what 1B means is a bit tricky. It's at the related information link at the top. The tapers are described at the very bottom. Here's the relevant image:
It's hard to read, but 1B is the straight line in the upper-left. This is an ordinary linear pot.
This is something of an industry convention. See for example Alpha's pot tapers. By convention, anything with a "B" in it is a linear taper. Anything with "A" in it is "audio" or "logarithmic". |
H: What is the difference between Flash memory and EEPROM?
Flash memory storage and EEPROM both use floating gate transistors for storage of data. What differs between the two and why is Flash so much faster?
AI: The first ROM devices had to have information placed in them via some mechanical, photolithographic, or other means (before integrated circuits, it was common to use a grid where diodes could be selectively installed or omitted). The first major improvement was a "fuse-PROM"--a chip containing a grid of fused diodes, and row-drive transistors that were sufficiently strong that selecting a row and forcing the state of the output one could blow the fuses on any diodes one didn't want. Although such chips were electrically writable, most of the devices in which they would be used did not have the powerful drive circuitry necessary to write to them. Instead, they would be written using a device called a "programmer", and then installed in the equipment that needed to be able to read them.
The next improvement was an implanted-charge memory device, which allowed charges to be electrically implanted but not removed. If such devices were packaged in UV-transparent packages (EPROM), they could be erased with about 5-30 minutes' exposure to ultraviolet light. This made it possible to reuse devices whose contents were found not to be of value (e.g. buggy or unfinished versions of software). Putting the same chips in an opaque package allowed them to be sold more inexpensively for end-user applications where it was unlikely anyone would want to erase and reuse them (OTPROM). A succeeding improvement made it possible to erase the devices electrically without the UV light (early EEPROM).
Early EEPROM devices could only be erased en masse, and programming required conditions very different from those associated with normal operation; consequently, as with PROM/EPROM devices, they were generally used in circuitry which could read but not write them. Later improvements to EEPROM made it possible to erase smaller regions, if not individual bytes, and also allowed them to be written by the same circuitry that used them. Nonetheless, the name did not change.
When a technology called "Flash ROM" came on the scene, it was pretty normal for EEPROM devices to allow individual bytes to be erased and rewritten within an application circuit. Flash ROM was in some sense a step back functionally since erasure could only take place in large chunks. Nonetheless, restricting erasure to large chunks made it possible to store information much more compactly than had been possible with EEPROM. Further, many flash devices have faster write cycles but slower erase cycles than would be typical of EEPROM devices (many EEPROM devices would take 1-10ms to write a byte, and 5-50ms to erase; flash devices would generally require less than 100us to write, but some required hundreds of milliseconds to erase).
I don't know that there's a clear dividing line between flash and EEPROM, since some devices that called themselves "flash" could be erased on a per-byte basis. Nonetheless, today's trend seems to be to use the term "EEPROM" for devices with per-byte erase capabilities and "flash" for devices which only support large-block erasure. |
H: Least noisy pre-amplifier design
I am building a frequency generator circuit and need some advice. I am using the AD9833 DDS generator (programmed from a PIC16F876) to generate frequencies and I wish to be able to adjust the gain.
Being unable to find a suitable Programmable Gain Amplifier I was going to use a non-inverting amplifier and a digital potentiometer.
The advice I need is:
Is it better (less noisy) to pass the signal through the potential divider (in a passive fashion) inputting in to a unity gain amplifier;
OR
Should I use a digital resistor in the feedback loop of the amplifier and set the gain that way?
Also, if anyone else has any better ideas they would also be welcome, but board space is limited so complex solutions maybe hard to implement.
AI: Look carefully at the specs for a digital pot, since they often are quite different than what you expect. For example, look closely at these issues:
Noise: Digital Potentiometers (DPs) often have terrible noise performance. Rarely better than -80 dB THD+N, and often only -60dB or worse. Many pots don't even put noise figures in the datasheets. DPs are often only suitable for the worst quality consumer audio gear, or applications where noise isn't much of an issue (like LCD contrast adjustments).
Accuracy: Many DPs only have a 20-30% accuracy on the total resistance from chip to chip (and sometimes between two pots on a single chip). The MAX5460 has a nominal resistance of 100K, but can vary between 75K and 125K. If you need two DPs to match, then you are out of luck.
Minimum resistance: DPs often do not go down to 0 ohms. Some only go down to 1K, or higher. This can be super important if you are using the DP in the feedback path of an op-amp, to give you good gain control.
I looked into using digital pots for gain control in audio applications and found them to be largely useless. Instead I use relays (low noise, low resistance), Analog CMOS switches (good noise, small-ish), or even JFETs (cheapest, reasonable noise, hard to use). |
H: PIC16: Out of Data Space - Make use all available banks
I'm using a Microchip PIC16F1825 with the XC8 (v1.12) compiler and defining some arrays (size between 16 and 64 bytes). I was able to declare them (linker output below). However, as soon as I try to access a few of them in a for-loop, I get an error on build:
error: could not find space (32 bytes) for variable _tempMeasurements
(908) exit status = 1
The more arrays I try to access the more Data Space usage goes up. How can I avoid running out of memory? Clearly, not all banks are used.
Memory Class Usage:
Program space:
CONST used 0h ( 0) of 2000h words ( 0.0%)
CODE used B8Dh ( 2957) of 2000h words ( 36.1%)
STRCODE used 0h ( 0) of 2000h words ( 0.0%)
ENTRY used 0h ( 0) of 2000h words ( 0.0%)
STRING used 5h ( 5) of 2000h words ( 0.1%)
Data space:
COMMON used Eh ( 14) of 10h bytes ( 87.5%)
BANK0 used 4Fh ( 79) of 50h bytes ( 98.8%)
BANK1 used 4Eh ( 78) of 50h bytes ( 97.5%)
BANK2 used 4Ah ( 74) of 50h bytes ( 92.5%)
BANK3 used 50h ( 80) of 50h bytes (100.0%)
BANK4 used 40h ( 64) of 50h bytes ( 80.0%)
BANK5 used 40h ( 64) of 50h bytes ( 80.0%)
BANK6 used 40h ( 64) of 50h bytes ( 80.0%)
BANK7 used 40h ( 64) of 50h bytes ( 80.0%)
BANK8 used 0h ( 0) of 50h bytes ( 0.0%)
BANK9 used 0h ( 0) of 50h bytes ( 0.0%)
BANK10 used 0h ( 0) of 50h bytes ( 0.0%)
BANK11 used 0h ( 0) of 50h bytes ( 0.0%)
BANK12 used 0h ( 0) of 30h bytes ( 0.0%)
ABS1 used 16Ah ( 362) of 400h bytes ( 35.4%)
EEPROM space:
EEDATA used 0h ( 0) of 100h bytes ( 0.0%)
Configuration bits:
CONFIG used 2h ( 2) of 2h words (100.0%)
ID Location space:
IDLOC used 0h ( 0) of 4h words ( 0.0%)
Memory Summary:
Program space used B92h ( 2962) of 2000h words ( 36.2%)
Data space used 3AFh ( 943) of 400h bytes ( 92.1%)
EEPROM space used 0h ( 0) of 100h bytes ( 0.0%)
Configuration bits used 2h ( 2) of 2h words (100.0%)
ID Location space used 0h ( 0) of 4h bytes ( 0.0%)
AI: Consecutive direct accesses to variables in the same bank will be faster than direct accesses to variables in different banks. Consequently, the compiler is probably trying to consolidate variables which are accessed near each other so they'll be placed in the same bank. Unfortunately, it may be attempting to consolidate more variables than will actually fit into a bank.
I'm not familiar with the particular compiler you're using; on some compilers, variables will only be consolidated if their primary (non-extern) definition is in the same source file. Moving some arrays to separately-compiled source files may prevent the compiler from trying to consolidate them. Alternatively, it may be helpful to have some arrays which are only accessed by routines that are used especially for that purpose. For example, have a source file that's something like:
static unsigned short foo[32];
unsigned short get_foo(unsigned char addr)
{
return foo[addr];
}
void put_foo(unsigned char addr, unsigned short value)
{
foo[addr] = value;
}
Note that if you use this approach, you may be able to work with arrays that are too large to fit in a single page, using something like:
static unsigned short foo0[32],foo1[32];
unsigned short get_foo(unsigned char addr)
{
if (addr & 32)
return foo0[addr];
else
return foo1[addr-32];
}
void put_foo(unsigned char addr, unsigned short value)
{
if (addr & 32)
foo0[addr] = value;
else
foo1[addr-32] = value;
}
Such things aren't beautiful, but they may save code compared to some of the other techniques that would otherwise be necessary. |
H: Why does an Oscillator produce sine waves?
By the definition of Oscillator: 'An Electronic circuit that produces a repetitive, oscillating electronic signal, often a sine wave or a square wave' I'm familiar with RC Phase Shift Oscillator and Wien Bridge Oscillator. Both satisfy the Barkhausen criteria,so should produce an output, But why is the output Sine ? If someone could elaborate using either of the two oscillators, or maybe some proof/result that give a better idea on the shape of the output wave. I also know the principle of a square wave generator using op-amp, but that isn't an oscillator and works on the principle of saturation of op-amp. Am I correct in stating that oscillator and sq. wave generator are different ?
AI: If the gain of a system at every particular delay is constant, the system will produce oscillations with those periods which have a gain of one. At periods where the gain exceeds one, the strength of the oscillations will grow unless or until something causes the gain falls to below one. If there were one frequency where the gain stabilized at exactly one, and it were less than one at all other frequencies, the circuit would produce a sine wave at the frequency in question. The wave would be a sine wave because any other type of wave would have content at frequencies where the gain is less than one.
Note that in practice, many types of oscillating circuits have gains which vary widely during the course of each "cycle". Such variations make it very difficult to predict analytically the frequency content of their output. Because there is a very fine line between having oscillations die down to nothing, and having oscillations grow without bound, even circuits which are intended to produce sine waves generally end up having a gain which is sometimes greater than 1 and sometimes less than one, though ideally there's a gain control mechanism that will try to settle on the right value.
Incidentally, some circuits use incandescent light bulbs for that purpose, since their resistance varies with temperature. If the power fed to a light bulb is proportional to the strength of an oscillator's signal, and if an increase in resistance will cause a reduction in gain, then the light bulb's temperature will tend to reach an equilibrium where the gain is 1. If the frequency in question is fast enough, the light bulb will only heat up or cool down a little bit during each cycle, allowing reasonably-clean sine waves to be generated.
Addendum
Rather than using the term "constant gain", it may be more helpful to use the term "linear circuit". To borrow an analogy from a magazine I read some years back, comparing "linear circuits" to "non-linear circuits" is like comparing "kangaroo biology" to "non-kangaroo biology"; linear circuits are a particular subcategory of circuits, and non-linear circuits are everything else.
A one-input one-output linear black box is one which takes an input signal and produces an output signal, with the characteristic that if F(x) represents the signal produced by the box when it is fed signal x, and if A and B are two input signals, then F(A+B) will equal F(A)+F(B). There are many kinds of things a linear black box can do to a signal, but all must obey the above criterion. The output produced by a linear black box when given a combination of many different frequency signals will be the sum of the outputs that would be produced for each frequency in isolation.
The behavior of many practical circuits is close to that of a one-input one-output linear black box. Since any wave other than a sine wave is a combination of sine waves at multiple frequencies, for a circuit to oscillate with anything other than a sine wave, there must be multiple frequencies which, if fed in individually, would cause the output to precisely match the input in phase and amplitude. While it is certainly possible to construct such circuits, most practical circuits will only have one frequency where such behavior will occur. |
H: Planning an amplifier using a transistor
I want to plan design an amplifier of tension voltage using a transistor:
but I don't know how I can choose the values of \$R_1\$, \$R_2\$, \$R_3\$, \$R_4\$, \$C_1\$ and \$C_2\$..
I want to obtain a gain of 3, and I want \$Z_{in}=15k\Omega\$ and \$Z_{out}=3k\Omega\$. Could you help me? I've just started to study this subject.
AI: Output impedance is specified by you as 3kΩ, this sets R4.
The ratio R4/R3 defines your gain in this circuit, which you specified as 3. You can calculate R3 now.
The parallel circuit \$R_1//R_2 = \dfrac{R_1×R_2}{R_1+R_2}\$ is specified by you as 15kΩ. The transistor's base will load the voltage divider, but this is easily less then 10% when the transistor's gain is 100 or more. You can neglect it.
All you need to decide on is the bias voltage at the base of the transistor. Start half way the supply voltage and see how it works. If you realize yourself that the voltage across R4 is three times higer than the voltage across R3, then you can calculate the optimum DC voltage for the base (which is 0.7V higher than the voltage on R3) for largest swing.
But this method of guesstimating is probably not what your teacher is looking for. |
H: How does a dual gate MOSFET reduce Miller effect?
How does a dual gate MOSFET reduce Miller effect? I am trying to gain a global understaning of the physics behind them, not necessarily exact formula's that come with it other than maybe some for practical use. The Wikipedia article refers to a tetrode article based on tubes, where I get slightly lost.
I guess the questions in order are:
What is a tetrode (in discrete transistor/MOSFET speak);
How is a dual gate MOSFET similar to a tetrode, what are the 'mechanics' behind it in global terms? (Trying to get a feeling for the physics behind it).
How does it reduce Miller effect and is a dual gate MOSFET different from a discrete tetrode in this.
Is a dual gate MOSFET any good for other properties?
AI: I'm going to ignore the reference to tetrode, I have never understood why an exact analogy reveals a fundamental truth.
The miller effect arises in situations from a connecting capacitance across two nodes that that have an inverting voltage gain/relationship between them. it doesn't have to be in transistors either, but in MOSFET's you have \$C_{GD}\$. How this is traditionally solved is to cascode the amplifier by isolating the offending capacitance so it doesn't appear across the gain stage. The dual gate Mosfet is basically a cascode stage with the cascode transistor built in (this has a secondary effect, see below), you just have to bias the the transistors so that they are in the active regime. M1 = amplifier, M2 = cascode
simulate this circuit – Schematic created using CircuitLab
The amplifer transistor converts the input voltage in the output current and the cascode transistor simply transfers this current to the output load. the output is on the drain of the cascode and the input is on the gate of the amplifier transistor. There is no capacitance across the two nodes, the miller effect is greatly reduced.
Cascoding greatly helps in gain too.
An interesting effect from manufacturing comes into play. The upper device is a longer gate device and the lower is a dual gate device. The S/D implant to channel capacitance tends to be lower than the S/D to isolation edge capacitance (the S/D's on the outer edge) so the S/D in between the gates will tend to have a lower capacitance that if you were to have designed the circuit using two separate transistors in a cascode configuration (and obviously they take up less area). This means that the \$C_{SB}\$ capacitance is less as well making for a higher speed circuit, here SB = Source to Bulk (AKA well). |
H: The electricity grid: what keeps small power generators from being 'driven' by large ones?
This is a two part question and pertains to power generation:
What prevents a larger plant (say nuclear) from turning an itsy-bitsy gas generator into an electric motor and drive current through it? (obnoxiously large diodes?)
How does the entire portfolio of power generators stay in sync/phase with the grid to produce one AC wave?
Edit: the second part seems to be already answered here. I'd appreciate a clear and convincing answer for the first part still.
AI: Short Answer: Synchronizers
Basically, feedback is used to keep the generator and grid in sync.
There are many ways to do this. A nice overview is here.
Virtually all modern power generation systems use some form of digital controller for the task. My grid-tied solar panel inverter has a PIC18F class microcontroller managing some solid-state relays (SSR) if I remember correctly.
Common Modern Power Station Design
Here is my summary of what I believe to be the most common basic approach to modern power generation plant design. Figure and text adapted from:
"Fundamentals and Advancements in Generator Synchronizing Systems,"
Michael J. Thompson, Schweitzer Engineering Laboratories, Inc.
Dec. 9, 2010.
In the figure...
Returns are not shown
G1, G2 are the generators
Squares 1,2,3,4 are relays
Bus1, Bus2 are out-bound power busses (redundant)
MGPS units are GPS-synchronized clock sources for timing the generators
A25A is the measurement and control unit (contains a microprocessor)
How it works...
Modern microprocessor-based components and "digital" timing gear, like synchrophasors, have revolutionized the way generator synchronizing systems are designed.
For example...
The "A25A" in the figure is a microprocessor-based automatic synchronizer with six isolated and independent single-phase voltage sensing inputs that eliminates the need to physically switch voltage signals.
The 1,2,3,4 "digital" relays provide streaming synchrophasor data.
Relay-to-Relay communication in the A25A allows it to be located close to the synchronizing breaker with control signals sent back to the devices which slow down (governor) or speed-up (exciter) the generator mechanism via fiber-optic links.
Timing and Control...
The ability to build systems for monitoring and control using low-cost, fiber-optic communications links has completely changed generator synchronizing systems.
The "digital" relays take direct synchronized measurements. Synchronized phasor measurements are measurements of the phase angle of power system quantities relative to a universal time reference.
Today, the precise time reference required to make this phase angle measurement is easily obtained from protective-relay-grade Global Positioning System (GPS) satellite clocks.
Synchrophasor technology allows voltage readings from various devices throughout the power station to be compared for angular difference. The data can be streamed at rates up to 60 messages per second with low latency.
Since phasor measurement unit (PMU) functionality in protective relays was first introduced in 2000, they have become nearly ubiquitous, and synchrophasor data are available nearly everywhere at no additional expense to the power plant owner.
A dedicated computer, running synchrophasor data concentrator (PDC) software, can receive streaming data from the various microprocessor-based relays applied for protection and control of the synchronizing breakers.
Just as the microprocessor-based automatic synchronizer can select the
appropriate voltages for each synchronizing scenario from those wired to its six input terminals, the PDC can select the proper signals in its incoming data streams for the incoming and running voltages based upon operator selection of the generator and breaker to be synchronized.
No physical signal switching is required. And the synchrophasor voltage measurements from the breaker control relays are independent from the measurements of the automatic synchronizer, which makes the systems redundant.
Lag-Lead
@Kaz had provided a nice summary of directly slaved motors/generators in the comments (documented here for posterity ;-) ):
This is like asking, what keeps the slave rowers in a boat from just
passively letting their oars drift with the water and not do any work?
Well, there is a guy who beats a drum and so everyone has to pull at
the same frequency, or get whipped. If the slaves get lazy, the boat
will slow down, and soon, they will not be able to maintain that
rowing frequency without exerting force on the water to speed up the
boat again, or else letting their strokes be so obviously small (to
match the slow speed relative to the water) that they all get a
whipping from the guard.
So,
suppose two generators are supplying a grid. One of the generators is
slightly lazy and so it just spins along with the frequency: it avoids
being driven, but does not put in any work. Then, demand on the grid
rises. The other generator gets bogged down and slows down. The lazy
one, lazy as it is, is still committed to maintaining the frequency.
Since the grid frequency has slowed down slightly, that means the lazy
one is now engaged: it is pushing the pace to help speed up the grid,
thereby becoming engaged. It's much like when people combine forces to
row a boat, or pull a load
In modern power plants, continuing our prior discussion, the approach is simple architecturally: each generator is slaved to a global time reference.
As explained above, the generators are phase locked to a global clock. They are each individually held responsible for their output being at a certain phase angle at a certain time.
If they are too fast, a device called a governor which is attached to the generator applies a braking force. If too slow, an attached exciter adds energy to speed up the generator.
As a side note, you can implement both functions in the same device in some architectures. For example, with a mechanical rotating mechanism, you can attach an electric motor to the axle and resist (govern) or assist (excite) the rotation by driving the attached motor in reverse or forward respectively.
Given that all generators are running in phase with the same time reference, sync is achieved.
Load Shedding
I can understand the sync, can you explain how 'it ensures that the
generator is pushing current out rather than taking current in'?
This part is intuitive. Look at Ohm's Law or Kerckhoff's Laws...
If two voltage sources are in sync it means they produce the same voltage at the same time. If a perfect wire connects two voltage sources at the same voltage, zero current will flow in that wire.
If you connect a "large" generator and a "small" generator you are only describing a difference in maximum current at the same voltage generated.
As the smaller generator gets overloaded, it's voltage will fall. In rotating generators this results in a reduction in frequency (the rotor slows down) as the electrical loading applies a mechanical braking force through the electromagnet.
In either case, the synchronizers detect the overload condition as a loss of sync and disconnect the generator. This is called "load-shedding." As you can see, load-shedding only makes the problem worse for the remaining generators and the problem can cascade.
This is what happened during the NorthEast Blackout of 2003, although the event was caused by, among many things, a software glitch being too agressive with load shedding rather than actual overload. |
H: De Sauty bridge with RC parallels
The bridge is described in this way:
Whit the equilibrium condition, when the current is zero between A and B, I'll have:
$$Z_x*R_2=Z_c*R_1$$
derived by Wheatstone Bridge's relation.
Evaluating the parallel impedances ( \$R_x\; ||\; 1/(j\omega C_x)\$ ), I obtain:
$$ R_x/(1+j\omega R_x*C_x) * R_2 = R_c/(1+j\omega R_c*C_c) * R_1$$
And so:
$$ R_x*R_2*(1+j\omega R_c*C_c)= R_c*R_1*(1+j\omega R_x*C_x)$$
Finally, It's obtained these results:
$$R_x=(R_c*R_1)/R_2$$
$$C_x=(R_2*C_2)/R_1$$
Solutions of the De Sauty Bridge.
But, how are obtained this results starting from the previous equation?
If we had not parallel scheme, as impedance between \$C_x\$ and \$R_x\$, the result should be obvious for \$C_x\$ starting by the equilibrium condition; but, as it is, I cannot figure out which steps are made.
AI: Your first equation is of course correct:
$$Z_x=Z_c\frac{R_1}{R_2}$$
Now it's convenient to invert this equation:
$$\frac{1}{Z_x}=\frac{1}{Z_c}\frac{R_2}{R_1}$$
Using \$1/Z_x=j\omega C_x+1/R_x\$ and \$1/Z_c=j\omega C_c+1/R_c\$ we obtain
$$j\omega C_x+1/R_x = (j\omega C_c+1/R_c)\frac{R_2}{R_1}$$
Comparing real and imaginary parts we get
$$C_x=C_c\frac{R_2}{R_1}\text{ and }R_x=R_c\frac{R_1}{R_2}$$ |
H: wake up 8052 using external interupt : problems
Heres the procedure I followed
I set an edge triggered external interrupt.
SET IT0
SETB EX0
SETB EA
Then I set the PCON
MOV PCON, #02H
When the external interupt is applied (a high to low signal) the controller is comming out of power down mode, the code that follows the above PCON code works, but the internal timmer interrupt remains off and when the controller then powers down, it never comes out of it, unless a reset is done.
PS: I am using LDR and a voltage divider circuit and a transistor as the external trigger circuit. The 'LDR Memory' is causing problems, but I am not sure the above mentioned anomalies is a result of that.
PS: The microcontroller is AT89S52 at 12 MHz.
PS: Power source is providing enough current.
AI: First off, it can help on an input such as that LDR to have hysterisys (positive feedback). You will need to sit down and work it out - but it means you need another transistor and a few more resistors - but it makes the circuit more reliable in operating the interrupt, and it makes the problem easier to debug - your choice as to whether you do this or not.
Next, I can't exactly answer your question BUT, what you describe can be caused by a missed interrupt. If your code gets an interrupt, but you never return from it, it will NOT accept more interrupts until you (1) Reti or (2) Reset.
You are (2) Resetting - and it fixes the problem.
But (1) Reti is a lot easier!
The BEST solution is to find out what is causing the interrupt and fix it. Chances are you need to disable the run flag on your timer before going to sleep. |
H: MOSFET symbol - what is the correct symbol
I've been on this site now a couple of months and I notice various symbols used for MOSFETs. What is the preferred symbol for an N Channel MOSFET and why?
AI: It is likely that you saw a Circuit Lab sysmbol and that this caused you to ask this question. The Circuit Lab N Channel MOSFET symbol is both unusual and illogical.
I'd avoid using them if at all possible.
Read on ...
Acceptable [tm] N Channel MOSFET symbol tends to have these characteristics.
Gate symbol on one side.
3 "contacts" on other side vertically.
Top of these is drain.
Bottom of these 3 is source.
Middle has an arrow pointing INTO the FET and the outside end is connected to source.
This indicates that there is a connected body diode and that it is non conducting when the source is more negative than the drain (arrow is same as would be for a discrete diode).
Any symbol which obeys these guidelines should be "clear enough" and OK to use.
I have very occasionally seen people use a symbol which does not comply with these guidelines but which is still recognisable as an N Channel MOSFET.
SO. Any of these are OK, and you can see the differences for the unmarked P Channels.
Many more examples here
But!!!
Jippie's example shows the rogue version.
[Note: See below - this is in fact intended to be a P Channel sysmbol].
Truly horrible. I'd have to wonder if this was a P Channel symbol or an N Channel one.
Even the discussion it is taken from has people expressing uncertainty re arrow direction. As shown IF that is an N Channel then it is implying body diode polarity and NOT current flow in source.
Thusly
________________'
Circuit Lab is apparently the (or a) culprit.
This is their symbol for an N Channel MOSFET.
A nasty piece of work, alas.
Arrow shows usual drain-source conduction direction BUT as a MOSFET is a 2 quadrant device and will provide a true resistive on channel with \$V_{gs}\$ positive BUT \$V_{ds}\$ negative, the arrow is meaningless and, as it is in the opposite direction to most N Channel MOSFET sysmbols it is misleading to most. (Note the proper use of this symbol in table below).
USER23909 helpfully pointed out this page - Wikipedia - MOSFET . This page includes the following symbols. User xxx says these may be IPC standards, but Wikipedia is silent re their source.
Wikipedia MOSFET symbols
http://en.wikipedia.org/wiki/MOSFET#Circuit_symbols |
H: How to uniquely identify USB HID class device?
I would like to identify a USB keyboard uniquely(something equivalent to unique mac-id for the Ethernet cards) on a computer. Does the USB HID profile has a support for such identification ? If so what is the field called ?
I understand that VID and PID uniquely identify a make of keyboard from a vendor, but I am looking forward to identifying each keyboard separately.
PS : Asking the question on Elex SE, since I would have to implement this USB profile on AVR32.
AI: The USB Serial Number is what you want. And Atmel has a small datasheet on how to implement it with their usb stack here.
Additionally, any of the user configurable USB descriptors could be used. Assuming you are using the same VID/PID pair, you still have the Device Release Number, Manufacturer String Descriptor (Manufacturer Name), Product String Descriptor (Product name), and the Serial Number Descriptor, all of which go into the basic usb device descriptor that is mandatory for any usb device. They are independent of the usb class (HID, CDC, Proprietary etc), all major OS can read them, and can be as unique as you need them to be. |
H: what transformer should i use?
OK, i am new at all of this and for my first project i desided to try to use the power from a coal (like the ones you sprinkle incense on), use a Peltier to convert the heat to dc, now i know i need 5v and i think 250 mAmps to charge a phone, thing is i dont know how to figure out best to regulate and amplify the current that will be produced. i figure a transformer of some sort because the coal wont produce enough voltage on its own, but the also would it need something else to regulate the current going in to the transformer, the coals out put will very. if i will need something to regulate it then what?
AI: Before anyone can make a useful suggestion, we need some numbers: What voltage and current do you expect from the Peltier device? What power (volts times amps) is that?
Since the Peltier device produces DC, a simple tranformer won't work, as transformers require AC to work.
You will need a DC-DC converter to change the Peltier output to the 5 Volts you want to charge the phone. 5 volts at 250 mA is 1.25 watts, so the Peltier device must supply at least this much power (the DC-DC converter will be less than 100% efficient, so you'll probably need 1.5 - 2 watts from the Peltier device...) |
H: What happens when the current fed to a device is higher than the specified value?
I have a solar panel which provides the output of up to 500mA with 6v potential difference. .5A is the maximum current output, and the usual output will be around 300-350mA. Can I use it as a power source to run a computer-fan which is specified to draw 0.1-0.3A with 5v? If it is not, can I use it to run 2 fans in parallel, so that the currents will be split to each?
What happens when the source produces more current than the specified input value of a device?
AI: The current drawn by a device (your fans) is a factor of that device's impedance. The current rating of a power source is the maximum current that source is capable of delivering or should be allowed to deliver.
Thus, your source having a higher current rating is not a problem, the fan will draw what it needs at the specific voltage expressed across the fan's contacts.
If the solar panel is not able to deliver that much current at a given time, i.e. if the panel is shaded or the light source is weak, the fan will run slower or not at all, but no harm will come to either.
You definitely do not need to split the current across two fans in parallel to consume all available current from the solar panel, what is not needed will simply not be delivered.
The only mild concern from the question is the 5 Volt rating of the fans compared to the 6 Volt capacity of the solar panel: Realistically, a 5 Volt rated fan should work fine in this specific situation, because once the fan starts drawing current, the solar panel's voltage will drop due to its internal resistance. Motors (i.e. the fan) are pretty resilient to slightly higher than rated voltage as well. |
H: How exactly do all FPGAs work together on this board to carry out high speed calculations
The board I am referring to is called "Merrick 3" from "Enterpoint (ltd)". The web page can be found here: http://enterpoint.co.uk/products/asic-development-high-performance-computing/merrick-3/
I can see that it uses PCIe and has a lot of FPGAs on the board itself. All these FPGAs work together to carry out calculations at very high speed. What is not clear to me is, how is the data coming into such a board structured? Does the main device on the board have somesort of state machine that helps it analyze incoming data and figure out what type of calculation needs to be done with the data?
The other thing not clear to me is how exactly does the board make so many FPGAs work together to achieve result of calculation? Can a Graphics card be made this way?
AI: The board simply provides an array of FPGAs and optional SDRAMs with "generic" connections among them as shown in the block diagram. As delivered, the board doesn't do anything at all (except consume power).
It is up to you, as the end user, to write HDL code for the FPGAs, either individually or collectively, that makes use of the on-chip and off-chip resources to solve whatever problem that you have.
Yes, you could make a very impressive graphics card out of this, but you would have to add a small amount of hardware (via the expansion connector at the top) to support the specific display interface you want to use.
To use this board, you would need to first get a (more) detailed block diagram of the resources on it, and then figure out how to "map" a hardware architecture for your problem solution onto it. You will need a copy of the Xilinx FPGA development toolchain; there's a free version, but for a project of this magnitude, you'll probably want to pay for the full version. You then write HDL code (e.g., Verilog or VHDL) to implement the logic you've mapped onto each FPGA. In some cases, you'll have identical (or nearly identical) code installed on all of the FPGAs, creating a mesh processor of sorts. In other cases, you'll create a "pipeline" of FPGAs, with each one working on a unique part of the problem.
You will also need to figure out how to get your data into and out of the board. You might do this by writing a driver for the host PC that does this via the PCIe interface, or you might interface the board to external hardware via its expansion connector.
Needless to say, any project involving this board is a major undertaking, but it's nice to know that it's there if you really need it. One application for this board is to test algorithms and their hardware implementations prior to designing a full-custom ASIC for mass production. |
H: Using Single Ended Output with Differential Input by Grounding one Input
I am making a frequency generator using the AD9833 (programmed from the PIC16F876). I wish to use a Programmable Gain Amplifier to adjust the signal level before being sent to a power amplifier (common collector coupled to class AB Push Pull). I have found several PGA's which fit the bill, for what I want, BUT...
The output from the AD9833 is single ended. All the PGA's I have found which fit my requirements use differential input. So my question is:
To use a differential input with a single ended device can I just ground Vin- and put my signal on Vin+ ???
This does stand to reason, but is there anything I have overlooked?
AI: AD8521 single ended input: -
It is a true instrumentation amplifier so it will work from a single-ended source as shown above. The circuit also shows how to connect to provide a differential output but this is irrelevant to your question. |
H: Battery powering an unknown DC motor
I know nothing about motors. I have DC motor (sealed in a casing) that uses 6v/12v 1a (mains switching power supply) with 2.1x5.5mm DC connector. It has variable speed controller, reversible direction, and can operate at between around 5-100rpm.
The only available spec states it can be used with powersources of 6v to 12v. Presumably too high a current could damage it though?
I've used it safely with P9 batteries but they go flat too quickly.
What batteries do you think it's safe to use this with? car batteries? Lawnmower batteries?
AI: You don't need to worry about the current input, the resistance of the motor (which can be obtained using V = IR : 12V = 1A*R => R = 12 Ohm ) will limit this. What ever 12V battery you use will only supply 1A at that resistance (V = IR again). A larger battery will last for a longer amount of time because it has more stored charge (measured in Amp Hours). Just make sure you don't use to much voltage. If you use a higher voltage than stated you WILL be allowing to much current to flow (the motor will spin faster but will burn out sooner). Which battery you want to use will depend on how long you want to use it for. For example: if you buy a 20 AH battery @ 1A it will run for 20 hours. |
H: What can be causing output voltage to drop on LT1763 with very little load?
On a breadboard, I am using an LT1763 5V regulator connected as per the "Typical Application" diagram on page one of the datasheet (LT1763 DataSheet). From a benchtop power supply I give 12V at the input and measure a steady 5.011V on the output.
Now, if I add a 10K resistor between the output and ground (which should only draw 0.5mA), the output voltage sinks to around 4.8V. I put an ammeter on the input line and can see that the regulator is only drawing well less than 1mA. This regulator is rated to 500mA.
I swapped out a 3.3V regulator and see similar behaviour (output voltage drops to well below 3V with the resistor applied). I moved around to another location on the breadboard and still the same. Checked all the capacitors on my Fluke and they are all good. Tried different input voltages from 6-15V and the behaviour is the same.
There is nothing else connected to this regulator and I am completely stumped.
Any ideas as to what I am missing and why the voltage could be dropping so much?
AI: It could be oscillating. It's difficult to ensure short connections unless a PCB is used. |
H: Reducing noise in an audio amplifer using opamp
I am trying to make an audio amplfier using an opamp for a project. It works kind of okay but the only issue is there seems to be a lot of noise in the output of a 0.5 watt speaker. I have tried changing the various capacitor values but there still seems to be noise. Whts the best way to bring down this noise in the circuit? My circuit is identical to the one http://www.elexp.com/t_audio.htm. Could someone please help me out?
The input is from my laptop jack output . Could this cause any ground issues which cause noise?
AI: With the exception of power op-amps, op-amps are not suitable for driving loudspeakers. The impedance of speakers is too low. You need a power amplifier chip for driving speakers, or to add a class B emitter-follower output stage made using two complementary power transistors.
Some op-amps are much more noisy than others. They produce noise and it cannot be eliminated; it is inherent to the op-amp. If you're doing audio work, and the circuitry doesn't have to be very low power, use an audiophile op-amp IC like LM4562 or the cheaper workhorse that is nearly as good: NE5532.
But neither of those will drive an 8 ohm speaker, or even a 32 ohm headphone speaker.
Also, do not expect to get anywhere near the 0V and 9V power rails with the signal swing. It's not realistic. Even if you get an op-amp that can do it, the speaker-driving output stage will not. I wouldn't plan on more than a +/- 2V displacement from the 4.5V middle bias, staying several volts clear of either power rail.
I sketched up the circuit below to illustrate the class B emitter follower output stage idea. The op-amp is basically used as a buffer with a modest voltage gain of 2 to interface the input to the output stage. You don't need a high gain because the available voltage swing is not so high. The output stage will only swing the voltage on the speaker to about +/- 2V before clipping. If the input signal is already +/- 1V, the gain headroom is only 2!
Note how everything is very similar to your original schematic, except that we have added the output stage, connected the feedback resistor R2 not from the op-amp output, but all the way from the output stage. This includes the output stage in the feedback loop, and so the feedback loop will cancel some of the distortion introduced by the output stage, such as its crossover distortion.
We still have serious problem here in that the output stage's input impedance is still too low for the op-amp! It's not nearly as bad as an 8 ohm speaker, but look at those 470 ohm resistors. Basically, they have to be considered in parallel, and so the input impedance is only about 230 ohms! Their values can be raised, but this cuts into our already limited voltage swing. We can fix that by using pairs of transistors in the output stage, to increase its current gain.
I can think of an op-amp off the top of my head which can handle this impedance as it is: the NJM4556. The op-amps on this chip can drive 150 ohm loads.
simulate this circuit – Schematic created using CircuitLab |
H: Circuit that switches one led or all three
For an analog photo enlarger (yep, that vintage stuff) I own, I would like to build my own lightsource. For the prototype I found 3 colored super bright led panels they use 12V
The problem is that I need to turn on the lights in a specific setting:
The Green Led source OR
The Blue Led source OR
The Red led source OR
All three at the same time (Green Red Blue, thus delivering white light).
I know how to put the lights on power, how to solder them on a board, but I have no idea what a smart solution should be for such a circuit, what kind of switches I need. The solution must provide ONLY the settings as described. So e.g. a Blue and Green at the same time is not allowed.
some background information: The black and white photo paper is sensitive to blue and green light, but in a different manner. By mixing both color's exposure times I can influence the contrast and the tone of the result. The paper is insensitive to red light, that enables me to project the image on the paper without starting the exposure process. The white light (RGB) is used for focussing purposes.
AI: With the LED panels, you shouldn't need any sort of current limiting resistor or special current driver source - just connect to 12V and go. I can't say they are the highest quality, but they should work fine for what you are trying to do, although, I think the using RGB LEDs would work better as the different colors would blend better to form white than these separated panels will.
I think this could be solved very easily using many different methods. The best method for you will depend upon what you know how to do. A simple microcontroller with a couple of external buttons and transistor switches would work flawlessly, but if you don't know how to program, that is not a good route. A few logic gates driving transistors with button inputs would also work fine, but I imagine you would have already done that if you knew how.
If you would be interested in seeing a simple logic circuit, let me know and one can easily be provided.
But what about using a couple of different simple switches. Take a look at this circuit:
Switch 1 is 6 pole rotary switch. It uses rotating knob to connect the main input to one of the 6 outputs. There are many types of rotary switches with many poles (number of contacts). You will need at least a 4 pole switch, but a 6 pole switch may be better. I'll explain why in a minute.
Switch 2 is a triple-pole, double-throw switch. It has three different poles, and has two ways to "throw" them. If the switch is throw in one direction, all three LED box positive leads are connected to 12V, so they all three turn on. If it is thrown in the other direction, each LED positive lead is connected to one of the poles on the rotary switch.
If using a 4 pole rotary switch, pole 4 should be left open - this would be all LEDs off. Pole 1 would go to LED 1, pole 2 goes to LED 2, and pole 3 goes to LED 3. As you turn the knob, a different LED will be powered. There are two reasons why a 6 pole switch may be better. First, there could be an off state between each of three LED off states (1 ON, all OFF, 2 On, all OFF, 3 On, all OFF). Secondly, some rotary switches are not completely off in between states, meaning that as you turn the knob, the two adjacent LEDs will both be on for a moment, and I don't think you are wanting that to happen.
The great thing about using the 6 pole rotary switch in combination with the 3PDT switch like this is that no two LEDs can be on at the same time - it's either none, one, or all of them. The down side to using the rotary switch is that you can just select an LED bank to turn on, you might have to cycle through the colors depending on the current state of the switch.
One way to avoid this is to use a third "main power" switch to disconnect power/ground to the whole thing while you select a specific color with the rotary dial. Since you are working with color sensitive paper, this might be the best way to go.
A different way to do it is to replace the rotary switch with three common single-pole, single-throw switches like this:
With this setup, you can easily choose which LED bank to turn on. The bad thing is that you could accidentally turn on more than one at a time if you aren't careful...
Of course, no matter what you do, the switches need to be at least rated for 12V DC and as much current as the LEDs are expected to draw.
There are other mechanical switches that will select one while automatically deselecting other inputs - like how a lot of old RCA selectors used a spring loaded lever to select between your VCR, Nintendo, DVD player, etc to input into the TV RCA jacks. But again, these switch selectors typically allow more than one input to be select as they change states. |
H: Cortex M3 (ATSAM3N4B) Peripheral DMA read from SRAM ok, FLASH fails
I've stumbled across a peculiar problem with my PDC (Peripheral DMA Controller) where using the PDC to transfer a constant string from flash over UART 0 seems to produce an unexpected result. The correct number of bytes is sent but they are all zero.
The string is defined in the global namespace as follows
char* str = "Hello world!";
I only send it once at the start of main like this:
UART0->UART_TPR = str; // PDC transfer pointer
UART0->UART_TCR = strlen(str); // PDC counter
UART0->UART_PTCR = UART_PTCR_TXTEN; // PDC enable for UART 0
which sends me 12 zeroes over UART on startup.
Now, if I copy the string into an array that is in function scope:
int main()
{
// ... some initialization stuff ...
char buffer[100];
int i;
for (i = 0; i < 100 && str[i] != '\0'; ++i)
{
buffer[i] = str[i];
}
buffer[i] = '\0';
UART0->UART_TPR = buffer; // PDC transfer pointer
UART0->UART_TCR = strlen(buffer); // PDC counter
UART0->UART_PTCR = UART_PTCR_TXTEN; // PDC enable for UART 0
// ... other code here ...
}
This one sends me the string "Hello world!" over UART + one random character which is easy enough to fix.
My question is, why did the first method not work?
The datasheet states that the PDC can access any of the on-chip memories, so what is going on with Flash?
Using SAM-ICE I've confirmed the obvious:
The global variable's address starts with 0x004..., meaning that it resides in Flash
The local buffer address starts with 0x200..., menaning that it resides in SRAM.
This problem is happening on a commercial prototype board. I do have a SAM3N4C evaluation kit board that I can rewrite the code for if you require it in order to help me but I would like to avoid that if possible.
The datasheet sections that are of interest are the following:
Section 10.5 : ARM Cortex M3 -> Memory model (10.5.2 and 10.5.3 in particular)
Section 22 : Peripheral DMA Controller
Section 29 : UART (if it is not enough information look at 30, USART, it might give some clues).
I'm not sure what to think since I'm only accessing bytes so endian-ness and alignment shouldn't be a problem. Also, the flash section in the datasheet also says that the Flash can be read in bytes so I don't see a problem. Hence, I'm turning to the community for help. Thanks in advance.
AI: It seems that I did not read the section 22.2.3 of the datasheet indicating that the PDC is not connected to the Internal Flash.
My apologies for wasting the communities time. |
H: Its a good practice use dc-dc converters and linear regulators in the same design?
Its a good practice use dc-dc converters and linear regulators? Or its better don't mix them?
Better use all linear tecnology or dc-dc converters in "cascade" or dc-dc with multiple outputs?
AI: The short answer: Yes, it is fairly common to mix different types of regulators in the same design.
The long answer: It totally depends on what you are trying to do. Switching regulators are going to be more efficient, but linear regulators are going to be less noisy. If you are working with noise critical applications like audio or video processing, you might have to use linear regulators just to keep the signal from being so noisy.
Cascading regulators can help - using a switching regulator to drop most of the voltage, then a linear to create the desired level - but even this might produce too much oscillation on the power line from the switching frequency. This can often be controlled with a ferrite bead or other passive filter, but sometimes, straight linear is the only way to go.
On top of that, switching regulators are typically more expensive and use more components than linear ones, so when efficiency isn't an issue the component cost factor may be the deciding factor. However, as noted by AndrejaKo, efficiency does have a big impact on operational cost, and additional cooling consideration may need to be taken when using linear regulation due to the excessive heat dissipation which will also increase cost. |
H: How to use integration or differentiation to optimize frequency in achieving a specific phase angle?
Question:
With source voltage kept constant at 8V peak to peak vary the frequency until the phase angle "theta" Vr referenced to Vs is approximately 45degrees. Record the Vpp value across R1 and the frequency at which "theta" is equal to 45degrees.
Situation:
For clarity I will call R1 the resistance in ohms and Theta Vr the phase angle.
I can approach this two ways from what I know. I could use my simulator and increase the frequency step by step. At each time I would have to figure the reactance and perform the following calculation to determine theta. This process would be very long to get an approximate answer for the frequency.
Theta Vr = ARCTAN(Xc/R1)
Xc = Reactance of the capacitor "ohms"
R1 = Resistance "ohms"
Theta Vr = "Theta" Phase angle of Vr referenced to the Source Voltage (VS)
NOTE:
With the source set to 8Vpp and frequency set to 1kHz Theta Vr = 78.27489 degrees.
With the source set to 8Vpp and frequency set to 1kHz Theta Vc = 11.72511 degrees.
The other way I thought would be to derive a formula that resembles a optimization problem. Derivatives will solve for which the slope is zero. So it would seem I could approach this the same way when solving for the frequency.
Finally, lets say we want to change R1's value and repeat this procedure. It would seem that there has to be a generic expression where X is in ohms and Y is in frequency so this calculation is much less tedious.
Any ideas?
Here is a screenshot of the circuit for clarification.
Here are the parameters of which I set my AC source to.
AI: The complex voltage phasor at the resistor is
$$V_R=V_S\frac{R}{R+\frac{1}{j\omega C}}= V_S\frac{j\omega RC}{1+j\omega RC}$$
For the capacitor we get
$$V_C=V_S\frac{\frac{1}{j\omega C}}{R+\frac{1}{j\omega C}}=V_S\frac{1}{1+j\omega RC}$$
For \$V_R\$ and \$V_C\$ to have a \$45\$ degree phase shift with respect to \$V_S\$, we need to have equal real and imaginary parts:
$$\omega RC = 1\quad\Rightarrow\quad f=\frac{1}{2\pi RC}$$
Of course there's always a frequency-independent phase shift of \$90\$ degrees between \$V_R\$ and \$V_C\$. |
H: How will the output of a 12V transformer wall wart differ from that of a 12V SMPS brick?
I have been working on a project to drive an electric door strike from an Arduino shield of my own design. Actually, I'm using a Freetronics Eleven and not an official Arduino, which is relevant because the Eleven accepts a wider range of input voltages-- up to 12V.
So, since the data plate on my door strike says it needs 12V and only 450mA, I figured I could drive the strike solenoid using power from the Vin pin of the shield's power header, using a SMPS brick that puts out 12V at up to 2A.
Well, the short version of this story is that the power from the brick only works sometimes. After carefully measuring the power at the terminals of my shield and verifying everything to be exactly in spec, I thought perhaps I simply had a bad door strike, so I procured a replacement.
But the new strike misbehaves in exactly the same way.
After some digging around in the junk bin, I found the 12V transformer wall-wart that originally came with my first door strike (in a kit). I plugged it in, and lo and behold it actuates the strike reliably every time. So of course I measured that beast's terminals and found it puts out ~12.4V-- no great surprise at the slight difference from the data plate, but is that .4V really the difference?
I try using my bench supply to see... Nope, still flakey at 12.5V from the bench supply. In fact, no perceptible improvement all the way up to 14V which is the maximum the strike is rated for.
But, that 12(.4)V transformer works like a champ. SO my question: What is the difference (to a solenoid) between the output of a transformer (rectified to DC of course) and the output of my switch-mode power supplies? Is there perhaps some surge current coming from the transformer that the SMPS doesn't produce?
Oh, and if I fab a cable that lets me plug the transformer into my Eleven (and thence through the shield Vin to the strike), is it going to toast the regulator on the Eleven? (It's only slightly over the 12V spec… but…)
Here is a picture of one of the strikes in question:
You can't quite make it out in the pic, but the strike came with a capacitor soldered across its leads. I presume this is for snubbing voltage spikes when the solenoid is de-energizing?
Edit: Strike plate is manufactured by HAI by Leviton, model 79A00-1 12-Volt DC Electric Door Strike.
AI: Dunno about the HAI Electric Strike, but yes, the inrush current may be 2 or 10 or 40 times the hold current. 4.5A rather than 450mA.
Not because the coil current is greater when the plunger is outside the coil, as is the case for AC solenoids.
Rather, because the hold-in current is artificially reduced, either by using a separate hold-in coil, or by switching a current limit into the circuit. You do this to get a good pull-in (what you are not getting) but not wasting power and burning out the coil when the door is left unlocked.
A simple tranformer plug pack had no effective limit to current supply: if you shorted it out for long enough, it burned out. A modern switching power supply does have an inherent current limit: if it doesn't burn out it will still only transfer the rated current. |
H: How do I hijack a reading from the circuit of my digital meter
I have a tri - meter (ph, ppm, temp) that reads and displays readings on three LCD screens. I'm trying to hijack the measurement at some point in the circuit and read it in through on of the inputs on my Arduino. Can anyone tell me where I might start by looking at this circuit? The ph meter (left has only two wires) the ppm meter, apears to have 5, hot, return and three others. I'm assuming the signals are run through some sort of op amp, then displayed on the screens through on of the three logic chips.
AI: You have received some excellent answers on intercepting the data in the digital domain but it may also be worth considering using the analog signals presented at pins 30 and 31 on the ICL7136. An adantage to this is only having a pair of lines to connect per device and probably a simpler software interface. Some things you'd need to check are:
Make sure attaching a small piece of shielded wire and the ADC channel doesn't interfere with the accuracy of the existing readings.
Check that the output voltage swing is sufficient to give enough resolution for your application with the AVR's ADC.
Possible solutions to a lack of resolution would be to add some extra signal conditioning and/or use a higher resolution external ADC. It's another avenue worth investigating depending on your requirements. |
H: How to escape redundant stated when using J-K Flip Flops?
I've designed a counter using three J-K flip flops, but I have two redundant states. How can I ensure that the system has a way to escape these states if they occur?
I've tried searching for help on the internet, but all of the results I found either skipped around the topic or didn't use J-K FFs.
The states being counted through are 000, 001, 010, 100, 101, 111 (first digit = A, second = B, third = C).
The circuit is:
Ps, please ignore the AND gate leading to Z.
AI: It's very likely that the unused states transition within one clock to a valid state; you should check this, but it looks like it to me.
In general, to make sure you get the behavior you want, you should include the unused states in the state diagram up front, and design the system so that they eventually lead to valid states under all circumstances. |
H: How to Calculate the charge/discharge power of a battery?
I need to measure the discharge power of a battery in general.
At the end i want the maximum charge/discharge power as a function of the state of charge(SOC).
So i need a curve that looks like the figure that is displayed here.
I already calculated the power as a function of the SOC but i am not sure if my method is correct.
Lets assume we are looking at a lithium ion battery. I found two ways to calculate the power.
The first one was simply using the voltage curve as a function of state of charge for different C- Rates. Then multiplying the Current with the voltage and getting my power.
P(SOC) = U(SOC) * C-Rate.
The second method was using two graphs of a battery the voltage as a function of the SOC and the internal resistance as a function of a SOC and then P(SOC) = (U(SOC)^2)/R(SOC).
AI: The first method calculates the power delivered to the load, the second one calculates the power dissipated (wasted) in the battery itself. I suspect you want the first one.
Are you sure you are interested in power and not energy? Or in remaining battery capacity in ampere-hours? |
H: Convert between dBA, dBV and RMS values
How do I convert between dBA, dBV and RMS values? For example, I have used a current probe (clamp) with a gain of 100mV = 1A to measure a series of currents in dB and I would like to know the equivalent RMS current values.
AI: I'll assume dBA is for amperes and not the 'A weighted' dB sound pressure level measurement.
Zero dBA will therefore mean 1A RMS and 6dBA will mean 2A RMS. Strictly speaking 2A is closer to 6.021dBA but everyone accepts that if you double the current (or voltage) it increases by 6dB
0dBV is 1V RMS and by the reasons above 2V is 6dBV
RMS values are always implied unless otherwise stated.
Calculating: if your meter read 13.5dBA, divide by 20 to get 0.675 and take the inverse log (base 10) to get 4.732A
Or dBA = 20 log(I)
EDIT - if your meter read 13.5dBV it actually measures 4.732V and if your clamp has a gain of 100mV per amp, the current flowing will be 47.32A. All values RMS. |
H: Power Supply Design - Multiple Voltage Regulators
I'm trying design a benchtop DC power supply for powering small projects, breadboards, arduino, etc. This is a list of what I want from it:
Fixed voltage rails for 24V, 12V, 9V, 5V & 3.3V
Edit: Current requirements: 1A will be alright, 2A I'll be happy with and anywhere close to the full 3A on offer from from the laptop power brick I'm using (see below) will be great.
Variable voltage rail from ~0V to ~24V
Pulse width modulation on the variable rail
Voltmeter panel on the variable rail
Power on indicator LED
USB ports for charging USB devices
(Other stuff that's not related to this question such as selectable
methods for dealing with transient voltage spikes from using PWM to
power inductive loads, adjustable PWM frequency ranges, etc)
I will use a 240V AC to 24V DC laptop power brick capable of outputting 3A.
To produce the desired voltages, I intend to use a linear voltage regulator for each rail, each taking 24v input from the power brick. An overview of my intended setup is shown below.
The PWM circuit I'll be using will be powered from the 12V rail. The USB ports will come off the 5V rail. The power on indicator LED (not shown) will most likely come off the 3.3V rail.
Here are my questions:
I'm assuming the voltage regulators should be in parallel, each
taking the full 24V input, even though there will be a large
difference between input and output for a few of them (eg 24V to
3.3V). I thought about putting them in series so that the 12V output of the first regulator would feed the 9V regulator which would feed
the 5V regulator and so on, but the circuitry of each regulator
block in my diagram above would divide away some current, leaving me
with very little of the 3A max input for the lower voltage rails. Is
this correct? I'm also assuming that the larger reductions in
voltage necessary for the parallel arrangement as shown will produce
more heat than in series, but each regulator will have a nice fat
heatsink and the whole thing will be enclosed in something with at
least a fan or two and plenty of holes for ventilation.
The variable voltage rail will be controlled with a potentiometer
into a variable voltage regulator (LM350). Should I use different
fixed voltage regulators for my fixed voltage rails, or use an LM350
for each, and set their outputs with either fixed resistors or trim
pots?
As the laptop power brick I'm using outputs 24v already, shall I
wire that directly to an output terminal for my 24V rail, or should
I also put a voltage regulator in there? Ideally, there'd be no
point regulating 24v to 24v, but I'm not sure how reliable the
voltage is from a laptop power brick. I'm not even sure you can get
out of a regulator exactly what you put in - there must be some
voltage dropped along the way. If necessary, is there another way I
could ensure a constant 24v output?
I saw a tutorial somewhere a while ago where someone hooked up a
voltmeter to a psu, but the instructions mentioned using a 9v
battery and a relay to power the voltmeter rather than drawing power
directly from the internals of the PSU. Should I do this? There was
no reason given in the tutorial I read. As mentioned above, I was
going to draw power from the 12V rail.
Is there anything missing that could be considered essential to the
design of a power supply? Any kind of safety features? The LM350
appears to be rated for 3A and has inbuilt overcurrent protection.
I'll also be adding fuses to each rail. Will this be adequate in the
event of a short circuit within any external load (eg poorly wired
breadboard, etc)
AI: I agree with others that switchers are a better choice in terms of efficiency, but they can be somewhat complicated to deal with if you're inexperienced, and there can be lots of weird effects that aren't immediately obvious (precharge sinking, beat frequencies, etc.) that can make life difficult. Assuming you've figured out your power dissipation and know how much current each rail can deliver, if the linears will work for you, stick with them (at least for the first pass).
If you're trying to achieve a variable-amplitude square wave output on your adjustable rail, the chopping may introduce noise into the main 24V rail, which could show up on the other rails. You may want to have an LC filter between the main 24V rail and the regulator input to provide high-frequency isolation, and will probably need extra capacitance on the adjustable regulator output (bulk electrolytic as well as low-impedance ceramic) if you expect the square wave edges to be sharp.
1, 5) There are some dangers with your scheme.
Power dissipation in the linear regulators will be
\$(V_{out} - V_{in}) \cdot I_{out} \$
which is significant, especially for the lower output rails. 78xx-type regulators have built-in thermal protection around 125°C, and (without heatsinking) a junction-to-air thermal resistance of 65°C/W. Your thermal management will be challenging.
Another potential problem - if the series-pass element in any of your low-voltage regulators fails or gets bypassed (shorted), you'll present the full 24V input to the output. This could be catastrophic to low-voltage logic. You should protect your low-voltage rails with SCR crowbars that can sink enough current to put the DC/DC brick into current limit and collapse the 24V rail (they'll need big heatsinks too). Fuses are unlikely to be good protection since the 24V brick likely isn't stiff enough to generate the \$I^2 \cdot t\$ needed to blow a fuse.
2) Whatever floats your boat.
4) Meters aren't huge loads. Just use one of your rails.
3) Correct - all regulators have headroom requirements. If you want the maximum 24V out, you'll need a direct connection, and will have to rely on whatever intrinsic protections the brick will provide you. |
H: How good is coaxial cable?
My question relates to the accumulated AC voltage that will appear on the screen of a length of coax:
If the cable is properly terminated at one end and fed with data (or any signal) at the other end, what will be the voltage on the screen relative to ground? Will it be ground potential(?) or will it be some other potential(?), and if so, will it be potentially acting as a "radiator" of the data?
AI: Plant leakage is a well known effect - The system of cables and connectors in distribution systems is known as "plant" for some reason - and causes signal to leak out and be received via antennas.
In an ideal coax, the wave travels between the conductors and imposes local current eddies and voltage nodes along the length of the transmission line, but most notably on the inner surface of the outer conductor and on the outer surface of the inner conductor (the skin effect). Again ideally, no signals that travel on the outside of the outer conductor can interact with the signals on the inner surface of the outer conductor.
Plant leakage arises from the divergence from this ideal, when you use wound or wrapped coax, poor connector termination and also mismatched termination loads.
In your drawing above, assuming the termination also is properly shielded, the return signal should travel along the inner surface of the outer connector if the system is ideal. So you shouldn't actually see any radiation. Evidence of this is how non-coaxial waveguides (TEM- mode) work - everything flows along the inner surface and there is very low leakage.
If this is beyond a hypothetical situation and you are seeing leakage, it can arise from the quality of the coax, if it is solid foil or braided, and that depends on the frequency you're driving it at too (wavelength vs. mesh size). Connector shield continuity, termination matching all are radiation points. Also, the attached eqt. on the receiving end may inject a current mode return signal into the grounded shield causing the whole outer surface to act as an antenna and if this is a signal derived from the feed signal (amplifier power rail bounce as one example) then it might appear that the coax is leaking.
In general cable television plant leakage arises because of the less expensive cables they use (they have many many miles/KM installed cost really matters), the difficulty in maintaining a connector over many years and damage, nicks and knicks etc.
There are some systems that use gas dielectric and solid conductors that transport 10's of MW to antennae with almost no leakage so ideal performance is approachable. |
H: What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?
I am trying to figure out some basics of digital electronics. We have all seen the squared graph of the computer clock signal:
I have read multiple articles on the Internet and still can't figure out whether the moment of signal value switch (I guess on the graph only approximated as point) is important. It would mean it represents the interval when a circuit gets feeds from the inputs and is expected to propagate the values to the outputs, during the interval and the periods of the stable signal are used for something else?
Or the edges are not important but the periods of the stable signal are and the clock signal could be considered as only one additional circuit input, with high or low voltage set? It would mean the circuit starts e.g. reacting on other inputs when the clock signal is set to 1 and it is expected to get values on the outputs somewhere in that clock cycle - when the clock signal is 1 or 0 right after that?
Only the second option seems logical to me but internet authors regularly write that something is expected to happen on the rising edge, and that a circuit should get its outputs in the interval? That is only a term for saying that signal is set to high now?
If the other option I favour is true look at, for example, a counter register made of a single JK flip flop with its inverted output feeding its J input. It is expected to toggle from 0 to 1 in every cycle. If the circuit should start reacting on its inputs when the clock signal becomes 1, what if the result propagates to the outputs while the clock signal is still 1 and there is enough time to propagate values through the whole circuit once more while the clock signal is still 1 in the same cycle, and toggle the counter once more? I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough?
AI: You are right. Edge triggering is just a much narrower form of level triggering, and depends on timing. Inside an edge-triggered device, the changing clock edge is just turned into a pulse which causes it to accept the inputs: a level trigger! But the level trigger is very short. It must be so short that the outputs are not able to propagate back to the input to do any harm in the time that the edge-triggered pulse appears and disappears.
Edge triggering would not work if signals propagated instantly through wires and had unlimited slew rates.
Also note that clocks can be divided into phases to solve problems where this isn't fast enough.
A master-slave flip-flop is an example of clock phasing. It splits the clock signal into two phases by reacting to both rising edges and falling edges, but differently. Input is accepted on a rising edge into an input latch, and then on a falling edge propagated into a second latch where it produces output. |
H: Multiplexing with or without transistors
I'm doing something in where I need to multiplex 6 7-segment displays. About doing it, I found things like this:
And things in where the same thing is done without the transistors, just by connecting the cathodes directly to pins of the microcontroller. What's the difference? When should I need the transistors? Is it because the microcontroller couldn't handle current for all the LEDs?
I'm using an Arduino with an ATMEGA328, if that's needed for something.
AI: Many MCUs won't handle the current for seven segments unless a transistor is used. You might be OK with the AVR (40 mA maximum per output, IIRC), but you need to check it, and the total current. |
H: Are additional smoothing capacitors required off of a voltage regulator
This is a subset of a circuit I am building to run motors off a PIC 16F884:
simulate this circuit – Schematic created using CircuitLab
I noticed last night as I was drawing up my schematics that I might have redundancy in the use of the smoothing capacitors off of the VDD/VSS pairs on the PIC.
My question is: Does the 0.1uF cap off the 7805 have the same smoothing effect for both VDD/VSS pairs thus eliminating the need for the two extra caps off of the PIC?
simulate this circuit
AI: Smoothing caps need to be as close to the power pins as possible of the target ICs. Trace parasitics add a whole bunch of invisible components in series with the power and return nets. It's a difficult concept to visualize from a schematic standpoint, since a schematic shows logical relationships (nets) but not physical relationships (how far apart parts are, how convoluted the routing is, etc.)
Unless your PCB layout is such that the regulator, capacitor and power pins are fractions of a millimeter apart, you'll need the local capacitors.
As a rule of thumb, it's always best to add decoupling everywhere you think you may need it on a layout - it's easy enough to not populate parts later, and much harder to add a cap where there isn't room for it. |
H: Make two bluetooth modules communicate directly?
Can one buy two cheap (and identical) bluetooth chips and make them talk to each other without needing a PC or a mobile phone?
I'm guessing the answer is a basic 'NO', but I might as well ask.
i.e.:
I want to design a PCB and make a number of copies that can talk to each other, but also to a PC or mobile app.
Bluetooth still seems good for the device to app case,
but when you take the mobile or the PC away, can you leave it with the devices paired to each other and not require the mobile to host it?
Can this be scaled further to make a basic network of bluetooth. ie: if i put 5 of these one of them pair to all the others? I don't have very high bandwidth requirements.
Like I said, probably not, but it is called "pairing", which I feel implies that the devices are equal somehow.
So, what exactly is in the mobile phone or PC or bluetooth dongle that makes it different from a bluetooth device?
Also, if it just so happens that one can recommend a module, I would be really great to be able to get it for under USD$10 each at volumes. : )
AI: yes, there are many bluetooth modules with serial (TTL) interfaces, some even have built-in MCUs for user applications which you can use as a standalone module without a micro. However, I don't think you can find anything that cheap, the cheapest one I know of is the Roving Networks RN-42. with trace antenna. |
H: How exactly does switched capacitor system work, what exactly is the detail of the primitive that switches
I have been seeing these switched capacitor circuits for some time now and have even seen Z-transform being used to model how these circuits behave. While I can see that there is some capacitor that switches, what exactly is the mystery behind this 3 terminal device one terminal of which comes from some sort of clock. How is this clock generated?
I am wondering how do these things work from within a circuit but don't know how to get a good thorough answer.
AI: Switched cap circuits are typically used in chip design because it's far far easier to get small, high value caps that match each other than it is to get resistors that meet all those same criteria. Until there was a need the circuit technology and theory wasn't developed, once circuits got smaller the need arose and bingo! it appeared.
The relationship between resistance and capacitance in a switched cap circuit is:
\$R_{equ}=\dfrac{1}{Cf_{clk}}\$
If I want to emulate a \$10M\Omega\$ resistor I can do it with a \$0.5pF\$ cap and two switches running at \$200 kHz\$. the switches can be a CMOS transmission gate of 1 PMOS and 1 NMOS. This might take up \$0.001 mm^2\$ in a \$0.5 \mu m\$ process. In comparison a \$10 M\Omega\$ diffused resistor in the same process might take \$ 1.0 mm^2\$. This is a factor of ~\$1000\$. |
H: Should one use resistors to protect an mbed when using it to simulate keyboard key presses
One can use mbed to act as USB Host or as a USB Device. One use of the latter is to have it emulate a USB Keyboard by sending normal key presses. The general page on using mbed as a USB Device is in their handbook here: https://mbed.org/handbook/USBDevice But looking at the photos of completed projects on that page, for example the one below, they do not use any resistors to protect the mbed from power errors coming over the USB connection.
Is that how one should do it? Would it be better to include protection and if so what would the amended schema/diagram be?
AI: As pjc50 said, you can't put resistors in the power or data of the USB without interfering with the communication.
If you want to avoid any damage to the USB port, I'd recommend leaving disconnected the VCC pin of the USB breakout board, powering the MBED with a different power source. You will prevent any shortcircuit due to incorrect wiring. |
H: Stability problem in unity-gain opAmp
As a part of a controlled power supply for hardware-in-loop testing for a student driven project, I had to develop a current buffer (voltage follower) which could source up to 1 A.
I had the (bad) idea of trying to implement this simple circuit:
The PMOS inside the feedback loop acts as an inverter (more V_gate, less V_out), and that's why the loop closes in the POSITIVE terminal of the opAmp instead of the negative.
In the lab I set VREF = 5V and VIN = 7V. I should get then 5V at VOUT, but I obtain this out-of-control output VOUT:
And this is the control signal (output of opAmp, connected to the gate of the MOSFET)
I find similar behaviors under different VREF, VIN and Rloads. Also note that the output of the opAmp is not saturated to any of the rails.
My assumption is that the gain of the loop is too high for keeping the opAmp in stability.
I have some background in control systems and opamps, but I don't know how to apply it to solve this situation...
Is it possible to apply some phase shift network to stabilize the loop?
I would appreciate both "quick hacks" or educational answers!
AI: This is really simple - use an N channel FET and have it as a source follower. You can even use a BJT. The one below has gain due to the 3k3 feedback and the 1k to ground from -Vin. If you don't want gain connect the output directly to -Vin and omit the 1k.
A unity gain buffer on the output of an op-amp is either an emitter follower or a source follower. Simple as that - feedback from the emitter/source back to inverting input of the op-amp.
Additionally, because the source/emitter voltage "follows" the op-amps output signal, the gate/base loading effects are minimal hence when using a MOSFET you don't need to worry about gate capacitance.
Think about this sensibly - Analog Devices or TI or MAXIM of LT - their marketing team are not going to wake up one morning and say to their designers - why can't you design an op-amp that allows someone to add a gain stage on it and expect it to be stable. If they did, the designers would say that they'd have to reduce the performance of the op-amp for it to be stable - just how would that op-amp compete in the market against all the op-amps that take the sensible road and keep building what they are good at. |
H: should I use 2 SPI devices on Arduino UNO/PRO or 2 I2C devices?
I am using a microSD breakout board and the accelerometer ADXL345 https://www.sparkfun.com/products/9836.
each one alone works perfectly fine, but once I put both (sharing pins 11,12,13, but with different CS pins) nothing works.
I'm using another sensor with the I2C which is the BMP085: https://www.sparkfun.com/products/11282
The accelerometer also works in I2C, but that requires pull-up resistors when several devices share I2C.
I wanted SPI as it seemed simpler where i can just specify the CS and everything should've worked.
Am I missing something in the SPI case? Is it better to share devices on I2C rather than SPI?
AI: The choice really makes little difference when you are using the Arduino libraries. You should see the same type of performance.
As for the i2c pullup resistors, the BMP085 board you link to has pullups already on the board, connected to a closed solder jumper. Those same pullups should be enough for both sensors, so you wouldn't need to add more.
But there is no reason the sensor shouldn't work on SPI with a sd card as well. Did you double check that you tied all grounds together? How does it not work? Does it only work for one read/write before failing? Are you making sure you drive both CS pins to a high/low, instead of leaving one as a floating input? |
H: How to calibrate an optical particle sensor (Mie scattering)
I have a very simple sensor that basically emits infrared light (1 micron wavelength in the infrared range). The light scatters off particles whose diameter is of the same order of magnitude as the wavelength (Mie scattering). The scattering angle is approximately 90 degrees. A photodiode is located diagonally with respect to the sensor ( scatter angle approx. 90 degress)
I am trying to find out how to calibrate my device with respect to particle size. I looked through commercial optical particle counters out there, and they don't really explain how they are calibrated. For example, the following is a plot of scattering intensity as a function of diameter, as you can see, there is not a simple relationship between intensity(or photodiode voltage output/my sensor output) and particle diameter.
Does anyone know how commercial particle counters are scaled?
AI: It's not obvious to me if you want to calibrate your instrument to measure the size of your particles, or to measure the concentration of particles in a volume. I'm assuming you want to measure particle concentration, but most of this applies to either case.
I'm not familiar with the measurement you're describing, but the obvious way to calibrate it is to buy samples of powders of known particle size, disperse them in a known volume, and measure the response of the detector. A web page at the University of Manchester supports this method:
"In practise, theoretical instrument response curves are not used for sizing of particles, rather a series of calibration particles of known size are used to determine the response of the instrument over its full size range. A curve is fitted to these measurements to allow sizing of particles which fall between the calibration points."
If the particles you're measuring are not very tightly distributed in size (say they vary by +/- 50% in diameter), then you probably don't need to worry about the ripples in the Mie scattering curve you showed. Just use an average value of the response over the range of sizes you expect in your sample. To calibrate the instrument you'd need a reference sample with a comparable spread of particle sizes.
Generally with a measurement like this there's so many factors that vary between experiments (maybe the shape of the particles, the amount of turbulence in the sample volume, or other sources of reflected light) that a factory calibration from the instrument vendor isn't likely to be very precise. More likely you'll need to start with a reference measurement in your lab, and then make further measurements relative to that. |
H: basic math question about voltage, ohms, resistance
total n00b here. After working on several projects by copy & paste from other people's schematics and code, I'm finally digging in and learning some of the math to know what I'm doing.
If I have a pushbutton (this one, to be exact) that lists max amps as 50mA, and I have a 9 volt battery, the math for the resistor that I need is 9/0.05 == 180ohm, right?
AI: What do you use the push button for? I doubt you need such high current and can easily do with much less, especially when you use it as input for a logic circuit. Although @rawbrawb's 360 ohm will probably work perfectly well, it does draw a lot of current from the power supply. When using a 9V battery, the cell will be drained very quickly.
If the push button indeed is only used for a logic level to drive an opamp or digital chip, a resistor of 10kΩ would already suffice. You didn't share the circuit diagram, that might help in deciding on a good value. |
H: What's an easy way to supply power to a breadboard without using batteries?
There are a number of kits available (for example sparkfun's Breadboard Power Supply USB - 5V/3.3V and Breadboard Power Supply 5V/3.3V or Adafruit's Adjustable breadboard power supply kit - v1.0) but these all come as kits. What is a common and easy of-the-shelf way for a beginner to supply DC power to a breadboard without using batteries?
AI: I have found these breadboard power supplies ($2.12 or so on ebay.com, shipped) very useful for the purpose described:
Jumper-selected 3.3 and 5 Volt simultaneous outputs from wall-wart, USB or 9 Volt battery.
They have a convenient 2.1 mm barrel jack port on board, besides a power button and an indicator LED. You can choose to have 3.3 Volts on one of the power rail rows of the breadboard, and 5 Volts on the other, something I find especially useful.
As a fellow breadboard user, you might also find two of my answers to other questions on this site, of interest:
On "Good Quality Breadboards"
On "“Starter Kit for electronics” - What to buy?" |
H: Custom USB Impedance question
I'm looking at making my own USB cable for a project. The primary issue I'm having is that I'm getting a lot of capacitance in my cable between D+ and D- (400ish pF) which is enough to throw off the signals being read by my pc. Is there an easy way to fix this? I understand this is an impedance matching issue, but I'm not sure where to begin with this one since the capacitance is between two input lines, not one line and ground which is what I remember from my electromagnetics course.
AI: The impedance of the data line is determined by
capacitance between wires and
inductance of the pair of wires.
It's a simple formula and I've used it to make custom cables for high speed data links in circumstances where the wires and overall covering needed to be made from PTFE material to suit high temperature applications. The formula is
Zo = sqrt(L/C) - this is the impedance for a lossless line. Here is a good article.
This tells you that to make a higher impedance cable L needs to grow and/or C needs to reduce. One of the methods is to make the actual conductor a smaller diameter whilst keeping the spacing between conductors the same. Or you can make the spacing between conductors bigger. Below is a picture of an on-line calculator: -
Note that the formula given on the page above (Zo) is exactly the same as the one I gave earlier but it uses the more fundamental properties of wires to give L and C. In other words, permeability and permittivity are built into the equations but the 2nd formula explicity lists permittivity because that will be a variable due to the insulation type.
And here is the link to the webpage for the calculator. Please note that there are several calculators on-line so you can double check other ones.
From memory USB cable impedance is 90 ohms.
And if all this seems to much trouble, just make the wires thinner and space them apart a bit more and see what happens. If it is a Zo issue then things should begin to improve as you do this. |
H: What is the minimum temperature for FR-4 PCBs?
My company is working on developing a product that will go into commercial freezers, so my boss asked me to provide operating temperature specifications for the product. I can find "operating range" temperatures listed for everything but the PCB itself, which is just plain old FR-4.
Wikipedia helpfully lists "Temperature Index" (whatever that means) as 140 C, but there are no indications of a minimum temperature.
I'm not really worried, as I'm sure that the other components on the board will be the limiting factors, but for the sake of completeness, I would like to have it listed.
Does anyone known the minimum operating temperature of FR-4? (And what would the failure mode be?)
AI: FR4 PCB is glass-reinforced epoxy laminate. Several research studies have been published of the effect of low temperatures on such material.
A specific quote from the paper "Dynamic failure behavior of glass/epoxy composites under low temperature using Charpy impact test method" (Shokrieh et al):
it is found that failure mechanism changes from matrix cracking at room temperature to delamination and fiber breakage at low temperatures.
This study applied a temperature of -30oC, not low enough for spontaneous crystalline brittleness.
Another study, "The Influence of High and Low Temperatures on the impact properties of glass-epoxy composites" (Putic et al) takes the temperature down to -50oC, and finds the appearance of brittle cracks in the material at such temperatures.
These are two key assumptions regarding the device touched upon in the question:
The freezer temperature will not reach as low as those used in these studies
There is limited risk of vibration or impact upon the actual circuit board, hence brittle cracks are unlikely but not ruled out
If either of these assumptions is invalid, the material in question needs to be reconsidered. There do exist special-purpose industrial ceramics / alumina PCB substrates designed specifically for extremely low temperatures, typically used for device deployment in space or in cryogenic equipment. Those materials might be more suitable in this case.
The point to note in such environments is the possible fracture of packages, casings and solder junctions for the electronic components on the board, not just the PCB itself.
A commonly recommended procedure for deploying circuit boards in extreme temperature conditions, is to bring the device to the desired temperature in slow stages, thus avoiding any rapid shrinkage or thermal shock to board or parts. |
H: Slowly turn a planisphere at the sidereal rate
My problem is to rotate a planisphere (a star chart) at the sidereal rate.
I will set the planisphere to its initial position manually, then turn on some device which rotates the planisphere on its central axis, to keep it in sync with the current sky at my location. That is, the problem is to rotate a circular, laminated bristol-board (heavy paper) disc once every 23 hours, 56 minutes. The laminated disc may be from 10 cm across to 60cm across, and is fairly lightweight. The disc may be horizontal, or vertical (hung on a wall).
Constraints:
A small, lightweight mechanism is preferred.
Battery power is preferred.
High accuracy isn't needed.
The disc would be rotated\updated once every 10 minutes or so.
I'm thinking that the mechanism would likely be placed at the edge of the disc, not the centre, and a little wheel would be firmly pressed against one face of the disc. When the little wheel spins a full rotation, it turns the disc by perhaps a few degrees.
I prefer simpler mechanisms over complex ones.
Can you provide suggestions for implementing this?
Here is a photo:
AI: My first thought would be to take a battery-operated clock mechanism (available from many suppliers for a few dollars) and replace the minute hand with a disk that drives the edge of your planisphere disk.
For example, to drive a 60-cm planisphere, you would need a drive disk of
60 cm / 23.93447 = 2.5068 cm
Since the basic accuracy of the clock mechanism is very good, the overall accuracy would depend on how accurately the diameter of the driving disk can be controlled (relative to that of the driven disk). |
H: Synchronizing SPI ports for higher data rate
I am designing a new board which uses the NXP LPC4330 (Cortex M4 microcontroller) with a XESS Xula2 FPGA development board. In this design, the Xula 2 has limited I/O pins since it is designed to fit into a DIP-40 form factor. The primary form of communication between the micro and the FPGA is through SPI.
I would like the bus to be fairly high speed, on the order of 80 to 100 Mbps. It might be enough to run a single SPI port at 80 MHz, but since the main clock on the FPGA is only running at 120 MHz (and it drives the SPI interface), I'm not sure that the SPI would work at such a high data rate. The LPC4330 has multiple SPI ports, and one idea I have is to use 2 SPI ports so that each can run at a slower bit rate. There is plenty of room on the Spartan 6 FPGA, but I do not have the I/O pins on the development board to have 2 sets of all 3 of MOSI/MISO/SCK (plus a single CS).
Therefore, I am wondering if it is possible to synchronize the ports on the LPC such that they share a SPI clock. The fast communication only has to happen in a single direction, so I would only need to double up the MISO pin (the micro needs to read quickly from the FPGA, not vice versa). There doesn't appear to be a special mode to synchronize the SPI ports, but I assume that they would be on the same clock domain due to the clocking architecture of the micro.
I realize there is also a multi-port SPIFI (spi-flash memory interface) on the NXP. Has anyone had an experience creating a block on the FPGA which basically emulates a SPI flash?
So my questions are a) do you think this will work? and b) is there a better way to do this?
AI: Use SGPIO.
It contains 16 shift registers with 32 bits each and is very flexible in what it can do. You can chain up to 8 registers or run up to 8 inputs or outputs in parallel. |
H: Faster IO on ARM Cortex-M3 (Sam3x8e) than PIO_SODR and PIO_CODR?
I have a very simple C program that toggles a pin on a Cortex-M3 board (SAM3X8E) with a 84MHz clock speed. I built this using Atmel Studio 6.1.
#include <asf.h>
int main (void)
{
board_init();
PIOB->PIO_PER = PIO_PB27; //Enable PIO
PIOB->PIO_OER = PIO_PB27; //Set to OUTPUT
PIOB->PIO_PUDR = PIO_PB27; //Disable the pull up resistor
while(1) {
PIOB->PIO_SODR = PIO_PB27; //Enable output
PIOB->PIO_CODR = PIO_PB27; //Disable output
}
}
Now when I load this onto the board, and hook up an oscilloscope up to the pin, I see the signal pulsating at about 700kHz. I would have thought that the speed of the cycle would have been much quicker with this minimalistic code.
Is it possible to get a GPIO frequency higher than a MHz using this setup? Is it my build environment that is not producing optimal code? Is it possible to get faster GPIO using another technique?
AI: I don't know the SAM3X family but the Atmel Studio IDE and the UC3 Family from Atmel.
Try adding the Clock Module to your project, configure it via the config_clock.h file, then add a sysclk_init() call to your main and it should be going a lot faster.
The SAM3X by default clocks at 4MHz if I'm not mistaken. |
H: How to read RPM from 3-wire fan - PIC18F4550
I am working a PIC µC project. I am using 12VDC PC fan (Coolermaster) for my application. A part of the project is to return the RPM from the third wire of the fan to an LCD.
First of all, How can I read the signal? Is it a sort of pulses every rotation?
Also, Do I need to use an ADC pin or just a Digital one would suffice?
I found lots of diagrams telling to connect a pull up resistor to +5V. Why?
A sample code of how this works will be helpful.
Thanks.
AI: Reading the signal
The main point to notice is that the tach output from the 3 wire fan switches from 0 to 12V. If connected directly to the input of the PIC it would exceed the voltage rating of the device. Connecting the tach output to a 5V supply through a resistor would not prevent it from exceeding 5V as that resistor would simply form a potential divider with R1 and leave the tach output sitting at a voltage between 12 and 5 volts. A quick check with an oscilloscope or voltmeter would verify this voltage.
To reduce the output to a 0 - 5V pulse suitable for the PIC input you could:
(i) Use a resistor (R2) across the output (a slightly smaller value than R1) to give a maximum 5V at the output (quick and dirty solution) ( R2 should be about 0.7 R1 to give a 5V output)
(ii) Connect a small signal npn transistor - base to the tach output. Connect a pull up resistor from its collector to 5V. Emitter to ground. Take the new tach (inverted) output from the collector to the PIC input line.
(iii) Connect an opto isolator with a pull up resistor to the 5V line
(pin 2, 4 to ground (0V) , pull up resistor from 5V to pin 5. Take output from pin 5. Pin 6 is left unconnected) This circuit will invert the pulse signal but as you are counting pulses it does not matter. It also protects the PIC input from exceeding 5V. |
H: Is mVtt the same as mVpp?
I am designing a driver circuit for S/PDIF, and in a couple different places, like this one, it specifies an amplitude of 500 mVtt. I'm not familiar with those units, and googling gives me nothing. However, I do see it specified as 500 mVpp in a few places, but I want to make sure one or the other isn't a mistranscription. Are they the same thing? Is mVtt a European term perhaps? What does the tt stand for?
AI: Vtt stands for Volts, Threshold to Threshold.
Vtt and mVtt units are used (apparently as differentiating terminology) for signaling systems where digital signals are carried over analog channels, and comparators are used for pulse stream regeneration at the receiving end. This allows a wide range of actual signal voltages to be used for transmission while keeping the specification fixed.
It is not equivalent to Voltage peak-to-peak, in that the actual signal over the medium by definition has a higher peak to peak amplitude than the designed threshold-to-threshold excursion.
S/PDIF is the one technology I can recall off-hand that uses this terminology, but yes, there are others.
Using a 500 mVpp signal for a 500 mVtt channel will cause a failure condition if the channel has the slightest attenuation. However, with S/PDIF this is typically not a concern, as the reception specification is for 200 mVtt, allowing both a high attenuation margin, and the ability to use a variety of waveforms (sawtooth or pulse for instance), not just sine waves.
Not sure why one would want to use a waveform with a higher upper harmonic requirement and thus a higher bandwidth, instead of a sine wave, though. I'm sure someone on the site could explain. |
H: why is wall voltage measuring 175V?
I was trying to use a DM-4100A multimeter to verify a power supply, and I'm not sure I'm using the multimeter correctly. The multimeter is >10 years old too, so maybe it is not working correctly.
When I set the meter to measure AC voltage, with a 500V or 200V max, it reports 170-175V. I was expected more around 120V (I am in the USA). Is 170V an expected voltage, or would that suggest I'm doing it wrong?
UPDATE: It sounds like it may be reporting peak voltage instead of RMS. The multimeter does not seem to have an RMS setting. Can I just take the voltage and divide by 1.414 to get the RMS voltage? I want to do this for the purposes of verifying whether power adapter is still producing the correct voltage.
AI: The manual you linked to, on page 3 says "Average responding, calibrated in RMS of sine wave", so it should not display the peak value of the AC voltage. I would not trust it, or "adjust the reading to RMS" by dividing by 1.4.
I suggest you get another meter, as this one appears to be broken in some way. |
H: Accurately measure relative intensity noise (RIN) using RF spectral analyzer?
I'm trying to measure the relative intensity noise (RIN) of a laser using an RF spectrum analyser. It's a fairly common method (outline: How to measure relative intensity noise in lasers) although I wondered if someone more experienced might be able to help clarify some of the nuances of noise measurement for me.
As I understand, RIN is defined as the mean square intensity-fluctuation spectral-density of an optical signal divided by the average optical power. To measure this, we often put the laser into a photodetector, use a bias-T to measure the DC voltage (which is proportional to photodetector current and hence gives a measure of average power) and connect the AC output of the bias-T into an RF spectrum analyszer.
To plot RIN as a function of frequency, the measured RF spectral intensity values are divided by spectrum analyzer resolution bandwidth (i.e. put into dBm / Hz units) and then divided by the average electrical power
$$P_{avg} = \frac{V_{DC}^2}{50 \Omega}$$
This apparently gives a value with units dBc/Hz or dB/Hz.
dB is a relative scale, so dB/Hz makes sense in that we're measuring AC power at a certain frequency in reference to the DC power. However, dBc/Hz is the power referenced to the carrier and I'm not sure what that is in this case. Additionally, some authors present system noise floor measurements in units of dBc/Hz. Is this wrong since in this case there's no carrier? Or is this a system noise floor with reference to the power from the laser being measured?
Finally, in some cases I find that the trace on the RF spectrum analyzer shows harmonics as a series of peaks (EDIT: my laser is pulsed, so the harmonics are at the repetition rate of the pulses, as expected). The levels between peaks is at the same level as the background level (i.e. when there is no signal input). Can we therefore infer that the RIN at these points (i.e. if we integrate from 10 Hz, say, up to the 1st harmonic) is equal to or less than the system RIN? Or would we need to amplify the signal just to ensure we can see it above the system noise level.
This seems a complex topic and perhaps I'm overthinking it, so any tips or pointers / good references would be greatly appreciated!
Thanks
AI: However, dBc/Hz is the power referenced to the carrier and I'm not sure what that is in this case.
I suspect the carrier in this case is the average optical power, which they may be thinking of as a many-terahertz carrier.
some authors present system noise floor measurements in units of dBc/Hz. Is this wrong since in this case there's no carrier?
It's not clear to me why somebody would choose those units for a noise floor. It may be wrong, but I'd want to see the context where you read it to say for sure.
I find that the trace on the RF spectrum analyzer shows harmonics as a series of peaks. The levels between peaks is at the same level as the background level (i.e. when there is no signal input). Can we therefore infer that the RIN at these points (i.e. if we integrate from 10 Hz, say, up to the 1st harmonic) is equal to or less than the system RIN?
In the RIN measurements I've seen, there are no measurable harmonics, just a single peak related to the laser's intrinsic relaxation oscillation frequency. Are you testing with a modulation signal applied to the laser? Most RIN measurement's I've seen were done with the laser operated CW, and I'd think the results are easier to interpret for a CW optical signal.
In general spectrum analyzers have a noise floor, but I wouldn't call it "RIN", because it is not "relative intensity" --- it doesn't change in proportion to the optical power. The measurement system noise is a fixed "floor" and you can't measure power spectral density below that floor. So whenever the trace is down at the noise floor, you're not measuring anything about the device you are testing, just the capabilities of the analyzer.
General comment
The RIN measurement is fairly difficult to do. Unless the laser has very bad performance you need a very low-noise detector, very low-noise preamplifier, and a very sensitive spectrum analyzer (with a low noise floor). You will want to test the noise floor of your whole receiver system (detector, preamplifier, spectrum analyzer) before measuring your laser to be sure you know when you're measuring the laser behavior and when you're just seeing instrument noise.
Edit
To follow up your questions in comments:
Sorry I'm not familiar with RIN measurements on pulsed lasers. But the units of dBc/Hz make a lot more sense now --- they're just talking about the fundamental of the pulse signal as the carrier.
The measurements I'm familiar with, you're most interested in the peak frequency in the RIN spectrum. I don't think you could do this with a pulsed laser because you'd have to pulse at a higher frequency than the RIN peak, which would also be beyond the modulation capabilities of the laser. But maybe there are tricks I'm not aware of.
I will suggest that for a pulsed RIN measurement, you don't need the bias tee, though you might want a blocking capacitor for the sake of your SA input. The peak of the fundamental of the pulse signal gives you the laser signal power that you'd be measuring the noise relative to.
is it fair to say then that the laser has equal or better noise performance?
I'd say it this way: if the laser noise is too small to measure on your detector/SA system, then the measurement system is not adequate to measure the noise of that laser.
how would you recommend characterising the system noise floor?
Typically, you turn on the photodetector and pre-amp, but don't apply any laser signal. Then take a sweep on the spectrum analyzer, using the exact settings you'll use for your measurement. This gives the combined floor for the detector plus the SA.
You should be able to display this for comparison to your laser RIN measurements by just using the save-trace features of the SA, without any need for calculations. |
H: How does this circuit diagram work?
I don't understand this circuit diagram here, but I'm sure that you can help me out.
I'll explain what I have figured out so far.
EDIT: It's a metronome circuit. Sorry for being unclear about that.
In every circuit, current tries to connect "ground" (-) and "+9 VOLTS" in this situation.
From the top down, 9 volts of current is waiting at the emitter side of Q2 (transistor). I'll get back to that.
On the left, the voltage is tuned down a bit by the R1 , then after it is a variable resistor (R2).
I am lost here. I know that R2 controls how fast C1 charges, and I know that at a certain point C1 will trigger Q1 and Q2 to release the 9 volts (see 2). This 9 volt burst creates the clicking sound.
What I am confused about is:
Why does C1 need to be directly connected to the speaker?
Doesn't some of the current from R2 go to Q1?
How does the capacitor discharge? I imagine that the capacitor will slowly charge up to a point, then let it out (presumably to Q1). When does it let out? Why does it stop it's "charging" routine to discharge?
Doesn't Q1's base run straight to ground? Why is it going to Q2?
AI: CircuitLab allows you to simulate this:
simulate this circuit – Schematic created using CircuitLab
Open the circuit, click on "simulate," and figure out how it works yourself!
Note that I had to simulate the inductance of the speaker (important in this circuit) by inserting a series inductor, as CircuitLab didn't include this in the speaker model.
Separately, the reason the capacitor is connected to the speaker's "top" terminal, rather than ground, is that it needs to see the voltage drop across the speaker, which fluctuates with both how the speaker conducts, and how Q2 conducts; this is what keeps the oscillation going. If the capacitor was connected directly to ground, there would be a single click, and then it would be silent.
Specifically, when Q2 is open, the voltage across C1 will drop to 0 (it will discharge.)
But, as C1 discharges, it turns from an isolator to a conductor (a discharged capacitor works a bit like a wire; a charged capacitor works a bit like an isolator.) |
H: What is the purpose of capacitors and resistors in this USB bus?
Trying to understand the purpose of the capacitors and resistors in this bus powered configuration for the FTDI chip, I think the capacitors are for filtering high frequency noise, not sure what the resistors for though, maybe line termination ?
AI: The series resistors are for line termination.
From http://www.semtech.com/images/datasheet/usb%20line%20termination%20_ag.pdf
The Universal Serial Bus (USB) line termintation is specified in the USB 1.1 specification to insure proper terminations so that signal integrity is maintained. The termination requirement varies depending on what driver chipset is used, whether the port is upstream or downstream, and if the transceiver operates in full or low speed.
When the USB 1.1 specification was written, a series resistor between the range of 28Ω to 44Ω was required. Most USB drivers will require a termination resistor of 16 - 33Ω.
This is in addition to the pullup/pulldowns used for identification.
The caps are used to ensure the line meets the required rise/fall times as well. |
H: Why is the output from this astable 555 the reverse of it's simulation?
The simulator in LTSpice looked OK ... so I moved to the breadboard with an LED (eventually replaced the LED with a buzzer) at pin 3. One more difference in the assembled circuit is the condenser at pin 5 is not electrolytic.
The supply is a retired AT SMPS from my old computer.
The waveform in LT Spice is initially LOW, and subsequently HIGH after a few hundred seconds. The assembled prototype however begins with the buzzer audible.
My impression is, therefore, that cycle has somehow got inverted in assembly. Is this impression correct? What need be done to have the output on the prototype behave as designed?
AI: You did something wrong. I reproduced your circuit in LTSpice and got this:
Output is high for the better part of an hour. Somewhere before 2800 seconds, it dives to zero. The blue trace tracks the capacitor voltage, by the way.
I suspect you forgot to checkbox "Skip Initial Operating Point Solution" in the Edit Simulation Command dialog box!
If I do the same, I get this:
Look familiar in any way?
For reference, the circuit: |
H: What are those black things on the board?
I'm a beginner in electronics, and I'm ignorant of many basic things.
Check out these black things on the board:
These are from a keyboard.
I'm disassembling it and I want to connect my own switches to it. All the connections seem to go to these black things. But I have no idea how to connect to them. How can I do that?
AI: Those black sections are either a carbon-glue paste, or a conductive, carbon-doped elastomer. The carbon makes them (somewhat) conductive, and the rest holds it together. They then make contact by simply pressing against the silver-laden ink traces of the keyboard (in the background of your picture, I would guess).
If you want to connect to them, you're probably going to have to scrape the black paste off the contacts, until you reach bare copper, which you can then solder to.
Are you sure that is a capacitive keyboard? The keyboard membrane in the background looks like a pretty standard pressure-activated membrane switch assembly to me. |
H: Connect 8051 serial port to multiple 8051s
I want to design a project in which one supervisor 8051 communicates with four other 8051s. I'd like the students to implement this project with some server-client view. That means that the TX port of the main 8051 will be connected to all other 8051s.
I want to make sure that there is no problem with fan out or power. I want all 8051s get the same data but decide if the data for them or not. Is it correct to connect one TX pin to 4 other RX pins without any buffering (and vice versa)?
AI: I wouldn't imagine fan-out or power problems so connecting the TX line of the master to four RX lines should be fine. The problem is in the reverse direction, you'll be connecting four TX lines (that are all outputs) to the master's RX line. A couple of solutions come to mind:
Enable the UART receiver on all slave devices but leave the transmit line in a high-impedance state. When a slave has received a message addressed to it set the transmit line as an output, send the message and then go back to a high-impedance state. Some microcontrollers support doing this and some don't because enabling the UART sets TX as an output an RX as an input automatically. If you use this method you'll need a pull-up on the master receive line so it's not floating when no slaves are transmitting.
Use a 4-1 multiplexer on the receive line of the master so that before sending a command to a slave it can select one of the slave TX lines so only one is logically connected at a time.
Option 1 is the way I'd go if using a microcontroller where the UART receiver can be left enabled while the transmitter is disabled. Other options to consider would be SPI and I2C which are both designed for multi-drop communications. Serial (which you can convert to RS232) is probably a nice option for a student project though because of the ease of debugging communications with a PC. |
H: Energy efficient one button on/off with extra function
(Old) cellphones have a button to turn it on (when off), end a call (when on, short press) or turn it off (when on, long press).
I need something similar for a microcontroller. The device is battery-powered so the circuit should be as energy-efficient as possible. In addition to that, the fewer IO pins I have to use the better. I understand I need at least one as an input to read the state. Size isn't really an issue, but smaller is better.
The microcontroller in question is an XLP PIC16F1829. If I'd use a SLEEP instructions and an input button on an interrupt pin, it would consume about 40uA in sleep, considering the peripherals I'm using. I hope I can get something drawing less current. The circuit should be energy-efficient when on as well.
What are some common energy efficient ways to make a one button on/off function with an extra option for a microcontroller?
As you can see, I already added a circuit myself. However, I don't know how energy-efficient it is when on, and there might be better options.
AI: If you need a solution that doesn't require a voltage regulator i.e. operates directly on the Vcc lines to the PIC then I've modified it slightly (and for a good reason): -
The reason it's modified is that the BJT pass transistor might drop a little too much voltage under load if you are just switching an already regulated Vcc to the PIC. I've replaced the pass-transistor with a P channel FET and removed the 2k2 and 33k resistors on your circuit. The 2k2 is needed to protect the BJT pass transistor and the 33k put a max limit on the pass transistor's base current - not needed when using a P channel FET.
I've also added a 10k pull-up on PD3 but this can be an internal pull-up in the PIC. What looks like a suitable P-channel FET is the TP0101 - it's the first one I came across when googling "Low Vgs(theshold) P channel MOSFET". There will be plenty that will do but this one has low on resistance (<1ohm) with just 2.5V drive on the gate and that was my primary aim.
It will also work up to over 10V so could be used prior to a regulator too.
Energy efficiency when "on" will be better that the BJT circuit because it doesn't need base current to keep it on. When powered off, both circuits will be really low on current but maybe the P channel leakage will "waste" 1uA leakage into the load - it's probably a good idea to make sure this 1uA doesn't somehow develop a voltage on the PIC that might cause it to "strangely" power-up - use a 100k load on the output - this will develop 0.1V across the PIC's power pins and kill off the possibility. |
H: xilinx schematics to truth table
I have a somewhat complicated Schematics design. Is there a program which could convert my design into truth tables?
If there is no such program, how can I represent the D flip-flops of the following design in a truth table?
AI: I wouldn't bother looking for tools and I would bypass truth tables and go straight to VHDL (or Verilog if you prefer). Given the schematic shown and a few coloured pens, this will take a few minutes, maybe up to an hour for a sheet as simple as the one you posted.
Presumably the whole circuit is many such sheets.
And I am assuming they are all similar to that shown; breaking the design down into simple representable elements, gates and FFs.
The strategy I would take is:
1) Identify and name each internal net (ignoring buffers, but recognising inverters). Thus S0 is connected to inputs on the top AND gate and the top left INV but the INV output is a separate net (call it SO_n or even N1). A coloured pen along each line as you go will help identify ones you haven't reached yet.
2) Identify and name the gates and registers.
3) Use a VHDL component (or entity instantiation) for each register
4) Use a signal assignment for each gate. These can be labelled with the name you gave each gate.
Then you have something like the following :
entity Sheet1 is
port (
S0 : in std_logic;
S1 : in std_logic;
Reset : in std_logic;
Clock : in std_logic;
F : out std_logic
);
end Sheet1;
architecture Netlist of Sheet1 is
signal S0_n : std_logic;
signal S1_n : std_logic;
signal FDR2_Q : std_logic;
signal AND3_1_Q : std_logic;
-- and one for every named net on the drawing
begin
AND3_1 : AND3_1_Q <= S0 and S1_n and FDR2_Q;
FDR2 : entity Work.FDR
port map (
D => Or4_1_Q,
Q => FDR2_Q,
C => Clock,
R => Reset
);
end Netlist;
The naming of each gate and net and, the labelling of each VHDL signal, component and concurrent signal assignment gives you the traceability back and forth between VHDL and schematic : more coloured pens to tick everything off, and you can quickly and reliably verify that the VHDL is an accurate rendition of the schematic.
Now you need models of the components like FDR : you can probably find them (e.g. in the Xilinx Unisims library in which case you would write FDR2 : entity Unisims.FDR ) but they are quick and easy to create by hand.
Now the VHDL version can be simulated (to find out what it does!) or synthesised as you wish. |
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