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H: How to route current for ATE?
I have many test points on a board, a small DAQ, and an SMU that I can program with LabView. Depending on the test, I need to change which test point the SMU is sending/measuring voltage or current.
To do this, I figured I should use a series of analog switches, and control the switch paths by using the DAQ's few outputs. (Eg. Outputting the high/low binary 000 sends the signal to the first test point TP1; 001 routes the SMU to TP2, etc.)
However, some of the tests I'm automating require sourcing/sinking up to 500mA of current from the SMU to the test point, and most switches advertise their "high-current capacity" of 150mA or so. Additionally, my SMU signal reaches a maximum of 20V at times, so it needs to be able to handle both.
I find it hard to believe that there isn't a switch that can do what I need, so what should I be searching for?
Is this usually how this kind of task is accomplished, or is there an alternative to switches that would be better?
AI: While you could look for analog mux's and switches, not many go into that range. Why not use relays? Relays support both wide voltage ranges and high currents.
Analog mux's have a varying resistance which may not sit well for your testing.
Relays have what is to be considered constant resistance and it's low usually under 1ohm.
Search for relays or SSR's at your favorite distributor. |
H: What is the working and reactive power in this circuit
i need help with solving this task (it's on croatian but i will translate): https://ibb.co/sb0cnsx ,it says what is the the working and reactive power for the given cirucit (Xl = 3 ohm ,Xc = 2ohm R = 2ohm, u(voltage) = 100)?
I found the equivalent resistance for the whole ciruit, 1+2j, but i don't know how to find the active and reactive power in circuit.
I think formula P = I^2 * R could help me.
in the given answers(a ,b ,c ,d ,e) 'kap' means capacitive and 'ind' means inductive.
AI: If you correctly calculated the impedance then:
\$I=\dfrac{U}{Z}\$ or simply \$|I|=\dfrac{U}{|Z|}\$.
\$Z=\sqrt{R^2+X^2}= \sqrt{1+4}\$ then \$P=I^2\cdot R\$ and \$Q=I^2\cdot X\$
Or yet simpler:
\$P=\dfrac{U^2\cdot R}{R^2+X^2}\$ and so on
Znači D. |
H: Electronic load, Problem turning MOSFET on
I am trying to make an adjustable dummy load to test a 12V supply, I’m having trouble with the op-amp feedback circuit.
Attached is a simplified schematic. I have tried lots of things and stripped it down to this.
Basically when +In of the op-amp is 0V, the output of the op-amp goes to the negative rail. In this case the negative rail is 0V, but when powered with a +/-5V supply, the output goes to -5V. In this state the MOSFET is fully off
When I add just a tiny bit of positive voltage to the +In of the op-amp, The output shoots straight into positive saturation and goes as close to the positive rail as it can get (about 3.7V) and stays there no matter how much voltage I give to the +In. At this point the MOSFET is on, and allows approximately 250mA to flow through though.
Any ideas on what this could be?
Things I have tried:
- removing R6 and Q1 and connecting R8 to -In. At this stage I get a normal voltage follower.
- Changing the FET
- Raising the resistance of R6
On a side note, there is one way that I can get the load to be variable, and that is by removing the heat sink from the MOSFET. I have only done this for short periods of time.
AI: What you have built is an oscillator.
There is nothing wrong with the LM324, it has been updated through the years, but I do agree with @laptop2D you could make a better choice of devices. You don't need a low offset opamp in this application.
The problem you have is that the FET you chose has a huge input capacitance (>5000pf).
With the 180 Ohm series resistor you guarantee that the circuit will oscillate around your setpoint.
You can try simply removing the 180 Ohm, which allows that LM358 to current limit into the gate, that might just work though it isn't pretty. However to fix the problem you really need a power driver stage for the FET gate, or chose a FET with much lower Gate capacitance.
The circuit has another problem though, the VGS(th) range for the IR1404 is 2-4V. You may have lucked out and got one that is closer to 2V ….but you will run out of drive voltage and not be able to use one that comes in at close to 4V.
You should at least double your supply to 10V (perhaps you could use the 12V supply you are testing to generate this).
To charge your gate capacitance at a reasonable slew rate I'd suggest you need to allow for up to +/-500mA drive. You could do this by using an NPN/PNP pair on the output of your opamp.
Perhaps something like this:
simulate this circuit – Schematic created using CircuitLab |
H: What is "Low Pulse Trigger" and how to use it?
I picked up some of these cheap Chinese Bistable relays and I am having trouble understanding how to get them hooked up. Do I put 5vdc + on VCC and 5vdc - on GND then use a low voltage pulse, such as 3.3vdc, to trigger it? I'm trying to use it with a Raspberry Pi.
AI: The advertising page you linked pretty clearly indicates that you provide a Low (zero volts, or close to it) to operate or release the relay - one Low pulse will activeate the relay, the next Low pulse will release the relay.
It is not clear if the 3.3V from a Pi will be considered a Logic High by that module. |
H: Problems with dc motor driver design: Mosfet fail
I made a brushed dc motor driver. The motor speed is controlled with PWM (from an Arduino). The motor that I'm using draws 3 amps without load.
This is the schematic:
As you can see there are two N channel mosfet in a parallel configuration.
The first problem that I had was that when I tested the PCB for the first time R2 burned and Q2 was damaged (all three pin where internally connected). I though that Q2 was defective so I change it and the PCB worked perfectly.
Then I tested the same circuit, different PCB, and happened the exact same thing, R3 burned and Q2 damaged, that can't be coincidence. Right?
Then I ran the motor at max speed for around 2 minutes, and the circuit worked fine, no overheating at all.
When I test the circuit with load (in a rc tank) the Heatsink heat a little bit (as expected), but then one of the drivers failed and the motor keep spinning. A mosfet failed.
Any suggestion on how to make the circuit work reliably, without the mosfet failing?
AI: One huge issue I'm seeing is a lack of any flyback diode for the motor. You need to add a high current diode from the mosfet drains to battery positive. This will give that energy somewhere to go. You'll want to connect the diode physically close to the mosfets (the motor wires will produce their own small inductive kick). This is probably the reason your mosfets are dying.
You'll want to read up on how to pick this diode, but the key parameters are current (a good rule of thumb is to handle as much as your motor draws), and reverse recovery time (I'd go with a schottkey).
A second problem is that you're driving the mosfets at only 5v Vgs (slightly less actually due to the resistors). Looking at the current/Vgs curve in the datasheet. The Rds will be approximately 0.25 ohms. In parallel that will be 0.125, so at 10A you're looking at 12.5W of dissipation. That's quite a bit.
The third problem is that you're driving the mosfets from the arduino directly. Since the arduino can only supply 20ma or so to the gate, the switching times will be slow. This means more power dissipation, especially as the frequency increases.
You can solve problems 2 and 3, by using a gate driver IC. This will drastically improve the power handling of your motor driver circuit. |
H: How to specify a value for each bit of the reg in Verilog?
I want to declare a reg of 8 bits and set the value for each one of the bits separately (based on another "counter" reg) inside an always block using Verilog.
Here is what I thought:
module readvalue (
button_1,
button_2,
value,
counter);
input button_1;
input button_2;
output value;
output counter;
reg [7:0] value;
reg [7:0] counter = 8'd0;
always@(posedge button_1 or posedge button_2)
begin
if(button_1)
begin
[counter]value <= 1'b0;
counter <= counter + 8'd1;
end
else if(button_2)
begin
[counter]value <= 1'b1;
counter <= counter + 8'd1;
end
end
endmodule
The idea behind the code is that when button_1 is pressed, 1 is stored in a particular bit of value and when button_2 is pressed, 0 is stored. I have a higher module in the hierarchy to make readvalue stop when counter is equal to 8 in decimal.
The code, as expected, gives me the following errors:
Error (10170): Verilog HDL syntax error at calculator.v(17) near text: "["; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at calculator.v(22) near text: "["; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
How can we put it to work?
I am using Intel's Quartus Premium Lite Edition 18.1 (with the latest update pack) on Ubuntu 18.04 with the default configuration. If I have not been clear or you need more information, just comment and I will provide.
I am a beginner on Verilog so, sorry for such a simple doubt.
EDIT 1: button_1 and button_2 are never going to have a posedge at the same time (or even in the same second) in my implementation.
AI: First, you need to put the index after the register name, like
value[counter]
not
[counter]value
However, I'm not sure if using a variable as an index into a register will be simulable and synthesizable.
If not, you could use something like
always@(posedge button_1 or posedge button_2)
begin
if(button_1)
begin
value <= value & ~(8'b1 << counter);
counter <= counter + 8'd1;
end
else if(button_2)
begin
value <= value | (8'b1 << counter);
counter <= counter + 8'd1;
end
end
However you should also be aware that this is likely not synthesizable because you are trying to make logic that is edge-sensitive to two different signals and if you consider all the subtleties, the actual logic in your FPGA or CPLD doesn't do that. You can probably make an SR latch, but that doesn't work exactly like your code because it will behave differently if, for example, button_1 is still asserted when the rising edge of button_2 arrives.
The usual way to code these things for an FPGA is to have a clock available that runs much faster than you expect button_1 and button_2 events to arrive, and use that to clock logic that detects edges on the input signals and responds to them.
For example (sorry, code not tested),
reg b1d; b2d; // delayed button signals
always @(posedge clk) begin
b1d <= button_1; // Notice: non-blocking assignment
b2d <= button_2;
if (button_1 & ~b1d) begin
// A rising edge on button 1 happened
// ...
end
else if (button_2 & ~b2d) begin
// ...
end
end |
H: Reading current memory image from a micro controller
I have the MPLAB XPress Evaluation Board, which has the PIC16F18855 microcontroller on it. The way to program it is just to copy a .hex file through the serial connection, which makes the bootloader update its memory image.
Is there a way to directly read the current memory image of the microcontroller? In other words, how is it possible to dump the memory image of a microcontroller?
AI: Either you use a microcontroller that has a debug port (e.g. JTAG, in case of ARM microcontrollers often SWD) and an appropriate debugger, or you'll need to write software for the microcontroller that outputs the memory contents e.g. via a serial interface. |
H: Proper voltages from same source
I'm building a small electromobile. I was planning on using a car alternator as the motor, however I'm now looking into buying a 48V 500W BLDC motor.
The problem is I'm not really sure how to manage the difference in voltage between what the motor requires and the rest of my circuitry.
I have a bunch of components that run at 12V as well as another bunch at 5V. In the scenario where I have a 12V battery I just use a buck converter to step-down the voltage for my 5V circuit and it all seems fine since it didn't draw anywhere near the 3A maximum rating of the converter.
Now my 12V circuit draws ~10A at full load. If I have a 48V battery I think I'll have trouble using a buck converter for that purpose. I was thinking I could tap into a point between the battery cells where the voltage will be 12V but that is probably dangerous, I'm pretty sure difference in voltage in the cells will upset the battery.
What would be the "proper" way to power my 48V motor and 12V as well as 5V circuit?
AI: Use a 48v battery, and a buck down to 12v. Both are nice commonly used voltages, and there should be plenty of converters available to choose from in that power range.
If you were only going to use a few mA at 12v, then it may be permissible to tap into an intermediate battery connection, and rely on your charge cycle to rebalance the batteries, but 10A is rather too much unbalance to handle this way.
You did right in rejecting the car alternator as a motor, they are horribly inefficient. They are built down to a price, have plenty of air-cooling and an abundant non-metered energy input, so efficiency is the last thing on the designers' minds. |
H: Will leaving 1 of the 3 GND pins on the ATMEGA328p ungrounded cause any problems?
I am creating a circuit using an ATMEGA328P and i am unable to ground one of the 3 ground pins (other 2 are fine) due to limitations of my design. I have tested the IC with a multimeter and the pin does seem to be connected to the other ground pins which makes me think that it should be ok if it is left out. is there any problem with me doing this? thanks.
AI: Depends on what that pin is for. It may be required to link two grounds in the silicon, in which case it would cause an issue. You say it is linked, so it shouldn't be that bad. But ground pins are used for two other reasons.
Thermal: a ground pin gives a nice thermal link to a large copper plane which can be used to suck heat out of the IC and stop it over heating. Not connecting it up will cause there to be more heat in the IC, possibly spot heating, shortening the life of the IC as well as possibly causing damage straight away.
EMC: ground pins give you more routes for the current loops to follow. This reduces the chance of EMC problems and means that the IC should perform better. The ground link also reduces the inductive path for the current, allowing faster signalling and general improvement in performance.
As mentioned in the comments, and which I completely forgot about, the extra ground pins may also be carrying extra current. For every bit of current in, there must be a bit of current out. It can be surprising just how much current needs to flow in/out of these ICs.
So, while not connecting the pin may not cause immediate issues, it may cause a lot of problems down the line. If your design does not let you connect the pin, I would suggest your design needs to change so that it can. Connecting a ground pin is an easy task compared to working out why the whole product fails at some random point. |
H: Logic gates for relay coils analogic control signals
I have 2 external signals arriving to my board, A and C. B is generated inverting A. They 3 will be used for generating 3 switch control signals: A', B', C' at every point (there will be 8x3 24 switch). Every one will be 12V or 0V. 12V state means to activate the coil of a relay, because of coil needs 12V for closing contacts.
According to the application, there can only be one active switch at the same time I thought a way for ensuring that only A', B' or C' will be ON and the other two signals: OFF.
I though about muxes and logic gates that supports input and output voltages of 12V. So I found useful products. But after thinking that I was having a good solution, I realized that:
these coils have a resistance = 150 Ohms. So Icoil = 12V/150 = 80mA -relay datasheet don't say anything about cutoff current, but drop-out voltage: 1V -
the most of existing logic gates provide a max output current = 10mA.
so, I'm afraid that coils will not be energized because 10mA < 80mA
questions:
I dont' know if my explanation and situation is correctly deduced. Is it generally only needed to have 12V or may the coils need 12V + I > 80mA?
If I can' t find AND and NOR gates with this current output features, how do you solve the situation?
Must I say bye to modifying control signals using logic gates? or can be applied some electronics to the outputs? I don't consider using current elevators due to the quantity of them that I would need.
Any information will help.
AI: The tidiest cheapest solution is likely to be to use a relay driver like the ULN2803. They have a logic-compatible input, an output capable of switching 500mA and 50v, there are 8 channels in a small package, they are used by the gazillion so are very obtainable and cheap, and they even incorporate the catch diodes you need to drive relays without blowing up your driver.
Think of it this way, eight 12v 80mA relays plus a single ULN2803 driver IC is equivalent to eight 'logic level input' relays. |
H: I want to measure 50 miliamps by multimeter which range i should select?
I have a multi meter I want to measure DC 1-50 milliamps which range I should select by the knob?
Also where I need to plug in 20A or mA?
AI: Use the 200m setting from the orange section with an A with a solid and dotted bar above. You can find the manual for the meter here. |
H: Lack of 'determinism' in Ethernet bus
While reading this website, I found out tha there is lack of 'determinism' in the Ethernet network bus as compared to some other buses like 1553. What I understand is that Ethernet is a single master full duplex serial data bus. But I cannot understand what is reason for it to be non-deterministic is data communication? If a terminal A wants to send data to terminal B when both are on the same shared Ethernet bus then A can do that without any chance of missing the data. Then why it is called non-deterministic bus?
AI: Etherenet is based on CSMA/CD, which signifies carrier-sense multiple access with collision detection. It's not single master, any device can send and recieve independly, like multi master / multi slave, so that's why collisions happen. In such case the message sending is repeated, for both devices that had collided but each has it's own random timer, so that one takes over faster.
Determinism is more than just delivering a message from point A to B, but also at exact time. |
H: What's the maximum time an interrupt service routine can take to execute on ATmega328P?
I have an ATmega328P that checks if a button was pressed via pin change interrupts. Now, I want to turn on an LED for 200 ms.
Can I just turn the LED on, wait 200 ms and turn it back off in the ISR like in the following code?
ISR(PCINT1_vect)
{
if(PINB & 0b1)
{
PORT = 0b10;
_delay_ms(200);
PORT = 0;
}
}
In a few forum posts on AVR Freaks, I've read that you shouldn't spend much time in an ISR, but I've never seen any exact numbers. I sadly can't find those posts anymore, so I can't link them. As far as I can remember, they all said, that if you spent to much time in the ISR, the microcontroller might crash.
Is that true? And if so, is there an exact time limit after that this might happen?
AI: If nothing else is running in the MCU, then you are free to take as long as you like in the ISR. But, this is a bad habit to get into, and it means that if you want to do anything else, you'll likely have to rework the code.
A particular case is if the MCU is using a serial library, that expects interrupts to be working often enough to service individual characters received. At 115,200 baud (a high serial speed often used to minimise download time), there is less than 100 µs between characters. If you block the interrupts for longer than that, you risk losing input characters.
As a general rule, do the absolute minimum in an ISR. In your application, a reasonable design would be to have an interrupt every ms, which increments and checks a counter value. I'm sure you can work out some suitable logic to set and test the counter to get 200 ms between turn on and turn off events. |
H: Values of components in ACPL 337J
I was going through datasheet of mosfet gate driver. I wonder why is the value of component the specified one only. On page no. 13 fig 23, why the value of resistor between pin 3 and pin 6 is 10k ohm only and not any other value? Similarly, capacitors between pin 6 and 8 are of value 330pF. Why not any other value?
The attached diagram is of recommended application circuit provided by Avago Technologies. Also if I am to use it in LTspice with a mosfet, what are the additional components and connection that are to be made so that the driver can driver the mosfet? The mosfet is to be operated at a frequency of 100kHZ.
AI: The 10k resistors are pulling up UVLO (pin 5) and Fault (pin 6). 10k is a pretty standard part used for this.
The 10k uses the available output current from those pins (for a 0.4V output) of between 4mA and 9mA to ensure they actually do go to a valid low when driven that way. Larger resistors (but not smaller as the outputs cannot sink enough current for smaller resistors) could be used. The ones here are suggested and are typical values that are easy to get.
The capacitors are filters from those pins to ground to filter glitches on the outputs.
The time constant is (ignoring where they might be connected elsewhere) 3.3uSec so this would filter out sub microsecond glitches due to false internal triggers (the device is expected to be used in rather noisy environments such as motor drives).
Larger filter capacitors could be used for more immunity at the expense of response time. Smaller devices may let false triggers through. |
H: Build electrical characteristic for gas measurament via IR sensor
I'm building a CO2 measurement unit via Arduino and I'm the phase of choosing the sensors.
I've found out this IR sensor that, thanks to an emitter with WL of 4.26um is able to output a voltage proportional to the concentration in air of CO2.
To calibrate the circuit I must use a titrated gas (% well known) and measure the voltage in output from the sensor.
My problem now is that I can't understand, with this measure done, how associate further measurement with the % of the gas.
Is this linear? Does it depend on the sensor (the distance between the LED and the sensor is fixed)?
I've never used IR or Gas sensors so, this is my first experience with them and I'm pretty disoriented
AI: The L13201 emitter is something I've looked at because it emits right on the sensitive wavelength for CO2 i.e. 4300 nm and it also has significant emissions at 3900 nm where CO2 has no effect: -
Vertical blue line added by me is the sensitivity at 3900 nm and the red line is about 4300 nm.
So, if you chose the Pyreos dual sensor of the type that has one channel sensitive to 3900 nm and the other channel at 4300 nm, you get a reference channel and a measurement channel all from one light source namely the L13201.
It's important to get the reference channel because that channel is unaffected by CO2 and can be used to stabilize the light output either by feedback or post compensation of the signals (in hardware but more likely software).
That reference channel is also subject to the same signal deteriorating factors that the CO2 channel suffers from such as contaminants such as water vapour or some other environmental effect. See below for the general idea: -
At 3900 nm there are no real signal perturbations due to any of the gases commonly associated with this part of the spectrum so it's "useful".
My problem now is that I can't understand, with this measure done, how
associate further measurement with the % of the gas.
The ratio of the measured signal to the reference signal is the approach taken by several CO2 sensor manufacturers such as City Technology and SGX Sensortech to name a few that I've come across. That ratio as it drops, is the measure of CO2 present in the sampled gas. |
H: Average Voltage of a 3phase full wave bridge diode rectifier derivation
Why three phase bridge rectified waveform is integrated over the half period \$\pi/6\$\ to find the average voltage? Should it not be integrated over \$\pi/3\$\, as the wave form repeat itself after \$\pi/3\$\ which is the time period of this waveform. Below is the waveform and related derivation. The book is Power Electronics 3rd Edition by Muhammad H. Rashid, page no 93.
AI: The waveform from \$\pi /6\$ to \$\pi /3\$ is just the symmetrical reflection of the waveform from \$0\$ to \$\pi /6\$. Therefore, the average value will be the same over those two periods. |
H: Replacing a missing capacitor
I've managed to break off a smd ceramic 1206 capacitor of a motherboard I am working on, I'm am new to electronics, so be gentle! Anyway this damn capacitor has vanished into the place where all missing tiny components seem to go! I cannot find any schematics for the board to see what I need to replace. Good news is I have two boards, I need both, so no I cannot swap it out. So how do I test the capacitor to replace the missing one as there's no markings at all? I have a Multimeter only and it's basic AstroAI AM33D. Any advice would be very helpful! I've attached a photo sorry about the quality the parts are small.
AI: These are all 805 cases.
If I were designing this for best rise time for a 1MHz to 1 GHz Load on current with 4 ceramic caps only, my reasoning follows.
The reason 1 is farther away is to add a few nH isolation with the 3 smaller 0.01 uF caps which have lower ESR and higher frequency response.
The isolated one will be a high quality X7R 0.1uF cap which due to physics and geometry. There will/may be others near load <100pF.(NPO)
The round can is an e-cap. |
H: Is there a direct to PCB punchdown Ethernet connector?
I’m attempting to design a small board that splits 802.3af and provides both data and 5v power to an MCU on the same board.
I can find plenty of ICs with reference schematics for the splitter part - but they all expect an RJ45 port, which I understand contains something called “magnetics”. So far as I can tell, this is both about isolation and impedance matching.
My intended application is for outside, where I’d expect just using a reel of solid core cable. Personally, I find it annoying having to crimp a plug, so use an IDC and then a short patch for that.
What I’d really like is somehow to avoid either the plug or IDC + patch, so there could be 8 punchdown connectors directly on the board. Presumably then you’d have to replicate these mysterious (to me) magnetics on board.
I’m struggling though to find anything like this.
Here’s a picture I found of the internals of a PoE splitter; essentially, I’d like to understand what would be needed to replace the RJ45 port with a punchdown connector.
AI: It's not uncommon to have the magnetics external to the RJ-45 socket, especially in cheaper devices — Just like in this case, where I'm certain the magnetics are inside the TMSEMI package closeby.
That board looks like it's only for 10/100 Mbps Ethernet; so I'm sure you could get by with nearly any PCB-mount punchdown connector there (preferrably rated cat 5 or better for 100MbE).
TL;DR:
Keep the magnetics package, and 'just' replace the RJ-45 socket with your punchdown connector of choice.
Edit:
Looking around, the magnetics part seems to be second sourced version of Pulse Electronics H2019NL/HX2019NL, a 100MbE, 15W PoE-specific part. Quite widely available too! |
H: How to wire a normally open switch to a recoil start engine with no external battery?
I am making an engine toggle switch for a recoil-start engine using two switches wired in series for safety. The engine will shut off only when two "kill" cables on the front have been connected. In the picture below, I have lengthened the wire to make it more noticeable and easier to work with.
Unfortunately, the switches are built to be normally open and cause the engine to shut off when both switches are on (hereinafter called "switch box"). The ideal situation is that the engine status reflects the switch box status: both switches ON activates the engine and turning either switch OFF in the switch box shuts down the engine.
Thankfully I was able to find some answers on how to flip the switches to act normally closed from using concepts from this kill switch post. I also viewed a post about latching relays to potentially use for hooking up to the engine. I spent some time prototyping these ideas and it works exactly as I need it to. Below are the schematic and pictures of the functioning prototype, whenever the LED is ON the engine is OFF because a connection has been established:
LED OFF means Engine ON
simulate this circuit – Schematic created using CircuitLab
For my question, I would have been able to hook up this circuit and been done with it except a recoil-start engine does not utilize an external battery like this prototype circuit and most of the engine kill-switch questions on this forum do. I've noticed through testing that the battery is crucial for making the circuit work. Given that the kill cables from the engine are wired with its spark plug, how would I be able to implement the Normally-Open to Normally-Closed wiring without having a battery? Is there some way to wire the same path the battery creates without using a battery?
AI: You don't want to be relying on a battery-powered circuit to actuate a relay that will kill the engine, if the battery is dead you lose the ability to stop the engine. Ideally a safety circuit is wired as Ron suggests so that is is failsafe and ceases operation of the circuit is opened, but that's not how stop switch on these engines work, they short a winding in the magneto that prevents the generation of a spark at the plug by diverting the generated current through the kill switch.
So you need the switches to be normally open such that if either one is closed it will kill the engine. To get the logic correct, you then wire the two in parallel.
If I remember right, the small rocker switch on my weed trimmer has the markings the wrong way around, it is biased to the '0' open side as you'd expect for a NO switch, and you push it to the '1' closed position to stop the engine. If you have the possibility of inverting the switches so that the markings or physical position are reversed, you may be able to achieve your intent without any additional componentry - the rocker on the small rocker switch typically will pop out of its housing with a screwdriver/knife blade pushed down either side to flex the body out enough. Looking at the photos - is the switched biased off? It's in the on position. |
H: Do RCDs work for DC systems?
I'm designing a product powered by an alternator with a DC regulator that will provide me with 24 V DC and something like 100 A rated consumption. Do RCDs protects against earth leakage current in DC circuits or only in AC systems?
If not, how should I protect my system agains current leakage?
Thanks!
AI: Standard RCDs only detect AC, as they are based around a transformer. The live and neutral both pass through a sense coil. Provided that the currents in each are equal and opposite, their magnetic fields cancel out, and the sense coil detects nothing. If current leaks from the live to the earth, then the live current is greater than the neutral, and there's an imbalance in the magnetic fields. The sense coil produces a signal, and the RCD trips.
What are you actually trying to protect against here? 24V DC is unlikely to electrocute anybody. |
H: What is the peak current for CR, LIR and AA batteries?
I'm working on a project that requires low energy consumption. In standby mode, it will consume about 11uA. However, when it starts working (it will transmit data in RF), the current goes up to 121mA. This is going to happen 4 times a day, and the peak current duration is 2 seconds, at most.
Because of it, I'm searching for a battery (rechargeable or not) that gives me a high autonomy. I'm expecting 1 year of autonomy, at least. However, most batteries datasheets don't give the information about the duration of a peak current, and how much the battery gets discharged for it. I'm looking for batteries like CR2032, LIR2450 and AA types.
Let me give an example: LIR2450 has a nominal capacity of 100mAh. With dc current of 11uA, the autonomy goes for about 9100h. However, if in the middle of the day (all over the week) my circuit requires about 121mA for 2 seconds, how much does the autonomy drop? Is the battery going to be killed by that consumption?
AI: Alkaline or NiMH AA batteries are certainly OK at 121 mA. The current draw in a speedlight/photoflash is higher than this based on the big cap charge time.
4 AA batteries can charge a 1000 uF, 300V cap in about 5 sec -> 0.5*C*V^2 = 45 Joules = 6V * 1.5A * 5 sec if my math is correct.
121 mA is more than I would draw from a coin cell. This Energizer "pulse" test only draws 7 mA. http://data.energizer.com/pdfs/cr2032.pdf Even if they aren't damaged at 121 mA, the internal resistance is likely to be an issue.
Edit: OK, here is some data on the autonomy. An Eneloop NiMH rated at 1900 mAh was tested to have a capacity of 1877 mAh at 200 mA. Therefore, there is minimal loss in capacity at 200 mA, slightly more loss at higher currents. https://lygte-info.dk/review/batteries2012/Eneloop%20AA%20HR-3UTGB%201900mAh%20(White)%20UK.html
Edit2: Discharge Time Calculation:
It is easiest to determine how many 6 hour cycles it will last. The calculation isn't hard, but you need to be careful with your units. Here everything is in hours and mA. If I made a mistake, the eagle-eyed people here should catch it.
Note that batteries will discharge even with no load. Modern batteries are quite good, they will go for several years with minimal loss. Still, I would shoot for 2X margin in your situation (calculation should show > 2 years).
If physical space is at a premium, consider AAA batteries. |
H: Colpitts / Clapp oscillator crystal drive level
simulate this circuit – Schematic created using CircuitLab
As I understand this circuit has some initial gain at startup, then as the oscillation builds up gain goes to unity at some moment. How to modify such circuit to change crystal power dissipation from lets say 1mw to 100uw, but still keep initial gain same for reliable startup? I mean, how to control transition point where it goes to unity gain? Also, what could be possible consequencies of adding series resistor to a crystal to lower drive level? Say 5 to 10 Ohms?
AI: The initial gain of the circuit is essentially what drops out of the small signal model -- some perturbation of the voltage or current at some point of the circuit will result in some perturbation of that same thing. In order for oscillation to occur, the output needs to be greater than, and equal in phase to, the input.
The operating point at which the circuit reaches effective unity gain is all about the nonlinear behavior of the circuit. Something will hit a limit, and what hits a limit has a strong effect on how well the oscillator will work. The received wisdom that I operate on comes from Wes Hayward's Introduction to RF Design (ISBN 978-0134940212), and Randal Rhea's Oscillator Design and Computer Simulation (ISBN 978-1884932304). It is, basically, to design the amplifying element of your oscillator so that it runs out of current before it hits any voltage limits.
In other words, you want to design your amplifying element so that as the oscillations grow stronger, the amplifying element delivers narrower and narrower current pulses, but never hits a voltage where a previously reverse-biased diode suddenly gets forward biased (e.g. the C-B junction in a BJT, or the gate junction in a FET, or if you're going retro, the grid-cathode or grid-anode "diode" in a tube).
The way that you change the operating point at which unity gain is achieved is mostly by varying the bias in that amplifying element, but also by changing the impedance level at which the circuit operates -- i.e., C1, C2 and C3 in your schematic. In general, for the same drive voltage, increasing the transistor current and decreasing the values of C1 and C2 will do this. Changing the ratio of C1 and C2 can also do this (in general, decreasing the value of C1 increases gain and thus final drive, but there's an optimal value that you can exceed).
I usually find this out by modeling the circuit in Spice (LTSpice seems to deal well with oscillators) and giving the simulation enough time to settle (for a crystal oscillator this will take a lot of processing time). You want to see current spikes on the emitter/source/cathode, with no dramatic spikes (indicating forward bias) on the base/gate/grid.
Adding a series resistor to the crystal will reduce drive, but it'll also reduce the circuit Q, which will make for a more poorly performing oscillator. It's necessary when you're using a CMOS inverter as an amplifying element because you can't control the bias -- but with a single transistor (BJT, JFET, MOSFET or Glass-FET) you have much more control. |
H: Does a potentiometer need a resistor in series between power and ground?
I have a potentiometer I use with a circuit to get data readings. This circuit is connected to an arduino mega 2560. I was wondering if I need a resistor in series with the potentiometer? Attached are two picture of what I mean, sorry if the circuits are a bit rough first time I have used an online schematic maker. I would also like to add that the potentiometer values are likely wrong, it was a generic one a friend gave me. All I know is that it goes from 5 ohm to 10k ohm.
AI: First, a couple of CircuitLab tips. Double-click a component to edit its properties. 'R' = rotate, 'H' = horizontal flip. 'V' = vertical flip. Note that when you use the CircuitLab button on the editor toolbar an editable schematic is saved in your post. That makes it easy for us to copy and edit in our answers. You don't need a CircuitLab account, no screengrabs, no image uploads, no background grid.
The important thing is that your potentiometer circuit shares the same ground as your microcontroller. If you leave out the ground connection then you have an open circuit and no current can flow from the potentiometer to the micro.
simulate this circuit – Schematic created using CircuitLab
Figure 1. Both circuits share a common ground with the microcontroller.
There is a difference between the two circuits.
The wiper on Figure 1a can go from 0 V at the bottom to 5 V at the top.
The wiper on Figure 1b can go from 0 V at the bottom to 5/4 V (1.25 V) at the top because R1 and R3 form a potential divider with the maximum voltage give by \$ \frac {R3}{R1 + R3} V_2 \$.
If your micro's analog input is 0 to 5 V then (a) uses the full scale (typically 1024 counts on a 10-bit ADC). (b) would give a maximum of 1024/4 = 256 counts for 1.25 V. |
H: Lithium Ion Battery Charger and Power Path Management IC
I am to analog electronics. I am building a circuit that has a lithium ion battery. I understand the importance battery charger in battery management.
My question is how does a designer set specifications of the battery charger IC. What tools are needed?
I would like to use BQ2423x by Texas Instruments
AI: The main parameter is the charge rate, or 1C, to determine the maximum current delivered while the battery is being charged. It is important to meet this specification to ensure the battery is not damaged, and to prevent overheating or catastrophic failure. It is equally important to not exceed the maximum charge voltage of 4.2V, nor to discharge below 2.8 to 3.0V. Your design should include protection for the battery to prevent this condition.
Here's a good tutorial about Li-ion batteries. https://batteryuniversity.com/learn/article/charging_lithium_ion_batteries |
H: PIC12F675 GP4 doesn't work
I'm using a PIC12F675 for a project, and everything works fine except one thing. GP4 does not work as digital IO. I've looked at the configs and the code a lot, but couldn't find anything.
Config:
#pragma config FOSC = INTRCCLK
#pragma config WDTE = OFF
#pragma config PWRTE = OFF
#pragma config MCLRE = OFF
#pragma config BOREN = ON
#pragma config CP = OFF
#pragma config CPD = OFF
Code:
#include <xc.h>
#include <math.h>
#include "config.h"
#define _XTAL_FREQ 4000000
void delay(unsigned int freq){
for(int i = 0; i < (int)freq; i++){
__delay_ms(1);
}
}
void dClock(unsigned int freq){
GPIO1 = 1;
delay(freq);
GPIO1 = 0;
delay(freq);
}
void InitADC(){
ANSEL = 0x11;
ADCON0 = 0b10000001;
CMCON = 0x7;
VRCON = 0;
}
unsigned int GetADCValue(){
ADCON0 = 0b10000011;
while(GO_nDONE);
return (ADRESH << 8) + ADRESL;
}
void main(void) {
TRISIO0 = 1; //analog input
TRISIO1 = 0; //output
TRISIO2 = 0; //indication
TRISIO3 = 1; //mode
TRISIO4 = 0; //halt
TRISIO5 = 1; //pulse_button
char pressed = 0;
GPIO1 = 0;
InitADC();
while(1){
if(GPIO4 == 0){
if(GPIO3 == 0){
GPIO2 = 1;
unsigned int freq = GetADCValue();
dClock(freq);
}
else{
GPIO2 = 0;
if(GPIO5 == 1 && pressed == 0){
GPIO1 = 1;
__delay_ms(50);
GPIO1 = 0;
pressed = 1;
}
else if(GPIO5 == 0 && pressed == 1){
pressed = 0;
}
}
}
}
return;
}
AI: Just to add to Spehro's correct answer:
Since the microcontroller you are using has only 8 pins, they necessarily must share functionality to provide the various features that the device is capable of.
I just wanted to provide a sort of "roadmap" to help explain how the configuration works.
Check out the pin function diagram on the datasheet page 2:
You'll notice that physical pin 3 has at least five functions: GP4, AN3, !T1G, OSC2, and CLKOUT. Sometimes you have to specify in the configuration which function the pin should have. It's definitely not always clear. I find it helpful to search the datasheet for references to the register or pin function I'm having issues with.
Here's an excerpt from page 52 on which GP4 was found:
Microcontrollers very often can operate using an internal oscillator if they have one, or from an external oscillator such as a crystal. Even further, they can connect their internal oscillator to a pin for clocking other devices. The configuration register here has three bits (FOSC) that determine how this gets set up.
If you look at the two modes listed with values 101 and 100, they both specify to use the internal oscillator, but one of the options connects GP4 to the clock, where the other maintains its function as GPIO.
The defined constants INTRCCLK and INTRCIO Spehro mentioned should reflect these values. |
H: Placement and values for ferrite bead/capacitor ESD protection / transient suppression filter
I've been researching but found it difficult to find a clear answer on this. I need to add ESD protection to my circuit, in this Texas Instruments video it talks about combining a TVS diode with a FBC (ferrite bead/capacitor) filter to maximize ESD protection, which to me seems like the best approach. I am wondering about placement and values for the filter. I will be powering a 3.3V ADC and MCU from a 5V AC adapter as shown in the schematic. Would the best placement of the FBC filter be right at the start of the circuit at the output of the AC adapter? I saw mention of using them at other places in the circuit and I think I saw using multiple FBC ESD filters mentioned. To me it seems like just one at the start of the circuit should work well but that's just my unknowing guess.
I am also looking for general values for the bead and capacitor. Most beads I looked at have a resistance of about 20-200 ohms at 100MHz. What size bead and capacitor would be ideal for ESD transient suppression? Should the capacitor be smaller value, or larger which could also double as a bulk supply decoupler for the circuit? Does the capacitor type matter? I've seen many mentions of the filter used but values have not been described. Thanks very much for any help.
AI: What you have shown is reasonable. The TVS wants to have a low-impedance path to the earth or frame ground to be most effective.
As far as the bead, choose a larger size (like 805) to handle the current. You can experiment with the value; 33 ohms or so for a feed line is a good starting point.
Add some high-frequency / smaller value caps to the input as well, either side of the bead, to form a pi filter. Choose values that won’t cause anti-resonance. 4.7uf/1uf/0.22uf is ok (spaced ~ 5x apart).
A couple of resources: Murata app note for filtering https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx
K-Sim for simulating cap resonance interaction: http://ksim.kemet.com/ |
H: Is the frequency response of a circuit only valid for steady state (phasors)?
This is my first post. I just finished a course about advanced circuit analysis techniques (the content was taken from textbooks by Sadiku, Hayt and Irwin.) As you know, phasors are used to solve sinusoidal AC circuits (and also non-sinusoidal AC circuits, with the help of Fourier series), however, the answer you get from analyzing a circuit with that technique is only the steady state response, not the complete response (which also includes the transient response). When we're introduced to the frequency response analysis, the only difference is that now frequency is an independent variable just like time, and we still solve the circuits with phasors.
So my question is this: is the answer obtained by a frequency analysis (output voltage, ratio of output to input voltage, transfer function, etc.) only valid for steady state? I'm assuming this because in freq. anal. we still use phasors, which give only the s.s. response.
AI: Yes, it assumes the transients have decayed to zero.
But note that the frequency response contains information on the transients, this is why it's so useful. It's a steady state measurement that gives transient information, so filtering etc can take place in a steady state environment which, potentially, gives more accurate results.
Furthermore, SS frequency response can detect transients that may not even be visible on, say, a step response. |
H: Serial communication between STM32F4 and PC -USART-
The question I will ask now is not about how to solve something, I am currently able to make the connection as it will be mentioned below, but my problem is I really did not understand WHY ? Thanks in advance.
Hey, I am trying to connect my STM32F4-DISC board to PC via USART. It is a very common and basic example like sending a string to PC COM port which is covered by lots of tutorials on the web. But my question is,
I first used this product and directly connected to my board's RX TX pins and I was able to get data but all the data was a mess.(Not random, always same but some characters I have never seen before.)
I think there was nothing wrong with connections because when I disconnect the jumper which connects the Rx of converter and Tx of DISC board, there was nothing ongoing even that messed up characters.
After lots of thinking about "what is wrong? is it code?( It could not be because only 3 lines of code and all examples writes the same thing) ", I found a little device which has a chip on it( I can't read what is the model or manufacturer) and one side is D sub 9 male and other side has 4 jumpers come out of that named as Rx,Tx,GND and 3.3V. Then I also used it and created a connection like this:
PC --USB ENTRANCE-- DIGITUS USB to serial adaptor -- D SUB 9 ENTRANCE -- THE IC I MENTIONED ABOVE -- JUMPERS -- STM32F4
After this setup I was able to see the correct text on the screen and everything worked well.
I researched about why this could be but did not understand. The digitus product itself looks like the only necessity to connect my board to PC but It does not work alone.
I wonder what is the real case?
AI: USB to Serial adapters with a DE9 connector use RS-232 Voltage levels, where logical 0 is a positive voltage between 3 and 15 volts, and logical 1 is a negative voltage between -3 and -15 volts.
STM32 Microcontrollers use TTL-like signaling, where logical 0 is between approximately 0 and 0.7 volts, logical 1 is between 2 and 5 volts. Voltages below 0V would be registered as logical 0, as long as the MCU works, but they can likely damage it permanently. Apart from being extremely lucky that your board didn't blow up, you've got the bits inverted, that's why strange characters have appeared.
The other device would be a level converter, which translates the signals between the two standards.
There are products that can directly connect an USB ports to a 3.3V microcontroller UART port, look for an USB RS232 TTL 3.3V adapter.
I've disassembled an USB-RS232 adapter similar to that of the question. There is the FT232RL doing the USB to serial-TTL conversion, and an RS-232 transceiver, doing the voltage level shifting. You could theoretically remove the SP213E part, and connect the microcontroller UART port directly to the FT232RL.
Top side
IC markings on top side
Bottom side
IC markings on bottom side |
H: Why does resistance reduce when a conductive fabric is stretched?
I just purchased some conductive fabric and noticed that stretching the fabric reduced its resistance. This seems counter-intuitive since stretching a wire leads to an increase in its resistance. I have also found this video where you can see this happen. Why is this happening? How does stretching the fabric lead to drop in the resistance? and is there any relation between the two?
AI: It probably causes closer contact between conductive bits, however note that your observation is not universally true. For example, this fabric from Holland Shielding has the following note:
When the material is stretched lengthwise, its conductivity increases;
when you stretch it crosswise, conductivity decreases |
H: STM32F411VE Custom bootloader USB de-Init issue causing Jump to app fail
I'm developing a custom a bootloader on STM32F411VE MCU which must download a .bin file from USB key and flash it into the application sectors of flash memory.
Following the examples provided with cube libraries i managed to open correctly the file with the FAT FS system, but I'm having hard times understanding how to exit from the bootloader and jump to my app.
These are the scenarios:
1) Power on the board with no USB Key inserted; the code has no usb stop/deinit/disconnect call -->boot ends its function and jumps correctly to the application. If I plug the USB key during application-life the system reboots. Note that in my application I have no USB driver running
2) Power on with USB key inserted; the code has no usb stop/deinit/disconnect call --> boot fails when setting the MSP of the application:
__set_MSP((uint32_t)*APPLICATION_START_ADDRESS);
3) Power on with no USB Key inserted and USBH_Stop call before jumping to app --> boot fails when setting the MSP of the application
This is my Jump to app implementation. It worked optimally before inserting the USB Host driver
static void JumpToApplication(void)
{
void (*pmain_app)(void);
/* First, disable all IRQs */
__disable_irq();
SCB->VTOR = (uint32_t)APPLICATION_START_ADDRESS;
__set_MSP((uint32_t)*APPLICATION_START_ADDRESS);
pmain_app = (void (*)(void))*(APPLICATION_START_ADDRESS + 1);
pmain_app();
}
Thanks a lot for supporting me
AI: Your overall issue is in trying to branch to an application after a bootloader has heavily operated the system. This is strongly dis-recommended on the STM32, as to get it to work you have to get every aspect of the chip back to a state the application code assumes. Likely more obvious failures include things like having the clock PLL on and selected (as required for USB) and then the application code expected the PLL is not selected when it starts configuring it. But chasing down everything will be extremely frustrating, and you can be left with 90% functionality but 10% seemingly inexplicable weirdness in some peripheral.
Instead, the usual recommendation is to set a flag in memory or the RCC backup registers, reboot the system, and then detect the flag and branch early in startup before doing any configuration. When I needed to implement this I did it in assembly before even the C startup had run; that was probably unnecessary though if you chose to use a memory flag beware of the likelihood of startup code initializing RAM. If entering the bootloader requires explicit action, you wouldn't even need the flag, but only to check that the "stay in bootloader" GPIO or whatever condition is not met, and that there is an application present matching whatever validity check you use.
boot fails when setting the MSP of the application
This is more easily explained. Your code attempts to utilize a local stack variable that was allocated before it changed the stack pointer, which is essentially a recipe for disaster. If you are going to do that, you don't want to make any use of the stack after you change it. |
H: Half Bridge Inverter Effect of Load on waveforms
I have made a half bridge inverter, in the lab and on simulation software. I have used the gate drive IR2110a and am supplying it with a square wave pulse and it is then applying the gate voltage to the high and low side MOSFETs (ho and lo on the diagram).
I have found that using a purely inductive load of 100uH causes the circuit to not work as expected, as the Vs (which should be a square wave) massively droops and therefore the Vho is too small to turn on the high side MOSFET for the normal time expected. Shown below:
Increasing the value of the inductance reduces this droop but there are still sloping tops on the Vs waveforms. The current in the inductor, I(L1), also becomes the expected triangular wave rather than the more curved wave found above.
Can anyone explain in terms of what is happening in the circuit why the droop happens? and also why the current in the inductor looks as it does in the first set of graphs?
AI: First, one misconception to clear up. You said:
as the Vs (which should be a square wave) massively droops and therefore the Vho is too small to turn on the high side MOSFET for the normal time expected.
However, you have a boot-strapped driver. It maintains a Vgs of about 15V (from VCC) at the gate. If you plotted both v(ho) and v(s) on the same graph, or (v(ho) - v(s)), you'll see the 15V is maintained when the gate is supposed to be on. Put another way, v(ho) looks weird because v(s) looks weird.
Which gets to the first problem with the 100µH inductor simulation: your currents (i(L)) vastly exceed what C1 and C3 can supply to keep v(va) near mid Vrail. Take a look at v(va) and it'll probably be swinging wildly around.
The second problem, which Tony mentioned, is the Rdson of your MOSFET. Looking at the part datasheet, it looks like it is about 0.25Ω nominal. Based on your inductor currents, it's one of the culprits for the crazy v(s) waveform. 50A at 0.25Ω Rdson gives 12.5V drain-source drop, which is dangerously approaching saturation in this device. The Rdson also explains what you call "droop" in the second simulation. |
H: Rectified current transformer output is asymmetric
I'm using a current transformer (CS4200V-01L) to measure the current in a half-bridge. I'm facing an issue where the signal out of the current transformer is asymmetric, almost as if the current transformer is DC biased. This is the rectified signal, measured across R42:
Below is the relevant circuit extract. The signal is rectified, fed to the burden resistor (R42), low pass filtered and fed into a microcontroller in the range 0 to 3.3V.
How come the signal is asymmetric? I figured that the current transformer operated as a floating current source - my simulation seems to think it is too.
Obviously there's something else going on here. I thought the transformer may be saturated but the current doesn't look to be higher than 20A and the transformer has a maximum sensed current of 35A. Also it does the same thing at 10A, and I don't think that would explain this problem anyway.
Any input would be appreciated.
AI: Bad assumptions
It is not saturated. It is poorly driven by a dual switch so that the currents are unequal. Show your drive details or else double the Vgs.
A current transformer never saturate from excess current, rather only excess voltage where the typical threshold is -10% inductance
The rated voltage is 1V out using max current input of 35A for \$R_T=5.7\Omega\$.
instead you used 40 Ohm Load with sense Voltage on 1K+0.1uF AC coupled, which although not significantly different as you indicated , has exceed the Tesla or weber/m of 1Vsec. /35A.pri.
The fundamental reason of asymmetry is due to your rectifier source not being symmetrical with 2 identical FETs yet different Vgs voltages (apparently) resulting in different RdsOn and compared to 40 Ohms transformed down to primary side presented a significant “Kirchhoff resistance” of I*RdsOn drop in the high side FET.
You assumed we know where your Nodes captured are located
You assumed you had a symmetrical linear circuit |
H: BJT Common Emiiter RF-Design Simulation
I'm trying to learn about RF amplifier design and build a common emitter stage with an BFR92P.
And now I'm struggeling with the simulation in LTspice, or maybe with reality.
As you can see attached is a simple common emitter testcircuit, that I have tried to optimize . .asc -file: https://drive.google.com/file/d/1T7y4zdWiqA7fs3u-jYscfxaS7kk1qGwp/view?usp=sharing
Stepping Re from 200 to 800 ohm there is a sudden change in amplification. 350ohm is maximum an 400ohm is completely broke down.
I can't see this from DC characteristics (also attached) or I don't unstand something fundamental
The spice model is from infineon.
Maybe someone can help me to understand what's happening and how get a maximum voltage amplification.
Many thanks
AI: If you increase the value of RL, the bias point of the collector voltage drops. If it gets too low, the BJT goes into saturation operation rather than forward active. In saturation, the \$h_{fe}\$ parameter of the BJT drops dramatically so the gain of your circuit also drops.
If you're really going to use this in an RF context, you should include the load impedance in your model. It won't affect the bias because you've AC-coupled the output. But it will likely reduce the RF gain of your circuit substantially.
If you don't consider the load impedance, you're likely to choose the wrong value of RL for optimizing the circuit's gain in the final application. |
H: RS-232 to I2C communication
I'm trying to establish communication between two boards, one of which has an RS232 output and the other with an I2C input. I've looked for adapters online and the only ones I've found seem to be RS232 to USB, which is not what I'm looking for. Is there a limitation in the technology that I've overlooked? What is the difficulty in converting RS232 to I2C?
AI: I2C is half-duplex. RS-232 is full-duplex.
I2C has addresses, RS-232 does not.
I2C specifically writes/reads registers at the destination. RS-232 just send arbitrary bytes.
They are completely different protocols used for completely different things. There is no set relationship between the two and so there is no way to generic way convert between the two. Whatever device sits in between needs to know the context of the messages being sent and received since it must read and re-interpet the messages.
It's like asking why can't I find something that automatically converts books into movies? You just can't run it through a set process. You need someone who knows both books and movies to sit down, go through the book, re-interpret it coherently, then make the movie.
Or it's like trying to translate cultural references in media works. You can't just run them through a set algorithm. You need something in between that understands both languages (understands both protocols) and understands both cultures (knows the context) to do the translation. Hell, it's tough enough to translate cultural references even when you don't have to worry about the language. |
H: Is Brownout Reset Circuit a standard or optional safety feature in an MCU?
I've been using STM32 MCU's without paying attention to the BOR circuit:
Some datasheets indicate that the device has a built-in BOR circuit but some doesn't include such an information.
Is it always a MUST to have a BOR circuit? Is it a standard feature nowadays which might be covered by some other feature (such as Power On Reset) or is it an optional safety measure where we must implement by an external circuit if datasheet doesn't explicitly state the BOR circuit existence?
AI: There is no governing body that decides what is "standard" in a microcontroller. You must always check the datasheet. |
H: Am I testing diodes properly?
I decided to test some diodes that I have, using a multimeter to measure their forward bias voltage. I set my multimeter to voltage test and connected the diode across:
I tested a bunch of different diodes, both germanium and silicone type, so I expected to see voltages around 0.2 - 0.7V. However, all diodes showed 0V!
I tried reversing the polarity of the diodes, as well switching multimeters. Always my measurement came out as 0V. So am I making some kind of mistake in measuring diodes, or are both of my multimeters/all diodes broken?
AI: In voltage mode, a multimeter just measures what voltage is present between its leads. What you want is diode test mode, which is usually indicated on the dial with a diode symbol. On your meter, it's the option one to the left of your voltage mode--set the dial to that and press the mode button a few times to put it in diode mode; it'll say on the LCD. In diode mode, the meter applies a known current to the diode -- you can check the meter's datasheet or instruction manual to know what current it uses, and fancier meters might even let you select a current -- and then measures the voltage across the diode.
Note that this usually won't work for LEDs, as most meters limit their diode test voltage to only one or two volts, which is too low to turn on any LEDs except maybe some red or yellow ones. But for a conventional diode like the one you show in the picture it will work fine. |
H: How to correct this solder?
I have repaired this circuit from a fridge but the soldering that I have marked in red seems to have pulled away from the copper track. That is because when I tried to replace the capacitor that was there, I had to pull and that was the problem. I have almost cut the track.
The circuit is now working, but I don't know if I can repair this in some way.
AI: Make sure that any components that are attached to the pad are attached to the board in a mechanically sound manner. A little dot of epoxy glue or hot glue should do. You'll have to use your judgement.
Then make sure that the trace has enough copper to carry the current it used to. Use your judgement -- usually this is repaired with a bit of bare wire, or copper foil.
If it won't move, and it won't burn up, you're done. |
H: How to connect solar panel to boost converter
Here I design a boost converter with 5 V input and 19.37 V output
and it is working very well when the source is DC battery
but when the source is a solar panel with also 5 V output I have no boost for the voltage did anyone know why this happens??
Here is the solar panel description:
Brand: GH Solar
Solar panel 10 W
Solar cell poly technology
Dimensions: 25.5 X 34.5 cm
Voltage at Pmax: 17.8 V
Current at Pmax: 0.57 A
Here the boost converter's input parameters
Vin: 5 V
RL: 100 Ω
Cout: 470 µF
Cin: 470 µF
L: 560 µH
AI: The huge difference between a battery which is a voltage source and a PV panel which a current source is impedance.
A charge needs a low impedance based on the need for a low voltage drop to rise in current ratio.
Any time voltage is transformed up by N, impedance is also transformed down by N\$^2\$ thus stressing worse your design problem of impedance mismatch.
Your goal , should you wish to learn, is to compute the required PV source impedance to drive your effective load impedance using : Load ESR/N^2=Voc/Isc=Zsource=V/I @ Pmax.
for OC=open circuit and SC= short circuit
Z(L)=2pi*f * L |
H: What connectors should I use with 5V DC current?
In a personal project, I need to power several 5V appliances which, together, use up to 12A.
I want to use a 60 inch cable between a case to which those appliances are connected, and the transformer with 230V AC in and 5V DC max. 30A out.
When I look at the specification for the cables and the connectors, they are all rated pretty low in terms of maximum amperage allowed. For instance, standard C13/C14 connectors used for personal computers are rated 10A.
I suppose that those ratings are likely to be for 250V AC.
Is it safe to simply scale the ratings down to 5V, so 10A for 250V would mean a power of 2500W, and so a maximum of 500A at 5V?
If not, what calculations should I use to determine the required AWG size of the cables and the type of connectors that I am allowed to use?
AI: Your best budget solution is to use 2 pairs of Molex 4 pin HDD contacts rated for 10A ea. for your 5V distributed loads.
These are used in PC towers to interconnect 5V/12V peripheral power with the centre pair joined at source and load, as ground return.
Use 1 connector pair for each peripheral and use wiki AWG tables for cable resistance per unit length of each cable. Voltage drop on each wire is I*R/m * m length.[ or ft]
LV contacts are always for current as temp rise increases with \$I^2Rs=Pd\$ for contact Rs. Hot insertion is not recommended to reduce pitting of contact surfaces and rise in Rs.
Use the largest AWG that you can to minimize the voltage drop or according to your load error budget, based on Ohms/ft or /m Vdrop=IR X2 for R length of cable.
If you care to use AWG 14 stranded or welding cable with jumpers to crimp or soldered pins that would be ideal, but if you can get away with xxx mV cable loss, lighter cable is O.K.
Use AWG tables Ohm/ft to compute drop and (x) for each wire length x Amps to achieve less drop than your voltage error tolerance. It’s not rocket science.
The contacts may be 5 to 30 mOhms max initially then may increase with aging abuse. So again from Ohm’s Law V=IR , each contact has a small,voltage drop. |
H: How do I figure out the equivalent resistance of a network of resistors on a microcontroller?
I am trying to figure out what the equivalent resistance would be at a certain point in a resistor network given different conditions of the GPIO pins they are connected to.
Configuration 1 is when the OUT pin on the micro is driven HIGH: In this case I know R1 and R3 are in parallel to one another, but I'm blanking on whether or not R2 would be a factor to the overall resistance seen for a device plugging into P.O.I? also blanking on what the voltage would be as seen on the IN pin.
Configuration 2 is when the OUT pin on the micro is driven LOW, this case I have the same questions as above with the added question of can we consider R2 and R3 as parallel resistors?
AI: Quick Answer
The equivalent impedance at P.O.I. is simply the two resistors in parallel \$R_1 \parallel R_3\$.
Detailed Answer
We make the following assumptions in this analysis:
The node IN has "infinite" input impedance -- its impedance is high enough that near-zero current flows through \$R_2\$ and so \$R_2\$ has no influence on the equivalent impedance seen.
The node OUT has "zero" output impedance -- when it is high we can treat OUT as a dead short to 3.3V, and when it is low we can treat OUT as a dead short to ground.
The equivalent impedance for the other resistors is found using Thévenin's theorem, which basically says that we can model this point by a voltage \$V_{th}\$ and a resistance \$R_{th}\$. To find these values, we find the open-circuit voltage \$V_{oc}\$ at P.O.I. if it is left as an open circuit, and the short-circuit current \$I_{sc}\$ through P.O.I. if we tie it to ground. Then \$V_{th} = V_{oc}\$, and \$R_{th} = {V_{oc} \over I_{sc}}\$. So the analysis becomes pretty straightforward:
If OUT is high (3.3V):
$$V_{th} = V_{oc} = 3.3V$$
$$I_{sc}= {3.3V \over R_1 \parallel R_3}$$
$$R_{th} = {V_{oc} \over I_{sc}} = {3.3V \over {3.3V \over R_1 \parallel R_3}} = R_1 \parallel R_3$$
If OUT is low (0V):
$$V_{th} = V_{oc} = 3.3V \cdot {R_3 \over R_1 + R_3}$$
$$I_{sc}= {3.3V \over R_1}$$
$$R_{th} = {V_{oc} \over I_{sc}} = {3.3V \cdot {R_3 \over R_1 + R_3} \over {3.3V \over R_1}} = {R_1R_3 \over R_1 + R_3} = R_1 \parallel R_3$$
So in both cases the impedance at P.O.I. looks like \$R_1 \parallel R_3\$, but the impedance is connected to a different effective voltage at the other end, depending on the voltage at OUT. |
H: Why do stoves need not be connected under the earth leakage?
On some stoves I've seen stickers stating that the stove doesn't need to be connected under the earth leakage... Which is rather confusing since we need to earth it in case of earth faults.
I'm just struggling to understand why a stove shouldn't be under earth leakage. Any information on this will be appreciated
AI: The sticker is not saying that the stove does not need to be earthed. It is saying that the stove does not need to be protected by an earth-leakage circuit breaker.
simulate this circuit – Schematic created using CircuitLab
Figure 1. A domestic fuseboard layout - Irish style.
Due to the amount of steam and spillages produced in cookers and stoves the likelihood of earth leakage is quite high. If the stove was protected by an earth leakage circuit breaker (ELCB / RCD / GFCI) nuisance tripping would become a problem. Because the stove is a fixed installation and more likely to be installed professionally the assumption is that the earth connection will be good and protect the chassis from reaching dangerous potentials. Similar decisions can be made for water heating, etc.
The highest risk of electric shock comes from portable appliances where cable damage, DIY errors, and accidents such as cutting through the hedge-trimmer cable, etc., are common and so earth-leakage detection is applied to all power sockets.
Interestingly lighting circuits can also be exempted on the basis that the number of accidents resulting from people stumbling around in the dark trying to find the fuseboard would exceed the number of electrocutions from lighting circuits which tend to be well out of harms way. |
H: Circuit requirements for 'fixed' output switching regulator
I am considering using one of these switching regulators in a circuit:
TPS560430YFDBVR ( output type PWM )
TPS560430X3FDBVT ( output type 'fixed' )
The datasheet for both are the same thing:
http://www.ti.com/lit/ds/symlink/tps560430.pdf
The datasheet gives this example of a simplified schematic:
The feedback voltage divider RFBB / RFBT can be used to adjust the desired output voltage.
The datasheet also says "Fixed 3.3-V Output Option". Presumably with a non-adjustable output the voltage divider is not necessary, so the circuit would be somewhat different. However I can't find any mention of how it should be arranged.
Should FB connect directly to VOUT in this case?
AI: Yes FB must be connected to output when using the fixed 3.3V version. |
H: Do you really need a satellite dish to communicate with satellites?
I'm doing a project where I have ground sensors that detect seismic activity and report their GPS coordinates via APRS if seismic activity is detected. I'd like to do the APRS over satellite.
The sensors are small and utilizing a satellite dish for each one would not suit my needs.
There is a product I came across called the Thuraya satsleeve for smartphones that is satellite-enabled and doesn't require a large antenna or dish to make satellite calls and send satellite text messages.
So would a small antenna work for APRS over satellite? If yes what kind of antenna would be appropriate? If no why?
AI: Do you really need a satellite dish to communicate with satellites?
No, if that were true, your phone's GPS would be rather unwieldy, wouldn't it? And satellite phones would be pretty impractical. (Satphones predate modern smartphones solidly.)
All that a satellite dish is an antenna with a very high directive gain. So, if your link budget says you don't need that, you can use a smaller antenna.
No general answer can be given – the amount of directivity you need is defined by the link budget, and the type of antenna you need to achieve that directivity is defined by the wavelength of your transmission.
Considering your previous question, I think I'd recommend looking into what a link budget is. To give you an idea, we can do a quick rough calculation based on purely fictive numbers.
\$\text{SNR}_\text{min}\$: APRS required SNR at receiver: 10 dB
\$b\$: APRS signal bandwidth: 1 kHz
\$\text{NF}\$: Receiver Noise Figure: 4 dB
\$N_0\$: Thermal Noise Density: -174 dBm/Hz (at 20 °C)
Required receive signal power at receiver: (-184 dBm/Hz + 30 dB Hz) + 10 dB = -144 dBm
Operational Carrier Frequency: 10 GHz
Transmitter – Satellite Relay free space distance 500 km
Satellite Relay – Receiver free space distance 500 km
Free space path loss per direction:
\begin{align}
\operatorname{FSPL}(\text{dB})
&= 10\log_{10}\left(\left(\frac{4\pi d f}{c}\right)^2\right) \\
&= 20\log_{10}\left(\frac{4\pi d f}{c}\right) \\
&= 20\log_{10}(d) + 20\log_{10}(f) + 20\log_{10}\left(\frac{4\pi}{c}\right) \\
&= 20\log_{10}(500\text{ km}) + 20\log_{10}(10\text{ GHz}) - 147.55\\
&= 20\cdot 5.7 + 20\cdot 10 - 147.55\\
&= 114 + 200 - 147.55\\
&= 366.45
\end{align}
Satellite Down- and Uplink antenna gains: 13 dB
Relay amplification on the satellite: 60 dB
Output power of your transmitter: 60 dBm (that's 1 freaking kilowatt at 10 GHz; that's nation-state level stuff)
Let the ground station antenna gains be undetermined, called \$G\$ at this point:
\begin{align}
-144\text{ dBm} &\overset!\le 60 \text{ dBm} + G_\text{TX} - \text{FSPL}_\text{uplink} + G_\text{Sat, uplink} + A_{sat} + G_\text{Sat, downlink} - \text{FSPL}_\text{downlink} + G_\text{RX} \\
&=\left(60 + 2\cdot 13 - 2\cdot 366.45 + 60\right)\text{ dBm} + G_\text{TX} + G_\text{RX}\\
&=\left(60 + 26 - 732.9 + 60\right)\text{ dBm} + G_\text{TX} + G_\text{RX} \\
&\approx -600 dBm + G_\text{TX} + G_\text{RX} \\
G_\text{TX} + G_\text{RX} &= 356 \text{ dB}
\end{align} |
H: Ondulatory routing in Raspberry Pi
I bought a Raspberry Pi and I noticed some of the routings are not straight lines but instead they make a funny ondulatory shape (see picture at the right and bottom of the processor).
I'm not sure the reason of this shape. I have two guesses:
It makes this signals slightly delayed compared to others.
It makes the the route a certain exact length which would avoid resonance frequencies.
Are my guesses correct? Or this shapes are for something else?
AI: You are correct, these meanders are used to get exact timings of the signals. It is necessary to match differential pairs with high speed signals. |
H: NE555 power controller not working with big motors
simulate this circuit – Schematic created using CircuitLab
Backstory:
Ok, so I thought that a making a PWM controller would be a fun weekend project, it's been a week now and I still can't make it work properly. The circuit I'm using is from this website.
The problem:
The circuit works perfectly with "small" motors e.g. 12V fans, 9V hobby motors and so on. When I connect a "bigger" motor such as the one from an electric drill or even RC car motors it just doesn't work. I can hear some humming and buzzing comming out of them but they won't even turn.
I've tried changing the frequency to no avail.
I know that the pwm signal works by hooking up leds and fans.
I've tried switching the mosfet for other ones laying around and still nothing.
AI: Big motors seem to wreak havoc on circuits because they make so much EMI noise and specifically with your circuit, you're trying to shove some back EMF into your power supply during the off portion of your PWM. If you have a 12 volt lead acid battery around you could try using the battery just for the motor supply and then only connect the ground of the battery to the ground of your circuit, that should isolate the two enough to see if it works (the battery is big and dumb and can accept the inductive spike). If it works then your problem is that your power supply can't accept power back from the circuit (likely) so you need to protect your power supply.
It also may be worth asking, this is a DC brushed motor you're driving right? A brushless motor will not work... I'm not insulting your intelligence, just covering all my bases. |
H: P-MOSFET failing
I am using this solution to drive a large (huge) relay on a boat.
The system works well for months on end, but eventually the MOSFET (T2) dies suddenly.
I have modified the schematic to include the modification suggested by Jack Creasey and others (circled in RED, not part of original design), as well as a further explanation as to how the system is wired to battery ground to illustrate why the typical snubber diode may be inadequate (it dissipates back-EMF to battery ground through a 4-ohm wire).
Simulations suggest that with this cable resistance back-EMF may push LOCAL_GND down to -20 V with respect to BATTERY_GND, the controller would see 34 V and fry.
I am hoping to find suggestions on the correct way to protect the MOSFET in this situation.
I am not able to make modifications to anything outside of the gray box and no strong GND connection is available in this part of the system.
12VDC is the battery voltage and may vary depending on load, generator output, other loads switching, etc. Typically 11-14.4 volts.
The relay draws approximately 6 A from PULSE_OUT, but I have never had access to the actual relay to perform measurements on its inductance or behavior when switched on or off.
Because the relay is bistable and requires only a pulse to turn on, PULSE_TTL is driven with 200 ms pulses at 3.3 V. These pulses are typically very infrequent, but they can occur every 5 seconds worst case. Another identical circuit drives the turn off coil in a similar fashion.
AI: The answer is simple, you need a diode across the output wire to the relay.
When you turn the current to the relay OFF you will get a large negative back EMF spike on the drain of the FET (IRFR5305). The spike will likely far exceed the 55 V rating for the FET, and although the FET will avalanche this may not provide the required protection depending on the energy stored in the relay coil.
Connect the diode like this:
simulate this circuit – Schematic created using CircuitLab
While I've shown a BAT54 here, almost any power diode will do. Even an 1N4001 would be more than adequate.
Update:
Your update to the question posed what problems long thin (small gauge) wire to the really would pose. I would suggest that there is no problem.
If the wiring is sufficient to carry a peak current of 6 A to drive the relay, then current at turn OFF cannot be higher than 6 A, and will fall exponentially after the OFF drive transition.
If you are really concerned about your configuration then I'd suggest the following configuration where the FET is kept on to dissipate the inductive energy.
simulate this circuit
The waveforms would look like the above, but I just used a dummy L limiting to 6 A to demonstrate.
In the schematic above, the components in the box result in the FET being turned on at about 34 V back EMF from the relay. This is all reference to the +12 V supply, so is not impacted in any way by the wiring. Allowing the back EMF to develop to 34 V means the FET never sees anything above 44 V (12 V + 34 V) so comfortably within its 55 V rating.
And before anyone asks ….D2 does not clamp during the back EMF, the voltage on the gate will be just enough (V(GS)) to cause M1 to conduct sufficiently to clamp the drain voltage.
NOTE: Your base resistor to Q1 is too high. You should lower this to about 2700 ohms. |
H: Why are overhead electric wires allowed to have higher voltages than third rails for rapid transit railways?
I hope this question is on-topic for this site.
The city I live in (Chennai, in India) got a rapid transit metro rail a few years ago that uses overhead electrification of 25kV, 50Hz AC voltage to power the trains. I also know several other rapid transits over the world sometimes use a different method of powering trains called a "third rail", where a solid rail close the ground, which carries 700-1000V DC voltage to power the trains.
Doing some research, I read that the overhead voltages can carry high voltages since they are located high above the ground and thus, wont arc to the ground due to the capacitance, and the sheer magnitude of the AC voltage. This seems to be the reason why third rails use such thick rails, to carry high current with such lower voltages to output the same power an overhead rail would.
Now, the rapid transit in my city has some sections elevated and some underground. The elevated sections have a catenary wire like arrangement for the overhead electrification, while the underground portions have a solid metal rod attached to the top of a circular tunnel. A picture of this rapid transit's tunnel at a crossover is here:
Now, since the tunnel is underground, the earth surrounds the tunnel from all directions, including up. Wouldnt the same problem of the third rail, i.e, arcing to the ground also occur here. What is preventing the 25kV AC from arcing to the ceiling (which is infact the earth, so it's more or less similar to grounding).
Can someone please help me understand what I'm missing here?
Edit: another relevant picture of the tunnel itself for viewer
AI: According to answers to this question:
The breakdown voltage of air varies significantly due to changes in
humidity, pressure, and temperature. However, a rough guide is that it
takes 1 kV per millimeter.
Therefore your 25 kV overhead rods will be adequately spaced from the ceiling at a minimum of 25 mm / 1 inch; it looks like they have several times that.
The main reason for using lower voltages on 3rd rail systems is probably the size of the insulators to support the rail mechanically. Insulators aren't free air clearance; as the answer explains:
The breakdown gradient for creepage is lower than for clearance since
dirt can accumulate on surfaces. Some dirt is partially conductive on
its own, but many things can provide leakage paths after soaking up
some humidity.
Your second photo of the tunnel appears to show the clearance from the ceiling is rather less than the creepage distance along the horizontal insulators. It would be impossible to mount a third rail on insulators of that size.
The safety of line personnel on 3rd rail is a factor for the lower voltage, but not the only one: direct contact with a 3rd rail at less than 1 kV is likely to be fatal to a human. |
H: Amplifier Audio Ground to Signal Ground
I am using a VS1053 (on a SparkFun Music Maker shield) to provide audio for my project. I am taking a line out signal and inputting it into an op amp for signal processing, ultimately being input to an Arduino.
The op amp(s) are using Vcc and ground from the Arduino as their power supply. The module with the VS1053 also uses the same supply connections.
But line out is referenced to the audio ground created by the VS1053. In order to see the input signal, somehow the op amp and VS1053 must have a common reference.
An early circuit connected the audio signal ground to the circuit ground. But this is explicitly prohibited in the VS1053 data sheet. It seems to work but probably does do as a matter of luck. And will likely fail eventually.
How do I connect the line output of the VS1053 to an op amp?
Thank you.
AI: The three signals, L, R and GBUF are for driving headphones and will have a DC offset on them. GBUF carries common signal voltage, mostly for low-frequency signal. It’s a way of boosting the loudness of the headphones without using a higher supply voltage.
For line-out use, GBUF should not be grounded or connected at all, other than the filter that’s on the shield board. Instead, leave GBUF unconnected, and use blocking capacitors for L and R to to your line-out to the op-amp. Reference the line-in to the shield board ground. |
H: 555 IC astable mode - Does the voltage generally affect the frequency?
I'm new to electronics, and I'm messing around with the perennial 555 IC. I've been introduced to the following formula which allows you to determine the frequency of the output when put in an astable mode:
f = 1.44 / (r1 + 2 * r2)C
I noticed how voltage is not part of the equation. However, wouldn't the VCC of the IC affect the frequency (generally speaking)? Internally, the IC creates a voltage divider and uses 1/3 and 2/3 of the VCC as references for the comparators. If VCC is 5 V, and it takes an x amount of time for the external capacitor's charge to build up and for the voltage to rise from 1.667 V to above 3.333 V, would it not take longer if VCC were 9 V? The references would now be 3 V and 6 V. If no components have been swapped (external capacitor, resistors), would it not take longer for the voltage to rise from 3 V to above 6 V? Or does the increase in voltage charge the capacitor faster, and the effects cancel out?
AI: Voltage is not part of the equation, and that is because the voltage does not matter.
I confirm that the default voltage references are 1/3 and 2/3 of the VCC.
The RC time is also constant. In electronics we can use RC time simply because it does not depend on voltage when using a constant voltage accros the R+C components in series.
When the voltage scales, all other properties scale accordingly, including the compare levels.
When VCC increases from 5V to 9V, the capacitor will charge faster from 1.667V to 3.333V, but it will require the same time to charge from \$\frac{VCC}{3}\$ to \$\frac{{2}{VCC}}{3}\$.
The RC time can be used as follows: if your capacitor is charged at V0, and you apply Vtot accross the RC series circuit, then your final voltage will be V0+0.63*(Vtot-V0) after a delay of RC. The 63% percentage is constant. You can replace Vtot with VCC and V0 with VCC/3. After one RC, the voltage change is \$\frac{VCC}{3}+\frac{{0.63}{2}}{3}{VCC}= (\frac{1}{3}+\frac{{0.63}{2}}{3}){VCC}\$ = about 75% of VCC. So, expressed as a % of VCC, the voltage change is constant and it will always reach 2/3 of VCC in the same delay. |
H: ESP32 with FTDI programmer
I recently broke my USB port on ESP 32 ...
... so I need somehow program it. I have this FTDI programmer. ...
I tried to flash it (I pushed boot and EN button together and when Arduino IDE finished compilation and started flashing, I released EN and then boot button.)
Connection:
ESP 32 VIN ... VCC programmer (3.3 V)
ESP 32 GND ... GND programmer
ESP 32 TX ... RX programmer
ESP 32 RX ... TX programmer
After this attempt I get this error:
I tried to use this programmer to program Arduino nano and it works.
Do you have any sugesstions about programming this ESP 32 without USB port?
AI: It's unclear from the image if you have set the FTDI adapter to the correct voltage 5.0V or 3.3V (it should be 3.3V).
I have experience programming bare ESP32 modules in this manner, but never a break-out board like this.
Looking at your log and reading through esptool.py is seems clear that you have communication in both directions, otherwise it should have failed earlier - BUT I would verify this by disconnecting one wire (TX, RX) at a time and try a download, just make sure that the download behavior does indeed change.
How are you powering the ESP32? It looks like you are taking VCC from the FTDI adapter. The ESP32 is a bit power hungrier than many other controllers, are you sure your FTDI adapter is able to power it adequately?
Removing the USB/TTL bridge should not be necessary as it should be passive with no USB connected, and most ESP32 breakout boards include a resistor on the bridge TX output to make sure you can "override" the signal externally, like you are doing now. However, if you keep being unable to program I would remove it or cut the relevant traces just to be sure. |
H: Relative difficulty between leading zero counting and addition
Consider a 32-bit or 64-bit ALU that must implement both count leading zeros and integer addition, with low latency (say a few cycles), implemented on a modern high frequency logic process.
Which is generally more complex, a fast adder or a fast leading zero count?
AI: For a 64-bit leading zero counter, what you'd need is at most a 6-NOR-deep combinatorial chain plus one XOR (or equivalent) ("is the first bit zero, and the second bit one", "are the previous bits zero, using the result from the previous step") and 6 bit LUT.
That's very little.
A trivial ripple-block carry lookahead adder with 64 bit operands needs six stages, so it might be minimally faster, which is also very little.
In other words: I can't give you a definite answer; actual fast implementations will depend on the standard blocks that the hardware designer can employ: for example, on a modern high-performance FPGA, you'd either just use an arithmetic block (and not care about the design), or build it from 6-LUTs; so, these combinatorial considerations have no relevance to FPGA design. On an ASIC of an actual silicon CPU, neither components will be close to being the most complex things to do during a single clock cycle, and thus, more combinatorial steps in favor of e.g. lower routing overhead or lower switching probability might be favored. |
H: Does anybody have PCIe (3.0) aka PCI Express module card edge connector technical drawing?
I was searching through the internet to find PCI Express card edge connector footprints / technical drawings / pin spacing / layout of the module cards that you stick in these connectors you can find on a modern PC/server motherboard.
I wasn't able to find anything so I thought I could maybe ask here? I found some for Altium Designer which I don't have access to and also I am using (Autodesk) Eagle.
If you are wondering, I wanted to create a PCIe 3.0 x8 card that could hold two M.2 NVME SSDs since I could not find this anywhere either. Everyone only sells the type that holds one NVME (PCIe) and one SATA SSD. This is not what I need.
M.2 NVME interface is basically just a PCIe x4 interface, in another form factor. Therefore I don't see a problem with making a x8 standard card for PCs/servers that could hold two of those and properly route their interfaces.
Can anyone help? Thank you!
AI: The official PCIe spec from PCI-SIG has this information. It’s downloadable from the PCI-SIG site for a fee, it’s free download for PCI-SIG members. Link: https://pcisig.com/specifications
By the way, Supermicro lists that kind of adapter (half-high to 2x NVMe.) Here it is on Amazon: https://www.amazon.com/Supermicro-AOC-SLG3-2M2-PCIe-Add-Card/dp/B071S3ZY8P
Check also ASUS, AIC and Funtin. These are ‘passive’ adapters that rely on the host to bifurcate the PCIe lanes - which means newer motherboards only with appropriate BIOS support (intel x299; AMD x399, Epyc, etc).
Amfeltec has an active adapter that can hold up to 4x M.2 in a half-high slot. It includes a switch and it’s rather expensive. It would literally be cheaper to get a different motherboard and use lane bifurcation.
If you can live with a full-height card there are more choices. The ASUS Hyper16 card, which takes 4x NVMe seems to be the most cost-effective. ASRock also has one. |
H: seek resources in design amplifier
I'm an electrical engineering student in my summer training. My adviser is busy, so my training is self-learning, I'm supposed to learn RF circuits, ADS, and finally, design an amplifier do some cool things.
To reach my trainee goal designing an amplifier in RF, can you recommend sources(slides/videos/book/Udemy-course) in amplifiers design?
AI: That's a bit tricky - ask a dozen RF engineers, and you'll probably get a dozen different answers.
I think the best "cookbook" resource I've personally encountered is RF Circuit Design by Chris Bowick. I have the second edition, but if you can find a used first edition for cheaper, feel free to grab it. The second edition added two chapters that weren't written by the original author that are mostly useless and disconnected from the rest of the text.
If you don't have it already, you should get a copy of Microwave Engineering by David Pozar. The current version is the fourth edition, but I have the third edition and that has suited me just fine. It is a great general purpose theory textbook that provides a strong theoretical view of almost every major topic in RF engineering. It does not take a deep dive into any of them, but it provides an excellent reference for developing a strong understanding of fundamental theory. If you are looking for a cheap copy, there are international editions available from online booksellers like AbeBooks for 1/10th the price of the US edition.
I would recommend starting with designing a low noise amplifier (LNA) rather than a power amplifier (PA). LNAs operate in their linear region, so provided you bias the transistor correctly and stabilize it, there is not a whole lot that can go wrong. Also, since LNAs operate with relatively low quiescent current, you don't have to deal with thermal management.
If you are using ADS, Keysight has a nice video series on power amplifier design. Many of the principles are also applicable to LNA design.
Whatever you design, I encourage you to actually build and test it to see how well your simulations match up with reality. RF test equipment is tremendously expensive (a half-decent starter Vector Network Analyzer that operates from DC to 6 GHz runs around $30k USD), so you will probably need to find a friendly professor willing to let you into his or her lab to do your tests. Make sure you ask plenty of questions when you go to use the equipment - like I said, it's quite expensive and things are easily broken. Most likely a prof or their lab tech will be happy to help out a keen student who's building an amplifier as a self-learning project. |
H: 74LS74AN Binary Up-Counter
I have an issue with my binary up-counter using a 74LS74AN D-Flip Flop
The issue is the following:
I am trying to toggle the flipflop state by sending it a 1Hz Square wave (5V Peak) to make it toggle every clock cycle (Rising Edge triggered)
This is the schematic I came up:
And this is the datasheet:
https://pdf1.alldatasheet.com/datasheet-pdf/view/12660/ONSEMI/SN74LS74AN.html
For some reason the flipFlop will not toggle when the LED is connected. I have measured at the D-Pin with the LED connected and it reads 3.3V roughly. Which is expected when the 74LS74AN Outputs at 3.5V. According to the datasheet High Level is 2V.
I already tried out another chip. I got the same issue there.
My idea is:
!Q Starts out HIGH, so when the CLK goes HIGH the FlipFlop will latch HIGH, so !Q will go LOW. On the next clock cycle the FlipFlop will latch LOW so !Q goes HIGH again.
AI: Connect the LED from Vcc through the resistor to the Q output (with the proper LED polarity, of course).
simulate this circuit – Schematic created using CircuitLab
The 74LS outputs can sink 8mA so the resistor should be no less than about 400 ohms. Try 510 ohms.
The sourcing capability is much less, as shown in this datasheet. The currents (-0.4mA and 8mA) represent the maximum loading with which the output is guaranteed to have valid logic output voltages including noise margin, if you abuse the output and don't need it to have a valid logic level you can get much more current but I don't advise that. |
H: Where does return current flow for a differential signal?
As far as I understand, return current flows the "negative" channel for a differential signal connection. Only if it is not balanced well, there might be unwanted return current in reference GND or power plane.
But some say the return path for both positive and negative are always the reference plane, which get me confused...
AI: It depends on the physical geometry of the transmission line.
I can route two tracks on a PCB, not too close together but matched in length, and use them as a differential pair. In this case, each of the individual lines will have its own return current on a nearby ground plane.
Or I can make a closely coupled pair of tracks on the PCB, with the line-to-line spacing less than the line-to-ground spacing. In this case most of the return current will be in the complementary line, but there will likely be some return current in the ground plane near each line.
Or I can make a purely differential line, like unshielded twisted pair, and pretty much the only return current for one line will be in the other and vice versa. |
H: What is the purpose of Vih and Vil in the comparator's datasheet?
Looking into the MAX999 datasheet I can not figure out how to utilize information given for the Vih and Vil
Logic-Input High --- Vih --- (Vcc/2 + 0.4) min
Logic-Input Low --- Vil --- (Vcc/2 - 0.4) max
The rest of datasheet says nothing about inputs' ability to be configured as logic inputs - it is the output which is logic level. What is the purpose of this information then?
AI: It's for the logic inputs: SHDN - shutdown; and LEA - Latch-Enable Input -
When SHDN is high, the MAX961/MAX963/MAX964/MAX997 is shut down.
The MAX961/MAX963 include internal latches (ie the LEA) that allow storage of comparison results.
The MAX999 doesn't have any of these logic inputs. |
H: Do electronic fiber optic selector switches exist?
From my research, I have been having a tough time finding and specifying a fiber optic selector switch or multiplexer. Do fiber optic selector switches exist?
Background - Simple
I have an application with a not-cheap sensor that does the following:
Sensor emits light
Light travels and hits an object
The object absorbs some of the light, and also reflects some back
Sensor receives returned light
Sensor processes the change and reports a sensed value
You can have the object be far away from the sensor via the use of a fiber optic cable. I do so, and it works great.
As a cost savings, I would like to have one sensor be able to senses from multiple different objects. This can be done using a bunch of fiber optic cables and a fiber optic selector switch or a multiplexer.
Background - Detailed
To be more detailed:
Sensor is a pH sensor, EOM-pH-mini.
Object is a small pH sensor spot, SP-HP5
Fiber optic cable is polymer, POF
Conclusion
Does anyone here have experience in this area? In case you can't tell, I have none. Can you please provide insight into:
Suggestions of fiber optic selector switches
Important parameters in specifying the switch
If this is even possible?
Thank you in advance for your help!
AI: Yes, this product exists.
It can be made using MEMS technology, as an electromechanical device (a relay with a fiber attached to the armature), or motorized (and probably other technologies).
Important characteristics are
fiber type compatibility (single-mode or multi-mode, and what core diameter)
insertion loss
return loss
wavelength compatibility
number of inputs and outputs
switching cycle durability
power consumption
switching speed
control interface
...
There are numerous vendors for these products. You can start searching them by looking in trade magazines like Laser Focus World and Photonics Spectra, or from exhibitor lists at trade shows like OFC (Optical Fiber Conference) and Photonics West. |
H: please explain this fourier equaton
reference from here
why are there 2 exponential terms on right side of equation in red box ?
i know euler identity but why does ,the left side is trigonometry form when n=1 equal to exponential form n=1 + exponential form n=-1
AI: The n= 1 trig form must equal the sum of the +/-1 exponential terms because those two exponentials are the only terms in that entire infinite summation with the same period (frequency). Without even thinking about the math and the fact that sinusoids of different frequencies are orthogonal, at a purely intuitive level, if two frequencies are to be equal, they must have the same period and for a given n in the trig series, only the +/- terms in the exponential series have the same period. Therefore that expression must be true.
If you want to understand at a deeper level what that means, you'll get to that once you learn about the Fourier relationship between even/odd functions and positive/negative frequencies. |
H: Digital electronics - how does a circuit determine when some element (like adder) is done? (delay handling)
Take for example a ripple carry adder, how does a circuit handle delays of some elements?If ripple carry adder starts working from some clock cycle, we can't expect that it will have correct results on the next clock cycle.
AI: No.
The ripple effect takes as long as it takes. It is up to the designer to make sure that the result is stable when it is used.
On purpose I don't write "the next clock edge" as the designer can invoke a so called multi-cycle path. In that case the result is not used until two or three clock cycles later.
If this is supposed to be the next clock edge, the designer must make sure the clock frequency is low enough.
How are delays introduced?Are counters used for that purpose?
Sometimes but in general you try to avoid adding delays. From what I gather from your questions is that you are looking for the answer how to do what we call in the profession timing closure.
Timing closure is a very complex process which involves various solutions depending on if you have set-up, hold time or maximum frequency problems.
It would take many pages and is thus beyond the scope of stack exchange to tell you even the beginning principles and techniques, but I hope with that as search term you learn a lot from the internet.
Just for completeness: delays are only added when a register has hold-time problems but has slack in its set-up time. |
H: feedback loop component dc converter
Consider the schematics below, the switching frequency is 250KHz, So, The cross over frequency be 250/5 = 50KHz. My ADC is able to sample at 1MS/s which is good as from the SNR perspective.Now, the doubts are below
For ADC selection-sampling rate the switching frequency should be considered while determining the sampling rate or the Cross over frequency ?
for the buffer used the Bandwidth should be 2 to 5 times the cross over frequency or the switching frequency?
In case i want to use current shunt amplifier for current sensing, How to select from the Bandwidth point of view ?
In general i wanted to understand how the Opamp parameter be looked at for converter design - unity gain BW, 3db bandwidth etc, used in control loop ?
simulate this circuit – Schematic created using CircuitLab
AI: With a ratio of 5 or about 2 octaves with only a 2nd order filter you get -11 to -13 dB of ripple rejection at Fs and only half this at the Nyquist rate of Fs/2 so it will be noisy.
If your ADC is say 10bit with -60dB quantization level and you want to reject PWM noise, then a higher order active Bessel or Chebychev filter with the group delay and rejection is required or a sigma delta type ADC.
Search this site for better ADC designs and filters, and learn to make a list of test criteria or specs.!!!
define your specs for input SNR , BW and level range then desired output SNR + quantization noise. From this choose your filter and oversample Fs, with decimation is the best way done by Sigma Delta types or others, just as it is done in DSO’s with Gb/s sampling rates and xxx MHz signal BW.
Unless you also sense input /output current for forward PWM loop error correction with Vout , you will probably experience horrid startup currents and step load overshoot or fancier lead/lag compromises with ripple to improve stability.
You must use minimal lag (group delays) filters and latency for best 1st order stability. 2nd and 3rd order OA effects or 4th order ADC averaging effects all reduce stability. |
H: Why is the collector feedback bias popular in electret-mic preamp circuits?
I got some simple electret microphone modules and I've been experimenting with audio amplifiers. I googled to find some example circuits, and I found that most of them resemble the circuit above. I built this one and it works fine. If I'm not mistaken, this circuit is biased using the collector feedback bias.
Searching for a circuit, I noticed that most electret microphone amplifier circuits use the collector feedback configuration. I wonder why is it so popular, over other usually more common configurations such as voltage divider bias? I understand that the use of feedback in this configuration causes the amp to be more stable, but wouldn't a voltage divider bias have the same advantage?
AI: Most of the hobbyist circuits you find by googling are crap originating from dubious tinkering and then copied from each other. The bias level of this circuit is not very predictable from BJT to BJT (meaning it may clip at high level one way or the other depending on the capsule sensitivity and actual sound pressure level) and the distortion is relatively bad (due to the lack of negative feedback or emitter degeneration).
The JFET (internal to the capsule) is much less of a problem because the signal levels are in the mV at the drain so the signal current is a very small percentage of the bias.
Try looking for commercial pre-amplifier circuits or (generally much more expensive, but also good performance) application notes from companies trying to sell chips. For example this circuit from Maxim. TI has some designs as well. |
H: What components would I need to build a basic circuit that completes when something is pulled with a certain amount of force?
As an example, a rope tied to a tree when pulled with Y newtons would illuminate an LED but wouldn't when only pulled with X newtons.
I guess what I'm looking for is a basic force meter.
AI: Not sure what your mechanical requirements are, but if you can afford some movement when the rope is pulled, go with DKNguyen's recommendation of using a linear spring with a contact at the spring deflection distance that indicates your "Y newton" point.
Green is insulation and orange is conductor (supposed to look like copper, eh) so you can trim your insulation at whatever length will give you the desired "d" distance based on the linear equation for springs:
\begin{equation}
Force = Spring Constant * Distance
\end{equation}
In actual implementation you'll want a way to reliably hold the wire against the rounded contact and prevent corrosion if left outside.
You can also measure it remotely with a water filled syringe. Attached the plunger to the rope/spring interface and the body of the syring to the fixed end of the spring. Run tubing to a safe area and use another syringe with a limit switch or an open vessel with a float switch.
Lastly, if you can't afford motion or need more accuracy, you can use a load cell. You could measure the pull of the rope directly using an S-type load cell like a cheap one scavenged from a hanging luggage scale. You could also use a flat load cell and compress it using a Class 1 lever, this would also give you flexibility to use the cheapest 1/2/5/10 kg cell you can find and adjust the lever arm for the force range you expect to measure. Either way, you could use a wheatstone bridge to set a threshold and trigger a response or use an ADC to read the load cell digitally with a microcontroller if you need to get actual numbers from the sensor.
For the variable resistance stretching cord that OP found:
simulate this circuit – Schematic created using CircuitLab |
H: What kind of amplifier design is this?
I am dissecting a design and I'm trying to wrap my head around the design pictured below. It is based on the TL064C amplifier and takes in single ended audio and outputs single ended audio as well.
What kind of amplifier is this?
Here's the schematic:
I believe R15/C1 & R16/C2 are RC filters, for what it's worth.
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. Left channel. A proper schematic makes it easy to see the function of the circuit.
What kind of amplifier is this?
This should be pretty obvious now. If unsure then please modify your question. |
H: Intriguing obsolete(?) PCB manufacture techniques in this old MSX
Browsing Wikipedia (as one does), I have stumbled upon this picture of a circuit board¹:
Now, when you look at it, there are several things that stand out as being interesting and different to today's commonly used PCB manufacturing techniques.
I don't have access to the board pictured, but here² are some more pictures of it. However I do recall seeing other circuit boards using these techniques; especially on lower-cost devices from the late 80s/early 90s and remote controls.
So, here is what I'd like to find more about:
Multiple soldermasks?
There seem to be at least two levels of soldermask. One of which is visible only around the vias, and the other opaque one covers and conceals stuff further.
What's the purpose of this second, very opaque layer?
To hinder reverse-engineering of the PCB layout. This however doesn't make that much sense to me, since the PCB pictured comes from an MSX computer, and AFAIK the MSX architecture was pretty much an open standard. Also, this additional opaque layer is absent on the bottom side.
Or is this not just an opaque soldermask, but that and another (rough) conductive layer over another (what you'd think of as traditional) soldermask; which would make some sense here too, perhaps for EMI shielding. Is this it? Another thing going for it is the large clearance around the vias.
Or is it something else entirely?
Blue vias
Don't the vias look interesting? How were those made? It seems that they did not use (now ubiquitous) plated through-holes manufacturing this board.
But what is this that they used instead and how were those made? Is this some sort of conductive epoxy?
The (relatively) large via size could be justified by it. It also seems like the material over the vias is rather concave with likely designed-in overlap over exposed copper around the hole. Were those filled-in one-by one?
Now, why did they use this method instead of the "modern" PTH? I suspect it must have been significantly cheaper for small enough number of holes. What would this method be called?
Searches for epoxy-filled vias do yield results, but of different-looking ones to this.
This is my first question here after all this time; I know however that having multiple sub-questions is sometimes frowned upon, but I hope this still counts as being reasonably related enough. Thank you for your answers.
I also hope some others find this as interesting, with the epoxy via technique perhaps finding another life in my homemade PCBs.
¹) Image taken from Wikipedia by Yaca2671. Wikimedia link
²) MSXinfo.net article on Panasonic FS-A1WX
AI: This appears to be a punched board (the outline and all the holes are punched in a single operation) with conductive liquid used to create vias. This is sometimes called STH (silver through hole) technology.
If you look at the holes where there is no via you can see that they are relatively rough and quite a bit larger than you might have for a drilled hole. This also helps speed assembly by minimizing accuracy requirements for machines or people.
Not sure about the solder mask appearance, maybe a second layer is applied (typically by screen printing) just to protect the vias.
My experience with this technology is that it's not all that reliable, especially in applications where a lot of vibration or shock is possible. It is very cheap per square meter because they can use low cost paper-based laminates and punch all the holes and outlines out of large panels in a single operation taking almost no time (on a cheap press too). Because the crappy cheap laminates are quite brittle (as anyone who has dealt with damaged cracked boards will attest to), they have to be heated in a batch before punching.
It was not all that uncommon in that era for factories to have quality problems with (what are now ubiquitous) plated through holes such as cracking around the holes, often caused by poor control of the various chemicals and processes involved, but those issues have mostly been vanquished. |
H: Floating input in Op-amp Readout Circuit?
I was analyzing this circuit diagram in a thesis about a capacitive EEG electrode. The author talks about a flaw in the design where there is a "floating analogue input" that is causing the op-amp to go to rail and consequently maxing out the output. She suggests adding a very high value resistor or even a Zener diode from the input to ground. I'm assuming that she means the non-inverting input of the gain amplifier. I think however that the cause of the floating input might be from trace input bias currents saturating the amp, but then the best solution would be to have the resistor to ground be equal to R10 and R11 in parallel in order to minimize offset voltage. Would the 100 ohm resistor between the buffer and gain amplifiers have any influence?
Should the resistor between the non-inverting input and ground be equal to the feedback resistors in parallel or have as high a resistance as possible?
The readout circuit consists of a buffer and gain amplifier.
AI: As people have said in the comments, the floating input is U3C pin 10, and R10/R11 don't have any influence on that.
The article Avoid Common Problems When Designing Amplifier Circuits from Analog Devices covers this pretty well. The situation with U3C is like Figure 1 of that article. (N.B. I don't have any expertise in EEG electrodes but I presume it's safe to model them as capacitive sources.) As shown in Figure 2 of that same article, the best solution is to provide a DC path to ground, ideally a high-value resistor.
As also mentioned in that article (and as you hint in your question) it is good practice to have both inputs of an op-amp see the same impedance, to minimize offset errors and other problems. So this would imply that the circuit needs two other modifications:
The path between the U3C output and the inverting input should not be a dead short, it should be a resistor of the same value that was just added to the + terminal. In practice this would mean finding a resistance that is high enough to work on the + terminal so the electrode still functions properly, but low enough that it still makes a good feedback resistor. I'm guessing 100k would work, though that's mostly a guess on my part.
R12 should be set to a value equal to R10//R11. The exact value is 952 ohms, but even a value of 1k ohms would probably be pretty good. |
H: Translating mic sensitivity dBV to dBSPL
In mic datasheets, mic sensitivity is usually expressed in dBV that equates to 94 dB SPL (@1kHz).
So if my mic sensitivity -46 dBV equates to 94 dB SPL, does that mean that if I double the signal by 2 (+6dB), a -40 dBV measurement will equate to 100 dBSPL for that mic?
I made a dBV to dBSPL calculator and based from this assumption (sens: -46dBV):
-46 dBV = 5mV (94dBSPL)
-40 dBV = 10mV (100dBSPL)
Are these correct? So the two dB units are just linear offsets?
AI: 94dB-SPL is a sound pressure level of 1 Pascal. This is the standard sound level used to characterize microphone 'sensitivity'.
A sensitivity of -46dBV means that when a 1kHz tone with intensity of 94dB-SPL is present at the microphone, it will produce an rms output voltage of 5mV. If you double this signal voltage using an amplifier then the effective sensitivity of the mic+amp is -40dBV, but the sound input for that output is still the same 94dB-SPL.
This figure means very little unless you know what the sound level relates to. A jackhammer at 1m distance produces 100dB-SPL, and hearing damage occurs over 85dB-SPL. So 94dB-SPL is far above the maximum sound level that the microphone will likely be used for. A more reasonable maximum would be 74dB-SPL.
If your mic+amp produces -40dBV from 94dB-SPL then at 74dB-SPL you get -40-(94-74) = -60dBV. If your 0VU level is -10dBV then you need a further 50dB of amplification to get full volume from a 74dB-SPL sound.
Sound pressure, showing sound-pressure-vs-frequency at different perceived loudness levels. |
H: Transformer ratings
What physical factors one needs to take into consideration (like maximum core field and saturation) to rate the "voltage rating" of a transformer?
Suppose that the voltage rating of a transformer isn't known (or you aren't allowed to look at its nameplate), is there an experimental way to determine the voltage ratings of the transformer?
As far as I understand, transformers are usually operated at their rated voltages. Also, if supply exceeds the rated voltage, current starts leaking through insulations, the core gets heated up and so on. Why then is it so that transformers are operated at a verge, voltages beyond which beyond could possibly harm the transformer?
AI: 1) Core saturation limits the maximum voltage.time product you can apply. Therefore at a higher frequency, you can use a higher voltage.
2) If you have a variable voltage supply, say a variac, or a sine-wave generator and a power amplifier, then measuring the magnetising current while increasing the voltage into a single winding on an unloaded transformer is the best way. Plot the measured current against the applied voltage. The graph will suddenly kick upwards at the onset of saturation. Exactly where you want to operate in the vicinity of this 'knee' is up to you.
If you don't have a variable voltage supply, then a constant or limited current supply from a high voltage is a good second. Use a low power filament lamp in series with a high voltage to limit the current into a low voltage winding. Measure the voltage developed. Note this is likely to be already in saturation, so you should operate comfortably below this.
3) Operating at the rated voltage, core heating occurs through hysteresis loss (function of the core magnetic properties alone) and through eddy current losses (function of its electrical conductivity and lamination thickness). If supply exceeds rated voltage, magnetising current rises dramatically and increases heating in the primary winding. Core heating increases a little due to the slightly increased field.
Transformers are operated at winding voltages suitable for their core saturation, and at maximum voltages between windings given by the insulation between the windings. If you exceed either of these, the transformer will fail. |
H: Will this High Frequency AC Signal Generator Circuit work?
I am going to make a variable DC to AC (10-100kHz). The circuit controlled by 2 PWM Signal from microcontroller to drive NMosfet connected to pull signal from two Ferrite core Transformer primary coil end which the CT connected to 3.3V. Here is the circuit
I simulated the circuit in Eagle, CircuitLab, and MultiSim. The circuit works great on MultiSim, sometimes work on CircuitLab, but it wont work on Eagle. Which makes me a bit hesitant.
What do you think about the circuit? will it work?
I am using [78253/35JC]2 for the transformer.
Thank you
AI: You have a push-pull configuration. I assume, you will turn: on positive->off positive->dead time->on negative->dead time-> ...repeat.
At 10kHZ with duty ratio 50:50, ommiting the dead time you get a voltage integral of 165uVs for each half cycle. So too big for a transformer that accepts 30uVS. You may not be able to work at lower frequency. |
H: Sampling Frequency and Bandwidth
If i have a Buck Regulator switching at 200KHz and i want to sample the Voltage and current using OpAmp in tha path connected to ADC(12 bit).
What would be the sampling frequency to measure the signal by ADC?
what shall be the Bandwidth of the OpAmp for Voltage and for current sense?
If somebody could provide some rule of thumb i could work further
P.S. : In my understanding sampling freq be >2 the switching freq.
voltage sense would require lower BW OpAmp as it is slow, i also get confused either to choose the Opamp based on cross over freq or switching freq.
AI: So you want to measure the mean value and not the waveform. At first place you have to determine what are the capabilities of your MCU. You will neeed an analog low pass filter on input of ADC to elliminate aliasing effect, then you can oversample and do a digital low pass filter.
For example: 1M sampling, 330kHz RC low pass filter, then a digital low pass filter - slighty higher cutoff frequency than the entire execution loop, let's say 20kHz.
BW of opamp is not an issue, you will hardly find an opamp with BW less than several Mhz. The high BW is desiderable an not viceversa, you do filtering with passive components RC, choosing a low BW product with the aim to eliminate high frequencies is a wrong way. |
H: I2C max pull-up resistors and current sink
I design a system with several devices connected to 400kHz I2C interface with wires.
For now, I get shark fins instead of square waves, so I decrease pull up resistors value. The MCU, which drives the I2C communication is STM32F303, and its datasheet states: "I2C Fast mode plus (1 Mbit/s) with 20mA current sink". Does it mean that each pin (Data and Clock) can sink 20mA, and is it sustainable current or short peak value?
I am testing 500 Ohm resistors on my 3.3V system now. 3.3V/500Ohm = 6.6mA. I still get errors and the square is not good enough, I guess. May I go lower, 250 maybe?
Edit: I tried 340 Ohm resistors (around 10mA sink), and it is working for now. Almost no errors (1-2 per minute maybe, under load).
The system has motors, when motor load goes up, errors increase. I am using ferrite rings on the motor lines. Moving motor wires and I2C lines around does not seem to affect anything. I see some noise via oscilloscope. The only thing that affects error count for now is resistors values.
AI: Yes, you could sink up to 20 mA on both I2C ports, but you have to keep the total current in mind.
It is explained in the chapter 6.3.14 I/O port characteristics:
Instead of lowering the pull-up resistors, you could also try if you can somehow lower the bus capacitance.
What do you mean with "the square is not good enough"? I2C still works with non-perfect square wave signals. Are you sure the signal shape is the problem?
Check how non-perfect the squares are in the datasheet:
The only relevant about the signal is the I2C timings specification, given in Table 61 of the datasheet. |
H: Why do these modules not include IPEX and trace/chip antenna connections simultaneously?
I'm looking a bluetooth modules for a project i'm working on. I want to have a small form factor version of the board be usable with a trace or chip antenna, and have the option of connecting a external antenna for better performance if need be.
However, when looking at bluetooth modules, i've noticed that the ones that include both options have a selection via a 0R link rather than simply having both connected (see pictures).
This is at odds with things like Nordic's nRF52 dev kit which has both a trace and IPEX/u.FL connector available at all times (see picture).
What is the reason for this? I can only assume that this is due to performance considerations but i'm not sure. Ideally, like the dev kit, I want both connections to avoid soldering to make my selection.
AI: I took a look around the Nordic documentation.
You don't need a jumper on the Nordic board because the RF connector it uses has a switch.
The connector is of SWF type (Murata part no. MM8130–2600) with an internal switch. By default, when there is no cable attached, the RF signal is routed to the onboard PCB trace antenna. |
H: Bus mastering VS Bus arbitration
If there are multiple bus masters possible in a bus architecture then is it certain that 'Bus arbitration' will take place before a master gets hold of the bus control or is it possible that bus control is handed over to another master without bus arbitration taking place? Theoretically it may be possible but I want to know this with reference to well known practical buses which are in vogue in industry these days, for example, Ethernet, PCI, PCIe, RS422, RS485, SCSI, SPI, I2C, 1553, USB , CAN, Modbus and others.
I am not at all expecting that someone will make a list for these buses. Instead what I expect is that if someone as any knowledge about a specific bus w.r.t its bus-arbitration then it would suffice if he/she can share that here.
AI: Bus arbitration is not part of several of the protocols you mention. RS422, RS485 and SPI can have bus arbitration but it is not part of the protocol, rather must be implemented on a different communications layer. Ethernet and USB do not really have the concept of multiple masters. The others I don't know well, except for I2C which will be the basis of my answer.
Note that there are I2C implementations that do not support bus arbitration or can be configured to disable this feature. Setting those aside and focusing on full and conformant implementations of I2C...
Since I2C uses open-drain signals pulled high by resistors. This means that anyone can at any time pull any signal LOW without an electrical "collision".
The state of signals are monitored by all active masters. If at any time during a transaction the master sees a LOW signal when it is not itself pulling the signal LOW - it backs off (looses arbitration).
This is essentially how arbitration is implemented on I2C. The master that was sending the LOW wins the arbitration and continues with its transaction.
Only masters that loose arbitration will know that there was a collision. For example, if two masters send the exact same transaction, bit for bit, at the same time they will never notice that there was another master on the bus.
My take on this is that bus arbitration will always occur and work, but in the strictest sense is not always detectable and could be considered to have failed depending on your applications requirements.
Example of a failure:
The slave has an event counter, each time a transaction comes in it counts up by one.
Two masters send a transaction with no data (or data is identical between masters).
It is important that every single transaction is counted at the slave.
If the two masters do a transaction at the same time they will both see it as successful, but the slave will only see one transaction and thus, one event is lost.
If you modify this example such that each master instead sends something unique for each master such as an identifier byte, arbitration will work. One master will loose and can subsequently try again, and no events are lost. |
H: Three phase systems - when is potential of a star node equal to zero?
I had to find total impedance of the following three phase circuit with symmetric line voltages:
I've been told that nodes 1 and 2 can be connected because their potentials are equal (zero).After connecting these two nodes, resistor R and inductor L are connected in parallel.Why can we connect these two nodes (/ why are their potentials equal to zero)?I know that in symmetric systems with one generator per phase (three generators in total) and one star receiver, node analysis shows that node potential of the receiving star's node is zero, but what happens in this case?
AI: Assuming that the three feed voltages are balanced and are sine waves i.e. line voltages are identical with exactly 120 degrees between them, any star connected load of equal values will produce 0 volts at the star point. This means that three identical resistors will yield 0 volts AND three identical inductors (or capacitors) will also yield 0 volts.
With zero volts between a star network of resistors and a star network of (say) inductors, connecting those nodes will not cause a current to flow hence, they can be connected. |
H: DC Fault Characteristics of a Voltage Source Converter
According to this paper, the three stages in the DC Fault characteristic of a VSC are
Capacitor-Discharge State (Natural Response)
Diode Freewheeling Stage (When source AC gets disconnected and \$V_C = 0\$; Natural Response)
Grid Side Current Feeding Stage (Forced Response)
The diode freewheeling stage comes into picture when the source of the AC power is disconnected and the capacitor is completely discharged. But then, the grid-side current feeding stage takes the source AC into consideration. How is this possible?
Also, the first and second stage is described as a natural response and the third stage is described as a forced response. What exactly is forced here?
The referenced content is in Section II, Subsection B under the title "VSC DC Fault Characteristics".
AI: Q: the grid-side current feeding stage takes the source AC into consideration. How is this possible?
A: the condition is a grid fault (0V sc.to gnd) with the voltage source now appearing as a current sink to the 400V charged microgrid capacitor.
Q2: Also, the first and second stage is described as a natural response and the third stage is described as a forced response. What exactly is forced here?
A: the Inductor charges up the current which becomes the new forcing Function and must be protected by opening some IGBT (s) to allow the free-wheel diodes to clamp the natural impulse Voltage.
When the diodes conduct, this current absorbed is “forced back onto the grid” for the RC time duration while the grid is in fault to ground with some natural LC damped ringing.
it is the same method used for regenerative braking in e-cars except instead of a motor-generator on DC,you have a storage inductor with flyback current or back EMF voltage clamped thru diode current rectifiers to a shorted grid fault. |
H: Why is this current source with both sides grounded still supplying current
Now if we write a node equation at \$C\$ we get
\$I_C = g_m − sC_μ V_π \$
But my question is, is it correct, how do we define the current through the branch with \$g_mV_π \$ since both of its terminals are connected to ground now, which means that there is no potential difference between both terminals ?
My initial thought was that since there is a constant current source then the current would be held constant by it. But then that would mean there is a potential difference between those ends. Now that means potential difference across \$C_μ\$ is not \$V_π \$ since one end is connected to the current source which if working would create potential difference (since current is held constant).
But here the equation suggests that the current source is working and as well as the capacitor \$C_μ\$ is grounded too.
Where are my wrong ? Please point it out. Thank you.
AI: What happens INSIDE a current sink is what allows the zero Ohm link to simply carry the current generated with the internal potential.
In any circuit that you deal with you would have no problem with the concept of current flowing in an ideal zero Ohm wire - having the current provided by a current source should not make any difference.
Imagine a high voltage source and a high value resistance in series in a "black box.
Bring out one high voltage source terminal directly to a contact and the other terminal via the resistor to another terminal.
Connect the two terminals together with a 0.00000000... Ohm link.
Current in the link will be I = V/T = Vhigh/Rhigh.
Potential drop across the link = 0.0000 ... V.
No "laws" have been violated.
For example, here is a hypothetical 1 amp near ideal current source. I chose an internal voltage of 100 million volts and an internal resistance of 100 million ohms. In practice somewhat smaller values are used [ :-) ! ].
Short circuit this CC source with a zero ohm resistor and 1 amp flows in the resistor. This is the equivalent of you example situation.
Use a 1 ohm resistor for R2 and current in R2 will be I = V/R
= 100,000,000 / 100,000,001 = 0.99999999 A.
Use a 1000 Ohm resistor for R2 and I will be 0.99999 A
ie the difference between bridging the output with 1000 or 1 or zero Ohms is minimal.
For an ideal current source the difference is zero.
simulate this circuit – Schematic created using CircuitLab
Because, what happens INSIDE the 'black box' is what allows the zero Ohm link to simply carry the current generated by the internal potential.
Note also the difference between a current source and a voltage source.
We are much more familiar with the latter.
A V Volt voltage source
Develops voltage V across its terminals as Voc when it is open circuited.
No power is dissipated in this state.
Shorting the output of an ideal voltage source produces infinite current.
An I ampere current source
Develops current I at its output as Isc when its output terminals are short circuited.
No power is dissipated in this state.
Open circuiting the output of an ideal current source produces infinite voltage at the output.
Our AC mains supply approximates an ideal voltage source.
We open circuit it when it is not in use.
If our AC mains was configured as an ~= ideal current source
we would need to short circuit it when not in use. |
H: Why won't "wait until a'active" return when the signal a is assigned the same value as before?
For a signal a, the attribute a'active is true whenever a is assigned to - even if its value does not change (i. e. the same value as before is assigned).
In the following example, the signal a is assigned its previous value, '0', at 100 ns. a'active should therefore be true, but the wait until a'active statement in process p1 does not return.
The wait statement in process p2 waits for a'transaction'event in addition to a'active (to my understanding, the conditions should be equivalent). This wait statement does return, confirming that a'active is, in fact, true.
So why doesn't the wait statement in p1 return, even though its condition is clearly fulfilled?
MWE:
library ieee;
use ieee.std_logic_1164.all;
library std;
entity vhdl_active_minimal_testbench is
end vhdl_active_minimal_testbench;
architecture rtl of vhdl_active_minimal_testbench is
signal a : std_logic := '0';
begin
p1: process
begin
wait until a'active;
report "p1: a'active";
end process;
p2: process
begin
wait until a'active and a'transaction'event;
report "p2: a'active AND a'transaction'event";
end process;
stimulus: process
begin
wait for 100 ns;
a <= '0';
wait for 100 ns;
std.env.stop;
end process;
end architecture;
ModelSim 10.5c output:
# Loading generic.vhdl_active_minimal_testbench(rtl)
# ** Note: p2: a'active AND a'transaction'event
# Time: 100 ns Iteration: 1 Instance: /vhdl_active_minimal_testbench
# Break in Process stimulus at [...]/test_vhdl_active_minimal.vhd line 29
AI: In summary, a'transaction is a signal (and is therefore added to the implicit sensitivity list of the process), whereas a'active is not a signal.
Your code is equivalent to
p1: process() is
begin
wait until a'active;
report "p1: a'active";
end process;
p2: process(a'transaction) is
begin
wait until a'active and a'transaction'event;
report "p2: a'active AND a'transaction'event";
end process;
p1 never fires after starting to wait: only signals can be used for a process to be sensitive to. Blank sensitivity lists will expand to all independent signals that are read in the process: these don't exist for p1.
p2 has a signal in a'transaction, which is a signal of type 'bit', which toggles each time there is a transaction, firing p2.
From the Doulos VHDL Golden Reference Guide (version 4.0):
S'TRANSACTION A signal of type BIT which toggles whenever there is a
transaction on S (A signal assignment creates a transaction. A
transaction that causes a change in value is an event).
S'ACTIVE TRUE if and only if there is a transaction (signal
assignment) on S in the current delta.
Gotchas!
The attribute S'EVENT is not a signal, so should not be used in a
context where a signal is needed to trigger a process. [..]
Same gotcha applies for 'active'. |
H: Baxandall tone circuit passes signal through but does not alter its tone
I added an Baxandall active tone circuit to an existing overdrive circuit and I'm having an issue. The signal passes through the circuit/opamp and out to my volume control but the bass and treble controls don't affect the signal at all, it seems as if the signal is completely bypassing the pots. What do I have wrong that would be causing this? Thanks for any insight!
AI: Normally a single supply Op Amp is biased on both input pins at Vcc/2 and not Gnd as you have done to Vin+.
This may pass residual signals but not function as a linear Op Amp. |
H: What type of printer port is this?
I just got a currency discriminator (Carnation CR1500) that can be connected to a receipt printer. There is a modular jack on the back of the machine, but I don't know what kind of cable it needs. It won't accept RJ45 or RJ11 connectors. It's taller and thinner than any RJ port I've seen and there's nothing in the manual about it.
Can anyone identify this?
AI: It's most likely an RJ10 (earphone cord) connector with ±5V RS232 on it. That's what common receipt printers accept.
You have to find out yourself which pin is TxD, RxD and GND. In idle state, TxD has -5V against GND. |
H: What is the difference between a multiplexed bus and a multi-master bus
The jargon of terms in bus architecture literature is half the difficulty in understanding it. At some places the term 'multiplexed' bus is used while at some other places 'multi-master' bus is used. They both look same to me but maybe they are different in some sense also. How to know what exactly is the meaning of these two terms?
AI: Muli-master is mainly for long serial communications. A bunch of masters on the same bus can simultaneously attempt to initate a transmission. Like a bunch of people trying to yell over each other in a room until everyone settles down to listen to just one person.
Multi-plexed is only (I think) for parallel processor to memory communications. It is definitely only for parallel since it has no meaning in serial. It is where not every line is dedicated to only a single address or data bit. Some lines might be used/shared for a low and high bit of the same type, or a data and address bit. This lets you reduce the number of lines between processor and memory at expense of speed.
These two things appear in different places. I don't know why they might ever overlap in application. |
H: Why is my seconds counter in verilog jumping values behaviour?
I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz clock signal (referred to as the 'pulse'), which will then be used to drive the normal counter. The down clocker module is as follows:
module downClockerTest(pulse, clk, reset);
output reg pulse;
reg [25:0] count;
input clk, reset;
always @(posedge clk or negedge reset) begin
if(~reset) begin
count <= 26'h0;
pulse <= 1'd0;
end
else if(count == 26'd49999999)
count <= 26'd0;
else begin
count <= count + 26'h1;
pulse <= (count > 26'd24999999);
end
end
endmodule
With the following RTL:
Notice that the output 'pulse' is registered. This design works fine; the counter counts as it should. However, if I try and remove the register at end by attempting to drive the 'pulse' output by a single assign statement, the seconds-counter seems to begin jumping by 1 and then 4 in 1 second, indicating 5 pos-edges from the down-clocker, where there should only be one.
The slightly modded down-clocker is as follows:
module downClockerTest(pulse, clk, reset);
output pulse;
reg [25:0] count;
input clk, reset;
assign pulse = (count > 26'd24999999); // The counter seems to increment by 1 and then 4 in quick succession (1 second).
always @(posedge clk or negedge reset) begin
if(~reset) begin
count <= 26'h0;
end
else if(count == 26'd49999999)
count <= 26'd0;
else begin
count <= count + 26'h1;
end
end
endmodule
The changed RTL without the register is:
Why is it that the down-clocker only works right when there is a register at the end? Is the register performing some king of 'debouncing'? Does 'bouncing' occur in non-mechanical switching circuits as well? What could be the possible reason from an electronics point of view?
It might be prudent to add that the TimeQuest Timing analysis fails in both cases with critical warning: 'Timing Requirements are not met'. But still, one works where other does not.
I am guessing this bizarre behavior has to do with a race condition caused when a sequence of bits drastically changes its 1's and 0's after an increment. For instance, 110111 becoming 111000 after increment-by-1. Since there is no telling which of the flip-flops - storing the individual bit positions in the sequence - will update their values first, the number (read: bit sequence) might fluctuate for an instant before attaining a stable value. There might exist numbers (bit-sequences) that, while tending towards their stable values, fluctuate through the value being compared (24999999, in our case) and cause the comparator to output Logic-HI.
A register at the end would certainly solve this issue. However, all this is guess work, with bases in little experimentation. Any learned opinion would be welcome.
AI: When you use the async assign for the pulse, you will see the influence of unequal delays in the comparator as glitches in the output. Registering the compare signal hides this, allowing everything to settle down before the next clock edge. (This is guaranteed by the place-route tool if it says the path meets timing.)
If, down the road, you have some reason you need to asynchronous-decode a set of counter outputs, and you want it to be glitch-free, there is an answer: use Gray-code counting. Gray codes guarantee that only one signal at a time changes state, so it avoids the multiple-path race condition that leads to the glitching. |
H: FPGA CPUs, how to find the max speed?
I'm just getting into FPGAs, and if I understand correctly, you are connecting logic gates together using code. So if I design a CPU in Verilog, it should connect some logic gates together and work, but how do I know how fast my DIY CPU can run? What does it depend on?
AI: The speed of a design is limited by several things. The biggest will most likely be the propagation delay through the combinatorial logic in your design, called the critical path. If you use a fast FPGA and write your HDL very carefully, you could probably hit 700 MHz on something like a Virtex UltraScale+. On a lower end FPGA, for example a Spartan 6, a reasonable figure is probably more like 250 MHz. This requires pipelining everywhere so you have the absolute minimum amount of combinatorial logic between stateful components (minimize levels of logic), low fan-outs (minimize loading on logic elements), and no congested rats-nests (efficient routing paths).
The fabric logic of different FPGAs will have different timing parameters. Faster, more expensive FPGAs will have smaller delays and as a result can achieve higher clock frequencies with the same design, or run a more complex design or design with less pipelining at the same frequency. Performance within a particular process can be similar - for example, Kintex UltraScale and Virtex UltraScale are made on the same process and have similar cell and routing delays. It is impossible to say how fast a given design will be without running it through the tool chain and looking at the timing reports from the static timing analysis.
When doing toolchain runs to determine maximum clock speed, bear in mind that the tools are timing-driven: they will try to meet the specified timing constraints. If no timing constraints are specified, the result can be very poor as the tools will not try to optimize the design for speed. Generally, the tools will have to be run several times with different clock period constraints to find the max achievable clock frequency.
If you can optimize your design so that the critical path is not the limit, then you'll run in to limitations in the clock generation and distribution (PLLs, DCMs, clock buffers, and global clock nets). These limits can be found in part datasheets, but getting near them with a non-trivial design is difficult. I have run stuff on a Virtex UltraScale at 500 MHz, but this was only a handful of counters to provide triggering signals to other components. |
H: Physical implementation of a band pass filter does not match simulations
I am building a pasive bandpass filter with the band pass between 134MHz and 139MHz. It is a third order eliptic filter, with theoretical attenuation of around 50 dB for the stop band and less than 1dB ripple in the pass band. This is the schematic:
And here is the response of the filter in a LTSpice simulation, from 50MHz to 500MHz:
Focusing on the pass band:
Everything seems to work fine enought for my requirements (I plan to use it to receive signals of small bandwidth from 137,1MHz to 137,9MHz, and S11 < -10dB there, so I should not have any problem. Besides, I thought about using a 20dB LNA to overcome the insertion loss of the filter).
After the simulations, I created the PCB in KiCAD. This is the final result:
It is just a microstrip (calculated with relative permitivity of 4,5 for FR4, with a thickness of the PCB of 1,6mm and 1oz of copper to have 50Ohm impedance) with the components attached to it. The board is 30mm x 21mm (I tried to keep it the shortest possible to avoid losses and parasitic effects). The PCB has only two layers and the bottom one is just a ground plane, connected both to the SMA connectora and to the upper groumd plane by the bias.
This is the filter bluid, where ±5% 0805 components are used:
I know that soldering can be improved, I am planning to buy better tools in the near future. However, all the connections are well soldered and the filter should work properly.
I then tested it with my homemade spectrum analyzer: a SDR with a BG7TBL noise source. The software used is callecalled Spektrum. It features a relative mode, where it records and averages the response of the noise source itself and then you can connect the filter to see its real response. This is the result, again, ploted from 50MHz to 500MHz:
Here, I see some serious problems:
The losses in the pass band are 28dB and not the simulated 5dB
The attenuation is of only 8dB, and not the simulated 50dB
As we increase in frequency, the effect of the filter dissappears
I have no clue about why this is happening. I have revised the schematics, simulated everything again, revised the PCB design, and even built 4 of these filter to ensure that it was not a soldering problem, but all of them have similar frequency responses. I have also tried different SDR software with no luck neither.
What am I doing wrong? How can I solve this problem? Any advice or improvement to the design will be appreciated.
Thank you very much in advantage.
Edit: In case the LTSpice/KiCAD files were needed, here is the github of the project:
Github
AI: If you built the above board with superconductors and used ideal components then the PCB would match up with the simulation nicely.
There is no parasitics being modeled in the simulation. The parasitic capacitance between planes will be approx 2pF between the connectors on the sides and the ground plane (I assumed 20mm by 3mm for the copper). The parasitic inductance of the same --roughly-- 20mm x 3mm conductors will be about 2nH.
The capacitors will have ESR and ESL that limit there effectiveness at high frequencies. Make sure you at minimum use low ESL capacitors. The ESR and ESL need to be modeled in spice, or use s-parameter models. Looking at the simulation the parasitics on the 620pF cap made the most difference. It may be better to select different component values with better parasitics. Either way, you need to start looking at frequency graphs of the components themselves.
Source: https://ds.murata.co.jp/simsurfing/mlcc.html?lcid=en-us#
Another problem that may arise is some SMT inductors lose their effectiveness at high frequencies, I don't know if this is the case for the design above, but if so then the inductors would be non-existent after a given frequency and could be considered open circuits.
Source: https://ds.yuden.co.jp/TYCOMPAS/ut/detail?pn=LBM2016T2R2J%20%20&u=M
Component tolerances also need to be accounted for.
http://blog.optimumdesign.com/clearance-and-creepage-rules-for-pcb-assembly |
H: Removing optimization changes I2C timing
I'm at using SAM E54 Xplained Pro to get temperature readings from a MCP9600 hooked up to a thermocouple over an I2C bus. I'm using Atmel Studio 7 with I2C drivers generated with Atmel Start. I'm using a Saleae logic analyzer to help debug.
The temperature read works fine using an optimization level of -O1, but when optimization is changed to -O0, the I2C timing is changed, resulting in faulty temperature reads.
Here is a temperature read with -O1 optimization level:
As you can see the temperature is read as 0x016B which corresponds to about 73 degrees F.
Here is a temperature read with -O0 optimization level:
The temperature is read as 0x0101, which is incorrect.
Can anyone offer insight into why removing optimization changes things, and how I can make the code work with optimization level -O0? Any help is greatly appreciated.
Here is the code:
#include "driver_init.h"
#define MCP9600_I2C_ADDR 0x60
int main(void)
{
struct io_descriptor *I2C_0_io;
uint8_t th_register = 0x00; //register that holds temperature measurement
uint8_t temp[2];
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, MCP9600_I2C_ADDR, I2C_M_SEVEN);
io_write(I2C_0_io, &th_register, 1);
io_read(I2C_0_io, &temp[0], 2);
while (1) {
}
}
AI: Finally figured it out. Just had to reduce SCL frequency. I noticed that the clock line was a low for a lot longer between bytes for the -O0 optimization waveforms, so I figured it had something to do with the slave clock stretching. I found a note in the MCP9600 datasheet that mentioned if the master doesn't have features to detect slave clock stretching you should reduce SCL frequency, and that worked out. |
H: Is this thyristor model or circuit wrong?
As far as I understand when the thyristor is triggered it should turn on and remain on unless negative voltage applied to its gate. I found the model from littelfuse website.
But I tried the following circuit with the model where I plot gate trigger voltage supply voltage and load current as follows:
And when the gate voltage is off the load current also goes off instead of remaining on, aka latching.
What could be the reason the thyristor is not latching as expected here?
AI: As far as I understand when the thyristor is triggered it should turn on and remain on unless negative voltage applied to its gate.
No, it remains on after the trigger has been removed until the anode current falls below the hold-on current which should be listed in the datasheet. Note that this value will depend on the temperature of the device.
From the datasheet.
Links
Phase Control Using Thyristors by Littlefuse.
Thyristor Theory and Design Considerations Handbook
by ON Semiconductor. |
H: Identification of an AC transformer
I have a broken Philips alarm clock FM/AM radio broken, so I stripped some parts out of it.
One of it seems like an AC converter, but I cannot find any reference/datasheet about it. Do you have any information about this? (or what the meaning of the yellow/green wires are, I assume the black is GND and Red is VCC).
The dimensions of the yellow 'block' are 35.3mm x 29.7mm x 11.6mm.
The text is:
SIL35T0000095
3004
So all wires going out of this transformer and I would like to know the meaning of the yellow and green wires:
Blue wire (on the top back), going into the black cable you can see on the right page, it's going to the AC mains power plug (220V).
Brown wire (on the top back), going into the black cable you can see on the right page, it's going to the AC mains power plug (220V).
Green wire: What is the meaning of this wire?
Yellow wire: What is the meaning of this wire?
Red wire: I assume this is output? (AC/DC?)
Black wire: I assume this is ground
AI: It's an AC/AC transformer, the rectifier was probably on the red/black lines. Usually Yellow\Green lines are for AC mains (according to international standards, but it also depends on the age of the device).
Your best bet is to hook up a signal generator, and see what the step down ratio is if you want to use it.
The other thing that will be of use is any markings on the outside of the clock that specify the current and voltage (you need the current) because that will give you a good idea of the saturation point of the transformer and how much power can be run through it.
EDIT:
I didn't see the blue black line in the picture which is not clearly indicated:
The primary is most likely blue brown and there are two secondaries, in this case red/black are one secondary and the other secondary is yellow/green
Source: https://airlinktransformers.com/post/chassis-mounting-toroidal-transformers-technical-notes |
H: Do I need a 50/60Hz notch filter for battery powered devices?
Given that battery powered devices are not plugged in the mains power, can I assume that there will be no 50/60 Hz frequency noise?
This question came up while thinking about what the circuit for a portable ECG monitor would look like and it seemed obvious that the 50 Hz notch filter could be eliminated. But is it so?
Thank you
AI: Assuming you're talking about the input signal, you may still want the filter because the long leads running to the chest pads (or wherever your detection location is) could pick up a 50/60Hz signal like a transformer's secondary from a nearby loaded mains cable.
If you're only referring to the power supply, you're correct, a battery produces very stable DC voltage, any instantaneous fluctuation in battery voltage would predominantly come from sudden loading/unloading of the battery. Therefore no filter would be needed. |
H: Common-emitter amplifier up to 10 MHz
For sure not the first time for me visiting this awesome site, it saved me quite a few times - this time, however, I have a specific question ... would be great if someone could help me with this!
I need a software-tunable oscillator with frequencies from 100 kHz to 2 MHz and an amplitude of at least 10 V(pp). So the -3dB bandwidth should be high enough to have a stable gain between 100k-2MHz. I realized that this is already quite a challenge. Well, I decided to go for the famous AD9850 which I successfully hooked up on an Arduino and it runs like a charm! However, the amplitude of the signal is only 1 Vpp, so I do need an amplifier. This is where it's hard for me to wrap my head around.
So far, I used OpAmps a lot. Here, this doesn't appear to be the best approach since a gain of at least 10 with 2 MHz bandwidth and 10 V(pp) sounds like I need an expensive OpAmp with both high GBP and insane slew rate ... So I decided to go for an common emitter amplifier! I read quite a few articles, but as a hobbyist - hell that's confusing stuff! However, I got a circuit running and the simulation looked quite promising as you can see below - and I am sure, those are not necessarily the best values to choose. I used a BC547C I found around and built the circuit ... and was quite disappointed when I hooked up the AnalogDiscovery2's network-analyser.
Unfortunately, I don't have an image of the Bode-plot anymore. Aafter digging deeper in the internet I figured that the collector-base parasitic capacitance, about 9 pF for the BC547C, is killing me - when inserting this capacitance (C3 in the image below) I get the EXACT same curve as measured with the AnalogDiscovery2 in the real circuit.
Well, crap! There is no way to get around this capacitance here ... again I went for a search on the internet and found some "HF"-labelled transistors with high GBP and (promised) low capacitance-values for C(cb). Now, here are some more details about the circuit's intended use:
Impedance of the (filtered) AD9850's output is 200 Ohms (at least that's what I designed the filter for and that works quite well...)
Output is going to be hooked to an high impedance conductivity sensing circuit with at least 200 kOhm input impedance (which is R6 here, 1 MOhm is just an educated guess, could even be more...)
... so effectively I need an VOLTAGE amplifier, not so much of an power amplifier.
I have a voltage source for up to 35 V as supply - this should not be a problem (above this is V2 with 20V here)
I do have some "HF" transistors/JFETs here, including the SC1730, BF545A, BF959, BFS17 an NTE312 and a BFW92 that do all have significantly lower C(cb) values
I would really appreciate some advice on:
if the use of one of these transistors/JFETs or - more generally - any transistor/JFET with lower C(cb) and GBP can fix my problem, or if I am running in a totally wrong direction here
Would you recommend more than one gain stage for a stable 20dB gain between 100 kHz and 2 MHz?
and would it even be possible to go beyond +20dB?
Just one last thing: I would like to keep the cost of the circuit as low as possible, which is why I reckon a CE-amplifier (or something like this) would be a good solution since transistors/JFETs are cheap.
EDIT:
Thanks for all your answers, great to get such nice help! Here a few things I'd like to share:
I looked it up, for sure C(cb) was included in the BC547's LTspice model - stupid me. Although I did made some substantial progress in understanding impedance, clearly I am bad in spotting it in action. The AD2's input impedance with its 25 pF as pointed out by some of you seems to be a major problem.
I rebuild the model posted by Bruce below with parts I had laying around, I've got a picture of the LTspice circuit:
And the actual thing:
I follwed the general advice and soldered it to a perfboard to minimise parasitic capacitance - and well, it works great! (although looking a bit like a bungling...). Below I got the actual Bode plot from the simulation and of the measurement with my AD2:
Since it's hard to see: I've got 25.3 dB @ 100 kHz, 25.7 dB @ 1 MHz and 25.3 dB @ 2 MHz - awesome!
The only thing that I noticed is a distortion of the wave form when using 20 V as supply voltage, that also occurs in the LTspice simulation, even worse there.
Now that seems to come from the high gain trying to amplify the signal beyond the actual supply-voltage. I turned up the voltage to 25 V which almost eliminated the distortion - 30 V were even better! However, that's where R2 whith it's 1/4 W power rating seems to say good by since it heats up quite quickly. I calculated the mean power dissipation with spice and yupp, 350 mW it is. So I guess I will switch to a 1 W resistor on my final amplifier pcb to be on the save side.
AI: after digging deeper in the internet I figured that the collector-base
parasitic capacitance, which is about 9 pF for the BC547C, is what
kills me - when inserting this capacitance (C3 in the image below) I
get the EXACT same curve as measured with the AnalogDiscovery2 in the
real circuit.
Collector-Base capacitance should be included in the transistor model, so you don't need to add it. However you do need to add any significant external parasitic capacitances. A solderless breadboard typically has 2~3pF between adjacent tracks. Input capacitance of the AnalogDiscovery2 is 24pF. The -3dB cutoff frequency for 4.7kΩ and 24pF is 1.4MHz.
To reduce the effect of parasitic capacitances you can increase the transistor's Collector current and reduce the load resistance. You can also reduce DC gain to improve bias stability, and bypass the emitter resistor with a lower value to get the required AC gain and amplitude.
I took your circuit and reduced R2 from 4.7kΩ to 1kΩ, adjusted the Emitter and Base bias resistors to get about 12V at the Collector and 2V at the Emitter, and bypassed the Emitter resistor with 68Ω to get the required AC gain. I added 2pF between the Collector and Base to simulate external wiring capacitance, and another 30pF at the output to simulate the measuring instrument or load and wiring to it.
With this configuration the -3dB bandwidth was 23kHz to 3.5MHz, and the output amplitude at 2MHz was 13.7Vpp.
If you need even less amplitude variation over the pass band you can put a 'peaking' coil in series with the Collector resistor. I tried 20uH, which raised the 2MHz point to 0dB and extended the -3dB point to 6MHz.
Note that using a peaking coil may make the response more sensitive to load capacitance, as the coil and capacitor form a tuned circuit. With no load capacitance the simulated circuit exhibited a +3.5dB peak at 8MHz. |
H: What's the difference between 74LS00 "gates" and 74LS37 "buffers"?
The TI 74LS00 is "quadruple 2-input positive-NAND gates" and the 74LS37 is "quadruple 2-input positive-NAND buffers."
The pinouts are identical. The LCCC package is documented exactly the same for both and, though the DIP package pinouts are labeled slightly differently (pins 9/10 are labeled "3B/3A" on the 74LS00 and "3A/3B" on the 74LS37), this this should make no difference in actual operation since there's no difference between the two inputs of a NAND gate.
The switching speeds may be slightly slower for the 74LS37; 12/24 ns typ/max versus 9 or 10/15 ns typ/max for the 74LS00, but I don't know if this might be simply because I'm looking at (the data sheet for) an older part for the 74LS37.
The input current draw seems the same for both.
The major difference appears to be the current capacity of the outputs; the 74LS00 sources up to 0.4 mA when high and sinks up to 8 mA when low; the 74LS37 sources up to 1.2 mA when high (3x) and sinks up to 48 mA (6x) when low.
Is this output current capacity the difference between this 74LS00 "gate" and 74LS37 "buffer"? According to the Wikipedia description of a "digital buffer" a buffer would offer better input characteristics, which don't seem to be different here. (Almost all of the other parts labeled "buffer" have open-collector or tri-state inputs.)
AI: Yes, the ‘LS37 is a buffer. The high drive figure is used for driving higher fan-out loads. Some other logic gates have equivalent high-drive ‘buffer’ versions. There are also some that are open-collector so that they can be used for wired-or buses and logic. There are still others designed to drive transmission lines.
At any rate, higher current is sometimes needed for large TTL fanout because each driven input presents a DC load that sources some current when the driven signal is low. High drive buffers increase the number of loads that can be reliably driven low.
Buffered outputs are also needed when termination is used to improve signal integrity - especially sensitive signals like clocks.
CMOS and LVCMOS gates also come in ‘buffer’ versions. The game is a bit different. Although CMOS inputs present no DC load, high drive helps CMOS overcome delay due to capacitive loading: it improves switching time. However, like TTL, the high-drive CMOS types help when termination is used. |
H: On off button for my microcontroller board
Here is my charger unit and voltage regulator for powering a MCU board that I designed. I'd like to ask, how can I add an on/off button which allow charging the batteries even we turn off the system but close the power for the other modules?
My idea was adding a button right after battery charger unit (Beginning of voltage regulator TPS7353). If my idea is true, should I directly connect the button or does it need a resistor?
I'd be so happy if you answer :)
AI: You can just use enable pin of IC3 to turn off the power to the MCU.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode.
The TPS735 only draws a quiescent current of 45 μA when it is not enabled.
So, add a switch between pins 4 and 6 of the TPS735 and add a 10k resistor and a 10nF or 100nF capacitor between pin 4 and ground.
The resistor will prevent pin 4 to float when the switch is open, the capacitor will prevent bouncing of the enable signal. |
H: What is this small circuit board used for in a 12v light?
Repairing a home-made disco light that was used in a nightclub during the 80's/90's and it consisted of 16 12v 50w lamps arranged on 8 legs.
I have discovered a small circuit board within each lamp which has an LED on the back. What was this small board used for and can it be removed?
The lights were powered in serial, so would this board of allowed for the rest of the lights to be powered if one light blew?
AI: It looks like the LED will light up if the 12V lamp blows, so as all are in series and all lamps turn off if one blows, it is easier to locate the broken lamp by just looking at the LED. As it is in parallel with the lamp, it can be removed. |
H: What are the additional transistors used for in this hex inverter?
I'm learning about electronics and was studying the SN7404 hex inverter schematic when I saw this:
I naively expected just a single transistor (the one in the bottom right) and the input at the base of that transistor to give the inverted input at Output Y.
Yet there are 3 other transistors, a bunch of resistors and a couple of diodes in addition.
Can someone here help to explain what the purposes of these are and the reason for the resistor values?
Source datasheet here: http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf
AI: This is a classic TTL gate.
To ensure that all TTL devices present the same load, the input is always a transistor with the emitter at the actual input (multi-input devices have multiple input emitters).
The next transistor is a drive stage and the output is a totem-pole stage which can both source (output high) and sink (output low) current.
The output current in the high and low states are different (and for a single fan out match the input current for TTL devices). |
H: Find ROM and RAM in .bin file for micro controller
I use the Arduino IDE to compile some code to a 32-bit ARM Cortex-M3 based microcontroller.
The result of the compilation is .bin file. The file is a stripped binary file, containing the RAM and ROM images to be programmed on the microcontroller.
Another possible result of the compilation is .elf file for the same code and the same microcontroller. In the elf file, I can easily find the RAM sections - .text, and the ROM sections - .bss, LOAD (ro-data) and so on.
What I can't understand, is how the bootloader of the microcontroller knows to distinguish between the RAM and the ROM while programming the board and loading the image? I can't see in the .bin file any reference to the sections, or anything that could hint it, and the RAM code comes just after the ROM in the .bin.
Any ideas how is it possible?
AI: The binary image only provides the contents of the Flash ROM memory; it does not provide an "image" of the RAM. Once programmed, the microcontroller does the same thing every time you turn it on...that wouldn't be possible if we tried to download data to the RAM as part of the programming process, because the RAM data is not saved when we cycle power.
Now, when programming in C we know that we can give an initial value to our variables. In reality, that initial value will be part of the ROM binary image and a small bit of C code will copy those values out to RAM when the processor is reset. Likewise, simple variables that are defined without an initial value will be set to zero. The RAM is initialized as part of the system initialization in C. In the Arduino environment, the initialization of RAM is performed before your setup() function is invoked.
Of course, the ROM must therefore contain the addresses of the RAM regions to be initialized, as well as the address range in the ROM that holds the initial values. Setting all of this up is part of the function of the linker/loader, which the Arduino IDE runs for you. |
H: What data is typically stored on RFID cards and why?
I understand that all RFID cards contain a UID in their memory from manufacture, normally in sector 0. But they also have additional sectors for data storage, my question is what is some example data that would be stored on these cards?
Saying for example that the example data could be user access rights, I can't seem to understand why this data would be stored directly onto the card itself and not on the backend where the readers do a UID check, is it to prevent easy cloning?
In my experience from some extremely limited RFID security research is that most organisations implementing RFID cards are simply utilising the cards UID and the rest of the storage is blank.
AI: in my experience from some extremely limited RFID security research is that most organisations implementing RFID cards are simply utilising the cards UID and the rest of the storage is blank.
You are right, this is typically how RFID cards like Mifare are used in simple access control schemes.
However, there are more complex schemes where being able to store data on the card can be beneficial. It is especially important in applications where:
The number of users is huge
The access rights are a bit more complex than just "allowed everywhere" / "disallowed"
You don't need to record each access in a central database (you just need to check the rights)
In this case, contacting a central backend for each access is not required, and would actually become a bottleneck. The data storage ability of the cards can be used to solve the problem much more efficiently, and you don't even need the access doors to be connected to a network anymore (which can also be beneficial in applications where network connection is not reliable enough, or not available at all).
There is one typical application where all these requirements are very important: public transport.
Checking rights against a central database for each traveller would be a huge problem. If you still want to track and record accesses, you can do it on a local database which make things much simpler. You can even simply record it on the card itself (another use of the card data storage ability): this way, you can easily tell your customers you're not spying on them (makes things much easier legally), but still have access to the history data if the customer is willing to provide his card.
As a practical example, here is the kind of information that are stored in Oyster cards (London public transport):
Generic Card Data: Identification number of the card, Pay As You Go
(PAYG) Balance, Passenger type, type of discount, Photocard
identification number if applicable, Staff identification number if
applicable, the deposit value, and Registration flag.
PAYG top up Data: Date, Time, Location, and value added.
Ticket Data: Type of ticket, start and expiry date, and time
restriction if applicable.
Transaction Data: Date, Time, Station number or bus route, and fare
charged.
(Source: https://www.whatdotheyknow.com/request/data_stored_on_oyster_cards)
Outside of public transport, you could imagine applications where some very personal data needs to be used to grant access, and you don't want this data to be stored in a database. Typical example is biometric data (e.g. fingerprint), for which there are specific legal considerations (you can't just store this anywhere you want, depending on the country). |
H: How to infer the max current output of this function generator from its datasheet/specs?
I need to figure out the max current a function generator can output from its signal waveform output. Here is its datasheet. But there is no such parameter here.
The output voltage can swing from -10V to +10V.
But I cannot find any detail about the maximum load or current. Can we say it can source current for a load down to 50 Ohm? Does that mean it can source max 10V/50Ohm = 200mA?
AI: This function generator has a 50\$\Omega\$ output impedance and is protected from short circuits. To me, this implies that the maximum current is limited by the open circuit voltage (up to 20V) and the output impedance. Ohm's Law says the maximum output current should be 400mA when the output is shorted or 200mA into an external 50\$\Omega\$ load.
Having said that, it makes me uncomfortable that there is no specification for the output voltage range with a 50\$\Omega\$ load. It may be that the sheet you linked is an abbreviated version of the full specifications. |
H: Correct wiring of Cortex-M 10-pin Debug Connector
The ARM Cortex-M 10-pin debug connector has five interesting signals, in the original PDF they're named:
SWDIO / TMS
SWDCLK / TCK
SWO / TDO
NC / TDI
nRESET
For MCUs which only support SWD and which might even not have SWO (such as the STM32F030), I'm assuming the wiring is as follows:
SWDIO / TMS: PA13 ("SWDIO")
SWDCLK / TCK: PA14 ("SWCLK")
SWO / TDO: Open
NC / TDI: Open
nRESET: NRST (Chip reset)
Is the assumption that nRESET means chip reset correct?
Because if it is, how about a larger device like an STM32F103:
SWDIO / TMS: PA13 ("JTMS/SWDIO")
SWDCLK / TCK: PA14 ("JTCK/SWCLK")
SWO / TDO: PB3 ("JTDO/TRACESWO")
NC / TDI: PA15 ("JTDI")
nRESET: NRST (Chip reset) or PB4 (JNTRST)
Here, it's not clear where to connect nRESET anymore: To the chip reset signal (NRST) or the JTAG reset signal (JNTRST)?
Additionally, is it good practice to hook up both SWD and JTAG connection to a device that supports both (like the STM32F103)? If such a device should be only connected to SWD, does the meaning of nRESET change (i.e., when using JTAG maybe it's connected to JNTRST, but when only using SWD it's connected to NRST)?
AI: nRESET and JNTRST do not fulfill the same purpose.
nRESET is full chip reset.
JNTRST is jtag reset, which is used for boundary scan.
The small 10 pin ARM SWD connector does not connect to JNTRST, that's a JTAG feature. You need the 20 pin version for that.
As also described in the manual of the ST Link V2, which has the 20 pin connector.
Note that NRST is always NRST.
nRESET is also optional. Only if you intend to disable access to SWDIO and SWCLK a full chip reset by the programmer is required.
I often add a non-populated resistor in series with NRST to the programming connector to reduce risk of problems in the field. I can add this for prototypes, where it might be required. Production programming is not impeded by this. |
H: Presence of Crossover Distortion in Class A Amplifier
This question is about theory facts of class A audio amplifier.
It is known that class A amplifier is usually biased so that an amplifier's quiescent point is in the middle of the amplifying device's load line. For class B amplifier is known that it is biased in such manner that quiescent point is sitting at the lowest point of load line (in cut-off region). In terms of practical terms, class A will be crossover distortion free, while there will be at least some crossover distortion seen in output signal of class B amplifier.
However, author G. Randy Slone had mentioned in a book named "High power audio amplifier construction manual" under section of distortion mechanisms that crossover distortion cannot be completely eliminated from class A amplifier.
I wonder, whether his statement is really true, since it doesn't seems logical that crossover distortion could be recognized or measured in any way in class A amplifier. It seems reasonable for class A amplifier to completely eliminate crossover distortion since amplifying devices are fully biased and are conduction 360° of overall input signal. Does his statement holds true from any point of view? Because to me it seems pretty unrealistic for class A to generate even negligible amount of crossover distortion.
AI: In the complementary pair you've drawn, altering the bias point alters the amount of gain variation you get in the open loop amplifier.
In 'class A' operation, the bias current is large, both devices stay conducting, so the open loop gain variation is very small, but not zero. The VBE has to vary to vary the emitter current, and this is non-linear.
In 'class B' operation, the bias current is small, so the open loop gain variation is large. The output devices turn on and off, causing large changes in gain.
In each case, once feedback is closed round the loop, the closed loop gain variation is suppressed by the loop gain.
In each case, the closed loop gain variation, therefore the distortion, is not zero.
In the case of class B amplifiers, it tends to be audible to many people, hence the preference for AB biassing, higher current than a pure class B, but still much lower power than class A.
In the case of class A amplifiers, it's generally inaudible to everybody, even those with golden ears. With enough loop gain, it may even be tough to measure. However, you can see that it will never be zero. |
H: How is Gyro drift error related to error in velocity and position?
While reading about IMU on wikipedia I found this about its disadvantages:
"A constant error in attitude rate (gyro) results in a quadratic error in velocity and a cubic error growth in position."
How is Gyro drift error related to error in velocity and position?
AI: In a typical pure inertial nav solution, you must cancel out the acceleration due to gravity by subtracting it out. If the vehicle's down vector is incorrect, this error appears as a lateral acceleration that is equal to \$\sin \theta_{error}\$ -- and for small angles is close to \$\theta_{error}\$ itself. So if the gyro has an offset, \$\theta_{error}\$ grows linearly and therefore acceleration error grows linearly (at first).
Since velocity is the integral of acceleration, and position is the integral of velocity, a constant, linear acceleration drift (1st order polynomial) will result in a quadratic velocity error (2nd order polynomial) and cubic position error (3rd order polynomial).
If all you have is a 6-DOF IMU and a model of the earth's gravity, then both the IMU and the gravity model have to be perfect. |
H: Intel FPGA: applying timing constraints
I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc.
I have tried to write and SDC file, but looking at the signal on the oscilloscope it doesn't seem to work, both clk and data transition happen at the same time.
Setup is min. 1 ns and hold time is 0.2 ns. I have assumed 0.5 ns clock jitter and 1 ns pcb travel time. The tx_clk is derived from a PLL (2MHz).
My sdc file looks like this:
create_clock -name clk_main -period 25.000 [get_ports {clk_main}]
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
set_output_delay -clock { u_nios_system|altpll_0|sd1|pll7|clk[1] } -max 2.5 [get_ports {tx_data[*] tx_sel}]
set_output_delay -clock { u_nios_system|altpll_0|sd1|pll7|clk[1] } -min -add_delay 0.3 [get_ports {tx_data[*] tx_sel}]
Am I misunderstanding how to calculate the appropriate delays or is there something wrong with the way i am applying the constraints?
Any help would be greatly appreciated.
AI: In your set_output_delay -min statement, just enter the hold time as a negative value, like this:
set_output_delay -clock <clock> -min -<hold time> <port>
Have a look here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/
Here too: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/td-p/549028 |
H: Would this protection and limiting circuitry work with 5.1V zener diode?
I have a small project for part of an experiment where a PWM controlled DC fan speed will be controlled by a -10/+10V function generator's analog DC output. So basically the chain will be:
Analog voltage------>PWM------->Buffer------>PWM TTL input to the FAN
To convert analog input to PWM I use Arduino Nano as a micro-controller board. I map 0-5V analog input voltage at A0 pin to a PWM pin duty cycle where I set the PWM freq. to 25kHz. I might not need the transistor buffer actually but I don't want to risk the uC.
Below schematics diagram shows the plan in my mind:
Left-click to enlarge
I want to power the Nano through its Vin pin by a 12V power supply named as PSU circuit in the diagram above. 5V linear regulator provides power to the buffer.
But since people will use the function generator as input, I need to protect the analog input A0 of the Nano from reverse polarity and maximum limits. For reverse polarity a 1N4148 D2 in the diagram is used. 1Meg R7 resistor is for preventing floating in case there is no input connection. And for limiting the max input voltage I plan to use a 500mW 5.1V zener Z1 in the diagram along with a 220 Ohm series resistor R1.
The Nano uses ATmega328P. I couldn't figure out the maximum analog input the uC can handle. If there is no other fundamental problem, would a 5.1V zener be fine for the analog input pin?
Edit:
I needed to make an edit with a new alternative after Jack Creasey's answer:
Edit2:
Inverted
AI: Would this circuitry work with 5.1V Zener diode to protect a Nano input?
Short answer: NO
A Zener is crude when it comes to use as a clamp, and the voltage variation will impact the A/D conversion on your Arduino Nano.
A typical Zener such as this has a range of voltage from 4.85 - 5.2 V for a nominally 5.1 V Zener. At 5.2 V you will already have significant current into the Nano intrinsic diode on the supply side.
If you want to protect the input then use a device such as the TLV6001 to buffer the input signals.
simulate this circuit – Schematic created using CircuitLab
The TLV6001 is rated for rail-rail operation and so allows the full range of A/D input ...in addition it is rated to carry 10mA in the input protection diodes. This would allow the configuration above to withstand voltages of +/-200 V on the input resistor R2 (providing your resistors are rated for this voltage).
Since the TLV600 is powered by the Nano +5 V supply it cannot produce an output voltage above 5 V or below 0 V, so the input is accurately clamped WITHOUT impacting the A/D range at all. You must make sure that your MCU solution is always drawing a minimum current greater than your expected protection current (this is only an issue if you put things into a sleep state).
Note:
While not asked as part of your question ….you are NOT driving the PWM fan correctly. You should NOT provide active pullup to the fan unless the datasheet specifically says you can.
You need to read and understand the specification for the 4-wire fan you are likley using.
Probably the best historical document describing the fan spec was produced by Intel on Formfactors.org, that site is long gone but you can get the document here.
In this document the PWM freq is stated as 21-28kHz and the PWM drive signal MUST be an open collector/Drain drive (in other words a pullup resistor or active pullup was NOT permitted). The voltage on the PWM pin was no more than 5.25V, but this was set by the fan ....not the driving elements.
In some fans available today, if you actively pullup the PWM pin or connect to two fans you will get the wrong speed. Most of the early fans had a limited low speed range too, with 20-30% full speed not unusual. In the worse case you may actually damage the fan with a high current pullup as you have it.
Things have changed over the years and many fan manufacturers have improved their specifications. One example here for the Delta fans which can use a PWM freq of 30Hz- 30kHz, tolerates active pullup and 10V PWM amplitude.
Arctic fans are another example, with their own specification for multiple fans (up to 4) on one PWM signal line.
The correct way to drive the fan PWM is like this:
simulate this circuit
Driven as shown above you would not need the extra regulator or the buffered driver you created.
Warning: One answer on this thread says it's quite ok to use the Absolute Maximum rating on the inputs. THIS WILL RESULT IN DEVICE FAMAGE.
The warning in the datasheet is clear:
For example, in the operational characteristics for the A/D inputs the datasheet shows the input voltage limits as Gnd and VCC. See Table 21-10.
You should never design to use the intrinsic diodes to clamp the input excursions. While Microchip don't have any clear characterization of the input protection you might find this helpful reading to understand the problem.
You may already know that the output current for I/O pins is limited, and for a group of pins you should not exceed 60mA total ..this is because you risk blowing a track on the chip. I would fear the same may apply to the input protection (intrinsic) diodes, and if you have excessive current you may permanently damage the device. In any professional design you should not be depending on the protection of these diodes. You should externally and accurate clamp all inputs (and outputs) especially if your design is subject to abuse (such as students). |
H: Am I applying the KCL the right way?
Applying KCL at the node where I have drawn the currents in order to find Vin/Vs,
I am not getting the correct answer which however I did obtain using the Voltage Divider. My question is, am I using the KCL wrong way?
Using KCL: Vin/Vs = (R/Rs)
Using Voltage divider (correct answer): Vin/Vout = R/(Rs+R)
The way I approached with KCL:
AI: the initial equation should be:
$$\frac{Vs-Vin}{Rs}+\frac{Vo-Vin}{Rf}=\frac{Vin}{R}$$
assuming Rf is large, this simplifies to:
$$\frac{Vs-Vin}{Rs}=\frac{Vin}{R}$$
$$\frac{Vs}{Rs}-\frac{Vin}{Rs}=\frac{Vin}{R}$$
$$R Vs - R Vin = Rs Vin$$
$$R Vs = R Vin + Rs Vin = (Rs+R) Vin$$
$$\frac{Vin}{Vs}=\frac{R}{R+Rs}$$ |
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