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#include <bits/stdc++.h> using namespace std; void solve(int* arr, int n) { int max_sum = 0; int answer = 0; for (int i = 1; i <= 30; i++) { int current = 0; max_sum = 0; for (int j = 0; j < n; j++) { if (arr[j] > i) { current = 0; continue; } current = current + arr[j]; if (current < 0) { current = 0; } max_sum = max(current, max_sum); } answer = max(answer, max_sum - i); } cout << answer << endl; } int main() { int n; cin >> n; int arr[200005]; for (int i = 0; i < n; i++) { cin >> arr[i]; } solve(arr, n); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; struct Rect { int right, left, top, bottom; int height() { return top - bottom; } int width() { return right - left; } int area() { return (top - bottom) * (right - left); } }; void solve() { int w, h; cin >> w >> h; Rect first, second; second.bottom = 0, second.left = 0; cin >> first.left >> first.bottom >> first.right >> first.top; cin >> second.right >> second.top; bool move_y = first.height() + second.height() <= h, move_x = first.width() + second.width() <= w; if (!move_y && !move_x) { cout << -1 << n ; return; } else { vector<int> moves; if (move_x) { moves.push_back(second.right - first.left); moves.push_back(first.right - (w - second.width())); } if (move_y) { moves.push_back(second.top - first.bottom); moves.push_back(first.top - (h - second.height())); } int ans = INT_MAX; for (auto i : moves) { ans = min(ans, max(i, 0)); } cout << ans; } cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; list<int> l[100005]; list<int> son[100005]; int n, dad[100005], x, y, val[100005], res; void f(int a) { for (list<int>::iterator it = l[a].begin(); it != l[a].end(); it++) if ((*it) != dad[a]) { dad[*it] = a; f(*it); son[a].push_back(*it); } } pair<long long int, long long int> calc(int a) { pair<long long int, long long int> ret = pair<long long int, long long int>(0, 0); pair<long long int, long long int> tmp; for (list<int>::iterator it = son[a].begin(); it != son[a].end(); it++) if (*it != dad[a]) { tmp = calc(*it); ret = pair<long long int, long long int>(max(tmp.first, ret.first), max(tmp.second, ret.second)); } int change = ret.first - ret.second; if (val[a] + change > 0) ret.second += abs(val[a] + change); else ret.first += abs(val[a] + change); return ret; } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; i++) { scanf( %d %d , &x, &y); l[x].push_back(y); l[y].push_back(x); } for (int i = 1; i <= n; i++) scanf( %d , &val[i]); f(1); pair<long long int, long long int> res = calc(1); cout << res.first + res.second << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; string str; cin >> n >> str; int sum = 0; bool flag = false; for (int i = 0; i < n - 1; i++) { sum += str[i] - 48; int ts = 0, ti = i + 1; while (ti < n && ts <= sum) { if (ts == sum && str[ti] != 48) { ts = 0; } ts += str[ti] - 48; ti++; } if (ti == n && ts == sum) { flag = true; break; } } if (flag) { cout << YES ; } else { cout << NO ; } } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module scales video streams on the DE boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_scaler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Frame's Channel Width
parameter DW = 7; // Frame's Data Width
parameter EW = 0; // Frame's Empty Width
parameter WIW = 9; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 640;
parameter WIDTH_DROP_MASK = 4'b0000;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 9; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 640; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [CW: 0] stream_out_channel;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [CW: 0] internal_channel;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_multiply_height Multiply_Height (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// Bi-Directional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_channel (stream_out_channel),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Multiply_Height.DW = DW,
Multiply_Height.WW = MH_WW,
Multiply_Height.WIDTH = MH_WIDTH_IN,
Multiply_Height.MCW = MH_CW;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, a[N]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); if (a[n] >= a[n - 1] + a[n - 2]) cout << NO ; else { cout << YES n ; cout << a[n] << ; for (int i = n - 2; i >= 1; i--) cout << a[i] << ; cout << a[n - 1]; } return 0; } |
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// Ternary CAM made from stitched RAM based blocks
module ram_based_cam (clk,rst,start_write,waddr,wdata,wcare,
lookup_data,match_lines,ready,match_found);
parameter DATA_BLOCKS = 4; // number of blocks of 7 bits
parameter ADDR_WIDTH = 5;
localparam DATA_PER_BLOCK = 8; // Note : affects write latency
localparam DATA_WIDTH = DATA_BLOCKS * DATA_PER_BLOCK;
localparam WORDS = (1 << ADDR_WIDTH);
input clk,rst,start_write;
input [ADDR_WIDTH-1:0] waddr;
input [DATA_WIDTH-1:0] wdata,wcare;
input [DATA_WIDTH-1:0] lookup_data;
output [WORDS-1:0] match_lines;
wire [WORDS-1:0] match_lines;
output ready;
output match_found;
wire match_found;
reg match_found_reg;
// Workhorse blocks, stitch to create wider data
wire [DATA_BLOCKS * WORDS-1:0] block_match_lines;
wire [DATA_BLOCKS-1:0] block_ready;
genvar i,j;
generate
for (i=0;i<DATA_BLOCKS;i=i+1)
begin : db
cam_ram_block cr (
.clk(clk),
.rst(rst),
.waddr(waddr),
.wdata(wdata[DATA_PER_BLOCK*(i+1)-1:DATA_PER_BLOCK*i]),
.wcare(wcare[DATA_PER_BLOCK*(i+1)-1:DATA_PER_BLOCK*i]),
.start_write(start_write),
.ready(block_ready[i]),
.lookup_data(lookup_data[DATA_PER_BLOCK*(i+1)-1:DATA_PER_BLOCK*i]),
.match_lines(block_match_lines[WORDS*(i+1)-1:WORDS*i])
);
defparam cr .DATA_WIDTH = DATA_PER_BLOCK;
defparam cr .ADDR_WIDTH = ADDR_WIDTH;
end
endgenerate
// In the current design all of the block readies will
// move together. If they were allowed to cut corners
// on the don't care for example they should be AND ed
// together
assign ready = block_ready[0];
// Combine match lines. Address match must be true for
// all data blocks to be true for the full data word.
generate
for (j=0;j<WORDS;j=j+1)
begin : mta
wire [DATA_BLOCKS-1:0] tmp_match;
for (i=0;i<DATA_BLOCKS;i=i+1)
begin : mtb
assign tmp_match[i] = block_match_lines[WORDS*i+j];
end
assign match_lines[j] = &tmp_match;
end
endgenerate
// Added by Hari; Need to verify whether its correct
always@(match_lines) begin
if (match_lines != 0) begin
match_found_reg = 1'b1;
end
else
match_found_reg = 1'b0;
end
assign match_found = match_found_reg;
endmodule |
#include <bits/stdc++.h> using namespace std; inline long long sqr(long long x) { return x * x; } mt19937 Random((int)time(0)); inline long long rnd(long long x) { return Random() % x; } const long long INF = (long long)1e9 + 2018; const long long MOD = (long long)1e9 + 7; const long double PI = acos(-1.0); pair<int, int> cnt(int n) { if (n & 1) { return {sqr(n / 2 + 1) + sqr(n / 2), n * n - sqr(n / 2 + 1) - sqr(n / 2)}; } else { return {n * n / 2, n * n / 2}; } } void $main() { int n; cin >> n; int a = 0, b = 0; for (int i = 0; i < n; i++) { string s; cin >> s >> s; a += s == hard ; b += s == soft ; } for (int i = 1;; i++) { pair<int, int> res = cnt(i); if ((res.first >= a && res.second >= b) || (res.second >= a && res.first >= b)) { cout << i; return; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.setf(ios_base::fixed, ios_base::floatfield); cout.precision(10); $main(); } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000005; struct node { int l, r, sum, id; } tr[200010 * 4]; void build(int l, int r, int x) { tr[x].l = l, tr[x].r = r; if (l == r) { tr[x].sum = 0; tr[x].id = l; return; } int mid = (l + r) >> 1; build(l, mid, x << 1); build(mid + 1, r, x << 1 | 1); if (tr[x << 1].sum > tr[x << 1 | 1].sum) tr[x].sum = tr[x << 1].sum, tr[x].id = tr[x << 1].id; else tr[x].sum = tr[x << 1 | 1].sum, tr[x].id = tr[x << 1 | 1].id; } pair<int, int> query(int L, int R, int x) { int l = tr[x].l, r = tr[x].r; if (L == tr[x].l && R == tr[x].r) { return make_pair(tr[x].sum, tr[x].id); } int mid = (l + r) >> 1; if (R <= mid) return query(L, R, x << 1); else if (L > mid) return query(L, R, x << 1 | 1); else { pair<int, int> p = query(L, mid, x << 1), q = query(mid + 1, R, x << 1 | 1); if (p.first > q.first) return p; else return q; } } void upd(int L, int R, int x, int val) { int l = tr[x].l, r = tr[x].r; if (L == l && R == r) { tr[x].sum = val; tr[x].id = l; return; } int mid = (l + r) >> 1; if (R <= mid) upd(L, R, x << 1, val); else upd(L, R, x << 1 | 1, val); if (tr[x << 1].sum > tr[x << 1 | 1].sum) tr[x].sum = tr[x << 1].sum, tr[x].id = tr[x << 1].id; else tr[x].sum = tr[x << 1 | 1].sum, tr[x].id = tr[x << 1 | 1].id; } struct EDGE { int v, next, val; } edges[200010 * 2]; int head[200010], cnt; void addedge(int u, int v, int val) { edges[cnt].v = v; edges[cnt].next = head[u]; edges[cnt].val = val; head[u] = cnt++; edges[cnt].v = u; edges[cnt].next = head[v]; edges[cnt].val = val; head[v] = cnt++; } int n, m; int size[200010], fa[200010], dep[200010], son[200010]; void dfs1(int u, int pre, int depth) { size[u] = 1; son[u] = -1; fa[u] = pre; dep[u] = depth; for (int i = head[u]; i != -1; i = edges[i].next) { int x = edges[i].v; if (x == pre) continue; dfs1(x, u, depth + 1); if (son[u] == -1 || size[son[u]] < size[x]) { son[u] = x; } size[u] += size[x]; } } int top[200010], pos[200010], no = 1, re[200010]; void dfs2(int u, int tops) { top[u] = tops; pos[u] = no++; if (son[u] == -1) { return; } dfs2(son[u], tops); for (int i = head[u]; i != -1; i = edges[i].next) { int x = edges[i].v; if (x == fa[u] || x == son[u]) continue; dfs2(x, x); } } void dfs3(int u, int fa) { for (int i = head[u]; i != -1; i = edges[i].next) { int x = edges[i].v; if (x == fa) continue; upd(pos[x], pos[x], 1, edges[i].val); dfs3(x, u); } } int sum[200010]; pair<int, int> qry(int x, int y) { int f1 = top[x], f2 = top[y]; pair<int, int> res(0, -1), tmp; while (f1 != f2) { if (dep[f1] < dep[f2]) { swap(f1, f2); swap(x, y); } tmp = query(pos[f1], pos[x], 1); if (tmp.first > res.first) res = tmp; x = fa[f1]; f1 = top[x]; } if (x == y) return res; if (dep[x] < dep[y]) swap(x, y); tmp = query(pos[son[y]], pos[x], 1); if (tmp.first > res.first) res = tmp; return res; } struct bian { pair<int, int> z; long long w, c; int id; } ed[200010]; bool cmp(bian a, bian b) { if (a.w == b.w) return a.c < b.c; else return a.w < b.w; } int pa[200010]; bool vis[200010]; int root(int x) { if (pa[x] == -1) return x; else { pa[x] = root(pa[x]); return pa[x]; } } int main() { int n, m, i, j; long long s; memset(head, -1, sizeof(head)); memset(pa, -1, sizeof(pa)); memset(vis, 0, sizeof(vis)); cnt = 0; scanf( %d %d , &n, &m); for (i = 1; i <= m; i++) scanf( %I64d , &ed[i].w), ed[i].id = i; for (i = 1; i <= m; i++) scanf( %I64d , &ed[i].c); for (i = 1; i <= m; i++) scanf( %d %d , &ed[i].z.first, &ed[i].z.second); scanf( %I64d , &s); sort(ed + 1, ed + m + 1, cmp); int mn = INF, mnid = -1; long long ans = 0, sm = 0; for (i = 1; i <= m; i++) { int u = ed[i].z.first, v = ed[i].z.second; if (root(u) != root(v)) { pa[root(u)] = root(v); vis[i] = 1; addedge(u, v, ed[i].w); if (ed[i].c < mn) mn = ed[i].c, mnid = i; ans += ed[i].w; } } build(1, n, 1); dfs1(1, 0, 1); dfs2(1, 1); dfs3(1, 0); for (i = 1; i <= n; i++) re[pos[i]] = i; int nw = -1, nwf = -1; ans -= s / mn; sm = ans + s / mn; for (i = 1; i <= m; i++) { if (vis[i]) continue; pair<int, int> mx = qry(ed[i].z.first, ed[i].z.second); if (sm - (long long)mx.first + ed[i].w - s / ed[i].c < ans) { ans = sm - (long long)mx.first + ed[i].w - s / ed[i].c; nw = i; nwf = mx.second; } } printf( %I64d n , ans); if (nw == -1) { for (i = 1; i <= m; i++) { if (vis[i] && i != mnid) { printf( %d %I64d n , ed[i].id, ed[i].w); } else if (mnid == i && vis[i]) { printf( %d %I64d n , ed[i].id, ed[i].w - s / ed[i].c); } } } else { for (i = 1; i <= m; i++) { if (i == nw) { printf( %d %I64d n , ed[i].id, ed[i].w - s / ed[i].c); } else if (vis[i]) { if (ed[i].z.first == re[nwf] && ed[i].z.second == fa[re[nwf]] || ed[i].z.second == re[nwf] && ed[i].z.first == fa[re[nwf]]) continue; printf( %d %I64d n , ed[i].id, ed[i].w); } } } } |
#include <bits/stdc++.h> using namespace std; int n, m, u, v, num_col = 1; vector<int> adjList[5001]; vector<int> edges[5001]; bitset<5001> vis; bitset<5001> act; bitset<5001> col; void dfs(int nd) { vis[nd] = 1; act[nd] = 1; for (int k = 0; k < adjList[nd].size(); k++) { int nd_b = adjList[nd][k]; int edge_num = edges[nd][k]; if (!vis[nd_b]) dfs(nd_b); else if (act[nd_b]) { num_col = 2; col[edge_num] = 1; } } act[nd] = 0; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { cin >> u >> v; u--; v--; adjList[u].push_back(v); edges[u].push_back(i); } for (int i = 0; i < n; i++) { if (!vis[i]) dfs(i); } cout << num_col << endl; for (int i = 0; i < m; i++) { cout << (((int)col[i]) + 1) << (i < m - 1 ? : ); } cout << endl; return 0; } |
// Check behaviour with out-of-range and undefined array indices
// on LHS of procedural continuous (reg) assignment.
module top;
reg [1:0] array1[2:1];
reg [1:0] array2[1:0];
reg [1:0] var1;
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
real var2;
`endif
reg failed;
initial begin
failed = 0;
array1[1] = 2'd0;
array1[2] = 2'd0;
array2[0] = 2'd0;
array2[1] = 2'd0;
assign array1[0] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[0];
/* This is not supported at present
assign array1[1] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[1];
assign array1[2] = var1;
var1 = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1;
var1 = 2'd2;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1;
deassign array1[2];
*/
assign array1[3] = var1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[3];
assign array2['bx] = 2'd1;
#1 $display("array = %h %h", array2[1], array2[0]);
if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1;
deassign array2['bx];
`ifndef VLOG95
array3[1] = 0.0;
array3[2] = 0.0;
array4[0] = 0.0;
array4[1] = 0.0;
assign array3[0] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[0];
/* This is not supported at present
assign array3[1] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[1];
assign array3[2] = var2;
var2 = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1;
var2 = 2.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1;
deassign array3[2];
*/
assign array3[3] = var2;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[3];
assign array4['bx] = 1.0;
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
deassign array4['bx];
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:19:47 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemWinner/MemWinner_stub.v
// Design : MemWinner
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module MemWinner(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[4:0],clk,spo[107:0]" */;
input [4:0]a;
input clk;
output [107:0]spo;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decaphe (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V |
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v1_8_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long mod = 1000000007; const double e = 2.718281828459; long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } long long gcd1(int a, int b) { if (!b) return a; return gcd(b, a % b); } long long pow_mod(long long a, long long b, long long c) { long long ans = 1; a = a % c; while (b > 0) { if (b % 2 == 1) ans = (ans * a) % c; b = b / 2; a = (a * a) % c; } return ans; } int pow_int(int a, int b) { int ans = 1; while (b > 0) { if (b % 2 == 1) ans = ans * a; b = b / 2; a = a * a; } return ans; } long long pow_llong(long long a, long long b) { long long ans = 1; while (b > 0) { if (b % 2 == 1) ans = ans * a; b = b / 2; a = a * a; } return ans; } const int dx[9] = {0, 1, 1, 1, 0, -1, -1, -1, 0}; const int dy[9] = {0, 1, 0, -1, -1, -1, 0, 1, 1}; int Scan() { int res = 0, flag = 0; char ch; if ((ch = getchar()) == - ) { flag = 1; } else if (ch >= 0 && ch <= 9 ) { res = ch - 0 ; } while ((ch = getchar()) >= 0 && ch <= 9 ) { res = res * 10 + (ch - 0 ); } return flag ? -res : res; } void Out(int a) { if (a < 0) { putchar( - ); a = -a; } if (a >= 10) { Out(a / 10); } putchar(a % 10 + 0 ); } long long jc_mod(long long a, long long b, long long mod) { long long ans = 1; b = max(b, a - b); for (long long i = a; i > b; i--) { ans *= i; ans %= mod; } return ans; } double lg(double a) { return (log(a) / log(10.0)); } int lowbit(int x) { return x & -x; } inline int read() { int f = 1, x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void lisan(int *x, int n) { int data[100010]; for (int i = 1; i <= n; i++) data[i] = x[i]; sort(data + 1, data + 1 + n); int o = unique(data + 1, data + 1 + n) - data - 1; for (int i = 1; i <= n; i++) x[i] = lower_bound(data + 1, data + 1 + o, x[i]) - data; } long long calc(int M) { return 1; } int sanfen(int L, int R) { int M, RM; while (L + 1 < R) { M = (L + R) / 2; RM = (M + R) / 2; if (calc(M) < calc(RM)) R = RM; else L = M; } return L; } int CaculateWeekDay(int y, int m, int d) { if (m == 1 || m == 2) { m += 12; y--; } int iWeek = (d + 2 * m + 3 * (m + 1) / 5 + y + y / 4 - y / 100 + y / 400) % 7; return iWeek; } map<string, int> mm; map<char, int> cc; string a; char t[100]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { cin >> a; int q = 0; cc.clear(); int len = a.length(); for (int i = 0; i < len; i++) { if (!cc[a[i]]) { cc[a[i]] = 1; t[q++] = a[i]; } } t[q] = 0; sort(t, t + q); string y = t; mm[y] = 1; } printf( %d n , mm.size()); return 0; } |
#include <bits/stdc++.h> const long long oo = 1e16; using namespace std; const int N = 1000005; long long n, dp[N]; long long num(long long n) { if (n == 0) return 0; if (dp[n] != -1) return dp[n]; string s = to_string(n); long long res = oo; for (int i = 0; i < s.size(); i++) if (s[i] != 0 ) res = min(res, 1 + num(n - (s[i] - 0 ))); return dp[n] = res; } int main() { cin >> n; memset(dp, -1, sizeof(dp)); cout << num(n); return 0; } |
//
// iverilog -DNO_DEBUG tb_top.v ...
//
//
`timescale 1ns/1ns
module tb_top;
reg clk, rst;
wire [31:0] addr;
wire write_en;
wire [31:0] wdata;
wire [31:0] rdata;
initial begin
clk <= 0;
rst <= 1;
#105
rst <= 0;
#1000
$finish;
end
always begin
#10 clk = ~clk;
end
`ifndef NO_DEBUG
// always @(posedge clk) begin
// $display("time %t, %d %d", $time, rst, dut.top_main_inst.cur_st);
// end
`endif
top dut(.clk(clk), .rst(rst)
`ifndef NO_MEMORY
,
.sram_addr(addr), .sram_wdata_en(write_en),
.sram_wdata(wdata), .sram_rdata(rdata)
`endif
);
`ifndef NO_MEMORY
mem16k mem(.clk_i(clk), .rst_i(rst),
.addr_i(addr[31:2]), .write_en_i(write_en),
.wdata_i(wdata), .rdata_o(rdata));
`endif
endmodule
// 1word = 4bytes
module mem16k(clk_i, rst_i, addr_i, write_en_i, wdata_i, rdata_o);
input clk_i, rst_i;
input [29:0] addr_i;
input write_en_i;
input [31:0] wdata_i;
output [31:0] rdata_o;
reg [31:0] storage[0:4095];
integer i;
initial begin
`ifndef NO_DEBUG
$display("mem16k init");
`endif
for (i = 0; i < 4096; i = i + 1) begin
storage[i] = 0;
end
end
always @(posedge clk_i) begin
if (rst_i) begin
end else begin
// $display("%t mem:read addr=%x,data=%x", $time, addr_i<<2, storage[addr_i[11:0]]);
if (write_en_i) begin
// $display("%t mem:write addr=%x,data=%x\n", $time, addr_i<<2, wdata_i);
storage[addr_i[11:0]] <= wdata_i;
end
end
end
assign rdata_o = storage[addr_i[11:0]];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int X = 100000 + 5; long long C[1005][1005]; long long n, m; long long iis, ii, jjs, jj, cc; void calc() { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cc += C[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { ii += C[i][j] * (i * 4 + 2); iis += (i * 4 + 2) * (i * 4 + 2) * C[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { jj += C[i][j] * (j * 4 + 2); jjs += (j * 4 + 2) * (j * 4 + 2) * C[i][j]; } } } long long dist(long long x, long long y) { x *= 4; y *= 4; long long s = iis + x * x * cc - 2 * x * ii + jjs + y * y * cc - 2 * y * jj; return s; } long long foo(long long x, long long& z) { long long lo = 0, hi = m, mm = LLONG_MAX; while (lo + 2 < hi) { long long ml = lo + (hi - lo) / 3, mr = hi - (hi - lo) / 3; long long l = dist(x, ml), r = dist(x, mr); if (l <= r) hi = mr; else lo = ml; } for (int i = 0; i <= 2; i++) { long long cc = dist(x, lo + i); if (cc < mm) { mm = cc; z = lo + i; } } return mm; } void MAIN() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> C[i][j]; } } calc(); long long mm = LLONG_MAX, xx = -1, yy = -1; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { long long z = dist(i, j); if (z < mm) { mm = z; xx = i; yy = j; } } } cout << mm << n << xx << << yy; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout << setprecision(12); MAIN(); return 0; } |
/*
// Verilog syntax highlighting test file.
* Ryan Dalzell, 19th October 2005
* License: as-is
* NOTE This whole comment section should fold
* Testing the alerts:
* FIXME HACK NOTE NOTICE TASK TODO ###
*/
`timescale 1ns/1ns // comment in a directive.
`define ns 1
// typical Verilog syntax.
module test (clock, reset, clear, enable, d, q);
parameter param = 8;
parameter name = "test";
localparam local = param*4;
input clock;
input reset;
input clear;
input enable;
input [param-1:0] d;
output [param-1:0] q;
wire [param-1:0] in;
wire [param-1:0] out;
// a generate block, should also fold.
genvar i;
generate
for (i=0; i<param; i=i+1)
begin: test
buf(out[i], in[i]);
end
endgenerate
reg signed [param-1:0] q;
always @(posedge clock or negedge reset)
begin: register // named block.
if (!reset || clear) begin // unnamed block.
q <= 0;
end else begin
if (enable) begin q <= $signed(d); end // block on one line, shouldn't fold.
end
end
endmodule
// a Verilog state machine.
module test2 (clock, reset, clear, enable, start, ready);
input clock;
input reset;
input clear;
input enable;
input start;
output ready;
parameter [1:0] idle = 2'b00; // binary number.
parameter [1:0] run = 2'b01;
parameter [1:0] same1 = 2'b10;
parameter [1:0] same2 = 2'b11;
reg [1:0] state;
wire state2;
wire state3;
wire state4;
always @(posedge clock or negedge reset)
begin
if (!reset)
state <= idle;
else
if (enable) begin
case (state)
idle: begin
if (start)
state <= run;
end
run: begin
state <= idle;
end
same1, same2: begin
state <= idle;
end
endcase
end
end
// some instantiations.
test test_positional(clock, reset, clear, enable, state, state2);
test test_named(.clock(clock), .reset(reset), .clear(clear), .enable(enable), .d(state), .q(state3));
// a conditional operator.
assign state4 = state==idle? state2 : state3;
endmodule
// bad syntax
modules bad (clock, reset, clear, enable);
inout clock;
inpu reset;
outputs enable;
endmod
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, a[N], d[N], b[21][N], a2[25], ans[N]; void dg(int x) { if (x > 20) { if (d[0] < ans[0]) for (int i = 0; i <= d[0]; i++) ans[i] = d[i]; return; } int pos = 0; for (int i = 1; i <= n; i++) pos |= a[i] & a2[x]; if (!pos) dg(x + 1); else { int n0 = n; for (int i = 1; i <= n0; i++) b[x][i] = a[i]; d[++d[0]] = a2[x]; for (int i = 1; i <= n0; i++) if (b[x][i] & a2[x]) a[i] = b[x][i] - a2[x]; else a[i] = b[x][i]; sort(a + 1, a + n0 + 1); n = 0; for (int i = 1; i <= n0; i++) if (i == 1 || a[i] != a[i - 1]) a[++n] = a[i]; dg(x + 1); d[d[0]] = -a2[x]; for (int i = 1; i <= n0; i++) if (b[x][i] & a2[x]) a[i] = b[x][i] + a2[x]; else a[i] = b[x][i]; n = 0; for (int i = 1; i <= n0; i++) if (i == 1 || a[i] != a[i - 1]) a[++n] = a[i]; dg(x + 1); d[0]--; } } int main() { a2[0] = 1; for (int i = 1; i <= 20; i++) a2[i] = a2[i - 1] * 2; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); ans[0] = 30; dg(0); printf( %d n , ans[0]); for (int i = 1; i <= ans[0]; i++) printf( %d , ans[i]); } |
#include <bits/stdc++.h> using namespace std; long long n, l, r, k, c, i; string s; int main() { ios_base::sync_with_stdio(0); cin >> n; if (n == 0) { cout << a << n ; return 0; } while (n > 0) { l = 1; r = 100000; k++; while (l < r) { c = (l + r) / 2; if (c * (c - 1) / 2 > n) r = c; else l = c + 1; } if (l * (l - 1) / 2 > n) l--; n -= (l * (l - 1) / 2); for (i = 1; i <= l; i++) s += char(96 + k); } cout << s << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_BLACKBOX_V
`define SKY130_FD_SC_LP__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NAND4_BEHAVIORAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1 << 18; const int MOD = 2013265921, MAX = MOD / 2; const int gen = 440564289; long long power(long long x, int n) { if (n <= 1) return n ? x : 1LL; long long t = power(x, n / 2); if (n & 1) return (t * t % MOD) * x % MOD; else return t * t % MOD; } long long tmp[maxn]; void DFT(long long *a, long long x, int n) { if (n == 1) { a[0] %= MOD; if (a[0] < 0) a[0] += MOD; return; } for (int i = 0; i < n; i++) tmp[i] = a[i]; for (int i = 0; i < n; i++) a[i % 2 ? n / 2 + i / 2 : i / 2] = tmp[i]; long long *a1 = a, *a2 = a + n / 2, xx = x * x % MOD; DFT(a1, xx, n / 2); DFT(a2, xx, n / 2); long long now = 1; for (int i = 0; i < n / 2; i++, now = now * x % MOD) { long long val = now * a2[i] % MOD; tmp[i] = a1[i] + val - MOD; tmp[i + n / 2] = a1[i] - val; } for (int i = 0; i < n; i++) a[i] = (tmp[i] < 0 ? tmp[i] + MOD : tmp[i]); } void mul(long long *a, long long *b, long long *c, int n) { long long x = power(gen, (1 << 27) / n), xinv = power(x, n - 1); long long ninv = power(n, MOD - 2); DFT(a, x, n); DFT(b, x, n); for (int i = 0; i < n; i++) c[i] = a[i] * b[i] % MOD; DFT(c, xinv, n); for (int i = 0; i < n; i++) { c[i] = c[i] * ninv % MOD; if (c[i] > MAX) c[i] -= MOD; } } int n, m, Q, L; char s[maxn], t[maxn]; unsigned long long sbit[maxn], tbit[maxn]; int match(int x, int y, int len) { int ret = 0; for (; len >= 64; len -= 64, x += 64, y += 64) ret += __builtin_popcountll(sbit[x] ^ tbit[y]); if (len) ret += __builtin_popcountll((sbit[x] << (64 - len)) ^ (tbit[y] << (64 - len))); return ret; } long long *poly[maxn], a[maxn], b[maxn]; void precal() { n = strlen(s), m = strlen(t); for (int i = 0; i < n; i++) for (int j = 0; j < 64 && i + j < n; j++) if (s[i + j] == 1 ) sbit[i] |= (1ULL << j); for (int i = 0; i < m; i++) for (int j = 0; j < 64 && i + j < m; j++) if (t[i + j] == 1 ) tbit[i] |= (1ULL << j); L = n * sqrt(150 * log2(n) / Q); int n2 = 1; while (n2 < L + m) n2 *= 2; for (int i = 0; i < n; i += L) { poly[i / L] = new long long[n2]; memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); for (int j = 0; j < L && i + j < n; j++) a[j] = (s[i + j] == 0 ? -1 : 1); for (int j = 0; j < m; j++) b[m - 1 - j] = (t[j] == 0 ? -1 : 1); mul(a, b, poly[i / L], n2); } } int main() { scanf( %s%s%d , s, t, &Q); precal(); while (Q--) { int x, y, l; scanf( %d%d%d , &x, &y, &l); if (l <= L) { printf( %d n , match(x, y, l)); continue; } int ans = 0; if (x % L) { int l2 = L - x % L; ans += match(x, y, l2); x += l2; y += l2; l -= l2; } if ((x + l) % L) { int l2 = (x + l - 1) % L + 1; ans += match(x + l - l2, y + l - l2, l2); l -= l2; } if (!l) { printf( %d n , ans); continue; } for (int i = x, j = y; l; i += L, j += L, l -= L) ans += (L - poly[i / L][m - 1 - j]) / 2; printf( %d n , ans); } } |
#include <bits/stdc++.h> int main(void) { int a, b, m, n, count = 0; scanf( %d %d , &n, &m); for (a = 0; a <= m; a++) { for (b = 0; b <= n; b++) { if (n - b != a * a) continue; if (m - a != b * b) continue; count++; break; } } printf( %d n , count); return 0; } |
#include <bits/stdc++.h> using namespace std; bool sushu(long long n) { long long t = sqrt(n); for (long long i = 2; i <= t; i++) { if (n % i == 0) return false; } return true; } long long ret(long long n) { long long ne = 0; while (n != 0) { ne = ne * 10 + n % 10; n = n / 10; } return ne; } int main() { long long n, ans; long long a[11190]; long long i, num = 0; for (i = 13;; i++) { if (sushu(i) && sushu(ret(i)) && i != ret(i)) { a[num++] = i; if (num == 11184) break; } } while (cin >> n) { cout << a[n - 1] << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_BLACKBOX_V
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* *** NOT FOR SYNTHESIS ***
*
*/
module LAG_traffic_sink (flit_in, cntrl_out, rec_count, stats, clk, rst_n);
parameter xdim = 4;
parameter ydim = 4;
parameter xpos = 0;
parameter ypos = 0;
parameter warmup_packets = 100;
parameter measurement_packets = 1000;
parameter global_links_num = 2;
parameter local_links_num = 2;
input flit_t flit_in [global_links_num-1:0];
output logic [global_links_num-1:0] cntrl_out;
output sim_stats_t stats;
input clk, rst_n;
output integer rec_count;
integer expected_flit_id [local_links_num-1:0];
integer head_injection_time [local_links_num-1:0];
integer latency, sys_time;
integer src_x, src_y;
integer j, i;
integer warmup_rec_count;
genvar ch;
for (ch=0; ch<local_links_num; ch++) begin:flow_control
always@(posedge clk) begin
if (!rst_n) begin
cntrl_out[ch] <= 0;
end else begin
if (flit_in[ch].control.valid) begin
if (ch < local_links_num) begin
cntrl_out[ch] <= 1;
end else begin
$display ("%m: Error: Flit Channel ID is out-of-range for exit from network!");
$display ("Channel ID = %1d (router_num_pls_on_exit=%1d)", ch, router_num_pls_on_exit);
$finish;
end
end else begin
cntrl_out[ch] <= 0;
end
end
end
end
always@(posedge clk) begin
if (!rst_n) begin
rec_count=-1;
stats.total_latency=0;
stats.total_hops=0;
stats.max_hops=0;
stats.min_hops=MAXINT;
stats.max_latency=0;
stats.min_latency=MAXINT;
stats.measure_start=-1;
stats.measure_end=0;
stats.flit_count=0;
warmup_rec_count = 0;
src_x = 0;
src_y = 0;
for(i = 0; i < xdim; i++)
for(j = 0; j < ydim; j++) begin
stats.flows_latencies[i][j][0] = 0;
stats.flows_latencies[i][j][1] = 0;
stats.flows_latencies[i][j][2] = 0;
stats.flows_latencies[i][j][3] = 32'd1000000;
stats.flows_latencies[i][j][4] = 0;
end
for (j=0; j<local_links_num; j++) begin
expected_flit_id[j]=1;
head_injection_time[j]=-1;
end
for (j=0; j<=100; j++) begin
stats.lat_freq[j]=0;
end
sys_time = 0;
end else begin // if (!rst_n)
sys_time++;
for (i=0; i<local_links_num; i++) begin
if (flit_in[i].control.valid) begin
//$display ("%m: Packet %d arrived!!!", rec_count);
//
// check flit was destined for this node!
//
if ((flit_in[i].debug.xdest!=xpos)||(flit_in[i].debug.ydest!=ypos)) begin
$display ("%m: Error: Flit arrived at wrong destination!");
$finish;
end
//
// check flit didn't originate at this node
//
if ((flit_in[i].debug.xdest==flit_in[i].debug.xsrc)&&
(flit_in[i].debug.ydest==flit_in[i].debug.ysrc)) begin
$display ("%m: Error: Received flit originated from this node?");
$finish;
end
//
// check flits for each packet are received in order
//
if (flit_in[i].debug.flit_id != expected_flit_id[i]) begin
$display ("%m: Error: Out of sequence flit received? (packet generated at %1d,%1d)",
flit_in[i].debug.xsrc, flit_in[i].debug.ysrc);
$display ("-- Flit ID = %1d, Expected = %1d", flit_in[i].debug.flit_id, expected_flit_id[i]);
$display ("-- Packet ID = %1d", flit_in[i].debug.packet_id);
$finish;
end else begin
// $display ("%m: Rec: Flit ID = %1d, Packet ID = %1d, PL ID=%1d",
// flit_in.debug.flit_id, flit_in.debug.packet_id, flit_in.control.pl_id);
end
expected_flit_id[i]++;
// $display ("rec flit");
// #####################################################################
// Head of new packet has arrived
// #####################################################################
if (flit_in[i].debug.flit_id==1) begin
// $display ("%m: new head, current_pl=%1d, inject_time=%1d", current_pl, flit_in.debug.inject_time);
head_injection_time[i] = flit_in[i].debug.inject_time;
if ((warmup_rec_count == warmup_packets) && (stats.measure_start==-1)) stats.measure_start = sys_time;
end
// count all flits received in measurement period
if (stats.measure_start!=-1) stats.flit_count++;
// #####################################################################
// Tail of packet has arrived
// Remember, latency = (tail arrival time) - (head injection time)
// #####################################################################
if (flit_in[i].control.tail) begin
expected_flit_id[i]=1;
warmup_rec_count++;
if (stats.measure_start!=-1) begin
rec_count++;
// time last measurement packet was received
stats.measure_end = sys_time;
//
// gather latency stats.
//
latency = sys_time - head_injection_time[i];
stats.total_latency = stats.total_latency + latency;
stats.min_latency = min (stats.min_latency, latency);
stats.max_latency = max (stats.max_latency, latency);
src_x = flit_in[i].debug.xsrc;
src_y = flit_in[i].debug.ysrc;
stats.flows_latencies[src_x][src_y][0] = 1;
stats.flows_latencies[src_x][src_y][1] += latency;
stats.flows_latencies[src_x][src_y][2]++;
stats.flows_latencies[src_x][src_y][3] = min(stats.flows_latencies[src_x][src_y][3], latency);
stats.flows_latencies[src_x][src_y][4] = max(stats.flows_latencies[src_x][src_y][4], latency);
//
// sum latencies for different packet distances (and keep total distance travelled by all packets)
//
// $display ("This packet travelled %1d hops", flit_in.debug.hops);
stats.total_hops = stats.total_hops + flit_in[i].debug.hops;
stats.min_hops = min (stats.min_hops, flit_in[i].debug.hops);
stats.max_hops = max (stats.max_hops, flit_in[i].debug.hops);
//
// bin latencies
//
stats.lat_freq[min(latency, 100)]++;
end
end // if (flit_in.control.tail)
end // if flit valid
end //for
end //if(!rst_n)
end //always
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int q = 30; if (n == 1 || n == 3 || n == 5 || n == 7 || n == 8 || n == 10 || n == 12) q++; if (n == 2) q = 28; q = q - 8 + m; if (q % 7 == 0) cout << (q / 7) + 1; else cout << (q / 7) + 2; } |
#include <bits/stdc++.h> using namespace std; char str[40], ans[2][40], p[40]; int pre[40], sum[40]; int main() { scanf( %s , str); int L = 0, R = 0; bool mark = true; memset(pre, -1, sizeof(pre)); for (int i = 0; i < 27; i++) { int a = str[i] - A ; sum[a]++; if (pre[a] == -1) pre[a] = i; else { L = pre[a]; R = i; if (R - 1 == L) { mark = false; } } } int k = 0; for (int i = 0; i < 26; i++) { if (sum[i] == 0 || sum[i] > 2) mark = false; if (sum[i] == 2) k++; } if (k != 1 || !mark) { printf( Impossible n ); return 0; } R = 26 - R; int cnt = 0; if (L > R) { int o = 0; for (int i = 26; i >= 0; i--) { p[o++] = str[i]; } for (int i = 0; i < 27; i++) str[i] = p[i]; swap(L, R); } int num = R - L; if (num & 1) { num = (num / 2) + 1; int i; for (i = num;; i++) { if (cnt == L) break; ans[0][i] = str[cnt++]; } int flag = i - 1; ans[1][i - 1] = str[cnt++]; for (; i < 13; i++) ans[0][i] = str[cnt++]; for (int i = 12; i > flag; i--) { ans[1][i] = str[cnt++]; } cnt++; for (int i = flag - 1; i >= 0; i--) ans[1][i] = str[cnt++]; if (num) { for (int i = 0; i < num; i++) ans[0][i] = str[cnt++]; } } else { num = num / 2; int i; for (i = num;; i++) { if (cnt == L) break; ans[0][i] = str[cnt++]; } int flag = i; ans[1][i] = str[cnt++]; for (; i < 13; i++) ans[0][i] = str[cnt++]; for (int i = 12; i > flag; i--) { ans[1][i] = str[cnt++]; } cnt++; for (int i = flag - 1; i >= 0; i--) ans[1][i] = str[cnt++]; if (num) { for (int i = 0; i < num; i++) ans[0][i] = str[cnt++]; } } if (L == 0 && R == 0) { cnt = 0; for (int i = 0; i < 13; i++) ans[0][i] = str[cnt++]; for (int i = 12; i >= 0; i--) ans[1][i] = str[cnt++]; } for (int i = 0; i < 2; i++) { for (int j = 0; j < 13; j++) printf( %c , ans[i][j]); printf( n ); } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N, M; struct MATRIX { int dim; long long MAT[100][100]; MATRIX(int N, int x = -1) { dim = N; for (int i = 0; i < dim; i++) for (int j = 0; j < dim; j++) { if (x != -1 && i == j) MAT[i][j] = x; else MAT[i][j] = 0; } } void operator+=(const MATRIX& a) { for (int i = 0; i < a.dim; i++) { for (int j = 0; j < a.dim; j++) { MAT[i][j] += a.MAT[i][j]; } } } void show() { for (int i = 0; i < dim; i++) { for (int j = 0; j < dim; j++) cout << MAT[i][j] << ; cout << endl; } cout << endl; } }; MATRIX operator*(MATRIX a, MATRIX b) { MATRIX res(a.dim); for (int i = 0; i < a.dim; i++) { for (int j = 0; j < b.dim; j++) { long long sum = 0; for (int z = 0; z < a.dim; z++) { sum += a.MAT[i][z] * b.MAT[z][j]; } sum %= M; res.MAT[i][j] = sum; } } return res; } MATRIX binpow(MATRIX a, long long n) { MATRIX res = a; while (n) { if (n & 1) res = res * a; a = a * a; n >>= 1; } return res; } int main() { int X; cin >> N >> X; for (int i = 0; i < N; i++) { int a, b; cin >> a >> b; if (a == 7 - X || b == 7 - X || a == X || b == X) { cout << NO ; return 0; } } cout << YES ; return 0; } |
/**
* pc_system.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module pc_system(
input wire [ 7 : 0] switch_in,
input wire button,
input wire clk,
input wire res,
output wire [ 7 : 0] LED_status,
output wire [ 3 : 0] anode,
output wire [ 6 : 0] cathode
);
/* clock divider */
wire clk_div;
/* processor signals */
wire [ 7 : 0] pc_out, mar_out, mdr_in, mdr_out;
wire [15 : 0] instruction_in;
/* direct board clock */
assign clk_div = clk;
/* clock divider */
/*clock_divider clk_div0 (
.clk(clk),
.res(res),
.prescaler(2'b10),
.clk_out(clk_div)
);*/
/* clock generator */
/*clk_gen clk0(
.button(button),
.clk(clk),
.res(res),
.clk_div(clk_div)
);
*/
/* debug unit
* show instruction in 7-segment display
*/
insn_out debug_unit0 (
.insn(instruction_in),
.clk(clk),
.res(res),
.anode(anode),
.cathode(cathode)
);
/* memory decoder unit */
memory_decoder md0 (
.address(mar_out),
.data_in(mdr_out),
.switch_in(switch_in),
.clk(clk_div),
.res(res),
.write_enable(write_mem),
.LED_status(LED_status),
.data_out(mdr_in)
);
/* the processor */
processor core0 (
.clk(clk_div),
.res(res),
.instruction_in(instruction_in),
.mdr_in(mdr_in),
.pc_out(pc_out),
.mdr_out(mdr_out),
.mar_out(mar_out),
.write_mem(write_mem)
);
/* program memory subsystem */
progmem prom0 (
.pc(pc_out),
.instruction(instruction_in)
);
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; string str; cin >> n; cin >> str; int len = n - 11; int coun = 0, cou = 0; for (int j = 0; j < len + 1; j++) { if (str[j] == 8 ) coun = 1, cou++; ; } if (cou > len / 2) cout << YES ; else cout << NO ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfstp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_BEHAVIORAL_PP_V |
// ============================================================================
// Copyright (c) 2012 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
//
// Major Functions: YCbCr to RGB Color Doamin Converter.
// ( 10 Bits Resolution )
//
// ============================================================================
//
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Chen :| 05/09/05 :| Initial Revision
// V2.0 :| Peli Li :| 04/19/2010 :| revised the megacore instance
// ============================================================================
module YCbCr2RGB ( Red,Green,Blue,oDVAL,
iY,iCb,iCr,iDVAL,
iRESET,iCLK);
// Input
input [7:0] iY,iCb,iCr;
input iDVAL,iRESET,iCLK;
wire iCLK;
// Output
output [9:0] Red,Green,Blue;
output reg oDVAL;
// Internal Registers/Wires
reg [9:0] oRed,oGreen,oBlue;
reg [3:0] oDVAL_d;
reg [19:0] X_OUT,Y_OUT,Z_OUT;
wire [26:0] X,Y,Z;
assign Red = oRed;
assign Green= oGreen;
assign Blue = oBlue;
always@(posedge iCLK)
begin
if(iRESET)
begin
oDVAL<=0;
oDVAL_d<=0;
oRed<=0;
oGreen<=0;
oBlue<=0;
end
else
begin
// Red
if(X_OUT[19])
oRed<=0;
else if(X_OUT[18:0]>1023)
oRed<=1023;
else
oRed<=X_OUT[9:0];
// Green
if(Y_OUT[19])
oGreen<=0;
else if(Y_OUT[18:0]>1023)
oGreen<=1023;
else
oGreen<=Y_OUT[9:0];
// Blue
if(Z_OUT[19])
oBlue<=0;
else if(Z_OUT[18:0]>1023)
oBlue<=1023;
else
oBlue<=Z_OUT[9:0];
// Control
{oDVAL,oDVAL_d}<={oDVAL_d,iDVAL};
end
end
always@(posedge iCLK)
begin
if(iRESET)
begin
X_OUT<=0;
Y_OUT<=0;
Z_OUT<=0;
end
else
begin
X_OUT<=( X - 114131 ) >>7;
Y_OUT<=( Y + 69370 ) >>7;
Z_OUT<=( Z - 141787 ) >>7;
end
end
// Y 596, 0, 817
MAC_3 u0(
.aclr0(iRESET),
.clock0(iCLK),
.dataa_0(iY),
.dataa_1(iCb),
.dataa_2(iCr),
.datab_0(17'h00254),
.datab_1(17'h00000),
.datab_2(17'h00331),
.result(X)
);
//MAC_3 u0( iRESET, iCLK,iY, iCb, iCr,
// 17'h00254, 17'h00000, 17'h00331,
// X);
// Cb 596, -200, -416
MAC_3 u1(
.aclr0(iRESET),
.clock0(iCLK),
.dataa_0(iY),
.dataa_1(iCb),
.dataa_2(iCr),
.datab_0(17'h00254),
.datab_1(17'h3FF38),
.datab_2(17'h3FE60),
.result(Y)
);
//MAC_3 u1( iRESET, iCLK,iY, iCb, iCr,
// 17'h00254, 17'h3FF38, 17'h3FE60,
// Y );
// Cr 596, 1033, 0
MAC_3 u2(
.aclr0(iRESET),
.clock0(iCLK),
.dataa_0(iY),
.dataa_1(iCb),
.dataa_2(iCr),
.datab_0(17'h00254),
.datab_1(17'h00409),
.datab_2(17'h00000),
.result(Z)
);
//MAC_3 u2( iRESET, iCLK,iY, iCb, iCr,
// 17'h00254, 17'h00409, 17'h00000,
// Z );
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, M; char A[2020][2020]; int B[2020][2020]; int D[2020][2020]; queue<int> qx; queue<int> qy; int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; long long ans; int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= N; i++) { scanf( %s , A[i] + 1); } ans = N * M; for (int i = 2; i < N; i++) { for (int j = 2; j < M; j++) { B[i][j] = 1; for (int d = 0; d < 4; d++) { if (A[i][j] != A[i + dx[d]][j + dy[d]]) B[i][j] = 0; } } } for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) { if (B[i][j]) { int c = 0; for (int d = 0; d < 4; d++) { c += B[i + dx[d]][j + dy[d]]; } if (c < 4) { D[i][j] = 1; qx.push(i); qy.push(j); } } } } while (qx.size()) { int x = qx.front(); qx.pop(); int y = qy.front(); qy.pop(); for (int i = 0; i < 4; i++) { int nx = x + dx[i], ny = y + dy[i]; if (!B[nx][ny] || D[nx][ny]) continue; D[nx][ny] = D[x][y] + 1; qx.push(nx); qy.push(ny); } } for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) ans += D[i][j]; printf( %lld n , ans); return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// Module Name: PWM_gen
// Description: This IP expects 100 MHz input clock and generates the desired output
// at PWM output with the configurable frequency (in Hz) and duty cycle.
//
// The configurable frequency should be less or equal to 100 MHz and
// the duty cycle can vary in step of 1/1024, i.e. 0. or
// approximately 0.1%
//////////////////////////////////////////////////////////////////////////////////
module PWM_gen (
input wire clk,
input wire reset,
input [31:0] freq,
input [9:0] duty,
output reg PWM
);
wire [31:0] count_max = 100_000_000 / freq;
wire [31:0] count_duty = count_max * duty / 1024;
reg [31:0] count;
always @(posedge clk, posedge reset) begin
if (reset) begin
count <= 0;
PWM <= 0;
end else if (count < count_max) begin
count <= count + 1;
if(count < count_duty)
PWM <= 1;
else
PWM <= 0;
end else begin
count <= 0;
PWM <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-7; const int MX = 1111 * 1111 * 2; int n, m; const double pi = acos(-1.0); int len, res[MX], mx; struct Complex { double r, i; Complex(double r = 0, double i = 0) : r(r), i(i){}; Complex operator+(const Complex &rhs) { return Complex(r + rhs.r, i + rhs.i); } Complex operator-(const Complex &rhs) { return Complex(r - rhs.r, i - rhs.i); } Complex operator*(const Complex &rhs) { return Complex(r * rhs.r - i * rhs.i, i * rhs.r + r * rhs.i); } } va[MX], vb[MX], ve[MX], vc[MX]; void rader(Complex F[], int len) { int j = len >> 1; for (int i = 1; i < len - 1; ++i) { if (i < j) swap(F[i], F[j]); int k = len >> 1; while (j >= k) { j -= k; k >>= 1; } if (j < k) j += k; } } void FFT(Complex F[], int len, int t) { rader(F, len); for (int h = 2; h <= len; h <<= 1) { Complex wn(cos(-t * 2 * pi / h), sin(-t * 2 * pi / h)); for (int j = 0; j < len; j += h) { Complex E(1, 0); for (int k = j; k < j + h / 2; ++k) { Complex u = F[k]; Complex v = E * F[k + h / 2]; F[k] = u + v; F[k + h / 2] = u - v; E = E * wn; } } } if (t == -1) for (int i = 0; i < len; ++i) F[i].r /= len; } void Conv(Complex a[], Complex b[], int len) { FFT(a, len, 1); FFT(b, len, 1); for (int i = 0; i < len; ++i) a[i] = a[i] * b[i]; FFT(a, len, -1); for (int i = 0; i < len; ++i) a[i].r = (a[i].r > 0.5); } void init(Complex *a, Complex *b) { for (int i = 0; i < len; i++) a[i].i = 0, a[i].r = b[i].r; } void _init(Complex *a) { for (int i = 0; i < len; i++) a[i].i = 0; } void Out(int a) { if (a > 9) Out(a / 10); putchar(a % 10 + 0 ); } void print(Complex *a) { for (int i = 0; i < len; i++) printf( %d , (int)(a[i].r + 0.5)); cout << endl; } void gao() { len = 1; while (len < mx) len <<= 1; ve[0].r = 1; while (m) { if (m & 1) { init(vc, va); Conv(ve, va, len); _init(ve); init(va, vc); if (m == 1) break; } init(vb, va); Conv(va, vb, len); _init(va); m >>= 1; } for (int i = 0; i < len; ++i) res[i] = ve[i].r + 0.5; for (int i = 0; i < len; i++) if (res[i]) Out(i), putchar( ); cout << endl; } int main() { while (cin >> n >> m) { int maxn = 0; for (int i = 0; i < n; i++) { int x; scanf( %d , &x); maxn = max(maxn, x); va[x].r = 1; va[x].i = 0; } mx = maxn * m + 1; gao(); } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int getint() { static char c; while ((c = getchar()) < 0 || c > 9 ) ; int res = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) res = res * 10 + c - 0 ; return res; } const int MaxN = 200000; int n; int col[MaxN + 1]; struct state { int x, l; state() {} state(const int &_x, const int &_l) : x(_x), l(_l) {} friend inline bool operator<(const state &lhs, const state &rhs) { if (lhs.x != rhs.x) return lhs.x < rhs.x; return lhs.l < rhs.l; } }; state lower[MaxN + 1], upper[MaxN + 1]; int used[MaxN + 1]; int main() { n = getint(); for (int i = 1; i <= n; ++i) col[i] = getint(); if (col[1] > 1) { printf( -1 n ); return 0; } lower[1] = state(1, 1); upper[1] = state(1, 1); for (int i = 2; i <= n; ++i) { lower[i] = lower[i - 1]; if (++lower[i].l > 5) ++lower[i].x, lower[i].l = 1; upper[i] = upper[i - 1]; if (++upper[i].l > 2) ++upper[i].x, upper[i].l = 1; if (col[i] > 0) { state l(col[i], 1); state r(col[i], 5); lower[i] = max(lower[i], l); upper[i] = min(upper[i], r); if (lower[i].x > col[i] || upper[i].x < col[i]) { printf( -1 n ); return 0; } } } state res = upper[n]; if (res.l == 1) res.l = 5, --res.x; if (res < lower[n]) { printf( -1 n ); return 0; } used[col[n] = res.x] = 1; for (int i = n - 1; i >= 1; --i) { col[i] = min(col[i + 1], upper[i].x); col[i] -= used[col[i]] == 5; ++used[col[i]]; } printf( %d n , res.x); for (int i = 1; i <= n; ++i) printf( %d , col[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; const long long int inf = 2e9 + 5; double PI = 3.14159265358979323846; void solve() { int n; cin >> n; int x = (int)sqrt(n); int best = inf; for (int i = max(1, x - 2); i <= x + 2; i++) { for (int j = max(1, x - 2); j <= x + 2; j++) { if (i * j >= n) { best = min(best, i + j - 2); } } } cout << best << n ; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T; cin >> T; while (T--) solve(); return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Inverse_Park_Transform.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Inverse_Park_Transform
// Source Path: velocityControlHdl/Transform_dq_to_ABC/Inverse_Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Inverse_Park_Transform
(
direct_voltage,
quadrature_voltage,
sin_coefficient,
cos_coefficient,
alpha_voltage,
beta_voltage
);
input signed [17:0] direct_voltage; // sfix18_En12
input signed [17:0] quadrature_voltage; // sfix18_En12
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
output signed [17:0] alpha_voltage; // sfix18_En10
output signed [17:0] beta_voltage; // sfix18_En10
wire signed [35:0] Product2_out1; // sfix36_En28
wire signed [35:0] Product3_out1; // sfix36_En28
wire signed [35:0] alpha_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En10
wire signed [35:0] Product_out1; // sfix36_En28
wire signed [35:0] Product1_out1; // sfix36_En28
wire signed [35:0] beta_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type1_out1; // sfix18_En10
// Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta)
//
// Inverse Park Transform
// <S44>/Product2
assign Product2_out1 = direct_voltage * cos_coefficient;
// <S44>/Product3
assign Product3_out1 = quadrature_voltage * sin_coefficient;
// <S44>/Add1
assign alpha_voltage_1 = Product2_out1 - Product3_out1;
// <S44>/Convert_Data_Type
velocityControlHdl_Convert_Data_Type_block1 u_Convert_Data_Type (.In1(alpha_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type_out1) // sfix18_En10
);
assign alpha_voltage = Convert_Data_Type_out1;
// <S44>/Product
assign Product_out1 = direct_voltage * sin_coefficient;
// <S44>/Product1
assign Product1_out1 = quadrature_voltage * cos_coefficient;
// <S44>/Add
assign beta_voltage_1 = Product_out1 + Product1_out1;
// <S44>/Convert_Data_Type1
velocityControlHdl_Convert_Data_Type1_block1 u_Convert_Data_Type1 (.In1(beta_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type1_out1) // sfix18_En10
);
assign beta_voltage = Convert_Data_Type1_out1;
endmodule // velocityControlHdl_Inverse_Park_Transform
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Internal DMA Control and status register file for PCIE-DDR2 DMA
// design. This register file should only be used for dma transfers
// up to 4KB in size.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module internal_dma_ctrl
(
input clk,
input rst,
//interface from dma_ctrl_status_reg file;
//these inputs could also be directly driven from the host system if desired
//in which case the dma_ctrl_status_reg_file block should be removed from the
//design
input [31:0] reg_data_in,
input [6:0] reg_wr_addr,
input [6:0] reg_rd_addr,
input reg_wren,
output reg [31:0] reg_data_out, //reg_data_out is never used
//DMA parameter control outputs to TX and RX engines
output [63:0] dmaras, //Read address source (from host memory)
output reg [31:0] dmarad, //Read address destination (to backend memory)
output reg [31:0] dmarxs, //Read transfer size in bytes
output rd_dma_start, //read dma start control signal
input rd_dma_done, //read dma done signal from RX engine
//Performance counts from performance counter module
//Not used in this module because the copies in dma_ctrl_status_reg_file
//are used instead
input [31:0] dma_wr_count,
input [31:0] dma_rd_count
);
reg [31:0] dmaras_l, dmaras_u;
reg [31:0] dmacst;
//concatanate to form the 64 bit outputs
assign dmaras[63:0] = {dmaras_u,dmaras_l};
////assign wr_dma_start = dmacst[0];
assign rd_dma_start = dmacst[2];
//block for writing into the regfile
//--when reg_wren is asserted, reg_data_in will be written to one of the
//registers as chosen by reg_wr_addr selection signal
always@(posedge clk or posedge rst) begin
if(rst) begin
dmaras_l <= 0;
dmaras_u <= 0;
dmarad <= 0;
dmarxs <= 0;
end else begin
if(reg_wren) begin
case(reg_wr_addr)
7'b000_1100: dmaras_l <= reg_data_in; //0x0C
7'b001_0000: dmaras_u <= reg_data_in; //0x10
7'b001_0100: dmarad <= reg_data_in; //0x14
7'b001_1100: dmarxs <= reg_data_in; //0x1C
default: begin
dmaras_l <= dmaras_l;
dmaras_u <= dmaras_u;
dmarad <= dmarad;
dmarxs <= dmarxs;
end
endcase
end
end
end
//use a separate always block for dmacst[3:2] for clarity
//dmacst[2] == rd_dma_start; host sets this bit to start a dma transfer
// it is automatically cleared when the
// dma transfer completes
//dmacst[3] == rd_dma_done; asserted when the dma transfer is finished
// this bit can be polled by the host or it could
// be used to drive hardware block to generate
// an interrupt
// this bit must be cleared by the host by
// writing a "1" to it.
always@(posedge clk) begin
if(rst) begin
dmacst[3:2] <= 2'b00;
end else begin
if(rd_dma_done) begin //rd_dma_done from RX Engine
dmacst[2] <= 1'b0;
dmacst[3] <= 1'b1;
end else if(reg_wren) begin
case(reg_wr_addr)
7'b010_1000: begin //0x28
/// Jiansong:
//take care of the unused bits in this always
//block
dmacst[31:4] <= reg_data_in[31:4];
dmacst[1:0] <= reg_data_in[1:0];
//set the start bit if the host writes a 1
//the host cannot clear this bit
if(reg_data_in[2])
dmacst[2] <= 1'b1;
else
dmacst[2] <= dmacst[2];
//clear the done bit if the host writes a 1
//the host cannot set this bit
if(reg_data_in[3])
dmacst[3] <= 1'b0;
else
dmacst[3] <= dmacst[3];
end
default: begin
dmacst[3:2] <= dmacst[3:2];
end
endcase
end
end
end
// output register for cpu
// this is a read of the reg_file
// the case stmt is a mux which selects which reg location
// makes it to the output data bus
// Not used in this design
always@(posedge clk or posedge rst )
begin
if(rst)
begin
reg_data_out <= 0;
end
else
begin
case(reg_rd_addr[6:0])
7'b000_1100: reg_data_out <= dmaras_l;
7'b001_0000: reg_data_out <= dmaras_u;
7'b001_0100: reg_data_out <= dmarad;
7'b001_1100: reg_data_out <= dmarxs;
7'b010_1000: reg_data_out <= dmacst;
7'b011_0000: reg_data_out <= dma_wr_count;
7'b011_0100: reg_data_out <= dma_rd_count;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXBP_PP_SYMBOL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> bool canWin(long long b, long long e) { if (e % 2 == 1) { return b % 2 == 0; } else if (e < 2 * b) { return b % 2 == 1; } else if (e < 4 * b) { return 1; } else { return canWin(b, e / 4); } } bool canLose(long long b, long long e) { if (e < 2 * b) { return 1; } else if (e / 2 % 2 == 1) { return b % 2 == 0; } else if (e < 4 * b) { return b % 2 == 1; } else { return canLose(b, e / 4); } } int main() { int t; scanf( %d , &t); bool canBeWinner, canBeLoser; bool canBeFirst = true; bool canBeSecond = false; for (int i = 0; i < t; i++) { long long b, e; scanf( %lld%lld , &b, &e); bool cWin = canWin(b, e); bool cLose = canLose(b, e); canBeWinner = (canBeFirst && cWin) || (canBeSecond && !cWin); canBeLoser = (canBeFirst && cLose) || (canBeSecond && !cLose); canBeFirst = canBeLoser; canBeSecond = canBeWinner; } printf( %d %d n , canBeWinner, canBeLoser); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int l, r; int p = 0, j = 0, i = 0, len = 0, cnt = 0; while (j < n) { if (a[j] == 0) { cnt++; } while (cnt > k) { if (a[i] == 0) cnt--; i++; } if (j - i + 1 > len) { l = i; r = j; len = j - i + 1; } j++; } cout << len << endl; for (i = 0; i < n; i++) { if (i >= l && i <= r) cout << 1 << ; else cout << a[i] << ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_BEHAVIORAL_V |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_data_pipeline
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The TX Data pipeline module takes arbitrarily 32-bit aligned data
// from the WR_TX_DATA interface and shifts the data so that it is 0-bit
// aligned. This data is presented on a set of N fifos, where N =
// (C_DATA_WIDTH/32). Each fifo provides it's own VALID signal and is
// controlled by a READY signal. Each fifo also provides an independent DATA bus
// and additional END_FLAG signal which inidicates that the dword provided in this
// fifo is the last dword in the current payload. The START_FLAG signal indicates
// that the dword at index N = 0 is the start of a new packet.
//
// The TX Data Pipeline is built from two modules: tx_data_shift.v and
// tx_data_fifo.v. See these modules for more information.
//
// Author: Dustin Richmond (@darichmond)
//----------------------------------------------------------------------------
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_data_pipeline
#(
parameter C_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD = 256,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: WR TX DATA
input WR_TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
input WR_TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
output WR_TX_DATA_READY,
// Interface: TX DATA FIFOS
input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID
);
`include "functions.vh"
wire wRdTxDataValid;
wire wRdTxDataReady;
wire wRdTxDataStartFlag;
wire [C_DATA_WIDTH-1:0] wRdTxData;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
tx_data_shift
#(
.C_PIPELINE_OUTPUT (0),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_VENDOR (C_VENDOR))
tx_shift_inst
(
// Outputs
.WR_TX_DATA_READY (WR_TX_DATA_READY),
.RD_TX_DATA (wRdTxData),
.RD_TX_DATA_VALID (wRdTxDataValid),
.RD_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.RD_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.RD_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
// Inputs
.WR_TX_DATA (WR_TX_DATA[C_DATA_WIDTH-1:0]),
.WR_TX_DATA_VALID (WR_TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (WR_TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (WR_TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_READY (wRdTxDataReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Data Fifo
tx_data_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_PIPELINE_INPUT (1),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD (C_MAX_PAYLOAD),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH))
txdf_inst
(
// Outputs
.WR_TX_DATA_READY (wRdTxDataReady),
.RD_TX_DATA (RD_TX_DATA[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_START_FLAG (RD_TX_DATA_START_FLAG),
.RD_TX_DATA_WORD_VALID (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_END_FLAGS (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]),
// Inputs
.WR_TX_DATA (wRdTxData),
.WR_TX_DATA_VALID (wRdTxDataValid),
.WR_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.WR_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.WR_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
.RD_TX_DATA_WORD_READY (RD_TX_DATA_WORD_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
#include <bits/stdc++.h> using namespace std; const int modd = 998244353; const int maxn = 2000 + 10; int n, k; long long dp[maxn][maxn][4]; void solve() { dp[1][1][0] = dp[1][1][3] = 1; dp[1][2][1] = dp[1][2][2] = 1; for (int i = 2; i <= n; i++) { dp[i][1][0] = dp[i][1][3] = 1; dp[i][1][1] = dp[i][1][2] = 0; for (int j = 2; j <= k; j++) { dp[i][j][0] = (dp[i - 1][j][0] % modd + dp[i - 1][j][1] % modd + dp[i - 1][j][2] % modd + dp[i - 1][j - 1][3] % modd) % modd; dp[i][j][1] = (dp[i - 1][j - 1][0] % modd + dp[i - 1][j][1] % modd + dp[i - 1][j - 2][2] % modd + dp[i - 1][j - 1][3] % modd) % modd; dp[i][j][2] = (dp[i - 1][j - 1][0] % modd + dp[i - 1][j - 2][1] % modd + dp[i - 1][j][2] % modd + dp[i - 1][j - 1][3] % modd) % modd; dp[i][j][3] = (dp[i - 1][j - 1][0] % modd + dp[i - 1][j][1] % modd + dp[i - 1][j][2] % modd + dp[i - 1][j][3] % modd) % modd; } } } int main() { cin >> n >> k; solve(); cout << (dp[n][k][0] % modd + dp[n][k][1] % modd + dp[n][k][2] % modd + dp[n][k][3] % modd) % modd << endl; } |
/* Karmanye vadhikaraste Ma Phaleshu Kadachana | Ma Karmaphalaheturbhurma Te Sangostvakarmani ||*/ //----------------------------------------------------------------------------------------------------------------// /* this is begining have to survive more and go through long journey*/ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #include<bits/stdc++.h> using namespace std; #define pb push_back #define vi vector<int> #define vii vector<vi> #define vll vector<long long> #define mx(v) *max_element(v.begin(),v.end()) #define mn(v) *min_element(v.begin(),v.end()) #define st(v) sort(v.begin(),v.end()) #define bg .begin() #define ed .end() #define fi first #define sc second #define fr(i,l,u) for(i=l;i<u;i++) #define rfr(i,l,u) for(i=l;i>u;i--) #define ll long long int #define lld long long double #define uld unsigned long long int #define pii pair<int,int> #define flash ios_base::sync_with_stdio(0);cin.tie(NULL); #define mod 1000000007 void solve() { ll n,i,x,sum=0,rem=0; cin>>n; vi v; fr(i,0,n) { cin>>x; sum+=x; } rem=sum%n; cout<<(n-rem)*rem<<endl; } int main() { int t; cin>>t; while(t--) solve(); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0]==0 ? 3'd0
: crc[1:0]==0 ? 3'd1
: crc[1:0]==0 ? 3'd2 : 3'd4);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [2:0] in;
output reg [31:0] out;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100002; int n, m, ok[N], a, b, c, l[N], nr[N]; vector<pair<int, int>> G[N]; int p[20][N]; void parentDFS(int x, int par) { p[0][x] = par; l[x] = l[par] + 1; for (auto it : G[x]) if (it.first != par) parentDFS(it.first, x); } int lca(int x, int y) { if (l[x] < l[y]) swap(x, y); for (int i = 0; i < 18; i++) if (((l[x] - l[y]) & (1 << i))) x = p[i][x]; if (x == y) return x; for (int i = 17; i >= 0; i--) if (p[i][x] != p[i][y]) { x = p[i][x]; y = p[i][y]; } return p[0][x]; } pair<int, int> dist[N], ans[N]; pair<int, int> maxx(pair<int, int> a, pair<int, int> b, int nod) { if (a.first < 0) return b; if (b.first < 0) return a; if (a.first == b.first) return {a.first, nod}; else return max(a, b); } void dfs1(int x, int p) { if (ok[x]) { dist[x] = {0, x}; } else dist[x] = {-1e9, -1}; for (auto it : G[x]) { int u = it.first, c = it.second; if (u == p) continue; dfs1(u, x); dist[x] = maxx(dist[x], {dist[u].first + c, dist[u].second}, x); } } void dfs2(int x, int par, pair<int, int> sus) { ans[x] = maxx(sus, dist[x], x); if (ok[x]) { int t = ans[x].second; int L = lca(x, t); nr[x]++; nr[t]++; nr[L]--; if (p[0][L] != 0) nr[p[0][L]]--; } pair<int, int> aux; if (ok[x]) aux = {0, x}; else aux = {-1e9, -1}; vector<pair<int, int>> child; vector<pair<int, int>> pr; int j = 0; for (auto it : G[x]) if (it.first != par) child.push_back(it); for (auto it : child) { int u = it.first, c = it.second; pr.push_back(aux); aux = maxx(aux, {dist[u].first + c, dist[u].second}, x); } for (int i = child.size() - 1; i >= 0; i--) { int u = child[i].first; int c = child[i].second; pair<int, int> aux1 = maxx(sus, pr[i], x); aux1.first += c; dfs2(u, x, aux1); sus = maxx(sus, {dist[u].first + c, dist[u].second}, x); } } void mars(int x, int p) { for (auto it : G[x]) { int u = it.first; if (u == p) continue; mars(u, x); } nr[p] += nr[x]; } int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> a; ok[a] = 1; } for (int i = 1; i < n; i++) { cin >> a >> b >> c; G[a].push_back({b, c}); G[b].push_back({a, c}); } parentDFS(1, 0); for (int i = 1; i < 18; i++) for (int j = 1; j <= n; j++) p[i][j] = p[i - 1][p[i - 1][j]]; dfs1(1, 0); dfs2(1, 0, {-1e9, -1}); mars(1, 0); int r = 0, sol = 0; for (int i = 1; i <= n; i++) { if (!ok[i]) { if (sol < nr[i]) { sol = nr[i]; r = 1; } else if (sol == nr[i]) r++; } } cout << sol << << r; return 0; } |
#include <bits/stdc++.h> using namespace std; long long f[105], g[105][2], q[105], t, n; int main() { f[1] = 1; f[2] = 2; for (int i = 3; i <= 86; ++i) f[i] = f[i - 1] + f[i - 2]; int cases; for (scanf( %d , &cases); cases--;) { scanf( %I64d , &n); t = 0; for (int i = 86; i; --i) if (f[i] <= n) q[++t] = i, n -= f[i]; g[t][0] = 1; g[t][1] = (q[t] - 1) >> 1; for (int i = t - 1; i; --i) { g[i][0] = g[i + 1][0] + g[i + 1][1]; int l = q[i] - q[i + 1] - 1; g[i][1] = (l >> 1) * g[i + 1][0] + ((l + 1) >> 1) * g[i + 1][1]; } printf( %I64d n , g[1][0] + g[1][1]); } return 0; } |
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module ram(
input clk,
input enable,
input write_enable,
input [WIDTH-1 : 0] addr,
input [WIDTH-1 : 0] data_in,
output [WIDTH-1 : 0] data_out);
parameter ADDRESS_WIDTH = 4;
parameter WIDTH = 8;
parameter MEMORY_SIZE = 1 << ADDRESS_WIDTH;
reg [WIDTH-1 : 0] mem [0 : MEMORY_SIZE-1];
initial begin
`ifdef IVERILOG_SIM
$readmemb(`TEST_PROG, mem);
`else
$readmemb("prog_fib.list", mem);
`endif
end
assign data_out = (enable) ? mem[addr] : {WIDTH{1'b0}};
always @(posedge clk) begin
if (write_enable) begin
mem[addr] <= data_in;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_pipe_misc.v
// Version : 1.11
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; bool t = false; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) t = true, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 48, ch = getchar(); return t ? -x : x; } int n, Q, lans; struct Line { int v, next, w; } e[100100 << 1]; int h[100100], cnt = 1; inline void Add(int u, int v, int w) { e[cnt] = (Line){v, h[u], w}; h[u] = cnt++; } struct Tree { int rt, p[19][100100], dfn[100100], low[100100], ln[100100], md[100100], dep[100100], tim; void dfs(int u, int ff) { p[0][u] = ff; ln[dfn[u] = ++tim] = u; md[u] = dep[u]; for (int i = 1; i < 19; ++i) p[i][u] = p[i - 1][p[i - 1][u]]; for (int i = h[u]; i; i = e[i].next) { int v = e[i].v; if (v == ff) continue; dep[v] = dep[u] + e[i].w; dfs(v, u); md[u] = max(md[u], md[v]); } low[u] = tim; } pair<int, int> mx[100100 << 2]; int tag[100100 << 2]; void pushup(int now) { mx[now] = max(mx[(now << 1)], mx[(now << 1 | 1)]); } void Build(int now, int l, int r) { if (l == r) { mx[now] = make_pair(dep[ln[l]], ln[l]); return; } int mid = (l + r) >> 1; Build((now << 1), l, mid); Build((now << 1 | 1), mid + 1, r); pushup(now); } void Modify(int now, int l, int r, int L, int R, int w) { if (L <= l && r <= R) { mx[now].first += w; tag[now] += w; return; } int mid = (l + r) >> 1; if (L <= mid) Modify((now << 1), l, mid, L, R, w); if (R > mid) Modify((now << 1 | 1), mid + 1, r, L, R, w); pushup(now); mx[now].first += tag[now]; } int ans[100100], vis[100100]; void pre(int _rt) { rt = _rt; dfs(rt, 0); Build(1, 1, n); for (int i = 2; i <= n; ++i) { ans[i] = ans[i - 1] + mx[1].first; for (int j = mx[1].second; j && !vis[j]; j = p[0][j]) vis[j] = i, Modify(1, 1, n, dfn[j], low[j], dep[p[0][j]] - dep[j]); } } int Solve(int x, int y) { y = min(y, n); if (vis[x] <= y) return ans[y]; int u = x; for (int i = 18; ~i; --i) if (vis[p[i][x]] > y) x = p[i][x]; x = p[0][x]; return ans[y] + md[u] - dep[x] - min(dep[x], min(ans[y] - ans[y - 1], md[x] - dep[x])); } } T1, T2; int mx, rt; void dfs(int u, int ff, int dep) { if (dep > mx) mx = dep, rt = u; for (int i = h[u]; i; i = e[i].next) if (e[i].v != ff) dfs(e[i].v, u, dep + e[i].w); } int main() { n = read(); Q = read(); for (int i = 1, u, v, w; i < n; ++i) u = read(), v = read(), w = read(), Add(u, v, w), Add(v, u, w); mx = 0; dfs(1, 0, 0); T1.pre(rt); while (Q--) { int u = (read() + lans - 1) % n + 1, v = (read() + lans - 1) % n + 1; printf( %d n , lans = T1.Solve(u, v << 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, string> > vc[100010]; vector<string> vc1[100010]; bool comp(pair<int, string> a, pair<int, string> b) { return a.first > b.first; } int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { string s; int a, b; cin >> s >> a >> b; vc[a].push_back(make_pair(b, s)); } for (int i = 1; i <= m; i++) { sort(vc[i].begin(), vc[i].end(), comp); } for (int i = 1; i <= m; i++) { if (vc[i].size() == 2) { for (int j = 0; j < vc[i].size(); j++) { vc1[i].push_back(vc[i][j].second); } } else if (vc[i].size() == 1) { for (int j = 0; j < vc[i].size(); j++) { vc1[i].push_back(vc[i][j].second); } } else if (vc[i].size() > 2) { if (vc[i][1].first == vc[i][2].first) { vc1[i].push_back( ? ); } else { for (int j = 0; j < 2; j++) { vc1[i].push_back(vc[i][j].second); } } } } for (int i = 1; i <= m; i++) { for (int j = 0; j < vc1[i].size(); j++) { cout << vc1[i][j]; if (j < vc1[i].size() - 1) cout << ; } cout << endl; } } |
module ball_control(
input clock, reset, load, enable, floor,
input [5:0] radius,
input [9:0] load_x, load_y,
input [3:0] s_x, s_y,
input [5:0] seed,
input bd_p, bd_bl,
input [1:0] bd_di,
output reg [9:0] x, y,
output dead
);
`include "def.v"
wire rstx, rsty;
wire [UBIT-1:0] cntx, cnty;
wire [31:0] rnum;
reg di_x, di_y;
reg [5:0] ang_x, ang_y;
wire [5:0] next_ang_x, next_ang_y;
assign rstx = reset || cntx*ang_x >= UNIT;
assign rsty = reset || cnty*ang_y >= UNIT;
assign bd = bd_p | bd_bl;
counter #(UBIT) cnt0(clock, rstx, enable, cntx);
counter #(UBIT) cnt1(clock, rsty, enable, cnty);
rand rnd(clock, reset, rnum);
// Ball moving
always @(posedge clock)
begin
if (reset) begin
x <= LEFT+MAXX;
y <= TOP+MAXY;
end else if (load) begin
x <= load_x;
y <= load_y;
end else if (enable) begin
if (rstx) begin
if (di_x)
x <= x-1;
else
x <= x+1;
end
if (rsty) begin
if (di_y)
y <= y-1;
else
y <= y+1;
end
end
end
// Ball bouncing
always @(posedge clock)
begin
if (reset) begin
di_x <= 1'b0;
di_y <= 1'b0;
end else if (enable) begin
if (bd) begin
case (bd_di)
B_UP: di_y <= 1'b1;
B_RIGHT: di_x <= 1'b0;
B_DOWN: di_y <= 1'b0;
B_LEFT: di_x <= 1'b1;
endcase
end
// bounce wall take priority ($note. nonblocking assignment of
// the same variable can be used in the same always block.)
if (LEFT + radius >= x) // bounce left side
di_x <= 1'b0;
else if (x + radius >= LEFT+MAXX) // bounce right side
di_x <= 1'b1;
if (TOP + radius > y) // bounce top side
di_y <= 1'b0;
else if (floor && y + radius >= TOP+MAXY) // bounce down side
di_y <= 1'b1;
end
end
// Ball speeding
always @(posedge clock)
begin
if (reset) begin
ang_x <= rnum[7:4] ? rnum[7:4] : 5;
ang_y <= rnum[11:8] ? rnum[11:8] : 6;
end else if (load) begin
ang_x <= rnum[7:4] + seed ? rnum[7:4] : 5;
ang_y <= rnum[11:8] - seed ? rnum[11:8] : 6;
end else if (enable && bd) begin
if (s_x) ang_x <= next_ang_x ? next_ang_x : ang_x;
if (s_y) ang_y <= next_ang_y ? next_ang_y : ang_y;
end
if (ang_x == 0) ang_x <= 5;
if (ang_y == 0) ang_y <= 6;
end
assign next_ang_x = rnum[1:0] + s_x;
assign next_ang_y = rnum[3:2] + s_y;
assign dead = y >= TOP+MAXY;
endmodule
|
`include "bsg_defines.v"
`include "config_defs.v"
module config_node_bind
#(parameter // node specific parameters
id_p = -1, // unique ID of this node
data_bits_p = -1) // number of bits of configurable register associated with this node
(input clk, // this reflects the destiniation domain clock
input [data_bits_p - 1 : 0] data_o);
logic [data_bits_p - 1 : 0] data_o_r, data_o_n;
logic [data_bits_p - 1 : 0] data_o_ref;
integer probe_file;
integer rt, ch;
integer test_idx = 0;
integer node_id = -1;
integer test_sets = -1;
integer node_id_found = 0;
integer restart_pos; // start position of valid probe reference
integer errors = 0;
initial
begin: initial_open_file
if ($test$plusargs("config-node-bind")) begin
probe_file = $fopen("config_probe.in", "r"); // open config_probe.in file to read
end else begin
probe_file = 0;
end
if (!probe_file) begin
disable initial_open_file;
end
data_o_ref = '0; // just to get rid of Lint warning about never assigning to this variable
ch = $fgetc(probe_file);
while(ch != -1) begin // end of file
if (ch == "#") begin // comments
rt = $ungetc(ch, probe_file);
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(probe_file);
end
end else if (ch == "c") begin // a line giving config_node id
rt = $ungetc(ch, probe_file);
rt = $fscanf(probe_file, "config id: %d\n", node_id);
if (node_id == id_p) begin // found relevant reference data
node_id_found = 1;
rt = $fscanf(probe_file, "test sets: %d\n", test_sets); // a line giving number of test sets for a config_node with that id
restart_pos = $ftell(probe_file); // bookmark the probe_file position
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // a line giving a reference configuration string in binary
break; // to be continued from here
end else begin // invalid patterns
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(probe_file);
end
end
end else begin
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(probe_file);
end
end
ch = $fgetc(probe_file);
end
end
assign data_o_n = data_o;
always @ (posedge clk) begin
data_o_r <= data_o_n;
end
// Since the design is synchronized to posedge of clk, using negedge clk
// here is to allow all flip-flops become stable in the register connected
// to data_o. This might guarantee simulation correct even at gate level,
// when all flip-flops don't necessarily change at the same time.
always @ (negedge clk)
begin: always_check_change
if (probe_file && (node_id_found == 1)) begin
if(test_idx == 0) begin
if (data_o === data_o_ref) begin
$display("\n @time %0d: \t output data_o_%0d\t reset to %b", $time, id_p, data_o);
test_idx += 1;
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // read next reference value
end
end else begin
if (data_o !== data_o_r) begin
$display("\n @time %0d: \t output data_o_%0d\t changed to %b", $time, id_p, data_o);
if (data_o !== data_o_ref) begin
$display("\n @time %0d: \t ERROR output data_o_%0d = %b <-> expected = %b", $time, id_p, data_o, data_o_ref);
errors += 1;
end
test_idx += 1;
if (test_idx == test_sets) begin
if ($test$plusargs("cyclic-test")) begin
rt = $fseek(probe_file, restart_pos, 0); // circulate
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // read next reference value
test_idx = 0;
end
end else begin
rt = $fscanf(probe_file, "reference: %b\n", data_o_ref); // read next reference value
end
end
end
end else begin // probe_file doesn't exist
disable always_check_change;
end
end
final
begin: final_statistics
if (probe_file) begin
if (node_id_found == 1) begin
if (errors != 0) begin
$display("### FAILED: Config node %5d has received at least %0d wrong packet(s)!\n", id_p, errors);
end else begin
$display("### PASSED: Config node %5d is probably working properly.\n", id_p);
end
if (!$test$plusargs("cyclic-test")) begin
if(test_idx == 0) begin
$display("### FAILED: Config node %5d has not reset properly!\n", id_p);
end else if (test_idx < test_sets) begin
$display("### FAILED: Config node %5d has missed at least %0d packet(s)!\n", id_p, test_sets - test_idx);
end else if (test_idx > test_sets) begin
$display("### FAILED: Config node %5d has received at least %0d more packet(s)!\n", id_p, test_idx - test_sets);
end
end
end else begin // config_node having id_p is instantiated but not listed in the probe_file
$display("### WARNING: Config node %5d is detected in design but not listed in the probe file.\n", id_p);
end
$fclose(probe_file);
end else begin
disable final_statistics;
end
end
endmodule
|
/* -----------------------------------------------------------------------
*
* Copyright 2008 Tommy Thorn - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
* Bostom MA 02111-1307, USA; either version 2 of the License, or
* (at your option) any later version; incorporated herein by reference.
*
* -----------------------------------------------------------------------
*/
`timescale 1ns/10ps
module ssram_ctrl
(input wire clock
,input wire reset
,output mem_waitrequest
,input [1:0] mem_id
,input [29:0] mem_address // *word* address
,input mem_read
,input mem_write
,input [31:0] mem_writedata
,input [3:0] mem_writedatamask
,output reg [31:0] mem_readdata
,output reg [1:0] mem_readdataid = 0
,output wire sram_clk
,output reg sram_adsc_n = 1 // controller address status
,output reg sram_adv_n = 1 // burst address advance
,output reg [18:0] sram_a = 0
,output reg [ 3:0] sram_be_n = 1 // byte write enable
,output reg sram_oe_n = 1 // output enable
,output reg sram_we_n = 1 // write enable
,inout wire [ 3:0] sram_dpa // "parity" bits, just extra bits
,inout wire [31:0] sram_dq
,output wire sram_adsp_n // processor address status
,output wire sram_ce1_n // chip enable
,output wire sram_ce2 // chip enable
,output wire sram_ce3_n // chip enable
,output wire sram_gw_n // global write, overrides WE# and BE#
,inout [14:0] FLASH_DQ // FLASH Data bus 15 Bits (0 to 14)
,inout FLASH_DQ15_AM1 // FLASH Data bus Bit 15 or Address A-1
,output [21:0] oFLASH_A // FLASH Address bus 22 Bits
,output oFLASH_WE_N // FLASH Write Enable
,output oFLASH_RST_N // FLASH Reset
,output oFLASH_WP_N // FLASH Write Protect /Programming Acceleration
,input iFLASH_RY_N // FLASH Ready/Busy output
,output oFLASH_BYTE_N // FLASH Byte/Word Mode Configuration
,output oFLASH_OE_N // FLASH Output Enable
,output oFLASH_CE_N // FLASH Chip Enable
);
parameter burst_bits = 2;
parameter need_wait = 0;
parameter burst_length = 3'd1 << burst_bits;
/* Flash timing parameters */
parameter tACC = 7'd90; // ns
parameter tCYCLE = 7'd20; // ns XXX pass in from outside!!
/* Fixed SSRAM outputs */
assign sram_clk = clock; // XXX, should be phase shifted (tested and it works but requires a rework of the logic that I don't have time for)
assign sram_adsp_n = 1; // we use adsc#
assign sram_gw_n = 1; // don't use global write
assign sram_ce1_n = 0; // chip enable
assign sram_ce2 = 1; // chip enable
assign sram_ce3_n = 0; // chip enable
reg [31:0] sram_dout;
reg sram_dout_en = 0;
// assign sram_dpa = sram_dout_en ? sram_dpa_out : 'hZ;
assign sram_dq = sram_dout_en ? sram_dout : 'hZ;
/* DE2-70 Flash RAM, 8 MiB = #80_0000
* Accessible at #B000_0000 - #B07F_FFFF
* Mirrored at #B080_0000 - #B07F_FFFF
* ...
* #BF80_0000 - #BF7F_FFFF
* Tinymon starts at #BFC0_0000, thus offset by
* #40_0000 bytes, that is, #20_0000 wydes.
*/
reg [ 1:0] flash_id = 2'd0;
reg [21:0] flash_address = 22'd0;
reg [31:0] flash_data = 0;
wire [15:0] flash_data_in;
wire flash_data_out = 1'd0;
reg flash_data_out_en= 1'd0;
parameter FLASH_DELAY_MSB = 7; // [-128; 127] more than enough
reg [FLASH_DELAY_MSB:0]
flash_delay = 1'd0;
assign {FLASH_DQ15_AM1,FLASH_DQ}
= flash_data_out_en ? flash_data_out : 16'hZZ;
assign flash_data_in = {FLASH_DQ15_AM1,FLASH_DQ};
assign oFLASH_A = flash_address;
assign oFLASH_CE_N = 0;
assign oFLASH_OE_N = 0;
assign oFLASH_WE_N = 1;
assign oFLASH_RST_N = 1;
assign oFLASH_WP_N = 0; // doesn't matter
assign oFLASH_BYTE_N = 1;
parameter S_IDLE = 0;
parameter S_READWAIT = 1;
parameter S_READ_BURST = 2;
parameter S_WRITE1 = 3;
parameter S_WRITE2 = 4;
parameter S_READ_FLASH = 5;
reg [ 5:0] state = S_IDLE;
reg [burst_bits:0] cnt = 0;
reg [ 1:0] pendingid = 0;
reg [ 1:0] pendingid2 = 0;
reg [ 1:0] readdataid = 0;
assign mem_waitrequest = state != S_IDLE ||
mem_write && pendingid2;
/*
* NOTE: It is important that sram_dout_en be (redundantly)
* assigned in every state to insure that the enable is packed into
* the IO buffer. Credit to Martin Schoeberl for finding this
* obscure fact.
*/
/*
Assuming ADSP_N = 1, CE_N = 0, etc and OE_N = 0 for reads
ADSC_N ADV_N WRITE_N
0 X 0 begin burst WRITE
0 X 1 begin burst READ
1 0 0 continue burst WRITE
1 0 1 continue burst READ
6. For a WRITE operation following a READ operation, OE must be
HIGH before the input data setup time and held HIGH during the
input data hold time.
XXX For proper operation, we need a PLL to phase shift the
external SRAM clock, but for 50 MHz we might be able to get away
with a less ideal solution.
*/
/* Read data follows two cycles behind the read command */
always @(posedge clock) begin
if (reset) begin
mem_readdataid <= 0;
readdataid <= 0;
pendingid2 <= 0;
state <= S_IDLE;
end else begin
mem_readdata <= sram_dq;
mem_readdataid <= readdataid;
readdataid <= pendingid2;
pendingid2 <= pendingid;
end
/* Set up default values so that writes below are one-shot */
sram_adsc_n <= 1;
sram_be_n <= 15;
sram_we_n <= 1;
sram_adv_n <= 1;
case (state)
S_IDLE:
if (mem_read && mem_address[29:26] == 4'hB) begin
/* Reading from Flash */
// byte address 16-byte aligned == {a[:4],4'd0}
// word address 16-byte aligned == {a[:2],4'd0}
// as wyde address == {a[:2],3'd0}
flash_address <= {mem_address[20:2],3'd0};
flash_delay <= (tACC + tCYCLE - 1'd1) / tCYCLE - 1'd1;
flash_id <= mem_id;
pendingid <= 0; // Too be safe
state <= S_READ_FLASH;
end else if (mem_read) begin
sram_a <= mem_address[18:0];
sram_adsc_n <= 0;
sram_dout_en <= 0;
sram_oe_n <= 0;
pendingid <= mem_id;
cnt <= burst_length - 2'd3; // 1
state <= S_READ_BURST;
end else if (mem_write && !pendingid2) begin
// sram_oe_n == 1
sram_a <= mem_address[18:0];
sram_adsc_n <= 0;
sram_dout_en <= 1;
sram_dout <= mem_writedata;
sram_be_n <= ~mem_writedatamask;
sram_we_n <= 0;
sram_oe_n <= 1 /*pendingid2 == 0*/;
pendingid <= 0;
end else begin
pendingid <= 0;
sram_dout_en <= 0;
end
S_READ_BURST: begin
// Burst reading: assert ADV# for three cycles
// cnt = 1, 0, -1
sram_adv_n <= 0;
sram_dout_en <= 0;
cnt <= cnt - 1'd1;
if (cnt[burst_bits])
state <= S_IDLE;
end
S_READWAIT: begin
state <= S_IDLE;
sram_dout_en <= 0;
end
S_WRITE1: begin
sram_dout_en <= 1;
sram_we_n <= 1;
state <= S_IDLE;
end
S_WRITE2: begin
sram_dout_en <= 1;
sram_we_n <= 1;
state <= S_IDLE;
end
S_READ_FLASH: begin
if (!flash_delay[FLASH_DELAY_MSB])
flash_delay <= flash_delay - 1'd1;
else begin
/* Readout the data. Notice that Terasic's control panel
stores the wydes in little endian, but YARI is
currently bigendian, thus a 76543210 word would be
stored in two wydes like 5476 1032.
We accumulate the read data in flash_data and copy it to mem_readdata.
*/
flash_data <= {flash_data[15:0], flash_data_in[7:0], flash_data_in[15:8]};
mem_readdata <= {flash_data[15:0], flash_data_in[7:0], flash_data_in[15:8]};
flash_address <= flash_address + 1'd1;
/* Every other read is a full word */
mem_readdataid <= flash_address[0] ? flash_id : 2'd0;
/* Every 4th read takes a while (XXX actually faster reads not implemented yet) */
flash_delay <= (tACC + tCYCLE - 1'd1) / tCYCLE - 1'd1;
if (flash_address[2:0] == 7)
state <= S_IDLE;
end
end
endcase
end
endmodule
|
`timescale 1ns/1ps
module VGA_Controlador(
input wire _clk_,
input wire _reset_,
output reg hsync,
output reg vsync,
output reg [10:0] PixelX,
output reg [10:0] PixelY,
output reg video_encendido
);
parameter TotalHorizontalPixels = 11'd800;
parameter HorizontalSyncWidth = 11'd96;
parameter VerticalSyncWidth = 11'd2;
parameter TotalVerticalLines = 11'd525;
parameter HorizontalBackPorchTime = 11'd144 ;
parameter HorizontalFrontPorchTime = 11'd784 ;
parameter VerticalBackPorchTime = 11'd12 ;
parameter VerticalFrontPorchTime = 11'd492;
reg VerticalSyncEnable;
reg [10:0] HorizontalCounter;
reg [10:0] VerticalCounter;
//Counter for the horizontal sync signal
always @(posedge _clk_ or posedge _reset_)
begin
if(_reset_ == 1)
HorizontalCounter <= 0;
else
begin
if(HorizontalCounter == TotalHorizontalPixels - 1)
begin //the counter has hreached the end of a horizontal line
HorizontalCounter<=0;
VerticalSyncEnable <= 1;
end
else
begin
HorizontalCounter<=HorizontalCounter+1;
VerticalSyncEnable <=0;
end
end
end
//Generate the hsync pulse
//Horizontal Sync is low when HorizontalCounter is 0-127
always @(*)
begin
if((HorizontalCounter<HorizontalSyncWidth))
hsync = 1;
else
hsync = 0;
end
//Counter for the vertical sync
always @(posedge _clk_ or posedge _reset_)
begin
if(_reset_ == 1)
VerticalCounter<=0;
else
begin
if(VerticalSyncEnable == 1)
begin
if(VerticalCounter==TotalVerticalLines-1)
VerticalCounter<=0;
else
VerticalCounter<=VerticalCounter+1;
end
end
end
//generate the vsync pulse
always @(*)
begin
if(VerticalCounter < VerticalSyncWidth)
vsync = 1;
else
vsync = 0;
end
always @(posedge _clk_)
begin
if((HorizontalCounter<HorizontalFrontPorchTime) && (HorizontalCounter>HorizontalBackPorchTime) && (VerticalCounter<VerticalFrontPorchTime) && (VerticalCounter>VerticalBackPorchTime))
begin
video_encendido <= 1;
PixelX<= HorizontalCounter - HorizontalBackPorchTime;
PixelY<= VerticalCounter - VerticalBackPorchTime;
end
else
begin
video_encendido <= 0;
PixelX<=0;
PixelY<=0;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_TB_V
`define SKY130_FD_SC_HD__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_TB_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; template <class T> inline void checkmin(T &a, T b) { if (a > b) a = b; } template <class T> inline void checkmax(T &a, T b) { if (a < b) a = b; } const int oo = 1 << 30; const double eps = 1e-7; const int N = 512; const int M = 1; const long long P = 10000000097ll; int sgn(double x) { return (x > eps) - (x < -eps); } int fcmp(double a, double b) { return sgn(a - b); } double sqr(double x) { return x * x; } struct Point { double x, y; Point() {} Point(double a, double b) : x(a), y(b) {} Point operator+(const Point &p) const { return Point(x + p.x, y + p.y); } Point operator-(const Point &p) const { return Point(x - p.x, y - p.y); } Point operator*(double d) const { return Point(x * d, y * d); } double operator*(const Point &p) const { return x * p.y - y * p.x; } Point operator/(double d) const { return Point(x / d, y / d); } double norm() const { return sqrt(x * x + y * y); } Point rot(double alpha) const { return Point(x * cos(alpha) - y * sin(alpha), x * sin(alpha) + y * cos(alpha)); } void cin() { scanf( %lf %lf , &x, &y); } void cout(char *s = p = ) const { printf( %s %f %f , s, x, y); } }; struct Line { Point a, b; Line() {} Line(const Point &p, const Point &q) : a(p), b(q) {} bool para(const Line &lin) const { Point u, v; u = b - a; v = lin.b - lin.a; return sgn(u * v) == 0; } bool l_to_s(const Line &seg) const { return sgn((b - a) * (seg.a - a)) * sgn((b - a) * (seg.b - a)) < 0; } bool s_to_s(const Line &seg) const { return l_to_s(seg) && seg.l_to_s(*this); } Point l_on_l(const Line &lin) const { double s1, s2; s1 = (lin.a - a) * (lin.b - a); s2 = (lin.b - b) * (lin.a - b); return (a * s2 + b * s1) / (s1 + s2); } int l_to_p(const Point &p) const { return sgn((b - a) * (p - a)); } }; Point ar[N][5]; Point br[N][5]; Point tmple[2][N]; Point *x, *y; double h, f; int n; double ans; double area(Point *p, int pn) { int i, j, k; double ans = 0; for (i = 1; i < pn; i++) ans += (p[i] - p[0]) * (p[i + 1] - p[0]); if (pn < -11) { for (i = 0; i < (pn); i++) printf( %.3f %.3f--> , p[i].x, p[i].y); puts( ); } return ans; } void read() { int i, j, k; double a, b; double fix, low; ans = 0; scanf( %d , &n); scanf( %lf %lf , &h, &f); fix = f / (f - h); low = (f + h) / (f - h); for (i = 0; i < (n); i++) { scanf( %lf %lf , &a, &b); ar[i][0] = Point(a * fix, 0); ar[i][1] = Point(b * fix, 0); ar[i][2] = Point(b, h); ar[i][3] = Point(a, h); ar[i][4] = ar[i][0]; br[i][0] = Point(a * fix, 0); br[i][1] = Point(b * fix, 0); br[i][2] = Point(b * low, h); br[i][3] = Point(a * low, h); br[i][4] = br[i][0]; ans += area(ar[i], 4) + area(br[i], 4); } } void cut(Point *p) { int xn, yn; int i, j, k; int ii, jj; Line lin, seg; for (i = 0; i < (n); i++) { for (j = 0; j < (5); j++) x[j] = p[j]; xn = 4; for (j = 0; j < (4); j++) { lin = Line(ar[i][j], ar[i][j + 1]); yn = 0; for (ii = 1; ii <= xn; ii++) { seg = Line(x[ii - 1], x[ii]); if (lin.l_to_s(seg)) y[yn++] = lin.l_on_l(seg); if (lin.l_to_p(x[ii]) >= 0) y[yn++] = x[ii]; } y[yn] = y[0]; swap(x, y); swap(xn, yn); } ans -= area(x, xn); } } void sub() { int i, j, k; x = tmple[0]; y = tmple[1]; for (i = 0; i < (n); i++) cut(br[i]); } int main() { int T, _ = 0; read(); sub(); printf( %.6f n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long int t, temp, i, ans = 0, n, m, index, j; cin >> n >> m; vector<pair<long long int, long long int> > pa; vector<long long int> v(n), finger(m); for (i = 0; i < n; i++) { cin >> v[i]; } for (i = 0; i < m; i++) { cin >> finger[i]; for (j = 0; j < n; j++) { if (v[j] == finger[i]) { pa.push_back(make_pair(j, finger[i])); } } } sort(pa.begin(), pa.end()); if (pa.size() == 0) cout << n ; else { for (auto it = pa.begin(); it != pa.end(); it++) { cout << it->second << ; } } } |
#include <bits/stdc++.h> using namespace ::std; const long long maxn = 5e5 + 500; long long seg[4 * maxn]; long long dp[maxn]; long long q[maxn]; long long houp[maxn]; long long a[maxn]; map<long long, long long> last; map<long long, vector<long long> > las; void bild() { fill(seg, seg + 4 * maxn, -1); } void update(long long L, long long R, long long node, long long l, long long r, long long v) { if (l <= L && R <= r) { seg[node] = max(seg[node], v); return; } if (r <= L || R <= l) { return; } seg[2 * node] = max(seg[2 * node], seg[node]); seg[2 * node + 1] = max(seg[2 * node + 1], seg[node]); long long mid = (L + R) / 2; update(L, mid, 2 * node, l, r, v); update(mid, R, 2 * node + 1, l, r, v); } long long findd(long long L, long long R, long long node, long long x) { long long mid = (L + R) / 2; if (L + 1 == R) { return seg[node]; } if (x < mid) { return max(seg[node], findd(L, mid, 2 * node, x)); } else { return max(seg[node], findd(mid, R, 2 * node + 1, x)); } } int main() { long long n; cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; } bild(); for (long long i = 0; i < n; i++) { long long v = a[i]; if (last.count(v) > 0) { q[i] = findd(0, n, 1, last[v]); update(0, n, 1, last[v] + 1, i, last[v]); } else { q[i] = -1; } last[v] = i; } for (long long i = 0; i < n; i++) { long long v = a[i]; las[v].push_back(i); if (las[v].size() >= 4) { q[i] = max(q[i], las[v][las[v].size() - 4]); } } dp[0] = 0; houp[0] = -1; for (long long i = 1; i < n; i++) { if (q[i] == -1) { houp[i] = -1; dp[i] = dp[i - 1]; } else { if (q[i] == 0) { dp[i] = max(dp[i - 1], 1LL); } else { dp[i] = max(dp[i - 1], 1 + dp[q[i] - 1]); } if (dp[i] == dp[i - 1]) { houp[i] = -1; } else { houp[i] = q[i]; } } } cout << 4 * dp[n - 1] << endl; vector<long long> stk; long long p = n - 1; while (p >= 0) { if (houp[p] == -1) { p--; } else { stk.push_back(a[p]); stk.push_back(a[houp[p]]); stk.push_back(a[p]); stk.push_back(a[houp[p]]); p = houp[p] - 1; } } reverse(stk.begin(), stk.end()); for (long long i = 0; i < stk.size(); i++) { cout << stk[i] << ; } } |
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module GrayCounter
#(parameter COUNTER_WIDTH = 4)
(output reg [COUNTER_WIDTH-1:0] gray_count_out, //'Gray' code count output.
input wire en, //Count enable.
input wire rst, //Count reset.
input wire clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] binary_count;
/////////Code///////////////////////
always @ (posedge clk)
if (rst) begin
binary_count <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
gray_count_out <= {COUNTER_WIDTH{1'b 0}}; // first 'en'.
end
else if (en) begin
binary_count <= binary_count + 1;
gray_count_out <= {binary_count[COUNTER_WIDTH-1],
binary_count[COUNTER_WIDTH-2:0] ^ binary_count[COUNTER_WIDTH-1:1]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1500 + 10; const int INF = 1e9; int ans[MAX_N][26]; int main() { ios::sync_with_stdio(0); int n; cin >> n; string s; cin >> s; for (int it = 0; it < 26; ++it) { char c = char(it + a ); for (int i = 0; i < n; ++i) { int cnt = 0; for (int j = i; j < n; ++j) { if (s[j] != c) cnt++; ans[cnt][it] = max(ans[cnt][it], j - i + 1); } } for (int i = 1; i <= n; ++i) { if (ans[i][it] == 0) { ans[i][it] = ans[i - 1][it]; } } } int q; cin >> q; while (q--) { int k; char c; cin >> k >> c; cout << ans[k][(int)(c - a )] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> g[100005]; int c[100005]; double r[100005]; void dfs(int x) { c[x] = 1; for (int i = 0; i < g[x].size(); ++i) { int y = g[x][i]; dfs(y); c[x] += c[y]; } } void calc(int x) { for (int i = 0; i < g[x].size(); ++i) { int y = g[x][i]; r[y] = r[x] + 1 + (c[x] - c[y] - 1) / 2.; calc(y); } } int main() { scanf( %d , &n); for (int i = 1; i < n; ++i) { int p; scanf( %d , &p); p--; g[p].push_back(i); } dfs(0); r[0] = 1; calc(0); printf( 1.0 ); for (int i = 1; i < n; ++i) printf( %.1lf , r[i]); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; map<int, int> mpp; map<int, int> tmp; multiset<int> adj[200005]; multiset<pair<int, int> > pairs; int cnt[200005]; int arra[100005]; int arrb[100005]; list<int> ans; void addpair(int u, int v) { pairs.insert(make_pair(u, v)); pairs.insert(make_pair(v, u)); } void removepair(int u, int v) { pairs.erase(pairs.find(make_pair(u, v))); pairs.erase(pairs.find(make_pair(v, u))); } int ispair(int u, int v) { if (pairs.find(make_pair(u, v)) == pairs.end()) return 0; return 1; } void bit() { printf( -1 n ); exit(0); } int main() { clock_t start = clock(); scanf( %d , &n); for (int i = 0; i < 2 * n; i++) cnt[i] = 0; for (int i = 0; i < n - 1; i++) { scanf( %d , arra + i); } for (int i = 0; i < n - 1; i++) { scanf( %d , arrb + i); } for (int i = 0; i < n - 1; i++) { int a = arra[i], b = arrb[i]; int ai = i * 2, bi = i * 2 + 1; if (a > b) bit(); if (tmp.count(a)) ai = tmp[a]; else { tmp[a] = ai; mpp[ai] = a; } if (tmp.count(b)) bi = tmp[b]; else { tmp[b] = bi; mpp[bi] = b; } cnt[ai]++; cnt[bi]++; addpair(ai, bi); adj[ai].insert(bi); adj[bi].insert(ai); } int tek1 = -1; int tek2 = -1; for (int i = 0; i < 2 * n; i++) { if (cnt[i] % 2 == 1) { if (tek2 != -1) bit(); else if (tek1 != -1) tek2 = i; else tek1 = i; } } if (tek1 != -1 && tek2 == -1) assert(0); list<int> ans; if (tek1 == -1) { tek1 = 0; } stack<int> st; st.push(tek1); while (!st.empty()) { int node = st.top(); if (adj[node].size() == 0) { ans.push_back(mpp[node]); st.pop(); } else { st.push(*adj[node].begin()); adj[*adj[node].begin()].erase(adj[*adj[node].begin()].find(node)); adj[node].erase(adj[node].begin()); } } for (int i = 0; i < 2 * n; i++) { if (adj[i].size() != 0) bit(); } for (list<int>::iterator it = ans.begin(); it != ans.end(); ++it) { printf( %d , *it); } } |
reg reset;
wire [WIDTH-1:0] data_in_sig;
reg data_in_clock;
wire data_in_enable;
wire data_in_start_sig;
wire data_in_end_sig;
wire [WIDTH-1:0] data_out_sig;
wire data_out_start_sig;
wire data_out_end_sig;
reg data_out_clock;
wire data_out_enable;
fifo #(
.DATA_WIDTH (WIDTH),
.FIFO_DEPTH (DEPTH)
)
ff (
.reset(reset),
// IN PORT
.data_in(data_in_sig),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start_sig),
.data_in_end(data_in_end_sig),
// OUT PORT
.data_out(data_out_sig),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start_sig),
.data_out_end(data_out_end_sig)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
util (
.data_in(),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(clock)
);
utilities #(.OUT_WIDTH (WIDTH),
.IN_WIDTH (WIDTH),
.DEBUG(1))
data_in (
.data_in(),
.data_in_enable(),
.data_out(data_in_sig),
.data_out_enable(data_in_enable),
.clock(data_in_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_in_start (
.data_in(),
.data_in_enable(),
.data_out(data_in_start_sig),
.data_out_enable(),
.clock(data_in_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_in_end (
.data_in(),
.data_in_enable(),
.data_out(data_in_end_sig),
.data_out_enable(),
.clock(data_in_clock)
);
utilities #(.OUT_WIDTH (WIDTH),
.IN_WIDTH (WIDTH),
.DEBUG(1))
data_out (
.data_in(data_out_sig),
.data_in_enable(data_out_enable),
.data_out(),
.data_out_enable(),
.clock(data_out_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_out_start (
.data_in(data_out_start_sig),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(data_out_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_out_end (
.data_in(data_out_end_sig),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(data_out_clock)
);
initial
begin
data_in_clock = 0;
data_out_clock = 0;
reset = 1;
end
always
#5 data_in_clock = ~data_in_clock;
always
#5 data_out_clock = ~data_out_clock;
|
#include <bits/stdc++.h> using namespace std; char x[15]; int main() { scanf( %s , x); int lenx = strlen(x); for (int i = lenx - 1; i >= 0; i--) { int dig = x[i] - 0 ; if (dig == 0) printf( O-|-OOOO n ); else if (dig == 1) printf( O-|O-OOO n ); else if (dig == 2) printf( O-|OO-OO n ); else if (dig == 3) printf( O-|OOO-O n ); else if (dig == 4) printf( O-|OOOO- n ); else if (dig == 5) printf( -O|-OOOO n ); else if (dig == 6) printf( -O|O-OOO n ); else if (dig == 7) printf( -O|OO-OO n ); else if (dig == 8) printf( -O|OOO-O n ); else printf( -O|OOOO- n ); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, a, b, c, d; scanf( %d%d%d%d%d%d , &n, &k, &a, &b, &c, &d); if (n <= 4 || k < n + 1) { puts( -1 ); return 0; } printf( %d %d , a, c); for (int i = 1; i <= n; i++) { if (i != a && i != b && i != c && i != d) printf( %d , i); } printf( %d %d n , d, b); printf( %d %d , c, a); for (int i = 1; i <= n; i++) { if (i != a && i != b && i != c && i != d) printf( %d , i); } printf( %d %d n , b, d); return 0; } |
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433832795; long long int inp() { long long int n = 0, s = 1; char c; for (c = getchar(); c < 48 || c > 58; c = getchar()) if (c == - ) s = -1; for (; c > 47 && c < 59; c = getchar()) n = n * 10 + c - 48; return n * s; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else gcd(b, a % b); } long long int square(long long int n) { return n * n; } long long int bigmod(long long int b, long long int p, long long int m) { if (p == 0) return 1; else if (p % 2 == 0) return square(bigmod(b, p / 2, m)) % m; else return ((b % m) * bigmod(b, p - 1, m)) % m; } long long mulmod(long long a, long long b, long long c) { long long x = 0, y = a % c; while (b > 0) { if (b % 2 == 1) { x = (x + y) % c; } y = (y * 2) % c; b /= 2; } return x % c; } long long int vis[55][55], n, m; char ch[55][55]; long long int fun(long long int i, long long int j, char z, char d) { long long int p = 0; vis[i][j] = 1; if ((j + 1) < m && vis[i][j + 1] == 0 && ch[i][j + 1] == z && d != l ) { p = fun(i, j + 1, z, r ); } else if ((j + 1) < m && vis[i][j + 1] == 1 && ch[i][j + 1] == z && d != l ) { return 1; } if ((i + 1) < n && vis[i + 1][j] == 0 && ch[i + 1][j] == z && d != u ) { p = fun(i + 1, j, z, d ); } else if ((i + 1) < n && vis[i + 1][j] == 1 && ch[i + 1][j] == z && d != u ) { return 1; } if ((j - 1) >= 0 && vis[i][j - 1] == 0 && ch[i][j - 1] == z && d != r ) { p = fun(i, j - 1, z, l ); } else if ((j - 1) >= 0 && vis[i][j - 1] == 1 && ch[i][j - 1] == z && d != r ) { return 1; } if ((i - 1) >= 0 && vis[i - 1][j] == 0 && ch[i - 1][j] == z && d != d ) { p = fun(i - 1, j, z, u ); } else if ((i - 1) >= 0 && vis[i - 1][j] == 1 && ch[i - 1][j] == z && d != d ) { return 1; } return p; } int main() { long long int t, ans = 0, i, j, k; cin >> n >> m; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) cin >> ch[i][j]; } long long int f = 0; for (k = 0; k < 25; k++) { f = 0; for (i = 0; i < n; i++) { f = 0; for (j = 0; j < m; j++) { if (ch[i][j] == (char)( A + k) && vis[i][j] != 1 && fun(i, j, (char)( A + k), a )) { cout << Yes n ; f = 1; break; } } if (f == 1) break; } if (f == 1) { break; } } if (f == 0) cout << No n ; return 0; } |
// system1_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module system1_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
system1_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Fri May 27 23:50:21 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/ClockDivider/ClockDivider_stub.v
// Design : ClockDivider
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ClockDivider(clkIn, clk108M, clk_cpu, clk2cpu, clk6cpu)
/* synthesis syn_black_box black_box_pad_pin="clkIn,clk108M,clk_cpu,clk2cpu,clk6cpu" */;
input clkIn;
output clk108M;
output clk_cpu;
output clk2cpu;
output clk6cpu;
endmodule
|
//======================================================================
//
// Module Name: WHIRLPOOL_WCIPHER_MU_INVERSE
// Description: Mu-inverse function of Whirlpool W-Cipher
//
// Language: Verilog-2001
//
// Module Dependencies: none
//
// Developer: Saied H. Khayat
// URL: https://github.com/saiedhk
// Date: May 2014
//
// Copyright Notice: Free use of this library is permitted under the
// guidelines and in accordance with the MIT License (MIT).
// http://opensource.org/licenses/MIT
//
//======================================================================
`timescale 1ns/1ps
//`define DEBUG
`define PRINT_TEST_VECTORS
module WHIRLPOOL_WCIPHER_MU_INVERSE (
output [0:511] A,
input [7:0] B00, B01, B02, B03, B04, B05, B06, B07,
B10, B11, B12, B13, B14, B15, B16, B17,
B20, B21, B22, B23, B24, B25, B26, B27,
B30, B31, B32, B33, B34, B35, B36, B37,
B40, B41, B42, B43, B44, B45, B46, B47,
B50, B51, B52, B53, B54, B55, B56, B57,
B60, B61, B62, B63, B64, B65, B66, B67,
B70, B71, B72, B73, B74, B75, B76, B77
);
//---------combinational processes----------
assign A[0 : 7 ] = B00;
assign A[8 : 15 ] = B01;
assign A[16 : 23 ] = B02;
assign A[24 : 31 ] = B03;
assign A[32 : 39 ] = B04;
assign A[40 : 47 ] = B05;
assign A[48 : 55 ] = B06;
assign A[56 : 63 ] = B07;
assign A[64 : 71 ] = B10;
assign A[72 : 79 ] = B11;
assign A[80 : 87 ] = B12;
assign A[88 : 95 ] = B13;
assign A[96 : 103] = B14;
assign A[104 : 111] = B15;
assign A[112 : 119] = B16;
assign A[120 : 127] = B17;
assign A[128 : 135] = B20;
assign A[136 : 143] = B21;
assign A[144 : 151] = B22;
assign A[152 : 159] = B23;
assign A[160 : 167] = B24;
assign A[168 : 175] = B25;
assign A[176 : 183] = B26;
assign A[184 : 191] = B27;
assign A[192 : 199] = B30;
assign A[200 : 207] = B31;
assign A[208 : 215] = B32;
assign A[216 : 223] = B33;
assign A[224 : 231] = B34;
assign A[232 : 239] = B35;
assign A[240 : 247] = B36;
assign A[248 : 255] = B37;
assign A[256 : 263] = B40;
assign A[264 : 271] = B41;
assign A[272 : 279] = B42;
assign A[280 : 287] = B43;
assign A[288 : 295] = B44;
assign A[296 : 303] = B45;
assign A[304 : 311] = B46;
assign A[312 : 319] = B47;
assign A[320 : 327] = B50;
assign A[328 : 335] = B51;
assign A[336 : 343] = B52;
assign A[344 : 351] = B53;
assign A[352 : 359] = B54;
assign A[360 : 367] = B55;
assign A[368 : 375] = B56;
assign A[376 : 383] = B57;
assign A[384 : 391] = B60;
assign A[392 : 399] = B61;
assign A[400 : 407] = B62;
assign A[408 : 415] = B63;
assign A[416 : 423] = B64;
assign A[424 : 431] = B65;
assign A[432 : 439] = B66;
assign A[440 : 447] = B67;
assign A[448 : 455] = B70;
assign A[456 : 463] = B71;
assign A[464 : 471] = B72;
assign A[472 : 479] = B73;
assign A[480 : 487] = B74;
assign A[488 : 495] = B75;
assign A[496 : 503] = B76;
assign A[504 : 511] = B77;
endmodule |
#include <bits/stdc++.h> using namespace std; int main(void) { int n; scanf( %d , &n); long a[n]; long long s = 0, ss = 0; for (int i = 0; i < n; i++) { scanf( %ld , &a[i]); s += a[i]; } if (s % 3 != 0) { printf( 0 n ); return 0; } s = s / 3; vector<int> sum1; vector<int> sum2; for (int i = 0; i < n - 1; i++) { ss += a[i]; if (ss == s) sum1.push_back(i); if (ss == 2 * s) sum2.push_back(i); } long long ans = 0; for (int i = 0; i < sum1.size(); i++) { ans += sum2.end() - lower_bound(sum2.begin(), sum2.end(), sum1[i] + 1); } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 2e5 + 4; int main() { int n; scanf( %d , &n); long long b[n], c[n], sum = 0; for (int i = 0; i < n; i++) scanf( %lld , &b[i]), sum += b[i]; for (int i = 0; i < n; i++) scanf( %lld , &c[i]), sum += c[i]; if (sum % 2 * n != 0) { printf( %d , -1); return 0; } sum /= 2 * n; long long a[n]; for (int i = 0; i < n; i++) { long long here = b[i] + c[i] - sum; if (here >= 0 and here % n != 0) { printf( %d , -1); return 0; } a[i] = here / n; } vector<int> fa(31, 0); for (int bit = 0; bit < 31; bit++) { for (int i = 0; i < n; i++) if (a[i] & (1LL << bit)) fa[bit]++; } for (int i = 0; i < n; i++) { for (int bit = 0; bit < 31; bit++) if (a[i] & (1LL << bit)) b[i] -= (1LL << bit) * fa[bit]; if (b[i] != 0) { printf( %d , -1); return 0; } } for (int i = 0; i < n; i++) printf( %lld , a[i]); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:49 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_stub.v
// Design : bg_low
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bg_low(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[10:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [10:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_BEHAVIORAL_PP_V |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cyclone3_pmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cyclone3_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone3_pmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//Defines an integer pipeline that can attempt to do internal dependency resolution.
//By shifting execution to individual components, the revision B core
//should be easier to debug.
module intpipe(op, clk, rst, opWt, regWt, aSel, bSel, cSel, aDat, bDat, flgIn, FLGWRI, COUT, CWRI, AS, BS, CS, FLGOUT);
input [3:0] op;
input clk;
input rst;
//Wait signals for operations and the register file.
input opWt;
input regWt;
input [2:0] aSel;
input [2:0] bSel;
input [2:0] cSel;
input [15:0] aDat;
input [15:0] bDat;
input [7:0] flgIn;
output [15:0] COUT;
output [2:0] AS;
output [2:0] BS;
output [2:0] CS;
output CWRI;
output FLGWRI;
output [7:0] FLGOUT;
assign AS=aSel;
assign BS=bSel;
//Now create some internal signals/shifters:
reg [3:0] opShifter[2:0]; //Fetch/data resolve, execute, writeback.
reg [2:0] destShifter[2:0]; //So that we can keep track of where each op wants to write.
reg [15:0] operandA;
reg [15:0] operandB;
reg [15:0] operandC;
reg cwr;
wire [2:0] dest0;
wire [2:0] dest1;
wire [2:0] dest2;
assign dest0=destShifter[0];
assign dest1=destShifter[1];
assign dest2=destShifter[2];
assign CS=destShifter[2];
assign CWRI=cwr;
wire [15:0] aluOut;
wire [7:0] flgs;
wire aluWriteback;
reg [7:0] curFlgs;
assign COUT=aluOut;
wire [3:0] curOp;
assign curOp=opShifter[1];
//wire [15:0] aluA [0:1];
//wire [15:0] aluB [0:1];
//assign aluA[0]=operandA;
//assign aluB[0]=operandB;
//assign aluA[1]=operandC;
//assign aluB[1]=operandC;
wire aluASelect;
wire aluBSelect;
assign aluASelect=(aSel==destShifter[1]);//||(aSel==destShifter[1]);
assign aluBSelect=(bSel==destShifter[1]);//||(bSel==destShifter[1]);
//This is so that ALU data can be checked:
//wire [15:0] a;
//wire [15:0] b;
//assign a=aluA[aluASelect];
//assign b=aluB[aluBSelect];
ALU crunchinator(opShifter[1], curFlgs, operandA, operandB, flgs, aluOut, aluWriteback);
always@(posedge clk) begin
//First, check whether we should shift:
if(~opWt&&~regWt) begin //TODO: consider converting to inverted or.
opShifter[0]<=op;
opShifter[1]<=opShifter[0];
opShifter[2]<=opShifter[1];
destShifter[0]<=cSel;
destShifter[1]<=destShifter[0];
destShifter[2]<=destShifter[1];
end
//Now do some general stuff:
cwr<=aluWriteback;
//operandA<=aDat;
//operandB<=bDat;
operandC<=aluOut;
if(aluASelect) begin //aSel==destShifter[1]) begin
operandA<=aluOut;
end
//This must be exclusive with the above.
//else if(aSel==destShifter[1]) begin
// operandA<=operandC;
//end
else begin
operandA<=aDat;
end
if(aluBSelect) begin//bSel==destShifter[1]) begin
operandB<=aluOut;
end
//else if(bSel==destShifter[1]) begin
// operandB<=operandC;
//end
else begin
operandB<=bDat;
end
//There need not be anything to handle writebacks if there's a stall, because the pipe
//will simply freeze.
end
initial begin
destShifter[0]=0;
destShifter[1]=0;
destShifter[2]=0;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_sergate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR
);
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 20:23:12 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_nmsuppression_0_0 -prefix
// system_vga_nmsuppression_0_0_ system_vga_nmsuppression_0_0_stub.v
// Design : system_vga_nmsuppression_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_nmsuppression,Vivado 2016.4" *)
module system_vga_nmsuppression_0_0(clk, enable, active, x_addr_in, y_addr_in,
hessian_in, x_addr_out, y_addr_out, hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk,enable,active,x_addr_in[9:0],y_addr_in[9:0],hessian_in[31:0],x_addr_out[9:0],y_addr_out[9:0],hessian_out[31:0]" */;
input clk;
input enable;
input active;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [31:0]hessian_in;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
output [31:0]hessian_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int m1[4] = {1, 1, 1, 1}; int m2[4] = {1, 2, 4, 3}; int m3[4] = {1, 3, 4, 2}; int m4[4] = {1, 4, 1, 4}; int main() { string s; cin >> s; int b = s[s.size() - 1] - 0 ; int a; if (s.size() > 1) a = s[s.size() - 2] - 0 ; else a = 0; int n = (10 * a + b) % 4; cout << (m1[n] + m2[n] + m3[n] + m4[n]) % 5; return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 100000; struct Node { int t; int id; }; bool cmp(Node lhs, Node rhs) { return lhs.t == rhs.t ? lhs.id < rhs.id : lhs.t < rhs.t; } int N, P; Node A[Maxn + 5]; queue<int> q1; priority_queue<int, vector<int>, greater<int> > q2; long long ans[Maxn + 5]; int main() { scanf( %d %d , &N, &P); for (int i = 1; i <= N; i++) { scanf( %d , &A[i].t); A[i].id = i; } sort(A + 1, A + N + 1, cmp); long long now = 0; int last = N + 1; for (int i = 1; i <= N;) { if (!q1.empty()) { int id = q1.front(); q1.pop(); ans[id] = now + P; now += P, last = id; } else if (A[i].t <= now) { if (q1.empty() && A[i].id < last) q1.push(A[i].id); else if (!q1.empty() && q1.back() > A[i].id && A[i].id < last) q1.push(A[i].id); else q2.push(A[i].id); i++; } else { if (!q2.empty()) { int id = q2.top(); q2.pop(); ans[id] = now + P; now += P, last = id; } else now = A[i].t, last = N + 1; } } while (!q1.empty()) { int id = q1.front(); q1.pop(), ans[id] = now + P; now += P; } while (!q2.empty()) { int id = q2.top(); q2.pop(), ans[id] = now + P; now += P; } for (int i = 1; i <= N; i++) printf( %lld , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int Maxn = 2e5 + 5, N = 4e5 + 5, Mod = 1e9 + 7, Inf = 1e18, Log = 22; int n, h[Maxn], r, mx; vector<int> adj[Maxn]; bool mrk[Maxn]; bool flg[2]; void Dfs(int v, int p) { for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (u == p) continue; h[u] = h[v] + 1; if (adj[u].size() == 1) { if (h[u] & 1) { flg[0] = 1; } else { flg[1] = 1; } } Dfs(u, v); } return; } void DFs(int v, int p) { for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (u == p) continue; if (adj[u].size() == 1) { mrk[v] = 1; mx--; continue; } DFs(u, v); } mx += mrk[v]; return; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); if (1 < adj[v].size()) r = v; else if (1 < adj[u].size()) r = u; } Dfs(r, -1); if (flg[0] && flg[1]) cout << 3 << ; else cout << 1 << ; DFs(r, -1); cout << n - 1 + mx << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long N = 1e5 + 10; vector<vector<long long> > v1(N, vector<long long>(2)); vector<vector<long long> > v; long long dfs(long long s, long long n, vector<long long>& level) { long long val = 0; for (auto u : v[s]) { if (level[u] == 0) { val = max(val, dfs(u, n, level)); } else if (level[u]) { val = max(val, level[u]); } } level[s] = val + 1; return level[s]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m; cin >> n >> m; for (long long i = 1; i <= m; i++) { cin >> v1[i][0] >> v1[i][1]; } long long low = 1, high = m, ans = -1; while (low <= high) { long long mid = (low + high) / 2; v.clear(); v.resize(n + 1); vector<long long> par(n + 1, -1), level(n + 1); for (long long i = 1; i <= mid; i++) { v[v1[i][0]].push_back(v1[i][1]); par[v1[i][1]] = v1[i][0]; } for (long long i = 1; i <= n; i++) { if (par[i] == -1) { if (dfs(i, n, level) == n) { ans = mid; high = mid - 1; } else { low = mid + 1; } break; } } } cout << ans; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
//wb_host_interface_tester.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_host_interface_tester
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/03/16
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module wb_host_interface_tester (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_0);
o_wbs_dat <= ADDR_0;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> std::vector<int> G[200006]; int check, a, i, x, y, D, o[200006], z[200006], par[200006], d[200006]; void dfs(int p) { d[p] = D; for (int k = 0; k < G[p].size(); k++) { if (d[G[p][k]] == 0) { D++; dfs(G[p][k]); D--; } else par[p] = G[p][k]; } } int main() { scanf( %d , &a); for (i = 1; i < a; i++) { scanf( %d%d , &x, &y); G[x].push_back(y); G[y].push_back(x); } D = 1; dfs(1); for (i = 1; i <= a; i++) { scanf( %d , &z[i]); o[z[i]] = i; } for (i = 1; i < a; i++) { if (d[z[i]] > d[z[i + 1]]) check = 1; else if (d[z[i]] == d[z[i + 1]]) { if (o[par[z[i]]] > o[par[z[i + 1]]]) check = 1; } } if (check == 1) puts( No ); else puts( Yes ); } |
#include <bits/stdc++.h> long long n, i, k, j, t, b; char a[2500]; bool s; using namespace std; int main() { k = 0; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == H ) k++; } b = n - k; for (i = n + 1; i <= 2 * n; i++) a[i] = a[i - n]; for (i = 1; i <= 2 * n; i++) if (i + k <= 2 * n) { t = 0; for (j = i; j < i + k; j++) if (a[j] != H ) t++; if (t < b) b = t; } cout << b << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> istream& operator>>(istream& is, vector<T>& v) { for (T& x : v) is >> x; return is; } ostream& operator<<(ostream& os, const pair<int, int>& unit) { return os << y = << unit.first << x + << unit.second; } template <class T> ostream& operator<<(ostream& os, const vector<T>& v) { if (!v.empty()) { os << v.front(); for (int i = 1; i < v.size(); ++i) os << << v[i]; } return os; } const int P = 1000000007; int norm(int x) { return x >= P ? x - P : x; } void add(int& x, int y) { if ((x += y) >= P) x -= P; } pair<long long, long long> operator+(const pair<long long, long long>& lhs, const pair<long long, long long>& rhs) { return pair<long long, long long>(lhs.first + rhs.first, lhs.second + rhs.second); } pair<long long, long long> operator-(const pair<long long, long long>& lhs) { return pair<long long, long long>(-lhs.first, -lhs.second); } pair<long long, long long> operator-(const pair<long long, long long>& lhs, const pair<long long, long long>& rhs) { return lhs + (-rhs); } long long operator^(const pair<long long, long long>& lhs, const pair<long long, long long>& rhs) { return lhs.first * rhs.first + lhs.second * rhs.second; } long long operator*(const pair<long long, long long>& lhs, const pair<long long, long long>& rhs) { return lhs.first * rhs.second - lhs.second * rhs.first; } long long dfrac(long long x, long long y) { if (x < 0) return (x - y + 1) / y; return x / y; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, m, q; cin >> n >> m >> q; vector<int> u(m), v(m), w(m); for (int i = 0; i < m; ++i) { cin >> u[i] >> v[i] >> w[i]; --u[i]; --v[i]; } vector<int> dp(n, numeric_limits<int>::min()); dp[0] = 0; int ans = 0; for (int i = 0; i < n; ++i) { add(ans, *max_element(dp.begin(), dp.end()) % P); vector<int> ndp(n, numeric_limits<int>::min()); for (int j = 0; j < m; ++j) { ndp[u[j]] = max(ndp[u[j]], dp[v[j]] + w[j]); ndp[v[j]] = max(ndp[v[j]], dp[u[j]] + w[j]); } swap(dp, ndp); } vector<pair<long long, long long> > pts; for (int i = 0; i < m; ++i) { int val = max(dp[u[i]], dp[v[i]]); pts.emplace_back(w[i], val - w[i] * n); } sort(pts.begin(), pts.end()); vector<pair<long long, long long> > stk; for (const auto& pt : pts) { if (!stk.empty() && stk.back().first == pt.first) stk.pop_back(); while (stk.size() > 1 && ((stk[stk.size() - 1] - stk[stk.size() - 2]) * (pt - stk[stk.size() - 1])) >= 0) { stk.pop_back(); } stk.push_back(pt); } auto contrib = [&](long long l, long long r, const pair<long long, long long>& lne) { l = max(l, (long long)n); r = min(r, (long long)q); if (l <= r) ans = (ans + (r - l + 1) * lne.second % P + (l + r) * (r - l + 1LL) / 2 % P * lne.first) % P; if (ans < 0) ans += P; }; long long cur = numeric_limits<long long>::min(); for (int i = 0; i + 1 < stk.size(); ++i) { long long nxt = dfrac(stk[i].second - stk[i + 1].second, stk[i + 1].first - stk[i].first); contrib(cur + 1, nxt, stk[i]); cur = nxt; } contrib(cur + 1, numeric_limits<long long>::max(), stk.back()); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, h; int main() { cin >> n >> h; for (int i = 1; i < n; i++) { double h1 = h * sqrt(1.0 * i / n); printf( %.12llf , h1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 4e6 + 5; long long n, a[N], b[N], sum[N], I, lim = 1, mx = -1, Ans; long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return f * x; } long long qpow(long long x, long long y) { long long ret = 1; while (y) { if (y & 1) ret = ret * x; y >>= 1; x = x * x; } return ret; } long long LG2(long long x) { long long ret = log2(x); if (qpow(2, ret) >= x) return ret; else return ret + 1; } int main() { memset(sum, 0, sizeof(sum)); memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); n = read(), I = read(); for (register long long i = (1); i <= (n); i++) a[i] = read(); sort(a + 1, a + n + 1); a[0] = -1; for (register long long i = (1); i <= (n); i++) { if (a[i] != a[i - 1]) b[++b[0]] = 1; else b[b[0]]++; } for (register long long i = (2); i <= (b[0]); i++) { if (LG2(i) * n <= 8 * I) lim = i; else break; } if (lim >= b[0]) printf( 0 n ); else { for (register long long i = (1); i <= (b[0]); i++) sum[i] = sum[i - 1] + b[i]; for (register long long i = (lim); i <= (b[0]); i++) mx = max(mx, sum[i] - sum[i - lim]); Ans = sum[b[0]] - mx; printf( %lld n , Ans); } return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_DETECTION_YN.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_DETECTION_YN (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [109:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [109:0] q;
wire sub_wire0;
wire sub_wire1;
wire [109:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [109:0] q = sub_wire2[109:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = 8,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 110,
scfifo_component.lpm_widthu = 3,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "110"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "110"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "110"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 110 0 INPUT NODEFVAL "data[109..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 110 0 OUTPUT NODEFVAL "q[109..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 110 0 data 0 0 110 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 110 0 @q 0 0 110 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN_bb.v TRUE
|
module nios_solo (
clk_clk,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
io_u2p_ack,
io_u2p_rdata,
io_u2p_read,
io_u2p_wdata,
io_u2p_write,
io_u2p_address,
io_u2p_irq,
mem_mem_req_address,
mem_mem_req_byte_en,
mem_mem_req_read_writen,
mem_mem_req_request,
mem_mem_req_tag,
mem_mem_req_wdata,
mem_mem_resp_dack_tag,
mem_mem_resp_data,
mem_mem_resp_rack_tag,
reset_reset_n,
dummy_export);
input clk_clk;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input io_u2p_ack;
input [7:0] io_u2p_rdata;
output io_u2p_read;
output [7:0] io_u2p_wdata;
output io_u2p_write;
output [19:0] io_u2p_address;
input io_u2p_irq;
output [25:0] mem_mem_req_address;
output [3:0] mem_mem_req_byte_en;
output mem_mem_req_read_writen;
output mem_mem_req_request;
output [7:0] mem_mem_req_tag;
output [31:0] mem_mem_req_wdata;
input [7:0] mem_mem_resp_dack_tag;
input [31:0] mem_mem_resp_data;
input [7:0] mem_mem_resp_rack_tag;
input reset_reset_n;
input dummy_export;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, j, t, k, x, y; scanf( %d , &t); int a[10] = {0}, b[10] = {0}; for (j = 0; j < t; j++) { scanf( %d%d%d , &k, &x, &y); if (k == 1) { a[0] = a[0] + x; a[1] = a[1] + y; } else { b[0] = b[0] + x; b[1] = b[1] + y; } } if (a[0] >= a[1]) printf( LIVE n ); else printf( DEAD n ); if (b[0] >= b[1]) printf( LIVE n ); else printf( DEAD n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; cout << 0 << << 0 << << n; return 0; } |
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