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#include <bits/stdc++.h> using namespace std; int A[5005], n, k, L[5005][5005], S[5005], E[5005]; void doc() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &A[i]); } } void xuly() { sort(A + 1, A + n + 1); for (int i = 1; i <= n; i++) { S[i] = 1; E[i] = i; for (int j = i - 1; j > 0; j--) if (A[i] - A[j] <= 5) { S[i]++; E[i] = j; } else break; } for (int i = 1; i <= k; i++) { for (int j = 1; j <= n; j++) { L[i][j] = max(max(L[i][j - 1], L[i][j]), L[i - 1][E[j] - 1] + S[j]); } } cout << L[k][n]; } int main() { doc(); xuly(); return 0; } |
#include<bits/stdc++.h> using namespace std; #define ll long long int #define M 1000000007 int main() { ios_base::sync_with_stdio(false); cin.tie(0),cout.tie(0); int t,n,x; cin>>t; string str= 2020 ; while(t--) { int a,b,c,d,e,c1,c2,c3; cin>>c1>>c2>>c3; cin>>a>>b>>c>>d>>e; bool flag=true; int te=min(c1,a); c1-=te; a-=te; te=min(c2,b); c2-=te; b-=te; te=min(c3,c); c3-=te; c-=te; te=min(c1,d); c1-=te; d-=te; te=min(c2,e); c2-=te; e-=te; te=min(c3,d); c3-=te; d-=te; te=min(c3,e); c3-=te; e-=te; if(a||b||c||d||e) cout<< no ; else cout<< yes ; cout<<endl; } return 0; } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: sa1_mult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sa1_mult (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 5, mod = 1e9 + 9, bit = 61, sq = 1000; const int T = (100001 + sq - 1) / sq; vector<int> lucky; bool isl[N] = {0}; int bid[100005], a[100005], beg[T], en[T], lazy[T] = {0}; int fq[T][N]; void create() { for (int d = 1; d <= 4; d++) { for (int mask = 0; mask < (1ll << d); mask++) { int curr = 0; for (int j = 0; j <= d - 1; j++) { curr = (curr * 10); if (mask & (1ll << j)) { curr += 4; } else { curr += 7; } } isl[curr] = 1; lucky.push_back(curr); } } } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int t = 1; memset(fq, 0, sizeof(fq)); create(); while (t--) { int n, q; cin >> n >> q; int j = -1; for (int i = 1; i <= n; i++) { cin >> a[i]; if (i % sq == 1) { bid[i] = ++j; beg[j] = i; en[j] = min(i + sq - 1, n); } else { bid[i] = j; } fq[j][a[i]]++; } while (q--) { string tp; int l, r; cin >> tp >> l >> r; if (tp[0] == c ) { int ans = 0; if (bid[l] == bid[r]) { for (int i = l; i <= r; i++) { ans += isl[a[i] + lazy[bid[l]]]; } } else { for (int i = l; i <= en[bid[l]]; i++) { ans += isl[a[i] + lazy[bid[l]]]; } for (int i = bid[l] + 1; i <= bid[r] - 1; i++) { for (auto x : lucky) { if (x >= lazy[i]) { ans += fq[i][x - lazy[i]]; } } } for (int i = beg[bid[r]]; i <= r; i++) { ans += isl[a[i] + lazy[bid[r]]]; } } cout << ans << n ; } else { int d; cin >> d; if (bid[l] == bid[r]) { for (int i = l; i <= r; i++) { fq[bid[i]][a[i]]--; fq[bid[i]][a[i] + d]++; a[i] += d; } } else { for (int i = l; i <= en[bid[l]]; i++) { fq[bid[i]][a[i]]--; fq[bid[i]][a[i] + d]++; a[i] += d; } for (int i = bid[l] + 1; i <= bid[r] - 1; i++) { lazy[i] += d; } for (int i = beg[bid[r]]; i <= r; i++) { fq[bid[i]][a[i]]--; fq[bid[i]][a[i] + d]++; a[i] += d; } } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long remi = 1000000007; const long long remi2 = 998244353; const long long inf = 1e18 + 1e17 + 1e16 + 1e15 + 1e14; long long Pow(long long x, long long y, long long m) { if (y == 0) return 1; long long p = Pow(x, y / 2, m) % m; p = (p * p) % m; return (y % 2 == 0) ? p : (x * p) % m; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j, k; long long n, m; cin >> n >> m; vector<long long> v(m); for (i = 0; i < m; i++) { cin >> v[i]; } sort(v.begin(), v.end()); bool ans = true; if (m == 0) { cout << YES ; exit(0); } if (v[0] == 1 or v[m - 1] == n) ans = false; for (i = 2; i < m; i++) { long long s0 = v[i - 2]; long long s1 = v[i - 1]; long long s2 = v[i]; if ((s0 == s2 - 2) and (s1 == s2 - 1)) ans = false; } if (ans) cout << YES ; else cout << NO ; } |
// We assume clock with frequency F = 100 Hz or period T = 10 ms
`timescale 1ms/1us
module trafficlight_controller_tb;
// Inputs
reg clk;
reg rst;
// outputs
wire light1_green;
wire light1_red;
wire light1_yellow;
wire light2_green;
wire light2_red;
wire light2_yellow;
// Constants
localparam CLK_PERIOD = 10; // in ms
task expect;
input light1_green_exp;
input light1_red_exp;
input light1_yellow_exp;
input light2_green_exp;
input light2_red_exp;
input light2_yellow_exp;
if ((light1_green_exp !== light1_green) ||
(light1_red_exp !== light1_red) ||
(light1_yellow_exp !== light1_yellow) ||
(light2_green_exp !== light2_green) ||
(light2_red_exp !== light2_red) ||
(light2_yellow_exp !== light2_yellow)) begin
$display("TEST FAILED");
$display("At time %0d: light1_green=%0b, light1_red=%0b, light1_yellow=%0b, light2_green=%0b, light2_red=%0b, light2_yellow=%0b",
$time,
light1_green, light1_red, light1_yellow,
light2_green, light2_red, light2_yellow);
$display("Should be light1_green=%0b, light1_red=%0b, light1_yellow=%0b, light2_green=%0b, light2_red=%0b, light2_yellow=%0b",
light1_green_exp, light1_red_exp, light1_yellow_exp,
light2_green_exp, light2_red_exp, light2_yellow_exp );
$finish;
end
else begin
$display("At time %0d: light1_green=%0b, light1_red=%0b, light1_yellow=%0b, light2_green=%0b, light2_red=%0b, light2_yellow=%0b",
$time,
light1_green, light1_red, light1_yellow,
light2_green, light2_red, light2_yellow);
end
endtask
// Instantiate the Unit Under Test (UUT)
trafficlight_controller uut(.clk(clk),
.rst(rst),
.light1_green(light1_green),
.light1_red(light1_red),
.light1_yellow(light1_yellow),
.light2_green(light2_green),
.light2_red(light2_red),
.light2_yellow(light2_yellow));
// Clock and async reset stimulus
initial begin
clk = 1'b0;
rst = 1'b1;
// hold sync reset for next 2 cc
repeat(4) #(CLK_PERIOD/2) clk = ~clk;
// deassert reset
rst = 1'b0;
// clock forever
forever #(CLK_PERIOD/2) clk = ~clk;
end
// Stimulus and checker
initial begin
// Wait for reset to Deassert
@(negedge rst);
// On reset the expected state: L1 - G, L2 - R
expect( 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0);
// After 60 sec or 6000 cc, the expected state: L1 - Y, L2 -R
#60010 expect( 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0);
// After 5 sec or 500 cc, the expected state: L1 - R, L2 -G
#5010 expect( 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0);
// After 60 sec or 6000 cc, the expected state: L1 - R, L2 -Y
#60010 expect( 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1);
// After 5 sec or 500 cc, the expected state: L1 - G, L2 -R
#5010 expect( 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0);
$display("TEST PASSED");
$finish;
end
endmodule // module trafficlight_controller_tb;
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <typename T> inline bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } const int INF = 0x3f3f3f3f; const int N = 2e3 + 10, mod = 1e9 + 7; int dir[4][2] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; int vis[N][N]; char Map[N][N]; struct node { int x, y; } dis[N][N]; deque<node> Q; inline int read() { int x = 0, flag = 1; char ch = getchar(); while (!isdigit(ch) && ch != - ) ch = getchar(); if (ch == - ) flag = -1, ch = getchar(); while (isdigit(ch)) x = (x << 3) + (x << 1) + (ch - 0 ), ch = getchar(); return x * flag; } int main() { int n = read(), m = read(), X = read(), Y = read(), L = read(), R = read(); for (int i = (1), iend = (n); i <= iend; i++) scanf( %s , Map[i] + 1); int cnt = 1; Q.push_back((node){X, Y}), vis[X][Y] = true; while (!Q.empty()) { node cur = Q.front(); Q.pop_front(); int x = cur.x, y = cur.y; for (int i = (0), iend = (3); i <= iend; i++) { int Nx = x + dir[i][0], Ny = y + dir[i][1], curdL = dis[x][y].x, curdR = dis[x][y].y; if (Nx <= 0 || Ny <= 0 || Nx > n || Ny > m || vis[Nx][Ny] || Map[Nx][Ny] == * ) continue; if (i == 2) curdR++; if (i == 3) curdL++; if (curdL > L || curdR > R) continue; if (i == 2 || i == 3) Q.push_back((node){Nx, Ny}); else Q.push_front((node){Nx, Ny}); dis[Nx][Ny] = (node){curdL, curdR}; vis[Nx][Ny] = true, cnt++; } } printf( %d n , cnt); return 0; } |
module fmrv32im_alu
(
input RST_N,
input CLK,
input INST_ADDI,
input INST_SLTI,
input INST_SLTIU,
input INST_XORI,
input INST_ORI,
input INST_ANDI,
input INST_SLLI,
input INST_SRLI,
input INST_SRAI,
input INST_ADD,
input INST_SUB,
input INST_SLL,
input INST_SLT,
input INST_SLTU,
input INST_XOR,
input INST_SRL,
input INST_SRA,
input INST_OR,
input INST_AND,
input INST_BEQ,
input INST_BNE,
input INST_BLT,
input INST_BGE,
input INST_BLTU,
input INST_BGEU,
input INST_LB,
input INST_LH,
input INST_LW,
input INST_LBU,
input INST_LHU,
input INST_SB,
input INST_SH,
input INST_SW,
input [31:0] RS1,
input [31:0] RS2,
input [31:0] IMM,
output reg RSLT_VALID,
output reg [31:0] RSLT
);
/*
下記の命令でrs1+IMMを行うのはLOAD, STORE命令のアドレス値を
算出するためです。
INST_LB, INST_LH, INST_LW, INST_LBU, INST_LHU,
INST_SB, INST_SH, INST_SW
*/
reg [31:0] reg_op2;
always @(*) begin
reg_op2 <= (INST_ADDI | INST_SLTI | INST_SLTIU |
INST_XORI | INST_ANDI | INST_ORI |
INST_SLLI | INST_SRLI | INST_SRAI |
INST_LB | INST_LH | INST_LW | INST_LBU | INST_LHU |
INST_SB | INST_SH | INST_SW)?IMM:RS2;
end
reg [31:0] alu_add_sub, alu_shl, alu_shr;
reg [31:0] alu_xor, alu_or, alu_and;
reg alu_eq, alu_ltu, alu_lts;
always @(*) begin
alu_add_sub <= (INST_SUB)?(RS1 - reg_op2):(RS1 + reg_op2);
alu_shl <= RS1 << reg_op2[4:0];
alu_shr <= $signed({(INST_SRA | INST_SRAI)?RS1[31]:1'b0, RS1}) >>> reg_op2[4:0];
alu_eq <= (RS1 == reg_op2);
alu_lts <= ($signed(RS1) < $signed(reg_op2));
alu_ltu <= (RS1 < reg_op2);
alu_xor <= RS1 ^ reg_op2;
alu_or <= RS1 | reg_op2;
alu_and <= RS1 & reg_op2;
end // always @ (posedge CLK)
always @(posedge CLK) begin
if(!RST_N) begin
RSLT <= 0;
RSLT_VALID <= 0;
end else begin
RSLT <= (INST_ADDI | INST_ADD | INST_SUB |
INST_LB | INST_LH | INST_LW | INST_LBU | INST_LHU |
INST_SB | INST_SH | INST_SW)?alu_add_sub:
(INST_SLTI | INST_SLT)?alu_lts:
(INST_SLTIU | INST_SLTU)?alu_ltu:
(INST_SLLI | INST_SLL)?alu_shl:
(INST_SRLI | INST_SRAI | INST_SRL | INST_SRA)?alu_shr:
(INST_XORI | INST_XOR)?alu_xor:
(INST_ORI | INST_OR)?alu_or:
(INST_ANDI | INST_AND)?alu_and:
(INST_BEQ)?alu_eq:
(INST_BNE)?!alu_eq:
(INST_BGE)?!alu_lts:
(INST_BGEU)?!alu_ltu:
(INST_BLT)?alu_lts:
(INST_BLTU)?alu_ltu:
32'd0;
RSLT_VALID <= INST_ADDI | INST_ADD | INST_SUB |
INST_LB | INST_LH | INST_LW | INST_LBU | INST_LHU |
INST_SB | INST_SH | INST_SW |
INST_SLTI | INST_SLT | INST_SLTIU | INST_SLTU |
INST_SLLI | INST_SLL |
INST_SRLI | INST_SRAI | INST_SRL | INST_SRA |
INST_XORI | INST_XOR |
INST_ORI | INST_OR |
INST_ANDI | INST_AND |
INST_BEQ | INST_BNE | INST_BGE | INST_BGEU |
INST_BLT | INST_BLTU;
end
end
endmodule // fmrv32im_alu
|
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
task registerTask;
input [17:0] signals;
//6 7 8 12 14 16
fork
//#2 set the alu signals
#2 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = {signals[17],1'b0,signals[15],1'b0,signals[13],1'b0,signals[11:9],1'b0,1'b0,1'b0,signals[5:0]};
//#4 set the register signals
#4 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
//#6 let data be saved
#6 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
join
endtask
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00001;ALUSTORE = 0 ; IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;CU=0; opcode=5'b10010;end
else
State <= NextState;
/*
STATUS REGISTER FLAGS
WE FETCH INSTRUCTIONS 8BITS AT A TIME 8BIT DATAPATH
31. Negative, N = (ADD)&&(A[31]==B[31])&&(A[31]!=OUT[31]) || (SUB)
30. Zero, Z = OUT == 0
29. Carry, C = CARRY
28. Overflow, V = OVERFLOW
END
*/
always @ (State, MFC)
case (State)
5'b00000 : NextState = 5'b00000;
5'b00001 : if(MFC) NextState = 5'b10001 ; else NextState = 5'b00010;
5'b00010 : NextState = 5'b00011; // goto stall cycle if not ready
5'b00011 : if(MFC)NextState = 5'b00100; else NextState = 5'b00011;
5'b00100 : NextState = 5'b00101;
5'b00101 : case(IR[31:28])//Decode Begin
4'b0000: if(SR[2]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0001: if(SR[2]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0010: if(SR[1]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0011: if(SR[1]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0100: if(SR[3]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0101: if(SR[3]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0110: if(SR[0]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0111: if(SR[0]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b1000: if(SR[1]==1&SR[2]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b1001: if(SR[1]==0|SR[2]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b1010: if(SR[3]==SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1011: if(SR[3]!=SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1100: if(SR[2]==0&SR[3]==SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1101: if(SR[2]==1|SR[3]!=SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1110: NextState = 5'b00110;
endcase
5'b00110 : case(IR[27:25])
3'b000,3'b001:NextState = 5'b00111;
3'b010,3'b011:NextState = 5'b01000;//Load/Store operation 1
3'b101:NextState = 5'b0001;//branch operation 1
default:NextState = 5'b0001;
endcase
5'b00111 : NextState = 5'b00001; // Data operation 1
5'b01000 : NextState = 5'b00001; //Load/Store operation 1
5'b01001 : NextState = 5'b01010;
5'b01010 : NextState = 5'b01011;
5'b01011 : NextState = 5'b01100;
5'b01100 : NextState = 5'b01101;
5'b01101 : NextState = 5'b01110;
5'b01110 : NextState = 5'b01111;
5'b01111 : NextState = 5'b10000;
5'b10000 : NextState = 5'b10001;
5'b10001 : if(MFC) NextState = 5'b10001 ; else NextState = 5'b00010; // Stall State MFC Already Up
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin end
5'b00001 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 1 ; CU=4'hf;opcode=5'b10010;end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 1 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= 1 ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10001;end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= 1 ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10010;end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 1 ;MBRLOAD= 0 ;MBRSTORE= 1 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10010;end // transfer data to IR
5'b00101 : begin ALUSTORE = 1 ;IR_CU=1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'h0;end // Check status codes
5'b00110 : begin ALUSTORE = 0 ;IR_CU= 1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;end // Decode instruction type and set out signals
5'b00111 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD= 1 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;opcode = {1'b0,IR[24:21]};end //Data Operation 1
5'b01000 : begin end //Load/Store operation 1
5'b01001 : begin end
5'b01010 : begin end
5'b01011 : begin end
5'b01100 : begin end
5'b01101 : begin end
5'b01110 : begin end
5'b01111 : begin end
5'b10000 : begin end
5'b10001 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10001;end // Stall State Purpusely Left Empty MFC Already Up
/*branch and load_store instruction*/
default : begin end
endcase
endmodule |
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9; int a, c; int arrA[2000]; int arrC[2000]; void sol() { cin >> c >> a; for (int i = 0; i < c; i++) { cin >> arrC[i]; } for (int i = 0; i < a; i++) { cin >> arrA[i]; } int result = 0; int j = 0; for (int i = 0; i < a && j < c; i++, j++) { while (j < c && arrC[j] > arrA[i]) j++; if (j >= c) break; result++; } cout << result << endl; } int main(void) { sol(); return 0; } |
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
reg `control_w flit1c;
reg `data_w flit1d;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(port2_ci), .port2_co(port2_co),
.port3_ci(port3_ci), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(flit1d), .port1_do(port1_do),
.port2_di(port2_di), .port2_do(port2_do),
.port3_di(port3_di), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
flit0c = 22'h200001;
flit0d = 128'h0123456789abcdef0123456789abcdef;
flit1c = 22'h200802;
flit1d = 128'h0123456789abcdef0123456789abcdef;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 22'h0;
flit0d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
//load_store station is for load-store instruction, they will be issued in order
//dispatch: p_rs, p_rt, immed, p_rd, some control signals
//issue: if the head is ready, issue it
//complete: receive <PR_rd#, RegDest_compl> from CDB, set the valid bit
module ls_station(
input clk, rst,
//from dispatch stage
input isDispatch,
input [3:0] rob_num_dp,
input [5:0] p_rd_new, //this rd from decode stage, it is actually rt for load
input [5:0] p_rs,
input read_rs, //asserted if rs is read
input v_rs, //this input is from map table, if rs is not used, set this to 1
input [5:0] p_rt,
input read_rt,
input v_rt,
input mem_ren, mem_wen, //enable signal for LSQ can be generated from these two signals
input [15:0] immed,
input stall_hazard,
input stall_issue,
//from branch/jump recovery
input recover,
input [3:0] rob_num_rec, //flush the instruction that has ROB match
//from complete stage
input [5:0] p_rd_compl, //set the complete bit if register p_rd_compl match rs or rt
input RegDest_compl,
input complete,
output [5:0] p_rs_out, p_rt_out,
output [5:0] p_rd_out, //part of the result
output [15:0] immed_out,
output [3:0] rob_num_out,
output RegDest_out, //for load instruction, write register, if mem_ren is 1, this must be 1, part of result
output mem_ren_out, //for load instruction, read memory
output mem_wen_out, //for store instruction, write memory
output issue, //asserted if an instruction issued
output lss_full
);
//[41]: isLW, [40]: isST, [39:36]:rob_num, [35:30] p_rd, [29:24]: p_rs, [23]:v_rs
//[22:17]: p_rt, [16] v_rt, [15:0] immed,
reg [41:0] ls_station [0:3];
reg [3:0] lss_valid; //valid array for the lss, initialized to 0, when allocate set to 1, deallocated set to 0
reg [2:0] counter;
reg [3:0] head, tail;
reg [1:0] head_addr;
wire read, write;
wire head_rdy; //the head is ready to be issued
assign write = isDispatch && !stall_hazard && !lss_full && !recover && (mem_ren || mem_wen);
assign read = !stall_hazard && !recover && head_rdy && lss_valid[head_addr] && !stall_issue; //stall_hazard from outside, asserted if other blocks have hazard
//counter recording full or empty status
always @(posedge clk or negedge rst) begin
if (!rst)
counter <= 3'b000;
else if (write && read)
counter <= counter;
else if (write)
counter <= counter + 1;
else if (read)
counter <= counter - 1;
end
assign lss_full = (counter == 3'b100);
//increase head when read, increase tail when write
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'b0001;
head_addr <= 2'b00;
tail <= 4'b0001;
end
else begin
if (write) begin
tail <= {tail[2:0], tail[3]};
end
if (read) begin
head <= {head[2:0], head[3]};
head_addr <= head_addr + 1;
end
end
end
///////////////////////////////////combinational logic///////////////////////////////////////////////////
wire [3:0] rob_match_array; //[2] ismatch [1:0] addr
wire [3:0] rs_match_array, rt_match_array;
//comparator array for flushing instruction
genvar j;
generate
for (j = 0; j < 4; j = j + 1) begin : combinational
assign rob_match_array[j] = (ls_station[j][39:36] == rob_num_rec) && lss_valid[j];
assign rs_match_array[j] = (ls_station[j][29:24] == p_rd_compl) && lss_valid[j] && RegDest_compl;
assign rt_match_array[j] = (ls_station[j][22:17] == p_rd_compl) && lss_valid[j] && RegDest_compl;
end
endgenerate
////////////////////////////////seqnential logic///////////////////////////////////
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : sequential
always @(posedge clk or negedge rst) begin
if (!rst) begin
ls_station[i] <= {42{1'b0}};
lss_valid[i] <= 1'b0;
end
else begin
if (write && tail[i]) begin //this is ok, because if a entry is tail, valid[i] is 0, head[i] is 0
ls_station[i] <= {mem_ren, mem_wen, rob_num_dp, p_rd_new, p_rs, v_rs || (!read_rs),
p_rt, v_rt || (!read_rt), immed};
lss_valid[i] <= 1'b1;
end
else begin
if (recover && rob_match_array[i]) begin //flush during recovery
ls_station[i][41:40] <= 2'b00;
end
if (complete && rs_match_array[i]) begin //set rs complete/valid
ls_station[i][23] <= 1'b1;
end
if (complete && rt_match_array[i]) begin
ls_station[i][16] <= 1'b1;
end
if (read && head[i]) begin
lss_valid[i] <= 1'b0;
end
end
end
end
end
endgenerate
//////////////////////////////////////issue logic outputs/////////////////////////////////////
assign head_rdy = ls_station[head_addr][23] && ls_station[head_addr][16];
assign p_rs_out = ls_station[head_addr][29:24];
assign p_rt_out = ls_station[head_addr][22:17];
assign p_rd_out = ls_station[head_addr][35:30];
assign immed_out = ls_station[head_addr][15:0];
assign RegDest_out = ls_station[head_addr][41]; //from isLW (mem_ren)
assign mem_ren_out = ls_station[head_addr][41]; //from isLW (mem_ren)
assign mem_wen_out = ls_station[head_addr][40]; //from isSW (mem_wen)
assign rob_num_out = ls_station[head_addr][39:36];
assign issue = read;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_2_V
`define SKY130_FD_SC_LP__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_monitor.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// pcx_monitor.v File to monitor PCX Address. Will print out IFETCH
// transactions, and will stop the simulation when GOOD_TRAP or
// BAD_TRAP is reached.
`timescale 1 ns/10 ps
module pcx_monitor (
rclk,
spc_pcx_req_pq,
spc_pcx_data_pa
);
input rclk;
input [4:0] spc_pcx_req_pq;
input [123:0] spc_pcx_data_pa;
parameter GOOD_TRAP_1 = 40'h1000122000;
parameter GOOD_TRAP_2 = 40'h0000082000;
parameter GOOD_TRAP_3 = 40'h1A00122000;
parameter BAD_TRAP_1 = 40'h1000122020;
parameter BAD_TRAP_2 = 40'h0000082020;
parameter BAD_TRAP_3 = 40'h1A00122020;
reg any_req_pa;
// OR together all request pins and delay one cycle
always @(posedge rclk) begin
any_req_pa <= | spc_pcx_req_pq;
end
// For simulation purposes, print a debug message whenever an I-fetch
// packet is seen
always @(posedge rclk) begin
if (any_req_pa && spc_pcx_data_pa[123] &&
spc_pcx_data_pa[122:118] == 5'b10000) begin
$display("PCX: %t : I-fetch from address 0x%h", $time,
spc_pcx_data_pa[103:64]);
if (spc_pcx_data_pa[103:64] === GOOD_TRAP_1 ||
spc_pcx_data_pa[103:64] === GOOD_TRAP_2 ||
spc_pcx_data_pa[103:64] === GOOD_TRAP_3) begin
$display("PCX: %t : Reached good trap: Diag Passed\n", $time);
#500;
$finish;
end
if (spc_pcx_data_pa[103:64] === BAD_TRAP_1 ||
spc_pcx_data_pa[103:64] === BAD_TRAP_2 ||
spc_pcx_data_pa[103:64] === BAD_TRAP_3) begin
$display( "PCX: %t : Reached bad trap: Diag Failed\n", $time);
#500;
$finish;
end
end
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test a case when two variables with the same name are used in two
// different processes.
module vhdl_process_scope_test;
vhdl_process_scope dut();
initial begin
#0;
// the test takes place in the dut processes
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_1_V
`define SKY130_FD_SC_MS__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_0_V
`define SKY130_FD_SC_LP__AND3_0_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_0 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_0 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_0_V
|
#include <bits/stdc++.h> using namespace std; double r1, x, A, B, p1, p2, ans, t, y[5002], z[5002], r2; int n, m, k; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> x; r1 = (((r1) > (x)) ? (r1) : (x)); } cin >> m; for (int i = 1; i <= m; i++) cin >> y[i]; cin >> k; for (int i = 1; i <= k; i++) cin >> z[i]; cin >> A >> B; for (int i = 1; i <= m; i++) for (int j = 1; j <= k; j++) { p1 = y[i]; p2 = z[j]; t = (p2 * A) / (p1 * B); r2 = sqrt((r1 * r1) / (t + 1)); ans = (((ans) > (r2)) ? (ans) : (r2)); } printf( %.9f n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_TB_V
`define SKY130_FD_SC_HS__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 CIN = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 CIN = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 CIN = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 CIN = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_TB_V
|
//#############################################################################
//# Function: Carry Save Adder (3:2) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa32 #(parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
input [DW-1:0] in2,//input
output [DW-1:0] s, //sum
output [DW-1:0] c //carry
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)
begin : asic
asic_csa32 i_csa32[DW-1:0] (.s(s[DW-1:0]),
.c(c[DW-1:0]),
.in2(in2[DW-1:0]),
.in1(in1[DW-1:0]),
.in0(in0[DW-1:0]));
end
else
begin : generic
assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) |
(in1[DW-1:0] & in2[DW-1:0]) |
(in2[DW-1:0] & in0[DW-1:0] );
end
endgenerate
endmodule // oh_csa32
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if (b > a) { swap(a, b); } cout << b << ; int r = a - b; cout << r / 2; return 0; } |
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; template <class T, class U> ostream &operator<<(ostream &os, const pair<T, U> &p) { os << ( << p.first << , << p.second << ) ; return os; } template <class T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; for (int i = 0; i < (int)v.size(); i++) { if (i) { os << , ; } os << v[i]; } os << } ; return os; } ostream &operator<<(ostream &os, const set<int> &se) { os << { ; int now = 0; for (auto x : se) { if (now) { os << , ; } os << x; now++; } os << } ; return os; } void debugg() { cerr << endl; } template <class T, class... Args> void debugg(const T &x, const Args &...args) { cerr << << x; debugg(args...); } using namespace std; const int inf = (1 << 30) - 1; const long long linf = 1LL << 61; const int MAX = 510000; int dy[8] = {0, 1, 0, -1, 1, -1, -1, 1}; int dx[8] = {-1, 0, 1, 0, 1, -1, 1, -1}; const double pi = acos(-1); const double eps = 1e-8; template <typename T1, typename T2> inline bool chmin(T1 &a, T2 b) { if (a > b) { a = b; return true; } else return false; } template <typename T1, typename T2> inline bool chmax(T1 &a, T2 b) { if (a < b) { a = b; return true; } else return false; } template <typename T> inline void print(T &a) { int sz = a.size(); for (auto itr = a.begin(); itr != a.end(); itr++) { cout << *itr; sz--; if (sz) cout << ; } cout << n ; } template <typename T1, typename T2> inline void print2(T1 a, T2 b) { cout << a << << b << n ; } template <typename T1, typename T2, typename T3> inline void print3(T1 a, T2 b, T3 c) { cout << a << << b << << c << n ; } void mark() { cout << # << n ; } long long pcount(long long x) { return __builtin_popcountll(x); } const int mod = 998244353; template <typename T> struct BIT { vector<T> dat; long long sz; BIT(long long sz) : sz(sz) { dat.assign(++sz, 0); } T sum(long long k) { T ret = 0; for (++k; k > 0; k -= k & -k) ret += dat[k]; return (ret); } void add(long long k, T x) { for (++k; k < dat.size(); k += k & -k) dat[k] += x; } long long get(T k) { if (k <= 0) return 0; long long ret = 0; int n = 1; while (n < sz) n *= 2; for (int i = n / 2; i > 0; i /= 2) { if (ret + i < sz && dat[ret + i] < k) { k -= dat[ret + i]; ret += i; } } return ret; } }; void solve() { int n, m; cin >> n >> m; vector<pair<long long, long long>> a(n * m); vector<long long> b(n * m); for (int i = 0; i < (n * m); i++) { cin >> a[i].first; a[i].second = i; b[i] = a[i].first; } sort((a).begin(), (a).end()); vector<vector<long long>> c(n, vector<long long>(m)); for (int i = 0; i < (n); i++) for (int j = 0; j < (m); j++) { c[i][j] = a[i * m + j].second; } for (int i = 0; i < (n); i++) for (int j = 0; j < (m); j++) { int k = j + 1; while (k < m && b[c[i][k]] == b[c[i][j]]) k++; reverse(c[i].begin() + j, c[i].begin() + k); j = k - 1; } vector<pair<long long, long long>> pos(n * m); for (int i = 0; i < (n); i++) for (int j = 0; j < (m); j++) { pos[c[i][j]] = {i, j}; } long long ans = 0; vector<BIT<long long>> bit(n, BIT<long long>(m)); for (int i = 0; i < (n * m); i++) { ans += bit[pos[i].first].sum(pos[i].second); bit[pos[i].first].add(pos[i].second, 1); } cout << ans << n ; } int main() { cin.tie(nullptr); ios::sync_with_stdio(false); int t = 1; cin >> t; while (t--) { solve(); } } |
#include<bits/stdc++.h> using namespace std; typedef unsigned long long int ull; typedef long long int ll; typedef long double ld; #define PB push_back #define MP make_pair #define F first #define S second #define Pair vector<pair<ll,ll>> #define vec vector <ll> #define all(a) a.begin(),a.end() #define mo 1000000007 #define decimal(i,n) fixed << setprecision(i) << n #define show(a) for(auto xyz:a)cout<<xyz<< ;cout<<endl; #define show_nl(a) for(auto xyz:a)cout<<xyz<<endl; #define MAX (ll)(pow(2,63)-1) #define fill(a,b) memset(a, b, sizeof(a)) #define yes cout<< YES <<endl; #define no cout<< NO <<endl; //modular inverse void eea(ll a,ll b,ll &x,ll &y) { if (a == 1) { x = 1; y = 0; return; } ll x1, y1; eea(b%a,a,x1,y1); x=y1-(b/a)*x1; y=x1; } ll mi(ll a,ll m) { ll x,y; eea(a,m,x,y); x= (x%m+m)%m; return x; } //complete void Sieve(int n) { int prime[n+1]; fill(prime,-1); for (int p=2; p*p<=n; p++) { if (prime[p] == -1) { for (int i=p*p; i<=n; i += p) prime[i] = 0; } } for (int p=2; p<=n; p++) { } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); // freopen( ladder.in , r , stdin); // name of input file // freopen( ladder.out , w , stdout); // name of output file // ifstream fin( art.in ); // ofstream fout( art.out ); // fstream file, output; // file.open(R () , ios::in); // add the address of local input file // output.open(R () , ios::out); // add the address of local output file ll t=1,t1=1; cin>>t; while(t--) { ll n; cin>>n; string s; cin>>s; ll t=0,m=0,x=0; for(ll i=0;i<n;i++) { if(s[i]== M ) { m++; } else if(s[i]== T ) { t++; } if(m>t) x=1; } t=0,m=0; for(ll i=n-1;i>=0;i--) { if(s[i]== M ) { m++; } else if(s[i]== T ) { t++; } if(m>t) x=1; } if(2*m!=t) x=1; if(x==1) cout<< NO n ; else cout<< YES n ; } } /* Some helpful points 1.) Calm yourself 2.) check for semicolon or data type mismatch 3.) It can be solved */ |
`timescale 10ns/10ns
module frame_buffer_tb();
// Declare inputs as regs and outputs as wires
reg clk;
reg [15:0] write_address;
reg [15:0] data_in;
reg load;
reg [10:0] vga_h;
reg [10:0] vga_v;
wire pixel_out;
frame_buffer U0(
.clk(clk),
.write_address(write_address),
.data_in(data_in),
.load(load),
.vga_h(vga_h),
.vga_v(vga_v),
.pixel_out(pixel_out)
);
// Initialize all variables
initial begin
clk = 1;
#2
write_address = 16'h00_00;
data_in = 16'b1101_1110_1110_1101;
load = 1;
#2
write_address = 16'h00_01;
data_in = 16'b0000_0000_0000_0111;
load = 1;
#4
load = 0;
vga_h = 10'd0;
vga_v = 10'd0;
#4
vga_h = 10'd1;
vga_v = 10'd0;
#4
vga_h = 10'd2;
vga_v = 10'd0;
#4
vga_h = 10'd3;
vga_v = 10'd0;
#4
vga_h = 10'd4;
vga_v = 10'd0;
#4
vga_h = 10'd5;
vga_v = 10'd0;
#4
vga_h = 10'd6;
vga_v = 10'd0;
#4
vga_h = 10'd7;
vga_v = 10'd0;
#4
vga_h = 10'd8;
vga_v = 10'd0;
#4
vga_h = 10'd9;
vga_v = 10'd0;
#4
vga_h = 10'd10;
vga_v = 10'd0;
#4
vga_h = 10'd11;
vga_v = 10'd0;
#4
vga_h = 10'd12;
vga_v = 10'd0;
#4
vga_h = 10'd13;
vga_v = 10'd0;
#4
vga_h = 10'd14;
vga_v = 10'd0;
#4
vga_h = 10'd15;
vga_v = 10'd0;
#4
vga_h = 10'd16;
vga_v = 10'd0;
#4
vga_h = 10'd17;
vga_v = 10'd0;
#4
vga_h = 10'd18;
vga_v = 10'd0;
#4
vga_h = 10'd19;
vga_v = 10'd0;
//#110
//$stop; // Terminate simulation
end
always begin
#1 clk = !clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; for (int i = 0; i < k; i++) { if (n % 10 > 0) { n--; } else n /= 10; } cout << n; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module hls_saturation_enqcK #(
parameter
ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
)(
input [27 : 0] din0,
input [27 : 0] din1,
input [27 : 0] din2,
input [27 : 0] din3,
input [1 : 0] din4,
output [27 : 0] dout);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [27 : 0] mux_1_0;
wire [27 : 0] mux_1_1;
// level 2 signals
wire [27 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din0 : din1;
assign mux_1_1 = (sel[0] == 0)? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxm = 3e5 + 5; const long long mod = 998244353; long long fac[maxm], inv[maxm]; long long l[maxm], r[maxm]; pair<long long, long long> p[25]; long long sum[maxm][45]; long long num[maxm]; long long n, m; long long ppow(long long a, long long b, long long mod) { long long ans = 1 % mod; a %= mod; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } void init() { fac[0] = 1; for (long long i = 1; i < maxm; i++) fac[i] = fac[i - 1] * i % mod; inv[maxm - 1] = ppow(fac[maxm - 1], mod - 2, mod); for (long long i = maxm - 2; i >= 0; i--) inv[i] = inv[i + 1] * (i + 1) % mod; } long long cal(long long x) { long long ans = 0; while (x) { ans++; x &= (x - 1); } return ans; } long long C(long long n, long long m) { if (m < 0 || m > n) return 0; return fac[n] * inv[m] % mod * inv[n - m] % mod; } signed main() { ios::sync_with_stdio(0); init(); cin >> n >> m; for (long long i = 1; i <= n; i++) { cin >> l[i] >> r[i]; } for (long long i = 0; i < m; i++) { cin >> p[i].first >> p[i].second; } for (long long i = 1; i <= n; i++) { num[l[i]]++; num[r[i] + 1]--; } for (long long i = 1; i <= n; i++) { num[i] += num[i - 1]; } for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= m * 2; j++) { sum[i][j] = (sum[i - 1][j] + C(num[i] - j, i - j)) % mod; } } long long ans = 0; for (long long i = 0; i < (1 << m); i++) { set<long long> s; for (long long j = 0; j < m; j++) { if (i >> j & 1) { s.insert(p[j].first); s.insert(p[j].second); } } long long tot = s.size(); long long L = 1, R = n; for (auto x : s) { L = max(L, l[x]); R = min(R, r[x]); } if (L > R) continue; long long t = (sum[R][tot] - sum[L - 1][tot] + mod) % mod; if (cal(i) & 1) { ans = (ans - t + mod) % mod; } else { ans = (ans + t) % mod; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class TH> void _dbg(const char *sdbg, TH h) { cerr << sdbg << = << h << endl; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cerr << *sdbg++; cerr << = << h << , ; _dbg(sdbg + 1, a...); } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> p) { return os << ( << p.first << , << p.second << ) ; } template <class Iterable, class = typename enable_if<!is_same<string, Iterable>::value>::type> auto operator<<(ostream &os, Iterable v) -> decltype(os << *begin(v)) { os << [ ; for (auto vv : v) os << vv << , ; return os << ] ; } const int inf = 0x3f3f3f3f; const long long infll = 0x3f3f3f3f3f3f3f3fll; template <class T> int sign(T x) { return (x > 0) - (x < 0); } template <class T> T abs(const T &x) { return (x < T(0)) ? -x : x; } template <class T> T gcd(T a, T b, T &x, T &y) { if (b == 0) { x = 1; y = 0; return a; } T x1, y1; T d = gcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } template <class T> T mod_inverse(T a, T m) { T x, y; assert(gcd(a, m, x, y) == 1); return (x % m + m) % m; } template <long long mod> struct mod_num { long long x; explicit mod_num(long long x = 0) : x(x % mod) {} mod_num operator+(mod_num b) { return mod_num(x + b.x); } mod_num operator-(mod_num b) { return mod_num(x - b.x + mod); } mod_num operator*(mod_num b) { return mod_num(x * b.x); } mod_num operator/(mod_num b) { return mod_num(x * mod_inverse(b.x, mod)); } mod_num operator^(long long e) { mod_num ans(1); mod_num b = *this; for (; e; b = b * b, e /= 2) if (e & 1) ans = ans * b; return ans; } void operator+=(mod_num b) { x = (x + b.x) % mod; } }; template <long long mod> ostream &operator<<(ostream &os, mod_num<mod> x) { return os << x.x; } vector<int> graph[512345]; int been[512345]; vector<int> st; vector<vector<int>> rings; vector<pair<int, int>> edges; mod_num<1000000007> vertex_rings_factor[512345]; void dfs(int a, int p) { been[a] = 1; st.push_back(a); for (int i = 0; i < ((int)(graph[a]).size()); i++) { if (graph[a][i] != p) { if (been[graph[a][i]] == 0) dfs(graph[a][i], a); else if (been[graph[a][i]] == 1) { vector<int> tmp; for (int j = ((int)(st).size()) - 1; st[j] != graph[a][i]; j--) tmp.push_back(st[j]); tmp.push_back(graph[a][i]); rings.push_back(tmp); } } } st.pop_back(); been[a] = 2; } bool intersect(const vector<int> &v1, const vector<int> &v2) { for (int i = 0; i < ((int)(v1).size()); i++) if (find(v2.begin(), v2.end(), v1[i]) != v2.end()) return true; return false; } int main() { cin.sync_with_stdio(0); cin.tie(0); int n, m, a, b; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> a >> b; edges.push_back({min(a, b), max(a, b)}); graph[a].push_back(b); graph[b].push_back(a); } dfs(1, 1); vector<mod_num<1000000007>> pot2div(max(11, n + 1)); pot2div[0] = mod_num<1000000007>(1); pot2div[1] = pot2div[0] / mod_num<1000000007>(2); for (int i = 2; i < ((int)(pot2div).size()); i++) pot2div[i] = pot2div[i - 1] * pot2div[1]; mod_num<1000000007> sum_rings_factors(0); for (int i = 0; i < ((int)(rings).size()); i++) { sum_rings_factors += pot2div[((int)(rings[i]).size())]; for (int x : rings[i]) { vertex_rings_factor[x] += pot2div[((int)(rings[i]).size())]; } } vector<mod_num<1000000007>> intersecting_rings_factors(((int)(rings).size())); for (int i = 0; i < ((int)(rings).size()); i++) for (int x : rings[i]) intersecting_rings_factors[i] += vertex_rings_factor[x] - pot2div[((int)(rings[i]).size())]; mod_num<1000000007> ex = (mod_num<1000000007>(2) ^ 0) * mod_num<1000000007>(n) / mod_num<1000000007>(2) - mod_num<1000000007>(m) / mod_num<1000000007>(4); for (int i = 0; i < ((int)(rings).size()); i++) ex += pot2div[((int)(rings[i]).size())]; mod_num<1000000007> ex2(0); mod_num<1000000007> ev2 = mod_num<1000000007>(n) * mod_num<1000000007>(n - 1) / (mod_num<1000000007>(2) ^ 2) + mod_num<1000000007>(n) / (mod_num<1000000007>(2) ^ 1); mod_num<1000000007> ee2(0); for (int i = 0; i < m; i++) { ee2 += pot2div[2]; ee2 += mod_num<1000000007>(((int)(graph[edges[i].first]).size()) + ((int)(graph[edges[i].second]).size()) - 2) * pot2div[3]; ee2 += mod_num<1000000007>(m - (((int)(graph[edges[i].first]).size()) + ((int)(graph[edges[i].second]).size()) - 1)) * pot2div[4]; } mod_num<1000000007> er2(0); for (int i = 0; i < ((int)(rings).size()); i++) { er2 += pot2div[((int)(rings[i]).size())]; er2 += pot2div[((int)(rings[i]).size()) - 1] * intersecting_rings_factors[i]; er2 += pot2div[((int)(rings[i]).size())] * (sum_rings_factors - intersecting_rings_factors[i] - pot2div[((int)(rings[i]).size())]); } mod_num<1000000007> eve; for (int i = 1; i <= n; i++) { eve += mod_num<1000000007>(((int)(graph[i]).size())) * pot2div[2]; eve += mod_num<1000000007>(m - ((int)(graph[i]).size())) * pot2div[3]; } mod_num<1000000007> eer; for (int j = 0; j < ((int)(rings).size()); j++) { int k = ((int)(rings[j]).size()); eer += mod_num<1000000007>(((int)(rings[j]).size())) * pot2div[((int)(rings[j]).size())]; for (int x : rings[j]) { eer += mod_num<1000000007>(((int)(graph[x]).size()) - 2) * pot2div[((int)(rings[j]).size()) + 1]; k += ((int)(graph[x]).size()) - 2; } eer += mod_num<1000000007>(m - k) * pot2div[((int)(rings[j]).size()) + 2]; } mod_num<1000000007> evr; for (int i = 1; i <= n; i++) { evr += vertex_rings_factor[i]; evr += (sum_rings_factors - vertex_rings_factor[i]) * pot2div[1]; } ex2 = ev2 + ee2 + er2 - mod_num<1000000007>(2) * eve - mod_num<1000000007>(2) * eer + mod_num<1000000007>(2) * evr; cout << (mod_num<1000000007>(2) ^ (1000000007)) * (ex2 - ex * ex) * (mod_num<1000000007>(2) ^ (1000000005)) << endl; } |
#include <bits/stdc++.h> using namespace std; int tt; string input; int main() { cin >> tt; for (int qq = 1; qq <= tt; qq++) { cin >> input; int count[250] = {}; for (char c : input) count[c - a ]++; int diff = 0; for (int i = 0; i < 250; i++) { if (count[i] > 0) diff++; } if (diff == 1) cout << -1 << endl; else { sort(input.begin(), input.end()); cout << input << endl; } } return 0; } |
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: OWM.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// Rev: Added Overdrive, Bit control, and strong pullup control --
// along with many other features described in the new spec --
// released version 2.0 9/5/01 - Greg Glennon --
// Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module OWM (
ADDRESS, ADS_bar, CLK, EN_bar, MR, RD_bar, WR_bar, /*DDIR, DOUT,*/ INTR,
STPZ, DATA_IN, DATA_OUT,
DQ0_T, DQ1_T, DQ2_T, DQ3_T, DQ4_T, DQ5_T, DQ6_T, DQ7_T,
DQ0_O, DQ1_O, DQ2_O, DQ3_O, DQ4_O, DQ5_O, DQ6_O, DQ7_O,
DQ0_I, DQ1_I, DQ2_I, DQ3_I, DQ4_I, DQ5_I, DQ6_I, DQ7_I);
input [2:0] ADDRESS; // SFR address
input ADS_bar; // address latch control (active low)
input CLK; // system clock
input EN_bar; // SFR access enable (active low)
input MR; // master reset
input RD_bar; // SFR read (active low)
input WR_bar; // SFR write (active low)
//output DDIR;
//output [7:0] DOUT;
output INTR; // one wire master interrupt
output STPZ; // strong pullup (active low)
input [7:0] DATA_IN; // input DATA bus
output [7:0] DATA_OUT; // output DATA bus
output DQ0_T;
output DQ1_T;
output DQ2_T;
output DQ3_T;
output DQ4_T;
output DQ5_T;
output DQ6_T;
output DQ7_T;
output DQ0_O;
output DQ1_O;
output DQ2_O;
output DQ3_O;
output DQ4_O;
output DQ5_O;
output DQ6_O;
output DQ7_O;
input DQ0_I;
input DQ1_I;
input DQ2_I;
input DQ3_I;
input DQ4_I;
input DQ5_I;
input DQ6_I;
input DQ7_I;
wire [2:0] dq_sel;
wire [7:0] DIN;
wire [7:0] DOUT;
wire [7:0] rcvr_buffer;
wire [7:0] xmit_buffer;
wire [2:0] ADDRESS;
wire clk_1us;
one_wire_io xone_wire_io
(
.CLK(CLK),
.DDIR(DDIR),
.DOUT(DOUT),
.DQ_CONTROL(DQ_CONTROL),
.MR(MR),
.DIN(DIN),
.DQ_IN(DQ_IN),
.DATA_IN(DATA_IN),
.DATA_OUT(DATA_OUT),
.DQ0_T(DQ0_T),
.DQ0_O(DQ0_O),
.DQ0_I(DQ0_I),
.DQ1_T(DQ1_T),
.DQ1_O(DQ1_O),
.DQ1_I(DQ1_I),
.DQ2_T(DQ2_T),
.DQ2_O(DQ2_O),
.DQ2_I(DQ2_I),
.DQ3_T(DQ3_T),
.DQ3_O(DQ3_O),
.DQ3_I(DQ3_I),
.DQ4_T(DQ4_T),
.DQ4_O(DQ4_O),
.DQ4_I(DQ4_I),
.DQ5_T(DQ5_T),
.DQ5_O(DQ5_O),
.DQ5_I(DQ5_I),
.DQ6_T(DQ6_T),
.DQ6_O(DQ6_O),
.DQ6_I(DQ6_I),
.DQ7_T(DQ7_T),
.DQ7_O(DQ7_O),
.DQ7_I(DQ7_I),
.DQ_SEL(dq_sel)
);
clk_prescaler xclk_prescaler
(
.CLK(CLK),
.CLK_EN(CLK_EN),
.div_1(div_1),
.div_2(div_2),
.div_3(div_3),
.MR(MR),
.pre_0(pre_0),
.pre_1(pre_1),
.clk_1us(clk_1us)
);
one_wire_interface xone_wire_interface
(
.ADDRESS(ADDRESS),
.ADS_bar(ADS_bar),
.clear_interrupts(clear_interrupts),
.DIN(DIN),
.DQ_IN(DQ_IN),
.EN_bar(EN_bar),
.FSM_CLK(FSM_CLK),
.MR(MR),
.OneWireIO_eq_Load(OneWireIO_eq_Load),
.pdr(pdr),
.OW_LOW(OW_LOW),
.OW_SHORT(OW_SHORT),
.rbf(rbf),
.rcvr_buffer(rcvr_buffer),
.RD_bar(RD_bar),
.reset_owr(reset_owr),
.rsrf(rsrf),
.temt(temt),
.WR_bar(WR_bar),
.BIT_CTL(BIT_CTL),
.CLK_EN(CLK_EN),
.clr_activate_intr(clr_activate_intr),
.DDIR(DDIR),
.div_1(div_1),
.div_2(div_2),
.div_3(div_3),
.DOUT(DOUT),
.EN_FOW(EN_FOW),
.EOWL(EOWL),
.EOWSH(EOWSH),
.epd(epd),
.erbf(erbf),
.ersf(ersf),
.etbe(etbe),
.etmt(etmt),
.FOW(FOW),
.ias(ias),
.LLM(LLM),
.OD(OD),
.owr(owr),
.pd(pd),
.PPM(PPM),
.pre_0(pre_0),
.pre_1(pre_1),
.rbf_reset(rbf_reset),
.sr_a(sr_a),
.STP_SPLY(STP_SPLY),
.STPEN(STPEN),
.tbe(tbe),
.xmit_buffer(xmit_buffer),
.dq_sel(dq_sel)
);
onewiremaster xonewiremaster(
.BIT_CTL(BIT_CTL),
.clk(CLK),
.clk_1us_en(clk_1us),
.clr_activate_intr(clr_activate_intr),
.DQ_IN(DQ_IN),
.EN_FOW(EN_FOW),
.EOWL(EOWL),
.EOWSH(EOWSH),
.epd(epd),
.erbf(erbf),
.ersf(ersf),
.etbe(etbe),
.etmt(etmt),
.FOW(FOW),
.ias(ias),
.LLM(LLM),
.MR(MR),
.OD(OD),
.owr(owr),
.pd(pd),
.PPM(PPM),
.rbf_reset(rbf_reset),
.sr_a(sr_a),
.STP_SPLY(STP_SPLY),
.STPEN(STPEN),
.tbe(tbe),
.xmit_buffer(xmit_buffer),
.clear_interrupts(clear_interrupts),
.DQ_CONTROL(DQ_CONTROL),
.FSM_CLK(FSM_CLK),
.INTR(INTR),
.OneWireIO_eq_Load(OneWireIO_eq_Load),
.OW_LOW(OW_LOW),
.OW_SHORT(OW_SHORT),
.pdr(pdr),
.rbf(rbf),
.rcvr_buffer(rcvr_buffer),
.reset_owr(reset_owr),
.rsrf(rsrf),
.STPZ(STPZ),
.temt(temt)
);
//synthesis attribute clock_signal of clk_1us IS no
//synthesis attribute buffer_type of clk_1us IS none
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 105; const double EPS = 1e-9; int n, k; double e; int px0, py0; int x[MAXN], y[MAXN]; double dp[MAXN][2]; double dist(int x1, int y1, int x2, int y2) { return sqrt(pow(x1 - x2, 2) + pow(y1 - y2, 2)); } double prob(int ind, double rad) { double _dist = dist(x[ind], y[ind], px0, py0); if (_dist <= rad) return 1; return exp(1 - pow(_dist, 2) / pow(rad, 2)); } bool check(double rad) { for (int i = 0; i < MAXN; i++) dp[i][0] = dp[i][1] = 0; dp[0][0] = 1; for (int i = 0; i < n; i++) { double p = prob(i, rad); for (int j = 0; j < MAXN - 1; j++) { dp[j + 1][1] += dp[j][0] * p; dp[j][1] += dp[j][0] * (1 - p); } for (int j = 0; j < MAXN; j++) dp[j][0] = dp[j][1], dp[j][1] = 0; } double sum = 0; for (int i = 0; i < k; i++) sum += dp[i][0]; return sum < e; } int main() { ios ::sync_with_stdio(0); if (fopen( input.txt , r )) freopen( input.txt , r , stdin); cin >> n >> k; int _e; cin >> _e; e = 1. * _e / 1000; cin >> px0 >> py0; for (int i = 0; i < n; i++) cin >> x[i] >> y[i]; double lo = 0, hi = 5000; while (abs(hi - lo) > 2 * EPS) { double mid = (lo + hi) / 2; if (check(mid)) hi = mid; else lo = mid + EPS; } cout << fixed << setprecision(10) << lo << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1005]; int main() { int n, maxp, mx2p; scanf( %d , &n); for (register int i = 1; i <= n; ++i) { scanf( %d , a + i); } if (a[1] > a[2]) { maxp = 1; mx2p = 2; } else { maxp = 2; mx2p = 1; } for (register int i = 3; i <= n; ++i) { if (a[i] > a[maxp]) { mx2p = maxp; maxp = i; } else if (a[i] > a[mx2p]) { mx2p = i; } } printf( %d %d , maxp, a[mx2p]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, mod = 1e9 + 7, L = 20; vector<int> G[N], g[N]; int h[N], x[5 * N], y[5 * N], par[N][L]; map<int, bool> mp[N]; void dfs(int v, int p) { par[v][0] = p; for (int i = 1; i < L; i++) par[v][i] = par[par[v][i - 1]][i - 1]; for (int u : g[v]) if (u != p && h[u] == -1) h[u] = h[v] + 1; for (int u : g[v]) if (h[u] == h[v] + 1) dfs(u, v); } int pr(int v, int x) { for (int i = 0; i < L; i++) if ((1 << i) & x) v = par[v][i]; return v; } int lca(int u, int v) { if (h[u] > h[v]) swap(u, v); v = pr(v, h[v] - h[u]); if (u == v) return v; for (int i = L - 1; i >= 0; i--) if (par[v][i] != par[u][i]) u = par[u][i], v = par[v][i]; return par[v][0]; } int solve(int u, int v) { int p = lca(u, v); int ret = h[u] + h[v] - 2 * h[p]; if (p == u || p == v) return ret; int x = pr(u, h[u] - h[p] - 1), y = pr(v, h[v] - h[p] - 1); if (x > y) swap(x, y); if (mp[x][y]) ret--; return ret; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(h, -1, sizeof(h)); int n, m, q; cin >> n >> m >> q; h[0] = 0; for (int i = 0; i < m; i++) { cin >> x[i] >> y[i]; x[i]--; y[i]--; if (x[i] > y[i]) swap(x[i], y[i]); g[x[i]].push_back(y[i]); g[y[i]].push_back(x[i]); mp[x[i]][y[i]] = true; } dfs(0, 0); for (int i = 0; i < q; i++) { int x, y; cin >> x >> y; x--; y--; cout << solve(x, y) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n, x; cin >> n >> x; string second; cin >> second; long long ans = 0; long long sm = 0; for (long long i = 0; i < n; i++) { if (second[i] == 0 ) sm++; else sm--; } long long c = 0; for (long long i = 0; i < n; i++) { if (sm == 0 && c == x) { cout << -1 << endl; return; } if ((x - c) % sm == 0 && (x - c) / sm >= 0 && sm != 0) ans++; if (second[i] == 0 ) c++; else c--; } cout << ans << endl; } int main() { long long t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; if (n * m % 2 == 1) cout << n * m / 2 + 1 << endl; else cout << n * m / 2 << endl; } } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev_lpddr2 altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 320.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "3125 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "low";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "false";
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = int(1e9) + 7; int debug = 0; const int N = int(2e3) + 5; using namespace std; int a[N], b[N], p[N]; int main() { int i, j, n, t; ios::sync_with_stdio(false); cin >> n; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n; i++) cin >> b[i]; int ans = 0; vector<pair<int, int> > moves; for (i = 0; i < n; i++) p[a[i]] = i; for (i = 0; i < n; i++) { int pos = -1; for (j = 0; j < n; j++) if (debug) cerr << j << : << j << | << b[j] << : << b[j] << endl; ; for (j = 0; j < n; j++) if (p[b[j]] == i) pos = j; if (j == i) continue; if (debug) cerr << pos << : << pos << | << i << : << i << endl; ; int cur = pos; for (j = pos - 1; j >= i; j--) { if (p[b[j]] >= cur) { ans += cur - j; moves.push_back(make_pair(j, cur)); b[cur] = b[j]; b[j] = i; cur = j; } } } cout << ans << n ; reverse(moves.begin(), moves.end()); cout << moves.size() << n ; for (i = 0; i < moves.size(); i++) cout << moves[i].second + 1 << << moves[i].first + 1 << n ; } |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module ip_arp
#(parameter NUM_QUEUES = 8,
parameter LUT_DEPTH = `ROUTER_OP_LUT_ARP_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to ip_arp
input [31:0] next_hop_ip,
input [NUM_QUEUES-1:0] lpm_output_port,
input lpm_vld,
input lpm_hit,
// --- interface to process block
output [47:0] next_hop_mac,
output [NUM_QUEUES-1:0] output_port,
output arp_mac_vld,
output arp_lookup_hit,
output lpm_lookup_hit,
input rd_arp_result,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] arp_rd_addr, // address in table to read
input arp_rd_req, // request a read
output [47:0] arp_rd_mac, // data read from the LUT at rd_addr
output [31:0] arp_rd_ip, // ip to match in the CAM
output arp_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] arp_wr_addr,
input arp_wr_req,
input [47:0] arp_wr_mac,
input [31:0] arp_wr_ip, // data to match in the CAM
output arp_wr_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//--------------------- Internal Parameter-------------------------
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
wire [47:0] next_hop_mac_result;
wire empty;
reg [NUM_QUEUES-1:0] output_port_latched;
reg lpm_hit_latched;
//------------------------- Modules-------------------------------
// 1 cycle read latency, 2 cycles write latency
/*
bram_cam_unencoded_32x32 arp_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
// wire cam_busy_signal_reg;
cam arp_cam
(
.reset(reset),
.wr_clk(clk),
.wr_en(cam_we),
.wr_key(cam_din),
.wr_index(cam_wr_addr),
.wr_erase_n(1'b1),
.rd_clk(clk),
.rd_en(lpm_vld),
.rd_key(cam_cmp_din),
.one_hot_addr(cam_match_addr),
.match_addr(),
.match(cam_match),
.multi_match(),
.index_reg(),
.cam_full(),
.multi_index()
);
//assign cam_busy = cam_busy_signal_reg;
//assign cam_busy = 1'b0;
localparam
IDLE_STATE_CAM = 2'b00,
FIRST_STATE_CAM = 2'b01,
SECOND_STATE_CAM = 2'b10;
reg [1:0] state_cam,state_cam_nxt;
reg cam_busy_signal_reg,cam_busy_signal_reg_next;
always @(posedge clk) begin
if (reset) begin
state_cam <= IDLE_STATE_CAM;
cam_busy_signal_reg <= 1'b0;
end
else begin
state_cam <= state_cam_nxt;
cam_busy_signal_reg <= cam_busy_signal_reg_next;
end // else
end
always @(*) begin
cam_busy_signal_reg_next = cam_busy_signal_reg;
state_cam_nxt = state_cam;
case (state_cam)
IDLE_STATE_CAM: begin
if (cam_we) begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = FIRST_STATE_CAM;
end
else
cam_busy_signal_reg_next = 1'b0;
end
FIRST_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = SECOND_STATE_CAM;
end
SECOND_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b0;
state_cam_nxt = IDLE_STATE_CAM;
end
endcase // case(state)
end
assign cam_busy = cam_busy_signal_reg;
unencoded_cam_lut_sm
#(.CMP_WIDTH(32), // IPv4 addr width
.DATA_WIDTH(48),
.LUT_DEPTH(LUT_DEPTH)
) cam_lut_sm
(// --- Interface for lookups
.lookup_req (lpm_vld),
.lookup_cmp_data (next_hop_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lookup_ack),
.lookup_hit (lookup_hit),
.lookup_data (next_hop_mac_result),
// --- Interface to registers
// --- Read port
.rd_addr (arp_rd_addr), // address in table to read
.rd_req (arp_rd_req), // request a read
.rd_data (arp_rd_mac), // data found for the entry
.rd_cmp_data (arp_rd_ip), // matching data for the entry
.rd_cmp_dmask (), // don't cares entry
.rd_ack (arp_rd_ack), // pulses high
// --- Write port
.wr_addr (arp_wr_addr),
.wr_req (arp_wr_req),
.wr_data (arp_wr_mac), // data found for the entry
.wr_cmp_data (arp_wr_ip), // matching data for the entry
.wr_cmp_dmask (32'h0), // don't cares for the entry
.wr_ack (arp_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
fallthrough_small_fifo #(.WIDTH(50+NUM_QUEUES), .MAX_DEPTH_BITS (2))
arp_fifo
(.din ({next_hop_mac_result, output_port_latched, lookup_hit, lpm_hit_latched}), // Data in
.wr_en (lookup_ack), // Write enable
.rd_en (rd_arp_result), // Read the next word
.dout ({next_hop_mac, output_port, arp_lookup_hit, lpm_lookup_hit}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic --------------------------------
assign arp_mac_vld = !empty;
always @(posedge clk) begin
if(reset) begin
output_port_latched <= 0;
lpm_hit_latched <= 0;
end
else if(lpm_vld) begin
output_port_latched <= lpm_output_port;
lpm_hit_latched <= lpm_hit;
end
end
endmodule // ip_arp
|
module GPIO_Board_test(CLOCK_50, GPIO0_D);
input CLOCK_50;
output [31:0] GPIO0_D;
wire [31:0]count;
count_32bit counter1(CLOCK_50, count);
wire GPIO_clock;
assign GPIO_clock = CLOCK_50;
wire [15:0]R0, R1, R2, R3, R4, R5, R6, R7;
assign R0 = {count[31:24], count[31:24]};
assign R1 = {count[31:28], count[31:28], count[31:28], count[31:28]};
assign R2 = {count[27:24], count[27:24], count[27:24], count[27:24]};
assign R3 = {count[27:24], count[31:28], count[27:24], count[31:28]};
assign R4 = ~R3;
assign R5 = ~R2;
assign R6 = ~R1;
assign R7 = ~R0;
wire HEX0_DP, HEX1_DP, HEX2_DP, HEX3_DP, HEX4_DP, HEX5_DP, HEX6_DP, HEX7_DP;
assign HEX0_DP = count[27];
assign HEX1_DP = ~count[27];
assign HEX2_DP = count[27];
assign HEX3_DP = ~count[27];
assign HEX4_DP = count[27];
assign HEX5_DP = ~count[27];
assign HEX6_DP = count[27];
assign HEX7_DP = ~count[27];
wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire [2:0] HEX_seg_count;
assign HEX_seg_count = count[28:26];
decoder3to8 d0(HEX_seg_count,HEX0[0],HEX0[1],HEX0[2],HEX0[3],HEX0[4],HEX0[5],HEX0[6]);
decoder3to8 d1(HEX_seg_count,HEX1[1],HEX1[2],HEX1[3],HEX1[4],HEX1[5],HEX1[6],HEX1[0]);
decoder3to8 d2(HEX_seg_count,HEX2[2],HEX2[3],HEX2[4],HEX2[5],HEX2[6],HEX2[0],HEX2[1]);
decoder3to8 d3(HEX_seg_count,HEX3[3],HEX3[4],HEX3[5],HEX3[6],HEX3[0],HEX3[1],HEX3[2]);
decoder3to8 d4(HEX_seg_count,HEX4[4],HEX4[5],HEX4[6],HEX4[0],HEX4[1],HEX4[2],HEX4[3]);
decoder3to8 d5(HEX_seg_count,HEX5[5],HEX5[6],HEX5[0],HEX5[1],HEX5[2],HEX5[3],HEX5[4]);
decoder3to8 d6(HEX_seg_count,HEX6[6],HEX6[0],HEX6[1],HEX6[2],HEX6[3],HEX6[4],HEX6[5]);
decoder3to8 d7(HEX_seg_count,HEX7[0],HEX7[1],HEX7[2],HEX7[3],HEX7[4],HEX7[5],HEX7[6]);
GPIO_Board DUT(
GPIO_clock,
R0, R1, R2, R3, R4, R5, R6, R7,
HEX0, HEX0_DP, HEX1, HEX1_DP,
HEX2, HEX2_DP, HEX3, HEX3_DP,
HEX4, HEX4_DP, HEX5, HEX5_DP,
HEX6, HEX6_DP, HEX7, HEX7_DP, GPIO0_D);
endmodule
module count_32bit(clock, out);
input clock;
output reg [31:0]out;
always @(posedge clock)
out <= out + 1'b1;
endmodule
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_axi_axi
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input inport_write_i
,input [ 31:0] inport_addr_i
,input [ 3:0] inport_id_i
,input [ 7:0] inport_len_i
,input [ 1:0] inport_burst_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_bready_i
,input inport_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport_accept_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-------------------------------------------------------------
// Write burst tracking
//-------------------------------------------------------------
reg [7:0] req_cnt_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
req_cnt_q <= 8'b0;
else if (inport_valid_i && inport_write_i && inport_accept_o)
begin
if (req_cnt_q != 8'b0)
req_cnt_q <= req_cnt_q - 8'd1;
else
req_cnt_q <= inport_len_i;
end
//-------------------------------------------------------------
// Request skid buffer
//-------------------------------------------------------------
reg valid_q;
reg [83:0] buf_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
valid_q <= 1'b0;
else if (inport_valid_i && inport_accept_o && ((outport_awvalid_o && !outport_awready_i) || (outport_wvalid_o && !outport_wready_i) || (outport_arvalid_o && !outport_arready_i)))
valid_q <= 1'b1;
else if ((!outport_awvalid_o || outport_awready_i) && (!outport_wvalid_o || outport_wready_i) && (!outport_arvalid_o || outport_arready_i))
valid_q <= 1'b0;
wire inport_valid_w = valid_q || inport_valid_i;
wire inport_write_w = valid_q ? buf_q[0:0] : inport_write_i;
wire [ 31:0] inport_addr_w = valid_q ? buf_q[32:1] : inport_addr_i;
wire [ 3:0] inport_id_w = valid_q ? buf_q[36:33] : inport_id_i;
wire [ 7:0] inport_len_w = valid_q ? buf_q[44:37] : inport_len_i;
wire [ 1:0] inport_burst_w = valid_q ? buf_q[46:45] : inport_burst_i;
wire [ 31:0] inport_wdata_w = valid_q ? buf_q[78:47] : inport_wdata_i;
wire [ 3:0] inport_wstrb_w = valid_q ? buf_q[82:79] : inport_wstrb_i;
wire inport_wlast_w = valid_q ? buf_q[83:83] : (inport_len_i == 8'd0 && req_cnt_q == 8'd0) || (req_cnt_q == 8'd1);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
buf_q <= 84'b0;
else
buf_q <= {inport_wlast_w, inport_wstrb_w, inport_wdata_w, inport_burst_w, inport_len_w, inport_id_w, inport_addr_w, inport_write_w};
wire skid_busy_w = valid_q;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
reg awvalid_q;
reg wvalid_q;
reg wlast_q;
wire wr_cmd_accepted_w = (outport_awvalid_o && outport_awready_i) || awvalid_q;
wire wr_data_accepted_w = (outport_wvalid_o && outport_wready_i) || wvalid_q;
wire wr_data_last_w = (wvalid_q & wlast_q) || (outport_wvalid_o && outport_wready_i && outport_wlast_o);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_q <= 1'b0;
else if (outport_awvalid_o && outport_awready_i && (!wr_data_accepted_w || !wr_data_last_w))
awvalid_q <= 1'b1;
else if (wr_data_accepted_w && wr_data_last_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wlast_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i)
wlast_q <= outport_wlast_o;
assign outport_awvalid_o = (inport_valid_w & inport_write_w & ~awvalid_q);
assign outport_awaddr_o = inport_addr_w;
assign outport_awid_o = inport_id_w;
assign outport_awlen_o = inport_len_w;
assign outport_awburst_o = inport_burst_w;
assign outport_wvalid_o = (inport_valid_w & inport_write_w & ~wvalid_q);
assign outport_wdata_o = inport_wdata_w;
assign outport_wstrb_o = inport_wstrb_w;
assign outport_wlast_o = inport_wlast_w;
assign inport_bvalid_o = outport_bvalid_i;
assign inport_bresp_o = outport_bresp_i;
assign inport_bid_o = outport_bid_i;
assign outport_bready_o = inport_bready_i;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign outport_arvalid_o = inport_valid_w & ~inport_write_w;
assign outport_araddr_o = inport_addr_w;
assign outport_arid_o = inport_id_w;
assign outport_arlen_o = inport_len_w;
assign outport_arburst_o = inport_burst_w;
assign outport_rready_o = inport_rready_i;
assign inport_rvalid_o = outport_rvalid_i;
assign inport_rdata_o = outport_rdata_i;
assign inport_rresp_o = outport_rresp_i;
assign inport_rid_o = outport_rid_i;
assign inport_rlast_o = outport_rlast_i;
//-------------------------------------------------------------
// Accept logic
//-------------------------------------------------------------
assign inport_accept_o = !skid_busy_w &&
((outport_awvalid_o && outport_awready_i) ||
(outport_wvalid_o && outport_wready_i) ||
(outport_arvalid_o && outport_arready_i));
endmodule
|
//pipeBreakU -- Breaks the instruction pipeline down into individual output wires.
//This should also significantly clean up the main CPU code.
module pipeBreakU(
OS1,
OS2,
OS3,
OS4,
OS5,
op1,
op2,
op3,
op4,
op5,
aSel2,
aSel3,
aSel4,
bSel2,
bSel3,
bSel4,
cSel2,
cSel3,
cSel4,
literalV
);
input [15:0] OS1;
input [15:0] OS2;
input [15:0] OS3;
input [15:0] OS4;
input [15:0] OS5;
output [6:0] op1;
output [6:0] op2;
output [6:0] op3;
output [6:0] op4;
output [6:0] op5;
output [2:0] aSel2;
output [2:0] aSel3;
output [2:0] aSel4;
output [2:0] bSel2;
output [2:0] bSel3;
output [2:0] bSel4;
output [2:0] cSel2;
output [2:0] cSel3;
output [2:0] cSel4;
output [14:0] literalV;
assign literalV=OS2[14:0];
assign op1=OS1[15:9];
assign op2=OS2[15:9];
assign op3=OS3[15:9];
assign op4=OS4[15:9];
assign op5=OS5[15:9];
assign aSel2=OS2[8:6];
assign aSel3=OS3[8:6];
assign aSel4=OS4[8:6];
assign bSel2=OS2[5:3];
assign bSel3=OS3[5:3];
assign bSel4=OS4[5:3];
assign cSel2=OS2[2:0];
assign cSel3=OS3[2:0];
assign cSel4=OS4[2:0];
endmodule |
#include <bits/stdc++.h> int main() { int x, y, a, b, cnt = 0; scanf( %d%d%d%d , &x, &y, &a, &b); for (int i = a; i <= x; i++) for (int j = b; j <= y && j < i; j++) cnt++; printf( %d n , cnt); for (int i = a; i <= x; i++) for (int j = b; j <= y && j < i; j++) printf( %d %d n , i, j); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_V |
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/IORegister.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2005-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: IORegister
// Desc: A register which should be packed in to IO pads.
// Author: <a href="http://www.gdgib.com/">Greg Gibeling</a>
// Version: $Revision: 26904 $
//------------------------------------------------------------------------------
module IORegister(Clock, Reset, Set, Enable, In, Out);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 32,
Initial = {Width{1'bx}},
AsyncReset = 0,
AsyncSet = 0,
ResetValue = {Width{1'b0}},
SetValue = {Width{1'b1}};
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Inputs & Outputs
//--------------------------------------------------------------------------
input Clock, Enable, Reset, Set;
input [Width-1:0] In;
output reg [Width-1:0] Out = Initial /* synthesis syn_useioff = 1 iob = true useioff = 1 */;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Behavioral Register
//--------------------------------------------------------------------------
generate if (AsyncReset) begin:AR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Reset or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock or posedge Reset) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end else begin:SR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end endgenerate
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
#include <bits/stdc++.h> int pos = 1 << 17; char buf[1 << 17]; inline char nextch() { if (pos == 1 << 17) fread(buf, 1 << 17, 1, stdin), pos = 0; return buf[pos++]; } inline int read() { char ch; while (!isdigit(ch = nextch())) ; int x = ch - 0 ; while (isdigit(ch = nextch())) x = 10 * x + ch - 0 ; return x; } const int N = 1 << 17; int ab[132000], de[132000], fr[132000], fib[132000]; inline int lgput(int a, int n) { int r = 1; while (n) { if (n % 2) r = 1LL * r * a % 1000000007; n /= 2; a = 1LL * a * a % 1000000007; } return r; } void fwht(int *data, int dim) { for (int len = 1; 2 * len <= dim; len <<= 1) { for (int i = 0; i < dim; i += 2 * len) { for (int j = 0; j < len; j++) { int a = data[i + j]; int b = data[i + j + len]; data[i + j] = a + b; if (data[i + j] >= 1000000007) data[i + j] -= 1000000007; data[i + j + len] = a - b; if (data[i + j + len] < 0) data[i + j + len] += 1000000007; } } } } void to_transform(int dim, int *data) { int len, i, j, u, v; for (len = 1; 2 * len <= dim; len <<= 1) { for (i = 0; i < dim; i += 2 * len) { for (j = 0; j < len; j++) { u = data[i + j]; v = data[i + len + j]; data[i + j] = v; data[i + len + j] = u + v; if (data[i + len + j] >= 1000000007) data[i + len + j] -= 1000000007; } } } } void inv_transform(int dim, int *data) { int len, i, j, u, v; for (len = 1; 2 * len <= dim; len <<= 1) { for (i = 0; i < dim; i += 2 * len) { for (j = 0; j < len; j++) { u = data[i + j]; v = data[i + len + j]; data[i + j] = v - u; data[i + len + j] = u; if (data[i + j] < 0) data[i + j] += 1000000007; } } } } int main() { int n = read(); for (int i = 0; i < n; i++) fr[read()]++; for (int i = 0; i < N; i++) { for (int j = i; j; j = (j - 1) & i) ab[i] = (ab[i] + 1LL * fr[j] * fr[i ^ j]) % 1000000007; ab[i] = (ab[i] + 1LL * fr[0] * fr[i]) % 1000000007; } for (int i = 0; i < N; i++) de[i] = fr[i]; fwht(de, N); for (int i = 0; i < N; i++) de[i] = 1LL * de[i] * de[i] % 1000000007; fwht(de, N); int inv = lgput(N, 1000000007 - 2); for (int i = 0; i < N; i++) de[i] = 1LL * de[i] * inv % 1000000007; fib[1] = 1; for (int i = 2; i < N; i++) { fib[i] = fib[i - 1] + fib[i - 2]; if (fib[i] >= 1000000007) fib[i] -= 1000000007; } for (int i = 0; i < N; i++) ab[i] = 1LL * ab[i] * fib[i] % 1000000007; to_transform(N, ab); for (int i = 0; i < N; i++) fr[i] = 1LL * fr[i] * fib[i] % 1000000007; to_transform(N, fr); for (int i = 0; i < N; i++) ab[i] = 1LL * ab[i] * fr[i] % 1000000007; inv_transform(N, ab); to_transform(N, ab); for (int i = 0; i < N; i++) de[i] = 1LL * de[i] * fib[i] % 1000000007; to_transform(N, de); for (int i = 0; i < N; i++) ab[i] = 1LL * ab[i] * de[i] % 1000000007; inv_transform(N, ab); int ans = 0; for (int i = 1; i < N; i++) if (i - (i & (-i)) == 0) ans = (ans + ab[i]) % 1000000007; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) #pragma comment(linker, /STACK:16777216 ) #pragma warning(disable : 4996) #pragma comment(linker, /STACK:16777216 ) #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) const int inf = 2e9; const long long linf = 5000000000000000000; const long double LDINF = 2e18; template <typename T> void print(vector<T>& a) { for (int i = 0; i < a.size(); i++) cout << a[i] << ; cout << n ; } template <typename T> void print(deque<T>& a) { for (int i = 0; i < a.size(); i++) cout << a[i] << ; cout << n ; } template <typename T> void print(vector<vector<T>>& a) { for (int i = 0; i < a.size(); i++) { for (int j = 0; j < a[i].size(); j++) cout << a[i][j] << ; cout << n ; } } template <typename T> void input(vector<T>& a) { for (int i = 0; i < a.size(); i++) cin >> a[i]; } template <typename T> void input(deque<T>& a) { for (int i = 0; i < a.size(); i++) cin >> a[i]; } template <typename T> void input(vector<vector<T>>& a) { for (int i = 0; i < a.size(); i++) for (int j = 0; j < a[i].size(); j++) cin >> a[i][j]; } long long mod = 998244353; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } vector<int> p, rang; void CreateSet(int v) { p[v] = v; rang[v] = 1; } int FindSet(int v) { if (p[v] == v) return v; return p[v] = FindSet(p[v]); } vector<pair<int, int>> ans; void UnionSet(int a, int b) { a = FindSet(a); b = FindSet(b); if (a == b) return; if (rang[a] < rang[b]) swap(a, b); p[b] = a; if (rang[a] == rang[b]) rang[a]++; ans.push_back({a, b}); } void solve() { long long n, d; cin >> n; long long a = 0, b = 0; for (int i = 0; i < n; i++) { cin >> d; a |= d; } for (int i = 0; i < n; i++) { cin >> d; b |= d; } cout << a + b; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tst = 1; while (tst--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int sizePermute, sizebkp, x, minimum = 100, maximum = 0, maximumIndex, minimumIndex, counter = 0; cin >> sizePermute; sizebkp = sizePermute; vector<int> myvec(sizePermute); myvec.clear(); while (sizePermute != 0) { cin >> x; if (x < minimum) { minimum = x; minimumIndex = counter; } if (x > maximum) { maximum = x; maximumIndex = counter; } myvec.push_back(x); sizePermute--; counter++; } if (maximumIndex == (sizebkp - 1) && minimumIndex == 0) { cout << sizebkp - 1 << endl; return 0; } else if (minimumIndex == (sizebkp - 1) && maximumIndex == 0) { cout << sizebkp - 1 << endl; return 0; } else if (maximumIndex < minimumIndex && (((sizebkp - 1) - minimumIndex) > (maximumIndex - 0))) { cout << sizebkp - 1 - maximumIndex << endl; return 0; } else if (maximumIndex < minimumIndex && (((sizebkp - 1) - minimumIndex) < (maximumIndex - 0))) { cout << minimumIndex << endl; return 0; } else if (maximumIndex > minimumIndex && (((sizebkp - 1) - maximumIndex) > (minimumIndex - 0))) { cout << sizebkp - 1 - minimumIndex << endl; return 0; } else if (maximumIndex > minimumIndex && (((sizebkp - 1) - maximumIndex) < (minimumIndex - 0))) { cout << maximumIndex << endl; return 0; } else if (maximumIndex > minimumIndex && (((sizebkp - 1) - maximumIndex) == (minimumIndex - 0))) { cout << sizebkp - 1 - minimumIndex << endl; return 0; } else if (maximumIndex < minimumIndex && (((sizebkp - 1) - minimumIndex) == (maximumIndex - 0))) { cout << sizebkp - 1 - maximumIndex << endl; return 0; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_1_V
`define SKY130_FD_SC_HD__O31A_1_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31a_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_1_V
|
#include <bits/stdc++.h> using namespace std; int a[200005]; bool got[200004], gave[200004]; queue<int> q; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; got[a[i]] = 1; if (a[i] != 0) { gave[i] = 1; } } for (int i = 1; i <= n; i++) { if (!got[i]) { q.push(i); } } for (int i = 1; i <= n; i++) { if (!got[i] && !gave[i]) { int x = q.front(); q.pop(); if (x == i) { q.push(x); x = q.front(); q.pop(); } a[i] = x; gave[i] = 1; got[x] = 1; } } for (int i = 1; i <= n; i++) { if (!gave[i]) { int x = q.front(); q.pop(); a[i] = x; gave[i] = 1; got[x] = 1; } } for (int i = 0; i < n; i++) { cout << a[i + 1] << ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V |
/*
* Handshake between two clock domains made from 6 FF's in a circle where
* a single edge travels around as an enable "token". If you see the token,
* you may write/sample data on a parallel bus of signals.
*
* (C) Arlet Ottens
*/
module handshake(
input clka, // clock domain A
output sync_a, // valid data for A, new data for B
input clkb, // clock domain B
output sync_b // valid data for B, new data for A
);
reg a = 0;
reg b = 0;
wire a_b;
wire b_a;
assign sync_a = ~(a ^ b_a);
assign sync_b = (b ^ a_b);
synchronizer synchronizer_a(
.clk_in(clka),
.clk_out(clkb),
.in(a),
.out(a_b) );
synchronizer synchronizer_b(
.clk_in(clkb),
.clk_out(clka),
.in(b),
.out(b_a) );
always @(posedge clka )
a <= ~b_a;
always @(posedge clkb )
b <= a_b;
endmodule
module synchronizer(
input clk_in,
input clk_out,
input in,
output reg out = 0 );
reg a = 0;
reg b = 0;
always @(posedge clk_in)
a <= in;
always @(posedge clk_out ) begin
b <= a;
out <= b;
end
endmodule
|
module booth(x,y,p);
input [7:0] x,y;
output [15:0] p;
wire [7:0] i,j,k,l,n,o,q,r;
wire [9:0] sp,tp,fop;
wire [7:0] fp;
wire [3:0] one,two,sign;
wire [10:0] c1,c2;
wire [8:0] ip1,ip2;
wire [9:0] c3;
wire [11:0] m;
wire [3:0] cry,z;
// carry generation
// 1st
xor n9(z[0],one[0],two[0]);
and n10(cry[0],z[0],sign[0]);
//2nd
xor n13(z[1],one[1],two[1]);
and n14(cry[1],z[1],sign[1]);
//3rd
xor n15(z[2],one[2],two[2]);
and n16(cry[2],z[2],sign[2]);
//4th
xor n17(z[3],one[3],two[3]);
and n18(cry[3],z[3],sign[3]);
code e1(one[0],two[0],sign[0],y[1],y[0],1'b0);
code e2(one[1],two[1],sign[1],y[3],y[2],y[1]);
code e3(one[2],two[2],sign[2],y[5],y[4],y[3]);
code e4(one[3],two[3],sign[3],y[7],y[6],y[5]);
//first product generation
product p0(x[0],sign[0],cry[0],one[0],two[0],sign[0],p[0],i[0],n[0]);
product p1(x[1],i[0],n[0],one[0],two[0],sign[0],p[1],i[1],n[1]);
product p2(x[2],i[1],n[1],one[0],two[0],sign[0],fp[0],i[2],n[2]);
product p3(x[3],i[2],n[2],one[0],two[0],sign[0],fp[1],i[3],n[3]);
product p4(x[4],i[3],n[3],one[0],two[0],sign[0],fp[2],i[4],n[4]);
product p5(x[5],i[4],n[4],one[0],two[0],sign[0],fp[3],i[5],n[5]);
product p6(x[6],i[5],n[5],one[0],two[0],sign[0],fp[4],i[6],n[6]);
product p7(x[7],i[6],n[6],one[0],two[0],sign[0],fp[5],i[7],n[7]);
xor x1(m[0],i[7],n[7]);
and a1(m[1],two[0],i[7]);
and a2(m[2],one[0],m[0]);
or o1(fp[6],m[1],m[2]);
not n1(fp[7],fp[6]);
//second product generation
product q0(x[0],sign[1],cry[1],one[1],two[1],sign[1],sp[0],j[0],o[0]);
product q1(x[1],j[0],o[0],one[1],two[1],sign[1],sp[1],j[1],o[1]);
product q2(x[2],j[1],o[1],one[1],two[1],sign[1],sp[2],j[2],o[2]);
product q3(x[3],j[2],o[2],one[1],two[1],sign[1],sp[3],j[3],o[3]);
product q4(x[4],j[3],o[3],one[1],two[1],sign[1],sp[4],j[4],o[4]);
product q5(x[5],j[4],o[4],one[1],two[1],sign[1],sp[5],j[5],o[5]);
product q6(x[6],j[5],o[5],one[1],two[1],sign[1],sp[6],j[6],o[6]);
product q7(x[7],j[6],o[6],one[1],two[1],sign[1],sp[7],j[7],o[7]);
xor x2(m[3],j[7],o[7]);
and a3(m[4],two[1],j[7]);
and a4(m[5],one[1],m[3]);
or o2(sp[8],m[4],m[5]);
not n2(sp[9],sp[8]);
//third product
product r0(x[0],sign[2],cry[2],one[2],two[2],sign[2],tp[0],k[0],q[0]);
product r1(x[1],k[0],q[0],one[2],two[2],sign[2],tp[1],k[1],q[1]);
product r2(x[2],k[1],q[1],one[2],two[2],sign[2],tp[2],k[2],q[2]);
product r3(x[3],k[2],q[2],one[2],two[2],sign[2],tp[3],k[3],q[3]);
product r4(x[4],k[3],q[3],one[2],two[2],sign[2],tp[4],k[4],q[4]);
product r5(x[5],k[4],q[4],one[2],two[2],sign[2],tp[5],k[5],q[5]);
product r6(x[6],k[5],q[5],one[2],two[2],sign[2],tp[6],k[6],q[6]);
product r7(x[7],k[6],q[6],one[2],two[2],sign[2],tp[7],k[7],q[7]);
xor x3(m[6],k[7],q[7]);
and a5(m[7],two[2],k[7]);
and a6(m[8],one[2],m[6]);
or o3(tp[8],m[7],m[8]);
not n3(tp[9],tp[8]);
//fourth product
product s0(x[0],sign[3],cry[3],one[3],two[3],sign[3],fop[0],l[0],r[0]);
product s1(x[1],l[0],r[0],one[3],two[3],sign[3],fop[1],l[1],r[1]);
product s2(x[2],l[1],r[1],one[3],two[3],sign[3],fop[2],l[2],r[2]);
product s3(x[3],l[2],r[2],one[3],two[3],sign[3],fop[3],l[3],r[3]);
product s4(x[4],l[3],r[3],one[3],two[3],sign[3],fop[4],l[4],r[4]);
product s5(x[5],l[4],r[4],one[3],two[3],sign[3],fop[5],l[5],r[5]);
product s6(x[6],l[5],r[5],one[3],two[3],sign[3],fop[6],l[6],r[6]);
product s7(x[7],l[6],r[6],one[3],two[3],sign[3],fop[7],l[7],r[7]);
xor x4(m[9],l[7],r[7]);
and a7(m[10],two[3],l[7]);
and a8(m[11],one[3],m[9]);
or o4(fop[8],m[10],m[11]);
not n4(fop[9],fop[8]);
//1st add
HAd fa1(sp[0],fp[0],c1[0],p[2]);
FAd fa2(sp[1],fp[1],c1[0],c1[1],p[3]);
FAd fa3(sp[2],fp[2],c1[1],c1[2],ip1[0]);
FAd fa4(sp[3],fp[3],c1[2],c1[3],ip1[1]);
FAd fa5(sp[4],fp[4],c1[3],c1[4],ip1[2]);
FAd fa6(sp[5],fp[5],c1[4],c1[5],ip1[3]);
FAd fa7(sp[6],fp[6],c1[5],c1[6],ip1[4]);
FAd fa8(sp[7],fp[6],c1[6],c1[7],ip1[5]);
FAd fa9(sp[8],fp[6],c1[7],c1[8],ip1[6]);
FAd fa10(sp[9],fp[7],c1[8],c1[9],ip1[7]);
HAd fa11(c1[9],1'b1,c1[10],ip1[8]);
//2rd add
HAd sa1(tp[0],ip1[0],c2[0],p[4]);
FAd sa2(tp[1],ip1[1],c2[0],c2[1],p[5]);
FAd sa3(tp[2],ip1[2],c2[1],c2[2],ip2[0]);
FAd sa4(tp[3],ip1[3],c2[2],c2[3],ip2[1]);
FAd sa5(tp[4],ip1[4],c2[3],c2[4],ip2[2]);
FAd sa6(tp[5],ip1[5],c2[4],c2[5],ip2[3]);
FAd sa7(tp[6],ip1[6],c2[5],c2[6],ip2[4]);
FAd sa8(tp[7],ip1[7],c2[6],c2[7],ip2[5]);
FAd sa9(tp[8],ip1[8],c2[7],c2[8],ip2[6]);
FAd sa10(tp[9],c1[10],c2[8],c2[9],ip2[7]);
HAd sa11(c2[9],1'b1,c2[10],ip2[8]);
//3th add
HAd foa1(fop[0],ip2[0],c3[0],p[6]);
FAd foa2(fop[1],ip2[1],c3[0],c3[1],p[7]);
FAd foa3(fop[2],ip2[2],c3[1],c3[2],p[8]);
FAd foa4(fop[3],ip2[3],c3[2],c3[3],p[9]);
FAd foa5(fop[4],ip2[4],c3[3],c3[4],p[10]);
FAd foa6(fop[5],ip2[5],c3[4],c3[5],p[11]);
FAd foa7(fop[6],ip2[6],c3[5],c3[6],p[12]);
FAd foa8(fop[7],ip2[7],c3[6],c3[7],p[13]);
FAd foa9(fop[8],ip2[8],c3[7],c3[8],p[14]);
FAd foa10(fop[9],c2[10],c3[8],c3[9],p[15]);
endmodule
// generation of codes
module code(one,two,sign,y2,y1,y0);
input y2,y1,y0;
output one,two,sign;
wire [1:0]k;
xor x1(one,y0,y1);
xor x2(k[1],y2,y1);
not n1(k[0],one);
and a1(two,k[0],k[1]);
assign sign=y2;
endmodule
//generation of inner products
module product(x1,x0,x2,one,two,sign,p,i,ca);
input x1,x0,x2,sign,one,two;
output p,i,ca;
wire [2:0] k;
xor xo1(i,x1,sign);
and a1(k[1],i,one);
and a0(k[0],x0,two);
or o0(k[2],k[1],k[0]);
xor xo2(p,k[2],x2);
and a2(ca,k[2],x2);
endmodule
//adders design
module HAd(a,b,c,s);
input a,b;
output c,s;
xor x1(s,a,b);
and a1(c,a,b);
endmodule
module FAd(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y,z;
HAd h1(a,b,x,z);
HAd h2(z,c,y,sm);
or o1(cy,x,y);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_eclbyplog.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_eclbyplog
// Description: This block implements the bypass logic for a single
// operand. It takes the destination registers of all
// four forwarding sources and the rs. It also has the
// thread for the instruction in each stage and whether
// the instruction writes to the register file. It won't
// bypass if rs =0.
*/
module sparc_exu_eclbyplog (/*AUTOARG*/
// Outputs
rs_sel_mux1_m, rs_sel_mux1_w, rs_sel_mux1_w2, rs_sel_mux1_other,
rs_sel_mux2_usemux1, rs_sel_mux2_rf, rs_sel_mux2_e,
rs_sel_mux2_ld, rs_sel_longmux_g2, rs_sel_longmux_w2,
rs_sel_longmux_ldxa,
// Inputs
sehold, use_other, rs, rd_e, rd_m, ecl_irf_rd_w, ld_rd_g,
wb_byplog_rd_w2, wb_byplog_rd_g2, tid_d, thr_match_de,
thr_match_dm, ecl_irf_tid_w, ld_thr_match_dg, wb_byplog_tid_w2,
ld_thr_match_dg2, ifu_exu_kill_e, wb_e, bypass_m,
lsu_exu_dfill_vld_g, bypass_w, wb_byplog_wen_w2, wb_byplog_wen_g2,
ecl_byp_ldxa_g
) ;
input sehold;
input use_other;
input [4:0] rs; // source register
input [4:0] rd_e; // destination regs for all stages
input [4:0] rd_m;
input [4:0] ecl_irf_rd_w;
input [4:0] ld_rd_g;
input [4:0] wb_byplog_rd_w2;
input [4:0] wb_byplog_rd_g2;
input [1:0] tid_d;
input thr_match_de;
input thr_match_dm;
input [1:0] ecl_irf_tid_w;
input ld_thr_match_dg;
input [1:0] wb_byplog_tid_w2;
input ld_thr_match_dg2;
input ifu_exu_kill_e;
input wb_e; // whether each stage writes to reg
input bypass_m; // file
input lsu_exu_dfill_vld_g;
input bypass_w;
input wb_byplog_wen_w2;
input wb_byplog_wen_g2;
input ecl_byp_ldxa_g;
output rs_sel_mux1_m;
output rs_sel_mux1_w;
output rs_sel_mux1_w2;
output rs_sel_mux1_other;
output rs_sel_mux2_usemux1;
output rs_sel_mux2_rf;
output rs_sel_mux2_e;
output rs_sel_mux2_ld;
output rs_sel_longmux_g2;
output rs_sel_longmux_w2;
output rs_sel_longmux_ldxa;
wire use_e, use_m, use_w, use_w2, use_rf, use_ld, use_ldxa;
wire match_e, match_m, match_w, match_w2, match_ld; // outputs of comparison
wire match_g2;
wire bypass; // boolean that allows bypassing
wire rs_is_nonzero;
// Don't bypass if rs == 0 or we are supposed to use other
assign rs_is_nonzero = rs[0]|rs[1]|rs[2]|rs[3]|rs[4];
assign bypass = rs_is_nonzero & ~use_other & ~sehold;
// Normal pipe priority: E, M, W, RF
// Ld priority: LD, RF
// W2 priority: E, M, W2, RF
assign use_e = match_e & wb_e & ~ifu_exu_kill_e;
assign use_m = match_m & bypass_m & ~use_e;
assign use_w = match_w & bypass_w & ~use_m & ~use_e;
assign use_ld = match_ld & lsu_exu_dfill_vld_g & ~ecl_byp_ldxa_g;
assign use_ldxa = match_ld & ecl_byp_ldxa_g;
assign use_w2 = (match_w2 & wb_byplog_wen_w2 | match_g2 & wb_byplog_wen_g2) & ~use_e & ~use_m;
assign use_rf = ~use_w2 & ~use_w & ~use_m & ~use_e & ~use_ld & ~use_ldxa;
// mux1[M, W, W2, OTHER(optional)]
// mux2[mux1, RF, E, LD]
assign rs_sel_mux2_e = (use_e & bypass);
assign rs_sel_mux2_rf = ((use_rf | ~bypass) & ~(use_other & ~sehold));
assign rs_sel_mux2_ld = (use_ld & ~use_e & ~use_w & ~use_m & ~use_w2 & bypass);
assign rs_sel_mux2_usemux1 = (use_other & ~sehold) | (~rs_sel_mux1_other & ~use_e);
assign rs_sel_mux1_other = ~((use_m | use_w | use_w2 | use_ldxa) & bypass);
assign rs_sel_mux1_w2 = ((use_w2 | use_ldxa) & bypass);
assign rs_sel_mux1_w = (use_w & ~use_w2 & ~use_ldxa & bypass);
assign rs_sel_mux1_m = (use_m & ~use_w2 & ~use_ldxa & bypass);
assign rs_sel_longmux_ldxa = use_ldxa;
assign rs_sel_longmux_g2 = match_g2 & wb_byplog_wen_g2 & ~use_ldxa;
assign rs_sel_longmux_w2 = ~use_ldxa & ~(match_g2 & wb_byplog_wen_g2);
// Comparisons
assign match_e = thr_match_de & (rs[4:0] == rd_e[4:0]);
// sparc_exu_eclcomp7 e_comp7(.out(match_e), .in1({tid_d[1:0],rs[4:0]}),
// .in2({ecl_rml_tid_e[1:0],rd_e[4:0]}));
assign match_m = thr_match_dm & (rs[4:0] == rd_m[4:0]);
// sparc_exu_eclcomp7 m_comp7(.out(match_m), .in1({tid_d[1:0],rs[4:0]}),
// .in2({tid_m[1:0],rd_m[4:0]}));
sparc_exu_eclcomp7 w_comp7(.out(match_w), .in1({tid_d[1:0],rs[4:0]}),
.in2({ecl_irf_tid_w[1:0],ecl_irf_rd_w[4:0]}));
sparc_exu_eclcomp7 w2_comp7(.out(match_w2), .in1({tid_d[1:0],rs[4:0]}),
.in2({wb_byplog_tid_w2[1:0],wb_byplog_rd_w2[4:0]}));
assign match_ld = ld_thr_match_dg & (rs[4:0] == ld_rd_g[4:0]);
assign match_g2 = ld_thr_match_dg2 & (rs[4:0] == wb_byplog_rd_g2[4:0]);
/* -----\/----- EXCLUDED -----\/-----
sparc_exu_eclcomp7 ld_comp7(.out(match_ld), .in1({tid_d[1:0],rs[4:0]}),
.in2({ld_tid_g[1:0],ld_rd_g[4:0]}));
sparc_exu_eclcomp7 g2_comp7(.out(match_g2), .in1({tid_d[1:0],rs[4:0]}),
.in2({wb_byplog_tid_g2[1:0],wb_byplog_rd_g2[4:0]}));
-----/\----- EXCLUDED -----/\----- */
endmodule // sparc_exu_eclbyplog
|
#include <bits/stdc++.h> using namespace std; const long long LLINF = 1ll << 60; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << setprecision(25); int T; cin >> T; while (T--) { int n; cin >> n; string s; cin >> s; int cnt = 1; vector<int> v; for (int i = 1; i < n; i++) { if (s[i] == s[i - 1]) cnt++; else { v.push_back(cnt); cnt = 1; } } v.push_back(cnt); int ans = 0; int l = (int)v.size(); for (int i = 0; i < l; i++) ans = min(i + 1, ans + v[i] - 1); cout << ans + (l - ans + 1) / 2 << n ; } } |
#include <bits/stdc++.h> using namespace std; template <class L, class R> ostream &operator<<(ostream &os, map<L, R> P) { for (auto const &vv : P) os << ( << vv.first << , << vv.second << ) ; return os; } template <class T> ostream &operator<<(ostream &os, set<T> V) { os << [ ; for (auto const &vv : V) os << vv << , ; os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto const &vv : V) os << vv << , ; os << ] ; return os; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { os << ( << P.first << , << P.second << ) ; return os; } inline int fstoi(const string &str) { auto it = str.begin(); bool neg = 0; int num = 0; if (*it == - ) neg = 1; else num = *it - 0 ; ++it; while (it < str.end()) num = num * 10 + (*it++ - 0 ); if (neg) num *= -1; return num; } inline void getch(char &x) { while (x = getchar_unlocked(), x < 33) { ; } } inline void getstr(string &str) { str.clear(); char cur; while (cur = getchar_unlocked(), cur < 33) { ; } while (cur > 32) { str += cur; cur = getchar_unlocked(); } } template <typename T> inline bool sc(T &num) { bool neg = 0; int c; num = 0; while (c = getchar_unlocked(), c < 33) { if (c == EOF) return false; } if (c == - ) { neg = 1; c = getchar_unlocked(); } for (; c > 47; c = getchar_unlocked()) num = num * 10 + c - 48; if (neg) num *= -1; return true; } template <typename T, typename... Args> inline void sc(T &num, Args &...args) { bool neg = 0; int c; num = 0; while (c = getchar_unlocked(), c < 33) { ; } if (c == - ) { neg = 1; c = getchar_unlocked(); } for (; c > 47; c = getchar_unlocked()) num = num * 10 + c - 48; if (neg) num *= -1; sc(args...); } int getsum(int a, int b) { int oor, oand; cout << and << a << << b << endl; cin >> oand; cout << or << a << << b << endl; cin >> oor; return oor + oand; } int main() { int n, k; cin >> n >> k; int cr; int x, y, z; x = getsum(1, 2); y = getsum(1, 3); z = getsum(2, 3); int a[n + 1]; a[3] = (y + z - x) / 2; a[2] = (-y + z + x) / 2; a[1] = (y - z + x) / 2; for (auto i = (4); i <= (n); ++i) { int wh = getsum(1, i); a[i] = wh - a[1]; } sort(a + 1, a + n + 1); cout << finish << a[k] << endl; cout << a[k] << endl; } |
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { if (x < 0) return -x; return x; } template <class T> T sqr(T a) { return a * a; } const double pi = acos(-1.0); const double eps = 1e-8; int a[100010]; int a1[100010]; int a2[100010]; int b; int ar[100010]; int flag[100010]; int main() { int i, n, m, k; while (2 == scanf( %d%d , &n, &m)) { int cnt = 0; for (i = 1; i <= n + m; i++) { if (i <= n) scanf( %d , &a1[i]); else scanf( %d , &a2[i - n]); } k = 0; for (i = 1; i <= n + m; i++) { scanf( %d , &b); if (b == 1) { cnt++; if (i <= n) ar[cnt] = a1[i]; else ar[cnt] = a2[i - n]; } else { ++k; if (i <= n) a[k] = a1[i]; else a[k] = a2[i - n]; } } k = 1; for (i = 1; i <= n; i++) { if (k + 1 <= cnt) { if (abs(a[i] - ar[k]) <= abs(a[i] - ar[k + 1])) flag[k]++; else { k++; i--; } } else flag[k]++; } for (i = 1; i <= cnt; i++) printf( %d , flag[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; const long long int N = 1e5 + 5; const long long int INF = 1e10; long long int mod = 998244353; long long int dx[4] = {0, 0, +1, -1}; long long int dy[4] = {+1, -1, 0, 0}; long long int n; void solve() { cin >> n; long long int c1 = 0, c2 = 0; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; (x == 1 ? c1++ : c2++); } long long int f = 0; for (long long int i = 0; i < n; i++) { if (f == 0 and c2 > 0 and c1 > 0) { cout << 2 << << 1 << ; c2--, c1--; f = 1; } else if (c2 > 0) { cout << 2 << ; c2--; } else if (c1 > 0) { cout << 1 << ; c1--; } } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000009; map<pair<int, int>, int> in, id; set<int> S; int X[100010], Y[100010]; bool check(pair<int, int> P) { int x = P.first, y = P.second + 1; for (int dx = x - 1; dx <= x + 1; dx++) { if (in.count(make_pair(dx, y)) && in[make_pair(dx, y)] == 1) return 0; } return 1; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; X[i] = x, Y[i] = y; in[make_pair(x, y)] = 0, id[make_pair(x, y)] = i; } for (map<pair<int, int>, int>::iterator it = in.begin(); it != in.end(); it++) { int x = it->first.first, y = it->first.second - 1; for (int dx = x - 1; dx <= x + 1; dx++) { if (in.count(make_pair(dx, y))) { in[it->first]++; } } } for (map<pair<int, int>, int>::iterator it = in.begin(); it != in.end(); it++) { if (check(it->first)) S.insert(id[it->first]); } long long ans = 0; for (int it = 0; it < n; it++) { if (it & 1) { int v = *S.begin(); S.erase(S.begin()); int y = Y[v] + 1; id.erase(make_pair(X[v], Y[v])); in[make_pair(X[v], Y[v])] = 0; for (int x = X[v] - 1; x <= X[v] + 1; x++) { if (!id.count(make_pair(x, y))) continue; in[make_pair(x, y)]--; } y--; for (int x = X[v] - 2; x <= X[v] + 2; x++) { if (!id.count(make_pair(x, y))) continue; if (check(make_pair(x, y))) S.insert(id[make_pair(x, y)]); else S.erase(id[make_pair(x, y)]); } y--; for (int x = X[v] - 2; x <= X[v] + 2; x++) { if (!id.count(make_pair(x, y))) continue; if (check(make_pair(x, y))) S.insert(id[make_pair(x, y)]); else S.erase(id[make_pair(x, y)]); } ans = (ans * n + v) % mod; } else { int v = *(--S.end()); S.erase(--S.end()); int y = Y[v] + 1; id.erase(make_pair(X[v], Y[v])); in[make_pair(X[v], Y[v])] = 0; for (int x = X[v] - 1; x <= X[v] + 1; x++) { if (!id.count(make_pair(x, y))) continue; in[make_pair(x, y)]--; } y--; for (int x = X[v] - 2; x <= X[v] + 2; x++) { if (!id.count(make_pair(x, y))) continue; if (check(make_pair(x, y))) S.insert(id[make_pair(x, y)]); else S.erase(id[make_pair(x, y)]); } y--; for (int x = X[v] - 2; x <= X[v] + 2; x++) { if (!id.count(make_pair(x, y))) continue; if (check(make_pair(x, y))) S.insert(id[make_pair(x, y)]); else S.erase(id[make_pair(x, y)]); } ans = (ans * n + v) % mod; } } cout << ans << endl; return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac_txfifo(
input sys_clk,
input tx_rst,
input stb,
input [7:0] data,
output full,
input can_tx,
output reg empty,
input phy_tx_clk,
output reg phy_tx_en,
output reg [3:0] phy_tx_data
);
wire [7:0] fifo_out;
wire fifo_empty;
reg fifo_read;
reg empty2;
always @(posedge sys_clk) begin
empty2 <= fifo_empty;
empty <= empty2;
end
minimac_asfifo #(
.DATA_WIDTH(8),
.ADDRESS_WIDTH(7)
) fifo (
.Data_out(fifo_out),
.Empty_out(fifo_empty),
.ReadEn_in(fifo_read),
.RClk(phy_tx_clk),
.Data_in(data),
.Full_out(full),
.WriteEn_in(stb),
.WClk(sys_clk),
.Clear_in(tx_rst)
);
reg can_tx1;
reg can_tx2;
always @(posedge phy_tx_clk) begin
can_tx1 <= can_tx;
can_tx2 <= can_tx1;
end
reg tx_rst1;
reg tx_rst2;
always @(posedge phy_tx_clk) begin
tx_rst1 <= tx_rst;
tx_rst2 <= tx_rst1;
end
wire interframe_gap;
wire transmitting = can_tx2 & ~fifo_empty & ~interframe_gap;
reg transmitting_r;
always @(posedge phy_tx_clk)
transmitting_r <= transmitting;
reg [4:0] interframe_counter;
always @(posedge phy_tx_clk) begin
if(tx_rst2)
interframe_counter <= 5'd0;
else begin
if(transmitting_r & ~transmitting)
interframe_counter <= 5'd24;
else if(interframe_counter != 5'd0)
interframe_counter <= interframe_counter - 5'd1;
end
end
assign interframe_gap = |interframe_counter;
reg hi_nibble;
always @(posedge phy_tx_clk) begin
if(tx_rst2) begin
hi_nibble <= 1'b0;
phy_tx_en <= 1'b0;
end else begin
hi_nibble <= 1'b0;
phy_tx_en <= 1'b0;
fifo_read <= 1'b0;
if(transmitting) begin
phy_tx_en <= 1'b1;
if(~hi_nibble) begin
phy_tx_data <= fifo_out[3:0];
fifo_read <= 1'b1;
hi_nibble <= 1'b1;
end else begin
phy_tx_data <= fifo_out[7:4];
hi_nibble <= 1'b0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[100001], l = 1; for (int i = 1; i <= n; i++) { int c, t; cin >> c >> t; int x = c * t; a[l] = c * t; l++; } int d = 1, s = 0; for (int i = 0; i < m; i++) { int k; cin >> k; if (s + a[d] >= k) { cout << d << endl; } else { while (1) { s += a[d]; d++; if (s + a[d] >= k) { cout << d << endl; break; } } } } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_top_v6.v
// Version : 2.3
//--
//-- Description: BlockRAM top level module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_top_v6
#(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 24,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [12:0] mim_tx_waddr,
input [71:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [12:0] mim_tx_raddr,
output [71:0] mim_tx_rdata,
input mim_rx_wen,
input [12:0] mim_rx_waddr,
input [71:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [12:0] mim_rx_raddr,
output [71:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
(VC0_RX_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule // pcie_bram_top
|
//==================================================================================================
// Filename : FSM_input_enable.v
// Created On : 2016-10-04 09:10:38
// Last Modified : 2016-10-04 09:45:50
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : Added extra state to the mix, pertaining to the
// initialization module (FSM).
//
//==================================================================================================
//==================================================================================================
// Filename : FSM_input_enable.v
// Created On : 2016-09-21 00:26:00
// Last Modified : 2016-10-04 09:08:38
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : FSM controlling the initialization and input of the operands and the
// desired operation
//
//==================================================================================================
`timescale 1ns / 1ps
module FSM_INPUT_ENABLE(
//INPUTS
input wire clk,
input wire rst,
input wire init_OPERATION,
output reg enable_input_internal,
//output enable for the first stage of the pipeline
output wire enable_Pipeline_input,
output reg enable_shift_reg
);
////////States///////////
//Zero Phase
parameter [3:0] State0 = 3'd0,
State1 = 3'd1,
State2 = 3'd2,
State3 = 3'd3,
State4 = 3'd4,
State5= 3'd5,
State6 = 3'd6,
State7 = 3'd7;
//State registers
reg [2:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= State0;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//DEFAULT INITIAL VALUES
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
enable_input_internal=1; //It is internal because its an intermediary value
enable_shift_reg = 0;
case(state_reg)
State0:
begin
//OUTPUT SIGNAL
//NEXT STATE
if(init_OPERATION)
state_next = State1; //JUMP TO NEXT STATE
else begin
state_next = State0; //STAY
end
end
State1:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State6;
end
State6:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State2;
end
State2:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State3;
end
State3:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State4;
end
State4:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State5;
end
State5:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
//state_next = State0;
if (init_OPERATION) begin
state_next = State1;
end else begin
state_next = State0;
end
end
// State6:
// begin
// //OUTPUT SIGNAL
// enable_input_internal=1;
// enable_shift_reg = 1;
// //NEXT STATE
// state_next = State1;
// end
// State7:
// begin
// //OUTPUT SIGNAL
// enable_input_internal=0;
// enable_shift_reg = 1;
// //NEXT STATE
// state_next = State0;
// end
default:
begin
state_next =State0;
end
endcase
end
assign enable_Pipeline_input = enable_input_internal & init_OPERATION;
endmodule
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
reg [1:0] orden;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge clk)
begin
if(wr&&!rd)
begin
orden = 2'b01;
end
if(!wr&&rd)
begin
orden = 2'b10;
end
if(wr&&rd)
begin
orden = 2'b11;
end
end
//always @(posedge reset or posedge wr or posedge rd)
always @(posedge clk)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case (orden)
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file background.v when simulating
// the core, background. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module background(
clka,
addra,
douta
);
input clka;
input [16 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(17),
.C_ADDRB_WIDTH(17),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("background.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(76800),
.C_READ_DEPTH_B(76800),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(76800),
.C_WRITE_DEPTH_B(76800),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 111111; long long tree[maxn * 4]; void Insert(int o, int l, int r, int k, int v) { if (l == r) { tree[o] = v; return; } int mid = (l + r) >> 1; if (k <= mid) Insert(o * 2, l, mid, k, v); else Insert(o * 2 + 1, mid + 1, r, k, v); tree[o] = tree[o * 2] + tree[o * 2 + 1]; } long long Query(int o, int l, int r, int L, int R) { if (L <= l && r <= R) return tree[o]; int mid = (l + r) >> 1; long double ans = 0; if (L <= mid) ans += Query(o * 2, l, mid, L, R); if (R > mid) ans += Query(o * 2 + 1, mid + 1, r, L, R); return ans; } int n, x, a[maxn], f[maxn]; int main() { cin >> n; long double ans = 0; for (int i = 1; i <= n; i++) cin >> a[i], f[a[i]] = i; for (int i = 1; i <= n; i++) { ans += Query(1, 1, n, a[i], n); Insert(1, 1, n, a[i], 1); } ans *= ((long long)n * (n + 1)); memset(tree, 0, sizeof(tree)); long long last = 0; for (int i = 1; i <= n; i++) { ans -= (last + Query(1, 1, n, a[i], n)); last = last + Query(1, 1, n, a[i], n); Insert(1, 1, n, a[i], f[a[i]] * 2); } for (int i = 1; i <= n; i++) ans += ((long long)(n - i + 1) * i * (i - 1) / 2); ans /= ((long long)n * (n + 1)); cout << setprecision(15) << ans << endl; } |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Retains unread words from reads that are a length
// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_128 #(
parameter C_FIFO_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_RD_EN_HIST = 2,
parameter C_FIFO_RD_EN_HIST = 2,
parameter C_CONSUME_HIST = 3,
parameter C_COUNT_HIST = 3,
parameter C_LEN_LAST_HIST = 1
)
(
input RST,
input CLK,
input LEN_VALID, // Transfer length is valid
input [1:0] LEN_LSB, // LSBs of transfer length
input LEN_LAST, // Last transfer in transaction
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data write count
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg [1:0] rRdPtr=0, _rRdPtr=0;
reg [1:0] rWrPtr=0, _rWrPtr=0;
reg [3:0] rLenLSB0=0, _rLenLSB0=0;
reg [3:0] rLenLSB1=0, _rLenLSB1=0;
reg [3:0] rLenLast=0, _rLenLast=0;
reg rLenValid=0, _rLenValid=0;
reg rRen=0, _rRen=0;
reg [2:0] rCount=0, _rCount=0;
reg [(C_COUNT_HIST*3)-1:0] rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
reg [C_LEN_LAST_HIST-1:0] rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
reg [C_RD_EN_HIST-1:0] rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_RD_EN_HIST-1:0] rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
reg [(C_CONSUME_HIST*3)-1:0] rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
reg [223:0] rData=224'd0, _rData=224'd0;
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
rRen <= #1 (RST ? 1'd0 : _rRen);
end
always @ (*) begin
_rLenValid = LEN_VALID;
_rRen = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Manage shifting of data in from the FIFO and shifting of data out once
// it is consumed. We'll keep 7 words of output registers to hold an input
// packet with up to 3 extra words of unread data.
wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
wire wLenLast = rLenLast[rRdPtr];
wire wAfterEnd = (!rRen & rRdEnHist[0]);
// consumed = 4 if RD+2
// consumed = remainder if EOP on RD+1 (~rRen & rRdEnHist[0])
// consumed = 4 if EOP on RD+3 and LAST on RD+3
wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
always @ (posedge CLK) begin
rCount <= #1 (RST ? 2'd0 : _rCount);
rCountHist <= #1 _rCountHist;
rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
rConsumedHist <= #1 _rConsumedHist;
rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
rFifoData <= #1 _rFifoData;
rData <= #1 _rData;
end
always @ (*) begin
// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
// rCount + remainder
_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
_rCountHist = ((rCountHist<<3) | rCount);
// Track read enables in the pipeline.
_rRdEnHist = ((rRdEnHist<<1) | rRen);
_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
// Track delayed length last value
_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
// Read from the FIFO unless we have 4 words cached.
_rFifoRdEn = (!rCount[2] & rRen);
// Buffer the FIFO data.
_rFifoData = wFifoData;
// Shift the buffered FIFO data into and the consumed data out of the output register.
if (rFifoRdEnHist[1])
_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
else
_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
end
// Buffer up to 4 length LSB values for use to detect unread data that was
// part of a consumed packet. Should only need 2. This is basically a FIFO.
always @ (posedge CLK) begin
rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
rLenLSB0 <= #1 _rLenLSB0;
rLenLSB1 <= #1 _rLenLSB1;
rLenLast <= #1 _rLenLast;
end
always @ (*) begin
_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
_rLenLSB0 = rLenLSB0;
_rLenLSB1 = rLenLSB1;
{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (rLenValid ? (~LEN_LSB + 1'd1) : {rLenLSB1[rWrPtr], rLenLSB0[rWrPtr]}); // Negative ,
_rLenLast = rLenLast;
_rLenLast[rWrPtr] = (rLenValid ? LEN_LAST : rLenLast[rWrPtr]);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512_max a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({2'd0, rCount, RD_EN, WR_EN, rFifoRdEn}),
.DATA({4'd0,
wLenLSB, // 2
wLenLast, // 1
wAfterEnd, // 1
wConsumed, // 3
rData, // 224
rFifoRdEn, // 1
rCount, // 3
rRen, // 1
RD_EN, // 1
RD_DATA, // 128
WR_COUNT, // 10
WR_EN, // 1
WR_DATA, // 128
LEN_LSB, // 2
LEN_LAST, // 1
LEN_VALID}) // 1
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1); const long long inf = 1LL << 30; const double eps = 1e-9; const long long mod = 1e9 + 7; const int N = 100100; pair<int, pair<int, int>> a[N]; int seg[N << 2], lazy[N << 2]; ; int ans[N]; int dp[N]; void push(int nd, int L, int R) { if (lazy[nd] == 0) return; seg[nd] = 0; if (L != R) { lazy[nd << 1] = 1; lazy[nd << 1 | 1] = 1; } lazy[nd] = 0; } void update(int nd, int L, int R, int idx, int val) { if (L == R) { seg[nd] = val; return; } int mid = (L + R) >> 1; if (idx <= mid) update(nd << 1, L, mid, idx, val); else update(nd << 1 | 1, mid + 1, R, idx, val); seg[nd] = seg[nd << 1] + seg[nd << 1 | 1]; } long long query(int nd, int L, int R, int from, int to) { push(nd, L, R); if (from <= L && R <= to) return seg[nd]; if (from > R || to < L) return 0; int mid = (L + R) >> 1; long long leftAns = query(nd << 1, L, mid, from, to); long long rightAns = query(nd << 1 | 1, mid + 1, R, from, to); return leftAns + rightAns; } void updateRange(int nd, int L, int R, int from, int to) { push(nd, L, R); if (R < from || L > to) return; if (from <= L && R <= to) { lazy[nd] = 1; push(nd, L, R); return; } int mid = (L + R) >> 1; updateRange(nd << 1, L, mid, from, to); updateRange(nd << 1 | 1, mid + 1, R, from, to); seg[nd] = seg[nd << 1] + seg[nd << 1 | 1]; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d , &a[i].first, &a[i].second.first); a[i].second.second = i; } sort(a, a + n); for (int i = n - 1; i >= 0; i--) { int j = lower_bound( a, a + n, make_pair(a[i].first + a[i].second.first, make_pair(0, 0))) - a - 1; dp[i] = 1 + query(1, 1, n, i, j); updateRange(1, 1, n, i + 1, j); update(1, 1, n, i, dp[i]); ans[a[i].second.second] = dp[i]; } for (int i = 0; i < n; i++) printf( %d , ans[i]); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 10; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) struct_bg <= '0;
else if (cnt[30:2]==1) struct_bg <= '0;
else if (cnt[30:2]==2) struct_bg <= '0;
else if (cnt[30:2]==3) struct_bg <= '0;
else if (cnt[30:2]==4) struct_bg <= '0;
else if (cnt[30:2]==5) struct_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '1;
else if (cnt[30:2]==2) struct_bg.e0 <= '1;
else if (cnt[30:2]==3) struct_bg.e1 <= '1;
else if (cnt[30:2]==4) struct_bg.e2 <= '1;
else if (cnt[30:2]==5) struct_bg.e3 <= '1;
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) struct_lt <= '0;
else if (cnt[30:2]==1) struct_lt <= '0;
else if (cnt[30:2]==2) struct_lt <= '0;
else if (cnt[30:2]==3) struct_lt <= '0;
else if (cnt[30:2]==4) struct_lt <= '0;
else if (cnt[30:2]==5) struct_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '1;
else if (cnt[30:2]==2) struct_lt.e0 <= '1;
else if (cnt[30:2]==3) struct_lt.e1 <= '1;
else if (cnt[30:2]==4) struct_lt.e2 <= '1;
else if (cnt[30:2]==5) struct_lt.e3 <= '1;
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mx[4005], need[4005]; int n, l[4005], r[4005], a[4005]; bool inter(int i, int j) { if (l[i] >= l[j] && l[i] <= r[j]) return 1; if (r[i] >= l[j] && r[i] <= r[j]) return 1; if (l[j] >= l[i] && l[j] <= r[i]) return 1; if (r[j] >= r[i] && r[j] <= r[i]) return 1; return 0; } bool check(int d) { int i, j, p, s; r[0] = (1 << 30); for (i = 1; i <= n; i++) need[i] = 0, mx[i] = n; need[n] = n; for (i = 1; i <= n; i++) { for (j = i, s = 0; j <= n; j++) if ((s += need[j]) > j - i + 1) return false; for (j = i, s = 0; j <= n; j++) if ((s += need[j]) == j - i + 1) break; s = j; for (j = 1, p = 0; j <= n; j++) if (mx[j] > 0 && mx[j] <= s && r[j] < r[p]) p = j; need[mx[p]]--, mx[p] = -1; for (j = 1; j <= n; j++) if (inter(p, j) && i + d < mx[j]) { need[i + d]++, need[mx[j]]--; mx[j] = i + d; } a[i] = p; } return 1; } int main() { int i, ll, rr, mid; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d %d , &l[i], &r[i]); ll = 0, rr = n - 1; while (rr - ll > 1) { mid = (ll + rr) >> 1; if (check(mid)) rr = mid; else ll = mid; } check(rr); for (i = 1; i <= n; i++) printf( %d , a[i]); return 0; } |
#include <bits/stdc++.h> struct M { int p, b; }; struct F { const int p, i; int r; int c; F(int p, int t, int i) : p(p), i(i), r(p + t), c(0) {} int t() { return r - p; } }; void solve(std::vector<F> &fs, std::vector<M> &ms) { std::multimap<int, int> ms_landed; std::map<int, F *> fs_active; { std::vector<F *> fs_sort; fs_sort.reserve(fs.size()); for (int i = 0; i < fs.size(); i++) fs_sort.push_back(&fs[i]); std::sort(fs_sort.begin(), fs_sort.end(), [](const F *lhs, const F *rhs) { return lhs->p < rhs->p; }); fs_active.insert({fs_sort[0]->p, fs_sort[0]}); int curr = fs_sort[0]->r; for (int i = 1; i < fs_sort.size(); i++) { F &f = *fs_sort[i]; if (f.r > curr) { int l = std::max(curr + 1, f.p); curr = f.r; fs_active.insert({l, &f}); } } } auto update = [&](F &f, std::map<int, F *>::iterator &f_it, const int &b) { f.c++; f.r += b; while (f_it != fs_active.end()) { int l_succ = f_it->first; F &f_succ = *f_it->second; if (f.r < f_succ.r) { if (f.r >= l_succ) { f_it = fs_active.insert(fs_active.erase(f_it), {f.r + 1, &f_succ}); } break; } f_it = fs_active.erase(f_it); } }; for (const M &m : ms) { auto f_it = --fs_active.upper_bound(m.p); if (f_it == fs_active.end()) continue; int l = f_it->first; F &f = *f_it->second; if (l <= m.p && m.p <= f.r) { update(f, ++f_it, m.b); auto m_succ = ms_landed.lower_bound(l); while (m_succ != ms_landed.end()) { M m{m_succ->first, m_succ->second}; if (l <= m.p && m.p <= f.r) { update(f, f_it, m.b); m_succ = ms_landed.erase(m_succ); } else { break; } } } else { ms_landed.insert({m.p, m.b}); } } for (F &f : fs) { printf( %d %d n , f.c, f.t()); } } int main() { int n; int m; scanf( %d%d , &n, &m); std::vector<F> fs; fs.reserve(n); std::vector<M> ms; ms.reserve(m); for (int i = 0; i < n; i++) { int p, t; scanf( %d%d , &p, &t); fs.push_back({p, t, i}); } for (int i = 0; i < m; i++) { int p, b; scanf( %d%d , &p, &b); ms.push_back({p, b}); } solve(fs, ms); return 0; } |
module x;
reg [31:0] mb_reg_output;
// 16 registers max, register 15 is always the version number, so 15 are useable
// NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
parameter NUMBER_INTERFACE_REGS = 16;
parameter MB_REG_START = 3; // start at 4th register location 'h0010
parameter CMD_REG_0_ADDR = MB_REG_START;
parameter CMD_REG_1_ADDR = MB_REG_START+1;
parameter CMD_REG_2_ADDR = MB_REG_START+2;
parameter CMD_REG_3_ADDR = MB_REG_START+3;
parameter CMD_REG_4_ADDR = MB_REG_START+4;
parameter CMD_REG_5_ADDR = MB_REG_START+5;
parameter CMD_REG_6_ADDR = MB_REG_START+6;
parameter CMD_REG_7_ADDR = MB_REG_START+7;
parameter CMD_REG_8_ADDR = MB_REG_START+8;
parameter CMD_REG_9_ADDR = MB_REG_START+9;
parameter CMD_REG_10_ADDR = MB_REG_START+10;
// mode regs
parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
// Absolute register 14 is Error counter
parameter CMD_REG_14_ADDR = 14;
parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
// ------------ VERSION register is 15
parameter VERSION_REG_ADDR = 15;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
wire [31:0] interface_from_core_fp;
assign
mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
integer mb_loop;
always @(/*AUTOSENSE*/ /*memory or*/ interface_from_core_fp or mb_reg_rwn or mb_reg_select)
begin: MB_READ_WRITE_SEL_P
mb_reg_wr = 'h0;
mb_reg_rd = 'h0;
mb_reg_output = interface_from_core_fp;
for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
begin
if(mb_reg_select[mb_loop] == 1'b1)
begin
mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
mb_reg_output = mb_reg_out_w[mb_loop];
end
end
end
endmodule // x
|
#include <bits/stdc++.h> using namespace std; int n, a[500005], b[500005]; char s[500005]; int res = 1e9, xx, yy; int calc2(int x, int y) { if (x == 0 && y == 0) return 1000000000; int ans = 0; for (int i = 1; i <= n; i++) { if (x <= a[i] && y <= b[i]) ans = max(ans, max(a[i] - x, b[i] - y)); else if (x <= a[i] || y <= b[i]) ans = max(ans, abs(a[i] - x) + abs(b[i] - y)); else ans = max(ans, max(x - a[i], y - b[i])); } if (ans < res) { res = ans; xx = x, yy = y; } return ans; } int calc1(int x) { int l = 0, r = 500000; if (x == 0) l = 1; while (l <= r) { int mid = (l + r) >> 1; if (calc2(x, mid) < calc2(x, mid + 1)) r = mid - 1; else l = mid + 1; } return min(calc2(x, l), calc2(x, r)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); int x = (int)strlen(s + 1); for (int j = 1; j <= x; j++) { if (s[j] == N ) a[i]++; else b[i]++; } } int l = 0, r = 500000; while (l <= r) { int mid = (l + r) >> 1; int v1 = calc1(mid), v2 = calc1(mid + 1); if (v1 < v2) r = mid - 1; else if (v1 > v2) l = mid + 1; else { int v3 = calc1(mid + 2); if (v1 < v3) r = mid - 1; else if (v1 > v3) l = mid + 1; else break; } } printf( %d n , res); for (int i = 1; i <= xx; i++) putchar( N ); for (int i = 1; i <= yy; i++) putchar( B ); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int first, long long int n) { if (n == 0) return 1; else if (n % 2 == 0) { long long int second = power(first, n / 2); return second * second; } else return first * power(first, n - 1); } int strTOint(string s) { stringstream ss; int first; ss << s; ss >> first; return first; } double geo_dist(int a, int b, int c, int d) { double dd = (double)(a - c) * (a - c) + (b - d) * (b - d); double r = sqrt(dd) + 1e-9; return r; } long long int bigmod(long long int a, long long int p, long long int m) { if (p == 0) return 1 % m; if (p % 2 == 0) { long long int second = bigmod(a, p / 2, m); return (second * second) % m; } else { return (a * bigmod(a, p - 1, m)) % m; } } long long int first, second, d, g; void ext_gcd(long long int a, long long int b) { if (b == 0) { first = 1; second = 0; d = a; return; } ext_gcd(b, a % b); long long int x1 = second; long long int y1 = first - (a / b) * second; first = x1; second = y1; } long long int modInv(long long int a, long long int m) { ext_gcd(a, m); first %= m; if (first < 0) first += m; return first; } int fx[] = {0, 0, -1, 1, -1, 1, 1, -1}; int fy[] = {1, -1, 0, 0, 1, 1, -1, -1}; map<string, int> mp; vector<pair<int, int> > adj[1000]; vector<int> v; int main() { long long int n, m; cin >> n >> m; long long int a, b, c, d, e, a1, b1, c1, d1, e1; long long int sum = 0; int j = 0; a = n / 5; a1 = m / 5; a *= a1; sum += a; for (int i = 1; i <= 4; i++) { j = 5 - i; j %= 5; a = n / 5; if (n % 5 >= i) a++; a1 = m / 5; if (m % 5 >= j) a1++; a *= a1; sum += a; } cout << sum << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_BEHAVIORAL_V |
module peripheral_bt(clk , rst , d_in , cs , addr , rd , wr, d_out, uart_tx, clk_uart );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output clk_uart;
output uart_tx;
//------------------------------------ regs and wires-------------------------------
reg [2:0] s; //selector mux_4 and demux_4
reg [7:0] d_in_uart; // data in uart
wire uart_busy; // out_uart
wire uart_done;
//------------------------------------ regs and wires-------------------------------
transmision tx(.reset(rst), .clk(clk), .din(d_in_uart), .tx(uart_tx), .busy(uart_busy), .done(uart_done), .clk_uart(clk_f));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 3'b001 : 3'b000 ;end //din_uart
4'h2:begin s = (cs && rd) ? 3'b010 : 3'b000 ;end //busy
4'h4:begin s = (cs && rd) ? 3'b100 : 3'b000 ;end //done
default:begin s=3'b000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
d_in_uart= (s[0]) ? d_in[7:0] : d_in_uart; // data in uart
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b010: d_out[0]= uart_busy;
3'b100: d_out[0]= uart_done;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int st = 0; cin >> s; int cnt[4] = {0}; for (int i = 0; i < s.size(); i++) { if ( 1 <= s[i] && s[i] <= 3 ) { ++cnt[s[i] - 0 ]; } } for (int i = 1; i <= 3; i++) { for (int j = 0; j < cnt[i]; j++) { if (st) { cout << + ; } else { st = 1; } cout << i; } } return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_85x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_85x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [84:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [84:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [84:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [84:0] q = sub_wire2[84:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 85,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "85"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "85"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "85"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 85 0 INPUT NODEFVAL data[84..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 85 0 OUTPUT NODEFVAL q[84..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 85 0 data 0 0 85 0
// Retrieval info: CONNECT: q 0 0 85 0 @q 0 0 85 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_85x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:24 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output UART0_TX;
input UART0_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
module deserializer(
clk, //serialized data proper clock
enable, //suspend while enable on low
reset, //set output to zero and reset counter to 0 on high
framesize, //number of bits to be deserialized
in, //serialized data
out, //deserialized data
complete //reset counter to 0 and hold out's data while high
);
parameter BITS = 32; //size of deserializer
parameter BITS_COUNTER = 8; //size of counter, must be at least log2(BITS)
input clk, enable, reset, in;
input [BITS_COUNTER-1:0] framesize;
output reg complete;
output reg [BITS-1:0] out;
reg [BITS_COUNTER-1:0] counter; //we need to know which array item (out) to write on
//always@(posedge clk) begin
//if (reset==1'b1) begin
//out <= 32'b00000000000000000000000000000000;
//counter <= 8'b00000000;
//complete <= 1'b0;
//end
// end
always@(posedge clk) begin
if (reset==1'b1) begin
out <= 32'b00000000000000000000000000000000;
counter <= 8'b00000000;
// complete <= 1'b0;
end
else begin
if(enable) begin
if (complete==1'b0) begin
out[counter] <= in;
counter <= counter + 1; //next item
end
end
end
end
always @ ( * ) begin
if (counter==framesize) begin
complete=1'b1;
end
else begin
complete=1'b0;
end
end
//always@(complete) begin
//counter = 0; //this way there's no need to reset every time we start a transaction (resetting all out bits consumes power)
//end
endmodule
|
`timescale 1ns / 1ps
module rx_DS_SE_tb();
reg d, s;
reg rxClk, rxReset;
wire [1:0] dq;
wire dqValid;
rx_DS_SE dut(
.d(d),
.s(s),
.rxClk(rxClk),
.rxReset(rxReset),
.dq(dq),
.dqValid(dqValid)
);
task assert_dqvalid;
input [7:0] story;
input expected;
begin
if(dqValid !== expected) begin
$display("@E %02X DQVALID Expected %d, got %d", story, expected, dqValid);
$stop;
end
end
endtask
task assert_dq;
input [7:0] story;
input [1:0] expected;
begin
if(dq !== expected) begin
$display("@E %02X DQ Expected %2b, got %2b", story, expected, dq);
$stop;
end
end
endtask
always begin
#10; rxClk <= ~rxClk;
end
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{d, s, rxClk, rxReset} <= 0;
#20;
rxReset <= 1;
#30;
rxReset <= 0;
assert_dqvalid(10, 0);
assert_dq(10, 0);
{d, s} <= 2'b01; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b10; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b00; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b10; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b00; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b10; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b11; #30;
{d, s} <= 2'b01; #30;
{d, s} <= 2'b00; #30;
#100;
$display("@I Done.");
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; long long a, b, f, k; int cnt() { int c = 0; int n = v.size(); long long now = 0; for (int i = 0; i < n; i++) { if (now + b < v[i]) return -1; while (i < n && now + b >= v[i]) i++; i--; c++; now = v[i]; } return c - 1; } int main() { scanf( %I64d%I64d%I64d%I64d , &a, &b, &f, &k); v.push_back(f); for (long long i = 1; i < k; i++) { if (i & 1) v.push_back(v[i - 1] + 2 * (a - f)); else v.push_back(v[i - 1] + 2 * f); } v.push_back(a * k); printf( %d , cnt()); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_1_V
`define SKY130_FD_SC_MS__OR4_1_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_1_V
|
/*
-----------------------------------------------------------------------------
General Sound
-----------------------------------------------------------------------------
18.08.2018 Reworked first verilog version
19.08.2018 Produce proper signed output
20.08.2018 Use external SDR/DDR RAM for page 2 and up
21.05.2020 Use external SDR/DDR RAM for all ROM/RAM
CPU: Z80 @ 28MHz
ROM: 32K
RAM: up to 4096KB
INT: 37.5KHz
#xxBB Command register - регистр команд, доступный для записи
#xxBB Status register - регистр состояния, доступный для чтения
bit 7 флаг данных
bit <6:1> Не определен
bit 0 флаг команд. Этот регистр позволяет определить состояние GS, в частности можно ли прочитать или записать очередной байт данных, или подать очередную команду, и т.п.
#xxB3 Data register - регистр данных, доступный для записи. В этот регистр Спектрум записывает данные, например, это могут быть аргументы команд.
#xxB3 Output register - регистр вывода, доступный для чтения. Из этого регистра Спектрум читает данные, идущие от GS
Внутренние порта:
#xx00 "расширенная память" - регистр доступный для записи
bit <3:0> переключают страницы по 32Kb, страница 0 - ПЗУ
bit <7:0> не используются
порты 1 - 5 "обеспечивают связь с SPECTRUM'ом"
#xx01 чтение команды General Sound'ом
bit <7:0> код команды
#xx02 чтение данных General Sound'ом
bit <7:0> данные
#xx03 запись данных General Sound'ом для SPECTRUM'a
bit <7:0> данные
#xx04 чтение слова состояния General Sound'ом
bit 0 флаг команд
bit 7 флаг данных
#xx05 сбрасывает бит D0 (флаг команд) слова состояния
порты 6 - 9 "регулировка громкости" в каналах 1 - 4
#xx06 "регулировка громкости" в канале 1
bit <5:0> громкость
bit <7:6> не используются
#xx07 "регулировка громкости" в канале 2
bit <5:0> громкость
bit <7:6> не используются
#xx08 "регулировка громкости" в канале 3
bit <5:0> громкость
bit <7:6> не используются
#xx09 "регулировка громкости" в канале 4
bit <5:0> громкость
bit <7:6> не используются
#xx0A устанавливает бит 7 слова состояния не равным биту 0 порта #xx00
#xx0B устанавливает бит 0 слова состояния равным биту 5 порта #xx06
Распределение памяти
#0000 - #3FFF - первые 16Kb ПЗУ
#4000 - #7FFF - первые 16Kb первой страницы ОЗУ
#8000 - #FFFF - листаемые страницы по 32Kb
страница 0 - ПЗУ,
страница 1 - первая страница ОЗУ
страницы 2... ОЗУ
Данные в каналы заносятся при чтении процессором ОЗУ по адресам #6000 - #7FFF автоматически.
*/
module gs
(
input RESET,
input CLK,
input CE_N,
input CE_P,
input A,
input [7:0] DI,
output [7:0] DO,
input CS_n,
input WR_n,
input RD_n,
output [20:0] MEM_ADDR,
output [7:0] MEM_DI,
input [7:0] MEM_DO,
output MEM_RD,
output MEM_WR,
input MEM_WAIT,
output [14:0] OUTL,
output [14:0] OUTR
);
parameter INT_DIV = 291;
// port #xxBB : #xxB3
assign DO = A ? {bit7, 6'b111111, bit0} : port_03;
// CPU
reg int_n;
wire cpu_m1_n;
wire cpu_mreq_n;
wire cpu_iorq_n;
wire cpu_rfsh_n;
wire cpu_rd_n;
wire cpu_wr_n;
wire [15:0] cpu_a_bus;
wire [7:0] cpu_do_bus;
T80pa cpu
(
.RESET_n(~RESET),
.CLK(CLK),
.CEN_n(CE_N),
.CEN_p(CE_P),
.INT_n(int_n),
.M1_n(cpu_m1_n),
.MREQ_n(cpu_mreq_n),
.RFSH_n(cpu_rfsh_n),
.IORQ_n(cpu_iorq_n),
.RD_n(cpu_rd_n),
.WR_n(cpu_wr_n),
.A(cpu_a_bus),
.DO(cpu_do_bus),
.DI(cpu_di_bus)
);
wire CE = CE_P;
// INT#
always @(posedge CLK) begin
reg [9:0] cnt;
if (RESET) begin
cnt <= 0;
int_n <= 1;
end else if(CE) begin
cnt <= cnt + 1'b1;
if (cnt == INT_DIV) begin // 37.48kHz
cnt <= 0;
int_n <= 0;
end
end
if (~cpu_iorq_n & ~cpu_m1_n) int_n <= 1;
end
reg bit7;
reg bit0;
always @(posedge CLK) begin
if (~cpu_iorq_n & cpu_m1_n) begin
case(cpu_a_bus[3:0])
'h2: bit7 <= 0;
'h3: bit7 <= 1;
'h5: bit0 <= 0;
'hA: bit7 <= ~port_00[0];
'hB: bit0 <= port_09[5];
endcase
end
else if (~CS_n) begin
if (~A & ~RD_n) bit7 <= 0;
if (~A & ~WR_n) bit7 <= 1;
if ( A & ~WR_n) bit0 <= 1;
end
end
reg [7:0] port_BB;
reg [7:0] port_B3;
always @(posedge CLK) begin
if (RESET) begin
port_BB <= 0;
port_B3 <= 0;
end
else if (~CS_n && ~WR_n) begin
if(A) port_BB <= DI;
else port_B3 <= DI;
end
end
reg [5:0] port_00;
reg [7:0] port_03;
reg signed [6:0] port_06, port_07, port_08, port_09;
reg signed [7:0] ch_a, ch_b, ch_c, ch_d;
always @(posedge CLK) begin
if (RESET) begin
port_00 <= 0;
port_03 <= 0;
end
else begin
if (~cpu_iorq_n & ~cpu_wr_n) begin
case(cpu_a_bus[3:0])
0: port_00 <= cpu_do_bus[5:0];
3: port_03 <= cpu_do_bus;
6: port_06 <= cpu_do_bus[5:0];
7: port_07 <= cpu_do_bus[5:0];
8: port_08 <= cpu_do_bus[5:0];
9: port_09 <= cpu_do_bus[5:0];
endcase
end
if (mem_rd && cpu_a_bus[15:13] == 3 && ~MEM_WAIT) begin
case(cpu_a_bus[9:8])
0: ch_a <= {~MEM_DO[7],MEM_DO[6:0]};
1: ch_b <= {~MEM_DO[7],MEM_DO[6:0]};
2: ch_c <= {~MEM_DO[7],MEM_DO[6:0]};
3: ch_d <= {~MEM_DO[7],MEM_DO[6:0]};
endcase
end
end
end
wire [7:0] cpu_di_bus =
mem_rd ? MEM_DO :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} :
8'hFF;
wire mem_wr = ~cpu_wr_n & ~cpu_mreq_n & |page_addr;
wire mem_rd = ~cpu_rd_n & ~cpu_mreq_n;
wire [5:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14];
assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]};
assign MEM_RD = mem_rd;
assign MEM_WR = mem_wr;
assign MEM_DI = cpu_do_bus;
reg signed [14:0] out_a,out_b,out_c,out_d;
always @(posedge CLK) begin
if(CE) begin
out_a <= ch_a * port_06;
out_b <= ch_b * port_07;
out_c <= ch_c * port_08;
out_d <= ch_d * port_09;
end
end
reg signed [14:0] outl, outr;
always @(posedge CLK) begin
if(CE) begin
outl <= out_a + out_b;
outr <= out_c + out_d;
end
end
assign OUTL = outl;
assign OUTR = outr;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool row[1100], col[1100]; int main() { int n, m; while (scanf( %d %d , &n, &m) != EOF) { memset(row, true, sizeof(row)); memset(col, true, sizeof(col)); while (m--) { int x, y; scanf( %d %d , &x, &y); row[x] = false; col[y] = false; } int res = 0; for (int i = 2; i <= n - 1; i++) { if (n % 2 && i == n / 2 + 1) { continue; } if (col[i]) { res++; } if (row[i]) { res++; } } if (n % 2 && (col[n / 2 + 1] || row[n / 2 + 1])) { res++; } printf( %d n , res); } return 0; } |
// Module m_ckt_jno is the circuit which handles the JNO or
// "jump if not overflow" instruction. When JNO is called, the
// status register is checked for an overflow of the program
// register. If the program register has not overflowed, the
// program counter will increment by 1, and the following value
// held in memory will be stored in the program counter (this is a
// "jump"). If the program register has overflowed, the program
// counter will increment by 2 on to the next word in memory.
module m_ckt_jno (m_bus_pc_in, w_bus_addr, w_bus_data, w_jno, w_sr_out, w_clock, w_reset);
output [1:0] m_bus_pc_in;
input [1:0] w_bus_addr, w_bus_data;
input w_jno, w_sr_out, w_clock, w_reset;
wire w_tmp_ovrflw, w_tmp_carry, w_tmp_add_in0, w_tmp_add_in1, w_tmp_sum0, w_tmp_sum1, w_demux_channel;
nand (w_tmp_add_in0, w_jno, w_sr_out);
and (w_tmp_add_in1, w_jno, w_sr_out);
and (w_tmp_ovrflw, w_jno, ~w_sr_out); // logic for demux channel
m_d_flip_flop dff_0 (w_demux_channel, w_tmp_ovrflw, w_clock, w_reset);
m_two_bit_adder two_bit_add_0 (w_tmp_carry, w_tmp_sum1, w_tmp_sum0, w_tmp_add_in1, w_tmp_add_in0, w_bus_addr[1], w_bus_addr[0]); // add 1 or 2 depending on overflow status
m_demux demux_0 (m_bus_pc_in[1], m_bus_pc_in[0], w_tmp_sum1, w_tmp_sum0, w_bus_data[1], w_bus_data[0], w_demux_channel);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_merge_node_priority_encoder_workgroup(clock, resetn, merge_block_selector,
merge_node_valid_in_0_staging_reg, merge_node_valid_in_1_staging_reg,
valid_in_0, valid_in_1, merge_stalled_by_successors, is_merge_data_to_local_regs_valid,
workgroup_size);
parameter WORKGROUP_SIZE_BITS = 10;
input clock, resetn;
input merge_node_valid_in_0_staging_reg, merge_node_valid_in_1_staging_reg;
input valid_in_0, valid_in_1, merge_stalled_by_successors;
input [WORKGROUP_SIZE_BITS-1:0] workgroup_size;
output merge_block_selector, is_merge_data_to_local_regs_valid;
reg [WORKGROUP_SIZE_BITS-1:0] in_count;
reg choose_0;
reg choose_1;
assign merge_block_selector = choose_1 ? 1'b1 : (choose_0 ? 1'b0 : ((merge_node_valid_in_1_staging_reg | valid_in_1) ? 1'b1 : 1'b0));
assign is_merge_data_to_local_regs_valid =
~merge_block_selector & merge_node_valid_in_0_staging_reg |
merge_block_selector & merge_node_valid_in_1_staging_reg |
~merge_block_selector & valid_in_0 | merge_block_selector & valid_in_1;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
in_count <= {WORKGROUP_SIZE_BITS{1'b0}};
choose_0 <= 1'b0;
choose_1 <= 1'b0;
end
else
begin
if (is_merge_data_to_local_regs_valid && !merge_stalled_by_successors)
begin
if (in_count == workgroup_size - 2'b01)
begin
in_count <= {WORKGROUP_SIZE_BITS{1'b0}};
choose_0 <= 1'b0;
choose_1 <= 1'b0;
end
else
begin
in_count <= in_count + 1'b1;
choose_0 <= ~merge_block_selector;
choose_1 <= merge_block_selector;
end
end
end
end
endmodule
|
/*
* Titor - System - Remote Controlled Servo Controller
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_RC
`else
`define INC_RC
`timescale 1 ns / 100 ps
// Note that this piece of hardware is only designed for a single accessor
// concurrent accesses must be serialized by making multiple instances of
// this piece of hardware or by software-combining the access.
//
// You also have to make sure that the timer is only accessed by privelaged code
// so you can't have the main accessing the hardware and then have an interrupt
// handler access it and then let the main continue to work on it. It's suggested
// that if your code accesses this hardware that you prevent interrupts from
// preempting the running code before even touching the timer.
module RC(
dout,
din,
address,
size,
read_write,
enable,
pwm,
reset,
clk
);
`include "definition/Definition.v"
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output wire pwm;
input reset;
input clk;
localparam RCPERIOD = 1*10**6; // 20ms * 50MHz
reg [WORD-1:0] periodshadow;
reg [WORD-1:0] periodhold;
reg [WORD-1:0] period;
reg [WORD-1:0] timer;
assign pwm = (timer < period);
always @(posedge clk) begin
if(reset) begin
periodshadow <= 0;
period <= 0;
timer <= 0;
end
else begin
if((enable==ENABLE) && (read_write==WRITE) && (address==0)) begin
periodshadow <= din;
end
else begin
periodshadow <= periodshadow;
end
if(timer==RCPERIOD-1+periodhold) begin
periodhold <= periodshadow;
period <= periodshadow;
timer <= 0;
end
else begin
periodhold <= periodhold;
period <= period;
timer <= timer+1;
end
end
end
always @(posedge clk) begin
if(reset) dout <= 0;
else if((enable==ENABLE) && (read_write==READ) && (address==0)) dout <= periodshadow;
else dout <= 0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; stringstream ans; int final_sum; string print_line(string a0) { int S = 0; for (int i = 0; i < a0.size() - 1; i++) { int digit = a0[i] - 0 ; S += digit; ans << digit << + ; } int digit = a0[a0.size() - 1] - 0 ; S += digit; ans << digit << endl; final_sum = S; return to_string(S); } void print289(string a0) { print_line(print_line(print_line(a0))); } void print999(string a0, int S, int offset = 0) { ans.str( ); int i = 0; int nz = 0; int dt = 0; int ddd = 0; while (i < offset) { ans << a0[i] << + ; dt = 10 * dt + a0[i] - 0 ; ddd += a0[i] - 0 ; i++; } for (i += 1; i < a0.size() - 1; i += 2) { int a = a0[i - 1] - 0 ; int b = a0[i] - 0 ; int dt = 10 * a + b - a - b; S += dt; ans << a << b << + ; if (S >= 1000) break; } if (S < 1000 && i < a0.size()) { int a = a0[i - 1] - 0 ; int b = a0[i] - 0 ; int dt = 10 * a + b - a - b; S += dt; ans << a << b; } i++; for (i; i < a0.size() - 1; i++) ans << a0[i] << + ; for (i; i < a0.size(); i++) ans << a0[a0.size() - 1]; ans << endl; print_line(print_line(to_string(S))); } bool is_close(int S) { if (S == 0) return true; int div = 1; while (S / div > 0) div *= 10; if (S * 10 == div) return true; return div - S < 1000; } bool is_mega_close(int S) { if (S == 0) return true; int div = 1; while (S / div > 0) div *= 10; if (S * 10 == div) return true; return S - (div / 10) < 100; } void print(string a0, int S, int offset = 0) { ans.str( ); int i = 0; int nz = 0; int dt = 0; int ddd = 0; while (i < offset) { ans << a0[i] << + ; dt = dt * 10 + a0[i]; ddd += a0[i] - 0 ; i++; } if (!is_close(S)) { for (i += 2; i < a0.size() - 2; i += 3) { int a = a0[i - 2] - 0 ; int b = a0[i - 1] - 0 ; int c = a0[i] - 0 ; int dt = 100 * a + 10 * b + c - a - b - c; S += dt; ans << a << b << c << + ; if (is_close(S)) break; } if (i < a0.size() - 2) i++; } if (!is_mega_close(S)) for (i += 2; i < a0.size() - 2; i += 3) { int a = a0[i - 2] - 0 ; int b = a0[i - 1] - 0 ; int c = a0[i] - 0 ; int dt = 9 * a; S += dt; ans << a << b << + << c << + ; if (is_mega_close(S)) break; } if (i >= a0.size() - 2) i -= 2; else i++; for (i; i < a0.size() - 1; i++) ans << a0[i] << + ; for (i; i < a0.size(); i++) ans << a0[a0.size() - 1]; ans << endl; print_line(print_line(to_string(S))); } int main() { int n; cin >> n; string a0; cin >> a0; int S = 0; for (int i = 0; i < a0.size(); i++) { int digit = a0[i] - 0 ; S += digit; } if (S < 199) { print289(a0); cout << ans.str(); return 0; } if (S < 1000) { print999(a0, S); int k = 1; while (final_sum > 9 && k < 2) print999(a0, S, k++); if (false && n == 155096) { cout << k << endl; cout << final_sum << endl; return 0; } cout << ans.str(); return 0; } print(a0, S); int k = 1; while (final_sum > 9 && k < 3) print(a0, S, k++); cout << ans.str(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_TB_V
`define SKY130_FD_SC_HVL__O21A_TB_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o21a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hvl__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_TB_V
|
// soc_system_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Clock generation for DDR2 MCB
*/
module ddr2_clock
(
// 250 MHz clock and reset
input wire clk_250mhz,
input wire rst_250mhz,
// Output clocks to MCB
output wire mcb_clk_0,
output wire mcb_clk_180,
output wire mcb_drp_clk,
output wire mcb_clk_locked
);
wire clkfb;
wire mcb_clk_0_int;
wire mcb_clk_180_int;
wire mcb_drp_clk_int;
// input is 250 MHz
// output0/1 are 250 MHz * 5 / 2 = 625 MHz (MCB 2x clock)
// output2 is 625 MHz / 10 = 62.5 MHz (MCB DRP clock)
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (4.000),
.CLKIN2_PERIOD (4.000),
.CLKOUT0_DIVIDE (1),
.CLKOUT1_DIVIDE (1),
.CLKOUT2_DIVIDE (10),
.CLKOUT3_DIVIDE (1),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT (5),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.025000)
)
mcb_pll
(
.CLKFBIN (clkfb),
.CLKINSEL (1'b1),
.CLKIN1 (clk_250mhz),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (rst_250mhz),
.CLKFBDCM (),
.CLKFBOUT (clkfb),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (mcb_clk_0),
.CLKOUT1 (mcb_clk_180),
.CLKOUT2 (mcb_drp_clk_int),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (mcb_clk_locked)
);
BUFGCE
mcb_drp_clk_bufg_inst
(
.I(mcb_drp_clk_int),
.O(mcb_drp_clk),
.CE(mcb_clk_locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int memo[500][26][26]; int son[500][26][26]; int cambios[500][26][26]; vector<string> A; int m, n; void solve(int x, int y, int z) { for (int row = 0; row < x; row++) for (int a = 0; a < y; a++) for (int b = 0; b < z; b++) { int &res = memo[row][a][b]; if (row == 0) { res = cambios[0][a][b]; continue; } int mn = 1 << 29; for (int i = 0; i < 26; i++) if (i != a) for (int j = 0; j < 26; j++) if (j != b) { int tmp = memo[row - 1][i][j] + cambios[row][a][b]; if (mn > tmp) mn = tmp, son[row][a][b] = 1000 * i + j; } res = mn; } } int main() { while (cin >> m >> n) { memset(memo, -1, sizeof(memo)); A.clear(); string cad; for (int i = 0; i < m; i++) cin >> cad, A.push_back(cad); reverse((A).begin(), (A).end()); for (int row = 0; row < m; row++) { for (int a = 0; a < 26; a++) for (int b = 0; b < 26; b++) if (b != a) { int s = 0; for (int k = 0; k < n; k++) { if ((k & 1) == 0 && A[row][k] - a != a) s++; if ((k & 1) == 1 && A[row][k] - a != b) s++; } cambios[row][a][b] = s; } else cambios[row][a][b] = 1 << 29; } solve(m, 26, 26); int mn = 1 << 29; int a, b; for (int i = 0; i < 26; i++) for (int j = 0; j < 26; j++) if (j != i) { if (mn > memo[m - 1][i][j]) mn = memo[m - 1][i][j], a = i, b = j; } printf( %d n , mn); for (int row = m - 1; row >= 0; row--) { for (int i = 0; i < n; i++) { if ((i & 1) == 0) cout << char(a + a ); else cout << char(b + a ); } cout << endl; int tmp = son[row][a][b]; a = tmp / 1000; b = tmp % 1000; } } } |
#include <bits/stdc++.h> using namespace std; string s[100] = { 111111101010101111100101001111111 , 100000100000000001010110001000001 , 101110100110110000011010001011101 , 101110101011001001111101001011101 , 101110101100011000111100101011101 , 100000101010101011010000101000001 , 111111101010101010101010101111111 , 000000001111101111100111100000000 , 100010111100100001011110111111001 , 110111001111111100100001000101100 , 011100111010000101000111010001010 , 011110000110001111110101100000011 , 111111111111111000111001001011000 , 111000010111010011010011010100100 , 101010100010110010110101010000010 , 101100000101010001111101000000000 , 000010100011001101000111101011010 , 101001001111101111000101010001110 , 101101111111000100100001110001000 , 000010011000100110000011010000010 , 001101101001101110010010011011000 , 011101011010001000111101010100110 , 111010100110011101001101000001110 , 110001010010101111000101111111000 , 001000111011100001010110111110000 , 000000001110010110100010100010110 , 111111101000101111000110101011010 , 100000100111010101111100100011011 , 101110101001010000101000111111000 , 101110100011010010010111111011010 , 101110100100011011110110101110000 , 100000100110011001111100111100000 , 111111101101000101001101110010001 }; int main() { int x, y; scanf( %d%d , &x, &y); printf( %c , s[x][y]); } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int n, c[100005], dp[100005][2], i, j; cin >> n; string s[100005], rs[100005]; for (i = 1; i <= n; i++) cin >> c[i]; for (i = 1; i <= n; i++) { cin >> s[i]; rs[i] = s[i]; dp[i][0] = dp[i][1] = 1e15; reverse(rs[i].begin(), rs[i].end()); } dp[1][0] = 0; dp[1][1] = c[1]; for (i = 2; i <= n; i++) { if (s[i] < s[i - 1] && s[i] < rs[i - 1] && rs[i] < rs[i - 1] && rs[i] < s[i - 1]) { cout << -1 ; return 0; } if ((string)s[i] >= s[i - 1] && dp[i - 1][0] != 1e15) dp[i][0] = min(dp[i][0], dp[i - 1][0]); if ((string)s[i] >= rs[i - 1] && dp[i - 1][1] != 1e15) dp[i][0] = min(dp[i][0], dp[i - 1][1]); if ((string)rs[i] >= s[i - 1] && dp[i - 1][0] != 1e15) dp[i][1] = min(dp[i][1], c[i] + dp[i - 1][0]); if ((string)rs[i] >= rs[i - 1] && dp[i - 1][1] != 1e15) dp[i][1] = min(dp[i][1], c[i] + dp[i - 1][1]); } long long int ans = min(dp[n][0], dp[n][1]); if (ans == 1e15) cout << -1 ; else cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 2; int n, m, a[N], cnt[N], nxt[N]; bool vis[N]; int main() { int test; cin >> test; while (test--) { cin >> n >> m; for (int i = 0; i <= n; ++i) cnt[i] = 0; for (int i = 1; i <= n; ++i) { cin >> a[i]; int t1 = i + n - a[i], t2 = i - a[i] + 1; int k1 = -1, k2 = -1; if (t1 < n) { k1 = t1; } if (t2 > 0) { k2 = t2 - 1; } if (k1 >= 0) ++cnt[k1]; if (k2 >= 0) cnt[k2] += k1 != k2; } vector<int> ans; ans.clear(); for (int i = 0; i < n; ++i) { if (n - cnt[i] > m * 2) continue; for (int j = 1; j <= n; ++j) { vis[j] = false; if (a[j] <= n - i) { nxt[j] = i + a[j]; } else { nxt[j] = a[j] - (n - i); } } int cycles = 0; for (int j = 1; j <= n; ++j) if (nxt[j] != j && !vis[j]) { int u = j; ++cycles; vis[j] = true; while (nxt[u] != j) { u = nxt[u]; vis[u] = true; } } if (n - cnt[i] - cycles <= m) { ans.push_back(i); } } cout << (int)ans.size() << ; for (int i : ans) cout << i << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int dy[] = {-1, 1, 0, 0}; const int dx[] = {0, 0, -1, 1}; int n, m; string s[1010]; int L[1010][1010]; int R[1010][1010]; int U[1010][1010]; int D[1010][1010]; int usedX[1010][1010], usedY[1010][1010]; int main() { cin.tie(0); ios_base::sync_with_stdio(false); cout << fixed << setprecision(10); cin >> n >> m; for (int i = 0; i < n; i++) { cin >> s[i]; } for (int i = 0; i < n; i++) { L[i][0] = s[i][0] == * ; for (int j = 1; j < m; j++) { if (s[i][j] == . ) L[i][j] = 0; else L[i][j] = L[i][j - 1] + 1; } R[i][m - 1] = s[i][m - 1] == * ; for (int j = m - 2; j >= 0; j--) { if (s[i][j] == . ) R[i][j] = 0; else R[i][j] += R[i][j + 1] + 1; } } for (int j = 0; j < m; j++) { U[0][j] = s[0][j] == * ; for (int i = 1; i < n; i++) { if (s[i][j] == . ) U[i][j] = 0; else U[i][j] = U[i - 1][j] + 1; } D[n - 1][j] = s[n - 1][j] == * ; for (int i = n - 2; i >= 0; i--) { if (s[i][j] == . ) D[i][j] = 0; else D[i][j] += D[i + 1][j] + 1; } } using P = tuple<int, int, int>; vector<P> vs; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int mx = min({U[i][j], R[i][j], D[i][j], L[i][j]}); if (mx > 1) { vs.emplace_back(i, j, mx - 1); if (j - mx + 1 >= 0) usedX[i][j - mx + 1]++; if (j + mx <= m) usedX[i][j + mx]--; if (i - mx + 1 >= 0) usedY[i - mx + 1][j]++; if (i + mx <= n) usedY[i + mx][j]--; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { usedX[i][j + 1] += usedX[i][j]; } } for (int j = 0; j < m; j++) { for (int i = 0; i < n; i++) { usedY[i + 1][j] += usedY[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == * && !(usedY[i][j] || usedX[i][j])) { cout << -1 << endl; return 0; } } } cout << vs.size() << endl; for (auto v : vs) { int y, x, p; tie(y, x, p) = v; cout << y + 1 << << x + 1 << << p << endl; } return 0; } |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous DDR output
*/
module ssio_ddr_out_diff #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock for transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire clk90,
input wire [WIDTH-1:0] input_d1,
input wire [WIDTH-1:0] input_d2,
output wire output_clk_p,
output wire output_clk_n,
output wire [WIDTH-1:0] output_q_p,
output wire [WIDTH-1:0] output_q_n
);
wire output_clk;
wire [WIDTH-1:0] output_q;
ssio_ddr_out #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.USE_CLK90(USE_CLK90),
.WIDTH(WIDTH)
)
ssio_ddr_out_inst(
.clk(clk),
.clk90(clk90),
.input_d1(input_d1),
.input_d2(input_d2),
.output_clk(output_clk),
.output_q(output_q)
);
genvar n;
generate
if (TARGET == "XILINX") begin
OBUFDS
clk_obufds_inst (
.I(output_clk),
.O(output_clk_p),
.OB(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
OBUFDS
data_obufds_inst (
.I(output_q[n]),
.O(output_q_p[n]),
.OB(output_q_n[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_OUTBUF_DIFF
clk_outbuf_diff_inst (
.i(output_clk),
.o(output_clk_p),
.obar(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_OUTBUF_DIFF
data_outbuf_diff_inst (
.i(output_q[n]),
.o(output_q_p[n]),
.obar(output_q_n[n])
);
end
end else begin
assign output_clk_p = output_clk;
assign output_clk_n = ~output_clk;
assign output_q_p = output_q;
assign output_q_n = ~output_q;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int a[300010]; long long ans = 0; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } sort(a + 1, a + 1 + n); for (int i = 1; i <= n / 2; ++i) { long long sum = a[i] + a[n - i + 1]; ans += sum * sum; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; long long f[1200]; long long mod = 1000000007; int arr[1100]; long long pw(long long x, long long sum) { long long res = 1, power = sum, val = x; while (power) { if (power & 1) { res *= val; res %= mod; } val *= val; val %= mod; power >>= 1ll; } return res; } int main() { f[0] = 1; for (int i = 1; i <= 1000; i++) f[i] = (f[i - 1] * i) % mod; int n, m; cin >> n >> m; long long ans = f[n - m]; vector<int> vec; for (int i = 0; i < m; i++) { scanf( %d , &arr[i]); } sort(arr, arr + m); if (!m) vec.push_back(n); else { vec.push_back(arr[0] - 1); for (int i = 1; i < m; i++) vec.push_back(arr[i] - arr[i - 1] - 1); vec.push_back(n - arr[m - 1]); } long long sum = 1; for (int i = 0; i < vec.size(); i++) sum = (sum * f[vec[i]]) % mod; ans = (ans * pw(sum, mod - 2)) % mod; for (int i = 1; i < vec.size() - 1; i++) if (vec[i] - 1 && vec[i]) ans = (ans * pw(2, vec[i] - 1)) % mod; cout << ans << endl; return 0; } |
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