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module serial_rx #(
parameter CLK_PER_BIT = 50,
parameter CTR_SIZE = 6
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule |
#include <bits/stdc++.h> using namespace std; bool G[30][30]; int main() { int T; scanf( %d , &T); while (T--) { int n, p; scanf( %d%d , &n, &p); memset(G, 0, sizeof(G)); for (int i = 0; i < n; ++i) G[i][(i + 1) % n] = G[(i + 1) % n][i] = G[i][(i + 2) % n] = G[(i + 2) % n][i] = 1; for (int step = 3; p; ++step) { for (int i = 0; p && i < n; ++i) { G[i][(i + step) % n] = G[(i + step) % n][i] = 1; --p; } } for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) if (G[i][j]) printf( %d %d n , i + 1, j + 1); } return 0; } |
#include <bits/stdc++.h> using std::bitset; using std::cerr; using std::cin; using std::complex; using std::cout; using std::deque; using std::endl; using std::ios_base; using std::iterator; using std::map; using std::max; using std::max_element; using std::min; using std::min_element; using std::multimap; using std::multiset; using std::pair; using std::queue; using std::reverse; using std::set; using std::sort; using std::stable_sort; using std::stack; using std::string; using std::swap; using std::unique; using std::vector; namespace MySpace { struct Small_Segment_Tree { vector<int> a; int l, r; private: int __summ(int L, int R, int l, int r, int v) { if (L <= l && r <= R) return a[v]; if (R <= l || r <= L) return 0; int m = (l + r) / 2; return __summ(L, R, l, m, 2 * v + 1) + __summ(L, R, m, r, 2 * v + 2); } void __set(int P, int l, int r, int v, int V) { if (l + 1 == r) { a[v] = V; return; } int m = (l + r) / 2; if (P < m) { __set(P, l, m, 2 * v + 1, V); a[v] = a[2 * v + 1] + a[2 * v + 2]; } else { __set(P, m, r, 2 * v + 2, V); a[v] = a[2 * v + 1] + a[2 * v + 2]; } } public: int Summ(int L, int R) { if (R < L) return 0; return __summ(L, R + 1, l, r, 0); } void Set(int P, int V) { __set(P, l, r, 0, V); } Small_Segment_Tree(int _n) { a.resize(4 * _n); l = 0, r = _n; } }; long long inq(long long x, long long q, long long MOD) { if (q == 0) return 1; long long l = inq(x, q / 2, MOD); if (q % 2) return l * l % MOD * x % MOD; return l * l % MOD; } }; // namespace MySpace using namespace MySpace; long long n, m; long long a[500000]; int main() { ios_base::sync_with_stdio(); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = n; i < 2 * n; i++) cin >> a[i]; sort(a, a + 2 * n); long long s1 = 0, s2 = 0; for (int i = 0; i < n; i++) s1 += a[i]; for (int i = n; i < 2 * n; i++) s2 += a[i]; if (s1 == s2) { cout << -1; return 0; } for (int i = 0; i < 2 * n; i++) cout << a[i] << ; } |
#include <bits/stdc++.h> using namespace std; int Gcd(int x, int y) { while (x > 0 && y > 0) { if (x > y) { x = x % y; } else { y = y % x; } } return x + y; } int Sign(int x) { return (x > 0) ? 1 : -1; } int Abs(int x) { return (x > 0) ? x : -x; } void ReduceFraction(int& x, int& y) { if (x == 0) { y = 1; } else if (y == 0) { x = 1; } else { int sgn = Sign(x) * Sign(y); x = Abs(x); y = Abs(y); int g = Gcd(x, y); x /= g; y /= g; x *= sgn; } } struct Vector { Vector(int vx, int vy) { ReduceFraction(vx, vy); x = vx; y = vy; } int x; int y; bool operator==(const Vector& other) const { return (x == other.x) && (y == other.y); } }; struct Line { Line(int x0, int y0, int x1, int y1) : a(x1 - x0, y1 - y0) { if (a.y != 0) { u = a.y * x0 - a.x * y0; v = a.y; ReduceFraction(u, v); } else { u = y0; v = 10001; } } int u; int v; Vector a; bool operator==(const Line& other) const { return (u == other.u) && (v == other.v) && (a == other.a); } }; struct VectorHasher { size_t operator()(Vector v) const { const size_t coef = 39916801; const hash<int> int_hasher; return coef * int_hasher(v.x) + int_hasher(v.y); } }; struct LineHasher { size_t operator()(const Line& l) const { const size_t coef = 514229; const hash<int> int_hasher; const VectorHasher vector_hasher; return coef * coef * int_hasher(l.u) + coef * int_hasher(l.v) + vector_hasher(l.a); } }; long long Cn2(long long n) { return n * (n - 1) / 2; } int main() { int n; cin >> n; vector<pair<int, int>> pts(n); for (int i = 0; i < n; ++i) { cin >> pts[i].first >> pts[i].second; } unordered_map<Vector, unordered_set<Line, LineHasher>, VectorHasher> store; for (int i = 0; i + 1 < n; ++i) { for (int j = i + 1; j < n; ++j) { Line new_line(pts[i].first, pts[i].second, pts[j].first, pts[j].second); store[new_line.a].insert(new_line); } } long long result = 0; long long count = 0; for (const auto& p : store) { result -= Cn2(p.second.size()); count += p.second.size(); } cout << result + Cn2(count); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_1_V
`define SKY130_FD_SC_HS__CLKBUF_1_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_1_V
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; ll n,m,pos,qwq,delta,a[1009],b[1009],p[1009][1009]; inline ll read(){ ll s = 0,w = 1; char ch = getchar(); while (ch > 9 || ch < 0 ){ if (ch == - ) w = -1; ch = getchar();} while (ch <= 9 && ch >= 0 ) s = (s << 1) + (s << 3) + (ch ^ 48),ch = getchar(); return s * w; } int main(){ m = read(),n = read(); for (ll i = 1;i <= n;i += 1) for (ll j = 1;j <= m;j += 1) p[i][j] = read(),a[i] += p[i][j],b[i] += p[i][j] * p[i][j]; for (ll i = 2;i < n;i += 1) if (a[i] - a[i - 1] != (a[n] - a[1]) / (n - 1)){pos = i,delta = a[i] - a[i - 1] - (a[n] - a[1]) / (n - 1); break;} if (pos <= 3) qwq = b[n - 2] + b[n] - 2 * b[n - 1]; else qwq = b[1] + b[3] - 2 * b[2]; for (ll i = 1;i <= m;i += 1) if (b[pos - 1] + b[pos + 1] - 2 * (b[pos] - p[pos][i] * p[pos][i] + (p[pos][i] - delta) * (p[pos][i] - delta)) == qwq){printf( %lld %lld ,pos - 1,p[pos][i] - delta); return 0;} return 0; } |
#include <bits/stdc++.h> const double pi = acos(-1); using namespace std; vector<int> v; int c[1000000]; int main() { int n; double h; cin >> n >> h; double s = h / (2 * double(n)); for (int i = 1; i < n; i++) { printf( %.10f n , sqrt(s * 2 * h * i)); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; int s[2], t[200007][2]; int x[200007]; int n, m, st[200007]; int absi(int x) { return x > 0 ? x : -x; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) scanf( %d , &x[i]); memset(s, 0, sizeof(s)); memset(t, 0, sizeof(t)); memset(st, 0, sizeof(st)); for (int i = 0; i < n; i++) ++s[x[i] > 0]; for (int i = 0; i < n; i++) t[absi(x[i])][x[i] > 0]++; int cnt = 0; for (int i = 1; i <= n; ++i) { int fake = 0; fake += t[i][1] + s[0] - t[i][0]; if (fake == m) { st[i] = 1; ++cnt; } } for (int i = 0; i < n; i++) { int ss = 0; if (x[i] > 0 && st[x[i]]) ss |= 1; if (x[i] > 0 && !st[x[i]]) ss |= 2; if (x[i] > 0 && cnt > 1) ss |= 2; if (x[i] < 0 && !st[-x[i]]) ss |= 1; if (x[i] < 0 && st[-x[i]]) ss |= 2; if (x[i] < 0 && cnt > 1) ss |= 1; if (ss == 1) cout << Truth n ; if (ss == 2) cout << Lie n ; if (ss == 3) cout << Not defined n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char c; int v[300], a; int main() { v[ > ] = 0; v[ < ] = 1; v[ + ] = 2; v[ - ] = 3; v[ . ] = 4; v[ , ] = 5; v[ [ ] = 6; v[ ] ] = 7; while (cin >> c) a = (a * 16 + 8 + v[c]) % 1000003; cout << a << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V |
#include<iostream> #include<string> #include<cstring> #include<cmath> #include<algorithm> #include<queue> #include<iomanip> #include<map> #include<cstdio> #include<stack> #include<set> using namespace std; #define endl n #define IOS ios::sync_with_stdio(false),cin.tie(0), cout.tie(0) typedef long long ll; typedef unsigned long long ull; typedef pair<int, int> pii; typedef pair<long, long>pll; const int inf = 0x3f3f3f3f; const ll lnf = 0x3f3f3f3f3f3f3f3f; const double pi = acos(-1.0); int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } ll lcm(ll a, ll b) { return a / gcd(a, b) * b; } #define re(i,a,b) for(int i = a;i <= b;i++) #define rre(i,a) for(int i = 0;i < a;i++) #define prre(i,a) for(int i = a;i >= 0;i--) #define pre(i,a) for(int i = a;i > 0;i--) #define bug system( pause ) const double eps = 1e-6; const int N = 1e6 + 10; const int M = 2e6 + 10; const int mod = 1e9 + 7; int n, t, x; map<pii, int>mp; int ask(int l, int r) { if (mp.count(make_pair(l, r)))return mp[make_pair(l, r)]; cout << ? << l << << r << endl; cout.flush(); int sum; cin >> sum; int num = r - l + 1 - sum; mp[make_pair(l, r)] = num; return num; } int query(int l, int r, int k) { if (l == r)return l; int mid = (l + r) >> 1; int v = ask(l, mid); if (v < k)return query(mid + 1, r, k - v); else return query(l, mid, k); } void update(int l, int r, int pos) { if (mp.count(make_pair(l, r)))mp[make_pair(l, r)]--; if (l == r)return; int mid = (l + r) >> 1; if (pos <= mid)update(l, mid, pos); if (pos > mid)update(mid + 1, r, pos); } int main() { cin >> n >> t; for (int i = 1; i <= t; i++) { cin >> x; int pos = query(1, n, x); update(1, n, pos); cout << ! << pos << endl; cout.flush(); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T x, T y) { while (y > 0) { x %= y; swap(x, y); } return x; } template <class _T> inline _T sqr(const _T& x) { return x * x; } template <class _T> inline string tostr(const _T& a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795L; template <typename T> inline void input(T& a) { static int c; a = 0; while (!isdigit(c = getchar()) && c != - ) { } char neg = 0; if (c == - ) { neg = 1; c = getchar(); } while (isdigit(c)) { a = 10 * a + c - 0 ; c = getchar(); } if (neg) a = -a; } template <typename T = int> inline T nxt() { T res; input(res); return res; } void solve() {} void imp() { puts( IMPOSSIBLE ); exit(0); } const int N = 1000010; vector<int> q[N][2]; int g[N][2]; int r[N]; int maleft[N]; int miright[N]; int n; int dfs(int v, int le, int ri) { if (r[v] >= ri) { imp(); } if (v >= ri) { imp(); } if (le >= ri) { imp(); } if (maleft[v] > v) { g[v][0] = v + 1; int ret = dfs(v + 1, maleft[v], min(ri, miright[v])); le = max(le, r[v]); if (ret < le) { g[v][1] = ret + 1; return dfs(ret + 1, le, ri); } else { return ret; } } else { le = max(le, r[v]); if (v < le) { g[v][1] = v + 1; return dfs(v + 1, le, ri); } } return v; } void print(int v) { if (v >= n) { return; } if (g[v][0]) { print(g[v][0]); } printf( %d , v + 1); if (g[v][1]) { print(g[v][1]); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int c; n = nxt(); c = nxt(); char s[10]; for (int i = 0; i < c; ++i) { int a = nxt() - 1; int b = nxt() - 1; if (b <= a) { imp(); } scanf( %s , s); if (s[0] == L ) { q[a][0].push_back(b); } else { q[a][1].push_back(b); } } for (int i = 0; i < n; ++i) { r[i] = i; maleft[i] = i; miright[i] = INT_MAX; } for (int i = n - 2; i >= 0; --i) { for (int x : q[i][0]) { r[i] = max(r[i], r[x]); } for (int x : q[i][1]) { r[i] = max(r[i], r[x]); } for (int x : q[i][0]) { maleft[i] = max(maleft[i], r[x]); } for (int x : q[i][1]) { miright[i] = min(miright[i], x); } if (miright[i] <= maleft[i]) { imp(); } } int val = dfs(0, n - 1, n); assert(val == n - 1); print(0); puts( ); return 0; }; |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
real r, r2;
integer cyc=0;
task check(integer line, real got, real ex);
if (got != ex) begin
if ((got - ex) > 0.000001) begin
$display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex);
$stop;
end
end
endtask
initial begin
// Check constant propagation
check(`__LINE__, $ceil(-1.2), -1);
check(`__LINE__, $ceil(1.2), 2);
check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125);
check(`__LINE__, $exp(0.0), 1);
check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375);
check(`__LINE__, $floor(-1.2), -2);
check(`__LINE__, $floor(1.2), 1);
check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625);
//check(`__LINE__, $ln(0), 0); // Bad value
//check(`__LINE__, $ln(-1.2), 0); // Bad value
check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875);
//check(`__LINE__, $log10(0), 0); // Bad value
//check(`__LINE__, $log10(-1.2), 0);
check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375);
check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875);
//check(`__LINE__, $pow(-2.3,1.2),0); // Bad value
check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125);
//check(`__LINE__, $sqrt(-1.2), 0); // Bad value
`ifndef VERILATOR
check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1
check(`__LINE__, $acosh(1.2), 0.622362503);
check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1
check(`__LINE__, $asinh(1.2), 1.015973134);
check(`__LINE__, $atan (0.2), 0.197395559);
check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1
check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1
check(`__LINE__, $cos (1.2), 0.362357754);
check(`__LINE__, $cosh (1.2), 1.810655567);
check(`__LINE__, $hypot(1.2,2.3), 2.594224354);
check(`__LINE__, $sin (1.2), 0.932039085);
check(`__LINE__, $sinh (1.2), 1.509461355);
check(`__LINE__, $tan (1.2), 2.572151622);
check(`__LINE__, $tanh (1.2), 0.833654607);
`endif
end
real sum_ceil;
real sum_exp;
real sum_floor;
real sum_ln;
real sum_log10;
real sum_pow1;
real sum_pow2;
real sum_sqrt;
real sum_acos;
real sum_acosh;
real sum_asin;
real sum_asinh;
real sum_atan;
real sum_atan2;
real sum_atanh;
real sum_cos ;
real sum_cosh;
real sum_hypot;
real sum_sin;
real sum_sinh;
real sum_tan;
real sum_tanh;
// Test loop
always @ (posedge clk) begin
r = $itor(cyc)/10.0 - 5.0; // Crosses 0
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n",$time, cyc, r, sum_ln);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
end
else if (cyc<90) begin
// Setup
sum_ceil += 1.0+$ceil(r);
sum_exp += 1.0+$exp(r);
sum_floor += 1.0+$floor(r);
if (r > 0.0) sum_ln += 1.0+$ln(r);
if (r > 0.0) sum_log10 += 1.0+$log10(r);
// Pow requires if arg1<0 then arg1 integral
sum_pow1 += 1.0+$pow(2.3,r);
if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3);
if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r);
`ifndef VERILATOR
if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r);
if (r>=1.0) sum_acosh += 1.0+$acosh(r);
if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r);
sum_asinh += 1.0+$asinh(r);
sum_atan += 1.0+$atan (r);
if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3);
if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r);
sum_cos += 1.0+$cos (r);
sum_cosh += 1.0+$cosh (r);
sum_hypot += 1.0+$hypot(r,2.3);
sum_sin += 1.0+$sin (r);
sum_sinh += 1.0+$sinh (r);
sum_tan += 1.0+$tan (r);
sum_tanh += 1.0+$tanh (r);
`endif
end
else if (cyc==99) begin
check (`__LINE__, sum_ceil, 85);
check (`__LINE__, sum_exp, 608.06652950);
check (`__LINE__, sum_floor, 4);
check (`__LINE__, sum_ln, 55.830941633);
check (`__LINE__, sum_log10, 46.309585076);
check (`__LINE__, sum_pow1, 410.98798177);
check (`__LINE__, sum_pow2, 321.94765689);
check (`__LINE__, sum_sqrt, 92.269677253);
`ifndef VERILATOR
check (`__LINE__, sum_acos, 53.986722862);
check (`__LINE__, sum_acosh, 72.685208498);
check (`__LINE__, sum_asin, 21);
check (`__LINE__, sum_asinh, 67.034973416);
check (`__LINE__, sum_atan, 75.511045389);
check (`__LINE__, sum_atan2, 21);
check (`__LINE__, sum_atanh, 0);
check (`__LINE__, sum_cos, 72.042023124);
check (`__LINE__, sum_cosh, 1054.);
check (`__LINE__, sum_hypot, 388.92858406);
check (`__LINE__, sum_sin, 98.264184989);
check (`__LINE__, sum_sinh, 0);
check (`__LINE__, sum_tan, 1.);
check (`__LINE__, sum_tanh, 79.003199681);
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-12-2018
*/
// Wrapper to output only combined channels. Defaults to YM2203 mode.
module jt03(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input addr,
input cs_n,
input wr_n,
output [7:0] dout,
output irq_n,
// I/O pins used by YM2203 embedded YM2149 chip
input [7:0] IOA_in,
input [7:0] IOB_in,
// Separated output
output [ 7:0] psg_A,
output [ 7:0] psg_B,
output [ 7:0] psg_C,
output signed [15:0] fm_snd,
// combined output
output [ 9:0] psg_snd,
output signed [15:0] snd,
output snd_sample,
// Debug
//input [ 7:0] debug_bus,
output [ 7:0] debug_view
);
jt12_top #(
.use_lfo(0),.use_ssg(1), .num_ch(3), .use_pcm(0), .use_adpcm(0) )
u_jt12(
.rst ( rst ), // rst should be at least 6 clk&cen cycles long
.clk ( clk ), // CPU clock
.cen ( cen ), // optional clock enable, it not needed leave as 1'b1
.din ( din ),
.addr ( {1'b0, addr} ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.dout ( dout ),
.irq_n ( irq_n ),
// YM2203 I/O pins, only input supported
.IOA_in ( IOA_in ),
.IOB_in ( IOB_in ),
// Unused ADPCM pins
.en_hifi_pcm ( 1'b0 ), // used only on YM2612 mode
.adpcma_addr ( ), // real hardware has 10 pins multiplexed through RMPX pin
.adpcma_bank ( ),
.adpcma_roe_n ( ), // ADPCM-A ROM output enable
.adpcma_data ( 8'd0 ), // Data from RAM
.adpcmb_data ( 8'd0 ),
.adpcmb_addr ( ), // real hardware has 12 pins multiplexed through PMPX pin
.adpcmb_roe_n ( ), // ADPCM-B ROM output enable
// Separated output
.psg_A ( psg_A ),
.psg_B ( psg_B ),
.psg_C ( psg_C ),
.psg_snd ( psg_snd ),
.fm_snd_left ( fm_snd ),
.fm_snd_right (),
.adpcmA_l (),
.adpcmA_r (),
.adpcmB_l (),
.adpcmB_r (),
.snd_right ( snd ),
.snd_left (),
.snd_sample ( snd_sample ),
//.debug_bus ( debug_bus ),
.debug_bus ( 8'd0 ),
.debug_view ( debug_view )
);
endmodule // jt03 |
/* Cross Clock Module Tested and check
*
* Creates a FIFO that sits between two clock domains. Read and write are
* both asynconous and can occur at the same time. The FIFO does check if
* it is full/empty before writing/reading.
*
* Created by David Tran
* Version 0.1.0.0
* Last Modified:05-03-2014
*/
module crossclock(wrEnable,
inputData,
outputData,
clkA,
clkB,
rst);
parameter bits = 8;
parameter ad_length = 2;
parameter length = 1<<ad_length;
parameter [2:0] GRAY0 = 3'b000;
parameter [2:0] GRAY1 = 3'b001;
parameter [2:0] GRAY2 = 3'b011;
parameter [2:0] GRAY3 = 3'b010;
parameter [2:0] GRAY4 = 3'b110;
parameter [2:0] GRAY5 = 3'b111;
parameter [2:0] GRAY6 = 3'b101;
parameter [2:0] GRAY7 = 3'b100;
input wrEnable, clkA, clkB, rst;
input [bits-1:0] inputData;
output [bits-1:0] outputData;
wire [bits-1:0] outputData;
wire wrEnable, rst;
wire [bits-1:0] inputData;
reg rstQA, rstA, rstQB, rstB;
reg rdPtrAQQ, rdPtrAQ, wrPtrBQ, wrPtrBQQ;
reg full;
wire empty;
reg [ad_length-1:0] wrPtrA, rdPtrA, wrPtrB, rdPtrB;
reg [bits-1:0] FIFO [length-1:0];
always @(posedge clkA or negedge rstA)
if(rstA)
wrPtrA <= {ad_length{1'h0}};
else if (wrEnable & !full)
wrPtrA <= grayInc(wrPtrA);
always @(posedge clkB or negedge rstB)
if(!rstB)
rdPtrB <= {ad_length{1'h0}};
else if (!empty)
rdPtrB <= grayInc(rdPtrB);
always @(wrPtrA or rdPtrAQQ)
case (wrPtrA)
GRAY0: full = (rdPtrAQQ == GRAY1);
GRAY1: full = (rdPtrAQQ == GRAY2);
GRAY2: full = (rdPtrAQQ == GRAY3);
GRAY3: full = (rdPtrAQQ == GRAY4);
GRAY4: full = (rdPtrAQQ == GRAY5);
GRAY5: full = (rdPtrAQQ == GRAY6);
GRAY6: full = (rdPtrAQQ == GRAY7);
GRAY7: full = (rdPtrAQQ == GRAY0);
endcase
always @(posedge clkA) begin
if (wrEnable) begin
FIFO[wrPtrA] <= inputData;
end
rdPtrAQ <= rdPtrB;
rdPtrAQQ <= rdPtrAQ;
end
always @(posedge clkB) begin
wrPtrBQ <= wrPtrA;
wrPtrBQQ <= wrPtrBQ;
end
// Dual Rank blocks
always @(posedge clkA or negedge rst)
if (!rst) begin
rstQA <= 1'b0;
rstA <= 1'b0;
end else begin
rstQA <= 1'b1;
rstA <= rstQA;
end
always @(posedge clkB or negedge rst)
if (!rst) begin
rstQB <= 1'b0;
rstB <= 1'b0;
end else begin
rstQB <= 1'b1;
rstB <= rstQB;
end
// Reset Block
always @(posedge clkA or posedge clkB or negedge rst) begin
if (rst) begin
wrPtrA <= {ad_length{1'b0}};
wrPtrB <= {ad_length{1'b0}};
wrPtrBQ <= {ad_length{1'b0}};
wrPtrBQQ <= {ad_length{1'b0}};
rdPtrB <= {ad_length{1'b0}};
rdPtrA <= {ad_length{1'b0}};
rdPtrAQ <= {ad_length{1'b0}};
rdPtrAQQ <= {ad_length{1'b0}};
end
end
assign empty = wrPtrBQQ == wrPtrA;
assign outputData = FIFO[rdPtrB];
// Gray Add Function
function [2:0] grayInc;
input [2:0] greyInput;
begin
case (greyInput)
GRAY0 : grayInc=GRAY1;
GRAY1 : grayInc=GRAY2;
GRAY2 : grayInc=GRAY3;
GRAY3 : grayInc=GRAY4;
GRAY4 : grayInc=GRAY5;
GRAY5 : grayInc=GRAY6;
GRAY6 : grayInc=GRAY7;
GRAY7 : grayInc=GRAY0;
endcase
end
endfunction
endmodule
//measly output rely on input and state
//moore output rely on state only
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
*/
`timescale 1 ns/1 ps
module wishbone_interconnect (
//control signals
input clk,
input rst,
//wishbone master signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int,
//Slave 1
output o_s1_we,
output o_s1_cyc,
output o_s1_stb,
output [3:0] o_s1_sel,
input i_s1_ack,
output [31:0] o_s1_dat,
input [31:0] i_s1_dat,
output [31:0] o_s1_adr,
input i_s1_int,
//Slave 2
output o_s2_we,
output o_s2_cyc,
output o_s2_stb,
output [3:0] o_s2_sel,
input i_s2_ack,
output [31:0] o_s2_dat,
input [31:0] i_s2_dat,
output [31:0] o_s2_adr,
input i_s2_int
);
parameter ADDR_0 = 0;
parameter ADDR_1 = 1;
parameter ADDR_2 = 2;
parameter ADDR_FF = 8'hFF;
//state
//wishbone slave signals
//this should be parameterized
wire [7:0]slave_select;
wire [31:0] interrupts;
assign slave_select = i_m_adr[31:24];
//data in from slave
always @ (slave_select or i_s0_dat or i_s1_dat or i_s2_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
ADDR_2: begin
o_m_dat <= i_s2_dat;
end
default: begin
o_m_dat <= interrupts;
end
endcase
end
//ack in from slave
always @ (slave_select or i_s0_ack or i_s1_ack or i_s2_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
ADDR_2: begin
o_m_ack <= i_s2_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
assign interrupts[2] = i_s2_int;
assign interrupts[31:3] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 1'b0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 4'h0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 32'h0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 1'b0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 1'b0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 4'h0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 1'b0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 32'h0;
assign o_s2_we = (slave_select == ADDR_2) ? i_m_we: 1'b0;
assign o_s2_stb = (slave_select == ADDR_2) ? i_m_stb: 1'b0;
assign o_s2_sel = (slave_select == ADDR_2) ? i_m_sel: 4'h0;
assign o_s2_cyc = (slave_select == ADDR_2) ? i_m_cyc: 1'b0;
assign o_s2_adr = (slave_select == ADDR_2) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s2_dat = (slave_select == ADDR_2) ? i_m_dat: 32'h0;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_Loop_1_proc_line_buffer_0_0_val_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1921;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
end
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_Loop_1_proc_line_buffer_0_0_val(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd1921;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
image_filter_Loop_1_proc_line_buffer_0_0_val_ram image_filter_Loop_1_proc_line_buffer_0_0_val_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long m; long long a[100005], b[100005], c[100005], ans[100005]; bool prime[100005]; vector<long long> pvec; long long modpow(long long a, long long n) { if (n == 0) return 1; if (n % 2) { return ((a % 998244353) * (modpow(a, n - 1) % 998244353)) % 998244353; } else { return modpow((a * a) % 998244353, n / 2) % 998244353; } } int main(void) { ios::sync_with_stdio(0); cin.tie(0); for (int i = 2; i < 1005; i++) { if (prime[i]) continue; for (int j = 2 * i; j < 100005; j += i) prime[j] = true; } for (int i = 2; i < 100005; i++) { if (!prime[i]) pvec.push_back(i); } cin >> m; long long x, y; for (int i = 1; i <= m; i++) { cin >> x >> y; a[x] += y; b[x] += x * y % 998244353, b[x] %= 998244353; c[x] += x * x % 998244353 * y % 998244353, c[x] %= 998244353; } for (int i = 0; i < pvec.size(); i++) { long long p = pvec[i]; for (int j = 100004 / p; j >= 1; j--) { a[j] += a[j * p]; b[j] += b[j * p], b[j] %= 998244353; c[j] += c[j * p], c[j] %= 998244353; } } for (int i = 1; i <= 100000; i++) { long long sum = 0, mul, mul2; if (a[i] >= 2) { mul = c[i], mul2 = (a[i] - 1) % 998244353 * modpow(2, a[i] - 2) % 998244353; sum += mul * mul2 % 998244353, sum %= 998244353; } if (a[i] >= 3) { mul = b[i] * b[i] % 998244353 + 998244353 - c[i], mul %= 998244353; mul2 = (a[i] - 2) % 998244353 * modpow(2, a[i] - 3) % 998244353; sum += mul * mul2 % 998244353, sum %= 998244353; } if (a[i] >= 2) { mul = b[i] * b[i] % 998244353 + 998244353 - c[i], mul %= 998244353; mul2 = modpow(2, a[i] - 2); sum += mul * mul2 % 998244353, sum %= 998244353; } ans[i] = sum; } for (int i = 0; i < pvec.size(); i++) { long long p = pvec[i]; for (int j = 1; j <= 100004 / p; j++) { ans[j] += 998244353 - ans[j * p], ans[j] %= 998244353; } } cout << ans[1] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_4_V
`define SKY130_FD_SC_LP__DLXTN_4_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_4 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_4 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_4_V
|
#include <bits/stdc++.h> using namespace std; typedef vector<vector<int>> graph; ifstream in( buffcraft.in , ios::in); ofstream out( buffcraft.out , ios::out); int main() { double m, R, ans = 0; cin >> m >> R; for (int x = 2; x < m; x++) ans += ((x - 1) * 2 + 2 * sqrt(2.0)) * 2 * (m - x); ans += 2 * m + (2 + sqrt(2.0)) * 2 * (m - 1); cout << setprecision(15) << ans / (m * m) * R; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; const int K = 3; int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int ans = -1; for (int i = 1; i <= n; ++i) { long long int x; cin >> x; ans = max(ans, x - i); } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); int k; int a[n]; for (k = 0; k < n; k++) scanf( %d , &a[k]); int p = n - 2; int i, j; for (i = 0; i < p; i++) { for (j = i + 2; j < n; j++) { if (a[i] == a[j]) { printf( YES n ); break; } } if (a[i] == a[j]) { break; } } if (a[i] == a[j]) continue; printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, c, s; vector<double> x, y11, z; double rx, ry, rz, mn = -1000000000; double mln(double x) { return log(x); } void upd(double nx, double ny, double nz) { if (nx + ny + nz > (s + 1e-7)) return; double cur = 0; if (a) cur += a * mln(nx); if (b) cur += b * mln(ny); if (c) cur += c * mln(nz); if (cur > mn) { mn = cur; rx = nx; ry = ny; rz = nz; } } int main() { scanf( %d %d %d %d , &s, &a, &b, &c); if (a == 0 && b == 0 && c == 0) { puts( 0.0 0.0 0.0 ); return 0; } if (a != 0) { double S = s; double m = 1 + b * 1. / a + c * 1. / a; double x0 = S / m; x.push_back(x0); y11.push_back(x0 * b * 1. / a); z.push_back(x0 * c * 1. / a); } else if (b != 0) { double S = s; double m = 1 + a * 1. / b + c * 1. / b; double x0 = S / m; x.push_back(x0 * a * 1. / b); y11.push_back(x0); z.push_back(x0 * c * 1. / b); } else if (c != 0) { double S = s; double m = 1 + a * 1. / c + b * 1. / c; double x0 = S / m; x.push_back(x0 * a * 1. / c); y11.push_back(x0 * b * 1. / c); z.push_back(x0); } double S = s; x.push_back(0); y11.push_back(0); z.push_back(s); x.push_back(0); y11.push_back(s); z.push_back(0); x.push_back(s); y11.push_back(0); z.push_back(0); if (a + b) { z.push_back(0); z.push_back(0); x.push_back(a * c / (b + a + 0.)); y11.push_back(S - a * c / (b + a + 0.)); x.push_back(b * c / (b + a + 0.)); y11.push_back(S - b * c / (b + a + 0.)); } if (b + c) { x.push_back(0); x.push_back(0); y11.push_back(b * a / (b + c + 0.)); z.push_back(S - b * a / (b + c + 0.)); y11.push_back(c * a / (b + c + 0.)); z.push_back(S - c * a / (b + c + 0.)); } if (a + c) { y11.push_back(0); y11.push_back(0); x.push_back(a * b / (c + a + 0.)); z.push_back(S - a * b / (c + a + 0.)); x.push_back(c * b / (c + a + 0.)); z.push_back(S - c * b / (c + a + 0.)); } for (int i = 0; i < x.size(); i++) { upd(x[i], y11[i], z[i]); } printf( %.11lf %.11lf %.11lf n , rx, ry, rz); return 0; } |
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// 64 bits worth of ticks
module time_compare
(input [63:0] time_now,
input [63:0] trigger_time,
output now,
output early,
output late,
output too_early);
assign now = time_now == trigger_time;
assign late = time_now > trigger_time;
assign early = ~now & ~late;
assign too_early = 0; //not implemented
endmodule // time_compare
|
// mbt 2-16-16
`include "bsg_defines.v"
module bsg_rocket_core_fsb
import bsg_fsb_packet::RingPacketType;
#(parameter nasti_destid_p="invalid"
, parameter htif_destid_p ="invalid"
, parameter htif_width_p = 16
, parameter ring_width_lp=$size(RingPacketType))
(input clk_i
, input reset_i
, input enable_i
// 0 = nasti, 1 = htif
, input [1:0] v_i
, input [1:0][ring_width_lp-1:0] data_i
, output [1:0] ready_o
, output [1:0] v_o
, output [1:0] [ring_width_lp-1:0] data_o
, input [1:0] yumi_i
);
wire w_ready, aw_ready, ar_ready, rd_ready, wr_ready;
bsg_nasti_write_data_channel_s w;
bsg_nasti_addr_channel_s ar;
bsg_nasti_addr_channel_s aw;
bsg_nasti_read_data_channel_s rd;
bsg_nasti_write_response_channel_s wr;
bsg_fsb_to_nasti_master_connector #(.destid_p(nasti_destid_p)) bsg_fsb_nasti_master
(.clk_i (clk_i )
,.reset_i (reset_i )
,.nasti_read_addr_ch_i (ar )
,.nasti_read_addr_ch_ready_o (ar_ready)
,.nasti_write_addr_ch_i (aw )
,.nasti_write_addr_ch_ready_o (aw_ready)
,.nasti_write_data_ch_i (w )
,.nasti_write_data_ch_ready_o (w_ready )
,.nasti_read_data_ch_o (rd )
,.nasti_read_data_ch_ready_i (rd_ready)
,.nasti_write_resp_ch_o (wr )
,.nasti_write_resp_ch_ready_i (rd_ready)
,.fsb_v_i (v_i [0])
,.fsb_data_i (data_i [0]) // --> from FSB
,.fsb_ready_o(ready_o[0])
,.fsb_v_o (v_o [0] )
,.fsb_data_o (data_o [0]) // --> to FSB
,.fsb_yumi_i (yumi_i [0])
);
wire htif_in_valid, htif_out_valid;
wire htif_in_ready, htif_out_ready;
wire [htif_width_p-1:0] htif_in_data;
wire [htif_width_p-1:0] htif_out_data;
bsg_fsb_to_htif_connector #(.destid_p(htif_destid_p)
,.htif_width_p(htif_width_p)
)
(.clk_i ( clk_i )
,.reset_i( reset_i )
// FSB interface
,.fsb_v_i ( v_i [1] )
,.fsb_data_i ( data_i [1] )
,.fsb_ready_o( ready_o[1] )
,.fsb_v_o ( v_o [1] )
,.fsb_data_o ( data_o [1] )
,.fsb_yumi_i ( yumi_i [1] )
// htif interface
,.htif_v_i ( htif_in_valid )
,.htif_data_i ( htif_in_data )
,.htif_ready_o ( htif_in_ready )
,.htif_v_o ( htif_out_valid )
,.htif_data_o ( htif_out_data )
,.htif_ready_o ( htif_out_ready )
);
top rocket
(.clk(clk_i)
,.reset(reset_i)
,.io_mem_0_ar_valid ( ar.v )
,.io_mem_0_ar_ready ( ar_ready )
,.io_mem_0_ar_bits_addr ( ar.addr )
,.io_mem_0_ar_bits_id ( ar.id )
,.io_mem_0_ar_bits_size ( ar.size )
,.io_mem_0_ar_bits_len ( ar.len )
,.io_mem_0_ar_bits_burst ()
,.io_mem_0_ar_bits_lock ()
,.io_mem_0_ar_bits_cache ()
,.io_mem_0_ar_bits_prot ()
,.io_mem_0_ar_bits_qos ()
,.io_mem_0_ar_bits_region ()
,.io_mem_0_ar_bits_user ()
,.io_mem_0_aw_valid ( aw.v )
,.io_mem_0_aw_ready ( aw_ready )
,.io_mem_0_aw_bits_addr ( aw.addr )
,.io_mem_0_aw_bits_id ( aw.id )
,.io_mem_0_aw_bits_size ( aw.size )
,.io_mem_0_aw_bits_len ( aw.len )
,.io_mem_0_aw_bits_burst ()
,.io_mem_0_aw_bits_lock ()
,.io_mem_0_aw_bits_cache ()
,.io_mem_0_aw_bits_prot ()
,.io_mem_0_aw_bits_qos ()
,.io_mem_0_aw_bits_region()
,.io_mem_0_aw_bits_user ()
,.io_mem_0_w_valid ( w.v )
,.io_mem_0_w_ready ( w_ready )
,.io_mem_0_w_bits_strb ( w.strb )
,.io_mem_0_w_bits_data ( w.data )
,.io_mem_0_w_bits_last ( w.last )
,.io_mem_0_w_bits_user ()
,.io_mem_0_r_valid ( r.v )
,.io_mem_0_r_ready ( r_ready )
,.io_mem_0_r_bits_resp ( r.resp )
,.io_mem_0_r_bits_id ( r.id )
,.io_mem_0_r_bits_data ( r.data )
,.io_mem_0_r_bits_last ( r.last )
,.io_mem_0_r_bits_user ( 1'b0 )
,.io_mem_0_b_valid ( wr.v )
,.io_mem_0_b_ready ( wr_ready )
,.io_mem_0_b_bits_resp ( wr.resp )
,.io_mem_0_b_bits_id ( wr.id )
,.io_mem_0_b_bits_user ( 1'b0 )
// we follow the "FPGA plan", because Berkeley "chip plan" currently broken
,.io_host_clk ()
,.io_host_clk_edge ()
,.io_host_debug_stats_csr ()
,.io_mem_backup_ctrl_en (1'b0)
,.io_mem_backup_ctrl_in_valid (1'b0)
,.io_mem_backup_ctrl_out_ready (1'b0)
,.io_mem_backup_ctrl_out_valid ()
// end "FPGA plan"
// this is the hostif; we need to attach it to the FSB as well
,.io_host_in_valid ( htif_in_valid )
,.io_host_in_ready ( htif_in_ready )
,.io_host_in_bits ( htif_in_bits )
,.io_host_out_valid ( htif_out_valid )
,.io_host_out_ready ( htif_out_ready )
,.io_host_out_bits ( htif_out_bits )
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_cpx_rptr_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_cpx_rptr_1 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
//output [7:0] sctag_cpx_req_cq_buf; // sctag to processor request
//output sctag_cpx_atom_cq_buf;
//output [`CPX_WIDTH-1:0] sctag_cpx_data_ca_buf; // sctag to cpx data pkt
//output [7:0] cpx_sctag_grant_cx_buf;
//input [7:0] sctag_cpx_req_cq; // sctag to processor request
//input sctag_cpx_atom_cq;
//input [`CPX_WIDTH-1:0] sctag_cpx_data_ca; // sctag to cpx data pkt
//input [7:0] cpx_sctag_grant_cx;
//assign sctag_cpx_atom_cq_buf = sctag_cpx_atom_cq;
//assign sctag_cpx_data_ca_buf = sctag_cpx_data_ca;
//assign cpx_sctag_grant_cx_buf = cpx_sctag_grant_cx;
//assign sctag_cpx_req_cq_buf = sctag_cpx_req_cq;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:02:41 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0_1/system_ov7670_vga_1_0_sim_netlist.v
// Design : system_ov7670_vga_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_vga_1_0,ov7670_vga,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_vga,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_vga_1_0
(pclk,
data,
rgb);
input pclk;
input [7:0]data;
output [15:0]rgb;
wire [7:0]data;
wire pclk;
wire [15:0]rgb;
system_ov7670_vga_1_0_ov7670_vga U0
(.data(data),
.pclk(pclk),
.rgb(rgb));
endmodule
(* ORIG_REF_NAME = "ov7670_vga" *)
module system_ov7670_vga_1_0_ov7670_vga
(rgb,
pclk,
data);
output [15:0]rgb;
input pclk;
input [7:0]data;
wire cycle;
wire [7:0]data;
wire p_0_in0;
wire pclk;
wire [15:0]rgb;
FDRE #(
.INIT(1'b0))
cycle_reg
(.C(pclk),
.CE(1'b1),
.D(p_0_in0),
.Q(cycle),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\rgb[15]_i_1
(.I0(cycle),
.O(p_0_in0));
FDRE \rgb_reg[0]
(.C(pclk),
.CE(cycle),
.D(data[0]),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(pclk),
.CE(p_0_in0),
.D(data[2]),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(pclk),
.CE(p_0_in0),
.D(data[3]),
.Q(rgb[11]),
.R(1'b0));
FDRE \rgb_reg[12]
(.C(pclk),
.CE(p_0_in0),
.D(data[4]),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(pclk),
.CE(p_0_in0),
.D(data[5]),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(pclk),
.CE(p_0_in0),
.D(data[6]),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(pclk),
.CE(p_0_in0),
.D(data[7]),
.Q(rgb[15]),
.R(1'b0));
FDRE \rgb_reg[1]
(.C(pclk),
.CE(cycle),
.D(data[1]),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[2]
(.C(pclk),
.CE(cycle),
.D(data[2]),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(pclk),
.CE(cycle),
.D(data[3]),
.Q(rgb[3]),
.R(1'b0));
FDRE \rgb_reg[4]
(.C(pclk),
.CE(cycle),
.D(data[4]),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(pclk),
.CE(cycle),
.D(data[5]),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(pclk),
.CE(cycle),
.D(data[6]),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(pclk),
.CE(cycle),
.D(data[7]),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[8]
(.C(pclk),
.CE(p_0_in0),
.D(data[0]),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(pclk),
.CE(p_0_in0),
.D(data[1]),
.Q(rgb[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; const int N = 1e5 + 3, M = 2e5 + 3; int b[N], st[N], tp, he[N], to[M], ne[M], d[N], a[N]; bool f[N]; void dfs(int x) { for (int i, j; i = he[x];) if (he[x] = ne[i], !f[j = i >> 1]) f[j] = 1, dfs(to[i]), st[++tp] = i; } int main() { int m, i, j, k, n = 0, t = 1; scanf( %d , &m), --m; for (i = 1; i <= m; ++i) if (scanf( %d , b + i), !mp[b[i]]) a[mp[b[i]] = ++n] = b[i]; for (i = 1; i <= m; ++i) { scanf( %d , &j); if (j < b[i]) puts( -1 ), exit(0); if (!mp[j]) a[mp[j] = ++n] = j; j = mp[j], k = mp[b[i]], ++d[j], ++d[k]; ne[++t] = he[j], to[t] = k, he[j] = t; ne[++t] = he[k], to[t] = j, he[k] = t; } for (i = 1, j = 0; i <= n; ++i) if (d[i] & 1) ++j; if (j > 2) puts( -1 ), exit(0); if (j == 2) { for (i = 1; i <= n; ++i) if (d[i] & 1) { dfs(i); break; } } else dfs(i = 1); if (tp < m) puts( -1 ), exit(0); for (printf( %d , a[i]), i = tp; i; --i) printf( %d , a[to[st[i]]]); return 0; } |
#include <bits/stdc++.h> char ar[10][10]; int q[10 * 10 * 10 * 10][3]; bool forb[10][10][10 * 10]; bool used[10][10][10 * 10]; int dir[9][2] = {{1, 1}, {1, 0}, {1, -1}, {0, 1}, {0, 0}, {0, -1}, {-1, 1}, {-1, 0}, {-1, -1}}; void BFS(void) { int x = 8, y = 1; q[1][0] = x; q[1][1] = y; q[1][2] = 1; used[x][y][1] = 1; for (int al = 1, at = 1; al <= at; al++) { x = q[al][0]; y = q[al][1]; if (x == 1 && y == 8) { printf( WIN n ); return; } for (int i = 0; i < 9; i++) { int cx = x + dir[i][0]; int cy = y + dir[i][1]; if (cx > 0 && cx <= 8 && cy > 0 && cy <= 8) if (!used[cx][cy][q[al][2] + 1]) if (!forb[cx][cy][q[al][2]] && !forb[cx][cy][q[al][2] + 1]) { q[++at][0] = cx; q[at][1] = cy; q[at][2] = q[al][2] + 1; used[cx][cy][q[al][2] + 1] = 1; } } } printf( LOSE n ); } int main() { for (int i = 1; i <= 8; i++) for (int j = 1; j <= 8; j++) { scanf( %c , &ar[i][j]); if (ar[i][j] == S ) for (int k = i; k <= 8; k++) forb[k][j][k - i + 1] = 1; } BFS(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MODULO = 1000000007; void ftime() {} void print_arr(int n, bool arr[]) { for (int i = 0; i < n; i++) { cout << arr[i] << ; } cout << n ; } void print_arr(int n, int arr[]) { for (int i = 0; i < n; i++) { cout << arr[i] << ; } cout << n ; } void print_vec(vector<int> &vec) { for (auto e : vec) { cout << e << ; } cout << n ; } void print_vec(vector<long long> &vec) { for (auto e : vec) { cout << e << ; } cout << n ; } void print_vec(vector<bool> &vec) { for (auto e : vec) { cout << e << ; } cout << n ; } static int speed_increase = []() { std::ios::sync_with_stdio(false); std::cin.tie(NULL); return 0; }(); void print_map(unordered_map<long long, long long> &comp) { for (auto e : comp) { cout << e.first << : << e.second << n ; } cout << n ; } vector<long long> fdp(1000, -1); long long fact(long long val) { if (fdp[val] > 0) { return fdp[val]; } if (val < 2) return 1; fdp[val] = (val * fact(val - 1)) % MODULO; return fdp[val]; } long long modexp(long long base, long long exponent) { long long res = 1; base = (base % MODULO + MODULO) % MODULO; while (exponent) { if (exponent & 1) res = (res * base) % MODULO; exponent >>= 1; base = (base * base) % MODULO; } return res; } int main() { int n, m; cin >> n >> m; vector<long long> vals(m + 1, 0); vector<long long> lights(m, 0); for (auto &x : lights) { cin >> x; } sort(lights.begin(), lights.end()); int last = 0; int curr; for (int i = 0; i < m; i++) { curr = lights[i]; vals[i] = curr - last - 1; last = curr; } vals[m] = n - last; long long sum = accumulate(vals.begin(), vals.end(), 0ll); long long ans = fact(sum) % MODULO; for (int i = 0; i < m + 1; i++) { if (vals[i] > 1) { ans *= modexp(fact(vals[i]), MODULO - 2); ans %= MODULO; } if (i != 0 && i != m && vals[i] > 1) { ans *= modexp(2, vals[i] - 1); ans %= MODULO; } } cout << ans; ftime(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char *argv[]) { int n; unsigned int a[200]; unsigned int ans; scanf( %d , &n); ans = 0; for (int i = 0; i < n; i++) scanf( %u , &a[i]); for (int i = 0; i < n; i++) { unsigned int temp = a[i]; if (temp > ans) ans = temp; for (int j = i + 1; j < n; j++) { temp = temp ^ a[j]; if (temp > ans) ans = temp; } } printf( %u n , ans); return 0; } |
module ram(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end // always @ (posedge clk)
endmodule // ram
module dram_256x16(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [DATA_WIDTH - 1 :0] mask,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 16;
localparam ADDR_WIDTH = 8;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
assign _d = d;
assign q = _q;
dram_#(
.MODE(0)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_256x16
module dram_512x8(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 8;
localparam ADDR_WIDTH = 9;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = d[i];
assign q[i] = _q[i * 2];
end
endgenerate
dram_#(
.MODE(1)
) dram(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_256x16
module dram_1024x4(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 4;
localparam ADDR_WIDTH = 10;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };
genvar i;
generate
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = d[i];
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
assign q[i] = _q[i * 4 + 1];
end
endgenerate
dram_#(
.MODE(2)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_1024x4
module dram_2048x2(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
localparam DATA_WIDTH = 2;
localparam ADDR_WIDTH = 11;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
wire [RAM_DATA_WIDTH - 1 : 0] _d, _q;
wire [RAM_ADDR_WIDTH - 1 : 0] _waddr, _raddr;
assign _waddr = waddr;
assign _raddr = raddr;
genvar i;
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = d[i];
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
assign q[i] = _q[i * 8 + 3];
end
dram_#(
.MODE(3)
) dram_(
.w_clk(w_clk),
.r_clk(r_clk),
.w_clk_en(w_clk_en),
.r_clk_en(r_clk_en),
.we(we),
.waddr(_waddr),
.d(_d),
.re(re),
.raddr(_raddr),
.q(_q),
.mask(16'b0)
);
endmodule // dram_2048x2
module dram_(
input w_clk,
input r_clk,
input w_clk_en,
input r_clk_en,
input we,
input [RAM_ADDR_WIDTH - 1 : 0] waddr,
input [RAM_DATA_WIDTH - 1 : 0] d,
input re,
input [RAM_DATA_WIDTH - 1 :0] mask,
input [RAM_ADDR_WIDTH - 1 : 0] raddr,
output [RAM_DATA_WIDTH - 1 : 0] q
);
parameter MODE = -1;
localparam RAM_DATA_WIDTH = 16;
localparam RAM_ADDR_WIDTH = 11;
SB_RAM40_4K #(
.WRITE_MODE(MODE),
.READ_MODE(MODE)
) bram (
.RDATA(q),
.RADDR(raddr),
.RCLK(r_clk),
.RCLKE(r_clk_en),
.RE(re),
.WADDR(waddr),
.WCLK(w_clk),
.WCLKE(w_clk_en),
.WDATA(d),
.WE(we),
.MASK(mask)
);
endmodule // dram_
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Implementation: we count down in quarter-baud amounts, sampling three
// points from the signal, at 1/4, 1/2, and 3/4. If they agree, we're happy.
// If they disagree, something is wrong and we transition to an error state.
//
// This comes at some complexity / area, but is nicer than sampling once in
// the anticipated center of the baud, because it can help us detect things
// like misconfigured baud rates or faulty transmitters. Ideally how we sample
// the signal could be some pluggable strategy, but we just choose the more
// robust checking-sampler here.
//
// If we see a voltage transition before the "4/4" baud point, we *could*
// adjust our notion of how long a baud actually is. However, given that the
// stop-bit / start-bit transition already is a "synchronizing" event, we'll
// avoid doing fancy things like that.
module uart_receiver(
input wire clk,
input wire rst_n,
input wire rx,
input wire rx_byte_done,
output wire clear_to_send_out,
output wire [7:0] rx_byte_out,
output wire rx_byte_valid_out
);
parameter ClocksPerBaud = 1250;
localparam QuarterBaud = (ClocksPerBaud >> 2);
localparam CountdownStart = QuarterBaud-1;
// Note: we shave one bit off the full clocks-per-baud-sized value because
// we only count down from the quarter-baud value.
localparam CountdownBits = $clog2(ClocksPerBaud >> 1);
localparam
StateIdle = 'd0,
StateStart = 'd1,
StateData = 'd2,
StateStop = 'd3,
// Sampled inconsistent values from the receive line.
StateInconsistentError = 'd4,
// Attempted to receive a byte when the previous byte hasn't been popped.
StateClobberError = 'd5,
// Did not sample three '1' values for stop bit.
StateStopBitError = 'd6;
localparam StateBits = 3;
`define ERROR_STATES StateInconsistentError,StateClobberError,StateStopBitError
reg [StateBits-1:0] state = StateIdle;
reg [2:0] samples = 0;
reg [1:0] sample_count = 0;
reg [2:0] data_bitno = 0;
reg [CountdownBits-1:0] rx_countdown = 0;
reg [7:0] rx_byte = 0;
reg rx_byte_valid = 0;
reg [StateBits-1:0] state_next;
// The data we've sampled from the current baud.
reg [2:0] samples_next;
// Tracks the number of samples we've collected from the current baud.
reg [1:0] sample_count_next;
// Tracks the bit number that we're populating in the received byte.
reg [2:0] data_bitno_next;
// Counts down to the next sampling / state transition activity.
reg [CountdownBits-1:0] rx_countdown_next;
// Storage for the received byte.
reg [7:0] rx_byte_next;
// Indicator that the received byte is complete and ready for consumption.
reg rx_byte_valid_next;
// Note: only in an idle or stop state can the outside world signal that the
// received byte is done (that is, without breaking the interface contract).
// Also, any time that the rx bit is not 1, something is currently in the
// process of being transmitted.
assign clear_to_send_out =
(state == StateIdle || state == StateStop) && (rx_byte_valid == 0) && (rx == 1);
assign rx_byte_out = rx_byte;
assign rx_byte_valid_out = rx_byte_valid;
// Several states transition when the countdown is finished and we've
// sampled three bits.
wire ready_to_transition;
assign ready_to_transition = rx_countdown == 0 && sample_count == 3;
// Check that the samples all contain the same sampled bit-value.
// This is the case when the and-reduce is equivalent to the or-reduce.
wire samples_consistent;
assign samples_consistent = &(samples) == |(samples);
// State updates.
always @(*) begin // verilog_lint: waive always-comb b/72410891
state_next = state;
case (state)
StateIdle: begin
if (rx == 0) begin
state_next = rx_byte_valid ? StateClobberError : StateStart;
end
end
StateStart: begin
if (rx_countdown == 0 && sample_count == 3) begin
state_next = samples_consistent ? StateData : StateInconsistentError;
end
end
StateData: begin
if (rx_countdown == 0 && sample_count == 3) begin
if (!samples_consistent) begin
state_next = StateInconsistentError;
end else if (data_bitno == 7) begin
state_next = StateStop;
end else begin
state_next = StateData;
end
end
end
StateStop: begin
if (rx_countdown == 0 && sample_count == 3) begin
if (&(samples) != 1) begin
// All stop-bit samples should be one.
state_next = StateStopBitError;
end else if (rx == 0) begin
// Permit transition straight to start state.
state_next = StateStart;
end else begin
// If the rx signal isn't already dropped to zero (indicating
// a start bit), we transition through the idle state.
state_next = StateIdle;
end
end
end
`ERROR_STATES: begin
// Stay in this state until we're externally reset.
end
default: begin
state_next = 3'hX;
end
endcase
end
// Non-state updates.
always @(*) begin // verilog_lint: waive always-comb b/72410891
samples_next = samples;
sample_count_next = sample_count;
data_bitno_next = data_bitno;
rx_countdown_next = rx_countdown;
rx_byte_next = rx_byte;
rx_byte_valid_next = rx_byte_valid;
case (state)
StateIdle: begin
samples_next = 0;
sample_count_next = 0;
rx_countdown_next = CountdownStart;
data_bitno_next = 0;
// Maintain the current "valid" value, dropping it if the outside
// world claims the byte is done.
rx_byte_valid_next = rx_byte_valid && !rx_byte_done;
end
StateStart: begin
if (rx_countdown == 0) begin
// Perform a sample.
samples_next[sample_count] = rx;
sample_count_next = sample_count + 1;
rx_countdown_next = CountdownStart;
end else begin
rx_countdown_next = rx_countdown - 1;
end
// Note: the following line is unnecessary, just makes waveforms
// easier to read (not shifting out garbage data).
rx_byte_next = 0;
data_bitno_next = 0;
end
StateData: begin
if (rx_countdown == 0) begin
if (sample_count == 3) begin
// Shift in the newly sampled bit. (Once we're done, the first
// sampled bit will be the LSb.)
rx_byte_next = {samples[0], rx_byte[7:1]};
// We flag the byte is done as early as we can, so we flop the new
// state in before we transition to the StateStop state. (Note:
// when we've just shifted in bitno 7 the data is ready).
rx_byte_valid_next = data_bitno == 7 && samples_consistent;
data_bitno_next = data_bitno + 1;
sample_count_next = 0;
end else begin
samples_next[sample_count] = rx;
sample_count_next = sample_count + 1;
end
rx_countdown_next = CountdownStart;
end else begin
rx_countdown_next = rx_countdown - 1;
end
end
StateStop: begin
// If the caller has dropped the valid signal by flagging "byte done"
// during the stop state we keep that property "sticky".
rx_byte_valid_next = rx_byte_valid == 0 || rx_byte_done ? 0 : 1;
// Set this up because we may transition StateStop->StateStart
// directly.
data_bitno_next = 0;
if (rx_countdown == 0) begin
samples_next[sample_count] = rx;
sample_count_next = sample_count + 1;
rx_countdown_next = CountdownStart;
end else begin
rx_countdown_next = rx_countdown - 1;
end
end
`ERROR_STATES: begin
rx_byte_next = 'hff;
rx_byte_valid_next = 0;
end
default: begin
samples_next = 'hX;
sample_count_next = 'hX;
data_bitno_next = 'hX;
rx_countdown_next = 'hX;
rx_byte_next = 'hX;
rx_byte_valid_next = 'hX;
end
endcase
end
// Note: our version of iverilog has no support for always_ff.
always @ (posedge clk) begin
if (rst_n == 0) begin
state <= StateIdle;
samples <= 0;
sample_count <= 0;
data_bitno <= 0;
rx_countdown <= 0;
rx_byte <= 0;
rx_byte_valid <= 0;
end else begin
state <= state_next;
samples <= samples_next;
sample_count <= sample_count_next;
data_bitno <= data_bitno_next;
rx_countdown <= rx_countdown_next;
rx_byte <= rx_byte_next;
rx_byte_valid <= rx_byte_valid_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_0_V
`define SKY130_FD_SC_LP__MAJ3_0_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__maj3_0 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__maj3_0 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_0_V
|
#include <bits/stdc++.h> using namespace std; int a[100004], d[32]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int j = 0; j < n; j++) { int x = a[j]; for (int i = 0; x > 0; i++) { d[i] += x % 2; x /= 2; } } int p = 1, e = 0; for (int i = 0; i < 32; i++) { if (d[i] == 1) { e += p; } p *= 2; } int c = -1, m = 0; for (int i = 0; i < n; i++) { int x = a[i] & e; if (x > m) { m = x; c = i; } } if (c != -1) { cout << a[c] << ; } for (int j = 0; j < n; j++) { if (c != j) cout << a[j] << ; } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [9:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [9:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({10'b0000000000, di[21:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[21:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({3'b000, addr}),
.DI({10'b0000000000,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
module top;
reg pass;
integer result;
reg [3:0] expr;
reg bval;
initial begin
pass = 1'b1;
result = $countbits(1'bx, 1'bx);
if (result != 1) begin
$display("FAILED: for 1'bx/x expected a count of 1, got %d", result);
pass = 1'b0;
end
result = $countbits(2'bxx, 1'bx);
if (result != 2) begin
$display("FAILED: for 2'bxx/x expected a count of 2, got %d", result);
pass = 1'b0;
end
result = $countbits(2'bxz, 1'bz, 1'bx);
if (result != 2) begin
$display("FAILED: for 2'bxz/zx expected a count of 2, got %d", result);
pass = 1'b0;
end
result = $countbits(4'b01zx, 1'bz, 1'bx);
if (result != 2) begin
$display("FAILED: for 4'b01zx/zx expected a count of 2, got %d", result);
pass = 1'b0;
end
result = $countbits(4'b01zx, 1'b0, 1'b1);
if (result != 2) begin
$display("FAILED: for 4'b01zx/01 expected a count of 2, got %d", result);
pass = 1'b0;
end
bval = 1'b0;
expr = 4'b1001;
result = $countbits(expr, bval);
if (result != 2) begin
$display("FAILED: for 4'b1001/0 expected a count of 2, got %d", result);
pass = 1'b0;
end
bval = 1'b1;
result = $countbits(expr, bval);
if (result != 2) begin
$display("FAILED: for 4'b1001/1 expected a count of 2, got %d", result);
pass = 1'b0;
end
result = $countbits(34'bzx00000000000000000000000000000000, 1'bz, 1'bx);
if (result != 2) begin
$display("FAILED: for 34'zx00000000000000000000000000000000/zx expected a count of 2, got %d", result);
pass = 1'b0;
end
result = $countbits(34'bzxxz000000xz000000xz000000xz000000, 1'bz, 1'bx);
if (result != 10) begin
$display("FAILED: for 34'zxxz000000xz000000xz000000xz000000/zx expected a count of 10, got %d", result);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool primes[1000007]; void sieve(int n) { for (long long i = 2; i <= n; i++) { if (primes[i]) continue; for (long long j = i * i; j <= n; j += i) { primes[j] = 1; } } } int main() { int n; cin >> n; sieve(1e6); while (n--) { long long tmp; scanf( %I64d , &tmp); long long limit = sqrt(tmp); if (tmp == 1) printf( NO n ); else if (limit * limit == tmp && tmp % 2 && !primes[limit]) printf( YES n ); else if (tmp == 4) printf( YES n ); else printf( NO n ); } } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_mux_64_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_0_axis_tdata = 0;
reg [7:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [63:0] input_1_axis_tdata = 0;
reg [7:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [63:0] input_2_axis_tdata = 0;
reg [7:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [63:0] input_3_axis_tdata = 0;
reg [7:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_mux_64_4.lxt");
$dumpvars(0, test_axis_mux_64_4);
end
axis_mux_64_4 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int fib[51]; vector<long long int> calc(long long int n, long long int k) { vector<long long int> res; if (!n) return res; if (n == 1) { res.push_back(1); return res; } if (k <= fib[n - 1]) { res.push_back(1); vector<long long int> v = calc(n - 1, k); for (auto i : v) res.push_back(i + 1); } else { res.push_back(2); res.push_back(1); vector<long long int> v = calc(n - 2, k - fib[n - 1]); for (auto i : v) res.push_back(i + 2); } return res; } void solve() { fib[1] = 1, fib[2] = 2; for (long long int i = 3; i <= 50; i++) fib[i] = fib[i - 1] + fib[i - 2]; long long int n, k; cin >> n >> k; vector<long long int> ans = calc(n, k); for (auto i : ans) cout << i << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cout.precision(20); long long int t = 1; for (long long int i = 1; i <= t; i++) { if (0) cout << Case # << i << : ; solve(); } } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/26/07 - Add else to handle x case for o_out (CR 424214).
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 03/19/09 - CR 511590 - Added Z condition handling
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 10/14/09 - CR 535630 - Added DIFF_TERM attribute.
// 05/12/10 - CR 559468 - Added DRC warnings for LVDS_25 bus architectures.
// 12/01/10 - CR 584500 - added attribute SLEW
// 08/08/11 - CR 616816 - ncsim compile error during XIL_TIMING
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/28/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS (O, IO, IOB, I, T);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
localparam MODULE_NAME = "IOBUFDS";
output O;
inout IO, IOB;
input I, T;
wire i_in, io_in, iob_in, t_in;
reg o_out, io_out, iob_out;
reg O_int;
reg DQS_BIAS_BINARY = 1'b0;
wire t_or_gts;
tri0 GTS = glbl.GTS;
assign i_in = I;
assign t_in = T;
assign io_in = IO;
assign iob_in = IOB;
assign t_or_gts = GTS || t_in;
assign IO = t_or_gts ? 1'bz : i_in;
assign IOB = t_or_gts ? 1'bz : ~i_in;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
#1 $finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
#1 $finish;
end
endcase
if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin
$display("DRC Warning : The IOSTANDARD attribute on %s instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", MODULE_NAME, IOSTANDARD);
end
end
always @(io_in or iob_in or DQS_BIAS_BINARY) begin
if (io_in == 1'b1 && iob_in == 1'b0)
o_out <= 1'b1;
else if (io_in == 1'b0 && iob_in == 1'b1)
o_out <= 1'b0;
else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((io_in === 1'bx) || (iob_in == 1'bx))
o_out <= 1'bx;
end
// assign O = (t_in === 1'b0) ? 1'b1 : ((t_in === 1'b1) ? o_out : 1'bx));
assign O = o_out;
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
(T => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
module DataPath
(
input wire b_sel,
input wire a_sel,
input wire add_sel,
input wire prod_sel,
input wire [31:0]Data_A,
input wire [31:0]Data_B,
input wire Shift_Enable,
input wire Clock,
input wire Reset,
output reg [63:0]Prod,
output wire oB_LSB
);
//-------------PARA B-----------------//
wire [31:0]Mux_B_Out;
wire [31:0]Reg_B_Out;
wire [31:0]Shifted_B;
assign oB_LSB= Reg_B_Out[0];
assign Shifted_B = Reg_B_Out >>1;
MUX #(32) Mux_B
(
.Select(b_sel),
.Data_A(Shifted_B),
.Data_B(Data_B),
.Out(Mux_B_Out)
);
FFD #(32) Reg_B
(
.Clock(Clock),
.Reset(Reset),
.Enable(1),
.D(Mux_B_Out),
.Q(Reg_B_Out)
);
/*Shift_Register_Right Shift_B
( .Clock(Clock),
.Data(Reg_B_Out),
.Enable(Shift_Enable),
.Shifted_Data(Shifted_B)
);*/
//--------PARA A----------//
wire [63:0]Mux_A_Out;
wire [63:0]Reg_A_Out;
wire [63:0]Shifted_A;
wire [63:0]A_64_Bits;
assign Shifted_A = {32'b0,Reg_A_Out} <<1;
assign A_64_Bits = {32'b0,Data_A} ;
MUX #(64) Mux_A
(
.Select(a_sel),
.Data_A(Shifted_A),
.Data_B(A_64_Bits),
.Out(Mux_A_Out)
);
FFD #(64) Reg_A
(
.Clock(Clock),
.Reset(Reset),
.Enable(1),
.D(Mux_A_Out),
.Q(Reg_A_Out)
);
/*
Shift_Register_Left Shift_A
( .Clock(Clock),
.Data(Reg_A_Out),
.Enable(Shift_Enable),
.Shifted_Data(Shifted_A)
);*/
//--------PARA EL PRODUCTO------------//
wire [63:0]Mux_Prod_Out;
wire [63:0]Add_Out;
wire [63:0]Sum_Prod;
MUX #(64) Mux_Prod1
(
.Select(prod_sel),
.Data_A(Sum_Prod),
.Data_B(64'b0),
.Out(Mux_Prod_Out)
);
wire [63:0]Product;
always @ (Product)
Prod=Product;
FFD #(64) Reg_Prod
(
.Clock(Clock),
.Reset(Reset),
.Enable(1),
.D(Mux_Prod_Out),
.Q(Product)
);
ADDER Adder_Prod
(
.Data_A(Reg_A_Out),
.Data_B(Product),
.Result(Add_Out)
);
MUX #(64) Mux_Prod0
(
.Select(add_sel),
.Data_A(Add_Out),
.Data_B(Product),
.Out(Sum_Prod)
);
endmodule
///////////////////MUX//////////////////
module MUX #(parameter SIZE=32)
(
input wire Select,
input wire [SIZE-1:0]Data_B,
input wire [SIZE-1:0]Data_A,
output reg [SIZE-1:0] Out
);
always @(*)
begin
if(Select==1)
Out<=Data_A;
else if (Select==0)
Out<=Data_B;
end
endmodule
///////////////REGISTER///////////////
module FFD # ( parameter SIZE=32 )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= 0;
else
begin
if (Enable)
Q <= D;
end
end
endmodule
////////////////SHIFT REGISTER RIGHT//////////
module Shift_Register_Right
( input wire Clock,
input wire [31:0]Data,
input wire Enable,
output reg [31:0]Shifted_Data
);
reg newClock;
initial
begin
newClock =0;
end
always
begin
# 125 newClock =1;
# 125 newClock =0;
end
always @( posedge newClock)
if(Enable)
begin
Shifted_Data = Data>>1;
end
else
begin
Shifted_Data = Data;
end
endmodule
////////////SHIFT REGISTER LEFT//////////////
module Shift_Register_Left
( input wire Clock,
input wire [31:0]Data,
input wire Enable,
output reg [31:0]Shifted_Data
);
reg newClock;
initial
begin
newClock =0;
end
always
begin
# 125 newClock =1;
# 125 newClock =0;
end
always @(posedge newClock)
if(Enable)
begin
Shifted_Data = Data<<1;
end
else
begin
Shifted_Data = Data;
end
endmodule
////////////ADDER///////////////////////////
module ADDER
(
input wire [63:0]Data_A,
input wire [63:0]Data_B,
output reg [63:0]Result
);
always @(*)
begin
Result <= Data_B + Data_A;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 10000000; long long n, a, b; long long dp[N + 1]; signed main() { cin >> n >> a >> b; dp[0] = 0; for (long long i = 1; i <= n; i++) if (i & 1) dp[i] = min(dp[i - 1] + a, dp[i + 1 >> 1] + a + b); else dp[i] = min(dp[i - 1] + a, dp[i >> 1] + b); cout << dp[n]; return 0; } |
//
// Paul Gao 02/2021
//
// This module generates 180-degree-phase-shifted clock (inverted clock)
//
// Input clock runs at 1x speed
// Output clock is generated with XOR logic
// Waveform below shows the detailed behavior of the module
//
// THIS MODULE SHOULD BE HARDENED TO IMPROVE QUALITY OF CLK_O
//
// WARNING:
// Source of clk_o is combinational logic instead of a register
// Duty-cycle of clk_o may not be ideal under certain cirtumstances
// Using negedge of clk_o may result in timing violation
//
/****************************************************************************
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
clk_i | | | | | | | | | | | | | | |
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
+--------+
reset_i |
+------------------------------------------------------+
+-------+ +-------+ +-------+
clk_r_p | | | | | |
+----------------+ +-------+ +-------+ +------+
+-------+ +-------+ +-------+ +--+
clk_r_n | | | | | | |
+------------+ +-------+ +-------+ +-------+
+---+ +---+ +---+ +---+ +---+ +---+ +--+
clk_o | | | | | | | | | | | | |
+------------+ +---+ +---+ +---+ +---+ +---+ +---+
****************************************************************************/
module bsg_link_osdr_phy_phase_align
(input clk_i
,input reset_i
,output clk_o
);
logic clk_r_p, clk_r_n;
bsg_xor #(.width_p(1)) clk_xor
(.a_i(clk_r_p),.b_i(clk_r_n),. o(clk_o));
bsg_dff_reset #(.width_p(1),.reset_val_p(0)) clk_ff_p
(.clk_i(clk_i),.reset_i(reset_i),.data_i(~clk_r_p),.data_o(clk_r_p));
bsg_dff_reset #(.width_p(1),.reset_val_p(0)) clk_ff_n
(.clk_i(~clk_i),.reset_i(reset_i),.data_i(~clk_r_n),.data_o(clk_r_n));
// synopsys translate_off
initial
begin
$display("## %L: instantiating unhardened bsg_link_osdr_phase_align (%m)");
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> solve(int k) { vector<string> s; if (k == 0) { s.push_back( + ); return s; } vector<string> prev = solve(k - 1), rev; for (int i = 0; i < prev.size(); i++) { string temp; for (int j = 0; j < prev.size(); j++) { if (prev[i][j] == + ) temp += * ; else temp += + ; } rev.push_back(temp); } for (int i = 0; i < prev.size(); i++) { s.push_back(prev[i] + prev[i]); s.push_back(prev[i] + rev[i]); } return s; } int main() { int k; cin >> k; vector<string> s; s = solve(k); for (int i = 0; i < s.size(); i++) { cout << s[i] << endl; } } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_nios2_qsys_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_slave_rrp #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
parameter integer FIFO_DEPTH = 32, // > 0 (don't care if SLAVE_FIXED_LATENCY > 0)
parameter integer USE_LL_FIFO = 1, // 0|1
parameter integer SLAVE_FIXED_LATENCY = 0, // 0=not fixed latency, >0=# fixed latency cycles
// if >0 effectively FIFO_DEPTH=SLAVE_FIXED_LATENCY+1
parameter integer PIPELINE = 1 // 0|1
)
(
input logic clock,
input logic resetn,
acl_arb_intf m_intf,
input logic s_readdatavalid,
input logic [DATA_W-1:0] s_readdata,
acl_ic_rrp_intf rrp_intf,
output logic stall
);
typedef struct packed {
logic valid;
logic [DATA_W-1:0] data;
} slave_raw_read;
slave_raw_read slave_read_in;
slave_raw_read slave_read; // this is the slave interface to the rest of the module
assign slave_read_in = {s_readdatavalid, s_readdata};
generate
if( PIPELINE )
begin
// Pipeline the return path from the slave.
slave_raw_read slave_read_pipe;
always @(posedge clock or negedge resetn)
if( !resetn )
begin
slave_read_pipe <= 'x;
slave_read_pipe.valid <= 1'b0;
end
else begin
if (m_intf.req.enable) begin
slave_read_pipe <= slave_read_in;
end
end
assign slave_read = slave_read_pipe;
end
else
begin
assign slave_read = slave_read_in;
end
endgenerate
generate
if( NUM_MASTERS > 1 )
begin
localparam READ_FIFO_DEPTH = SLAVE_FIXED_LATENCY > 0 ? SLAVE_FIXED_LATENCY : FIFO_DEPTH;
typedef struct packed {
logic [ID_W-1:0] id;
logic [BURSTCOUNT_W-1:0] burstcount;
} raw_read_item;
typedef struct packed {
logic valid;
logic [ID_W-1:0] id;
logic [BURSTCOUNT_W-1:0] burstcount;
} read_item;
logic rf_full, rf_empty, rf_read, rf_write, next_read_item;
raw_read_item m_raw_read_item, rf_raw_read_item;
read_item rf_read_item, cur_read_item;
if (READ_FIFO_DEPTH == 1)
begin
assign rf_raw_read_item = m_raw_read_item;
end
// FIFO of pending reads.
// Two parts to this FIFO:
// 1. An actual FIFO (either llfifo or scfifo).
// 2. cur_read_item is the current pending read
//
// Together, there must be at least READ_FIFO_DEPTH
// entries. Since cur_read_item counts as one,
// the actual FIFOs are sized to READ_FIFO_DEPTH-1.
else if( USE_LL_FIFO == 1 )
begin
acl_ll_fifo #(
.WIDTH( $bits(raw_read_item) ),
.DEPTH( READ_FIFO_DEPTH - 1 )
)
read_fifo(
.clk( clock ),
.reset( ~resetn ),
.data_in( m_raw_read_item ),
.write( rf_write ),
.data_out( rf_raw_read_item ),
.read( rf_read ),
.empty( rf_empty ),
.full( rf_full )
);
end
else
begin
scfifo #(
.lpm_width( $bits(raw_read_item) ),
.lpm_widthu( $clog2(READ_FIFO_DEPTH-1) ),
.lpm_numwords( READ_FIFO_DEPTH-1 ),
.add_ram_output_register( "ON" ),
.intended_device_family( "stratixiv" )
)
read_fifo (
.aclr( ~resetn ),
.clock( clock ),
.empty( rf_empty ),
.full( rf_full ),
.data( m_raw_read_item ),
.q( rf_raw_read_item ),
.wrreq( rf_write ),
.rdreq( rf_read ),
.sclr(),
.usedw(),
.almost_full(),
.almost_empty()
);
end
assign m_raw_read_item.id = m_intf.req.id;
assign m_raw_read_item.burstcount = m_intf.req.burstcount;
assign rf_read_item.id = rf_raw_read_item.id;
assign rf_read_item.burstcount = rf_raw_read_item.burstcount;
// Place incoming read requests from the master into read FIFO.
assign rf_write = ~m_intf.stall & m_intf.req.read & m_intf.req.enable;
// Read next item from the FIFO.
assign rf_read = ~rf_empty & (~rf_read_item.valid | next_read_item) & m_intf.req.enable;
// Determine when cur_read_item can be updated, which is controlled by next_read_item.
assign next_read_item = ~cur_read_item.valid | (slave_read.valid & (cur_read_item.burstcount == 1));
// Stall upstream when read FIFO is full. If the slave is fixed latency, the read FIFO
// is sized such that it can never stall.
assign stall = SLAVE_FIXED_LATENCY > 0 ? 1'b0 : rf_full;
// cur_read_item
always @( posedge clock or negedge resetn )
begin
if( !resetn )
begin
cur_read_item <= 'x; // only fields explicitly reset below need to be reset at all
cur_read_item.valid <= 1'b0;
end
else
begin
if( next_read_item & m_intf.req.enable) begin
// Update current read from the read FIFO.
cur_read_item <= rf_read_item;
end else if( slave_read.valid & m_intf.req.enable) begin
// Handle incoming data from the slave.
cur_read_item.burstcount <= cur_read_item.burstcount - 1;
end
end
end
// rrp_intf
assign rrp_intf.datavalid = slave_read.valid;
assign rrp_intf.data = slave_read.data;
assign rrp_intf.id = cur_read_item.id;
if (READ_FIFO_DEPTH == 1) begin
assign rf_read_item.valid = rf_write;
end
// Handle the rf_read_item.valid signal. Different behavior between
// sc_fifo and acl_ll_fifo.
else if( USE_LL_FIFO == 1 )
begin
// The data is already at the output of the acl_ll_fifo, so the
// data is valid as long as the FIFO is not empty.
assign rf_read_item.valid = ~rf_empty;
end
else
begin
// The data is valid on the next cycle (due to output register on
// scfifo RAM block).
always @( posedge clock or negedge resetn )
begin
if( !resetn )
rf_read_item.valid <= 1'b0;
else if( rf_read & m_intf.req.enable)
rf_read_item.valid <= 1'b1;
else if( next_read_item & ~rf_read & & m_intf.req.enable)
rf_read_item.valid <= 1'b0;
end
end
end
else // NUM_MASTERS == 1
begin
// Only one master so don't need to check the id.
assign rrp_intf.datavalid = slave_read.valid;
assign rrp_intf.data = slave_read.data;
assign stall = 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> struct event { int t, time, L, R, idx; event() {} event(int t, int time, int L, int R, int idx) : t(t), time(time), L(L), R(R), idx(idx) {} bool operator<(const event& a) const { return (time < a.time || (time == a.time && t < a.t)); } } e[200005 * 23]; int n, m, i, j, ai, place[200005], L, R, en, idx, ans[200005], fw[200005]; void modify(int j) { for (; j <= n; j = (j | (j - 1)) + 1) ++fw[j]; } int query(int j) { int rt = 0; for (; j; j &= (j - 1)) rt += fw[j]; return rt; } int main(int argc, char* const argv[]) { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { scanf( %d , &ai); place[ai] = i; } for (i = 1; i <= m; i++) { scanf( %d%d , &L, &R); e[++en] = event(2, R, L, R, i); e[++en] = event(2, L - 1, L, R, -i); } for (i = 1; i <= n; i++) { j = i; while (j <= n) { e[++en] = event(1, place[i], place[j], 0, 0); j += i; } } std::sort(e + 1, e + en + 1); for (i = 1; i <= en; i++) if (e[i].t == 1) modify(e[i].L); else { idx = abs(e[i].idx); ans[idx] += (query(e[i].R) - query(e[i].L - 1)) * (e[i].idx / idx); } for (i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; } |
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : RAM Control Block
// File : ram_ctl.v
// Author : Jim MacLeod
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//-- Modified Cursor Ram logic. NO LONGER USING INTERLEAVE.
//-- CURSOR PIXEL READ IS NOW USING THE EVEN SIDE ONLY.
//-- THE ODD PORT OF THE CURSOR IS NOW PERMANANTLY TIED TO 0.
//
/////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module ram_ctl
(
input pixclk,
input hresetn,
input colres,
input sixbitlin,
input [7:0] p0_red_pal_adr,
input [7:0] p0_grn_pal_adr,
input [7:0] p0_blu_pal_adr,
input [7:0] palr2dac_evn,
input [7:0] palg2dac_evn,
input [7:0] palb2dac_evn,
output reg [7:0] p0_red_pal, // Output to Dac.
output reg [7:0] p0_grn_pal, // Output to Dac.
output reg [7:0] p0_blu_pal, // Output to Dac.
output reg [7:0] palr_addr_evn,
output reg [7:0] palg_addr_evn,
output reg [7:0] palb_addr_evn
);
wire apply_lin = ! (colres | sixbitlin);
//---------------------- address for palette -----
always @( posedge pixclk or negedge hresetn)
if (!hresetn) begin
palr_addr_evn <= 8'b0;
palg_addr_evn <= 8'b0;
palb_addr_evn <= 8'b0;
end else begin
palr_addr_evn <= p0_red_pal_adr;
palg_addr_evn <= p0_grn_pal_adr;
palb_addr_evn <= p0_blu_pal_adr;
end
//-------------- Mux the odd / even data from palette -----
always @( posedge pixclk or negedge hresetn)
if (!hresetn) begin
p0_red_pal <= 8'b0;
p0_grn_pal <= 8'b0;
p0_blu_pal <= 8'b0;
end else begin
p0_red_pal <= apply_lin ? {palr2dac_evn[7:2] ,palr2dac_evn[7:6]} :
palr2dac_evn ;
p0_grn_pal <= apply_lin ? {palg2dac_evn[7:2] ,palg2dac_evn[7:6]} :
palg2dac_evn ;
p0_blu_pal <= apply_lin ? {palb2dac_evn[7:2] ,palb2dac_evn[7:6]} :
palb2dac_evn ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_LP2_V
`define SKY130_FD_SC_LP__MUX2I_LP2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_lp2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_lp2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_LP2_V
|
#include <bits/stdc++.h> using namespace std; int n, arr[100000], r, arr1[100000], z; bool boo[100000]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> r; arr[i] = r; } for (int i = 0; i < n; i++) arr1[i] = arr[i]; reverse(arr1, arr1 + n); z = arr1[0]; boo[0] = 1; for (int i = 0; i < n; i++) { if (arr1[i] > z) boo[i] = 1; if (arr1[i] >= z) z = arr1[i]; else arr1[i] = z; } reverse(arr1, arr1 + n); reverse(boo, boo + n); for (int i = 0; i < n; i++) { int k = arr1[i] - arr[i]; if (boo[i] == 1) cout << 0 << endl; else cout << k + 1 << endl; } return 0; } |
`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
`include "../../../rtl/verilog/gfx/gfx_line.v"
`include "../../../rtl/verilog/gfx/gfx_triangle.v"
`include "../../../rtl/verilog/gfx/div_uu.v"
module raster_bench();
parameter point_width = 16;
parameter subpixel_width = 16;
reg clk_i;
reg rst_i;
reg clip_ack_i;
reg interp_ack_i;
wire ack_o;
reg rect_write_i;
reg line_write_i;
reg triangle_write_i;
reg interpolate_i;
reg texture_enable_i;
reg clipping_enable_i;
reg [point_width-1:0] src_pixel0_x_i;
reg [point_width-1:0] src_pixel0_y_i;
reg [point_width-1:0] src_pixel1_x_i;
reg [point_width-1:0] src_pixel1_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_y_i;
reg [point_width-1:0] clip_pixel0_x_i;
reg [point_width-1:0] clip_pixel0_y_i;
reg [point_width-1:0] clip_pixel1_x_i;
reg [point_width-1:0] clip_pixel1_y_i;
reg [point_width-1:0] target_size_x_i;
reg [point_width-1:0] target_size_y_i;
wire [point_width-1:0] x_counter_o;
wire [point_width-1:0] y_counter_o;
wire [point_width-1:0] u_o;
wire [point_width-1:0] v_o;
wire clip_write_o;
wire interp_write_o;
parameter FIXEDW = 2**subpixel_width;
initial begin
$dumpfile("raster.vcd");
$dumpvars(0,raster_bench);
// init values
clk_i = 0;
rst_i = 1;
clip_ack_i = 0;
interp_ack_i = 0;
rect_write_i = 0;
line_write_i = 0;
triangle_write_i = 0;
interpolate_i = 0;
dest_pixel0_x_i = -5 * FIXEDW;
dest_pixel0_y_i = 5 * FIXEDW;
dest_pixel1_x_i = 10 * FIXEDW;
dest_pixel1_y_i = 10 * FIXEDW;
dest_pixel2_x_i = 5 * FIXEDW;
dest_pixel2_y_i = 10 * FIXEDW;
src_pixel0_x_i = 5;
src_pixel0_y_i = 5;
src_pixel1_x_i = 10;
src_pixel1_y_i = 10;
clip_pixel0_x_i = 0;
clip_pixel0_y_i = 0;
clip_pixel1_x_i = 10;
clip_pixel1_y_i = 10;
target_size_x_i = 640;
target_size_y_i = 480;
texture_enable_i = 0;
clipping_enable_i = 0;
//timing
#4 rst_i = 0;
#2 rect_write_i = 1;
#2 rect_write_i = 0;
#100 line_write_i = 1;
#2 line_write_i = 0;
#100 triangle_write_i = 1;
#2 triangle_write_i = 0;
// end sim
#1000 $finish;
end
always begin
#1 clk_i = ~clk_i;
end
always @(posedge clk_i)
begin
clip_ack_i <= #1 clip_write_o;
interp_ack_i <= #1 interp_write_o;
end
gfx_rasterizer #(point_width, subpixel_width) raster(
.clk_i (clk_i),
.rst_i (rst_i),
.clip_ack_i (clip_ack_i),
.interp_ack_i (interp_ack_i),
.ack_o (ack_o),
.rect_write_i (rect_write_i),
.line_write_i (line_write_i),
.triangle_write_i (triangle_write_i),
.interpolate_i (interpolate_i),
.texture_enable_i (texture_enable_i),
.src_pixel0_x_i (src_pixel0_x_i),
.src_pixel0_y_i (src_pixel0_y_i),
.src_pixel1_x_i (src_pixel1_x_i),
.src_pixel1_y_i (src_pixel1_y_i),
.dest_pixel0_x_i (dest_pixel0_x_i),
.dest_pixel0_y_i (dest_pixel0_y_i),
.dest_pixel1_x_i (dest_pixel1_x_i),
.dest_pixel1_y_i (dest_pixel1_y_i),
.dest_pixel2_x_i (dest_pixel2_x_i),
.dest_pixel2_y_i (dest_pixel2_y_i),
.clipping_enable_i(clipping_enable_i),
.clip_pixel0_x_i (clip_pixel0_x_i),
.clip_pixel0_y_i (clip_pixel0_y_i),
.clip_pixel1_x_i (clip_pixel1_x_i),
.clip_pixel1_y_i (clip_pixel1_y_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.x_counter_o (x_counter_o),
.y_counter_o (y_counter_o),
.u_o (u_o),
.v_o (v_o),
.clip_write_o (clip_write_o),
.interp_write_o (interp_write_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 505; const int mod = 1000000007; int a, b, c, d, e, f, g, h, i, j; int Mi[N * N]; int F[N][N], K; void Work() { Mi[0] = 1; for (int ii = 1; ii <= a * a; ii++) Mi[ii] = (Mi[ii - 1] << 1) % mod; F[0][0] = 1; for (int ii = 1; ii <= a; ii++) for (int jj = 1; jj <= K; jj++) { for (int kk = 0; kk < ii; kk++) (F[ii][jj] += (long long)F[kk][jj - 1] * (Mi[ii - kk] - 1) % mod * (Mi[(ii - kk) * kk]) % mod) %= mod; } int an = 0; for (int ii = 0; ii <= a; ii++) (an += (long long)F[ii][K] * Mi[(a - ii) * ii] % mod) %= mod; cout << an << endl; } int main() { cin >> a >> K; Work(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for vector sizes
localparam WA = 8; // address dimension size
localparam NO = 6; // number of access events
// 1D vectors
logic [WA-1:0] vector_bg; // big endian vector
/* verilator lint_off LITENDIAN */
logic [0:WA-1] vector_lt; // little endian vector
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'bx)
if (cnt[30:2]==0) vector_bg <= 'x;
else if (cnt[30:2]==1) vector_bg <= 'x;
else if (cnt[30:2]==2) vector_bg <= 'x;
else if (cnt[30:2]==3) vector_bg <= 'x;
else if (cnt[30:2]==4) vector_bg <= 'x;
else if (cnt[30:2]==5) vector_bg <= 'x;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the vector using assignment patterns
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) vector_bg <= '{ 3, 2, 1, 0, '0, '1, 1'b1, 1'b0};
else if (cnt[30:2]==2) vector_bg <= '{0:3, 1:2, 2:1, 3:0, 4:'0, 5:'1, 6:1'b1, 7:1'b0};
else if (cnt[30:2]==3) vector_bg <= '{default:'1};
else if (cnt[30:2]==4) vector_bg <= '{2:'1, default:'0};
else if (cnt[30:2]==5) vector_bg <= '{cnt+0, cnt+1, cnt+2, cnt+3, cnt+4, cnt+5, cnt+6, cnt+7};
end else if (cnt[1:0]==2'd2) begin
// chack vector agains expected value
if (cnt[30:2]==0) begin if (vector_bg !== 8'bxxxxxxxx) begin $display("%b", vector_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (vector_bg !== 8'b10100110) begin $display("%b", vector_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (vector_bg !== 8'b01100101) begin $display("%b", vector_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (vector_bg !== 8'b11111111) begin $display("%b", vector_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (vector_bg !== 8'b00000100) begin $display("%b", vector_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (vector_bg !== 8'b10101010) begin $display("%b", vector_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'bx)
if (cnt[30:2]==0) vector_lt <= 'x;
else if (cnt[30:2]==1) vector_lt <= 'x;
else if (cnt[30:2]==2) vector_lt <= 'x;
else if (cnt[30:2]==3) vector_lt <= 'x;
else if (cnt[30:2]==4) vector_lt <= 'x;
else if (cnt[30:2]==5) vector_lt <= 'x;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the vector using assignment patterns
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) vector_lt <= '{ 3, 2, 1, 0, '0, '1, 1'b1, 1'b0};
else if (cnt[30:2]==2) vector_lt <= '{0:3, 1:2, 2:1, 3:0, 4:'0, 5:'1, 6:1'b1, 7:1'b0};
else if (cnt[30:2]==3) vector_lt <= '{default:'1};
else if (cnt[30:2]==4) vector_lt <= '{2:'1, default:'0};
else if (cnt[30:2]==5) vector_lt <= '{cnt+0, cnt+1, cnt+2, cnt+3, cnt+4, cnt+5, cnt+6, cnt+7};
end else if (cnt[1:0]==2'd2) begin
// chack vector agains expected value
if (cnt[30:2]==0) begin if (vector_lt !== 8'bxxxxxxxx) begin $display("%b", vector_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (vector_lt !== 8'b10100110) begin $display("%b", vector_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (vector_lt !== 8'b10100110) begin $display("%b", vector_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (vector_lt !== 8'b11111111) begin $display("%b", vector_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (vector_lt !== 8'b00100000) begin $display("%b", vector_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (vector_lt !== 8'b10101010) begin $display("%b", vector_lt); $stop(); end end
end
endmodule
|
module test(
input clk, wen,
input [7:0] uns,
input signed [7:0] a, b,
input signed [23:0] c,
input signed [2:0] sel,
output [15:0] s, d, y, z, u, q, p, mul, div, mod, mux, And, Or, Xor, eq, neq, gt, lt, geq, leq, eqx, shr, sshr, shl, sshl, Land, Lor, Lnot, Not, Neg, pos, Andr, Orr, Xorr, Xnorr, Reduce_bool,
output [7:0] PMux
);
//initial begin
//$display("shr = %b", shr);
//end
assign s = a+{b[6:2], 2'b1};
assign d = a-b;
assign y = x;
assign z[7:0] = s+d;
assign z[15:8] = s-d;
assign p = a & b | x;
assign mul = a * b;
assign div = a / b;
assign mod = a % b;
assign mux = x[0] ? a : b;
assign And = a & b;
assign Or = a | b;
assign Xor = a ^ b;
assign Not = ~a;
assign Neg = -a;
assign eq = a == b;
assign neq = a != b;
assign gt = a > b;
assign lt = a < b;
assign geq = a >= b;
assign leq = a <= b;
assign eqx = a === b;
assign shr = a >> b; //0111111111000000
assign sshr = a >>> b;
assign shl = a << b;
assign sshl = a <<< b;
assign Land = a && b;
assign Lor = a || b;
assign Lnot = !a;
assign pos = $signed(uns);
assign Andr = &a;
assign Orr = |a;
assign Xorr = ^a;
assign Xnorr = ~^a;
always @*
if(!a) begin
Reduce_bool = a;
end else begin
Reduce_bool = b;
end
//always @(sel or c or a)
// begin
// case (sel)
// 3'b000: PMux = a;
// 3'b001: PMux = c[7:0];
// 3'b010: PMux = c[15:8];
// 3'b100: PMux = c[23:16];
// endcase
// end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_2_V
`define SKY130_FD_SC_MS__DLXBN_2_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxbn_2 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxbn_2 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_2_V
|
module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001;
parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 8e5 + 100; struct Bit { int bit[N], n; int sum(int i) { int s = 0; while (i > 0) { s += bit[i]; i -= i & -i; } return s; } void add(int i, int x) { while (i <= n) { bit[i] += x; i += i & -i; } } } bit; vector<int> que[N]; int t[N], ans[N]; struct AcTrie { int next[N][26], go[N][26], fail[N], pos[N >> 1]; int root, tot; vector<int> end[N]; int newnode() { for (int i = 0; i < 26; ++i) next[tot][i] = -1; end[tot++].clear(); return tot - 1; } void init() { tot = 0; pos[0] = root = newnode(); } int flx(char c) { return c - a ; } void add(int i, int now, char c) { if (next[now][flx(c)] == -1) next[now][flx(c)] = newnode(); now = next[now][flx(c)]; pos[i] = now; } int insert(char *buf) { int len = strlen(buf), now = root; for (int i = 0; i < len; ++i) { if (next[now][flx(buf[i])] == -1) next[now][flx(buf[i])] = newnode(); now = next[now][flx(buf[i])]; } return now; } void copy() { for (int i = 0; i < tot; ++i) memcpy(go[i], next[i], sizeof(next[i])); } int head[N], nex[N], to[N], tol; int l[N], r[N], dfs_clock; void build() { queue<int> Q; fail[root] = root; for (int i = 0; i < 26; ++i) { if (next[root][i] == -1) next[root][i] = root; else { fail[next[root][i]] = root; Q.push(next[root][i]); } } while (!Q.empty()) { int now = Q.front(); Q.pop(); for (int i = 0; i < 26; ++i) { if (next[now][i] == -1) next[now][i] = next[fail[now]][i]; else { fail[next[now][i]] = next[fail[now]][i]; Q.push(next[now][i]); } } } for (int i = 0; i < tot; ++i) head[i] = -1; dfs_clock = tol = 0; bit.n = tot; for (int i = 1; i < tot; ++i) { to[tol] = i; nex[tol] = head[fail[i]]; head[fail[i]] = tol++; } } void dfs1(int u) { l[u] = ++dfs_clock; for (int i = head[u]; ~i; i = nex[i]) dfs1(to[i]); r[u] = dfs_clock; } void dfs2(int u) { bit.add(l[u], 1); for (int i = 0, j; i < que[u].size(); ++i) { j = que[u][i]; ans[j] = bit.sum(r[t[j]]) - bit.sum(l[t[j]] - 1); } for (int i = 0; i < 26; ++i) if (~go[u][i]) dfs2(go[u][i]); bit.add(l[u], -1); } } ac; char read_char() { char ch = getchar(); while (ch > z || ch < a ) ch = getchar(); return ch; } int n, m, op, x; char s[N], c; int main() { scanf( %d , &n); ac.init(); for (int i = 1; i <= n; ++i) { scanf( %d , &op); op == 2 ? scanf( %d , &x) : x = 0; x = ac.pos[x]; c = read_char(); ac.add(i, x, c); } scanf( %d , &m); for (int i = 0; i < m; ++i) { scanf( %d %s , &x, s); x = ac.pos[x]; t[i] = ac.insert(s); que[x].push_back(i); } ac.copy(); ac.build(); ac.dfs1(ac.root); ac.dfs2(ac.root); for (int i = 0; i < m; ++i) printf( %d n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; int nn, n, b, q; vector<pair<int, int> > d; int main() { d.push_back(make_pair(0, 0)); scanf( %d%d%d , &n, &b, &q), nn = n; d.push_back(make_pair(b, n)); for (int i = 1; i <= q; i++) scanf( %d%d , &b, &n), d.push_back(make_pair(b, n)); sort(d.begin(), d.end()); for (int i = 1; i <= q; i++) if (d[i].second > d[i + 1].second || d[i + 1].second - d[i].second > d[i + 1].first - d[i].first) return printf( unfair n ), 0; for (int k = 0; k < 32; k++) { int res = 0; for (int i = 1; i <= q + 1; i++) { int cnt = 0; for (int j = d[i - 1].first + 1; j <= d[i].first; j++) cnt += bool((1 << (j % 5)) & k); res += min(cnt, d[i].second - d[i - 1].second); } if (res < nn / 5 * __builtin_popcount(k)) return printf( unfair n ), 0; } printf( fair n ); return 0; } |
/*---------------------------------------------------------------------------------------------------------------------
-- Author: Peter Hasza,
--
-- Create Date: 04/02/2017
-- Module Name: apb_reg_if
-- Project Name: AXI_SPI_IF
-- Description:
-- APB Slave module for register interface
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2017.apr.18 | hp3265 || Initial version
--
-----------------------------------------------------------------------------------------------------------------------*/
module apb_reg_if (
/* Generic Parameters */
parameter g_apb_addr_width = 8,
localparam c_data_width = 32;
localparam c_log2_data_width = clogb2(c_data_width)
) (
/* System Clock and Reset */
input pclk_i, // APB clock
input preset_n_i, // APB asynchronous reset
/* APB Bridge signals */
input [g_apb_addr_width-1:0] paddr_i,
input [2:0] pprot_i,
input psel_i,
input penable_i,
input pwrite_i,
input [c_data_width-1:0] pwdata_i,
input [c_log2_data_width-1:0] pstrb_i,
/* APB Slave interface signals */
output pready_o,
output [c_data_width-1:0] prdata_o,
output pslverr_o,
/* Internal register interface */
input [c_data_width-1:0] reg_control_i,
input [c_data_width-1:0] reg_addr_window_0_i,
input [c_data_width-1:0] reg_addr_window_1_i,
input [c_data_width-1:0] reg_addr_window_2_i;
input [c_data_width-1:0] reg_addr_window_3_i,
input [c_data_width-1:0] reg_status_i,
output [c_data_width-1:0] reg_data_o,
output reg_load_o,
output [2:0] reg_sel_o
);
/*=============================================================================================
-- APB Clock Domain
--=============================================================================================*/
parameter [1:0]
IDLE = 2'd0,
R_ENABLE = 2'd1,
W_ENABLE = 2'd2;
reg [2:0]
state, next_state;
always @ (posedge pclk_i, negedge preset_n_i)
begin
if (!preset_n_i)
state <= IDLE;
else
state <= next_state;
end
reg pready_y;
reg pslverr_y;
reg [g_apb_data_width-1:0] prdata_y;
reg reg_sel_y;
reg [c_data_width-1:0] reg_data_y;
reg reg_load_y;
always @ (posedge pclk_i)
begin
case (reg_sel_y)
3'd0 : prdata_y <= reg_control_i;
3'd1 : prdata_y <= reg_addr_window_0_i;
3'd2 : prdata_y <= reg_addr_window_1_i;
3'd3 : prdata_y <= reg_addr_window_2_i;
3'd4 : prdata_y <= reg_addr_window_2_i;
3'd5 : prdata_y <= reg_status_i;
default : prdata_y <= reg_status_i;
endcase;
end
genvar i;
generate
for (i = 0; i < c_log2_data_width ; i = i + 1) begin:
always @(posedge pclk_i) begin
reg_data_y[(i*8+7):(i*8)] <= (pstrb_i[i] == 1) ? pwdata_i[(i*8+7):(i*8)] : 8'd0;
end
end
endgenerate
always @ (posedge pclk_i, negedge preset_n_i)
begin
case (state)
IDLE :
begin
pready_y <= 0;
pslverr_y <= 0;
reg_load_y <= 0;
end
R_ENABLE :
begin
pready_y <= 1;
reg_sel_y <= paddr_i[3:0];
if (paddr_i > 3'd5)
pslverr_y <= 1;
else
pslverr_y <= 0;
end
W_ENABLE :
begin
pready_y <= 1;
reg_sel_y <= paddr_i[3:0];
reg_load_y <= 1;
if (paddr_i > 3'd4) // Status register is HW-Modified
pslverr_y <= 1;
else
pslverr_y <= 0;
end
default : // Should never go into default state
begin
pready_y <= 0;
pslverr_y <= 0;
reg_load_y <= 0;
end
endcase;
end
always @ (posedge pclk_i, negedge preset_n_i)
begin
if (!preset_n_i)
next_state <= IDLE;
else
begin
if (psel_i and (!penable_i) and pwrite_i)
next_state <= #1 W_ENABLE;
else if (psel_i and (!penable_i) and (!pwrite_i))
next_state <= #1 R_ENABLE;
else
next_state <= #1 IDLE;
end
end
pready_o <= pready_y;
prdata_o <= prdata_y;
pslverr_o <= pslverr_y;
reg_data_o <= reg_data_y;
reg_load_o <= reg_load_y;
reg_sel_o <= reg_sel_y;
endmodule; |
#include <bits/stdc++.h> using namespace std; long long a[200010]; long long l[200010]; long long r[200010]; int main() { ios_base::sync_with_stdio(0); long long n, h; cin >> n >> h; vector<long long> rast2(n + 1, 0); for (int i = 1; i <= n; i++) { cin >> l[i] >> r[i]; rast2[i] = r[i] - l[i]; } for (int i = 1; i <= n; i++) { rast2[i] += rast2[i - 1]; } vector<long long> rast(n + 1, 0); for (int i = 1; i < n; i++) { rast[i] = l[i + 1] - r[i]; } rast[n] = 2e9; for (int i = 1; i <= n; i++) { rast[i] += rast[i - 1]; } long long ans = 0; for (int i = 1; i <= n; i++) { long long r = lower_bound(rast.begin(), rast.end(), h + rast[i - 1]) - (rast.begin()); if (r <= n) ans = max(ans, (rast2[r] - rast2[i - 1]) + h); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; template <class T> const T& max(const T& a, const T& b, const T& c) { return max(a, max(b, c)); } template <class T> const T& min(const T& a, const T& b, const T& c) { return min(a, min(b, c)); } void sc(int& a) { scanf( %d , &a); } void sc(long long& a) { scanf( %lld , &a); } void sc(int& a, int& b) { sc(a); sc(b); } void sc(long long& a, long long& b) { sc(a); sc(b); } void sc(int& a, int& b, int& c) { sc(a, b); sc(c); } void sc(long long& a, long long& b, long long& c) { sc(a, b); sc(c); } void prl(int a) { printf( %d n , a); } void prl(long long a) { printf( %lld n , a); } void prl() { printf( n ); } void prs(int a) { printf( %d , a); } void prs(long long a) { printf( %lld , a); } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long poww(long long a, long long b) { if (b == 0) return 1; long long tmp = poww(a, b / 2); return (b & 1 ? a * tmp * tmp : tmp * tmp); } long long sumOfDigs(string s) { long long sum = 0; for (int i = 0; i < s.length(); i++) sum += s[i] - 0 ; return sum; } long long sumOfDigs(long long n) { return (n < 10 ? n : n % 10 + sumOfDigs(n / 10)); } string itos(long long i) { string s = ; while (i) { s += char(i % 10 + 0 ); i /= 10; } reverse(s.begin(), s.end()); return s; } long long stoi(string& s) { long long tot = 0; for (int i = (int)s.length() - 1, j = 1; i >= 0; i--, j *= 10) { tot += j * (s[i] + 0 ); } return tot; } int months[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; using namespace std; void tt() { freopen( test.txt , r , stdin); } long long mod = 1000000000000000003; long long modpower(long long x, long long y, long long p) { x %= mod; if (!y) return 1; long long res = 1; if (y & 1) { res *= x; res %= p; } long long z = modpower(x, y / 2, p); z %= p; z *= z; z %= mod; res *= z; res %= p; return res; } double ans = 1e60; long long a = -1, b = -1; int main() { long long t1, t2, x1, x2, t0; cin >> t1 >> t2 >> x1 >> x2 >> t0; if (t1 == t0 && t2 == t0) { return cout << x1 << << x2 << endl, 0; } else if (t1 == t0) { return cout << x1 << << 0 << endl, 0; } for (long long y2 = 1; y2 <= x2; y2++) { long long y1 = (t2 * y2 - t0 * y2) / (t0 - t1); if (y1 > x1) { y1 = x1; } double t = (long double)(1.0 * y1 * t1 + 1.0 * y2 * t2) / (y1 + y2); if (t < t0) continue; if (t < ans || t == ans && a + b < y1 + y2) { ans = t; a = y1; b = y2; } } cout << a << << b << endl; return 0; } |
module OK_WB_Bridge(
input wire [30:0] ok1,
output wire [16:0] ok2,
input wire ti_clk,
input wire clk_i,
input wire rst_i,
input wire stb_i,
input wire [7:0] adr_i,
input wire we_i,
input wire [31:0] dat_i,
output wire [31:0] dat_o
);
// Wire declarations
wire OKfifowrite;
wire OKfiforead;
wire [15:0] OKdatain;
wire [15:0] OKdataout;
wire [15:0] OK_rec_dat;
wire n_fifo_em;
wire fifoem;
wire fifofull1;
wire fifofull2;
wire [17*2-1:0] ok2x;
okWireOR # (.N(2)) wireOR (ok2, ok2x);
//Circuit behavior
assign dat_o = {15'b0, ~n_fifo_em, OK_rec_dat};
FIFO_16bit_dual_port fifo_in (
.rst(rst_i), // input rst
.wr_clk(ti_clk), // input wr_clk
.rd_clk(clk_i), // input rd_clk
.din(OKdatain), // input [15 : 0] din
.wr_en(OKfifowrite), // input wr_en
.rd_en(stb_i & ~we_i), // input rd_en
.dout(OK_rec_dat), // output [15 : 0] dout
.full(fifofull1), // output full
.empty(n_fifo_em) // output empty
);
FIFO_16bit_dual_port fifo_out (
.rst(rst_i), // input rst
.wr_clk(clk_i), // input wr_clk
.rd_clk(ti_clk), // input rd_clk
.din(dat_i), // input [15 : 0] din
.wr_en(stb_i & we_i), // input wr_en
.rd_en(OKfiforead), // input rd_en
.dout(OKdataout), // output [15 : 0] dout
.full(fifofull2), // output full
.empty(fifoem) // output empty
);
//FrontPanel endpoint instantiations
okBTPipeIn pipe80(
.ok1(ok1),
.ok2(ok2x[0*17 +: 17]),
.ep_addr(8'h80),
.ep_write(OKfifowrite),
.ep_dataout(OKdatain),
.ep_ready(~fifofull1)
);
okBTPipeOut pipeA0(
.ok1(ok1),
.ok2(ok2x[1*17 +: 17]),
.ep_addr(8'hA0),
.ep_read(OKfiforead),
.ep_datain(OKdataout),
.ep_ready(~fifoem)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { return !b ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { return a * (b / gcd(a, b)); } template <typename T> T sqr(T a) { return a * a; } template <typename T> T cube(T a) { return a * a * a; } template <typename T> inline void smin(T &a, T b) { a = a < b ? a : b; } template <typename T> inline void smax(T &a, T b) { a = a > b ? a : b; } int in() { int n; scanf( %d , &n); return n; } long long Lin() { long long n; scanf( %lld , &n); return n; } double Din() { double n; scanf( %lf , &n); return n; } const long long inf = (long long)1e17; const long long mod = (long long)1e9 + 7; const int N = 1e5 + 5; struct CHT_DEC_MIN { vector<long long> m, b; bool bad(int f1, int f2, int f3) { return 1.0 * (b[f2] - b[f1]) * (m[f1] - m[f3]) >= 1.0 * (b[f3] - b[f1]) * (m[f1] - m[f2]); } void add(long long M, long long B) { m.push_back(M), b.push_back(B); int sz = (int)m.size(); while (sz >= 3 && bad(sz - 3, sz - 2, sz - 1)) { m.erase(m.end() - 2); b.erase(b.end() - 2); sz--; } } long long f(int idx, long long X) { return m[idx] * X + b[idx]; } long long query(long long X) { int low = 0, high = (int)m.size() - 1; while (high - low > 5) { int mid1 = (low + low + high) / 3; int mid2 = (low + high + high) / 3; if (f(mid1, X) >= f(mid2, X)) { low = mid1 + 1; } else { high = mid2 - 1; } } long long res = f(low, X); for (int i = low + 1; i <= high; i++) { res = min(res, f(i, X)); } return res; } }; long long a[N], s[N]; CHT_DEC_MIN tree[4 * N]; void update(int pos, int left, int right, int x, long long M, long long B) { tree[pos].add(M, B); if (left == right) return; int mid = (left + right) >> 1; if (x <= mid) update(pos * 2, left, mid, x, M, B); else update(pos * 2 + 1, mid + 1, right, x, M, B); } long long query(int pos, int left, int right, int x, int y, long long X) { if (left > y || right < x) return (long long)1e17; if (left >= x && right <= y) { return tree[pos].query(X); } int mid = (left + right) >> 1; long long m = query(pos * 2, left, mid, x, y, X); long long n = query(pos * 2 + 1, mid + 1, right, x, y, X); return min(m, n); } int solve() { int n = in(); vector<pair<long long, int> > tem; for (int i = 1; i <= n; i++) { a[i] = Lin(); s[i] += s[i - 1] + a[i]; tem.push_back({a[i], i}); } sort(tem.begin(), tem.end()); for (int i = 0; i < n; i++) { int idx = tem[i].second; long long M = -a[idx], B = a[idx] * idx - s[idx]; update(1, 1, n, idx, M, B); } int q = in(); while (q--) { int x = in(), y = in(); x = y - x + 1; printf( %lld n , s[y] + query(1, 1, n, x, y, (long long)x - 1)); } return 0; } int main() { int test = 1, tc = 0; while (test--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int maxPrime[10000005]; long long cnt_prime[10000005]; int primes[10000005]; int cnt_p; void init() { for (int i = 2; i < 10000005; i += 2) maxPrime[i] = 2; for (int i = 3; i * i < 10000005; i += 2) { if (maxPrime[i] == i || maxPrime[i] == 0) { maxPrime[i] = i; for (int j = i * 2; j < 10000005; j += i) { maxPrime[j] = i; } } } for (int i = 2; i < 10000005; i++) { if (maxPrime[i] == 0) maxPrime[i] = i; if (maxPrime[i] == i) { primes[cnt_p++] = i; } } } bool good(long long x) { for (int i = 0; i < cnt_p; i++) { long long temp = x; long long res = 0; while (temp) { temp /= primes[i]; res += temp; } if (res < cnt_prime[primes[i]]) return false; } return true; } int main() { long long sum = 0; int n; int maxx = 0; init(); scanf( %d , &n); for (int i = 0; i < n; i++) { int a; scanf( %d , &a); maxx = max(maxx, a); sum += a; cnt_prime[a]++; } for (int i = maxx; i >= 2; i--) { cnt_prime[i] += cnt_prime[i + 1]; } for (int i = maxx; i >= 2; i--) { cnt_prime[i / maxPrime[i]] += cnt_prime[i]; if (maxPrime[i] != i) { cnt_prime[maxPrime[i]] += cnt_prime[i]; } } long long left = maxx, right = sum; while (left <= right) { long long mid = (left + right) / 2; if (good(mid)) { right = mid - 1; } else { left = mid + 1; } } cout << left << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433832795l; template <typename T> inline auto sqr(T x) -> decltype(x * x) { return x * x; } template <typename T1, typename T2> inline bool umx(T1& a, T2 b) { if (a < b) { a = b; return 1; } return 0; } template <typename T1, typename T2> inline bool umn(T1& a, T2 b) { if (b < a) { a = b; return 1; } return 0; } struct Input { int n, k; vector<vector<int> > g; vector<int> h; vector<int> s; bool read() { if (!(cin >> n)) { return 0; } h.resize(n); for (int i = int(0); i < int(n); ++i) { cin >> h[i]; } g.assign(n, vector<int>()); for (int i = int(0); i < int(n - 1); ++i) { int u, v; cin >> u >> v; --u, --v; g[u].push_back(v); g[v].push_back(u); } cin >> k; s.resize(k); for (int i = int(0); i < int(k); ++i) { cin >> s[i]; } return 1; } void init(const Input& input) { *this = input; } }; struct Data : Input { int ans; void write() { cout << ans << n ; } virtual void solve() {} virtual void clear() { *this = Data(); } }; struct Solution : Data { vector<int> sc_best; vector<int> fs_best; vector<int> all_vals; vector<int> heights; vector<int> backw_pos; vector<int> forw_pos; vector<int> fail_pos; vector<int> fail_vers; void dfs(int x, int par, int first, int second) { if (first == -1 || h[x] <= h[first]) { second = first; first = x; } else if (second == -1 || h[x] <= h[second]) { second = x; } fs_best[x] = first; sc_best[x] = second; for (auto to : g[x]) { if (to != par) { dfs(to, x, first, second); } } } int mfit() { int ans = -1; int ln = 0; for (int i = int(0); i < int(((int)(all_vals).size())); ++i) { int cur = 0; vector<int> new_h; int rn = ln; while (rn < n && fs_best[heights[rn]] == all_vals[i]) ++rn; int fail_from = 0, fail_to = fail_pos[i]; int lp = forw_pos[i], rp = backw_pos[i]; bool ok = true; for (int j = int(ln); j < int(rn); ++j) { int a = h[all_vals[i]]; int b = 2000000000; if (sc_best[heights[j]] != -1) { b = h[sc_best[heights[j]]]; } if (fail_from != fail_to) { if (b >= fail_vers[fail_from]) { umx(cur, fail_vers[fail_from] - a); ++fail_from; } else { ok = false; } } else if (lp != rp) { if (b >= s[lp]) { umx(cur, s[lp] - a); ++lp; } else { ok = false; } } } if (ok && fail_from == fail_to && lp == rp && (ans == -1 || ans > cur)) { ans = cur; } ln = rn; } return ans; } void solve() { sort((s).begin(), (s).end()); reverse((s).begin(), (s).end()); sc_best.assign(n, -1); fs_best.assign(n, -1); dfs(0, -1, -1, -1); heights.resize(n); for (int i = int(0); i < int(n); ++i) { heights[i] = i; } sort((heights).begin(), (heights).end(), [&](int a, int b) { return (h[fs_best[a]] > h[fs_best[b]] || (h[fs_best[a]] == h[fs_best[b]] && fs_best[a] < fs_best[b]) || (fs_best[a] == fs_best[b] && (sc_best[b] != -1 && (sc_best[a] == -1 || h[sc_best[a]] > h[sc_best[b]])))); }); all_vals.clear(); for (auto x : heights) { if (all_vals.empty() || all_vals.back() != fs_best[x]) { all_vals.push_back(fs_best[x]); } } int lp = 0, ln = 0; int cnt = ((int)(all_vals).size()); forw_pos.assign(cnt, 0); fail_pos.assign(cnt, 0); for (int i = int(0); i < int(cnt - 1); ++i) { while (ln < n && fs_best[heights[ln]] == all_vals[i]) { int cur_h = h[all_vals[i]]; while (lp < k && cur_h < s[lp]) { fail_vers.push_back(s[lp]); ++lp; } if (lp < k) { ++lp; } ++ln; } forw_pos[i + 1] = lp; fail_pos[i + 1] = ((int)(fail_vers).size()); }; backw_pos.assign(cnt, k); int rp = k - 1, rn = n - 1; for (int i = int(cnt) - 1; i >= int(1); --i) { while (rn >= 0 && fs_best[heights[rn]] == all_vals[i]) { int cur_h = h[all_vals[i]]; if (rp >= 0) { if (cur_h >= s[rp]) { --rp; } } --rn; } backw_pos[i - 1] = rp + 1; } ans = mfit(); } void clear() { *this = Solution(); } }; Solution sol; int main() { cout.setf(ios::showpoint | ios::fixed); cout.precision(20); ios_base::sync_with_stdio(false); sol.read(); sol.solve(); sol.write(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_BLACKBOX_V
`define SKY130_FD_SC_LS__AND4BB_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_BLACKBOX_V
|
//==================================================================================================
// Filename : uart_tx.v
// Created On : 2015-01-08 19:21:16
// Last Modified : 2015-05-24 21:04:24
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Transmitter module for UART
// Based on the Tx module from XUM project
// Author: Grant Ayers ()
//==================================================================================================
module uart_tx(
input clk,
input rst,
input uart_tick, // module "tick". More like an enable.
input [7:0] TxD_data, // Input data
input TxD_start, // Enable transmission
output ready, // Tx buffer is empty, and ready for a new transmission
output reg TxD // Tx output pin
);
//--------------------------------------------------------------------------
// "local variables": the FMS states.
//--------------------------------------------------------------------------
localparam [3:0] IDLE=0; // FSM states
localparam [3:0] START=1; // FSM states
localparam [3:0] BIT_0=2; // FSM states
localparam [3:0] BIT_1=3; // FSM states
localparam [3:0] BIT_2=4; // FSM states
localparam [3:0] BIT_3=5; // FSM states
localparam [3:0] BIT_4=6; // FSM states
localparam [3:0] BIT_5=7; // FSM states
localparam [3:0] BIT_6=8; // FSM states
localparam [3:0] BIT_7=9; // FSM states
localparam [3:0] STOP=10; // FSM states
//--------------------------------------------------------------------------
// registers
//--------------------------------------------------------------------------
reg [3:0] tx_state = IDLE;
reg [7:0] TxD_data_r = 8'h00; // Registered input data so it doesn't need to be held
//--------------------------------------------------------------------------
// assignment output signals
//--------------------------------------------------------------------------
assign ready = (tx_state == IDLE) || (tx_state == STOP);
always @(posedge clk) begin
TxD_data_r <= (ready & TxD_start) ? TxD_data : TxD_data_r;
end
//--------------------------------------------------------------------------
// Get the new state
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst)
tx_state <= IDLE;
else begin
case (tx_state)
IDLE: if (TxD_start) tx_state <= START;
START: if (uart_tick) tx_state <= BIT_0;
BIT_0: if (uart_tick) tx_state <= BIT_1;
BIT_1: if (uart_tick) tx_state <= BIT_2;
BIT_2: if (uart_tick) tx_state <= BIT_3;
BIT_3: if (uart_tick) tx_state <= BIT_4;
BIT_4: if (uart_tick) tx_state <= BIT_5;
BIT_5: if (uart_tick) tx_state <= BIT_6;
BIT_6: if (uart_tick) tx_state <= BIT_7;
BIT_7: if (uart_tick) tx_state <= STOP;
STOP: if (uart_tick) tx_state <= (TxD_start) ? START : IDLE;
default: tx_state <= 4'bxxxx;
endcase
end
end
//--------------------------------------------------------------------------
// Set Tx pin
//--------------------------------------------------------------------------
always @(tx_state, TxD_data_r) begin
case (tx_state)
IDLE: TxD <= 1;
START: TxD <= 0;
BIT_0: TxD <= TxD_data_r[0];
BIT_1: TxD <= TxD_data_r[1];
BIT_2: TxD <= TxD_data_r[2];
BIT_3: TxD <= TxD_data_r[3];
BIT_4: TxD <= TxD_data_r[4];
BIT_5: TxD <= TxD_data_r[5];
BIT_6: TxD <= TxD_data_r[6];
BIT_7: TxD <= TxD_data_r[7];
STOP: TxD <= 1;
default: TxD <= 1'bx;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUFLP_FUNCTIONAL_PP_V
/**
* buflp: Buffer, Low Power.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__buflp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_FUNCTIONAL_PP_V |
`timescale 1 ns / 1 ps
//Input clock 125 MHz
module dac_control
(
input clk,
input enable_update,
input enable,
input [7:0]dbA,
input [7:0]dbB,
input [7:0]dbC,
input [7:0]dbD,
output reg [7:0]db,
output wire clr_n,
output wire pd_n,
output reg cs_n,
output reg wr_n,
output reg [1:0]A,
output reg ldac_n
);
reg [7:0] clk_div;
reg clk_int;
always @(posedge clk) begin
clk_div <= clk_div + 1;
clk_int <= (clk_div == 8'HFF);
/* if (clk_div == 8'HFF) */
/* clk_int <= 1; */
/* else */
/* clk_int <= 0; */
end
assign clr_n = enable;
assign pd_n = 1;
reg [7:0]dbA_prev;
reg [7:0]dbB_prev;
reg [7:0]dbC_prev;
reg [7:0]dbD_prev;
reg update_trigger;
always @(posedge clk_int && enable_update) begin
if ((dbA != dbA_prev) || (dbB != dbB_prev) || (dbC != dbC_prev) || (dbD != dbD_prev))
update_trigger <= 1;
else
update_trigger <= 0;
dbA_prev <= dbA;
dbB_prev <= dbB;
dbC_prev <= dbC;
dbD_prev <= dbD;
end
reg [3:0] cntr;
always @(posedge clk_int) begin
if ((update_trigger == 1) || (cntr != 0)) begin
cntr <= (cntr + 1) % 10;
case (cntr)
0 : begin
A <= 2'b00;
db <= dbA;
end
1 :
wr_n <= 1;
2 : begin
A <= 2'b01;
db <= dbB;
wr_n <= 0;
end
3 :
wr_n <= 1;
4 : begin
A <= 2'b10;
db <= dbC;
wr_n <= 0;
end
5 :
wr_n <= 1;
6 : begin
A <= 2'b11;
db <= dbD;
wr_n <= 0;
end
7 :
wr_n <= 1;
8 :
wr_n <= 0;
9 :
ldac_n <= 1;
10 :
ldac_n <= 0;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> int main() { int cnt = 0, f[4], i, j, x[200], y[200], n; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d %d , &x[i], &y[i]); } for (i = 0; i < n; i++) { f[1] = 0; f[2] = 0; f[3] = 0; f[0] = 0; for (j = 0; j < n; j++) { if (j != i) { if (x[i] == x[j] && y[i] < y[j]) f[0] = 1; if (x[i] == x[j] && y[i] > y[j]) f[1] = 1; } } for (j = 0; j < n; j++) { if (j != i) { if (y[i] == y[j] && x[i] < x[j]) f[2] = 1; if (y[i] == y[j] && x[i] > x[j]) f[3] = 1; } } if (f[0] == 1 && f[1] == 1 && f[2] == 1 && f[3] == 1) { cnt++; } } printf( %d , cnt); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; for (int i = 0; i < t; i++) { long long n, k; cin >> n >> k; if (n < k * k) { cout << NO << n ; } else if (n % 2 != k % 2) { cout << NO << n ; } else { cout << YES << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int num[500005]; int maps[500005]; int to[500005]; int main() { ios::sync_with_stdio(0); int n, m; int l, r; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &num[i]); to[num[i]] = i; } for (int i = 1; i <= m; i++) { scanf( %d%d , &l, &r); if (to[r] < to[l]) { int tmp = r; r = l; l = tmp; } maps[to[r]] = max(to[l], maps[to[r]]); } l = 1; long long ans = 0; for (int i = 1; i <= n; i++) { if (maps[i] >= l) l = maps[i] + 1; ans += i - l + 1; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; long long int dx[] = {0, 0, 1, -1}; long long int dy[] = {1, -1, 0, 0}; long long int m = 0, n, res = 0, k; string s2, ch = , s, t, s1 = ; vector<pair<string, long long int> > vm; vector<pair<pair<long long int, long long int>, long long int> > vvv; vector<pair<long long int, long long int> > vv, vv2; vector<long long int> v[200005], v2, v1; long long int a[500005], vis[500005], dp[500005]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long int i = 0, x = 0, z = 0, y = 0, j = 0, q, mx = 0, idx = 0, ok = 0, l = 0, r = 0, negatif = 0, positif = 0, l1, r1, p, t, d; set<pair<long long int, long long int> >::iterator itp; cin >> n >> k >> d; for (i = 1; i <= n; i++) { cin >> a[i]; dp[i] = 0; } sort(a + 1, a + 1 + n); dp[0] = 1; dp[1] = -1; for (i = 1; i <= n; i++) { if (!dp[i - 1]) continue; dp[i] += dp[i - 1]; x = a[i] + d; l = i + k - 1; r = upper_bound(a + i, a + 1 + n, x) - a - 1; if (r >= l) { dp[l]++; dp[r + 1]--; } } if (dp[n]) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; scanf( %lld , &n); long long a, b, c; scanf( %lld , &a); scanf( %lld , &b); scanf( %lld , &c); if (a <= (b - c)) { printf( %lld n , n / a); } else { n -= b; long long x = 0; if (n >= 0) { x = n / (b - c); n %= (b - c); } n += b; if (n >= b) { n = n - (b - c); x++; } x += max(n / a, n / b); printf( %lld n , x); } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : tlm_rx_data_snk_pwr_mgmt.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/*****************************************************************************
* Description : Rx Data Sink power management packet interpretation
*
* Hierarchical :
*
* Functional :
* Removes power management packets from the stream and signals
* sideband to CMM
*
****************************************************************************/
`timescale 1ns/1ps
`ifndef TCQ
`define TCQ 1
`endif
`ifndef AS
module tlm_rx_data_snk_pwr_mgmt
(
input clk_i,
input reset_i,
// Power management signals for CMM
output reg pm_as_nak_l1_o, // Pkt detected, implies src_rdy
output reg pm_turn_off_o, // Pkt detected, implies src_rdy
output reg pm_set_slot_pwr_o, // Pkt detected, implies src_rdy
output reg [9:0] pm_set_slot_pwr_data_o, // value of field
output reg pm_msg_detect_o, // grabbed a pm signal
input ismsg_i, // Packet data type
input [7:0] msgcode_i, // message code
input [9:0] pwr_data_i, // set slot value
input eval_pwr_mgmt_i, // grab the sideband fields
input eval_pwr_mgmt_data_i, // get the data, if it exists
input act_pwr_mgmt_i // transmit the sideband fields
);
//-----------------------------------------------------------------------------
// PCI Express constants
//-----------------------------------------------------------------------------
// Message code
localparam PM_ACTIVE_STATE_NAK = 8'b0001_0100;
localparam PME_TURN_OFF = 8'b0001_1001;
localparam SET_SLOT_POWER_LIMIT = 8'b0101_0000;
reg cur_pm_as_nak_l1;
reg cur_pm_turn_off;
reg cur_pm_set_slot_pwr;
reg eval_pwr_mgmt_q1;
reg eval_pwr_mgmt_data_q1;
reg act_pwr_mgmt_q1;
reg [9:0] pm_set_slot_pwr_data_d1;
// grab the fields at the beginning of the packet when known
//----------------------------------------------------------
always @(posedge clk_i) begin
if (reset_i) begin
cur_pm_as_nak_l1 <= #`TCQ 0;
cur_pm_turn_off <= #`TCQ 0;
cur_pm_set_slot_pwr <= #`TCQ 0;
end else if (eval_pwr_mgmt_i) begin
// ismsg is ANY message - malformed will are another modules
// problem
if (ismsg_i) begin
cur_pm_as_nak_l1 <= #`TCQ (msgcode_i == PM_ACTIVE_STATE_NAK);
cur_pm_turn_off <= #`TCQ (msgcode_i == PME_TURN_OFF);
cur_pm_set_slot_pwr <= #`TCQ (msgcode_i == SET_SLOT_POWER_LIMIT);
// if we aren't a mesg, these can't be true
end else begin
cur_pm_as_nak_l1 <= #`TCQ 0;
cur_pm_turn_off <= #`TCQ 0;
cur_pm_set_slot_pwr <= #`TCQ 0;
end
end
end
// We need to know which packets we're dropping because we're
// already signalling them sideband
// pipelined due to timing
//------------------------------------------------------
always @(posedge clk_i) begin
if (reset_i) begin
pm_msg_detect_o <= #`TCQ 0;
end else if (eval_pwr_mgmt_q1) begin
pm_msg_detect_o <= #`TCQ cur_pm_as_nak_l1 ||
cur_pm_turn_off ||
cur_pm_set_slot_pwr;
end
end
// Data comes two cycles after the header fields, so we can't
// share the input latching fields
// Furthermore, it will not go away until after eof_q2, so we
// can cheat on registers
// Lastly, it does not imply activation, so we can always grab
// the field
//-----------------------------------------------------------
always @(posedge clk_i) begin
if (eval_pwr_mgmt_data_i) begin
pm_set_slot_pwr_data_d1 <= #`TCQ pwr_data_i;
end
if (eval_pwr_mgmt_data_q1) begin
pm_set_slot_pwr_data_o <= #`TCQ pm_set_slot_pwr_data_d1;
end
end
// transmit sidebands when we know they are good for
// one cycle only
always @(posedge clk_i) begin
if (reset_i) begin
pm_as_nak_l1_o <= #`TCQ 0;
pm_turn_off_o <= #`TCQ 0;
pm_set_slot_pwr_o <= #`TCQ 0;
// at this point, we know the packet is valid
end else if (act_pwr_mgmt_i) begin
pm_as_nak_l1_o <= #`TCQ cur_pm_as_nak_l1;
pm_turn_off_o <= #`TCQ cur_pm_turn_off;
pm_set_slot_pwr_o <= #`TCQ cur_pm_set_slot_pwr;
// implies src_rdy, return to zero
end else if (act_pwr_mgmt_q1) begin
pm_as_nak_l1_o <= #`TCQ 0;
pm_turn_off_o <= #`TCQ 0;
pm_set_slot_pwr_o <= #`TCQ 0;
end
end
// Also need delayed version
always @(posedge clk_i) begin
if (reset_i) begin
eval_pwr_mgmt_q1 <= #`TCQ 0;
eval_pwr_mgmt_data_q1 <= #`TCQ 0;
act_pwr_mgmt_q1 <= #`TCQ 0;
end else begin
eval_pwr_mgmt_q1 <= #`TCQ eval_pwr_mgmt_i;
eval_pwr_mgmt_data_q1 <= #`TCQ eval_pwr_mgmt_data_i;
act_pwr_mgmt_q1 <= #`TCQ act_pwr_mgmt_i;
end
end
endmodule
`endif
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ram_loader
#(parameter AWIDTH=16, RAM_SIZE=16384)
(
// Wishbone I/F and clock domain
input wb_clk,
input dsp_clk,
input ram_loader_rst,
output wire [31:0] wb_dat,
output wire [AWIDTH-1:0] wb_adr,
output wb_stb,
output reg [3:0] wb_sel,
output wb_we,
output reg ram_loader_done,
// CPLD signals and clock domain
input cpld_clk,
input cpld_din,
output reg cpld_start,
output reg cpld_mode,
output reg cpld_done,
input cpld_detached
);
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam RESET = 7;
localparam WB_IDLE = 0;
localparam WB_WRITE = 1;
reg [AWIDTH+2:0] count; // 3 LSB's count bits in, the MSB's generate the Wishbone address
reg [6:0] shift_reg;
reg [7:0] data_reg;
reg sampled_clk;
reg sampled_clk_meta;
reg sampled_din;
reg inc_count;
reg load_data_reg;
reg shift;
reg wb_state, wb_next_state;
reg [2:0] state, next_state;
//
// CPLD clock doesn't free run and is approximately 12.5MHz.
// Use 50MHz Wishbone clock to sample it as a signal and avoid having
// an extra clock domain for no reason.
//
always @(posedge dsp_clk or posedge ram_loader_rst)
if (ram_loader_rst)
begin
sampled_clk_meta <= 1'b0;
sampled_clk <= 1'b0;
sampled_din <= 1'b0;
count <= 'h7FFF8; // Initialize so that address will be 0 when first byte fully received.
data_reg <= 0;
shift_reg <= 0;
end
else
begin
sampled_clk_meta <= cpld_clk;
sampled_clk <= sampled_clk_meta;
sampled_din <= cpld_din;
if (inc_count)
count <= count + 1'b1;
if (load_data_reg)
data_reg <= {shift_reg,sampled_din};
if (shift)
shift_reg <= {shift_reg[5:0],sampled_din};
end // else: !if(ram_loader_rst)
always @(posedge dsp_clk or posedge ram_loader_rst)
if (ram_loader_rst)
state <= RESET;
else
state <= next_state;
always @*
begin
// Defaults
next_state = state;
cpld_start = 1'b0;
shift = 1'b0;
inc_count = 0;
load_data_reg = 1'b0;
ram_loader_done = 1'b0;
cpld_mode = 1'b0;
cpld_done = 1'b1;
case (state) //synthesis parallel_case full_case
// After reset wait until CPLD indicates its detached.
RESET: begin
if (cpld_detached)
next_state = S0;
else
next_state = RESET;
end
// Assert cpld_start to signal the CPLD its to start sending serial clock and data.
// Assume cpld_clk is low as we transition into search for first rising edge
S0: begin
cpld_start = 1'b1;
cpld_done = 1'b0;
if (~cpld_detached)
next_state = S2;
else
next_state = S0;
end
//
S1: begin
cpld_start = 1'b1;
cpld_done = 1'b0;
if (sampled_clk)
begin
// Found rising edge on cpld_clk.
if (count[2:0] == 3'b111)
// Its the last bit of a byte, send it out to the Wishbone bus.
begin
load_data_reg = 1'b1;
inc_count = 1'b1;
end
else
// Shift databit into LSB of shift register and increment count
begin
shift = 1'b1;
inc_count = 1'b1;
end // else: !if(count[2:0] == 3'b111)
next_state = S2;
end // if (sampled_clk)
else
next_state = S1;
end // case: S1
//
S2: begin
cpld_start = 1'b1;
cpld_done = 1'b0;
if (~sampled_clk)
// Found negative edge of clock
if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant
// All firmware now downloaded
next_state = S3;
else
next_state = S1;
else
next_state = S2;
end // case: S2
// Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done
// and that mode is now SPI mode.
S3: begin
if (sampled_clk)
begin
cpld_mode = 1'b1;
cpld_done = 1'b1;
next_state = S4;
end
else
next_state = S3;
end
// Search for negedge of cpld_clk whilst keeping done sequence asserted.
// Keep done assserted
S4: begin
cpld_mode = 1'b1;
cpld_done = 1'b1;
if (~sampled_clk)
next_state = S5;
else
next_state = S4;
end
// Search for posedge of cpld_clk whilst keeping done sequence asserted.
S5: begin
cpld_mode = 1'b1;
cpld_done = 1'b1;
if (sampled_clk)
next_state = S6;
else
next_state = S5;
end
// Stay in this state until reset/power down
S6: begin
ram_loader_done = 1'b1;
cpld_done = 1'b1;
cpld_mode = 1'b1;
next_state = S6;
end
endcase // case(state)
end
always @(posedge dsp_clk or posedge ram_loader_rst)
if (ram_loader_rst)
wb_state <= WB_IDLE;
else
wb_state <= wb_next_state;
reg do_write;
wire empty, full;
always @*
begin
wb_next_state = wb_state;
do_write = 1'b0;
case (wb_state) //synthesis full_case parallel_case
//
WB_IDLE: begin
if (load_data_reg)
// Data reg will load ready to write wishbone @ next clock edge
wb_next_state = WB_WRITE;
else
wb_next_state = WB_IDLE;
end
// Drive address and data onto wishbone.
WB_WRITE: begin
do_write = 1'b1;
if (~full)
wb_next_state = WB_IDLE;
else
wb_next_state = WB_WRITE;
end
endcase // case(wb_state)
end // always @ *
wire [1:0] count_out;
wire [7:0] data_out;
fifo_xlnx_16x40_2clk crossclk
(.rst(ram_loader_rst),
.wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full),
.rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty));
assign wb_dat = {4{data_out}};
always @*
case(count_out[1:0]) //synthesis parallel_case full_case
2'b00 : wb_sel = 4'b1000;
2'b01 : wb_sel = 4'b0100;
2'b10 : wb_sel = 4'b0010;
2'b11 : wb_sel = 4'b0001;
endcase
assign wb_we = ~empty;
assign wb_stb = ~empty;
endmodule // ram_loader
|
#include <bits/stdc++.h> using namespace std; void solve(string s) { int n = s.size(); s = # + s; vector<int> pi(n + 1); pi[0] = 0, pi[1] = 0; for (int i = 2; i <= n; i++) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j + 1]) j = pi[j]; if (s[i] == s[j + 1]) j++; pi[i] = j; } int dp[n + 1]; for (int i = 0; i <= n; i++) dp[i] = 1; for (int i = n; i >= 1; i--) dp[pi[i]] += dp[i]; vector<pair<int, int> > res; res.push_back(pair<int, int>(n, 1)); int j = pi[n]; if (j == 0) { cout << 1 << endl; cout << n << 1 << endl; return; } res.push_back(pair<int, int>(j, dp[j])); while (j > 0) { j = pi[j]; if (j == 0) break; res.push_back(pair<int, int>(j, dp[j])); } cout << res.size() << endl; for (int i = res.size() - 1; i >= 0; i--) cout << res[i].first << << res[i].second << endl; } int main() { string s; cin >> s; solve(s); } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/counter.v
*/
// Behavioral model for the 32-bit program counter
module prog_counter2 (out_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] out_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] out_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst==1)
begin
// Set its value to ZERO
out_pc<=32'd0;
end
else
begin
out_pc<=out_pc+32'd4;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) { cerr << n ; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << setw(2) << *it << = << setw(2) << a << ; err(++it, args...); } void solve() { int n; cin >> n; int a[n], status[n], res[n]; memset(res, 0, sizeof res); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> status[i]; for (int i = 0; i < n; i++) if (status[i]) res[i] = a[i]; vector<int> v; for (int i = 0; i < n; i++) { if (status[i] == 0) v.push_back(a[i]); } sort(v.rbegin(), v.rend()); int idx = 0; for (int i = 0; i < n; i++) if (status[i] == 0) res[i] = v[idx++]; for (int i = 0; i < n; i++) cout << res[i] << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int test; cin >> test; while (test--) solve(); return 0; } |
#include <bits/stdc++.h> const int MN = 1e5 + 4, INF = 0x3f3f3f3f; int N, R, M, ans, D, A[MN], depth[MN], ord[MN], ecnt, ein[MN], eout[MN], st[MN]; std::vector<int> adj[MN]; struct nd { int l, r, val; nd *ch[2]; nd() : l(0), r(0), val(INF), ch{0} {} } * sgt[MN]; void dfs(int src, int p, int d) { depth[src] = d; ein[src] = ++ecnt; for (int i : adj[src]) { if (i == p) continue; dfs(i, src, d + 1); } eout[src] = ecnt; } inline void upd(nd *n) { n->val = std::min(n->ch[0]->val, n->ch[1]->val); } void build(nd *&n, int l, int r) { n = new nd(); n->l = l, n->r = r; if (l == r) return; int mid = l + r >> 1; build(n->ch[0], l, mid); build(n->ch[1], mid + 1, r); } void mod(nd *&n, nd *o, int p, int v) { n = new nd(); n->l = o->l, n->r = o->r; if (n->l == n->r) { n->val = v; return; } int mid = n->l + n->r >> 1; bool b = p > mid; n->ch[!b] = o->ch[!b]; mod(n->ch[b], o->ch[b], p, v); upd(n); } int qry(nd *n, int l, int r) { if (l > n->r || r < n->l) return INF; if (l <= n->l && n->r <= r) return n->val; return std::min(qry(n->ch[0], l, r), qry(n->ch[1], l, r)); } int main() { scanf( %d%d , &N, &R); for (int i = 1; i <= N; scanf( %d , A + i++)) ; for (int i = 1, a, b; i < N; ++i) { scanf( %d%d , &a, &b); adj[a].emplace_back(b); adj[b].emplace_back(a); } dfs(R, -1, 1); for (int i = 0; i < N; ++i) ord[i] = i + 1; std::stable_sort(ord, ord + N, [=](const int &a, const int &b) { return depth[a] < depth[b]; }); build(sgt[0], 1, N); for (int i = 0; i < N; ++i) { if (depth[ord[i]] != D) st[D++] = i; mod(sgt[i + 1], sgt[i], ein[ord[i]], A[ord[i]]); } st[D] = N; scanf( %d , &M); for (int i = 0, a, b; i < M; ++i) { scanf( %d%d , &a, &b); a = ((a + ans) % N) + 1, b = (b + ans) % N; printf( %d n , ans = qry(sgt[st[std::min(depth[a] + b, D)]], ein[a], eout[a])); } } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { int t; cin >> t; while (t--) { int n; cin >> n; int ar[n]; for (int i = 0; i < n; i++) { cin >> ar[i]; --ar[i]; } for (int i = 0; i < n; i++) { int pos = i, j = i, cnt = 1, kaku = ar[i]; while (kaku != pos) { j = ar[j]; kaku = ar[j]; cnt++; } cout << cnt << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int dx[4] = {-1, 0, 0, +1}; long long int dy[4] = {0, -1, +1, 0}; const long long int LINF = 1e18; const long long int INF = 1e9; const long long int mod = 1e9 + 7; long long int power(long long int a, long long int b, long long int m) { if (b == 0) return 1; if (b == 1) return a % m; long long int t = power(a, b / 2, m); t = (t * t) % m; if (b & 1) t = (t * a) % m; return t; } long long int modInverse(long long int a, long long int m) { return power(a, m - 2, m); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, ans = 0, i, j; string ip; cin >> ip; long long int sz = ip.size(); if (ip[0] == ? ) { if (sz >= 2 && ip[1] == a ) ip[0] = b ; else ip[0] = a ; } for (long long int i = 1; i <= -1 + ip.size(); i++) { if (ip[i] == ? ) { if (ip[i - 1] == a ) { if ((i + 1) < sz && ip[i + 1] == b ) ip[i] = c ; else ip[i] = b ; } else if (ip[i - 1] == b ) { if ((i + 1) < sz && ip[i + 1] == a ) ip[i] = c ; else ip[i] = a ; } else if (ip[i - 1] == c ) { if ((i + 1) < sz && ip[i + 1] == a ) ip[i] = b ; else ip[i] = a ; } else ip[i] = a ; } } bool poss = true; for (long long int i = 1; i <= sz - 1; i++) { if (ip[i] == ip[i - 1]) { cout << -1 << endl; poss = false; break; } } if (poss) cout << ip << endl; } return 0; } |
//****************************************************************************/
// AMBA conponents
// RTL IMPLEMENTATION, Synchronous Version
//
// Copyright (C) yyyy Ronan Barzic -
// Date : Mon Nov 9 10:03:03 2015
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : sync_ram_wf.v
//
// Description : Synchronous RAM model, write first
// suitable for FPGA synthesis (Xilinx Block RAM)
// Source : ug901-vivado-synthesis-examples.zip
//
//****************************************************************************/
module sync_ram_wf (/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, we, en, addr, din
);
parameter WORD_WIDTH = 16;
parameter ADDR_WIDTH = 10;
input clk;
input we;
input en;
input [9:0] addr;
input [WORD_WIDTH-1:0] din;
output [WORD_WIDTH-1:0] dout;
reg [WORD_WIDTH-1:0] RAM [(2<<ADDR_WIDTH)-1:0];
reg [WORD_WIDTH-1:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
begin
RAM[addr] <= din;
dout <= din;
end
else begin
dout <= RAM[addr];
end
end
end
endmodule // sync_ram_wf
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; int n, a, b, x, r; int main() { for (cin >> n >> a >> b, r = n; x * a <= n; x++) r = min(r, (n - x * a) % (5 * b)); cout << r; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100; int n, x, a; int f[MAXN + 1]; int main() { cin >> n >> x; memset(f, 0, sizeof f); for (int i = 0; i < n; i++) { cin >> a; f[a] = 1; } int ans = 0; for (int i = 0; i < x; i++) { if (f[i] == 0) ans++; } if (f[x] == 1) ans++; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; namespace Xrocks {} using namespace Xrocks; namespace Xrocks { class in { } user_input; class out { } output; in& operator>>(in& X, int& Y) { scanf( %d , &Y); return X; } in& operator>>(in& X, char* Y) { scanf( %s , Y); return X; } in& operator>>(in& X, float& Y) { scanf( %f , &Y); return X; } in& operator>>(in& X, double& Y) { scanf( %lf , &Y); return X; } in& operator>>(in& X, char& C) { scanf( %c , &C); return X; } in& operator>>(in& X, string& Y) { cin >> Y; return X; } in& operator>>(in& X, long long& Y) { scanf( %lld , &Y); return X; } template <typename T> in& operator>>(in& X, vector<T>& Y) { for (auto& x : Y) user_input >> x; return X; } template <typename T> out& operator<<(out& X, T Y) { cout << Y; return X; } template <typename T> out& operator<<(out& X, vector<T>& Y) { for (auto& x : Y) output << x << ; return X; } out& operator<<(out& X, const int& Y) { printf( %d , Y); return X; } out& operator<<(out& X, const char& C) { printf( %c , C); return X; } out& operator<<(out& X, const string& Y) { printf( %s , Y.c_str()); return X; } out& operator<<(out& X, const long long& Y) { printf( %lld , Y); return X; } out& operator<<(out& X, const float& Y) { printf( %f , Y); return X; } out& operator<<(out& X, const double& Y) { printf( %lf , Y); return X; } out& operator<<(out& X, const char Y[]) { printf( %s , Y); return X; } template <typename T> T max(T A) { return A; } template <typename T, typename... args> T max(T A, T B, args... S) { return max(A > B ? A : B, S...); } template <typename T> T min(T A) { return A; } template <typename T, typename... args> T min(T A, T B, args... S) { return min(A < B ? A : B, S...); } template <typename T> void vectorize(int y, vector<T>& A) { A.resize(y); } template <typename T, typename... args> void vectorize(int y, vector<T>& A, args&&... S) { A.resize(y); vectorize(y, S...); } long long fast(long long a, long long b, long long pr) { if (b == 0) return 1 % pr; long long ans = 1 % pr; while (b) { if (b & 1) ans = (ans * a) % pr; b >>= 1; a = (a * a) % pr; } return ans; } int readInt() { int n = 0; scanf( %d , &n); return n; int ch = getchar_unlocked(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar_unlocked(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar_unlocked(); n = n * sign; return n; } long long readLong() { long long n = 0; int ch = getchar_unlocked(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar_unlocked(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar_unlocked(); n = n * sign; return n; } long long inv_(long long val, long long pr = static_cast<long long>(163577857)) { return fast(val, pr - 2, pr); } } // namespace Xrocks int op1(int a, int b) { return a | b; } int op2(int a, int b) { return a & b; } int op3(int a, int b) { return a ^ b; } class solve { public: solve() { vector<int (*)(int, int)> g = {op1, op2, op3}; vector<int> v{0, 1, 2}; vector<int> w(4); user_input >> w; int x = 0; do { vector<int (*)(int, int)> f = g; for (int i = 0; i < 3; i++) f[i] = g[v[i]]; if (x == 5) output << f[0](f[1](f[0](w[0], w[1]), f[2](w[2], w[3])), f[2](f[1](w[1], w[2]), f[0](w[3], w[0]))) << n ; ++x; } while (next_permutation(v.begin(), v.end())); } }; int32_t main() { int t = 1, i = 1; if (0) scanf( %d , &t); while (t--) { if (0) printf( Case #%d: , i++); new solve; } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_dst_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_dst_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_dst_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_dst_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T in() { char ch; T n = 0; bool ng = false; while (1) { ch = getchar(); if (ch == - ) { ng = true; ch = getchar(); break; } if (ch >= 0 && ch <= 9 ) break; } while (1) { n = n * 10 + (ch - 0 ); ch = getchar(); if (ch < 0 || ch > 9 ) break; } return (ng ? -n : n); } template <typename T> inline T POW(T B, T P) { if (P == 0) return 1; if (P & 1) return B * POW(B, P - 1); else return (POW(B, P / 2) * POW(B, P / 2)); } template <typename T> inline T Gcd(T a, T b) { if (a < 0) return Gcd(-a, b); if (b < 0) return Gcd(a, -b); return (b == 0) ? a : Gcd(b, a % b); } template <typename T> inline T Lcm(T a, T b) { if (a < 0) return Lcm(-a, b); if (b < 0) return Lcm(a, -b); return a * (b / Gcd(a, b)); } long long Bigmod(long long base, long long power, long long MOD) { long long ret = 1; while (power) { if (power & 1) ret = (ret * base) % MOD; base = (base * base) % MOD; power >>= 1; } return ret; } bool isVowel(char ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } template <typename T> long long int isLeft(T a, T b, T c) { return (a.x - b.x) * (b.y - c.y) - (b.x - c.x) * (a.y - b.y); } long long ModInverse(long long number, long long MOD) { return Bigmod(number, MOD - 2, MOD); } bool isConst(char ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } int toInt(string s) { int sm; stringstream second(s); second >> sm; return sm; } int a[3][77]; int Ln[3]; int n; int dp[77][77][77][2]; int lol(int v, int k, int x, int f) { if ((v + k + x) == n) return 0; int &res = dp[v][k][x][f]; if (res != -1) return res; res = 20000; int np = v + k + x + 1; if (v < Ln[1]) { int tp = 0; int ps = a[1][v]; for (int i = x; i < Ln[0]; i++) { if (a[0][i] < ps) tp++; else break; } for (int i = k; i < Ln[2]; i++) { if (a[2][i] < ps) tp++; else break; } res = min(res, tp + lol(v + 1, k, x, 1)); } if (!f) { if (k < Ln[2]) { int tp = 0; int ps = a[2][k]; for (int i = x; i < Ln[0]; i++) { if (a[0][i] < ps) tp++; else break; } for (int i = v; i < Ln[1]; i++) { if (a[1][i] < ps) tp++; else break; } res = min(res, tp + lol(v, k + 1, x, 0)); } } if (x < Ln[0]) { int tp = 0; int ps = a[0][x]; for (int i = v; i < Ln[1]; i++) { if (a[1][i] < ps) tp++; else break; } for (int i = k; i < Ln[2]; i++) { if (a[2][i] < ps) tp++; else break; } res = min(res, tp + lol(v, k, x + 1, 0)); } return res; } map<char, int> mp; int main() { mp[ V ] = 1; mp[ K ] = 2; string s; cin >> n; cin >> s; for (int i = 1; i <= n; i++) { int tp = mp[s[i - 1]]; a[tp][Ln[tp]] = i; Ln[tp]++; } memset(dp, -1, sizeof(dp)); cout << lol(0, 0, 0, 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, dp[30010][210][4], num[30010]; int main() { int i, j; cin >> n >> m; for (i = 1; i <= n; i++) scanf( %d , &num[i]); memset(dp[0], -0x3f, sizeof(dp[0])); for (i = 0; i < 4; i++) dp[0][0][i] = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { int tmp = 1 + (j != 1 && j != m); dp[i][j][0] = max(dp[i - 1][j][0], dp[i - 1][j - 1][3]) - tmp * num[i]; dp[i][j][1] = max(dp[i - 1][j][1], dp[i][j][0]); dp[i][j][2] = max(dp[i - 1][j][2], dp[i - 1][j - 1][1]) + tmp * num[i]; dp[i][j][3] = max(dp[i - 1][j][3], dp[i][j][2]); if (tmp == 2) { dp[i][j][1] = max(dp[i][j][1], dp[i - 1][j - 1][1]); dp[i][j][3] = max(dp[i][j][3], dp[i - 1][j - 1][3]); } } } cout << max(max(dp[n][m][0], dp[n][m][1]), max(dp[n][m][2], dp[n][m][3])); } |
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, m; cin >> n >> m; long long int n1, m1; cin >> n1 >> m1; long long int a[n], b[m]; for (long long int i = 0; i < n; i++) cin >> a[i]; for (long long int i = 0; i < m; i++) cin >> b[i]; if (a[n1 - 1] < b[m - m1]) cout << YES << endl; else cout << NO << endl; } int32_t main() { ios_base ::sync_with_stdio(false), cin.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 11; const long long MOD = 1000000007LL; int dp[N][N][3]; long long t[N][N]; int cnt[N], c[N]; int n; string s; long long ans = 0; void init() { for (int i = 0; i <= n; ++i) { for (int k = 1; k <= 6; ++k) { if (cnt[i] < k) t[i][k] = 0; else { t[i][k] = 1LL; for (int j = cnt[i] - k + 1; j <= cnt[i]; ++j) { t[i][k] = (t[i][k] * (long long)j) % MOD; } } } } } void solve(int i, int k, int st) { if (i > 6) { long long p = cnt[st] * 1LL; for (int j = 0; j <= n; ++j) { if (c[j] == 0) continue; if (c[j] > cnt[j]) return; p = (p * t[j][c[j]]) % MOD; } ans = (ans + p) % MOD; return; } for (int j = 0; j < k; ++j) { c[j]++; solve(i + 1, k - j, st); c[j]--; } } int main() { cin >> s; n = (int)(s).size(); memset(dp, 0, sizeof(dp)); for (int i = 1; i <= 9; ++i) { int k; if (i == 4 || i == 7) k = 1; else k = 0; dp[1][k][0] += (s[0] - 0 > i) ? 1 : 0; dp[1][k][1] += (s[0] - 0 == i) ? 1 : 0; dp[1][k][2] += (s[0] - 0 < i) ? 1 : 0; } for (int i = 2; i <= n; ++i) { for (int k = 0; k <= i; ++k) { dp[i][k][1] = ((s[i - 1] == 4 || s[i - 1] == 7 ) ? dp[i - 1][k - 1][1] : dp[i - 1][k][1]); if ((s[i - 1] == 4 || s[i - 1] == 7 ) && k == 0) dp[i][k][1] = 0; for (int j = 0; j < 10; ++j) { if (j == 4 || j == 7) { if (k != 0) { dp[i][k][0] += (dp[i - 1][k - 1][0] + (j < (s[i - 1] - 0 ) ? dp[i - 1][k - 1][1] : 0)); dp[i][k][2] += (dp[i - 1][k - 1][2] + (j > (s[i - 1] - 0 ) ? dp[i - 1][k - 1][1] : 0)); } } else { dp[i][k][0] += (dp[i - 1][k][0] + ((j < s[i - 1] - 0 ) ? dp[i - 1][k][1] : 0)); dp[i][k][2] += (dp[i - 1][k][2] + ((j > s[i - 1] - 0 ) ? dp[i - 1][k][1] : 0)); } } } } for (int k = 0; k <= n; ++k) { cnt[k] = 0; for (int i = 1; i <= n; ++i) { cnt[k] += dp[i][k][0] + dp[i][k][1]; if (i < n) cnt[k] += dp[i][k][2]; } } init(); ans = 0; for (int i = 1; i <= n; ++i) { solve(1, i, i); } printf( %I64d , ans); return 0; } |
`include "defines.v"
module cp0_reg(
input wire clk,
input wire rst,
input wire we_i,
input wire[4:0] waddr_i,
input wire[4:0] raddr_i,
input wire[`RegBus] data_i,
input wire[31:0] excepttype_i,
input wire[5:0] int_i,
input wire[`RegBus] current_inst_addr_i,
input wire is_in_delayslot_i,
output reg[`RegBus] data_o,
output reg[`RegBus] count_o,
output reg[`RegBus] compare_o,
output reg[`RegBus] status_o,
output reg[`RegBus] cause_o,
output reg[`RegBus] epc_o,
output reg[`RegBus] config_o,
output reg[`RegBus] prid_o,
output reg timer_int_o
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
count_o <= `ZeroWord;
compare_o <= `ZeroWord;
//status¼Ä´æÆ÷µÄCUΪ0001£¬±íʾд¦ÀíÆ÷CP0´æÔÚ
status_o <= 32'b00010000000000000000000000000000;
cause_o <= `ZeroWord;
epc_o <= `ZeroWord;
//config¼Ä´æÆ÷µÄBEΪ1£¬±íʾBig-Endian£»MTΪ00£¬±íʾûÓÐMMU
config_o <= 32'b00000000000000001000000000000000;
//ÖÆ×÷ÕßÊÇL£¬¶ÔÓ¦µÄÊÇ0x48£¬ÀàÐÍÊÇ0x1£¬»ù±¾ÀàÐÍ£¬°æ±¾ºÅÊÇ1.0
prid_o <= 32'b00000000010011000000000100000010;
timer_int_o <= `InterruptNotAssert;
end else begin
count_o <= count_o + 1 ;
cause_o[15:10] <= int_i;
if(compare_o != `ZeroWord && count_o == compare_o) begin
timer_int_o <= `InterruptAssert;
end
if(we_i == `WriteEnable) begin
case (waddr_i)
`CP0_REG_COUNT: begin
count_o <= data_i;
end
`CP0_REG_COMPARE: begin
compare_o <= data_i;
//count_o <= `ZeroWord;
timer_int_o <= `InterruptNotAssert;
end
`CP0_REG_STATUS: begin
status_o <= data_i;
end
`CP0_REG_EPC: begin
epc_o <= data_i;
end
`CP0_REG_CAUSE: begin
//cause¼Ä´æÆ÷Ö»ÓÐIP[1:0]¡¢IV¡¢WP×Ö¶ÎÊÇ¿ÉдµÄ
cause_o[9:8] <= data_i[9:8];
cause_o[23] <= data_i[23];
cause_o[22] <= data_i[22];
end
endcase //case addr_i
end
case (excepttype_i)
32'h00000001: begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b00000;
end
32'h00000008: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01000;
end
32'h0000000a: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01010;
end
32'h0000000d: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01101;
end
32'h0000000c: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
end else begin
epc_o <= current_inst_addr_i;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01100;
end
32'h0000000e: begin
status_o[1] <= 1'b0;
end
default: begin
end
endcase
end //if
end //always
always @ (*) begin
if(rst == `RstEnable) begin
data_o <= `ZeroWord;
end else begin
case (raddr_i)
`CP0_REG_COUNT: begin
data_o <= count_o ;
end
`CP0_REG_COMPARE: begin
data_o <= compare_o ;
end
`CP0_REG_STATUS: begin
data_o <= status_o ;
end
`CP0_REG_CAUSE: begin
data_o <= cause_o ;
end
`CP0_REG_EPC: begin
data_o <= epc_o ;
end
`CP0_REG_PrId: begin
data_o <= prid_o ;
end
`CP0_REG_CONFIG: begin
data_o <= config_o ;
end
default: begin
end
endcase //case addr_i
end //if
end //always
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_fpio.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_buf_fpio(/*AUTOARG*/
// Outputs
pcx_fpio_data_px, pcx_fpio_data_rdy_px,
// Inputs
pcx_fpio_data_ff_px, pcx_fpio_data_rdy_arb_px
);
output [`PCX_WIDTH-1:0]pcx_fpio_data_px;
output pcx_fpio_data_rdy_px;
input [`PCX_WIDTH-1:0]pcx_fpio_data_ff_px;
input pcx_fpio_data_rdy_arb_px;
assign pcx_fpio_data_px[`PCX_WIDTH-1:0] = pcx_fpio_data_ff_px[`PCX_WIDTH-1:0];
assign pcx_fpio_data_rdy_px = pcx_fpio_data_rdy_arb_px;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
delay_clk,
up_status,
dma_dbg_data,
dma_dbg_trigger,
adc_clk,
adc_dbg_data,
adc_dbg_trigger,
adc_mon_valid,
adc_mon_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_CF_BUFTYPE = 0;
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
input delay_clk;
output [ 7:0] up_status;
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
output adc_clk;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_mon_valid;
output [15:0] adc_mon_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_adc_1c #(.C_CF_BUFTYPE(C_CF_BUFTYPE)) i_adc_1c (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.up_status (up_status),
.delay_clk (delay_clk),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_clk (adc_clk),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; vector<long long int> graph[250]; long long int n, a[250]; long long int visit[250]; long long int sol(long long int pos) { memset(visit, 0, sizeof(visit)); long long int ans = 0; long long int c = 0; while (c <= n) { long long int f = 0; for (long long int i = 1; i <= n; i++) { if (a[i] != pos || visit[i]) { continue; } long long int ff = 1; for (auto p : graph[i]) { if (!visit[p]) { ff = 0; break; } } if (ff) { f = 1; ans++; c++; visit[i] = 1; } } if (c == n) { break; } if (!f) { pos++; ans++; if (pos == 4) { pos = 1; } } } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long int i = 1; i <= n; i++) { cin >> a[i]; } for (long long int i = 1; i <= n; i++) { long long int k; cin >> k; for (long long int j = 1; j <= k; j++) { long long int tl; cin >> tl; graph[i].push_back(tl); } } long long int ans = 1e18; for (long long int i = 1; i <= 3; i++) { ans = min(ans, sol(i)); } cout << ans << n ; } |
module EX(
input [31:0] PC_ID_EX_out,
input [31:0] PC_IF_ID,
input [1:0] ExResultSrc,
input ALUSrcA,
input ALUSrcB,
input [3:0] ALUOp,
input [1:0] RegDst,
input ShiftAmountSrc,
input [1:0] ShiftOp,
input [31:0] A_in,
input [31:0] B_in,
input [4:0] Rs,Rt,Rd,
input [31:0] Imm32,
input [4:0] Shamt,
input [7:0] A_in_sel,
input [7:0] B_in_sel,
input [31:0] WBData_Mem,
input [31:0] Data,
output reg [31:0] Branch_Addr,
output [31:0] WBData_EX,
output [31:0] MemData,
output [31:0] A,
output Less,Zero,Overflow,
output [4:0] Rd_Dst,
output [31:0] ALU_A, ALU_B
//output [31:0]Rs_out_EX, Rt_out_EX
);
//wire [31:0] ALU_A,ALU_B;
wire [4:0] ShiftAmount;
wire [31:0] ALU_out;
wire [31:0] Shift_out;
//转发选择单元
always@(PC_ID_EX_out or Imm32)begin
Branch_Addr[31:2] <= PC_ID_EX_out[31:2] + Imm32[31:2];
Branch_Addr[1:0] <= 2'b00;
end
select3_8 s41(A_in[31:24],WBData_Mem[31:24],Data[31:24],A_in_sel[7:6],A[31:24]);
select3_8 s42(A_in[23:16],WBData_Mem[31:24],Data[23:16],A_in_sel[5:4],A[23:16]);
select3_8 s43(A_in[15:8],WBData_Mem[31:24],Data[15:8],A_in_sel[3:2],A[15:8]);
select3_8 s44(A_in[7:0],WBData_Mem[31:24],Data[7:0],A_in_sel[1:0],A[7:0]);
select3_8 s45(B_in[31:24],WBData_Mem[31:24],Data[31:24],B_in_sel[7:6],MemData[31:24]);
select3_8 s46(B_in[23:16],WBData_Mem[31:24],Data[23:16],B_in_sel[5:4],MemData[23:16]);
select3_8 s47(B_in[15:8],WBData_Mem[31:24],Data[15:8],B_in_sel[3:2],MemData[15:8]);
select3_8 s48(B_in[7:0],WBData_Mem[31:24],Data[7:0],B_in_sel[1:0],MemData[7:0]);
//A操作数选择
select2_32 s2(A,32'b0,ALUSrcA,ALU_A);
//B操作数选择
select2_32 s3(MemData,Imm32,ALUSrcB,ALU_B);
//ALU
ALU ALU(ALU_A,ALU_B,ALUOp,ALU_out,Less,Zero,Overflow);
//Rd写入地址xuanze
select3_5 s4(Rd,Rt,5'b11111,RegDst,Rd_Dst);
//移位位数选择
select3_32 s5(Shamt,A[4:0],ShiftAmountSrc,ShiftAmount);
//桶形移位器
Shifter Shifter(ShiftAmount,MemData,ShiftOp,Shift_out);
//EX段结果选择
select3_32 s6(PC_IF_ID,ALU_out,Shift_out,ExResultSrc,WBData_EX);
endmodule
//ALU
module ALU(
input [31:0] a,
input [31:0] b,
input [3:0] ALU_op,
output reg [31:0] ALU_out,
output reg less,
output reg zero,
output reg overflow
);
reg [2:0] ALU_ctr;
reg [31:0] result [7:0];
reg carry;
reg OF;
reg negative;
reg [31:0] temp;
reg [31:0] b_not;
reg flag;
integer i;
always@(*)
begin
case(ALU_op) //由ALU_op产生对应ALU_ctr控制信号
4'b0000:ALU_ctr=3'b111;
4'b0001:ALU_ctr=3'b111;
4'b0010:ALU_ctr=3'b000;
4'b0011:ALU_ctr=3'b000;
4'b0100:ALU_ctr=3'b100;
4'b0101:ALU_ctr=3'b101;
4'b0110:ALU_ctr=3'b010;
4'b0111:ALU_ctr=3'b101;
4'b1000:ALU_ctr=3'b011;
4'b1001:ALU_ctr=3'b001;
4'b1010:ALU_ctr=3'b110;
4'b1011:ALU_ctr=3'b110;
4'b1110:ALU_ctr=3'b111;
4'b1111:ALU_ctr=3'b111;
default:ALU_ctr=3'b000;
endcase
if(ALU_op[0]==0) //由ALU_op[0]控制加减法
b_not=b^32'h00000000;
else
b_not=b^32'hffffffff;
{carry,result[7]}=b_not+a+ALU_op[0];//计算a+b+ALU_op[0]
OF=((~a[31])&(~b_not[31])&result[7][31])|(a[31]&(b_not[31])&(~result[7][31]));//ALU运算产生的Overflow
negative=result[7][31];
if(result[7]==32'b0)
zero=1;
else
zero=0;
overflow=OF&ALU_op[1]&&ALU_op[2]&&ALU_op[3];//最终Overflow
if(ALU_op[0]&&ALU_op[1]&&ALU_op[2]&&(!ALU_op[3]))
less=!carry;
else
less=OF^negative;
if(ALU_op[0]==1) //seb/seh
begin
if(b[15]==0)
result[6]={16'h0000,b[15:0]};
else
result[6]={16'hffff,b[15:0]};
end
else
begin
if(b[7]==0)
result[6]={24'h000000,b[7:0]};
else
result[6]={24'hffffff,b[7:0]};
end
if(less==0) //slt/slti/sltu/sltiu
result[5]=32'h00000000;
else
result[5]=32'hffffffff;
result[4]=a&b;//与
result[3]=~(a|b);//或非
result[2]=(a|b);//或
result[1]=a^b;//异或
if(ALU_op[0]==0) //计算前导0前导1
temp=a^32'h00000000;
else
temp=a^32'hffffffff;
result[0]=32'h00000000;
flag=0;
for(i=31;i>=0;i=i-1)
begin
if(flag==0&&temp[i]==0)
result[0]=result[0]+32'h00000001;
if(temp[i]==1)
flag=1;
end
ALU_out=result[ALU_ctr];
end
endmodule
module Shifter(
input [4:0] shift_amount,
input [31:0] shift_in,
input [1:0] shift_op,
output reg [31:0] shift_out
);
integer i; //循环计数
always@(shift_in or shift_op or shift_amount)
begin
shift_out={shift_in[31:0]};
for(i=0;i<shift_amount;i=i+1) //由移位位数控制循环次数
case(shift_op)
2'b00:
shift_out={shift_out[30:0],1'b0}; //逻辑左移一位
2'b01:
shift_out={1'b0,shift_out[31:1]};//逻辑右移一位
2'b10:
begin
if(shift_out[31]==0) //算数右移一位
shift_out={1'b0,shift_out[31:1]};
else
shift_out={1'b1,shift_out[31:1]};
end
2'b11:
shift_out={shift_out[0],shift_out[31:1]}; //循环右移一位
endcase
end
endmodule
|
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