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module relay_encode(
clk,
reset,
mode,
data_in,
data_out
);
input clk, reset, mode, data_in;
output data_out;
reg [0:0] data_out = 1'b0;
reg [7:0] buffer_in = 8'b0;
reg [7:0] data_out_counter = 8'b0;
reg [6:0] data_out_delay_counter = 7'b0;
reg [2:0] bit_counter = 3'b0;
reg [0:0] comm_active = 1'b0;
reg [0:0] received_zero = 1'b0;
reg [3:0] counter = 4'b0;
always @(posedge clk)
begin
// encode
counter = counter + 1;
if (counter[3:0] == 4'b0)
begin
bit_counter = bit_counter + 1;
buffer_in = {buffer_in[6:0], data_in};
end
if (|data_out_counter == 1'b1)
data_out_counter = data_out_counter - 1;
if (|data_out_delay_counter == 1'b1)
data_out_delay_counter = data_out_delay_counter - 1;
if (mode == 1'b0 && counter[3:0] == 4'b0) // encode (and demodulate) reader data
begin
// start of comm
if (buffer_in[7:6] == 2'b0 && buffer_in[3:0] == 4'hf && comm_active == 1'b0)
begin
bit_counter = 3'b0;
comm_active = 1'b1;
received_zero = 1'b0;
end
if (comm_active == 1'b1 && bit_counter == 3'b0)
begin
// end of comm
if (buffer_in == 8'hff && received_zero == 1'b1)
begin
comm_active = 1'b0;
received_zero = 1'b0;
end
// 0xff => 0x00
if (buffer_in == 8'hff)
begin
data_out = 1'b0;
received_zero = 1'b1;
end
// 0xXf => 0xc0
else if (buffer_in[3:0] == 4'hf)
begin
data_out_counter = 8'b1000000;
data_out = 1'b1;
received_zero = 1'b1;
end
// 0xfX => 0x0c
else if (buffer_in[7:4] == 4'hf)
begin
data_out_delay_counter = 7'b1000000;
data_out_counter = 8'b10000000;
data_out = 1'b0;
received_zero = 1'b0;
end
end
end
else if (mode == 1'b1 && counter[3:0] == 4'b0)
begin
// start of comm
if (buffer_in[7:5] == 3'b111 && buffer_in[3:1] == 3'b0 && comm_active == 1'b0)
begin
bit_counter = 3'b0;
comm_active = 1'b1;
received_zero = 1'b0;
end
if (comm_active == 1'b1 && bit_counter == 3'b0)
begin
// end of comm
if (buffer_in == 8'h00)
begin
if (received_zero == 1'b1)
comm_active = 1'b0;
received_zero = 1'b1;
end
// 0xX0 => 0xf0
else if (buffer_in[3:0] == 4'h0)
begin
data_out_counter = 8'b1000000;
data_out = 1'b1;
received_zero = 1'b0;
end
// 0x0X => 0x0f
else if (buffer_in[7:4] == 4'h0)
begin
data_out_delay_counter = 7'b1000000;
data_out_counter = 8'b10000000;
data_out = 1'b0;
received_zero = 1'b0;
end
end
end
if (data_out_counter == 8'b0)
data_out = 1'b0;
if (data_out_delay_counter == 7'b0 && |data_out_counter == 1'b1)
data_out = 1'b1;
// reset
if (reset == 1'b1)
begin
buffer_in = 8'b0;
data_out = 1'b0;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; string slv(string s) { int sz = s.size(); if (sz % 2 == 1) return s; else { string a = slv(s.substr(0, sz / 2)); string b = slv(s.substr(sz / 2, sz)); return a < b ? a + b : b + a; } } int main() { string a, b; cin >> a >> b; cout << ((slv(a) == slv(b)) ? YES : NO ); } |
////////////////////////////////////////////////////////////////////////////////
//
// Filename: memops.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A memory unit to support a CPU.
//
// In the interests of code simplicity, this memory operator is
// susceptible to unknown results should a new command be sent to it
// before it completes the last one. Unpredictable results might then
// occurr.
//
// 20150919 -- Added support for handling BUS ERR's (i.e., the WB
// error signal).
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module memops(i_clk, i_rst, i_stb, i_lock,
i_op, i_addr, i_data, i_oreg,
o_busy, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=30;
parameter [0:0] IMPLEMENT_LOCK=1'b0,
WITH_LOCAL_BUS=1'b0;
localparam AW=ADDRESS_WIDTH;
input wire i_clk, i_rst;
input wire i_stb, i_lock;
// CPU interface
input wire [2:0] i_op;
input wire [31:0] i_addr;
input wire [31:0] i_data;
input wire [4:0] i_oreg;
// CPU outputs
output wire o_busy;
output reg o_valid;
output reg o_err;
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl;
output reg o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
output reg [3:0] o_wb_sel;
// Wishbone inputs
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [31:0] i_wb_data;
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
wire gbl_stb, lcl_stb;
assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff);
assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff));
initial r_wb_cyc_gbl = 1'b0;
initial r_wb_cyc_lcl = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
begin
if ((i_wb_ack)||(i_wb_err))
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
end
end else if (i_stb) // New memory operation
begin // Grab the wishbone
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
end
always @(posedge i_clk)
if (o_wb_cyc_gbl)
o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
else
o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation
always @(posedge i_clk)
if (o_wb_cyc_lcl)
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
else
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation
reg [3:0] r_op;
always @(posedge i_clk)
if (i_stb)
begin
o_wb_we <= i_op[0];
casez({ i_op[2:1], i_addr[1:0] })
`ifdef ZERO_ON_IDLE
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 };
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 };
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 };
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
`else
4'b10??: o_wb_data <= { (2){ i_data[15:0] } };
4'b11??: o_wb_data <= { (4){ i_data[7:0] } };
`endif
default: o_wb_data <= i_data;
endcase
o_wb_addr <= i_addr[(AW+1):2];
`ifdef SET_SEL_ON_READ
if (i_op[0] == 1'b0)
o_wb_sel <= 4'hf;
else
`endif
casez({ i_op[2:1], i_addr[1:0] })
4'b01??: o_wb_sel <= 4'b1111;
4'b100?: o_wb_sel <= 4'b1100;
4'b101?: o_wb_sel <= 4'b0011;
4'b1100: o_wb_sel <= 4'b1000;
4'b1101: o_wb_sel <= 4'b0100;
4'b1110: o_wb_sel <= 4'b0010;
4'b1111: o_wb_sel <= 4'b0001;
default: o_wb_sel <= 4'b1111;
endcase
r_op <= { i_op[2:1] , i_addr[1:0] };
end
`ifdef ZERO_ON_IDLE
else if ((!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl))
begin
o_wb_we <= 1'b0;
o_wb_addr <= 0;
o_wb_data <= 32'h0;
o_wb_sel <= 4'h0;
end
`endif
initial o_valid = 1'b0;
always @(posedge i_clk)
o_valid <= (!i_rst)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
initial o_err = 1'b0;
always @(posedge i_clk)
o_err <= (!i_rst)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
always @(posedge i_clk)
if (i_stb)
o_wreg <= i_oreg;
always @(posedge i_clk)
`ifdef ZERO_ON_IDLE
if (!i_wb_ack)
o_result <= 32'h0;
else
`endif
casez(r_op)
4'b01??: o_result <= i_wb_data;
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };
default: o_result <= i_wb_data;
endcase
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
end
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
// Make verilator happy
// verilator lint_off UNUSED
wire unused;
assign unused = i_lock;
// verilator lint_on UNUSED
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SEDFXTP_PP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_PP_BLACKBOX_V
|
/**
* bsg_mesh_router.v
*
*
* dims_p network
* ------------------------
* 1 1-D mesh
* 2 2-D mesh
* 3 2-D mesh + half ruche x
* 4 2-D mesh + full ruche
*
* ruche_factor_X/Y_p determines the number of hops that ruche links extend in the direction.
*
* Currently only tested for
* - 2-D mesh
* - 2-D mesh + half ruche x
*/
`include "bsg_defines.v"
module bsg_mesh_router
import bsg_noc_pkg::*;
import bsg_mesh_router_pkg::*;
#(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(x_cord_width_p )
, parameter `BSG_INV_PARAM(y_cord_width_p )
, parameter ruche_factor_X_p = 0
, parameter ruche_factor_Y_p = 0
, parameter dims_p = 2
, parameter dirs_lp = (2*dims_p)+1
, parameter XY_order_p = 1
, parameter bit [dirs_lp-1:0][dirs_lp-1:0] routing_matrix_p =
(dims_p == 2) ? (XY_order_p ? StrictXY : StrictYX) : (
(dims_p == 3) ? (XY_order_p ? HalfRucheX_StrictXY : HalfRucheX_StrictYX) : (
(dims_p == 4) ? (XY_order_p ? FullRuche_StrictXY : FullRuche_StrictYX) : "inv"))
, parameter debug_p = 0
)
(
input clk_i
, input reset_i
, input [dirs_lp-1:0][width_p-1:0] data_i
, input [dirs_lp-1:0] v_i
, output logic [dirs_lp-1:0] yumi_o
, input [dirs_lp-1:0] ready_i
, output [dirs_lp-1:0][width_p-1:0] data_o
, output logic [dirs_lp-1:0] v_o
// node's x and y coord
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
);
// input x,y coords
logic [dirs_lp-1:0][x_cord_width_p-1:0] x_dirs;
logic [dirs_lp-1:0][y_cord_width_p-1:0] y_dirs;
for (genvar i = 0; i < dirs_lp; i++) begin
assign x_dirs[i] = data_i[i][0+:x_cord_width_p];
assign y_dirs[i] = data_i[i][x_cord_width_p+:y_cord_width_p];
end
// dimension-ordered routing logic
logic [dirs_lp-1:0][dirs_lp-1:0] req, req_t;
for (genvar i = 0; i < dirs_lp; i++) begin: dor
logic [dirs_lp-1:0] temp_req;
bsg_mesh_router_decoder_dor #(
.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.ruche_factor_X_p(ruche_factor_X_p)
,.ruche_factor_Y_p(ruche_factor_Y_p)
,.dims_p(dims_p)
,.XY_order_p(XY_order_p)
,.from_p((dirs_lp)'(1 << i))
,.debug_p(debug_p)
) dor_decoder (
.clk_i(clk_i)
,.reset_i(reset_i)
,.x_dirs_i(x_dirs[i])
,.y_dirs_i(y_dirs[i])
,.my_x_i(my_x_i)
,.my_y_i(my_y_i)
,.req_o(temp_req)
);
assign req[i] = {dirs_lp{v_i[i]}} & temp_req;
end
bsg_transpose #(
.width_p(dirs_lp)
,.els_p(dirs_lp)
) req_tp (
.i(req)
,.o(req_t)
);
// Instantiate crossbars for each output direction
logic [dirs_lp-1:0][dirs_lp-1:0] yumi_lo, yumi_lo_t;
for (genvar i = 0; i < dirs_lp; i++) begin: xbar
localparam input_els_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[i]);
logic [input_els_lp-1:0][width_p-1:0] conc_data;
logic [input_els_lp-1:0] conc_req;
logic [input_els_lp-1:0] grants;
bsg_array_concentrate_static #(
.pattern_els_p(routing_matrix_p[i])
,.width_p(width_p)
) conc0 (
.i(data_i)
,.o(conc_data)
);
bsg_concentrate_static #(
.pattern_els_p(routing_matrix_p[i])
) conc1 (
.i(req_t[i])
,.o(conc_req)
);
assign v_o[i] = |conc_req;
bsg_arb_round_robin #(
.width_p(input_els_lp)
) rr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.reqs_i(conc_req)
,.grants_o(grants)
,.yumi_i(v_o[i] & ready_i[i])
);
bsg_mux_one_hot #(
.els_p(input_els_lp)
,.width_p(width_p)
) data_mux (
.data_i(conc_data)
,.sel_one_hot_i(grants)
,.data_o(data_o[i])
);
bsg_unconcentrate_static #(
.pattern_els_p(routing_matrix_p[i])
,.unconnected_val_p(1'b0)
) unconc0 (
.i(grants & {input_els_lp{ready_i[i]}})
,.o(yumi_lo[i])
);
end
bsg_transpose #(
.width_p(dirs_lp)
,.els_p(dirs_lp)
) yumi_tp (
.i(yumi_lo)
,.o(yumi_lo_t)
);
for (genvar i = 0; i < dirs_lp; i++) begin
assign yumi_o[i] = |yumi_lo_t[i];
end
// synopsys translate_off
if (debug_p) begin
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
for (integer i = 0; i < dirs_lp; i++) begin
assert($countones(yumi_lo_t[i]) < 2)
else $error("multiple yumi detected. i=%d, %b", i, yumi_lo_t[i]);
end
end
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesh_router)
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Oct 26 08:39:00 EDT 2015
//
// Method conflict info:
// Method: gen_grant_carry
// Conflict-free: gen_grant_carry
//
//
// Ports:
// Name I/O size props
// gen_grant_carry O 2
// gen_grant_carry_c I 1
// gen_grant_carry_r I 1
// gen_grant_carry_p I 1
//
// Combinational paths from inputs to outputs:
// (gen_grant_carry_c, gen_grant_carry_r, gen_grant_carry_p) -> gen_grant_carry
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module module_gen_grant_carry(gen_grant_carry_c,
gen_grant_carry_r,
gen_grant_carry_p,
gen_grant_carry);
// value method gen_grant_carry
input gen_grant_carry_c;
input gen_grant_carry_r;
input gen_grant_carry_p;
output [1 : 0] gen_grant_carry;
// signals for module outputs
wire [1 : 0] gen_grant_carry;
// value method gen_grant_carry
assign gen_grant_carry =
{ gen_grant_carry_r && (gen_grant_carry_c || gen_grant_carry_p),
!gen_grant_carry_r &&
(gen_grant_carry_c || gen_grant_carry_p) } ;
endmodule // module_gen_grant_carry
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
`timescale 1ps/1ps
module ad_serdes_clk (
// clock and divided clock
mmcm_rst,
clk_in_p,
clk_in_n,
clk,
div_clk,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFR_N = 1;
parameter MMCM_DEVICE_TYPE = 0;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clock and divided clock
input mmcm_rst;
input clk_in_p;
input clk_in_n;
output clk;
output div_clk;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal signals
wire clk_in_s;
// instantiations
IBUFGDS i_clk_in_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_s));
generate
if (MMCM_OR_BUFR_N == 1) begin
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_mmcm_drp (
.clk (clk_in_s),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 0)) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (clk));
assign div_clk = clk;
end
if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));
BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (div_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int a[n + 1]; for (int i = 0; i < n; i++) cin >> a[i]; map<int, int> mp; if (n & 1) { cout << -1 << endl; continue; } for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) mp[a[i] ^ a[j]]++; int ans = -1; for (auto it = mp.begin(); it != mp.end(); it++) { if (it->second == (n / 2)) { ans = it->first; break; } } cout << ans << endl; } } |
/*
A simplistic test for OBUFDS. Two of them are instanciated and their outpus
are connected to LEDs. Data inputs are controlled by switches.
Truth tables:
SW8 | LED3 LED2
0 | 1 0
1 | 0 1
SW10 | LED8 LED7
0 | 0 1
0 | 1 0
Couldn't use all switches and buttons at the same time as the differential
IOs use different IOSTANDARD than the single ended ones and have to be in
a separate bank.
*/
`default_nettype none
// ============================================================================
module top
(
input wire [11:8] sw,
output wire [1:0] diff_p,
output wire [1:0] diff_n
);
// ============================================================================
// OBUFTDS
wire [1:0] buf_i;
OBUFDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_0 (
.I(buf_i[0]),
.O(diff_p[0]), // LED2
.OB(diff_n[0]) // LED3
);
OBUFDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_1 (
.I(buf_i[1]),
.O(diff_p[1]), // LED8
.OB(diff_n[1]) // LED7
);
// ============================================================================
assign buf_i[0] = sw[ 8];
assign buf_i[1] = sw[10];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500000; int n, m; vector<int> nei[N + 1]; bool vis[N + 1]; int fa[N + 1], dep[N + 1]; void dfs(int x = 1) { vis[x] = true; for (int i = 0; i < nei[x].size(); i++) { int y = nei[x][i]; if (vis[y]) continue; fa[y] = x; dep[y] = dep[x] + 1; dfs(y); } } vector<int> buc[N + 1]; void mian() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) nei[i].clear(), buc[i].clear(), vis[i] = fa[i] = dep[i] = 0; while (m--) { int x, y; scanf( %d%d , &x, &y); nei[x].push_back(y); nei[y].push_back(x); } dep[1] = 1; dfs(); for (int i = 1; i <= n; i++) if (dep[i] >= n + 1 >> 1) { puts( PATH ); printf( %d n , dep[i]); while (i) printf( %d , i), i = fa[i]; puts( ); return; } else buc[dep[i]].push_back(i); puts( PAIRING ); int cnt = 0; for (int i = 1; i <= n; i++) cnt += buc[i].size() >> 1; printf( %d n , cnt); for (int i = 1; i <= n; i++) { for (int j = 0; j + 1 < buc[i].size(); j += 2) printf( %d %d n , buc[i][j], buc[i][j + 1]); } } int main() { int testnum; cin >> testnum; while (testnum--) mian(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32, 64, or 96 bit received data into a 128 bit wide
// FIFO. Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_128 (
input CLK,
input RST,
input [127:0] DATA_IN, // Incoming data
input [2:0] DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [127:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg [2:0] rPackedCount=0, _rPackedCount=0;
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [223:0] rPackedData=224'd0, _rPackedData=224'd0;
reg [127:0] rDataIn=128'd0, _rDataIn=128'd0;
reg [2:0] rDataInEn=0, _rDataInEn=0;
reg [127:0] rDataMasked=128'd0, _rDataMasked=128'd0;
reg [2:0] rDataMaskedEn=0, _rDataMaskedEn=0;
assign PACKED_DATA = rPackedData[127:0];
assign PACKED_WEN = rPackedCount[2];
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data until 4 words are available, then writes 4 words out.
wire [127:0] wMask = {128{1'b1}}<<(32*rDataInEn);
wire [127:0] wDataMasked = ~wMask & rDataIn;
always @ (posedge CLK) begin
rPackedCount <= #1 (RST ? 3'd0 : _rPackedCount);
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rPackedData <= #1 (RST ? 224'd0 : _rPackedData);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 3'd0 : _rDataInEn);
rDataMasked <= #1 _rDataMasked;
rDataMaskedEn <= #1 (RST ? 3'd0 : _rDataMaskedEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
_rDataMasked = wDataMasked;
_rDataMaskedEn = rDataInEn;
// Count what's in our buffer. When we reach 4 words, 4 words will be written
// out. If flush is requested, write out whatever remains.
if (rPackedFlush && (rPackedCount[1] | rPackedCount[0]))
_rPackedCount = 4;
else
_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[2], 2'd0};
// Shift data into and out of our buffer as we receive and write out data.
if (rDataMaskedEn != 3'd0)
_rPackedData = ((rPackedData>>(32*{rPackedCount[2], 2'd0})) | (rDataMasked<<(32*rPackedCount[1:0])));
else
_rPackedData = (rPackedData>>(32*{rPackedCount[2], 2'd0}));
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_SYMBOL_V
`define SKY130_FD_SC_HD__TAP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool f(int k, int n) { int s = k; while (k > 0) { s += k % 10; k /= 10; } return s == n; } int main() { int i, n; vector<int> ans; cin >> n; for (i = n - 100; i <= n + 100; ++i) { if (f(i, n)) { ans.push_back(i); } } cout << ans.size() << endl; for (i = 0; i < ans.size(); ++i) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; double ans[1024 * 1024], l, r, x[20], y[20], a[20], cosA[20], sinA[20], maxi; int main() { scanf( %d %lf %lf , &n, &l, &r); maxi = l; for (int i = 0; i < n; i++) { scanf( %lf %lf %lf , &x[i], &y[i], &a[i]); cosA[i] = cos(a[i] * 3.14159265359 / 180); sinA[i] = sin(a[i] * 3.14159265359 / 180); } int maxiMask = 1 << n; for (int i = 0; i < maxiMask; i++) ans[i] = l; for (int i = 0; i < maxiMask; i++) { double curAns = ans[i]; for (int j = 0; j < n; j++) { int newPotPos = 1 << j; if (!(newPotPos & i)) { double vx = curAns - x[j]; double vy = -y[j]; double nvx = vx * cosA[j] - vy * sinA[j]; double nvy = vx * sinA[j] + vy * cosA[j]; double pAns = x[j] - y[j] * nvx / nvy; int newPos = newPotPos ^ i; if (nvy >= 0.0) { ans[newPos] = r; maxi = r; } else { ans[newPos] = max(ans[newPos], pAns); maxi = max(maxi, ans[newPos]); } } } } maxi = min(maxi, r); printf( %.11lf , maxi - l); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INIT_SIZE_MAX = (1 << 29) + 10; const int INIT_SIZE_MIN = -(1 << 29) - 10; const int INIT_SIZE = 0; const int MAX = 8; const int DIR_SIZE = 12; const double PI = 3.1415926535897932384; template <class T, class U> void convert(T &t, U &u) { stringstream ss; ss << t; ss >> u; } int dfs(int pos, vector<vector<int> > &tb) { if (pos % 2) return pos; int half = pos / 2; int res = 0; for (int(i) = 0; (i) < (half); ++(i)) { bool f = true; for (int(j) = 0; (j) < (tb[0].size()); ++(j)) { if (tb[0 + i][j] != tb[(pos - 1) - i][j]) { f = false; break; } } if (f) { res = dfs(pos / 2, tb); } else { return pos; } } return res; } int main() { int h, w; cin >> h >> w; vector<vector<int> > tb(h, vector<int>(w, 0)); for (int(i) = 0; (i) < (h); ++(i)) for (int(j) = 0; (j) < (w); ++(j)) cin >> tb[i][j]; if (h % 2) { cout << h << endl; return 0; } int ans = 1 << 29; ans = min(ans, dfs(h, tb)); cout << ans << endl; } |
`default_nettype none
`timescale 1ns / 1ps
`include "ipl_config.vh"
// This core aims to implement a simple, reusable Wishbone B.4 compatible
// bus master. EMPHASIS ON SIMPLE -- pipelined mode can get pretty complex
// if you're not careful.
//
// Pipelined masters and slaves are really quite simple to implement overall.
// You just register the address, the bus command (read/write), and if writing,
// the data.
//
// Be careful about edge cases though. If you implement back-to-back cycles
// to two different peripherals, and your pipeline depth is different for each,
// you can get an out-of-order response which leads to read 1 getting read 2's
// data, or worse. Ultimately, since most masters are built to be generic,
// it's up to the intercon to prevent this from happening by forcing STALL_I
// on the master high until order can be preserved. But, this is getting into
// that complexity that I specifically wanted to avoid above. The simpler way
// of preventing this from happening is sticking to one, and only one, outstanding
// transaction per bus cycle: one strobe, one ack, in that order.
`include "asserts.vh"
module master_tb();
parameter ADDR_WIDTH = 16;
parameter AW = ADDR_WIDTH - 1;
reg [11:0] story_to;
reg clk_i, reset_i, fault_to;
wire [AW:0] adr_o;
wire cyc_o, stb_o, we_o;
reg ack_i;
reg dreq_i;
wire dack_o;
always begin
#5 clk_i <= ~clk_i;
end
master #(
.ADDR_WIDTH(ADDR_WIDTH)
) m(
.clk_i(clk_i),
.reset_i(reset_i),
.dreq_i(dreq_i),
.dack_o(dack_o),
.adr_o(adr_o),
.cyc_o(cyc_o),
.stb_o(stb_o),
.we_o(we_o),
.ack_i(ack_i)
);
`STANDARD_FAULT
`DEFASSERT(adr, AW, o)
`DEFASSERT0(cyc, o)
`DEFASSERT0(stb, o)
`DEFASSERT0(we, o)
`DEFASSERT0(dack, o)
initial begin
$dumpfile("master.vcd");
$dumpvars;
{ack_i, dreq_i, clk_i, reset_i, fault_to} <= 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
reset_i <= 0;
story_to <= 12'h000;
wait(~clk_i); wait(clk_i); #1;
assert_adr(0);
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_dack(0);
// Given CYC_O is negated,
// When DREQ_I is asserted,
// I want CYC_O to assert
// and a valid SIA address presented
// and a read command offered.
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
// Given CYC_O is asserted,
// If DREQ_I is (still) asserted,
// I want the STB_O to negate to avoid re-reading the same address before we're ready.
dreq_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
// Given CYC_O is asserted,
// and a read cycle is in progress,
// If ACK_I is asserted,
// I want the cycle to end, and the data latched for the subsequent write cycle.
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
// Given CYC_O is asserted during a write cycle,
// If unacknowledged,
// I want the cycle to continue as-is.
ack_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
// Given CYC_O is asserted during a write cycle,
// When acknowledged,
// I want the cycle to terminate.
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
// ATTENTION: This works on my simulator (iverilog).
// UNSURE if this will work on yours or on real hardware.
//
// When we peg DREQ_I and ACK_I to an asserted state,
// I want back-to-back transactions to occur in as few cycles as possible.
// N.B.: This means 2 cycles (one read, one write).
ack_i <= 0;
wait(~clk_i); wait(clk_i);
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
ack_i <= 1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
dreq_i <= 0;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i);
ack_i <= 0;
$display("@I Done.");
onFault;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100 * 1000 + 7, MAX_LOG = 20; int n, m; vector<int> adj[MAXN]; bool isPassed[MAXN]; int par[MAXN][MAX_LOG], cycleCnt[MAXN], h[MAXN]; void pre(int root) { isPassed[root] = true; for (auto nei : adj[root]) { if (!isPassed[nei]) { par[nei][0] = root; h[nei] = h[root] + 1; pre(nei); cycleCnt[root] = cycleCnt[root] + cycleCnt[nei]; } else if (par[root][0] != nei and h[nei] < h[root]) { cycleCnt[nei]--; cycleCnt[root]++; } } return; } int nanCyCnt[MAXN][MAX_LOG]; void dfs(int root, int lstRt) { par[root][0] = lstRt; if (lstRt != -1 and cycleCnt[root] == 0) nanCyCnt[root][0] = 1; for (int i = 1; i < MAX_LOG and h[root] >= (1 << i) and par[par[root][i - 1]][i - 1] != -1; ++i) { par[root][i] = par[par[root][i - 1]][i - 1]; nanCyCnt[root][i] = nanCyCnt[root][i - 1] + nanCyCnt[par[root][i - 1]][i - 1]; } isPassed[root] = true; for (auto nei : adj[root]) { if (!isPassed[nei]) { h[nei] = h[root] + 1; dfs(nei, root); } } return; } int lca(int v, int u) { int nancy = 0; if (h[v] > h[u]) swap(v, u); for (int i = 0; h[v] ^ h[u]; ++i) { if ((h[u] - h[v]) & (1 << i)) { nancy += nanCyCnt[u][i]; u = par[u][i]; } } if (v == u) return nancy; for (int i = MAX_LOG - 1; i >= 0; --i) { if (par[v][i] != par[u][i]) { nancy += (nanCyCnt[v][i] + nanCyCnt[u][i]); v = par[v][i], u = par[u][i]; } } return nancy + nanCyCnt[v][0] + nanCyCnt[u][0]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(par, -1, sizeof par); cin >> n >> m; for (int i = 0; i < m; ++i) { int v, u; cin >> v >> u, v--, u--; adj[v].push_back(u); adj[u].push_back(v); } memset(isPassed, 0, sizeof isPassed); pre(0); memset(isPassed, 0, sizeof isPassed); memset(h, 0, sizeof h); dfs(0, -1); int mercsNum; cin >> mercsNum; while (mercsNum--) { int sh, wa; cin >> wa >> sh, wa--, sh--; cout << lca(wa, sh) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int dp[505][505], dp2[505]; void solve() { int n; cin >> n; vector<int> a(n); for (auto &i : a) cin >> i; memset(dp, 0, sizeof(dp)); for (int i = 0; i < n; i++) dp[i][i] = a[i]; for (int i = 1; i < n; i++) { for (int j = i - 1; j >= 0; j--) { for (int k = i; k > j; k--) { if (dp[k][i] and dp[k][i] == dp[j][k - 1]) dp[j][i] = dp[k][i] + 1; } } } memset(dp2, INT_MAX, sizeof(dp2)); for (int i = 0; i <= n; i++) dp2[i] = i + 1; for (int i = 0; i < n; i++) { for (int j = 0; j <= i; j++) { if (dp[j][i]) { if (j == 0) dp2[i] = 1; else dp2[i] = min(dp2[i], dp2[j - 1] + 1); } } } cout << dp2[n - 1]; } int main() { int t; t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m = 1; vector<vector<int> > edge(105); int from[105]; int to[105]; bool bfs(int a, int b) { int use[105] = {0}; queue<int> q; q.push(a); use[a] = 1; while (!q.empty()) { int cur = q.front(); q.pop(); for (int i = 0; i < edge[cur].size(); i++) { if (edge[cur][i] == b) return true; if (use[edge[cur][i]] == 0) { q.push(edge[cur][i]); use[edge[cur][i]] = 1; } } } return false; } int main() { cin >> n; for (int i = 0; i < n; i++) { int t, x, y; cin >> t >> x >> y; if (t == 1) { from[m] = x; to[m] = y; for (int j = 1; j < m; j++) { if ((from[j] < x && x < to[j] && y >= to[j]) || (from[j] < y && y < to[j]) && x <= from[j]) { edge[j].push_back(m); edge[m].push_back(j); } else if (x <= from[j] && y >= to[j]) { edge[j].push_back(m); } } m++; } else { if (bfs(x, y)) cout << YES << endl; else cout << NO << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * f; } const int MAXN = 200010; const int INF = 1e9; const int Mod = 998244353LL; int mx; int N; int tms = 0; pair<int, int> sta[MAXN * 10 + 1]; int top; int Node[MAXN << 1], Next[MAXN << 1], Root[MAXN + 1], cnt; int deg[MAXN + 1]; inline void insert(int u, int v) { Node[++cnt] = v; Next[cnt] = Root[u]; Root[u] = cnt; return; } inline void solve(int k, int Fa, int val) { if (k != 1) --deg[k]; int last = deg[k]; sta[++top] = make_pair(k, tms); bool flag = 0; if (tms == mx && val != -1) { tms = max(val - last, 0); if (tms + last != val) flag = 1; sta[++top] = make_pair(k, tms); } for (int x = Root[k]; x; x = Next[x]) { int v = Node[x]; if (v == Fa) continue; ++tms; --last; solve(v, k, ((tms == val && flag) ? tms : tms - 1)); ++tms; sta[++top] = make_pair(k, tms); if (tms == mx && val != -1) { tms = max(val - last, 0); if (tms + last != val) flag = 1; sta[++top] = make_pair(k, tms); } } if (val != -1 && tms > val) { sta[++top] = make_pair(k, val); tms = val; } return; } int main() { N = read(); for (int i = 1; i < N; i++) { int u = read(), v = read(); insert(u, v); insert(v, u); ++deg[u]; ++deg[v]; } mx = 0; for (int i = 1; i <= N; i++) mx = max(mx, deg[i]); solve(1, 0, -1); printf( %d n , top); for (int i = 1; i <= top; i++) printf( %d %d n , sta[i].first, sta[i].second); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (!(n & 1)) cout << -1 << endl; else { for (int i = 0; i < n; i++) cout << i << ; cout << endl; for (int i = 0; i < n; i++) cout << i << ; cout << endl; for (int i = 0; i < n; i++) cout << 2 * i % n << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; char zf = 1; char ch = getchar(); while (ch != - && !isdigit(ch)) ch = getchar(); if (ch == - ) zf = -1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * zf; } void write(long long y) { if (y < 0) putchar( - ), y = -y; if (y > 9) write(y / 10); putchar(y % 10 + 48); } void writeln(const long long y) { write(y); putchar( n ); } int i, j, k, m, n, cnt; const double PI = acos(-1.0); struct node { int x, y; } a[3030]; double b[5030]; int main() { n = read(); for (register int i = 1; i <= n; i++) a[i].x = read(), a[i].y = read(); unsigned long long ans = 0; for (register int i = 1; i <= n; i++) { cnt = 0; for (register int j = 1; j <= n; j++) if (i != j) b[++cnt] = atan2(a[j].x - a[i].x, a[j].y - a[i].y); sort(b + 1, b + cnt + 1); for (register int i = cnt + 1; i <= 2 * cnt; i++) b[i] = b[i - cnt] + PI * 2; for (register int j = k = 1; j <= cnt; j++) { if (k < j) k = j; while (k < cnt * 2 && b[k + 1] - b[j] < PI) k++; int sum = k - j, sum2 = cnt - sum - 1; ans += (unsigned long long)sum * (sum - 1) * sum2 * (sum2 - 1) / 4; } } cout << ans / 2; return 0; } |
`default_nettype none
module module_scope_Example(o1, o2);
parameter [31:0] v1 = 10;
parameter [31:0] v2 = 20;
output [31:0] o1, o2;
assign module_scope_Example.o1 = module_scope_Example.v1;
assign module_scope_Example.o2 = module_scope_Example.v2;
endmodule
module module_scope_ExampleLong(o1, o2);
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
output [31:0] o1, o2;
assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
endmodule
module module_scope_top(
output [31:0] a1, a2, b1, b2, c1, c2,
output [31:0] d1, d2, e1, e2, f1, f2
);
module_scope_Example a(a1, a2);
module_scope_Example #(1) b(b1, b2);
module_scope_Example #(1, 2) c(c1, c2);
module_scope_ExampleLong d(d1, d2);
module_scope_ExampleLong #(1) e(e1, e2);
module_scope_ExampleLong #(1, 2) f(f1, f2);
endmodule
|
#include <bits/stdc++.h> using namespace std; char in[100000 + 1]; int main() { vector<array<int, 4> > cur, nex; cur.push_back(array<int, 4>{{}}); int n; scanf( %d , &n); scanf( %s , in); for (int i = 0; i < n; i++) { int p = -1; switch (in[i]) { case G : p = 0; break; case H : p = 1; break; case R : p = 2; break; case S : p = 3; break; } if (p >= 0) { for (int i = 0; i < cur.size(); i++) { cur[i][p]++; } continue; } nex.clear(); for (auto a : cur) { int m = a[0]; for (int i = 1; i < 4; i++) { m = min(m, a[i]); } for (int i = 0; i < 4; i++) { if (a[i] == m) { nex.push_back(a); nex.back()[i]++; } } } sort(nex.begin(), nex.end()); nex.resize(unique(nex.begin(), nex.end()) - nex.begin()); nex.swap(cur); } const char* str[] = { Gryffindor , Hufflepuff , Ravenclaw , Slytherin }; for (int i = 0; i < 4; i++) { for (auto a : cur) { int m = a[0]; for (int i = 1; i < 4; i++) { m = min(m, a[i]); } if (a[i] == m) { puts(str[i]); break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s, k; cin >> s; map<string, int> m; for (int i = 0; i < s.size() - 9; i++) { if (s[i] != - && s[i + 1] != - && s[i + 2] == - && s[i + 3] != - && s[i + 4] != - && s[i + 5] == - && s[i + 6] != - && s[i + 7] != - && s[i + 8] != - && s[i + 9] != - ) { if (s[i + 6] == 2 && s[i + 7] == 0 && s[i + 8] == 1 && s[i + 9] >= 3 && s[i + 9] <= 5 ) { if ((s[i + 3] == 0 && (s[i + 4] == 1 || s[i + 4] == 8 || s[i + 4] == 7 || s[i + 4] == 5 || s[i + 4] == 3 )) || (s[i + 3] == 1 && (s[i + 4] == 0 || s[i + 4] == 2 ))) { if ((s[i] == 0 && s[i + 1] > 0 ) || (s[i] < 3 && s[i] > 0 ) || (s[i] == 3 && (s[i + 1] == 1 || s[i + 1] == 0 ))) { k = s[i]; k += s[i + 1]; k += s[i + 2]; k += s[i + 3]; k += s[i + 4]; k += s[i + 5]; k += s[i + 6]; k += s[i + 7]; k += s[i + 8]; k += s[i + 9]; m[k]++; } } else if ((s[i + 3] == 0 && (s[i + 4] == 4 || s[i + 4] == 6 || s[i + 4] == 9 )) || (s[i + 3] == 1 && (s[i + 4] == 1 ))) { if ((s[i] == 0 && s[i + 1] > 0 ) || (s[i] < 3 && s[i] > 0 ) || (s[i] == 3 && (s[i + 1] == 0 ))) { k = s[i]; k += s[i + 1]; k += s[i + 2]; k += s[i + 3]; k += s[i + 4]; k += s[i + 5]; k += s[i + 6]; k += s[i + 7]; k += s[i + 8]; k += s[i + 9]; m[k]++; } } else if (s[i + 3] == 0 && s[i + 4] == 2 ) { if ((s[i] == 0 && s[i + 1] > 0 ) || (s[i] < 2 && s[i] > 0 ) || (s[i] == 2 && (s[i + 1] >= 0 && s[i + 1] <= 8 ))) { k = s[i]; k += s[i + 1]; k += s[i + 2]; k += s[i + 3]; k += s[i + 4]; k += s[i + 5]; k += s[i + 6]; k += s[i + 7]; k += s[i + 8]; k += s[i + 9]; m[k]++; } } } } } map<string, int>::iterator it = m.begin(); int maxx = -1; for (; it != m.end(); it++) { if (maxx < it->second) { maxx = it->second; s = it->first; } } cout << s; } |
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
// file: Clock70HMz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock70HMz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70HMz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, V, M; int Size[310], Final[310], T[310]; vector<int> G[310]; vector<pair<pair<int, int>, int> > ANS; int source, sink, flow; void FindSource(int node) { if (Size[node] > Final[node]) { source = node; return; } for (vector<int>::iterator it = G[node].begin(); it != G[node].end(); ++it) if (T[*it] == 0 && *it != sink) { T[*it] = node; FindSource(*it); } } void Transfer(int source, int sink, int flow) { Size[source] -= flow; Size[sink] += flow; ANS.push_back(make_pair(make_pair(source, sink), flow)); } void Push(int node) { int next = T[node]; if (next == sink) { Transfer(node, sink, flow); return; } int add = 0; if (Size[next] < flow) { add = flow - Size[next]; Transfer(node, next, add); } Push(next); Transfer(node, next, flow - add); } void Fill(int node) { sink = node; while (Size[node] < Final[node]) { source = 0; memset(T, 0, sizeof(T)); FindSource(node); if (source == 0) break; flow = min(Size[source] - Final[source], Final[sink] - Size[sink]); Push(source); } } int main() { cin >> N >> V >> M; for (int i = 1; i <= N; i++) cin >> Size[i]; for (int i = 1; i <= N; i++) cin >> Final[i]; for (int i = 1; i <= M; i++) { int a, b; cin >> a >> b; G[a].push_back(b); G[b].push_back(a); } for (int i = 1; i <= N; i++) if (Size[i] < Final[i]) Fill(i); bool OK = 1; for (int i = 1; i <= N; i++) if (Size[i] != Final[i]) OK = 0; if (OK == 0) cout << NO << n ; else { cout << ANS.size() << n ; for (vector<pair<pair<int, int>, int> >::iterator it = ANS.begin(); it != ANS.end(); ++it) cout << (it->first).first << << (it->first).second << << (it->second) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5050; const int inf = 0x37373737; int L[N], R[N], size[N], tot, n, i, a, b, cnt, j, k; int d[N], root; int dp[N][N]; vector<pair<int, int> > vec[N]; vector<int> e[N]; void dfs(int x, int fa) { int i, j, k; if (e[x].size() == 1) size[x] = 1; for (i = 0; i < e[x].size(); i++) if (e[x][i] != fa) { dfs(e[x][i], x); for (j = size[x]; j >= 0; j--) for (k = 0; k <= size[e[x][i]]; k++) dp[x][j + k] = min(dp[x][j + k], dp[x][j] + dp[e[x][i]][k]); size[x] += size[e[x][i]]; } for (i = 0; i <= size[x]; i++) dp[x][i] = min(dp[x][i], dp[x][size[x] - i] + 1); } int main() { scanf( %d , &n); for (i = 1; i < n; i++) { scanf( %d%d , &a, &b); e[a].push_back(b); e[b].push_back(a); d[a]++; d[b]++; } if (n == 2) { printf( 1 ); return 0; } for (i = 1; i <= n; i++) if (d[i] != 1) break; root = i; for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) dp[i][j] = inf; dfs(root, 0); printf( %d n , dp[root][size[root] / 2]); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O22A_FUNCTIONAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_FUNCTIONAL_V |
`timescale 1ns/1ps
module dpram_xlx #(
parameter ADDRWIDTH = 4,
parameter DATAWIDTH = 8,
parameter [ADDRWIDTH:0] DEPTH = 16
) (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [ADDRWIDTH-1 : 0] addra;
input [DATAWIDTH-1 : 0] dina;
output[DATAWIDTH-1 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [ADDRWIDTH-1 : 0] addrb;
input [DATAWIDTH-1 : 0] dinb;
output[DATAWIDTH-1 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(ADDRWIDTH),
.C_ADDRB_WIDTH(ADDRWIDTH),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(DEPTH),
.C_READ_DEPTH_B(DEPTH),
.C_READ_WIDTH_A(DATAWIDTH),
.C_READ_WIDTH_B(DATAWIDTH),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(DEPTH),
.C_WRITE_DEPTH_B(DEPTH),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(DATAWIDTH),
.C_WRITE_WIDTH_B(DATAWIDTH),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of dpram_xlx is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t, n, i, x; cin >> t; while (t--) { cin >> n; i = n - 1; x = n; cout << 2 << endl; while (i != 0) { cout << i << << x << endl; x = ceil((i + x) / 2.0); i--; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long f(string s, long long m) { map<char, long long> a; map<char, long long>::iterator ii; long long i; for (i = 0; i < s.size(); i++) { a[s[i]]++; } long long best = 0; for (ii = a.begin(); ii != a.end(); ii++) best = max(best, ii->second); long long p = s.size(); if (best == p && m == 1) return p - 1; return min(p, best + m); } int main() { string s1, s2, s3; long long n; cin >> n; cin >> s1 >> s2 >> s3; if (f(s1, n) > f(s2, n) && f(s1, n) > f(s3, n)) { cout << Kuro ; return 0; } if (f(s2, n) > f(s1, n) && f(s2, n) > f(s3, n)) { cout << Shiro ; return 0; } if (f(s3, n) > f(s1, n) && f(s3, n) > f(s2, n)) { cout << Katie ; return 0; } cout << Draw ; return 0; } |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel Buffers
* =======================
*
* Instantiates 'N' FIFOs in parallel, if 'push' is asserted
* data_in is sent to FIFO[vc_id].
*
* The output is determined by an external 'select' input.
*
* if 'pop' is asserted by the end of the clock cycle, the
* FIFO that was read (indicated by 'select') recieves a
* pop command.
*
* - flags[] provides access to all FIFO status flags.
* - output_port[] provides access to 'output_port' field of flits at head of FIFOs
*
* Assumptions:
* - 'vc_id' is binary encoded (select is one-hot) //and 'select' are binary encoded.
*
*/
module NW_vc_buffers (push, pop, data_in, vc_id, select,
data_out, output_port, data_in_reg,
flags, buf_finished_empty,
head_is_tail, flit_buffer_out,
clk, rst_n);
`include "NW_functions.v"
// length of VC FIFOs
parameter size = 3;
// number of virtual channels
parameter n = 4;
// what does each FIFO hold?
//parameter type fifo_elements_t = flit_t;
// optimize FIFO parameters for different fields of flit
parameter optimize_fifo_fields = 0;
// export output of each VC buffer
parameter output_all_head_flits = 0;
input push;
input [n-1:0] pop;
input fifo_elements_t data_in;
input [clogb2(n)-1:0] vc_id;
// input [clogb2(n)-1:0] select;
input [n-1:0] select;
output fifo_elements_t data_out;
output fifov_flags_t flags [n-1:0];
output output_port_t output_port [n-1:0];
output flit_t data_in_reg;
output fifo_elements_t flit_buffer_out [n-1:0];
output [n-1:0] head_is_tail;
// at the end of the last clock cycle was vc_buffer[i] empty?
// - i.e. is the next flit entering an empty FIFO
// used for various things, e.g. abort detection
output [n-1:0] buf_finished_empty;
input clk, rst_n;
// logic [clogb2(n)-1:0] select_bin;
fifo_elements_t sel_fifo_out;
// single input register
fifo_elements_t in_reg;
// fifo outputs
fifo_elements_t fifo_out [n-1:0];
// fifo push/pop control
logic [n-1:0] push_fifo, pop_fifo;
// need to bypass FIFO and output contents of input register?
logic [n-1:0] fifo_bypass;
logic [n-1:0] fifo_bypass2;
output_port_t op_fifo_out [n-1:0];
control_flit_t control_fifo_out [n-1:0];
genvar i;
integer j;
assign data_in_reg = in_reg;
assign buf_finished_empty = fifo_bypass;
// assign select_bin = vc_index_t'(oh2bin(select));
generate
for (i=0; i<n; i++) begin:vcbufs
if (optimize_fifo_fields) begin
//
// use multiple FIFOs for different fields of flit so there
// parameters can be optimized individually. Allows us to
// move logic from start to end of clock cycle and vice-versa -
// depending on what is on critical path.
//
//
// break down into control and data fields
//
// *** CONTROL FIFO ***
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(control_flit_t),
.size(size),
.output_reg(0),
.input_reg(1) // must be 1 - assume external input reg.
) vc_fifo_c
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg.control),
.data_out(control_fifo_out[i]),
.flags(flags[i]),
.clk, .rst_n);
// *** OUTPUT PORT REQUEST ONLY ***
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(output_port_t),
.size(size),
.output_reg(1),
.input_reg(1) // must be 1 - assume external input reg.
) vc_fifo_op
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg.control.output_port),
.data_out(op_fifo_out[i]),
// .flags(flags[i]),
.clk, .rst_n);
always_comb
begin
fifo_out[i].control = control_fifo_out[i];
fifo_out[i].control.output_port = op_fifo_out[i];
end
// *** DATA FIFO ***
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(data_t),
.size(size),
.output_reg(0), // remove FIFO output register ****
.input_reg(1) // must be 1 - assume external input reg.
) vc_fifo_d
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg.data),
.data_out(fifo_out[i].data),
// .flags(flags[i]), only need one set of flags (obviously identical to control FIFO's)
.clk, .rst_n);
`ifdef DEBUG
// need FIFO for debug too
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(debug_flit_t),
.size(size),
.output_reg(1),
.input_reg(1)
) vc_fifo
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
//.data_in(in_reg.debug),
//.data_out(fifo_out[i].debug),
// .flags(flags[i]),
.clk, .rst_n);
`endif
end else begin
// **********************************
// SINGLE FIFO holds complete flit
// **********************************
NW_fifo_v #(.init_fifo_contents(0),
//.fifo_elements_t(fifo_elements_t),
.size(size),
.output_reg(0),
.input_reg(1)
) vc_fifo
(.push(push_fifo[i]),
.pop(pop_fifo[i]),
.data_in(in_reg),
.data_out(fifo_out[i]),
.flags(flags[i]),
.clk, .rst_n);
end
always@(posedge clk) begin
if (!rst_n) begin
fifo_bypass[i] <= 1'b1;
fifo_bypass2[i] <= 1'b1; // duplicate
end else begin
fifo_bypass[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);
fifo_bypass2[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]); // duplicate
end
end
assign push_fifo[i] = push & (vc_id==i);
assign pop_fifo[i] = pop[i]; //pop & (select==i);
assign head_is_tail[i] = fifo_out[i].control.tail; // && !flags[i].empty;
// we need to know which output port is required by all packets, in order to make
// virtual-channel and switch allocation requests.
assign output_port[i] =
fifo_bypass2[i] ? in_reg.control.output_port : fifo_out[i].control.output_port;
end
endgenerate
//
// assign data_out = (fifo_bypass[select]) ? in_reg : fifo_out[select];
//
NW_mux_oh_select #( .n(n))
fifosel (.data_in(fifo_out), .select(select), .data_out(sel_fifo_out));
assign sel_fifo_bypass = |(fifo_bypass & select);
assign data_out = sel_fifo_bypass ? in_reg : sel_fifo_out; //fifo_out[select_bin];
//
// some architectures require access to head of all VC buffers
//
generate
if (output_all_head_flits) begin
for (i=0; i<n; i++) begin:allvcs
assign flit_buffer_out[i] = (fifo_bypass[i]) ? in_reg : fifo_out[i];
end
end
endgenerate
//
// in_reg
//
always@(posedge clk) begin
if (!rst_n) begin
in_reg.control.valid <= 1'b0;
in_reg.control.tail <= 1'b1;
in_reg.control.output_port <='0;
end else begin
if (push) begin
in_reg <= data_in;
end else begin
in_reg.control.valid<=1'b0;
in_reg.control.output_port<='0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool comp[30000]; int P[30000]; int seive(int n, int* P) { int p, q, K = 0; comp[1] = true; char even = 1; for (p = 2; p * p <= n; p += 2) { if (!comp[p]) { for (q = p * p; q <= n; q += p * (2 - even)) comp[q] = true; } if (p == 2) --p, even = 0; } for (int i = (1); i <= (n); ++i) if (!comp[i]) P[K++] = i; return K; } int muls[30000]; int has[30000]; int main() { int K; cin >> K; int lim = 2 * K * K; int least = (K + 1) / 2; vector<int> ans; ans.push_back(1); int max_added = 0; int L = seive(5 * K, P); for (int l = 0; l < L && ((int)ans.size()) < K; ++l) { for (int l2 = 0; l2 < (l); ++l2) { has[l2] = 0; for (int i = 0; i < (((int)ans.size())); ++i) if (!(ans[i] % P[l2])) ++has[l2]; } int p = P[l]; set<int> tmp; for (long long q = p; q <= lim; q *= p) { for (int i = 0; i < ((int)ans.size()) && (ans[i] % p); ++i) { long long new_num = 1ll * q * ans[i]; if (new_num <= lim) { tmp.insert(new_num); } } } set<int>::iterator it = tmp.begin(); for (int i = 0; it != tmp.end() && i < least; ++it) { int v = *it; assert(!(v % p)); for (int j = 0; j < (l); ++j) if (!(v % P[j])) ++has[j]; if (((int)ans.size()) < K) { ans.push_back(v); } else { bool found = false; for (int j = (K - 1); j >= (0); --j) { int w = ans[j]; bool good = true; for (int h = (0); h <= (l); ++h) { int& pr = P[h]; if (!(w % pr)) { if (has[h] <= least) { good = false; break; } } } if (good) { for (int h = (0); h <= (l - 1); ++h) { int& pr = P[h]; if (!(w % pr)) { has[h]--; } } assert(ans[j] % p); ans[j] = v; found = true; break; } } assert(found); assert(ans.size() == K); } ++i; } assert(((int)ans.size()) <= K); } assert(((int)ans.size()) == K); sort(ans.begin(), ans.end()); ans.erase(unique(ans.begin(), ans.end()), ans.end()); assert(((int)ans.size()) == K); for (int l = 0; l < (L); ++l) { int cnt = 0; for (int i = 0; i < ((int)ans.size()); ++i) if (!(ans[i] % P[l])) { ++cnt; } assert(cnt == 0 || cnt >= least); } for (int i = 0; i < (((int)ans.size())); ++i) assert(ans[i] <= lim); for (int i = 0; i < (K); ++i) { if (i > 0) printf( ); printf( %d , ans[i]); } printf( n ); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_PP_V |
// Filename: sevensegmentdecoder_assign.v
// Author: Danny Dutton
// Date: 03/03/15
// Version: 1
// Description: Decode 4-bit input and drive a seven segment using assignment
module sevensegdecoder_always(digit, drivers);
input [3:0] digit;
output [6:0] drivers; // Take a to be the MSB of the vector.
reg [6:0] drivers;
always @(digit) begin
if(digit == 4'h0)
begin
drivers = 7'b0000001;
end
if(digit == 4'h1)
begin
drivers = 7'b1001111;
end
if(digit == 4'h2)
begin
drivers = 7'b0010010;
end
if(digit == 4'h3)
begin
drivers = 7'b0000110;
end
if(digit == 4'h4)
begin
drivers = 7'b1001100;
end
if(digit == 4'h5)
begin
drivers = 7'b0100100;
end
if(digit == 4'h6)
begin
drivers = 7'b0100000;
end
if(digit == 4'h7)
begin
drivers = 7'b0001101;
end
if(digit == 4'h8)
begin
drivers = 7'b0000000;
end
if(digit == 4'h9)
begin
drivers = 7'b0000100;
end
if(digit == 4'hA)
begin
drivers = 7'b0001000;
end
if(digit == 4'hB)
begin
drivers = 7'b1100000;
end
if(digit == 4'hC)
begin
drivers = 7'b0110001;
end
if(digit == 4'hD)
begin
drivers = 7'b1000010;
end
if(digit == 4'hE)
begin
drivers = 7'b0110000;
end
if(digit == 4'hF)
begin
drivers = 7'b0111000;
end
end
endmodule |
`include "bsg_defines.v"
module bsg_8b10b_shift_decoder
( input clk_i
, input data_i
, output logic [7:0] data_o
, output logic k_o
, output logic v_o
, output logic frame_align_o
);
// 8b10b decode running disparity and error signals
wire decode_rd_r, decode_rd_n, decode_rd_lo;
wire decode_data_err_lo;
wire decode_rd_err_lo;
// Signal if a RD- or RD+ comma code has been shifted in
wire comma_code_rdn, comma_code_rdp;
// Signal that indicates that a frame (10b) have arrived
wire frame_recv;
// Input Shift Register
//======================
// We need to use a shift register (rather than a SIPO) becuase we don't have
// reset and we need to detect frame alignments. 8b10b shifts LSB first, so
// don't change the shift direction!
logic [9:0] shift_reg_r;
always_ff @(posedge clk_i)
begin
shift_reg_r[8:0] <= shift_reg_r[9:1];
shift_reg_r[9] <= data_i;
end
// Comma Code Detection and Frame Alignment
//==========================================
// We are using a very simple comma code detection to reduce the amount of
// logic. This means that use of K.28.7 is not allowed. Sending a K.28.7's
// to this channel will likely cause frame misalignment.
assign comma_code_rdn = (shift_reg_r[6:0] == 7'b1111100); // Comma code detect (sender was RD-, now RD+)
assign comma_code_rdp = (shift_reg_r[6:0] == 7'b0000011); // Comma code detect (sender was RD+, now RD-)
assign frame_align_o = (comma_code_rdn | comma_code_rdp);
// Frame Counter
//===============
// Keeps track of where in the 10b frame we are. Resets when a comma code is
// detected to realign the frame.
bsg_counter_overflow_en #( .max_val_p(9), .init_val_p(0) )
frame_counter
( .clk_i ( clk_i )
, .reset_i ( frame_align_o )
, .en_i ( 1'b1 )
, .count_o ()
, .overflow_o( frame_recv )
);
// 8b/10b Decoder
//================
// The 8b10b decoder has a running disparity (RD) which normally starts at
// -1. However on boot, the RD register is unknown and there is no reset.
// Therefore, we use the comma code to determine what our starting disparity
// should be. If the comma code was a RD- encoding, then we set our disparity
// to RD+ and vice-versa. This is because the allowed comma codes (K.28.1 and
// K.28.5) will swap the running disparity.
assign decode_rd_n = frame_align_o ? comma_code_rdn : (v_o ? decode_rd_lo : decode_rd_r);
bsg_dff #(.width_p($bits(decode_rd_r)))
decode_rd_reg
( .clk_i ( clk_i )
, .data_i( decode_rd_n )
, .data_o( decode_rd_r )
);
bsg_8b10b_decode_comb
decode_8b10b
( .data_i ( shift_reg_r )
, .rd_i ( decode_rd_r )
, .data_o ( data_o )
, .k_o ( k_o )
, .rd_o ( decode_rd_lo )
, .data_err_o( decode_data_err_lo )
, .rd_err_o ( decode_rd_err_lo )
);
assign v_o = frame_recv & ~(decode_data_err_lo | decode_rd_err_lo);
// Error Detection
//=================
// Display an error if we ever see a K.28.7 code. This code is not allowed
// with the given comma code detection logic.
// synopsys translate_off
always_ff @(negedge clk_i)
begin
assert (shift_reg_r !== 10'b0001_111100 && shift_reg_r !== 10'b1110_000011) else
$display("## ERROR (%M) - K.28.7 Code Detected!");
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char a, b; int A, B; cin >> a >> A; cin >> b >> B; int chess[9][9] = {0}; for (int i = 1; i < 9; i++) { chess[i][A] = 1; } for (int i = 1; i < 9; i++) { chess[a - 96][i] = 1; } if (b - 98 > 0) { if (B - 1 > 0) { chess[b - 98][B - 1] = 1; } if (B + 1 < 9) { chess[b - 98][B + 1] = 1; } } if (b - 94 < 9) { if (B - 1 > 0) { chess[b - 94][B - 1] = 1; } if (B + 1 < 9) { chess[b - 94][B + 1] = 1; } } if (B - 2 > 0) { if (b - 97 > 0) { chess[b - 97][B - 2] = 1; } if (b - 95 < 9) { chess[b - 95][B - 2] = 1; } } if (B + 2 < 9) { if (b - 97 > 0) { chess[b - 97][B + 2] = 1; } if (b - 95 < 9) { chess[b - 95][B + 2] = 1; } } if (a - 97 > 0) { if (A + 2 < 9) { chess[a - 97][A + 2] = 1; } if (A - 2 > 0) { chess[a - 97][A - 2] = 1; } } if (a - 95 < 9) { if (A + 2 < 9) { chess[a - 95][A + 2] = 1; } if (A - 2 > 0) { chess[a - 95][A - 2] = 1; } } if (A - 1 > 0) { if (a - 94 < 9) { chess[a - 94][A - 1] = 1; } if (a - 98 > 0) { chess[a - 98][A - 1] = 1; } } if (A + 1 < 9) { if (a - 94 < 9) { chess[a - 94][A + 1] = 1; } if (a - 98 > 0) { chess[a - 98][A + 1] = 1; } } chess[b - 96][B] = 1; int w = 0; for (int i = 1; i < 9; i++) { for (int j = 1; j < 9; j++) { if (chess[i][j] == 0) { w++; } } } cout << w; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3010; const int MOD = 1000000007; int n, m; long long f[MAXN][MAXN], ans1, ans2, ans3, ans4; char a[MAXN][MAXN]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , a[i] + 1); if (a[1][2] == . ) f[1][2] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (i == 1 && j == 2) continue; if (a[i][j] == . ) f[i][j] = (f[i - 1][j] + f[i][j - 1]) % MOD; } ans1 = f[n - 1][m]; memset(f, 0, sizeof(f)); if (a[2][1] == . ) f[2][1] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (i == 2 && j == 1) continue; if (a[i][j] == . ) f[i][j] = (f[i - 1][j] + f[i][j - 1]) % MOD; } ans2 = f[n][m - 1]; memset(f, 0, sizeof(f)); if (a[1][2] == . ) f[1][2] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (i == 1 && j == 2) continue; if (a[i][j] == . ) f[i][j] = (f[i - 1][j] + f[i][j - 1]) % MOD; } ans3 = f[n][m - 1]; memset(f, 0, sizeof(f)); if (a[2][1] == . ) f[2][1] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (i == 2 && j == 1) continue; if (a[i][j] == . ) f[i][j] = (f[i - 1][j] + f[i][j - 1]) % MOD; } ans4 = f[n - 1][m]; memset(f, 0, sizeof(f)); printf( %I64d n , ((ans1 * ans2) % MOD - (ans3 * ans4) % MOD + MOD) % MOD); return 0; } |
/**
* testbench.v
*
* mul_32 test
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p*2;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_li;
logic [width_p-1:0] a_li;
logic [width_p-1:0] b_li;
logic ready_lo;
logic v_lo;
logic yumi_li;
logic [width_p-1:0] z_lo;
logic unimplemented;
logic invalid;
logic overflow;
logic underflow;
bsg_fpu_mul #(
.e_p(8)
,.m_p(23)
) dut (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_li)
,.a_i(a_li)
,.b_i(b_li)
,.ready_o(ready_lo)
,.v_o(v_lo)
,.z_o(z_lo)
,.unimplemented_o(unimplemented)
,.invalid_o(invalid)
,.overflow_o(overflow)
,.underflow_o(underflow)
,.yumi_i(yumi_li)
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_lo)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(v_li)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign yumi_li = v_lo & tr_ready_lo;
assign tr_yumi_li = v_li & ready_lo;
assign {sub_li, a_li, b_li} = tr_data_lo;
assign tr_data_li = {
{ring_width_p-width_p-4{1'b0}},
unimplemented,
invalid,
overflow,
underflow,
z_lo
};
initial begin
wait(done_lo);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const int maxm = 1e3 + 5; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; int a[maxn], ans[maxn], l[maxn][6], r[maxn][6]; inline void solve() { int n; scanf( %d , &n); for (int i = 1; i < n + 1; i++) scanf( %d , &a[i]); memset(l, -1, sizeof l); memset(r, -1, sizeof r); if (a[1] > 1) { puts( -1 ); exit(0); } l[1][1] = r[1][1] = 1; for (int i = 2; i < n + 1; i++) { for (int j = 2; j < 5 + 1; j++) { if (l[i - 1][j - 1] != -1) { l[i][j] = l[i - 1][j - 1]; r[i][j] = r[i - 1][j - 1]; } } for (int j = 2; j < 5 + 1; j++) { if (l[i - 1][j] != -1) { if (l[i][1] == -1) l[i][1] = inf; l[i][1] = min(l[i][1], l[i - 1][j] + 1); r[i][1] = max(r[i][1], r[i - 1][j] + 1); } } if (a[i]) { for (int j = 1; j < 5 + 1; j++) { if (l[i][j] != -1) { if (l[i][j] <= a[i] && a[i] <= r[i][j]) l[i][j] = r[i][j] = a[i]; else l[i][j] = r[i][j] = -1; } else r[i][j] = -1; } } bool ok = 0; for (int j = 1; j < 5 + 1; j++) { if (l[i][j] <= r[i][j] && l[i][j] != -1) { ok = 1; break; } } if (!ok) { puts( -1 ); exit(0); } } int up = 0, j = 2; for (int i = 2; i < 5 + 1; i++) { if (l[n][i] <= r[n][i] && l[n][i] != -1) { if (r[n][i] > up) { up = r[n][i]; j = i; } } } if (up == 0) { puts( -1 ); exit(0); } printf( %d n , up); int m = n; while (m) { for (int i = m - j; i < m + 1; i++) ans[i] = up; m -= j; up--; for (int i = 2; i < 5 + 1; i++) { if (l[m][i] <= up && up <= r[m][i]) j = i; } } for (int i = 1; i < n + 1; i++) { if (i == 1) printf( %d , ans[i]); else printf( %d , ans[i]); } puts( ); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> const int N = 1e3 + 10; using namespace std; int a[N], b[N], c[N]; char str1[N], str2[N], str3[N]; int main() { int tc; cin >> tc; while (tc--) { long long n, k, sum{0}, suma{0}, sumb{0}; cin >> n >> k; for (int i = 0; i < n; ++i) { cin >> a[i]; suma += a[i]; } for (int i = 0; i < n; ++i) { cin >> b[i]; sumb += b[i]; } if (k > 0) { for (int i = 0; i < n; ++i) { for (int j = i; j < n - 1; ++j) { if (a[i] >= a[j + 1]) swap(a[i], a[j + 1]); if (b[i] <= b[j + 1]) swap(b[i], b[j + 1]); } } for (int i = 0; i < k; ++i) { if (a[i] < b[i]) swap(a[i], b[i]); } for (int i = 0; i < n; ++i) { sum += a[i]; } cout << sum << n ; } else cout << suma << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Module supplies
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepb ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
and and0 (and0_out_X, sleepb, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_V |
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
/*
* Pointer-based fifo
*
* Note: Due to the output register in the dual port ram,
* the output will be delayed by one clock cycle following
* the unload enable.
*/
module ptrfifo #(
// Default parameters. These can be overrriden
parameter WIDTH = 64,
parameter DEPTH = 6
) (
//
input wire clk,
input wire rstn,
input wire loaden,
input wire unloaden,
input wire [WIDTH-1: 0] datain,
output wire empty,
output wire full,
output wire [WIDTH-1: 0] dataout,
output wire [DEPTH-1: 0] itemsinfifo
);
wire [DEPTH-1: 0] inptr;
wire [DEPTH-1: 0] outptr;
wire [WIDTH-1: 0] a_dataout;
wire [WIDTH-1: 0] b_datain = 0;
wire [DEPTH-1: 0] itemsinfifo_int;
wire qual_loaden;
wire qual_unloaden;
reg empty_int;
reg full_int;
// Instantiate input pointer counter
counter ipctr(
.clk(clk),
.up(qual_loaden),
.down(1'b0),
.rstn(rstn),
.count(inptr)
);
// Instantiate output pointer counter
counter opctr(
.clk(clk),
.up(qual_unloaden),
.down(1'b0),
.rstn(rstn),
.count(outptr)
);
// Instantiate the accounting counter
counter accounting(
.clk(clk),
.up(qual_loaden),
.down(qual_unloaden),
.rstn(rstn),
.count(itemsinfifo_int)
);
// Instantiate dual port ram
dualportram dpram(
.clk_a(clk),
.we_a(qual_loaden),
.addr_a(inptr),
.din_a(datain),
.dout_a(a_dataout), // Park the output bits, we don't need 'em
.clk_b(clk),
.we_b(1'b0), // Never going to write on this side
.addr_b(outptr),
.din_b(b_datain), // These will always be 0
.dout_b(dataout)
);
// Set the parameters for the dual port ram, pointer and accounting counters
defparam dpram.DEPTH = DEPTH;
defparam dpram.WIDTH = WIDTH;
defparam ipctr.WIDTH = DEPTH;
defparam opctr.WIDTH = DEPTH;
defparam accounting.WIDTH = DEPTH;
assign empty = empty_int;
assign full = full_int;
assign qual_loaden = loaden & ~full_int;
assign qual_unloaden = unloaden & ~empty_int;
assign itemsinfifo = itemsinfifo_int;
// Derive empty and full flags from the accounting counter
always @(*) begin
empty_int <= 0;
full_int <= 0;
if(itemsinfifo_int == 0) begin
empty_int <= 1;
end
if(itemsinfifo_int == (2**DEPTH) - 1) begin
full_int <= 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, q, x; map<int, int> M; map<int, int>::iterator it; int main() { scanf( %d %d , &n, &k); for (int i = (1); i <= (n); i++) { int a; scanf( %d , &a); for (int j = (0); j <= (k); j++) { if (!M.count(a * j)) M[a * j] = j; else M[a * j] = min(M[a * j], j); } } scanf( %d , &q); while (q--) { scanf( %d , &x); int res = 99; for (it = M.begin(); it != M.end(); it++) { int v = (*it).first, c = (*it).second; if (M.count(x - v)) { int cc = M[x - v]; res = min(res, c + cc); } } if (res > k) res = -1; printf( %d n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, ans; string s; cin >> s; x = s.size(); for (int i = 1; i < x; i++) { if (s[i] == 1 ) { x++; break; } } cout << x / 2 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int N, M; const int MAX = 1e6; vector<int> edges[MAX]; int indeg[MAX]; vector<int> source; map<int, int> sink; int reachable[20]; const int BITMAX = 1 << 20; int dp[BITMAX]; void dfs(int start, int i) { if (sink.count(i)) { reachable[start] |= sink[i]; } else { for (auto j : edges[i]) dfs(start, j); } } int main() { int i, j, k; cin >> N >> M; for (i = 0; i < M; i++) { int x, y; scanf( %d %d , &x, &y); edges[x - 1].push_back(y - 1); indeg[y - 1]++; } int num = 1; for (i = 0; i < N; i++) { if (indeg[i] == 0) source.push_back(i); if (edges[i].size() == 0) { sink[i] = num; num *= 2; } } int sz = source.size(); for (i = 0; i < sz; i++) dfs(i, source[i]); int bitmax = 1 << sz; for (i = 1; i < bitmax; i++) { bool updated = false; int in = 0; for (j = 0; j < sz; j++) { if ((i >> j) & 1) { in++; if (!updated) { dp[i] = dp[i - (1 << j)] | reachable[j]; updated = true; } } } int out = 0; for (j = 0; j < sz; j++) { if ((dp[i] >> j) & 1) out++; } if (in >= out && in < sz) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char *argv[]) { ios::sync_with_stdio(false); cin.tie(nullptr); string s, t; cin >> s >> t; int ns = s.size() - 1; int nt = t.size() - 1; bool stop = true; while (stop && (ns >= 0 && nt >= 0)) { if (s[ns] != t[nt]) { stop = false; } if (stop) { ns--; nt--; } } int r = ns + nt + 2; cout << r; return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:1000000000 ) static long long m1[70][70]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); m1[0][0] = 1; for (int i = 1; i <= 30; ++i) { m1[i][0] = 1; for (int j = 1; j <= 30; ++j) m1[i][j] = m1[i - 1][j - 1] + m1[i - 1][j]; } long long n, m, t, r = 0; cin >> n >> m >> t; for (int i = 4; i < t; ++i) if (t - i >= 0) r += m1[n][i] * m1[m][t - i]; cout << r << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 11; string s; bool vis[maxn]; int n; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> s; n = s.length(); vector<pair<int, int> > vec, tmp; for (int i = 0; i < n; i++) { if (vec.empty() || s[vec.back().first] != s[i]) vec.emplace_back(i, i); else { pair<int, int> p = vec.back(); vec.pop_back(); vec.emplace_back(p.first, i); } } int ans = 0; while (vec.size() > 1) { for (int i = 0; i < (int)(vec).size(); i++) { int sub = 2 - (i == 0 || i == (int)(vec).size() - 1); if (vec[i].second >= vec[i].first + sub) { if (tmp.empty() || s[tmp.back().first] != s[vec[i].first]) { vec[i].second -= sub; tmp.push_back(vec[i]); } else { pair<int, int> p = tmp.back(); tmp.pop_back(); p.second += vec[i].second - vec[i].first + 1 - sub; tmp.push_back(p); } } } ans++; tmp.swap(vec); tmp.clear(); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n + 1]; vector<int> v; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] == 1) { v.push_back(1); } else { v[v.size() - 1] = max(arr[i], v[v.size() - 1]); } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { cout << v[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 20005; const int M = 400005; vector<pair<int, int> > E[N]; int dep[N], fa[N][16], fav[N][16]; int n, m, S, T, nd, jud[N * 2]; int head[M], vis[M], tot = 1; int dis[M], q[M]; struct edge { int to, next, f; } e[M * 5]; void add(int x, int y, int f) { e[++tot] = (edge){y, head[x], f}; head[x] = tot; e[++tot] = (edge){x, head[y], 0}; head[y] = tot; } bool bfs() { for (int i = (int)(1); i <= (int)(nd); i++) dis[i] = -1; int h = 0, t = 1; q[1] = S; dis[S] = 0; while (h != t) { int x = q[++h]; for (int i = head[x]; i; i = e[i].next) if (dis[e[i].to] == -1 && e[i].f) { dis[e[i].to] = dis[x] + 1; if (e[i].to == T) return 1; q[++t] = e[i].to; } } return 0; } int dfs(int x, int flow) { if (x == T) return flow; int k, rest = flow; for (int i = head[x]; i && rest; i = e[i].next) if (dis[e[i].to] == dis[x] + 1 && e[i].f) { k = dfs(e[i].to, min(rest, e[i].f)); e[i].f -= k; e[i ^ 1].f += k; rest -= k; } if (rest) dis[x] = -1; return flow - rest; } void dfs(int x) { for (auto i : E[x]) if (i.first != fa[x][0]) { dep[i.first] = dep[x] + 1; fa[i.first][0] = x; fav[i.first][0] = i.second; dfs(i.first); } } int LCA(int x, int y) { if (dep[x] < dep[y]) swap(x, y); int tmp = dep[x] - dep[y]; for (int i = (int)(14); i >= (int)(0); i--) if (tmp & (1 << i)) x = fa[x][i]; for (int i = (int)(14); i >= (int)(0); i--) if (fa[x][i] != fa[y][i]) x = fa[x][i], y = fa[y][i]; return x == y ? x : fa[x][0]; } int main() { scanf( %d%d , &n, &m); for (int i = (int)(1); i <= (int)(n - 1); i++) { int x, y; scanf( %d%d , &x, &y); E[x].push_back(pair<int, int>(y, i)); E[y].push_back(pair<int, int>(x, i)); } S = nd = n; T = ++nd; for (int i = (int)(1); i <= (int)(n - 1); i++) add(S, i, 1), jud[i] = tot; for (int i = (int)(1); i <= (int)(m); i++) add(++nd, T, 1), jud[i + n] = tot; dfs(1); for (int i = (int)(1); i <= (int)(14); i++) for (int j = (int)(1); j <= (int)(n); j++) { fa[j][i] = fa[fa[j][i - 1]][i - 1]; if (dep[j] >= 1 << i) { fav[j][i] = ++nd; add(fav[j][i - 1], fav[j][i], 1 << 30); add(fav[fa[j][i - 1]][i - 1], fav[j][i], 1 << 30); } } for (int i = (int)(1); i <= (int)(m); i++) { int p = n + 1 + i, x, y; scanf( %d%d , &x, &y); int L = LCA(x, y); for (int j = (int)(14); j >= (int)(0); j--) { if (dep[x] - dep[L] >= 1 << j) add(fav[x][j], n + 1 + i, 1 << 30), x = fa[x][j]; if (dep[y] - dep[L] >= 1 << j) add(fav[y][j], n + 1 + i, 1 << 30), y = fa[y][j]; } assert(x == L && y == L); } int tmp = 0; for (; bfs(); tmp += dfs(S, 1 << 30)) ; vector<int> ans1, ans2; for (int i = (int)(1); i <= (int)(n - 1); i++) if (dis[i] == -1) ans1.push_back(i); for (int i = (int)(1); i <= (int)(m); i++) if (dis[i + n + 1] != -1) ans2.push_back(i); assert(ans1.size() + ans2.size() == tmp); printf( %d n , ans1.size() + ans2.size()); printf( %d , ans2.size()); for (auto i : ans2) printf( %d , i); puts( ); printf( %d , ans1.size()); for (auto i : ans1) printf( %d , i); puts( ); } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CPU Read State Machine
// File : cpu_rd.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module contanins a state machince which generates
// cpu_rd_req to arbitration block to get the cpu_cycle
// grant. The state machine also generates svga_req to
// the memory block and after the svga_ack is obtained
// it reads the data from the memory block.
//
// This module also generates cpu_rd address form g_addr_out
// [22:0] for both memory 32 and 64 bit transfers.
//
// The memory data is transfered to the graphic module as g_graph_data[31:0].
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module cpu_rd
(
input g_memwr,
input g_cpu_cycle_done,
input g_cpu_data_done,
input c_misc_b1,
input h_svga_sel,
input hreset_n,
input g_memrd,
input cpu_rd_gnt,
input svga_ack,
input t_data_ready_n,
input mem_clk,
input [31:0] m_t_mem_data_in,
output reg cpu_rd_req,
output reg cpu_rd_svga_req,
output reg [31:0] g_graph_data_in,
output m_memrd_ready_n,
output reg m_cpurd_state1,
output reg m_cpurd_s0,
output en_cpurd_addr
);
reg cpurd_s2;
reg cpurd_s3;
reg cpurd_s4;
reg [2:0] current_state;
reg [2:0] next_state;
wire [22:3] int_mem_addr;
wire [22:3] int_rdmem_add;
wire [63:0] mem_data_df1;
wire dummy_out_1;
wire int_d_dly;
wire mem_clk_dly;
parameter cpurd_state0 = 3'b000,
cpurd_state1 = 3'b001,
cpurd_state2 = 3'b011,
cpurd_state4 = 3'b111,
cpurd_state3 = 3'b110;
always @ (posedge mem_clk or negedge hreset_n) begin
if (!hreset_n) current_state <= cpurd_state0;
else current_state <= next_state;
end
always @* begin
m_cpurd_s0 = 1'b0;
cpu_rd_req = 1'b0;
m_cpurd_state1 = 1'b0;
cpu_rd_svga_req = 1'b0;
cpurd_s2 = 1'b0;
cpurd_s3 = 1'b0;
cpurd_s4 = 1'b0;
case (current_state) // synopsys parallel_case full_case
cpurd_state0: begin
m_cpurd_s0 = 1'b1;
if (g_memrd & h_svga_sel & c_misc_b1)
next_state = cpurd_state1;
else
next_state = cpurd_state0;
end
cpurd_state1:
begin
cpu_rd_req = 1'b1;
m_cpurd_state1 = 1'b1;
if (cpu_rd_gnt)
next_state = cpurd_state2;
else
next_state = cpurd_state1;
end
cpurd_state2:
begin
cpu_rd_req = 1'b1;
cpu_rd_svga_req = 1'b1;
cpurd_s2 = 1'b1;
if (svga_ack)
next_state = cpurd_state4;
else
next_state = cpurd_state2;
end
cpurd_state4:
begin
cpurd_s4 = 1'b1;
cpu_rd_req = 1'b1;
if (g_cpu_cycle_done)
next_state = cpurd_state3;
else
next_state = cpurd_state2;
end
cpurd_state3:
begin
cpu_rd_req = 1'b1;
cpurd_s3 = 1'b1;
if (g_cpu_data_done)
next_state = cpurd_state0;
else
next_state = cpurd_state3;
end
endcase
end
//
// Generating cpu read address
//
assign en_cpurd_addr = g_memwr & cpu_rd_gnt;
//
// Generating cpu write address
//
assign m_memrd_ready_n = ~(g_cpu_cycle_done& cpu_rd_gnt & ~t_data_ready_n);
always @* g_graph_data_in = m_t_mem_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 2e9; const long long infll = 1e18; double eps = 0.0000001; ifstream in( input.txt ); ofstream out( output.txt ); ; long long n; vector<long long> c; vector<long long> t; void init() { cin >> n; c.resize(n); t.resize(n); for (long long i = 0; i < n; i++) cin >> c[i]; for (long long i = 0; i < n; i++) cin >> t[i]; } void solve() { multiset<long long> razn1, razn2; for (long long i = 0; i < n - 1; i++) { razn1.insert(c[i + 1] - c[i]); razn2.insert(t[i + 1] - t[i]); } if (razn1 == razn2 && c[0] == t[0] && c[n - 1] == t[n - 1]) cout << Yes ; else cout << No ; } signed main() { init(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; string makeCentered(int len) { string output; for (int i = 0; i < 27; i++) { output.push_back( . ); } for (int i = 0; i < len; i++) { output[13 + i] = X ; output[13 - i] = X ; } return output; } string blank() { string output; for (int i = 0; i < 27; i++) { output.push_back( . ); } return output; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string input; cin >> input; vector<int> target; for (int i = 0; i < input.size(); i++) { target.push_back(int(input[i])); } vector<string> output; int val = 0; for (int i = 0; i < target.size(); i++) { int curTarget = target[i]; vector<int> triSizes; int distance = curTarget - val; if (i != 0) distance = val - curTarget; while (distance < 0) distance += 256; while (distance > 0) { if (i == 0) { for (int j = 12; j >= (i == 0 ? 1 : 2); j--) { int next; if (i != 0) next = j * j - 1; else next = j * j; if (next <= distance) { for (int k = 1; k <= j + 1; k++) { cout << makeCentered(k) << endl; } distance -= next; val += next; val %= 256; cout << blank() << endl; break; } } } else { cout << makeCentered(1) << endl; cout << blank() << endl; distance -= 1; val -= 1; if (val < 0) val += 256; } } cout << blank() << endl; string curString = blank(); curString[0] = X ; curString[curString.size() - 1] = X ; cout << curString << endl; curString[curString.size() - 1] = . ; cout << curString << endl; cout << blank() << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = atan(1.0) * 4.0; const long long int MOD = 1e9 + 7; const long long int INF = 1e5; const long double EPS = 0.0000001; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL); int a[1005], k; a[0] = -1; a[1] = 0; for (int i = 2; i <= 1005; i++) { a[i] = a[i - 1] + i - 1; } cin >> k; if (k == 0) { cout << a << endl; return 0; } char ch = a ; while (k > 0) { int lb = lower_bound(a, a + 1005, k) - a; if (a[lb] != k) lb--; for (int i = 1; i <= lb; i++) cout << ch; k -= a[lb]; ch++; } cout << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIO_OVTV2_SYMBOL_V
`define SKY130_FD_IO__TOP_GPIO_OVTV2_SYMBOL_V
/**
* top_gpio_ovtv2: General Purpose I/0.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpio_ovtv2 (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H ,
inout PAD_A_ESD_1_H ,
inout PAD_A_NOESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ANALOG_EN ,
input ANALOG_POL ,
input ANALOG_SEL ,
input [2:0] DM ,
input ENABLE_H ,
input ENABLE_INP_H ,
input ENABLE_VDDA_H ,
input ENABLE_VDDIO ,
input ENABLE_VSWITCH_H,
input HLD_H_N ,
input HLD_OVR ,
input HYS_TRIM ,
input [1:0] IB_MODE_SEL ,
input OE_N ,
input [1:0] SLEW_CTL ,
//# {{power|Power}}
input VTRIP_SEL ,
output TIE_HI_ESD ,
input VINREF ,
output TIE_LO_ESD
);
// Voltage supply signals
supply1 VDDIO ;
supply1 VDDIO_Q;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIO_OVTV2_SYMBOL_V
|
`default_nettype none
// ============================================================================
module serializer #
(
parameter WIDTH = 4, // Serialization rate
parameter MODE = "SDR" // "SDR" or "DDR"
)
(
// Clock & reset
input wire CLK,
input wire RST,
// Data input
input wire[WIDTH-1:0] I,
output wire RD,
output wire CE,
// Serialized output
output wire O_CLK,
output wire O_DAT
);
// ============================================================================
generate if (MODE == "DDR" && (WIDTH & 1)) begin
error for_DDR_mode_the_WIDTH_must_be_even ();
end endgenerate
// ============================================================================
// Output clock generation
reg o_clk;
wire ce;
always @(posedge CLK)
if (RST) o_clk <= 1'd1;
else o_clk <= !o_clk;
assign ce = !o_clk;
// ============================================================================
reg [7:0] count;
reg [WIDTH-1:0] sreg;
wire sreg_ld;
always @(posedge CLK)
if (RST) count <= 2;
else if (ce) begin
if (count == 0) count <= ((MODE == "DDR") ? (WIDTH/2) : WIDTH) - 1;
else count <= count - 1;
end
assign sreg_ld = (count == 0);
always @(posedge CLK)
if (ce) begin
if (sreg_ld) sreg <= I;
else sreg <= sreg << ((MODE == "DDR") ? 2 : 1);
end
wire [1:0] o_dat = sreg[WIDTH-1:WIDTH-2];
// ============================================================================
// SDR/DDR output FFs
reg o_reg;
always @(posedge CLK)
if (!o_clk && MODE == "SDR") o_reg <= o_dat[1]; // +
else if (!o_clk && MODE == "DDR") o_reg <= o_dat[0]; // +
else if ( o_clk && MODE == "DDR") o_reg <= o_dat[1]; // -
else o_reg <= o_reg;
// ============================================================================
assign O_DAT = o_reg;
assign O_CLK = o_clk;
assign RD = (count == 1);
assign CE = ce;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T inline sqr(T x) { return x * x; } template <class T> inline void relaxMin(T &a, T b) { a = min(a, b); } template <class T> inline void relaxMax(T &a, T b) { a = max(a, b); } template <class T> inline T sign(T x) { return x > 0 ? 1 : (x < 0 ? -1 : 0); } template <class T> inline T myAbs(T a) { return a > 0 ? a : -a; } template <class T> T iteratorK(T a, int k) { while (k--) a++; return a; } void err(const char *fmt, ...) {} void Assert(bool f, const char *fmt = , ...) { if (!f) { va_list list; va_start(list, fmt); err(fmt, list); exit(1); } } unsigned R() { return (rand() << 15) + rand(); } double start = clock(); void TimeStamp() { fprintf(stderr, time = %.2f n , (clock() - start) / CLOCKS_PER_SEC); start = clock(); } const int maxN = (int)1e5 + 10; int n, a, d; int main() { scanf( %d%d%d , &n, &a, &d); long double minT = 0; for (int i = 0; i < (int)(n); i++) { int t, v; scanf( %d%d , &t, &v); long double D, T, T0 = (long double)v / a; if ((D = 0.5 * T0 * T0 * a) >= d) T = sqrt((long double)2.0 * d / a); else T = T0 + (long double)(d - D) / v; T += t; minT = T = max(minT, T); printf( %.20f n , (double)T); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:44 04/06/2010
// Design Name:
// Module Name: path
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MDPath(input clk,
input reset,
input MIO_ready, //=1
input IorD,
input IRWrite,
input[1:0] RegDst,
input RegWrite,
input[1:0]MemtoReg,
input ALUSrcA,
input[1:0]ALUSrcB,
input[1:0]PCSource,
input PCWrite,
input PCWriteCond,
input Branch,
input[2:0]ALU_operation,
output[31:0]PC_Current,
input[31:0]data2CPU,
output[31:0]Inst,
output[31:0]data_out,
output[31:0]M_addr,
output zero,
output overflow
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; if (n <= 30) cout << NO n ; else { cout << YES n ; long long d = n - 30; long long a = 6, b = 10, c = 14; if (d == 6 || d == 10 || d == 14) cout << 6 10 15 << d - 1 << endl; else cout << 6 10 14 << d << endl; } } signed main() { long long t; cin >> t; while (t--) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRBP_PP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; map<pair<int, int>, int> weight; vector<int> edges[MAXN]; bool visited[MAXN]; long long int maximum; void dfs(int v, long long int sum) { visited[v] = true; maximum = max(maximum, sum); for (int i : edges[v]) { if (!visited[i]) dfs(i, sum + weight[make_pair(v, i)]); } return; } int main() { long long int n, a, b, c, sum_of_edges = 0; cin >> n; for (int i = 0; i < n - 1; i++) { cin >> a >> b >> c; sum_of_edges += c; a--; b--; edges[a].push_back(b); edges[b].push_back(a); weight[make_pair(a, b)] = c; weight[make_pair(b, a)] = c; } dfs(0, 0); sum_of_edges *= 2; sum_of_edges -= maximum; cout << sum_of_edges << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> split(string s) { vector<int> xs; stringstream ss(s); string item; while (getline(ss, item, , )) { xs.push_back(stoi(item)); } return xs; } int main() { string s; getline(cin, s); vector<int> xxs = split(s); sort(xxs.begin(), xxs.end()); vector<pair<int, int>> sol; for (int i = 0; i < xxs.size(); i++) { int st = xxs[i]; int e = st; while (i < xxs.size() - 1 && (e + 1 == xxs[i + 1] || e == xxs[i + 1])) { e = xxs[i + 1]; i++; } sol.push_back(make_pair(st, e)); } for (int i = 0; i < sol.size(); i++) { if (sol[i].first != sol[i].second) { cout << sol[i].first << - << sol[i].second; } else { cout << sol[i].first; } if (i != sol.size() - 1) { cout << , ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A211O_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_SYMBOL_V
|
/*
First construct a D-Flipflop and then reuse this in the asynchronous counter
In fact this is a reuse of the dflipflop code already done in an earlier exercise
NOTE the difference is that the reset signal is also part of the sensitivity list
Just the name of the module is changed so that there is no conflict
*/
module jAsyncCntrDFlipFlop(q,qbar,clk,rst,d);
output reg q;
output qbar;
input clk, rst;
input d;
assign qbar = ~q;
// NOTE it is important to mention the edge for each of the parameter
// if it is not mentioned default is all edges i.e. positive and negative edges
always @(posedge clk, posedge rst)
begin
if (rst)
q <= 0;
else
q <= d;
end
endmodule
module jAsynchronousCounter(count,countbar,clk,rst);
input clk, rst;
output [3:0] count, countbar;
jAsyncCntrDFlipFlop m1(count[0],countbar[0],clk ,rst,countbar[0]);
jAsyncCntrDFlipFlop m2(count[1],countbar[1],count[0],rst,countbar[1]);
jAsyncCntrDFlipFlop m3(count[2],countbar[2],count[1],rst,countbar[2]);
jAsyncCntrDFlipFlop m4(count[3],countbar[3],count[2],rst,countbar[3]);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, l, r, deg[100005], num; int main() { scanf( %d%d , &n, &m); for (int i = 1; i < n; i++) { scanf( %d%d , &l, &r); deg[l]++; deg[r]++; } for (int i = 1; i <= n; i++) if (deg[i] == 1) num++; printf( %.7f n , (double)2.0 * m / num); } |
#include <bits/stdc++.h> using namespace std; auto main() -> int { int N, X, Y; cin >> N; vector<int> C(N); for (int i = 0; i < N; i++) cin >> C[i]; cin >> X >> Y; int l = 0; int ret = 0; for (int i = 0; i < N; i++) { if (l < X) { if (l + C[i] <= Y) l += C[i]; else break; } else if (l >= X && l <= Y) { int t = 0; for (int j = i; j < N; j++) t += C[j]; if (t >= X && t <= Y) { ret = i + 1; break; } else { l += C[i]; } } } cout << ret << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_FUNCTIONAL_PP_V |
module datapath (input clk, reset,
input memtoreg, pcsrc,
input alusrc, regdst,
input regwrite, jump,
input [2:0] alucontrol,
output zero,
output [31:0] pc,
input [31:0] instr,
output [31:0] aluout, writedata,
input [31:0] readdata);
wire [4:0] writereg;
wire [31:0] pcnext, pcnextbr, pcplus4, pcbranch;
wire [31:0] signimm, signimmsh;
wire [31:0] srca, srcb;
wire [31:0] result;
// next PC logic
flopr #(32) pcreg(clk, reset, pcnext, pc);
adder pcadd1 (pc, 32'b100, pcplus4);
sl2 immsh(signimm, signimmsh);
adder pcadd2(pcplus4, signimmsh, pcbranch);
mux2 #(32) pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);
mux2 #(32) pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00},jump, pcnext);
// register file logic
regfile rf(clk, regwrite, instr[25:21],
instr[20:16], writereg, result, srca, writedata);
mux2 #(5) wrmux(instr[20:16], instr[15:11],regdst, writereg);
mux2 #(32) resmux(aluout, readdata, memtoreg, result);
signext se(instr[15:0], signimm);
// ALU logic
mux2 #(32) srcbmux(writedata, signimm, alusrc, srcb);
alu alu(srca, srcb, alucontrol, aluout, zero);
endmodule |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] pcie_dev_id,
output tx_err_drop,
input tx_cpld_gnt,
input tx_mrd_gnt,
input tx_mwr_gnt,
//pcie tx signal
input m_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] m_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_tx_tkeep,
output [3:0] m_axis_tx_tuser,
output m_axis_tx_tlast,
output m_axis_tx_tvalid,
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last
);
wire w_tx_arb_valid;
wire [5:0] w_tx_arb_gnt;
wire [2:0] w_tx_arb_type;
wire [11:2] w_tx_pcie_len;
wire [127:0] w_tx_pcie_head;
wire [31:0] w_tx_cpld_udata;
wire w_tx_arb_rdy;
pcie_tx_arb # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_arb_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (pcie_dev_id),
.tx_cpld_gnt (tx_cpld_gnt),
.tx_mrd_gnt (tx_mrd_gnt),
.tx_mwr_gnt (tx_mwr_gnt),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy)
);
pcie_tx_tran # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_tran_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.tx_err_drop (tx_err_drop),
//pcie tx signal
.m_axis_tx_tready (m_axis_tx_tready),
.m_axis_tx_tdata (m_axis_tx_tdata),
.m_axis_tx_tkeep (m_axis_tx_tkeep),
.m_axis_tx_tuser (m_axis_tx_tuser),
.m_axis_tx_tlast (m_axis_tx_tlast),
.m_axis_tx_tvalid (m_axis_tx_tvalid),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
#include <iostream> #include <algorithm> #include <vector> #include <cmath> using namespace std; int main() { int t = 0; cin>>t; for(int i = 0; i < t; i++) { int n = 0; cin>>n; int v[100] = {0}; for(int j = 0; j < n; j++) cin>>v[j]; if(v[0] == n && v[n-1] == 1) { cout<<3<< n ; } else if(v[0] != 1 && v[n-1] != n) { cout<<2<< n ; } else if(v[0] == 1 && v[n-1] != n) { cout<<1<< n ; } else if(v[0] != 1 && v[n-1] == n) { cout<<1<< n ; } else { bool d = false; for(int j = 0; j < n; j++) { if(v[j] != j+1) { d = true; break; } } if(!d) cout<<0<< ; else cout<<1<< ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void join(vector<T>& arr, string sep) { bool first = true; for (auto t : arr) { if (first) { first = false; cout << t; } else { cout << sep << t; } } cout << n ; } struct Euler { vector<vector<pair<long long, long long>>> g; long long n; vector<long long> path; long long edge_count; Euler(long long n) : n(n) { g.resize(n); edge_count = 0; } void addEdge(long long u, long long v) { long long w = edge_count++; g[u].push_back({v, w}); g[v].push_back({u, w}); } bool compute() { int first = 0; while (first < n && g[first].empty()) first++; if (first == n) return true; long long v1 = -1, v2 = -1; for (long long u = 0; u < (long long)(n); ++u) { if (g[u].size() & 1) { return false; } } if (v1 != -1) { assert(v2 != -1); } vector<long long> visited(edge_count); vector<long long> s = {first}; while (!s.empty()) { long long u = s.back(); long long v; while (true) { if (g[u].empty()) { v = -1; path.push_back(u); s.pop_back(); break; } long long v = g[u].back().first; long long w = g[u].back().second; g[u].pop_back(); if (visited[w]) { continue; } visited[w] = true; s.push_back(v); break; } } if (v1 != -1) { for (long long i = 0; i < (long long)(path.size() - 1); ++i) { if ((path[i] == v1 && path[i + 1] == v2) || (path[i] == v2 && path[i + 1] == v1)) { vector<long long> res; for (long long j = (long long)(i + 1); j < (long long)(path.size()); ++j) { res.push_back(path[j]); } for (long long j = (long long)(1); j < (long long)(i + 1); ++j) { res.push_back(path[j]); } path = res; break; } } } for (long long u = 0; u < (long long)(n); ++u) { if (!g[u].empty()) { return false; } } return true; } }; long long getPref(long long c, long long i) { return ((1 << i) - 1) & c; } struct PairHash { int operator()(const pair<long long, long long>& pp) const { const int p = 31; const int m = 1e9 + 9; long long l = pp.first; long long r = (pp.second * p) % m; return (l + r) % m; } }; void solve() { long long n; cin >> n; vector<pair<long long, long long>> colors(n); for (long long i = 0; i < (long long)(n); ++i) { long long a, b; cin >> a >> b; colors[i] = {a, b}; } vector<long long> res; for (long long i = (long long)(1); i < (long long)(2 * n + 1); ++i) { res.push_back(i); } long long lowest = 0; long long l = 1; long long r = 20; while (l <= r) { long long i = l + (r - l) / 2; unordered_map<pair<long long, long long>, vector<pair<long long, long long>>, PairHash> nodes2Idx; Euler e(1 << i); for (long long j = 0; j < (long long)(n); ++j) { long long pref1 = getPref(colors[j].first, i); long long pref2 = getPref(colors[j].second, i); long long idx1 = 2 * j + 1; long long idx2 = 2 * j + 2; if (pref1 > pref2) { swap(pref1, pref2); swap(idx1, idx2); } nodes2Idx[{pref1, pref2}].push_back({idx1, idx2}); e.addEdge(pref1, pref2); } if (!e.compute()) { r = i - 1; continue; } l = i + 1; lowest = i; assert(e.path.size() == n + 1); for (long long j = 0; j < (long long)(n); ++j) { long long pref1 = e.path[j]; long long pref2 = e.path[j + 1]; bool swaped = false; if (pref1 > pref2) { swap(pref1, pref2); swaped = true; } auto it = nodes2Idx.find({pref1, pref2}); pair<long long, long long> idxPair = it->second.back(); it->second.pop_back(); long long idx1 = idxPair.first; long long idx2 = idxPair.second; if (swaped) swap(idx1, idx2); res[2 * j] = idx1; res[2 * j + 1] = idx2; } } cout << lowest << n ; join(res, ); } int main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using ll = long long; using namespace std; const long double PI = acos(-1); const long long M = 998244353; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); inline long long mod(long long n, long long m = M) { long long ret = n % m; if (ret < 0) ret += m; return ret; } long long exp(long long n, long long k, long long m = M) { if (k == 0) return 1; if (k == 1) return n; long long ax = exp(n, k / 2, m); ax = mod(ax * ax, m); if (k % 2) ax = mod(ax * n, m); return ax; } long long gcd(long long a, long long b) { if (a == 0) return b; else return gcd(b % a, a); } void solution() { list<long long> l; long long n, k; cin >> n >> k; vector<list<long long>::iterator> elems(n + 1); for (long long i = 0; i < n; i++) { long long x; cin >> x; l.push_back(x); auto ed = l.end(); ed--; elems[x] = ed; } long long ans = 1; vector<bool> mark(n + 1, true); vector<long long> b(k); for (long long i = 0; i < k; i++) { cin >> b[i]; mark[b[i]] = false; } for (long long i = 0; i < k; i++) { auto it = elems[b[i]]; long long mult = 0; if (it != l.begin()) { auto it2 = it; it2--; mult += mark[*it2]; } auto it2 = it; it2++; if (it2 != l.end()) mult += mark[*it2]; ans *= mult; ans = mod(ans); mark[b[i]] = true; } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) solution(); } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone RAM
*/
module wb_ram #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire [ADDR_WIDTH-1:0] adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] dat_o, // DAT_O() data out
input wire we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] sel_i, // SEL_I() select input
input wire stb_i, // STB_I strobe input
output wire ack_o, // ACK_O acknowledge output
input wire cyc_i // CYC_I cycle input
);
// for interfaces that are more than one word wide, disable address lines
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
// width of data port in words (1, 2, 4, or 8)
parameter WORD_WIDTH = SELECT_WIDTH;
// size of words (8, 16, 32, or 64 bits)
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg [DATA_WIDTH-1:0] dat_o_reg = {DATA_WIDTH{1'b0}};
reg ack_o_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] adr_i_valid = adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign dat_o = dat_o_reg;
assign ack_o = ack_o_reg;
integer i;
initial begin
for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 1) begin
mem[i] = 0;
end
end
always @(posedge clk) begin
ack_o_reg <= 1'b0;
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (cyc_i & stb_i & ~ack_o) begin
if (we_i & sel_i[i]) begin
mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= dat_i[WORD_SIZE*i +: WORD_SIZE];
end
dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
ack_o_reg <= 1'b1;
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
// Title : PCI Express BFM Message Logging Include File
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcietb_bfm_log.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This include file provides routines to log various information to the standard
// output
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
// Constants for the logging package
parameter EBFM_MSG_DEBUG = 0;
parameter EBFM_MSG_INFO = 1;
parameter EBFM_MSG_WARNING = 2;
parameter EBFM_MSG_ERROR_INFO = 3; // Preliminary Error Info Message
parameter EBFM_MSG_ERROR_CONTINUE = 4;
// Fatal Error Messages always stop the simulation
parameter EBFM_MSG_ERROR_FATAL = 101;
parameter EBFM_MSG_ERROR_FATAL_TB_ERR = 102;
// Maximum Message Length in characters
parameter EBFM_MSG_MAX_LEN = 100 ;
// purpose: sets the suppressed_msg_mask
task ebfm_log_set_suppressed_msg_mask;
input [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG] msg_mask;
begin
// ebfm_log_set_suppressed_msg_mask
bfm_log_common.suppressed_msg_mask = msg_mask;
end
endtask
// purpose: sets the stop_on_msg_mask
task ebfm_log_set_stop_on_msg_mask;
input [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG] msg_mask;
begin
// ebfm_log_set_stop_on_msg_mask
bfm_log_common.stop_on_msg_mask = msg_mask;
end
endtask
// purpose: Opens the Log File with the specified name
task ebfm_log_open;
input [200*8:1] fn; // Log File Name
begin
bfm_log_common.log_file = $fopen(fn);
end
endtask
// purpose: Opens the Log File with the specified name
task ebfm_log_close;
begin
// ebfm_log_close
$fclose(bfm_log_common.log_file);
bfm_log_common.log_file = 0;
end
endtask
// purpose: stops the simulation, with flag to indicate success or not
function ebfm_log_stop_sim;
input success;
integer success;
begin
if (success == 1)
begin
$display("SUCCESS: Simulation stopped due to successful completion!");
`ifdef VCS
$finish;
`else
$stop ;
`endif
end
else
begin
$display("FAILURE: Simulation stopped due to error!");
`ifdef VCS
$finish;
`else
$stop ;
`endif
end
ebfm_log_stop_sim = 1'b0 ;
end
endfunction
// purpose: This displays a message of the specified type
function ebfm_display;
input msg_type;
integer msg_type;
input [EBFM_MSG_MAX_LEN*8:1] message;
reg [9*8:1] prefix ;
reg [80*8:1] amsg;
reg sup;
reg stp;
reg dummy ;
integer i ;
time ctime ;
integer itime ;
begin
for (i = 0 ; i < EBFM_MSG_MAX_LEN ; i = i + 1)
begin : msg_shift
if (message[(EBFM_MSG_MAX_LEN*8)-:8] != 8'h00)
begin
disable msg_shift ;
end
message = message << 8 ;
end
if (msg_type > EBFM_MSG_ERROR_CONTINUE)
begin
sup = 1'b0;
stp = 1'b1;
case (msg_type)
EBFM_MSG_ERROR_FATAL :
begin
amsg = "FAILURE: Simulation stopped due to Fatal error!" ;
prefix = "FATAL: ";
end
EBFM_MSG_ERROR_FATAL_TB_ERR :
begin
amsg = "FAILURE: Simulation stopped due error in Testbench/BFM design!";
prefix = "FATAL: ";
end
default :
begin
amsg = "FAILURE: Simulation stopped due to unknown message type!";
prefix = "FATAL: ";
end
endcase
end
else
begin
sup = bfm_log_common.suppressed_msg_mask[msg_type];
stp = bfm_log_common.stop_on_msg_mask[msg_type];
if (stp == 1'b1)
begin
amsg = "FAILURE: Simulation stopped due to enabled error!";
end
if (msg_type < EBFM_MSG_INFO)
begin
prefix = "DEBUG: ";
end
else
begin
if (msg_type < EBFM_MSG_WARNING)
begin
prefix = "INFO: ";
end
else
begin
if (msg_type > EBFM_MSG_WARNING)
begin
prefix = "ERROR: ";
end
else
begin
prefix = "WARNING: ";
end
end
end
end // else: !if(msg_type > EBFM_MSG_ERROR_CONTINUE)
itime = ($time/1000) ;
// Display the message if not suppressed
if (sup != 1'b1)
begin
if (bfm_log_common.log_file != 0)
begin
$fdisplay(bfm_log_common.log_file,"%s %d %s %s",prefix,itime,"ns",message);
end
$display("%s %d %s %s",prefix,itime,"ns",message);
end
// Stop if requested
if (stp == 1'b1)
begin
if (bfm_log_common.log_file != 0)
begin
$fdisplay(bfm_log_common.log_file, "%s", amsg);
end
$display("%s",amsg);
dummy = ebfm_log_stop_sim(0);
end
// Dummy function return so we can call from other functions
ebfm_display = 1'b0 ;
end
endfunction
// purpose: produce 1-digit hexadecimal string from a vector
function [8:1] himage1;
input [3:0] vec;
begin
case (vec)
4'h0 : himage1 = "0" ;
4'h1 : himage1 = "1" ;
4'h2 : himage1 = "2" ;
4'h3 : himage1 = "3" ;
4'h4 : himage1 = "4" ;
4'h5 : himage1 = "5" ;
4'h6 : himage1 = "6" ;
4'h7 : himage1 = "7" ;
4'h8 : himage1 = "8" ;
4'h9 : himage1 = "9" ;
4'hA : himage1 = "A" ;
4'hB : himage1 = "B" ;
4'hC : himage1 = "C" ;
4'hD : himage1 = "D" ;
4'hE : himage1 = "E" ;
4'hF : himage1 = "F" ;
4'bzzzz : himage1 = "Z" ;
default : himage1 = "X" ;
endcase
end
endfunction // himage1
// purpose: produce 2-digit hexadecimal string from a vector
function [16:1] himage2 ;
input [7:0] vec;
begin
himage2 = {himage1(vec[7:4]),himage1(vec[3:0])} ;
end
endfunction // himage2
// purpose: produce 4-digit hexadecimal string from a vector
function [32:1] himage4 ;
input [15:0] vec;
begin
himage4 = {himage2(vec[15:8]),himage2(vec[7:0])} ;
end
endfunction // himage4
// purpose: produce 8-digit hexadecimal string from a vector
function [64:1] himage8 ;
input [31:0] vec;
begin
himage8 = {himage4(vec[31:16]),himage4(vec[15:0])} ;
end
endfunction // himage8
// purpose: produce 16-digit hexadecimal string from a vector
function [128:1] himage16 ;
input [63:0] vec;
begin
himage16 = {himage8(vec[63:32]),himage8(vec[31:0])} ;
end
endfunction // himage16
// purpose: produce 1-digit decimal string from an integer
function [8:1] dimage1 ;
input [31:0] num ;
begin
case (num)
0 : dimage1 = "0" ;
1 : dimage1 = "1" ;
2 : dimage1 = "2" ;
3 : dimage1 = "3" ;
4 : dimage1 = "4" ;
5 : dimage1 = "5" ;
6 : dimage1 = "6" ;
7 : dimage1 = "7" ;
8 : dimage1 = "8" ;
9 : dimage1 = "9" ;
default : dimage1 = "U" ;
endcase // case(num)
end
endfunction // dimage1
// purpose: produce 2-digit decimal string from an integer
function [16:1] dimage2 ;
input [31:0] num ;
begin
dimage2 = {dimage1(num/10),dimage1(num % 10)} ;
end
endfunction // dimage2
// purpose: produce 3-digit decimal string from an integer
function [24:1] dimage3 ;
input [31:0] num ;
begin
dimage3 = {dimage1(num/100),dimage2(num % 100)} ;
end
endfunction // dimage3
// purpose: produce 4-digit decimal string from an integer
function [32:1] dimage4 ;
input [31:0] num ;
begin
dimage4 = {dimage1(num/1000),dimage3(num % 1000)} ;
end
endfunction // dimage4
// purpose: produce 5-digit decimal string from an integer
function [40:1] dimage5 ;
input [31:0] num ;
begin
dimage5 = {dimage1(num/10000),dimage4(num % 10000)} ;
end
endfunction // dimage5
// purpose: produce 6-digit decimal string from an integer
function [48:1] dimage6 ;
input [31:0] num ;
begin
dimage6 = {dimage1(num/100000),dimage5(num % 100000)} ;
end
endfunction // dimage6
// purpose: produce 7-digit decimal string from an integer
function [56:1] dimage7 ;
input [31:0] num ;
begin
dimage7 = {dimage1(num/),dimage6(num % )} ;
end
endfunction // dimage7
// purpose: select the correct dimage call for ascii conversion
function [800:1] image ;
input [800:1] msg ;
input [32:1] num ;
begin
if (num <= 10)
begin
image = {msg, dimage1(num)};
end
else if (num <= 100)
begin
image = {msg, dimage2(num)};
end
else if (num <= 1000)
begin
image = {msg, dimage3(num)};
end
else if (num <= 10000)
begin
image = {msg, dimage4(num)};
end
else if (num <= 100000)
begin
image = {msg, dimage5(num)};
end
else if (num <= )
begin
image = {msg, dimage6(num)};
end
else image = {msg, dimage7(num)};
end
endfunction
|
#include <bits/stdc++.h> using namespace std; int main() { map<int, int> container_1; map<int, int> container_2; int n; cin >> n; for (int i = 0; i < n; ++i) { int a, b; cin >> a >> b; container_1[a] = b; container_2[a] = 0; } int k; cin >> k; for (int i = 0; i < k; ++i) { int a, b; cin >> a >> b; container_2[a] = b; if (container_1.find(a) == container_1.end()) { container_1[a] = 0; } } long long sum = 0; for (auto it : container_1) { if (it.second > container_2[it.first]) { sum += it.second; } else { sum += container_2[it.first]; } } cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 20, INF = 1e9 + 20; int n, h[N], pmx[N], pmn[N], ans; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> h[i]; for (int i = 0; i < n; i++) pmx[i] = i ? max(h[i], pmx[i - 1]) : h[i]; pmn[n] = INF; for (int i = n - 1; ~i; i--) pmn[i] = min(h[i], pmn[i + 1]); for (int i = 0; i < n; i++) { if (pmx[i] <= pmn[i + 1]) ans++; } return cout << ans, 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; long long int a[n + 1][m + 1], i, j, p = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { cin >> a[i][j]; } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { int d = 4; if (i == 1) { d--; } if (j == 1) { d--; } if (i == n) { d--; } if (j == m) { d--; } if (a[i][j] <= d) { a[i][j] = d; } else { p = 1; } } } if (p == 1) { cout << NO << endl; } else { cout << YES << endl; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { cout << a[i][j] << ; } cout << endl; } } } return 0; } |
// DESCRIPTION: Verilator: Test symbol table scope map and general public
// signal reflection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
module t (
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo #(.WIDTH (65)) foo65 (.*);
foo #(.WIDTH (96)) foo96 (.*);
foo #(.WIDTH (97)) foo97 (.*);
foo #(.WIDTH (128)) foo128 (.*);
foo #(.WIDTH (256)) foo256 (.*);
foo #(.WIDTH (1024)) foo1024 (.*);
bar #(.WIDTH (1024)) bar1024 (.*);
endmodule
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ];
value_q = initial_value[ WIDTH - 1 : 0 ];
end
always @(posedge CLK)
value_q <= ~value_q;
endmodule
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 25, mod = 1e9 + 7; int a[N][N], used[N][N], cur, first, n, m, k; long long ans; int count(int x) { int ans = 0; for (; x; x -= x & -x) ans++; return ans; } void dfs(int x, int y) { if (x == n) { int p = count(cur & ~first), q = count(((1 << k) - 1) & ~first); long long curans = 1; while (p--) { curans = (curans * q) % mod; q--; } ans = (ans + curans) % mod; return; } int nx = x, ny = y + 1; if (ny == m) { nx++; ny = 0; } if (a[x][y]) { dfs(nx, ny); return; } else { bool flag = true; int can = (1 << k) - 1; can &= ~used[x][y]; for (int i = 0; (1 << i) <= can; i++) { if (!((can >> i) & 1)) continue; bool preused[N][N], preusedcur; preusedcur = true; memset(preused, false, sizeof(preused)); if (!((cur >> i) & 1)) { if (flag) flag = false; else continue; preusedcur = false; } cur |= 1 << i; for (int px = x; px < n; px++) for (int py = y; py < m; py++) { if ((used[px][py] >> i) & 1) preused[px][py] = true; else used[px][py] |= 1 << i; } dfs(nx, ny); if (!preusedcur) cur &= ~(1 << i); for (int px = x; px < n; px++) for (int py = y; py < m; py++) { if (!preused[px][py]) used[px][py] &= ~(1 << i); } } } } int main() { scanf( %d%d%d , &n, &m, &k); if (n + m - 1 > k) { printf( 0 n ); return 0; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { scanf( %d , &a[i][j]); if (a[i][j]) { first |= 1 << a[i][j] - 1; if ((used[i][j] >> a[i][j] - 1) & 1) { printf( 0 n ); return 0; } for (int r = 0; r < n; r++) for (int c = 0; c < m; c++) { if (r <= i && c <= j || r >= i && c >= j) used[r][c] |= 1 << a[i][j] - 1; } } } cur = first; dfs(0, 0); printf( %d n , ans); return 0; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in1.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : sys_clk_gen_ds.v
// Version : 2.4
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen_ds (sys_clk_p, sys_clk_n);
output sys_clk_p;
output sys_clk_n;
parameter offset = 0;
parameter halfcycle = 500;
sys_clk_gen #(
.offset( offset ),
.halfcycle( halfcycle )
)
clk_gen (
.sys_clk(sys_clk_p)
);
assign sys_clk_n = !sys_clk_p;
endmodule // sys_clk_gen_ds
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100100; int n; long long a[maxn]; map<long long, long long> mp; long long mul(long long x, long long n) { long long ret = 1; while (n) { if (n & 1) ret *= x; x *= x; n >>= 1; } return ret; } int main() { while (~scanf( %d , &n)) { mp.clear(); for (int i = (1); i < (n + 1); i++) { cin >> a[i]; mp[a[i]]++; } long long ret = 0; for (int i = (1); i < (n + 1); i++) { for (int j = 0; j < (31); j++) { long long cur = mul(2, j); if (mp.find(cur - a[i]) != mp.end()) { if (mp[cur - a[i]] == 1 && cur - a[i] == a[i]) continue; else if (mp[cur - a[i]] > 1 && cur - a[i] == a[i]) ret += mp[cur - a[i]] - 1; else ret += mp[cur - a[i]]; } } } cout << ret / 2 << endl; } return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 1212 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w255,
w32,
w287,
w16,
w303,
w1212;
assign w1 = i_data0;
assign w1212 = w303 << 2;
assign w16 = w1 << 4;
assign w255 = w256 - w1;
assign w256 = w1 << 8;
assign w287 = w255 + w32;
assign w303 = w287 + w16;
assign w32 = w1 << 5;
assign o_data0 = w1212;
//multiplier_block area estimate = 5125.98244440588;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
`timescale 100ns/100ps
module dummy;
parameter [1:0] ipval = 2;
endmodule
`timescale 1us/1ns
module top;
parameter [1:0] ipval = 2;
parameter spval = "Help";
parameter rpval = 1.0;
event evt;
reg [1:0] rgval;
reg rgarr [2:0];
wire [1:0] wval;
wire warr [2:0];
integer ival;
real rval;
real rarr [2:0];
time tval;
initial begin:blk
$printtimescale(dummy);
$printtimescale(dummy.ipval);
// These should all print a timescale of 1us / 1ns.
$printtimescale;
$printtimescale(top.ipval);
/* This does not currently work because Icarus does not know how
* to keep the parameter reference in the part select. For now
* it just returns a constant which the runtime will complain
* does not have a vpiModule. */
// $printtimescale(top.ipval[0]);
$printtimescale(top.spval);
/* The same goes here. */
// $printtimescale(top.spval[0]);
$printtimescale(top.rpval);
$printtimescale(top.evt);
$printtimescale(top.rgval);
$printtimescale(top.rgval[0]);
$printtimescale(top.rgarr);
$printtimescale(top.rgarr[0]);
$printtimescale(top.wval);
$printtimescale(top.wval[0]);
$printtimescale(top.warr);
$printtimescale(top.warr[0]);
$printtimescale(top.ival);
$printtimescale(top.ival[1]);
$printtimescale(top.rval);
$printtimescale(top.rarr);
$printtimescale(top.rarr[0]);
$printtimescale(top.tval);
$printtimescale(top.blk);
$printtimescale(top.frk);
$printtimescale(top.tsk);
$printtimescale(top.fnc);
end
initial fork:frk
$write("");
join
task tsk;
begin
end
endtask
function integer fnc;
input integer tmp;
fnc = 2 * tmp;
endfunction
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / DSP_PREADD
// /___/ /\ Filename : DSP_PREADD.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_PREADD
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output [26:0] AD,
input ADDSUB,
input [26:0] D_DATA,
input INMODE2,
input [26:0] PREADD_AB
);
// define constants
localparam MODULE_NAME = "DSP_PREADD";
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
// begin behavioral model
wire [26:0] D_DATA_mux;
//*********************************************************
//*** Preaddsub AD
//*********************************************************
assign D_DATA_mux = INMODE2 ? D_DATA : 27'b0;
assign AD = ADDSUB ? (D_DATA_mux - PREADD_AB) : (D_DATA_mux + PREADD_AB);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(ADDSUB *> AD) = (0:0:0, 0:0:0);
(D_DATA *> AD) = (0:0:0, 0:0:0);
(INMODE2 *> AD) = (0:0:0, 0:0:0);
(PREADD_AB *> AD) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> struct vertex { long long x, y; int adj[4], k; } vv[30]; void dfs(int p, int v, long long x, long long y, long long a, int d) { int i; vv[v].x = x; vv[v].y = y; d = (d + 2) % 4; for (i = 0; i < vv[v].k; i++) if (vv[v].adj[i] != p) { long long x_ = x, y_ = y; d = (d + 1) % 4; if (d == 0) x_ += a; else if (d == 1) y_ += a; else if (d == 2) x_ -= a; else y_ -= a; dfs(v, vv[v].adj[i], x_, y_, a / 2, d); } } int main() { int n, i, yes; scanf( %d , &n); yes = 1; for (i = 0; i < n; i++) vv[i].k = 0; for (i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); u--, v--; if (vv[u].k == 4 || vv[v].k == 4) { yes = 0; break; } vv[u].adj[vv[u].k++] = v; vv[v].adj[vv[v].k++] = u; } printf( %s n , yes ? YES : NO ); if (yes) { dfs(-1, 0, 0, 0, 1LL << n, 0); for (i = 0; i < n; i++) printf( %lld %lld n , vv[i].x, vv[i].y); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
|
// megafunction wizard: %RAM: 3-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt3pram
// ============================================================
// File Name: regfile.v
// Megafunction Name(s):
// alt3pram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module regfile (
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
enable,
qa,
qb);
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
input [4:0] rdaddress_b;
input wren;
input clock;
input enable;
output [31:0] qa;
output [31:0] qb;
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] qa = sub_wire0[31:0];
wire [31:0] qb = sub_wire1[31:0];
alt3pram alt3pram_component (
.inclocken (enable),
.wren (wren),
.inclock (clock),
.data (data),
.rdaddress_a (rdaddress_a),
.wraddress (wraddress),
.rdaddress_b (rdaddress_b),
.qa (sub_wire0),
.qb (sub_wire1));
defparam
alt3pram_component.intended_device_family = "Cyclone",
alt3pram_component.width = 32,
alt3pram_component.widthad = 5,
alt3pram_component.indata_reg = "INCLOCK",
alt3pram_component.write_reg = "INCLOCK",
alt3pram_component.rdaddress_reg_a = "INCLOCK",
alt3pram_component.rdaddress_reg_b = "INCLOCK",
alt3pram_component.rdcontrol_reg_a = "UNREGISTERED",
alt3pram_component.rdcontrol_reg_b = "UNREGISTERED",
alt3pram_component.outdata_reg_a = "UNREGISTERED",
alt3pram_component.outdata_reg_b = "UNREGISTERED",
alt3pram_component.indata_aclr = "OFF",
alt3pram_component.write_aclr = "OFF",
alt3pram_component.rdaddress_aclr_a = "OFF",
alt3pram_component.rdaddress_aclr_b = "OFF",
alt3pram_component.rdcontrol_aclr_a = "OFF",
alt3pram_component.rdcontrol_aclr_b = "OFF",
alt3pram_component.outdata_aclr_a = "OFF",
alt3pram_component.outdata_aclr_b = "OFF",
alt3pram_component.lpm_type = "alt3pram",
alt3pram_component.ram_block_type = "AUTO",
alt3pram_component.lpm_hint = "USE_EAB=ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden_a NUMERIC "0"
// Retrieval info: PRIVATE: rden_b NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwrite NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"
// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"
// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"
// Retrieval info: PRIVATE: REGqa NUMERIC "0"
// Retrieval info: PRIVATE: REGqb NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "1"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"
// Retrieval info: PRIVATE: CLRqa NUMERIC "0"
// Retrieval info: PRIVATE: CLRqb NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD NUMERIC "5"
// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"
// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"
// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK"
// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK"
// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF"
// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF"
// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: qa 0 0 32 0 OUTPUT NODEFVAL qa[31..0]
// Retrieval info: USED_PORT: qb 0 0 32 0 OUTPUT NODEFVAL qb[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
// Retrieval info: USED_PORT: rdaddress_a 0 0 5 0 INPUT NODEFVAL rdaddress_a[4..0]
// Retrieval info: USED_PORT: rdaddress_b 0 0 5 0 INPUT NODEFVAL rdaddress_b[4..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC enable
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: qa 0 0 32 0 @qa 0 0 32 0
// Retrieval info: CONNECT: qb 0 0 32 0 @qb 0 0 32 0
// Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @rdaddress_a 0 0 5 0 rdaddress_a 0 0 5 0
// Retrieval info: CONNECT: @rdaddress_b 0 0 5 0 rdaddress_b 0 0 5 0
// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @inclocken 0 0 0 0 enable 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
//--------------------------------------------------------------------------------
// rle_enc.vhd
//
// Copyright (C) 2007 Jonas Diemer
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Run Length Encoder
//
// If enabled, encode the incoming data with the following scheme:
// The MSB (bit 31) is used as a flag for the encoding.
// If the MSB is clear, the datum represents "regular" data
// if set, the datum represents the number of repetitions of the previous data
//
//--------------------------------------------------------------------------------
//
// 01/11/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
// This was basically a total rewrite for cleaner synth.
//
// RLE_MODE: Controls how <value>'s & <rle-count>'s are output.
// 0 : Repeat. <value>'s reissued after every <rle-count> field -and- <rle-count> is inclusive of <value>
// 1 : Always. <value>'s reissued after every <rle-count> field.
// 2 : Periodic. <value>'s reissued approx every 256 <rle-count> fields.
// 3 : Unlimited. <value>'s can be followed by unlimited numbers of <rle-count> fields.
//
`timescale 1ns/100ps
module rle_enc #(
parameter integer DW = 32
)(
// system signals
input wire clk,
input wire rst,
// configuration/control signals
input wire enable,
input wire arm,
input wire [1:0] rle_mode,
input wire [3:0] disabledGroups,
// input stream
input wire [DW-1:0] sti_data,
input wire sti_valid,
// output stream
output reg [DW-1:0] sto_data,
output reg sto_valid = 0
);
localparam RLE_COUNT = 1'b1;
//
// Registers...
//
reg active = 0, next_active;
reg mask_flag = 0, next_mask_flag;
reg [1:0] mode;
reg [30:0] data_mask;
reg [30:0] last_data, next_last_data;
reg last_valid = 0, next_last_valid;
reg [31:0] next_sto_data;
reg next_sto_valid;
reg [30:0] count = 0, next_count; // # of times seen same input data
reg [8:0] fieldcount = 0, next_fieldcount; // # times output back-to-back <rle-counts> with no <value>
reg [1:0] track = 0, next_track; // Track if at start of rle-coutn sequence.
wire [30:0] inc_count = count+1'b1;
wire count_zero = ~|count;
wire count_gt_one = track[1];
wire count_full = (count==data_mask);
reg mismatch;
wire [30:0] masked_sti_data = sti_data & data_mask;
// Repeat mode: In <value><rle-count> pairs, a count of 4 means 4 samples.
// In other words, in repeat mode the count is inclusive of the value.
// When disabled (repitition mode), the count is exclusive.
wire rle_repeat_mode = 0; // (rle_mode==0); // Disabled - modes 0 & 1 now identical
//
// Figure out what mode we're in (8/16/24 or 32 bit)...
//
always @ (posedge clk)
begin
case (disabledGroups)
4'b1110,4'b1101,4'b1011,4'b0111 : mode <= 2'h0; // 8-bit
4'b1100,4'b1010,4'b0110,4'b1001,4'b0101,4'b0011 : mode <= 2'h1; // 16-bit
4'b1000,4'b0100,4'b0010,4'b0001 : mode <= 2'h2; // 24-bit
default : mode <= 2'h3; // 24 or 32-bit
endcase
// Mask to strip off disabled groups. Data must have already been
// aligned (see data_align.v)...
case (mode)
2'h0 : data_mask <= 32'h0000007F;
2'h1 : data_mask <= 32'h00007FFF;
2'h2 : data_mask <= 32'h007FFFFF;
default : data_mask <= 32'h7FFFFFFF;
endcase
end
//
// Control Logic...
//
always @ (posedge clk, posedge rst)
if (rst) begin
active <= 0;
mask_flag <= 0;
end else begin
active <= next_active;
mask_flag <= next_mask_flag;
end
always @ (posedge clk)
begin
count <= next_count;
fieldcount <= next_fieldcount;
track <= next_track;
sto_data <= next_sto_data;
sto_valid <= next_sto_valid;
last_data <= next_last_data;
last_valid <= next_last_valid;
end
always @*
begin
next_active = active | (enable && arm);
next_mask_flag = mask_flag | (enable && arm); // remains asserted even if rle_enable turned off
next_sto_data = (mask_flag) ? masked_sti_data : sti_data;
next_sto_valid = sti_valid;
next_last_data = (sti_valid) ? masked_sti_data : last_data;
next_last_valid = 1'b0;
next_count = count & {31{active}};
next_fieldcount = fieldcount & {9{active}};
next_track = track & {2{active}};
mismatch = |(masked_sti_data^last_data); // detect any difference not masked
if (active)
begin
next_sto_valid = 1'b0;
next_last_valid = last_valid | sti_valid;
if (sti_valid && last_valid)
if (!enable || mismatch || count_full) // if mismatch, or counter full, then output count (if count>1)...
begin
next_active = enable;
next_sto_valid = 1'b1;
next_sto_data = {RLE_COUNT,count};
case (mode)
2'h0 : next_sto_data = {RLE_COUNT,count[6:0]};
2'h1 : next_sto_data = {RLE_COUNT,count[14:0]};
2'h2 : next_sto_data = {RLE_COUNT,count[22:0]};
endcase
if (!count_gt_one) next_sto_data = last_data;
next_fieldcount = fieldcount+1'b1; // inc # times output rle-counts
// If mismatch, or rle_mode demands it, set count=0 (which will force reissue of a <value>).
// Otherwise, set to 1 to avoid thre redundant <value> from being output.
next_count = (mismatch || ~rle_mode[1] || ~rle_mode[0] & fieldcount[8]) ? 0 : 1;
next_track = next_count[1:0];
end
else // match && !count_full
begin
next_count = inc_count;
if (count_zero) // write initial data if count zero
begin
next_fieldcount = 0;
next_sto_valid = 1'b1;
end
if (rle_repeat_mode && count_zero) next_count = 2;
next_track = {|track,1'b1};
end
end
end
endmodule
|
#include <bits/stdc++.h> int main() { char jak[1000005], tak[1000005]; gets(jak); gets(tak); int k, r, i, t, flag = 0, count = 0, fount = 0, f, x, y, j, p = 0; k = strlen(jak); r = strlen(tak); for (i = 0; i < k; i++) { t = jak[i] - 48; if (t != 0 && flag == 0) { flag = 1; x = i; } if (flag == 1) { count++; } } flag = 0; for (i = 0; i < r; i++) { f = tak[i] - 48; if (f != 0 && flag == 0) { flag = 1; y = i; } if (flag == 1) { fount++; } } if (count > fount) { printf( > ); } else if (count < fount) { printf( < ); } else if (count == 0) { printf( = ); } else { for (i = x, j = y; i < k, j < r; i++, j++) { if (jak[i] > tak[j]) { printf( > ); break; } else if (jak[i] < tak[j]) { printf( < ); break; } else { p++; } } if (p == count) { printf( = ); } } } |
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