text
stringlengths 59
71.4k
|
|---|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, r; cin >> n; if (n == 0) { cout << 1 << endl; return 0; } r = n % 4; if (r == 1) { cout << 8 << endl; } else if (r == 2) { cout << 4 << endl; } else if (r == 3) { cout << 2 << endl; } else if (r == 0) { cout << 6 << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 5050; int c, d; char ch[N]; int Calc(int b, int e) { c = 0, d = 0; int ret = 0, i; for (i = b; i <= e; i++) { if (ch[i] == ( ) c++; if (ch[i] == ) ) { if (c) c--; else { if (d > 0) d--, c++; else return ret; } } if (ch[i] == ? ) { if (c) c--, d++; else c++; } if (c == 0) { ret++; } } return ret; } int main() { int n, i, sol = 0; scanf( %s , ch + 1); n = strlen(ch + 1); for (i = 1; i <= n; i++) sol += Calc(i, n); printf( %i n , sol); return 0; } |
#include<bits/stdc++.h> #define fast {ios_base::sync_with_stdio(false);cin.tie(NULL);} using namespace std; const int mxn=2e5+5,mod=1e9+7; int dp[mxn][20],a[mxn],nxt[mxn],n; vector<int>prime_factors[mxn]; void sieve(){ for(int i=2;i<mxn;i++){ if(prime_factors[i].empty()){ nxt[i]=mxn; for(int j=1;i*j<mxn;j++) prime_factors[i*j].push_back(i); } } } void lifting(){ dp[n+1][0]=n+1; for(int i=n;i>=1;i--){ dp[i][0]=dp[i+1][0]; for(auto x:prime_factors[a[i]]){ dp[i][0]=min(dp[i][0],nxt[x]); nxt[x]=i; } } for(int i=1;i<=19;i++){ for(int j=1;j<=n+1;j++) dp[j][i]=dp[dp[j][i-1]][i-1]; } } void solve(){ int q,i,j; cin>>n>>q; for(i=1;i<=n;i++) cin>>a[i]; sieve(); lifting(); while(q--){ int l,r; cin>>l>>r; int ans=0; for(i=19;i>=0;i--){ if(dp[l][i]<=r){ ans+=1<<i; l=dp[l][i]; } } cout<<ans+1<< n ; } } int main(void){ fast; solve(); } |
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
`define NS_DBG_SRC 9
`define NS_DBG_RED 10
module io_1to2
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
OPER_1=`NS_GT_OP,
REF_VAL_1=0,
IS_RANGE=`NS_FALSE,
OPER_2=`NS_GT_OP,
REF_VAL_2=0,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src0_clk,
input wire snk0_clk,
input wire snk1_clk,
input wire reset,
// SRC
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
// SNK_1
`NS_DECLARE_IN_CHNL(i1),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src0_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk0_clk, reset, i0)
`NS_DEBOUNCER_REQ(snk1_clk, reset, i1)
`NS_DECLARE_REG_DBG(rg_dbg)
reg [RSZ-1:0] err_mg_redun = 0;
reg [3:0] cnt_0 = 0;
reg [3:0] cnt_1 = 0;
reg [DSZ-1:0] r_dat1 = 0;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [0:0] ro0_busy = `NS_OFF;
reg [ASZ-1:0] ro0_src = `NS_DBG_SRC;
reg [DSZ-1:0] ro0_dat = 0;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [RSZ-1:0] ro0_red = 0;
reg [0:0] ro0_req = `NS_OFF;
reg [0:0] ro0_err = `NS_OFF;
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp0)
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_back_dat = 15;
//reg [ASZ-1:0] inp0_back_dst = 0;
reg [0:0] inp0_err = `NS_OFF;
// SNK_1 regs
reg [3:0] err1_case = 0;
reg [0:0] has_inp1 = `NS_OFF;
reg [0:0] inp1_has_redun = `NS_OFF;
reg [0:0] inp1_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp1)
wire [RSZ-1:0] inp1_calc_redun;
reg [RSZ-1:0] inp1_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red1 (inp1_src, inp1_dst, inp1_dat, inp1_calc_redun);
reg [0:0] inp1_ack = `NS_OFF;
reg [DSZ-1:0] inp1_back_dat = 15;
reg [0:0] inp1_err = `NS_OFF;
//reg r_curr_src = 0;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
r1 (ro0_src, ro0_dst, ro0_dat, ro0_redun);
//SRC
always @(posedge src0_clk)
begin
if((! ro0_req) && (! o0_ckd_ack)) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
/*if(ro0_dat > 15) begin
ro0_err <= `NS_ON;
end
if(ro0_dat < 0) begin
ro0_err <= `NS_ON;
end*/
if(! `NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, ro0_dst, OPER_2, REF_VAL_2, ro0_dst)) begin
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end else begin
ro0_dat[3:0] <= cnt_1;
cnt_1 <= cnt_1 + 1;
end
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
ro0_req <= `NS_ON;
end
end
if(ro0_req && o0_ckd_ack) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
//SNK_0
always @(posedge snk0_clk)
begin
if(i0_ckd_req && (! inp0_ack)) begin
if(! has_inp0) begin
has_inp0 <= `NS_ON;
`NS_MOV_REG_MSG(inp0, i0)
end
else
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err) begin
if(! `NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, inp0_dst, OPER_2, REF_VAL_2, inp0_dst)) begin
inp0_err <= `NS_ON;
end
else
if(inp0_src != `NS_DBG_SRC) begin
inp0_err <= `NS_ON;
end
/*else
if(inp0_dat > 15) begin
inp0_err <= `NS_ON;
end
else
if(inp0_dat < 0) begin
inp0_err <= `NS_ON;
end*/
else
if(inp0_red != inp0_redun) begin
inp0_err <= `NS_ON;
end
//else
if((inp0_back_dat <= 14) && ((inp0_back_dat + 1) != inp0_dat)) begin
inp0_err <= `NS_ON;
//rg_dbg_disp0 <= inp0_back_dat[3:0];
//rg_dbg_disp1 <= inp0_dat[3:0];
end
else
begin
inp0_back_dat <= inp0_dat;
end
end
end
if(inp0_done_cks) begin
rg_dbg_disp0 <= inp0_dat[3:0];
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
inp0_ack <= `NS_ON;
end
end
else
if((! i0_ckd_req) && inp0_ack) begin
inp0_ack <= `NS_OFF;
end
end
//SNK_1
always @(posedge snk1_clk)
begin
if(i1_ckd_req && (! inp1_ack)) begin
if(! has_inp1) begin
has_inp1 <= `NS_ON;
`NS_MOV_REG_MSG(inp1, i1)
end
else
if(! inp1_has_redun) begin
inp1_has_redun <= `NS_ON;
inp1_redun <= inp1_calc_redun;
end
else
if(! inp1_done_cks) begin
inp1_done_cks <= `NS_ON;
if(! inp1_err) begin
if(`NS_RANGE_CMP_OP(IS_RANGE, OPER_1, REF_VAL_1, inp1_dst, OPER_2, REF_VAL_2, inp1_dst)) begin
inp1_err <= `NS_ON;
end
else
if(inp1_src != `NS_DBG_SRC) begin
inp1_err <= `NS_ON;
end
/*else
if(inp1_dat > 15) begin
inp1_err <= `NS_ON;
end
else
if(inp1_dat < 0) begin
inp1_err <= `NS_ON;
end*/
else
if(inp1_red != inp1_redun) begin
inp1_err <= `NS_ON;
end
//else
if((inp1_back_dat <= 14) && ((inp1_back_dat + 1) != inp1_dat)) begin
inp1_err <= `NS_ON;
end
else
begin
inp1_back_dat <= inp1_dat;
end
end
end
if(inp1_done_cks) begin
rg_dbg_disp1 <= inp1_dat[3:0];
has_inp1 <= `NS_OFF;
inp1_has_redun <= `NS_OFF;
inp1_done_cks <= `NS_OFF;
inp1_ack <= `NS_ON;
end
end
else
if((! i1_ckd_req) && inp1_ack) begin
inp1_ack <= `NS_OFF;
end
end
//DBG
/*
always @(posedge dbg_clk)
begin
case(dbg_case)
8'h30 :
begin
end
endcase
end
*/
//SRC
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = inp0_ack;
//SNK_1
assign i1_ack_out = inp1_ack;
//`NS_ASSIGN_OUT_DBG(dbg, rg_dbg)
assign dbg_leds[0:0] = inp0_err;
assign dbg_leds[1:1] = inp1_err;
assign dbg_leds[2:2] = ro0_err;
assign dbg_leds[3:3] = 0;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule
|
/* Model for xilinx async fifo*/
module fifo_async_104x16
(/*AUTOARG*/
// Outputs
full, prog_full, almost_full, dout, empty, valid,
// Inputs
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104;//104 wide
parameter DEPTH = 16; //
//##########
//# RESET/CLOCK
//##########
input wr_rst; //asynchronous reset
input rd_rst; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
output almost_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
defparam fifo_model.DW=104;
defparam fifo_model.DEPTH=16;
fifo_async_model fifo_model (/*AUTOINST*/
// Outputs
.full (full),
.prog_full (prog_full),
.almost_full (almost_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../../memory/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_never_assert
assert_never_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_never_assume
assert_never_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_never.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_never_assume (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_sync_flops.v,v $
// Revision 1.1 2004/05/21 11:43:25 tadejm
// Added to synchronize RX input to Wishbone clock.
//
//
`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
/*
* Wishbone 2 port multiplexer
*/
module wb_mux_2 #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire rst,
/*
* Wishbone master input
*/
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
/*
* Wishbone slave 0 output
*/
output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
output wire wbs0_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
output wire wbs0_stb_o, // STB_O strobe output
input wire wbs0_ack_i, // ACK_I acknowledge input
input wire wbs0_err_i, // ERR_I error input
input wire wbs0_rty_i, // RTY_I retry input
output wire wbs0_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 0 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
/*
* Wishbone slave 1 output
*/
output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
output wire wbs1_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
output wire wbs1_stb_o, // STB_O strobe output
input wire wbs1_ack_i, // ACK_I acknowledge input
input wire wbs1_err_i, // ERR_I error input
input wire wbs1_rty_i, // RTY_I retry input
output wire wbs1_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 1 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs1_addr_msk // Slave address prefix mask
);
wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
wire wbs0_sel = wbs0_match;
wire wbs1_sel = wbs1_match & ~(wbs0_match);
wire master_cycle = wbm_cyc_i & wbm_stb_i;
wire select_error = ~(wbs0_sel | wbs1_sel) & master_cycle;
// master
assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
wbs1_sel ? wbs1_dat_i :
{DATA_WIDTH{1'b0}};
assign wbm_ack_o = wbs0_ack_i |
wbs1_ack_i;
assign wbm_err_o = wbs0_err_i |
wbs1_err_i |
select_error;
assign wbm_rty_o = wbs0_rty_i |
wbs1_rty_i;
// slave 0
assign wbs0_adr_o = wbm_adr_i;
assign wbs0_dat_o = wbm_dat_i;
assign wbs0_we_o = wbm_we_i & wbs0_sel;
assign wbs0_sel_o = wbm_sel_i;
assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
// slave 1
assign wbs1_adr_o = wbm_adr_i;
assign wbs1_dat_o = wbm_dat_i;
assign wbs1_we_o = wbm_we_i & wbs1_sel;
assign wbs1_sel_o = wbm_sel_i;
assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFBBP_BLACKBOX_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; const int inf = 1e9 + 1; const long long OO = 1e18; long long p1, p2, c1, c2, w1, w2; long long solve() { long long a2, b1, b3, ans = 0; for (int i = 0; i <= min(p1 / w1, c1); i++) { long long a2 = min((p1 - i * w1) / w2, c2); long long b1 = min(p2 / w1, c1 - i); long long b2 = min((p2 - b1 * w1) / w2, c2 - a2); ans = max(ans, i + a2 + b1 + b2); } return ans; } int main() { int t; cin >> t; while (t--) { cin >> p1 >> p2 >> c1 >> c2 >> w1 >> w2; if (w1 > w2) { swap(w1, w2); swap(c1, c2); } cout << solve() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200; const int maxm = maxn * maxn; const int INF = 0x3f3f3f3f; int n, k, s, ans, res; int a[maxn]; int dp[maxn][maxm]; inline int read() { int x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } int main() { if (fopen( D.in , r ) != NULL) { freopen( D.in , r , stdin); freopen( D.out , w , stdout); } n = read(), k = read(), s = read(); s = min(s, n * (n - 1) / 2); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= k; i++) ans += a[i]; memset(dp, INF, sizeof(dp)); dp[0][0] = 0; for (int p = 1; p <= k; p++) for (int i = p - 1; i >= 0; i--) for (int j = s - (k + 1 - p); j >= 0; j--) dp[i + 1][j + k + 1 - p] = min(dp[i + 1][j + k + 1 - p], dp[i][j] - a[p]); for (int p = k + 1; p <= n; p++) for (int i = 1; i <= k; i++) for (int j = s - (p - (k + 1)); j >= 0; j--) dp[i - 1][j + p - (k + 1)] = min(dp[i - 1][j + p - (k + 1)], dp[i][j] + a[p]); for (int i = 0; i <= s; i++) res = min(res, dp[0][i]); printf( %d n , ans + res); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad6676_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [31:0] adc_data;
input adc_or;
// channel interface
output [31:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad6676_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 2010, M = N * N; int n, m, dist[N][N], deg[N][N], fx[N][N], fy[N][N]; char str[N][N]; pair<int, int> p[M]; int hh, tt; bool st[N][N]; void topsort() { hh = 0; tt = -1; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) { dist[i][j] = 1; fx[i][j] = i; fy[i][j] = j; if (!deg[i][j]) p[++tt] = {i, j}; } pair<int, int> u; int x, y, distance; while (hh <= tt) { u = p[hh++]; x = u.first, y = u.second, distance = dist[x][y]; if (str[x][y] == U ) x--; else if (str[x][y] == D ) x++; else if (str[x][y] == L ) y--; else if (str[x][y] == R ) y++; if (x <= 0 || x > n || y <= 0 || y > m) continue; deg[x][y]--; if (!deg[x][y]) p[++tt] = {x, y}; if (dist[x][y] < distance + 1) { dist[x][y] = distance + 1; fx[x][y] = fx[u.first][u.second]; fy[x][y] = fy[u.first][u.second]; } } } void dfs(int x, int y) { if (st[x][y]) return; p[tt++] = {x, y}; st[x][y] = 1; if (str[x][y] == U ) x--; else if (str[x][y] == D ) x++; else if (str[x][y] == L ) y--; else if (str[x][y] == R ) y++; dfs(x, y); } int main() { int T, res, x, y; cin >> T; while (T--) { cin >> n >> m; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) deg[i][j] = st[i][j] = 0; for (int i = 1; i <= n; ++i) { scanf( %s , str[i] + 1); for (int j = 1; j <= m; ++j) { int x = i, y = j; if (str[i][j] == U ) x--; if (str[i][j] == D ) x++; if (str[i][j] == L ) y--; if (str[i][j] == R ) y++; if (x <= 0 || x > n || y <= 0 || y > m) continue; deg[x][y]++; } } topsort(); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (deg[i][j]) { tt = 0; dfs(i, j); for (int k = 0; k < tt; ++k) { int x = p[k].first, y = p[k].second; deg[x][y] = 0; dist[x][y] += tt - 1; } } res = 0; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (res < dist[i][j]) { res = dist[i][j]; x = fx[i][j]; y = fy[i][j]; } cout << x << << y << << res << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1024; int n; int a[maxn], b[maxn], c[maxn]; vector<int> g[maxn]; vector<pair<pair<int, int>, int> > ans; void add(int v, int u, int x) { ans.push_back({{v, u}, x}); } int gfs(int v, int par, int d) { if (g[v].size() == 1) return v; for (int i : g[v]) { int u = a[i] + b[i] - v; if (u != par and u != d) { int res = gfs(u, v, d); if (res != -1) return res; } } return -1; } pair<int, int> gpr(int v, int d) { pair<int, int> ret = {-1, -1}; for (int i : g[v]) { int u = a[i] + b[i] - v; if (u != d) { int l = gfs(u, v, d); if (l != -1) { if (ret.first == -1) ret.first = l; else ret.second = l; } } } return ret; } void see(int v, int u, int x) { pair<int, int> vp = gpr(v, u); pair<int, int> up = gpr(u, v); add(vp.first, up.first, x / 2); add(vp.second, up.second, x / 2); add(vp.first, vp.second, -x / 2); add(up.first, up.second, -x / 2); } void zee(int v, int d, int x) { pair<int, int> vp = gpr(d, v); add(vp.first, v, x / 2); add(vp.second, v, x / 2); add(vp.first, vp.second, -x / 2); } void dfs(int v, int par = -1, int lst = -1, int x = 0) { if (g[v].size() > 2) { if (lst != -1) see(v, lst, x); lst = v; } else if (g[v].size() == 1) { zee(v, lst, x); } for (int i : g[v]) { int u = a[i] + b[i] - v; if (u != par) { dfs(u, v, lst, c[i]); } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n - 1; i++) { cin >> a[i] >> b[i] >> c[i]; a[i]--, b[i]--; g[a[i]].push_back(i); g[b[i]].push_back(i); } for (int i = 0; i < n; i++) if (g[i].size() == 2) { if (c[g[i][0]] != c[g[i][1]]) { cout << NO << endl; return 0; } } cout << YES << endl; vector<int> lv; int r = -1; for (int i = 0; i < n; i++) if (g[i].size() > 2) r = i; else if (g[i].size() == 1) lv.push_back(i); if (r == -1) { cout << 1 << endl; cout << lv[0] + 1 << << lv[1] + 1 << << c[0] << endl; return 0; } dfs(r); cout << ans.size() << endl; for (auto p : ans) cout << p.first.first + 1 << << p.first.second + 1 << << p.second << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long oo = 1000000007; vector<long long> G; bool v[1000010]; long long a[1000010]; long long f[1000010]; long long p, k, i, j, ans; void dfs(long long o, long long st) { v[o] = 1; if (!v[(o * k) % p]) { dfs((o * k) % p, st + 1); } else { G.push_back(st); a[st]++; } } int main() { scanf( %I64d%I64d , &p, &k); if (k == 0) { long long tem = 1; for (i = 1; i < p; ++i) tem = (tem * p) % oo; printf( %I64d n , tem); return 0; } for (i = 0; i < p; ++i) { if (!v[i]) { dfs(i, 1); } } memset(v, 0, sizeof(v)); for (i = 0; i < G.size(); ++i) { if (v[G[i]]) continue; v[G[i]] = 1; for (j = 1; j * j <= G[i]; ++j) { if (G[i] % j) continue; f[G[i]] = (f[G[i]] + a[j] * j) % oo; if (j * j != G[i]) f[G[i]] = (f[G[i]] + (a[G[i] / j] * (G[i] / j)) % oo) % oo; } } ans = 1; for (i = 0; i < G.size(); ++i) { ans = (ans * f[G[i]]) % oo; } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> d[256]; int mask[256]; vector<int> q; bool b[256]; bool good[256]; int kd[256]; vector<int> g; vector<pair<pair<int, int>, pair<int, int> > > res; int n; int need; void Debug(vector<int> A) { for (int i = 0; i < A.size(); i++) { printf( %d , A[i]); } puts( ); } int read() { char ch = ; int x = 0; while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x; } void Init() { n = read(); for (int i = 0; i < n; i++) { int x = read(); need = need | (1 << x); b[x] = true; } if (n > 6) { puts( 0 ); exit(0); } for (int i = 255; i >= 0; i--) { good[i] = true; int x = i; mask[i] = 0; while (x > 0) { mask[i] = mask[i] | (1 << (x % 10)); if (!b[x % 10]) good[i] = false; d[i].push_back(x % 10); x = x / 10; } if (i == 0 and !b[i]) good[i] = false; if (i == 0) { d[i].push_back(0); mask[i] = mask[i] | 1; } if (good[i]) g.push_back(i); } } void Solve() { for (int x = 0; x < 256; x++) { if (good[x]) { for (int y = 0; y < 256; y++) { if (good[y]) { for (int w = 0; w < 256; w++) { if (good[w]) { if ((mask[x] | mask[y] | mask[w]) != need) continue; for (int z = 0; z < 256; z++) { if (good[z]) { q.clear(); for (int i = d[x].size() - 1; i >= 0; i--) q.push_back(d[x][i]); for (int i = d[y].size() - 1; i >= 0; i--) q.push_back(d[y][i]); for (int i = d[w].size() - 1; i >= 0; i--) q.push_back(d[w][i]); for (int i = d[z].size() - 1; i >= 0; i--) q.push_back(d[z][i]); bool ok = true; for (int i = 0; i < q.size(); i++) { if (q[i] != q[q.size() - 1 - i]) { ok = false; break; } } if (ok) res.push_back(make_pair(make_pair(x, y), make_pair(w, z))); } } } } } } } } } void Print() { printf( %d n , res.size()); for (int i = 0; i < res.size(); i++) { printf( %d.%d.%d.%d n , res[i].first.first, res[i].first.second, res[i].second.first, res[i].second.second); } } int main() { Init(); Solve(); Print(); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 gen(time(NULL)); const long double eps = 1e-9; const int inf = 1e9; const int mod = 1e9 + 7; const long long infinity = 2 * 1e18; vector<int> g[100005]; int n, m, q; int p2[100005], d[100005], cmp[100005]; int rt[100005]; vector<int> plen[100005]; vector<int> cs[100005]; vector<long long> csp[100005]; int s[100005]; void dfs_cl(int u, int e, int cl) { cmp[u] = cl; cs[cl].push_back(u); for (auto v : g[u]) if (v != e) dfs_cl(v, u, cl); } int dfs(int u, int e) { for (auto v : g[u]) if (v != e) plen[u].push_back(dfs(v, u) + 1); int maxc = 0; sort(plen[u].begin(), plen[u].end(), greater<int>()); for (auto v : plen[u]) maxc = max(v, maxc); if (plen[u].size()) { if (plen[u].size() == 1) d[cmp[u]] = max(d[cmp[u]], plen[u].back()); else d[cmp[u]] = max(d[cmp[u]], plen[u][0] + plen[u][1]); } return p2[u] = maxc; } void path(int u, int e, int carry) { p2[u] = max(p2[u], carry); if (plen[u].size() <= 1) { for (auto v : g[u]) if (v != e) path(v, u, carry + 1); return; } for (auto v : g[u]) if (v != e) { int x = p2[v] + 1; int t = 0; if (x == plen[u][0]) t++; path(v, u, max(carry + 1, plen[u][t] + 1)); } } map<pair<int, int>, double> memo; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> q; int u, v; for (int i = 0; i < m; i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } int cl = 0; for (int i = 1; i <= n; i++) if (!cmp[i]) { dfs_cl(i, i, ++cl); rt[cl] = i; } for (int i = 1; i <= n; i++) s[cmp[i]]++; for (int i = 1; i <= cl; i++) dfs(rt[i], -1); for (int i = 1; i <= cl; i++) path(rt[i], -1, 0); for (int i = 1; i <= cl; i++) sort(cs[i].begin(), cs[i].end(), [&](int a, int b) { return p2[a] < p2[b]; }); for (int i = 1; i <= cl; i++) for (auto v : cs[i]) csp[i].push_back(csp[i].size() ? csp[i].back() + p2[v] + 1 : p2[v] + 1); for (int i = 0; i < q; i++) { cin >> u >> v; u = cmp[u], v = cmp[v]; if (u == v) cout << -1 << n ; else { if (s[u] > s[v]) swap(u, v); if (memo.count(make_pair(u, v))) cout << memo[make_pair(u, v)] << n ; else { long long ans = 0; int dp = max(d[u], d[v]); for (auto x : cs[u]) { if (cs[v].size() == 1) { ans += max(dp, p2[x] + p2[cs[v].back()] + 1); continue; } int l = -1, r = cs[v].size() - 1; while (l < r - 1) { int m = (l + r) / 2; if (p2[cs[v][m]] + p2[x] + 1 < dp) l = m; else r = m; } ans += (r * 1LL * dp + p2[x] * 1LL * (s[v] - r) + csp[v].back() - (r ? csp[v][r - 1] : 0)); } memo[make_pair(u, v)] = (double)ans / (s[v] * 1LL * s[u]); cout << fixed << setprecision(10) << memo[make_pair(u, v)] << n ; } } } } |
#include <bits/stdc++.h> int const INF = 2e9; int const MOD = 1000000007; int const MAXN = 100010; using namespace std; int n, m, sum1, sum2, ans; int a[MAXN], b[MAXN]; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int j = 0; j < m; j++) cin >> b[j]; int i = 1, j = 1; sum1 = a[0], sum2 = b[0]; while (true) { if (sum1 < sum2) sum1 += a[i], i++; else if (sum2 < sum1) sum2 += b[j], j++; else { if (i == n && j == m) { ans++; break; } else sum1 = a[i], sum2 = b[j], i++, j++, ans++; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int64_t *arry[3]; int main(void) { int64_t n, p, q, r; cin >> n >> p >> q >> r; for (int i = 0; i < 3; i++) { arry[i] = (int64_t *)malloc(sizeof(int64_t) * n); } for (int i = 0; i < n; i++) { int buf; cin >> buf; arry[0][i] = buf * p; arry[1][i] = buf * q; arry[2][i] = buf * r; } { int64_t *pt = (int64_t *)malloc(sizeof(int64_t) * n); pt[n - 1] = arry[2][n - 1]; for (int i = n - 1; i > 0; i--) { pt[i - 1] = max(pt[i], arry[2][i - 1]); } free(arry[2]); arry[2] = pt; } { int64_t *pt = (int64_t *)malloc(sizeof(int64_t) * n); for (int i = 0; i < n; i++) { pt[i] = arry[1][i] + arry[2][i]; } free(arry[1]); arry[1] = pt; } { int64_t *pt = (int64_t *)malloc(sizeof(int64_t) * n); pt[0] = *arry[0]; for (int i = 1; i < n; i++) { pt[i] = max(pt[i - 1], arry[0][i]); } free(arry[0]); arry[0] = pt; } int64_t max = arry[0][0] + arry[1][0]; for (int i = 1; i < n; i++) { int64_t buf = arry[0][i] + arry[1][i]; if (buf > max) max = buf; } cout << max << endl; for (int i = 0; i < 3; i++) { free(arry[i]); } } |
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "hi_iso14443a.v"
`include "relay.v"
`include "relay_test.v"
`include "util.v"
`define SNIFFER 3'b000
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
`define FAKE_READER 3'b101
`define FAKE_TAG 3'b110
module fpga(
spck, miso, mosi, ncs,
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spck, mosi, ncs;
output miso;
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
input dbg;
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg = 16'b0;
reg [7:0] divisor = 8'b0;
reg [7:0] conf_word = 8'b0;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire major_mode;
assign major_mode = conf_word[5];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
wire [2:0] relay_mod_type;
wire [2:0] mod_type;
wire hisn_ssp_dout;
wire relay_out;
wire relay_active = (hi_simulate_mod_type == `FAKE_READER || hi_simulate_mod_type == `FAKE_TAG || hi_simulate_mod_type == 3'b111);
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, hisn_ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
,
mod_type
);
relay r(
ck_1356meg,
~relay_active,
dbg,
hi_simulate_mod_type,
relay_mod_type,
relay_out,
hisn_ssp_din,
relay_relay
);
relay_test rt(
pck0, ck_1356meg, ck_1356megb,
rt_ssp_frame, rt_ssp_din, ssp_dout, rt_ssp_clk,
dbg, rt_data_out,
hi_simulate_mod_type
);
mux2 mux_ssp_clk (major_mode, ssp_clk, hisn_ssp_clk, rt_ssp_clk);
mux2 mux_ssp_din (major_mode, ssp_din, hisn_ssp_din, rt_ssp_din);
mux2 mux_ssp_frame (major_mode, ssp_frame, hisn_ssp_frame, rt_ssp_frame);
mux2 mux_pwr_oe1 (major_mode, pwr_oe1, hisn_pwr_oe1, 1'b0);
mux2 mux_pwr_oe2 (major_mode, pwr_oe2, hisn_pwr_oe2, 1'b0);
mux2 mux_pwr_oe3 (major_mode, pwr_oe3, hisn_pwr_oe3, 1'b0);
mux2 mux_pwr_oe4 (major_mode, pwr_oe4, hisn_pwr_oe4, 1'b0);
mux2 mux_pwr_lo (major_mode, pwr_lo, relay_relay, rt_data_out);
mux2 mux_pwr_hi (major_mode, pwr_hi, hisn_pwr_hi, 1'b0);
mux2 mux_adc_clk (major_mode, adc_clk, hisn_adc_clk, 1'b0);
assign mod_type = relay_active ? relay_mod_type : hi_simulate_mod_type;
assign hisn_ssp_dout = relay_active ? relay_out : ssp_dout;
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int n, m; long long c[maxn], ans, s; vector<int> g[maxn]; bool v[maxn]; void dfs(int a) { s = min(s, c[a]); v[a] = 1; for (int i = 0; i < g[a].size(); i++) { int b = g[a][i]; if (!v[b]) dfs(b); } } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %lld , &c[i]); for (int i = 1; i <= m; i++) { int x, y; scanf( %d %d , &x, &y); g[x].push_back(y); g[y].push_back(x); } ans = 0; for (int i = 1; i <= n; i++) { if (v[i]) continue; s = (1e9) + 1; dfs(i); ans += s; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } int ara[55][55]; void solve() { int n; cin >> n; vector<pair<int, int> > odds; map<pair<int, int>, int> done; for (int i = 1; i <= n; i++) { odds.push_back({i, n / 2 + 1}); done[{i, n / 2 + 1}] = 1; } for (int j = 1; j <= n; j++) { if (!done[{n / 2 + 1, j}]) odds.push_back({n / 2 + 1, j}); done[{n / 2 + 1, j}] = 1; } for (int k = 1; k <= n / 2; k++) { int i = k; int j = 1; while (i < n && j < n) { if (!done[{i, j}]) { odds.push_back({i, j}); done[{i, j}] = 1; } if (!done[{i, n - j + 1}]) { odds.push_back({i, n - j + 1}); done[{i, n - j + 1}] = 1; } if (!done[{n - i + 1, j}]) { odds.push_back({n - i + 1, j}); done[{n - i + 1, j}] = 1; } if (!done[{n - i + 1, n - j + 1}]) { odds.push_back({n - i + 1, n - j + 1}); done[{n - i + 1, n - j + 1}] = 1; } i++; j++; } } for (int i = 0, k = 1; k <= n * n; k += 2, i++) { int x = odds[i].first; int y = odds[i].second; ara[x][y] = k; } for (int i = 1, k = 2; i <= n; i++) { for (int j = 1; j <= n; j++) { if (!ara[i][j]) { ara[i][j] = k; k += 2; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) cout << ara[i][j] << ; cout << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[111111], b[111111], n, m, k; int main() { while (scanf( %d%d%d , &n, &m, &k) != EOF) { for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= m; i++) scanf( %d , &b[i]); sort(a + 1, a + 1 + n); sort(b + 1, b + 1 + m); bool yes = 0; for (int i = 0; i <= max(n, m); i++) { if (n - i < 1 || m - i < 1) break; if (a[n - i] > b[m - i]) { yes = 1; printf( YES n ); break; } } if (yes) continue; if (n > m) printf( YES n ); else printf( NO n ); } } |
module fa1242(
output ml,
output md,
output mc,
output rstb,
input clk_s, // should be slower than 5Mhz
input rst);
parameter IDLE = 0;
parameter RST = 1;
parameter RST_WAIT = 2;
parameter SET_FUNCTION = 3;
parameter SET_FUNCTION_WAIT = 4;
// attn settings
wire [10:0] al = 0;
wire [10:0] ar = 0;
// mode settings
wire [1:0] om = 2'b0; // outlp: L, outlm: -L, outrp: R, outrm: -R
wire [1:0] bit = 2'b10; // 24bit
wire [1:0] zm = 2'b0; // open drain + pull up
wire atc = 2'b0; // attn. common for LR (off)
wire mute = 2'b0; // unmute
wire [1:0] emph = 2'b0; // no de-emphasis
// for reset
reg [4:0] wait_counter;
parameter WAIT_COUNTER_MAX = 5'h1f;
// for mode set
reg [1:0] mode;
reg [4:0] mode_set_counter;
// FSM transition
reg [3:0] state;
initial state = IDLE;
always @(posedge clk_s or rst) begin
if(rst) begin
state <= RST;
wait_counter <= 0;
mode_set_counter <= 0;
end else begin
case(state)
IDLE: state <= IDLE;
RST: begin
state <= RST_WAIT;
wait_counter <= 0;
end
RST_WAIT: begin
if(wait_counter == WAIT_COUNTER_MAX) begin
state <= SET_FUNCTION;
mode <= 2'd0;
mode_set_counter <= 2'd0;
end else begin
wait_counter <= wait_counter + 1;
end
end
SET_FUNCTION: begin
if(mode_set_counter == 5'h1f) begin
mode_set_counter <= 0;
state <= SET_FUNCTION_WAIT;
wait_counter <= 0;
end else
mode_set_counter <= mode_set_counter + 1;
end
SET_FUNCTION_WAIT: begin
if(wait_counter == WAIT_COUNTER_MAX) begin
if(mode == 2'd2)
// all done!
state <= IDLE;
else begin
// set next mode vector
state <= SET_FUNCTION;
mode <= mode + 1;
mode_set_counter <= 2'd0;
end
end else begin
wait_counter <= wait_counter + 1;
end
end
default: state <= IDLE;
endcase
end
end
assign rstb = (state == RST);
assign mc = mode_set_counter[0];
assign ml = ~((state == SET_FUNCTION_WAIT) && (wait_counter == 2));
function mode_set_data(
input [3:0] mode_set_idx,
input [1:0] mode);
reg [10:0] mode3;
begin
mode3 = {om, /*rst*/1'b0, bit, zm, atc, mute, emph};
if(mode_set_idx < 5)
case(mode_set_idx)
// res
4'd00: mode_set_data = 0;
4'd01: mode_set_data = 0;
4'd02: mode_set_data = 0;
// mode
4'd03: mode_set_data = mode[1];
4'd04: mode_set_data = mode[0];
endcase
else
case(mode)
2'd0: mode_set_data = al[10+5-mode_set_idx];
2'd1: mode_set_data = ar[10+5-mode_set_idx];
2'd2: mode_set_data = mode3[10+5-mode_set_idx];
endcase
end
endfunction
assign md = mode_set_data(mode_set_counter[4:1], mode);
endmodule
|
module Control (
input irq, PC31,
input [5:0] OpCode, Funct,
output [2:0] PCSrc,
output [1:0] RegDst, MemtoReg, //nextPC,
output RegWrite, ALUSrc1, ALUSrc2, Branch,
MemWrite, MemRead, ExtOp, LuOp, Sign,
output reg Jump,
//output [3:0] ALUOp,
output reg [5:0] ALUFun
);
wire EXC; // no operation exception
reg [5:0] f;
parameter ALUadd = 6'b000_000;
parameter ALUsub = 6'b000_001;
parameter ALUand = 6'b011_000;
parameter ALUor = 6'b011_110;
parameter ALUxor = 6'b010_110;
parameter ALUnor = 6'b010_001;
parameter ALUnop = 6'b011_010;
parameter ALUsll = 6'b100_000;
parameter ALUsrl = 6'b100_001;
parameter ALUsra = 6'b100_011;
parameter ALUeq = 6'b110_011;
parameter ALUneq = 6'b110_001;
parameter ALUlt = 6'b110_101;
parameter ALUlez = 6'b111_101;
parameter ALUgez = 6'b111_001;
parameter ALUgtz = 6'b111_111;
assign EXC = ~( ( OpCode <= 6'hd && OpCode >= 6'h1 ) || (OpCode == 6'hf || OpCode == 6'h23 || OpCode == 6'h2b) ||
( OpCode == 6'h0 && (Funct == 6'h8 || Funct == 6'h9 || Funct == 6'h0 || Funct == 6'h2 || Funct == 6'h3 || (Funct >= 6'h20 && Funct <= 6'h27) || Funct == 6'h2a || Funct == 6'h2b ) ) );
assign PCSrc = (~PC31&irq) ? 3'h4 : // Interrupt
(~PC31&EXC) ? 3'h5 : // Exception
(OpCode == 6'h00) ? ( (Funct == 6'h08)|(Funct == 6'h09) ? 3'h3 : 3'h0 ) : // R: jr jalr 3
(OpCode == 6'h02 || OpCode == 6'h03) ? 3'h2 : // J
(OpCode == 6'h01 || (OpCode > 6'h03 && OpCode < 6'h08)) ? 3'h1 : // branch
3'h0 ; // I
// assign nextPC = (OpCode == 6'h00) ? ( (Funct == 6'h08)|(Funct == 6'h09) ? 2'h3 : 2'h0 ) : // R: jr jalr 3
// (OpCode == 6'h02 || OpCode == 6'h03) ? 2'h2 : // J
// (OpCode == 6'h01 || (OpCode > 6'h03 && OpCode < 6'h08)) ? 2'h1 : // branch
// 2'h0 ;
assign Branch = (OpCode <= 6'h07 && OpCode >= 6'h4)|(OpCode == 6'h1)|(OpCode == 6'h00 && (Funct == 6'h8 || Funct == 6'h9)) ? 1'b1 : 1'b0;
always @ (*)
case (OpCode)
6'h2: Jump = 1'h1;
6'h3: Jump = 1'h1;
6'h0: Jump = (Funct == 6'h8 || Funct == 6'h9) ? 1'h1 : 1'h0;
default: Jump = 1'h0;
endcase
assign RegWrite = (~PC31&irq)|(~PC31&EXC) ? 1'b1 :
(OpCode == 6'h01 || OpCode == 6'h02 || OpCode == 6'h04 || OpCode == 6'h05 || OpCode == 6'h06 || OpCode == 6'h07 || OpCode == 6'h2b || (OpCode==6'h00 && Funct==6'h08)) ? 1'b0 : 1'b1;
assign RegDst = (~PC31&irq)|(~PC31&EXC) ? 2'h3 :
(OpCode == 6'h23 || OpCode == 6'hf || OpCode == 6'h8 || OpCode == 6'h9 || OpCode == 6'hc || OpCode == 6'hd || OpCode == 6'ha || OpCode == 6'hb) ? 2'h1 :
(OpCode == 6'h03 || (OpCode == 6'h0 && Funct == 6'h9) ) ? 2'h2 :
2'h0 ;
assign MemRead = (~PC31&irq) ? 1'b0 :
(OpCode == 6'h23) ? 1'b1 : 1'b0;
assign MemWrite = (OpCode == 6'h2b) ? 1'b1 : 1'b0;
assign MemtoReg = (~PC31&irq) ? 2'h0 :
(~PC31&EXC) ? 2'h2 :
(OpCode == 6'h23) ? 2'h1 :
( OpCode == 6'h03 || (OpCode==6'h00 && (Funct == 6'h08 || Funct == 6'h09)) ) ? 2'h2 :
2'h0 ;
assign ALUSrc1 = (~PC31&irq) ? 1'b0 :
(OpCode == 6'h00) ? ( (Funct == 6'h0 || Funct == 6'h2 || Funct == 6'h3) ? 1'b1 : 1'b0 ) : 1'b0;
assign ALUSrc2 = (~PC31&irq) ? 1'b0 :
(OpCode == 6'h00 || (OpCode >= 6'h1 && OpCode <= 6'h7) ) ? 1'b0 : 1'b1;
assign ExtOp = (OpCode == 6'h0) ? ( (Funct == 6'h20 || Funct == 6'h22 || Funct == 6'h2a || Funct == 6'h8) ? 1'b1 : 1'b0 ) :
( (OpCode == 6'h23 || OpCode == 6'h2b || OpCode == 6'h8 || OpCode == 6'h1 || OpCode == 6'ha || (OpCode >= 6'h4 && OpCode <= 6'h7) ) ? 1'b1 : 1'b0 );
assign LuOp = (OpCode == 6'h0f) ? 1'b1 : 1'b0;
assign Sign = ExtOp;
always @ (*)
case (Funct)
6'd32: f = ALUadd;
6'd33: f = ALUadd;
6'd34: f = ALUsub;
6'd35: f = ALUsub;
6'd36: f = ALUand;
6'd37: f = ALUor;
6'd38: f = ALUxor;
6'd39: f = ALUnor;
6'd0 : f = ALUsll;
6'd2 : f = ALUsrl;
6'd3 : f = ALUsra;
6'd42: f = ALUlt;
6'd43: f = ALUlt;
6'd8 : f = ALUadd;
6'd9 : f = ALUadd;
default : f = ALUnop;
endcase
always @ (*)
if (~PC31&irq)
ALUFun = ALUadd;
else
case (OpCode)
6'h00: ALUFun = f;
6'h23: ALUFun = ALUadd;
6'h2b: ALUFun = ALUadd;
6'h0f: ALUFun = ALUadd;
6'h08: ALUFun = ALUadd;
6'h09: ALUFun = ALUadd;
6'h0c: ALUFun = ALUand;
6'h0d: ALUFun = ALUor;
6'h0a: ALUFun = ALUlt;
6'h0b: ALUFun = ALUlt;
6'h04: ALUFun = ALUeq;
6'h05: ALUFun = ALUneq;
6'h06: ALUFun = ALUlez;
6'h07: ALUFun = ALUgtz;
6'h01: ALUFun = ALUgez;
6'h02: ALUFun = ALUadd;
6'h03: ALUFun = ALUadd;
default : ALUFun = ALUnop; // through
endcase
endmodule
|
module test_LEDState(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-ST LED Control.
output [23:0] aso_fled0_data,
output aso_fled0_valid,
//Avalon-ST LED Control.
output [23:0] aso_fled1_data,
output aso_fled1_valid,
//Avalon-ST LED Control.
output [23:0] aso_fled2_data,
output aso_fled2_valid,
//Avalon-ST LED Control.
output [23:0] aso_fled3_data,
output aso_fled3_valid
);
assign aso_fled0_valid = 1;
assign aso_fled0_data = {r_cnt, g_cnt, b_cnt};
assign aso_fled1_valid = 1;
assign aso_fled1_data = {g_cnt, b_cnt, r_cnt};
assign aso_fled2_valid = 1;
assign aso_fled2_data = {b_cnt, r_cnt, g_cnt};
assign aso_fled3_valid = 1;
assign aso_fled3_data = {g_cnt, r_cnt, b_cnt};
reg [5:0] state;
reg [7:0] r_cnt, g_cnt, b_cnt;
reg [18:0] delay_cnt;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
state <= 0;
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
end
else begin
case(state)
0: begin
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) r_cnt <= r_cnt + 1;
if(r_cnt == 255) state <= 1;
end
1: begin
delay_cnt <= 0;
state <= 2;
end
2: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) r_cnt <= r_cnt - 1;
if(r_cnt == 0) state <= 3;
end
3: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 4;
end
4: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) g_cnt <= g_cnt + 1;
if(g_cnt == 255) state <= 5;
end
5: begin
delay_cnt <= 0;
state <= 6;
end
6: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) g_cnt <= g_cnt - 1;
if(g_cnt == 0) state <= 7;
end
7: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 8;
end
8: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) b_cnt <= b_cnt + 1;
if(b_cnt == 255) state <= 9;
end
9: begin
delay_cnt <= 0;
state <= 10;
end
10: begin
delay_cnt <= delay_cnt + 1;
if(delay_cnt == 19'h7FFFF) b_cnt <= b_cnt - 1;
if(b_cnt == 0) state <= 11;
end
11: begin
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
state <= 0;
end
default: begin
state <= 0;
r_cnt <= 0;
g_cnt <= 0;
b_cnt <= 0;
delay_cnt <= 0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int sol[] = {19, 873, 834, 665}; int main() { int a, b; bool found = false; cin >> a >> b; for (int i = 0; i < (int)sizeof(sol) / (int)sizeof(int); i++) { found = true; break; } if (found) cout << a + b << endl; else cout << 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int n, x; scanf( %d%d , &n, &x); int sum = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); sum += a[i]; } if (n == 1) { if (a[0] == x) printf( YES n ); else printf( NO n ); return 0; } if (sum + n - 1 == x) printf( YES n ); else printf( NO n ); } |
#include <bits/stdc++.h> using namespace std; int num[105]; double cal(int w, int e, int s) { if (e < s) return 1.0; double res = 1, dw = (double)w, de = (double)e; for (int i = 0; i < s; i++) { res = res * de / dw; dw--; de--; } return 1.0 - res; } int main() { int n, m, h; int s; while (~scanf( %d%d%d , &n, &m, &h)) { s = 0; for (int i = 1; i <= m; i++) { scanf( %d , &num[i]); s += num[i]; } if (s < n) printf( -1.0 n ); else { printf( %.7lf n , cal(s - 1, s - num[h], n - 1)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1LL << 28; const long long mod = 1LL; vector<int> adj[30]; long long b_search(int val, int indx) { int lo, hi, mid; long long ans = 1e12; lo = 0; hi = (int)adj[indx].size() - 1; while (lo <= hi) { mid = (lo + hi) / 2; if (adj[indx][mid] == val) return 0; if (adj[indx][mid] < val) lo = mid + 1; else hi = mid - 1; ans = min(ans, (long long)abs(val - adj[indx][mid])); } return ans; } int main() { int n, k, i, j; long long l; string s, c; while (scanf( %d %d , &n, &k) == 2) { for (i = 0; i < 26; i++) adj[i].clear(); cin >> s; for (i = 0; i < s.length(); i++) { adj[s[i] - a ].push_back(i); } while (n--) { l = 0; cin >> c; for (i = 0; i < c.length(); i++) { if ((int)adj[c[i] - a ].size() == 0) l += (int)c.size(); else l += b_search(i, c[i] - a ); } printf( %I64d n , l); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; int main() { int n, k, sol = 0; cin >> n >> k; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); int maxB = (a[n - 1] - a[0]) / (k - 1); vector<int> ble(maxB + 2); vector<vector<int>> b(n + 1); for (int i = 1; i <= maxB; i++) { b[0] = vector<int>(k + 1); b[0][0] = 1; int p = 0; for (int j = 1; j <= n; j++) { while (a[p] <= a[j - 1] - i) p++; b[j] = b[j - 1]; for (int l = 0; l < k; l++) { b[j][l + 1] = (b[j][l + 1] + b[p][l]) % mod; if (b[j][l + 1] == 0) break; } } ble[i] = b[n][k]; } for (int i = 0; i <= maxB; i++) sol = (sol + i * (long long)(ble[i] - ble[i + 1]) + mod) % mod; cout << sol << endl; return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip
*/
module test_ip;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [7:0] s_eth_payload_axis_tdata = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg arp_request_ready = 0;
reg arp_response_valid = 0;
reg arp_response_error = 0;
reg [47:0] arp_response_mac = 0;
reg s_ip_hdr_valid = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [7:0] s_ip_payload_axis_tdata = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
reg m_ip_hdr_ready = 0;
reg m_ip_payload_axis_tready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [7:0] m_eth_payload_axis_tdata;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire arp_request_valid;
wire [31:0] arp_request_ip;
wire arp_response_ready;
wire m_ip_hdr_valid;
wire [47:0] m_ip_eth_dest_mac;
wire [47:0] m_ip_eth_src_mac;
wire [15:0] m_ip_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [7:0] m_ip_payload_axis_tdata;
wire m_ip_payload_axis_tvalid;
wire m_ip_payload_axis_tlast;
wire m_ip_payload_axis_tuser;
wire rx_busy;
wire tx_busy;
wire rx_error_header_early_termination;
wire rx_error_payload_early_termination;
wire rx_error_invalid_header;
wire rx_error_invalid_checksum;
wire tx_error_payload_early_termination;
wire tx_error_arp_failed;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
arp_request_ready,
arp_response_valid,
arp_response_error,
arp_response_mac,
s_ip_hdr_valid,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_ttl,
s_ip_protocol,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
m_ip_hdr_ready,
m_ip_payload_axis_tready,
local_mac,
local_ip
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
arp_request_valid,
arp_request_ip,
arp_response_ready,
m_ip_hdr_valid,
m_ip_eth_dest_mac,
m_ip_eth_src_mac,
m_ip_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_ip_payload_axis_tdata,
m_ip_payload_axis_tvalid,
m_ip_payload_axis_tlast,
m_ip_payload_axis_tuser,
rx_busy,
tx_busy,
rx_error_header_early_termination,
rx_error_payload_early_termination,
rx_error_invalid_header,
rx_error_invalid_checksum,
tx_error_payload_early_termination,
tx_error_arp_failed
);
// dump file
$dumpfile("test_ip.lxt");
$dumpvars(0, test_ip);
end
ip
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Status signals
.rx_busy(rx_busy),
.tx_busy(tx_busy),
.rx_error_header_early_termination(rx_error_header_early_termination),
.rx_error_payload_early_termination(rx_error_payload_early_termination),
.rx_error_invalid_header(rx_error_invalid_header),
.rx_error_invalid_checksum(rx_error_invalid_checksum),
.tx_error_payload_early_termination(tx_error_payload_early_termination),
.tx_error_arp_failed(tx_error_arp_failed),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, q, a[300005], ans[300005]; vector<pair<int, int> > queries[300005]; int tree[1200006]; void upd(int l, int r, int pos, int x) { if (l == r) { tree[pos]++; return; } int mid = l + r >> 1; if (x <= mid) upd(l, mid, pos << 1, x); else upd(mid + 1, r, pos << 1 | 1, x); tree[pos]++; } int query(int l, int r, int pos, int x) { if (l == r) return r; int mid = l + r >> 1; if (tree[pos << 1] >= x) return query(l, mid, pos << 1, x); else return query(mid + 1, r, pos << 1 | 1, x - tree[pos << 1]); } int query1(int l, int r, int pos, int ql, int qr) { if (l >= ql && r <= qr) return tree[pos]; if (l > qr || r < ql) return 0; int mid = l + r >> 1; return query1(l, mid, pos << 1, ql, qr) + query1(mid + 1, r, pos << 1 | 1, ql, qr); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> q; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 0; i < q; i++) { int x, y; cin >> x >> y; queries[n - y].push_back({x, i}); } for (int i = 1; i <= n; i++) { if (a[i] > i) upd(0, n, 1, 0); else if (a[i] == i) upd(0, n, 1, i); else { int x = query(0, n, 1, a[i]); upd(0, n, 1, x); } for (auto p : queries[i]) { int x = query1(0, n, 1, 0, p.first); ans[p.second] = i - x; } } for (int i = 0; i < q; i++) cout << ans[i] << n ; } |
#include <bits/stdc++.h> using namespace std; double dp[2005][2005]; int main() { ios::sync_with_stdio(0); a: int n, t; double p; cin >> n >> p >> t; dp[0][0] = 1.0; for (int i = 1; i <= t; i++) dp[i][0] = dp[i - 1][0] * (1.0 - p); for (int j = 1; j <= n; j++) dp[0][j] = 0.0; for (int i = 1; i <= t; i++) { for (int j = 1; j <= n; j++) { if (j == n) dp[i][j] = dp[i - 1][j - 1] * p + dp[i - 1][j]; else dp[i][j] = dp[i - 1][j - 1] * p + dp[i - 1][j] * (1.0 - p); } } double res = 0.0; for (int i = 0; i <= n; i++) res += (dp[t][i] * ((double)i)); printf( %.10f n , (double)res); } |
#include <bits/stdc++.h> using namespace std; int q[123456]; vector<int> sq; int main() { int n, k; int a, b; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d%d , &a, &b); sq.push_back(min(2 * a, b) - min(a, b)); q[i] = min(a, b); 1; } sort(sq.begin(), sq.end(), greater<int>()); long long sum = 0; int flag = 1; for (int i = 0; i < k; i++) sum += sq[i], sq[i] < 0 ? flag = 0 : 0; for (int i = 1; i <= n; i++) sum += q[i]; printf( %lld , flag * sum); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 110; int n, m; string s; int a[maxn]; int main() { cin >> n >> m; int cnt = 0; while (n--) { cin >> s; if (s[0] == a ) { int x; cin >> x; int num = 0; bool flag = false; for (int i = 1; i + x - 1 <= m; i++) { num = 0; for (int j = i; j <= i + x - 1; j++) { if (a[j] == 0) num++; } if (num == x) { cnt++; flag = true; for (int j = i; j <= i + x - 1; j++) a[j] = cnt; cout << cnt << endl; break; } } if (!flag) cout << NULL << endl; } else if (s[0] == e ) { int x; cin >> x; if (x <= 0) cout << ILLEGAL_ERASE_ARGUMENT << endl; else { bool flag = false; for (int i = 1; i <= m; i++) { if (a[i] == x) { a[i] = 0; flag = true; } } if (!flag) cout << ILLEGAL_ERASE_ARGUMENT << endl; } } else { int k = 1; for (int i = 1; i <= m; i++) { if (a[i]) { a[k++] = a[i]; } } for (; k <= m; k++) a[k] = 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const double eps = 1e-6; template <typename A, typename B> ostream& operator<<(ostream& os, const pair<A, B>& p) { return os << p.first << , << p.second; } template <typename T> struct point { T x, y; point(T xx = 0, T yy = 0) : x(xx), y(yy) {} T len2() const { return x * x + y * y; } double len() const { return sqrt(double(len2())); } bool operator==(const point<T>& p) const { return x == p.x && y == p.y; } }; template <typename T> point<T> operator+(const point<T>& a, const point<T>& b) { return point<T>(a.x + b.x, a.y + b.y); } template <typename T> point<T> operator-(const point<T>& a, const point<T>& b) { return point<T>(a.x - b.x, a.y - b.y); } template <typename T> T scal(const point<T>& a, const point<T>& b) { return a.x * b.x + a.y * b.y; } template <typename T> T vect(const point<T>& a, const point<T>& b) { return a.x * b.y - a.y * b.x; } template <typename T> ostream& operator<<(ostream& os, const point<T>& p) { return os << ( << p.x << , << p.y << ) ; } const int maxn = 100100; pair<int, pair<int, int> > a[maxn], b[maxn]; int below[maxn], direct[maxn], belowsecond[maxn]; long long d[maxn][2]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { scanf( %d%d , &a[i].second.first, &a[i].first); a[i].second.second = i; } int m; cin >> m; for (int i = 0; i < m; i++) { scanf( %d%d , &b[i].second.first, &b[i].first); b[i].second.second = i; } sort(a, a + n); sort(b, b + m); memset(direct, -1, sizeof(direct)); memset(below, -1, sizeof(below)); memset(belowsecond, -1, sizeof(belowsecond)); for (int i = 0; i < n; i++) { pair<int, pair<int, int> >* d1 = lower_bound(b, b + m, pair<int, pair<int, int> >( a[i].first, pair<int, int>(a[i].second.first, 0))); pair<int, pair<int, int> >* d2 = lower_bound(b, b + m, pair<int, pair<int, int> >( a[i].first - 1, pair<int, int>(a[i].second.first, 0))); if (d1 != b + m && d1->first == a[i].first && d1->second.first >= a[i].second.first) { direct[i] = d1->second.second; } if (d2 != b + m && d2->first + 1 == a[i].first && d2->second.first >= a[i].second.first) { below[i] = d2->second.second; d2++; if (d2 != b + m && d2->first + 1 == a[i].first && d2->second.first >= a[i].second.first) { belowsecond[i] = d2->second.second; } } } long long mx = 0; for (int i = 0; i < n; i++) { if (direct[i] >= 0) { long long q = max(d[i][0], d[i][1]); d[i + 1][1] = max(d[i + 1][1], a[i].second.first + q); } if (below[i] >= 0) { d[i + 1][0] = max(d[i + 1][0], d[i][0] + a[i].second.first); if (i > 0 && direct[i - 1] != below[i]) { d[i + 1][0] = max(d[i + 1][0], d[i][1] + a[i].second.first); } if (i > 0 && direct[i - 1] == below[i] && belowsecond[i] >= 0) { d[i + 1][0] = max(d[i + 1][0], d[i][1] + a[i].second.first); } } d[i + 1][0] = max(d[i + 1][0], max(d[i][0], d[i][1])); mx = max(mx, max(d[i + 1][0], d[i + 1][1])); } cout << mx << endl; int cur = n; int t = 0; if (d[cur][t] != mx) t++; assert(d[cur][t] == mx); vector<pair<int, int> > res; set<int> guyused; for (; cur > 0; cur--) { if (res.size()) { guyused.insert(res.back().second); } if (d[cur - 1][0] == d[cur][t]) { t = 0; continue; } if (d[cur - 1][1] == d[cur][t]) { t = 1; continue; } int p = a[cur - 1].second.first; if (!guyused.count(direct[cur - 1])) { if (p + d[cur - 1][1] == mx && direct[cur - 1] >= 0) { res.push_back( pair<int, int>(a[cur - 1].second.second, direct[cur - 1])); mx -= p; t = 1; continue; } if (p + d[cur - 1][0] == mx && direct[cur - 1] >= 0) { res.push_back( pair<int, int>(a[cur - 1].second.second, direct[cur - 1])); mx -= p; t = 0; continue; } } assert(below[cur - 1] >= 0); if (!guyused.count(below[cur - 1])) { if (d[cur - 1][0] + p == mx) { res.push_back(pair<int, int>(a[cur - 1].second.second, below[cur - 1])); mx -= p; t = 0; continue; } if (cur - 2 < 0 || (direct[cur - 2] != below[cur - 1] && d[cur - 1][1] + p == mx)) { res.push_back(pair<int, int>(a[cur - 1].second.second, below[cur - 1])); mx -= p; t = 1; continue; } } assert(!guyused.count(belowsecond[cur - 1])); if (cur - 2 >= 0 && direct[cur - 2] == below[cur - 1] && belowsecond[cur - 1] >= 0 && d[cur - 1][1] + p == mx) { res.push_back( pair<int, int>(a[cur - 1].second.second, belowsecond[cur - 1])); mx -= p; t = 1; continue; } assert(0); } printf( %d n , res.size()); for (int i = 0; i < res.size(); i++) { printf( %d %d n , res[i].second + 1, res[i].first + 1); } return 0; } |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
module ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) const long long INF = 0x3f3f3f3f3f3f3f3f; const long long llinf = (1LL << 61); const int inf = (1 << 30); const int nmax = 4e5 + 50; const int mod = 1e9 + 7; using namespace std; string s; long long n, a[nmax], st[4 * nmax], i, lzy[4 * nmax], x, q, st1[4 * nmax], ms[4 * nmax], msk[nmax], m, ans, j, inv[100], l, r, sv[500], x1; long long pr[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293}; long long pw(long long n, long long p) { long long tmp = n, ans = 1, mx; if (p == mod - 2) mx = 31; else mx = 18; for (int i = 0; i <= mx; i++) { if (p & (1LL << i)) ans = (ans * tmp) % mod; tmp = (tmp * tmp) % mod; } return ans; } void build(int x, int l, int r) { if (l == r) { st[x] = a[l]; st1[x] = msk[l]; return; } int mid = (l + r) / 2; build(2 * x, l, mid); build(2 * x + 1, mid + 1, r); st[x] = st[2 * x] * st[2 * x + 1]; st[x] %= mod; st1[x] = st1[2 * x] | st1[2 * x + 1]; } void push(int nod, int l, int r) { if (!lzy[nod]) return; if (lzy[nod] != 1) st[nod] = (st[nod] * pw(lzy[nod], r - l + 1)) % mod; st1[nod] |= ms[nod]; if (l != r) { if (lzy[nod] != 1) { lzy[nod * 2] *= lzy[nod]; lzy[nod * 2 + 1] *= lzy[nod]; lzy[nod * 2] %= mod; lzy[nod * 2 + 1] %= mod; } ms[nod * 2] |= ms[nod]; ms[nod * 2 + 1] |= ms[nod]; } lzy[nod] = 1; } void upd(int nod, int l, int r, int tl, int tr, long long v, long long m) { push(nod, l, r); if (tl <= l && r <= tr) { lzy[nod] = (lzy[nod] * v) % mod; ms[nod] |= m; push(nod, l, r); return; } int mid = (l + r) / 2; if (tl <= mid) upd(nod * 2, l, mid, tl, tr, v, m); if (mid < tr) upd(nod * 2 + 1, mid + 1, r, tl, tr, v, m); push(nod * 2, l, mid); push(nod * 2 + 1, mid + 1, r); st[nod] = st[nod * 2] * st[nod * 2 + 1]; st[nod] %= mod; st1[nod] = st1[nod * 2] | st1[nod * 2 + 1]; } pair<long long, long long> qry(int nod, int l, int r, int tl, int tr) { push(nod, l, r); if (tl <= l && r <= tr) return {st[nod], st1[nod]}; int mid = (l + r) / 2; pair<long long, long long> vl, x; vl.first = 1, vl.second = 0; if (tl <= mid) { x = qry(nod * 2, l, mid, tl, tr); vl.first = (vl.first * x.first) % mod; vl.second |= x.second; } if (mid < tr) { x = qry(nod * 2 + 1, mid + 1, r, tl, tr); vl.first = (vl.first * x.first) % mod; vl.second |= x.second; } return vl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n >> q; for (j = 0; j < 62; j++) { inv[j] = pw(pr[j], mod - 2); sv[pr[j]] = j; } for (i = 1; i <= n; i++) { cin >> a[i]; for (j = 0; j < 62; j++) if (a[i] % pr[j] == 0) msk[i] |= (1LL << j); } for (i = 1; i <= 1600000; i++) lzy[i] = 1; build(1, 1, n); while (q--) { cin >> s; if (s[0] == M ) { cin >> l >> r >> x; x1 = x, m = 0; for (j = 0; j < 62; j++) if (x % pr[j] == 0) m |= (1LL << j); upd(1, 1, n, l, r, x, m); } else { cin >> l >> r; pair<long long, long long> p = qry(1, 1, n, l, r); ans = p.first; for (j = 0; j < 62; j++) { if (p.second & (1LL << j)) { ans = (ans * (1 - inv[j] + mod)) % mod; } } cout << ans << endl; } } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ae_e
//
// Generated
// by: wig
// on: Wed Aug 18 12:44:01 2004
// cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../constant.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ae_e.v,v 1.4 2005/10/06 11:16:04 wig Exp $
// $Date: 2005/10/06 11:16:04 $
// $Log: inst_ae_e.v,v $
// Revision 1.4 2005/10/06 11:16:04 wig
// Got testcoverage up, fixed generic problem, prepared report
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
//
// Generator: mix_0.pl Revision: 1.32 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ae_e
//
// No `defines in this module
module inst_ae_e
//
// Generated module inst_ae
//
(
bus20040728_altop_i,
//!wig20050930: ERROR: p_mix_bus20040728_top_7_4_gi
p_mix_bus20040728_top_7_4_gi
);
// Generated Module Inputs:
input [7:0] bus20040728_altop_i;
//!wig20050930: ERROR: input [3:0] p_mix_bus20040728_top_7_4_gi;
input [7:0] p_mix_bus20040728_top_7_0_gi;
// Generated Wires:
wire [7:0] bus20040728_altop_i;
//!wig20050930: ERROR: wire [3:0] p_mix_bus20040728_top_7_4_gi;
wire [7:0] p_mix_bus20040728_top_7_0_gi;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] bus20040728_altop; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] bus20040728_top; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign bus20040728_altop = bus20040728_altop_i; // __I_I_BUS_PORT
assign bus20040728_top[7:4] = p_mix_bus20040728_top_7_4_gi[3:0]; // __I_I_SLICE_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aea
inst_aea_e inst_aea(
.bus20040728_altop_i(bus20040728_altop),
.bus20040728_top_i(bus20040728_top)
);
// End of Generated Instance Port Map for inst_aea
endmodule
//
// End of Generated Module rtl of inst_ae_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program demonstrates the mixing of reg and memories in l-value
* contatenations.
*/
module main;
reg [3:0] mem [2:0];
reg a, b;
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
{b, mem[1], a} <= 6'b0_0000_1;
#1
if (a !== 1'b1) begin
$display("FAILED -- a = %b", a);
$finish;
end
if (mem[1] !== 4'b0000) begin
$display("FAILED -- mem[1] = %b", mem[1]);
$finish;
end
if (b !== 1'b0) begin
$display("FAILED -- b = %b", b);
$finish;
end
{b, mem[1], a} <= 6'b0_1111_0;
#1
if (a !== 1'b0) begin
$display("FAILED -- a = %b", a);
$finish;
end
if (mem[0] !== 4'b0000) begin
$display("FAILED -- mem[0] - %b", mem[0]);
$finish;
end
if (mem[1] !== 4'b1111) begin
$display("FAILED -- mem[1] = %b", mem[1]);
$finish;
end
if (b !== 1'b0) begin
$display("FAILED -- b = %b", b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
`timescale 1ns/10ps
module c25Board (
clk, // clock I1
reset, // reset I1
// io
buttons, // buttons I4
leds, // leds O4
// rs232
rx, // receive I1
tx, // send O1
// flash 32M x16
flashWeN, // write enable O1
flashCsN, // cable select O1
flashOeN, // output enable O1
flashResetN,// reset O1
flashAdvN, // active-low address valid O1
flashClk, // clock O1
flashWait, // ??? O1
// ssram 256 x32
sramOeN, // output O1
sramCeN, // clock enable O1
sramWeN, // write enable O1
sramBeN, // byte enable O4
sramAdscN, // adress controller O1
sramClk, // clock O1
// flash & ssram
flash_sramAddr, // addr O24
flash_sramData, // data T32
);
input clk;
input resetN;
input [3:0] buttons;
output [3:0] leds;
wire [3:0] leds;
input rx;
output tx;
wire tx;
wire c100mhz;
wire [15:0] memoryaddr;
wire [31:0] memQ;
wire [31:0] memData;
wire romrden;
wire ramrden;
wire ramwren;
wire [31:0] romOut;
wire [31:0] ramOut;
assign memQ = romrden ? romOut : 'bz;
assign memQ = ramrden ? ramOut : 'bz;
wire [7:0] fifodata;
wire [7:0] fifoq;
wire fifore;
wire fifowe;
wire fifoempty;
processor procI (
.clk(clk),
.reset(resetN),
.buttons(buttons),
.leds(leds),
.rx(rx),
.tx(tx),
.memoryaddr(memoryaddr),
.memoryin(memQ),
.memoryout(memData),
.romrden(romrden),
.ramrden(ramrden),
.ramwren(ramwren),
.fifodata(fifodata),
.fifore(fifore),
.fifowe(fifowe),
.fifoempty(fifoempty),
.fifofull(1'b0),
.fifoq(fifoq)
);
ram ramI (
.address(memoryaddr[9:0]),
.byteena(4'h1),
.clock(clk),
.data(memData),
.rden(ramrden),
.wren(ramwren),
.q(ramOut)
);
rom romI (
.address(memoryaddr[7:0]),
.clock(clk),
.rden(romrden),
.q(romOut)
);
fifo rsrBuffer (
.clock(clk),
.data(fifodata),
.rdreq(fifore),
.wrreq(fifowe),
.empty(fifoempty),
.q(fifoq)
);
disppll dpll (
.areset(reset),
.inclk0(clk),
.c0(c100mhz)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 1, inf = 1e18; vector<pair<long long, long long> > a, b; vector<pair<pair<long long, long long>, long long> > z; long long add[4 * N], t[4 * N]; void push(long long v, long long l, long long r) { t[v] += add[v]; if (l != r - 1) { add[2 * v] += add[v]; add[2 * v + 1] += add[v]; } add[v] = 0; } void update(long long v, long long l, long long r, long long vl, long long vr, long long val) { push(v, l, r); if (l >= vr || vl >= r) return; if (l >= vl && r <= vr) { add[v] += val; push(v, l, r); return; } long long m = (l + r) / 2; update(2 * v, l, m, vl, vr, val); update(2 * v + 1, m, r, vl, vr, val); t[v] = max(t[2 * v + 1], t[2 * v]); } long long get(long long v, long long l, long long r, long long vl, long long vr) { push(v, l, r); if (l >= vr || vl >= r) return -inf; if (l >= vl && r <= vr) { return t[v]; } long long m = (l + r) / 2; return max(get(2 * v, l, m, vl, vr), get(2 * v + 1, m, r, vl, vr)); } void fuckyou(long long v, long long l, long long r, long long pos, long long val) { if (l > pos || r <= pos) return; if (l == r - 1) { t[v] = max(t[v], val); return; } long long m = (l + r) / 2; fuckyou(2 * v, l, m, pos, val); fuckyou(2 * v + 1, m, r, pos, val); t[v] = max(t[2 * v], t[2 * v + 1]); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (long long i = 0; i < 4 * N; i++) t[i] = -inf; long long n, m, p, ans = -inf; cin >> n >> m >> p; a.resize(n); b.resize(m); z.resize(p); for (long long i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } for (long long i = 0; i < m; i++) { cin >> b[i].first >> b[i].second; fuckyou(1, 0, N, b[i].first, -b[i].second); } for (long long i = 0; i < p; i++) { cin >> z[i].first.first >> z[i].first.second >> z[i].second; } sort((z).begin(), (z).end()); sort((a).begin(), (a).end()); cout << endl; long long j = 0; for (long long i = 0; i < n; i++) { while (j < z.size() && a[i].first > z[j].first.first) { update(1, 0, N, z[j].first.second + 1, N, z[j].second); j++; } ans = max(ans, -a[i].second + get(1, 0, N, 0, N)); } cout << ans; } |
/*############################################################################
* PROGRAMMABLE DELAY ELEMENT
*
* NOTE: NOT AVAILABLE IN HR BANKS!
*
*############################################################################
*/
module ODELAYE2 (/*AUTOARG*/
// Outputs
CNTVALUEOUT, DATAOUT,
// Inputs
C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "ODATAIN";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
parameter ODELAY_TYPE = "FIXED";
parameter integer ODELAY_VALUE = 0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
input C; //clock for VARIABLE, VAR_LOAD,VAR_LOAD_PIPE mode
input REGRST; //reset pipeline reg to all zeroes
input LD; //loads programmed values depending on "mode"
input CE; //enable encrement/decrement function
input INC; //increment/decrement tap delays
input CINVCTRL; //dynamically inverts clock polarity
input [4:0] CNTVALUEIN; //input value from FPGA logic
input CLKIN; //clk from I/O clock mux??
input ODATAIN; //data from OSERDESE2 output
output DATAOUT; //delayed data to pin
input LDPIPEEN; //enables pipeline reg??
output [4:0] CNTVALUEOUT; //current value for FPGA logic
assign DATAOUT=ODATAIN;
endmodule // ODELAYE2
|
#include <bits/stdc++.h> using namespace std; int n, m, a[1000006], ans[1000006]; bool b[1000006]; stack<pair<int, int> > s1, s2; int main() { int i, j; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d , &j); b[j] = true; } for (i = 1; i <= n; i++) { if (b[i]) { while (s1.size()) { if (s1.top().first == a[i] && s2.size() == 0) { break; } else if (s2.size() && s1.top().first == s2.top().first) { ans[s1.top().second] = 1; ans[s2.top().second] = -1; s1.pop(); s2.pop(); } else { s2.push(s1.top()); s1.pop(); } } if (s1.size() == 0) return cout << NO << endl, 0; ans[s1.top().second] = 1; ans[i] = -1; s1.pop(); } else { s1.push({a[i], i}); } } while (s1.size()) { if (s2.size() == 0) { s2.push(s1.top()); s1.pop(); } else if (s1.top().first == s2.top().first) { ans[s1.top().second] = 1; ans[s2.top().second] = -1; s1.pop(); s2.pop(); } else { s2.push(s1.top()); s1.pop(); } } if (s2.size()) return cout << NO << endl, 0; printf( YES n ); for (i = 1; i <= n; i++) printf( %d , a[i] * ans[i]); } |
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) using namespace std; namespace ywy { char v[300][300]; long long dk1[300], dk2[300]; int dp[600]; typedef struct _p { long long h1, h2; _p() { h1 = 2333; h2 = 6663; } friend bool operator==(const _p &a, const _p &b) { return (a.h1 == b.h1 && a.h2 == b.h2); } friend bool operator!=(const _p &a, const _p &b) { return ((a.h1 != b.h1) || (a.h2 != b.h2)); } inline void insert(char x) { h1 += dk1[x - a + 1]; h1 %= 998244353; h2 += dk2[x - a + 1]; h2 %= 1000000007; } } pair; pair str[600], real[600]; int s[300]; inline int solve(int n) { int ptr = 0, mid = 1, ans = 0; for (register int i = 2; i <= n; i++) { if (mid + ptr < i) mid = i, ptr = 0, dp[i] = 0; else dp[i] = min(mid + ptr - i, dp[mid * 2 - i]); while (dp[i] < min(n - i, i - 1) && str[i + dp[i] + 1] == str[i - dp[i] - 1]) dp[i]++; if (i + dp[i] >= mid + ptr) mid = i, ptr = dp[i]; if ((i & 1) == 0 && (s[i >> 1] != (s[i >> 1] & -s[i >> 1]))) continue; ans += (dp[i] + 1) / 2; } return (ans); } void ywymain() { int n, m; cin >> n >> m; for (register int i = 1; i <= n; i++) { for (register int j = 1; j <= m; j++) cin >> v[i][j]; } dk1[0] = dk2[0] = 1; for (register int i = 1; i <= 26; i++) { dk1[i] = (dk1[i - 1] * 233) % 998244353; dk2[i] = (dk2[i - 1] * 233) % 1000000007; } int ans = 0; for (register int l = 1; l <= m; l++) { memset(s, 0, sizeof(s)); for (register int i = 1; i <= n * 2 + 1; i++) str[i] = real[i] = _p(); for (register int r = l; r <= m; r++) { for (register int i = 1; i <= n; i++) { s[i] ^= (1 << (v[i][r] - 1)); real[i].insert(v[i][r]); if (s[i] != (s[i] & -s[i])) { str[i * 2].h1 = i + 19260817; str[i * 2].h2 = 19260817 - i; } else str[i * 2] = real[i]; } ans += solve(n * 2 + 1); } } cout << ans << endl; } } // namespace ywy int main() { ywy::ywymain(); return (0); } |
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ()
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
// Sound module, channel 3. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlChannel3 //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc256, //OSC1 clock 256Hz
input wire iOsc262k, //OSC2 clock 131072Hz
input wire [7:0] iNR30,
input wire [7:0] iNR31,
input wire [7:0] iNR32,
input wire [7:0] iNR33,
input wire [7:0] iNR34,
output reg [4:0] oOut,
output wire oOnFlag
);
reg [8:0] rLength;
reg [19:0] rLengthCounter;
reg rTimedMode;
reg rLengthComplete; // Channe disable.
reg rTone;
reg [10:0] rSoundFrequency;
reg [10:0] rSoundFrequencyCounter;
reg rChannelEnable;
reg [1:0] rOutLevel;
reg [3:0] rStep;
reg [3:0] rStepScaled;
wire [4:0] up_value, down_value;
reg [4:0] rWaveRamIndex;
reg rWaveRamHnL;
reg [7:0] iWaveRam [0:31]; // Wave samples Ram 64 samples of 4 bits
// triangular waveform
///*
always @ (posedge iClock) begin
if (iReset) begin
iWaveRam[0]=8'h01;
iWaveRam[1]=8'h23;
iWaveRam[2]=8'h45;
iWaveRam[3]=8'h67;
iWaveRam[4]=8'h89;
iWaveRam[5]=8'hAB;
iWaveRam[6]=8'hCD;
iWaveRam[7]=8'hEF;
iWaveRam[8]=8'hED;
iWaveRam[9]=8'hCB;
iWaveRam[10]=8'hA9;
iWaveRam[11]=8'h87;
iWaveRam[12]=8'h65;
iWaveRam[13]=8'h43;
iWaveRam[14]=8'h21;
iWaveRam[15]=8'h00;
iWaveRam[16]=8'h01;
iWaveRam[17]=8'h23;
iWaveRam[18]=8'h45;
iWaveRam[19]=8'h67;
iWaveRam[20]=8'h89;
iWaveRam[21]=8'hAB;
iWaveRam[22]=8'hCD;
iWaveRam[23]=8'hEF;
iWaveRam[24]=8'hED;
iWaveRam[25]=8'hCB;
iWaveRam[26]=8'hA9;
iWaveRam[27]=8'h87;
iWaveRam[28]=8'h65;
iWaveRam[29]=8'h43;
iWaveRam[30]=8'h21;
iWaveRam[31]=8'h00;
end
end
//*/
// sawtooth waveform
/*
always @ (posedge iClock) begin
if (iReset) begin
iWaveRam[0]=8'hFE;
iWaveRam[1]=8'hDC;
iWaveRam[2]=8'hBA;
iWaveRam[3]=8'h98;
iWaveRam[4]=8'h76;
iWaveRam[5]=8'h54;
iWaveRam[6]=8'h32;
iWaveRam[7]=8'h10;
iWaveRam[8]=8'hFE;
iWaveRam[9]=8'hDC;
iWaveRam[10]=8'hBA;
iWaveRam[11]=8'h98;
iWaveRam[12]=8'h76;
iWaveRam[13]=8'h54;
iWaveRam[14]=8'h32;
iWaveRam[15]=8'h10;
iWaveRam[16]=8'hFE;
iWaveRam[17]=8'hDC;
iWaveRam[18]=8'hBA;
iWaveRam[19]=8'h98;
iWaveRam[20]=8'h76;
iWaveRam[21]=8'h54;
iWaveRam[22]=8'h32;
iWaveRam[23]=8'h10;
iWaveRam[24]=8'hFE;
iWaveRam[25]=8'hDC;
iWaveRam[26]=8'hBA;
iWaveRam[27]=8'h98;
iWaveRam[28]=8'h76;
iWaveRam[29]=8'h54;
iWaveRam[30]=8'h32;
iWaveRam[31]=8'h10;
end
end
*/
// register load
always @(posedge iClock) begin
if (iReset || iNR34[7]) begin // Register reload and counters restart.
rChannelEnable <= iNR30[7];
rLength <= iNR31[7:0];
rLengthCounter <= 256 - iNR31[7:0]; // Decrements to zero then load rLength.
rLengthComplete <= 0; // Disables channel when is asserted.
rTimedMode <= iNR34[6];
rOutLevel <= iNR32[6:5];
rStep <= iWaveRam[0][3:0];
rWaveRamIndex <= 0;
rWaveRamHnL <= 1; // Indicates if low or high part have been read.
rTone <= 0;
rSoundFrequency[10:0] <= 2048-{iNR34[2:0],iNR33[7:0]};
rSoundFrequencyCounter <= 2048-{iNR34[2:0],iNR33[7:0]};
end
end
// wave ram reader
always @ (posedge rTone) begin
if (rChannelEnable) begin
if (~rWaveRamHnL) begin
rStep <= iWaveRam[rWaveRamIndex][7:4];
rWaveRamHnL <= ~rWaveRamHnL;
end
else begin
rStep <= iWaveRam[rWaveRamIndex][3:0];
rWaveRamHnL <= ~rWaveRamHnL;
if (rWaveRamIndex == 5'd31) begin
rWaveRamIndex <= rWaveRamIndex+1;
rLengthComplete <= rTimedMode;
end
else begin
rWaveRamIndex <= rWaveRamIndex+1;
end
end
end
else begin
rStep <= 4'b0;
end
end
// tone gen: generates the frecuency of the output.
always @(posedge iOsc262k) begin
if (rSoundFrequencyCounter ==0) begin
rSoundFrequencyCounter <= rSoundFrequency;
rTone <= ~rTone;
end
else begin
rSoundFrequencyCounter <= rSoundFrequencyCounter-1;
end
end
// timmer: enable or disable channel output.
always @(posedge iOsc256) begin
if (rLengthCounter == 0) begin
rLengthCounter <= 256-rLength;
rLengthComplete <= rTimedMode; // Disable channel only if timmer is enabled.
end
else begin
rLengthCounter <= rLengthCounter-1;
end
end
//re-map mux
assign up_value = 5'd15 + rStepScaled;
assign down_value = 5'd15 - rStepScaled;
always @(posedge iClock) begin
if (rLengthComplete) begin
oOut[4:0] <= 5'd15;
end
else begin
if (rTone) begin
oOut[4:0] <= up_value[4:0];
end
else begin
oOut[4:0] <= down_value[4:0];
end
end
end
// output level manager
always @ (rOutLevel or rStep) begin
case (rOutLevel[1:0])
2'd0: rStepScaled = 0;
2'd1: rStepScaled = rStep;
2'd2: rStepScaled = rStep >> 1;
2'd3: rStepScaled = rStep >> 2;
endcase
end
assign oOnFlag = rLengthComplete;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_1_V
`define SKY130_FD_SC_HDLL__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_SYMBOL_V
`define SKY130_FD_SC_HS__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using point = pair<int, int>; int D(point a, point b, point c) { return a.first * (b.second - c.second) - a.second * (b.first - c.first) + (b.first * c.second - b.second * c.first); } int main() { int n, d; cin >> n >> d; vector<point> poligon; poligon.push_back(make_pair(0, d)); poligon.push_back(make_pair(d, 0)); poligon.push_back(make_pair(n, n - d)); poligon.push_back(make_pair(n - d, n)); poligon.push_back(poligon[0]); int k; cin >> k; vector<point> points(k); for (auto &[x, y] : points) cin >> x >> y; for (auto each : points) { int s1 = 0, s2 = 0; for (int i = 0; i < poligon.size() - 1; ++i) { int test = D(each, poligon[i], poligon[i + 1]); if (test > 0) s1++; else if (test < 0) s2++; } if (s2 == 0 or s1 == 0) cout << YES << endl; else cout << NO << endl; } return 0; } |
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_shl.list"
`include "top.v"
module top_test_shl;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output == 0) begin
$display("Shift left test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Shift left test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output << 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> const double pi = acos(-1); const int MOD = 1e9 + 7; const int INF = 1e9 + 7; const int MAXN = 1e6 + 5; const double eps = 1e-9; using namespace std; double xp, yp, vp, x, y, v, r, R; double P, len, L; pair<double, double> pos[2]; double f(double dphi) { if (dphi > pi) dphi = 2 * pi - dphi; if (dphi > P) return ((dphi - P) * r + L) / v; return sqrt(len * len + R * R - 2 * len * R * cos(dphi)) / v; } int main() { scanf( %lf %lf %lf %lf %lf %lf %lf , &xp, &yp, &vp, &x, &y, &v, &r); double lo = 0, hi = 1e18; R = hypot(xp, yp); double omega = vp / R; double phi0 = 0; if (x * yp == xp * y) { if (x * xp < 0 || y * yp < 0) phi0 = pi; } else { phi0 = acos((x * xp + y * yp) / (hypot(xp, yp) * hypot(x, y))); if (x * yp < xp * y) phi0 = 2 * pi - phi0; } len = hypot(x, y); L = sqrt(len * len - r * r) + sqrt(R * R - r * r); P = acos(r / len) + acos(r / R); hi = fabs(R - len) / v + 2 * pi * R / vp; while (abs(hi - lo) > eps) { double T = (lo + hi) / 2.; double dphi = fmod(omega * T + phi0, 2 * pi); if (dphi < 0) dphi += 2 * pi; if (f(dphi) < T) hi = T; else lo = T; } printf( %.20f n , lo); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_SN_TB_V
/**
* udp_dlatch$PR_pp$PKG$sN: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_SN_TB_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always block instantiation.
//
// D: Test validate others versions of always block
// D: including posedge, negedge.
//
//
module main ();
reg working;
reg clock ;
initial // Used to generate timing of events
begin
working = 0;
clock = 0;
#4 ;
working = 0;
#1 ;
clock = 1; // 1ns between setting working and clock edge.
#4 ;
working = 0;
#1 ;
clock = 0; // 1ns between setting working and clock edge.
#5 ;
end
always #2
working = 1 ;
initial // This is the validation block
begin
# 3; // Check #2 always at 3ns
if(!working)
begin
$display("FAILED - delayed always\n");
$finish ;
end
# 3; // Check posedge at 6 ns
if(!working)
begin
$display("FAILED - posedge always\n");
$finish ;
end
# 7; // Check negedge at 11ns
if(!working)
begin
$display("FAILED - posedge always\n");
$finish ;
end
$display("PASSED\n");
$finish;
end
always @ (posedge clock)
working = 1;
always @ (negedge clock)
working = 1;
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:gcd:1.0
// IP Revision:
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_block_design_gcd_0_1,gcd,{}" *)
(* CORE_GENERATION_INFO = "gcd_block_design_gcd_0_1,gcd,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=gcd,x_ipVersion=1.0,x_ipCoreRevision=,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_GCD_BUS_ADDR_WIDTH=6,C_S_AXI_GCD_BUS_DATA_WIDTH=32}" *)
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_block_design_gcd_0_1 (
s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_BRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR" *)
input wire [5 : 0] s_axi_gcd_bus_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID" *)
input wire s_axi_gcd_bus_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY" *)
output wire s_axi_gcd_bus_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA" *)
input wire [31 : 0] s_axi_gcd_bus_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB" *)
input wire [3 : 0] s_axi_gcd_bus_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID" *)
input wire s_axi_gcd_bus_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY" *)
output wire s_axi_gcd_bus_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP" *)
output wire [1 : 0] s_axi_gcd_bus_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID" *)
output wire s_axi_gcd_bus_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY" *)
input wire s_axi_gcd_bus_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR" *)
input wire [5 : 0] s_axi_gcd_bus_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID" *)
input wire s_axi_gcd_bus_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY" *)
output wire s_axi_gcd_bus_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA" *)
output wire [31 : 0] s_axi_gcd_bus_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP" *)
output wire [1 : 0] s_axi_gcd_bus_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID" *)
output wire s_axi_gcd_bus_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, \
ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY" *)
input wire s_axi_gcd_bus_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN \
gcd_block_design_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
gcd #(
.C_S_AXI_GCD_BUS_ADDR_WIDTH(6),
.C_S_AXI_GCD_BUS_DATA_WIDTH(32)
) inst (
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_AWREADY(s_axi_gcd_bus_AWREADY),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID),
.s_axi_gcd_bus_WREADY(s_axi_gcd_bus_WREADY),
.s_axi_gcd_bus_BRESP(s_axi_gcd_bus_BRESP),
.s_axi_gcd_bus_BVALID(s_axi_gcd_bus_BVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_ARREADY(s_axi_gcd_bus_ARREADY),
.s_axi_gcd_bus_RDATA(s_axi_gcd_bus_RDATA),
.s_axi_gcd_bus_RRESP(s_axi_gcd_bus_RRESP),
.s_axi_gcd_bus_RVALID(s_axi_gcd_bus_RVALID),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; double p[1001]; double getp(unsigned long long a, unsigned long long b) { unsigned long long st = 1, ed = 1; double ret; while (st < a) st = st * 10; while (ed < b) ed = ed * 10; if (ed > b) ed = ed / 10; if (st > a) st = st / 10; if (ed + ed - 1 < a) return 0; if ((ed + ed - 1) <= b) { ret = st * (pow(10, log10(ed / st) + 1) - 1) / 9; } else ret = st * (pow(10, log10(ed / st)) - 1) / 9 + (b - ed + 1); if (st + st - 1 >= a) ret = ret - (a - st); if (st + st - 1 < a) ret = ret - (st); return (double)ret / (b - a + 1); } double memo[1001][1001]; double dp(int i, int j) { if (j < 0 || i < 0) return 0; if (memo[i][j] != -1) return memo[i][j]; if (i == 0 && j == 0) { memo[i][j] = 1; return 1; } double ret = p[i - 1] * dp(i - 1, j - 1) + (1 - p[i - 1]) * dp(i - 1, j); memo[i][j] = ret; return ret; } int main() { scanf( %d , &n); for (int i = 0; i <= n; i++) { for (int j = 0; j <= n; j++) { memo[i][j] = -1; } } unsigned long long a, b; int i = 0; int t = n; while (t--) { cin >> a >> b; p[i++] = getp(a, b); } for (int j = 0; j <= n; j++) { if (memo[n][j] == -1) dp(n, j); } double k; cin >> k; k = ceil(k * n / 100); double sum = 0; for (int j = 0; j <= n; j++) { if (j >= k) sum = sum + memo[n][j]; } printf( %.15f , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; bool isprime[1000001]; void sieve() { for (long long i = 0; i <= 1000001; i++) { isprime[i] = true; } isprime[0] = false; isprime[1] = false; for (long long i = 2; i * i <= 1000001; i++) { if (isprime[i] == true) { for (long long j = i * i; j <= 1000001; j = j + i) { isprime[j] = false; } } } } long long gcd(long long a, long long b) { if (a < b) { swap(a, b); } if (b == 0) { return a; } return gcd(b, a % b); } bool comparen(pair<long long, long long> a, pair<long long, long long> b) { return a.second < b.second; } bool comparem(pair<long long, long long> a, pair<long long, long long> b) { return a.first > b.first; } void remove(long long n, char x, string s) { ; } void solve() { long long t = 1; while (t--) { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } long long i = 0; while (i < n - 1 && a[i] <= a[i + 1]) { i++; } long long k = i + 1; i++; while (i < n - 1 && a[i] <= a[i + 1]) { i++; } if (i == n) { cout << 0 << endl; } else if (i != n - 1 || a[0] < a[n - 1]) { cout << -1 << endl; } else { cout << n - k << endl; } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; double sqr(double x) { return x * x; } double distsqr(double x, double y, double a, double b) { return sqr((x - a)) + sqr((y - b)); } double cosine_angle(double a, double b, double c) { return (double)(sqr(a) + sqr(b) - sqr(c)) / ((double)2.0 * a * b); } template <class T> T Maximum(T a, T b) { return a > b ? a : b; } template <class T> T Minimum(T a, T b) { return a < b ? a : b; } template <class T> T GCD(T a, T b) { if (!b) return a; return GCD(b, a % b); } template <class T> void SWAP(T &a, T &b) { T temp = a; a = b; b = temp; return; } template <class T> T BigMod(T a, T n, T mod) { if (!n) return (T)1 % mod; long long int power = BigMod(a, n >> 1, mod); power %= mod; power *= power; power %= mod; if (n & 1) power *= a % mod, power %= mod; return power; } template <class T> T ExtendedEuclid(T a, T b, T c) { if (!a) return 0; return (b * ExtendedEuclid(b % a, a, -c) + c) / a; } template <class T> T ModInverse(T a, T m) { return ((ExtendedEuclid(a, m, (T)GCD(a, m))) % (m) + (m)) % (m); } long long int valk[100010], valk_1[100010], cval[100010]; void Processsing(int n, int k) { int i; long long int power, temp; if (k > 0) valk_1[k - 1] = 1; for (i = k, power = 1; i < n; i++) { if (i == k) valk[i] = 1; else { valk[i] = valk[i - 1] * i; valk[i] %= 1000000007; valk[i] *= ModInverse((long long int)(i - k), (long long int)1000000007); valk[i] %= 1000000007; } valk_1[i] = valk_1[i - 1] * i; valk_1[i] %= 1000000007; valk_1[i] *= ModInverse((long long int)(i - k + 1), (long long int)1000000007); valk_1[i] %= 1000000007; } for (i = 0; i < n - k; i++) { if (i) power *= 10; else power = 1; power %= 1000000007; temp = valk_1[n - 2 - i] * power; temp %= 1000000007; if (i) cval[i] = cval[i - 1] + temp; else cval[i] = temp; cval[i] %= 1000000007; } } int main() { int i, n, k; char c; long long int counts, temp; scanf( %d %d , &n, &k); Processsing(n, k); for (i = counts = 0; i < n; i++) { scanf( %c , &c); c -= 0 ; if (i < k) counts += cval[n - k - 1] * (int)c; else { temp = cval[n - 2 - i] + valk[i] * BigMod((long long int)10, (long long int)(n - 1 - i), (long long int)1000000007); temp %= 1000000007; temp *= (int)c; temp %= 1000000007; counts += temp; } counts %= 1000000007; } printf( %I64d n , counts); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inft = 1000000009; const int MAXN = 2000006; bool P[MAXN]; int SP[MAXN]; int PAL[MAXN]; char S[123]; bool pal(int a) { sprintf(S, %d , a); reverse(S, S + strlen(S)); int q; sscanf(S, %d , &q); return a == q; } int main() { for (int i = 0; i < (MAXN); ++i) P[i] = 1; for (int i = 2; i < MAXN; ++i) if (P[i]) for (int j = 2 * i; j < MAXN; j += i) P[j] = 0; P[0] = P[1] = 0; for (int i = 0; i < (MAXN); ++i) if (i) SP[i] = SP[i - 1] + P[i]; for (int i = 1; i < MAXN; ++i) PAL[i] = PAL[i - 1] + pal(i); int ret = 0; int p, q; scanf( %d%d , &p, &q); for (int i = 0; i < (MAXN); ++i) if (i && q * SP[i] <= p * PAL[i]) ret = i; if (ret) printf( %d n , ret); else printf( Palindromic tree is better than splay tree n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n <= 70000) { ++n; int x = n; int a[10] = {0}; for (int i = 0; i < 4; i++) { int m = x % 10; ++a[m]; x = x / 10; } int count = 0; for (int i = 0; i < 10; i++) { if (a[i] == 1) ++count; } if (count == 4) { cout << n; break; } } } |
#include <bits/stdc++.h> using namespace std; const int N = 105, M = N * N; int n; int a[N]; int f[N][M]; vector<pair<int, int> > b; int main() { scanf( %d , &n); int sum = 0; for (int i = 1; i <= n; i++) { scanf( %d , a + i); sum += a[i]; } sort(a + 1, a + n + 1); b.push_back(pair<int, int>(a[1], 1)); for (int i = 2; i <= n; i++) { if (a[i] == b.back().first) { b.back().second++; } else { b.push_back(pair<int, int>(a[i], 1)); } } int m = b.size(); if (m == 1) { printf( %d n , n); } else { f[0][0] = 1; int sumc = 0; for (int i = 0; i < m; i++) { int x = b[i].first, y = b[i].second; sumc += y; for (int c = sumc; c; c--) { for (int j = sum; j >= x; j--) { for (int k = 1; k * x <= j && k <= y && k <= c && f[c][j] < 2; k++) { f[c][j] = min(2, f[c][j] + f[c - k][j - x * k]); } } } } if (m == 2) { int ans = 0; for (int i = 0; i < m; i++) { int x = b[i].first, y = b[i].second; for (int j = 1; j <= y; j++) { if (f[j][j * x] == 1) { if (j < y) { ans = max(ans, j); } else { ans = n; } } } } printf( %d n , ans); } else { int ans = 0; for (int i = 0; i < m; i++) { int x = b[i].first, y = b[i].second; for (int j = 1; j <= y; j++) { if (f[j][j * x] == 1) { ans = max(ans, j); } } } printf( %d n , ans); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_TB_V
`define SKY130_FD_SC_HDLL__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_1_V
`define SKY130_FD_SC_LS__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__TAP_PP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int x, y; vector<int> v1[200086], v2[200086]; bool ins[200086]; bool vis[200086], vis1[200086], vis2[200086]; bool e[200086]; int ans; void dfs(int i) { vis[i] = ins[i] = true; for (int j = 0; j < v1[i].size(); j++) { int to = v1[i][j]; if (ins[to]) { printf( -1 ); exit(0); } if (!vis[to]) dfs(to); } ins[i] = false; } void dfs1(int i) { vis1[i] = true; for (int j = 0; j < v1[i].size(); j++) { int to = v1[i][j]; if (!vis1[to]) dfs1(to); } } void dfs2(int i) { vis2[i] = true; for (int j = 0; j < v2[i].size(); j++) { int to = v2[i][j]; if (!vis2[to]) dfs2(to); } } int main() { scanf( %d%d , &n, &m); ans = n; for (int i = 1; i <= m; i++) scanf( %d%d , &x, &y), v1[x].push_back(y), v2[y].push_back(x); for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i); for (int i = 1; i <= n; i++) { if (vis1[i]) e[i] = true; else dfs1(i); if (vis2[i]) e[i] = true; else dfs2(i); if (e[i]) ans--; } printf( %d n , ans); for (int i = 1; i <= n; i++) printf( %c , e[i] ? E : A ); } |
#include <bits/stdc++.h> using namespace std; int main() { string nameOne, nameTwo, tmpOne, tmpTwo; cin >> nameOne >> nameTwo; int n; cin >> n; cout << nameOne << << nameTwo << endl; for (int i = 0; i < n; i++) { cin >> tmpOne; cin >> tmpTwo; if (tmpOne == nameOne) nameOne = tmpTwo; else nameTwo = tmpTwo; cout << nameOne << << nameTwo << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> Height(n); vector<int> count(n, 0); for (int i = 0; i < n; i++) { cin >> Height[i]; } int x = 0, after = 1, befor = 0; while (after < n && Height[x] >= Height[after]) { count[0]++; x++; after++; } for (int i = 1; i < n - 1; i++) { x = i, after = i + 1, befor = i - 1; while (befor >= 0 && Height[x] >= Height[befor]) { count[i]++; x--; befor--; } x = i; while (after < n && Height[x] >= Height[after]) { count[i]++; x++; after++; } } x = n - 1; befor = n - 2; while (befor >= 0 && Height[x] >= Height[befor]) { count[n - 1]++; x--; befor--; } sort(count.begin(), count.end()); cout << count[count.size() - 1] + 1; return 0; } |
/*
* Titor - System - Bank selection manager
* Copyright (C) 2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_BANK_MANAGER
`else
`define INC_BANK_MANAGER
`timescale 1 ns / 100 ps
module BankManager(
dout,
din,
address,
size,
read_write,
enable,
bank,
bank_enable,
reset,
clk
);
`include "definition/Definition.v"
localparam ELEM_VALID = 0;
localparam ELEM_SLOT = 1;
localparam ELEM_LINK = 2;
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output reg [WORD-1:0] bank;
output reg bank_enable;
input reset;
input clk;
reg valid [NUM_BANK-1:0];
reg [WORD-1:0] slot [NUM_BANK-1:0];
reg [WORD-1:0] link [NUM_BANK-1:0];
reg sel_section [NUM_BANK-1:0];
reg [WORD-1:0] stage;
// under the standard configuration (8 banks and 7 pipeline stages + PC-only stage)
// this initialization is inefficient since one bubble per round can be cut out and only one bank is used
// to get the most efficient bootup set the next-to-last link to point back to 0 and/or enable
// more banks working in multiprocessing mode with trusted code
genvar i;
generate
for(i=0; i<NUM_BANK; i=i+1) begin : GENBANK
always @(posedge clk) begin
if(reset) begin
// for bank 0:
// turn on bank by default to enable bootstrapping
// for other banks:
// leave the other banks off at reset so they don't interfere with bank 0
// until explicitly told to active with bank 0 at the root of that activation chain
valid[i] <= (i==0) ? ENABLE : DISABLE; // enable only 0 by default
slot[i] <= i; // for bank i
link[i] <= (i+1)%NUM_BANK; // point to next slot
end
else begin
if( sel_section[i] && ((address/(WORDBYTE*NUM_BANK))==ELEM_VALID) ) begin
valid[i] <= din;
end
else begin
valid[i] <= valid[i];
end
if( sel_section[i] && ((address/(WORDBYTE*NUM_BANK))==ELEM_SLOT) ) begin
slot[i] <= din;
end
else begin
slot[i] <= slot[i];
end
if( sel_section[i] && ((address/(WORDBYTE*NUM_BANK))==ELEM_LINK) ) begin
link[i] <= din;
end
else begin
link[i] <= link[i];
end
end
end
always @(*) begin
sel_section[i] <= (((address/WORDBYTE)%NUM_BANK)==i) && (read_write==WRITE) && (enable==ENABLE);
end
end
endgenerate
always @(posedge clk) begin
if(reset) begin
stage <= 0;
end
else begin
stage <= link[stage];
end
end
always @(*) begin
bank <= slot[stage];
bank_enable <= valid[stage];
end
endmodule
`endif
|
#include <bits/stdc++.h> int main(void) { int i, j, k, m, n, max_length, length; char string[101]; for (n = 0, scanf( %s , string); string[n]; n++) ; for (m = 1, max_length = 0; m < n; m++) { for (i = m - 1; i >= 0; i--) { for (j = i, k = m, length = 0; k && string[j] == string[k]; j--, k--, length++) ; if (max_length < length) { max_length = length; } } } printf( %d , max_length); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_8_V
`define SKY130_FD_SC_LP__DECAPKAPWR_8_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog wrapper for decapkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decapkapwr_8 (
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decapkapwr base (
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decapkapwr_8 ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_8_V
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int>> G[262144]; int d1[26][262144]; pair<int, int> d2[2][262144]; int vis[2][262144]; long long mod = 998244353ll; long long qpow(long long x, long long y) { long long a = x, ans = 1; while (y) { if (y & 1) ans = (ans * a) % mod; y >>= 1; a = (a * a) % mod; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; G[u].push_back(make_pair(v, 0)); G[v].push_back(make_pair(u, 1)); } queue<pair<int, int>> q; q.push(make_pair(0, 1)); for (int i = 1; i <= n; i++) for (int j = 0; j <= 25; j++) d1[j][i] = -1; d1[0][1] = 0; while (!q.empty()) { pair<int, int> top = q.front(); q.pop(); int flips = top.first, u = top.second; for (auto i : G[u]) { int v = i.first, f = i.second; int flip = ((flips & 1) ^ f); if (flips + flip > 25) continue; if (d1[flips + flip][v] == -1) { d1[flips + flip][v] = d1[flips][u] + 1; q.push(make_pair(flips + flip, v)); } } } int ans = 2100000000; for (int j = 0; j <= 25; j++) if (d1[j][n] != -1) { ans = min(ans, (1 << j) - 1 + d1[j][n]); } if (ans < 2100000000) { cout << ans << endl; return 0; } priority_queue<pair<pair<int, int>, pair<int, int>>> q2; q2.push(make_pair(make_pair(0, 0), make_pair(0, 1))); for (int i = 1; i <= n; i++) for (int j = 0; j <= 1; j++) d2[j][i] = make_pair(2100000000, 2100000000); d2[0][1] = make_pair(0, 0); while (!q2.empty()) { pair<pair<int, int>, pair<int, int>> top = q2.top(); q2.pop(); int flipsbit = top.second.first, u = top.second.second; if (vis[flipsbit][u]) continue; vis[flipsbit][u] = 1; int flips = d2[flipsbit][u].first, dist = d2[flipsbit][u].second; for (auto i : G[u]) { int v = i.first, f = i.second; int flip = (flipsbit ^ f); int vflipsbit = ((flips + flip) & 1); pair<int, int> dv = make_pair(flips + flip, dist + 1); if (d2[vflipsbit][v] > dv) { d2[vflipsbit][v] = dv; q2.push(make_pair(make_pair(-dv.first, -dv.second), make_pair(vflipsbit, v))); } } } int flips = d2[0][n].first, dist = d2[0][n].second; if (d2[1][n].first < d2[0][n].first) { flips = d2[1][n].first, dist = d2[1][n].second; } long long ans2 = (qpow(2, flips) + dist - 1) % mod; cout << ans2 << endl; } |
#include <bits/stdc++.h> using namespace std; vector<int> graph[100001]; int color[100001]; vector<int> b, w; void bfs(int v) { queue<int> q; q.push(v); color[v] = 1; b.push_back(v); while (!q.empty()) { int v = q.front(); q.pop(); for (int u : graph[v]) { if (color[u] == 0) { if (color[v] == 1) color[u] = 2, w.push_back(u); else color[u] = 1, b.push_back(u); q.push(u); } if (color[v] == color[u]) { printf( -1 ); exit(0); } } } } int main() { int n, m; scanf( %d %d , &n, &m); while (m--) { int a, b; scanf( %d %d , &a, &b); graph[a].push_back(b); graph[b].push_back(a); } for (int i = 1; i <= n; i++) if (color[i] == 0) bfs(i); printf( %d n , (int)b.size()); for (int i = 0; i < b.size(); i++) printf( %d , b[i]); printf( n%d n , (int)w.size()); for (int i : w) printf( %d , i); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, d; int a[105]; int main() { ios_base::sync_with_stdio(false); cin >> n >> d; for (int i = 0; i < n; i++) cin >> a[i]; int dp[n][n]; sort(a, a + n); for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) dp[i][j] = a[j] - a[i]; } int ans = 0; for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { if (dp[i][j] <= d) ans = max(ans, j - i + 1); } } cout << n - ans; return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ns / 1ps
module clk_gen(
input CLKIN,
output wire BUS_CLK,
output U2_CLK5,
output U2_CLK80,
output U2_CLK160,
output U2_CLK320,
output SPI_CLK,
output LOCKED
);
wire GND_BIT;
assign GND_BIT = 0;
wire U1_CLK0, U1_CLK0_BUF, U1_CLKDV, U1_CLKDV_BUF;
assign BUS_CLK = U1_CLK0_BUF;
wire U2_CLKDV_BUF, U2_CLK0_BUF, U2_CLK2X_BUF, U2_CLKFX_BUF;
assign U2_CLK5 = U2_CLKDV_BUF;
assign U2_CLK80 = U2_CLK0_BUF;
assign U2_CLK160 = U2_CLK2X_BUF;
assign U2_CLK320 = U2_CLKFX_BUF;
BUFG CLKFB_BUFG_INST (.I(U1_CLK0), .O(U1_CLK0_BUF));
BUFG CLKDV_BUFG_INST (.I(U1_CLKDV), .O(U1_CLKDV_BUF));
assign SPI_CLK = U1_CLKDV_BUF;
wire U1_CLKFX;
DCM #(
.CLKDV_DIVIDE(4), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(3), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(5), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.833), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_BUS (
.CLKFB(U1_CLK0_BUF),
.CLKIN(CLKIN),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(U1_CLKDV),
.CLKFX(U1_CLKFX),
.CLKFX180(),
.CLK0(U1_CLK0),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED),
.PSDONE(),
.STATUS());
wire U1_CLKFX_BUF, U2_CLKDV;
wire U2_CLK0, U2_CLKFX, U2_CLK2X;
BUFG CLKFX_2_BUFG_INST (.I(U1_CLKFX), .O(U1_CLKFX_BUF));
BUFG CLKDV_2_BUFG_INST (.I(U2_CLKDV), .O(U2_CLKDV_BUF));
BUFG CLKFB_2_BUFG_INST (.I(U2_CLK0), .O(U2_CLK0_BUF));
BUFG CLKFX2_2_BUFG_INST (.I(U2_CLKFX), .O(U2_CLKFX_BUF));
BUFG U2_CLK2X_INST (.I(U2_CLK2X), .O(U2_CLK2X_BUF));
DCM #(
.CLKDV_DIVIDE(16), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(4), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(2), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(12.5), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_U2 (
.DSSEN(GND_BIT),
.CLK0(U2_CLK0), // 0 degree DCM_SP CLK output
.CLK180(), // 180 degree DCM_SP CLK output
.CLK270(), // 270 degree DCM_SP CLK output
.CLK2X(U2_CLK2X), // 2X DCM_SP CLK output
.CLK2X180(), // 2X, 180 degree DCM_SP CLK out
.CLK90(), // 90 degree DCM_SP CLK output
.CLKDV(U2_CLKDV), // DCM_SP CLK out (CLKDV_DIVIDE)
.CLKFX(U2_CLKFX), // DCM_SP CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM_SP LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM_SP status bits output
.CLKFB(U2_CLK0_BUF), // DCM_SP clock feedback
.CLKIN(U1_CLKFX_BUF), // Clock input (from IBUFG, BUFG or DCM_SP)
.PSCLK(GND_BIT), // Dynamic phase adjust clock input
.PSEN(GND_BIT), // Dynamic phase adjust enable input
.PSINCDEC(GND_BIT), // Dynamic phase adjust increment/decrement
.RST(GND_BIT)// // DCM_SP asynchronous reset input
);
/*
X 48
2X - 96
DV 12
FX 80
X 80
2X 160
DV 5
FX 320
*/
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "mul4x4.v"
module alu(
input [WIDTH-1 : 0] a,
input [WIDTH-1 : 0] b,
input mul_enable,
input sub_enable,
input shift_enable,
input [2 : 0] shift_pos,
output [WIDTH-1 : 0] result,
output carry_out);
parameter WIDTH = 8;
wire [WIDTH-1 : 0] adder_res;
wire adder_carry;
wire [7 : 0] shift_res;
wire shift_carry;
wire [7: 0] mul_res;
assign result = (mul_enable) ? mul_res :
(shift_enable) ? shift_res :
(adder_res);
assign carry_out = (shift_enable) ? shift_carry :
adder_carry;
fadder #(.WIDTH(WIDTH)) ripple_adder(
.a(a),
.b(b),
.sub_enable(sub_enable),
.carry_in(sub_enable),
.res(adder_res),
.carry_out(adder_carry));
shl8 left_shift(
.a(a),
.shift(shift_pos),
.res(shift_res),
.carry(shift_carry));
mul4x4 multiply(a[3:0], a[7:4], mul_res);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mas[1010]; unordered_map<long long, int> sootv; long long num[100100]; long long gcd(long long a, long long b) { if (!a) return b; return gcd(b % a, a); } int main() { int n; long long k; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> mas[i]; } if (k == 1) { cout << 1 << endl; int minidx = 1; for (int i = 0; i < n; i++) { if (mas[i] < mas[minidx]) minidx = i; } cout << minidx + 1; return 0; } vector<long long> divs; vector<long long> rdivs; for (long long i = 1; i * i <= k; i++) { if (k % i == 0) { divs.push_back(i); if (i * i != k) { rdivs.push_back(k / i); } } } for (auto it = rdivs.rbegin(); it != rdivs.rend(); it++) { divs.push_back(*it); } int cnt = 1; sootv.rehash((int)(divs).size() * 5); for (int i = 0; i < (int)(divs).size(); i++) { sootv.emplace(divs[i], cnt); num[cnt] = divs[i]; cnt++; } int oo = 1e9; vector<vector<int> > dp(n + 3); vector<vector<long long> > sum(n + 3); vector<vector<int> > lst(n + 3); for (int i = 0; i < (int)(dp).size(); i++) { dp[i].resize(cnt + 3); lst[i].resize(cnt + 3); sum[i].resize(cnt + 3); for (int j = 0; j < (int)(dp[i]).size(); j++) { dp[i][j] = oo; } for (int j = 0; j < (int)(lst[i]).size(); j++) { lst[i][j] = -1; } for (int j = 0; j < (int)(sum[i]).size(); j++) { sum[i][j] = (long long)oo * (long long)oo; } } dp[0][sootv[k]] = 0; sum[0][sootv[k]] = 0; int res = oo; for (int i = 0; i < n; i++) { for (int divi = 1; divi < cnt; divi++) { if (dp[i][divi] >= oo) continue; if (dp[i + 1][divi] > dp[i][divi] || dp[i + 1][divi] == dp[i][divi] && sum[i + 1][divi] > sum[i][divi]) { lst[i + 1][divi] = divi; dp[i + 1][divi] = dp[i][divi]; sum[i + 1][divi] = sum[i][divi]; } long long nxt = num[divi] / gcd(num[divi], mas[i]); if (nxt == num[divi]) continue; int idx = sootv[nxt]; if (dp[i + 1][idx] > dp[i][divi] + 1 || dp[i + 1][idx] == dp[i][divi] + 1 && sum[i + 1][idx] > sum[i][divi] + mas[i]) { lst[i + 1][idx] = divi; dp[i + 1][idx] = dp[i][divi] + 1; sum[i + 1][idx] = sum[i][divi] + mas[i]; } } } res = dp[n][sootv[1]]; if (res == oo) { res = -1; cout << res << endl; return 0; } cout << res << endl; vector<int> path; int cur = sootv[1]; for (int i = n; i >= 1; i--) { int l = lst[i][cur]; if (l != cur) { path.push_back(i); } cur = l; if ((int)(path).size() == res) break; } for (int i = (int)(path).size() - 1; i >= 0; i--) printf( %d , path[i]); return 0; } |
//----------------------------------------------------------------------------
// Wishbone SRAM controller
//----------------------------------------------------------------------------
module wb_sram16 #(
parameter adr_width = 19,
parameter latency = 0 // 0 .. 7
) (
input clk,
input reset,
// Wishbone interface
input wb_stb_i,
input wb_cyc_i,
input wb_tga_i,
output reg wb_ack_o,
input wb_we_i,
input [18:0] wb_adr_i,
input [1:0] wb_sel_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
// SRAM connection
output reg [adr_width-1:0] sram_adr,
inout [15:0] sram_dat,
output reg [1:0] sram_be_n, // Byte Enable
output reg sram_ce_n, // Chip Enable
output reg sram_oe_n, // Output Enable
output reg sram_we_n // Write Enable
);
//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
// Wishbone handling
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
// Translate wishbone address to sram address
wire [adr_width-1:0] adr = wb_adr_i[adr_width-1:0];
// Tri-State-Driver
reg [15:0] wdat;
reg wdat_oe;
assign sram_dat = wdat_oe ? wdat : 16'bz;
// Latency countdown
reg [2:0] lcount;
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
parameter s_idle = 0;
parameter s_read = 1;
parameter s_write = 2;
reg [2:0] state;
always @(posedge clk)
begin
if (reset) begin
state <= s_idle;
lcount <= 0;
wb_ack_o <= 0;
end else begin
case (state)
s_idle: begin
wb_ack_o <= 0;
if (wb_rd) begin
sram_ce_n <= 0;
sram_oe_n <= 0;
sram_we_n <= 1;
sram_adr <= adr;
sram_be_n <= 2'b00;
wdat_oe <= 0;
lcount <= latency;
state <= s_read;
end else if (wb_wr) begin
sram_ce_n <= 0;
sram_oe_n <= 1;
sram_we_n <= 0;
sram_adr <= adr;
sram_be_n <= ~wb_sel_i;
wdat <= wb_dat_i;
wdat_oe <= 1;
lcount <= latency;
state <= s_write;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wdat_oe <= 0;
end
end
s_read: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wb_dat_o <= sram_dat;
wb_ack_o <= 1;
state <= s_idle;
end
end
s_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wb_ack_o <= 1; // XXX We could acknoledge write XXX
state <= s_idle; // XXX requests 1 cycle ahead XXX
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; int main() { long long n, k; cin >> n >> k; map<int, int, greater<int> > st; long long n1 = n; for (int i = 0; n1 > 0; ++i) { if (n1 & 1) st[i] = 1; n1 >>= 1; } k -= (int)(st.size()); if (k < 0) { cout << No n ; return 0; } while (k > 0) { auto it = *st.begin(); if (k >= it.second) { st.erase(it.first); st[it.first - 1] += it.second * 2; k -= it.second; } else { auto it = *st.rbegin(); st[it.first] -= 1; st[it.first - 1] += 2; k -= 1; if (st[it.first] == 0) st.erase(it.first); } } cout << Yes n ; for (auto it : st) { for (int i = 0; i < (it.second); ++i) cout << it.first << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, i; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> n >> s; for (i = 1; i <= n; i++) { if (n % i == 0) { reverse(s.begin(), s.begin() + i); } } cout << s; } |
#include <bits/stdc++.h> using namespace std; const long long mm = 2; long long n, m0[mm][mm], m1[mm][mm] = {{0, 1}, {2, 1}}, mz[mm][mm], tmp[mm][mm], pwk, dv = 1e9 + 7; void cop(long long x[mm][mm], long long y[mm][mm]) { long long i, j; for (i = 0; i < mm; i++) { for (j = 0; j < mm; j++) { y[i][j] = x[i][j]; } } } void mul(long long x[mm][mm], long long y[mm][mm], long long z[mm][mm]) { long long i, j, r; for (i = 0; i < mm; i++) { for (j = 0; j < mm; j++) { tmp[i][j] = 0; for (r = 0; r < mm; r++) { tmp[i][j] = (tmp[i][j] + x[i][r] * y[r][j]) % dv; } } } cop(tmp, z); } long long pw(long long x, long long y) { if (!y) { return 1; } pwk = pw(x, y / 2); pwk = pwk * pwk % dv; if (y % 2) { pwk = pwk * x % dv; } return pwk; } void mpw(long long x) { if (!x) { cop(m0, mz); return; } mpw(x / 2); mul(mz, mz, mz); if (x % 2) { mul(mz, m1, mz); } } int main() { long long i, k, dn = 2; for (i = 0; i < mm; i++) { m0[i][i] = 1; } scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld , &k); mpw(k); cop(mz, m1); dn = pw(dn, k) % dv; } printf( %lld/%lld n , mz[0][0] * pw(2, dv - 2) % dv, dn * pw(2, dv - 2) % dv); } |
#include <bits/stdc++.h> using namespace std; int t, n, a[110]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) a[i] %= 2; int sum = 0; for (int i = 0; i < n; i++) sum += a[i]; if (sum == 0 || sum == n) printf( YES n ); else printf( NO n ); } } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( O1 ) #pragma GCC optimize( O2 ) #pragma GCC optimize( Os ) #pragma GCC optimize( Ofast ) #pragma GCC target( avx2 ) #pragma GCC optimization( unroll-loops ) long long int gcd(long long int a, long long int b) { return (b ? gcd(b, a % b) : a); } long long int P(long long int B, long long int power, long long int modulo) { long long int ans = 1LL; while (power > 0LL) { if (power % 2LL == 1LL) { ans = (ans * B) % modulo; } B = (B * B) % modulo; power /= 2LL; } return ans; } bool isPrime(long long int n) { if (n <= 1LL) { return false; } if (n <= 3LL) { return true; } if (n % 2 == 0LL || n % 3 == 0LL) { return false; } for (long long int i = 5LL; (i * i) <= n; i += 6LL) { if (n % i == 0LL || n % (i + 2LL) == 0LL) { return false; } } return true; } using namespace std; void vok() { ios_base::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); } const int mxN = int(1e5) + 100; int dp[mxN]; bool vis[mxN]; void dfs(int u, vector<int> graph[]) { vis[u] = 1; for (auto x : graph[u]) { if (!vis[x]) { dfs(x, graph); } dp[u] = max(dp[u], dp[x] + 1); } } int main() { vok(); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; vector<int> v(n); set<int> index; for (int i = 0; i < n; i++) { cin >> v[i]; if (v[i] == k) { index.insert(i); } } if (int(index.size()) == 0) { cout << no << n ; continue; } bool flag = false; for (int i = 0; i < n - 1; i++) { if (v[i] >= k && v[i + 1] >= k) { flag = true; break; } if (i < n - 2) { if (v[i] >= k && v[i + 2] >= k) { flag = true; break; } } } if (flag || int(index.size()) == n || n == 1) { cout << yes << n ; continue; } cout << no << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int> > AdjList; vector<int> dist; vector<int> unused; void update() { queue<int> now; for (int i = 0; i < unused.size(); i++) { dist[unused[i]] = 0; now.push(unused[i]); } while (!now.empty()) { int u = now.front(); now.pop(); for (int i = 0; i < AdjList[u].size(); i++) { int v = AdjList[u][i]; if (dist[u] + 1 < dist[v]) { dist[v] = dist[u] + 1; now.push(v); } } } unused.clear(); } int main() { int V, q; cin >> V >> q; AdjList.assign(V + 1, vector<int>()); dist.assign(V + 1, -1); for (int x, y, i = 0; i < V - 1; i++) { cin >> x >> y; AdjList[x].push_back(y); AdjList[y].push_back(x); } dist[1] = 0; queue<int> now; now.push(1); while (!now.empty()) { int u = now.front(); now.pop(); for (int i = 0; i < AdjList[u].size(); i++) { int v = AdjList[u][i]; if (dist[v] == -1) { dist[v] = dist[u] + 1; now.push(v); } } } for (int t, from, i = 0; i < q; i++) { cin >> t >> from; if (t == 1) { unused.push_back(from); } else { update(); cout << dist[from] << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_LS__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_BLACKBOX_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_underflow (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 0;
parameter max = ((1<<width)-1);
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_UNDERFLOW";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_underflow_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_underflow_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_underflow_psl_logic.v"
`else
`endmodule // ovl_no_underflow
`endif
|
#include <bits/stdc++.h> const int MAXN = (int)1e5 + 5; const int MODN = (int)1e9 + 7; int inf = 0x3f3f3f3f; using namespace std; char str[MAXN]; int num[MAXN]; int a[MAXN]; struct Com { int cost; int qua; } c[MAXN]; int cmp(Com a, Com b) { return a.cost < b.cost; } int main() { int n, m; while (scanf( %d , &n) != EOF) { for (int i = 0; i < n; i++) { scanf( %d%d , &c[i].cost, &c[i].qua); } sort(c, c + n, cmp); int flag = 0; for (int i = 1; i < n; i++) { if (c[i].qua < c[i - 1].qua && c[i].cost > c[i - 1].cost) { flag = 1; } } if (flag) puts( Happy Alex ); else puts( Poor Alex ); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_2_V
`define SKY130_FD_SC_LS__SEDFXBP_2_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxbp_2 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; int to[2000]; char used[2000]; int a[2000]; int s; char res[3000]; int calc(int x, char &f) { f = 0; int cnt = 1; if (x == s) f = 1; while (to[x] != -1) { ++cnt; x = to[x]; if (x == s) { f = 1; cnt = 1; } } return cnt; } int main() { int n, x; cin >> n >> x; --x; s = x; for (int i = 0; i < n; ++i) to[i] = -1; for (int i = 0; i < n; ++i) { cin >> to[i]; --to[i]; if (to[i] >= 0) used[to[i]] = 1; } int sl = -1; int q = 0; for (int i = 0; i < n; ++i) if (!used[i]) { char f; int len = calc(i, f); if (f) sl = len; else a[q++] = len; } assert(sl != -1); res[sl] = 1; for (int i = 0; i < q; ++i) { for (int j = n; j >= 0; --j) if (res[j]) res[j + a[i]] = 1; } for (int i = 0; i <= n; ++i) if (res[i]) cout << i << ; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 9e18; const int inf = 2147483647; long long qpow(long long a, long long b, long long mod) { long long r = 1; for (; b; b >>= 1) { if (b & 1) r = (r * a) % mod; a = (a * a) % mod; } return r; } const int N = 1e5 + 5; void work() { int t; scanf( %d , &t); while (t--) { int r, g, b, w; scanf( %d%d , &r, &g); scanf( %d%d , &b, &w); int sum = 0; if (r % 2) sum++; if (g % 2) sum++; if (b % 2) sum++; if (sum == 0) puts( YES ); else if (sum == 1) { puts(w % 2 == 0 ? YES : NO ); } else if (sum == 2) { if (r && g && b) puts(w % 2 ? YES : NO ); else puts( NO ); } else { puts( YES ); } } } int main() { work(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, t, d; cin >> n >> m; map<long long, long long> mp; set<pair<long long, long long> > st; vector<long long> a(n), c(n); for (int i = 0; i < n; i++) { cin >> a[i]; mp[i] = a[i]; } for (int i = 0; i < n; i++) { cin >> c[i]; st.insert({c[i], i}); } for (int i = 0; i < m; i++) { cin >> t >> d; long long cost = 0; t--; if (st.size() == 0) cout << 0 << endl; else { if (mp[t] != 0) { if (mp[t] > d) { mp[t] -= d; cout << (long long)d * c[t] << endl; d = 0; } else if (mp[t] == d) { mp[t] -= d; cout << (long long)d * c[t] << endl; d = 0; st.erase({c[t], t}); } else { cost += (long long)mp[t] * c[t]; d -= mp[t]; mp[t] = 0; st.erase({c[t], t}); } } if (d > 0) { while (d > 0 && st.size() > 0) { pair<int, int> now = *st.begin(); if (mp[now.second] > d) { mp[now.second] -= d; cout << (long long)cost + d * now.first << endl; d = 0; } else if (mp[now.second] == d) { mp[now.second] -= d; cout << (long long)cost + d * now.first << endl; d = 0; st.erase(st.begin()); } else { cost += (long long)mp[now.second] * now.first; d -= mp[now.second]; mp[now.second] = 0; st.erase(st.begin()); } } if (d > 0) { cout << 0 << endl; } } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ms__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_8_V
`define SKY130_FD_SC_HDLL__NOR2_8_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_8_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_memory2_0.hex";
output [ 63: 0] readdata;
input [ 12: 0] address;
input [ 7: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 63: 0] writedata;
wire clocken0;
wire [ 63: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 64,
the_altsyncram.width_byteena_a = 8,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int len, cnt[8010], f[8010], nxt[8010]; char st[8010]; void kmp(char *st, int len, int nxt[]) { nxt[0] = nxt[1] = 0; for (int i = 1; i < len; i++) { int j = nxt[i]; while (j && st[i] != st[j]) { j = nxt[j]; } nxt[i + 1] = st[j] == st[i] ? j + 1 : 0; } } int main() { cin >> st; len = strlen(st); for (int i = 1; i <= len; i++) { cnt[i] = cnt[i / 10] + 1, f[i] = i + 1; } for (int i = 0; i < len; i++) { kmp(st + i, len - i, nxt); for (int j = 1; j + i <= len; j++) { if (j % (j - nxt[j]) == 0) { f[j + i] = min(f[j + i], f[i] + cnt[j / (j - nxt[j])] + (j - nxt[j])); } else { f[j + i] = min(f[j + i], f[i] + 1 + j); } } } cout << f[len]; return 0; } |
// file: clk_wiz_v3_2.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
// Please set INPUT_FREQUENCY to the MHz of the incoming clock!!
// WARNING: This module will currently NOT handle anything other than a 100MHz
// clock because the CLKIN_PERIOD is not properly calculated.
//
// SYNTHESIS_FREQUENCY is used to determine at what frequency the design is
// synthesized for.
//
//
// NOTE: Internally, the divider is set to half of
// INPUT_FREQUENCY. This allows a greater range of output frequencies.
// So when you look at the COMM code, you'll see that it takes the requested
// frequency and divides by 2 to get the proper multiplier.
module dynamic_clock # (
parameter INPUT_FREQUENCY = 100,
parameter SYNTHESIS_FREQUENCY = 200
) (
input CLK_IN1,
output CLK_OUT1,
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE
);
// Input buffering
//------------------------------------
/*IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));*/
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
wire clkfx;
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (2),
.CLKFX_DIVIDE (INPUT_FREQUENCY >> 1),
.CLKFX_MULTIPLY (SYNTHESIS_FREQUENCY >> 1),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (CLK_IN1),
// Output clocks
.CLKFX (clkfx),
.CLKFX180 (),
.CLKFXDV (),
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (),
.STATUS (),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mxN = 1e5, mxV = 7001; int n, q, qt, xi, yi, zi; bitset<mxV> in[mxV], cq[mxV], ms[mxN], c; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); for (int i = 1; i < mxV; ++i) { for (int j = 0; (j += i) < mxV;) in[j][i] = 1; for (int j = i; j < mxV; ++j) { if (j == i ? !c[j] : c[j]) { for (int k = 0; (k += j) < mxV;) c.flip(k); cq[i][j] = 1; } } c.reset(); } cin >> n >> q; while (q--) { cin >> qt; if (qt == 1) { cin >> xi >> yi, --xi; ms[xi] = in[yi]; } else if (qt == 2) { cin >> xi >> yi >> zi, --xi, --yi, --zi; ms[xi] = ms[yi] ^ ms[zi]; } else if (qt == 3) { cin >> xi >> yi >> zi, --xi, --yi, --zi; ms[xi] = ms[yi] & ms[zi]; } else { cin >> xi >> yi, --xi; cout << ((ms[xi] & cq[yi]).count() & 1); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int m, n, l, r, mid, t; int a[200002], b[200002], ida[200002], idb[200002], to[200002]; long long ans[200002] = {}; template <class T> void read(T &x) { x = 0; int f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) f |= (ch == - ), ch = getchar(); while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + (ch ^ 48), ch = getchar(); x = f ? -x : x; return; } inline bool cmpa(int x, int y) { return a[x] > a[y] ? 1 : 0; } inline bool cmpb(int x, int y) { return b[x] > b[y] ? 1 : 0; } inline void add(int l, int r, long long d) { --l, r -= (l / n) * n, l %= n, ++l; if (r <= n) ans[l] += d, ans[r] -= d; else ans[l] += d, ans[1] += d, ans[(r - 1) % n + 1] -= d; } int main() { read(m), read(n); for (int i = 1; i <= n; ++i) read(a[i]), ida[i] = i; for (int i = 1; i <= n; ++i) read(b[i]), idb[i] = i; sort(ida + 1, ida + n + 1, cmpa), sort(idb + 1, idb + n + 1, cmpb); for (int i = 1; i <= n; ++i) { t = l = 1, r = n; while (l <= r) { mid = ((l + r) >> 1); if (a[ida[i]] < b[idb[mid]] - m / 2) l = mid + 1; else r = mid - 1; } add(t + n - i + 1, l + n - i + 1, m + a[ida[i]]), t = l, r = n; while (l <= r) { mid = ((l + r) >> 1); if (a[ida[i]] < b[idb[mid]]) l = mid + 1; else r = mid - 1; } add(t + n - i + 1, l + n - i + 1, -a[ida[i]]), t = l, r = n; while (l <= r) { mid = ((l + r) >> 1); if (a[ida[i]] <= b[idb[mid]] + m / 2) l = mid + 1; else r = mid - 1; } add(t + n - i + 1, l + n - i + 1, a[ida[i]]), add(l + n - i + 1, 2 * n - i + 2, m - a[ida[i]]), t = l = 1, r = n; while (l <= r) { mid = ((l + r) >> 1); if (b[idb[i]] < a[ida[mid]] - m / 2) l = mid + 1; else r = mid - 1; } add(n - l + i + 2, n - t + i + 2, b[idb[i]]), t = l, r = n; while (l <= r) { mid = ((l + r) >> 1); if (b[idb[i]] <= a[ida[mid]]) l = mid + 1; else r = mid - 1; } add(n - l + i + 2, n - t + i + 2, -b[idb[i]]), t = l, r = n; while (l <= r) { mid = ((l + r) >> 1); if (b[idb[i]] <= a[ida[mid]] + m / 2) l = mid + 1; else r = mid - 1; } add(n - l + i + 2, n - t + i + 2, b[idb[i]]), add(i + 1, n - l + i + 2, -b[idb[i]]); } t = 1; for (int i = 2; i <= n; ++i) if ((ans[i] += ans[i - 1]) < ans[t]) t = i; for (int i = 1; i <= n; ++i) to[ida[i]] = idb[(i + t - 2) % n + 1]; printf( %lld n , ans[t]); for (int i = 1; i <= n; ++i) printf( %d , to[i]); return 0; } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.