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#include <bits/stdc++.h> using namespace std; long long a, b, x; int n; int main() { scanf( %d , &n); scanf( %lld%lld , &a, &b); while (n--) { scanf( %lld , &x); printf( %lld , ((x * a) - b * ((x * a) / b)) / a); } return 0; } |
#include <bits/stdc++.h> using namespace std; unsigned long long pow_of_two[10000]; int create() { unsigned long long i = 0; unsigned long long num = 1; while (num <= INT_MAX and num >= 0) { num = pow(2, i); pow_of_two[i] = num; i++; } } int main() { int n; cin >> n; string str; cin >> str; int len = str.length(); int swapi = 0; for (int i = len - 1; i >= 0; i--) { if (str[i] == 1 ) { for (int j = i - 1; j >= 0; j--) { if (str[j] == 1 ) { int left = j; int right = i; while (left + 1 < right) { swap(str[right], str[right - 1]); right--; swapi++; } if (str[right] == 1 && str[right - 1] == 1 ) { str[right] = 4 ; } break; } } } } for (int i = 0; i < str.length(); i++) { if (str[i] != 4 ) cout << str[i]; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); long long n; cin >> n; long long a[n]; map<long long, long long> m, ans; vector<long long> v; for (long long i = 0; i < n; i++) { cin >> a[i]; if (m[a[i]] == 0 && a[i] <= n) { m[a[i]] = 1; ans[i] = a[i]; } else { v.push_back(i); } } long long j = 0; for (long long i = 1; i <= n; i++) { if (m[i] == 0) { ans[v[j]] = i; j++; } } for (long long i = 0; i < n; i++) { cout << ans[i] << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, n, x, y; scanf( %d , &t); while (t--) { scanf( %d%d%d , &n, &x, &y); int d, dif = y - x; for (int i = 1; i <= dif; i++) { if (dif % i == 0 && (dif / i <= n - 1)) { d = i; break; } } printf( %d , y); n--; int val = y - d; while (val > 0 && n > 0) { n--; printf( %d , val); val -= d; } val = y + d; while (n > 0) { n--; printf( %d , val); val += d; } printf( n ); } } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_20_64.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_20_64 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [19:0] data;
input rdreq;
input wrreq;
output empty;
output [19:0] q;
wire sub_wire0;
wire [19:0] sub_wire1;
wire empty = sub_wire0;
wire [19:0] q = sub_wire1[19:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 20,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "20"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "20"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "20"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 20 0 INPUT NODEFVAL "data[19..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 20 0 OUTPUT NODEFVAL "q[19..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 20 0 data 0 0 20 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 20 0 @q 0 0 20 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_20_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_20_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_20_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_20_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_20_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_20_64_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_arb2
#(
// Configuration
parameter string PIPELINE = "data_stall", // none|data|stall|data_stall|stall_data
parameter integer KEEP_LAST_GRANT = 1, // 0|1 - if one request can last multiple cycles (e.g. write burst), KEEP_LAST_GRANT must be 1
parameter integer NO_STALL_NETWORK = 0, // 0|1 - if one, remove the ability for arb to stall backward - must guarantee no collisions!
// Masters
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
// INPUTS
input logic clock,
input logic resetn,
// INTERFACES
acl_arb_intf m0_intf,
acl_arb_intf m1_intf,
acl_arb_intf mout_intf
);
/////////////////////////////////////////////
// ARCHITECTURE
/////////////////////////////////////////////
// mux_intf acts as an interface immediately after request arbitration
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
mux_intf();
// Selector and request arbitration.
logic mux_sel;
assign mux_intf.req = mux_sel ? m1_intf.req : m0_intf.req;
generate
if( KEEP_LAST_GRANT == 1 )
begin
logic last_mux_sel_r;
always_ff @( posedge clock )
last_mux_sel_r <= mux_sel;
always_comb
// Maintain last grant.
if( last_mux_sel_r == 1'b0 && m0_intf.req.request )
mux_sel = 1'b0;
else if( last_mux_sel_r == 1'b1 && m1_intf.req.request )
mux_sel = 1'b1;
// Arbitrarily favor m0.
else
mux_sel = m0_intf.req.request ? 1'b0 : 1'b1;
end
else
begin
// Arbitrarily favor m0.
assign mux_sel = m0_intf.req.request ? 1'b0 : 1'b1;
end
endgenerate
// Stall signal for each upstream master.
generate
if( NO_STALL_NETWORK == 1 )
begin
assign m0_intf.stall = '0;
assign m1_intf.stall = '0;
end
else
begin
assign m0_intf.stall = ( mux_sel & m1_intf.req.request) | mux_intf.stall;
assign m1_intf.stall = (~mux_sel & m0_intf.req.request) | mux_intf.stall;
end
endgenerate
// What happens at the output of the arbitration block? Depends on the pipelining option...
// Each option is responsible for the following:
// 1. Connecting mout_intf.req: request output of the arbitration block
// 2. Connecting mux_intf.stall: upstream (to input masters) stall signal
generate
if( PIPELINE == "none" )
begin
// Purely combinational. Not a single register to be seen.
// Request for downstream blocks.
assign mout_intf.req = mux_intf.req;
// Stall signal from downstream blocks
assign mux_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "data" )
begin
// Standard pipeline register at output. Latency of one cycle.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_intf();
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( pipe_intf )
);
// Request for downstream blocks.
assign mout_intf.req = pipe_intf.req;
// Stall signal from downstream blocks.
assign pipe_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "stall" )
begin
// Staging register at output. Min. latency of zero cycles, max. latency of one cycle.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_intf();
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( staging_intf )
);
// Request for downstream blocks.
assign mout_intf.req = staging_intf.req;
// Stall signal from downstream blocks.
assign staging_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "data_stall" )
begin
// Pipeline register followed by staging register at output. Min. latency
// of one cycle, max. latency of two cycles.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_intf(), staging_intf();
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( pipe_intf )
);
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( pipe_intf ),
.out_intf( staging_intf )
);
// Request for downstream blocks.
assign mout_intf.req = staging_intf.req;
// Stall signal from downstream blocks.
assign staging_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "stall_data" )
begin
// Staging register followed by pipeline register at output. Min. latency
// of one cycle, max. latency of two cycles.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_intf(), pipe_intf();
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( staging_intf )
);
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( staging_intf ),
.out_intf( pipe_intf )
);
// Request for downstream blocks.
assign mout_intf.req = pipe_intf.req;
// Stall signal from downstream blocks.
assign pipe_intf.stall = mout_intf.stall;
end
endgenerate
endmodule
module acl_arb_pipeline_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
input clock,
input resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
acl_arb_data #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_r();
// Pipeline register.
always @( posedge clock or negedge resetn )
if( !resetn )
begin
pipe_r.req <= 'x; // only signals reset explicitly below need to be reset at all
pipe_r.req.request <= 1'b0;
pipe_r.req.read <= 1'b0;
pipe_r.req.write <= 1'b0;
end
else if( !(out_intf.stall & pipe_r.req.request) )
pipe_r.req <= in_intf.req;
// Request for downstream blocks.
assign out_intf.req = pipe_r.req;
// Upstream stall signal.
assign in_intf.stall = out_intf.stall & pipe_r.req.request;
endmodule
module acl_arb_staging_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
input clock,
input resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
logic stall_r;
acl_arb_data #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_r();
// Staging register.
always @( posedge clock or negedge resetn )
if( !resetn )
begin
staging_r.req <= 'x; // only signals reset explicitly below need to be reset at all
staging_r.req.request <= 1'b0;
staging_r.req.read <= 1'b0;
staging_r.req.write <= 1'b0;
end
else if( !stall_r )
staging_r.req <= in_intf.req;
// Stall register.
always @( posedge clock or negedge resetn )
if( !resetn )
stall_r <= 1'b0;
else
stall_r <= out_intf.stall & (stall_r | in_intf.req.request);
// Request for downstream blocks.
assign out_intf.req = stall_r ? staging_r.req : in_intf.req;
// Upstream stall signal.
assign in_intf.stall = stall_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, countt = 0, counts = 0, maxi = 0; cin >> n >> k; long long int a[n]; for (long long int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == -1) counts++; else countt++; } for (long long int b = 0; b < k; b++) { long long int ts = counts, tt = countt; for (long long int j = 0; b + (j * k) + 1 <= n; j++) { if (a[b + (j * k) + 1] == -1) ts--; else tt--; } maxi = max(maxi, abs(ts - tt)); } cout << maxi << endl; return 0; } |
`ifndef SHIFTER_V
`define SHIFTER_V
`include "mux.v"
`ifndef WIDTH
`define WIDTH 32
`endif
`ifndef SHIFT_WIDTH
`define SHIFT_WIDTH 5
`endif
`ifndef OPS
`define OPS 2
`endif
`define LEFT_SHIFTA 2'b00
`define LEFT_SHIFTL 2'b01
`define RIGHT_SHIFTA 2'b10
`define RIGHT_SHIFTL 2'b11
module shifter(
input[`WIDTH - 1:0] i_data,
input[`SHIFT_WIDTH - 1:0] i_shift,
input[`OPS - 1:0] i_op,
input i_start,
output[`WIDTH - 1:0] o_result);
reg[`WIDTH - 1:0] zeroes;
reg[`WIDTH - 1:0] ones;
reg[`WIDTH - 1:0] result;
initial begin
zeroes = 0;
ones = ~0;
end
wire[`WIDTH - 1: 0] left;
wire[`WIDTH - 1: 0] right;
wire[`WIDTH - 1: 0] rightA;
assign o_result = result;
genvar i;
generate
for (i = 0; i < `WIDTH; i = i + 1) begin
if (i == 0)
mux #(.width(`WIDTH), .channels(`WIDTH)) m(i_data, `WIDTH - i_shift - 1, left[`WIDTH - i - 1]);
else
mux #(.width(`WIDTH), .channels(`WIDTH)) m({i_data[`WIDTH - 1 - i:0], zeroes[i - 1:0]}, `WIDTH - 1 - i_shift, left[`WIDTH - i - 1]);
if (i == 0)
mux #(.width(`WIDTH), .channels(`SHIFT_WIDTH)) m(i_data, i_shift, right[i]);
else
mux #(.width(`WIDTH), .channels(`SHIFT_WIDTH)) m({zeroes[i-1:0], i_data[`WIDTH-1:i]}, i_shift, right[i]);
if (i == 0)
mux #(.width(`WIDTH), .channels(`SHIFT_WIDTH)) m(i_data, i_shift, rightA[i]);
else
mux #(.width(`WIDTH), .channels(`SHIFT_WIDTH)) m({ones[i-1:0], i_data[`WIDTH-1:i]}, i_shift, rightA[i]);
end
endgenerate
always @* begin
if (i_start) begin
case (i_op)
`LEFT_SHIFTA: result <= left;
`LEFT_SHIFTL: result <= left;
`RIGHT_SHIFTA: result <= i_data[`WIDTH-1] == 1'b1 ? rightA : right;
`RIGHT_SHIFTL: result <= right;
default: $display("Error!");
endcase
end
end
endmodule
`endif
|
#include <bits/stdc++.h> int main() { long int n, m; int t; scanf( %d , &t); while (t--) { scanf( %ld%ld , &n, &m); if (n == 1) printf( 0 n ); else if (n == 2) { printf( %ld n , m); } else { printf( %ld n , 2 * m); } } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using lpair = pair<ll, ll>; const ll MOD = 1e9 + 7; const ll INF = 8e18; void print() {} template <class H, class... T> void print(H&& h, T&&... t) { cout << h << n [sizeof...(t) == 0]; print(forward<T>(t)...); } int main() { cin.tie(0); ios::sync_with_stdio(false); ll t; cin >> t; while (t--) { ll nr, ng, nb; cin >> nr >> ng >> nb; vector<ll> r(nr), g(ng), b(nb); for (ll i = (0); i < (nr); i++) cin >> r[i]; for (ll i = (0); i < (ng); i++) cin >> g[i]; for (ll i = (0); i < (nb); i++) cin >> b[i]; sort(r.begin(), r.end()); sort(g.begin(), g.end()); sort(b.begin(), b.end()); ll ans = INF; vector<lpair> lp; for (ll i = (0); i < (nr); i++) { lp.push_back({r[i], 0}); } for (ll i = (0); i < (ng); i++) { lp.push_back({g[i], 1}); } for (ll i = (0); i < (nb); i++) { lp.push_back({b[i], 2}); } sort(lp.begin(), lp.end()); vector<ll> pr, pg, pb; for (ll i = (0); i < (nr + ng + nb); i++) { if (lp[i].second == 0) { pr.push_back(i); } else if (lp[i].second == 1) { pg.push_back(i); } else { pb.push_back(i); } } for (ll i = (1); i < (nr + ng + nb - 1); i++) { if (lp[i].second == 0) { ll val_g = -1, val_b = -1; ll pos = lower_bound(pg.begin(), pg.end(), i) - pg.begin(); if (pos != 0) { val_g = g[pos - 1]; } pos = lower_bound(pb.begin(), pb.end(), i) - pb.begin(); if (pos != nb) { val_b = b[pos]; } if (val_g != -1 && val_b != -1) { ll val_r = lp[i].first; ll res = (val_r - val_g) * (val_r - val_g) + (val_r - val_b) * (val_r - val_b) + (val_b - val_g) * (val_b - val_g); ans = min(ans, res); } val_b = -1, val_g = -1; pos = lower_bound(pb.begin(), pb.end(), i) - pb.begin(); if (pos != 0) { val_b = b[pos - 1]; } pos = lower_bound(pg.begin(), pg.end(), i) - pg.begin(); if (pos != ng) { val_g = g[pos]; } if (val_g != -1 && val_b != -1) { ll val_r = lp[i].first; ll res = (val_r - val_g) * (val_r - val_g) + (val_r - val_b) * (val_r - val_b) + (val_b - val_g) * (val_b - val_g); ans = min(ans, res); } } else if (lp[i].second == 1) { ll val_r = -1, val_b = -1; ll pos = lower_bound(pr.begin(), pr.end(), i) - pr.begin(); if (pos != 0) { val_r = r[pos - 1]; } pos = lower_bound(pb.begin(), pb.end(), i) - pb.begin(); if (pos != nb) { val_b = b[pos]; } if (val_r != -1 && val_b != -1) { ll val_g = lp[i].first; ll res = (val_r - val_g) * (val_r - val_g) + (val_r - val_b) * (val_r - val_b) + (val_b - val_g) * (val_b - val_g); ans = min(ans, res); } val_r = -1, val_b = -1; pos = lower_bound(pb.begin(), pb.end(), i) - pb.begin(); if (pos != 0) { val_b = b[pos - 1]; } pos = lower_bound(pr.begin(), pr.end(), i) - pr.begin(); if (pos != nr) { val_r = r[pos]; } if (val_r != -1 && val_b != -1) { ll val_g = lp[i].first; ll res = (val_r - val_g) * (val_r - val_g) + (val_r - val_b) * (val_r - val_b) + (val_b - val_g) * (val_b - val_g); ans = min(ans, res); } } else { ll val_r = -1, val_g = -1; ll pos = lower_bound(pr.begin(), pr.end(), i) - pr.begin(); if (pos != 0) { val_r = r[pos - 1]; } pos = lower_bound(pg.begin(), pg.end(), i) - pg.begin(); if (pos != ng) { val_g = g[pos]; } if (val_r != -1 && val_g != -1) { ll val_b = lp[i].first; ll res = (val_r - val_g) * (val_r - val_g) + (val_r - val_b) * (val_r - val_b) + (val_b - val_g) * (val_b - val_g); ans = min(ans, res); } val_g = -1, val_r = -1; pos = lower_bound(pg.begin(), pg.end(), i) - pg.begin(); if (pos != 0) { val_g = g[pos - 1]; } pos = lower_bound(pr.begin(), pr.end(), i) - pr.begin(); if (pos != nr) { val_r = r[pos]; } if (val_r != -1 && val_g != -1) { ll val_b = lp[i].first; ll res = (val_r - val_g) * (val_r - val_g) + (val_r - val_b) * (val_r - val_b) + (val_b - val_g) * (val_b - val_g); ans = min(ans, res); } } } print(ans); } } |
#include <bits/stdc++.h> using namespace std; long long int a[200]; int main() { long long int n, ans = 0, m, i, j, x, y; cin >> n >> m; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= m; i++) { cin >> x >> y; long long int ret = 0; for (j = x; j <= y; j++) { ret += a[j]; } if (ret > 0) ans += ret; } cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
module INSTRUCTION_DECODER(input CLK, input [7:0] RXD, input RXD_START, input TXD_DONE, output TXD_ENABLE, output reg MUX_SEL,
output reg [9:0] RAM_ADDR, output reg [31:0] TRIG_DATA, output reg TRIG_UPDATE, output reg TRIG_FORCE);
/*0x01 SET TRIG CONDITION
*0x02 CHECK TRIGGERED
*0x03 FORCE TRIGGER
*0x04 READ DATA
*/
reg [2:0] STATE=0; /* 0 IDLE
* 1 SET TRIG CONDITION
* 2 SEND TRIG COMMAND
* 3 GET TRIGGERED
* 4 FORCE TRIG
* 5 READ
*/
reg [1:0] COUNT; //no. of bytes received
reg [23:0] TMP;
//reg TXD_ENABLE_INT; //uncomment for postiive edge-triggered TXD_ENABLE
reg TXD_ENABLE_INT;
assign TXD_ENABLE=TXD_ENABLE_INT;
//always@(posedge CLK) TXD_ENABLE<=TXD_ENABLE_INT;
always@(posedge CLK)
case(STATE)
0: begin
TXD_ENABLE_INT<=0;
TRIG_UPDATE<=0;
TRIG_FORCE<=0;
COUNT<=0;
if(RXD_START && RXD==1) begin
STATE<=1;
COUNT<=0;
end
if(RXD_START && RXD==2) begin
STATE<=3;
TXD_ENABLE_INT<=1;
end
if(RXD_START && RXD==3) STATE<=4;
if(RXD_START && RXD==4) begin
STATE<=5;
RAM_ADDR<=0;
//TXD_ENABLE_INT<=1;
end
end
1: begin
TRIG_UPDATE<=0;
if(COUNT<3 && RXD_START) begin
COUNT<=COUNT+1;
TMP<={TMP[15:0], RXD};
end
if(COUNT==3 && RXD_START) begin
TRIG_DATA<={TMP[23:0], RXD};
STATE<=2;
end
end
2: begin
TRIG_UPDATE<=1;
COUNT<=0;
STATE<=0;
end
3: begin
// TXD_ENABLE_INT<=0;
if(TXD_DONE) begin
STATE<=0;
TXD_ENABLE_INT<=0;
end
else MUX_SEL<=0;
end
4: begin
TRIG_FORCE<=1;
STATE<=0;
end
5: begin
MUX_SEL<=1;
//TXD_ENABLE_INT<=0;
TXD_ENABLE_INT<=1;
if(RAM_ADDR==1023 && TXD_DONE) STATE<=0;
else begin
if(TXD_DONE) begin
RAM_ADDR<=RAM_ADDR+1;
// TXD_ENABLE_INT<=1;
end
end
end
endcase
endmodule |
#include <bits/stdc++.h> using namespace std; int n, m; int xans[200005]; bool pos; vector<pair<int, int> > xoc[200005]; vector<pair<int, int> > V[200005]; int erased[200005]; queue<int> toErase; int sgn(int v) { return abs(v) / v; } vector<pair<int, int> > E[200005]; int vis[200005]; int cycleRoot; bool assigned[200005]; bool arcUsed[200005]; void dfs(int u) { vis[u] = 2; for (int i = 0, v, x, i1, i2; i < E[u].size(); i++) { v = E[u][i].first; x = E[u][i].second; if (!assigned[x]) { i1 = xoc[x][1].first == u; i2 = 1 - i1; xans[x] = (xoc[x][i2].second == 1); assigned[x] = true; if (vis[v] != 2) dfs(v); } } } bool findCycle(int u) { vis[u] = 1; for (int i = 0, v, x; i < E[u].size(); i++) { v = E[u][i].first; x = E[u][i].second; if (arcUsed[x]) continue; arcUsed[x] = true; if (vis[v]) { cycleRoot = v; return true; } else if (findCycle(v)) { return true; } } return false; } void makeE(int c1) { for (int i = 0, x, i1, i2, c2; i < V[c1].size(); i++) { x = V[c1][i].first; i1 = xoc[x][1].first == c1; i2 = 1 - i1; c2 = xoc[x][i2].first; if (c1 < c2) { E[c1].push_back(make_pair(c2, x)); E[c2].push_back(make_pair(c1, x)); } } } void erase(int c) { int x, s, i1, i2; for (int i = 0; i < V[c].size(); i++) { x = V[c][i].first; s = V[c][i].second; if (xoc[x].size() == 1) { xans[x] = (xoc[x][0].second == 1); } else { i1 = (xoc[x][1].first == c); i2 = 1 - i1; if (xoc[x][i1].second == xoc[x][i2].second) { xans[x] = xoc[x][i1].second == 1; if (!erased[xoc[x][i2].first]) { erased[xoc[x][i2].first] = 1; erase(xoc[x][i2].first); } } else { if (erased[xoc[x][i2].first]) { xans[x] = xoc[x][i1].second == 1; } else { erased[xoc[x][i2].first] = 1; erase(xoc[x][i2].first); } } } } } int main() { scanf( %d%d , &n, &m); int cs, x, s; for (int i = 0; i < n; i++) { scanf( %d , &cs); for (int j = 0; j < cs; j++) { scanf( %d , &x); s = sgn(x); x = abs(x) - 1; V[i].push_back(make_pair(x, s)); xoc[x].push_back(make_pair(i, s)); } } for (int x = 0, c1, c2; x < m; x++) { if (xoc[x].size() == 1) { c1 = xoc[x][0].first; if (!erased[c1]) { erased[c1] = 1; erase(c1); } } else if (xoc[x].size() == 2 && xoc[x][0].second == xoc[x][1].second) { c1 = xoc[x][0].first; if (!erased[c1]) { erased[c1] = 1; erase(c1); } c2 = xoc[x][1].first; if (!erased[c2]) { erased[c2] = 1; erase(c2); } } } for (int i = 0; i < n; i++) { if (!erased[i]) { makeE(i); } } pos = true; for (int u = 0; u < n; u++) { if (!erased[u] && !vis[u]) { if (findCycle(u)) { dfs(cycleRoot); } else { pos = false; break; } } } if (!pos) printf( NO n ); else { printf( YES n ); for (int i = 0; i < m; i++) printf( %d , xans[i]); printf( n ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__OR2B_FUNCTIONAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or2b (
VPWR,
VGND,
X ,
A ,
B_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B_N ;
// Local signals
wire X not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_SYMBOL_V
`define SKY130_FD_SC_HVL__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; set<pair<long long, long long> > S; set<pair<long long, long long> >::iterator it; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t, n; for (cin >> t; t--;) { cin >> n; S.clear(); long long a = 1, b = 0, ans = 0, u; for (int i = 0; i < n; i++) { cin >> u; long long s = a * (1 - b), e = a * (u - 1 - b); if (a < 0) swap(s, e); while (!S.empty()) { pair<long long, long long> v = *S.begin(); if (v.first >= s) break; else { S.erase(S.begin()); if (v.second >= s) S.insert(pair<long long, long long>(s, v.second)); } } while (!S.empty()) { it = S.end(); it--; pair<long long, long long> v = *it; if (v.second > e) S.erase(it); else break; if (v.first <= e) S.insert(pair<long long, long long>(v.first, e)); } if (S.empty()) { if (a > 0) S.insert(pair<long long, long long>(a * (1 - b), a * (u - b))); else S.insert(pair<long long, long long>(a * (u - b), a * (1 - b))); } else ans++; a *= -1, b = u - b; if (u % 2 == 0) { it = S.upper_bound( pair<long long, long long>(a * (u / 2 - b), 1000000000000000000ll)); if (it == S.begin()) S.insert( pair<long long, long long>(a * (u / 2 - b), a * (u / 2 - b))); else { it--; pair<long long, long long> v = *it; if (v.first <= a * (u / 2 - b) && v.second >= a * (u / 2 - b)) { S.clear(); a = 1; b = 0; ans++; } S.insert( pair<long long, long long>(a * (u / 2 - b), a * (u / 2 - b))); } } } cout << n * 2 - ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; #define int long long bool local=false; int z1; int n; vector <int> a; mt19937 rnd; int med(int x,int y,int z) { vector <int> h={x,y,z}; sort(h.begin(),h.end()); return h[1]; } int query(int u,int v,int w) { cout<< ? <<u+1<< <<v+1<< <<w+1<<endl; if(!local) { int ans; cin>>ans; return ans; } else { return med(abs(a[u]-a[v]),abs(a[v]-a[w]),abs(a[w]-a[u])); } } bool check(int x) { //cout<<n<< n <<endl; if(x==z1) return false; int sum=0; for(int i=0;i<18;++i) { int u=rnd()%n; int v=rnd()%n; if(u==v || u==z1 || u==x || v==z1 || v==x) {i--;continue;} int res1=query(u,v,z1);int res2=query(u,v,x); if(res1==(res2+1) || res1==res2) { ++sum; } } //cout<< trfe <<endl; return (sum==18); } int32_t main() { ios_base::sync_with_stdio(false);cin.tie(0);cout.tie(0); int t; cin>>t; while(t--) { cin>>n; a.clear(); rnd.seed(4824948+rnd()); if(local) { for(int i=0;i<n;++i) a.push_back(i+1); shuffle(a.begin(),a.end(),default_random_engine(rand()+rnd()+6432)); if(a[0]>a[1]) { for(int i=0;i<n;++i) a[i]=(n+1-a[i]); } } int ans1=1e9; vector <int> z; for(int i=0;i<200;++i) { int u=rnd()%n;int v=rnd()%n;int w=rnd()%n; if(u!=v && v!=w && w!=u) { int r=query(u,v,w); if(r<ans1) { ans1=r; z={u,v,w}; } } } vector <pair<int,int> > v; for(int x=0;x<n;++x) { if(x!=z[1] && x!=z[2]) { int res1=query(x,z[1],z[2]); v.push_back({res1,x}); } } sort(v.begin(),v.end());reverse(v.begin(),v.end()); int pos1=v[0].second; z1=pos1;int z2=(-1); int pos2=v[1].second; int pos3=v[2].second; int pos4=v[3].second; //cout<<z[0]<< <<z[1]<< <<z[2]<<endl; //cout<<pos1<< <<pos2<< <<pos3<< <<pos4<<endl; { if(check(pos2)) {z2=pos2;} else if(check(pos3)) {z2=pos3;} else if(check(pos4)) {z2=pos4;} else if(check(z[1])) {z2=z[1];} else if(check(z[2])) {z2=z[2];} } if(z2==(-1)) assert(false); vector <int> ans(n); ans[z1]=1; ans[z2]=2; for(int i=0;i<n;++i) { if(i!=z1 && i!=z2) { ans[i]=query(z1,z2,i)+2; } } if(ans[0]>ans[1]) for(int i=0;i<n;++i) ans[i]=(n+1-ans[i]); if(local) {for(int i=0;i<n;++i) cout<<a[i]<< ; cout<<endl;} cout<< ! ; for(int i=0;i<n;++i) cout<<ans[i]<< ; cout<<endl; int res; cin>>res; if(res==(-1)) { exit(0); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a; int count = 0, c = 0; cin >> a; count = a.size(); for (int i = 0; a[i] != 0 ; i++) { if (a[i] >= A && a[i] <= Z ) c++; } if ((c == count) || ((c == count - 1) && (a[0] >= a && a[0] <= z ))) { for (int i = 0; a[i] != 0 ; i++) { if (a[i] >= A && a[i] <= Z ) a[i] = a[i] + 32; else a[i] = a[i] - 32; } } for (int i = 0; a[i] != 0 ; i++) { cout << a[i]; } } |
#include <bits/stdc++.h> using namespace std; long long maxn = -1e18; long long minn = 1e18; long long mod = 1000000007; long long ans = 0; long long cur = 0; long long tong = 0, tong2 = 0; long long cnt = 0; long long k, l; string s; long long n, m, x, y; long long b[100005]; long long was[200005]; bool flag = true; vector<long long> node[200005]; long long dp[105][105]; long long a[55]; long long c[55]; map<string, int> ok; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> a[2] >> a[3] >> a[5] >> a[6]; cout << min(a[2], min(a[5], a[6])) * 256 + min(a[2] - min(a[2], min(a[5], a[6])), a[3]) * 32; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 100; const int oo = 1e9 + 7; int N; int H[MAXN]; deque<int> dq; int L[MAXN], R[MAXN], l[MAXN], r[MAXN]; int d[MAXN]; vector<int> G[MAXN]; void Dijkstra(int u) { for (int i = (1), _b = (N + 1); i <= _b; ++i) d[i] = +oo; d[u] = 0; priority_queue<pair<int, int>, vector<pair<int, int>>, greater<pair<int, int>>> pq; pq.push(pair<int, int>(0, u)); while (pq.size()) { int du = pq.top().first; int u = pq.top().second; pq.pop(); if (du != d[u]) continue; for (auto &v : G[u]) { if (d[v] > du + 1) { d[v] = du + 1; pq.push(pair<int, int>(d[v], v)); } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N; for (int i = (1), _b = (N); i <= _b; ++i) cin >> H[i]; dq.clear(); for (int i = (N), _a = (1); i >= _a; --i) { while (dq.size() && H[dq.front()] <= H[i]) dq.pop_front(); if (dq.size()) R[i] = dq.front() - 1; else R[i] = i; dq.push_front(i); } dq.clear(); for (int i = (1), _b = (N); i <= _b; ++i) { while (dq.size() && H[dq.front()] <= H[i]) dq.pop_front(); if (dq.size()) L[i] = dq.front() + 1; else L[i] = i; dq.push_front(i); } dq.clear(); for (int i = (1), _b = (N); i <= _b; ++i) { while (dq.size() && H[dq.front()] >= H[i]) dq.pop_front(); if (dq.size()) l[i] = dq.front() + 1; else l[i] = i; dq.push_front(i); } dq.clear(); for (int i = (N), _a = (1); i >= _a; --i) { while (dq.size() && H[dq.front()] >= H[i]) dq.pop_front(); if (dq.size()) r[i] = dq.front() - 1; else r[i] = i; dq.push_front(i); } for (int i = (1), _b = (N); i <= _b; ++i) G[i].push_back(i + 1); for (int i = (1), _b = (N); i <= _b; ++i) { if (H[i] < min(H[L[i] - 1], H[R[i] + 1])) { G[L[i] - 1].push_back(R[i] + 1); } } for (int i = (1), _b = (N); i <= _b; ++i) { if (max(H[l[i] - 1], H[r[i] + 1]) < H[i]) { G[l[i] - 1].push_back(r[i] + 1); } } Dijkstra(1); cout << d[N] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read(int f = 1, int x = 0, char ch = ) { while (!isdigit(ch = getchar())) if (ch == - ) f = -1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f * x; } const int N = 5e5 + 5; int n, m, f[N], g[N], fs[N], gs[N], ft[N], gt[N], cls[N]; vector<pair<int, long long> > s[N]; int find(int *p, int x) { return p[x] == x ? x : find(p, p[x]); } void merge(int *p, int *s, int *t, int x, int y, int z) { x = find(p, x), y = find(p, y); if (s[x] > s[y]) swap(x, y); p[x] = y, s[y] += s[x], t[x] = z; } long long ask(vector<pair<int, long long> > &s, int t) { return s.back().second - (--lower_bound(s.begin(), s.end(), pair<int, long long>(t, 0))) ->second; } int main() { n = read(), m = read(); for (int i = 1; i <= n; ++i) f[i] = g[i] = i, fs[i] = gs[i] = 1, s[i].emplace_back(-1, 0); for (int i = 1; i <= m; ++i) { char op[2]; int x, y; scanf( %s , op); if (op[0] == U ) x = read(), y = read(), merge(f, fs, ft, x, y, i); else if (op[0] == M ) x = read(), y = read(), merge(g, gs, gt, x, y, i); else if (op[0] == A ) x = read(), x = find(f, x), s[x].emplace_back(i, s[x].back().second + fs[x]); else if (op[0] == Z ) x = read(), x = find(g, x), cls[x] = i; else { int x = read(), y, t = cls[x]; for (y = x; g[y] != y; y = g[y]) if (cls[g[y]] > gt[y]) t = max(t, cls[g[y]]); long long ans = ask(s[x], t); for (y = x; f[y] != y; y = f[y]) ans += ask(s[f[y]], max(t, ft[y])); printf( %lld n , ans); } } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) #pragma comment(linker, /STACK:20000007 ) #pragma GCC optimize( unroll-loops ) const int N = (int)1e6 + 100; const int maxn = (int)1e3 + 100; const int base = (int)1e9; const int mod = (int)1e9 + 7; const int inf = INT_MAX; const long long ll_inf = LLONG_MAX; const long double pi = acos((long double)-1.0); const long double eps = 1e-8; void yes() { exit(!(printf( YES n ))); } void no() { exit(!(printf( NO n ))); } void solve() { string s; cin >> s; int n = s.size(); if (n < 4) no(); set<char> S; vector<int> Cnt(26); for (char c : s) Cnt[c - a ]++, S.insert(c); int L = S.size(); if (L > 4) no(); if (3 <= L && L <= 4) yes(); if (L == 1) no(); if (L == 2) { if (!any_of(Cnt.begin(), Cnt.end(), [&](int Count) -> bool { return Count >= 2; })) no(); vector<int> others; for (int i = 0; i < 26; ++i) if (Cnt[i] >= 2) others.push_back(i); if (others.size() >= 2) yes(); else no(); } no(); } int main() { int T = 1; for (; T; --T) solve(); return 0; } |
#include <bits/stdc++.h> const int N = 200005; int n, m, b[N]; char a[N], A[N]; int main() { scanf( %d%d%s , &n, &m, a); memset(b, 0x3f, sizeof(b)); for (int i = 0; i < n; i++) { int l = (i - 1 + n) % n, r = (i + 1) % n; if (a[i] == a[r]) { for (int j = l, k = 1; a[j] != a[(j + 1) % n] && a[j] != a[(j - 1 + n) % n]; j = (j - 1 + n) % n, k++) { if (k < b[j]) { b[j] = k; if (k <= m) A[j] = a[i]; } } for (int j = (r + 1) % n, k = 1; a[j] != a[(j - 1 + n) % n] && a[j] != a[(j + 1) % n]; j = (j + 1) % n, k++) { if (k < b[j]) { b[j] = k; if (k <= m) A[j] = a[i]; } } } } for (int i = 0; i < n; i++) { if (b[i] <= m) printf( %c , A[i]); else if (a[i] == a[(i + 1) % n] || a[i] == a[(i - 1 + n) % n]) { printf( %c , a[i]); } else { if (m & 1) printf( %c , BW [a[i] == B ]); else printf( %c , a[i]); } } } |
#include <bits/stdc++.h> using namespace std; const int NMAX = 300000; const double eps = 1e-6; double sy, a, b; int n, q; double L[NMAX], R[NMAX]; double sum[NMAX]; int dcmp(double x, double y) { if (fabs(x - y) < eps) return 0; if (x > y) return 1; return -1; } int bin_search(double x) { int l = 1, r = n, ret = 0; while (l <= r) { int mid = (l + r) / 2; if (dcmp(x, R[mid]) >= 0) { ret = mid; l = mid + 1; } else r = mid - 1; } return ret; } int main() { scanf( %lf%lf%lf , &sy, &a, &b); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lf%lf , &L[i], &R[i]); sum[i] = sum[i - 1] + R[i] - L[i]; } scanf( %d , &q); while (q--) { double x0, y0, x1, x2; scanf( %lf%lf , &x0, &y0); if (dcmp(x0, a) == 0) x1 = a; else { double k = (y0 - sy) / (x0 - a); x1 = a - sy / k; } if (dcmp(x0, b) == 0) x2 = b; else { double k = (y0 - sy) / (x0 - b); x2 = b - sy / k; } int r1 = bin_search(x1); int r2 = bin_search(x2); double ans = (sum[r2] - sum[r1]); if (r1 + 1 <= n && dcmp(L[r1 + 1], x1) < 0) ans -= x1 - L[r1 + 1]; if (r2 + 1 <= n && dcmp(L[r2 + 1], x2) < 0) ans += x2 - L[r2 + 1]; printf( %.15lf n , (b - a) * ans / (x2 - x1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, neg, zero; cin >> x; int arr[x]; for (int i = 0; i < x; i++) cin >> arr[i]; sort(arr, arr + x); if (arr[x - 1] <= 0) { cout << 1 << << arr[0] << endl; cout << 2 << << arr[1] << << arr[2] << endl; for (int i = 3; i < x; i++) { if (i == 3) cout << x - i << << arr[3]; else cout << << arr[i]; } } else { for (int i = 0; i < x; i++) { if (arr[i] < 0) neg = i; else if (arr[i] == 0) zero = i; } cout << 1 << arr[0] << endl; cout << x - zero - 1 << ; for (int i = zero + 1; i < x; i++) cout << arr[i] << ; cout << endl; cout << zero; for (int i = 1; i <= zero; i++) cout << << arr[i]; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; std::vector<int> Edge[510]; std::vector<int> Current[510]; int Right[510]; int Left[510]; int Vis[510]; int N, M; bool dfs(int idx) { if (Vis[idx]) return false; Vis[idx] = 1; for (int i = 0; i < Current[idx].size(); i++) { int v = Current[idx][i]; if (Left[v] == -1 || dfs(Left[v])) { Left[v] = idx; Right[idx] = v; return true; } } return false; } int bpm() { int Ans = 0; memset(Left, -1, sizeof(Left)); memset(Right, -1, sizeof(Right)); for (int i = 0; i < N; i++) { memset(Vis, false, sizeof(Vis)); Ans += dfs(i); } return Ans; } int main() { cin >> N >> M; int u, v; for (int i = 0; i < M; i++) { cin >> u >> v; u -= 1, v -= 1; Edge[u].push_back(v); } int Ans = 1e9; for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) Current[j].clear(); int cnt = 0, other = 0; for (int j = 0; j < N; j++) { for (int k = 0; k < Edge[j].size(); k++) { if (j == i || Edge[j][k] == i) { cnt += 1; continue; } other += 1; Current[j].push_back(Edge[j][k]); } } int max_match = bpm(); Ans = min(Ans, 2 * N - 1 + other - cnt - 2 * max_match + N - 1); } cout << Ans << endl; return 0; } |
#include <bits/stdc++.h> const int INFI = (1 << 29); const long long INFL = (1LL << 62); using namespace std; void solve() { long long a, n, m; cin >> a >> n >> m; bitset<2010> rain; vector<long long> v(m + 1); vector<pair<long long, long long> > umb(a + 1, {INFL, 0}); for (long long i = 0; i < n; i++) { long long l, r; cin >> l >> r; for (long long j = l; j <= r - 1; j++) rain[j] = 1; } for (long long i = 1; i <= m; i++) { long long l, r; cin >> l >> r; v[i] = r; umb[l] = min(umb[l], {r, i}); } vector<vector<long long> > dp(a + 1, vector<long long>(m + 1, INFL)); dp[0][0] = 0; for (long long i = 0; i < a; i++) { for (long long j = 0; j <= m; j++) { if (dp[i][j] == INFL) continue; if (umb[i].first != INFL) dp[i + 1][umb[i].second] = min(dp[i + 1][umb[i].second], dp[i][j] + umb[i].first); if (j) dp[i + 1][j] = min(dp[i + 1][j], dp[i][j] + v[j]); if (!rain[i]) dp[i + 1][0] = min(dp[i + 1][0], dp[i][j]); } } long long r = *min_element(dp[a].begin(), dp[a].end()); if (r == INFL) r = -1; cout << r << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if (k >= (n - 1) * n / 2) { cout << no solution n ; } else { for (int i = 1; i <= n; i++) { cout << 0 << << i << n ; } } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, I, IB, IBUFDISABLE, INTERMDISABLE);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
input I;
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
localparam MODULE_NAME = "IBUFDS_DIFF_OUT_INTERMDISABLE";
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
wire out_val;
wire out_b_val;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
end
always @(I or IB or DQS_BIAS_BINARY) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
default : begin
assign out_val = 1'b0;
assign out_b_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? out_val : 1'bx;
assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? out_b_val : 1'bx;
end
"FALSE" : begin
assign O = o_out;
assign OB = ~o_out;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_qpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 8
) (
input sys_clk,
/* Read port 1 */
input [depth-1:0] a1,
output [width-1:0] d1,
/* Read port 2 */
input [depth-1:0] a2,
output [width-1:0] d2,
/* Read port 3 */
input [depth-1:0] a3,
output [width-1:0] d3,
/* Read port 4 */
input [depth-1:0] a4,
output [width-1:0] d4,
/* Write port - we=1 disables read ports 1 and 3 */
input we,
input [depth-1:0] aw,
input [width-1:0] dw
);
tmu2_dpram_sw #(
.depth(depth),
.width(width)
) ram1 (
.sys_clk(sys_clk),
.a(we ? aw : a1),
.we(we),
.di(dw),
.do(d1),
.a2(a2),
.do2(d2)
);
tmu2_dpram_sw #(
.depth(depth),
.width(width)
) ram2 (
.sys_clk(sys_clk),
.a(we ? aw : a3),
.we(we),
.di(dw),
.do(d3),
.a2(a4),
.do2(d4)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; long long MOD = 1000000007; struct mi { long long v; explicit operator long long() const { return v; } mi() { v = 0; } mi(long long _v) { v = (-MOD < _v && _v < MOD) ? _v : _v % MOD; if (v < 0) v += MOD; } friend bool operator==(const mi &a, const mi &b) { return a.v == b.v; } friend bool operator!=(const mi &a, const mi &b) { return !(a == b); } friend bool operator<(const mi &a, const mi &b) { return a.v < b.v; } mi &operator+=(const mi &m) { if ((v += m.v) >= MOD) v -= MOD; return *this; } mi &operator-=(const mi &m) { if ((v -= m.v) < 0) v += MOD; return *this; } mi &operator*=(const mi &m) { v = v * m.v % MOD; return *this; } mi &operator/=(const mi &m) { return (*this) *= inv(m); } friend mi pow(mi a, long long p) { mi ans = 1; assert(p >= 0); for (; p; p /= 2, a *= a) if (p & 1) ans *= a; return ans; } friend mi inv(const mi &a) { assert(a.v != 0); return pow(a, MOD - 2); } mi operator-() const { return mi(-v); } mi &operator++() { return *this += 1; } mi &operator--() { return *this -= 1; } mi operator++(int) { mi temp; temp.v = v++; return temp; } mi operator--(int) { mi temp; temp.v = v--; return temp; } friend mi operator+(mi a, const mi &b) { return a += b; } friend mi operator-(mi a, const mi &b) { return a -= b; } friend mi operator*(mi a, const mi &b) { return a *= b; } friend mi operator/(mi a, const mi &b) { return a /= b; } friend ostream &operator<<(ostream &os, const mi &m) { os << m.v; return os; } friend istream &operator>>(istream &is, mi &m) { long long x; is >> x; m.v = x; return is; } }; void solve() { long long n; cin >> n; long long m; cin >> m; MOD = m; vector<mi> dp(n + 1, 0); vector<mi> suffix(n + 2, 0); dp[n] = 1; suffix[n] = 1; mi sum = 0; for (long long i = (n)-1; i >= 1; i--) { sum = sum + dp[i + 1]; dp[i] = sum; for (long long j = 2; j < (n + 1); j++) { if (i * j > n) break; else { mi sf = suffix[i * j] - suffix[min(i * j + j, n + 1)]; dp[i] = dp[i] + sf; } } suffix[i] = suffix[i + 1] + dp[i]; } cout << dp[1] << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); solve(); } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datrom.v when simulating
// the core, upd77c25_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1536),
.C_READ_DEPTH_B(1536),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1536),
.C_WRITE_DEPTH_B(1536),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_MS__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; template <class T> int getbit(int i, T X) { return (X & (1 << (i - 1))); } template <class T> T onbit(int i, T X) { return (X | (1 << (i - 1))); } template <class T> T offbit(int i, T X) { return (X | (1 << (i - 1)) - (1 << (i - 1))); } template <class T> T sqr(T x) { return (x * x); } template <class T> T cube(T x) { return (x * x * x); } template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } int csx[4] = {0, 0, -1, 1}; int csy[4] = {-1, 1, 0, 0}; const int MOD = 1000000007; const int infi = 1e9; const int maxn = 300; const int maxv = 800; struct Dinic { int n, s, t, E, adj[maxv + 5], next[maxv + 5], last[maxn + 5], run[maxv + 5], level[maxv + 5], que[maxv + 5], pre[maxv + 5]; long long flow[maxv + 5], cap[maxv + 5]; void init(int _n, int _s, int _t) { n = _n; s = _s; t = _t; E = 0; for (typeof(n) i = 0; i <= n; i++) last[i] = -1; } void add(int u, int v, long long c1, long long c2) { adj[E] = v; flow[E] = 0; cap[E] = c1; pre[E] = u; next[E] = last[u]; last[u] = E++; adj[E] = u; flow[E] = 0; cap[E] = c2; pre[E] = v; next[E] = last[v]; last[v] = E++; } bool bfs() { for (typeof(n) i = 0; i <= n; i++) level[i] = -1; level[s] = 0; int qsize = 0; que[qsize++] = s; for (typeof(qsize) i = 0; i < qsize; i++) { for (int u = que[i], e = last[u]; e != -1; e = next[e]) { int v = adj[e]; if (flow[e] < cap[e] && level[v] == -1) { level[v] = level[u] + 1; que[qsize++] = v; } } } return level[t] != -1; } long long dfs(int u, long long bot) { if (u == t) return bot; for (int &e = run[u]; e != -1; e = next[e]) { int v = adj[e]; long long delta = 0; if (level[v] == level[u] + 1 && flow[e] < cap[e] && (delta = dfs(v, min(bot, cap[e] - flow[e] * 1ll))) > 0) { flow[e] += delta; flow[e ^ 1] -= delta; return delta; } } return 0; } long long maxFlow() { long long total = 0; while (bfs()) { for (typeof(n) i = 0; i <= n; i++) run[i] = last[i]; for (int delta = dfs(s, infi); delta > 0; delta = dfs(s, infi)) total += delta; } return total; } }; int n, m, a[maxn + 5]; pair<int, long long> P[maxn + 5]; map<int, int> M[maxn + 5]; set<int> prime; Dinic dinic; void enter() { scanf( %d %d , &n, &m); for (typeof(n) i = 1; i <= n; i++) scanf( %d , &a[i]); for (typeof(m) i = 1; i <= m; i++) scanf( %d %d , &P[i].first, &P[i].second); } void Phantich(int id, int n) { for (int i = 2; i * i <= n; i++) if (n % i == 0) { int cnt = 0; while (n % i == 0) { cnt++; n /= i; } M[id][i] = cnt; prime.insert(i); } if (n > 1) { M[id][n] = 1; prime.insert(n); } } void solve() { for (typeof(n) i = 1; i <= n; i++) { Phantich(i, a[i]); } long long res = 0; for (typeof(prime.begin()) it = prime.begin(); it != prime.end(); it++) { dinic.init(n + 2, 0, n + 1); for (typeof(m) i = 1; i <= m; i++) { int u = P[i].first; int v = P[i].second; if (u % 2) swap(u, v); if ((M[u].find(*it) == M[u].end()) || (M[v].find(*it) == M[v].end())) continue; int c = min(M[u][*it], M[v][*it]); dinic.add(u, v, c, 0); } for (typeof(n) i = 1; i <= n; i++) if (i % 2 == 0) { if (M[i].find(*it) == M[i].end()) continue; dinic.add(0, i, M[i][*it], 0); } else { if (M[i].find(*it) == M[i].end()) continue; dinic.add(i, n + 1, M[i][*it], 0); } res += dinic.maxFlow(); } cout << res << endl; } int main() { enter(); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Author(s): ////
//// - Michael Unneback, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram
(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, ce, we, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input ce; // Chip enable input
input we; // Write enable input
//input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
`ifdef OR1200_GENERIC
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
reg [dw-1:0] mem [(1<<aw)-1:0];
`endif
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
//assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
assign doq = mem[addr_reg];
// synthesis translate_off
integer k;
initial begin
for(k = 0; k < (1 << aw); k = k + 1) begin
mem[k] = 0;
end
end
// synthesis translate_on
//
// RAM read address register
//
always @(posedge clk)
if (ce)
addr_reg <= addr;
//
// RAM write
//
always @(posedge clk)
if (we && ce)
mem[addr] <= di;
endmodule // or1200_spram
|
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) struct E { int to; vector<long long> w; }; const long long INF = 1e18; const int N = 3e5 + 5, L = 20; vector<E> g[N]; long long t[N], d[2][2][N][L]; int anc[N][L], tin[N], tout[N]; int timer = 0, n; void deep(int node) { for (E e : g[node]) { if (e.to != anc[node][0]) { anc[e.to][0] = node; deep(e.to); t[node] = min(t[node], t[e.to] + e.w[0] + e.w[1]); } } } void walk(int node, long long u) { u = min(u, t[node]); t[node] = u; for (E e : g[node]) { if (e.to != anc[node][0]) walk(e.to, u + e.w[0] + e.w[1]); } } void dfs(int node) { tin[node] = timer++; for (int i = 1; i < L; i++) { anc[node][i] = anc[anc[node][i - 1]][i - 1]; for (int x = 0; x < 2; x++) { for (int y = 0; y < 2; y++) { for (int z = 0; z < 2; z++) { d[x][z][node][i] = min(d[x][z][node][i], d[x][y][node][i - 1] + d[y][z][anc[node][i - 1]][i - 1]); } } } } for (E e : g[node]) { if (e.to != anc[node][0]) { anc[e.to][0] = node; for (int i = 0; i < 2; i++) { d[i][i][e.to][0] = min(e.w[i], e.w[1 - i] + t[node] + t[e.to]); d[i][1 - i][e.to][0] = min(e.w[1 - i] + t[e.to], t[node] + e.w[i]); } dfs(e.to); } } tout[node] = timer; } bool upper(int a, int b) { return tin[a] <= tin[b] && tout[a] >= tout[b]; } long long calc(int x, int a, int y, int b) { long long dp[2]; dp[x] = 0; dp[1 - x] = t[a]; if (a == b) return dp[y]; for (int i = L - 1; i >= 0; i--) { if (!upper(anc[a][i], b)) { long long ndp[2] = {INF, INF}; for (int j = 0; j < 2; j++) { for (int k = 0; k < 2; k++) { ndp[k] = min(ndp[k], dp[j] + d[j][k][a][i]); } } for (int j = 0; j < 2; j++) dp[j] = ndp[j]; a = anc[a][i]; } } return min(dp[0] + d[0][y][a][0], dp[1] + d[1][y][a][0]); } int getLca(int a, int b) { if (upper(a, b)) return a; for (int i = L - 1; i >= 0; i--) { if (!upper(anc[a][i], b)) a = anc[a][i]; } return anc[a][0]; } long long getAns(int a, int b) { int x = a % 2, y = b % 2; a /= 2; b /= 2; int l = getLca(a, b); long long ans = min(calc(x, a, 0, l) + calc(y, b, 0, l), calc(x, a, 1, l) + calc(y, b, 1, l)); return ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> t[i]; } for (int i = 0; i < n - 1; i++) { int x, y; long long w1, w2; cin >> x >> y >> w1 >> w2; x--, y--; g[x].push_back({y, {w1, w2}}); g[y].push_back({x, {w1, w2}}); } for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { for (int k = 0; k < n; k++) { for (int h = 0; h < L; h++) { d[i][j][k][h] = INF; } } } } deep(0); walk(0, INF); dfs(0); int q; cin >> q; while (q--) { int a, b; cin >> a >> b; a--, b--; cout << getAns(a, b) << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_XRES4V2_SYMBOL_V
`define SKY130_FD_IO__TOP_XRES4V2_SYMBOL_V
/**
* top_xres4v2: XRES (Input buffer with Glitch filter).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_xres4v2 (
//# {{data|Data Signals}}
input FILT_IN_H ,
input INP_SEL_H ,
inout PAD ,
inout PAD_A_ESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input DISABLE_PULLUP_H,
input ENABLE_H ,
input ENABLE_VDDIO ,
input EN_VDDIO_SIG_H ,
output XRES_H_N ,
//# {{power|Power}}
inout PULLUP_H ,
output TIE_HI_ESD ,
inout TIE_WEAK_HI_H ,
output TIE_LO_ESD
);
// Voltage supply signals
supply1 VCCD ;
supply1 VCCHIB ;
supply1 VDDA ;
supply1 VDDIO ;
supply1 VDDIO_Q;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO ;
supply0 VSSIO_Q;
supply1 VSWITCH;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_XRES4V2_SYMBOL_V
|
#include <iostream> #include <algorithm> #define int long long using namespace std; void solve () { int a, b, c, d; cin >> a >> b >> c >> d; int arr[4] = {a,b,c,d}; sort (arr, arr+4); int max1 = arr[4-1]; int max2 = arr[4-2]; int win1 = max (a, b); int win2 = max (c, d); if (win1 == max1 && win2 == max2){ cout << YES << n ; return; } if (win1 == max2 && win2 == max1){ cout << YES << n ; return; } cout << NO << n ; } signed main () { ios_base::sync_with_stdio (0);cin.tie (0); int t; cin >> t; while (t--) { solve (); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_LP_V
`define SKY130_FD_SC_LP__A31OI_LP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_lp (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_LP_V
|
module GS_3032(
config_n, // ACEX1K config pins
status_n, //
conf_done, //
cs, //
init_done, //
clk24in, // 24mhz in
clk20in, // 20mhz in
clkout, // clock out
clksel0, // clock select 0 (1=divide by 2, 0=no divide)
clksel1, // clock select 1 (1=clk20in, 0=clk24in)
a6,a7,a14,a15, // z80 signals
iorq_n,mreq_n, //
rd_n,wr_n, //
d7,d0, //
mema14,mema15, // signals to memories
romcs_n,ramcs0_n,
memoe_n,memwe_n,
coldres_n, // cold reset input
warmres_n, // warm reset output
clkin // input of clkout signal
);
output config_n; reg config_n;
input status_n;
input conf_done;
output cs; reg cs;
input init_done;
input clk24in;
input clk20in;
output clkout; reg clkout;
input clksel0,clksel1;
input a6,a7,a14,a15;
input iorq_n,mreq_n,rd_n,wr_n;
inout d7,d0; reg d7,d0;
output mema14,mema15; reg mema14,mema15;
output romcs_n,ramcs0_n; reg romcs_n,ramcs0_n;
output memoe_n,memwe_n; reg memoe_n,memwe_n;
input coldres_n;
input warmres_n;
input clkin;
reg int_mema14,int_mema15;
reg int_romcs_n,int_ramcs0_n;
reg int_memoe_n,int_memwe_n;
reg int_cs;
reg [1:0] memcfg; // memcfg[1]: 1 ram, 0 roms
// memcfg[0]: 0 page0, 1 page1 -> in 8000-ffff region
reg diver [0:10];
reg disbl; // =1 - 3032 disabled, =0 - enabled
reg was_cold_reset_n; // 1 - no cold reset, 0 - was cold reset
reg [1:0] dbout;
wire [1:0] dbin;
assign dbin[1] = d7;
assign dbin[0] = d0;
wire memcfg_write;
wire rescfg_write;
wire coldrstf_read;
wire fpgastat_read;
reg [3:0] rstcount; // counter for warm reset period
reg [2:0] disbl_sync;
clocker myclk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout) );
always @*
begin
cs <= 1'b0;
d0 <= 1'bZ;
d7 <= 1'bZ;
mema14 <= 1'bZ;
mema15 <= 1'bZ;
romcs_n <= 1'bZ;
ramcs0_n <= 1'bZ;
memoe_n <= 1'bZ;
memwe_n <= 1'bZ;
end
always @(coldres_n, warmres_n)
begin
if( coldres_n==1'b0)
config_n <= 1'b0;
else if( warmres_n==1'b0 )
config_n <= 1'b1;
end
endmodule
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
/**
Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx
*/
`timescale 1ps/1ps
`default_nettype none
module clock_divider_sim
#(
parameter DIVISOR = 2
)
(
input wire CLK,
output reg CLOCK
);
integer cnt;
initial cnt = 0;
always@(posedge CLK)
if(cnt == DIVISOR -1)
cnt <= 0;
else
cnt <= cnt + 1;
initial begin
CLOCK = 0;
forever begin
@(posedge CLK);
if(cnt == DIVISOR-1)
CLOCK = 1;
if(cnt == DIVISOR/2-1) begin
if(DIVISOR % 2 == 1) @(negedge CLK);
CLOCK = 0;
end
end
end
endmodule
module DCM
#( parameter CLKFX_MULTIPLY = 4,
parameter CLKFX_DIVIDE = 1,
parameter CLKDV_DIVIDE = 2,
parameter CLKIN_PERIOD = 10,
parameter CLK_FEEDBACK = 0,
parameter CLKOUT_PHASE_SHIFT = 0,
parameter CLKIN_DIVIDE_BY_2 = "FALSE",
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS",
parameter DFS_FREQUENCY_MODE = "LOW",
parameter DLL_FREQUENCY_MODE = "LOW",
parameter DUTY_CYCLE_CORRECTION = "TRUE",
parameter FACTORY_JF = 16'hC080,
parameter PHASE_SHIFT = 0,
parameter STARTUP_WAIT = "TRUE"
)
(
CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS,
CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
input wire CLKFB, CLKIN, DSSEN;
input wire PSCLK, PSEN, PSINCDEC, RST;
output wire CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
output wire CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
output wire [7:0] STATUS;
assign STATUS = 0;
assign CLK0 = CLKIN;
assign CLK180 = ~CLKIN;
assign CLK270 = ~CLK90;
assign CLK2X180 = ~CLK2X;
assign CLKFX180 = ~CLKFX;
wire resetb = ~RST;
wire clk2x;
clock_multiplier #( .MULTIPLIER(2) ) i_clock_multiplier_two(.CLK(CLKIN),.CLOCK(clk2x));
reg clk90;
reg [1:0] cnt;
always @(posedge clk2x or negedge clk2x or negedge resetb) begin
if (!resetb) begin
clk90 <= 0;
cnt <= 0;
end else begin
cnt <= cnt + 1;
if (!cnt[0]) clk90 <= ~clk90;
end
end
assign CLK2X = clk2x;
assign CLK90 = clk90;
generate
if (CLKFX_MULTIPLY==2 && CLKFX_DIVIDE==1) begin
assign CLKFX = clk2x;
end else begin
wire CLKINM;
clock_multiplier #( .MULTIPLIER(CLKFX_MULTIPLY) ) i_clock_multiplier(.CLK(CLKIN),.CLOCK(CLKINM));
clock_divider_sim #(.DIVISOR(CLKFX_DIVIDE)) i_clock_divisor_rx (.CLK(CLKINM), .CLOCK(CLKFX));
end
endgenerate
clock_divider_sim #(.DIVISOR(CLKDV_DIVIDE)) i_clock_divisor_dv (.CLK(CLKIN), .CLOCK(CLKDV));
assign LOCKED = 1'b1;
endmodule
|
#include <bits/stdc++.h> int n, m, x, tab[11][1001][1001], mx[11][1001][1001], i = 1, j = 1, ij = 1; char a[1001], b[1001], q; inline int max(int a, int b) { if (a >= b) return a; return b; } int main() { scanf( %d %d %d , &n, &m, &x); q = getchar(); while (i <= n) { a[i] = getchar(); i++; } q = getchar(); i = 1; while (i <= m) { b[i] = getchar(); i++; } i = 1; while (ij <= x) { while (i <= n) { while (j <= m) { if (a[i] == b[j]) tab[ij][i][j] = max(tab[ij][i - 1][j - 1] + 1, mx[ij - 1][i - 1][j - 1] + 1); else tab[ij][i][j] = 0; mx[ij][i][j] = max(mx[ij][i - 1][j], mx[ij][i][j - 1]); mx[ij][i][j] = max(mx[ij][i][j], tab[ij][i][j]); j++; } i++, j = 1; } i = 1, j = 1, ij++; } printf( %d , mx[x][n][m]); return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> stations[200001]; int nxt[200001]; int main() { int d, n, m; scanf( %d%d%d , &d, &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &stations[i].first, &stations[i].second); } sort(stations, stations + m); stack<int> s; for (int i = m - 1; i > -1; i--) { nxt[i] = -1; while (!s.empty()) { if (stations[s.top()].second > stations[i].second) { s.pop(); } else { nxt[i] = s.top(); break; } } s.push(i); } long long cost = 0; int gas = n; for (int i = 0; i < m; i++) { gas -= stations[i].first - (i == 0 ? 0 : stations[i - 1].first); if (gas < 0) { cout << -1 << endl; return 0; } int needed; if (nxt[i] == -1 || stations[nxt[i]].first - stations[i].first > n) { needed = min(n, d - stations[i].first); } else { needed = stations[nxt[i]].first - stations[i].first; } if (gas < needed) { cost += (long long)stations[i].second * (needed - gas); gas = needed; } } gas -= d - stations[m - 1].first; if (gas < 0) { cout << -1 << endl; } else { cout << cost << endl; } } |
`begin_keywords "1364-2005"
/*
* Copyright (c) 2005 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* tern7.v
* This tests types.
*/
module main;
reg b, c, d, e;
wire a = b ? c : (d&e);
reg [4:0] tmp;
reg ref;
initial begin
// Do an exaustive scan of the possible values.
for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1) begin
b <= tmp[0];
c <= tmp[1];
d <= tmp[2];
e <= tmp[3];
ref = tmp[0] ? tmp[1] : (tmp[2]&tmp[3]);
#1 if (ref !== a) begin
$display("FAILED -- a=%b, b=%b, c=%b, d=%b, e=%b",
a, b, c, d, e);
$finish;
end
end // for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1)
b <= 0;
c <= 1;
d <= 1;
e <= 0;
#1 if (a !== 1'b0) begin
$display("FAILED (1)");
$finish;
end
e <= 1;
#1 if (a !== 1'b1) begin
$display("FAILED (2)");
$finish;
end
$display("PASSED");
end
endmodule // main
`end_keywords
|
module main;
reg [2:0] ADDR;
wire [1:0] data0 = 0, data1 = 1, data2 = 2, data3 = 3;
reg [1:0] data;
always @*
case (ADDR[2:0])
3'b000: data = data0;
3'b001: data = data1;
3'b010: data = data2;
3'b011: data = data3;
default: data = 0;
endcase // case(ADDR[2:0])
initial begin
ADDR = 0;
#1 $display("data=%b", data);
if (data !== ADDR) begin
$display("FAILED");
$finish;
end
ADDR = 1;
#1 $display("data=%b", data);
if (data !== ADDR) begin
$display("FAILED");
$finish;
end
ADDR = 2;
#1 $display("data=%b", data);
if (data !== ADDR) begin
$display("FAILED");
$finish;
end
ADDR = 3;
#1 $display("data=%b", data);
if (data !== ADDR) begin
$display("FAILED");
$finish;
end
ADDR = 4;
#1 $display("data=%b", data);
if (data !== 0)begin
$display("FAILED");
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2012, Jahanzeb Ahmad
/// All rights reserved.
///
/// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
/*!
ROM for EDID DVI structure only, not for HDMI.
*/
module edidrom (clk,adr,data);
input clk;
input [7:0] adr;
output [7:0] data;
reg [7:0] data ;
reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;
initial $readmemh("..//hdl//edid//edidrom.hex", mem);
always @ (posedge clk)
begin
data <= mem[adr];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { long long r; while (b != 0) { r = a % b; a = b; b = r; } return a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long fpow(long long n, long long k, int p = (int)1e9 + 7) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } const int MOD = (int)1e9 + 7; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = 2 * acos((long double)0); const int maxn = 500010; int n, w, h; char s[maxn]; int xmin[maxn]; int xmax[maxn]; int ymin[maxn]; int ymax[maxn]; long long alox[maxn]; long long aloy[maxn]; long long tot[maxn]; void solve() { scanf( %d%d%d%s , &n, &h, &w, s); int dx = 0, dy = 0; for (int i = (0); i < (n); i++) { if (s[i] == L ) dx--; else if (s[i] == R ) dx++; else if (s[i] == U ) dy--; else dy++; if (!i) { xmin[i] = xmax[i] = dx; ymin[i] = ymax[i] = dy; } else { xmin[i] = min(xmin[i - 1], dx); xmax[i] = max(xmax[i - 1], dx); ymin[i] = min(ymin[i - 1], dy); ymax[i] = max(ymax[i - 1], dy); } } for (int i = (0); i < (w); i++) { int c = 0; if (i + xmin[n - 1] >= 0 && i + xmax[n - 1] < w) { int l = 0, r = INF; while (l < r) { int m = (l + r) >> 1; if (dx >= 0) { if (i + xmax[n - 1] + 1LL * m * dx < w) l = m + 1; else r = m; } else { if (i + xmin[n - 1] + 1LL * m * dx >= 0) l = m + 1; else r = m; } } c = l; } if (c == INF) { alox[i] = -1; continue; } int l = 0, r = n - 1; while (l < r) { int m = (l + r) >> 1; if (i + xmin[m] + 1LL * c * dx >= 0 && i + xmax[m] + 1LL * c * dx < w) l = m + 1; else r = m; } alox[i] = 1LL * c * n + l + 1; } for (int i = (0); i < (h); i++) { int c = 0; if (i + ymin[n - 1] >= 0 && i + ymax[n - 1] < h) { int l = 0, r = INF; while (l < r) { int m = (l + r) >> 1; if (dy >= 0) { if (i + ymax[n - 1] + 1LL * m * dy < h) l = m + 1; else r = m; } else { if (i + ymin[n - 1] + 1LL * m * dy >= 0) l = m + 1; else r = m; } } c = l; } if (c == INF) { aloy[i] = -1; continue; } int l = 0, r = n - 1; while (l < r) { int m = (l + r) >> 1; if (i + ymin[m] + 1LL * c * dy >= 0 && i + ymax[m] + 1LL * c * dy < h) l = m + 1; else r = m; } aloy[i] = 1LL * c * n + l + 1; } int flagx = 0, flagy = 0; for (int i = (0); i < (w); i++) { if (!~alox[i]) { flagx = 1; alox[i] = LINF; } } for (int i = (0); i < (h); i++) { if (!~aloy[i]) { flagy = 1; aloy[i] = LINF; } } if (flagx && flagy) { printf( -1 ); return; } int ans = 0; sort(aloy, aloy + h); for (int i = (0); i < (h); i++) { if (!i) tot[i] = aloy[i] % MOD; else tot[i] = (tot[i - 1] + aloy[i]) % MOD; } for (int i = (0); i < (w); i++) { int k = upper_bound(aloy, aloy + h, alox[i]) - aloy - 1; if (~k) ans = (ans + tot[k]) % MOD; ans = (ans + 1LL * (h - k - 1) * alox[i]) % MOD; } printf( %d , ans); } int main() { solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_SYMBOL_V
`define SKY130_FD_SC_HS__DLXBN_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void solve() { int m, k; scanf( %d %d , &m, &k); vector<int> a(k, 0); vector<int> t(m - 1), r(m - 1, 0); vector<int> last(k, 0); for (int i = 0; i < k; ++i) { scanf( %d , &a[i]); } int free_num = 0; for (int i = 0; i + 1 < m; ++i) { scanf( %d %d , &t[i], &r[i]); if (t[i] > 0) { last[t[i] - 1] = i; } } int first_upset_id = -1; int before_upset_num = 0; for (int i = 0; i + 1 < m; ++i) { if (r[i] == 1) { first_upset_id = i; break; } else if (t[i] == 0) { ++before_upset_num; } } for (int i = 0; i + 1 < m; ++i) { if (t[i] == 0) { ++free_num; } else { --a[t[i] - 1]; } } if (first_upset_id >= 0) { int min_id = -1; for (int i = 0; i < k; ++i) { if ((last[i] < first_upset_id) && ((min_id == -1) || (a[min_id] > a[i]))) { min_id = i; } } free_num -= a[min_id]; } for (int i = 0; i < k; ++i) { if ((a[i] <= free_num) || ((last[i] < first_upset_id) && (a[i] <= before_upset_num))) { printf( Y ); } else { printf( N ); } } printf( n ); } int main() { int t; scanf( %d , &t); while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; bool Check(long long A, long long B, long long T1, long long T2) { if (!A && !B) return !T1 && !T2; return !((T1 * A + T2 * B) % (A * A + B * B)) && !((T2 * A - T1 * B) % (A * A + B * B)); } int main() { long long X0, Y0, X1, Y1, X2, Y2; cin >> X0 >> Y0 >> X1 >> Y1 >> X2 >> Y2; cout << ((Check(X2, Y2, X1 - X0, Y1 - Y0) || Check(X2, Y2, Y1 - X0, -X1 - Y0) || Check(X2, Y2, -X1 - X0, -Y1 - Y0) || Check(X2, Y2, -Y1 - X0, X1 - Y0)) ? YES : NO ) << endl; return 0; } |
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int,uart_cts_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 9600 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char c; int s = 0, k = 0, n = 0, x, f = 0; ; int main() { while (cin.get(c)) { if (c == n ) break; switch (s) { case 0: { if (c >= a && c <= z || c >= A && c <= Z || c == _ || c >= 0 && c <= 9 ) { s = 1; k++; } else { cout << NO ; return 0; } break; } case 1: { if ((c >= a && c <= z || c >= A && c <= Z || c == _ || c >= 0 && c <= 9 ) && k < 16) k++; else if (c == @ ) { s = 2; k = 0; f = 1; } else { cout << NO ; return 0; } break; } case 2: { if ((c >= a && c <= z || c >= A && c <= Z || c == _ || c >= 0 && c <= 9 ) && k < 16 && n < 32) { k++; n++; f = 0; } else if (c == . && f == 0) { k = 0; n++; f = 1; } else if (c == / && f == 0) { k = 0; f = 1; s = 3; } else { cout << NO ; return 0; } break; } case 3: { if (c >= a && c <= z || c >= A && c <= Z || c == _ || c >= 0 && c <= 9 ) { k++; f = 0; } else if (c == / && f == 0) { k = 0; f = 1; } else { cout << NO ; return 0; } break; } } } if (f == 1) cout << NO ; else cout << YES ; } |
#include <bits/stdc++.h> using namespace std; void solve(long long tc) { long long n, m, k; cin >> n >> m >> k; vector<long long> v(n); for (long long i = (0), ed = (n); i < (ed); ++i) { cin >> v[i]; } sort(v.begin(), v.end()); unsigned long long mx1 = v[n - 1], mx2 = v[n - 2]; if (0) cout << :>> << mx1 << : << mx1 << n , cout << :>> << mx2 << : << mx2 << n ; unsigned long long ans = mx2 * (m / (k + 1)); if (0) cout << :>> << ans << : << ans << n ; m = m - (m / (k + 1)); ans += mx1 * m; cout << ans << n ; } int32_t main() { solve(1); return 0; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// Input buffer map
module \$__inpad (input I, output O);
cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: SPI_MASTER
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_MASTER#
(
parameter integer m = 15 // Data packet size
)
(
input clk,
input wire RST,
output reg EN_TX=0,
input ce,
output wire LOAD,
input st,
output wire SCLK,
input MISO,
output wire MOSI,
input [m-1:0] TX_MD,
output reg [m-1:0] RX_SD=0,
input LEFT,
output wire CEfront,
input R,
output wire CEspad
);
reg [m-1:0] MQ=0 ; //Ðåãèñòð ñäâèãà âûõîäíûõ äàííûõ MASTER-à
reg [m-1:0] MRX=0 ; //Ðåãèñòð ñäâèãà âõîäíûõ äàííûõ MASTER-à
reg [3:0] cb_bit=0; //Ñ÷åò÷èê áèò
assign MOSI = LEFT? MQ[m-1] : MQ[0] ; // Âûõîäíûå äàííûå MASTER-à
assign LOAD = !EN_TX ; // Èíòåðâàë ïåðåäà÷è/ïðèåìà
assign SCLK = EN_TX & ce;
reg st_buf = 1'b0;
always @(posedge ce) begin
if (!EN_TX & st) begin
st_buf <= 1'b1;
end
else begin
st_buf <= 1'b0;
end
end
always @(negedge ce) begin
MQ <= st_buf? TX_MD : LEFT ? MQ<<1 : MQ>>1;
EN_TX <= (cb_bit == (m-1))? 0 : st_buf? 1'b1 : EN_TX;
cb_bit <= st_buf? 0 : cb_bit + 4'd1 ;
end
reg wready = 1'b0;
always @(posedge ce) begin
MRX <= (EN_TX == 1'b1) ? MRX<<1 | MISO : 0;
if (RST == 1'b1) begin
RX_SD <= 0;
wready <= 1'b0;
end
else if (EN_TX == 1'b0) begin
if (wready == 1'b0) begin
RX_SD <= MRX;
end
wready <= 1'b1;
end
else begin
wready <= 1'b0;
RX_SD <= RX_SD;
end
end
//always @(posedge LOAD) begin
//end
endmodule |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_fpext_32ns_64_1
#(parameter
ID = 6,
NUM_STAGE = 1,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
HLS_accel_ap_fpext_0_no_dsp_32 HLS_accel_ap_fpext_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int grid[201][201]{0}; int main() { string s; cin >> s; int x = 100; int y = 100; grid[x][y] = true; for (auto& it : s) { switch (it) { case L : x--; break; case R : x++; break; case U : y--; break; case D : y++; } if (grid[x][y] || (it != L && grid[x + 1][y]) || (it != R && grid[x - 1][y]) || (it != U && grid[x][y + 1]) || (it != D && grid[x][y - 1])) { cout << BUG << endl; return 0; } grid[x][y] = true; } cout << OK << endl; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_axi_trn_bridge.v
// Version : 1.11
//
// Description : AXI - TRN Bridge for Root Port Model.
// Root Port Usrapp's require TRN interface.
//-----------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_axi_trn_bridge # (
parameter C_DATA_WIDTH = 64,
parameter RBAR_WIDTH = 7,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
)
(
// Common
input user_clk,
input user_reset,
input user_lnk_up,
// AXI TX
//-----------
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
output s_axis_tx_tvalid, // TX data is valid
input s_axis_tx_tready, // TX ready for data
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
output s_axis_tx_tlast, // TX data is last
output [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
output m_axis_rx_tready, // RX ready for data
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Usrapp I/O //
//---------------------------------------------//
// TRN TX
//-----------
input [C_DATA_WIDTH-1:0] trn_td, // TX data from usrapp
input trn_tsof, // TX start of packet
input trn_teof, // TX end of packet
input trn_tsrc_rdy, // TX source ready
output trn_tdst_rdy, // TX destination ready
input trn_tsrc_dsc, // TX source discontinue
input [REM_WIDTH-1:0] trn_trem, // TX remainder
input trn_terrfwd, // TX error forward
input trn_tstr, // TX streaming enable
input trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
output [C_DATA_WIDTH-1:0] trn_rd, // RX data to usrapp
output trn_rsof, // RX start of packet
output trn_reof, // RX end of packet
output trn_rsrc_rdy, // RX source ready
input trn_rdst_rdy, // RX destination ready
output reg trn_rsrc_dsc, // RX source discontinue
output [REM_WIDTH-1:0] trn_rrem, // RX remainder
output wire trn_rerrfwd, // RX error forward
output [RBAR_WIDTH-1:0] trn_rbar_hit // RX BAR hit
);
//DWORD Reordering between AXI and TRN interface//
generate begin:gen_axis_txdata
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32]};
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32],trn_td[95:64],trn_td[127:96]};
end
end
endgenerate
//Coversion from trn_rem to s_axis_tkeep[7:0]//
generate begin: gen_axis_tx_tkeep
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tkeep = (trn_teof && ~trn_trem) ? 8'h0F : 8'hFF;
// always @*
// begin
// if (trn_teof && ~trn_trem) begin
// s_axis_tx_tkeep <= 8'h0F;
// end else begin
// s_axis_tx_tkeep <= 8'hFF;
// end
// end
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tkeep = (trn_teof) ? ((trn_trem == 2'b11) ? 16'hFFFF :
((trn_trem == 2'b10) ? 16'h0FFF :
((trn_trem == 2'b01) ? 16'h00FF : 16'h000F ))) :
16'hFFFF;
// always @*
// begin
// if (trn_teof)
// begin
// case (trn_trem)
// 2'b11: begin s_axis_tx_tkeep <= 16'hFFFF; end
// 2'b10: begin s_axis_tx_tkeep <= 16'h0FFF; end
// 2'b01: begin s_axis_tx_tkeep <= 16'h00FF; end
// 2'b00: begin s_axis_tx_tkeep <= 16'h000F; end
// endcase
// end
// else
// begin
// s_axis_tx_tkeep <= 16'hFFFF;
// end
// end
end
end
endgenerate
//Connection of s_axis_tx_tuser with trn_tsrc_dsc,trn_tstr,trn_terr_fwd and trn_terr_fwd
assign s_axis_tx_tuser [3] = trn_tsrc_dsc;
assign s_axis_tx_tuser [2] = trn_tstr;
assign s_axis_tx_tuser [1] = trn_terrfwd;
assign s_axis_tx_tuser [0] = trn_tecrc_gen;
//Constraint trn_tsrc_rdy. If constrained, testbench keep trn_tsrc_rdy constantly asserted. This makes axi bridge to generate trn_tsof immeditely after trn_teof of previous packet.//
reg trn_tsrc_rdy_derived = 1'b0;
always @*
begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof)
begin
trn_tsrc_rdy_derived <= 1'b1;
end
else if(trn_tsrc_rdy_derived && trn_teof && trn_tsrc_rdy && trn_tdst_rdy)
begin
trn_tsrc_rdy_derived <= 1'b0;
end
end
assign s_axis_tx_tvalid = trn_tsrc_rdy_derived || trn_tsof || trn_teof;
assign trn_tdst_rdy = s_axis_tx_tready;
assign s_axis_tx_tlast = trn_teof;
assign m_axis_rx_tready = trn_rdst_rdy;
generate begin:gen_trn_rd
if (C_DATA_WIDTH == 64) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata[63:32]};
end else if (C_DATA_WIDTH == 128) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata [63:32],m_axis_rx_tdata [95:64],m_axis_rx_tdata [127:96]};
end
end
endgenerate
//Regenerate trn_rsof
//Used clock. Latency may have been added
reg in_packet_reg;
generate begin:gen_trn_rsof
if (C_DATA_WIDTH == 64)
begin
always @(posedge user_clk)
begin
if (user_reset)
in_packet_reg <= 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready)
in_packet_reg <= ~m_axis_rx_tlast;
end
assign trn_rsof = m_axis_rx_tvalid & ~in_packet_reg;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rsof = m_axis_rx_tuser [14];
end
end
endgenerate
generate begin: gen_trn_reof
if (C_DATA_WIDTH == 64)
begin
assign trn_reof = m_axis_rx_tlast;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_reof = m_axis_rx_tuser[21]; //is_eof[4];
end
end
endgenerate
assign trn_rsrc_rdy = m_axis_rx_tvalid;
//Regenerate trn_rsrc_dsc
//Used clock. Latency may have been added
always @(posedge user_clk)
begin
if (user_reset)
trn_rsrc_dsc <= 1'b1;
else
trn_rsrc_dsc <= ~user_lnk_up;
end
wire [4:0] is_sof;
wire [4:0] is_eof;
assign is_sof = m_axis_rx_tuser[14:10];
assign is_eof = m_axis_rx_tuser[21:17];
generate begin:gen_trn_rrem
if (C_DATA_WIDTH == 64)
begin
assign trn_rrem = m_axis_rx_tlast ? (m_axis_rx_tkeep == 8'hFF) ? 1'b1 : 1'b0: 1'b1;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rrem[0] = is_eof[2];
assign trn_rrem[1] = (is_eof[4] || is_sof[4] ) ? ( (is_sof[4] && is_eof[4] && is_eof[3]) || (!is_sof[4] && is_eof[4] && is_eof[3]) || (is_sof[4] && !is_eof[4] && !is_sof[3]) ) : 1'b1;
end
end
endgenerate
assign trn_rerrfwd = m_axis_rx_tuser[1];
assign trn_rbar_hit = m_axis_rx_tuser[8:2];
endmodule
|
#include <bits/stdc++.h> using namespace std; int const sz = 2 * 1e5; int const oo = 1e9; bool comp(int i, int j) { return i < j; } long long num[1000000], kk[101]; void fill(int n, int m) { long long arr[4] = {0, 1, 2, 3}; int l = 0; num[0] = 1; num[1] = 2; num[2] = 3; for (int i = 3; i < n; i++) { arr[(l % 3) + 1] = ((arr[1] + arr[2] + arr[3]) % m) + 1; num[i] = arr[(l++ % 3) + 1]; if (num[i] < 101) kk[num[i]]++; } } long long check(long long m, int k) { long long a = 1; long long sum = 0; while (m / a > 0) { sum = sum + (m / a); a *= k; } return sum; } void solve() { long long n, k; cin >> n >> k; long long l = 0, r = n; while (l < r - 1) { long long m = (l + r) / 2; if (check(m, k) >= n) r = m; else l = m; } cout << r; } int main() { ios::sync_with_stdio(0); cin.tie(0); solve(); } |
#include <bits/stdc++.h> using namespace std; const int inf = 1000000007; const long long linf = 1LL << 62; const unsigned long long ulinf = 1ULL << 63; const double eps = 0.000001; const double pi = 3.14159265358979323846; template <class T> T abs(T a) { return a >= 0 ? a : -a; } template <class T> T sqr(T a) { return a * a; } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> T mod(T a, T b) { return (a % b + b) % b; } template <class T> T addmod(T a, T b, T c) { return (T)mod((long long)a + b, (long long)c); } template <class T> T mulmod(T a, T b, T c) { return (T)mod((long long)a * b, (long long)c); } template <class T> T powmod(T a, T b, T c) { return (T)mod( b ? mulmod(mod(sqr((long long)powmod(a, b >> 1, c)), (long long)c), (b & 1LL) ? a : 1LL, (long long)c) : 1LL, (long long)c); } template <class T> void maxe(T &a, T b) { a = max(a, b); } template <class T> void mine(T &a, T b) { a = min(a, b); } template <class T> void mode(T &a, T b) { a = mod(a, b); } template <class T> void addmode(T &a, T b, T c) { a = addmod(a, b, c); } template <class T> void mulmode(T &a, T b, T c) { a = mulmod(a, b, c); } template <class T> void powmode(T &a, T b, T c) { a = powmod(a, b, c); } int iszero(double a) { return abs(a) <= eps; } template <class T> void getint(T &a) { a = 0; int b = 1, c = getchar(); if (c == - ) b = -1; else a = c - 48; while ((c = getchar()) != && c != n ) a = a * 10 + c - 48; a *= b; } void fileio_in_out() { freopen( .in , r , stdin); freopen( .out , w , stdout); } void fileio_txt() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } const int N = 1111; int test; int n, m, k, ans; int a[41] = {0, 2, 3, 5, 7, 13, 17, 19, 31, 61, 89, 107, 127, 521, 607, 1279, 2203, 2281, 3217, 4253, 4423, 9689, 9941, 11213, 19937, 21701, 23209, 44497, 86243, 110503, 132049, 216091, 756839, 859433, 1257787, 1398269, 2976221, 3021377, 6972593, 13466917, 20996011}; const int md = inf; int main() { scanf( %d , &n); printf( %d n , addmod(powmod(2, a[n] - 1, md), -1, md)); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int MOD = INF + 7; int memo[3000 + 1][100 + 1][100]; int N; vector<int> a, b; int solve(int len, int w, int nouse) { if (len == 0) return 1; if (len < 0) return 0; if (memo[len][w][nouse] != -1) return memo[len][w][nouse]; int res = 0; for (int i = 0; i < N; i++) if (i != nouse) { if (a[i] == w) res = (res + solve(len - b[i], b[i], i)) % MOD; else if (b[i] == w) res = (res + solve(len - a[i], a[i], i)) % MOD; } memo[len][w][nouse] = res; return res; } int main() { ios_base::sync_with_stdio(false); memset(memo, -1, sizeof(memo)); int l; cin >> N >> l; a.resize(N); b.resize(N); for (int i = 0, _n = N; i < _n; i++) { cin >> a[i] >> b[i]; } int res = 0; for (int i = 0, _n = 100; i < _n; i++) res = (res + solve(l, i + 1, -1)) % MOD; cout << res << endl; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:54 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_sim_netlist.v
// Design : system_util_vector_logic_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_util_vector_logic_0_0,util_vector_logic,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_vector_logic,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_util_vector_logic_0_0
(Op1,
Op2,
Res);
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
wire [0:0]Op1;
wire [0:0]Op2;
wire [0:0]Res;
LUT2 #(
.INIT(4'h8))
\Res[0]_INST_0
(.I0(Op1),
.I1(Op2),
.O(Res));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXTP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i; double sum = 0, num, av, av1; cin >> n >> k; int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; sum = sum + a[i]; } av1 = sum / n; if (av1 >= (k - .5)) { cout << 0 << endl; return 0; } else { for (i = 1;; i++) { sum = sum + k; num = n + i; av = sum / num; if (av >= (k - 0.5)) { cout << i << endl; return 0; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[200000]; map<long long, bool> mm; int main() { int n, t, k, d; cin >> n >> t >> k >> d; int res0 = 0, res1 = 0, sum0 = 0, sum1 = 0; while (sum0 < n) res0 += t, sum0 += k; for (int i = 1; i <= 10000; i++) { if (i % t == 0) sum1 += k, res1 = i; if (sum1 >= n) break; if (i % (d + t) == 0) sum1 += k, res1 = i; if (sum1 >= n) break; } if (res1 < res0) cout << YES n ; else cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, i, j; char e, f; string s, x, y; set<string> v; cin >> x >> y; x[0] = x[0] - a + 1 + 0 ; a = x[0] - a + 1; b = x[1] - 0 + 1; e = x[0]; f = x[1]; y[0] = y[0] - a + 1 + 0 ; v.insert(x); v.insert(y); for (i = 1; i <= 8; i++) { s = ; s += x[0]; s += (i + 0 ); v.insert(s); s = ; s += (i + 0 ); s += x[1]; v.insert(s); } s = ; s = x[0] + 1; s += x[1] + 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] - 1; s += x[1] + 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] + 2; s += x[1] + 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] - 2; s += x[1] + 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] + 1; s += x[1] - 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] + 2; s += x[1] - 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] - 1; s += x[1] - 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = x[0] - 2; s += x[1] - 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] + 1; s += y[1] + 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] - 1; s += y[1] + 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] + 2; s += y[1] + 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] - 2; s += y[1] + 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] + 1; s += y[1] - 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] + 2; s += y[1] - 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] - 1; s += y[1] - 2; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } s = ; s = y[0] - 2; s += y[1] - 1; if (s[1] >= 1 && s[1] <= 8 && s[0] >= 1 && s[0] <= 8 ) { v.insert(s); } cout << 64 - v.size() << endl; return 0; } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; struct Query { int idx, k; }; int n, m; int c[N], ans[N], cnt[N], pref[N]; vector<Query> qs[N]; vector<int> adj[N]; void read() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= n - 1; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } for (int i = 1; i <= m; i++) { int v, k; cin >> v >> k; qs[v].push_back({i, k}); } } int idx = 0; int fs[N], ed[N], euler[N], sz[N]; void findSz(int u, int p) { sz[u] = 1; fs[u] = ++idx; euler[idx] = u; for (auto& v : adj[u]) { if (v != p) { findSz(v, u); sz[u] += sz[v]; } } ed[u] = idx; } void dfs(int u, int p, bool keep) { int mx = -1, bigChild = -1; for (auto& v : adj[u]) { if (v != p && mx < sz[v]) mx = sz[v], bigChild = v; } for (auto& v : adj[u]) { if (v != p && v != bigChild) dfs(v, u, 0); } if (bigChild != -1) dfs(bigChild, u, 1); for (auto& v : adj[u]) { if (v != p && v != bigChild) { for (int i = fs[v]; i <= ed[v]; i++) { pref[cnt[c[euler[i]]]]--; cnt[c[euler[i]]]++; } } } pref[cnt[c[u]]]--; cnt[c[u]]++; for (auto& q : qs[u]) ans[q.idx] = N - pref[q.k - 1]; if (!keep) { for (int i = fs[u]; i <= ed[u]; i++) { cnt[c[euler[i]]]--; pref[cnt[c[euler[i]]]]++; } } } void solve() { findSz(1, 0); memset(cnt, 0, sizeof cnt); for (int i = 0; i < N; i++) pref[i] = N; dfs(1, 0, 1); for (int i = 1; i <= m; i++) cout << ans[i] << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); read(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int n, m, c; cin >> n >> m >> c; for (int i = 1; i <= m; i++) { int x, ans; cin >> x; if (x <= c / 2) { for (int j = 1; j <= n; j++) { if (x < a[j] || a[j] == 0) { a[j] = x; ans = j; break; } } } else { for (int j = n; j >= 1; j--) { if (x > a[j] || a[j] == 0) { a[j] = x; ans = j; break; } } } cout << ans << endl; } } |
module test_bench(clk, rst);
input clk;
input rst;
wire [63:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [63:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [63:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
double_multiplier multiplier_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
module digital_sound_output (
input clk,
input rst,
input enabled,
input[15:0] left,
input[15:0] right,
output bck,
output sd,
output lrck,
output consume
);
parameter CLK_FREQUENCY = 33868800;
localparam BCK_HALF_PERIOD = (CLK_FREQUENCY / 44100 / 64 / 2);
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
reg [log2(BCK_HALF_PERIOD)-1:0] bck_counter_d, bck_counter_q;
reg bck_d, bck_q;
reg sd_d, sd_q;
reg lrck_d, lrck_q;
reg bit_active_d, bit_active_q;
reg [5:0] bit_counter_d, bit_counter_q;
reg [31:0] shiftreg_d, shiftreg_q;
reg consume_d, consume_q;
assign bck = bck_q;
assign sd = sd_q;
assign lrck = lrck_q;
assign consume = consume_q;
always @(*) begin
if (enabled) begin
if (bck_counter_q == BCK_HALF_PERIOD-1) begin
bck_counter_d = 0;
bck_d = ~bck_q;
end else begin
bck_counter_d = bck_counter_q + 1;
bck_d = bck_q;
end
end else begin
bck_counter_d = 0;
bck_d = bck_q;
end
if ((bck_counter_q == BCK_HALF_PERIOD-2) & bck_q & enabled)
bit_active_d = 1'b1;
else
bit_active_d = 1'b0;
shiftreg_d = (enabled? shiftreg_q : 32'h00000000);
consume_d = 1'b0;
if (bit_active_q) begin
if (bit_counter_q[4]) begin
sd_d = shiftreg_q[31];
shiftreg_d = {shiftreg_q[30:0],1'b0};
end else begin
sd_d = 1'b0;
if (bit_counter_q == 0) begin
shiftreg_d = {left, right};
consume_d = 1'b1;
end
end
lrck_d = ~bit_counter_q[5];
bit_counter_d = bit_counter_q+1;
end else begin
sd_d = sd_q;
lrck_d = lrck_q;
bit_counter_d = bit_counter_q;
end
end
always @(posedge clk) begin
if (rst) begin
bck_counter_q <= 0;
bck_q <= 1'b0;
sd_q <= 1'b0;
lrck_q <= 1'b0;
bit_active_q <= 1'b0;
bit_counter_q <= 5'b00000;
shiftreg_q <= 32'h00000000;
consume_q <= 1'b0;
end else begin
bck_counter_q <= bck_counter_d;
bck_q <= bck_d;
sd_q <= sd_d;
lrck_q <= lrck_d;
bit_active_q <= bit_active_d;
bit_counter_q <= bit_counter_d;
shiftreg_q <= shiftreg_d;
consume_q <= consume_d;
end
end
endmodule // digital_sound_output
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<vector<pair<int, string> > > rg(m, vector<pair<int, string> >(1)); for (int i = 0; i < n; i++) { string sn; int r, s; cin >> sn; scanf( %d %d , &r, &s); rg[r - 1].push_back(make_pair(s, sn)); } for (int i = 0; i < m; i++) { rg[i][0] = make_pair(-10, xD ); sort(rg[i].begin(), rg[i].end()); reverse(rg[i].begin(), rg[i].end()); cout << (rg[i][1].first == rg[i][2].first ? ? : string(rg[i][0].second + + rg[i][1].second)) << endl; } } |
#include <bits/stdc++.h> using namespace std; int x[3010], y[3010]; vector<int> py[3010]; int L[3010], R[3010], q, k; void nxt(int &u, int k = 1) { while (k-- > 0) u = R[u]; } void pre(int &u, int k = 1) { while (k-- > 0) u = L[u]; } long long res = 0; struct node { int x, y; bool operator<(const node a) const { return x < a.x; } } p[3010]; int n, m; void solve() { res = 0; int l = 0, r = 0; nxt(r, k); if (r == q + 1) return; for (; r != q + 1; nxt(r)) { nxt(l); res += 1ll * p[l].x * (p[R[r]].x - p[r].x); } } void del(int u) { R[L[u]] = R[u], L[R[u]] = L[u]; } void erase(int u) { int l = u; pre(l, k + 1); int l0 = l; int r = l; nxt(r, k); for (; l < u && r < q + 1; nxt(r)) { nxt(l); res -= 1ll * p[l].x * (p[R[r]].x - p[r].x); } del(u); l = r = l0; nxt(r, k); for (; R[l] < u && r < q + 1; nxt(r)) { nxt(l); res += 1ll * p[l].x * (p[R[r]].x - p[r].x); } } int main() { scanf( %d%d%d%d , &n, &m, &q, &k); for (int i = 1; i <= q; i++) scanf( %d%d , &p[i].x, &p[i].y); sort(p + 1, p + q + 1); p[q + 1] = (node){n + 1, m + 1}; for (int i = 1; i <= q; i++) py[p[i].y].push_back(i); long long ans = 0; R[q + 1] = q + 1; for (int y0 = 1; y0 <= m; y0++) { int pr = 0; for (int i = 1; i <= q; i++) if (p[i].y <= y0) L[i] = pr, pr = i; else L[i] = 0; L[q + 1] = pr; pr = q + 1; for (int i = q; i >= 1; i--) if (p[i].y <= y0) R[i] = pr, pr = i; else R[i] = 0; R[0] = pr; solve(); ans += res; for (int y = 1; y <= y0; y++) { for (int u : py[y]) erase(u); ans += res; } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; char c; int mo = 1000003; int main() { int pre = 0; while (scanf( %c , &c) != EOF) { if (c < 32 || c > 126) break; int w = c; int tmp = 0; for (int j = 0; j < 8; j++) { tmp = tmp * 2 + w % 2; w /= 2; } w = tmp; tmp = pre - tmp; pre = w; if (tmp < 0) tmp += 256; printf( %d n , tmp); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1 << 30; const long long Inf = 1ll << 60ll; namespace io { char buf[(1 << 23)], *p1 = buf, *p2 = buf, c; long long f; template <typename T> T read() { T x = 0; f = 0; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, (1 << 23), stdin), p1 == p2) ? EOF : *p1++); while (!isdigit(c)) (c == - ) && (f = 1), c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, (1 << 23), stdin), p1 == p2) ? EOF : *p1++); while (isdigit(c)) x = x * 10 + (c & 15), c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, (1 << 23), stdin), p1 == p2) ? EOF : *p1++); return f ? -x : x; } } // namespace io const long long N = 200005, mod = 998244353; long long n, k, fac[N], a[N], inv[N]; long long qpow(long long b, long long p) { long long res = 1; while (p) { if (p & 1) res = res * b % mod; b = b * b % mod; p >>= 1ll; } return res; } long long C(long long x, long long y) { return fac[x] * inv[y] % mod * inv[x - y] % mod; } signed main() { scanf( %lld%lld , &n, &k); long long cnt = 0; fac[0] = inv[0] = 1; for (long long i = 1; i <= n; ++i) fac[i] = fac[i - 1] * i % mod, inv[i] = qpow(fac[i], mod - 2); for (long long i = 1; i <= n; ++i) scanf( %lld , &a[i]); for (long long i = 1; i < n; ++i) if (a[i] != a[i + 1]) cnt++; if (a[1] != a[n]) cnt++; long long ans = qpow(k, n), v = 0; for (long long i = 0; i <= cnt / 2; ++i) (v += qpow(k - 2, cnt - i * 2) * C(cnt, i) % mod * C(cnt - i, i)) %= mod; v = v * qpow(k, n - cnt) % mod; printf( %lld n , (ans - v + mod) * (mod / 2 + 1) % mod); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_io.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_io(/*AUTOARG*/
// Outputs
cpx_io_grant_bufio_ca, io_cpx_req_bufio_cq_l,
// Inputs
cpx_io_grant_ca, io_cpx_req_cq
);
output [7:0] cpx_io_grant_bufio_ca;
output [7:0] io_cpx_req_bufio_cq_l;
input [7:0] cpx_io_grant_ca;
input [7:0] io_cpx_req_cq;
assign cpx_io_grant_bufio_ca = cpx_io_grant_ca;
assign io_cpx_req_bufio_cq_l = ~io_cpx_req_cq;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
//
// Filename : mc_chroma_ip4x4.v
// Created On : 2013-11-18 12:42:37
// Last Modified : 2013-11-24 16:38:17
// Revision :
// Author : Yufeng Bai
// Email :
// Description :
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_chroma_ip4x4(
clk,
rstn,
frac_i,
blk_start_i,
refuv_valid_i,
refuv_p0_i,
refuv_p1_i,
refuv_p2_i,
refuv_p3_i,
refuv_p4_i,
refuv_p5_i,
refuv_p6_i,
frac_valid_o ,
end_oneblk_ip_o,
fracuv_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rstn;
input [5 :0] frac_i;
input blk_start_i;
input refuv_valid_i;
input [`PIXEL_WIDTH-1:0] refuv_p0_i;
input [`PIXEL_WIDTH-1:0] refuv_p1_i;
input [`PIXEL_WIDTH-1:0] refuv_p2_i;
input [`PIXEL_WIDTH-1:0] refuv_p3_i;
input [`PIXEL_WIDTH-1:0] refuv_p4_i;
input [`PIXEL_WIDTH-1:0] refuv_p5_i;
input [`PIXEL_WIDTH-1:0] refuv_p6_i;
output end_oneblk_ip_o;
output frac_valid_o;
output [4*`PIXEL_WIDTH-1:0] fracuv_o;
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [1:0] cnt_ip_row;
//reg end_oneblk_ip_o;
reg frac_valid_o;
reg [4*`PIXEL_WIDTH-1:0] fracuv_o;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire [2:0] fracx;
wire [2:0] fracy;
wire fracuv_valid;
wire [`PIXEL_WIDTH-1:0] fracuv_p0;
wire [`PIXEL_WIDTH-1:0] fracuv_p1;
wire [`PIXEL_WIDTH-1:0] fracuv_p2;
wire [`PIXEL_WIDTH-1:0] fracuv_p3;
assign fracx = frac_i[2:0];
assign fracy = frac_i[5:3];
// ********************************************
//
// Sequential Logic Combinational Logic
//
// ********************************************
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt_ip_row <= 'd0;
end
else if (blk_start_i || (end_oneblk_ip_o)) begin
cnt_ip_row <= 'd0;
end
else if (frac_valid_o) begin
cnt_ip_row <= cnt_ip_row + 'd1;
end
end
assign end_oneblk_ip_o = (cnt_ip_row == 'd3);
// ********************************************
//
// Sub Module
//
// ********************************************
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
fracuv_o <= 'd0;
frac_valid_o<= 'd0;
end
else if (fracuv_valid) begin
fracuv_o <= {fracuv_p0,fracuv_p1,fracuv_p2,fracuv_p3};
frac_valid_o<= 'd1;
end
else begin
fracuv_o <= fracuv_o;
frac_valid_o<= 'd0;
end
end
mc_chroma_ip_1p mc_chroma_ip0(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p0_i),
.refuv_p1_i (refuv_p1_i),
.refuv_p2_i (refuv_p2_i),
.refuv_p3_i (refuv_p3_i),
.fracuv_valid_o(fracuv_valid),
.fracuv_p_o (fracuv_p0)
);
mc_chroma_ip_1p mc_chroma_ip1(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p1_i),
.refuv_p1_i (refuv_p2_i),
.refuv_p2_i (refuv_p3_i),
.refuv_p3_i (refuv_p4_i),
.fracuv_valid_o(/*fracuv_valid*/),
.fracuv_p_o (fracuv_p1)
);
mc_chroma_ip_1p mc_chroma_ip2(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p2_i),
.refuv_p1_i (refuv_p3_i),
.refuv_p2_i (refuv_p4_i),
.refuv_p3_i (refuv_p5_i),
.fracuv_valid_o(/*fracuv_valid*/),
.fracuv_p_o (fracuv_p2)
);
mc_chroma_ip_1p mc_chroma_ip3(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p3_i),
.refuv_p1_i (refuv_p4_i),
.refuv_p2_i (refuv_p5_i),
.refuv_p3_i (refuv_p6_i),
.fracuv_valid_o(/*fracuv_valid*/),
.fracuv_p_o (fracuv_p3)
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; int main() { int n; scanf( %d , &n); printf( %d , n); for (int i = 1; i < n; i++) printf( %d , i); return 0; } |
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_bidir_ramif_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "FALSE" // First word fall-through, not sure it can be disabled for this
) (
input wire a_clk,
input wire a_rst_n,
input wire a_winc,
input wire [DSIZE-1:0] a_wdata,
input wire a_rinc,
output wire [DSIZE-1:0] a_rdata,
output wire a_full,
output wire a_afull,
output wire a_empty,
output wire a_aempty,
input wire a_dir, // dir = 1: this side is writing, dir = 0: this side is reading
input wire b_clk,
input wire b_rst_n,
input wire b_winc,
input wire [DSIZE-1:0] b_wdata,
input wire b_rinc,
output wire [DSIZE-1:0] b_rdata,
output wire b_full,
output wire b_afull,
output wire b_empty,
output wire b_aempty,
input wire b_dir, // dir = 1: this side is writing, dir = 0: this side is reading
// Dual-port RAM interface
output wire o_ram_a_clk,
output wire [DSIZE-1:0] o_ram_a_wdata,
input wire [DSIZE-1:0] i_ram_a_rdata,
output wire [ASIZE-1:0] o_ram_a_addr,
output wire o_ram_a_rinc,
output wire o_ram_a_winc,
output wire o_ram_b_clk,
output wire [DSIZE-1:0] o_ram_b_wdata,
input wire [DSIZE-1:0] i_ram_b_rdata,
output wire [ASIZE-1:0] o_ram_b_addr,
output wire o_ram_b_rinc,
output wire o_ram_b_winc
);
wire [ASIZE-1:0] a_addr, b_addr;
wire [ASIZE-1:0] a_waddr, a_raddr, b_waddr, b_raddr;
wire [ ASIZE:0] a_wptr, b_rptr, a2b_wptr, b2a_rptr;
wire [ ASIZE:0] a_rptr, b_wptr, a2b_rptr, b2a_wptr;
assign a_addr = a_dir ? a_waddr : a_raddr;
assign b_addr = b_dir ? b_waddr : b_raddr;
//////////////////////////////////////////////////////////////////////////////
// A-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync b write pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_wptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_wptr),
.dest_ptr (b2a_wptr)
);
// Sync b read pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_rptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_rptr),
.dest_ptr (b2a_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (a is writing)
wptr_full #(ASIZE)
a_wptr_inst
(
.wclk (a_clk),
.wrst_n (a_rst_n),
.winc (a_winc),
.wq2_rptr (b2a_rptr),
.awfull (a_afull),
.wfull (a_full),
.waddr (a_waddr),
.wptr (a_wptr)
);
// dir == 1 read pointer on a side calculation
rptr_empty #(ASIZE)
a_rptr_inst
(
.rclk (a_clk),
.rrst_n (a_rst_n),
.rinc (a_rinc),
.rq2_wptr (b2a_wptr),
.arempty (a_aempty),
.rempty (a_empty),
.raddr (a_raddr),
.rptr (a_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// B-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync a write pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_wptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_wptr),
.dest_ptr (a2b_wptr)
);
// Sync a read pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_rptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_rptr),
.dest_ptr (a2b_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (b is writing)
wptr_full #(ASIZE)
b_wptr_inst
(
.wclk (b_clk),
.wrst_n (b_rst_n),
.winc (b_winc),
.wq2_rptr (a2b_rptr),
.awfull (b_afull),
.wfull (b_full),
.waddr (b_waddr),
.wptr (b_wptr)
);
// dir == 1 read pointer on b side calculation
rptr_empty #(ASIZE)
b_rptr_inst
(
.rclk (b_clk),
.rrst_n (b_rst_n),
.rinc (b_rinc),
.rq2_wptr (a2b_wptr),
.arempty (b_aempty),
.rempty (b_empty),
.raddr (b_raddr),
.rptr (b_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// FIFO RAM interface
//////////////////////////////////////////////////////////////////////////////
assign o_ram_a_clk = a_clk;
assign o_ram_a_wdata = a_wdata;
assign a_rdata = i_ram_a_rdata;
assign o_ram_a_addr = a_addr;
assign o_ram_a_rinc = a_rinc & !a_dir;
assign o_ram_a_winc = a_winc & a_dir;
assign o_ram_b_clk = b_clk;
assign o_ram_b_wdata = b_wdata;
assign b_rdata = i_ram_b_rdata;
assign o_ram_b_addr = b_addr;
assign o_ram_b_rinc = b_rinc & !b_dir;
assign o_ram_b_winc = b_winc & b_dir;
endmodule
`resetall
|
#include <bits/stdc++.h> namespace XX { template <template <typename> class Compare, typename T> inline T& UP(T& x, const T& y) { if (Compare<T>()(y, x)) x = y; return x; } template <typename Compare, typename T> inline T& UP(T& x, const T& y, Compare comp) { if (comp(y, x)) x = y; return x; } template <typename T> inline T& GT(T& x, const T& y) { return UP<std::greater>(x, y); } template <typename T> inline T& LS(T& x, const T& y) { return UP<std::less>(x, y); } template <typename T> struct Mapper { int operator[](const T& v) { int& ret = table[v]; if (!ret) rtable[ret = table.size()] = v; return ret - 1; } template <typename... Args> int operator()(Args... args) { return (*this)[T(args...)]; } T rev(int idx) { return rtable[idx + 1]; } std::map<T, int> table; std::map<int, T> rtable; }; template <typename T, int S> struct ReferenceArray { struct It { typename std::array<T*, S>::iterator it; T& operator*() { return **it; } void operator++() { it++; } bool operator!=(const It& other) { return it != other.it; } }; int size() const { return _ptr.size(); } It begin() const { return {_ptr.begin()}; } It end() const { return {_ptr.end()}; } T& operator[](int idx) const { return *_ptr[idx]; } mutable std::array<T*, S> _ptr; }; template <typename T, typename... Args> ReferenceArray<T, sizeof...(Args) + 1> MAKEV(T& arg1, Args&... args) { return {&arg1, &args...}; } struct Range { struct It { int num, step; int operator*() { return num; } void operator++() { num += step; } bool operator!=(const It& other) { return num != other.num; } }; Range(int ee) : b(0), e(ee) {} Range(int bb, int ee) : b(bb), e(ee) {} It begin() { return {b, (b < e ? 1 : -1)}; } It end() { return {e, 0}; } int b, e; }; } // namespace XX template <typename T> struct ScanfSpecifier {}; template <> struct ScanfSpecifier<int> { static constexpr const char* value = %d ; }; template <> struct ScanfSpecifier<double> { static constexpr const char* value = %lf ; }; template <> struct ScanfSpecifier<float> { static constexpr const char* value = %f ; }; template <> struct ScanfSpecifier<char> { static constexpr const char* value = %c ; }; template <> struct ScanfSpecifier<const char*> { static constexpr const char* value = %s ; }; template <> struct ScanfSpecifier<unsigned long> { static constexpr const char* value = %lu ; }; template <> struct ScanfSpecifier<char*> { static constexpr const char* value = %s ; }; template <> struct ScanfSpecifier<unsigned int> { static constexpr const char* value = %u ; }; template <> struct ScanfSpecifier<long long int> { static constexpr const char* value = %lld ; }; template <typename T> int RD(T& arg) { return std::scanf(ScanfSpecifier<T>::value, &arg); } template <int S> int RD(char (&arg)[S]) { return std::scanf( %s , arg); } template <> int RD<char*>(char*& arg) { return std::scanf( %s , arg); } template <> int RD<char>(char& arg) { return std::scanf( %c , &arg); } template <typename T, typename... Args> int RD(T& arg1, Args&... args) { return RD(arg1) + RD(args...); } template <typename T> T RD() { T ret; RD(ret); return ret; } template <typename It> void RDV(It begin, It end) { while (begin != end) RD(*begin++); } template <typename C> void RDV(C& c) { RDV(std::begin(c), std::end(c)); } template <typename... Args> void WT(Args... args) { int alc = 0; int dummy[] = {((alc++ ? std::printf( ) : 0), std::printf(ScanfSpecifier<Args>::value, args), 0)...}; } template <typename... Args> void WTL(Args... args) { WT(args...); std::printf( n ); } template <typename It> void WTV(It begin, It end) { int alc = 0; while (begin != end) (alc++ ? std::printf( ) : 0), WT(*begin++); } template <typename C> void WTV(const C& c) { WTV(std::begin(c), std::end(c)); } template <typename It> void WTVL(It begin, It end) { WTV(begin, end); std::printf( n ); } template <typename C> void WTVL(const C& c) { WTVL(std::begin(c), std::end(c)); } template <typename T> T& UMAX(T& x, T y) { return XX::UP<std::greater>(x, y); } template <typename T> T& UMIN(T& x, T y) { return XX::UP<std::less>(x, y); } using XX::UP; using RG = XX::Range; using XX::MAKEV; using XX::Mapper; using namespace std; map<pair<long long int, long long int>, long long int> cost; vector<pair<long long int, long long int> > road(long long int u, long long int v) { vector<pair<long long int, long long int> > ret; while (u != v) { if (u > v) swap(u, v); ret.emplace_back(v, v / 2); v /= 2; } return ret; } int main() { int Q; RD(Q); while (Q--) { int t; RD(t); if (t == 1) { long long int u, v, w; RD(u, v, w); for (pair<long long int, long long int> r : road(u, v)) cost[r] += w; } else { long long int u, v; RD(u, v); long long int ans = 0; for (pair<long long int, long long int> r : road(u, v)) ans += cost[r]; WTL(ans); } } } |
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("65.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("130.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int r, c; string str_col[1000006]; string str_dir[1000006]; vector<int> e[1000006], rev[1000006]; int col[1000006], vis[1000006], vis2[1000006]; int cyc_len, black_cnt; inline int id(int x, int y) { return c * x + y; } vector<int> st; int got[1000006]; void dfs2(int v, int mod, int d = 0) { if (0) cerr << vis2 << v << << col[v] << n ; vis2[v] = 1; got[d] |= col[v]; for (int u : rev[v]) { if (not vis2[u]) dfs2(u, mod, (d + 1) % mod); } } void dfs(int v) { if (vis[v] or vis2[v]) return; if (0) cerr << dfs << v << n ; vis[v] = 1; st.push_back(v); for (int u : e[v]) { if (not vis[u]) dfs(u); else { int cyc = st.end() - find(st.begin(), st.end(), u); if (cyc == 0) continue; fill(got, got + cyc, 0); if (0) cerr << call cyc << v << << u << n ; dfs2(u, cyc); black_cnt += accumulate(got, got + cyc, 0); cyc_len += cyc; } } st.pop_back(); } void solve() { cin >> r >> c; for (int i = 0; i < r; i++) cin >> str_col[i]; for (int i = 0; i < r; i++) cin >> str_dir[i]; for (int x = 0; x < r; x++) for (int y = 0; y < c; y++) { int nx = x, ny = y; if (str_dir[x][y] == U ) nx--; if (str_dir[x][y] == D ) nx++; if (str_dir[x][y] == L ) ny--; if (str_dir[x][y] == R ) ny++; e[id(x, y)].push_back(id(nx, ny)); rev[id(nx, ny)].push_back(id(x, y)); if (0) cerr << rev << id(nx, ny) << << id(x, y) << n ; col[id(x, y)] = str_col[x][y] == 0 ; } int n = r * c; for (int i = 0; i < n; i++) { if (not vis[i] and not vis2[i]) { if (0) cerr << call dfs << i << n ; dfs(i); } } cout << cyc_len << << black_cnt << n ; } void reset() { for (int i = 0; i < r * c; i++) { e[i].clear(); rev[i].clear(); vis[i] = vis2[i] = cyc_len = black_cnt = 0; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; cin >> t; for (int no = 1; no <= t; no++) { solve(); reset(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_BEHAVIORAL_V |
// file: mmcm_mkid_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module mmcm_mkid_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.812*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (7.812*1*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise4;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", /period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", /period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", /period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", /period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
mmcm_mkid_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, x, i, w[100005], sum; int main() { cin >> n >> x; for (i = 1; i <= n; i++) { cin >> w[i]; sum = sum + w[i]; } if (sum + n - 1 == x) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, i; while (scanf( %lld %lld , &n, &k) != EOF) { vector<long long int> v; for (i = 1; i * i <= n; i++) { if (n % i == 0) { v.push_back(i); if ((n / i) != i) v.push_back(n / i); } } sort(v.begin(), v.end()); if (v.size() < k) { cout << -1 << endl; } else { printf( %lld n , v[k - 1]); } } return 0; } |
#include <bits/stdc++.h> int main() { int t, j; scanf( %d , &t); for (j = 1; j <= t; j++) { int n, d = 0, i; char a[100000], b[100000], c[100000]; scanf( %s %s %s , a, b, c); n = strlen(a); for (i = 0; i < n; i++) { if (a[i] == c[i] || b[i] == c[i]) d++; if (a[i] == b[i] && b[i] != c[i]) break; } if (d == n) printf( YES n ); else printf( NO n ); } } |
#include <bits/stdc++.h> using namespace std; int n, k, p; int dp[111][555555], cur[111], a[555555], ld[111], sum[555555], dpp[555555], bit[1111], sz; void update(int x, int p) { while (x <= sz) { bit[x] = max(bit[x], p); x += x & (-x); } } int query(int x) { int res = 0; while (x >= 1) { res = max(res, bit[x]); x -= x & (-x); } return res; } int main() { scanf( %d%d%d , &n, &k, &p); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); a[i] %= p; } if (k * p >= n) { for (int i = 0; i <= k; i++) { for (int j = 0; j <= n; j++) dp[i][j] = 1e9; } dp[0][0] = 0; for (int i = 1; i <= k; i++) { for (int j = 0; j < p; j++) cur[j] = 1e9; for (int j = 1; j <= n; j++) { for (int h = 0; h < p; h++) ld[(h + a[j]) % p] = cur[h]; for (int h = 0; h < p; h++) cur[h] = ld[h]; cur[a[j]] = min(cur[a[j]], dp[i - 1][j - 1]); for (int h = 0; h < p; h++) dp[i][j] = min(dp[i][j], cur[h] + h); } } cout << dp[k][n] << endl; } else { for (int i = 1; i <= n; i++) sum[i] = (sum[i - 1] + a[i]) % p; sz = 1; while (sz < p) sz *= 2; for (int i = 1; i <= n; i++) { dpp[i] = query(sum[i] + 1) + 1; update(sum[i] + 1, dpp[i]); } if (dpp[n] >= k) cout << sum[n] << endl; else cout << sum[n] + p << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100 + 5; int n, m, ord[N << 1], nord = 0; vector<int> adj[N << 1], radj[N << 1]; bool vis[N << 1]; int ncmp = 0, cmp[N << 1]; vector<int> ans; inline void addedge(int u, int v) { adj[u].push_back((v > n ? v - n : v + n)); ; radj[(v > n ? v - n : v + n)].push_back(u); ; adj[(u > n ? u - n : u + n)].push_back(v); ; radj[v].push_back((u > n ? u - n : u + n)); ; } inline void dfs(int v) { vis[v] = 1; for (int i = 0; i < (int)adj[v].size(); i++) if (!vis[adj[v][i]]) dfs(adj[v][i]); ord[++nord] = v; } inline void rdfs(int v) { cmp[v] = ncmp; vis[v] = 1; for (int i = 0; i < (int)radj[v].size(); i++) if (!vis[radj[v][i]]) rdfs(radj[v][i]); } int main() { scanf( %d%d , &n, &m); int u, v, c; for (int i = 1; i <= m; i++) { scanf( %d%d%d , &u, &v, &c); if (!c) { addedge(u, v); addedge(v, u); } else { addedge(u, (v > n ? v - n : v + n)); addedge((v > n ? v - n : v + n), u); } } memset(vis, 0, sizeof vis); for (int i = 1; i <= 2 * n; i++) if (!vis[i]) dfs(i); memset(vis, 0, sizeof vis); for (; nord--;) { u = ord[nord]; if (!vis[u]) { ncmp++; rdfs(u); } } for (int i = 1; i <= n; i++) { if (cmp[i] == cmp[i + n]) { printf( Impossible n ); return 0; } if (cmp[i + n] < cmp[i]) ans.push_back(i); ; } printf( %d n , (int)ans.size()); for (int i = 0; i < (int)ans.size(); i++) printf( %d , ans[i]); printf( n ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_PP_V |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Tue Jun 21 04:37:54 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_stub.v}
// Design : clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_gen(clk_in1, clk_out1, reset)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset" */;
input clk_in1;
output clk_out1;
input reset;
endmodule
|
// MBT 4/1/2014
// DWP 11/27/2019
//
// 3 read-port, 1 write-port ram
//
// reads are asynchronous
//
// this file should not be directly instantiated by end programmers
// use bsg_mem_3r1w instead
//
`include "bsg_defines.v"
module bsg_mem_3r1w_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
wire unused = w_reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{w_clk_i, w_v_i, w_addr_i, w_data_i, r0_v_i, r0_addr_i, r1_v_i, r1_addr_i, r2_v_i, r2_addr_i};
assign r0_data_o = '0;
assign r1_data_o = '0;
assign r2_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this implementation ignores the r_v_i
assign r2_data_o = mem[r2_addr_i];
assign r1_data_o = mem[r1_addr_i];
assign r0_data_o = mem[r0_addr_i];
wire unused = w_reset_i;
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
mem[w_addr_i] <= w_data_i;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_3r1w_synth)
|
#include <bits/stdc++.h> int s, k; long long f[1000], res[1000]; int main() { scanf( %d %d , &s, &k); f[0] = 0; f[1] = 1; int i; for (i = 2; f[i - 1] <= s; i++) for (int j = 1; i - j > 0 && j <= k; j++) f[i] += f[i - j]; int cnt = 0; for (i = i - 1; i >= 0; i--) if (f[i] <= s) { s -= f[i]; res[cnt++] = f[i]; } printf( %d n , cnt); for (int i = 0; i < cnt; i++) printf( %d , res[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, q, a[200010], b[200010], pos[200010], lst[200010]; int f[200010][30], G[200010][30], L[200010]; int amax(int a, int b) { return a > b ? a : b; } int main() { int i, j, cnt, poss, t, l, r; scanf( %d%d%d , &n, &m, &q); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); pos[a[i]] = i; } for (i = 1; i <= m; i++) { scanf( %d , &b[i]); t = a[pos[b[i]] - 1]; if (!t) t = a[n]; f[i][0] = lst[t]; lst[b[i]] = i; } for (i = 1; 1 << i <= n; i++) { for (j = 1; j <= m; j++) { f[j][i] = f[f[j][i - 1]][i - 1]; } } for (i = 1; i <= m; i++) { poss = i; cnt = n - 1; for (j = 20; j >= 0; j--) { if (cnt - (1 << j) >= 0) { cnt -= 1 << j; poss = f[poss][j]; } } G[i][0] = poss; } for (j = 1; (1 << j) <= m; j++) { for (i = 1; i + (1 << j) - 1 <= m; i++) { G[i][j] = amax(G[i][j - 1], G[i + (1 << (j - 1))][j - 1]); } } L[0] = -1; for (i = 1; i <= m; i++) L[i] = L[i >> 1] + 1; for (i = 1; i <= q; i++) { scanf( %d%d , &l, &r); cnt = L[r - l + 1]; if (amax(G[l][cnt], G[r - (1 << cnt) + 1][cnt]) >= l) printf( 1 ); else printf( 0 ); } return 0; } |
`timescale 1ns / 1ps
module controler_tb();
reg power, start_pause, weight_ch, mode_ch, clk_src;
wire power_light;
wire start_pause_light, water_in_light, washing_light, rinsing_light, dewatering_light, water_out_light;
wire [7:0]anodes, cnodes;
wire [2:0]weight_ch_light;
wire [2:0]state;
wire alarm;
parameter TIME = 1000, DELAY = 10;
controler #(32,0) CONTROLER (.power(power),
.start_pause(start_pause),
.weight_ch(weight_ch),
.mode_ch(mode_ch),
.clk_src(clk_src),
.start_pause_light(start_pause_light),
.weight_ch_light(weight_ch_light),
.water_in_light(water_in_light),
.washing_light(washing_light),
.rinsing_light(rinsing_light),
.dewatering_light(dewatering_light),
.water_out_light(water_out_light),
.power_light(power_light),
.state(state),
.alarm(alarm),
.anodes(anodes),
.cnodes(cnodes)
);
initial begin
power = 0;
clk_src = 0;
start_pause = 0;
weight_ch = 0;
mode_ch = 0;
#TIME $finish;
end
always begin
#(DELAY/10) clk_src = ~clk_src;
end
always begin
#(2*DELAY) mode_ch = 1;
#(2*DELAY) weight_ch = 1; mode_ch = 0; // cann't change when machine isn't turn on
#(2*DELAY) power = 1; weight_ch = 0;
#(2*DELAY) mode_ch = 1; weight_ch = 1;
#(DELAY/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 1;
#(2*DELAY) mode_ch = 1; weight_ch = 1; // cann't change when machine is start
#((2*DELAY)/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 0;
#(2*DELAY) mode_ch = 1; weight_ch = 1; // change when machine is pause
#(DELAY/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 1; // start in new mode
#(2*DELAY) start_pause = 0;
#(5*DELAY) start_pause = 1; // test start_pause
#(73*DELAY) ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_0_V
`define SKY130_FD_SC_LP__O22A_0_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_0 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_0 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_0_V
|
Require Import StructTact.StructTactics.
Require Import InfSeqExt.infseq.
(**
Given a hypothesis H of the form
H: forall ex,
P ex ->
Q ex ->
rest,
replace H with
H: forall ex,
(Q /\_ P) ex ->
rest.
*)
Ltac accum_and_tl H P Q rest ex :=
let H' := fresh in
rename H into H';
assert (H: forall ex, (and_tl Q P) ex -> rest)
by (intros; invcs_prop and_tl; auto);
clear H'.
Ltac prep_eventually_monotonic :=
repeat lazymatch goal with
| [H: forall ex, ?fst ex -> ?P ex -> @?conclusion ex,
H_P : eventually ?P ?s |- _] =>
fail
| H: forall ex, ?fst ex -> ?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, ?fst ex -> @?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, @?fst ex -> ?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, @?fst ex -> @?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
end.
Ltac prep_always_inv :=
apply always_inv;
unfold and_tl in *;
[intros; repeat break_and; break_and_goal|tauto].
Ltac lift_eventually lem :=
pose proof lem;
unfold continuously in *;
prep_eventually_monotonic;
eapply eventually_monotonic; eauto;
try prep_always_inv.
(* would be nice to be able to tell which possible invariant things are actually
going to be invariants before we apply inf_often_monotonic_invar, maybe a
typeclass would help? *)
Ltac prep_inf_often_monotonic_invar :=
repeat lazymatch goal with
| [H: forall ex, ?fst ex -> ?P ex -> @?conclusion ex,
H_P : inf_often ?P ?s |- inf_often ?conclusion ?s] =>
fail
| H: forall ex, ?fst ex -> ?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, ?fst ex -> @?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, @?fst ex -> ?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, @?fst ex -> @?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
end.
Ltac lift_inf_often lem :=
pose proof lem;
prep_inf_often_monotonic_invar;
eapply inf_often_monotonic_invar; eauto;
try prep_always_inv.
Ltac prep_always_monotonic :=
repeat lazymatch goal with
(* | [H: forall ex, ?fst ex -> ?P ex -> @?conclusion ex, *)
(* H_P : always ?P ?s |- _] => *)
(* accum_and_tl H fst P (conclusion ex) ex; fail *)
| H: forall ex, ?fst ex -> ?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, ?fst ex -> @?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, @?fst ex -> ?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
| H: forall ex, @?fst ex -> @?snd ex -> ?tl |- _ =>
accum_and_tl H fst snd tl ex
end.
Ltac lift_always lem :=
pose proof lem;
unfold inf_often in *;
prep_always_monotonic;
eapply always_monotonic; eauto;
try prep_always_inv.
Ltac find_continuously_and_tl :=
match goal with
| H : continuously ?P ?ex, H' : continuously ?Q ?ex |- _ =>
pose proof (continuously_and_tl H H');
clear H H'
end.
Ltac find_always_and_tl :=
match goal with
| H : always ?P ?ex, H' : always ?Q ?ex |- _ =>
pose proof (always_and_tl H H');
clear H H'
end.
|
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