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#include <bits/stdc++.h> using namespace std; int main() { double a, v; cin >> a >> v; double l, d, w; cin >> l >> d >> w; w = min(w, v); double s = w / a; double t = a * s * s / 2; double thead = 0; double vhead = 0; if (t < d) { double t1 = v / a; double t2 = (v - w) / a; double dd = t1 * v / 2 + t2 * (v + w) / 2; if (dd < d) { double t3 = (d - dd) / v; thead = t1 + t2 + t3; vhead = w; } else { double vv = sqrt((2 * a * d + w * w) / 2); thead = vv / a + (vv - w) / a; vhead = w; } } else { thead = sqrt(2 * d / a); vhead = a * thead; } double ttail = 0; double tt = (-vhead + sqrt(vhead * vhead + 2 * a * (l - d))) / a; if (vhead + tt * a < v) { ttail = tt; } else { double t1 = (v - vhead) / a; double rest = (l - d) - (vhead + v) * t1 / 2; double t2 = rest / v; ttail = t1 + t2; } cout << setiosflags(ios::fixed) << setprecision(12); cout << thead + ttail << endl; return 0; } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that conbinational UDPs with x outputs are
* properly executed.
*/
module main;
wire Y;
reg A, B, S;
muxx1 MUX2 ( Y, S, A, B ) ;
initial begin
S = 0;
A = 0;
B = 0;
#1 if (Y !== 1'b0) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 1;
#1 if (Y !== 1'b0) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
S = 1;
#1 if (Y !== 1'b1) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 1'bx;
#1 if (Y !== 1'bx) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 1;
S = 1'bx;
#1 if (Y !== 1'bx) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 0;
#1 if (Y !== 1'b0) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
primitive muxx1(Q, S, A, B);
output Q;
input S, A, B;
table
// S A B Q
0 0 ? : 0 ;
0 1 ? : 1 ;
0 x ? : x ; // problem line
1 ? 0 : 0 ;
1 ? 1 : 1 ;
1 ? x : x ; // problem line
x 0 0 : 0 ;
x 1 1 : 1 ;
endtable
endprimitive
|
`timescale 1ns/10ps
module tb_mathsop;
reg clock, reset;
reg [15:0] x;
wire [15:0] ym1, ym2, yb1, yb2, yc1, yc2;
initial begin
$dumpfile("vcd/mathsop.vcd");
$dumpvars(0, tb_mathsop);
end
initial begin
$from_myhdl(clock, reset, x);
$to_myhdl(ym1, ym2, yb1, yb2, yc1, yc2);
end
/** the myhdl verilog */
mm_sop1 dut_myhdl1(.clock(clock), .reset(reset),
.x(x), .y(ym1));
mm_sop2 dut_myhdl2(.clock(clock), .reset(reset),
.x(x), .y(ym2));
/** the bluespec verilog (wrapper) */
mkSOP1 dut_bsv1(.CLK(clock), .RST_N(reset),
.write_x(x), .read(yb1));
mkSOP2 dut_bsv2(.CLK(clock), .RST_N(reset),
.write_x(x), .read(yb2));
/** the chisel verilog */
// chisel use active high reset
wire mc_reset = ~reset;
mc_sop1 dut_chisel1(.clk(clock), .reset(mc_reset),
.io_x(x), .io_y(yc1));
//mc_sop2 dut_chisel2(.clk(clock), .reset(mc_reset),
// .io_x(x), .io_y(yc1));
endmodule
|
package pkg;
typedef logic [1:0] my_type;
endpackage
module top;
import pkg::*;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pkg::my_type_t a; // From sub_2 of sub_2.v
pkg::my_type_t z; // From sub_1 of sub_1.v
// End of automatics
sub_1 sub_1 (.*,
// Outputs
.z (z), // Implicit .*
// Inputs
.a (a)); // Implicit .*
sub_2 sub_2 (.*,
// Outputs
.a (a), // Implicit .*
// Inputs
.z (z)); // Implicit .*
endmodule
module sub_1
import pkg::*; // bug317
(
input pkg::my_type_t a,
output pkg::my_type_t z
);
endmodule
module sub_2
(
input pkg::my_type_t z,
output pkg::my_type_t a
);
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
|
/*--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- File Name : diffeq.v
-- Author(s) : P. Sridhar
-- Affiliation : Laboratory for Digital Design Environments
-- Department of Electrical & Computer Engineering
-- University of Cincinnati
-- Date Created : June 1991.
-- Introduction : Behavioral description of a differential equation
-- solver written in a synthesizable subset of VHDL.
-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ.
-- Obtained from the Highlevel Synthesis Workshop
-- Repository.
--
-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
-- Date Modified : Sept, 91.
--
-- Disclaimer : This comes with absolutely no guarantees of any
-- kind (just stating the obvious ...)
--
-- Acknowledgement : The Distributed Synthesis Systems research at
-- the Laboratory for Digital Design Environments,
-- University of Cincinnati, is sponsored in part
-- by the Defense Advanced Research Projects Agency
-- under order number 7056 monitored by the Federal
-- Bureau of Investigation under contract number
-- J-FBI-89-094.
--
--------------------------------------------------------------------------
-------------------------------------------------------------------------*/
module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
input clk;
input reset;
input [31:0]aport;
input [31:0]dxport;
output [31:0]xport;
output [31:0]yport;
output [31:0]uport;
reg [31:0]xport;
reg [31:0]yport;
reg [31:0]uport;
wire [31:0]temp;
assign temp = uport * dxport;
always @(posedge clk )
begin
if (reset == 1'b1)
begin
xport <= 0;
yport <= 0;
uport <= 0;
end
else
if (xport < aport)
begin
xport <= xport + dxport;
yport <= yport + temp;//(uport * dxport);
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
end
end
endmodule
|
#include <bits/stdc++.h> int main() { long long int n, a, b, i, t; scanf( %lld %lld %lld , &n, &a, &b); t = n / a + 1; for (i = 0; i < t; i++) { if ((n - (a * i)) % b == 0 && n - (a * i) >= 0) { printf( YES n%lld %lld , i, (n - (a * i)) / b); return 0; } } printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 10; const long long INF = 1e18; const long double EPS = 1e-12; struct Point { long double x, y; Point() {} Point(long double x, long double y) : x(x), y(y) {} Point(const Point &p) : x(p.x), y(p.y) {} Point operator+(const Point &p) const { return Point(x + p.x, y + p.y); } Point operator-(const Point &p) const { return Point(x - p.x, y - p.y); } Point operator*(long double c) const { return Point(x * c, y * c); } Point operator/(long double c) const { return Point(x / c, y / c); } }; long double dot(Point p, Point q) { return p.x * q.x + p.y * q.y; } long double dist2(Point p, Point q) { return dot(p - q, p - q); } long double cross(Point p, Point q) { return p.x * q.y - p.y * q.x; } ostream &operator<<(ostream &os, const Point &p) { os << ( << p.x << , << p.y << ) ; } bool operator<(const Point &a, const Point &b) { return make_pair(a.x, a.y) < make_pair(b.x, b.y); } bool operator==(const Point &a, const Point &b) { return abs(a.x - b.x) < EPS && abs(a.y - b.y) < EPS; } Point RotateCCW90(Point p) { return Point(-p.y, p.x); } Point RotateCW90(Point p) { return Point(p.y, -p.x); } Point RotateCCW(Point p, long double t) { return Point(p.x * cos(t) - p.y * sin(t), p.x * sin(t) + p.y * cos(t)); } Point ProjectPointLine(Point a, Point b, Point c) { return a + (b - a) * dot(c - a, b - a) / dot(b - a, b - a); } Point ProjectPointSegment(Point a, Point b, Point c) { long double r = dot(b - a, b - a); if (fabs(r) < EPS) return a; r = dot(c - a, b - a) / r; if (r < 0) return a; if (r > 1) return b; return a + (b - a) * r; } pair<Point, Point> Perpendicularline(Point a, Point b, Point c) { c = ProjectPointLine(a, b, c); if (a == c) a = b; return make_pair(c, c + RotateCW90(a - c)); } long double DistancePointSegment(Point a, Point b, Point c) { return sqrt(dist2(c, ProjectPointSegment(a, b, c))); } long double DistancePointPlane(long double x, long double y, long double z, long double a, long double b, long double c, long double d) { return fabs(a * x + b * y + c * z - d) / sqrt(a * a + b * b + c * c); } bool LinesParallel(Point a, Point b, Point c, Point d) { return fabs(cross(b - a, c - d)) < EPS; } bool LinesCollinear(Point a, Point b, Point c, Point d) { return LinesParallel(a, b, c, d) && fabs(cross(a - b, a - c)) < EPS && fabs(cross(c - d, c - a)) < EPS; } bool SegmentsIntersect(Point a, Point b, Point c, Point d) { if (LinesCollinear(a, b, c, d)) { if (dist2(a, c) < EPS || dist2(a, d) < EPS || dist2(b, c) < EPS || dist2(b, d) < EPS) return true; if (dot(c - a, c - b) > 0 && dot(d - a, d - b) > 0 && dot(c - b, d - b) > 0) return false; return true; } if (cross(d - a, b - a) * cross(c - a, b - a) > 0) return false; if (cross(a - c, d - c) * cross(b - c, d - c) > 0) return false; return true; } Point ComputeLineIntersection(Point a, Point b, Point c, Point d) { b = b - a; d = c - d; c = c - a; assert(dot(b, b) > EPS && dot(d, d) > EPS); return a + b * cross(c, d) / cross(b, d); } Point ComputeCircleCenter(Point a, Point b, Point c) { b = (a + b) / 2; c = (a + c) / 2; return ComputeLineIntersection(b, b + RotateCW90(a - b), c, c + RotateCW90(a - c)); } bool PointInPolygon(const vector<Point> &p, Point q) { bool c = 0; for (int i = 0; i < p.size(); i++) { int j = (i + 1) % p.size(); if ((p[i].y <= q.y && q.y < p[j].y || p[j].y <= q.y && q.y < p[i].y) && q.x < p[i].x + (p[j].x - p[i].x) * (q.y - p[i].y) / (p[j].y - p[i].y)) c = !c; } return c; } bool PointOnPolygon(const vector<Point> &p, Point q) { for (int i = 0; i < p.size(); i++) if (dist2(ProjectPointSegment(p[i], p[(i + 1) % p.size()], q), q) < EPS) return true; return false; } vector<Point> CircleLineIntersection(Point a, Point b, Point c, long double r) { vector<Point> ret; b = b - a; a = a - c; long double A = dot(b, b); long double B = dot(a, b); long double C = dot(a, a) - r * r; long double D = B * B - A * C; if (D < -EPS) return ret; ret.push_back(c + a + b * (-B + sqrt(D + EPS)) / A); if (D > EPS) ret.push_back(c + a + b * (-B - sqrt(D)) / A); return ret; } vector<Point> CircleCircleIntersection(Point a, Point b, long double r, long double R) { vector<Point> ret; long double d = sqrt(dist2(a, b)); if (d > r + R || d + min(r, R) < max(r, R)) return ret; long double x = (d * d - R * R + r * r) / (2 * d); long double y = sqrt(r * r - x * x); Point v = (b - a) / d; ret.push_back(a + v * x + RotateCCW90(v) * y); if (y > 0) ret.push_back(a + v * x - RotateCCW90(v) * y); return ret; } long double ComputeSignedArea(const vector<Point> &p) { long double area = 0; for (int i = 0; i < p.size(); i++) { int j = (i + 1) % p.size(); area += p[i].x * p[j].y - p[j].x * p[i].y; } return area / 2.0; } long double ComputeArea(const vector<Point> &p) { return fabs(ComputeSignedArea(p)); } Point ComputeCentroid(const vector<Point> &p) { Point c(0, 0); long double scale = 6.0 * ComputeSignedArea(p); for (int i = 0; i < p.size(); i++) { int j = (i + 1) % p.size(); c = c + (p[i] + p[j]) * (p[i].x * p[j].y - p[j].x * p[i].y); } return c / scale; } bool IsSimple(const vector<Point> &p) { for (int i = 0; i < p.size(); i++) { for (int k = i + 1; k < p.size(); k++) { int j = (i + 1) % p.size(); int l = (k + 1) % p.size(); if (i == l || j == k) continue; if (SegmentsIntersect(p[i], p[j], p[k], p[l])) return false; } } return true; } long double area2(Point a, Point b, Point c) { return cross(b - a, c - a); } void ConvexHull(vector<Point> &pts) { sort(pts.begin(), pts.end()); pts.erase(unique(pts.begin(), pts.end()), pts.end()); vector<Point> up, dn; for (int i = 0; i < pts.size(); i++) { while (up.size() > 1 && area2(up[up.size() - 2], up.back(), pts[i]) >= 0) up.pop_back(); while (dn.size() > 1 && area2(dn[dn.size() - 2], dn.back(), pts[i]) <= 0) dn.pop_back(); up.push_back(pts[i]); dn.push_back(pts[i]); } pts = dn; for (int i = (int)up.size() - 2; i >= 1; i--) pts.push_back(up[i]); } bool in_convex(vector<Point> &l, Point p) { int a = 1, b = l.size() - 1, c; if (((l[a].x - l[0].x) * (l[b].y - l[0].y) - (l[a].y - l[0].y) * (l[b].x - l[0].x)) > 0) swap(a, b); if (((l[a].x - l[0].x) * (p.y - l[0].y) - (l[a].y - l[0].y) * (p.x - l[0].x)) >= 0 || ((l[b].x - l[0].x) * (p.y - l[0].y) - (l[b].y - l[0].y) * (p.x - l[0].x)) <= 0) return false; while (abs(a - b) > 1) { c = (a + b) / 2; if (((l[c].x - l[0].x) * (p.y - l[0].y) - (l[c].y - l[0].y) * (p.x - l[0].x)) > 0) b = c; else a = c; } return ((l[b].x - l[a].x) * (p.y - l[a].y) - (l[b].y - l[a].y) * (p.x - l[a].x)) <= 0; } vector<pair<Point, Point> > find_tangent(Point a, Point b, long double r1, long double r2) { vector<pair<Point, Point> > Q; if (dist2(a, b) <= (r1 - r2) * (r1 - r2)) return Q; int f = 0; if (r2 > r1) swap(a, b), swap(r1, r2), f = 1; if (abs(r2 - r1) <= EPS) { pair<Point, Point> m = Perpendicularline(a, b, a), n = Perpendicularline(a, b, b); vector<Point> l1 = CircleLineIntersection(m.first, m.second, a, r1), l2 = CircleLineIntersection(n.first, n.second, b, r2); assert(l1.size() == 2 && l2.size() == 2); if (cross(b - a, l1[0] - b) * cross(b - a, l2[0] - b) < 0) swap(l2[0], l2[1]); Q.push_back(make_pair(l1[0], l2[0])); Q.push_back(make_pair(l1[1], l2[1])); } else { Point out = (b * r1 - a * r2) / (r1 - r2); assert(dist2(out, a) >= r1 && dist2(out, b) >= r2); vector<Point> l1 = CircleCircleIntersection( a, out, r1, sqrt(dist2(out, a) - (r1) * (r1))), l2 = CircleCircleIntersection( b, out, r2, sqrt(dist2(out, b) - (r2) * (r2))); assert(l1.size() == 2 && l2.size() == 2); if (cross(b - a, l1[0] - b) * cross(b - a, l2[0] - b) < 0) swap(l2[0], l2[1]); Q.push_back(make_pair(l1[0], l2[0])); Q.push_back(make_pair(l1[1], l2[1])); } if (dist2(a, b) > (r1 + r2) * (r1 + r2) + EPS) { Point out = (b * r1 + a * r2) / (r1 + r2); assert(dist2(out, a) >= r1 && dist2(out, b) >= r2); vector<Point> l1 = CircleCircleIntersection( a, out, r1, sqrt(dist2(out, a) - (r1) * (r1))), l2 = CircleCircleIntersection( b, out, r2, sqrt(dist2(out, b) - (r2) * (r2))); assert(l1.size() == 2 && l2.size() == 2); if (cross(b - a, l1[0] - b) * cross(b - a, l2[0] - b) > 0) swap(l2[0], l2[1]); Q.push_back(make_pair(l1[0], l2[0])); Q.push_back(make_pair(l1[1], l2[1])); } else if (abs((r1 + r2) * (r1 + r2) - dist2(a, b)) < EPS) { Point out = (b * r1 + a * r2) / (r1 + r2); Q.push_back(Perpendicularline(a, b, out)); } if (f == 1) { for (int i = 0; i < Q.size(); ++i) swap(Q[i].first, Q[i].second); } return Q; } long double error = 1e-8; Point rect; vector<pair<Point, long double> > circ; bool inpoly(vector<Point> &a, Point b) { int n = a.size(); for (int i = 0; i < a.size(); ++i) { if (DistancePointSegment(a[i], a[(i + 1) % n], b) < error) return 1; } return in_convex(a, b); } bool outcircle(Point cen, long double rad, Point a) { if (dist2(cen, a) > rad * rad - error) return 1; return 0; } Point bottom; bool cmp(Point a, Point b) { long double val = cross(a - bottom, b - a); if (fabs(val) < EPS) { return dist2(bottom, b) > dist2(bottom, a); } return val > EPS; } int myconvexhull(vector<Point> &pts) { sort(pts.begin(), pts.end()); pts.resize(unique(pts.begin(), pts.end()) - pts.begin()); bottom = pts[0]; sort(pts.begin() + 1, pts.end(), cmp); vector<Point> hull; hull.clear(); for (int i = 0; i < pts.size(); ++i) { while (hull.size() >= 2 && cross(hull[hull.size() - 2] - hull[hull.size() - 1], pts[i] - hull[hull.size() - 1]) >= -1 * EPS) { hull.pop_back(); } hull.push_back(pts[i]); } pts.clear(); for (int i = 0; i < hull.size(); ++i) { pts.push_back(hull[i]); } return 0; } vector<Point> vec; long double getslope(int a, int b) { if (abs(vec[a].x - vec[b].x) < EPS) { return INF; } long double val = vec[a].y - vec[b].y; val /= vec[a].x - vec[b].x; return val; } Point get(long double sl, int a, int b, int c) { if (abs(sl - INF) < EPS) { if (vec[b].y != vec[a].y) { return Point(vec[a].x, vec[b].y); } else { return Point(vec[a].x, vec[c].y); } } if (vec[b].x == vec[a].x) { b = c; } long double y2 = vec[a].y + sl * (vec[b].x - vec[a].x); return Point(vec[b].x, y2); } int main() { std::ios::sync_with_stdio(false); int n, i, j, k, a, b, c; long long iinf = INF; iinf *= INF; long double x, y, area = iinf; long long s; cin >> n >> s; for (int i = 0; i < n; ++i) { cin >> x >> y; vec.push_back(Point(x, y)); } myconvexhull(vec); n = vec.size(); for (int i = 0; i < n; ++i) { k = (i + 2) % n; for (j = (i + 1) % n; j != i; j = (j + 1) % n) { while (-1.0 * area2(vec[i], vec[j], vec[k]) + area2(vec[i], vec[j], vec[(k + 1) % n]) > EPS) { k = (k + 1) % n; } if (area2(vec[i], vec[j], vec[k]) - area > EPS) { area = area2(vec[i], vec[j], vec[k]); a = i; b = j; c = k; } } } long double slopeab, slopebc, slopeac; Point p1, p2, p3, ans1, ans2, ans3; slopeab = getslope(a, b); slopebc = getslope(b, c); slopeac = getslope(a, c); p1 = get(slopeab, c, a, b); p2 = get(slopebc, a, b, c); p3 = get(slopeac, b, a, c); ans1 = ComputeLineIntersection(p1, vec[c], p2, vec[a]); ans2 = ComputeLineIntersection(p1, vec[c], p3, vec[b]); ans3 = ComputeLineIntersection(p2, vec[a], p3, vec[b]); cout << setprecision(30) << round(ans1.x) << << round(ans1.y) << endl; cout << setprecision(30) << round(ans2.x) << << round(ans2.y) << endl; cout << setprecision(30) << round(ans3.x) << << round(ans3.y) << endl; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 100; long long a[N]; pair<long long, long long> ask(long long l, long long r) { cout << ? << l << << r << endl; long long first; cin >> first; if (first == -1) exit(0); long long f; cin >> f; return {first, f}; } void solve(long long l, long long r) { if (l > r) return; long long first, f; tie(first, f) = ask(l, r); long long l1 = r + 1 - f, r1 = l - 1 + f; if (l1 <= r1) { for (long long i = l1; i <= r1; i++) a[i] = first; solve(l, l1 - 1); solve(r1 + 1, r); } else { long long m = (l + r) / 2; solve(l, m); solve(m + 1, r); } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; solve(1, n); cout << ! ; for (long long i = 1; i <= n; i++) cout << a[i] << ; cout << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFRTN_PP_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:25 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: chbond_count_dec_4byte.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHBOND_COUNT_DEC_4BYTE
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: This module decodes the MGT's RXCLKCORCNT. Its
// CHANNEL_BOND_LOAD output is active when RXCLKCORCNT
// indicates the elastic buffer has executed channel
// bonding for the current RXDATA.
//
// * Supports Virtex 2 Pro
`timescale 1 ns / 10 ps
module CHBOND_COUNT_DEC_4BYTE (
RX_CLK_COR_CNT,
CHANNEL_BOND_LOAD,
USER_CLK
);
`define DLY #1
//******************************Parameter Declarations*******************************
parameter CHANNEL_BOND_LOAD_CODE = 3'b101; // Code indicating channel bond load complete
//***********************************Port Declarations*******************************
input [2:0] RX_CLK_COR_CNT;
output CHANNEL_BOND_LOAD;
input USER_CLK;
//**************************External Register Declarations****************************
reg CHANNEL_BOND_LOAD;
//*********************************Main Body of Code**********************************
always @(posedge USER_CLK)
CHANNEL_BOND_LOAD <= (RX_CLK_COR_CNT == CHANNEL_BOND_LOAD_CODE);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date: 03:22:12 07/25/2015
// Design Name: SAM Coupé clone
// Module Name: rom
// Project Name: SAM Coupé clone
// Target Devices: Spartan 6
// Tool versions: ISE 12.4
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
(* rom_extract = "yes" *)
(* rom_style = "block" *)
module rom (
input wire clk,
input wire [14:0] a,
output reg [7:0] dout
);
reg [7:0] mem[0:32767];
//reg [7:0] mem[0:16383];
initial begin
`ifdef SYNTH
$readmemh ("rom30.hex", mem);
//$readmemh ("48.hex", mem);
//$readmemh ("128k_paul_farrow.hex", mem);
//$readmemh ("test48kmcleod.hex", mem);
`else
mem[ 0] = 8'd33;
mem[ 1] = 8'd14;
mem[ 2] = 8'd0;
mem[ 3] = 8'd17;
mem[ 4] = 8'd0;
mem[ 5] = 8'd128;
mem[ 6] = 8'd1;
mem[ 7] = 8'd6;
mem[ 8] = 8'd0;
mem[ 9] = 8'd237;
mem[10] = 8'd176;
mem[11] = 8'd195;
mem[12] = 8'd0;
mem[13] = 8'd128;
mem[14] = 8'd175;
mem[15] = 8'd211;
mem[16] = 8'd254;
mem[17] = 8'd195;
mem[18] = 8'd0;
mem[19] = 8'd128;
`endif
end
always @(posedge clk)
dout <= mem[a];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO0N_PP_BLACKBOX_V
/**
* iso0n: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_PP_BLACKBOX_V
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
module VgaDriver(input clk,
output reg vga_h, output reg vga_v,
output reg [3:0] vga_r, output reg[3:0] vga_g, output reg[3:0] vga_b,
output [9:0] vga_hcounter,
output [9:0] vga_vcounter,
output [9:0] next_pixel_x, // The pixel we need NEXT cycle.
input [14:0] pixel, // Pixel for current cycle.
input sync,
input border);
// Horizontal and vertical counters
reg [9:0] h, v;
wire hpicture = (h < 512); // 512 lines of picture
wire hsync_on = (h == 512 + 23 + 35); // HSync ON, 23+35 pixels front porch
wire hsync_off = (h == 512 + 23 + 35 + 82); // Hsync off, 82 pixels sync
wire hend = (h == 681); // End of line, 682 pixels.
wire vpicture = (v < 480); // 480 lines of picture
wire vsync_on = hsync_on && (v == 480 + 10); // Vsync ON, 10 lines front porch.
wire vsync_off = hsync_on && (v == 480 + 12); // Vsync OFF, 2 lines sync signal
wire vend = (v == 523); // End of picture, 524 lines. (Should really be 525 according to NTSC spec)
wire inpicture = hpicture && vpicture;
assign vga_hcounter = h;
assign vga_vcounter = v;
wire [9:0] new_h = (hend || sync) ? 0 : h + 1;
assign next_pixel_x = {sync ? 1'b0 : hend ? !v[0] : v[0], new_h[8:0]};
always @(posedge clk) begin
h <= new_h;
if (sync) begin
vga_v <= 1;
vga_h <= 1;
v <= 0;
end else begin
vga_h <= hsync_on ? 0 : hsync_off ? 1 : vga_h;
if (hend)
v <= vend ? 0 : v + 1;
vga_v <= vsync_on ? 0 : vsync_off ? 1 : vga_v;
vga_r <= pixel[4:1];
vga_g <= pixel[9:6];
vga_b <= pixel[14:11];
if (border && (h == 0 || h == 511 || v == 0 || v == 479)) begin
vga_r <= 4'b1111;
vga_g <= 4'b1111;
vga_b <= 4'b1111;
end
if (!inpicture) begin
vga_r <= 4'b0000;
vga_g <= 4'b0000;
vga_b <= 4'b0000;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int N = 200005; int prime[1100000], primesize; bool isprime[11000000]; long long f[N], invf[N]; long long inv[N]; void getlist(int listsize) { memset(isprime, 1, sizeof(isprime)); isprime[1] = false; for (int i = 2; i <= listsize; i++) { if (isprime[i]) prime[++primesize] = i; for (int j = 1; j <= primesize && i * prime[j] <= listsize; j++) { isprime[i * prime[j]] = false; if (i % prime[j] == 0) break; } } } void extend_gcd(long long a, long long b, long long& d, long long& x, long long& y) { if (!b) { d = a; x = 1; y = 0; } else { extend_gcd(b, a % b, d, y, x); y -= x * (a / b); } } void ni(int n) { inv[0] = inv[1] = 1; for (int i = 2; i <= n; i++) { inv[i] = (mod - (mod / i)) * inv[mod % i] % mod; } } long long fpow(long long a, long long k) { long long res = 1; while (k) { if (k & 1) res = (res * a) % mod; k >>= 1; a = a * a % mod; } return res; } void init(int n) { f[0] = 1; for (int i = 1; i <= n; ++i) { f[i] = f[i - 1] * i % mod; } invf[n] = fpow(f[n], mod - 2); for (int i = n - 1; i >= 0; --i) { invf[i] = invf[i + 1] * (i + 1) % mod; } } long long C(int n, int k) { if (k < 0 || k > n) return 0; return f[n] * invf[k] % mod * invf[n - k] % mod; } long long pos[27][200005]; long long num[27]; void solve() { long long n; cin >> n; string s; cin >> s; for (int i = 0; i < s.size(); i++) { pos[s[i] - a ][0]++; pos[s[i] - a ][pos[s[i] - a ][0]] = i + 1; } long long m; cin >> m; for (int i = 1; i <= m; i++) { memset(num, 0, sizeof(num)); string x; cin >> x; long long res = 0; for (auto j : x) { num[j - a ]++; res = max(res, pos[j - a ][num[j - a ]]); } cout << res << endl; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int t = 1; while (t--) { solve(); } } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
end
end
assign do = dout[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_OSERDES
#(
.LOC("BITSLICE_RX_TX_X0Y305"),
.DATA_WIDTH(8),
.INIT(1'b0),
.IS_CLKDIV_INVERTED(1'b0),
.IS_CLK_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.SIM_DEVICE("ULTRASCALE_PLUS")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 4]),
.dout(dout[ 0 +: 2])
);
endmodule
// ---------------------------------------------------------------------
module my_OSERDES (input clk, input [3:0] din, output [1:0] dout);
parameter LOC = "";
parameter DATA_WIDTH = 1;
parameter INIT = 1'b0;
parameter IS_CLKDIV_INVERTED = 1'b0;
parameter IS_CLK_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
(* LOC=LOC *)
OSERDESE3 #(
.DATA_WIDTH(DATA_WIDTH), // Parallel data width (4,8)
.INIT(INIT), // Initialization value of the OSERDES flip-flops
.IS_CLKDIV_INVERTED(IS_CLKDIV_INVERTED),// Optional inversion for CLKDIV
.IS_CLK_INVERTED(IS_CLK_INVERTED), // Optional inversion for CLK
.IS_RST_INVERTED(IS_RST_INVERTED), // Optional inversion for RST
.SIM_DEVICE(SIM_DEVICE) // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
// ULTRASCALE_PLUS_ES2)
)
OSERDESE3_inst (
.OQ(oq), // 1-bit output: Serial Output Data
.T_OUT(t), // 1-bit output: 3-state control output to IOB
.CLK(clk), // 1-bit input: High-speed clock
.CLKDIV(din[0]), // 1-bit input: Divided Clock
.D(din[1]), // 8-bit input: Parallel Data Input
.RST(din[2]), // 1-bit input: Asynchronous Reset
.T(din[3]) // 1-bit input: Tristate input from fabric
);
OBUFT OBUFT_inst (
.O(dout[0]), // 1-bit output: Buffer output (connect directly to top-level port)
.I(oq), // 1-bit input: Buffer input
.T(t) // 1-bit input: 3-state enable input
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { long long y, z; long long x; int choice; }; node g[2000001]; int cmp(node head, node a) { if (head.y != a.y) return head.y < a.y; if (head.z != a.z) return head.z < a.z; return head.x > a.x; } struct info { int choice; long long x; } f[2000001]; int m, n; int has = 0; struct self { int x, y, z; } s[33]; long long ans; int choicex, choicey; int ipow(int i, int k) { if (k == 0) return 1; return i * ipow(i, k - 1); } int bs(long long y, long long z) { int l = 1, r = has, mid, ret = 0; while (l <= r) { mid = (l + r) >> 1; if (g[mid].y > y || (g[mid].y == y && g[mid].z >= z)) { ret = mid; r = mid - 1; } else l = mid + 1; } if (g[ret].y == y && g[ret].z == z) return ret; else return 0; } void rep(int i, int u) { if (i == 1) { int t = u % 3; if (t == 0) printf( LM n ); if (t == 1) printf( LW n ); if (t == 2) printf( MW n ); return; } rep(i - 1, u / 3); int t = u % 3; if (t == 0) printf( LM n ); if (t == 1) printf( LW n ); if (t == 2) printf( MW n ); } void p(int i, int u) { while (i <= m) { int t = u % 3; u /= 3; i++; if (t == 0) printf( LM n ); if (t == 1) printf( LW n ); if (t == 2) printf( MW n ); } } void print(int l, int r) { rep(n, l); p(n + 1, r); } int main() { ans = -1e14; scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d%d%d , &s[i].x, &s[i].y, &s[i].z); if (m % 2 == 0) n = m / 2; else n = m / 2 + 1; for (int i = 0; i < ipow(3, n); i++) { int v = i; long long x = 0, y = 0, z = 0; for (int j = n; j >= 1; j--) { int k = v % 3, li = j; long long a = x, b = y; if (k == 0) { x += s[li].x; y += s[li].y; } if (k == 1) { x += s[li].x; z += s[li].z; } if (k == 2) { y += s[li].y; z += s[li].z; } v /= 3; } y -= x; z -= x; has++; g[has].x = x; g[has].y = y; g[has].z = z; g[has].choice = i; } sort(g + 1, g + has + 1, cmp); for (int i = 0; i < ipow(3, m - n); i++) { int v = i; long long x = 0, y = 0, z = 0; for (int j = n + 1; j <= m; j++) { int k = v % 3, li = j; if (k == 0) { x += s[li].x; y += s[li].y; } if (k == 1) { x += s[li].x; z += s[li].z; } if (k == 2) { y += s[li].y; z += s[li].z; } v /= 3; } y -= x; z -= x; int pos = bs(-y, -z); if (pos != 0) if (g[pos].x + x > ans) { ans = g[pos].x + x; choicex = g[pos].choice; choicey = i; } } if (ans != -1e14) print(choicex, choicey); else printf( Impossible n ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long aabs(long long a) { if (a < 0) return -a; else return a; } struct node { long long num; int id; bool operator<(const node &a) const { return aabs(num) > aabs(a.num); } }; long long a[200005]; long long n, k, x; int main() { int i; scanf( %I64d%I64d%I64d , &n, &k, &x); int sign = 1; priority_queue<node> que; for (i = 1; i <= n; i++) { scanf( %I64d , &a[i]); if (a[i] < 0) sign = -sign; que.push((node){a[i], i}); } while (k--) { node temp = que.top(); que.pop(); if (a[temp.id] < 0) { if (sign == -1) a[temp.id] -= x; else a[temp.id] += x; if (a[temp.id] >= 0) sign = -sign; } else { if (sign == -1) a[temp.id] += x; else a[temp.id] -= x; if (a[temp.id] < 0) sign = -sign; } que.push((node){a[temp.id], temp.id}); } for (i = 1; i < n; i++) { printf( %I64d , a[i]); } printf( %I64d n , a[n]); return 0; } |
`define OP 31:26
`define RS 25:21
`define RT 20:16
`define RD 15:11
`define SHAMT 10:6
`define FUNCT 5:0
`define IMM 15:0
`define RTYPE 6'b00_0000
`define REGIMM 6'b00_0001
`define ADDU_R 6'b10_0001
`define ADD_R 6'b10_0000
`define DIVU_R 6'b01_1011
`define DIV_R 6'b01_1010
`define JR_R 6'b00_1000
`define JALR_R 6'b00_1001
`define MULTU_R 6'b01_1001
`define MULT_R 6'b01_1000
`define SLLV_R 6'b00_0100
`define SLL_R 6'b00_0000
`define SLT_R 6'b10_1010
`define SLTU_R 6'b10_1011
`define SRAV_R 6'b00_0111
`define SRA_R 6'b00_0011
`define SRLV_R 6'b00_0110
`define SRL_R 6'b00_0010
`define SUBU_R 6'b10_0011
`define SUB_R 6'b10_0010
`define AND_R 6'b10_0100
`define OR_R 6'b10_0101
`define NOR_R 6'b10_0111
`define XOR_R 6'b10_0110
`define MFHI_R 6'b01_0000
`define MFLO_R 6'b01_0010
`define MTHI_R 6'b01_0001
`define MTLO_R 6'b01_0011
`define COP0 6'b01_0000
`define MF 5'b00000
`define MT 5'b00100
`define ERET_R 6'b01_1000
`define LB 6'b10_0000
`define LBU 6'b10_0100
`define LH 6'b10_0001
`define LHU 6'b10_0101
`define LW 6'b10_0011
`define SB 6'b10_1000
`define SH 6'b10_1001
`define SW 6'b10_1011
`define ADDI 6'b00_1000
`define ADDIU 6'b00_1001
`define ANDI 6'b00_1100
`define ORI 6'b00_1101
`define XORI 6'b00_1110
`define SLTI 6'b00_1010
`define SLTIU 6'b00_1011
`define BEQ 6'b00_0100
`define BNE 6'b00_0101
`define BLEZ 6'b00_0110
`define BGTZ 6'b00_0111
`define BLTZ 5'b00000
`define BGEZ 5'b00001
`define J 6'b00_0010
`define JAL 6'b00_0011
`define LUI 6'b00_1111
`define CALC_R (add|addu|sub|subu|sll|srl|sra|sllv|srlv|srav|and_r|or_r|nor_r|xor_r|slt|sltu)
`define CALC_I (addi|addiu|lui|andi|ori|xori|slti|sltiu)
`define LOAD (lb|lbu|lh|lhu|lw)
`define STORE (sb|sh|sw)
`define ALL_BTYPE (beq|bne|blez|bgtz|bltz|bgez)
`define ALL_SUPPORT_INSTR add,addu,sub,subu,mult,multu,div,divu,ori,lb,lbu,lh,lhu,lw,sb,sh,sw,beq,bne,blez,bgtz,bltz,bgez,lui,jal,jalr,addi,slt,slti,sltiu,sltu,jr,addiu,j,sll,srl,sra,sllv,srlv,srav,andi,xori,and_r,or_r,nor_r,xor_r,mfhi,mflo,mthi,mtlo,mfc0,mtc0,eret
`ifndef CTLDEFINE_V
`define CTLDEFINE_V ctldefine
`timescale 1ns/1ns
module parse_instr (input [31:0] instr,
output `ALL_SUPPORT_INSTR);
wire rtype,regimm,cop0;
wire [5:0] OpCode;
wire [5:0] Funct;
assign OpCode=instr[`OP];
assign Funct=instr[`FUNCT];
assign rtype=(OpCode==`RTYPE);
assign add=rtype&(Funct==`ADD_R);
assign addu=rtype&(Funct==`ADDU_R);
assign sub=rtype&(Funct==`SUB_R);
assign subu=rtype&(Funct==`SUBU_R);
assign mult=rtype&(Funct==`MULT_R);
assign multu=rtype&(Funct==`MULTU_R);
assign div=rtype&(Funct==`DIV_R);
assign divu=rtype&(Funct==`DIVU_R);
assign slt=rtype&(Funct==`SLT_R);
assign sltu=rtype&(Funct==`SLTU_R);
assign sll=rtype&(Funct==`SLL_R);
assign srl=rtype&(Funct==`SRL_R);
assign sra=rtype&(Funct==`SRA_R);
assign sllv=rtype&(Funct==`SLLV_R);
assign srlv=rtype&(Funct==`SRLV_R);
assign srav=rtype&(Funct==`SRAV_R);
assign and_r=rtype&(Funct==`AND_R);
assign or_r=rtype&(Funct==`OR_R);
assign nor_r=rtype&(Funct==`NOR_R);
assign xor_r=rtype&(Funct==`XOR_R);
assign andi=(OpCode==`ANDI);
assign ori=(OpCode==`ORI);
assign lui=(OpCode==`LUI);
assign xori=(OpCode==`XORI);
assign lb=(OpCode==`LB);
assign lbu=(OpCode==`LBU);
assign lh=(OpCode==`LH);
assign lhu=(OpCode==`LHU);
assign lw=(OpCode==`LW);
assign sb=(OpCode==`SB);
assign sh=(OpCode==`SH);
assign sw=(OpCode==`SW);
assign slti=(OpCode==`SLTI);
assign sltiu=(OpCode==`SLTIU);
assign beq=(OpCode==`BEQ);
assign bne=(OpCode==`BNE);
assign blez=(OpCode==`BLEZ);
assign bgtz=(OpCode==`BGTZ);
assign regimm=(OpCode==`REGIMM);
assign bltz=regimm&(instr[`RT]==`BLTZ);
assign bgez=regimm&(instr[`RT]==`BGEZ);
assign addi=(OpCode==`ADDI);
assign addiu=(OpCode==`ADDIU);
assign j=(OpCode==`J);
assign jal=(OpCode==`JAL);
assign jr=rtype&(Funct==`JR_R);
assign jalr=rtype&(Funct==`JALR_R);
assign mtlo=rtype&(Funct==`MTLO_R);
assign mthi=rtype&(Funct==`MTHI_R);
assign mflo=rtype&(Funct==`MFLO_R);
assign mfhi=rtype&(Funct==`MFHI_R);
assign cop0=(OpCode==`COP0);
assign mtc0=cop0&(instr[`RS]==`MT);
assign mfc0=cop0&(instr[`RS]==`MF);
assign eret=cop0&(Funct==`ERET_R);
endmodule // parse_instr
module processInstr (instr,cal_r,cal_i,ld,st,brs,brt,jr_o,jal_o,muldiv,mtc0_o,mfc0_o);
input [31:0] instr;
output cal_r,cal_i,ld,st,brs,brt,jr_o,jal_o,muldiv;
output mtc0_o,mfc0_o;
wire `ALL_SUPPORT_INSTR;
parse_instr parser(instr,`ALL_SUPPORT_INSTR);
assign cal_r=`CALC_R|mult|multu|div|divu|mfhi|mflo|jalr;
assign cal_i=`CALC_I|mthi|mtlo;
assign ld=`LOAD;
assign st=`STORE;
assign brt=beq|bne;
assign brs=`ALL_BTYPE;
assign jr_o=jr|jalr;
assign jal_o=jal;
assign mtc0_o=mtc0;
assign mfc0_o=mfc0;
assign muldiv=mult|multu|div|divu|mfhi|mflo|mthi|mtlo;
endmodule // processInstr
`endif
|
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using vvi = vector<vi>; using ii = pair<int, int>; using vii = vector<ii>; using l = long long; using vl = vector<l>; using vvl = vector<vl>; using ll = pair<l, l>; using vll = vector<ll>; using vvll = vector<vll>; using lu = unsigned long long; using vb = vector<bool>; using vvb = vector<vb>; using vd = vector<double>; using vvd = vector<vd>; const int INF = numeric_limits<int>::max(); const double EPS = 1e-10; const l e5 = 100000, e6 = 1000000, e7 = 10000000, e9 = 1000000000; struct node; struct edge; using pnode = shared_ptr<node>; using graph = vector<pnode>; struct node { bool visited = false; vector<pnode> adjusted; char letter = x ; l same = 0; }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); l n, m; while (cin >> n >> m) { graph g(n); for (auto &u : g) { u = make_shared<node>(); } for (l i = 0; i < m; i++) { l a, b; cin >> a >> b; a--; b--; g[a]->adjusted.push_back(g[b]); g[b]->adjusted.push_back(g[a]); } bool ok = true; for (auto u : g) { if (u->adjusted.size() == n - 1) { u->letter = b ; u->visited = true; } } char x = a ; for (auto u : g) { if (u->visited) continue; if (x == x ) { ok = false; break; } queue<pnode> q; q.emplace(u); l marked = 0; u->visited = true; u->letter = x; marked++; while (!q.empty()) { auto v = q.front(); q.pop(); for (auto r : v->adjusted) { if (!r->visited || r->letter == v->letter) v->same++; if (r->visited) continue; r->visited = true; r->letter = x; marked++; q.emplace(r); } } for (auto v : g) { if (v->letter != x) continue; if (v->same != marked - 1) ok = false; } if (!ok) break; if (x == a ) { x = c ; } else { x = x ; } } if (ok) { cout << Yes << endl; for (auto u : g) cout << u->letter; cout << endl; } else { cout << No << endl; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_0_V
`define SKY130_FD_SC_LP__O31A_0_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_0 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_0_V
|
`timescale 1ns/1ps
module SPIFSM #(
parameter SPPRWidth = 4,
parameter SPRWidth = 4,
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// FSM control
input Start_i,
output reg Done_o,
output reg [DataWidth-1:0] Byte0_o,
output reg [DataWidth-1:0] Byte1_o,
// to/from SPI_Master
input SPI_Transmission_i,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg [DataWidth-1:0] SPI_Data_o,
input [DataWidth-1:0] SPI_Data_i,
input SPI_FIFOFull_i,
input SPI_FIFOEmpty_i,
// to ADT7310
output reg ADT7310CS_n_o,
// parameters
input [15:0] ParamCounterPreset_i
);
// SPI FSM
localparam stIdle = 4'b0000;
localparam stWriteValue = 4'b0001;
localparam stWaitSent = 4'b0010;
localparam stConsume1 = 4'b0011;
localparam stWait = 4'b0100;
localparam stWriteDummy1= 4'b0101;
localparam stWriteDummy2= 4'b0110;
localparam stRead1 = 4'b0111;
localparam stRead2 = 4'b1000;
localparam stRead3 = 4'b1001;
localparam stPause = 4'b1010;
reg [3:0] SPI_FSM_State;
reg [3:0] SPI_FSM_NextState;
wire SPI_FSM_TimerOvfl;
reg SPI_FSM_TimerPreset;
reg SPI_FSM_TimerEnable;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdle;
end
else
begin
SPI_FSM_State <= SPI_FSM_NextState;
end
end
always @(SPI_FSM_State, Start_i, SPI_Transmission_i, SPI_FSM_TimerOvfl)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
ADT7310CS_n_o = 1'b1;
SPI_Data_o = 8'bxxxxxxxx; // most time we don't care which value is set
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
Done_o = 1'b1;
// next state and output logic
case (SPI_FSM_State)
stIdle: begin
if (Start_i == 1'b1)
begin
// single-shot measurement mode: write to 8-bit configuration
// register (0x01): send 0x08 0x20 (one shot mode)
SPI_FSM_NextState = stWriteValue;
ADT7310CS_n_o = 1'b0;
SPI_Data_o = 8'h08;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
end
stWriteValue: begin
SPI_FSM_NextState = stWaitSent;
ADT7310CS_n_o = 1'b0;
// send 0x20
SPI_Data_o = 8'h20;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
stWaitSent: begin
// wait until SPI transmission has finished
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
if (SPI_Transmission_i == 1'b0)
begin
SPI_FSM_NextState = stConsume1;
SPI_ReadNext_o = 1'b1; // consume first received value
SPI_FSM_TimerPreset = 1'b1;
end
end
stConsume1: begin
SPI_FSM_NextState = stWait;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_ReadNext_o = 1'b1; // consume second received value
SPI_FSM_TimerEnable = 1'b1; // start timer
end
stWait: begin
// wait for 240ms
ADT7310CS_n_o = 1'b1;
Done_o = 1'b0;
if (SPI_FSM_TimerOvfl == 1'b0)
begin
SPI_FSM_TimerEnable = 1'b1; // timer running
end
else
begin
// timer overflow -> continue: send read command and two dummy bytes
ADT7310CS_n_o = 1'b0;
SPI_FSM_NextState = stWriteDummy1;
SPI_Data_o = 8'h50;
SPI_Write_o = 1'b1;
end
end
stWriteDummy1: begin
SPI_FSM_NextState = stWriteDummy2;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stWriteDummy2: begin
SPI_FSM_NextState = stRead1;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stRead1: begin
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead2;
// consume and ignore first byte
SPI_ReadNext_o = 1'b1;
end
end
stRead2: begin
Done_o = 1'b0;
// consume and store second byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
SPI_FSM_NextState = stRead3;
end
stRead3: begin
Done_o = 1'b0;
// consume and store third byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
SPI_FSM_NextState = stPause;
end
stPause: begin
SPI_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0_o <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1_o <= SPI_Data_i;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [15:0] SPI_FSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_Timer <= 16'd0;
end
else
begin
if (SPI_FSM_TimerPreset)
begin
SPI_FSM_Timer <= ParamCounterPreset_i;
end
else if (SPI_FSM_TimerEnable)
begin
SPI_FSM_Timer <= SPI_FSM_Timer - 1'b1;
end
end
end
assign SPI_FSM_TimerOvfl = (SPI_FSM_Timer == 0) ? 1'b1 : 1'b0;
endmodule // SPIFSM
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); struct Event { long long x, t, i; Event() {} Event(long long x, long long t, long long i) : x(x), t(t), i(i) {} }; bool cmpEvents(const Event &a, const Event &b) { return tie(a.x, a.t, a.i) < tie(b.x, b.t, b.i); } const long long MAX_N = 2e5 + 5; long long n; long long cnt[MAX_N]; pair<bool, bool> cover[MAX_N]; void solve() { cin >> n; vector<Event> sc; for (long long i = 1; i <= n; ++i) { cnt[i] = 0; cover[i] = make_pair(false, false); long long l, r; cin >> l >> r; l *= 2, r *= 2; sc.emplace_back(l, -1, i); sc.emplace_back(r, 1, i); } sort(sc.begin(), sc.end(), cmpEvents); for (long long i = 1; i < 2 * n; ++i) { sc.emplace_back((sc[i - 1].x + sc[i].x) / 2, 0, 0); } sort(sc.begin(), sc.end(), cmpEvents); set<long long> alive; long long start_ans = 2; for (long long i = 0; i < (long long)sc.size();) { long long j = i; while (j < (long long)sc.size() && sc[i].x == sc[j].x && sc[j].t == -1) { alive.emplace(sc[j].i); ++j; } while (i < j) { cover[sc[i].i].first = (long long)alive.size() > 1; ++i; } while (j < (long long)sc.size() && sc[i].x == sc[j].x && sc[j].t == 0) { if ((long long)alive.size() == 1) { cnt[*alive.begin()]++; } ++j; } if (alive.empty()) { start_ans++; } i = j; while (j < (long long)sc.size() && sc[i].x == sc[j].x && sc[j].t == 1) { cover[sc[j].i].second = (long long)alive.size() > 1; ++j; } while (i < j) { alive.erase(sc[i].i); ++i; } } long long ans = 0; for (long long i = 1; i <= n; ++i) { ans = max(ans, start_ans + cnt[i] - !cover[i].first - !cover[i].second - 1); } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long T; cin >> T; while (T--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_1_V
`define SKY130_FD_SC_MS__A41OI_1_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_1_V
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dport_axi
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input axi_awready_i
,input axi_wready_i
,input axi_bvalid_i
,input [ 1:0] axi_bresp_i
,input [ 3:0] axi_bid_i
,input axi_arready_i
,input axi_rvalid_i
,input [ 31:0] axi_rdata_i
,input [ 1:0] axi_rresp_i
,input [ 3:0] axi_rid_i
,input axi_rlast_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output axi_awvalid_o
,output [ 31:0] axi_awaddr_o
,output [ 3:0] axi_awid_o
,output [ 7:0] axi_awlen_o
,output [ 1:0] axi_awburst_o
,output axi_wvalid_o
,output [ 31:0] axi_wdata_o
,output [ 3:0] axi_wstrb_o
,output axi_wlast_o
,output axi_bready_o
,output axi_arvalid_o
,output [ 31:0] axi_araddr_o
,output [ 3:0] axi_arid_o
,output [ 7:0] axi_arlen_o
,output [ 1:0] axi_arburst_o
,output axi_rready_o
);
//-------------------------------------------------------------
// Description:
// Bridges between dcache_if -> AXI4/AXI4-Lite.
// Allows 1 outstanding transaction, but can buffer upto
// REQUEST_BUFFER dache_if requests before back-pressuring.
//-------------------------------------------------------------
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
// Output accept
wire write_complete_w;
wire read_complete_w;
reg request_pending_q;
wire req_pop_w = read_complete_w | write_complete_w;
wire req_valid_w;
wire [69-1:0] req_w;
// Push on transaction and other FIFO not full
wire req_push_w = (mem_rd_i || mem_wr_i != 4'b0) && res_accept_w;
dport_axi_fifo
#(
.WIDTH(32+32+4+1),
.DEPTH(2),
.ADDR_W(1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i({mem_rd_i, mem_wr_i, mem_data_wr_i, mem_addr_i}),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(req_pop_w)
);
assign mem_accept_o = req_accept_w & res_accept_w;
//-------------------------------------------------------------
// Response Tracking FIFO
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = (mem_rd_i || mem_wr_i != 4'b0) && req_accept_w;
dport_axi_fifo
#(
.WIDTH(11),
.DEPTH(2),
.ADDR_W(1)
)
u_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(mem_req_tag_i),
.push_i(res_push_w),
.accept_o(res_accept_w),
// Outputs
.valid_o(), // UNUSED
.data_out_o(mem_resp_tag_o),
.pop_i(mem_ack_o)
);
assign mem_ack_o = axi_bvalid_i || axi_rvalid_i;
assign mem_error_o = axi_bvalid_i ? (axi_bresp_i != 2'b0) : (axi_rresp_i != 2'b0);
wire request_in_progress_w = request_pending_q & !mem_ack_o;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
wire req_is_read_w = ((req_valid_w & !request_in_progress_w) ? req_w[68] : 1'b0);
wire req_is_write_w = ((req_valid_w & !request_in_progress_w) ? ~req_w[68] : 1'b0);
reg awvalid_inhibit_q;
reg wvalid_inhibit_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_inhibit_q <= 1'b0;
else if (axi_awvalid_o && axi_awready_i && axi_wvalid_o && !axi_wready_i)
awvalid_inhibit_q <= 1'b1;
else if (axi_wvalid_o && axi_wready_i)
awvalid_inhibit_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_inhibit_q <= 1'b0;
else if (axi_wvalid_o && axi_wready_i && axi_awvalid_o && !axi_awready_i)
wvalid_inhibit_q <= 1'b1;
else if (axi_awvalid_o && axi_awready_i)
wvalid_inhibit_q <= 1'b0;
assign axi_awvalid_o = req_is_write_w && !awvalid_inhibit_q;
assign axi_awaddr_o = {req_w[31:2], 2'b0};
assign axi_wvalid_o = req_is_write_w && !wvalid_inhibit_q;
assign axi_wdata_o = req_w[63:32];
assign axi_wstrb_o = req_w[67:64];
assign axi_awid_o = 4'd0;
assign axi_awlen_o = 8'b0;
assign axi_awburst_o = 2'b01;
assign axi_wlast_o = 1'b1;
assign axi_bready_o = 1'b1;
assign write_complete_w = (awvalid_inhibit_q || axi_awready_i) &&
(wvalid_inhibit_q || axi_wready_i) && req_is_write_w;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign axi_arvalid_o = req_is_read_w;
assign axi_araddr_o = {req_w[31:2], 2'b0};
assign axi_arid_o = 4'd0;
assign axi_arlen_o = 8'b0;
assign axi_arburst_o = 2'b01;
assign axi_rready_o = 1'b1;
assign mem_data_rd_o = axi_rdata_i;
assign read_complete_w = axi_arvalid_o && axi_arready_i;
//-------------------------------------------------------------
// Outstanding Request Tracking
//-------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
request_pending_q <= 1'b0;
else if (write_complete_w || read_complete_w)
request_pending_q <= 1'b1;
else if (mem_ack_o)
request_pending_q <= 1'b0;
endmodule
//-----------------------------------------------------------------
// dport_axi_fifo: FIFO
//-----------------------------------------------------------------
module dport_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:32:33 05/12/2015
// Design Name:
// Module Name: IF_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IF_ID(clk,rst,if_pcplus4, stall, BJ,
if_instr,id_pcplus4, id_instr,if_pc,id_pc
);
input clk,rst,stall, BJ;
input wire [31:0] if_pcplus4,if_instr,if_pc;
output reg [31:0] id_pcplus4,id_instr,id_pc;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
id_pcplus4 <= 4;
id_instr <= 32'b100000;
id_pc<=0;
end
else if(stall | BJ)
begin
id_pcplus4 <= if_pcplus4;
id_instr <= 32'b100000;
id_pc<=if_pc;
end
else
begin
id_pcplus4 <= if_pcplus4;
id_instr <= if_instr;
id_pc<=if_pc;
end
end
endmodule
//module IF_ID(clk,rst,stall,if_pcplus4, if_instr,id_pcplus4, id_instr
// );
// input clk,rst, stall;
// input wire [31:0] if_pcplus4,if_instr;
// output reg [31:0] id_pcplus4,id_instr;
//
// always @(posedge clk or posedge rst)
// begin
// if(rst)
// begin
// id_pcplus4 <= 4;
// id_instr <= 32'b100000;
// end
// else if(stall)
// begin
// id_pcplus4 <= if_pcplus4-4;
// id_instr <= 32'b100000;
// end
// else
// begin
// id_pcplus4 <= if_pcplus4;
// id_instr <= if_instr;
// end
// end
//endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> a; int gcd(int a, int b) { if (b == 0) { return a; } return gcd(b, a % b); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T; cin >> T; while (T--) { int n; cin >> n; a.clear(); a.resize(n + 1); bool can = true; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] % (i + 1) == 0) { bool updated = false; int max = (a[i] < i + 1) ? a[i] : i; for (int j = 1; j + 1 <= max; j++) { if (a[i] % (j + 1) != 0) { updated = true; break; } } if (!updated) { can = false; } } } if (can) { cout << YES n ; } else { cout << NO n ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_S_TB_V
/**
* udp_dlatch$P_pp$PKG$s: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_p_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 KAPWR = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 KAPWR = 1'b0;
#260 SLEEP_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SLEEP_B = 1'b1;
#380 KAPWR = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SLEEP_B = 1'bx;
#480 KAPWR = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$s dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_S_TB_V
|
/************************************************************************
* File Name : mod.v
* Version :
* Date :
* Description :
* Dependencies :
*
* Company : Beijing Soul Tech.
*
* Copyright (C) 2008 Beijing Soul tech.
*
***********************************************************************/
module mod(/*AUTOARG*/
// Outputs
m_src_getn, m_dst_putn, m_dst, m_dst_last, m_endn, m_cap,
// Inputs
wb_clk_i, m_reset, m_enable, dc, m_src, m_src_last,
m_src_almost_empty, m_src_empty, m_dst_almost_full, m_dst_full
);
input wb_clk_i;
input m_reset;
input m_enable;
wire wb_rst_i = m_reset;
input [23:0] dc;
output m_src_getn;
input [63:0] m_src;
input m_src_last;
input m_src_almost_empty;
input m_src_empty;
output m_dst_putn;
output [63:0] m_dst;
output m_dst_last;
input m_dst_almost_full;
input m_dst_full;
output m_endn;
output [7:0] m_cap;
// synopsys translate_off
pullup(m_dst_putn);
pullup(m_src_getn);
pullup(m_endn);
// synopsys translate_on
wire fo_full = m_dst_full || m_dst_almost_full;
wire src_empty = m_src_empty || m_src_almost_empty;
wire [15:0] en_out_data, de_out_data;
wire en_out_valid, de_out_valid;
wire en_out_done, de_out_done;
encode encode(.ce(dc[5] && m_enable),
.fi(m_src),
.clk(wb_clk_i),
.rst(wb_rst_i),
.data_o(en_out_data),
.done_o(en_out_done),
.valid_o(en_out_valid),
.m_last(m_src_last),
/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
// Inputs
.fo_full (fo_full),
.src_empty (src_empty));
decode decode(.ce(dc[6] && m_enable),
.fi(m_src),
.clk(wb_clk_i),
.rst(wb_rst_i),
.data_o(de_out_data),
.done_o(de_out_done),
.valid_o(de_out_valid),
.m_last(m_src_last),
/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
// Inputs
.fo_full (fo_full),
.src_empty (src_empty));
codeout codeout (/*AUTOINST*/
// Outputs
.m_dst (m_dst[63:0]),
.m_dst_putn (m_dst_putn),
.m_dst_last (m_dst_last),
.m_endn (m_endn),
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.dc (dc[23:0]),
.en_out_data (en_out_data[15:0]),
.de_out_data (de_out_data[15:0]),
.en_out_valid (en_out_valid),
.de_out_valid (de_out_valid),
.en_out_done (en_out_done),
.de_out_done (de_out_done),
.m_enable (m_enable));
assign m_cap = {1'b1, /* decode */
1'b1, /* encode */
1'b0, /* memcpy */
1'b0,
1'b0,
1'b0,
1'b0};
endmodule // mod
// Local Variables:
// verilog-library-directories:("." "/p/hw/lzs/encode/rtl/verilog" "/p/hw/lzs/decode/rtl/verilog/")
// verilog-library-files:("/some/path/technology.v" "/some/path/tech2.v")
// verilog-library-extensions:(".v" ".h")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
parameter N = 4;
// verilator lint_off LITENDIAN
interface a_if #(parameter PARAM = 0) ();
logic long_name;
modport source (output long_name);
modport sink (input long_name);
endinterface
module intf_source
(
input logic [0:N-1] intf_input,
a_if.source i_intf_source[0:N-1]
);
generate
for (genvar i=0; i < N;i++) begin
assign i_intf_source[i].long_name = intf_input[i];
end
endgenerate
endmodule
module intf_sink
(
output [0:N-1] a_out,
a_if.sink i_intf_sink[0:N-1]
);
generate
for (genvar i=0; i < N;i++) begin
assign a_out[i] = i_intf_sink[i].long_name;
end
endgenerate
endmodule
module t
(
clk
);
input clk;
logic [0:N-1] a_in;
logic [0:N-1] a_out;
logic [0:N-1] ack_out;
a_if #(.PARAM(1)) tl_intf [0:N-1] ();
intf_source source(a_in, tl_intf);
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
if (ack_out != a_out) begin
$stop;
end
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:15:45 06/08/2013
// Design Name:
// Module Name: Control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control(input [3:0] opcode,output [2:0]ALUControl,output RegWrite,RegDst,ALUSrc,Branch,
MemWrite,MemtoReg
);
reg [8:0] combin;
assign {RegWrite,RegDst,ALUSrc,ALUControl,Branch,MemWrite,MemtoReg} = combin ;
always @(opcode)
case(opcode)
4'b0000: combin=9'b0_0000_0000; //NOP
4'b0001: combin=9'b1_1000_1000; //ADD
4'b0010: combin=9'b1_1001_0000; //SUB
4'b0011: combin=9'b1_1001_1000; //AND
4'b0100: combin=9'b1_1001_0000; //OR
4'b0101: combin=9'b1_0110_1000; //LFT SHift
4'b0110: combin=9'b1_0111_0000; //RT Shift
4'b0111: combin=9'b1_0100_1000; //ADDI
4'b1000: combin=9'b1_0101_0000; //SUBI
4'b1001: combin=9'b1_0100_1001; //LD REG
4'b1010: combin=9'b0_0100_1010; //Store Reg
4'b1011: combin=9'b1_0100_1001; //LD I
4'b1100: combin=9'b0_0100_1010; //Store I
4'b1101: combin=9'b0_0001_0100; //Jump
default: combin=9'b0_0000_0000; //NOP
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; string b[1 << 15]; int x[100], y[100], n; map<string, int> mp; int main() { scanf( %d , &n); for (int i = 0, z; i < n; i++) { scanf( %d , &z); x[i] = z & ((1 << 15) - 1); y[i] = z >> 15; } for (int B = 0; B < (1 << 15); B++) { for (int i = 1, j = __builtin_popcount(B ^ y[0]); i < n; i++) { b[B].push_back(__builtin_popcount(B ^ y[i]) - j); } if (!mp.count(b[B])) mp[b[B]] = B; } for (int B = 0; B < 1 << 15; B++) { string tmp; for (int i = 1, j = __builtin_popcount(B ^ x[0]); i < n; i++) { tmp.push_back(j - __builtin_popcount(B ^ x[i])); } if (mp.count(tmp)) { printf( %d n , B + (mp[tmp] << 15)); return 0; } } puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; set<int> x, y; int vx[200006], vy[200006]; set<int> mx, my; set<int>::iterator it1, it2; void gao(set<int> &t1, set<int> &t2, int *v, int x) { if (!t1.count(x)) { it1 = t1.lower_bound(x); it2 = it1, it1--; int l = *it2 - *it1; v[l]--; if (v[l] == 0) t2.erase(l); t2.insert(*it2 - x), v[*it2 - x]++; t2.insert(x - *it1), v[x - *it1]++; t1.insert(x); } } int main() { int w, h, n, t, T; while (~scanf( %d%d%d , &w, &h, &n)) { memset(vx, 0, sizeof(vx)); memset(vy, 0, sizeof(vy)); char c; x.clear(), y.clear(); mx.clear(), my.clear(); x.insert(w), y.insert(h); x.insert(0), y.insert(0); mx.insert(w), my.insert(h); vx[w]++, vy[h]++; while (n--) { cin >> c >> t; if (c == V ) gao(x, mx, vx, t); else gao(y, my, vy, t); it1 = mx.end(), it2 = my.end(); it1--, it2--; long long x1 = (*it1) * 1ll, x2 = (*it2) * 1ll; long long ans = x1 * x2; cout << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int Nx = 200005; int ct[Nx], MMsize, A, B, tree[Nx * 4]; map<int, int> MM; vector<int> pos[Nx]; int query(int a, int b, int key) { if (A <= a && b <= B) return tree[key]; if (B < a || b < A) return 0; int m = (a + b) / 2; return query(a, m, key * 2) + query(m + 1, b, key * 2 + 1); } void insert(int a, int b, int key) { if (A < a || A > b) return; tree[key]++; if (a == b) return; int m = (a + b) / 2; insert(a, m, key * 2); insert(m + 1, b, key * 2 + 1); } int main() { int N; scanf( %d , &N); for (int i = 1, v, p; i <= N; i++) { scanf( %d , &v); if ((p = MM[v]) == 0) p = MM[v] = ++MMsize; pos[p].push_back(i); } for (map<int, int>::iterator i = MM.begin(); i != MM.end(); i++) { int p = i->second; for (vector<int>::iterator j = pos[p].begin(); j != pos[p].end(); j++) { int v = *j; for (int k = 1; k < N; k++) { if ((k * (v - 1) + 2) > N) break; A = k * (v - 1) + 2; B = min(N, k * v + 1); ct[k] += query(1, N, 1); } } for (vector<int>::iterator j = pos[p].begin(); j != pos[p].end(); j++) { A = *j; insert(1, N, 1); } } for (int i = 1; i < N; i++) { printf( %d , ct[i]); if (i == (N - 1)) putchar( n ); else putchar(32); } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using D = double; using uint = unsigned int; template <typename T> using pair2 = pair<T, T>; const int maxn = 300005; bool used[maxn]; int n, k; vector<int> all; int main() { cin >> n >> k; if (k == 6) { if (n < 6) printf( No n ); else { printf( Yes n ); printf( 5 n ); printf( 1 2 4 5 6 n ); } return 0; } int cur = 0; int mx = 0; for (int i = 1; i <= n && cur < k; i++) { mx = i; used[i] = true; for (int j = 1; j < i && j * j <= i; j++) if (i % j == 0) { cur++; if (i / j > j && i / j < i) cur++; } } if (cur < k) { printf( No n ); return 0; } for (int IT = 0; IT < 3; IT++) { for (int i = mx; i >= 1 && cur > k; i--) if (used[i]) { int cnt = 0; for (int j = 1; j < i && j * j <= i; j++) if (i % j == 0) { if (used[j]) cnt++; if (i / j > j && i / j < i && used[i / j]) cnt++; } for (int j = 2 * i; j <= mx; j++) if (used[j]) cnt++; if (cnt <= cur - k) { used[i] = false; cur -= cnt; } } } assert(cur == k); for (int i = 0; i <= mx; i++) if (used[i]) all.push_back(i); printf( Yes n ); printf( %d n , (int)all.size()); for (auto t : all) printf( %d , t); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long x; cin >> x; while (x--) { string str; cin >> str; long long n, b, m, v, finl, finl2; finl2 = 0; v = 0; b = 0; m = 0; v = 0; for (n = 0; n < str.size(); n++) { finl = (int)str[n] - 48; if (finl == 0) b++; else if (finl % 2 == 0) m++; finl2 = finl + finl2; } if (finl2 % 3 == 0) v = 1; if (b >= 2 && v == 1 || b >= 1 && m >= 1 && v == 1) cout << red ; else cout << cyan ; cout << endl; } return 0; } |
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module vga(clk, r, g, b, hs, vs, cs_, oe_, we_, addr, data);
input clk;
output reg r;
output reg g;
output reg b;
output reg hs;
output reg vs;
input cs_;
input oe_;
input we_;
input [11:0] addr;
inout [7:0] data;
/* See http://martin.hinner.info/vga/vga.html
The VGA signal is composed of lines and frames. The frame is:
Active video -> front porch -> sync pulse (HS#) -> back porch
The lines are:
Active video (certain number of frames) -> front porch -> sync pulse (VS#) -> back porch
Note that during sync pulses, the green output is equal to HS ^ VS, and all sync pulses are
active low.
The 640x480 mode has the following characteristics:
VRefresh 60 Hz
HRefresh 31.5 kHz
Pixel frequency 25.175 MHz
Line:
Active video 640 pixels
Front porch 16 pixels
Sync pulse 96 pixels
Back porch 48 pixels
Thus a total of 800 pixels
Frame:
Active video 480 lines
Front porch 10 lines
Sync pulse 2 lines
Back porch 33 lines
Total of 525 lines
We assume modern monitors can cope with a slightly different frequency
and use a pixel frequency of 25 MHz instead, with the same 800x525 window.
This means that each pixel is displayed for a total of 2 clock cycles at
a input frequency of 50 MHz. This gives us three states per colour i.e.
11, 10 or 01 (these will be displayed the same) and 00. With 3 colours
(RGB) we can thus output up to 27 different colours. For any more we'd need
to use a PLL to multiply our clock sufficiently.
*/
reg [10:0] counterX = 11'd0; // count up to 1600 (2 counts per pixel)
reg [9:0] counterY = 10'd0; // count up to 525
parameter Width = 640;
parameter Height = 480;
parameter LineFrontPorch = 16;
parameter LineSyncPulse = 96;
parameter LineBackPorch = 48;
parameter FrameFrontPorch = 11;
parameter FrameSyncPulse = 2;
parameter FrameBackPorch = 31;
parameter ClocksPerPixel = 2;
localparam TotalLine = (Width + LineFrontPorch + LineSyncPulse + LineBackPorch) * ClocksPerPixel;
localparam TotalFrame = Height + FrameFrontPorch + FrameSyncPulse + FrameBackPorch;
localparam LWVal = Width * ClocksPerPixel;
localparam LFPVal = (Width + LineFrontPorch) * ClocksPerPixel;
localparam LSPVal = (Width + LineFrontPorch + LineSyncPulse) * ClocksPerPixel;
localparam FFPVal = Height + FrameFrontPorch;
localparam FSPVal = Height + FrameFrontPorch + FrameSyncPulse;
wire counterXMaxed = (counterX == TotalLine);
wire counterYMaxed = (counterY == TotalFrame);
always @(posedge clk)
if(counterXMaxed)
counterX <= 11'd0;
else
counterX <= counterX + 11'd1;
always @(posedge clk)
if(counterXMaxed)
if(counterYMaxed)
counterY <= 10'd0;
else
counterY <= counterY + 10'd1;
/* We implement a simple text based frame buffer with 80 x 25 characters. For 640x480 this means
the characters are 8 pixels across and 16 characters high (we lose the last 80 lines).
The character values in the RAM framebuffer reference a font in the ROM.
We can determine the framebuffer address of a given character by xchar + ychar * 2^charsAcrossLog -
ie round up CharsAcross to a power of 2 then use bit indexes to get the appropriate value
*/
parameter CharsAcross = 80;
parameter CharsAcrossLog = 7;
parameter CharsDown = 25;
parameter CharWidth = 8;
parameter CharHeight = 16;
parameter AllCharWidth = CharsAcross * CharWidth * ClocksPerPixel;
parameter AllCharHeight = CharsDown * CharHeight;
wire [6:0] xchar = (counterX < AllCharWidth) ? counterX[10:4] : 7'h7f;
wire xcharvalid = ~&xchar;
wire [6:0] ychar = (counterY < AllCharHeight) ? { 1'b0, counterY[9:4] } : 7'h7f;
wire ycharvalid = ~&ychar;
wire charvalid = xcharvalid & ycharvalid;
wire [11:0] mem_addr = { ychar[4:0], xchar[6:0] };
// Framebuffer - side A is CPU, side B is video
wire [7:0] fbuf_out;
wire [7:0] fbuf_out_to_cpu;
assign data = (~cs_ & ~oe_) ? fbuf_out_to_cpu : 8'bzzzzzzzz;
vga_ram ram_fb(.address_a(addr), .address_b(mem_addr), .clock_a(clk), .clock_b(clk), .data_a(data), .q_a(fbuf_out_to_cpu), .q_b(fbuf_out), .wren_a(~cs_ & ~we_), .wren_b(1'b0));
// ROM contains fonts
wire [2:0] charxbit = counterX[3:1];
wire [3:0] charybit = counterY[3:0];
wire [7:0] font_out;
// change to wire [11:0] font_addr = { fbuf_out[7:0],... } to support all 256 characters (requires 4 kiB font memory)
wire [11:0] font_addr = { fbuf_out[7:0], charybit };
vga_font_rom font_rom(.clock(clk), .address(font_addr), .q(font_out));
wire font_bit = font_out[charxbit] & charvalid;
always @(posedge clk)
if(counterY < Height)
begin
if(counterX < LWVal)
{ r, g, b, hs, vs } <= { font_bit, font_bit, font_bit, 1'b1, 1'b1 };
else if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
end
else if(counterY < FFPVal)
begin
if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
end
else if(counterY < FSPVal)
begin
if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 }; // note G also high here (VS^HS)
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 };
end
else
begin
if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> a, const pair<int, int> b) { return a.second < b.second; } int main() { string s1; cin >> s1; string s2; cin >> s2; bool flag = false; string ans = 0 ; for (int i = 0; i < s1.length(); i++) { if (int(s1[i]) < int(s2[i])) flag = true; } if (s1.length() != s2.length()) flag = true; if (flag == false) { for (int i = 0; i < s1.length(); i++) { if (int(s1[i]) == int(s2[i])) ans += z ; else if (int(s1[i]) > int(s2[i])) ans += s2[i]; } } if (flag == true) cout << -1 << endl; else cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { int n; cin >> n; vector<long long> v(2 * n); for (int i = 0; i < 2 * n; i++) cin >> v[i]; sort(v.begin(), v.end()); long long ans = (v[n - 1] - v[0]) * (v[2 * n - 1] - v[n]); long long minx = 1e9 + 10; for (int i = 0; i < n; i++) { long long k = v[n + i - 1] - v[i]; minx = min(minx, k); } long long k = (v[2 * n - 1] - v[0]) * minx; cout << (long long)min(ans, k); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n; cin >> n; vector<int> v(n); int mx = 0; for (int i = 0; i < n; i++) { cin >> v[i]; mx = max(mx, v[i]); } int count = 1, l = 0; for (int i = 0; i < n; i++) { if (i && v[i] == v[i - 1] && v[i] == mx) count++; else { l = max(count, l); count = 1; } if (i == n - 1) l = max(count, l); } cout << l << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 10005; long long int p[N], s[N], n, c; long long int dp[2][N]; int main() { cin >> n >> c; for (int i = 0; i < n; i++) cin >> p[i]; for (int i = 0; i < n; i++) cin >> s[i]; dp[0][0] = p[0]; dp[0][1] = s[0]; int row = 1; for (int i = 1; i < n; i++) { for (int j = 0; j <= i + 1; j++) { dp[row][j] = (long long)(1e18); if (j != i + 1) dp[row][j] = dp[1 - row][j] + j * c + p[i]; if (j != 0) dp[row][j] = min(dp[row][j], dp[1 - row][j - 1] + s[i]); } row = 1 - row; } row = 1 - row; long long ansa = (long long)(1e18); for (int j = 0; j <= n; j++) ansa = min(ansa, dp[row][j]); cout << ansa << endl; return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; long long dyn[5001][5001]; int A[300000]; int main() { int n, k; scanf( %d , &(n)); scanf( %d , &(k)); for (int(i) = 0; (i) < n; (i)++) scanf( %d , &(A[i])); sort(A, A + n); int rem = n % k; int q = n / k; for (int i = 0; i <= k; i++) { if (i == 0) { dyn[0][0] = 0; dyn[0][1] = -1; continue; } int j = min(i, rem); for (int t = 0; t <= j; t++) { dyn[i][t] = 2000000000; if (t > 0) { dyn[i][t] = min(dyn[i][t], dyn[i - 1][t - 1] + A[i * q + t - 1] - A[(i - 1) * q + t - 1]); } if (dyn[i - 1][t] != -1) { dyn[i][t] = min(dyn[i][t], dyn[i - 1][t] + A[i * q + t - 1] - A[(i - 1) * q + t]); } } dyn[i][j + 1] = -1; } printf( %I64d , dyn[k][rem]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; const int base = 31337; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const int logo = 20; const int off = 1 << logo; const int treesiz = off << 1; int n; char niz[maxn]; int his[maxn]; int main() { scanf( %d%s , &n, niz); long long sol = 0; long long tren = 0; memset(his, -1, sizeof his); for (int i = 0; i < n; i++) { if (niz[i] == 0 ) sol += tren; else { int ptr = i; while (ptr + 1 < n && niz[ptr + 1] == 1 ) ptr++; int cnt = 1; for (int j = i; j <= ptr; j++) { tren += j - his[cnt]; his[cnt] = ptr - cnt + 1; sol += tren; cnt++; } i = ptr; } } printf( %lld n , sol); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; int n, k, sz, trie[MAX][26]; bool win[MAX], lose[MAX]; char s[MAX]; void dfs(int u) { int ady = 0; for (int i = 0; i < 26; i++) { if (trie[u][i] == 0) continue; ady++; int v = trie[u][i]; dfs(v); win[u] |= !win[v]; lose[u] |= !lose[v]; } if (ady == 0) { win[u] = 0; lose[u] = 1; } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %s , s); int l = strlen(s); int r = 0; for (int i = 0; i < l; i++) { int c = s[i] - a ; if (trie[r][c] == 0) trie[r][c] = ++sz; r = trie[r][c]; } } dfs(0); if (win[0] && lose[0]) printf( First n ); else if (win[0] && !lose[0]) { if (k & 1) printf( First n ); else printf( Second n ); } else if (!win[0] && lose[0]) printf( Second n ); else printf( Second n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 300001; int f[maxn], a[maxn]; inline void add(int x, int val) { for (int i = x + 1; i < maxn; i += i & (-i)) f[i] += val; } inline int get(int x) { int ans = 0; for (int i = x; i > 0; i -= i & (-i)) ans += f[i]; return ans; } inline int sum(int x, int y) { return get(y) - get(x); } int main() { int q, l, r, n, m, rev = 0; scanf( %d%d , &n, &m); int cr = n - 1, cl = 0; int len = cr - cl + 1; for (int i = 0; i < n; ++i) add(i, a[i] = 1); for (int t = 0; t < m; ++t) { scanf( %d , &q); if (q == 1) { scanf( %d , &l); if (l > len - l) rev ^= 1, l = len - l; if (rev) { cr = cr - l; for (int i = cr; i >= cr - l + 1; --i) add(i, a[2 * cr - i + 1]), a[i] += a[2 * cr - i + 1]; } else { cl = cl + l; for (int i = cl; i <= cl + l - 1; ++i) add(i, a[2 * cl - i - 1]), a[i] += a[2 * cl - i - 1]; } len = cr - cl + 1; } if (q == 2) { scanf( %d%d , &l, &r); int ln = (r - l); if (rev) l = cr - l + 1, r = l - ln, swap(l, r); else l += cl, r += cl; printf( %d n , sum(l, r)); } } } |
#include <bits/stdc++.h> using namespace std; int main() { string str; getline(cin, str); str.erase(remove(str.begin(), str.end(), ), str.end()); int n = str.size(); if (str[n - 2] == a || str[n - 2] == e || str[n - 2] == i || str[n - 2] == o || str[n - 2] == u || str[n - 2] == y || str[n - 2] == A || str[n - 2] == E || str[n - 2] == I || str[n - 2] == O || str[n - 2] == U || str[n - 2] == Y ) { cout << YES ; } else { cout << NO ; } } |
#include <bits/stdc++.h> long long MOD = 1e9 + 7; using namespace std; int in() { int x; scanf( %d , &x); return x; } long long lin() { long long x; scanf( %lld , &x); return x; } template <typename A, size_t NNN, typename T> void Fill(A (&array)[NNN], const T &val) { fill((T *)array, (T *)(array + NNN), val); } struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; struct pair_hash { template <class T1, class T2> size_t operator()(const pair<T1, T2> &p) const { return hash<T1>()(p.first) ^ hash<T2>()(p.second); } }; vector<pair<long long, long long> > G[400001]; long long ans[400001], w[400001]; long long s; long long dfs(int t, int p) { long long temp1 = w[t], temp2 = 0; for (int i = 0; i < G[t].size(); i++) { if (G[t][i].first == p) continue; temp2 = max(temp2, dfs(G[t][i].first, t) + w[t] - G[t][i].second); if (temp2 > temp1) swap(temp1, temp2); } s = max(s, temp1 + temp2 - w[t]); return temp1; } int main() { long long n = lin(); for (long long i = 1; i <= n; ++i) w[i] = lin(); for (long long i = 1; i <= n; ++i) { ans[i] = w[i]; } for (int i = 0; i < n - 1; i++) { long long u = lin(), v = lin(), c = lin(); G[u].push_back({v, c}); G[v].push_back({u, c}); } s = max(s, dfs(1, 0)); for (long long i = 1; i <= n; ++i) s = max(s, w[i]); cout << s; } |
#include <bits/stdc++.h> template <typename T> void MACRO_VAR_Scan(T& t) { std::cin >> t; } template <typename First, typename... Rest> void MACRO_VAR_Scan(First& first, Rest&... rest) { std::cin >> first; MACRO_VAR_Scan(rest...); } template <typename T> void MACRO_VEC_ROW_Init(int n, T& t) { t.resize(n); } template <typename First, typename... Rest> void MACRO_VEC_ROW_Init(int n, First& first, Rest&... rest) { first.resize(n); MACRO_VEC_ROW_Init(n, rest...); } template <typename T> void MACRO_VEC_ROW_Scan(int p, T& t) { std::cin >> t[p]; } template <typename First, typename... Rest> void MACRO_VEC_ROW_Scan(int p, First& first, Rest&... rest) { std::cin >> first[p]; MACRO_VEC_ROW_Scan(p, rest...); } template <class T> inline T CHMAX(T& a, const T b) { return a = (a < b) ? b : a; } template <class T> inline T CHMIN(T& a, const T b) { return a = (a > b) ? b : a; } template <class T> using V = std::vector<T>; template <class T> using VV = V<V<T>>; template <typename S, typename T> std::ostream& operator<<(std::ostream& os, std::pair<S, T> p) { os << ( << p.first << , << p.second << ) ; return os; } using ll = long long; using ull = unsigned long long; using ld = long double; using PAIR = std::pair<ll, ll>; using PAIRLL = std::pair<ll, ll>; constexpr ll INFINT = 1 << 30; constexpr ll INFINT_LIM = (1LL << 31) - 1; constexpr ll INFLL = 1LL << 60; constexpr ll INFLL_LIM = (1LL << 62) - 1 + (1LL << 62); constexpr double EPS = 1e-6; constexpr ll MOD = 1000000007; constexpr double PI = 3.141592653589793238462643383279; template <class T, size_t N> void FILL(T (&a)[N], const T& val) { for (auto& x : a) x = val; } template <class ARY, size_t N, size_t M, class T> void FILL(ARY (&a)[N][M], const T& val) { for (auto& b : a) FILL(b, val); } template <class T> void FILL(std::vector<T>& a, const T& val) { for (auto& x : a) x = val; } template <class ARY, class T> void FILL(std::vector<std::vector<ARY>>& a, const T& val) { for (auto& b : a) FILL(b, val); } struct Trie { std::vector<std::vector<ll>> g; ll p; Trie() : p(0) { g.emplace_back(std::vector<ll>(2, -1)); ++p; } void add(const std::string& s) { size_t par = 0; for (size_t i = 0; i < s.size(); ++i) { ll t = s[i] - 0 ; if (g[par][t] == -1) { g.emplace_back(std::vector<ll>(2, -1)); g[par][t] = p++; } par = g[par][t]; } } ll next(size_t par, char c) { ll t = c - 0 ; return g[par][t]; } }; bool ng(std::string s) { return s == 1100 || s == 1010 || s == 0111 || s == 1111 ; } signed main() { std::ios::sync_with_stdio(false); std::cin.tie(0); ; ll n; MACRO_VAR_Scan(n); ; std::string s; for (ll i = 0; i < ll(n); ++i) { char c; MACRO_VAR_Scan(c); ; s += c; } Trie tr; std::vector<ll> c(n, 0); for (ll i = 0; i < ll(n); ++i) { auto S = s.substr(0, i + 1); std::reverse((S).begin(), (S).end()); std::vector<ll> dp(S.size() + 1, 0); dp[0] = 1; for (ll j = 0; j < ll(S.size()); ++j) { for (ll k = 0; k < ll(4); ++k) { if (j < k) break; if (k == 3) { if (ng(S.substr(j - 3, 4))) continue; } (dp[j + 1] += dp[j - k]) %= MOD; } } ll p = 0; ll len = 0; for (ll j = 0; j < ll(S.size()); ++j) { ll ne = tr.next(p, S[j]); if (ne == -1) break; p = ne; dp[++len] = 0; } tr.add(S); for (ll j = (1); j < (S.size() + 1); ++j) { (c[i] += dp[j]) %= MOD; } } for (ll i = 0; i < ll(n - 1); ++i) (c[i + 1] += c[i]) %= MOD; for (ll i = 0; i < ll(n); ++i) { std::cout << (c[i]); std::cout << n ; ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); ; } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } int fx[] = {0, 0, +1, -1}; int fy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long &a) { a %= 998244353; (a < 0) && (a += 998244353); } inline long long modMul(long long a, long long b) { a %= 998244353, b %= 998244353; normal(a), normal(b); return (a * b) % 998244353; } inline long long modAdd(long long a, long long b) { a %= 998244353, b %= 998244353; normal(a), normal(b); return (a + b) % 998244353; } inline long long modSub(long long a, long long b) { a %= 998244353, b %= 998244353; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { return modPow(a, 998244353 - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } inline bool isInside(pair<int, int> p, long long n, long long m) { return (p.first >= 0 && p.first < n && p.second >= 0 && p.second < m); } inline bool isInside(pair<int, int> p, long long n) { return (p.first >= 0 && p.first < n && p.second >= 0 && p.second < n); } inline bool isSquare(long long x) { long long s = sqrt(x); return (s * s == x); } inline bool isFib(long long x) { return isSquare(5 * x * x + 4) || isSquare(5 * x * x - 4); } inline bool isPowerOfTwo(long long x) { return ((1LL << (long long)log2(x)) == x); } struct func { bool operator()(pair<int, int> const &a, pair<int, int> const &b) { if (a.first == b.first) return (a.second < b.second); return (a.first < b.first); } }; long long corner(long long n, long long i) { return (((n - i - 1ll) >= 0) ? modMul(180ll, modPow(10ll, n - i - 1ll)) : 0); } long long middle(long long n, long long i) { return (((n - i - 2) >= 0) ? modMul(n - i - 1, modMul(810ll, modPow(10ll, n - i - 2))) : 0); } long long getResult(long long n, long long i) { if (i == n) return 10; return modAdd(corner(n, i), middle(n, i)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; for (int i = 1; i <= n; ++i) { cout << getResult(n, i) << ; } cout << n ; return 0; } |
module quad(clk, reset, quadA, quadB, count);
parameter SCREENHEIGHT=0;
parameter PADDLESIZE = 0;
input clk, reset, quadA, quadB;
output [9:0] count;
reg [2:0] quadA_delayed, quadB_delayed;
always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};
always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};
wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];
reg [5:0] accelcount;
reg [9:0] count;
wire [3:0] ac = (accelcount == 0) ? 1 : 5;
always @(posedge clk or posedge reset)
begin
if (reset) begin
count <= SCREENHEIGHT/2;
end
else begin
if(count_enable)
begin
count <= paddlelimiter(count_direction ? count + ac : count - ac);
accelcount <= -1;
end
if (accelcount != 0) accelcount <= accelcount - 1;
end
end
function [9:0] paddlelimiter;
input [9:0] py;
begin
if (py < PADDLESIZE/2)
paddlelimiter = PADDLESIZE/2;
else
if (py > SCREENHEIGHT-PADDLESIZE/2)
paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
else
paddlelimiter = py;
end
endfunction
endmodule |
#include <bits/stdc++.h> using namespace std; int i, j, k, l; int n, m, d, a[100010][4]; int ms[11111]; double cx, cy, ccx, ccy; int x1, stupid_cmath, x2, y2; int main() { cin >> n; for (i = 0; i < n; ++i) { cin >> x1 >> stupid_cmath >> x2 >> y2; a[i][0] = ((x1) < (x2) ? (x1) : (x2)); a[i][1] = ((stupid_cmath) < (y2) ? (stupid_cmath) : (y2)); a[i][2] = ((x1) > (x2) ? (x1) : (x2)); a[i][3] = ((stupid_cmath) > (y2) ? (stupid_cmath) : (y2)); ms[i] = (a[i][2] - a[i][0]) * (a[i][2] - a[i][0]) * (a[i][2] - a[i][0]); } for (i = 0; i < n; ++i) { for (j = i - 1; j >= 0; --j) { cx = cy = 0; m = 0; for (k = j + 1; k <= i; ++k) { cx += (a[k][0] + a[k][2]) / 2. * ms[k]; cy += (a[k][1] + a[k][3]) / 2. * ms[k]; m += ms[k]; } cx /= m; cy /= m; if (cx < a[j][0] || cx > a[j][2] || cy < a[j][1] || cy > a[j][3]) { cout << i << endl; return 0; } } } cout << n; return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_mult_cell (
// inputs:
M_mul_src1,
M_mul_src2,
clk,
reset_n,
// outputs:
M_mul_cell_result
)
;
output [ 31: 0] M_mul_cell_result;
input [ 31: 0] M_mul_src1;
input [ 31: 0] M_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_result;
wire [ 31: 0] M_mul_cell_result_part_1;
wire [ 15: 0] M_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altmult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[15 : 0]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.intended_device_family = "CYCLONEII",
the_altmult_add_part_1.lpm_type = "altmult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altmult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[31 : 16]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.intended_device_family = "CYCLONEII",
the_altmult_add_part_2.lpm_type = "altmult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign M_mul_cell_result = {M_mul_cell_result_part_1[31 : 16] +
M_mul_cell_result_part_2,
M_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void chkmin(T &x, T y) { x = min(x, y); } template <typename T> inline void chkmax(T &x, T y) { x = max(x, y); } template <typename T> inline void read(T &x) { T f = 1; x = 0; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + c - 0 ; x *= f; } int main() { int q; read(q); while (q--) { long long l, r; read(l); read(r); long long ans = (l + r) * (r - l + 1) / 2; if (!(r & 1)) --r; if (!(l & 1)) ++l; if (l > r) cout << ans << n ; else cout << ans - (l + r) * ((r - l) / 2 + 1) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll mod = 1e9 + 7; const int maxn = 1e5 + 5, maxa = 71, lim = 1 << 19; ll ev[maxn], od[maxn], dp[2][lim]; int n, a, f[lim], comp[maxa]; vector<int> p; int calc_msk(int x) { int msk = 0, b = 1; for (int y : p) { while (x % (y * y) == 0) x /= y * y; msk = (x % y == 0) * b + msk; b *= 2; } return msk; } int main() { ios_base::sync_with_stdio(0); for (int i = (2); i < (maxa); i++) for (int j = i + i; j < maxa; j += i) comp[j] = 1; for (int i = (2); i < (maxa); i++) if (!comp[i]) p.push_back(i); ev[0] = ev[1] = 1; for (int i = (2); i < (maxn); i++) ev[i] = ev[i - 1] * 2 % mod; od[0] = 0; od[1] = 1; for (int i = (2); i < (maxn); i++) od[i] = od[i - 1] * 2 % mod; cin >> n; for (int i = (0); i < (n); i++) { cin >> a; f[calc_msk(a)]++; } dp[0][0] = 1; for (int i = (1); i < (maxa); i++) { int x = calc_msk(i); for (int msk = (0); msk < (lim); msk++) dp[i & 1][msk] = (dp[i & 1 ^ 1][msk] * ev[f[x]] + dp[i & 1 ^ 1][msk ^ x] * od[f[x]]) % mod; f[x] = 0; } cout << (dp[maxa & 1 ^ 1][0] + mod - 1) % mod << n ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 20:32:40 05/17/2016
// Design Name:
// Module Name: picture_timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module generador_imagenes
(
input clk,
input reset,
input wire video_on,//señal que indica que se encuentra en la región visible de resolución 640x480
input wire [9:0] pixel_x, pixel_y,
output wire pic_on,
output wire [7:0] pic_RGB
);
//Declaración de constantes
localparam pic_hora_XL = 256; //Límite izquierdo
localparam pic_hora_XR = 384; //Límite derecho
localparam pic_hora_YB = 64; //Límite inferior
localparam pic_hora_size = 8192;// (128x64)
localparam pic_timer_XL = 416; //Límite izquierdo
localparam pic_timer_XR = 496; //Límite derecho
localparam pic_timer_YT = 416; //Límite superior
localparam pic_timer_YB = 479; //Límite inferior
localparam pic_timer_size = 2560;// (80x32)
localparam pic_ring_XL = 512; //Límite izquierdo
localparam pic_ring_XR = 639; //Límite derecho
localparam pic_ring_YT = 128; //Límite superior
localparam pic_ring_YB = 191; //Límite inferior
localparam pic_ring_size = 8192;// (128x64)
localparam pic_ringball_XL = 544; //Límite izquierdo
localparam pic_ringball_XR = 592; //Límite derecho
localparam pic_ringball_YT = 64; //Límite superior
localparam pic_ringball_YB = 112; //Límite inferior
localparam pic_ringball_size = 2304;// (48x48)
localparam pic_logo_XR = 128; //Límite derecho
localparam pic_logo_YB = 16; //Límite inferior
localparam pic_logo_size = 2048;// (128x16)
//Declaración de señales
reg [7:0] pic_RGB_aux;
reg [7:0] colour_data_hora [0:pic_hora_size-1]; //datos de los colores
reg [7:0] colour_data_timer [0:pic_timer_size-1]; //datos de los colores
reg [7:0] colour_data_ring [0:pic_ring_size-1]; //datos de los colores
reg [7:0] colour_data_ringball [0:pic_ringball_size-1]; //datos de los colores
reg [7:0] colour_data_logo [0:pic_logo_size-1]; //datos de los colores
wire pic_hora_on, pic_timer_on, pic_ring_on, pic_ringball_on, pic_logo_on;
reg [12:0] index_counter_hora_reg, index_counter_hora_next;
wire [12:0] index_counter_hora;
reg [11:0] index_counter_timer_reg, index_counter_timer_next;
wire [11:0] index_counter_timer;
reg [12:0] index_counter_ring_reg, index_counter_ring_next;
wire [12:0] index_counter_ring;
reg [11:0] index_counter_ringball_reg, index_counter_ringball_next;
wire [11:0] index_counter_ringball;
reg [10:0] index_counter_logo_reg, index_counter_logo_next;
wire [10:0] index_counter_logo;
//Contadores para recorrer la memoria
always @(posedge clk)//Todos los contadores tienen la misma lógica de asignación de estados
begin
if(reset)
begin
index_counter_hora_reg <= 0;
index_counter_timer_reg <= 0;
index_counter_ring_reg <= 0;
index_counter_ringball_reg <= 0;
index_counter_logo_reg <= 0;
end
else
begin
index_counter_hora_reg <= index_counter_hora_next;
index_counter_timer_reg <= index_counter_timer_next;
index_counter_ring_reg <= index_counter_ring_next;
index_counter_ringball_reg <= index_counter_ringball_next;
index_counter_logo_reg <= index_counter_logo_next;
end
end
//===================================================
// Imagen HORA
//===================================================
initial
$readmemh ("hora.list", colour_data_hora);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_hora_on = (pic_hora_XL<=pixel_x)&&(pixel_x<=pic_hora_XR)&&(pixel_y<=pic_hora_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_hora_on)
begin
index_counter_hora_next = index_counter_hora_reg + 1'b1;
end
else
begin
index_counter_hora_next = 0;
end
end
assign index_counter_hora = index_counter_hora_reg;
//===================================================
// Imagen TIMER
//===================================================
initial
$readmemh ("timer.list", colour_data_timer);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_timer_on = (pic_timer_XL<=pixel_x)&&(pixel_x<=pic_timer_XR)&&(pic_timer_YT<=pixel_y)&&(pixel_y<=pic_timer_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_timer_on)
begin
index_counter_timer_next = index_counter_timer_reg + 1'b1;
end
else
begin
index_counter_timer_next = 0;
end
end
assign index_counter_timer = index_counter_timer_reg;
//===================================================
// Imagen RING
//===================================================
initial
$readmemh ("ring.list", colour_data_ring);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_ring_on = (pic_ring_XL<=pixel_x)&&(pixel_x<=pic_ring_XR)&&(pic_ring_YT<=pixel_y)&&(pixel_y<=pic_ring_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_ring_on)
begin
index_counter_ring_next = index_counter_ring_reg + 1'b1;
end
else
begin
index_counter_ring_next = 0;
end
end
assign index_counter_ring = index_counter_ring_reg;
//===================================================
// Imagen RING BALL
//===================================================
initial
$readmemh ("ring_ball.list", colour_data_ringball);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_ringball_on = (pic_ringball_XL<=pixel_x)&&(pixel_x<=pic_ringball_XR)&&(pic_ringball_YT<=pixel_y)&&(pixel_y<=pic_ringball_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_ringball_on)
begin
index_counter_ringball_next = index_counter_ringball_reg + 1'b1;
end
else
begin
index_counter_ringball_next = 0;
end
end
assign index_counter_ringball = index_counter_ringball_reg;
//===================================================
// Imagen LOGO
//===================================================
initial
$readmemh ("logo.list", colour_data_logo);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_logo_on = (pixel_x<=pic_logo_XR)&&(pixel_y<=pic_logo_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_logo_on)
begin
index_counter_logo_next = index_counter_logo_reg + 1'b1;
end
else
begin
index_counter_logo_next = 0;
end
end
assign index_counter_logo = index_counter_logo_reg;
//------------------------------------------------------------------------------------------------------------------------
//Multiplexa el RGB
always @*
begin
if(~video_on)
pic_RGB_aux = 12'b0;//fondo negro
else
if(pic_hora_on) pic_RGB_aux = colour_data_hora[index_counter_hora];
else if (pic_timer_on) pic_RGB_aux = colour_data_timer[index_counter_timer];
else if (pic_ring_on) pic_RGB_aux = colour_data_ring[index_counter_ring];
else if (pic_ringball_on) pic_RGB_aux = colour_data_ringball[index_counter_ringball];
else if (pic_logo_on) pic_RGB_aux = colour_data_logo[index_counter_logo];
else pic_RGB_aux = 12'b0;//fondo negro
end
//assign pic_RGB = {pic_RGB_aux[7:5],1'b0,pic_RGB_aux[4:2],1'b0,pic_RGB_aux[1:0],2'b0}; //Rellena pic_RGB para pasar de 8 bits a 12 bits
assign pic_RGB = pic_RGB_aux;//Para 8 bits (Nexys 3)
assign pic_on = pic_hora_on | pic_timer_on| pic_ring_on| pic_ringball_on| pic_logo_on;
endmodule
|
Require Import Iron.Language.SystemF2.Preservation.
Require Export Iron.Language.SystemF2.Step.
Require Export Iron.Language.SystemF2.SubstExpExp.
Require Export Iron.Language.SystemF2.SubstTypeExp.
Require Import Iron.Language.SystemF2.TyJudge.
Require Export Iron.Language.SystemF2.Exp.
(* Big Step Evaluation.
This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value. *)
Inductive EVAL : exp -> exp -> Prop :=
| EVDone
: forall v2
, wnfX v2
-> EVAL v2 v2
| EVLAMAPP
: forall x1 x12 t2 v3
, EVAL x1 (XLAM x12) -> EVAL (substTX 0 t2 x12) v3
-> EVAL (XAPP x1 t2) v3
| EVLamApp
: forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12) -> EVAL x2 v2 -> EVAL (substXX 0 v2 x12) v3
-> EVAL (XApp x1 x2) v3.
Hint Constructors EVAL.
(* A terminating big-step evaluation always produces a wnf.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma. *)
Lemma eval_produces_wnfX
: forall x1 v1
, EVAL x1 v1
-> wnfX v1.
Proof.
intros. induction H; eauto.
Qed.
Hint Resolve eval_produces_wnfX.
(* Big to Small steps
Convert a big-step evaluation into a list of individual
machine steps. *)
Lemma steps_of_eval
: forall x1 t1 x2
, TYPE nil nil x1 t1
-> EVAL x1 x2
-> STEPS x1 x2.
Proof.
intros x1 t1 v2 HT HE. gen t1.
(* Induction over the form of (EVAL x1 x2) *)
induction HE.
Case "EVDone".
intros. apply ESNone.
Case "EVLAMAPP".
intros. inverts HT.
lets E1: IHHE1 H3. clear IHHE1.
lets T1: preservation_steps H3 E1. inverts keep T1.
lets T2: subst_type_exp H4 H5.
simpl in T2.
lets E2: IHHE2 T2.
eapply ESAppend.
apply steps_APP1. eauto.
eapply ESAppend.
eapply ESStep.
eapply ESLAMAPP. auto.
Case "EVLamApp".
intros. inverts HT.
lets E1: IHHE1 H3.
lets E2: IHHE2 H5.
lets T1: preservation_steps H3 E1. inverts keep T1.
lets T2: preservation_steps H5 E2.
lets T3: subst_exp_exp H8 T2.
lets E3: IHHE3 T3.
eapply ESAppend.
eapply steps_app1. eauto.
eapply ESAppend.
eapply steps_app2. eauto. eauto.
eapply ESAppend.
eapply ESStep.
eapply ESLamApp. eauto.
eauto.
Qed.
(* Small to Big steps
Convert a list of individual machine steps to a big-step
evaluation. The main part of this is the expansion lemma, which
we use to build up the overall big-step evaluation one small-step
at a time. The other lemmas are used to feed it small-steps.
*)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall ke te x1 t1 x2 v3
, TYPE ke te x1 t1
-> STEP x1 x2 -> EVAL x2 v3
-> EVAL x1 v3.
Proof.
intros. gen ke te t1 v3.
(* Induction over the form of (STEP x1 x2) *)
induction H0; intros.
Case "XApp".
SCase "value app".
eapply EVLamApp.
eauto.
apply EVDone. auto. auto.
SCase "x1 steps".
inverts H. inverts H1.
inverts H.
eapply EVLamApp; eauto.
SCase "x2 steps".
inverts H1. inverts H2.
inverts H1.
eapply EVLamApp; eauto.
Case "XAPP".
SCase "type app".
eapply EVLAMAPP.
eauto.
inverts H.
auto.
SCase "x1 steps".
inverts H. inverts H1.
inverts H.
eapply EVLAMAPP; eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall x1 t1 v2
, TYPE nil nil x1 t1
-> STEPSL x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
induction H0; eauto using eval_expansion.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps.
*)
Lemma eval_of_steps
: forall x1 t1 v2
, TYPE nil nil x1 t1
-> STEPS x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
eauto using eval_of_stepsl, stepsl_of_steps.
Qed.
|
#include <bits/stdc++.h> using namespace std; char x; int n; int main() { cin >> n; cin >> x; cout << x; cin >> x; cout << x; n -= 2; if (n % 2 == 1) { cin >> x; cout << x; n--; } for (int i = 1; i <= n; i++) { if (i % 2 == 1) cout << - ; cin >> x; cout << x; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long t, m, n, a, u, v; void printAnswer(vector<int> ans) { sort(ans.begin(), ans.end()); cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) { cout << ans[i] << ; } cout << endl; } int main() { cin >> t; for (int j = 0; j < t; j++) { cin >> n >> m; vector<vector<int> > G(n + 1); for (int i = 0; i < m; i++) { cin >> v >> u; G[v].push_back(u); G[u].push_back(v); } vector<int> odd; vector<int> even; bool seen[n + 1]; for (int i = 0; i <= n; i++) { seen[i] = false; } bool oddLevel = true; vector<int> currLevel; currLevel.push_back(1); seen[1] = true; while (currLevel.size() > 0) { if (oddLevel) { odd.insert(odd.end(), currLevel.begin(), currLevel.end()); } else { even.insert(even.end(), currLevel.begin(), currLevel.end()); } vector<int> nextLevel; for (int i = 0; i < currLevel.size(); i++) { int n = currLevel[i]; for (int k = 0; k < G[n].size(); k++) { if (!seen[G[n][k]]) { seen[G[n][k]] = true; nextLevel.push_back(G[n][k]); } } } currLevel = nextLevel; oddLevel = !oddLevel; } if (odd.size() >= even.size()) { printAnswer(even); } else { printAnswer(odd); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1234567; int n, a, b, T, used, ans; int lft[N], rgt[N]; char s[N]; void fill_array(int v[]) { for (int i = 1; i < n; i++) { v[i] = v[i - 1] + a + 1 + ((s[i] == w ) ? b : 0); } } void solve(int lft[], int rgt[]) { for (int i = 1; i < n; i++) { int need = used + lft[i]; if (need <= T) { ans = max(ans, i + 1); } need += (i * a); if (need > T) { continue; } if (rgt[n - i - 1] + need <= T) { ans = n; break; } int pos = upper_bound(rgt, rgt + n, T - need) - rgt; ans = max(ans, i + 1 + pos - 1); } } int main() { scanf( %d %d %d %d , &n, &a, &b, &T); scanf( %s , s); fill_array(lft); reverse(s + 1, s + n); fill_array(rgt); reverse(s + 1, s + n); used = 1; if (s[0] == w ) { used += b; } if (used > T) { puts( 0 ); return 0; } ans = 1; solve(lft, rgt); solve(rgt, lft); cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
//this code was generated by cReComp
module motor_ctl(
input clk,
input rst_32,
input [31:0] din_32,
input [0:0] wr_en_32,
input [0:0] rd_en_32,
output [31:0] dout_32,
output [0:0] full_32,
output [0:0] empty_32,
output dir_out_r,
output dir_out_l,
output en_out_r,
output en_out_l
);
// //copy this instance to top module
//motor_ctl motor_ctl
//(
//.clk(bus_clk),
//.rst_32(!user_w_write_32_open && !user_r_read_32_open),
//.din_32(user_w_write_32_data),
//.wr_en_32(user_w_write_32_wren),
//.rd_en_32(user_r_read_32_rden),
//.dout_32(user_r_read_32_data),
//.full_32(user_w_write_32_full),
//.empty_32(user_r_read_32_empty),
//
// .dir_out_r(dir_out_r),
// .dir_out_l(dir_out_l),
// .en_out_r(en_out_r),
// .en_out_l(en_out_l)
//);
parameter INIT_32 = 0,
READY_RCV_32 = 1,
RCV_DATA_32 = 2,
POSE_32 = 3,
READY_SND_32 = 4,
SND_DATA_32 = 5;
// for input fifo
wire [31:0] rcv_data_32;
wire rcv_en_32;
wire data_empty_32;
// for output fifo
wire [31:0] snd_data_32;
wire snd_en_32;
wire data_full_32;
// state register
reg [3:0] state_32;
//fifo 32bit
fifo_32x512 input_fifo_32(
.clk(clk),
.srst(rst_32),
.din(din_32),
.wr_en(wr_en_32),
.full(full_32),
.dout(rcv_data_32),
.rd_en(rcv_en_32),
.empty(data_empty_32)
);
fifo_32x512 output_fifo_32(
.clk(clk),
.srst(rst_32),
.din(snd_data_32),
.wr_en(snd_en_32),
.full(data_full_32),
.dout(dout_32),
.rd_en(rd_en_32),
.empty(empty_32)
);
//for 32bit FIFO;
reg dir_right;
reg [14:0] para_right;
reg dir_left;
reg [14:0] para_left;
//instance for pwm_ctl
pwm_ctl right
(
.clk(clk),
.rst(rst_32),
.para_in(para_right),
.dir_in(dir_right),
.dir_out(dir_out_r),
.en_out(en_out_r)
);
//instance for pwm_ctl
pwm_ctl left
(
.clk(clk),
.rst(rst_32),
.para_in(para_left),
.dir_in(dir_left),
.dir_out(dir_out_l),
.en_out(en_out_l)
);
always @(posedge clk)begin
if(rst_32)
state_32 <= 0;
else
case (state_32)
INIT_32: state_32 <= READY_RCV_32;
READY_RCV_32: if(data_empty_32 == 0) state_32 <= RCV_DATA_32;
RCV_DATA_32: state_32 <= POSE_32;
POSE_32: state_32 <= READY_SND_32;
READY_SND_32: if(1) state_32 <= SND_DATA_32;
SND_DATA_32: state_32 <= READY_RCV_32;
endcase
end
assign rcv_en_32 = (state_32 == RCV_DATA_32);
assign snd_en_32 = (state_32 == SND_DATA_32);
//assign full_32 = 0;
//assign empty_32 = 1;
always @(posedge clk)begin
if(rst_32)begin
/*user defined init*/
dir_right <= 0;
para_right <= 0;
dir_left <= 0;
para_left <= 0;
end
else if (state_32 == RCV_DATA_32)begin
/*user defined rcv*/
dir_right <= din_32[0:0];
para_right <= din_32[15:1];
dir_left <= din_32[16:16];
para_left <= din_32[31:17];
end
// else if (state_32 == READY_SND_32)begin
///*user defined */
// end
end
/*user assign*/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 12:23:27
// Design Name:
// Module Name: carry_look_ahead_adder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module carry_look_ahead_adder(
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] s,
output p,
output g,
output c
);
wire [3:0] p;
wire [3:0] g;
wire [3:0] c;
assign p = a ^ b;
assign g = a & b;
assign c[0] = p[0] & cin | g[0];
assign c[1] = p[1] & (p[0] & cin | g[0]) | g[1];
assign c[2] = p[2] & (p[1] & (p[0] & cin | g[0]) | g[1]) | g[2];
assign c[3] = p[3] & (p[2] & (p[1] & (p[0] & cin | g[0]) | g[1]) | g[2]) | g[3];
assign cout = c[3];
assign s[0] = a[0] + b[0] + cin;
assign s[1] = a[1] + b[1] + c[0];
assign s[2] = a[2] + b[2] + c[1];
assign s[3] = a[3] + b[3] + c[2];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int scs(long long int a) { long long int u = 0; while (a) { u++; a /= 10; } return u; } long long int mul(long long int a, long long int b, long long int m) { if (b == 1) return a % m; if (b == 0) return 1 % m; a %= m; b %= m; long long int q = mul(a, b / 2, m); if (b % 2 == 0) return (q + q) % m; else return (q + q + a) % m; } long long int mu(long long int a, long long int n, long long int m) { if (n == 0) return 1 % m; long long int q = mu(a, n / 2, m); if (n % 2 == 0) return mul(q, q, m); else return mul(mul(q, q, m), a, m); } long long int mu5[20]; int main() { ios::sync_with_stdio(0); cin.tie(NULL); long long int t; cin >> t; mu5[0] = 1; for (int i = 1; i <= 19; i++) mu5[i] = mu5[i - 1] * 5; for (int z = 1; z <= t; z++) { long long int a; cin >> a; long long int n = scs(a); long long int v = 0, m = 0; for (int mmm = 0; mmm <= 6; mmm++) { m = mmm; long long int b = (-a) % (1LL << (m + n)) * mu5[m] % (1LL << (m + n)) * (1LL << m) % (1LL << (m + n)); b %= (1LL << (m + n)); if (b < 0) b += (1LL << (m + n)); bool q = 0; while (b < mu5[m] * (1LL << m)) { v = (b + mu5[m] * (1LL << m) * a) / (1LL << (m + n)); if (v % 5 != 0) { q = 1; break; } b += (1LL << (m + n)); } if (q == 1) { break; } } v %= mu5[m + n]; long long int mm[4] = {1, 2, 4, 3}; long long int res = 0; for (int i = 0; i <= 3; i++) { if (mm[i] == v % 5) res = i; } for (int i = 2; i <= m + n; i++) { long long int r = res; for (int u = 0; u <= 4; u++) { if (mu(2, r + u * 4 * mu5[i - 2], mu5[i]) == v % mu5[i]) { res = r + u * 4 * mu5[i - 2]; break; } } } res += m + n; cout << res << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int dp[100000 + 10]; vector<int> ma[100000 + 10]; int a[100000 + 10]; long long int dp1[100000 + 10]; long long int gcd(long long int x, long long int y) { return y == 0 ? x : gcd(y, x % y); } long long int lcm(long long int x, long long int y) { long long int tmp = gcd(x, y); return x / tmp * y; } void tree_dp(int fa, int n) { if (ma[n].size() == 1) { dp1[n] = 1; dp[n] = (long long int)a[n]; return; } int i; long long int tmp = 1; long long int mins = LLONG_MAX; for (i = 0; i < ma[n].size(); i++) { if (ma[n][i] == fa) continue; tree_dp(n, ma[n][i]); tmp = lcm(tmp, dp1[ma[n][i]]); if (tmp == 0) tmp = 1; mins = min(mins, dp[ma[n][i]]); } dp[n] = (long long int)a[n] + mins / tmp * tmp * (ma[n].size() - 1); dp1[n] = tmp * (ma[n].size() - 1); } int main() { int n; cin >> n; int i; long long int all = 0; for (i = 1; i <= n; i++) { cin >> a[i]; ma[i].clear(); all += a[i]; } ma[1].push_back(1); for (i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; ma[x].push_back(y); ma[y].push_back(x); } tree_dp(1, 1); cout << all - dp[1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; char str[MAXN]; class Value { public: char c1, c2, last_c1, last_c2; int pos, l1, sz; Value() { c1 = 0; c2 = 0; pos = 0; l1 = 0; last_c1 = 0; last_c2 = 0; } void push_front(char c) { if (c == c1) { l1++; } else { c2 = c1; c1 = c; l1 = 1; } if (last_c2 == 0) { last_c2 = c; } else if (last_c1 == 0) { last_c1 = c; } sz++; } bool operator<(const Value &value) const { if (c1 != value.c1) { return c1 < value.c1; } char cl = c1, cr = c1; if (l1 < value.l1) { cl = c2; } else if (value.l1 < l1) { cr = value.c2; } return cl < cr; } } f[MAXN]; void print(int idx, int cnt) { for (int i = 0; i < cnt; i++) { putchar(f[idx].c1); idx = f[idx].pos + 1; } } int main() { scanf( %s , str); int len = strlen(str); f[len].pos = len; for (int i = len - 1; i >= 0; i--) { f[i] = f[i + 1]; f[i].push_front(str[i]); f[i].pos = i; if (i + 1 < len && str[i] == str[i + 1]) { f[i] = min(f[i], f[i + 2]); } } for (int i = 0; i < len; i++) { printf( %d , f[i].sz); if (f[i].sz <= 10) { print(i, f[i].sz); putchar( n ); } else { print(i, 5); printf( ...%c%c n , f[i].last_c1, f[i].last_c2); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, a, b, i = 0, arr[100000], j = 0; cin >> n >> k; for (int x = 0; x < n; x++) { cin >> a >> b; i++; while (a != b) if (a < b) a++, i++; else a--, i++; } while (i % k != 0) { i++; j++; } cout << j; return 0; } |
#include <bits/stdc++.h> using namespace std; unsigned long long gcd(unsigned long long a, unsigned long long b) { if (b == 0) { return a; } return gcd(b, a % b); } int main() { unsigned long long n, m, k; cin >> n >> m >> k; unsigned long long h = 2 * n * m; if (h % k == 0) { cout << YES << endl; bool isKEven = false; if (k % 2 == 0) { isKEven = true; k /= 2; } int y1 = 0, x2 = 0, x3 = 0, y3 = 0; unsigned long long gx = gcd(n, k); k /= gx; unsigned long long x1 = n / gx; unsigned long long gy = gcd(m, k); k /= gy; unsigned long long y2 = m / gy; if (!isKEven) { if (x1 < n) { x1 *= 2; } else { y2 *= 2; } } cout << x1 << << y1 << endl; cout << x2 << << y2 << endl; cout << x3 << << y3 << endl; } else { cout << NO ; } } |
#include <bits/stdc++.h> using namespace std; int n, m, a[100010], s[100010], sp, cnt; long long tot, sum, pj; int main() { cin >> n >> m; for (register int i = 1; i <= n; i++) cin >> a[i], tot += a[i]; if (tot % m != 0) { cout << No << endl; return 0; } pj = tot / m; for (register int i = 1; i <= n; i++) { sum += a[i]; if (sum == pj) { sum = 0; s[++cnt] = i - sp; sp = i; } if (sum > pj) { cout << No << endl; return 0; } } cout << Yes << endl; for (register int i = 1; i <= cnt; i++) cout << s[i] << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_1_V
`define SKY130_FD_SC_HD__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_8_V
`define SKY130_FD_SC_HDLL__NOR4_8_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_8 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_8 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n; string s; cin >> n >> s; map<long long int, vector<long long int>> mp; for (long long int i = 0; i < s.size(); i++) { mp[s[i] - 0 ].push_back(i); } vector<long long int> ans(n + 1, 0); long long int las = -1; for (auto x : mp) { vector<long long int> v = x.second; long long int cnt = 0; for (long long int i = 0; i < v.size(); i++) { if (v[i] > las) { ans[v[i]] = 1; cnt++; las = v[i]; } } if (cnt != v.size()) { break; } } vector<long long int> ck; for (long long int i = 0; i < n; i++) { if (ans[i] == 1) { ck.push_back(s[i] - 0 ); } } for (long long int i = 0; i < n; i++) { if (ans[i] != 1) { ck.push_back(s[i] - 0 ); } } long long int f = 0; for (long long int i = 1; i < n; i++) { if (ck[i] < ck[i - 1]) { f = 1; break; } } if (f == 1) { cout << - << endl; } else { string str; for (long long int i = 0; i < n; i++) { if (ans[i] == 0) { str += 2 ; } else { str += 1 ; } } cout << str << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100500]; int sp[2005]; int f[100500], l[100500]; int n, m; int ns[2 * 100500]; int ps[2 * 100500]; int used[2 * 100500]; int lp[100500]; int rp[100500]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( %d , a + i); } sort(a + 1, a + n + 1); for (int i = 1; i <= m; ++i) { scanf( %d , sp + i); used[sp[i]] = true; ns[sp[i]] = sp[i]; ps[sp[i]] = sp[i]; } for (int i = n; i >= 1; --i) { if (i != n && a[i] == a[i + 1] - 1) { rp[i] = rp[i + 1]; } else { rp[i] = i; } } for (int i = 1; i <= n; ++i) { if (i != 1 && a[i] == a[i - 1] + 1) { lp[i] = lp[i - 1]; } else { lp[i] = i; } } for (int i = 2 * 100500 - 2; i >= 0; --i) { if (ns[i] == 0) { ns[i] = ns[i + 1]; } } for (int i = 1; i < 2 * 100500; ++i) { if (ps[i] == 0) { ps[i] = ps[i - 1]; } } sort(sp + 1, sp + m + 1); f[0] = 0, l[0] = 0; for (int i = 1; i <= n; ++i) { int df = a[i] - i; for (int cp = a[i], cnt = used[a[i]]; cp && df < cp; ++cnt, cp = ps[cp - 1]) { l[i] = max(l[i], f[lp[i - a[i] + cp] - 1] + cnt); } f[i] = max(f[i], l[i]); df = n - i + a[i]; for (int cp = a[i], cnt = used[a[i]]; cp && df >= cp; ++cnt, cp = ns[cp + 1]) { f[rp[i + cp - a[i]]] = max(f[rp[i + cp - a[i]]], l[i] + cnt - used[a[i]]); } } int res = *max_element(f + 1, f + n + 1); printf( %d n , res); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: ff_64x256_fwft.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ff_64x256_fwft (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [63:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [63:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [63:0] sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [63:0] q = sub_wire3[63:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 64,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M10K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_64x256_fwft_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_PP_SYMBOL_V
|
// nios_dut_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_delay_cntrl (
// delay interface
delay_clk,
delay_rst,
delay_locked,
// io interface
up_dld,
up_dwdata,
up_drdata,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter DATA_WIDTH = 8;
parameter BASE_ADDRESS = 6'h02;
// delay interface
input delay_clk;
output delay_rst;
input delay_locked;
// io interface
output [(DATA_WIDTH-1):0] up_dld;
output [((DATA_WIDTH*5)-1):0] up_dwdata;
input [((DATA_WIDTH*5)-1):0] up_drdata;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_preset = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_dlocked_m1 = 'd0;
reg up_dlocked = 'd0;
reg [(DATA_WIDTH-1):0] up_dld = 'd0;
reg [((DATA_WIDTH*5)-1):0] up_dwdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 4:0] up_rdata_s;
wire [(DATA_WIDTH-1):0] up_drdata4_s;
wire [(DATA_WIDTH-1):0] up_drdata3_s;
wire [(DATA_WIDTH-1):0] up_drdata2_s;
wire [(DATA_WIDTH-1):0] up_drdata1_s;
wire [(DATA_WIDTH-1):0] up_drdata0_s;
// variables
genvar n;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0;
assign up_rdata_s[4] = | up_drdata4_s;
assign up_rdata_s[3] = | up_drdata3_s;
assign up_rdata_s[2] = | up_drdata2_s;
assign up_rdata_s[1] = | up_drdata1_s;
assign up_rdata_s[0] = | up_drdata0_s;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_drd
assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
end
endgenerate
// processor interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_preset <= 1'd1;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
up_dlocked_m1 <= 'd0;
up_dlocked <= 'd0;
end else begin
up_preset <= 1'd0;
up_wack <= up_wreq_s;
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
if (up_dlocked == 1'b0) begin
up_rdata <= 32'hffffffff;
end else begin
up_rdata <= {27'd0, up_rdata_s};
end
end else begin
up_rdata <= 32'd0;
end
up_dlocked_m1 <= delay_locked;
up_dlocked <= up_dlocked_m1;
end
end
// write does not hold- read back what goes into effect.
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dld[n] <= 'd0;
up_dwdata[((n*5)+4):(n*5)] <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
up_dld[n] <= 1'd1;
up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
end else begin
up_dld[n] <= 1'd0;
up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
end
end
end
end
endgenerate
// resets
ad_rst i_delay_rst_reg (
.preset (up_preset),
.clk (delay_clk),
.rst (delay_rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; inline int read() { int res = 0, f = 1; char ch; while (ch = getchar(), ch < 0 || ch > 9 ) if (ch == - ) f = -1; while (ch >= 0 && ch <= 9 ) res = res * 10 + ch - 0 , ch = getchar(); return res * f; } const int N = 14, M = 4782969, P = 1e9 + 7; inline int qpow(int a, int b) { int ans = 1, base = a; while (b) { if (b & 1) ans = 1ll * ans * base % P; base = 1ll * base * base % P; b >>= 1; } return ans; } int rev[1 << N], cnt[1 << N], n, A, a[N]; int F[1 << N], G[1 << N], v[N][1 << N]; inline int get(int S, int T) { if (!S) return 1; if (G[S]) return G[S]; return G[S] = 1ll * get(S & (S - 1), T) * v[rev[S & -S]][T] % P; } int main() { n = read(), A = (1 << n) - 1; for (int i = 0; i < n; ++i) a[i] = read(), rev[1 << i] = i; for (int i = 0; i < n; ++i) { v[i][0] = 1; for (int S = 1; S < (1 << n); ++S) v[i][S] = 1ll * v[i][S & (S - 1)] * a[i] % P * qpow((a[rev[S & -S]] + a[i]) % P, P - 2) % P; } for (int S = 1; S < (1 << n); ++S) { int tmp = 0; cnt[S] = cnt[S >> 1] + (S & 1); for (int T = (S - 1) & S; T; T = (T - 1) & S) (tmp += 1ll * F[T] * get(S ^ T, A ^ S) % P) %= P; F[S] = (get(S, A ^ S) - tmp + P) % P; for (int T = S; T; T = (T - 1) & S) G[T] = 0; } int res = 0; for (int S = 1; S < (1 << n); ++S) (res += 1ll * F[S] * cnt[S] % P) %= P; printf( %d , res); return 0; } |
/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: begin
dmem[addr] <= asubb;
$display("mw:DMEM,%h,%h", addr, asubb);
end
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor("%d:%b:%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h",
$time, clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1, PC);
end // initial begin
endmodule
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = %CYCLES%;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule
|
module ram0(
// Read port
input rdclk,
input [9:0] rdaddr,
output reg [35:0] do);
(* ram_style = "block" *) reg [35:0] ram[0:1023];
genvar i;
generate
for (i=0; i<1024; i=i+1)
begin
initial begin
ram[i] <= i | (i << 16);
end
end
endgenerate
always @ (posedge rdclk) begin
do <= ram[rdaddr];
end
endmodule
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [9:0] read_address;
wire [35:0] read_data;
wire [9:0] rom_read_address;
reg [35:0] rom_read_data;
always @(posedge clk) rom_read_data <= {2{6'd0, rom_read_address}};
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [9:0] error_address;
wire [35:0] expected_data;
wire [35:0] actual_data;
ROM_TEST #(
.ADDR_WIDTH(10),
.DATA_WIDTH(36),
.ADDRESS_STEP(1),
.MAX_ADDRESS(1023)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.read_address(read_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
ram0 #(
) bram (
// Read port
.rdclk(clk),
.rdaddr(read_address),
.do(read_data)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(32),
.ADDR_WIDTH(10)
) output_logic (
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int m, n, row[1010], col[1010], ans = 0, sum = 0; char a[1010][1010]; cin >> m >> n; memset(row, 0, sizeof row); memset(col, 0, sizeof col); for (long long int i = 0; i < m; i++) for (long long int j = 0; j < n; j++) { cin >> a[i][j]; if (a[i][j] == * ) { row[i]++; col[j]++; } } for (long long int i = 0; i < n; i++) { sum = 0; for (long long int j = 0; j < m; j++) { if (a[j][i] == * ) sum = sum + row[j] - 1; } ans = ans + sum * (col[i] - 1); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); ios::sync_with_stdio(0); int n, r1 = 0, r2 = 0; cin >> n; vector<int> r(n); for (int &i : r) cin >> i; for (int i = 0; i < n; i++) { int a; cin >> a; if (a != r[i]) { if (a) r1++; else r2++; } } if (!r2) cout << -1 n ; else if (r2 > r1) cout << 1 n ; else cout << (int)ceil((r1 + 1.0) / r2) << n ; } |
#include <bits/stdc++.h> using namespace std; string s; pair<int, int> st[3000002]; void build(int v, int l, int r) { if (l == r) { st[v] = make_pair(s[l] == ( , s[l] == ) ); return; } int lv, rv, mid; lv = 2 * v; rv = 2 * v + 1; mid = (l + r) / 2; build(lv, l, mid); build(rv, mid + 1, r); st[v].first = st[rv].first + max(0, st[lv].first - st[rv].second); st[v].second = st[lv].second + max(0, st[rv].second - st[lv].first); } pair<int, int> query(int v, int l, int r, int L, int R) { if (r < L || R < l) return make_pair(0, 0); if (L <= l && r <= R) return st[v]; pair<int, int> L1 = query(2 * v, l, (l + r) / 2, L, R); pair<int, int> R1 = query(2 * v + 1, (l + r) / 2 + 1, r, L, R); return make_pair(R1.first + max(0, L1.first - R1.second), L1.second + max(0, R1.second - L1.first)); } int main() { cin >> s; int n = s.length(); build(1, 0, n - 1); int m; cin >> m; for (int i = 0; i < m; ++i) { int l, r; cin >> l >> r; l--; r--; pair<int, int> q = query(1, 0, n - 1, l, r); cout << r - l + 1 - (q.first + q.second) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100 * 1000 + 7, MAX_LOG = 20; int n, m; vector<int> adj[MAXN]; bool isPassed[MAXN]; int par[MAXN][MAX_LOG], cycleCnt[MAXN], h[MAXN]; void pre(int root) { isPassed[root] = true; for (auto nei : adj[root]) { if (!isPassed[nei]) { par[nei][0] = root; h[nei] = h[root] + 1; pre(nei); cycleCnt[root] = cycleCnt[root] + cycleCnt[nei]; } else if (par[root][0] != nei and h[nei] < h[root]) { cycleCnt[nei]--; cycleCnt[root]++; } } return; } int nanCyCnt[MAXN][MAX_LOG]; void dfs(int root, int lstRt) { par[root][0] = lstRt; if (lstRt != -1 and cycleCnt[root] == 0) nanCyCnt[root][0] = 1; for (int i = 1; i < MAX_LOG and h[root] >= (1 << i) and par[par[root][i - 1]][i - 1] != -1; ++i) { par[root][i] = par[par[root][i - 1]][i - 1]; nanCyCnt[root][i] = nanCyCnt[root][i - 1] + nanCyCnt[par[root][i - 1]][i - 1]; } isPassed[root] = true; for (auto nei : adj[root]) { if (!isPassed[nei]) { h[nei] = h[root] + 1; dfs(nei, root); } } return; } int lca(int v, int u) { int nancy = 0; if (h[v] > h[u]) swap(v, u); for (int i = 0; h[v] ^ h[u]; ++i) { if ((h[u] - h[v]) & (1 << i)) { nancy += nanCyCnt[u][i]; u = par[u][i]; } } if (v == u) return nancy; for (int i = MAX_LOG - 1; i >= 0; --i) { if (par[v][i] != par[u][i]) { nancy += (nanCyCnt[v][i] + nanCyCnt[u][i]); v = par[v][i], u = par[u][i]; } } return nancy + nanCyCnt[v][0] + nanCyCnt[u][0]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(par, -1, sizeof par); cin >> n >> m; for (int i = 0; i < m; ++i) { int v, u; cin >> v >> u, v--, u--; adj[v].push_back(u); adj[u].push_back(v); } memset(isPassed, 0, sizeof isPassed); pre(0); memset(isPassed, 0, sizeof isPassed); memset(h, 0, sizeof h); dfs(0, -1); int mercsNum; cin >> mercsNum; while (mercsNum--) { int sh, wa; cin >> wa >> sh, wa--, sh--; cout << lca(wa, sh) << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void doicho(int &t1, int &t2) { if (t1 > t2) swap(t1, t2); } void sapxep(pair<double, int> result[], int n) { for (int i = 0; i < n - 1; i++) { for (int j = i + 1; j < n; j++) { if (result[i].first < result[j].first) { swap(result[i].first, result[j].first); swap(result[i].second, result[j].second); } else if (result[i].first == result[j].first && result[i].second > result[j].second) { swap(result[i].first, result[j].first); swap(result[i].second, result[j].second); } } } } int main() { int n, t1, t2, k; cin >> n >> t1 >> t2 >> k; int a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i] >> b[i]; pair<double, int> result[n]; for (int i = 0; i < n; i++) { double x, y, z, t; x = (a[i] * t1 - t1 * a[i] * ((double)k / 100) + b[i] * t2); t = (a[i] * t2 - t1 * b[i] * ((double)k / 100) + b[i] * t1); double max2 = x > t ? x : t; result[i].first = max2; result[i].second = i + 1; } sapxep(result, n); for (int i = 0; i < n; i++) printf( %d %.2f n , result[i].second, result[i].first); } |
//----------------------------------------------------------------------------
//--By Kyle Williams, 11/20/2012-----------------------------------------------------
//--MODULE DESCRIPTION---------------------------------------------------------------
//----------------Simple single Port Ram used to store data--------------------------
//----------------reset is not required ram can be filled with useless data----------
//Instead of using a case statement it would be quicker to act on multiple data at once
//SHOULD BE MADE ABUNDANTLY CLEAR ANY BANK THAT IS ONLY PARTIALLY FILLED WILL BE DROPPED
///ie 1011xxxx will be dropped since it is not fully displaying a word
module Decryption
#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 8,
parameter MEM_DEPTH = 64
)(
//------------Input Ports------------
input clk,
input rst,
input ena,
input[DATA_WIDTH-1:0] key,
input[DATA_WIDTH-1:0] data_in,
//------------Output Ports-----------
output reg finished,
output reg mem_wr_ena,
output reg[ADDR_WIDTH-1:0] memIn_addr,
output reg[ADDR_WIDTH-1:0] memOut_addr,
output reg[DATA_WIDTH-1:0] data_out
);
parameter shift = DATA_WIDTH/2;//swap by nibbles instead of shift by address since Range must be bounded by constant expressions.
// ------------- Regs/ wires -----------
//internal memory for encryption
//store address then data in a memory module instead of seperate busses to keep design tidy and easier to follow
parameter MEM_WIDTH = ADDR_WIDTH+DATA_WIDTH;
reg [MEM_WIDTH-1:0] mem [0:8];
reg start;//need to be used to make sure initial statements are correct
reg done;//needs to know when data becomes irrelevant and can stop hardware
always@(posedge clk)
begin:Main_Module
case(rst)
1'b0:
if(ena==1'b1 && start==1'b0)begin
start <= 1'b1;
done <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
mem_wr_ena <= 1'b0;
end else
if(ena==1'b1) begin:Encryption
begin:Stage_FetchData
if(data_in!=={DATA_WIDTH{1'bx}})begin//bad practice but good assumption
mem[0] <= {memIn_addr-1,data_in};//decrement address since process happens one clock cycle in the future
memIn_addr <= memIn_addr+1;//increment m ram address
end else begin
done <= 1'b1;
mem[0] <= {MEM_WIDTH{1'b0}};
end
end
begin:Stage0_Stage3_Stage7_AddRoundKey//XOR with pin append address to the end
mem[1] <= |mem[0]==1'b0 ? mem[0] : {mem[0][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[0][DATA_WIDTH-1:0] ^ key};
mem[4] <= |mem[3]==1'b0 ? mem[3] : {mem[3][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[3][DATA_WIDTH-1:0] ^ key};
mem[8] <= |mem[7]==1'b0 ? mem[7] : {mem[7][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[7][DATA_WIDTH-1:0] ^ key};
end
begin:Stage2_Stage6_SubBytes//Replace each byte according to loopup table
//Due to complexity and time constraint instead use 2's compliment
mem[3] <= |mem[2]==1'b0 ? mem[2] : {mem[2][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
~mem[2][DATA_WIDTH-1:0]+1'b1};
mem[7] <= |mem[6]==1'b0 ? mem[6] : {mem[6][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
~mem[6][DATA_WIDTH-1:0]+1'b1};
end
begin:Stage1_Stage5_ShiftRows
mem[2] <= |mem[1]==1'b0 ? mem[1] : {mem[1][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[1][shift:0],mem[1][DATA_WIDTH-1:shift+1]};//>>mem[1][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
mem[6] <= |mem[5]==1'b0 ? mem[5] : {mem[5][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[5][shift:0],mem[5][DATA_WIDTH-1:shift+1]};//<<mem[5][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
end
begin:Stage4_MixColumns//multMatrix by a set amount...this section is not implimented correctly
//due to time constraints data data by address
mem[5] <= |mem[4]==1'b0 ? mem[4] : {mem[4][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH],
mem[4][DATA_WIDTH-1:0]-mem[4][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH]};
end
begin:Stage8_Push_Data//if Performing Bitwise & on all bits doesn't return 0 or 1 then no more data needs to be processed
//placing & infront of a signal performs the AND operator on all bits
if(mem[8]!=={MEM_WIDTH{1'b0}})begin
mem_wr_ena <= 1'b1;
memOut_addr <= mem[8][ADDR_WIDTH+DATA_WIDTH-1:DATA_WIDTH];
data_out <= mem[8][DATA_WIDTH-1:0];
end
else if (done==1'b1) begin
finished <= 1'b1;
start <=1'b0;
done <= 1'b0;
mem_wr_ena <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
$display("Decryption Completed");
end
end
end
1'b1:
begin:Reset
start <=1'b0;
done <= 1'b0;
finished <= 1'b0;
mem_wr_ena <= 1'b0;
memIn_addr <= {ADDR_WIDTH{1'b0}};
memOut_addr <= {ADDR_WIDTH{1'b0}};
data_out <= {DATA_WIDTH{1'b0}};
mem[0] <= {MEM_WIDTH{1'b0}};
mem[1] <= {MEM_WIDTH{1'b0}};
mem[2] <= {MEM_WIDTH{1'b0}};
mem[3] <= {MEM_WIDTH{1'b0}};
mem[4] <= {MEM_WIDTH{1'b0}};
mem[5] <= {MEM_WIDTH{1'b0}};
mem[6] <= {MEM_WIDTH{1'b0}};
mem[7] <= {MEM_WIDTH{1'b0}};
mem[8] <= {MEM_WIDTH{1'b0}};
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, c, r[200001], u, v, i, t, k; vector<long long> graph[200001], ans; bool dfs(long long x, long long p) { long long s = 0; for (auto i : graph[x]) if (i != p) s += dfs(i, x); if (r[x] && !s) ans.push_back(x); return s + (long long)(r[x] && r[p]); } int main() { cin >> n; for (i = 0; i < n - 1; i++) { cin >> u >> v >> t, graph[u].push_back(v), graph[v].push_back(u); if (t == 2) r[u] = 1, r[v] = 1; } dfs(1, 0); for (cout << ans.size() << endl, i = 0; i < ans.size(); i++) cout << ans[i] << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__AND3_PP_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_PP_SYMBOL_V
|
/*
* include/linux/ion.h
*
* Copyright (C) 2011 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _LINUX_ION_H
#define _LINUX_ION_H
#include "config.h"
#include <linux/types.h>
#ifdef CONFIG_COMPAT
#include "hacked/compat.h"
#endif
typedef int ion_user_handle_t;
/**
* enum ion_heap_types - list of all possible types of heaps
* @ION_HEAP_TYPE_SYSTEM: memory allocated via vmalloc
* @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc
* @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved
* carveout heap, allocations are physically
* contiguous
* @ION_HEAP_TYPE_DMA: memory allocated via DMA API
* @ION_NUM_HEAPS: helper for iterating over heaps, a bit mask
* is used to identify the heaps, so only 32
* total heap types are supported
*/
enum ion_heap_type {
ION_HEAP_TYPE_SYSTEM,
ION_HEAP_TYPE_SYSTEM_CONTIG,
ION_HEAP_TYPE_CARVEOUT,
ION_HEAP_TYPE_CHUNK,
ION_HEAP_TYPE_DMA,
ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always
are at the end of this enum */
ION_NUM_HEAPS = 16,
};
#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG)
#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT)
#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA)
#define ION_NUM_HEAP_IDS sizeof(unsigned int) * 8
/**
* allocation flags - the lower 16 bits are used by core ion, the upper 16
* bits are reserved for use by the heaps themselves.
*/
#define ION_FLAG_CACHED 1 /* mappings of this buffer should be
cached, ion will do cache
maintenance when the buffer is
mapped for dma */
#define ION_FLAG_CACHED_NEEDS_SYNC 2 /* mappings of this buffer will created
at mmap time, if this is set
caches must be managed manually */
#define ION_FLAG_PRESERVE_KMAP 4 /* deprecated. ignored. */
#define ION_FLAG_NOZEROED 8 /* Allocated buffer is not initialized
with zero value and userspace is not
able to access the buffer
*/
/**
* DOC: Ion Userspace API
*
* create a client by opening /dev/ion
* most operations handled via following ioctls
*
*/
/**
* struct ion_allocation_data - metadata passed from userspace for allocations
* @len: size of the allocation
* @align: required alignment of the allocation
* @heap_id_mask: mask of heap ids to allocate from
* @flags: flags passed to heap
* @handle: pointer that will be populated with a cookie to use to
* refer to this allocation
*
* Provided by userspace as an argument to the ioctl
*/
struct ion_allocation_data {
size_t len;
size_t align;
unsigned int heap_id_mask;
unsigned int flags;
ion_user_handle_t handle;
};
/**
* struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair
* @handle: a handle
* @fd: a file descriptor representing that handle
*
* For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with
* the handle returned from ion alloc, and the kernel returns the file
* descriptor to share or map in the fd field. For ION_IOC_IMPORT, userspace
* provides the file descriptor and the kernel returns the handle.
*/
struct ion_fd_data {
ion_user_handle_t handle;
int fd;
};
/**
* struct ion_handle_data - a handle passed to/from the kernel
* @handle: a handle
*/
struct ion_handle_data {
ion_user_handle_t handle;
};
/**
* struct ion_custom_data - metadata passed to/from userspace for a custom ioctl
* @cmd: the custom ioctl function to call
* @arg: additional data to pass to the custom ioctl, typically a user
* pointer to a predefined structure
*
* This works just like the regular cmd and arg fields of an ioctl.
*/
struct ion_custom_data {
unsigned int cmd;
unsigned long arg;
};
/**
* struct ion_preload_data - metadata for preload buffers
* @heap_id_mask: mask of heap ids to allocate from
* @len: size of the allocation
* @flags: flags passed to heap
* @count: number of buffers of the allocation
*
* Provided by userspace as an argument to the ioctl
*/
struct ion_preload_object {
size_t len;
unsigned int count;
};
struct ion_preload_data {
unsigned int heap_id_mask;
unsigned int flags;
unsigned int count;
struct ion_preload_object *obj;
};
#define ION_IOC_MAGIC 'I'
/**
* DOC: ION_IOC_ALLOC - allocate memory
*
* Takes an ion_allocation_data struct and returns it with the handle field
* populated with the opaque handle for the allocation.
*/
#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \
struct ion_allocation_data)
/**
* DOC: ION_IOC_FREE - free memory
*
* Takes an ion_handle_data struct and frees the handle.
*/
#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data)
/**
* DOC: ION_IOC_MAP - get a file descriptor to mmap
*
* Takes an ion_fd_data struct with the handle field populated with a valid
* opaque handle. Returns the struct with the fd field set to a file
* descriptor open in the current address space. This file descriptor
* can then be used as an argument to mmap.
*/
#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data)
/**
* DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation
*
* Takes an ion_fd_data struct with the handle field populated with a valid
* opaque handle. Returns the struct with the fd field set to a file
* descriptor open in the current address space. This file descriptor
* can then be passed to another process. The corresponding opaque handle can
* be retrieved via ION_IOC_IMPORT.
*/
#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data)
/**
* DOC: ION_IOC_IMPORT - imports a shared file descriptor
*
* Takes an ion_fd_data struct with the fd field populated with a valid file
* descriptor obtained from ION_IOC_SHARE and returns the struct with the handle
* filed set to the corresponding opaque handle.
*/
#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)
/**
* DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory
*
* Deprecated in favor of using the dma_buf api's correctly (syncing
* will happend automatically when the buffer is mapped to a device).
* If necessary should be used after touching a cached buffer from the cpu,
* this will make the buffer in memory coherent.
*/
#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)
/**
* DOC: ION_IOC_PRELOAD_ALLOC - prefetches pages to page pool
*/
#define ION_IOC_PRELOAD_ALLOC _IOW(ION_IOC_MAGIC, 8, struct ion_preload_data)
/**
* DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl
*
* Takes the argument of the architecture specific ioctl to call and
* passes appropriate userdata for that ioctl
*/
#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
//support for compat
#ifdef CONFIG_COMPAT
struct compat_ion_allocation_data {
compat_size_t len;
compat_size_t align;
compat_uint_t heap_id_mask;
compat_uint_t flags;
compat_int_t handle;
};
struct compat_ion_custom_data {
compat_uint_t cmd;
compat_ulong_t arg;
};
struct compat_ion_handle_data {
compat_int_t handle;
};
#define COMPAT_ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \
struct compat_ion_allocation_data)
#define COMPAT_ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, \
struct compat_ion_handle_data)
#define COMPAT_ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, \
struct compat_ion_custom_data)
#endif
#endif /* _LINUX_ION_H */
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [255:0] sum;
// Take CRC data and apply to testblock inputs
wire [127:0] in = {~crc[63:0], crc[63:0]};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [127:0] o1; // From test of Test.v
wire [127:0] o2; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.o1 (o1[127:0]),
.o2 (o2[127:0]),
// Inputs
.in (in[127:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
o1, o2,
// Inputs
in
);
input [127:0] in;
output logic [127:0] o1;
output logic [127:0] o2;
always_comb begin: b_test
logic [127:0] tmpp;
logic [127:0] tmp;
tmp = '0;
tmpp = '0;
tmp[63:0] = in[63:0];
tmpp[63:0] = in[63:0];
tmpp[63:0] = {tmp[0+:32], tmp[32+:32]};
tmp[63:0] = {tmp[0+:32], tmp[32+:32]};
o1 = tmp;
o2 = tmpp;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105]; int f[105]; int v[105]; bool cmp(int i, int j) { return a[i] > a[j]; } int main() { int n, w; while (cin >> n >> w) { int sum = 0; int sum2 = 0; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; if (a[i] % 2 == 0) f[i] = a[i] / 2; else f[i] = (a[i] + 1) / 2; sum2 += f[i]; } for (int i = 0; i < n; i++) v[i] = i; sort(v, v + n, cmp); if (sum2 > w || sum < w) { cout << -1 << endl; continue; } w -= sum2; for (int i = 0; i < n; i++) { if (w > a[v[i]] - f[v[i]]) { w -= (a[v[i]] - f[v[i]]); f[v[i]] = a[v[i]]; } else if (w <= a[v[i]] - f[v[i]]) { f[v[i]] += w; break; } } for (int i = 0; i < n; i++) { cout << f[i]; if (i != n - 1) cout << ; } cout << endl; } } |
// File: elevator.v
// Generated by MyHDL 0.8.1
// Date: Sun Jun 14 22:11:56 2015
`timescale 100ms/1ms
module elevator (
clk,
reset,
en,
F,
D,
Q,
A,
B,
A_latch,
B_latch,
LED,
io_seg
);
input clk;
input reset;
input en;
input [3:0] F;
output [3:0] D;
wire [3:0] D;
output [3:0] Q;
reg [3:0] Q;
output A;
reg A;
output B;
reg B;
output A_latch;
reg A_latch;
output B_latch;
reg B_latch;
output [3:0] LED;
wire [3:0] LED;
output [7:0] io_seg;
wire [7:0] io_seg;
always @(en, F) begin: ELEVATOR_ENCODER
if (((F != 0) && en)) begin
A = ((F[3] || (F[1] && (!F[2]))) != 0);
B = ((F[2] || F[3]) != 0);
end
end
always @(reset, A, B, en, F) begin: ELEVATOR_LATCH
if (reset) begin
A_latch = (1'b0 != 0);
B_latch = (1'b0 != 0);
end
else if (((F != 0) && en)) begin
A_latch = A;
B_latch = B;
end
end
assign D = {((((!Q[3]) && (!Q[2]) && (!Q[1]) && (!Q[0]) && B_latch && A_latch) || ((!Q[3]) && (!Q[2]) && Q[1] && (!Q[0]) && (!B_latch) && (!A_latch)) || (Q[3] && Q[2] && Q[1] && (!Q[0])) || ((!Q[3]) && (!Q[2]) && Q[1] && Q[0] && (!B_latch))) != 0), ((((!Q[3]) && (!Q[2]) && Q[1] && Q[0] && (!B_latch) && (!A_latch)) || ((!Q[3]) && (!Q[2]) && (!Q[1]) && B_latch && A_latch) || (Q[3] && Q[2] && (!Q[1]) && Q[0]) || ((!Q[3]) && (!Q[2]) && (!Q[1]) && (!Q[0]) && B_latch)) != 0), ((((!Q[3]) && (!Q[2]) && Q[1] && Q[0] && (!B_latch)) || ((!Q[3]) && (!Q[2]) && Q[0] && B_latch) || (Q[2] && (!Q[1]) && Q[0]) || ((!Q[3]) && Q[1] && (!Q[0]) && B_latch) || ((!Q[3]) && Q[2] && Q[1] && (!Q[0]))) != 0), ((((!Q[3]) && (!Q[2]) && Q[1] && (!Q[0]) && (!B_latch) && (!A_latch)) || ((!Q[3]) && (!Q[2]) && (!Q[1]) && (!B_latch) && A_latch) || ((!Q[3]) && (!Q[2]) && Q[1] && B_latch && A_latch) || ((!Q[3]) && (!Q[2]) && (!Q[1]) && (!Q[0]) && B_latch) || (Q[3] && Q[1] && (!Q[0])) || ((!Q[3]) && Q[2] && Q[1] && (!Q[0])) || (Q[1] && (!Q[0]) && A_latch)) != 0)};
always @(posedge clk, posedge reset) begin: ELEVATOR_DFF
if (reset == 1) begin
Q <= 0;
end
else begin
if (en) begin
Q <= D;
end
end
end
assign LED = {((Q[1] && Q[0]) != 0), ((Q[1] && (!Q[0])) != 0), (((!Q[1]) && Q[0]) != 0), (((!Q[1]) && (!Q[0])) != 0)};
assign io_seg[0] = ~(LED[0] | LED[2] | LED[3]);
assign io_seg[1] = ~(LED[0] | LED[1] | LED[2] | LED[3]);
assign io_seg[2] = ~(LED[0] | LED[1] | LED[3]);
assign io_seg[3] = ~(LED[0] | LED[2] | LED[3]);
assign io_seg[4] = ~(LED[0] | LED[2]);
assign io_seg[5] = ~(LED[0]);
assign io_seg[6] = ~(LED[2] | LED[3]);
assign io_seg[7] = 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, x, y, neg, pos; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; if (x < 0) neg++; else pos++; } if (pos <= 1 || neg <= 1) cout << Yes ; else cout << No ; return 0; } |
#include <bits/stdc++.h> int cut; int q[100005] = {0}; int totalnode, totaledge, i, j, k, l, a, b, t1, t2; int c(int q) { if (q == 2) { return cut; } else if (q == cut) { return 2; } else return q; } int main() { for (i = 0; i < 100005; i++) q[i] = i; scanf( %d %d %d , &totalnode, &totaledge, &cut); q[cut] = 2; q[2] = cut; if (totaledge >= totalnode - 1 && (totalnode - 1) * (totalnode - 2) / 2 + 1 >= totaledge) { for (i = 1; i <= totalnode - 1; i++) { printf( %d %d n , q[i], q[i + 1]); totaledge--; } for (i = 2; i <= totalnode && totaledge > 0; i++) { for (j = i + 2; j <= totalnode && totaledge > 0; j++) { printf( %d %d n , q[i], q[j]); totaledge--; } } } else { printf( -1 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { int n; cin >> n; int a[n]; bool ok = true; bool f = true; for (int i = 0; i < n; i++) { cin >> a[i]; if (!ok) continue; if (f && a[i] < i) { f = false; } if (!f && a[i] < n - i - 1) ok = false; } if (n % 2 == 0 && a[n / 2] == (n / 2 - 1) && a[n / 2 - 1] == (n / 2 - 1)) ok = false; if (ok) cout << Yes n ; else cout << No n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int> > g; bool flag[100003]; int down[100003]; int max1[100003]; int max2[100003]; int up[100003]; void dfs(int x) { flag[x] = true; int i; for (i = 0; i < g[x].size(); i++) { if (!flag[g[x][i]]) { dfs(g[x][i]); if (down[g[x][i]] + 1 > max1[x]) { max2[x] = max1[x]; max1[x] = down[g[x][i]] + 1; } else if (down[g[x][i]] + 1 > max2[x]) max2[x] = down[g[x][i]] + 1; } } down[x] = max1[x]; } void dfs2(int x) { flag[x] = true; int i; int res; for (i = 0; i < g[x].size(); i++) { if (!flag[g[x][i]]) { if (down[g[x][i]] + 1 > max1[x] - 1) res = max2[x]; else res = max1[x]; up[g[x][i]] = max(up[x] + 1, res + 1); dfs2(g[x][i]); } } } int n, m, d; int main() { scanf( %d %d %d , &n, &m, &d); g.resize(n); int x, y; int i; for (i = 0; i < n; i++) max1[i] = max2[i] = up[i] = down[i] = -2000000000; for (i = 0; i < m; i++) { scanf( %d , &x); x--; down[x] = 0; up[x] = 0; max1[x] = 0; } for (i = 0; i < n - 1; i++) { scanf( %d %d , &x, &y); x--; y--; g[x].push_back(y); g[y].push_back(x); } dfs(0); for (i = 0; i < n; i++) flag[i] = false; dfs2(0); int ans = 0; for (i = 0; i < n; i++) if (down[i] < d + 1 && up[i] < d + 1) ans++; printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_PP_SYMBOL_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
// Design of the 2-bit pipe
module pipeline_buffer_2bit (in,out,clock,reset);
// Output signal for the design module
output [1:0] out; // Output data signal
// Input signals for the design module
input [1:0] in; // Input data signal
input clock; // Input clock signal
input reset; // Input reset signal
// Declare "reg" signals... that will be assigned values
reg [1:0] out;
reg [1:0] o1; // Output of flip-flop #1
reg [1:0] o2; // Output of flip-flop #2
reg [1:0] o3; // Output of flip-flop #3
reg [1:0] o4; // Output of flip-flop #4
reg [1:0] o5; // Output of flip-flop #5
reg [1:0] o6; // Output of flip-flop #6
reg [1:0] o7; // Output of flip-flop #7
reg [1:0] o8; // Output of flip-flop #8
reg [1:0] o9; // Output of flip-flop #9
reg [1:0] o10; // Output of flip-flop #10
reg [1:0] o11; // Output of flip-flop #11
reg [1:0] o12; // Output of flip-flop #12
reg [1:0] o13; // Output of flip-flop #13
reg [1:0] o14; // Output of flip-flop #14
reg [1:0] o15; // Output of flip-flop #15
reg [1:0] o16; // Output of flip-flop #16
reg [1:0] o17; // Output of flip-flop #17
reg [1:0] o18; // Output of flip-flop #18
reg [1:0] o19; // Output of flip-flop #19
reg [1:0] o20; // Output of flip-flop #20
reg [1:0] o21; // Output of flip-flop #21
reg [1:0] o22; // Output of flip-flop #22
reg [1:0] o23; // Output of flip-flop #23
reg [1:0] o24; // Output of flip-flop #24
reg [1:0] o25; // Output of flip-flop #25
reg [1:0] o26; // Output of flip-flop #26
reg [1:0] o27; // Output of flip-flop #27
reg [1:0] o28; // Output of flip-flop #28
reg [1:0] o29; // Output of flip-flop #29
reg [1:0] o30; // Output of flip-flop #30
reg [1:0] o31; // Output of flip-flop #31
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Create the 1st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o1 = 2'd0;
else
o1 = in;
end
// Create the 2nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o2 = 2'd0;
else
o2 = o1;
end
// Create the 3rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o3 = 2'd0;
else
o3 = o2;
end
// Create the 4th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o4 = 2'd0;
else
o4 = o3;
end
// Create the 5th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o5 = 2'd0;
else
o5 = o4;
end
// Create the 6th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o6 = 2'd0;
else
o6 = o5;
end
// Create the 7th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o7 = 2'd0;
else
o7 = o6;
end
// Create the 8th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o8 = 2'd0;
else
o8 = o7;
end
// Create the 9th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o9 = 2'd0;
else
o9 = o8;
end
// Create the 10th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o10 = 2'd0;
else
o10 = o9;
end
// Create the 11th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o11 = 2'd0;
else
o11 = o10;
end
// Create the 12th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o12 = 2'd0;
else
o12 = o11;
end
// Create the 13th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o13 = 2'd0;
else
o13 = o12;
end
// Create the 14th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o14 = 2'd0;
else
o14 = o13;
end
// Create the 15th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o15 = 2'd0;
else
o15 = o14;
end
// Create the 16th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o16 = 2'd0;
else
o16 = o15;
end
// Create the 17th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o17 = 2'd0;
else
o17 = o16;
end
// Create the 18th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o18 = 2'd0;
else
o18 = o17;
end
// Create the 19th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o19 = 2'd0;
else
o19 = o18;
end
// Create the 20th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o20 = 2'd0;
else
o20 = o19;
end
// Create the 21st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o21 = 2'd0;
else
o21 = o20;
end
// Create the 22nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o22 = 2'd0;
else
o22 = o21;
end
// Create the 23rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o23 = 2'd0;
else
o23 = o22;
end
// Create the 24th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o24 = 2'd0;
else
o24 = o23;
end
// Create the 25th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o25 = 2'd0;
else
o25 = o24;
end
// Create the 26th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o26 = 2'd0;
else
o26 = o25;
end
// Create the 27th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o27 = 2'd0;
else
o27 = o26;
end
// Create the 28th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o28 = 2'd0;
else
o28 = o27;
end
// Create the 29th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o29 = 2'd0;
else
o29 = o28;
end
// Create the 30th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o30 = 2'd0;
else
o30 = o29;
end
// Create the 31st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o31 = 2'd0;
else
o31 = o30;
end
// Create the 32nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
out = 2'd0;
else
out = o31;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 9e18; const int mod = 4e4 + 7; vector<int> prime; bool p[100005]; void init() { p[1] = true; for (int i = 2; i <= 100005; i++) { if (!p[i]) { prime.push_back(i); for (int j = i + i; j < 100005; j += i) p[j] = true; } } } bool isp(int n) { for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return false; return true; } int main() { init(); int n; cin >> n; int s[100005]; int mx = 0; for (int i = 0; i < n; i++) scanf( %d , &s[i]), mx = max(mx, s[i]); sort(s, s + n); int ans = 1; int num[100005]; for (int i = 2; i <= mx; i++) num[i] = upper_bound(s, s + n, i) - lower_bound(s, s + n, i); for (int i = 0; i < prime.size(); i++) { int sum = 0; int x = prime[i]; for (int j = x; j <= mx; j++) { if (j % x == 0) sum += num[j]; } ans = max(ans, sum); } cout << ans << endl; } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sequencer_scc_reg_file (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter WIDTH = "";
parameter DEPTH = "";
input clock;
input [WIDTH-1:0] data;
input [DEPTH-1:0] rdaddress;
input [DEPTH-1:0] wraddress;
input wren;
output [WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [WIDTH-1:0] sub_wire0;
wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0];
altdpram altdpram_component (
.data (data),
.outclock (clock),
.rdaddress (rdaddress),
.wren (wren),
.inclock (clock),
.wraddress (wraddress),
.q (sub_wire0),
.aclr (1'b0),
.byteena (1'b1),
.inclocken (1'b1),
.outclocken (1'b1),
.rdaddressstall (1'b0),
.rden (1'b1),
.wraddressstall (1'b0));
defparam
altdpram_component.indata_aclr = "OFF",
altdpram_component.indata_reg = "INCLOCK",
altdpram_component.intended_device_family = "Stratix IV",
altdpram_component.lpm_type = "altdpram",
altdpram_component.outdata_aclr = "OFF",
altdpram_component.outdata_reg = "UNREGISTERED",
altdpram_component.ram_block_type = "MLAB",
altdpram_component.rdaddress_aclr = "OFF",
altdpram_component.rdaddress_reg = "UNREGISTERED",
altdpram_component.rdcontrol_aclr = "OFF",
altdpram_component.rdcontrol_reg = "UNREGISTERED",
altdpram_component.width = WIDTH,
altdpram_component.widthad = DEPTH,
altdpram_component.width_byteena = 1,
altdpram_component.wraddress_aclr = "OFF",
altdpram_component.wraddress_reg = "INCLOCK",
altdpram_component.wrcontrol_aclr = "OFF",
altdpram_component.wrcontrol_reg = "INCLOCK";
endmodule
|
#include <bits/stdc++.h> using namespace std; int F[100000], S[100000]; int main(int argc, char *argv[]) { int n, x, adg, i, j, k, L, A, B; cin >> n >> x; for (i = 0; i < n; i++) cin >> F[i]; for (i = 0; i < n; i++) cin >> S[i]; if (n == 1) cout << 1 << << 1; else { cout << 1 << ; sort(F, F + n); sort(S, S + n); adg = 0; j = L = 0; i = k = n - 1; while (adg < n && i >= L && k >= j) { A = F[i] + S[j]; B = S[k] + F[L]; if (A >= B && A >= x) { adg++; i--; j++; } else if (B > A && B >= x) { adg++; k--; L++; } else if (A < B) j++; else L++; } cout << adg; } return EXIT_SUCCESS; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14_V
/**
* sleep_pargate_plv: ????.
*
* Verilog wrapper for sleep_pargate_plv with size of 14 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_pargate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_14 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_14 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14_V
|
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