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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:47:54 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_shield_0/system_axi_quad_spi_shield_0_stub.v
// Design : system_axi_quad_spi_shield_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_quad_spi,Vivado 2016.4" *)
module system_axi_quad_spi_shield_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
/* synthesis syn_black_box black_box_pad_pin="ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [6:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input io0_i;
output io0_o;
output io0_t;
input io1_i;
output io1_o;
output io1_t;
input sck_i;
output sck_o;
output sck_t;
input [0:0]ss_i;
output [0:0]ss_o;
output ss_t;
output ip2intc_irpt;
endmodule
|
#include <bits/stdc++.h> using namespace std; int getDiff(int n, string s1, string s2) { int cnt = 0; for (int i = 0; i < n; i++) { if (s1[i] != s2[i]) { cnt++; } } return cnt; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; string s; cin >> s; string temp = s; for (int i = 0; i < n - 1; i++) { if (i < n - 2) { if (s[i] == s[i + 1] && s[i + 1] == s[i + 2] && s[i + 2] == s[i]) { if (s[i] == R ) { s[i + 1] = G ; } else if (s[i] == G ) { s[i + 1] = R ; } else { s[i + 1] = R ; } continue; } } if (s[i] == s[i + 1]) { if (i == 0) { if (s[i] == R ) { s[i] = G ; } else if (s[i] == G ) { s[i] = R ; } else { s[i] = R ; } } else { if (s[i - 1] == R ) { if (s[i] == B ) { s[i] = G ; } else { s[i] = B ; } } else if (s[i - 1] == B ) { if (s[i] == R ) { s[i] = G ; } else { s[i] = R ; } } else { if (s[i] == B ) { s[i] = R ; } else { s[i] = B ; } } } } } int ans = getDiff(n, s, temp); cout << ans << n ; cout << s << n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; const int len = 700, MAX = 1e7 + 10; int n, m, k, a[maxn]; int f[MAX], g[MAX]; long long ans[maxn]; struct query { int l, r, id; } q[maxn]; bool operator<(const query &a, const query &b) { if ((a.l - 1) / len != (b.l - 1) / len) return a.l < b.l; return a.r < b.r; } void enter() { cin >> n >> m >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= m; ++i) { cin >> q[i].l >> q[i].r; q[i].id = i; } sort(q + 1, q + m + 1); } int lim(int i) { return ((i - 1) / len + 1) * len; } void solve() { long long ret = 0; int rgt = 0, it, cur = 0; g[0] = 1; for (int i = 1; i <= m; ++i) { if (rgt < lim(q[i].l)) { rgt = lim(q[i].l); it = rgt + 1; memset(f, 0, sizeof(f)); f[0] = 1; cur = 0; ret = 0; } if (q[i].r <= rgt) { long long tmp = 0; for (int j = q[i].l, v = 0; j <= q[i].r; ++j) { v ^= a[j]; tmp += g[v ^ k]; ++g[v]; } ans[q[i].id] = tmp; for (int j = q[i].l, v = 0; j <= q[i].r; ++j) { v ^= a[j]; --g[v]; } continue; } while (it <= q[i].r) { cur ^= a[it++]; ret += f[cur ^ k]; ++f[cur]; } long long save = ret; --f[0]; for (int j = rgt, v = 0; j >= q[i].l; --j) { v ^= a[j]; ret += f[v ^ k]; ret += g[v ^ k]; ++g[v]; } ++f[0]; ans[q[i].id] = ret; for (int j = rgt, v = 0; j >= q[i].l; --j) { v ^= a[j]; --g[v]; } ret = save; } } int main() { ios_base ::sync_with_stdio(0); enter(); solve(); for (int i = 1; i <= m; ++i) printf( %I64d n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 9; const long long INF = 1e12; int n = 100000; long long a[MAXN]; long long f[20][MAXN]; void init() { for (int i = 1; i <= n; i++) { a[i] = i; } for (int i = 1; i <= n; i++) { for (int j = i + i; j < MAXN; j += i) { a[j] -= a[i]; } } } long long c(int l, int r) { long long ans = 0; int lst = 0; for (int i = l; i <= r; i = lst + 1) { lst = r / (r / i); ans += a[r / i] * (lst - i + 1ll); } return ans; } void work(long long *dpf, long long *dpg, int l, int r, int L, int R) { if (l > r) return; int mid = (l + r) / 2; int opt = -1; long long cost = c(min(mid - 1, R) + 1, mid); for (int i = min(mid - 1, R); i >= L; i--) { long long newf = dpf[i] + cost; if (newf < dpg[mid]) { dpg[mid] = newf; opt = i; } cost += a[mid / i]; } if (opt == -1) opt = L; work(dpf, dpg, l, (mid - 1), L, opt); work(dpf, dpg, (mid + 1), r, opt, R); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); init(); for (int i = 1; i < MAXN; i++) { a[i] += a[i - 1]; } f[0][0] = 0; memset(f, 0x3f, sizeof(f)); for (int i = 1; i <= n; i++) { f[1][i] = 1ll * i * (i + 1) / 2; } for (int i = 1; i < 16; i++) { work(f[i], f[i + 1], 1, n, 1, n); } int T; cin >> T; while (T--) { int n, k; cin >> n >> k; if (k >= 17) { cout << n << endl; } else { cout << f[k][n] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int di[] = {-1, 0, 1, 0}; const int dj[] = {0, 1, 0, -1}; const long long MOD = 1e9 + 7; const long long INF = 1e9; const double EPS = 1e-11; class UnionFind { private: vector<long long> p, rank, setSize; int numSets; public: UnionFind(int N) { setSize.assign(N, 1); numSets = N; rank.assign(N, 0); p.assign(N, 0); for (int i = 0; i < N; i++) p[i] = i; } int findSet(int i) { return (p[i] == i) ? i : (p[i] = findSet(p[i])); } bool isSameSet(int i, int j) { return findSet(i) == findSet(j); } void unionSet(int i, int j) { if (!isSameSet(i, j)) { numSets--; int x = findSet(i), y = findSet(j); if (rank[x] > rank[y]) { p[y] = x; setSize[x] += setSize[y]; } else { p[x] = y; setSize[y] += setSize[x]; if (rank[x] == rank[y]) rank[y]++; } } } int numDisjointSets() { return numSets; } int sizeOfSet(int i) { return setSize[findSet(i)]; } }; int main() { ios::sync_with_stdio(false), cin.tie(0); int n; cin >> n; vector<long long> num(n); map<int, int> idx, vis; for (int i = 0; i < n; ++i) cin >> num[i], idx[num[i]] = i; vector<long long> num2 = num; sort(num2.begin(), num2.end()); UnionFind dsu(n); for (int i = 0; i < n; ++i) { swap(num[i], num[idx[num2[i]]]); dsu.unionSet(i, idx[num2[i]]); } for (int i = 0; i < n; ++i) num[i] = dsu.findSet(i); map<int, vector<long long> > r; for (int i = 0; i < n; ++i) r[num[i]].push_back(i + 1); cout << r.size() << endl; for (map<int, vector<long long> >::iterator i = r.begin(); i != r.end(); ++i) { cout << i->second.size() << ; for (int j = 0; j < i->second.size(); ++j) cout << i->second[j] << n [j == i->second.size() - 1]; } } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int dx[4] = {0, 0, 1, -1}; const int dy[4] = {1, -1, 0, 0}; int n, a, b, c; string s; map<pair<int, pair<int, int> >, int> dic; bool bo1 = false, bo2 = false, bo3 = false; void dfs(int a, int b, int c) { pair<int, pair<int, int> > temp = make_pair(a, make_pair(b, c)); if (dic[temp]) return; dic[temp] = 1; if (a + b + c == 1) { if (a == 1) bo1 = true; if (b == 1) bo2 = true; if (c == 1) bo3 = true; return; } if (a > 0 && b > 0) dfs(a - 1, b - 1, c + 1); if (a > 0 && c > 0) dfs(a - 1, b + 1, c - 1); if (b > 0 && c > 0) dfs(a + 1, b - 1, c - 1); if (a > 1) dfs(a - 1, b, c); if (b > 1) dfs(a, b - 1, c); if (c > 1) dfs(a, b, c - 1); } int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n; cin >> s; for (int i = 0; i < (int)s.size(); i++) { if (s[i] == B ) a++; if (s[i] == G ) b++; if (s[i] == R ) c++; } dfs(a, b, c); if (bo1) cout << B ; if (bo2) cout << G ; if (bo3) cout << R ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long ret = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) ret = ret * 10 + ch - 0 , ch = getchar(); return ret * f; } const long long maxn = 100005; long long n, A, cj, cm, m; pair<long long, long long> a[maxn]; long long sum[maxn]; long long ans = 0, ansx = -1, ansy = -1; inline bool cmp_value(pair<long long, long long> aa, pair<long long, long long> bb) { return aa.first < bb.first; } inline bool cmp_id(pair<long long, long long> aa, pair<long long, long long> bb) { return aa.second < bb.second; } inline long long get_all_sum(long long x, long long up) { long long L = 1, R = up; long long ret = 0; while (L <= R) { long long mid = ((R - L) >> 1) + L; if (a[mid].first > x) R = mid - 1; else ret = x * mid - sum[mid], L = mid + 1; } return ret; } signed main() { n = read(); A = read(); cj = read(); cm = read(); m = read(); for (long long i = 1; i <= n; i++) a[i].first = read(), a[i].second = i; sort(a + 1, a + 1 + n, cmp_value); for (long long i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i].first; long long need = 0; for (long long i = n + 1; i >= 1; i--) { if (i <= n) need += A - a[i].first; if (need > m) break; long long L = 0, R = A; while (L <= R) { long long mid = ((R - L) >> 1) + L; long long all_sum = get_all_sum(mid, i - 1); if (all_sum > m - need) R = mid - 1; else { if ((n - i + 1) * cj + mid * cm > ans) { ans = (n - i + 1) * cj + mid * cm; ansx = mid; ansy = i; } L = mid + 1; } } } printf( %lld n , ans); if (ansx != -1 && ansy != -1) { for (long long i = 1; i < ansy; i++) a[i].first = max(ansx, a[i].first); for (long long i = ansy; i <= n; i++) a[i].first = A; } sort(a + 1, a + 1 + n, cmp_id); for (long long i = 1; i <= n; i++) printf( %lld , a[i].first); printf( n ); return 0; } |
#include <bits/stdc++.h> int arr1[500005]; using namespace std; int main() { int t; cin >> t; for (int i = 1; i <= t; i++) { int a; cin >> a; arr1[a] = i; } long long int sum = 0; for (int i = 1; i < t; i++) { sum += abs(arr1[i] - arr1[i + 1]); } cout << sum; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFXTP_PP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_PP_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module filesystem_encrypt_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
output wire [127:0] iv_V,
output wire [31:0] length_r,
output wire length_r_ap_vld
);
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of iv_V
// bit 31~0 - iv_V[31:0] (Read/Write)
// 0x14 : Data signal of iv_V
// bit 31~0 - iv_V[63:32] (Read/Write)
// 0x18 : Data signal of iv_V
// bit 31~0 - iv_V[95:64] (Read/Write)
// 0x1c : Data signal of iv_V
// bit 31~0 - iv_V[127:96] (Read/Write)
// 0x20 : reserved
// 0x24 : Data signal of length_r
// bit 31~0 - length_r[31:0] (Read/Write)
// 0x28 : Control signal of length_r
// bit 0 - length_r_ap_vld (Read/Write/SC)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_IV_V_DATA_0 = 6'h10,
ADDR_IV_V_DATA_1 = 6'h14,
ADDR_IV_V_DATA_2 = 6'h18,
ADDR_IV_V_DATA_3 = 6'h1c,
ADDR_IV_V_CTRL = 6'h20,
ADDR_LENGTH_R_DATA_0 = 6'h24,
ADDR_LENGTH_R_CTRL = 6'h28,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg [127:0] int_iv_V = 'b0;
reg [31:0] int_length_r = 'b0;
reg int_length_r_ap_vld = 1'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_IV_V_DATA_0: begin
rdata <= int_iv_V[31:0];
end
ADDR_IV_V_DATA_1: begin
rdata <= int_iv_V[63:32];
end
ADDR_IV_V_DATA_2: begin
rdata <= int_iv_V[95:64];
end
ADDR_IV_V_DATA_3: begin
rdata <= int_iv_V[127:96];
end
ADDR_LENGTH_R_DATA_0: begin
rdata <= int_length_r[31:0];
end
ADDR_LENGTH_R_CTRL: begin
rdata[0] <= int_length_r_ap_vld;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign iv_V = int_iv_V;
assign length_r = int_length_r;
assign length_r_ap_vld = int_length_r_ap_vld;
// int_iv_V[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_iv_V[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IV_V_DATA_0)
int_iv_V[31:0] <= (WDATA[31:0] & wmask) | (int_iv_V[31:0] & ~wmask);
end
end
// int_iv_V[63:32]
always @(posedge ACLK) begin
if (ARESET)
int_iv_V[63:32] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IV_V_DATA_1)
int_iv_V[63:32] <= (WDATA[31:0] & wmask) | (int_iv_V[63:32] & ~wmask);
end
end
// int_iv_V[95:64]
always @(posedge ACLK) begin
if (ARESET)
int_iv_V[95:64] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IV_V_DATA_2)
int_iv_V[95:64] <= (WDATA[31:0] & wmask) | (int_iv_V[95:64] & ~wmask);
end
end
// int_iv_V[127:96]
always @(posedge ACLK) begin
if (ARESET)
int_iv_V[127:96] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IV_V_DATA_3)
int_iv_V[127:96] <= (WDATA[31:0] & wmask) | (int_iv_V[127:96] & ~wmask);
end
end
// int_length_r[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_length_r[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_LENGTH_R_DATA_0)
int_length_r[31:0] <= (WDATA[31:0] & wmask) | (int_length_r[31:0] & ~wmask);
end
end
// int_length_r_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_length_r_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_LENGTH_R_CTRL && WSTRB[0] && WDATA[0])
int_length_r_ap_vld <= 1'b1;
else
int_length_r_ap_vld <= 1'b0; // self clear
end
end
//------------------------Memory logic-------------------
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[500500], y[500500]; long long minl[500500], maxl[500500], minr[500500], maxr[500500], ll, rr; int n; pair<long long, long long> a[500500]; bool ok(long long M) { int j = 0; for (int i = 0; i < n; i++) { while ((j < n) && (a[j].first - a[i].first <= M)) j++; if (max((i > 0) ? maxl[i - 1] : -10000000000LL, (j < n) ? maxr[j] : -10000000000LL) - min((i > 0) ? minl[i - 1] : 10000000000LL, (j < n) ? minr[j] : 10000000000LL) <= M) return 1; } return 0; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d%d , &x[i], &y[i]); for (int i = 0; i < n; i++) a[i] = make_pair(x[i] - y[i], x[i] + y[i]); sort(a, a + n); for (int i = 0; i < n; i++) { minl[i] = min((i > 0) ? minl[i - 1] : 10000000000LL, a[i].second); maxl[i] = max((i > 0) ? maxl[i - 1] : -10000000000LL, a[i].second); } for (int i = n - 1; i >= 0; i--) { minr[i] = min((i + 1 < n) ? minr[i + 1] : 10000000000LL, a[i].second); maxr[i] = max((i + 1 < n) ? maxr[i + 1] : -10000000000LL, a[i].second); } ll = 0; rr = 3e9; for (int it = 0; it < 40; it++) if (ok((ll + rr) / 2)) rr = (ll + rr) / 2; else ll = (ll + rr) / 2; if (!ok(ll)) ll = rr; printf( %.10lf n , ll * 1.0 / 2); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_PP_V |
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module sync_w2r
#(
parameter ASIZE = 4
)(
input wire rclk,
input wire rrst_n,
output reg [ASIZE:0] rq2_wptr,
input wire [ASIZE:0] wptr
);
reg [ASIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n) begin
if (!rrst_n)
{rq2_wptr,rq1_wptr} <= 0;
else
{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
end
endmodule
`resetall
|
module top();
reg consumer_iclk;
reg producer_iclk;
wire cr;
wire [3:0] cd;
wire [3:0] pd;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
begin
/*
consumer_iclk = 0;
producer_iclk = 0;
cr =0;
cd=0;
pd=0;
*/
#5000 $finish;
end
producer p1(
pd
);
fifo f1(
cd,
pd,
cr
);
consumer c1(
cr,
cd
);
endmodule
//------------------------------
//PRODUCER IS PRODUCING DATA
module producer (/*producer_iclk,*/producer_data);
//input producer_iclk;
output producer_data;
reg producer_iclk;
reg [3:0] producer_data;
//assign producer_data = 0;
reg [3:0] i = 4'b0000;
always @(producer_iclk)
begin
producer_data = producer_data + 1;
end
initial
begin
producer_data = 0;
producer_iclk = 0;
//$monitor("time=%t data produced = %b clk=%b",$time,producer_data,producer_iclk);
//#100 $finish;
end
//internal 5 unit clk
always
begin
#5 producer_iclk = ~(producer_iclk);
end
endmodule
//-------------------------------
module fifo(consumer_data,producer_data, consumer_req);
input consumer_req;
input producer_data;
output consumer_data;
reg [3:0] consumer_data;
reg [3:0] producer_data;
reg consumer_req;
int i;
int j;
int last;
int start;
int diff;
int last_s;
int start_s;
reg [3:0] queue [9:0];
initial
begin
assign last_s = last % 10;
assign start_s = start % 10;
assign diff = last - start;
//$monitor("producer data = %b %d",producer_data,producer_data);
//producer_data = 0;
#30for(j=0;j<10;j++)
begin
//$display("queue[%d] =%d at time =%t",j,queue[j],$time);
end
end
//add_data thingy
always @ (producer_data)
if((diff < 10))
begin
begin
queue[last_s] = producer_data;
//$display("add queue[%d] is %d",last_s,queue[last_s]);
#0 last = last +1;
end
end else begin
$finish;
end
//pop data thingy
always @(consumer_req)
begin
if(consumer_req == 1)
begin
if(diff != 0)
begin
// $display("pop queue[%d] = %d",start_s,queue[start_s]);
consumer_data = queue[start_s];
//$display("consumer data = %d",consumer_data);
#0 start = start +1;
end
/*
queue[start] = consumer_data;
#0 start = start + 1;
$display("start = %d at time = %t",start,$time);
$display("consumer data = %d",consumer_data);
*/
end
end
endmodule
//------------------------
module consumer(/*consumer_iclk,*/consumer_req,consumer_data);
//input consumer_iclk;
input consumer_data;
output consumer_req;
reg consumer_iclk;
reg [3:0] consumer_data;
reg consumer_req;
// consumer_req = 0;
always @(consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
begin
//consumer_data = 0;
consumer_req=0;
consumer_iclk =1;
$monitor("data consumed : %d at time = %t", consumer_data,$time);
//#20 $finish;
end
//internal clk
always
begin
#10 consumer_iclk = ~consumer_iclk;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [34:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [34:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [9:0] sub_wire1;
wire [34:0] sub_wire2;
wire rdempty = sub_wire0;
wire [9:0] wrusedw = sub_wire1[9:0];
wire [34:0] q = sub_wire2[34:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 35,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "35"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "35"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "35"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 35 0 INPUT NODEFVAL data[34..0]
// Retrieval info: USED_PORT: q 0 0 35 0 OUTPUT NODEFVAL q[34..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
// Retrieval info: CONNECT: @data 0 0 35 0 data 0 0 35 0
// Retrieval info: CONNECT: q 0 0 35 0 @q 0 0 35 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n; long long N[100006]; long long sum[1000006], S[1000006]; long long t[1000006]; long long t1[1000006]; long long lowbit(long long u) { return u & (-u); } void add(long long u, long long w) { while (u <= n) { t[u] += w; u += lowbit(u); } } long long Find(long long u) { long long ans = 0; while (u) { ans += t[u]; u -= lowbit(u); } return ans; } void add1(long long u, long long w) { while (u <= n) { t1[u] += w; u += lowbit(u); } } long long Find1(long long u) { long long ans = 0; while (u) { ans += t1[u]; u -= lowbit(u); } return ans; } double ans; signed main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld , &N[i]); for (long long i = 1; i <= n; i++) { sum[i] += Find(n) - Find(N[i]); S[i] += Find1(n) - Find1(N[i]); if (sum[i] != 0) ans += ((double)(n * (n + 1ll) / 2ll) * sum[i] - (double)(n - i + 1ll) * S[i]) / (double)(n * (n + 1ll) / 2ll); add(N[i], 1); add1(N[i], i); } for (long long i = 2; i <= n; i++) ans += (double)((i - 1) * i) / 2.00 / 2.00 * (double)(n - i + 1) / (double)(n * (n + 1ll) / 2ll); printf( %.12lf n , ans); return 0; } |
#include <bits/stdc++.h> #define rep(i,a,b) for(int i = (a); i < (b); ++i) #define rrep(i,a,b) for(int i = (b); i --> (a);) #define sz(v) int(v.size()) using namespace std; string inf, zero; string add(string x, string y, int init){ string res(sz(x), ? ); int todo = init; rrep(i,0,sz(x)){ todo += x[i] + y[i] - 2 * 0 ; res[i] = todo % 2 + 0 ; todo /= 2; } if(todo) return inf; return res; } int main(){ int n, b; cin >> n >> b; inf = string(b, 1 ); zero = string(b, 0 ); vector<string> fibs = {zero, zero}; // fibonacci numbers minus one while(fibs.back() < inf) fibs.push_back(add(fibs.back(), fibs[sz(fibs)-2], 1)); int todo = sz(fibs)-1; deque<pair<int, bool>> ls; rep(i,0,n) ls.push_back({i+1, true}); string lb = zero; // current lower bound while(!ls.empty()){ string ans; if(add(lb, fibs[todo], 0) == inf) ans = no ; else { cout << ls.back().first << << add(lb, fibs[max(0, todo)], 0) << endl; cin >> ans; } if(ans == yes ){ lb = add(lb, fibs[todo], 1); while(!ls.empty() && ls[0].second){ ls.pop_front(); todo += 2; } if(ls.empty()) break; ls[0].second = true; } else { ls.push_front({ls.back().first, false}); ls.pop_back(); } if(--todo <= 0){ todo += ls[0].second ? 2 : 1; ls.pop_front(); } } cout << 0 << << lb << endl; } |
#include <bits/stdc++.h> using namespace std; const long MAX_N = 1e3 + 1; long n, m, h; long aw[MAX_N]; long bw[MAX_N]; vector<long> g[MAX_N]; bool v[MAX_N]; vector<long> st; vector<pair<pair<long, long>, long> > ans; void add_edge(long a, long b) { g[a].push_back(b); g[b].push_back(a); } void try_flow(long i, long need) { if (i + 1 >= st.size()) return; long a = st[i], b = st[i + 1]; long can = min(need, h - aw[b]); if (can > 0) { ans.push_back(make_pair(make_pair(a, b), can)); } try_flow(i + 1, need); if (need - can > 0) { ans.push_back(make_pair(make_pair(a, b), need - can)); } } void flow() { long a = st[0]; long b = st[st.size() - 1]; long need = min(aw[a] - bw[a], bw[b] - aw[b]); if (need > 0) { try_flow(0, need); aw[a] -= need; aw[b] += need; } } void dfs(long a) { v[a] = true; st.push_back(a); if (aw[a] < bw[a]) flow(); for (size_t i = 0; i < g[a].size(); i++) { long b = g[a][i]; if (!v[b]) dfs(b); } st.pop_back(); } int main() { cin >> n >> h >> m; for (long i = 1; i <= n; i++) { cin >> aw[i]; } for (long i = 1; i <= n; i++) { cin >> bw[i]; } for (long i = 1; i <= m; i++) { long x, y; cin >> x >> y; add_edge(x, y); } for (long i = 1; i <= n; i++) { if (aw[i] > bw[i]) { for (long j = 1; j <= n; j++) v[j] = false; dfs(i); } } for (long i = 1; i <= n; i++) { if (aw[i] != bw[i]) { cout << NO ; return 0; } } cout << ans.size() << endl; for (size_t i = 0; i < ans.size(); i++) { cout << ans[i].first.first << << ans[i].first.second << << ans[i].second << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; inline int in() { int x; scanf( %d , &x); return x; } inline long long lin() { long long x; scanf( %I64d , &x); return x; } vector<int> G[N + N]; pair<int, int> edg[N + N]; int n, k, start; int inp[N + N]; int st[N + N], T = 1; long long res, f[N + N]; void dfs(int u, int par) { st[u] = T++; if (inp[u] == 1) f[u]++; for (int i = 0; i < (int)G[u].size(); i++) { int v = G[u][i]; if (v != par) { dfs(v, u); f[u] += f[v]; res += min(f[v], 2LL * k - f[v]); } } } int main() { n = in(); k = in(); for (int i = 1; i <= k + k; i++) { int x = in(); inp[x] = 1; } for (int i = 1; i <= n - 1; i++) { int u = in(), v = in(); G[u].push_back(v); G[v].push_back(u); edg[i] = make_pair(u, v); } res = 0; dfs(1, -1); printf( %I64d n , res); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLRTP_BEHAVIORAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire B2 nand2_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_FUNCTIONAL_PP_V |
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx espresso fetch unit
Fetch insn, advance PC (or take new branch address) on padv_i.
What we might want to do is have a 1-insn buffer here, so when the current
insn is fetched, but the main pipeline doesn't want it yet
indicate ibus errors
Copyright (C) 2012 Authors
Author(s): Julius Baxter <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_fetch_espresso
(/*AUTOARG*/
// Outputs
ibus_adr_o, ibus_req_o, ibus_burst_o, decode_insn_o,
next_fetch_done_o, fetch_rfa_adr_o, fetch_rfb_adr_o, pc_fetch_o,
pc_fetch_next_o, decode_except_ibus_err_o, fetch_advancing_o,
// Inputs
clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, padv_i,
branch_occur_i, branch_dest_i, du_restart_i, du_restart_pc_i,
fetch_take_exception_branch_i, execute_waiting_i, du_stall_i,
stepping_i
);
parameter OPTION_OPERAND_WIDTH = 32;
parameter OPTION_RF_ADDR_WIDTH = 5;
parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
`OR1K_RESET_VECTOR,8'd0};
input clk, rst;
// interface to ibus
output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o;
output ibus_req_o;
output ibus_burst_o;
input ibus_err_i;
input ibus_ack_i;
input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i;
// pipeline control input
input padv_i;
// interface to decode unit
output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o;
// Indication to pipeline control that the fetch is valid
output next_fetch_done_o;
output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;
output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;
// Signal back to the control
output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_o;
output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;
// branch/jump indication
input branch_occur_i;
input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i;
// restart signals from debug unit
input du_restart_i;
input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i;
input fetch_take_exception_branch_i;
input execute_waiting_i;
// CPU is stalled
input du_stall_i;
// We're single stepping - this should cause us to fetch only a single insn
input stepping_i;
// instruction ibus error indication out
output reg decode_except_ibus_err_o;
output fetch_advancing_o;
// registers
reg [OPTION_OPERAND_WIDTH-1:0] pc_fetch;
reg fetch_req;
reg next_insn_buffered;
reg [OPTION_OPERAND_WIDTH-1:0] insn_buffer;
reg branch_occur_r;
reg bus_access_done_re_r;
reg advancing_into_branch;
reg bus_access_done_r;
reg wait_for_exception_after_ibus_err;
wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next;
wire bus_access_done;
wire bus_access_done_fe;
wire branch_occur_re;
wire awkward_transition_to_branch_target;
wire taking_branch;
wire jal_buffered;
wire retain_fetch_pc;
assign taking_branch = branch_occur_i & padv_i;
assign bus_access_done = (ibus_ack_i | ibus_err_i) & !(taking_branch);
assign pc_fetch_next = pc_fetch + 4;
assign ibus_adr_o = pc_fetch;
assign ibus_req_o = fetch_req;
assign ibus_burst_o = 0;
assign fetch_advancing_o = (padv_i | fetch_take_exception_branch_i |
stepping_i) &
next_fetch_done_o;
// Early RF address fetch
assign fetch_rfa_adr_o = insn_buffer[`OR1K_RA_SELECT];
assign fetch_rfb_adr_o = insn_buffer[`OR1K_RB_SELECT];
assign jal_buffered = insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JALR ||
insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JAL;
assign retain_fetch_pc = jal_buffered & bus_access_done;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
pc_fetch <= OPTION_RESET_PC;
else if (fetch_take_exception_branch_i |
(((bus_access_done & !ibus_err_i) | taking_branch) &
(!execute_waiting_i | !next_insn_buffered) &
!retain_fetch_pc) |
awkward_transition_to_branch_target |
du_restart_i)
// next PC - are we going somewhere else or advancing?
pc_fetch <= du_restart_i ? du_restart_pc_i :
(fetch_take_exception_branch_i | taking_branch) ?
branch_dest_i : pc_fetch_next;
// Actually goes to pipeline control
assign pc_fetch_o = pc_fetch;
assign pc_fetch_next_o = pc_fetch_next;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
fetch_req <= 1;
else if (fetch_take_exception_branch_i | du_restart_i)
fetch_req <= 1;
else if (padv_i)
// Force de-assert of req signal when branching.
// This is to stop (ironically) the case where we've got the
// instruction we're branching to already coming in on the bus,
// which we usually don't assume will happen.
// TODO: fix things so that we don't have to force a penalty to make
// it work properly.
fetch_req <= !branch_occur_i & !du_stall_i;
else if (du_stall_i)
fetch_req <= fetch_req & !bus_access_done;
else if (!fetch_req & !execute_waiting_i &
!wait_for_exception_after_ibus_err & !retain_fetch_pc &
!du_stall_i & !stepping_i)
fetch_req <= 1;
else if (bus_access_done & (fetch_take_exception_branch_i |
execute_waiting_i | ibus_err_i | stepping_i))
fetch_req <= 0;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
begin
bus_access_done_r <= 0;
branch_occur_r <= 0;
end
else
begin
bus_access_done_r <= bus_access_done;
branch_occur_r <= branch_occur_i;
end
always @(posedge clk `OR_ASYNC_RST)
if (rst)
advancing_into_branch <= 0;
else
advancing_into_branch <= fetch_advancing_o & branch_occur_i;
assign next_fetch_done_o = (bus_access_done_r | next_insn_buffered) &
// Whenever we've just changed the fetch PC to
// take a branch this will gate off any ACKs we
// might get (legit or otherwise) from where we're
// getting our instructions from (bus/cache).
!(advancing_into_branch);
assign branch_occur_re = branch_occur_i & !branch_occur_r;
/* When this occurs we had the insn burst stream finish just as we
had a new branch address requested. Because the control logic will
immediately continue onto the delay slot instruction, the branch target
is only valid for 1 cycle. The PC out to the bus/cache will then need
to change 1 cycle after it requested the insn after the delay slot.
This is annoying for the bus control/cache logic, but should result in
less cycles wasted fetching something we don't need, and as well reduce
the number of flops as we don't need to save the target PC which we had
for only 1 cycle */
assign awkward_transition_to_branch_target = branch_occur_re &
bus_access_done_fe;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
else if (fetch_take_exception_branch_i | (du_stall_i & !execute_waiting_i))
// Put a NOP in the pipeline when starting exception - remove any state
// which may be causing the exception
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
else if ((padv_i & (
bus_access_done_r |
bus_access_done |
next_insn_buffered
) &
!branch_occur_r ) |
// This case is when we stalled to get the delay-slot instruction
// and we don't get enough padv to push it through the buffer
(branch_occur_i & padv_i & bus_access_done_re_r) |
(bus_access_done_fe & stepping_i))
decode_insn_o <= insn_buffer;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
decode_except_ibus_err_o <= 0;
else if ((padv_i | fetch_take_exception_branch_i) & branch_occur_i |
du_stall_i)
decode_except_ibus_err_o <= 0;
else if (fetch_req)
decode_except_ibus_err_o <= ibus_err_i;
// Register rising edge on bus_access_done
always @(posedge clk `OR_ASYNC_RST)
if (rst)
bus_access_done_re_r <= 0;
else
bus_access_done_re_r <= bus_access_done & !bus_access_done_r;
assign bus_access_done_fe = !bus_access_done & bus_access_done_r;
/* If insn_buffer contains the next insn we need, save that information
here */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
next_insn_buffered <= 0;
else if (fetch_take_exception_branch_i)
next_insn_buffered <= 0;
else if (padv_i)
// Next instruction is usually buffered when we've got bus ack and
// pipeline advance, except when we're branching (usually throw
// away the fetch when branch is being indicated)
next_insn_buffered <= ibus_ack_i & !branch_occur_i;
else if (ibus_ack_i & execute_waiting_i)
next_insn_buffered <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
insn_buffer <= {`OR1K_OPCODE_NOP,26'd0};
else if (ibus_ack_i & (!execute_waiting_i | !next_insn_buffered) &
// Don't buffer instruction after delay slot instruction
// (usually we're receiving it as taking branch is asserted)
// it could be another jump instruction and having it in
// the insn_buffer has annoying side-effects.
!taking_branch)
insn_buffer <= ibus_dat_i;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
wait_for_exception_after_ibus_err <= 0;
else if (fetch_take_exception_branch_i)
wait_for_exception_after_ibus_err <= 0;
else if (ibus_err_i)
wait_for_exception_after_ibus_err <= 1;
endmodule // mor1kx_fetch_espresso
|
module decoder(INST, DR, SA, SB, IMM, MB, FS, MD, LD, MW, BS, OFF, HALT);
input [15:0] INST;
output [2:0] DR;
output [2:0] SA;
output [2:0] SB;
output [5:0] IMM;
output MB;
output [2:0] FS;
output MD;
output LD;
output MW;
output [2:0] BS;
output [5:0] OFF;
output HALT;
reg [2:0] DR;
reg [2:0] SA;
reg [2:0] SB;
reg MB;
reg [2:0] FS;
reg MD;
reg LD;
reg MW;
reg [2:0] BS;
reg [5:0] OFF;
reg HALT;
reg [5:0] IMM;
wire [3:0] OP;
wire [2:0] RS;
wire [2:0] RT;
wire [2:0] RD;
wire [2:0] FUNCT;
wire [5:0] IMM_INST;
assign OP = INST[15:12];
assign RS = INST[11:9];
assign RT = INST[8:6];
assign RD = INST[5:3];
assign FUNCT = INST[2:0];
assign IMM_INST = INST[5:0];
always @(*) begin
case (OP)
4'b0000: begin
DR = 3'b0;
SA = 3'b0;
SB = 3'b0;
MB = 1'b0;
FS = 3'b0;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = (FUNCT == 3'b001) ? 1'b1 : 1'b0;
IMM = IMM_INST;
end
4'b0010: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b1;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0100: begin
DR = 3'b0;
SA = RS;
SB = RT;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b0;
MW = 1'b1;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0101: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0110: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b101;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0111: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b110;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b1000: begin
DR = 3'b0;
SA = RS;
SB = RT;
MB = 1'b0;
FS = 3'b001;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b000;
OFF = IMM_INST;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b1001: begin
DR = 3'b0;
SA = RS;
SB = RT;
MB = 1'b0;
FS = 3'b001;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b001;
OFF = IMM_INST;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b1010: begin
DR = 3'b0;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b010;
OFF = IMM_INST;
HALT = 1'b0;
IMM = 6'b0;
end
4'b1011: begin
DR = 3'b0;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b011;
OFF = IMM_INST;
HALT = 1'b0;
IMM = 6'b0;
end
4'b1111: begin
DR = RD;
SA = RS;
SB = RT;
MB = 1'b0;
FS = FUNCT;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
default: begin
DR = 3'b0;
SA = 3'b0;
SB = 3'b0;
MB = 1'b0;
FS = 3'b0;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5010; int n; int a[maxn], f[maxn]; long long b[maxn]; int main() { int i, ans = 0, j; long long w; scanf( %d , &n); for (i = 1; i <= n; ++i) { scanf( %I64d , &w); while (w % 2 == 0) ++a[i], w /= 2; b[i] = w; } for (i = 1; i <= n; ++i) { for (j = 1; j < i; ++j) if ((a[i] == a[j] + i - j || a[i] < i - j) && b[j] % b[i] == 0) f[i] = max(f[i], f[j]); ans = max(ans, ++f[i]); } printf( %d , n - ans); return 0; } |
// This module interfaces the minimig's synchronous bus to the asynchronous sram
// on the Minimig rev1.0 board
//
// JB:
// 2008-09-23 - generation of write strobes moved to clk28m clock domain
module minimig_sram_bridge
(
//clocks
input clk, // 28 MHz system clock
input c1, // clock enable signal
input c3, // clock enable signal
//chipset internal port
input [7:0] bank, // memory bank select (512KB)
input [18:1] address_in, // bus address
input [15:0] data_in, // bus data in
output [15:0] data_out, // bus data out
input rd, // bus read
input hwr, // bus high byte write
input lwr, // bus low byte write
//SRAM external signals
// output reg _bhe = 1, // sram upper byte
// output reg _ble = 1, // sram lower byte
// output reg _we = 1, // sram write enable
// output reg _oe = 1, // sram output enable
// output reg [3:0] _ce = 4'b1111, // sram chip enable
// output reg [19:1] address, // sram address bus
// inout [15:0] data // sram data das
output _bhe, // sram upper byte
output _ble, // sram lower byte
output _we, // sram write enable
output _oe, // sram output enable
output [21:1] address, // sram address bus
output [15:0] data, // sram data das
input [15:0] ramdata_in // sram data das in
);
/* basic timing diagram
phase : Q0 : Q1 : Q2 : Q3 : Q0 : Q1 : Q2 : Q3 : Q0 : Q1 :
: : : : : : : : : : :
___________ ___________ ___________
clk ___/ \___________/ \___________/ \_____ (7.09 MHz - dedicated clock)
: : : : : : : : : : :
__ __ __ __ __ __ __ __ __ __ __
clk28m ___/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ (28.36 MHz - dedicated clock)
: : : : : : : : : : :
___________ ___________ ___________
c1 ___/ \___________/ \___________/ \_____ (7.09 MHz)
: : : : : : : : : : :
___________ ___________ ___________
c3 _________/ \___________/ \___________/ (7.09 MHz)
: : : : : : : : : : :
_________ _____ _____
_ce \_________________/ \_________________/ \___________ (ram chip enable)
: : : : : : : : : : :
_______________ ___________ ___________
_we \___________/ \___________/ \_____ (ram write strobe)
: : : : : : : : : : :
_________ _____ _____
_oe \_________________/ \_________________/ \___________ (ram output enable)
: : : : : : : : : : :
_________________ _________________ ___________
doe _________/ \_____/ \_____/ (data bus output enable)
: : : : : : : : : : :
*/
wire enable; // indicates memory access cycle
reg doe; // data output enable (activates ram data bus buffers during write cycle)
// generate enable signal if any of the banks is selected
//assign enable = |bank[7:0];
assign enable = (bank[7:0]==8'b00000000) ? 1'b0 : 1'b1;
// generate _we
assign _we = (!hwr && !lwr) | !enable;
//always @(posedge clk28m)
// if (!c1 && !c3) // deassert write strobe in Q0
// _we <= 1'b1;
// else if (c1 && c3 && enable && !rd) //assert write strobe in Q2
// _we <= 1'b0;
// generate ram output enable _oe
assign _oe = !rd | !enable;
//assign _oe = !enable;
//always @(posedge clk28m)
// if (!c1 && !c3) // deassert output enable in Q0
// _oe <= 1'b1;
// else if (c1 && !c3 && enable && rd) //assert output enable in Q1 during read cycle
// _oe <= 1'b0;
// generate ram upper byte enable _bhe
assign _bhe = !hwr | !enable;
//always @(posedge clk28m)
// if (!c1 && !c3) // deassert upper byte enable in Q0
// _bhe <= 1'b1;
// else if (c1 && !c3 && enable && rd) // assert upper byte enable in Q1 during read cycle
// _bhe <= 1'b0;
// else if (c1 && c3 && enable && hwr) // assert upper byte enable in Q2 during write cycle
// _bhe <= 1'b0;
// generate ram lower byte enable _ble
assign _ble = !lwr | !enable;
//always @(posedge clk28m)
// if (!c1 && !c3) // deassert lower byte enable in Q0
// _ble <= 1'b1;
// else if (c1 && !c3 && enable && rd) // assert lower byte enable in Q1 during read cycle
// _ble <= 1'b0;
// else if (c1 && c3 && enable && lwr) // assert lower byte enable in Q2 during write cycle
// _ble <= 1'b0;
//generate data buffer output enable
always @(posedge clk)
if (!c1 && !c3) // deassert output enable in Q0
doe <= 1'b0;
else if (c1 && !c3 && enable && !rd) // assert output enable in Q1 during write cycle
doe <= 1'b1;
// generate sram chip selects (every sram chip is 512K x 16bits)
//assign _ce[3:0] = {~|bank[7:6],~|bank[5:4],~|bank[3:2],~|bank[1:0]};
//always @(posedge clk28m)
// if (!c1 && !c3) // deassert chip selects in Q0
// _ce[3:0] <= 4'b1111;
// else if (c1 && !c3) // assert chip selects in Q1
// _ce[3:0] <= {~|bank[7:6],~|bank[5:4],~|bank[3:2],~|bank[1:0]};
// ram address bus
assign address = {bank[7]|bank[6]|bank[5]|bank[4], bank[7]|bank[6]|bank[3]|bank[2], bank[7]|bank[5]|bank[3]|bank[1], address_in[18:1]};
//assign address = {bank[7]|bank[5]|bank[3]|bank[1],address_in[18:1]};
//always @(posedge clk28m)
// if (c1 && !c3 && enable) // set address in Q1
// address <= {bank[7]|bank[5]|bank[3]|bank[1],address_in[18:1]};
// data_out multiplexer
assign data_out[15:0] = (enable && rd) ? ramdata_in[15:0] : 16'b0000000000000000;
// data bus output buffers
//assign data[15:0] = doe ? data_in[15:0] : 16'bz;
assign data[15:0] = data_in[15:0];
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
ram
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE(`ICACHE_ENABLED),
.ENABLE_DCACHE(`DCACHE_ENABLED),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
.uart_tx_o(),
.uart_rx_i(1'b0),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; char ch[111111]; int main() { scanf( %d%d , &n, &k); scanf( %s , ch); int pos = 0; for (int act = 0; act <= 1000000 && act < k && pos < n - 1; ++act) { if (act >= 1000000 && act % 2 == k % 2) break; while (pos < n - 1 && !(ch[pos] == 4 && ch[pos + 1] == 7 )) pos++; if (pos == n - 1) break; if (pos % 2 == 0) ch[pos] = ch[pos + 1] = 4 ; else ch[pos] = ch[pos + 1] = 7 ; --pos; if (pos < 0) pos = 0; } printf( %s n , ch); } |
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int> > H; vector<int> Ans[1000010]; int S[1000010]; int main() { scanf( %d%d , &n, &m), H.resize(m); int tot = 0; for (int i = 0; i < m; i++) scanf( %d , &H[i].first), tot += H[i].first, H[i].second = i + 1; if (tot % n != 0) H[0].first += n - tot % n, tot += n - tot % n; int k = tot / n, tmpk = k; printf( %d n , k); sort(H.begin(), H.end()); int detert = 0; for (int cnt = 0, t = 0;; cnt++) { while (t != H.size() && H[t].first == 0) t++; if (t == H.size()) break; if (H.back().first >= n) { for (int j = detert + 1; j <= m; j++) Ans[j].push_back(H.back().second); H.back().first -= n; pair<int, int> tmp = H.back(); for (int j = (int)H.size() - 2; j >= t - 1; j--) if (j != t - 1 && H[j] > tmp) H[j + 1] = H[j]; else { H[j + 1] = tmp; break; } k--; continue; } int mn = H[t].first; S[++detert] = mn; n -= mn; for (int i = t, s = k; s; i++) if (H[i].first >= mn) { H[i].first -= mn; Ans[detert].push_back(H[i].second); if (!--s) break; } } if (n) { S[++detert] = n; } for (int i = 1; i <= m; i++) printf( %d , S[i]); putchar( n ); for (int i = 0; i < tmpk; i++) { for (int j = 1; j <= m; j++) if (Ans[j].size() > i) printf( %d , Ans[j][i]); else printf( 1 ); putchar( n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int x = 0; int n; cin >> n; for (int i = 0; i < n; i++) { string statement; cin >> statement; if (statement.find( + ) != std::string::npos) { x += 1; } else { x -= 1; } } cout << x << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e6 + 10; const int mod = 998244353; long long a[maxn], b[maxn], n, m, sum1, sum2, res1, res2; long long dp[3030][3030]; inline long long qm(long long a, long long b, long long res = 1) { for (a %= mod; b; b >>= 1, a = a * a % mod) if (b & 1) res = res * a % mod; return res; } int main() { scanf( %I64d%I64d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i]); } for (int i = 1; i <= n; i++) { scanf( %I64d , &b[i]); if (a[i] == 1) sum1 += b[i]; else sum2 += b[i]; } dp[1][1] = sum1 * qm(sum1 + sum2, mod - 2) % mod; dp[1][0] = sum2 * qm(sum1 + sum2, mod - 2) % mod; for (int i = 1; i < m; i++) { for (int j = 0; j <= i; j++) { int tmp = i - j; dp[i + 1][j + 1] = (dp[i + 1][j + 1] + dp[i][j] * (sum1 + j) % mod * qm(sum1 + sum2 + j - tmp, mod - 2)) % mod; dp[i + 1][j] = (dp[i + 1][j] + dp[i][j] * max(0LL, sum2 - tmp) % mod * qm(sum1 + sum2 + j - tmp, mod - 2)) % mod; } } for (int i = 0; i <= m; i++) { res1 = (res1 + dp[m][i] * (sum1 + i) % mod) % mod; res2 = (res2 + dp[m][i] * max(0LL, sum2 - m + i) % mod) % mod; } for (int i = 1; i <= n; i++) { if (a[i]) { printf( %I64d n , res1 * b[i] % mod * qm(sum1, mod - 2) % mod); } else { printf( %I64d n , res2 * b[i] % mod * qm(sum2, mod - 2) % mod); } } } |
#include <bits/stdc++.h> using namespace std; bool bad[105]; string A[105]; bool check(string a, string b) { if ((int)a.size() != (int)b.size()) return false; for (int i = 0; i < (int)a.size(); i++) if (tolower(a[i]) != tolower(b[i])) return false; return true; } int main() { int n, i, j, k; char c, c2; string s; cin >> n; for (i = 0; i < n; i++) cin >> A[i]; cin >> s >> c; for (i = 0; i < n; i++) { for (j = 0; j < (int)s.size(); j++) if (check(s.substr(j, (int)A[i].size()), A[i])) for (k = j; k < j + (int)A[i].size(); k++) bad[k] = true; } for (i = 0; i < (int)s.size(); i++) if (bad[i]) { if (isupper(s[i])) c2 = toupper(c); else c2 = tolower(c); if (s[i] == c2) { if (isupper(s[i])) { for (c2 = A ; c2 <= Z ; c2++) if (c2 != s[i]) { s[i] = c2; break; } } else { for (c2 = a ; c2 <= z ; c2++) if (c2 != s[i]) { s[i] = c2; break; } } } else s[i] = c2; } cout << s; return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_queue_1(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [7:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output [7:0] io_deq_bits,
output [3:0] io_count
);
reg [7:0] ram [0:7];
reg [31:0] GEN_0;
wire [7:0] ram_T_51_data;
wire [2:0] ram_T_51_addr;
wire [7:0] ram_T_35_data;
wire [2:0] ram_T_35_addr;
wire ram_T_35_mask;
wire ram_T_35_en;
reg [2:0] T_27;
reg [31:0] GEN_1;
reg [2:0] T_29;
reg [31:0] GEN_2;
reg maybe_full;
reg [31:0] GEN_3;
wire ptr_match;
wire T_32;
wire empty;
wire full;
wire T_33;
wire do_enq;
wire T_34;
wire do_deq;
wire [3:0] T_39;
wire [2:0] T_40;
wire [2:0] GEN_4;
wire [3:0] T_44;
wire [2:0] T_45;
wire [2:0] GEN_5;
wire T_46;
wire GEN_6;
wire T_48;
wire T_50;
wire [3:0] T_52;
wire [2:0] ptr_diff;
wire T_53;
wire [3:0] T_54;
assign io_enq_ready = T_50;
assign io_deq_valid = T_48;
assign io_deq_bits = ram_T_51_data;
assign io_count = T_54;
assign ram_T_51_addr = T_29;
assign ram_T_51_data = ram[ram_T_51_addr];
assign ram_T_35_data = io_enq_bits;
assign ram_T_35_addr = T_27;
assign ram_T_35_mask = do_enq;
assign ram_T_35_en = do_enq;
assign ptr_match = T_27 == T_29;
assign T_32 = maybe_full == 1'h0;
assign empty = ptr_match & T_32;
assign full = ptr_match & maybe_full;
assign T_33 = io_enq_ready & io_enq_valid;
assign do_enq = T_33;
assign T_34 = io_deq_ready & io_deq_valid;
assign do_deq = T_34;
assign T_39 = T_27 + 3'h1;
assign T_40 = T_39[2:0];
assign GEN_4 = do_enq ? T_40 : T_27;
assign T_44 = T_29 + 3'h1;
assign T_45 = T_44[2:0];
assign GEN_5 = do_deq ? T_45 : T_29;
assign T_46 = do_enq != do_deq;
assign GEN_6 = T_46 ? do_enq : maybe_full;
assign T_48 = empty == 1'h0;
assign T_50 = full == 1'h0;
assign T_52 = T_27 - T_29;
assign ptr_diff = T_52[2:0];
assign T_53 = maybe_full & ptr_match;
assign T_54 = {T_53,ptr_diff};
always @(posedge clock) begin // The RAM block does not need reset
if(ram_T_35_en & ram_T_35_mask) begin
ram[ram_T_35_addr] <= ram_T_35_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_27 <= 3'h0;
end else begin
if (do_enq) begin
T_27 <= T_40;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_29 <= 3'h0;
end else begin
if (do_deq) begin
T_29 <= T_45;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (T_46) begin
maybe_full <= do_enq;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:00 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_dlmb_v10_0 -prefix
// system_dlmb_v10_0_ system_ilmb_v10_0_stub.v
// Design : system_ilmb_v10_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "lmb_v10,Vivado 2016.4" *)
module system_dlmb_v10_0(LMB_Clk, SYS_Rst, LMB_Rst, M_ABus, M_ReadStrobe,
M_WriteStrobe, M_AddrStrobe, M_DBus, M_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, Sl_CE, LMB_ABus,
LMB_ReadStrobe, LMB_WriteStrobe, LMB_AddrStrobe, LMB_ReadDBus, LMB_WriteDBus, LMB_Ready,
LMB_Wait, LMB_UE, LMB_CE, LMB_BE)
/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]" */;
input LMB_Clk;
input SYS_Rst;
output LMB_Rst;
input [0:31]M_ABus;
input M_ReadStrobe;
input M_WriteStrobe;
input M_AddrStrobe;
input [0:31]M_DBus;
input [0:3]M_BE;
input [0:31]Sl_DBus;
input [0:0]Sl_Ready;
input [0:0]Sl_Wait;
input [0:0]Sl_UE;
input [0:0]Sl_CE;
output [0:31]LMB_ABus;
output LMB_ReadStrobe;
output LMB_WriteStrobe;
output LMB_AddrStrobe;
output [0:31]LMB_ReadDBus;
output [0:31]LMB_WriteDBus;
output LMB_Ready;
output LMB_Wait;
output LMB_UE;
output LMB_CE;
output [0:3]LMB_BE;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Point { int x; int y; int z; int id; }; bool compY(Point a, Point b) { if (a.y != b.y) { return a.y < b.y; } return a.z < b.z; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; map<int, vector<Point>> m; for (int i = 0; i < n; i++) { int x, y, z; cin >> x >> y >> z; m[x].push_back({x, y, z, i}); } vector<pair<int, int>> ans; vector<bool> deleted(n, false); for (auto &e : m) { if (e.second.size() < 2) { continue; } vector<Point> a = e.second; int k = a.size(); if (k < 2) { continue; } sort(a.begin(), a.end(), compY); for (int i = 0; i < k - 1; i++) { if (a[i].y == a[i + 1].y) { ans.emplace_back(a[i].id, a[i + 1].id); deleted[a[i].id] = true; deleted[a[i + 1].id] = true; i++; } } int l = 0; int r = 0; while (l < k) { if (deleted[a[l].id]) { l++; continue; } r = max(r, l + 1); while (r < k && deleted[a[r].id]) { r++; } if (r == k) { break; } ans.emplace_back(a[l].id, a[r].id); deleted[a[l].id] = true; deleted[a[r].id] = true; l++; } } bool havePrev = false; Point prev; for (auto &e : m) { bool here = false; Point cur; for (auto &x : e.second) { if (!deleted[x.id]) { here = true; cur = x; break; } } if (!here) { continue; } if (havePrev) { ans.emplace_back(prev.id, cur.id); havePrev = false; } else { havePrev = true; prev = cur; } } for (auto &e : ans) { cout << e.first + 1 << << e.second + 1 << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, d; cin >> n >> d; int a[n]; int x = 0; for (int i = 0; i < n; i++) { cin >> a[i]; x += a[i]; } if (x + (n - 1) * 10 > d) { cout << -1; } else { cout << 2 * n - 2 + (d - x - (n - 1) * 10) / 5; } } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Simple 32-bit Wishbone compatible slave output port
// with 8-bit granularity, modeled after the one in the spec
// Allows for readback
// Assumes a 32-bit wishbone bus
// Lowest order bits get sel[0]
//
module wb_output_pins32
(wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i,
port_output);
input wb_rst_i;
input wb_clk_i;
input wire [31:0] wb_dat_i;
output wire [31:0] wb_dat_o;
input wb_we_i;
input wire [3:0] wb_sel_i;
input wb_stb_i;
output wb_ack_o;
input wb_cyc_i;
output wire [31:0] port_output;
reg [31:0] internal_reg;
always @(posedge wb_clk_i)
if(wb_rst_i)
internal_reg <= #1 32'b0;
else
begin
if(wb_stb_i & wb_we_i & wb_sel_i[0])
internal_reg[7:0] <= #1 wb_dat_i[7:0];
if(wb_stb_i & wb_we_i & wb_sel_i[1])
internal_reg[15:8] <= #1 wb_dat_i[15:8];
if(wb_stb_i & wb_we_i & wb_sel_i[2])
internal_reg[23:16] <= #1 wb_dat_i[23:16];
if(wb_stb_i & wb_we_i & wb_sel_i[3])
internal_reg[31:24] <= #1 wb_dat_i[31:24];
end // else: !if(wb_rst_i)
assign wb_dat_o = internal_reg;
assign port_output = internal_reg;
assign wb_ack_o = wb_stb_i;
endmodule // wb_output_pins32
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:13 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_stub.v
// Design : ip_design_zed_audio_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "i2s_ctrl,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(BCLK, LRCLK, SDATA_I, SDATA_O, S_AXI_ACLK,
S_AXI_ARESETN, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WVALID,
S_AXI_BREADY, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_RREADY, S_AXI_ARREADY, S_AXI_RDATA,
S_AXI_RRESP, S_AXI_RVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_AWREADY)
/* synthesis syn_black_box black_box_pad_pin="BCLK,LRCLK,SDATA_I,SDATA_O,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[31:0],S_AXI_AWVALID,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_BREADY,S_AXI_ARADDR[31:0],S_AXI_ARVALID,S_AXI_RREADY,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_AWREADY" */;
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input [31:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input [31:0]S_AXI_WDATA;
input [3:0]S_AXI_WSTRB;
input S_AXI_WVALID;
input S_AXI_BREADY;
input [31:0]S_AXI_ARADDR;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_ARREADY;
output [31:0]S_AXI_RDATA;
output [1:0]S_AXI_RRESP;
output S_AXI_RVALID;
output S_AXI_WREADY;
output [1:0]S_AXI_BRESP;
output S_AXI_BVALID;
output S_AXI_AWREADY;
endmodule
|
//wb_master_test.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_master_test
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/06/02
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module wb_master_test (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
reg [31:0] r_control;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
r_control <= 2;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
r_control <= i_wbs_dat;
o_wbs_int <= i_wbs_dat[1];
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_0);
o_wbs_dat <= r_control;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 405; const int maxm = 5005; const int INF = 1000000000; const int mod = 1000000; struct EDGE { int cap, cost, v, next; } edge[mod]; int head[maxn], E, q[mod]; bool used[maxn]; int pre[maxn], cur[maxn], dis[maxn]; void add_edge(int s, int t, int cap, int cost) { edge[E].cap = cap; edge[E].cost = cost; edge[E].next = head[s]; edge[E].v = t; head[s] = E++; edge[E].cap = 0; edge[E].cost = -cost; edge[E].next = head[t]; edge[E].v = s; head[t] = E++; } int min(int a, int b) { return (a == -1 || b < a) ? b : a; } int SPFA(int s, int t, int n) { int f = -1, r = 0; int i, v; q[r] = s; for (i = 0; i < n; i++) dis[i] = INF; dis[s] = 0; pre[s] = s; cur[s] = -1; memset(used, false, sizeof(bool) * n); used[s] = true; while (f != r) { f++; if (f >= mod) f -= mod; s = q[f]; used[s] = false; for (i = head[s]; i != -1; i = edge[i].next) { v = edge[i].v; if (edge[i].cap > 0 && dis[s] + edge[i].cost < dis[v]) { dis[v] = dis[s] + edge[i].cost; pre[v] = s; cur[v] = i; if (!used[v]) { used[v] = true; r++; if (r >= mod) r -= mod; q[r] = v; } } } } return dis[t]; } int MinCost(int s, int t, int n) { int ans = 0; int u, v, cap; int cost; while (1) { cost = SPFA(s, t, n); if (cost == INF) break; u = v = t; cap = -1; for (u = t; u != s; u = pre[u]) { cap = min(cap, edge[cur[u]].cap); } ans += cost * cap; u = v = t; for (u = t; u != s; u = pre[u]) { edge[cur[u]].cap -= cap; edge[cur[u] ^ 1].cap += cap; } } return ans; } int dx[maxn]; int dy[maxn]; int c[maxm]; int x[maxm]; int y[maxm]; int main() { int n, m, g, k, z; int i, j; int s, t; while (scanf( %d%d%d%d , &n, &m, &k, &g) != -1) { memset(dx, 0, sizeof(int) * n); memset(dy, 0, sizeof(int) * m); for (i = 0; i < k; i++) { scanf( %d%d , &x[i], &y[i]); dx[--x[i]]++; dy[--y[i]]++; } int ans = 0; for (i = 0; i < n; i++) ans += dx[i] % g != 0; for (i = 0; i < m; i++) ans += dy[i] % g != 0; printf( %d n , ans); memset(c, -1, sizeof(int) * k); s = n + m; t = s + 1; for (; g >= 1; g--) { E = 0; memset(head, -1, sizeof(int) * (t + 1)); for (i = 0; i < k; i++) if (c[i] == -1) add_edge(x[i], y[i] + n, 1, 0); for (i = 0; i < n; i++) { add_edge(s, i, dx[i] / g, 0); if (dx[i] % g) add_edge(s, i, 1, 1); } for (i = 0; i < m; i++) { add_edge(i + n, t, dy[i] / g, 0); if (dy[i] % g) add_edge(i + n, t, 1, 1); } MinCost(s, t, t + 1); for (i = 0, z = 0; i < k; i++) if (c[i] == -1) { if (edge[z].cap == 0) { c[i] = g; dx[x[i]]--; dy[y[i]]--; } z += 2; } } for (i = 0; i < k; i++) { if (i) printf( ); printf( %d , c[i]); } puts( ); } return 0; } |
//
// Spartan-3E on-chip RAM interface.
//
// Author(s):
// - Serge Vakulenko,
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
//----------------------
// CVS Revision History
//
// $Log: onchip_ram_top.v,v $
// Revision 1.3 2006-12-22 17:16:26 vak
// Added comments and copyrights.
//
// Revision 1.2 2006/12/22 11:07:34 vak
// Amount of on-chip RAM increased to 16 kbytes.
// The generated bit file is successfully downloaded to the target board.
// Debug interface is functioning (jp1) via Xilinx parallel cable III.
// Hello-uart is running fine.
//
// Revision 1.1 2006/12/22 08:34:00 vak
// The design is successfully compiled using on-chip RAM.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module onchip_ram_top (
//
// I/O Ports
//
input wb_clk_i,
input wb_rst_i,
//
// WB slave i/f
//
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o
);
//
// Paraneters
//
parameter AW = 12; // RAM size = 4 kwords (16 kbytes)
//
// Internal wires and regs
//
wire we;
wire [3:0] be_i;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (| wb_adr_i[23:AW+2]);
// If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (| wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// Read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
//
// Generate 8 blocks of standard Xilinx library component:
// 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
//
RAMB16_S4 block_ram_00 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [3 : 0]),
.DO (wb_dat_o [3 : 0]),
.EN (be_i [0]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_01 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [7 : 4]),
.DO (wb_dat_o [7 : 4]),
.EN (be_i [0]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_10 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [11 : 8]),
.DO (wb_dat_o [11 : 8]),
.EN (be_i [1]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_11 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [15 : 12]),
.DO (wb_dat_o [15 : 12]),
.EN (be_i [1]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_20 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [19 : 16]),
.DO (wb_dat_o [19 : 16]),
.EN (be_i [2]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_21 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [23 : 20]),
.DO (wb_dat_o [23 : 20]),
.EN (be_i [2]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_30 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [27 : 24]),
.DO (wb_dat_o [27 : 24]),
.EN (be_i [3]),
.WE (we),
.SSR (0));
RAMB16_S4 block_ram_31 (
.ADDR (wb_adr_i [AW+1 : 2]),
.CLK (wb_clk_i),
.DI (wb_dat_i [31 : 28]),
.DO (wb_dat_o [31 : 28]),
.EN (be_i [3]),
.WE (we),
.SSR (0));
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; void OUT_TST(string s, istream_iterator<string> it) { cerr << s; } template <typename T, typename... Args> void OUT_TST(string s, istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << ; OUT_TST(s, ++it, args...); } template <class T> void rd(T &ret) { ret = 0; bool ok = 0, u = 0; for (;;) { int c = getchar(); if (c >= 0 && c <= 9 ) ret = (ret << 3) + (ret << 1) + c - 0 , ok = 1; else if (c == - ) u = 1; else if (ok) { if (u) ret *= -1; return; } } } long long powmod(long long p, long long n, long long mod) { long long ret = 1; for (; n; n >>= 1) { if (n & 1) ret = ret * p % mod; p = p * p % mod; } return ret; } template <class T> bool chmin(T &a, const T &b) { return b < a ? a = b, 1 : 0; } template <class T> bool chmax(T &a, const T &b) { return b > a ? a = b, 1 : 0; } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } bool ok(vector<pair<int, int> > &bn, vector<int> &pos, bool tmp) { vector<pair<int, int> > an(4); for (int i = (0); i < (4); i++) an[i] = bn[pos[i]]; if (tmp == 1) { if (an[0].first != an[2].first) return 0; if (an[0].second >= an[2].second) return 0; if (an[1].second != an[3].second) return 0; if (an[1].first <= an[3].first) return 0; return 1; } return 1; if (an[0].first != an[3].first) return 0; if (an[0].second >= an[3].second) return 0; if (an[1].second >= an[2].second) return 0; return 1; } vector<pair<int, int> > gao(vector<pair<int, int> > an, bool tmp) { vector<int> pos; for (int i = (0); i < (4); i++) pos.push_back(i); bool fg = 0; if (ok(an, pos, tmp)) fg = 1; while (!fg && next_permutation((pos).begin(), (pos).end())) { if (ok(an, pos, tmp)) { assert(fg == 0); fg = 1; } } vector<pair<int, int> > cn(4); for (int i = (0); i < (4); i++) cn[i] = an[pos[i]]; return cn; } vector<pair<int, int> > an, bn; int xlow, ylow, xup, yup; bool ins(int first, int second) { if (first >= xlow && first <= xup && second >= ylow && second <= yup) return 1; return 0; } int main() { pair<int, int> t; for (int i = (0); i < (4); i++) { scanf( %d%d , &t.first, &t.second); an.push_back(t); } for (int i = (0); i < (4); i++) { scanf( %d%d , &t.first, &t.second); bn.push_back(t); } an = gao(an, 0); bn = gao(bn, 1); xlow = INT_MAX, ylow = INT_MAX, xup = -INT_MAX, yup = -INT_MAX; for (int i = (0); i < (4); i++) { chmin(xlow, an[i].first); chmax(xup, an[i].first); chmin(ylow, an[i].second); chmax(yup, an[i].second); } for (int i = (0); i < (4); i++) { string _s = an[i].x, an[i].y ; replace(_s.begin(), _s.end(), , , ); stringstream _ss(_s); istream_iterator<string> _it(_ss); OUT_TST( , _it, an[i].first, an[i].second); }; puts( ); for (int i = (0); i < (4); i++) { string _s = bn[i].x, bn[i].y ; replace(_s.begin(), _s.end(), , , ); stringstream _ss(_s); istream_iterator<string> _it(_ss); OUT_TST( , _it, bn[i].first, bn[i].second); }; puts( ); int l = bn[1].second, r = bn[1].second; for (int i = (bn[3].first); i < (bn[1].first + 1); i++) { for (int j = (l); j < (r + 1); j++) if (ins(i, j)) { puts( YES ); return 0; } if (i < bn[0].first) --l, ++r; else ++l, --r; } puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; if (n <= min(m, k)) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i; cin >> n; string s; cin >> s; if (n == 24) { if (s[0] == 2 && s[1] > 3 ) { s[0] = 1 ; } else if (s[0] > 2 ) { s[0] = 1 ; } } else { if (s[0] == 1 && s[1] > 2 ) { s[0] = 0 ; } else if (s[0] == 0 && s[1] == 0 ) { s[1] = 1 ; } else if (s[0] > 1 ) { if (s[1] == 0 ) s[0] = 1 ; else s[0] = 0 ; } } if (s[3] > 5 ) { s[3] = 1 ; } cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; char s[N]; int m, n; void sol() { int b[26] = {0}; scanf( %d %d , &n, &m); int a[N] = {0}; scanf( %s , s); int t; for (int i = 0; i < m; i++) { scanf( %d , &t); a[t - 1]++; } a[n - 1] = 1; for (int i = n - 1; i >= 0; i--) { if (i < n - 1) a[i] += a[i + 1]; int num = s[i] - a ; b[num] += a[i]; } for (int i = 0; i < 26; i++) { if (i != 25) printf( %d , b[i]); else printf( %d n , b[i]); } } int main() { int T; scanf( %d , &T); while (T--) sol(); return 0; } |
`timescale 1ns / 1ps
module test_engine_tb();
reg clk;
reg reset;
reg start_strobe;
reg [63:0] wordA;
reg [63:0] wordB;
wire done_strobe;
wire active_test_engine;
wire [63:0] wordC;
wire [63:0] wordD;
test_engine
#(
.ROUNDS(5)
)
test_engine
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.start_strobe_din (start_strobe),
.wordA_din (wordA),
.wordB_din (wordB),
// -- outputs ------------------------------------------------ >>>>>
.done_strobe_dout (done_strobe),
.active_test_engine_dout (active_test_engine),
.wordC_dout (wordC),
.wordD_dout (wordD)
);
// -- Parametros de lectura de archivo --------------------------- >>>>>
localparam SAMPLES = 100;
reg [63:0] file_read [0:(SAMPLES * 2) - 1];
integer index;
integer fp;
always
begin
clk = 1'b0;
#(20);
clk = 1'b1;
#(20);
end
initial
$readmemh("/home/hector/Dropbox/red/processing_element/test_engine/tools/reference_model/origin.txt", file_read);
initial
fp = $fopen("/home/hector/Dropbox/red/processing_element/test_engine/tools/reference_model/hardware.txt", "w");
/*
initial
begin
$readmemh("/home/hector/Dropbox/red/processing_element/test_engine/tools/reference_model/origin.txt", file_read);
for(index = 0; index < 20; index = index + 1)
begin
$display("Valor en posicion %d: \t %h", index+1, file_read[index]);
end
end
*/
initial
begin
clk = 0;
reset = 1;
start_strobe = 0;
wordA = 0;
wordB = 0;
repeat (5)
@(negedge clk);
reset = 0;
repeat (5)
@(negedge clk);
for (index = 0; index < SAMPLES; index = index + 1)
begin
wordA = file_read[(index*2)];
wordB = file_read[(index*2) + 1];
start_strobe = 1;
@(negedge clk);
start_strobe = 0;
wait(done_strobe)
@(negedge clk);
$fwrite(fp, "0x%h\n", wordC);
$fwrite(fp, "0x%h\n", wordD);
@(negedge clk);
end
repeat (10)
@(negedge clk);
$fclose(fp);
$finish;
end
endmodule // test_engine_tb |
/*
* Microcode instruction generator for Zet
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_micro_data (
input [`MICRO_ADDR_WIDTH-1:0] n_micro,
input [15:0] off_i,
input [15:0] imm_i,
input [ 3:0] src,
input [ 3:0] dst,
input [ 3:0] base,
input [ 3:0] index,
input [ 1:0] seg,
input [ 2:0] fdec,
output div,
output end_seq,
output [`IR_SIZE-1:0] ir,
output [15:0] off_o,
output [15:0] imm_o
);
// Net declarations
wire [`MICRO_DATA_WIDTH-1:0] micro_o;
wire [ 6:0] ir1;
wire [ 1:0] ir0;
wire var_s, var_off;
wire [1:0] var_a, var_b, var_c, var_d;
wire [2:0] var_imm;
wire [3:0] addr_a, addr_b, addr_c, addr_d;
wire [3:0] micro_a, micro_b, micro_c, micro_d;
wire [1:0] addr_s, micro_s;
wire [2:0] t;
wire [2:0] f;
wire [2:0] f_rom;
wire wr_flag;
wire wr_mem;
wire wr_rom;
wire wr_d;
// Module instantiations
zet_micro_rom micro_rom (n_micro, micro_o);
// Assignments
assign micro_s = micro_o[1:0];
assign micro_a = micro_o[5:2];
assign micro_b = micro_o[9:6];
assign micro_c = micro_o[13:10];
assign micro_d = micro_o[17:14];
assign wr_flag = micro_o[18];
assign wr_mem = micro_o[19];
assign wr_rom = micro_o[20];
assign ir0 = micro_o[22:21];
assign t = micro_o[25:23];
assign f_rom = micro_o[28:26];
assign ir1 = micro_o[35:29];
assign var_s = micro_o[36];
assign var_a = micro_o[38:37];
assign var_b = micro_o[40:39];
assign var_c = micro_o[42:41];
assign var_d = micro_o[44:43];
assign var_off = micro_o[45];
assign var_imm = micro_o[48:46];
assign end_seq = micro_o[49];
assign imm_o = var_imm == 3'd0 ? (16'h0000)
: (var_imm == 3'd1 ? (16'h0002)
: (var_imm == 3'd2 ? (16'h0004)
: (var_imm == 3'd3 ? off_i
: (var_imm == 3'd4 ? imm_i
: (var_imm == 3'd5 ? 16'hffff
: (var_imm == 3'd6 ? 16'b11 : 16'd1))))));
assign off_o = var_off ? off_i : 16'h0000;
assign addr_a = var_a == 2'd0 ? micro_a
: (var_a == 2'd1 ? base
: (var_a == 2'd2 ? dst : src ));
assign addr_b = var_b == 2'd0 ? micro_b
: (var_b == 2'd1 ? index : src);
assign addr_c = var_c == 2'd0 ? micro_c
: (var_c == 2'd1 ? dst : src);
assign addr_d = var_d == 2'd0 ? micro_d
: (var_d == 2'd1 ? dst : src);
assign addr_s = var_s ? seg : micro_s;
assign div = (t==3'd3 && (f_rom[2]|f_rom[1]) && !wr_rom);
assign f = (t==3'd6 && wr_flag || t==3'd5 && wr_rom) ? fdec : f_rom;
assign wr_d = (t==3'd5 && f==3'd7) ? 1'b0 : wr_rom; /* CMP doesn't write */
assign ir = { ir1, f, t, ir0, wr_d, wr_mem, wr_flag, addr_d,
addr_c, addr_b, addr_a, addr_s };
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007,2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
//
// Main module
/*
4000_0000 - 400F_FFFF Extern SRAM (1 MiB)
BFC0_0000 - BFC0_3FFF Boot ROM (16 KiB) (Preloaded I$ cache)
FF00_0000 - FF00_1FFF Peripherals
Read Write
0 rs232out busy rs232out data
1 rs232in data
2 rs232in count
3 TSC
*/
`timescale 1ns/10ps
`include "pipeconnect.h"
`ifdef SIMULATE_MAIN
`define BLOCKRAM 1
`endif
module main(// Clock and reset
input wire clkin // K5 PLL input clock (50 MHz)
,output wire pld_clkout // L8 Clock to zero-skew buffer Lancelot board
,input wire pld_clkfb // L14 Feedback from pld_clkout to PLL2
,input wire reset_n // C4 CPU Reset button
// Lancelot VGA interface
,output wire [7:0] vga_r // VGA red
,output wire [7:0] vga_g // VGA green
,output wire [7:0] vga_b // VGA blue
,output wire vga_hs // VGA horz sync
,output wire vga_vs // VGA vert sync
,output wire vga_blank_n // VGA DAC force blank
,output wire vga_sync_n // VGA sync enable
,output wire vga_sync_t // VGA sync on R/G/B
,output wire vga_m1 // VGA color space config
,output wire vga_m2 // VGA color space config
`ifdef PS2_ENABLED
// PS/2 keyboard/mouse
,output ps2_sel // PS/2 port input/output select
,inout ps2_kclk // PS/2 keyboard clock
,inout ps2_kdata // PS/2 keyboard data
,inout ps2_mclk // PS/2 mouse clock
,inout ps2_mdata // PS/2 mouse data
`endif
// Push buttons LEDs 7-segments
,input wire [3:0] sw // Pushbutton switches
,output [7:0] led // Debugging LEDs
,output wire [7:0] s7_0 // Debugging 7-segment LEDs
,output wire [7:0] s7_1 // --
`ifndef SIMULATE_MAIN
// Flash-SRAM-Ethernet bus
,output wire [22:0] fse_a // Mainboard common bus address
,inout wire [31:0] fse_d // Mainboard common bus data
,output wire flash_cs_n // Flash ROM CS#
,output wire enet_aen // Ethernet Access Enable
,output wire sram_cs_n // SRAM CS#
,output wire [3:0] sram_be_n // SRAM byte enables
,output wire sram_oe_n // SRAM OE#
,output wire sram_we_n // SRAM WE#
`endif
`ifdef SERIAL_ENABLED
// Serial IO
,output ttya_dcd // Console DCD#
,output ttya_txd // Console TxD
,input ttya_rxd // Console RxD
,input ttya_dtr // Console DTR#
,output ttya_dsr // Console DSR#
,input ttya_rts // Console RTS#
,output ttya_cts // Console CTS#
,output ttya_ri // Console RI#
`endif
,output ttyb_txd // Debug TxD
,input ttyb_rxd // Debug RxD
`ifdef CF_ENABLED
// CompactFlash slot
,output [10:0] cf_a // CompactFlash address bus
,inout [15:0] cf_d // CompactFlash data bus
,input cf_rdy // CompactFlash RDY
,input cf_wait_n // CompactFlash WAIT#
,output cf_ce1_n // CompactFlash CE1#
,output cf_ce2_n // CompactFlash CE2#
,output cf_oe_n // CompactFlash OE#
,output cf_we_n // CompactFlash WE#
,output cf_reg_n // CompactFlash REG#
,input cf_cd1_n // CompactFlash card detect
`endif
// SDRAM
// Audio
// Ethernet
// Flash memory
);
// ------------------------------------------------------------------------
// Reset
// (there is option for extending the reset internally here, if necessary)
// ------------------------------------------------------------------------
// wire rst = ~reset_n;
// ------------------------------------------------------------------------
// PLLs and clock distribution
// ------------------------------------------------------------------------
// XXX Note 45 MHz appears to be the limit for the sram with just 1
// wait state (I happen to know the memory is good for much more
// with a trick I can't explain why works.)
parameter FREQ = 45_454_545; // match clock frequency
parameter BPS = 115_200; // Serial speed
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
`ifdef SIMULATE_MAIN
// Flash-SRAM-Ethernet bus
wire [22:0] fse_a; // Mainboard common bus address
wire [31:0] fse_d; // Mainboard common bus data
wire flash_cs_n; // Flash ROM CS#
wire enet_aen; // Ethernet Access Enable
wire sram_cs_n; // SRAM CS#
wire [3:0] sram_be_n; // SRAM byte enables
wire sram_oe_n; // SRAM OE#
wire sram_we_n; // SRAM WE#
`ifndef BLOCKRAM
idt71v416s10 u35(fse_d[15: 0], fse_a[19:2], sram_we_n, sram_oe_n, sram_cs_n,
sram_be_n[0], sram_be_n[1]); // Yep, strange order...
idt71v416s10 u36(fse_d[31:16], fse_a[19:2], sram_we_n, sram_oe_n, sram_cs_n,
sram_be_n[2], sram_be_n[3]);
`endif
`endif
assign flash_cs_n = 1; // Disable flash ROM
assign enet_aen = 1; // Disable Ethernet
`ifdef SIMULATE_MAIN
reg clk = 0;
`else
wire clk;
wire pll_locked;
pll pll(
.inclk0(clkin), // 50 MHz input clock
.c0(clk),
.locked(pll_locked)
);
assign led = {rled[0],rled[1],rled[2],rled[3],rled[4],rled[5],rled[6],rled[7]};
reg [7:0] rled = 0;
`endif // SIMULATE_MAIN
reg [ 3:0] reset_count_up = 0;
`ifdef SIMULATE_MAIN
wire rst = 0;
`else
wire rst = ~reset_n /*reset_count_up != 15*/;
`endif
always @(posedge clk)
if (~reset_n)
reset_count_up <= 0;
else if (rst) begin
if (reset_count_up == 14)
$display("Reset count %d", reset_count_up);
reset_count_up <= reset_count_up + 1'd1;
end
yari yari_inst(
.clock(clk)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
`ifdef SIMULATE_MAIN
blockram blockram_inst
(.clock(clk)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
);
defparam blockram_inst.INIT_FILE="`SRAM_INIT";
`else
sram_ctrl sram_ctrl_inst
(.clock(clk)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(fse_a[19:2])
,.sram_d(fse_d)
,.sram_cs_n(sram_cs_n)
,.sram_be_n(sram_be_n)
,.sram_oe_n(sram_oe_n)
,.sram_we_n(sram_we_n)
);
defparam sram_ctrl_inst.need_wait = 1;
`endif
rs232out rs232out_inst
(.clock(clk),
.serial_out(ttyb_txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clk),
.serial_in(ttyb_rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clk),
.rst(rst),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
`ifdef SIMULATE_MAIN
always #50 clk = ~clk;
initial #50 clk = 0;
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_LP_V
`define SKY130_FD_SC_LP__NOR4_LP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_lp (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_lp (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_LP_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_BUF_SIZE = 16384; char BUFOR[MAX_BUF_SIZE]; int BUF_SIZE, BUF_POS; char ZZZ; const int MXN = 100010; const int C = 262144; const int INF = 1000000001; string a[MXN]; int aa; int typ[MXN], gender[MXN]; string fem[3] = { liala , etra , inites }; string masc[3] = { lios , etr , initis }; string mowa[6] = { lios , etr , initis , liala , etra , inites }; int n; void test() { string tmp; while (cin >> tmp) a[aa++] = tmp; n = aa; bool czy = 1; for (int i = 0; i < aa; i++) { int dec = -1; gender[i] = -1; for (int j = 0; j < 3; j++) { string w = masc[j]; if (w.length() <= a[i].length() && w == string(a[i], (int)(a[i]).size() - (int)(w).size(), (int)(w).size())) dec = 1; gender[i] = dec; } dec = -1; for (int j = 0; j < 3; j++) { string w = fem[j]; if (w.length() <= a[i].length() && w == string(a[i], (int)(a[i]).size() - (int)(w).size(), (int)(w).size())) dec = 0; if (gender[i] == -1) gender[i] = dec; } for (int j = 0; j < 6; j++) { string w = mowa[j]; typ[i] = -1; if (w.length() <= a[i].length() && w == string(a[i], (int)(a[i]).size() - (int)(w).size(), (int)(w).size())) { typ[i] = j % 3; break; } } if (gender[i] == -1 || typ[i] == -1) czy = 0; } int iter = 0; while (iter < n && typ[iter] == 0) iter++; if (typ[iter] == 1) iter++; else if (n > 1) czy = 0; while (czy && iter < n) if (typ[iter++] != 2) czy = 0; for (int i = 1; i < n; i++) if (gender[0] != gender[i]) czy = 0; if (czy) printf( YES n ); else printf( NO n ); } int main() { int te = 1; while (te--) test(); } |
module sockit_test (
input CLOCK_50,
input [3:0] KEY,
output [3:0] LED,
output [14:0] hps_memory_mem_a,
output [2:0] hps_memory_mem_ba,
output hps_memory_mem_ck,
output hps_memory_mem_ck_n,
output hps_memory_mem_cke,
output hps_memory_mem_cs_n,
output hps_memory_mem_ras_n,
output hps_memory_mem_cas_n,
output hps_memory_mem_we_n,
output hps_memory_mem_reset_n,
inout [39:0] hps_memory_mem_dq,
inout [4:0] hps_memory_mem_dqs,
inout [4:0] hps_memory_mem_dqs_n,
output hps_memory_mem_odt,
output [4:0] hps_memory_mem_dm,
input hps_memory_oct_rzqin
);
wire [3:0] key_os;
wire [3:0] delay;
wire main_clk = CLOCK_50;
oneshot os (
.clk (main_clk),
.edge_sig (KEY),
.level_sig (key_os)
);
blinker b (
.clk (main_clk),
.delay (delay),
.led (LED),
.reset (key_os[3]),
.pause (key_os[2])
);
soc_system soc (
.delay_ctrl_delay (delay),
.delay_ctrl_slower (key_os[0]),
.delay_ctrl_faster (key_os[1]),
.memory_mem_a (hps_memory_mem_a),
.memory_mem_ba (hps_memory_mem_ba),
.memory_mem_ck (hps_memory_mem_ck),
.memory_mem_ck_n (hps_memory_mem_ck_n),
.memory_mem_cke (hps_memory_mem_cke),
.memory_mem_cs_n (hps_memory_mem_cs_n),
.memory_mem_ras_n (hps_memory_mem_ras_n),
.memory_mem_cas_n (hps_memory_mem_cas_n),
.memory_mem_we_n (hps_memory_mem_we_n),
.memory_mem_reset_n (hps_memory_mem_reset_n),
.memory_mem_dq (hps_memory_mem_dq),
.memory_mem_dqs (hps_memory_mem_dqs),
.memory_mem_dqs_n (hps_memory_mem_dqs_n),
.memory_mem_odt (hps_memory_mem_odt),
.memory_mem_dm (hps_memory_mem_dm),
.memory_oct_rzqin (hps_memory_oct_rzqin),
.clk_clk (main_clk),
.reset_reset_n (!key_os[3])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; int n, a, b, k; int d[3][N]; int sum[N]; int ans = 0; int cur = 1; int main() { scanf( %d%d%d%d , &n, &a, &b, &k); d[0][a] = 1; for (int cnt = 1; cnt <= k; ++cnt) { for (int i = 1; i <= n; ++i) sum[i] = (sum[i - 1] + d[cur ^ 1][i]) % 1000000007; for (int i = 1; i <= n; ++i) { if (i == b) continue; if (i < b) { int r = i + (b - i) / 2; if ((b - i) % 2 == 0) --r; d[cur][i] = (sum[r] - d[cur ^ 1][i] + 1000000007) % 1000000007; } else { int l = i - (i - b) / 2; if ((i - b) % 2 == 0) ++l; d[cur][i] = (((sum[n] - sum[l - 1] - d[cur ^ 1][i]) % 1000000007) + 1000000007) % 1000000007; } } cur ^= 1; } for (int i = 1; i <= n; ++i) ans = (ans + d[cur ^ 1][i]) % 1000000007; printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_12_V
`define SKY130_FD_SC_HD__INV_12_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_12 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_12 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_12_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a; int main(int argc, char *argv[]) { int n; cin >> n; if (n == 1) { cout << 1; return 0; } if (n == 2) { cout << 1 << << 2; return 0; } if (n == 3) { cout << 1 << << 1 << << 3; return 0; } int so = 1, ts = 2, ss = n, luu = 1; while (ss > 2) { int m = n / ts; m = ss - m; for (int i = 1; i <= m; i++) cout << luu << ; ss = ss - m; if (ss == 1) { cout << ts; return 0; } if (ss == 2) { cout << ts << << ts * 2; return 0; } if (ss == 3) { cout << ts << << ts << << ts * 3; return 0; } luu = ts; ts = ts * 2; } } |
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder4to16.v"
`include "encoder.v"
`include "decoder.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [14:0] c;
// Output of stage 2
wire [15:1] err;
wire [14:0] cx;
// Output of stage 3
wire [10:0] q;
wire [10:0] qx;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [10:0] b;
reg [10:0] r_b;
reg [3:0] e;
reg [3:0] r_e;
// 2nd stage
reg [14:0] r_c;
reg [3:0] rr_e;
reg [10:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [14:0] r_qx;
reg [10:0] rb;
reg clk,reset;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
decoder4to16 dec4to16 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_e,err);
ham_15_11_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
ham_15_11_decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,err,cx);
parity_stripper ps (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,qx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
r_qx<=0;
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int R = 1000; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n, s, d; cin >> n >> s >> d; vector<bitset<R>> a(s); for (int i = 0, k, x; i < s; ++i) { cin >> k; while (k--) cin >> x, a[i][x - 1] = 1; } vector<pair<int, bitset<R>>> f1; int m = min(s, 10); for (int i = 0; i < 1 << m; ++i) { f1.push_back({0, {}}); for (int j = 0; j < m; ++j) if (i >> j & 1) ++f1.back().first, f1.back().second ^= a[j]; } unordered_map<bitset<R>, int> mp; int m2 = s - m; for (int i = 0; i < 1 << m2; ++i) { bitset<R> b; int c = 0; for (int j = 0; j < m2; ++j) if (i >> j & 1) ++c, b ^= a[m + j]; if (!mp.count(b)) mp[b] = c; else mp[b] = min(mp[b], c); } for (int k, x; d--;) { cin >> k; bitset<R> b; while (k--) cin >> x, b[x - 1] = 1; int ans = 1 << 30; for (auto &i : f1) { b ^= i.second; if (mp.count(b)) ans = min(ans, i.first + mp[b]); b ^= i.second; } if (ans == 1 << 30) ans = -1; cout << ans << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e6; vector<long long int> adj[N]; long long int depth[N]; void dfs(long long int n, long long int p) { for (auto x : adj[n]) { if (x != p) { depth[x] = depth[n] + 1; dfs(x, n); } } } void solve() { long long int n, a, b, da, db; cin >> n >> a >> b >> da >> db; for (long long int i = 1; i <= n; ++i) { adj[i].clear(); depth[i] = 0; } for (long long int i = 1; i < n; ++i) { long long int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } long long int maxi = -1, idx = -1; dfs(1, -1); for (long long int i = 1; i <= n; ++i) { if (depth[i] > maxi) { idx = i; maxi = depth[i]; } } for (long long int i = 1; i <= n; ++i) { depth[i] = 0; } dfs(idx, -1); for (long long int i = 1; i <= n; ++i) { if (depth[i] > maxi) { idx = i; maxi = depth[i]; } } for (long long int i = 1; i <= n; ++i) { depth[i] = 0; } if (2 * da >= min(maxi, db)) { cout << Alice << endl; return; } dfs(a, -1); if (da >= depth[b]) { cout << Alice << endl; } else { cout << Bob << endl; } } int main() { ios_base::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); int t = 1; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:66777216 ) using namespace std; int RAND() { return (rand() << 16) + rand(); } const long long MOD = 1000000007; const int N = 2000007; int n; long long f[N]; long long power(long long a, long long b) { if (b == 0) return 1; if (b & 1) return a * power(a, b - 1) % MOD; long long r = power(a, b >> 1); return r * r % MOD; } long long inv(long long a) { return power(a, MOD - 2); } long long C(int n, int k) { return f[n] * inv(f[k] * f[n - k] % MOD) % MOD; } void solve() { f[0] = 1; for (int i = 1; i < N; ++i) f[i] = i * f[i - 1] % MOD; cin >> n; long long ans = ((n + 2) * C(2 * n + 2, n) - n - 1) % MOD * inv(n + 1) % MOD; if (ans < 0) ans += MOD; cout << ans << endl; } void testgen() { FILE* f = fopen( input.txt , w ); fclose(f); } int main() { cout << fixed; cout.precision(16); cerr << fixed; cerr.precision(3); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, p, q, r; cin >> n >> p >> q >> r; long long int a[n], ans = LLONG_MIN; for (long long int i = 0; i < n; i++) cin >> a[i]; long long int prefixMax[n], suffixMax[n]; prefixMax[0] = p * a[0]; suffixMax[n - 1] = r * a[n - 1]; for (long long int i = 1; i < n; i++) prefixMax[i] = max(prefixMax[i - 1], p * a[i]); for (long long int i = n - 2; i >= 0; i--) suffixMax[i] = max(suffixMax[i + 1], r * a[i]); for (long long int i = 0; i < n; i++) { ans = max(ans, prefixMax[i] + suffixMax[i] + (q * a[i])); } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ls__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_BLACKBOX_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// ======================================================================
// This is intended to be a complex example of several features, please also
// see the simpler examples/make_hello_c.
module top
(
// Declare some signals so we can see how I/O works
input clk,
input fastclk,
input reset_l,
output wire [1:0] out_small,
output wire [39:0] out_quad,
output wire [69:0] out_wide,
input [1:0] in_small,
input [39:0] in_quad,
input [69:0] in_wide
);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
// Print some stuff as an example
initial begin
$display("[%0t] Model running...\n", $time);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long f[800][800][3][3]; int b[400][2], c[800]; int main() { string s; while (cin >> s) { memset(f, 0, sizeof(f)); int t[800]; for (int i = 0, x = 0, k = 0; i < s.size(); i++) { if (s[i] == ( ) { b[++x][0] = i + 1; c[i + 1] = x; k++; t[k] = i + 1; } else { c[i + 1] = c[t[k--]]; b[c[i + 1]][1] = i + 1; } } for (int i = 1; i < s.size(); i++) { if (c[i] == c[i + 1]) { f[i][i + 1][1][0] = 1; f[i][i + 1][2][0] = 1; f[i][i + 1][0][1] = 1; f[i][i + 1][0][2] = 1; } } for (int d = 3; d < s.size(); d += 2) { for (int i = 1; i <= s.size() - d; i++) { int j = i + d; if (s[i - 1] == s[j - 1] || (s[i - 1] == ) && s[j - 1] == ( )) continue; if (c[i] == c[j]) { f[i][j][0][1] = (f[i + 1][j - 1][1][0] + f[i + 1][j - 1][2][0] + f[i + 1][j - 1][1][2] + f[i + 1][j - 1][2][2] + f[i + 1][j - 1][0][2] + f[i + 1][j - 1][0][0]) % 1000000007; f[i][j][1][0] = (f[i + 1][j - 1][0][1] + f[i + 1][j - 1][0][2] + f[i + 1][j - 1][2][1] + f[i + 1][j - 1][2][2] + f[i + 1][j - 1][2][0] + f[i + 1][j - 1][0][0]) % 1000000007; f[i][j][0][2] = (f[i + 1][j - 1][1][0] + f[i + 1][j - 1][2][0] + f[i + 1][j - 1][1][1] + f[i + 1][j - 1][2][1] + f[i + 1][j - 1][0][1] + f[i + 1][j - 1][0][0]) % 1000000007; f[i][j][2][0] = (f[i + 1][j - 1][0][1] + f[i + 1][j - 1][0][2] + f[i + 1][j - 1][1][1] + f[i + 1][j - 1][1][2] + f[i + 1][j - 1][1][0] + f[i + 1][j - 1][0][0]) % 1000000007; } else { for (int x = 0; x <= 2; x++) { for (int y = 0; y <= 2; y++) { for (int m = 0; m <= 2; m++) { for (int n = 0; n <= 2; n++) { if (m == n && m != 0 && n != 0) continue; f[i][j][x][y] += f[i][b[c[i]][1]][x][m] * f[b[c[i]][1] + 1][j][n][y] % 1000000007; f[i][j][x][y] %= 1000000007; } } } } } } } int n = s.size(); cout << (f[1][n][0][0] + f[1][n][0][1] + f[1][n][0][2] + f[1][n][1][0] + f[1][n][1][1] + f[1][n][1][2] + f[1][n][2][0] + f[1][n][2][1] + f[1][n][2][2]) % 1000000007 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(0); long long n, m, k, x, y; cin >> n >> m >> k >> x >> y; long long ti = (n * m) + ((n - 2) * m); if (n == 1 || n == 2) ti = n * m; long long upd = 0, mid = 0; long long a[110][110]; long long num = k / ti; long long rem = k % ti; upd = num; mid = 2 * num; long long ma = mid, mi = upd, ans; if (n == 1 || n == 2) { ma = mi; } if (x - 1 == 0 || x - 1 == n - 1) ans = mi; else ans = ma; if (rem == 0) { cout << ma << << mi << << ans << endl; return 0; } long long flag = 0; if (rem != 0) { for (long long i = 0; i < n; ++i) for (long long j = 0; j < m; ++j) { if (i == 0 || i == n - 1) { a[i][j] = upd; } else { a[i][j] = mid; } } for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) { if (i == 0 || i == n - 1) { a[i][j]++; rem--; } else { a[i][j]++; rem--; } if (rem == 0) { flag = 1; break; } } if (flag) break; } } flag = 0; if (rem != 0) { for (long long i = n - 2; i > 0; i--) { for (long long j = 0; j < m; ++j) { a[i][j]++; rem--; if (rem == 0) { flag = 1; break; } } if (flag) break; } } ma = -INFINITY, mi = INFINITY; for (long long i = 0; i < n; ++i) for (long long j = 0; j < m; ++j) { ma = max(a[i][j], ma); mi = min(a[i][j], mi); if (i == x - 1 && j == y - 1) { ans = a[i][j]; } } cout << ma << << mi << << ans << endl; return 0; } |
module pdm(clk, level, O);
parameter N = 16; /* The resolution in bits */
input wire clk;
input wire [N-1:0] level;
output wire O;
/*
* A completely ridiculous side project. Pulse Density Modulation
* for controlling led intensity. The theory is pretty simple:
* given a desired target level 0 <= T <= 1, control the output O
* in {1,0}, such that O on on average is T. Do this by
* integrating the error T - O over time and switching O such that
* the sum of (T - O) is finite.
*
* S = 0, O = 0
* forever
* S = S + (T - O)
* if (S >= 0)
* O = 1
* else
* O = 0
*
* Check: T=0, O is never turned on; T=1, O is always on; T=0.5, O toggles
*
* In fixed point arithmetic this becomes even simpler (assume N-bit arith)
* S = Sf * 2^N = Sf << N. As |S| <= 1, N+2 bits is sufficient
*
* S = 0, O = 0
* forever
* D = T + (~O + 1) << N === T + (O << N) + (O << (N+1))
* S = S + D
* O = 1 & ~(S >> (N+1))
*/
reg [N+1:0] sigma = 0;
assign O = ~sigma[N+1];
always @(posedge clk) sigma <= sigma + {O,O,level};
endmodule // pdm
|
#include <bits/stdc++.h> using namespace std; long long i, j, n, c[123456], a[1111234], b[1125678], d[123456], l, ll, s, t, k, m, xh, x, x1, y, z; string p, r, w; map<string, long long> q; int main() { cin >> n >> k >> m; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); cout << a[m] - a[m - 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T1> void deb(T1 e1) { cout << e1 << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } int main() { long long n, m, x, y, sum = 0, total; vector<long> v, v1, v2; set<int> s, s1, s2; map<long long, bool> Mymap; scanf( %I64d %I64d , &n, &m); for (long long int i = 1; i <= n; i++) { cin >> x; Mymap[x]++; } for (long long int j = 1; j <= m; j++) { if (Mymap[j] != true) { m -= j; v.push_back(j); } } cout << v.size() << endl; for (auto it : v) { cout << it << ; } cout << endl; v.clear(); Mymap.clear(); return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI4Lite Upizer
// Converts 32-bit AXI4Lite on Slave Interface to 64-bit AXI4Lite on Master Interface.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_axi4lite_upsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range 3 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [32-1:0] s_axi_wdata,
input wire [32/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [32-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [64-1:0] m_axi_wdata,
output wire [64/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [64-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg s_axi_rvalid_i ;
reg ar_done ;
reg araddr2 ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg aw_done ;
reg w_done ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1;
ar_done <= 1'b0 ;
araddr2 <= 1'b0 ;
end else begin
s_axi_arready_i <= 1'b0 ; // end single-cycle pulse
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
ar_done <= 1'b0;
end
end else if (m_axi_rvalid & ar_done) begin
s_axi_rvalid_i <= 1'b1;
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1 ; // begin single-cycle pulse
araddr2 <= s_axi_araddr[2];
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ~ar_done) begin
m_axi_arvalid_i <= 1'b1;
end
end
end
assign m_axi_arvalid = m_axi_arvalid_i ;
assign s_axi_arready = s_axi_arready_i ;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign s_axi_rdata = araddr2 ? m_axi_rdata[63:32] : m_axi_rdata[31:0];
assign s_axi_rresp = m_axi_rresp;
end else begin : gen_noread
assign m_axi_arvalid = 1'b0 ;
assign s_axi_arready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_arprot = 3'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 32'b0 ;
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
m_axi_awvalid_i <= 1'b0 ;
s_axi_awready_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
aw_done <= 1'b0;
w_done <= 1'b0;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end else begin
if (m_axi_awvalid_i) begin
if (m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
end else if (s_axi_awvalid & ~aw_done) begin
m_axi_awvalid_i <= 1'b1;
end
if (m_axi_wvalid_i) begin
if (m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_wvalid & (m_axi_awvalid_i | aw_done) & ~w_done) begin
m_axi_wvalid_i <= 1'b1;
end
end
end
end
assign m_axi_awvalid = m_axi_awvalid_i ;
assign s_axi_awready = s_axi_awready_i ;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign s_axi_wready = s_axi_awready_i ;
assign m_axi_wdata = {s_axi_wdata,s_axi_wdata};
assign m_axi_wstrb = s_axi_awaddr[2] ? {s_axi_wstrb, 4'b0} : {4'b0, s_axi_wstrb};
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign s_axi_bresp = m_axi_bresp;
end else begin : gen_nowrite
assign m_axi_awvalid = 1'b0 ;
assign s_axi_awready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_awprot = 3'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign m_axi_wdata = 64'b0 ;
assign m_axi_wstrb = 8'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign s_axi_bresp = 2'b0 ;
end
endgenerate
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_sequencer_rom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_sequencer_rom.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input debugaccess;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write & debugaccess;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_sequencer_rom.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[1010]; long long b[1010]; long long c[2020]; long long d[1010]; long long mex(long long m) { sort(b, b + m); long long j = 0; long long k = 0; long long ans = m; while (j < m) { if (b[k] > j) { ans = j; break; } else if (b[k] == j) { k++; j++; } else { k++; } } return ans; } long long check(long long m) { long long ct3 = 0; for (long long i = 1; i < m; i++) { if (a[i] < a[i - 1]) { ct3 = 1; break; } } if (ct3 == 1) return 0; else return 1; } int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long ct = 1; long long ct1 = 0; for (long long i = 0; i <= n; i++) { a[i] = 0; b[i] = 0; c[i] = 0; d[i] = 0; } for (long long i = n; i <= (n + n); i++) { c[i] = 0; } for (long long i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; if (a[i] == i) d[i] = 1; } while (ct <= (2 * n)) { if (check(n) == 1) break; ct1 = mex(n); if (ct1 == n) { for (long long i = 0; i < n; i++) { if (d[i] != 1) { a[i] = n; c[ct] = i; break; } } } else { c[ct] = ct1; a[ct1] = ct1; d[ct1] = 1; } for (long long i = 0; i < n; i++) b[i] = a[i]; ct++; } cout << ct - 1 << n ; for (long long i = 1; i < ct; i++) { cout << c[i] + 1 << ; } cout << n ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:29:26 11/16/2014
// Design Name:
// Module Name: vCounter2BCD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vCounter4DigitBCD(
input clk,
output [15:0]count,
input enable,
output cout,
input grst
);
wire [3:0]w0,w1,w2,w3;
wire c_out0,c_out1,c_out2;
wire rco0,rco1,rco2,rco3;
assign rco0 = enable;
assign rco1 = rco0 & c_out0;
assign rco2 = rco1 & c_out1;
assign rco3 = rco2 & c_out2;
vCounter counterDigit0(
.enable(rco0),
.carryout(c_out0),
.clk(clk),
.count(w0),
.grst(grst)
);
vCounter counterDigit1(
.enable(rco1),
.carryout(c_out1),
.clk(clk),
.count(w1),
.grst(grst)
);
vCounter counterDigit2(
.enable(rco2),
.carryout(c_out2),
.clk(clk),
.count(w2),
.grst(grst)
);
vCounter counterDigit3(
.enable(rco3),
.carryout(cout),
.clk(clk),
.count(w3),
.grst(grst)
);
assign count = {w3,w2,w1,w0};
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.ne1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.ne1_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 0);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_AsyncResetRegVec_36(
input clock,
input reset,
input [2:0] io_d,
output [2:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire T_8;
wire T_9;
wire T_10;
wire [1:0] T_11;
wire [2:0] T_12;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
assign io_q = T_12;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = {reg_2_q,reg_1_q};
assign T_12 = {T_11,reg_0_q};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_TB_V
`define SKY130_FD_SC_HS__SEDFXTP_TB_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sedfxtp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_TB_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_window (clock, reset, enable, start_event, test_expr, end_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event, test_expr, end_event;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WINDOW";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_window_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_window_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_window_psl_logic.v"
`else
`endmodule // ovl_window
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_4_V
`define SKY130_FD_SC_HS__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Peter Monsson.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk(clk),
.cyc(cyc));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$display("cyc=%0d", cyc);
`endif
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input integer cyc
);
`ifdef FAIL_ASSERT_1
assert property (
@(posedge clk)
1 |-> 0
) else $display("[%0t] wrong implication", $time);
assert property (
@(posedge clk)
1 |=> 0
) else $display("[%0t] wrong implication", $time);
assert property (
@(posedge clk)
cyc%3==1 |=> cyc%3==1
) else $display("[%0t] wrong implication (step)", $time);
assert property (
@(posedge clk)
cyc%3==1 |=> cyc%3==0
) else $display("[%0t] wrong implication (step)", $time);
assert property (
@(posedge clk) disable iff (cyc == 3)
(cyc == 4) |=> 0
) else $display("[%0t] wrong implication (disable)", $time);
assert property (
@(posedge clk) disable iff (cyc == 6)
(cyc == 4) |=> 0
) else $display("[%0t] wrong implication (disable)", $time);
`endif
// Test |->
assert property (
@(posedge clk)
1 |-> 1
);
assert property (
@(posedge clk)
0 |-> 0
);
assert property (
@(posedge clk)
0 |-> 1
);
// Test |=>
assert property (
@(posedge clk)
1 |=> 1
);
assert property (
@(posedge clk)
0 |=> 0
);
assert property (
@(posedge clk)
0 |=> 1
);
// Test correct handling of time step in |=>
assert property (
@(posedge clk)
cyc%3==1 |=> cyc%3==2
);
// Test correct handling of disable iff
assert property (
@(posedge clk) disable iff (cyc < 3)
1 |=> cyc > 3
);
// Test correct handling of disable iff in current cycle
assert property (
@(posedge clk) disable iff (cyc == 4)
(cyc == 4) |=> 0
);
// Test correct handling of disable iff in previous cycle
assert property (
@(posedge clk) disable iff (cyc == 5)
(cyc == 4) |=> 0
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: unencoded_cam_lut_sm.v
// Project: NF2.1
// Description: controls an unencoded muli-match cam and provides a LUT.
// Matches data and provides reg access
//
///////////////////////////////////////////////////////////////////////////////
module unencoded_cam_lut_sm_lpm
#(parameter CMP_WIDTH = 32,
parameter DATA_WIDTH = 3,
parameter LUT_DEPTH = 16,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH),
parameter DEFAULT_DATA = 0, // DATA to return on a miss
parameter RESET_DATA = {DATA_WIDTH{1'b0}}, // value of data on reset
parameter RESET_CMP_DATA = {CMP_WIDTH{1'b0}}, // value of compare datae on reset
parameter RESET_CMP_DMASK = {CMP_WIDTH{1'b0}} // value compare of data mask on reset
)
(// --- Interface for lookups
input lookup_req,
input [CMP_WIDTH-1:0] lookup_cmp_data,
input [CMP_WIDTH-1:0] lookup_cmp_dmask,
output reg lookup_ack,
output reg lookup_hit,
output [DATA_WIDTH-1:0] lookup_data,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] rd_addr, // address in table to read
input rd_req, // request a read
output [DATA_WIDTH-1:0] rd_data, // data found for the entry
output [CMP_WIDTH-1:0] rd_cmp_data, // matching data for the entry
output [CMP_WIDTH-1:0] rd_cmp_dmask, // don't cares entry
output reg rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] wr_addr,
input wr_req,
input [DATA_WIDTH-1:0] wr_data, // data found for the entry
input [CMP_WIDTH-1:0] wr_cmp_data, // matching data for the entry
input [CMP_WIDTH-1:0] wr_cmp_dmask, // don't cares for the entry
output reg wr_ack,
// --- CAM interface
input cam_busy,
input cam_match,
input [LUT_DEPTH-1:0] cam_match_addr,
output [CMP_WIDTH-1:0] cam_cmp_din,
output reg [CMP_WIDTH-1:0] cam_din,
output reg cam_we,
output reg [LUT_DEPTH_BITS-1:0] cam_wr_addr,
output [CMP_WIDTH-1:0] cam_cmp_data_mask,
output reg [CMP_WIDTH-1:0] cam_data_mask,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//-------------------- Internal Parameters ------------------------
localparam RESET = 0;
localparam READY = 1;
//---------------------- Wires and regs----------------------------
reg [LUT_DEPTH_BITS-1:0] lut_rd_addr;
reg [DATA_WIDTH+2*CMP_WIDTH-1:0] lut_rd_data;
reg [DATA_WIDTH-1:0] lut_wr_data;
reg [DATA_WIDTH+2*CMP_WIDTH-1:0] lut[LUT_DEPTH-1:0];
reg lookup_latched;
reg cam_match_found;
reg cam_lookup_done;
reg rd_req_latched;
reg cam_match_encoded;
reg cam_match_found_d1;
reg [LUT_DEPTH-1:0] cam_match_unencoded_addr;
reg [LUT_DEPTH_BITS-1:0] cam_match_encoded_addr;
reg lookup_latched_first_time;
// synthesis attribute PRIORITY_EXTRACT of cam_match_encoded_addr is force;
integer i;
/* used to track the addresses for resetting the CAM and the LUT */
reg [LUT_DEPTH_BITS:0] reset_count;
reg state;
//reg lookup_latched_first_time;
//------------------------- Logic --------------------------------
assign cam_cmp_din = lookup_cmp_data;
assign cam_cmp_data_mask = lookup_cmp_dmask;
assign lookup_data = (lookup_hit & lookup_ack) ? lut_rd_data[DATA_WIDTH-1:0] : DEFAULT_DATA;
assign rd_data = lut_rd_data[DATA_WIDTH-1:0];
assign rd_cmp_data = lut_rd_data[DATA_WIDTH+CMP_WIDTH-1:DATA_WIDTH];
assign rd_cmp_dmask = lut_rd_data[DATA_WIDTH+2*CMP_WIDTH-1:DATA_WIDTH+CMP_WIDTH];
/* encode the match address */
always @(*) begin
cam_match_encoded_addr = LUT_DEPTH[LUT_DEPTH_BITS-1:0] - 1'b1;
for (i = LUT_DEPTH-2; i >= 0; i = i-1) begin
if (cam_match_unencoded_addr[i]) begin
cam_match_encoded_addr = i[LUT_DEPTH_BITS-1:0];
end
end
end
always @(posedge clk) begin
if(reset) begin
lookup_latched <= 0;
cam_match_found <= 0;
cam_lookup_done <= 0;
rd_req_latched <= 0;
lookup_ack <= 0;
lookup_hit <= 0;
cam_we <= 0;
cam_wr_addr <= 0;
cam_din <= 0;
cam_data_mask <= 0;
wr_ack <= 0;
state <= RESET;
reset_count <= 0;
end // if (reset)
else begin
if (state == RESET && !cam_busy) begin
if(1) begin // if(reset_count == LUT_DEPTH) begin
state <= READY;
cam_we <= 1'b0;
end
else begin
reset_count <= reset_count + 1'b1;
cam_we <= 1'b1;
cam_wr_addr <= reset_count[LUT_DEPTH_BITS-1:0];
cam_din <= RESET_CMP_DATA;
cam_data_mask <= RESET_CMP_DMASK;
lut_wr_data <= RESET_DATA;
end
end
else if (state == READY) begin
/* first pipeline stage -- do CAM lookup */
lookup_latched_first_time <= lookup_req;
lookup_latched <= lookup_latched_first_time;
/* second pipeline stage -- CAM result/LUT input*/
cam_match_found <= lookup_latched & cam_match;
cam_lookup_done <= lookup_latched;
cam_match_unencoded_addr <= cam_match_addr;
/* third pipeline stage -- encode the CAM output */
cam_match_encoded <= cam_lookup_done;
cam_match_found_d1 <= cam_match_found;
lut_rd_addr <= (!cam_match_found && rd_req) ? rd_addr : cam_match_encoded_addr;
rd_req_latched <= (!cam_match_found && rd_req);
/* fourth pipeline stage -- read LUT */
lookup_ack <= cam_match_encoded;
lookup_hit <= cam_match_found_d1;
lut_rd_data <= lut[lut_rd_addr];
rd_ack <= rd_req_latched;
/* Handle writes */
if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1) begin
cam_we <= 1;
cam_wr_addr <= wr_addr;
cam_din <= wr_cmp_data ;
cam_data_mask <= ~wr_cmp_dmask;
wr_ack <= 1;
lut_wr_data <= wr_data;
end
else begin
cam_we <= 0;
wr_ack <= 0;
end // else: !if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1)
end // else: !if(state == RESET)
end // else: !if(reset)
// separate this out to allow implementation as BRAM
if(cam_we) begin
lut[cam_wr_addr] <= {cam_data_mask, cam_din, lut_wr_data};
end
end // always @ (posedge clk)
endmodule // cam_lut_sm
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const long long inf = 1e18 + 9; long long ans = inf; long long ans1 = 0, ans2 = 0; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, a, b; cin >> n >> a >> b; long long need = n * 6; if (a * b >= need) { cout << a * b << n ; cout << a << << b; return 0; } for (long long i = 0; i <= 1e7; i++) { long long new_x = a + i; long long new_y = need / new_x; if (need % new_x != 0) new_y++; new_y = max(new_y, b); new_x = max(new_x, a); if (new_x * new_y < ans) ans = new_x * new_y, ans1 = new_x, ans2 = new_y; } for (long long i = 0; i <= 1e7; i++) { long long new_y = b + i; long long new_x = need / new_y; if (need % new_y != 0) new_x++; new_y = max(new_y, b); new_x = max(new_x, a); if (new_x * new_y < ans) ans = new_x * new_y, ans1 = new_x, ans2 = new_y; } cout << ans << n ; cout << ans1 << << ans2; return 0; } |
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main (
input [1:0] vc83501,
input [1:0] v78d66e,
output [1:0] vbb8263,
output [1:0] v6f5c59
);
wire [0:1] w0;
wire [0:1] w1;
wire [0:1] w2;
assign w0 = vc83501;
assign vbb8263 = w0;
assign w1 = v78d66e;
assign v6f5c59 = w2;
v76f7ce v165459 (
.va8fcbc(w1),
.v8fd8fb(w2)
);
endmodule
//---- Top entity
module v76f7ce (
input [1:0] va8fcbc,
output [1:0] v8fd8fb
);
wire [0:1] w0;
wire [0:1] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign w0 = va8fcbc;
assign v8fd8fb = w1;
v0dbcb9 v7d1cb8 (
.v8b19dd(w0),
.v3f8943(w2),
.v64d863(w4)
);
v80ac84 v1cc6f4 (
.v67a3fc(w1),
.vee8a83(w3),
.v03aaf0(w5)
);
v3676a0 v214cf3 (
.v0e28cb(w2),
.vcbab45(w3)
);
v3676a0 v8b12b1 (
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- not-x2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- not-x2: 2-bits not gate
//---------------------------------------------------
//---- Top entity
module v0dbcb9 (
input [1:0] v8b19dd,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:1] w2;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = v8b19dd;
v0dbcb9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus2-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus2-Split-all: Split the 2-bits bus into two wires
//---------------------------------------------------
module v0dbcb9_v9a2a06 (
input [1:0] i,
output o1,
output o0
);
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module v80ac84 (
input vee8a83,
input v03aaf0,
output [1:0] v67a3fc
);
wire w0;
wire w1;
wire [0:1] w2;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v67a3fc = w2;
v80ac84_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2)
);
endmodule
//---------------------------------------------------
//-- Bus2-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus2-Join-all: Joint two wires into a 2-bits Bus
//---------------------------------------------------
module v80ac84_v9a2a06 (
input i1,
input i0,
output [1:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 5, nax = 1e6 + 5; char rodz[25]; int id[25]; int res[2 * nax]; int cob(int a) { if (a) return (a % 2 ? 1 : 0) + cob(a / 2); return 0; } int pro() { int n; cin >> n; vector<int> w; for (int _ = 1, _n = (n); _ <= _n; ++_) { int a; cin >> a; w.push_back(a); } sort(w.begin(), w.end()); reverse(w.begin(), w.end()); cin >> n; for (int i = 0, _n = (n); i < _n; ++i) cin >> rodz[i] >> id[i]; for (int m = 0, _n = (1 << n); m < _n; ++m) if (m) { int jed = cob(m), zer = n - jed; if (id[zer] == 1) { res[m] = -inf; if (rodz[zer] == p ) { for (int i = 0, _n = (n); i < _n; ++i) if (m & (1 << i)) res[m] = max(res[m], (res[m ^ (1 << i)] + w[i])); } else for (int i = 0, _n = (n); i < _n; ++i) if (m & (1 << i)) res[m] = max(res[m], (res[m ^ (1 << i)])); } else { res[m] = inf; if (rodz[zer] == p ) { for (int i = 0, _n = (n); i < _n; ++i) if (m & (1 << i)) res[m] = min(res[m], (res[m ^ (1 << i)] - w[i])); } else for (int i = 0, _n = (n); i < _n; ++i) if (m & (1 << i)) res[m] = min(res[m], (res[m ^ (1 << i)])); } } cout << res[(1 << n) - 1]; return 0; } int main() { ios_base::sync_with_stdio(0); int z = 1; for (int _ = 1, _n = (z); _ <= _n; ++_) pro(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int q[N]; int n; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n; for (int i = 1; i <= n; i++) cin >> q[i]; if (n & 1) { cout << YES << n ; cout << n - 1 << n ; for (int i = 1; i < n; i += 2) { cout << i << << i + 1 << << i + 2 << n ; } for (int i = 1; i < n; i += 2) { cout << i << << i + 1 << << n << n ; } } else { int tmp = 0; for (int i = 1; i <= n; i++) tmp ^= q[i]; if (tmp != 0) { cout << NO << n ; } else { cout << YES << n ; cout << n - 2 << n ; for (int i = 1; i < n - 1; i += 2) { cout << i << << i + 1 << << i + 2 << n ; } for (int i = 1; i < n - 1; i += 2) { cout << i << << i + 1 << << n - 1 << n ; } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_SYMBOL_V
`define SKY130_FD_SC_LP__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:45 02/20/2015
// Design Name:
// Module Name: Fetch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Fetch(
input [15:0] InstructionPacket,
input clock,
input stall,
output reg [31:0] x_input = 32'h00000000,
output reg [31:0] y_input = 32'h00000000,
output reg [31:0] z_input = 32'h00000000,
output reg [1:0] mode,
output reg operation,
output reg load = 1'b0
);
wire [3:0] Opcode;
wire [3:0] x_address;
wire [3:0] y_address;
wire [3:0] z_address;
assign Opcode = InstructionPacket[15:12];
assign x_address = InstructionPacket[11:8];
assign y_address = InstructionPacket[7:4];
assign z_address = InstructionPacket[3:0];
reg [31:0] Register_File [0:15];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // This requires pre processing. x = (a+1)/4 and y = (a-1)/4
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10;
parameter vectoring = 1'b0,
rotation = 1'b1;
parameter circular = 2'b01,
linear = 2'b00,
hyperbolic = 2'b11;
initial
begin
$readmemh("test_reg.txt",Register_File,0,15);
end
always @ (posedge clock)
begin
if (stall == 1'b0) begin
case(Opcode)
sin_cos:
begin
mode <= circular;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= Register_File[z_address];
load <= 1'b1;
end
sinh_cosh:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= Register_File[z_address];
load <= 1'b1;
end
arctan:
begin
mode <= circular;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
arctanh:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
exp:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h3F800000;
z_input <= Register_File[z_address];
load <= 1'b1;
end
sqr_root:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= Register_File[x_address];
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
division:
begin
mode <= linear;
operation <= vectoring;
x_input <= Register_File[x_address];
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
hypotenuse:
begin
mode <= circular;
operation <= vectoring;
x_input <= Register_File[x_address];
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
endcase
end
else begin
load <= 1'b0;
end
end
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output phy_rst_n_0,
inout mdio_0_io,
output mdio_0_mdc,
inout mdio_1_io,
output mdio_1_mdc,
inout mdio_2_io,
output mdio_2_mdc,
inout mdio_3_io,
output mdio_3_mdc,
input [3:0]rgmii_0_rd,
input rgmii_0_rx_ctl,
input rgmii_0_rxc,
output [3:0]rgmii_0_td,
output rgmii_0_tx_ctl,
output rgmii_0_txc,
input [3:0]rgmii_1_rd,
input rgmii_1_rx_ctl,
input rgmii_1_rxc,
output [3:0]rgmii_1_td,
output rgmii_1_tx_ctl,
output rgmii_1_txc,
input [3:0]rgmii_2_rd,
input rgmii_2_rx_ctl,
input rgmii_2_rxc,
output [3:0]rgmii_2_td,
output rgmii_2_tx_ctl,
output rgmii_2_txc,
input [3:0]rgmii_3_rd,
input rgmii_3_rx_ctl,
input rgmii_3_rxc,
output [3:0]rgmii_3_td,
output rgmii_3_tx_ctl,
output rgmii_3_txc,
input btn_rst_n,
output [3:0] testled
);
wire testpin_0;
wire testpin_1;
wire testpin_2;
reg[23:0] cnt_0;
reg[23:0] cnt_1;
reg[23:0] cnt_2;
reg[23:0] cnt_3;
always @(posedge testpin_0) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge testpin_1) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge testpin_2) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge testpin_0) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign testled[0] = cnt_0[23];
assign testled[1] = cnt_1[23];
assign testled[2] = cnt_2[23];
assign testled[3] = cnt_3[23];
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.mdio_0_io (mdio_0_io ),
.mdio_0_mdc (mdio_0_mdc ),
.mdio_1_io (mdio_1_io ),
.mdio_1_mdc (mdio_1_mdc ),
.mdio_2_io (mdio_2_io ),
.mdio_2_mdc (mdio_2_mdc ),
.mdio_3_io (mdio_3_io ),
.mdio_3_mdc (mdio_3_mdc ),
.phy_rst_n_0 (phy_rst_n_0),
.phy_rst_n_1 (),
.phy_rst_n_2 (),
.phy_rst_n_3 (),
.rgmii_0_rd (rgmii_0_rd ),
.rgmii_0_rx_ctl (rgmii_0_rx_ctl ),
.rgmii_0_rxc (rgmii_0_rxc ),
.rgmii_0_td (rgmii_0_td ),
.rgmii_0_tx_ctl (rgmii_0_tx_ctl ),
.rgmii_0_txc (rgmii_0_txc ),
.rgmii_1_rd (rgmii_1_rd ),
.rgmii_1_rx_ctl (rgmii_1_rx_ctl ),
.rgmii_1_rxc (rgmii_1_rxc ),
.rgmii_1_td (rgmii_1_td ),
.rgmii_1_tx_ctl (rgmii_1_tx_ctl ),
.rgmii_1_txc (rgmii_1_txc ),
.rgmii_2_rd (rgmii_2_rd ),
.rgmii_2_rx_ctl (rgmii_2_rx_ctl ),
.rgmii_2_rxc (rgmii_2_rxc ),
.rgmii_2_td (rgmii_2_td ),
.rgmii_2_tx_ctl (rgmii_2_tx_ctl ),
.rgmii_2_txc (rgmii_2_txc ),
.rgmii_3_rd (rgmii_3_rd ),
.rgmii_3_rx_ctl (rgmii_3_rx_ctl ),
.rgmii_3_rxc (rgmii_3_rxc ),
.rgmii_3_td (rgmii_3_td ),
.rgmii_3_tx_ctl (rgmii_3_tx_ctl ),
.rgmii_3_txc (rgmii_3_txc ),
.ext_rst (1'b0),
.testpin_0 (testpin_0 ),
.testpin_1 (testpin_1 ),
.testpin_2 (testpin_2 )
);
endmodule |
#include <bits/stdc++.h> using namespace std; const int maxn = 2000 + 5; vector<int> g[maxn]; bool used[maxn][maxn]; int v[maxn], stk[maxn]; void dfs(int z, int m, int x, bool eq) { stk[z] = x; if (z == m) { if (eq) return; for (int i = 0; i < m + 1; ++i) printf( %d , stk[i] + 1); puts( ); exit(0); } for (int i = 0; i < (int)g[x].size(); ++i) { if (!used[x][g[x][i]] && !used[g[x][i]][x]) { if (!eq || g[x][i] >= v[z + 1]) { used[x][g[x][i]] = true; dfs(z + 1, m, g[x][i], g[x][i] > v[z + 1] ? false : eq); used[x][g[x][i]] = false; } } } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m + 1; ++i) { scanf( %d , &v[i]); --v[i]; } for (int i = 0; i < m; ++i) { g[v[i]].push_back(v[i + 1]); g[v[i + 1]].push_back(v[i]); } for (int i = 0; i < n; ++i) { sort(g[i].begin(), g[i].end()); } dfs(0, m, v[0], true); puts( No solution ); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; const int INF = (int)1E8; const long long INF64 = (long long)1E18; const double EPS = 1E-9; const double PI = acos((double)0) * 2; const int MAXN = 160; int n, cost[MAXN]; string s; bool read() { if (!(cin >> n)) return false; for (int i = 0; i < int(n); ++i) { cin >> cost[i + 1]; if (cost[i + 1] == -1) cost[i + 1] = -INF; } cin >> s; return true; } int d[MAXN][MAXN][MAXN]; bool u[MAXN][MAXN][MAXN]; int get_d(int l, int r, int len) { if (l > r) return cost[len]; if (l == r) return max(cost[len] + cost[1], cost[len + 1]); int& my = d[l][r][len]; bool& myu = u[l][r][len]; if (myu) return my; myu = true; my = -INF; if (len != 0) my = max(my, cost[len] + get_d(l, r, 0)); for (int i = int(l); i < int(r); ++i) my = max(my, get_d(l, i, 0) + get_d(i + 1, r, len)); for (int i = int(l + 1); i < int(r + 1); ++i) my = max(my, get_d(i, r, 0) + get_d(l, i - 1, len)); for (int i = int(l); i < int(r + 1); ++i) my = max(my, get_d(l, i - 1, 0) + cost[len + 1] + get_d(i + 1, r, 0)); if (s[l] == s[r]) my = max(my, get_d(l + 1, r - 1, len + 2)); return my; } int d2[MAXN]; void solve() { memset(u, 0, sizeof u); int x = get_d(0, n - 1, 0); for (int i = 0; i < int(n); ++i) { d2[i] = i ? d2[i - 1] : 0; for (int j = 0; j < int(i + 1); ++j) d2[i] = max(d2[i], get_d(j, i, 0) + (j ? d2[j - 1] : 0)); } cout << d2[n - 1] << endl; } int main() { if (!read()) throw; solve(); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) using namespace std; vector<vector<int> > vec; set<vector<int> > myset, vis; map<vector<int>, int> p; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, t, a, b; cin >> n >> m >> t; vec.resize(n); while (m--) { cin >> a >> b; a--, b--; vec[a].push_back(b); vec[b].push_back(a); } while (t--) { cin >> m >> a >> b; m--, a--, b--; myset.insert({m, a, b}); } vector<int> state, ans; queue<vector<int> > q; bool ok = 0; for (auto it : vec[0]) { if (it == (n - 1)) { cout << 1 << n << 1 << << n << n ; return 0; } q.push({0, it}), vis.insert({0, it}); } while (!q.empty()) { vector<int> f = q.front(); q.pop(); for (auto it : vec[f[1]]) { if (myset.find({f[0], f[1], it}) != myset.end()) continue; if (vis.find({f[1], it}) != vis.end()) continue; if (it == (n - 1)) { ok = 1, state = f; break; } q.push({f[1], it}); p[{f[1], it}] = f[0]; vis.insert({f[1], it}); } if (ok) break; } if (!ok) { cout << -1; return 0; } ans.push_back(state[1]); int c = 100005; while ((state[0] != 0)) { ans.push_back(state[0]); t = p[state]; state[1] = state[0], state[0] = t; } reverse(ans.begin(), ans.end()); cout << ans.size() + 1 << n1 ; for (auto it : ans) cout << it + 1 << ; cout << n << n ; return 0; } |
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
Require Import Coq.Logic.Eqdep Coq.Lists.List.
Require Import Omega.
Set Primitive Projection.
Set Implicit Arguments.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite app_ass.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
| [ H : ?P = _
, H1: ?P = _ |- _ ] => rewrite H1 in H; clear H1
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => try rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'. |
#include <bits/stdc++.h> using namespace std; const int NN = 111 * 1000; int n, a, d; int t[NN], v[NN]; int main() { ios::sync_with_stdio(false); cin >> n >> a >> d; for (int i = 0; i < n; i++) { cin >> t[i] >> v[i]; } double Max = -1.; for (int i = 0; i < n; i++) { double v2 = (double)v[i] * v[i]; double dx = v2 / a / 2.; dx = min((double)d, dx); double tl = sqrt(dx * 2. / a); double tr = (d - dx) / v[i]; double t_cur = t[i] + tl + tr; Max = max(Max, t_cur); printf( %.16f n , Max); } } |
#include <bits/stdc++.h> using namespace std; int n, m, aa[300005], bb[300005], v[1000005], q; int x[4000005], y[4000005], dx; void build(int l, int r, int i) { if (l + 1 == r) { y[i] = v[l]; return; } int mi = (l + r) / 2; build(l, mi, i * 2); build(mi, r, i * 2 + 1); y[i] = max(y[i * 2], y[i * 2 + 1]); } void add(int a, int b, int l, int r, int i) { if (a == l && b == r) { x[i] += dx; y[i] += dx; return; } int mi = (l + r) / 2; if (a < mi) add(a, min(mi, b), l, mi, i * 2); if (mi < b) add(max(a, mi), b, mi, r, i * 2 + 1); y[i] = max(y[i * 2], y[i * 2 + 1]) + x[i]; } int find(int l, int r, int i, int vv) { if (l + 1 == r) return l; vv -= x[i]; int mi = (l + r) / 2; if (y[i * 2 + 1] > vv) return find(mi, r, i * 2 + 1, vv); return find(l, mi, i * 2, vv); } int main() { scanf( %d%d , &n, &m); v[0] = n + 1; for (int i = 1; i <= n; i++) { scanf( %d , aa + i); v[aa[i]]++; } for (int i = 1; i <= m; i++) { scanf( %d , bb + i); v[bb[i]]--; } for (int i = 1000000; i >= 0; i--) v[i] += v[i + 1]; build(0, 1000001, 1); scanf( %d , &q); while (q--) { int ta, tb, tc; scanf( %d%d%d , &ta, &tb, &tc); if (ta == 1) { if (aa[tb] < tc) { dx = 1; add(aa[tb] + 1, tc + 1, 0, 1000001, 1); } else if (aa[tb] > tc) { dx = -1; add(tc + 1, aa[tb] + 1, 0, 1000001, 1); } aa[tb] = tc; } else { if (bb[tb] < tc) { dx = -1; add(bb[tb] + 1, tc + 1, 0, 1000001, 1); } else if (bb[tb] > tc) { dx = 1; add(tc + 1, bb[tb] + 1, 0, 1000001, 1); } bb[tb] = tc; } ta = find(0, 1000001, 1, 0); if (ta == 0) ta = -1; printf( %d n , ta); } } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module contains a character map for 128 different ASCII characters. *
* *
******************************************************************************/
module altera_up_video_ascii_rom_128 (
// Inputs
clk,
clk_en,
character,
x_coordinate,
y_coordinate,
// Bidirectionals
// Outputs
character_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input [ 6: 0] character;
input [ 2: 0] x_coordinate;
input [ 2: 0] y_coordinate;
// Bidirectionals
// Outputs
output reg character_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [12: 0] character_address;
// Internal Registers
reg rom [8191:0];
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
initial
begin
$readmemb("altera_up_video_ascii_rom_128.txt", rom);
end
always @ (posedge clk)
begin
if (clk_en)
character_data <= rom[character_address];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign character_address = {character, y_coordinate, x_coordinate};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long int lli; const lli N = 1000009, K = z - a + 1; string s, t; lli n, k, a[K], b[K]; void Solve() { for(int i = 0; i < K - 1; i++) { while(a[i] > b[i] && a[i] >= k) { a[i] -= k; a[i + 1] += k; } } for(int i = 0; i < K; i++) { if(a[i] != b[i]) { cout<< No <<endl; return ; } } cout<< Yes <<endl; } void Inp() { lli ntest; cin>>ntest; while(ntest--) { cin>>n>>k>>s>>t; for(int i = 0; i < K; i++) { a[i] = 0; b[i] = 0; } for(int i = 0; i < n; i++) { a[s[i] - a ]++; b[t[i] - a ]++; } Solve(); } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); //freopen( inp.inp , r ,stdin); Inp(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRDLSTP_PP_SYMBOL_V
/**
* srdlstp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Samuel A. Falvo II
//
// Create Date: 18:16:26 10/30/2011
// Design Name: UXA 1A
// Module Name: M_uxa_ps2_wrtlgc
// Project Name: Kestrel-2
// Target Devices: Nexys2
// Tool versions:
// Description:
// When the PS/2 deserializer receives a byte, it asserts
// its frame_o signal to tell upstream logic that data is now
// available for processing. We want to take that same data
// and stuff it into the 16-byte FIFO. Only after that's done
// do we want to clear the deserializer's shift register for
// the next incoming byte.
//
// All this timing-based behavior depends on a state-machine.
// This module implements the state machine necessary to achieve
// the above goals.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_uxa_ps2_wrtlgc(
input frame_i,
output reset_o,
output we_o,
output ptr_inc_o,
input sys_clk_i,
input sys_reset_i
);
// We kick things off only when frame_i becomes true.
// We don't much care about the level of the signal.
// Thus, we need a historical copy of frame_i to do
// synchronized edge-detection with.
reg prev_frame_i;
// To prevent spurious timing, we need to synchronize
// frame_i against the system clock.
reg curr_frame_i;
// We're only concerned with the rising edge of frame_i.
wire ready = curr_frame_i & ~prev_frame_i;
// The first thing we want to do when we have data ready
// is to write the data byte into the FIFO.
assign we_o = ready;
// After that's done, we want to reset the deserializer,
// so that we're ready for the next byte.
reg reset;
assign reset_o = reset;
// At the same time as we're resetting the deserializer,
// we can increment the FIFO's write pointer.
assign ptr_inc_o = reset;
// We use a walking bit counter to implement our state
// machine. The timing diagram should look something
// like this:
// _____ _____ _____ ___
// sys_clk_i / \_____/ \_____/ \_____/
// _______________________
// frame_i _________/ \\\\\\\\\\\\\\\\\\\______
// ___________
// we_o ______________/ \_____________
// ___________
// reset_o __________________________/ \_
// ___________
// ptr_inc_o __________________________/ \_
always @(posedge sys_clk_i) begin
if (sys_reset_i) begin
curr_frame_i <= 0;
prev_frame_i <= 0;
reset <= 0;
end else begin
curr_frame_i <= frame_i;
prev_frame_i <= curr_frame_i;
reset <= we_o;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double PI = 3.141592653589793; const int P = 1e9 + 9; class mint { public: static int init_siz; static vector<mint> inverse, factorial; static int mintP; int n; static mint exp(mint a, long long e) { mint res = 1; while (e) { if (e & 1) res *= a; a *= a; e >>= 1; } return res; } static void init(int n) { init_siz = n; inverse.resize(n + 1); factorial.resize(n + 1); factorial[0] = 1; for (int i = 1; i <= n; i++) factorial[i] = factorial[i - 1] * i; inverse[n] = exp(factorial[n], mintP - 2); for (int i = n - 1; i >= 0; i--) inverse[i] = inverse[i + 1] * (i + 1); } static mint inv(mint const& a) { return (init_siz >= a.n ? inverse[a.n] * (a.n > 1 ? fac(a - 1) : 1) : exp(a, mintP - 2)); } static mint cinv(mint const& a) { return (init_siz >= a.n ? inverse[a.n] : exp(fac(a), mintP - 2)); } static mint fac(mint const& a) { if (init_siz >= a.n) return factorial[a.n]; else { mint out = 1; for (int i = 0; i < a.n; i++) out *= (i + 1); return out; } } mint(long long val = 0) { n = val % mintP; if (n < 0) n += mintP; } mint& operator+=(mint const& b) { n += b.n; if (n >= mintP) n -= mintP; return *this; } mint& operator-=(mint const& b) { n -= b.n; if (n < 0) n += mintP; return *this; } mint& operator*=(mint const& b) { n = (long long)n * b.n % mintP; return *this; } mint exp(long long e) { return exp(*this, e); } mint inv() { return inv(*this); } mint& operator/=(mint const& b) { return *this *= inv(b); } friend std::ostream& operator<<(std::ostream& os, mint const& a) { return os << (a.n < 0 ? a.n + mintP : a.n); } friend mint operator+(mint a, mint const b) { return a += b; } friend mint operator-(mint a, mint const b) { return a -= b; } friend mint operator-(mint const a) { return 0 - a; } friend mint operator*(mint a, mint const b) { return a *= b; } friend mint operator/(mint a, mint const b) { return a /= b; } friend bool operator==(mint const& a, mint const& b) { return a.n == b.n; } friend bool operator!=(mint const& a, mint const& b) { return a.n != b.n; } }; int mint::init_siz = 0; int mint::mintP = P; vector<mint> mint::factorial, mint::inverse; class dsu { private: int N; vector<int> par; int getpar(int v) { if (par[v] != v) par[v] = getpar(par[v]); return par[v]; } pair<int, int> getparhei(int v) { if (par[v] == v) return {v, 0}; else { auto temp = getparhei(par[v]); temp.second++; return temp; } } public: dsu(int siz) { N = siz; par.resize(N); iota(par.begin(), par.end(), 0); } int id(int v) { return getpar(v); } void merge(int v1, int v2) { auto par1 = getparhei(v1); auto par2 = getparhei(v2); if (par1.second < par2.second) swap(par1, par2); par[par2.first] = par1.first; } bool same(int v1, int v2) { return getpar(v1) == getpar(v2); } }; void solve() { int n, m; cin >> n >> m; dsu id(n); int cnt = 0; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; if (id.id(u) == id.id(v)) cnt++; else id.merge(u, v); cout << mint::exp(2, cnt) - 1 << n ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int T = 1; for (int c = 1; c < T + 1; c++) { solve(); } } |
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