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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { long long tmp; while (b) { a %= b; tmp = a; a = b; b = tmp; } return a; } int main() { int n; cin >> n; vector<int> a(n + 1, 0); for (int i = 0; i < n; i++) { cin >> a[i + 1]; } sort(a.begin(), a.end()); long long sum1 = 0, sum2 = 0; vector<long long> sum(n + 1, 0); for (int i = 1; i <= n; i++) { sum[i] += sum[i - 1] + (long long)i * (a[i] - a[i - 1]); sum1 += sum[i]; sum2 += a[i]; } long long num = 2 * sum1 - sum2; long long den = n; long long g = gcd(num, den); cout << num / g << << den / g << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int eps = -1e6; const int MAX = 200010; long long int n, k, x; long long int a[MAX], pre[MAX], s[MAX]; long long int expo(long long int a, long long int b) { long long int x = 1, y = a; while (b > 0) { if (b & 1) x = (x * y); y = (y * y); b >>= 1; } return x; } int main() { ios_base::sync_with_stdio(0); cin >> n >> k >> x; for (int i = 0, _n = (n); i < _n; ++i) { cin >> a[i]; if (i == 0) pre[i] = a[i]; else pre[i] = pre[i - 1] | a[i]; } for (int i = n - 1; i >= 0; i--) { if (i == n - 1) s[i] = a[i]; else s[i] = s[i + 1] | a[i]; } long long int tmp = expo(x, k); long long int res = 0; for (int i = 0, _n = (n); i < _n; ++i) { long long int z = a[i] * 1ll * tmp; if (i == 0) res = max(res, z | s[1]); else if (i == n - 1) res = max(res, pre[n - 2] | z); else res = max(res, pre[i - 1] | z | s[i + 1]); } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Query { int id, left, right, time, blockLeft, blockRight; Query() : id(-1), left(-1), right(-1), time(-1), blockLeft(-1), blockRight(-1) {} Query(int id, int left, int right, int time, int blockLeft, int blockRight) : id(id), left(left), right(right), time(time), blockLeft(blockLeft), blockRight(blockRight) {} bool operator<(const Query &otherQuery) const { if (blockLeft != otherQuery.blockLeft) { return blockLeft < otherQuery.blockLeft; } if (blockRight != otherQuery.blockRight) { return blockRight < otherQuery.blockRight; } return time < otherQuery.time; } }; struct Operation { int pos, oldValue, newValue; Operation() : pos(-1), oldValue(-1), newValue(-1) {} Operation(int pos, int oldValue, int newValue) : pos(pos), oldValue(oldValue), newValue(newValue) {} }; void del(int value, int *cnts, int *saveValues) { saveValues[cnts[value]]--; cnts[value]--; saveValues[cnts[value]]++; } void add(int value, int *cnts, int *saveValues) { saveValues[cnts[value]]--; cnts[value]++; saveValues[cnts[value]]++; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; int sqrtValue = pow(n, 2.0 / 3.0), *values = new int[n + 1], *tmpValues = new int[n + 1]; if (sqrtValue == 0) sqrtValue = 1; vector<int> disValues; for (int i = 1; i <= n; i++) { cin >> values[i]; tmpValues[i] = values[i]; disValues.push_back(values[i]); } Query *querys = new Query[q + 1]; Operation *opts = new Operation[q + 1]; int cntQuerys = 0, cntOpts = 0; for (int i = 1; i <= q; i++) { int opt; cin >> opt; if (opt == 1) { int left, right; cin >> left >> right; ++cntQuerys; querys[cntQuerys] = Query(cntQuerys, left, right, cntOpts, left / sqrtValue, right / sqrtValue); } else { int pos, value; cin >> pos >> value; ++cntOpts; opts[cntOpts] = Operation(pos, tmpValues[pos], value); tmpValues[pos] = value; disValues.push_back(value); } } sort(disValues.begin(), disValues.end()); disValues.resize(unique(disValues.begin(), disValues.end()) - disValues.begin()); for (int i = 1; i <= cntOpts; i++) { Operation &tmpOpt = opts[i]; tmpOpt.oldValue = lower_bound(disValues.begin(), disValues.end(), tmpOpt.oldValue) - disValues.begin(); tmpOpt.newValue = lower_bound(disValues.begin(), disValues.end(), tmpOpt.newValue) - disValues.begin(); } for (int i = 1; i <= n; i++) { values[i] = lower_bound(disValues.begin(), disValues.end(), values[i]) - disValues.begin(); } int valueSize = static_cast<int>(disValues.size()), *cnts = new int[valueSize + 3], *saveValues = new int[n + 2]; memset(cnts, 0, sizeof(int) * (valueSize + 3)); memset(saveValues, 0, sizeof(int) * (n + 2)); int *results = new int[cntQuerys + 1]; sort(querys + 1, querys + cntQuerys + 1); int l = 1, r = 0, time = 0; for (int i = 1; i <= cntQuerys; i++) { Query &tmpQuery = querys[i]; while (r < tmpQuery.right) { r++; add(values[r], cnts, saveValues); } while (l > tmpQuery.left) { l--; add(values[l], cnts, saveValues); } while (r > tmpQuery.right) { del(values[r], cnts, saveValues); r--; } while (l < tmpQuery.left) { del(values[l], cnts, saveValues); l++; } while (time < tmpQuery.time) { time++; Operation &tmpOpt = opts[time]; if (tmpOpt.pos >= l && tmpOpt.pos <= r) { del(tmpOpt.oldValue, cnts, saveValues); add(tmpOpt.newValue, cnts, saveValues); } values[tmpOpt.pos] = tmpOpt.newValue; } while (time > tmpQuery.time) { Operation &tmpOpt = opts[time]; if (tmpOpt.pos >= l && tmpOpt.pos <= r) { del(tmpOpt.newValue, cnts, saveValues); add(tmpOpt.oldValue, cnts, saveValues); } values[tmpOpt.pos] = tmpOpt.oldValue; time--; } for (int i = 1;; i++) { if (i > n) { results[tmpQuery.id] = 0; } if (saveValues[i] == 0) { results[tmpQuery.id] = i; break; } } } for (int i = 1; i <= cntQuerys; i++) { cout << results[i] << endl; } return 0; } |
// This is the first part of a two-part test that checks that the argument to
// a $signed or $unsigned function is treated as a self-determined expression.
// This part performs tests where the argument is unsigned.
module pr2922063a;
reg [3:0] op1;
reg [2:0] op2;
reg [7:0] result;
reg fail;
task check_result;
input [7:0] value;
begin
$write("Expected %b, got %b", value, result);
if (result !== value) begin
$write(" *");
fail = 1;
end
$write("\n");
end
endtask
initial begin
fail = 0;
$display("-- Addition tests --");
op1 = 4'b1111; op2 = 3'b111;
result = 8'sd0 + $signed(op1 + op2);
check_result(8'b00000110);
result = 8'sd0 + $unsigned(op1 + op2);
check_result(8'b00000110);
op1 = 4'b1000; op2 = 3'b011;
result = 8'sd0 + $signed(op1 + op2);
check_result(8'b11111011);
result = 8'sd0 + $unsigned(op1 + op2);
check_result(8'b00001011);
$display("-- Multiply tests --");
op1 = 4'b0101; op2 = 3'b100;
result = 8'sd0 + $signed(op1 * op2);
check_result(8'b00000100);
result = 8'sd0 + $unsigned(op1 * op2);
check_result(8'b00000100);
op1 = 4'b0010; op2 = 3'b100;
result = 8'sd0 + $signed(op1 * op2);
check_result(8'b11111000);
result = 8'sd0 + $unsigned(op1 * op2);
check_result(8'b00001000);
$display("-- Left ASR tests --");
op1 = 4'b1010;
result = 8'sd0 + $signed(op1 <<< 1);
check_result(8'b00000100);
result = 8'sd0 + $unsigned(op1 <<< 1);
check_result(8'b00000100);
op1 = 4'b0101;
result = 8'sd0 + $signed(op1 <<< 1);
check_result(8'b11111010);
result = 8'sd0 + $unsigned(op1 <<< 1);
check_result(8'b00001010);
$display("-- Right ASR tests --");
op1 = 4'b1010;
result = 8'sd0 + $signed(op1 >>> 1);
check_result(8'b00000101);
result = 8'sd0 + $unsigned(op1 >>> 1);
check_result(8'b00000101);
op1 = 4'b1010;
result = 8'sd0 + $signed(op1 >>> 0);
check_result(8'b11111010);
result = 8'sd0 + $unsigned(op1 >>> 0);
check_result(8'b00001010);
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:38:58 12/01/2015
// Design Name: peripheral_crc_7
// Module Name: /home/jorge/Documentos/SPI_SD/crc_7_peripheral_testbench.v
// Project Name: SPI_SD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: peripheral_crc_7
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module crc_7_peripheral_testbench;
// Inputs
reg clk;
reg rst;
reg [15:0] d_in;
reg cs;
reg [3:0] addr;
reg rd;
reg wr;
// Outputs
wire [15:0] d_out;
//parameters
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
// Instantiate the Unit Under Test (UUT)
peripheral_crc_7 uut (
.clk(clk),
.rst(rst),
.d_in(d_in),
.cs(cs),
.addr(addr),
.rd(rd),
.wr(wr),
.d_out(d_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
d_in = 0;
cs = 1;
addr = 0;
rd = 0;
wr = 0;
//clk
#OFFSET
forever
begin
clk = 1'b1;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Wait 10 ns for global reset to finish
#10;
rst = 1;
#10;
rst = 0;
#10
// se coloca en la direccion data in la primera parte del dato a operar
wr = 1;
addr = 4'h0;
d_in = 16'h3A5E;
#10
//se coloca start en 1 en la direccion de start
wr = 1;
addr = 4'h2;
d_in [0] = 1;
#10
//se coloca start en 0 en la direccion de start
wr = 1;
addr = 4'h2;
d_in [0] = 0;
#10
// se lee la direccion done
wr = 0;
rd = 1;
addr = 4'h4;
#10
@(*)begin
if (d_out[0]) begin //si se tiene un nuevo dato se lee la direccion d_out y se resetea
addr = 4'h6;
#20
rst=1;
cs=0;
#10
rst=0;
end
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module writes data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_out_serializer (
// Inputs
clk,
reset,
transmit_data,
transmit_data_en,
// Bidirectionals
// Outputs
fifo_write_space,
serial_data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] transmit_data;
input transmit_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_write_space;
output reg serial_data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_transmitted;
wire read_fifo_en;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
wire [DW: 0] data_from_fifo;
// Internal Registers
reg transmitting_data;
reg [DW+1:0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_write_space <= 8'h00;
else
fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
serial_data_out <= 1'b1;
else
serial_data_out <= data_out_shift_reg[0];
end
always @(posedge clk)
begin
if (reset)
transmitting_data <= 1'b0;
else if (all_bits_transmitted)
transmitting_data <= 1'b0;
else if (fifo_is_empty == 1'b0)
transmitting_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_out_shift_reg <= {(DW + 2){1'b1}};
else if (read_fifo_en)
data_out_shift_reg <= {data_from_fifo, 1'b0};
else if (shift_data_reg_en)
data_out_shift_reg <=
{1'b1, data_out_shift_reg[DW+1:1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_fifo_en =
~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_Out_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~transmitting_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (shift_data_reg_en),
.baud_clock_falling_edge (),
.all_bits_transmitted (all_bits_transmitted)
);
defparam
RS232_Out_Counters.CW = CW,
RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Counters.TDW = TDW;
altera_up_sync_fifo RS232_Out_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (transmit_data_en & ~fifo_is_full),
.write_data (transmit_data),
.read_en (read_fifo_en),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (data_from_fifo)
);
defparam
RS232_Out_FIFO.DW = DW,
RS232_Out_FIFO.DATA_DEPTH = 128,
RS232_Out_FIFO.AW = 6;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<char> v; string s; int main() { cin >> s; for (int i = 0; i < s.size(); i++) { if (!v.empty() && v.back() == s[i]) v.pop_back(); else v.push_back(s[i]); } cout << (v.empty() ? Yes : No ); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:36:58 05/16/2015
// Design Name:
// Module Name: IO_memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IO_memory(
input clock,
input IO_write,
input [11:0] IO_address,
input [15:0] IO_data_in,
input [15:0] processor_input,
input processor_uart_rx,
output reg [15:0] IO_data_out,
output reg [15:0] processor_output,
output processor_uart_tx,
output internal_IRQ
);
reg [3:0] IO_selection_enable;
reg [3:0] IO_selection_enable_next;
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
reg [15:0] uart_rx_stat, uart_rx_stat_1, uart_rx_stat_2, uart_rx_stat_3, uart_rx_stat_4, uart_rx_stat_5;
initial begin
IO_data_out = 0;
processor_output = 0;
IO_selection_enable = 0;
IO_selection_enable_next = 0;
uart_rx_stat = 0;
end
wire [15:0] ram_data_out;
RAM_4K data_ram (
.clka(clock), // input clka
.ena(1'b1), // input ena
.wea(IO_write), // input [0 : 0] wea
.addra(IO_address), // input [11 : 0] addra
.dina(IO_data_in), // input [15 : 0] dina
.douta(ram_data_out) // output [15 : 0] douta
);
uart uart_module (
.clk(clock),
.rst(0),
.input_axis_tdata(uart_tx_axis_tdata),
.input_axis_tvalid(uart_tx_axis_tvalid),
.input_axis_tready(uart_tx_axis_tready),
.output_axis_tdata(uart_rx_axis_tdata),
.output_axis_tvalid(uart_rx_axis_tvalid),
.output_axis_tready(uart_rx_axis_tready),
.rxd(processor_uart_rx),
.txd(processor_uart_tx),
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
.prescale(25000000/(115200*8))
);
always @(*) begin
case (IO_address)
12'hff0: begin
IO_selection_enable <= 4'h1; // processor_input
end
12'hff1: begin
IO_selection_enable <= 4'h2; // processor_output
end
12'hff2: begin
IO_selection_enable <= 4'h3; // UART RX
end
12'hff3: begin
IO_selection_enable <= 4'h4; // UART TX
end
default: begin
IO_selection_enable <= 4'h0; // RAM
end
endcase
// For read
if (clock == 1) begin
case (IO_selection_enable_next)
4'h0: IO_data_out = ram_data_out; // RAM
4'h1: IO_data_out = processor_input; // processor_input
4'h2: IO_data_out = processor_output; // processor_output
4'h3: IO_data_out = uart_rx_stat; // UART RX
4'h4: IO_data_out = {6'h00, uart_tx_axis_tready, uart_tx_axis_tvalid, uart_tx_axis_tdata}; // UART TX
endcase
end
end
always @(negedge clock) begin
IO_selection_enable_next <= IO_selection_enable;
// For write
if (IO_write == 1) begin
case (IO_selection_enable) ////////////////////////////////// next olabilir
4'h2: processor_output <= IO_data_in; // processor_output
4'h3: uart_rx_axis_tready <= IO_data_in[9]; // UART RX
4'h4: begin // UART TX
uart_tx_axis_tdata <= IO_data_in[7:0];
uart_tx_axis_tvalid <= IO_data_in[8];
end
endcase
end
end
always @(posedge clock) begin
uart_rx_stat_1 = {6'h00, uart_rx_axis_tready, uart_rx_axis_tvalid, uart_rx_axis_tdata};
uart_rx_stat_2 = uart_rx_stat_1;
uart_rx_stat_3 = uart_rx_stat_2;
uart_rx_stat_4 = uart_rx_stat_3;
uart_rx_stat_5 = uart_rx_stat_4;
uart_rx_stat = uart_rx_stat_5;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/15/2016 12:05:10 PM
// Design Name:
// Module Name: Full_Adder_PG
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Full_Adder_PG
#(parameter SWR=26) (
input wire clk,
input wire rst,
input wire [SWR-1:0] Op_A_i,
input wire [SWR-1:0] Op_B_i,
input wire C_i, //Carry in
////////////////////////////////77
output wire [SWR-1:0] S_o, // Solution out
output reg [SWR-1:1] Cn_o, //Carry for each Full adder
output wire C_o, //Carry out for last full adder
output wire [SWR-1:0] P_o //Propagate (for LZA)
);
wire [SWR-1:1] C_n;
wire reg_to_carry;
genvar j;
generate
case (SWR)
26: begin
for (j=0; j<SWR ; j=j+1) begin
case (j)
0:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[0]),
.Op_B_i(Op_B_i[0]),
.C_i(C_i),
.S_o(S_o[0]),
.C_o(C_n[1]),
.P_o(P_o[0])
);
end
SWR-1:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[j]),
.Op_B_i(Op_B_i[j]),
.C_i(C_n[j]),
.S_o(S_o[j]),
.C_o(C_o),
.P_o(P_o[j])
);
end
default:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[j]),
.Op_B_i(Op_B_i[j]),
.C_i(C_n[j]),
.S_o(S_o[j]),
.C_o(C_n[j+1]),
.P_o(P_o[j])
);
end
endcase
end
end
default: begin
for (j=0; j<27 ; j=j+1) begin
case (j)
0:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[0]),
.Op_B_i(Op_B_i[0]),
.C_i(C_i),
.S_o(S_o[0]),
.C_o(C_n[1]),
.P_o(P_o[0])
);
end
default:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[j]),
.Op_B_i(Op_B_i[j]),
.C_i(C_n[j]),
.S_o(S_o[j]),
.C_o(C_n[j+1]),
.P_o(P_o[j])
);
end
endcase
end
RegisterAdd #(.W(1)) MidRegister ( //Data Add_Subtract input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(C_n[27]),
.Q(reg_to_carry)
);
for (j=27; j<SWR ; j=j+1) begin
case (j)
27:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[27]),
.Op_B_i(Op_B_i[27]),
.C_i(reg_to_carry),
.S_o(S_o[27]),
.C_o(C_n[28]),
.P_o(P_o[27])
);
end
SWR-1:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[j]),
.Op_B_i(Op_B_i[j]),
.C_i(C_n[j]),
.S_o(S_o[j]),
.C_o(C_o),
.P_o(P_o[j])
);
end
default:begin
Full_Adder_PG_1b FA1bit(
.Op_A_i(Op_A_i[j]),
.Op_B_i(Op_B_i[j]),
.C_i(C_n[j]),
.S_o(S_o[j]),
.C_o(C_n[j+1]),
.P_o(P_o[j])
);
end
endcase
end
end
endcase
endgenerate
always @(C_n)
Cn_o <= C_n;
endmodule |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 5; char a[MAX_N]; int main() { int N; cin >> N; scanf( %s , a + 1); int cnt = 0; for (int i = 1; i <= N; i++) { if (a[i] == S && a[i] >= 2 && a[i - 1] == G ) { cnt++; } } if (a[N] == G ) cnt++; int len = 0, prelen = (cnt >= 2), ans = 0; for (int i = 1; i <= N; i++) { if (a[i] == G ) { len++; ans = max(ans, len + prelen); } if (a[i] == S ) { if (2 <= i && i <= N - 1 && a[i - 1] == G && a[i + 1] == G ) { if (cnt == 2) { prelen = len; } else if (cnt >= 3) { prelen = len + 1; } } else { prelen = (cnt >= 2); } len = 0; } } cout << ans << endl; return 0; } |
// vga.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module vga (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) vga (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) using namespace std; int n; string s; string A[] = { 123456 , 154236 , 145326 , 516324 , 261453 , 132546 }; string B[] = { 123456 , 523164 , 623541 , 423615 }; vector<string> P; vector<string> T; vector<string> H; bool BB[1000]; bool F(string a, string b) { for (long long(i) = (0); (i) < (T.size()); ++(i)) { string t = a; for (long long(j) = (0); (j) < (6); ++(j)) t[j] = a[T[i][j] - 0 ]; if (t == b) return true; } return false; } int main() { cin >> s; int Q[6]; for (long long(i) = (0); (i) < (6); ++(i)) Q[i] = i; do { string p = ; for (long long(i) = (0); (i) < (6); ++(i)) p += char( 0 + Q[i]); P.push_back(p); } while (next_permutation(Q, Q + 6)); for (long long(i) = (0); (i) < (6); ++(i)) for (long long(j) = (0); (j) < (4); ++(j)) { string t = A[i]; string p = t; for (long long(k) = (0); (k) < (6); ++(k)) { int x = B[j][k] - 0 ; x--; p[k] = t[x]; p[k]--; } T.push_back(p); } for (long long(i) = (0); (i) < (P.size()); ++(i)) { string t = ; for (long long(j) = (0); (j) < (6); ++(j)) t += s[P[i][j] - 0 ]; H.push_back(t); } int res = 0; for (long long(i) = (0); (i) < (H.size()); ++(i)) if (BB[i] == false) { res++; for (long long(j) = (i + 1); (j) < (H.size()); ++(j)) if (F(H[i], H[j])) BB[j] = true; } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > que; stringstream ssin; const long long LINF = 0x7fffffffffffffffll; const int N = 4e5 + 5, M = 4e5 + 5, mod = 1e9 + 7, INF = 0x3f3f3f3f; int n, idx, sum; int e[M], ne[M], h[N], ans[N]; inline long long read() { char c = getchar(); long long x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } void add(int a, int b) { e[idx] = b; ne[idx] = h[a]; h[a] = idx++; } void dfs(int u, int fa) { for (int i = h[u]; ~i; i = ne[i]) { int v = e[i]; if (v == fa) continue; dfs(v, u); } if (fa != -1) { if (ans[u] == u) { swap(ans[u], ans[fa]); sum += 2; } } } int main() { n = read(); memset(h, -1, sizeof h); ; for (int i = 1; i < n; ++i) { ans[i] = i; int a, b; a = read(); b = read(); add(a, b); add(b, a); } ans[n] = n; dfs(1, -1); if (ans[1] == 1) { sum += 2; for (int i = h[1]; ~i; i = ne[i]) { int v = e[i]; swap(ans[1], ans[v]); break; } } cout << sum << n ; for (int i = 1; i <= n; ++i) cout << ans[i] << ; puts( ); } |
#include <bits/stdc++.h> const int N = 1e5 + 5; const unsigned long long bigN = 1e18; const long long mod9 = 1e9 + 9; const long long mod7 = 1e9 + 7; using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); vector<int> a, b; int n, l, r, x; cin >> n >> l >> r; for (int i = 1; i <= n; i++) { cin >> x; if (i >= l && i <= r) { continue; } else { a.push_back(x); } } for (int i = 1; i <= n; i++) { cin >> x; if (i >= l && i <= r) { continue; } else { b.push_back(x); } } if (a == b) { cout << TRUTH ; } else { cout << LIE ; } } |
//#############################################################################
//# Function: 6:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux6 #(parameter DW = 1 ) // width of mux
(
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0] |
{(DW){sel4}} & in4[DW-1:0] |
{(DW){sel5}} & in5[DW-1:0]);
endmodule // oh_mux6
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); long long x, y, m; cin >> x >> y >> m; if (x <= 0 && y <= 0) { if (max(x, y) >= m) cout << 0 ; else cout << -1 ; return 0; } if (x > y) swap(x, y); long long odp = 0; if (x < 0 && y > 0) { if (y < m) { long long ile = abs(x) / y; odp += ile; x += ile * y; } } while (max(x, y) < m) { if (x < y) x += y; else y += x; ++odp; } cout << odp; return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long Getint() { char ch = getchar(); long long x = 0, fh = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) fh = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { (x *= 10) += ch ^ 48; ch = getchar(); } return fh * x; } const int N = 200005; int n, h; long long mod, fc[N], fiv[N], inv[N], sm[N]; int su[N]; struct nod { int a, l; nod(int x = 0, int y = 0) { a = x; l = y; } }; vector<nod> a; inline long long Solve(int l1, int l2) { long long Ans = 1ll * l1 * l2 % mod * inv[2] % mod; for (int i = 1; i <= l1; i++) (Ans += sm[i] - sm[i + l2] + mod) %= mod; return (Ans % mod + mod) % mod; } void Build(int l, int r, int h) { if (h == 1) { su[r - l + 1]++; return; } if (l == r) { su[1]++; return; } int mid = l + r >> 1; Build(l, mid, h - 1); Build(mid + 1, r, h - 1); } int main() { n = Getint(); h = Getint(); mod = Getint(); fc[0] = fc[1] = fiv[0] = fiv[1] = inv[0] = inv[1] = 1; for (int i = 2; i <= N - 1; i++) { fc[i] = fc[i - 1] * i % mod; inv[i] = (mod - mod / i) * inv[mod % i] % mod; fiv[i] = fiv[i - 1] * inv[i] % mod; } for (int i = 1; i <= N - 1; i++) { sm[i] = (sm[i - 1] + inv[i]) % mod; } Build(1, n, h); long long Ans = 0; for (int i = 1; i <= n; i++) { if (!su[i]) continue; a.push_back(nod(su[i], i)); (Ans += 1ll * su[i] * i % mod * (i - 1) % mod * inv[4]) %= mod; } for (int i = 0; i <= int(a.size()) - 1; i++) { (Ans += 1ll * a[i].a * (a[i].a - 1) % mod * inv[2] % mod * Solve(a[i].l, a[i].l)) %= mod; for (int j = i + 1; j <= int(a.size()) - 1; j++) { (Ans += 1ll * a[i].a * a[j].a % mod * Solve(a[i].l, a[j].l)) %= mod; } } cout << Ans % mod << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__OR2B_FUNCTIONAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long n, m, x, y, k, T, p[300], a[300][300]; void dfs(int i) { for (int j = 0; j <= n; j++) if (a[i][j]) { a[i][j] = a[j][i] = 0; p[i]--; p[j]--; if (j && i) cout << j << << i << endl; dfs(j); } } int main() { ios::sync_with_stdio(false); cin >> T; for (int t = 0; t < T; t++) { cin >> n >> m; for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) a[i][j] = 0, p[i] = 0; for (int i = 0; i < m; i++) cin >> x >> y, a[x][y]++, a[y][x]++, p[x]++, p[y]++; k = 0; for (int i = 1; i <= n; i++) if (p[i] & 1) a[0][i] = a[i][0] = 1; else k++; cout << k << endl; for (int i = 1; i <= n; i++) if (p[i]) dfs(i); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct point { long long int x, y; point() {} point(long long int _x, long long int _y) { x = _x; y = _y; } }; bool cmp(const point &a, const point &b) { if (a.x == b.x) return a.y < b.y; return a.x < b.x; } struct freq { long long int x_freq; set<long long int> y_freq; }; freq freq_list[200005]; point S[200010]; long long int mod; long long int fact_mod(long long int k) { long long int ans = 1; while (k > 0) { ans = (ans % mod * k % mod) % mod; --k; } return ans % mod; } int main() { int N; cin >> N; for (int i = 0; i < N; ++i) { int x; cin >> x; S[i] = point(x, i); } for (int i = 0; i < N; ++i) { int x; cin >> x; S[N + i] = point(x, i); } cin >> mod; sort(S, S + 2 * N, cmp); int last = -1, cnt = -1, m; for (int i = 0; i < 2 * N; ++i) { if (S[i].x != last) { ++cnt; last = S[i].x; freq_list[cnt].x_freq = 1; freq_list[cnt].y_freq.insert(S[i].y); } else { ++freq_list[cnt].x_freq; freq_list[cnt].y_freq.insert(S[i].y); } } long long int ans = 1, n; for (int i = 0; i <= cnt; ++i) { m = freq_list[i].x_freq - freq_list[i].y_freq.size(); n = freq_list[i].x_freq; int k = n; for (int j = 0; j < m; ++j) { ans = ((ans % mod) * ((n * (n - 1) / 2LL) % mod)) % mod; n -= 2; } ans = ((ans % mod) * (fact_mod(k - 2 * m) % mod)) % mod; } cout << ans % mod << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 7; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'bx)
if (cnt[30:2]==0) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==1) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==2) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==3) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==4) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==5) struct_bg <= {WS{1'bx}};
else if (cnt[30:2]==6) struct_bg <= {WS{1'bx}};
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0};
else if (cnt[30:2]==4) struct_bg <= '{default:13};
else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_bg !== 15'bx_xx_xxxx_xxxxxxxx) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'bx)
if (cnt[30:2]==0) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==1) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==2) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==3) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==4) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==5) struct_lt <= {WS{1'bx}};
else if (cnt[30:2]==6) struct_lt <= {WS{1'bx}};
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0};
else if (cnt[30:2]==4) struct_lt <= '{default:13};
else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_lt !== 15'bx_xx_xxxx_xxxxxxxx) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000020; const int maxx = 1000000; const int MOd = 1e9 + 7; const int K = 1000; const int P = 143; int loc[maxn]; class Aho_Corasick { public: int last, next[maxn][26]; short used[maxn][26], step; int deg[maxn], dad[maxn]; int dep, fail[maxn]; char name[maxn]; int now[maxn], pre[maxn], E, go[maxn]; int beg[maxn], end[maxn], cnt; int n, segment[1 << 21]; vector<int> w[maxn]; void update(int k, int x) { for (int l = beg[k] + n - 1, r = end[k] + n - 1; l <= r; l = (l + 1) >> 1, r = (r - 1) >> 1) { if (l & 1) segment[l] += x; if (~r & 1) segment[r] += x; } } inline void add(int i, int j) { pre[++E] = now[i]; now[i] = E; go[E] = j; } void calc() { for (int l = 1; l <= dep; l++) { for (int i = now[l]; i; i = pre[i]) { int t = fail[dad[go[i]]]; char c = name[go[i]]; while (t && used[t][c] != step) t = fail[t]; if (used[t][c] == step && next[t][c] != go[i]) t = next[t][c]; fail[go[i]] = t; w[t].push_back(go[i]); } } } void dfs(int n) { beg[n] = ++cnt; for (int i = 0; i < w[n].size(); i++) dfs(w[n][i]); end[n] = cnt; } inline long long find(int k) { long long ret = 0; for (k += n - 1; k; k >>= 1) ret += segment[k]; return ret; } void build(char *ar, int sz, int id) { int p = 0; for (int i = 1; i <= sz; i++) { char h = ar[i] - a ; if (used[p][h] != step) { used[p][h] = step; next[p][h] = ++last; deg[last] = deg[p] + 1; dep = max(dep, (deg[last])); dad[last] = p; name[last] = h; add(deg[last], last); } p = next[p][h]; if (i == sz) loc[id] = p; } } long long get(char *ar, int sz) { long long ret = 0; int p = 0; for (int i = 1; i <= sz; i++) { char c = ar[i] - a ; while (p && used[p][c] != step) p = fail[p]; if (used[p][c] == step) p = next[p][c]; ret += find(beg[p]); } return ret; } } trie; int len[maxn]; bool exist[maxn], used[maxn]; char ch[maxn]; int q, a; char *ar[maxn]; int main() { scanf( %d %d , &q, &a); trie.n = 1 << 20; trie.step = 1; for (int i = 1; i <= a; i++) { scanf( %s , ch); exist[i] = 1; ar[i] = new char[strlen(ch) + 20]; memset(ar[i], 0, sizeof(ar[i])); len[i] = strlen(ch); for (int j = 1; j <= len[i]; j++) { ar[i][j] = ch[j - 1]; ch[j - 1] = 0; } trie.build(ar[i], len[i], i); } trie.calc(); trie.dfs(0); for (int i = 1; i <= a; i++) trie.update(loc[i], 1); vector<int> w; while (q--) { char c; int x; scanf( %c , &c); if (c == ? ) { scanf( %s , ch + 1); int l = strlen(ch + 1); cout << trie.get(ch, l) << endl; } if (c == - || c == + ) { scanf( %d , &x); if (c == - && exist[x]) trie.update(loc[x], -1), exist[x] = 0; if (c == + && !exist[x]) trie.update(loc[x], 1), exist[x] = 1; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[4] = {0, -1, 0, 1}; int dy[4] = {1, 0, -1, 0}; int x[100000], y[100000], DP[100000], CP[100000], R, C, used[50][50][4][4]; char s[64][64]; bool Out(int xx, int yy) { return xx < 0 || yy < 0 || xx >= R || yy >= C; } void next(int x1, int y1, int DP1, int CP1, int &x2, int &y2, int &DP2, int &CP2) { int i; for (i = 1;; i++) { int nx = x1 + dx[DP1] * i; int ny = y1 + dy[DP1] * i; if (Out(nx, ny) || s[nx][ny] != s[x1][y1]) break; } i--; x1 += dx[DP1] * i; y1 += dy[DP1] * i; for (i = 1;; i++) { int nx = x1 + dx[(DP1 + CP1) & 3] * i; int ny = y1 + dy[(DP1 + CP1) & 3] * i; if (Out(nx, ny) || s[nx][ny] != s[x1][y1]) break; } i--; x1 += dx[(DP1 + CP1) & 3] * i; y1 += dy[(DP1 + CP1) & 3] * i; int nx = x1 + dx[DP1]; int ny = y1 + dy[DP1]; if (Out(nx, ny) || !s[nx][ny]) { x2 = x1; y2 = y1; if (CP1 == 1) { CP2 = 3; DP2 = DP1; } else { CP2 = 1; DP2 = (DP1 + 3) & 3; } } else { x2 = nx; y2 = ny; DP2 = DP1; CP2 = CP1; } } int main() { int i, j, k, m; scanf( %d%d , &R, &m); for (i = 0; i < R; i++) scanf( %s , s[i]); C = strlen(s[0]); for (i = 0; i < R; i++) for (j = 0; j < C; j++) s[i][j] -= 0 ; CP[0] = 1; memset(used, -1, sizeof(used)); used[0][0][0][1] = 0; for (i = 1;; i++) { next(x[i - 1], y[i - 1], DP[i - 1], CP[i - 1], x[i], y[i], DP[i], CP[i]); if (used[x[i]][y[i]][DP[i]][CP[i]] >= 0) { break; } used[x[i]][y[i]][DP[i]][CP[i]] = i; } int tmp = used[x[i]][y[i]][DP[i]][CP[i]]; if (m < i) printf( %d n , (int)s[x[m]][y[m]]); else printf( %d n , (int)s[x[tmp + (m - tmp) % (i - tmp)]][y[tmp + (m - tmp) % (i - tmp)]]); return 0; } |
#include <bits/stdc++.h> #include <iomanip> // std::setprecision #define ll long long const long modulo=1000000007; using namespace std; int ctoi(char c) {return c- 0 ;} int compare(pair <int,pair<int,int>> one, pair <int,pair<int,int>> two){ if(one.first<two.first) return 1; return 0; } ll power(ll a, ll b){ ll res=1; while(b!=0){ if(b%2==1){ res*=a; //res%=modulo; } a*=a; //a%=modulo; b/=2; } return res; } int dp[501][501][21]={0}; int n,m,k; int dn[501][501]; int rightt[501][501]; int explore(int q,int i,int j){ if(q==0){ return 0; } if(dp[i][j][q]!=0){ //cout<< 1 ; return dp[i][j][q]; } int ans = dp[i][j][k]; ans=INT_MAX; if(j<m-1) ans=min(ans,explore(q-2,i,j+1) + 2*dn[i][j]); if(j>0)ans=min(ans,explore(q-2,i,j-1) +2*dn[i][j-1]); if(i<n-1)ans=min(ans,explore(q-2,i+1,j) +2*rightt[i][j]); if(i>0)ans=min(ans,explore(q-2,i-1,j) +2*rightt[i-1][j]); //ans=min(min(explore(d,r,n-2,i,j-1,dn,right) +2*dn[i][y0], explore(d,r,n-2,i,j+1,dn,right) +2*dn[i][y]),min(explore(d,r,n-2,i-1,j,dn,right)+2*right[x0][j], explore(d,r,n-2,i+1,j,dn,right)+2*right[x][j])); dp[i][j][q]=ans; return ans; } void solve() { cin>>n>>m>>k; if(k%2!=0){ for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ cout<< -1 << ; } cout<<endl; } return; } for(int i=0;i<n;i++){ for(int j=0;j<m-1;j++){ cin>>dn[i][j]; } } for(int i=0;i<n-1;i++){ for(int j=0;j<m;j++){ cin>>rightt[i][j]; } } int ans[501][501]; for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ ans[i][j]=explore(k,i,j); cout<<ans[i][j]<< ; } cout<<endl; } } int main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif ios_base::sync_with_stdio(false); cin.tie(NULL); ll t=1;//cin>>t; while(t--){ solve(); } return 0; } //rememberhere |
#include <bits/stdc++.h> using namespace std; int read() { int x; scanf( %d , &x); return x; } const int N = 1123456; int a[N]; vector<int> v[N]; int c[N]; priority_queue<int> q[N]; void dfs(int x, int t) { c[x] = t; q[t].push(a[x]); for (int i = 0; i < v[x].size(); i++) { int to = v[x][i]; if (!c[to]) { dfs(to, t); } } } int main() { int n, m, i, j, x, y; n = read(); m = read(); for (i = 1; i <= n; i++) { a[i] = read(); } for (i = 1; i <= m; i++) { x = read(); y = read(); v[x].push_back(y); v[y].push_back(x); } int cnt = 1; for (i = 1; i <= n; i++) { if (!c[i]) { dfs(i, cnt++); } } for (i = 1; i <= n; i++) { printf( %d , q[c[i]].top()); q[c[i]].pop(); } } |
#include <bits/stdc++.h> using namespace std; bool st[1000000]; int main() { int N, K; cin >> N >> K; for (int i = 0; i < 1000000; i++) st[i] = false; int cnt = 0; for (int i = 0; i < N; i++) { int te1, te2; cin >> te1 >> te2; te1 += 100000, te2 += 100000; for (int j = te1; j <= te2; j++) { if (!st[j]) { st[j] = true; cnt++; } } } cout << ((cnt + K - 1) / K) * K - cnt << endl; return 0; } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2s_ctrl
*/
module test_i2s_ctrl;
// Parameters
parameter WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [15:0] prescale = 0;
// Outputs
wire sck;
wire ws;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
prescale);
$to_myhdl(sck,
ws);
// dump file
$dumpfile("test_i2s_ctrl.lxt");
$dumpvars(0, test_i2s_ctrl);
end
i2s_ctrl #(
.WIDTH(WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.sck(sck),
.ws(ws),
.prescale(prescale)
);
endmodule
|
/****************************************************************************
AddSub unit
- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU
is_slt signext addsub
op[2] op[1] op[0] | Operation
0 0 0 0 SUBU
2 0 1 0 SUB
1 0 0 1 ADDU
3 0 1 1 ADD
4 1 0 0 SLTU
6 1 1 0 SLT
****************************************************************************/
module addersub (
opA, opB,
op,
result,
result_slt );
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
//wire [WIDTH:0] sum;
reg [WIDTH:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt=op[2];
assign signext=op[1];
assign addsub=op[0];
assign result=sum[WIDTH-1:0];
//assign result_slt[WIDTH-1:1]={31{1'b0}};
//assign result_slt[0]=sum[WIDTH];
assign result_slt=sum[WIDTH];
wire [WIDTH-1:0] oA;
wire [WIDTH-1:0] oB;
wire [WIDTH-1:0] o_B;
assign oA = {signext&opA[WIDTH-1],opA};
assign oB = {signext&opB[WIDTH-1],opB};
assign o_B = ~{signext&opB[WIDTH-1],opB} + 1'b1;
always @(*) begin
if(addsub == 1'b1) begin
sum = oA + oB;
end else begin
sum = oA + o_B;
end
end
/*
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
defparam
adder_inst.lpm_width=WIDTH+1,
adder_inst.lpm_representation="SIGNED";
*/
assign carry_out=sum[WIDTH];
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T checkmin(T &a, T b) { return (a < b) ? a : a = b; } template <class T> inline T checkmax(T &a, T b) { return (a > b) ? a : a = b; } template <class T> T GCD(T a, T b) { if (a < 0) return GCD(-a, b); if (b < 0) return GCD(a, -b); return (a == 0) ? b : GCD(b % a, a); } template <class T> T LCM(T a, T b) { if (a < 0) return LCM(-a, b); if (b < 0) return LCM(a, -b); return (a == 0 || b == 0) ? 0 : a / GCD(a, b) * b; } template <class T> inline T sqr(T X) { return X * X; } namespace Poor { const int MaxiL = 1000005; const int MaxiN = 205; const int MaxiM = 205; const int MaxiQL = 3005; int N, L; char St[MaxiL]; char Rule[MaxiQL]; int SeqX[MaxiM], SeqY[MaxiM]; int Stack[MaxiL]; inline bool Same(const int a, const int b, const int c, const int d) { if (b - a != d - c) return 0; for (register int i = 0; i < b - a; ++i) if (St[a + i] != Rule[c + i]) return 0; return 1; } void Run() { gets(St); L = strlen(St); scanf( %d n , &N); for (int i = 0; i < N; ++i) { gets(Rule); int M = 0; for (int p = 0; Rule[p] != 0 ; ++p) if (isalpha(Rule[p])) { int q = p; for (; isalpha(Rule[q]); ++q) ; SeqX[M] = p; SeqY[M] = q; ++M; p = q - 1; } register int res = 0; register int *Top = Stack; *Top = 0; ++Top; for (register int p = 0, q = 0; p < L; p = q + 1) { for (q = p; St[q] != > ; ++q) ; if (St[p + 1] == / ) { --Top; continue; } if (St[q - 1] == / ) { if (*(Top - 1) >= M - 1 && Same(p + 1, q - 1, SeqX[M - 1], SeqY[M - 1])) ++res; continue; } *Top = *(Top - 1); if (*Top < M - 1) { if (Same(p + 1, q, SeqX[*Top], SeqY[*Top])) ++*Top; } else { if (Same(p + 1, q, SeqX[M - 1], SeqY[M - 1])) ++res; } ++Top; } printf( %d n , res); } } } // namespace Poor int main() { Poor::Run(); return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, w = 1; register char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch ^ 48), ch = getchar(); return s * w; } void print(long long x) { if (x < 0) x = -x, putchar( - ); if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } long long n, c, x, y, res = 1, now = 1; signed main() { n = read(), x = read(), y = read(), c = read(); if (c == 1) { puts( 0 ); return 0; } for (; c > res; now++) { long long L = min(now, y - 1); if (L == now) res--; res += max(0ll, L - max(now - x + 1, 1ll) + 1) + max(0ll, L - max(x + now - n, 1ll) + 1); long long R = min(now, n - y); if (R == now) res--; res += max(0ll, R - max(now - x + 1, 0ll) + 1) + max(0ll, R - max(x + now - n, 0ll) + 1); } printf( %lld n , --now); return 0; } |
#include <bits/stdc++.h> using namespace std; int binary_search(vector<int> a, int korol) { if (a[a.size() - 1] < korol) return a.size() - 1; if (a[0] > korol) return -1; int max = a.size() - 1, min = 0, mid; if (min + max >= 0) mid = (int)((min + max) / 2); else mid = (int)((min + max - 1) / 2); while (1) { while (a[mid] > korol) { max = mid; if (min + max >= 0) mid = (int)((min + max) / 2); else mid = (int)((min + max - 1) / 2); } while (a[mid] < korol && mid != min) { min = mid; if (min + max >= 0) mid = (int)((min + max) / 2); else mid = (int)((min + max - 1) / 2); } if (min == mid) return min; } } int result(vector<int> a, vector<int> b, int korol) { sort(a.begin(), a.begin() + a.size()); sort(b.begin(), b.begin() + b.size()); int min_a = binary_search(a, korol); int min_b = binary_search(b, korol); if (min_a != -1 && min_b == -1) { cout << YES ; return 1; } if (min_b != -1 && min_a != -1 && a[min_a] > b[min_b]) { cout << YES ; return 1; } if (min_a + 1 != a.size() && min_b + 1 == b.size()) { cout << YES ; return 1; } if (min_a + 1 != a.size() && min_b + 1 != b.size() && a[min_a + 1] < b[min_b + 1]) { cout << YES ; return 1; } return 0; } int main() { int n; cin >> n; int korol_x, korol_y; cin >> korol_x >> korol_y; vector<int> slon_na_glav(0); vector<int> slon_na_dobav(0); vector<int> pomecha_gor(0); vector<int> pomecha_ver(0); vector<int> ladia_na_gor(0); vector<int> ladia_na_ver(0); vector<int> pomecha_glav(0); vector<int> pomecha_dobav(0); for (int i = 0; i < n; i++) { char fig; cin >> fig; int x, y; cin >> x >> y; if (fig == B ) { if (y - x == korol_y - korol_x) slon_na_glav.push_back(x); if (y + x == korol_x + korol_y) slon_na_dobav.push_back(x); if (x == korol_x) pomecha_ver.push_back(y); if (y == korol_y) pomecha_gor.push_back(x); } if (fig == R ) { if (y - x == korol_y - korol_x) pomecha_glav.push_back(x); if (y + x == korol_x + korol_y) pomecha_dobav.push_back(x); if (x == korol_x) ladia_na_ver.push_back(y); if (y == korol_y) ladia_na_gor.push_back(x); } if (fig == Q ) { if (y - x == korol_y - korol_x) slon_na_glav.push_back(x); if (y + x == korol_x + korol_y) slon_na_dobav.push_back(x); if (x == korol_x) ladia_na_ver.push_back(y); if (y == korol_y) ladia_na_gor.push_back(x); } } int progress = 0; if (!slon_na_glav.empty()) { if (pomecha_glav.empty()) { cout << YES ; return 0; } progress = result(slon_na_glav, pomecha_glav, korol_x); if (progress) return 0; } if (!slon_na_dobav.empty()) { if (pomecha_dobav.empty()) { cout << YES ; return 0; } progress = result(slon_na_dobav, pomecha_dobav, korol_x); if (progress) return 0; } if (!ladia_na_gor.empty()) { if (pomecha_gor.empty()) { cout << YES ; return 0; } progress = result(ladia_na_gor, pomecha_gor, korol_x); if (progress) return 0; } if (!ladia_na_ver.empty()) { if (pomecha_ver.empty()) { cout << YES ; return 0; } progress = result(ladia_na_ver, pomecha_ver, korol_y); if (progress) return 0; } cout << NO ; return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg1_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bg1_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bg1-new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg1-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg1-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg1_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_TB_V
`define SKY130_FD_SC_HS__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__sdfrtn dut (.RESET_B(RESET_B), .D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLXBN_PP_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int NMax = 110000; const long long INF = 4294967296LL; int N, sum[NMax]; char A[NMax]; int S[NMax], L; unsigned int dp[3][NMax]; int main() { scanf( %d %s , &N, A); if (N & 1) { puts( 0 ); return 0; } int cur = 1, cnt = 0; dp[1][0] = 1; for (int i = 0; i < N; i++) { cur = 1 - cur; int start = 1 - (i & 1), end = min(N / 2, i + 1); if (A[i] == ? ) for (int j = start; j <= end; j += 2) dp[cur][j] = dp[1 - cur][j + 1] + (j > 0 ? dp[1 - cur][j - 1] : 0); else { cnt++; for (int j = start; j <= end; j += 2) dp[cur][j] = j > 0 ? dp[1 - cur][j - 1] : 0; } } if (cnt > N / 2) { puts( 0 ); return 0; } cnt = N / 2 - cnt; while (cnt--) dp[cur][0] *= 25; printf( %u n , dp[cur][0]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x1, y1, x2, y2; scanf( %d%d%d%d%d%d , &n, &m, &x1, &y1, &x2, &y2); int x, y; x = abs(x1 - x2); y = abs(y1 - y2); if (x > y) swap(x, y); if (y < 4) { cout << First << endl; return 0; } if (x < 3 && y < 5) { cout << First << endl; return 0; } cout << Second << endl; } |
#include <bits/stdc++.h> using namespace std; int str2int(string s) { istringstream ss(s); int t; ss >> t; return t; } int main() { string s; cin >> s; int ans = -1; for (int i = 1; i < s.length(); i++) { string s1 = s.substr(0, i); if (s1.length() > 1 && s1[0] == 0 ) continue; int t1 = str2int(s1); if (t1 > 1000000) continue; for (int j = 1; j < s.length(); j++) { if (i + j >= s.length()) continue; string s2 = s.substr(i, j); string s3 = s.substr(i + j); if (s2.length() > 1 && s2[0] == 0 ) continue; if (s3.length() > 1 && s3[0] == 0 ) continue; int t2 = str2int(s2); int t3 = str2int(s3); if (t2 > 1000000) continue; if (t3 > 1000000) continue; int temp = t1 + t2 + t3; if (temp > ans) ans = temp; } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using vvi = vector<vi>; using ll = long long; using vll = vector<ll>; using vvll = vector<vll>; using pii = pair<int, int>; using pll = pair<ll, ll>; void solve() { int n; cin >> n; vi a(n), b(n); vector<pii> p, q; for (int& x : a) cin >> x; for (int& x : b) cin >> x; if (n % 2 == 1) { if (a[n / 2] != b[n / 2]) { puts( No ); return; } } for (int i = 0; i < n / 2; i++) { p.push_back(make_pair(min(a[i], a[n - 1 - i]), max(a[i], a[n - 1 - i]))); } for (int i = 0; i < n / 2; i++) { q.push_back(make_pair(min(b[i], b[n - 1 - i]), max(b[i], b[n - 1 - i]))); } sort(p.begin(), p.end()); sort(q.begin(), q.end()); if (p == q) { puts( Yes ); } else { puts( No ); } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; while (n--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[10] = {0}; char S[100001]; cin >> S; for (int i = 0; S[i]; i++) { int j = 0; if (S[i] == L ) { while (arr[j] == 1) j++; arr[j] = 1; } j = 10 - 1; if (S[i] == R ) { while (arr[j] == 1) j--; arr[j] = 1; } if (S[i] >= 48 && S[i] <= 57) { arr[S[i] - 48] = 0; } } for (int i = 0; i < 10; i++) cout << arr[i]; cout << endl; } |
#include <bits/stdc++.h> const long long mod = 1000000000; class V { public: long long a[2]; V(long long a0 = 0, long long a1 = 0) { a[0] = a0 % mod; a[1] = a1 % mod; } V operator+(const V &v) { return V(a[0] + v.a[0], a[1] + v.a[1]); } }; class M { public: long long a[2][2]; M(long long a00 = 1, long long a01 = 0, long long a10 = 0, long long a11 = 1) { a[0][0] = a00 % mod; a[0][1] = a01 % mod; a[1][0] = a10 % mod; a[1][1] = a11 % mod; } M operator+(const M &m) { return M(a[0][0] + m.a[0][0], a[0][1] + m.a[0][1], a[1][0] + m.a[1][0], a[1][1] + m.a[1][1]); } M operator*(const M &m) { M r(0, 0, 0, 0); for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { for (int k = 0; k < 2; k++) r.a[i][j] += a[i][k] * m.a[k][j]; r.a[i][j] %= mod; } return r; } V operator*(const V &v) { return V(a[0][0] * v.a[0] + a[0][1] * v.a[1], a[1][0] * v.a[0] + a[1][1] * v.a[1]); } }; const int maxn = 200010; const int maxit = (1 << 19) + 5; M pow_m[maxn], sum_m[maxn], m0; long long it_a[maxit], it_b[maxit]; V it_v[maxit]; V it_vr(int u, int L, int R, long long bonus = 0) { return it_v[u] + sum_m[R - L + 1] * V(it_b[u] + bonus, it_b[u] + bonus); } void it_update(int u, int L, int R, int x, int v) { if (x < L || x > R) return; if (L == R) { it_a[u] = v; it_b[u] = 0; it_v[u] = V(v, v); return; } it_b[2 * u] += it_b[u]; it_b[2 * u + 1] += it_b[u]; it_b[u] = 0; int M = (L + R) / 2; it_update(2 * u, L, M, x, v); it_update(2 * u + 1, M + 1, R, x, v); it_v[u] = it_vr(2 * u, L, M) + pow_m[M - L + 1] * it_vr(2 * u + 1, M + 1, R); } void it_add(int u, int L, int R, int l, int r, int v) { if (r < L || l > R) return; if (l <= L && r >= R) { it_b[u] += v; return; } int M = (L + R) / 2; it_add(2 * u, L, M, l, r, v); it_add(2 * u + 1, M + 1, R, l, r, v); it_v[u] = it_vr(2 * u, L, M) + pow_m[M - L + 1] * it_vr(2 * u + 1, M + 1, R); } V it_get(int u, int L, int R, int l, int r, long long bonus = 0) { if (r < L || l > R) return V(0, 0); if (l <= L && r >= R) { return pow_m[L - l] * it_vr(u, L, R, bonus); } int M = (L + R) / 2; return it_get(2 * u, L, M, l, r, bonus + it_b[u]) + it_get(2 * u + 1, M + 1, R, l, r, bonus + it_b[u]); } int main() { m0 = M(0, 1, 1, 1); pow_m[0] = M(1, 0, 0, 1); sum_m[0] = M(0, 0, 0, 0); for (int i = 0; i + 1 < maxn; i++) { pow_m[i + 1] = pow_m[i] * m0; sum_m[i + 1] = sum_m[i] + pow_m[i]; } memset(it_b, 0, sizeof(it_b)); int n, m, x, l, r, a, t; assert(scanf( %d%d , &n, &m) == 2); for (int i = 0; i < n; i++) { assert(scanf( %d , &a) == 1); it_update(1, 0, n - 1, i, a); } for (int i = 0; i < m; i++) { assert(scanf( %d , &t) == 1); if (t == 1) { assert(scanf( %d%d , &x, &a) == 2); it_update(1, 0, n - 1, x - 1, a); } else if (t == 2) { assert(scanf( %d%d , &l, &r) == 2); V v = it_get(1, 0, n - 1, l - 1, r - 1); printf( %d n , (int)v.a[0]); } else if (t == 3) { assert(scanf( %d%d%d , &l, &r, &a) == 3); it_add(1, 0, n - 1, l - 1, r - 1, a); } else assert(t == 1); } return 0; } |
`timescale 1ns/1ps
//**********************************************************************
// File: check_pin.v
// Module:check_pin
// by Robin zhang
//**********************************************************************
module check_pin(
clk,rst_n,tx_start,capture_ready,tx_data,tx_complete,tx_end,bps_start_t,receive_status,capture_rst
);
input clk;
input rst_n;
input capture_ready;
input tx_complete;
input bps_start_t;
input receive_status;
input capture_rst;
output tx_start;
output tx_end;
output [7:0] tx_data;
reg tx_start;
reg[15:0] tx_counter;
reg[3:0] tx_count;
reg[7:0] tx_data;
reg tx_end;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end
else if(capture_ready && (tx_counter >'d600) && receive_status)begin
case(tx_count)
4'b0000:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd112;
end
4'b0001:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd97;
end
4'b0010:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd115;
end
4'b0011:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd115;
end
// 4'b0100:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'h5;
// end
// 4'b0101:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'h6;
// end
// 4'b0110:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'h7;
// end
// 4'b0111:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'h8;
// end
default:begin
tx_start <= 1'b1;
tx_data <= 8'hzz;
end
endcase
end
else if(capture_ready && (tx_counter >'d600) && (receive_status == 1'b0))begin
case(tx_count)
4'b0000:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd102;
end
4'b0001:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd97;
end
4'b0010:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd105;
end
4'b0011:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= 8'd108;
end
// 4'b0100:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'd7;
// end
// 4'b0101:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'd8;
// end
// 4'b0110:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'd9;
// end
// 4'b0111:begin
// tx_start <= tx_start ? 1'b0:1'b1;
// tx_data <= 8'd0;
// end
default:begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end
endcase
end
end
always @ (posedge tx_complete or negedge capture_rst) begin
if (!capture_rst)begin
tx_count <= 'h0;
tx_end <= 'h0;
end
else if(tx_complete && (tx_count<3)&&capture_ready)begin
tx_count <= tx_count + 1'b1;
end
else begin
tx_end <= 'h1;
end
end
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)begin
tx_counter <= 'h0;
end
else if(!bps_start_t)begin
tx_counter <= tx_counter + 1'b1;
end
else begin
tx_counter <= 'h0;
end
end
endmodule |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_div.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU divider; building block used by several other APU components. Outputs a pulse every n input
* pulses, where n is the divider's period. It contains a counter which is decremented on the
* arrival of each pulse. When the counter reaches 0, it is reloaded with the period and an output
* pulse is generated. A divider can also be forced to reload its counter immediately, but this
* does not output a pulse. When a divider's period is changed, the current count is not affected.
*
* apu_div_const is a variation on apu_div that has an immutable period.
***************************************************************************************************/
module apu_div
#(
parameter PERIOD_BITS = 16
)
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire pulse_in, // input pulse
input wire reload_in, // reset counter to period_in (no pulse_out generated)
input wire [PERIOD_BITS-1:0] period_in, // new period value
output wire pulse_out // divided output pulse
);
reg [PERIOD_BITS-1:0] q_cnt;
wire [PERIOD_BITS-1:0] d_cnt;
always @(posedge clk_in)
begin
if (rst_in)
q_cnt <= 0;
else
q_cnt <= d_cnt;
end
assign d_cnt = (reload_in || (pulse_in && (q_cnt == 0))) ? period_in :
(pulse_in) ? q_cnt - 1'h1 : q_cnt;
assign pulse_out = pulse_in && (q_cnt == 0);
endmodule
|
#include <bits/stdc++.h> typedef struct { double x, y; } point_t; typedef struct { double x, y, r; } circle_t; typedef struct { double A, B, C; } Line; Line zhong_chui_xian(circle_t circle1, circle_t circle2) { Line L1; point_t p; double k; p.x = (circle1.x + circle2.x) / 2; p.y = (circle1.y + circle2.y) / 2; if (fabs(circle1.y - circle2.y) < 1E-8) { L1.A = 1; L1.B = 0; L1.C = -p.x; } else if (fabs(circle1.x - circle2.x) < 1E-8) { L1.A = 0; L1.B = 1; L1.C = -p.y; } else { k = -1 / ((circle1.y - circle2.y) / (circle1.x - circle2.x)); L1.A = k; L1.B = -1; L1.C = p.y - k * p.x; } return L1; } int line_intersect(Line L1, Line L2, point_t& p) { double d, d1, d2, d3; d = L1.A * L2.B - L2.A * L1.B; if (fabs(d) < 1E-8) { d1 = L1.A / L2.A; d2 = L1.B / L2.B; d3 = L1.C / L2.C; if (fabs(d1 - d2) < 1E-8 && fabs(d2 - d3) < 1E-8) return 2; else return 0; } p.x = (L2.C * L1.B - L1.C * L2.B) / d; p.y = (L2.A * L1.C - L1.A * L2.C) / d; return 1; } circle_t yuan_guiji(circle_t circle1, circle_t circle2) { circle_t circle3; double keep1, keep2, keep3; keep1 = (circle2.r * circle2.r * circle1.x - circle1.r * circle1.r * circle2.x) / (circle1.r * circle1.r - circle2.r * circle2.r); keep2 = (circle2.r * circle2.r * circle1.y - circle1.r * circle1.r * circle2.y) / (circle1.r * circle1.r - circle2.r * circle2.r); keep3 = (circle2.r * circle2.r * circle1.x * circle1.x - circle1.r * circle1.r * circle2.x * circle2.x - circle1.r * circle1.r * circle2.y * circle2.y + circle2.r * circle2.r * circle1.y * circle1.y) / (circle1.r * circle1.r - circle2.r * circle2.r); circle3.x = -keep1; circle3.y = -keep2; circle3.r = sqrt(keep3 + keep1 * keep1 + keep2 * keep2); return circle3; } int equa(double A, double B, double C, double& x1, double& x2) { double f = B * B - 4 * A * C; if (f < 0) return -1; x1 = (-B + sqrt(f)) / (2 * A); x2 = (-B - sqrt(f)) / (2 * A); return 1; } double point_line_dis(point_t a, Line ln) { return (fabs(ln.A * a.x + ln.B * a.y + ln.C) / sqrt(ln.A * ln.A + ln.B * ln.B)); } int line_circle_intersect(Line ln, circle_t Y, point_t& p1, point_t& p2) { double t1, t2, len; point_t p3; p3.x = Y.x; p3.y = Y.y; len = point_line_dis(p3, ln); if (len > Y.r) return 0; int zz = -1; if (fabs(ln.B) < 1e-8) { p1.x = p2.x = -1.0 * ln.C / ln.A; zz = equa(1.0, -2.0 * Y.y, Y.y * Y.y + (p1.x - Y.x) * (p1.x - Y.x) - Y.r * Y.r, t1, t2); p1.y = t1; p2.y = t2; } else if (fabs(ln.A) < 1e-8) { p1.y = p2.y = -1.0 * ln.C / ln.B; zz = equa(1.0, -2.0 * Y.x, Y.x * Y.x + (p1.y - Y.y) * (p1.y - Y.y) - Y.r * Y.r, t1, t2); p1.x = t1; p2.x = t2; } else { zz = equa( ln.A * ln.A + ln.B * ln.B, 2.0 * ln.A * ln.C + 2.0 * ln.A * ln.B * Y.y - 2.0 * ln.B * ln.B * Y.x, ln.B * ln.B * Y.x * Y.x + ln.C * ln.C + 2 * ln.B * ln.C * Y.y + ln.B * ln.B * Y.y * Y.y - ln.B * ln.B * Y.r * Y.r, t1, t2); p1.x = t1, p1.y = -1 * (ln.A / ln.B * t1 + ln.C / ln.B); p2.x = t2, p2.y = -1 * (ln.A / ln.B * t2 + ln.C / ln.B); } if (p1.x - p2.x < 1E-8 && p1.y - p2.y < 1E-8) return 1; else return 2; } double dist(double xa, double ya, double xb, double yb) { return sqrt((xa - xb) * (xa - xb) + (ya - yb) * (ya - yb)); } double max(double a, double b) { return a > b ? a : b; } double min(double a, double b) { return a < b ? a : b; } int circle_intersect(circle_t A, circle_t B, point_t& ia, point_t& ib) { if (A.x == B.x && A.y == B.y) return 5; double dd = dist(A.x, A.y, B.x, B.y); if (A.r + B.r + 1E-8 < dd) return 1; double k, a, b, d, aa, bb, cc, c, drt; k = A.r; a = B.x - A.x; b = B.y - A.y; c = B.r; d = (c * c) - (k * k) - (a * a) - (b * b); aa = 4 * (a * a) + 4 * (b * b); bb = 4 * b * d; cc = (d * d) - 4 * (a * a) * (k * k); drt = (bb * bb) - 4 * aa * cc; if (drt < 0) return 5; drt = sqrt(drt); ia.y = (-bb + drt) / 2 / aa; ib.y = (-bb - drt) / 2 / aa; if (fabs(a) < 1E-8) { ia.x = sqrt((k * k) - (ia.y * ia.y)); ib.x = -ia.x; } else { ia.x = (2 * b * ia.y + d) / -2 / a; ib.x = (2 * b * ib.y + d) / -2 / a; } ia.x += A.x; ia.y += A.y; ib.x += A.x; ib.y += A.y; if (fabs(ia.y - ib.y) < 1E-8) { if (fabs(A.r + B.r - dd) < 1E-8) return 2; if (fabs(dd - (max(A.r, B.r) - min(A.r, B.r))) < 1E-8) return 3; } return 4; } int main() { circle_t circle[3]; int i, count; Line L1, L2; point_t p, p1, p2; circle_t circle1, circle2; for (i = 0; i < 3; i++) scanf( %lf%lf%lf , &circle[i].x, &circle[i].y, &circle[i].r); if (fabs(circle[0].r - circle[1].r) < 1E-8) { L1 = zhong_chui_xian(circle[0], circle[1]); if (fabs(circle[1].r - circle[2].r) < 1E-8) { L2 = zhong_chui_xian(circle[1], circle[2]); line_intersect(L1, L2, p); printf( %0.5lf %0.5lf n , p.x, p.y); } else { circle2 = yuan_guiji(circle[1], circle[2]); count = line_circle_intersect(L1, circle2, p1, p2); if (count == 1) { printf( %0.5lf %0.5lf n , p1.x, p1.y); } else if (count == 2) { if ((circle[0].r / dist(circle[0].x, circle[0].y, p1.x, p1.y)) > (circle[0].r / dist(circle[0].x, circle[0].y, p2.x, p2.y))) printf( %0.5lf %0.5lf n , p1.x, p1.y); else printf( %0.5lf %0.5lf n , p2.x, p2.y); } } } else { circle1 = yuan_guiji(circle[0], circle[1]); if (fabs(circle[1].r - circle[2].r) < 1E-8) { L2 = zhong_chui_xian(circle[1], circle[2]); count = line_circle_intersect(L2, circle1, p1, p2); if (count == 1) { printf( %0.5lf %0.5lf n , p1.x, p1.y); } else if (count == 2) { if ((circle[0].r / dist(circle[0].x, circle[0].y, p1.x, p1.y)) > (circle[0].r / dist(circle[0].x, circle[0].y, p2.x, p2.y))) printf( %0.5lf %0.5lf n , p1.x, p1.y); else printf( %0.5lf %0.5lf n , p2.x, p2.y); } } else { circle2 = yuan_guiji(circle[1], circle[2]); count = circle_intersect(circle1, circle2, p1, p2); if (count == 2 || count == 3) { printf( %0.5lf %0.5lf n , p1.x, p1.y); } else if (count == 4) { if ((circle[0].r / dist(circle[0].x, circle[0].y, p1.x, p1.y)) > (circle[0].r / dist(circle[0].x, circle[0].y, p2.x, p2.y))) printf( %0.5lf %0.5lf n , p1.x, p1.y); else printf( %0.5lf %0.5lf n , p2.x, p2.y); } } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off COMBDLY
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off BLKANDNBLK
reg c1_start; initial c1_start = 0;
wire [31:0] c1_count;
comb_loop c1 (.count(c1_count), .start(c1_start));
wire s2_start = c1_start;
wire [31:0] s2_count;
seq_loop s2 (.count(s2_count), .start(s2_start));
wire c3_start = (s2_count[0]);
wire [31:0] c3_count;
comb_loop c3 (.count(c3_count), .start(c3_start));
reg [7:0] cyc; initial cyc = 0;
always @ (posedge clk) begin
//$write("[%0t] %x counts %x %x %x\n", $time,cyc,c1_count,s2_count,c3_count);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
c1_start <= 1'b0;
end
8'd01: begin
c1_start <= 1'b1;
end
default: ;
endcase
case (cyc)
8'd02: begin
// On Verilator, we expect these comparisons to match exactly,
// confirming that our settle loop repeated the exact number of
// iterations we expect. No '$stop' should be called here, and we
// should reach the normal '$finish' below on the next cycle.
if (c1_count!=32'h3) $stop;
if (s2_count!=32'h3) $stop;
if (c3_count!=32'h5) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
module comb_loop (/*AUTOARG*/
// Outputs
count,
// Inputs
start
);
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (posedge start) begin
runner = 3;
end
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner = runnerm1;
$write ("%m count=%d runner =%x\n",count, runnerm1);
end
end
endmodule
module seq_loop (/*AUTOARG*/
// Outputs
count,
// Inputs
start
);
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (posedge start) begin
runner <= 3;
end
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner <= runnerm1;
$write ("%m count=%d runner<=%x\n",count, runnerm1);
end
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module ResetInverter(RESET_IN, RESET_OUT);
input RESET_IN; // input reset
output RESET_OUT; // output reset
wire RESET_OUT;
assign RESET_OUT = ! RESET_IN ;
endmodule // ResetInverter
|
#include <bits/stdc++.h> int Set(int N, int pos) { return N = N | (1 << pos); } int reSet(int N, int pos) { return N = N & ~(1 << pos); } bool check(int N, int pos) { return (bool)(N & (1 << pos)); } using namespace std; string s; int n; bool dp[10010][4], taken[10010][4]; bool isSafe(int pos, int l1) { if (pos - l1 < 0) return true; for (int i = 0; i < l1; i++) { if (s[pos + i] != s[pos - l1 + i]) return true; } return false; } bool go(int pos, int pre) { if (pos > n) return false; if (pos == n) return dp[pos][pre] = true; if (taken[pos][pre]) return dp[pos][pre]; taken[pos][pre] = true; bool ret = false; if (pre == 3) { ret |= go(pos + 2, 2); if (isSafe(pos, 3)) ret |= go(pos + 3, 3); } if (pre == 2) { ret |= go(pos + 3, 3); if (isSafe(pos, 2)) ret |= go(pos + 2, 2); } if (pre == 1) { ret |= go(pos + 1, 1); ret |= go(pos + 2, 2); ret |= go(pos + 3, 3); } return dp[pos][pre] = ret; } set<string> S; void get_solution(int pos, int pre) { if (pos > n || taken[pos][pre]) return; taken[pos][pre] = true; string res; if (pre == 1) { if (dp[pos + 1][1]) get_solution(pos + 1, 1); if (dp[pos + 2][2]) { res = s.substr(pos, 2); S.insert(res); get_solution(pos + 2, 2); } if (dp[pos + 3][3]) { res = s.substr(pos, 3); S.insert(res); get_solution(pos + 3, 3); } } if (pre == 2) { if (dp[pos + 2][2]) { res = s.substr(pos, 2); S.insert(res); get_solution(pos + 2, 2); } if (dp[pos + 3][3]) { res = s.substr(pos, 3); S.insert(res); get_solution(pos + 3, 3); } } if (pre == 3) { if (dp[pos + 2][2]) { res = s.substr(pos, 2); S.insert(res); get_solution(pos + 2, 2); } if (dp[pos + 3][3]) { res = s.substr(pos, 3); S.insert(res); get_solution(pos + 3, 3); } } } int main() { int tc, t = 1; while (cin >> s) { n = s.size(); memset(taken, false, sizeof taken); if (go(5, 1)) { memset(taken, false, sizeof taken); get_solution(5, 1); } for (int i = 0; i < n + 1; i++) { for (int j = 1; j < 4; j++) { } } set<string>::iterator it; cout << S.size() << endl; for (it = S.begin(); it != S.end(); it++) { cout << *it << endl; } S.clear(); } return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Basic ifdef test with else, no define
//
module ifdef1;
reg error ;
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`else
initial
begin
#20;
error = 0;
#20;
end
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND4BB_PP_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_PP_SYMBOL_V
|
// Calculates a CRC32 (Ethernet, polynomial 0x04C11DB7).
//
module CRC32 (
input clk,
input reset,
input rx_we,
input [7:0] rx_byte,
output reg [31:0] tx_crc = 32'd0
);
localparam [31:0] poly = 32'b0000_0100_1100_0001_0001_1101_1011_0111;
wire [31:0] crc = reset ? 32'd0 : tx_crc;
wire [7:0] byte = rx_we ? rx_byte : 8'd0;
wire [31:0] shifted0 = {crc[30:0], byte[7]} ^ ({32{crc[31]}} & poly);
wire [31:0] shifted1 = {shifted0[30:0], byte[6]} ^ ({32{shifted0[31]}} & poly);
wire [31:0] shifted2 = {shifted1[30:0], byte[5]} ^ ({32{shifted1[31]}} & poly);
wire [31:0] shifted3 = {shifted2[30:0], byte[4]} ^ ({32{shifted2[31]}} & poly);
wire [31:0] shifted4 = {shifted3[30:0], byte[3]} ^ ({32{shifted3[31]}} & poly);
wire [31:0] shifted5 = {shifted4[30:0], byte[2]} ^ ({32{shifted4[31]}} & poly);
wire [31:0] shifted6 = {shifted5[30:0], byte[1]} ^ ({32{shifted5[31]}} & poly);
wire [31:0] shifted7 = {shifted6[30:0], byte[0]} ^ ({32{shifted6[31]}} & poly);
always @ (posedge clk)
begin
if (rx_we | reset)
tx_crc <= shifted7;
end
endmodule
|
/*
* This program is explicitly placed in the public domain for any uses
* whatsoever.
*/
module TestMultiplier();
reg clk;
initial begin
clk = 0;
forever #0.5 clk = ~clk;
end
reg[5:0] left, right;
wire[2:0] exp;
Multiplier mul(clk, left, right, exp);
parameter ONE = {3'b011, 3'b0}; // 1.000 * 2**(3 - bias of 3) == 1.000
always @ (posedge clk) begin
left = ONE;
right = ONE;
#10
if (exp !== 3'b011)
$display("FAIL: expected %b, got %b",
3'b011, exp);
else
$display("PASSED");
$finish();
end
endmodule
/**
* A little bit of an incomplete floating-point multiplier. In/out format is
* [5:3] specify biased exponent (and hidden bit), [2:0] specify fraction.
*
* @param left[5:0], right[5:0]
* values being multiplied
* @param exp[2:0]
* exponent from product of left and right when put in the floating-point
* format of left/right
*/
module Multiplier(clk,
left, right,
exp);
input clk;
input[5:0] left, right;
output[2:0] exp;
reg[2:0] exp;
// IMPLEMENTATION
wire signed[2:0] expl = left[5:3] - 3;
wire signed[2:0] expr = right[5:3] - 3;
/** Sum of unbiased exponents in operands. */
reg signed[3:0] sumExp;
always @ (posedge clk) begin
sumExp <= (expl + expr) < -2 // why can't I move -2 to the right-hand side?
? -3
: expl + expr;
exp[2:0] <= sumExp + 3;
end
endmodule
|
#include<bits/stdc++.h> using namespace std; long long ans; int d[100005]; int main(){ int t; cin>>t; while(t--){ int n; scanf( %d ,&n); for(int i=1;i<=n;++i)scanf( %d ,&d[i]); sort(d+1,d+1+n); ans=d[n]; for(int i=1;i<=n;++i)ans+=d[i]*(n+1ll-i-i); printf( %lld n ,ans); } } |
`timescale 1 ns / 1 ps
`include "AXIOutputRegisters_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module AXIOutputRegisters_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_TB_V
`define SKY130_FD_SC_LP__ISOBUFSRC_TB_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__isobufsrc.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__isobufsrc dut (.SLEEP(SLEEP), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_TB_V
|
#include <bits/stdc++.h> using namespace std; map<char, long long> mp; map<pair<char, long long>, long long> cnt; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); for (char c = a ; c <= z ; c++) cin >> mp[c]; string s; cin >> s; long long n = s.length(); long long sum = mp[s[0]]; cnt[{s[0], mp[s[0]]}]++; long long ans = 0; for (long long i = 1; i < n; i++) { ans += cnt[{s[i], sum}]; sum += mp[s[i]]; cnt[{s[i], sum}]++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000005; long long fac[N], dp[N]; int mod = 1000000007; long long pow(int a, int b, int MOD) { long long x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y); if (x > MOD) x %= MOD; } y = (y * y); if (y > MOD) y %= MOD; b /= 2; } return x % MOD; } long long ncr(int n, int r) { long long temp = (fac[r] * fac[n - r]) % mod; return (fac[n] * pow(temp, mod - 2, mod)) % mod; } int main() { int n, i, k; long long temp; fac[0] = 1; for (i = 1; i < N; i++) { fac[i] = (fac[i - 1] * i) % mod; } scanf( %d%d , &n, &k); for (i = k + 1; i <= n; i++) { dp[i] = (i * dp[i - 1]) % mod; temp = (fac[k] * ncr(i - 1, k)) % mod; dp[i] += (((fac[i - k - 1] - dp[i - k - 1]) % mod + mod) * temp) % mod; dp[i] %= mod; } long long ans = 0; for (i = 1; i <= n; i++) { temp = (ncr(n - 1, i - 1) * dp[i - 1]) % mod; temp = (temp * fac[n - i]) % mod; ans += temp; ans %= mod; } printf( %lld , ans); } |
#include <bits/stdc++.h> using namespace std; char buf[1 << 21], *p1 = buf, *p2 = buf; template <class T> void read(T &x) { x = 0; int c = getchar(); int flag = 0; while (c < 0 || c > 9 ) flag |= (c == - ), c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); if (flag) x = -x; } template <class T> T _max(T a, T b) { return b < a ? a : b; } template <class T> T _min(T a, T b) { return a < b ? a : b; } template <class T> bool checkmax(T &a, T b) { return a < b ? a = b, 1 : 0; } template <class T> bool checkmin(T &a, T b) { return b < a ? a = b, 1 : 0; } const int N = 1000005; int n; int a[N], b[N], sa[N], sb[N]; void init() { read(n); for (int i = 1; i <= n; ++i) read(a[i]); for (int i = 1; i <= n; ++i) read(b[i]); sa[n + 1] = 0; for (int i = n; i >= 1; --i) sa[i] = sa[i + 1] + a[i]; sb[0] = 0; for (int i = 1; i <= n; ++i) sb[i] = sb[i - 1] + b[i]; } void solve() { int ans = -1; for (int i = 1; i <= n; ++i) { int w = max(sb[i - 1], sa[i + 1]); if (i == 1) ans = w; else checkmin(ans, w); } printf( %d n , ans); } int main() { int t; read(t); while (t--) { init(); solve(); } return 0; } |
// frame_decoder.v
`timescale 1 ns / 1 ps
module frame_detector
(
input clk400,
input clk80,
input reset,
input enable,
input sdata,
output reg [4:0]pdata,
output reg error
);
reg [5:0]s; // shift register
reg detect; // 000001 pattern detected
reg [2:0]c; // frame pos counter
wire sync = c[2]; // periodic frame sync signal
reg [4:0]p; // parallel data register
reg e; // error flag
always @(posedge clk400 or posedge reset)
begin
if (reset)
begin
s <= 0;
detect <= 0;
c <= 0;
p <= 0;
e <= 0;
end
else if (enable)
begin
s <= {s[4:0],sdata};
detect <= (s[5:0] == 6'b100000) || (s[5:0] == 6'b011111);
if (sync || detect) c <= 3'd0; else c <= c + 3'd1;
if (sync) p <= s[5:1];
if (sync) e <= 0; else if (detect) e <= 1;
end
end
always @(posedge clk80 or posedge reset)
begin
if (reset)
begin
pdata <= 5'd0;
error <= 0;
end
else if (enable)
begin
pdata <= p;
error <= e;
end
else
begin
pdata <= 5'd0;
error <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class TH> void _dbg(const char *sdbg, TH h) { cerr << sdbg << = << h << endl; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cerr << *sdbg++; cerr << = << h << , ; _dbg(sdbg + 1, a...); } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> p) { return os << ( << p.first << , << p.second << ) ; } template <class Iterable, class = typename enable_if<!is_same<string, Iterable>::value>::type> auto operator<<(ostream &os, Iterable v) -> decltype(os << *begin(v)) { os << [ ; for (auto vv : v) os << vv << , ; return os << ] ; } const int inf = 0x3f3f3f3f; const long long infll = 0x3f3f3f3f3f3f3f3fll; template <class T> int sign(T x) { return (x > 0) - (x < 0); } template <class T> T abs(const T &x) { return (x < T(0)) ? -x : x; } vector<int> graph[112345]; int c[112345][4]; int main() { cin.sync_with_stdio(0); cin.tie(0); int n, a, b; cin >> n; for (int k = 1; k <= 3; k++) for (int i = 1; i <= n; i++) cin >> c[i][k]; for (int i = 0; i + 1 < n; i++) { cin >> a >> b; graph[a].push_back(b); graph[b].push_back(a); } int start; for (int i = 1; i <= n; i++) { if (graph[i].size() > 2) { cout << -1 << endl; return 0; } if (graph[i].size() == 1) start = i; } vector<int> pi = {1, 2, 3}; long long ans = infll; vector<int> best_color; vector<int> color(n + 1); do { long long tmp = 0; int cur = start; int prev = start; for (int i = 0; i < n; i++) { color[cur] = pi[i % 3]; tmp += c[cur][pi[i % 3]]; for (int j = 0; j < graph[cur].size(); j++) if (graph[cur][j] != prev) { prev = cur; cur = graph[cur][j]; break; } } if (tmp < ans) { ans = min(ans, tmp); best_color = color; } } while (next_permutation(pi.begin(), pi.end())); cout << ans << endl; for (int i = 1; i <= n; i++) cout << best_color[i] << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005, mod = 1e9 + 7; inline int Add(int x, int y) { return (x += y) >= mod ? x - mod : x; } int n, cnt[maxn], vec[maxn], tot; int main() { scanf( %d , &n); cnt[0] = 1; for (int i = 1, x; i <= n; ++i) { scanf( %d , &x), tot = 0; for (int j = 1; j * j <= x; ++j) { if (x % j == 0) { vec[++tot] = j; if (j * j != x && x / j <= n) cnt[x / j] = Add(cnt[x / j], cnt[x / j - 1]); } } for (int j = tot; j; --j) if (vec[j] <= n) cnt[vec[j]] = Add(cnt[vec[j]], cnt[vec[j] - 1]); } int ans = 0; for (int i = 1; i <= n; ++i) ans = Add(ans, cnt[i]); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; set<string> st; const int N = 1e6 + 5; int a[3000]; int c1 = 0, c2; string s, c; int na, nb, m, ans = 0, mx = 0; int main() { int n, a, b; cin >> n; while (n--) { cin >> a >> b; if (a == 2) { cout << b / a << endl; continue; } if (a == 1) { cout << b << endl; continue; } if (a % 2 == 1) { cout << b / (a - a / 2) << endl; } else cout << b / (a - (a / 2 - 1)) << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:43:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.v
// Design : system_clock_splitter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_clock_splitter_0_0,clock_splitter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "clock_splitter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_clock_splitter_0_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_0_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodule
(* ORIG_REF_NAME = "clock_splitter" *)
module system_clock_splitter_0_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edge),
.I2(clk_out),
.O(clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_reg
(.C(clk_in),
.CE(1'b1),
.D(clk_i_1_n_0),
.Q(clk_out),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_edge_reg
(.C(clk_in),
.CE(1'b1),
.D(latch_edge),
.Q(last_edge),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-------------------------------------------------------------------
//-- Test para arranque del tipo "warm boot" en la iCE40HX.
//-- Pulsando el botón 1 cambiamos el valor de la imagen a cargar.
//-- Pulsando el botón 2 generamos la señal "boot" para cargar dicha
//-- imagen.
//-------------------------------------------------------------------
//-- Juan Manuel Rico - Ridotech - Marzo 2017.
//-------------------------------------------------------------------
module test_warmboot (input wire btn1, btn2, output reg [7:0] data);
//-- Instanciar el bloque warm boot.
top wb (
.boot(btn2),
.s1(image[1]),
.s0(image[0])
);
// Registro del valor de la imagen a cargar.
reg [1:0] image = 2'b00;
//-- Al pulsar el botón 1 hacemos cambiar el bit 7
// para mostrar la pulsación y elegimos la siguiente imagen.
always @(posedge(btn1)) begin
data[7] = ~data[7];
image = image + 1;
end
// Se muestra la imagen a cargar tras el warn boot (al pulsar el botón 2).
assign data[6:0] = {5'b00000, image[1], image[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[20], b[20]; char s[110000]; int main() { int n, i, j; scanf( %s , s); for (i = 0; s[i]; i++) { if (s[i] == 5 ) a[2]++; else if (s[i] == 9 ) a[6]++; else a[s[i] - 0 ]++; } scanf( %s , s); for (i = 0; s[i]; i++) { if (s[i] == 5 ) b[2]++; else if (s[i] == 9 ) b[6]++; else b[s[i] - 0 ]++; } int ans = 210000; for (i = 0; i <= 9; i++) if (i - 9 && i - 5) { if (a[i]) ans = min(ans, b[i] / a[i]); } printf( %d n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_lp__udp_mux_4to2.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct Vec { double x, y; Vec(double newX = 0, double newY = 0) { x = newX; y = newY; } Vec operator+(Vec r) { return Vec(x + r.x, y + r.y); } Vec operator-(Vec r) { return Vec(x - r.x, y - r.y); } Vec operator*(double r) { return Vec(x * r, y * r); } Vec operator/(double r) { return Vec(x / r, y / r); } double operator*(Vec r) { return x * r.x + y * r.y; } Vec normal() { return Vec(y, -x); } double len() { return sqrt(x * x + y * y); } }; double cprod(Vec l, Vec r) { return l.x * r.y - l.y * r.x; } Vec intersection(Vec first1, Vec first2, Vec second1, Vec second2) { Vec n1 = (first2 - first1).normal(); Vec n2 = (second2 - second1).normal(); double c1 = first1 * n1; double c2 = second1 * n2; double x = c1 * n2.y - c2 * n1.y; double y = c2 * n1.x - c1 * n2.x; double div = n1.x * n2.y - n1.y * n2.x; return Vec(x, y) / div; } double getArea(vector<Vec> pts) { double result = 0; for (size_t i = 0; i < pts.size(); i++) result += cprod(pts[i], pts[(i + 1) % pts.size()] - pts[i]) / 2; return abs(result); } int n, r; double pi = acos(-1); Vec getPt(int ind) { ind = (ind % n + n) % n; return Vec(r * sin(2 * pi * ind / n), r * cos(2 * pi * ind / n)); } int main() { double area = 0; cin >> n >> r; { vector<Vec> pts = { getPt(0), getPt(n / 2), intersection(getPt(n / 2), getPt(-1), getPt(n / 2 + 1), getPt(1)), getPt(n / 2 + 1)}; area += getArea(pts); } int segments = 2, cursize = (n - 3) / 2; while (cursize > 0) { Vec mid; if (cursize + 1 != n / 2) mid = intersection(getPt(0), getPt(n / 2), getPt(cursize + 1), getPt(cursize + 1 - n / 2)); else mid = getPt(0) + (getPt(n / 2) - getPt(0)) / 2; if (cursize % 2) { Vec top = getPt((cursize + 1) / 2); Vec lopp = getPt((cursize + 1) / 2 - n / 2); Vec ropp = getPt((cursize + 1) / 2 + n / 2); vector<Vec> pts = {top, intersection(top, lopp, getPt(0), getPt(n / 2)), mid, intersection(top, ropp, getPt(cursize + 1), getPt(cursize + 1 - n / 2))}; area += segments * getArea(pts); cursize = (cursize - 1) / 2; } else { Vec top1 = getPt((cursize + 1) / 2); Vec top2 = getPt((cursize + 1) / 2 + 1); Vec bot1 = getPt((cursize + 1) / 2 + n / 2); Vec bot2 = getPt((cursize + 1) / 2 - n / 2); Vec bot3 = getPt((cursize + 1) / 2 + 1 - n / 2); vector<Vec> pts = { top1, intersection(top1, bot2, getPt(0), getPt(n / 2)), mid, intersection(top2, bot2, getPt(cursize + 1), getPt(cursize + 1 - n / 2)), top2, intersection(top1, bot1, top2, bot3)}; area += segments * getArea(pts); cursize = (cursize - 2) / 2; } segments *= 2; } cout << fixed << setprecision(8) << area << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A22OI_PP_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_PP_BLACKBOX_V
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module I2C_AV_Config ( //Host Side
iCLK,
iRST_N,
// I2C Side
oI2C_SCLK,
oI2C_SDAT
);
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output oI2C_SCLK;
inout oI2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [3:0] LUT_INDEX;
reg [1:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 24000000; // 24 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 11;
// Audio Data Index
parameter Dummy_DATA = 0;
parameter SET_LIN_L = 1;
parameter SET_LIN_R = 2;
parameter SET_HEAD_L = 3;
parameter SET_HEAD_R = 4;
parameter A_PATH_CTRL = 5;
parameter D_PATH_CTRL = 6;
parameter POWER_ON = 7;
parameter SET_FORMAT = 8;
parameter SAMPLE_CTRL = 9;
parameter SET_ACTIVE = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N) begin
if(!iRST_N) begin
mI2C_CTRL_CLK <= 1'd0;
mI2C_CLK_DIV <= 16'd0;
end else begin
if (mI2C_CLK_DIV < (CLK_Freq/I2C_Freq))
mI2C_CLK_DIV <= mI2C_CLK_DIV + 16'd1;
else begin
mI2C_CLK_DIV <= 16'd0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 (
.CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(oI2C_SCLK), // I2C CLOCK
.I2C_SDAT(oI2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N)
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N) begin
if(!iRST_N) begin
LUT_INDEX <= 4'd0;
mSetup_ST <= 2'd0;
mI2C_GO <= 1'd0;
end else begin
if(LUT_INDEX < LUT_SIZE) begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'h34,LUT_DATA};
mI2C_GO <= 1'd1;
mSetup_ST <= 2'd1;
end
1: begin
if(mI2C_END) begin
if(!mI2C_ACK)
mSetup_ST <= 2'd2;
else
mSetup_ST <= 2'd0;
mI2C_GO <= 1'd0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX + 4'd1;
mSetup_ST <= 2'd0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always @ (*)
begin
case(LUT_INDEX)
// Audio Config Data
Dummy_DATA : LUT_DATA <= 16'h0000;
SET_LIN_L : LUT_DATA <= 16'h009A;//16'h001A; //R0 LINVOL = 1Ah (+4.5bB)
SET_LIN_R : LUT_DATA <= 16'h029A;//16'h021A; //R1 RINVOL = 1Ah (+4.5bB)
SET_HEAD_L : LUT_DATA <= 16'h0479; //R2 LHPVOL = 7Bh (+2dB)
SET_HEAD_R : LUT_DATA <= 16'h0679; //R3 RHPVOL = 7Bh (+2dB)
A_PATH_CTRL : LUT_DATA <= 16'h08D2;//16'h08F8; //R4 DACSEL = 1
D_PATH_CTRL : LUT_DATA <= 16'h0A06; //R5 DEEMP = 11 (48 KHz)
POWER_ON : LUT_DATA <= 16'h0C00; //R6
SET_FORMAT : LUT_DATA <= 16'h0E01; //R7 FORMAT=01,16 bit
SAMPLE_CTRL : LUT_DATA <= 16'h1009; //R8 48KHz,USB-mode
SET_ACTIVE : LUT_DATA <= 16'h1201; //R9 ACTIVE
default : LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Oct 30 13:48:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0],probe26[3:0],probe27[7:0],probe28[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
input [3:0]probe26;
input [7:0]probe27;
input [0:0]probe28;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/28/2016 01:49:26 AM
// Design Name:
// Module Name: KOA_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KOA_2 //#(parameter SW = 24)
//#(parameter SW = 54)
#(parameter SW = 12)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder; /*P=SW/2+1*/
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder; /*P=SW/2+1*/
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [SW-1:0] Q_left;
wire [SW+1:0] Q_right;
wire [SW+3:0] Q_middle; ///Modificación J: Le he agregado dos bits al largo del puerto, para acomodar los 2 cero el resultado de una multiplicacion
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2-3:0] leftside1;
wire [SW/2:0] rightside2;
wire fill;
wire [4*(SW/2)-1:0] sgf_r;
assign fil = 1'b0;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0;
localparam half = SW/2;
localparam full_port = SW - 1;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_1 #(.SW(SW/2)/*,.level(level1)*/) left(
.Data_A_i(Data_A_i[full_port:half]/*P=SW/2*/),
.Data_B_i(Data_B_i[full_port:half]/*P=SW/2*/),
.sgf_result_o(Q_left) /*P=SW*//*result_left_mult*/
);
KOA_1 #(.SW(SW/2)) right( /*,.level(level1)*/
.Data_A_i(Data_A_i[half-1:0]/*P=SW/2*/),
.Data_B_i(Data_B_i[half-1:0]/*P=SW/2*/),
.sgf_result_o(Q_right[full_port:0]/*P=SW*/) /*result_right_mult[2*(SW/2)-1:0]*/
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW/2]/*P=SW/2*/),
.Data_B_i(Data_A_i[SW/2-1:0]/*P=SW/2*/),
.Data_S_o(result_A_adder[SW/2:0]/*P=SW/2+1*/)
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW/2]/*P=SW/2*/),
.Data_B_i(Data_B_i[SW/2-1:0]/*P=SW/2*/),
.Data_S_o(result_B_adder[SW/2:0]/*P=SW/2+1*/)
);
//multiplication for middle
//Introducimos un par de ceros, ya que esta multiplicacion es siempre impar, gracias al sumador que viene detras.
//Modificación: Le agregué otro bit al puerto de este multiplicador, para que fuera par.
KOA_1 #(.SW(SW/2+2)/* Port length = SW/2 + 2*/) middle (
.Data_A_i({fill /*P=1*/,result_A_adder[SW/2:0]/*P=SW/2+1*/}), /*Q_result_A_adder[SW/2+1:0]*/
.Data_B_i({fill /*P=1*/,result_B_adder[SW/2:0]/*P=SW/2+1*/}), /*Q_result_B_adder[SW/2+1:0]*/
.sgf_result_o(Q_middle[SW+3:0]) /*result_middle_mult[2*(SW/2)+2:0]*/
//Vamos a truncar este resultado en la siguiente etapa del puerto
);
// wire [SW-1:0] Q_left;
// wire [SW+1:0] Q_right;
// wire [SW+3:0] Q_middle;
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(Q_middle[SW+1:0] /*P=SW+2*/), /*result_middle_mult//*/
.Data_B_i({zero1/*P=2*/, Q_left /*P=SW*/}), /*result_left_mult//*/
.Data_S_o(S_A[SW+1:0]/*P=SW+2*/)
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0] /*P=SW+2*/),
.Data_B_i({zero1 /*P=2*/, Q_right[SW-1:0] /*P=SW*/}), /*result_right_mult//*/
.Data_S_o(S_B[2*(SW/2)+1:0]) //Port width is SW+1
);
//wire [SW-1:0] Q_left; /*P=SW*/
//wire [SW+1:0] Q_right; /*P=SW+2*/
//Final adder
adder #(.W(2*SW)) Final(
.Data_A_i({Q_left /*P=SW*/ ,Q_right[SW-1:0]/*P=SW*/}), //Port width is 2*SW /*result_left_mult,result_right_mult*/
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0]/*P=2*SW+1*/)
);
//Final Register
RegisterAdd #(.W(2*SW)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_1 #(.SW(SW/2)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2]),
.Data_B_i(Data_B_i[SW-1:SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
KOA_1 #(.SW((SW/2)+1)/*,.level(level2)*/) right_lower(
.Data_A_i(Data_A_i[SW/2-1:0]), //Numeros pares debe de hacer un redondeo hacia abajo
.Data_B_i(Data_B_i[SW/2-1:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_1 #(.SW(SW/2+2)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
// $Id: whr_op_ctrl_mac.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// output port controller
//==============================================================================
module whr_op_ctrl_mac
(clk, reset, flow_ctrl_in, flit_valid_in, flit_head_in, flit_tail_in,
flit_data_in, channel_out, elig, full, error);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "whr_constants.v"
// total buffer size per port in flits
parameter buffer_size = 8;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// number of input and output ports on router
parameter num_ports = 5;
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
// select type of flow control
parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
// make incoming flow control signals bypass the output VC state tracking
// logic
parameter flow_ctrl_bypass = 1;
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? 1 :
-1;
// select whether to exclude full or non-empty VCs from VC allocation
parameter elig_mask = `ELIG_MASK_NONE;
// generate almost_empty signal early on in clock cycle
localparam fast_almost_empty
= flow_ctrl_bypass && (elig_mask == `ELIG_MASK_USED);
// maximum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter max_payload_length = 4;
// minimum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter min_payload_length = 1;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// enable link power management
parameter enable_link_pm = 1;
// width of link management signals
localparam link_ctrl_width = enable_link_pm ? 1 : 0;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + 1) :
-1;
// width of flit payload data
parameter flit_data_width = 64;
// channel width
localparam channel_width
= link_ctrl_width + flit_ctrl_width + flit_data_width;
// configure error checking logic
parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
// ID of current input port
parameter port_id = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// incoming flow control signals
input [0:flow_ctrl_width-1] flow_ctrl_in;
// grant from allocator module
input flit_valid_in;
// grant is for head flit
input flit_head_in;
// grant is for tail flit
input flit_tail_in;
// incoming flit data
input [0:flit_data_width-1] flit_data_in;
// outgoing channel
output [0:channel_width-1] channel_out;
wire [0:channel_width-1] channel_out;
// output is available for allocation
output elig;
wire elig;
// output is full
output full;
wire full;
// internal error condition detected
output error;
wire error;
//---------------------------------------------------------------------------
// input staging
//---------------------------------------------------------------------------
wire fcs_fc_active;
wire flow_ctrl_active;
assign flow_ctrl_active = fcs_fc_active;
wire fc_event_valid;
wire fc_event_sel_ovc;
rtr_flow_ctrl_input
#(.num_vcs(1),
.flow_ctrl_type(flow_ctrl_type),
.reset_type(reset_type))
fci
(.clk(clk),
.reset(reset),
.active(flow_ctrl_active),
.flow_ctrl_in(flow_ctrl_in),
.fc_event_valid_out(fc_event_valid),
.fc_event_sel_out_ovc(fc_event_sel_ovc));
//---------------------------------------------------------------------------
// track buffer occupancy
//---------------------------------------------------------------------------
wire fcs_active;
assign fcs_active = flit_valid_in | fc_event_valid;
wire fcs_empty;
wire fcs_almost_full;
wire fcs_full;
wire fcs_full_prev;
wire [0:1] fcs_errors;
rtr_fc_state
#(.num_vcs(1),
.buffer_size(buffer_size),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.mgmt_type(`FB_MGMT_TYPE_STATIC),
.fast_almost_empty(fast_almost_empty),
.disable_static_reservations(0),
.reset_type(reset_type))
fcs
(.clk(clk),
.reset(reset),
.active(fcs_active),
.flit_valid(flit_valid_in),
.flit_head(flit_head_in),
.flit_tail(flit_tail_in),
.flit_sel_ovc(1'b1),
.fc_event_valid(fc_event_valid),
.fc_event_sel_ovc(1'b1),
.fc_active(fcs_fc_active),
.empty_ovc(fcs_empty),
.almost_full_ovc(fcs_almost_full),
.full_ovc(fcs_full),
.full_prev_ovc(fcs_full_prev),
.errors_ovc(fcs_errors));
assign full = fcs_full;
//---------------------------------------------------------------------------
// track whether this output VC is currently in use
//---------------------------------------------------------------------------
// NOTE: For the reset condition, we don't have to worry about whether or
// not sufficient buffer space is available: If the VC is currently
// allocated, these checks would already have been performed at the
// beginning of switch allocation; on the other hand, if it is not currently
// allocated, 'allocated_q' is zero, and thus the reset condition does not
// have any effect.
wire allocated;
wire allocated_s, allocated_q;
assign allocated_s = allocated;
c_dff
#(.width(1),
.reset_type(reset_type))
allocatedq
(.clk(clk),
.reset(reset),
.active(fcs_active),
.d(allocated_s),
.q(allocated_q));
assign allocated = flit_valid_in ? ~flit_tail_in : allocated_q;
generate
case(elig_mask)
`ELIG_MASK_NONE:
assign elig = ~allocated;
`ELIG_MASK_FULL:
assign elig = ~allocated & ~fcs_full;
`ELIG_MASK_USED:
assign elig = ~allocated & fcs_empty;
endcase
endgenerate
//---------------------------------------------------------------------------
// output staging
//---------------------------------------------------------------------------
wire flit_out_active;
assign flit_out_active = flit_valid_in;
rtr_channel_output
#(.num_vcs(1),
.packet_format(packet_format),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.reset_type(reset_type))
cho
(.clk(clk),
.reset(reset),
.active(flit_out_active),
.flit_valid_in(flit_valid_in),
.flit_head_in(flit_head_in),
.flit_tail_in(flit_tail_in),
.flit_data_in(flit_data_in),
.flit_sel_in_ovc(1'b1),
.channel_out(channel_out));
//---------------------------------------------------------------------------
// error checker logic
//---------------------------------------------------------------------------
generate
if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:1] errors_s, errors_q;
assign errors_s = fcs_errors;
c_err_rpt
#(.num_errors(2),
.capture_mode(error_capture_mode),
.reset_type(reset_type))
chk
(.clk(clk),
.reset(reset),
.active(1'b1),
.errors_in(errors_s),
.errors_out(errors_q));
assign error = |errors_q;
end
else
assign error = 1'bx;
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; map<string, int> f, reff; int n, m, q, w[13], ans[4097][101]; string s; string tob(int x) { string t = ; while (x > 0) { x % 2 == 0 ? t = 0 + t : t = 1 + t; x /= 2; } while (t.length() < n) { t = 0 + t; } return t; } int tod(string x) { int r = 0, v = 1; for (int i = n - 1; i >= 0; i--) { if (x[i] == 1 ) r += v; v *= 2; } return r; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> q; for (int i = 0; i < n; i++) cin >> w[i]; while (m--) { getline(cin >> ws, s); f[s]++; } int maxnum = (1 << n) - 1; for (int i = 0; i <= maxnum; i++) { string tmp = tob(i); map<string, int>::iterator j; for (j = f.begin(); j != f.end(); j++) { int v = 0; for (int k = 0; k < n; k++) if (tmp[k] == j->first[k]) v += w[k]; if (v <= 100) ans[i][v] += j->second; } } for (int i = 0; i <= maxnum; i++) for (int j = 1; j <= 100; j++) ans[i][j] += ans[i][j - 1]; while (q--) { int kk; cin >> ws >> s >> kk; cout << ans[tod(s)][kk] << n ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Methods defined by IEEE:
// function int unsigned $urandom [ (int seed ) ] ;
// function int unsigned $urandom_range( int unsigned maxval,
// int unsigned minval = 0 );
module t(/*AUTOARG*/);
`ifndef VERILATOR
`define PROC
`endif
`ifdef PROC
process p;
`endif
int unsigned v1;
int unsigned v2;
int unsigned v3;
string s;
initial begin
`ifdef PROC
if (p != null) $stop;
p = process::self();
`endif
v1 = $urandom;
v2 = $urandom;
v3 = $urandom();
if (v1 == v2 && v1 == v3) $stop; // Possible, but 2^-64
// Range
v2 = $urandom_range(v1, v1);
if (v1 != v2) $stop;
v2 = $urandom_range(0, 32'hffffffff);
if (v2 == v1) $stop;
for (int test = 0; test < 20; ++test) begin
v1 = 2;
v1 = $urandom_range(0, v1);
if (v1 != 0 && v1 != 1 && v1 != 2) $stop;
v1 = $urandom_range(2, 0);
if (v1 != 0 && v1 != 1 && v1 !=2) $stop;
v1 = $urandom_range(3);
if (v1 != 0 && v1 != 1 && v1 != 2 && v1 != 3) $stop;
end
// Seed stability
// Note UVM doesn't use $urandom seeding
v1 = $urandom(1);
v2 = $urandom(1);
if (v1 != v2) $stop;
v2 = $urandom(1);
if (v1 != v2) $stop;
`ifdef PROC
// Seed stability via process.srandom
p.srandom(1);
v1 = $urandom();
p.srandom(1);
v2 = $urandom();
if (v1 != v2) $stop;
p.srandom(1);
v2 = $urandom();
if (v1 != v2) $stop;
// Seed stability via process.get_randstate
s = p.get_randstate();
v1 = $urandom();
p.set_randstate(s);
v2 = $urandom();
if (v1 != v2) $stop;
p.set_randstate(s);
v2 = $urandom();
if (v1 != v2) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxm = 1e5 + 5; const int maxn = 1e5 + 5; const int inf = 0x3f3f3f3f; int n, m; int a[maxn]; struct edge { int u, v, w, next; } e[maxm * 2]; int head[maxn]; bool vis[maxn]; int cnt; priority_queue<int, vector<int>, greater<int> > q; void addedge(int u, int v, int w) { e[cnt].u = u; e[cnt].v = v; e[cnt].w = w; e[cnt].next = head[u]; head[u] = cnt++; } void add_edge(int u, int v, int w) { addedge(u, v, w); addedge(v, u, w); } void bfs() { vis[1] = 1; q.push(1); int temp = 1; while (!q.empty()) { int u = q.top(); a[temp++] = u; q.pop(); for (int i = head[u]; ~i; i = e[i].next) { int v = e[i].v; if (!vis[v]) { q.push(v); vis[v] = 1; } } } } int main() { cnt = 0; memset(vis, 0, sizeof(vis)); memset(head, -1, sizeof(head)); cin >> n >> m; int u, v; for (int i = 1; i <= m; i++) { cin >> u >> v; add_edge(u, v, 1); } bfs(); for (int i = 1; i <= n; i++) { printf( %d%c , a[i], i == n ? n : ); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; struct cate { long long num, t; bool operator<(const cate& other) const { return t > other.t; } } a[maxn]; int n; set<long long> has; map<long long, long long> fa; long long find(long long x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i].num; fa[a[i].num] = a[i].num; } for (int i = 1; i <= n; ++i) cin >> a[i].t; sort(a + 1, a + n + 1); long long ans = 0; for (int i = 1; i <= n; ++i) { long long cur = a[i].num; if (has.find(cur) != has.end()) { cur = find(cur); cur += 1; fa[cur] = cur; ans += (cur - a[i].num) * a[i].t; } has.insert(cur); if (has.find(cur - 1) != has.end()) fa[cur - 1] = cur; if (has.find(cur + 1) != has.end()) fa[cur] = cur + 1; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > vec; void update() { int x; scanf( %d , &x); vector<pair<int, int> > a, b; a.push_back({1000010, 0}); b.push_back({1000010, 0}); a.push_back({0, 0}); b.push_back({0, 0}); int sz = vec.size(); for (int i = 0; i + 1 < sz; i++) { int p = x - vec[i].first; if (p > 0) a.push_back({p, vec[i + 1].second}); if (p < 0) b.push_back({-p, vec[i].second}); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); vec.clear(); int i = 0, j = 0; int as = a.size(), bs = b.size(); while (i < as || j < bs) { if (a[i].first == b[j].first) { vec.push_back({a[i].first, a[i].second + b[j].second}); i++, j++; } else if (a[i].first < b[j].first) { vec.push_back({a[i].first, a[i].second + b[j].second}); i++; } else { vec.push_back({b[j].first, a[i].second + b[j].second}); j++; } } vec[0].second = 0; return; } void qry() { int s, e, ans = 0; scanf( %d %d , &s, &e); int sz = vec.size(); for (auto cur : vec) { if (e > cur.first) { if (cur.first > s) { ans += cur.second * (cur.first - s); s = cur.first; } } else { ans += cur.second * (e - s); break; } } printf( %d n , ans); return; } int main() { int n, q; scanf( %d %d , &n, &q); vec.push_back({0, 0}); vec.push_back({n, 1}); vec.push_back({1000010, 0}); while (q--) { int type; scanf( %d , &type); if (type == 1) update(); else qry(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_2_V
`define SKY130_FD_SC_LS__OR2B_2_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_2_V
|
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using vll = vector<long long>; using vvll = vector<vll>; using vpii = vector<pair<int, int> >; using vpll = vector<pair<long long, long long> >; using vld = vector<long double>; using vb = vector<bool>; const int inf = (int)1e9 + 7; const long long llinf = (long long)1e18 + 7; void solve() { long long n; cin >> n; vll a[n]; for (long long i = 0; i < n; i++) { long long ki; cin >> ki; for (long long j = 0; j < ki; j++) { long long x; cin >> x; a[i].push_back(x); } sort(a[i].begin(), a[i].end()); } long long ans = 0; for (long long i = 0; i < n; i++) { long long l, r; l = (i - 1 + n) % n; r = (i + 1 + n) % n; for (long long j = 1; j <= (a[i].size()) - 1; j++) { ans += (upper_bound(a[r].begin(), a[r].end(), a[i][j]) - upper_bound(a[r].begin(), a[r].end(), a[i][j - 1]) != upper_bound(a[l].begin(), a[l].end(), a[i][j]) - upper_bound(a[l].begin(), a[l].end(), a[i][j - 1])); } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int ttt = 1; while (ttt--) { solve(); } } |
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("f32.const.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("f32.const_tb.vcd");
$dumpvars(0, cpu_tb);
#12
`assert(result, 32'hc0000000);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int solve() { int n; cin >> n; if (n == 1) cout << 1 << endl; else { cout << n << ; for (int i = 1; i <= n - 1; ++i) cout << i << ; cout << n ; } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; t = 1; while (t-- != 0) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_SYMBOL_V
`define SKY130_FD_SC_HVL__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_SYMBOL_V
|
// ============================================================================
// Copyright (c) 2010 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
// Major Functions:
// Generate Reset Signal
//
// ============================================================================
// Design Description:
//
// ===========================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Eric Chen :| 10/06/01 :| Initial Version
// ============================================================================
module gen_reset_n(
tx_clk,
reset_n_in,
reset_n_out
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
parameter ctr_width = 20; // richard 16;
//===========================================================================
// PORT declarations
//===========================================================================
input tx_clk;
input reset_n_in;
output reset_n_out;
reg reset_n_out;
//=============================================================================
// REG/WIRE declarations
//=============================================================================
reg [ctr_width-1:0] ctr; // Reset counter
//=============================================================================
// Structural coding
//=============================================================================
always @(posedge tx_clk or negedge reset_n_in)
begin
if (!reset_n_in)
begin
reset_n_out <= 0;
ctr <= 0;
end else begin
if (ctr == {ctr_width{1'b1}})
begin
reset_n_out <= 1'b1; //Auto reset phy 1st time
end else begin
ctr <= ctr + 1;
reset_n_out <= 0;
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Top Level Miscelaneos module
// File : de_top_misc.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module contains functionality which used to be instantiated at the
// top level
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module de_top_misc
(// inputs
input de_clk,
input sys_locked,
input hb_clk,
input hb_rstn,
input [1:0] ps_2,
input pc_mc_rdy,
input busy_hb,
input mw_de_fip,
input [4:0] dr_style_2,
input dx_blt_actv_2,
input load_actvn,
input line_actv_2,
input wb_clip_ind,
input clip,
input deb,
input cmd_trig_comb,
input line_actv_1,
input blt_actv_1,
input [23:0] de_key_2,
input cmdcpyclr,
input pc_empty,
input abort_cmd_flag,
input [3:0] opc_1,
output reg mw_fip,
output ca_busy,
output ps8_2,
output ps16_2,
output ps565_2,
output ps32_2,
output de_pad8_2,
output [1:0] stpl_2,
output reg de_rstn,
output reg de_clint_tog,
output reg dx_clp,
output reg dx_deb,
output [31:0] kcol_2,
output de_trnsp_2,
output reg de_ddint_tog,
output [3:0] probe_misc
);
parameter LD_TEX = 4'hA, LD_TPAL = 4'hB;
wire wb_clip_rstn;
wire clip_ddd;
reg mw_fip_dd, de_busy_sync;
reg ca_busyi;
reg tmp_rstn;
reg clip_disab;
reg wb_clip;
reg clip_d, clip_dd;
reg deb_clr_hold;
reg deb_clr_q0,deb_clr_q1,deb_clr_q2;
reg deb_last;
reg de_clint;
reg abort_cmd_flag_d;
reg deb_inv_clr_q0;
reg deb_inv_clr_q1;
reg deb_inv_clr;
assign probe_misc = {ca_busyi, busy_hb, de_busy_sync, pc_mc_rdy};
// Syncronizers.
always @ (posedge de_clk) begin
de_busy_sync <= busy_hb;
mw_fip_dd <= mw_de_fip;
mw_fip <= mw_fip_dd;
end
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) ca_busyi <= 1'b0;
else ca_busyi <= ~pc_empty | ((busy_hb & de_busy_sync) |
(~pc_mc_rdy & ca_busyi));
end
assign ca_busy = (ca_busyi | busy_hb);
// create the pixel size bits
assign ps8_2 = (ps_2==2'b00);
assign ps16_2 = (ps_2==2'b01) | (ps_2==2'b11);
assign ps565_2 = (ps_2==2'b11);
assign ps32_2 = (ps_2==2'b10);
// 8 bit padding for linear
assign de_pad8_2 = dr_style_2[3] & dr_style_2[2];
// transparent enable bit
assign de_trnsp_2 = (dr_style_2[1] & ~dr_style_2[0] & ~(dx_blt_actv_2)) |
(dr_style_2[1] & ~dr_style_2[0] &
(dr_style_2[3] | dr_style_2[2]));
// stipple packed enable bit
assign stpl_2[1] = dr_style_2[3] & ~line_actv_2;
// stipple planar enable bit
assign stpl_2[0] = ~dr_style_2[3] & dr_style_2[2] & ~line_actv_2;
// syncronize the drawing engine reset.
always @ (posedge de_clk) begin
tmp_rstn <= (sys_locked & hb_rstn);
de_rstn <= tmp_rstn;
end //
//
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) clip_disab <= 1'b0;
else if (!load_actvn) clip_disab <= 1'b0;
else if (clip_ddd) clip_disab <= 1'b1;
end //
// grab the wb clip pulse.
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) wb_clip <= 1'b0;
else if (clip_ddd) wb_clip <= 1'b0; // checkme ???? ~
else if (wb_clip_ind) wb_clip <= 1'b1;
end //
always @ (posedge de_clk) begin
clip_d <= ((clip & line_actv_2) | wb_clip);
clip_dd <= clip_d;
de_clint <= (clip_ddd & ~clip_disab);
end //
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) de_clint_tog <= 1'b0;
else if(de_clint) de_clint_tog <= ~de_clint_tog;
end //
assign clip_ddd = clip_d & ~clip_dd;
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) de_ddint_tog <= 1'b0;
else if(cmdcpyclr) de_ddint_tog <= ~de_ddint_tog;
end //
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) dx_clp <= 1'b0;
else if (!load_actvn) dx_clp <= 1'b0;
else if (de_clint) dx_clp <= 1'b1;
end //
// Detect DEB going away
always @(posedge de_clk or negedge hb_rstn) begin
if (!hb_rstn) begin
deb_last <= 1'b0;
deb_clr_hold <= 1'b0;
abort_cmd_flag_d <= 1'b0;
end else begin
deb_last <= deb;
abort_cmd_flag_d <= abort_cmd_flag;
if((deb_last & ~deb) | (abort_cmd_flag_d & ~abort_cmd_flag)) deb_clr_hold <= ~deb_clr_hold;
// deb_clr_hold <= (deb_last & ~deb) ^ deb_clr_hold; // Selectable inverter
end
end
always @ (posedge hb_clk) begin
deb_clr_q0 <= deb_clr_hold;
deb_clr_q1 <= deb_clr_q0;
deb_clr_q2 <= deb_clr_q1;
end //
wire busy_and_not_noop;
assign busy_and_not_noop = (busy_hb && (line_actv_1 || blt_actv_1));
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) dx_deb <= 1'b0;
else if (cmd_trig_comb && !((opc_1 == LD_TEX) || (opc_1 == LD_TPAL))) dx_deb <= 1'b1;
else if ((deb_clr_q2 ^ deb_clr_q1) && !busy_and_not_noop) dx_deb <= 1'b0;
end //
// else if (cmd_trig_comb && (line_actv_1 || blt_actv_1)) dx_deb <= 1'b1;
assign kcol_2 = (ps8_2) ?
{de_key_2[7:0],de_key_2[7:0],de_key_2[7:0],de_key_2[7:0]} :
(ps16_2) ? {de_key_2[15:0],de_key_2[15:0]} : {8'h0,de_key_2};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Base;
endclass
class BasedA extends Base;
endclass
class BasedB extends Base;
endclass
module t (/*AUTOARG*/);
int i;
int a;
int ao;
Base b;
Base bo;
BasedA ba;
BasedA bao;
BasedB bb;
BasedB bbo;
// verilator lint_off CASTCONST
initial begin
a = 1234;
i = $cast(ao, a);
if (i != 1) $stop;
if (ao != 1234) $stop;
a = 12345;
$cast(ao, a);
if (ao != 12345) $stop;
i = $cast(ao, 2.1 * 3.7);
if (i != 1) $stop;
if (ao != 8) $stop;
i = $cast(bo, null);
if (i != 1) $stop;
if (bo != null) $stop;
ba = new;
b = ba;
i = $cast(bao, b);
if (i != 1) $stop;
if (b != ba) $stop;
bb = new;
b = bb;
i = $cast(bbo, b);
if (i != 1) $stop;
if (b != bb) $stop;
bb = new;
b = bb;
bao = ba;
i = $cast(bao, b);
if (i != 0) $stop;
if (bao != ba) $stop; // Unchanged
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a1, a2, b1, b2, c1, c2; int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> a1 >> b1 >> c1 >> a2 >> b2 >> c2; if (!a1 && !b1 && c1 || !a2 && !b2 && c2) { cout << 0 ; return 0; } if (a1 * b2 != a2 * b1) { cout << 1; return 0; } if (c1 * b2 == c2 * b1 && c1 * a2 == c2 * a1) { cout << -1 ; return 0; } cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, a[5001], b[1000001], d[1000001]; void doc() { for (int i = 1; i <= n; i++) cin >> a[i]; } void xuli() { sort(a + 1, a + n + 1); for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) d[a[j] - a[i]]++; int m = 0; while (true) { m++; int dem = 0, res = 0; for (int j = m; j <= 1000001; j += m) dem += d[j]; if (dem > (k * (k + 1)) / 2) continue; for (int i = 1; i <= n; i++) { if (b[a[i] % m] == m) res++; b[a[i] % m] = m; } if (res <= k) break; } cout << m; } int main() { cin >> n >> k; doc(); xuli(); } |
module game_text_top_ya
(
input wire clk, reset,
input wire [1:0] btn,
// we use the button now to control the FSM
output wire hsync, vsync,
output wire [2:0] rgb
);
// symbolic state declaration
// you may use one-hot if you wish
localparam [1:0]
newgame = 2'b00,
// display the registration information
play = 2'b01,
newball = 2'b10,
over = 2'b11;
// display the game over information
// score and logo are displayed in all these stages
// signal declaration
reg [1:0] state_reg, state_next;
wire [9:0] pixel_x, pixel_y;
wire video_on, pixel_tick;
// pixel_tick is the same as refr_tick
wire [3:0] text_on;
wire [2:0] text_rgb;
reg [2:0] rgb_reg, rgb_next;
wire [3:0] dig0, dig1;
// without actual meaning
reg [1:0] ball_reg, ball_next;
// ball's number
// I have to use ball's number to change the state machine
// as usual
assign dig0 = 4'b0000;
assign dig1 = 4'b0000;
// I assume I don't worry about the actual score for now
// instantiate video synchronization unit
vga_sync vsync_unit
(.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
.video_on(video_on), .p_tick(pixel_tick),
.pixel_x(pixel_x), .pixel_y(pixel_y));
// instantiate text module
game_text game_text_unit
(.clk(clk),
.pix_x(pixel_x), .pix_y(pixel_y),
.dig0(dig0), .dig1(dig1), .ball(ball_reg),
.text_on(text_on), .text_rgb(text_rgb));
//=======================================================
// FSMD
//=======================================================
// // FSMD state & data registers
// always @(posedge clk, posedge reset)
// if (reset)
// begin
// state_reg <= newgame;
// ball_reg <= 0;
// rgb_reg <= 0;
// end
// else
// begin
// state_reg <= state_next;
// ball_reg <= ball_next;
// if (pixel_tick)
// rgb_reg <= rgb_next;
// end
// // FSMD next-state logic
// always @*
// begin
// state_next = state_reg;
// ball_next = ball_reg;
// // the above two lines
// case (state_reg)
// newgame:
// begin
// ball_next = 2'b11; // three balls
// if (btn != 2'b00) // button pressed
// begin
// state_next = play;
// ball_next = ball_reg - 1;
// end
// end
// play:
// begin
// if (btn == 2'b11)
// begin
// state_next = newball;
// ball_next = ball_reg - 2;
// end
// end
// newball:
// if ((btn == 2'b00))
// begin
// state_next = over;
// ball_next = 2'b00;
// end
// over:
// state_next = newgame;
// endcase
// end
// //=======================================================
// // rgb multiplexing circuit
// // without graph, text only
// //=======================================================
// always @*
// if (~video_on)
// rgb_next = 3'b000; // blank the edge/retrace
// else
// // display score, rule, or game over
// if (text_on[3] ||
// ((state_reg==newgame) && text_on[1]) || // rule
// ((state_reg==over) && text_on[0]))
// rgb_next = text_rgb;
// else if (text_on[2]) // display logo
// rgb_next = text_rgb;
// else
// rgb_next = 3'b110; // yellow background
// // output
// assign rgb = rgb_reg;
// designate to the output pin (buffer, reason as before)
// CPP should be familiar with this trend by now
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int N, i, sum = 0, max; cin >> N; int A[N]; for (i = 0; i <= N - 1; i++) cin >> A[i]; max = *max_element(A, A + N); for (i = 0; i <= N - 1; i++) sum += (max - A[i]); cout << sum << endl; return 0; } |
//-----------------------------------------------------------------------------
// File : wishbone_bus.v
// Creation date : 06.04.2017
// Creation time : 11:52:40
// Description : Bus used to connect one wishbone master to multiple slaves. Used slave is determined using the address output of the master and parameters of each slave interface.
// Created by : TermosPullo
// Tool : Kactus2 3.4.27 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:communication:wishbone_bus:master_to_4
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication/wishbone_bus/master_to_4/wishbone_bus.master_to_4.xml
//-----------------------------------------------------------------------------
module wishbone_bus #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter SLAVE_0_BASE = 'h0100,
parameter SLAVE_1_BASE = 'h0200,
parameter SLAVE_2_BASE = 'h0300,
parameter SLAVE_3_BASE = 'h0400,
parameter SLAVE_RANGE = 'h0040
) (
// Interface: one_to_many_master
input [ADDR_WIDTH-1:0] adr_master,
input cyc_master,
input [DATA_WIDTH-1:0] dat_ms_master,
input stb_master,
input we_master,
output reg ack_master,
output reg [DATA_WIDTH-1:0] dat_sm_master,
output reg err_master,
// Interface: slave_0
input ack_slave_0,
input [DATA_WIDTH-1:0] dat_sm_slave_0,
input err_slave_0,
output [ADDR_WIDTH-1:0] adr_slave_0,
output cyc_slave_0,
output [DATA_WIDTH-1:0] dat_ms_slave_0,
output stb_slave_0,
output we_slave_0,
// Interface: slave_1
input ack_slave_1,
input [DATA_WIDTH-1:0] dat_sm_slave_1,
input err_slave_1,
output [ADDR_WIDTH-1:0] adr_slave_1,
output cyc_slave_1,
output [DATA_WIDTH-1:0] dat_ms_slave_1,
output stb_slave_1,
output we_slave_1,
// Interface: slave_2
input ack_slave_2,
input [DATA_WIDTH-1:0] dat_sm_slave_2,
input err_slave_2,
output [ADDR_WIDTH-1:0] adr_slave_2,
output cyc_slave_2,
output [DATA_WIDTH-1:0] dat_ms_slave_2,
output stb_slave_2,
output we_slave_2,
// Interface: slave_3
input ack_slave_3,
input [DATA_WIDTH-1:0] dat_sm_slave_3,
input err_slave_3,
output [ADDR_WIDTH-1:0] adr_slave_3,
output cyc_slave_3,
output [DATA_WIDTH-1:0] dat_ms_slave_3,
output stb_slave_3,
output we_slave_3
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// Assign most of the master outputs directly to slave inputs.
assign adr_slave_0 = adr_master;
assign cyc_slave_0 = cyc_master;
assign dat_ms_slave_0 = dat_ms_master;
assign we_slave_0 = we_master;
assign adr_slave_1 = adr_master;
assign cyc_slave_1 = cyc_master;
assign dat_ms_slave_1 = dat_ms_master;
assign we_slave_1 = we_master;
assign adr_slave_2 = adr_master;
assign cyc_slave_2 = cyc_master;
assign dat_ms_slave_2 = dat_ms_master;
assign we_slave_2 = we_master;
assign adr_slave_3 = adr_master;
assign cyc_slave_3 = cyc_master;
assign dat_ms_slave_3 = dat_ms_master;
assign we_slave_3 = we_master;
// Choose selected slave based on the address.
wire slave_0_sel = (adr_master >= SLAVE_0_BASE && adr_master < SLAVE_0_BASE+SLAVE_RANGE) ? 1 : 0;
wire slave_1_sel = (adr_master >= SLAVE_1_BASE && adr_master < SLAVE_1_BASE+SLAVE_RANGE) ? 1 : 0;
wire slave_2_sel = (adr_master >= SLAVE_2_BASE && adr_master < SLAVE_2_BASE+SLAVE_RANGE) ? 1 : 0;
wire slave_3_sel = (adr_master >= SLAVE_3_BASE && adr_master < SLAVE_3_BASE+SLAVE_RANGE) ? 1 : 0;
// Choose master inputs based on the selected slave.
always @* begin
if (slave_0_sel) begin
dat_sm_master <= dat_sm_slave_0;
ack_master <= ack_slave_0;
err_master <= err_slave_0;
end
else if (slave_1_sel) begin
dat_sm_master <= dat_sm_slave_1;
ack_master <= ack_slave_1;
err_master <= err_slave_1;
end
else if (slave_2_sel) begin
dat_sm_master <= dat_sm_slave_2;
ack_master <= ack_slave_2;
err_master <= err_slave_2;
end
else if (slave_3_sel) begin
dat_sm_master <= dat_sm_slave_3;
ack_master <= ack_slave_3;
err_master <= err_slave_3;
end
else begin
dat_sm_master <= 0;
ack_master <= 0;
err_master <= 0;
end
end
// Choose strobe based on the selected slave.
assign stb_slave_0 = slave_0_sel ? stb_master : 0;
assign stb_slave_1 = slave_1_sel ? stb_master : 0;
assign stb_slave_2 = slave_2_sel ? stb_master : 0;
assign stb_slave_3 = slave_3_sel ? stb_master : 0;
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_Audio_Out_Serializer *
* Description: *
* This module writes data to the Audio DAC on the Altera DE2 board. *
* *
*****************************************************************************/
module Altera_UP_Audio_Out_Serializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
left_channel_data,
left_channel_data_en,
right_channel_data,
right_channel_data_en,
// Bidirectionals
// Outputs
left_channel_fifo_write_space,
right_channel_fifo_write_space,
serial_audio_out_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUDIO_DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input [AUDIO_DATA_WIDTH:1] left_channel_data;
input left_channel_data_en;
input [AUDIO_DATA_WIDTH:1] right_channel_data;
input right_channel_data_en;
// Bidirectionals
// Outputs
output reg [7:0] left_channel_fifo_write_space;
output reg [7:0] right_channel_fifo_write_space;
output reg serial_audio_out_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_left_channel;
wire read_right_channel;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [6:0] left_channel_fifo_used;
wire [6:0] right_channel_fifo_used;
wire [AUDIO_DATA_WIDTH:1] left_channel_from_fifo;
wire [AUDIO_DATA_WIDTH:1] right_channel_from_fifo;
// Internal Registers
reg left_channel_was_read;
reg [AUDIO_DATA_WIDTH:1] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_fifo_write_space <= 8'h00;
else
left_channel_fifo_write_space <= 8'h80 - {left_channel_fifo_is_full,left_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_channel_fifo_write_space <= 8'h00;
else
right_channel_fifo_write_space <= 8'h80 - {right_channel_fifo_is_full,right_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
serial_audio_out_data <= 1'b0;
else
serial_audio_out_data <= data_out_shift_reg[AUDIO_DATA_WIDTH];
end
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_was_read <= 1'b0;
else if (read_left_channel)
left_channel_was_read <=1'b1;
else if (read_right_channel)
left_channel_was_read <=1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (read_left_channel)
data_out_shift_reg <= left_channel_from_fifo;
else if (read_right_channel)
data_out_shift_reg <= right_channel_from_fifo;
else if (left_right_clk_rising_edge | left_right_clk_falling_edge)
data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (bit_clk_falling_edge)
data_out_shift_reg <=
{data_out_shift_reg[(AUDIO_DATA_WIDTH - 1):1], 1'b0};
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign read_left_channel = left_right_clk_rising_edge &
~left_channel_fifo_is_empty &
~right_channel_fifo_is_empty;
assign read_right_channel = left_right_clk_falling_edge &
left_channel_was_read;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_SYNC_FIFO Audio_Out_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_channel_data_en & ~left_channel_fifo_is_full),
.write_data (left_channel_data),
.read_en (read_left_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_from_fifo)
);
defparam
Audio_Out_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_Out_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Left_Channel_FIFO.ADDR_WIDTH = 7;
Altera_UP_SYNC_FIFO Audio_Out_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (right_channel_data_en & ~right_channel_fifo_is_full),
.write_data (right_channel_data),
.read_en (read_right_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_from_fifo)
);
defparam
Audio_Out_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_Out_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Right_Channel_FIFO.ADDR_WIDTH = 7;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_SYMBOL_V
`define SKY130_FD_SC_MS__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; string ans; cin >> s; int i = 0; int j = 0; while (i < s.size() & j < 3) { if (j == 0) { if (s[i] == f ) { ans = ftp:// ; i = 3; } else { ans = http:// ; i = 4; } j = 1; } if (j == 1) { int temp = i; while (s[i + 1] != r || s[i + 2] != u ) { i++; } ans += s.substr(temp, i + 1 - temp); ans += .ru ; i = i + 3; j = 2; } if (j == 2) { if (s.size() - i) { ans += / ; ans += s.substr(i, s.size() - i); i = s.size(); } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int N = 1000001; vector<int> count(N); long long n; cin >> n; vector<long long> a(n), ans; long long sum = 0, i, j, k; for (i = 0; i < n; i++) cin >> a[i], sum += a[i], count[a[i]]++; for (i = 0; i < n; i++) if ((sum - a[i]) % 2 == 0 && (sum - a[i]) / 2 < N && (count[(sum - a[i]) / 2] > 1 || (count[(sum - a[i]) / 2] == 1 && a[i] != (sum - a[i]) / 2))) ans.push_back(i + 1); cout << ans.size() << endl; for (auto x : ans) cout << x << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class A, class B> inline bool mina(A &first, B second) { return (first > second) ? (first = second, 1) : 0; } template <class A, class B> inline bool maxa(A &first, B second) { return (first < second) ? (first = second, 1) : 0; } const int MAXN = 1e5 + 5; int N, K; int ans[MAXN]; long long minimum(long long prev, long long num) { long long start = prev + 1; long long end = start + num - 1; return (start + end) * num / 2; } int main() { cin >> N >> K; int ll = 1, rr = N; while (ll <= rr) { int mid = (ll + rr) / 2; if (mid + minimum(mid, K - 1) > N) { rr = mid - 1; } else { ll = mid + 1; } } if (rr == 0) { cout << NO << endl; return 0; } ans[0] = rr; int left = N - rr; int now = 1; while (left) { if (now >= K) { cout << NO << endl; return 0; } else if (now + 1 == K) { ans[now] = left; if (left > ans[now - 1] && left <= 2 * ans[now - 1]) { break; } else { cout << NO << endl; return 0; } } else { if (2LL * ans[now - 1] + minimum(ans[now - 1] * 2, K - now - 1) > left) { int ll = ans[now - 1] + 1; int rr = 2LL * ans[now - 1]; while (ll <= rr) { int mid = (ll + rr) / 2; if (mid + minimum(mid, K - now - 1) > left) { rr = mid - 1; } else { ll = mid + 1; } } if (rr < ans[now - 1] + 1) { cout << NO << endl; return 0; } ans[now] = rr; left -= ans[now]; now++; } else { ans[now] = ans[now - 1] * 2; left -= ans[now]; now++; } } } cout << YES << endl; for (int i = 0; (i) < (K); ++(i)) { cout << ans[i] << ; } cout << endl; return 0; } |
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Jan 27 13:19:39 2015"
module reg_8x8_bit(
clock,
reset,
WR,
DA,
AA,
BA,
D,
A,
B,
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7
);
input wire clock;
input wire WR;
input wire reset;
input wire [2:0] AA;
input wire [2:0] BA;
input wire [7:0] D;
input wire [2:0] DA;
output wire [7:0] A;
output wire [7:0] B;
output wire [7:0] R0;
output wire [7:0] R1;
output wire [7:0] R2;
output wire [7:0] R3;
output wire [7:0] R4;
output wire [7:0] R5;
output wire [7:0] R6;
output wire [7:0] R7;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire [7:0] SYNTHESIZED_WIRE_32;
wire [7:0] SYNTHESIZED_WIRE_33;
wire [7:0] SYNTHESIZED_WIRE_34;
wire [7:0] SYNTHESIZED_WIRE_35;
wire [7:0] SYNTHESIZED_WIRE_36;
wire [7:0] SYNTHESIZED_WIRE_37;
wire [7:0] SYNTHESIZED_WIRE_38;
wire [7:0] SYNTHESIZED_WIRE_39;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_26;
wire SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_28;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
assign R0 = SYNTHESIZED_WIRE_32;
assign R1 = SYNTHESIZED_WIRE_33;
assign R2 = SYNTHESIZED_WIRE_34;
assign R3 = SYNTHESIZED_WIRE_35;
assign R4 = SYNTHESIZED_WIRE_36;
assign R5 = SYNTHESIZED_WIRE_37;
assign R6 = SYNTHESIZED_WIRE_38;
assign R7 = SYNTHESIZED_WIRE_39;
reg_8bit b2v_inst(
.clk(clock),
.Load(SYNTHESIZED_WIRE_0),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_32));
assign SYNTHESIZED_WIRE_29 = WR & SYNTHESIZED_WIRE_1;
reg_8bit b2v_inst10(
.clk(clock),
.Load(SYNTHESIZED_WIRE_2),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_39));
reg_8bit b2v_inst11(
.clk(clock),
.Load(SYNTHESIZED_WIRE_3),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_34));
reg_8bit b2v_inst12(
.clk(clock),
.Load(SYNTHESIZED_WIRE_4),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_36));
reg_8bit b2v_inst13(
.clk(clock),
.Load(SYNTHESIZED_WIRE_5),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_35));
reg_8bit b2v_inst14(
.clk(clock),
.Load(SYNTHESIZED_WIRE_6),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_37));
reg_8bit b2v_inst15(
.clk(clock),
.Load(SYNTHESIZED_WIRE_7),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_38));
decoder3to8 b2v_inst16(
.S(DA),
.m0(SYNTHESIZED_WIRE_8),
.m1(SYNTHESIZED_WIRE_1),
.m2(SYNTHESIZED_WIRE_25),
.m3(SYNTHESIZED_WIRE_26),
.m4(SYNTHESIZED_WIRE_27),
.m5(SYNTHESIZED_WIRE_28),
.m6(SYNTHESIZED_WIRE_30),
.m7(SYNTHESIZED_WIRE_31));
assign SYNTHESIZED_WIRE_0 = WR & SYNTHESIZED_WIRE_8;
mux8to1_8bit b2v_inst18(
.i1(SYNTHESIZED_WIRE_32),
.i2(SYNTHESIZED_WIRE_33),
.i3(SYNTHESIZED_WIRE_34),
.i4(SYNTHESIZED_WIRE_35),
.i5(SYNTHESIZED_WIRE_36),
.i6(SYNTHESIZED_WIRE_37),
.i7(SYNTHESIZED_WIRE_38),
.i8(SYNTHESIZED_WIRE_39),
.S(BA),
.Q(B));
mux8to1_8bit b2v_inst2(
.i1(SYNTHESIZED_WIRE_32),
.i2(SYNTHESIZED_WIRE_33),
.i3(SYNTHESIZED_WIRE_34),
.i4(SYNTHESIZED_WIRE_35),
.i5(SYNTHESIZED_WIRE_36),
.i6(SYNTHESIZED_WIRE_37),
.i7(SYNTHESIZED_WIRE_38),
.i8(SYNTHESIZED_WIRE_39),
.S(AA),
.Q(A));
assign SYNTHESIZED_WIRE_3 = WR & SYNTHESIZED_WIRE_25;
assign SYNTHESIZED_WIRE_5 = WR & SYNTHESIZED_WIRE_26;
assign SYNTHESIZED_WIRE_4 = WR & SYNTHESIZED_WIRE_27;
assign SYNTHESIZED_WIRE_6 = WR & SYNTHESIZED_WIRE_28;
reg_8bit b2v_inst7(
.clk(clock),
.Load(SYNTHESIZED_WIRE_29),
.not_reset(reset),
.D(D),
.Q(SYNTHESIZED_WIRE_33));
assign SYNTHESIZED_WIRE_7 = WR & SYNTHESIZED_WIRE_30;
assign SYNTHESIZED_WIRE_2 = WR & SYNTHESIZED_WIRE_31;
endmodule
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