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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); string str; cin >> str; bool flag = false; for (int i = 0; i < str.size(); i++) { if (str[i] == H || str[i] == Q || str[i] == 9 ) { flag = true; break; } } if (flag) cout << YES n ; else cout << NO n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long dp[5011][5011]; void solve() { long long n, m; cin >> n >> m; string s1, s2; cin >> s1 >> s2; s1 = . + s1; s2 = . + s2; long long ans = 0; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { dp[i][j] = max({0ll, dp[i - 1][j] - 1, dp[i][j - 1] - 1}); if (s1[i] == s2[j]) dp[i][j] = max( {0ll, dp[i - 1][j] - 1, dp[i][j - 1] - 1, dp[i - 1][j - 1] + 2}); ans = max(ans, dp[i][j]); } } cout << ans; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int read() { int kkk = 0, x = 1; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) c = getchar(), x = -1; while (c >= 0 && c <= 9 ) kkk = (kkk << 3) + (kkk << 1) + (c - 0 ), c = getchar(); return kkk * x; } int n, can[200001], maxn, ans, sum[200001], a[200001], minn[400001]; int c1[200001], c2[200001]; void check(int v) { memset(c1, 0, sizeof(c1)); memset(c2, 0, sizeof(c2)); int L = 1; c2[0] = n; for (int i = 1; i <= n; ++i) { if (a[i] == maxn && c1[a[i]] == v) { while (a[L] != maxn) { --c2[c1[a[L]]]; --c1[a[L]]; ++c2[c1[a[L]]]; ++L; } ++L; } else { --c2[c1[a[i]]]; ++c1[a[i]]; ++c2[c1[a[i]]]; } if (c1[maxn] == v && c2[c1[maxn]] >= 2) ans = max(ans, i - L + 1); } } int main() { n = read(); for (int i = 1; i <= n; ++i) { a[i] = read(); ++can[a[i]]; if (can[a[i]] > can[maxn]) maxn = a[i]; } for (int i = 1; i <= n; ++i) sum[i] = sum[i - 1] + (a[i] == maxn); int lim = sqrt(n); for (int col = 1; col <= n; ++col) { if (col == maxn) continue; if (can[col] >= lim) { for (int i = 1; i <= 2 * n; ++i) minn[i] = n + 1; minn[n] = 0; int sumv = 0; for (int i = 1; i <= n; ++i) { sumv += (a[i] == col); int v = sumv - sum[i] + n; ans = max(ans, i - minn[v]); minn[v] = min(minn[v], i); } } } for (int i = 1; i <= lim; ++i) check(i); printf( %d n , ans); return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_srl_fifo
*/
module test_axis_srl_fifo_64;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
count
);
// dump file
$dumpfile("test_axis_srl_fifo_64.lxt");
$dumpvars(0, test_axis_srl_fifo_64);
end
axis_srl_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.count(count)
);
endmodule
|
//*******************************************************************************************************************************************************/
// Module Name: smr_reg
// Module Type: Synchronous Register
// Author: Shreyas Vinod
// Purpose: Memory Address Register (MAR) and Program Counter (PC) for Neptune I v3.0
// Description: A synchronous register specifically designed for Neptune I's Memory Address Register (MAR) and Program Counter (PC) with memory reset
// support.
//*******************************************************************************************************************************************************/
module smr_reg(clk, rst, we, incr, wr, rd);
// Parameter Definitions
parameter width = 'd16; // Register Width
parameter add_width = 'd13; // Addressing Width, cannot be larger than the Data Width
// Inputs
input wire clk /* System Clock Input */, rst /* System Reset. Resets memory contents. */; // Management Interfaces
input wire we /* Register Write Enable */, incr /* Increment contents */; // Control Interfaces
input wire [width-1:0] wr /* Write Port */;
// Outputs
output wire [add_width-1:0] rd /* Read Port to A Bus */;
// Internal
reg [width-1:0] mem /* Register Memory */;
// Read Logic
assign rd [add_width-1:0] = mem [add_width-1:0];
// Memory Write Block
always@(posedge clk) begin
if(rst) mem [width-1:0] <= {width{1'b0}}; // Resets the contents of memory if rst is true.
else if(we) mem [width-1:0] <= wr [width-1:0]; // Writes the value at wr to memory if we is true.
else if(incr) mem [width-1:0] <= mem [width-1:0] + 1'b1; // Increment Memory contents.
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; inline void chkmax(long long &a, long long b) { if (a < b) a = b; } inline void chkmin(long long &a, long long b) { if (a > b) a = b; } inline long long read() { long long a = 0, fh = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) fh = -1; c = getchar(); } while ( 0 <= c && c <= 9 ) { a = a * 10 + c - 48; c = getchar(); } return a * fh; } vector<long long> edge[300005]; long long f[300005][2][2], tmp[2][2]; long long n, fa[300005]; void dfs(long long x) { f[x][0][0] = 1; f[x][0][1] = 1; for (long long i = 0; i < edge[x].size(); ++i) { if (fa[x] == edge[x][i]) continue; fa[edge[x][i]] = x; dfs(edge[x][i]); long long v = edge[x][i]; for (long long j = 0; j < 2; ++j) for (long long k = 0; k < 2; ++k) tmp[j][k] = f[x][j][k]; f[x][0][0] *= (f[v][0][0] + f[v][1][0] + f[v][1][1]) % 998244353; f[x][0][1] *= (f[v][0][0] + f[v][1][0] + f[v][1][1]) % 998244353; f[x][1][0] = (f[x][1][0] * ((f[v][0][0] * 2 + f[v][0][1] + f[v][1][1] * 2 + f[v][1][0] * 2) % 998244353) % 998244353 + tmp[0][0] * ((f[v][0][0] + f[v][0][1] + f[v][1][1] + f[v][1][0]) % 998244353)) % 998244353; f[x][1][1] = (f[x][1][1] * ((f[v][0][0] + f[v][1][0] * 2 + f[v][0][1] + f[v][1][1]) % 998244353) % 998244353 + tmp[0][1] * (f[v][0][0] + f[v][1][0])) % 998244353; for (long long j = 0; j < 2; ++j) for (long long k = 0; k < 2; ++k) f[x][j][k] %= 998244353; } } signed main() { n = read(); for (long long i = 1; i < n; ++i) { long long x = read(), y = read(); edge[x].push_back(y); edge[y].push_back(x); } dfs(1); printf( %lld n , (f[1][1][0] + f[1][1][1] + f[1][0][0] - 1 + 998244353) % 998244353); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dir_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_dir_ctl(/*AUTOARG*/
// Outputs
so, rd_data_en_c4, wr_data_en_c4, cam_en_c4, rw_entry_c4,
inval_mask_c4, warm_rst_c4, rd_data_sel0_c5, rd_data_sel1_c5,
rd_data_sel_right_c6, rd_data_sel_left_c6,
// Inputs
lkup_en_c4_buf, inval_mask_c4_buf, rw_dec_c4_buf, rd_en_c4_buf,
wr_en_c4_buf, rw_entry_c4_buf, dir_clear_c4_buf, rclk, si, se,
sehold
);
input [3:0] lkup_en_c4_buf ; // Right
input [7:0] inval_mask_c4_buf ; // Right
input [3:0] rw_dec_c4_buf; // Right
input rd_en_c4_buf ; // Right
input wr_en_c4_buf ; // Right
input [5:0] rw_entry_c4_buf; // Right
input dir_clear_c4_buf ; // Right
input rclk;
input si, se;
input sehold; // POST_4.2 pin
output so;
output [3:0] rd_data_en_c4, wr_data_en_c4; //( 0 leftTOp, 1 rightTOp, 2 leftBOttom 3 RightBottom )
output [3:0] cam_en_c4; //( 0 leftTOp, 1 rightTOp, 2 leftBOttom 3 RightBottom )
// Pins on TOP
output [5:0] rw_entry_c4;
output [7:0] inval_mask_c4; // one output
output warm_rst_c4;
// Pin on left
output rd_data_sel0_c5;
// pin on right
output rd_data_sel1_c5;
// Pin on the right
output rd_data_sel_right_c6;
// Pin on left
output rd_data_sel_left_c6;
wire rd_data_sel_left_c5, rd_data_sel_right_c5;
wire [3:0] rd_data_en_c5; //( 0 leftTOp, 1 rightTOp, 2 leftBOttom 3 RightBottom )
assign warm_rst_c4 = dir_clear_c4_buf ;
assign rd_data_en_c4 = {4{rd_en_c4_buf}} & rw_dec_c4_buf ;
//---------------\/ added to prevent a write and valid bit reset conflict \/-----------
assign wr_data_en_c4 = {4{wr_en_c4_buf & ~warm_rst_c4 }} & rw_dec_c4_buf ;
dffe_s #(2) ff_rd_data_en_c5_en (
.q (rd_data_en_c5[1:0]), .din (rd_data_en_c4[1:0]),
.en(~sehold),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(2) ff_rd_data_en_c5 (
.q (rd_data_en_c5[3:2]), .din (rd_data_en_c4[3:2]),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign rd_data_sel0_c5 = rd_data_en_c5[0] ;
assign rd_data_sel1_c5 = rd_data_en_c5[1] ;
assign rd_data_sel_left_c5 = rd_data_en_c5[0] | rd_data_en_c5[2] ;
dff_s #(1) ff_rd_data_sel_left_c6 (
.q (rd_data_sel_left_c6), .din (rd_data_sel_left_c5),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign rd_data_sel_right_c5 = rd_data_en_c5[1] | rd_data_en_c5[3] ;
dff_s #(1) ff_rd_data_sel_right_c6 (
.q (rd_data_sel_right_c6), .din (rd_data_sel_right_c5),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign cam_en_c4[3:0] = lkup_en_c4_buf[3:0] ;
assign inval_mask_c4[7:0] = inval_mask_c4_buf[7:0] ;
assign rw_entry_c4[5:0] = rw_entry_c4_buf[5:0] ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_FUNCTIONAL_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S
);
// Module ports
output Z;
input [7:0] D;
input [7:0] S;
// Name Output Other arguments
bufif1 bufif10 (Z , !D[0], S[0] );
bufif1 bufif11 (Z , !D[1], S[1] );
bufif1 bufif12 (Z , !D[2], S[2] );
bufif1 bufif13 (Z , !D[3], S[3] );
bufif1 bufif14 (Z , !D[4], S[4] );
bufif1 bufif15 (Z , !D[5], S[5] );
bufif1 bufif16 (Z , !D[6], S[6] );
bufif1 bufif17 (Z , !D[7], S[7] );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_FUNCTIONAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
preset,
clk,
rst);
// clock reset
input preset;
input clk;
output rst;
// simple reset gen
lpm_ff #(.LPM_WIDTH(1), .LPM_AVALUE(1'b1)) i_rst_reg (
.enable (1'b1),
.data (1'b0),
.aset (preset),
.clock (clk),
.q (rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Forward Discrete Cosine Transform and ZigZag unit ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: fdct.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: fdct.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module fdct(clk, ena, rst, dstrb, din, dout, douten);
//
// parameters
//
////////////////////////////////////////////////////////////////////
// //
// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
// //
////////////////////////////////////////////////////////////////////
// //
// Worst case error (all input values -128) is //
// zero (i.e. no errors) when using 15bit coefficients //
// //
// Using less bits for the coefficients produces a biterror //
// approx. equal to (15 - used_coefficient-bits). //
// i.e. 14bit coefficients, errors in dout-bit[0] only //
// 13bit coefficients, errors in dout-bits[1:0] //
// 12bit coefficients, errors in dout-bits[2:0] etc. //
// Tests with real non-continous tone image data have shown that //
// even when using 13bit coefficients errors remain in the lsb //
// only (i.e. dout-bit[0] //
// //
// The amount of coefficient-bits needed is dependent on the //
// desired quality. //
// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
// that the output of the combined DCT AND Quantization unit //
// shall not exceed 1 for the desired quality. //
// //
// This means for high quantization levels, lesser bits //
// for the DCT unit can be used. //
// //
// Looking at the recommended "quantization tables for generic //
// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
// it can be noticed that relatively large quantization values //
// are being used. Errors in the lower-order bits should //
// therefore not be visible. //
// For certain applications some of the lower-order bits could //
// actually be discarded. When looking at the luminance and //
// chrominance example quantization tables (ITU-T.81 annex K) //
// it can be seen that the smallest quantization value is ten //
// (qnt_val_min = 10). This means that the lowest 2bits can be //
// discarded (set to zero '0') without having any effect on the //
// final result. In this example 11 bit or 12 bit coefficients //
// would be sufficient. //
// //
////////////////////////////////////////////////////////////////////
parameter coef_width = 11;
parameter di_width = 8;
parameter do_width = 12;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // active low asynchronous reset
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width-1:0] din;
output [do_width-1:0] dout;
output douten; // data-out enable
//
// variables
//
wire doe;
wire [do_width -1:0] // results from DCT module
res00, res01, res02, res03, res04, res05, res06, res07,
res10, res11, res12, res13, res14, res15, res16, res17,
res20, res21, res22, res23, res24, res25, res26, res27,
res30, res31, res32, res33, res34, res35, res36, res37,
res40, res41, res42, res43, res44, res45, res46, res47,
res50, res51, res52, res53, res54, res55, res56, res57,
res60, res61, res62, res63, res64, res65, res66, res67,
res70, res71, res72, res73, res74, res75, res76, res77;
//
// module body
//
// Hookup DCT module
dct #(coef_width, di_width, do_width)
dct_mod(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout_00(res00),
.dout_01(res01),
.dout_02(res02),
.dout_03(res03),
.dout_04(res04),
.dout_05(res05),
.dout_06(res06),
.dout_07(res07),
.dout_10(res10),
.dout_11(res11),
.dout_12(res12),
.dout_13(res13),
.dout_14(res14),
.dout_15(res15),
.dout_16(res16),
.dout_17(res17),
.dout_20(res20),
.dout_21(res21),
.dout_22(res22),
.dout_23(res23),
.dout_24(res24),
.dout_25(res25),
.dout_26(res26),
.dout_27(res27),
.dout_30(res30),
.dout_31(res31),
.dout_32(res32),
.dout_33(res33),
.dout_34(res34),
.dout_35(res35),
.dout_36(res36),
.dout_37(res37),
.dout_40(res40),
.dout_41(res41),
.dout_42(res42),
.dout_43(res43),
.dout_44(res44),
.dout_45(res45),
.dout_46(res46),
.dout_47(res47),
.dout_50(res50),
.dout_51(res51),
.dout_52(res52),
.dout_53(res53),
.dout_54(res54),
.dout_55(res55),
.dout_56(res56),
.dout_57(res57),
.dout_60(res60),
.dout_61(res61),
.dout_62(res62),
.dout_63(res63),
.dout_64(res64),
.dout_65(res65),
.dout_66(res66),
.dout_67(res67),
.dout_70(res70),
.dout_71(res71),
.dout_72(res72),
.dout_73(res73),
.dout_74(res74),
.dout_75(res75),
.dout_76(res76),
.dout_77(res77),
.douten(doe)
);
// Hookup ZigZag unit
zigzag zigzag_mod(
.clk(clk),
.ena(ena),
.dstrb(doe),
.din_00(res00),
.din_01(res01),
.din_02(res02),
.din_03(res03),
.din_04(res04),
.din_05(res05),
.din_06(res06),
.din_07(res07),
.din_10(res10),
.din_11(res11),
.din_12(res12),
.din_13(res13),
.din_14(res14),
.din_15(res15),
.din_16(res16),
.din_17(res17),
.din_20(res20),
.din_21(res21),
.din_22(res22),
.din_23(res23),
.din_24(res24),
.din_25(res25),
.din_26(res26),
.din_27(res27),
.din_30(res30),
.din_31(res31),
.din_32(res32),
.din_33(res33),
.din_34(res34),
.din_35(res35),
.din_36(res36),
.din_37(res37),
.din_40(res40),
.din_41(res41),
.din_42(res42),
.din_43(res43),
.din_44(res44),
.din_45(res45),
.din_46(res46),
.din_47(res47),
.din_50(res50),
.din_51(res51),
.din_52(res52),
.din_53(res53),
.din_54(res54),
.din_55(res55),
.din_56(res56),
.din_57(res57),
.din_60(res60),
.din_61(res61),
.din_62(res62),
.din_63(res63),
.din_64(res64),
.din_65(res65),
.din_66(res66),
.din_67(res67),
.din_70(res70),
.din_71(res71),
.din_72(res72),
.din_73(res73),
.din_74(res74),
.din_75(res75),
.din_76(res76),
.din_77(res77),
.dout(dout),
.douten(douten)
);
endmodule
|
module blinki (
(* intersynth_port = "Reset_n_i" *)
input Reset_n_i,
(* intersynth_port = "Clk_i" *)
input Clk_i,
(* intersynth_port = "Outputs_o", intersynth_conntype = "Bit" *)
output reg LED_o,
(* intersynth_param = "PeriodH_i", intersynth_conntype = "Word" *)
input[15:0] PeriodH_i,
(* intersynth_param = "PeriodL_i", intersynth_conntype = "Word" *)
input[15:0] PeriodL_i
);
// Sensor FSM
localparam stStart = 3'b000;
localparam stOn = 3'b001;
localparam stOff = 3'b010;
reg [2:0] State;
reg [2:0] NextState;
reg TimerPreset;
reg TimerEnable;
wire TimerOvfl;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
State <= stStart;
end
else
begin // rising clock edge
// state register
State <= NextState;
end
end
always @(State, TimerOvfl)
begin // process CombProc
NextState = State;
// control signal default values
TimerEnable = 1'b1;
TimerPreset = 1'b0;
// next state and output logic
case (State)
stStart: begin
TimerPreset = 1'b1;
NextState = stOn;
end
stOn: begin
LED_o = 1'b1;
if (TimerOvfl == 1'b1)
begin
NextState = stOff;
TimerPreset = 1'b1;
end
end
stOff: begin
LED_o = 1'b0;
if (TimerOvfl == 1'b1)
begin
NextState = stOn;
TimerPreset = 1'b1;
end
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [31:0] Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Timer <= 32'd0;
end
else
begin
if (TimerPreset)
begin
Timer <= {PeriodH_i, PeriodL_i};
end
else if (TimerEnable)
begin
Timer <= Timer - 1'b1;
end
end
end
assign TimerOvfl = (Timer == 0) ? 1'b1 : 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_SYMBOL_V
`define SKY130_FD_SC_MS__A2111OI_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int inf = 0x3f3f3f3f; const double eps = 1e-10; const long long INF = (1LL << 60); int main() { int a, b; scanf( %d%d , &a, &b); if (a == b) { printf( %d n , a); return 0; } double ans = -1; if (a >= b) { int k = (int)floor((a * 1.0 / b - 1) / 2); ans = (a - b) * 1.0 / (2 * k); ans = min(ans, (a + b) * 1.0 / (2 * k + 2)); } printf( %0.12f n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int top = 0; int N, Q, NN; int K, M, R; vector<int> Adj[100005]; int dep[100005]; int anc[100005][21]; int pre[100005], pst[100005], tt; void dfs(int u) { pre[u] = ++tt; for (int j = 1; j <= 20; j++) { if (dep[u] <= (1 << j)) break; anc[u][j] = anc[anc[u][j - 1]][j - 1]; } int v; for (int k = 0; k < Adj[u].size(); k++) { v = Adj[u][k]; if (v == anc[u][0]) continue; anc[v][0] = u; dep[v] = dep[u] + 1; dfs(v); } pst[u] = ++tt; } int lca(int u, int v) { if (dep[u] < dep[v]) swap(u, v); for (int j = 20; j >= 0; j--) { if (dep[anc[u][j]] >= dep[v]) { u = anc[u][j]; } } if (u == v) return u; for (int j = 20; j >= 0; j--) { if (anc[u][j] != anc[v][j]) { u = anc[u][j]; v = anc[v][j]; } } return anc[u][0]; } int h[100005], c[2 * 100005]; int lbt(int x) { return x & (-x); } void update(int x, int dv) { for (; x <= NN; x += lbt(x)) { c[x] += dv; } } int getsum(int x) { int ans = 0; for (; x > 0; x -= lbt(x)) { ans += c[x]; } return ans; } bool cmp(const int& a, const int& b) { return dep[a] < dep[b]; } int query(int u, int lca) { return getsum(pre[u] - 1) - getsum(pre[lca] - 1); } int a[100005]; bool vis[100005]; long long dp[100005][305]; int work() { int u, z; for (int i = 1; i <= K; i++) { u = a[i]; update(pre[u], 1); update(pst[u], -1); vis[a[i]] = 1; } int x; for (int i = 1; i <= K; i++) { u = a[i]; z = lca(u, R); if (u == R) h[i] = 0; else if (u == z) h[i] = query(R, u) - (vis[u] == true) + (vis[R] == true); else if (z == R) h[i] = query(u, R); else h[i] = query(u, z) + query(R, z) - (vis[z] == true) + (vis[R] == true); } sort(h + 1, h + 1 + K); dp[1][1] = 1; for (int i = 2; i <= K; i++) { for (int j = 1; j <= M; j++) { if (j > h[i]) dp[i][j] = ((long long)dp[i - 1][j] * (j - h[i]) % int(1e9 + 7) + dp[i - 1][j - 1]) % int(1e9 + 7); else dp[i][j] = 0; } } long long ans = 0; for (int j = 1; j <= M; j++) { ans = (ans + dp[K][j]) % int(1e9 + 7); } for (int i = 1; i <= K; i++) { u = a[i]; update(pre[u], -1); update(pst[u], +1); vis[a[i]] = 0; } return ans; } int main() { scanf( %d%d , &N, &Q); int u, v; for (int i = 1; i < N; i++) { scanf( %d%d , &u, &v); Adj[u].push_back(v); Adj[v].push_back(u); } dep[1] = 1; dfs(1); NN = 2 * N; while (Q--) { scanf( %d%d%d , &K, &M, &R); for (int i = 1; i <= K; i++) { scanf( %d , &a[i]); } printf( %d n , work()); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 9; int main() { long long n, m; cin >> n >> m; vector<int> row(n), col(n); int r = 0, c = 0; int x, y; long long ans = n * n; for (int i = 0; i < m; i++) { scanf( %d %d , &x, &y); long long v = 0; if (row[x - 1] == 0 && col[y - 1] == 0) v = n + n - (1 + r + c); else if (row[x - 1] && col[y - 1]) v = 0; else if (row[x - 1]) v = n - r; else if (col[y - 1]) v = n - c; ans -= v; if (row[x - 1] == 0) row[x - 1] = 1, r++; if (col[y - 1] == 0) col[y - 1] = 1, c++; printf( %lld , ans); } printf( n ); } |
#include <bits/stdc++.h> using namespace std; typedef struct { long long j, x1, x2; } inter; struct comp1 { bool operator()(const inter& a, const inter& b) const { return a.x1 < b.x1; }; }; struct comp2 { bool operator()(const inter& a, const inter& b) const { return (a.x2 == b.x2) ? (a.x1 < b.x1) : (a.x2 < b.x2); }; }; void solve() { long long n; cin >> n; vector<long long> a(n), b(n), m(n); unordered_map<long long, vector<long long>> dsize; for (long long i = 0; i < (n); i++) { cin >> a[i] >> b[i] >> m[i]; dsize[a[i] + b[i] - m[i]].push_back(i); } long long c = 0; vector<long long> ea(n); for (auto& x : dsize) { multiset<inter, comp1> inter1; multiset<inter, comp2> inter2; for (auto& i : x.second) { long long eamax = min(m[i], a[i]); long long eamin = max(m[i] - b[i], 0LL); inter1.insert(inter{i, a[i] - eamax, a[i] - eamin}); inter2.insert(inter{i, a[i] - eamax, a[i] - eamin}); } auto p1 = inter1.begin(); while (!inter2.empty()) { long long targ = inter2.begin()->x2; while ((p1 == inter1.end()) ? false : (p1->x1 <= targ)) { inter2.erase(*p1); ea[p1->j] = a[p1->j] - targ; p1++; } c++; } } cout << c << endl; for (long long i = 0; i < (n); i++) cout << ea[i] << << m[i] - ea[i] << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); ifstream ifs; if ( [0]) cin.rdbuf((ifs = ifstream( )).rdbuf()); ; ofstream ofs; if ( [0]) cout.rdbuf((ofs = ofstream( )).rdbuf()); ; ofstream lfs; if ( [0]) clog.rdbuf((lfs = ofstream( )).rdbuf()); ; int t; cin >> t; for (int i = 1; i <= t; i++) { solve(); } } |
#include <bits/stdc++.h> using namespace std; vector<int> vi; void primefact(int n) { while (n % 2 == 0) { vi.push_back(2); n /= 2; } int i = 3; while (i <= n) { while (n % i == 0) { vi.push_back(i); n /= i; } i += 2; } if (n > 2) vi.push_back(n); } int main() { int n, k, last = 1, i; cin >> n >> k; primefact(n); if (k > vi.size()) cout << -1 << endl; else { for (i = 0; i < k - 1; i++) cout << vi[i] << ; for (i = k - 1; i < vi.size(); i++) last *= vi[i]; cout << last; } return 0; } |
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module i2s
(
// Clock & Reset
clk_i,
rst_i,
// PCM Data In (2x16-bit BE signed data)
pcm_data_i,
pcm_fifo_empty_i,
pcm_fifo_rd_o,
pcm_fifo_ur_o,
// I2S DAC Interface
bclk_o,
ws_o,
data_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_DIVISOR = 6;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input[31:0] pcm_data_i /*verilator public*/;
input pcm_fifo_empty_i /*verilator public*/;
output pcm_fifo_rd_o /*verilator public*/;
output pcm_fifo_ur_o /*verilator public*/;
output bclk_o /*verilator public*/;
output ws_o /*verilator public*/;
output data_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
// Data clock (generated)
reg audio_clock;
// Input clock divider (to generate audio_clock)
integer audio_clock_div;
// Input clock divider (to generate audio_clock)
integer bit_count;
// Word select
reg word_sel;
// Registered audio input data
reg [15:0] input_reg0;
reg [15:0] input_reg1;
// Last sample
reg [31:0] pcm_data_last;
reg prev_audio_clock;
reg pcm_fifo_rd_o;
reg pcm_fifo_ur_o;
reg bclk_o;
reg data_o;
//-----------------------------------------------------------------
// Bit Clock Generator
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
audio_clock_div <= 0;
audio_clock <= 1'b0;
end
else
begin
// Clock divider cycle_count matched?
if (audio_clock_div == (CLK_DIVISOR - 1))
begin
// Toggle clock
audio_clock <= ~audio_clock;
// Reset counter
audio_clock_div <= 0;
end
// Increment clock divider counter
else
audio_clock_div <= audio_clock_div + 1;
end
end
//-----------------------------------------------------------------
// I2S Output Generator
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
input_reg0 <= 16'h0000;
input_reg1 <= 16'h0000;
bit_count <= 0;
data_o <= 1'b0;
word_sel <= 1'b0;
prev_audio_clock<= 1'b0;
pcm_fifo_rd_o <= 1'b0;
pcm_fifo_ur_o <= 1'b0;
pcm_data_last <= 32'h00000000;
end
else
begin
pcm_fifo_rd_o <= 1'b0;
pcm_fifo_ur_o <= 1'b0;
// Update previous audio_clock value
prev_audio_clock <= audio_clock;
// CLK 1->0 - Falling Edge
if ((prev_audio_clock == 1'b1) && (audio_clock == 1'b0))
begin
bclk_o <= 1'b0;
// Cycle 0
if (bit_count == 0)
begin
// Output last bit (LSB)
if (word_sel == 1'b0)
data_o <= input_reg0[15];
// Output last bit (LSB)
else
data_o <= input_reg1[15];
// Toggle ws_o
word_sel <= ~word_sel;
// Increment cycle counter
bit_count <= bit_count + 1;
// Audio data ready?
if (pcm_fifo_empty_i == 1'b0)
begin
// Convert to big endian 16-bit left & right
pcm_data_last <= pcm_data_i;
input_reg0 <= pcm_data_i[31:16];
input_reg1 <= pcm_data_i[15:0];
pcm_fifo_rd_o <= 1'b1;
end
// Audio data buffer under run condition
else
begin
// Use previous data instead
input_reg0 <= pcm_data_last[31:16];
input_reg1 <= pcm_data_last[15:0];
pcm_fifo_ur_o <= 1'b1;
end
// Cycle 1 - 15
end
else
begin
if (word_sel == 1'b0)
begin
// Output MSB
data_o <= input_reg0[15];
// Shift data right
input_reg0 <= {input_reg0[14:0], 1'b0};
end
else
begin
// Output MSB
data_o <= input_reg1[15];
// Shift data right
input_reg1 <= {input_reg1[14:0], 1'b0};
end
if (bit_count == 15)
bit_count <= 0;
else
bit_count <= bit_count + 1;
end
end
// CLK 0->1 - Rising Edge
else if((prev_audio_clock == 1'b0) && (audio_clock == 1'b1))
bclk_o <= 1'b1;
end
end
//-----------------------------------------------------------------
// Combinatorial
//-----------------------------------------------------------------
assign ws_o = word_sel;
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[200000 + 10]; int arr2[200000 + 10]; int main() { int n, num1 = 0, num2 = 0, tem1, l1 = 0, l2 = 0, num = 0; long long ans = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> tem1; if (tem1 == 0) { ans += num; } else num++; } cout << ans; return 0; } |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
#include <bits/stdc++.h> const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const double eps = 1e-8; const int MAXN = 1e3 + 10; const int mod = 1e9 + 7; const int dir[][2] = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}}; const int seed = 131; int cases = 0; char str[MAXN]; int mp[MAXN], col[MAXN], cnt[30], vis[MAXN], need[MAXN], ans[MAXN]; std::vector<int> primes, fac[MAXN], f[MAXN]; std::priority_queue<std::pair<int, int> > num; std::vector<std::pair<int, int> > number_of_need; void init() { for (int i = 2; i < MAXN; i++) if (!vis[i]) for (int j = i; j < MAXN; j += i) { fac[j].push_back(i); if (j != i) vis[j] = 1; } for (int i = 2; i < MAXN; i++) if (!vis[i]) primes.push_back(i); } int find(int n) { return col[n] = n == col[n] ? n : find(col[n]); } int main() { init(); scanf( %s , str); int len = strlen(str); for (int i = 0; i < len; i++) cnt[str[i] - a ]++; for (int i = 0; i < 26; i++) if (cnt[i]) num.push({cnt[i], i}); for (int i = 2; i <= len; i++) { if ((int)fac[i].size() == 1) col[i] = i; else { int v = find(fac[i][0]); for (int j = 1; j < (int)fac[i].size(); j++) col[fac[i][j]] = v; } } for (int pri : primes) { if (pri > len) break; find(pri); } for (int i = 2; i <= len; i++) f[col[fac[i][0]]].push_back(i); for (int i = 2; i <= len; i++) if (!f[i].empty()) { if (num.empty() || num.top().first < (int)f[i].size()) { puts( NO ); return 0; } std::pair<int, int> u = num.top(); num.pop(); for (int j : f[i]) str[j] = char(u.second + a ); if (u.first - (int)f[i].size() > 0) num.push({u.first - (int)f[i].size(), u.second}); } if (num.empty()) { puts( NO ); return 0; } str[1] = char(num.top().second + a ); puts( YES ); printf( %s n , str + 1); return 0; } |
module ShowControl(clk, enhe, outcont, Reset, change, Z, Start, EN, creaenhe, Init, Shift, Ready, Cycend, rst, Beg, scrinit);
input clk, enhe, outcont, Reset, change, Z, Ready, Cycend;
output reg Start, EN, creaenhe, Init, Shift, rst, Beg;
output reg [2:0]scrinit;
reg [3:0] current_state;
reg [3:0] next_state;
parameter INITIAL1=4'b0000, INITIAL2=4'b0001,INITIAL3=4'b0010, INITIAL4=4'b0011, CLEARSCREEN=4'b0100, LOADCAD=4'b0101, CHECKCON=4'b0110, CREATESTATE=4'b0111, CHECKENHE=4'b1000, PRINTSCR=4'b1001, INITIAL5=4'b1010, INITIAL6=4'b1011, INITIAL7=4'b1100, PRIENHE=4'b1101, RESETSCREEN=4'b1110 ,RESETSTATE=4'b1111;
initial begin
current_state<=INITIAL1;
end
always @(enhe or outcont or Reset or change or Z or current_state or Ready or Cycend) begin
case(current_state)
INITIAL1: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b101;
if(~Ready) begin
EN=1;
next_state<=INITIAL1;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=INITIAL2;
end
else
next_state<=INITIAL1;
end
end
INITIAL2: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b101;
if(~Ready) begin
EN=1;
next_state<=INITIAL2;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=INITIAL3;
end
else
next_state<=INITIAL2;
end
end
INITIAL3: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b101;
if(~Ready) begin
EN=1;
next_state<=INITIAL3;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=INITIAL4;
end
else
next_state<=INITIAL3;
end
end
INITIAL4: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b001;
if(~Ready) begin
EN=1;
next_state<=INITIAL4;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=INITIAL5;
end
else
next_state<=INITIAL4;
end
end
INITIAL5: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b010;
if(~Ready) begin
EN=1;
next_state<=INITIAL5;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=INITIAL6;
end
else
next_state<=INITIAL5;
end
end
INITIAL6: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b011;
if(~Ready) begin
EN=1;
next_state<=INITIAL6;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=INITIAL7;
end
else
next_state<=INITIAL6;
end
end
INITIAL7: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b100;
if(~Ready) begin
EN=1;
next_state<=INITIAL7;
end
else begin
EN=0;
if(Cycend) begin
Beg=1;
next_state<=LOADCAD;
end
else
next_state<=INITIAL7;
end
end
LOADCAD: begin
Start=1;
EN=1;
creaenhe=0;
Init=1;
Shift=0;
rst=0;
Beg=1;
scrinit=3'b000;
if (Reset==1'b1)
next_state<=RESETSTATE;
else begin
if (change == 1'b1)
next_state<=CLEARSCREEN;
else
next_state<=LOADCAD;
end
end
CHECKCON: begin
Start=0;
EN=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=1;
scrinit=3'b000;
if (Reset==1'b1)
next_state<=RESETSTATE;
else begin
if (outcont == 1'b1)
next_state<=CHECKENHE;
else
next_state<=CREATESTATE;
end
end
CREATESTATE: begin
Start=0;
EN=1;
creaenhe=0;
Init=0;
Shift=1;
rst=0;
Beg=1;
scrinit=3'b000;
if (Reset==1'b1)
next_state<=RESETSTATE;
else begin
next_state<=CHECKCON;
end
end
CHECKENHE: begin
Start=0;
EN=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=1;
scrinit=3'b000;
if (Reset==1'b1)
next_state<=RESETSTATE;
else begin
if (enhe == 1'b0)
next_state<=PRINTSCR;
else
next_state<=PRIENHE;
end
end
PRIENHE: begin
Start=1;
creaenhe=1;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b110;
if (Reset==1'b1) begin
EN=1;
next_state<=RESETSTATE;
end
else begin
if(~Ready) begin
EN=1;
next_state<=PRIENHE;
end
else begin
EN=0;
if(Cycend) begin
if(Z)
next_state<=LOADCAD;
else
next_state<=CHECKCON;
end
else
next_state<=PRIENHE;
end
end
end
PRINTSCR: begin
Start=1;
creaenhe=0;
Init=0;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b110;
if (Reset==1'b1) begin
EN=1;
next_state<=RESETSTATE;
end
else begin
if(~Ready) begin
EN=1;
next_state<=PRINTSCR;
end
else begin
EN=0;
if(Cycend) begin
if(Z)
next_state<=LOADCAD;
else
next_state<=CHECKCON;
end
else
next_state<=PRINTSCR;
end
end
end
CLEARSCREEN: begin
Start=1;
creaenhe=0;
Init=1;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b000;
if (Reset==1'b1) begin
EN=1;
next_state<=RESETSTATE;
end
else begin
if(~Ready) begin
EN=1;
next_state<=CLEARSCREEN;
end
else begin
EN=0;
if(Cycend)
next_state<=CHECKCON;
else
next_state<=CLEARSCREEN;
end
end
end
RESETSTATE: begin
Start=0;
EN=1;
creaenhe=0;
Init=0;
Shift=0;
rst=1;
Beg=1;
scrinit=3'b000;
next_state<=RESETSCREEN;
end
RESETSCREEN: begin
Start=1;
creaenhe=0;
Init=1;
Shift=0;
rst=0;
Beg=0;
scrinit=3'b000;
if (Reset==1'b1) begin
EN=1;
next_state<=RESETSTATE;
end
else begin
if(~Ready) begin
EN=1;
next_state<=RESETSCREEN;
end
else begin
EN=0;
if(Cycend)
next_state<=LOADCAD;
else
next_state<=RESETSCREEN;
end
end
end
default begin
Start=0;
EN=0;
creaenhe=0;
Init=0;
Shift=0;
rst=1;
Beg=1;
scrinit=3'b000;
next_state<=RESETSTATE;
end
endcase
end
always @(posedge clk) begin
current_state<=next_state;
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_SUMHSQ_CHANNEL0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 23: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 23: 0] data_out;
wire [ 23: 0] out_port;
wire [ 23: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {24 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[23 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bg_low (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [10 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bg_low.mif"),
.C_INIT_FILE("bg_low.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(1092),
.C_READ_DEPTH_A(1092),
.C_ADDRA_WIDTH(11),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(1092),
.C_READ_DEPTH_B(1092),
.C_ADDRB_WIDTH(11),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5912999999999999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(11'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_gt_common.v
// Version : 3.0
`timescale 1ns / 1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_gt_common #(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "2.1", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
)
(
input CPLLPDREFCLK,
input PIPE_CLK,
input QPLL_QPLLPD,
input QPLL_QPLLRESET,
input QPLL_DRP_CLK,
input QPLL_DRP_RST_N,
input QPLL_DRP_OVRD,
input QPLL_DRP_GEN3,
input QPLL_DRP_START,
output [5:0] QPLL_DRP_CRSCODE,
output [8:0] QPLL_DRP_FSM,
output QPLL_DRP_DONE,
output QPLL_DRP_RESET,
output QPLL_QPLLLOCK,
output QPLL_QPLLOUTCLK,
output QPLL_QPLLOUTREFCLK
);
//---------- QPLL DRP Module Output --------------------
wire [7:0] qpll_drp_addr;
wire qpll_drp_en;
wire [15:0] qpll_drp_di;
wire qpll_drp_we;
//---------- QPLL Wrapper Output -----------------------
wire [15:0] qpll_drp_do;
wire qpll_drp_rdy;
//---------- QPLL Resets -----------------------
//---------- QPLL DRP Module ---------------------------------------
pcie_7x_0_core_top_qpll_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_drp_i
(
//---------- Input -------------------------
.DRP_CLK (QPLL_DRP_CLK),
.DRP_RST_N (!QPLL_DRP_RST_N),
.DRP_OVRD (QPLL_DRP_OVRD),
.DRP_GEN3 (&QPLL_DRP_GEN3),
.DRP_QPLLLOCK (QPLL_QPLLLOCK),
.DRP_START (QPLL_DRP_START),
.DRP_DO (qpll_drp_do),
.DRP_RDY (qpll_drp_rdy),
//---------- Output ------------------------
.DRP_ADDR (qpll_drp_addr),
.DRP_EN (qpll_drp_en),
.DRP_DI (qpll_drp_di),
.DRP_WE (qpll_drp_we),
.DRP_DONE (QPLL_DRP_DONE),
.DRP_QPLLRESET (QPLL_DRP_RESET),
.DRP_CRSCODE (QPLL_DRP_CRSCODE),
.DRP_FSM (QPLL_DRP_FSM)
);
//---------- QPLL Wrapper ------------------------------------------
pcie_7x_0_core_top_qpll_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_wrapper_i
(
//---------- QPLL Clock Ports --------------
.QPLL_CPLLPDREFCLK (CPLLPDREFCLK),
.QPLL_GTGREFCLK (PIPE_CLK),
.QPLL_QPLLLOCKDETCLK (1'd0),
.QPLL_QPLLOUTCLK (QPLL_QPLLOUTCLK),
.QPLL_QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK),
.QPLL_QPLLLOCK (QPLL_QPLLLOCK),
//---------- QPLL Reset Ports --------------
.QPLL_QPLLPD (QPLL_QPLLPD),
.QPLL_QPLLRESET (QPLL_QPLLRESET),
//---------- QPLL DRP Ports ----------------
.QPLL_DRPCLK (QPLL_DRP_CLK),
.QPLL_DRPADDR (qpll_drp_addr),
.QPLL_DRPEN (qpll_drp_en),
.QPLL_DRPDI (qpll_drp_di),
.QPLL_DRPWE (qpll_drp_we),
.QPLL_DRPDO (qpll_drp_do),
.QPLL_DRPRDY (qpll_drp_rdy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long H; int N, M, K; long long A[100002], C[100002]; long long add[100002]; bool can[100002]; long long minget[10002]; set<pair<long long, int> > Q; set<pair<int, int>, greater<pair<int, int> > > S; int main() { cin.sync_with_stdio(false); cin >> H >> N >> M >> K; for (int i = 0; i < K; ++i) minget[i] = 1LL << 62; minget[0] = 0; for (int i = 1; i <= N; ++i) { cin >> C[i] >> A[i]; --C[i]; if (minget[C[i] % K] <= C[i]) { S.insert(make_pair(A[i], -i)); can[i] = true; } } for (int i = 1, type; i <= M; ++i) { cin >> type; if (type == 1) { long long val; cin >> val; add[++add[0]] = val; for (int j = 0; j < K; ++j) minget[j] = 1LL << 62; minget[0] = 0; Q.insert(make_pair(0, 0)); while (!Q.empty()) { int now = (*Q.begin()).second; Q.erase(Q.begin()); for (int j = 1; j <= add[0]; ++j) if (minget[(now + add[j]) % K] > minget[now] + add[j]) { minget[(now + add[j]) % K] = minget[now] + add[j]; Q.insert(make_pair(minget[(now + add[j]) % K], (now + add[j]) % K)); } } for (int j = 1; j <= N; ++j) if (!can[j] && minget[C[j] % K] <= C[j]) { S.insert(make_pair(A[j], -j)); can[j] = true; } } else if (type == 2) { int pos, val; cin >> pos >> val; if (!can[pos]) A[pos] -= val; else { S.erase(S.find(make_pair(A[pos], -pos))); A[pos] -= val; S.insert(make_pair(A[pos], -pos)); } } else if (type == 3) { if (S.empty()) { cout << 0 << n ; continue; } cout << (*S.begin()).first << n ; A[-(*S.begin()).second] = 0; S.erase(S.begin()); } } } |
// The shader asserts row lines for a length of time that is proportional
// to the intensity value stored in the values vector.
// Synchronous active low reset.
module shader(input clk,
input rst_n,
input [(32*5-1):0] values,
output reg [31:0] rows
);
reg [4:0] n;
always @(posedge clk) begin
if (!rst_n)
n = 0;
// icarus verilog doesn't implement the generate statement.
`define pulse(i) rows[i] = n < values[4+(5*i):(5*i)]
`pulse(0);
`pulse(1);
`pulse(2);
`pulse(3);
`pulse(4);
`pulse(5);
`pulse(6);
`pulse(7);
`pulse(8);
`pulse(9);
`pulse(10);
`pulse(11);
`pulse(12);
`pulse(13);
`pulse(14);
`pulse(15);
`pulse(16);
`pulse(17);
`pulse(18);
`pulse(19);
`pulse(20);
`pulse(21);
`pulse(22);
`pulse(23);
`pulse(24);
`pulse(25);
`pulse(26);
`pulse(27);
`pulse(28);
`pulse(29);
`pulse(30);
`pulse(31);
n = n+1;
end
endmodule // line
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; const int mod = 1e9 + 7; const long long inf = 1e17; char a[maxn], b[maxn], s[maxn]; int v[200]; int main() { int q; scanf( %s%s , a, b); int n = strlen(a); for (int i = 0; i < n; ++i) v[a[i]] = 1; n = strlen(b); scanf( %d , &q); while (q--) { scanf( %s , s); int len = strlen(s); int o = len - n + 1; if (o < 0) { puts( NO ); continue; } int i = 0, j = 0, k; while (i < n) { if (b[i] == s[j]) { i++; j++; } else if (b[i] == ? && v[s[j]]) { i++; j++; } else if (b[i] == * ) { for (k = 0; k < o && j < len; ++k, ++j) if (v[s[j]]) break; if (k < o) break; i++; } else { break; } } if (i < n || j < len) puts( NO ); else puts( YES ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; vector<int> g[2 * N]; vector<pair<int, int> > mark[N]; int n, m; long long val[N]; struct Bit { long long c[N]; int lowbit(int x) { return x & -x; } long long Sum(int x) { long long res = 0; while (x > 0) { res += c[x]; x -= lowbit(x); } return res; } void Add(int x, int d) { while (x <= n) { c[x] += d; x += lowbit(x); } } } b; void dfs(int u, int fa, int dep) { for (auto it : mark[u]) { b.Add(max(n - dep - it.first, 1), it.second); } val[u] = b.Sum(max(n - dep, 1)); for (auto v : g[u]) { if (v == fa) continue; dfs(v, u, dep + 1); } for (auto it : mark[u]) { b.Add(max(n - dep - it.first, 1), -it.second); } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y; scanf( %d %d , &x, &y); g[x].push_back(y); g[y].push_back(x); } scanf( %d , &m); for (int i = 1; i <= m; i++) { int u, d, x; scanf( %d %d %d , &u, &d, &x); mark[u].push_back({d, x}); } dfs(1, 0, 0); for (int i = 1; i <= n; i++) { printf( %lld , val[i]); } } |
#include <bits/stdc++.h> using namespace std; int pro(int *a, int *b, int t, int s) { int k = 0; for (int i = 1; i < t; i++) { if (b[i] != s) { return 2; } if (b[i] == 0) { k++; } } if (k == (t - 1)) { return 3; } return 1; } int main() { int t, a[105], b[105]; a[0] = 0; cin >> t; for (int i = 1; i <= t; i++) { cin >> a[i]; b[i - 1] = a[i] - a[i - 1]; } if (t == 1) { cout << a[1]; } int c = pro(a, b, t, b[1]); if (c == 3) { cout << a[1]; } else if (c == 1) { cout << a[t] + b[1]; } else { cout << a[t]; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, m, tren, pos[N], cnt[N]; vector<int> g[N]; int dist(int a, int tr) { if (a > tr) return a - tr; else return n + a - tr; } bool cmp(int a, int b) { if (dist(a, tren) < dist(b, tren)) return true; return false; } int next(int i) { if (i < n) return i + 1; return 1; } int check(int i) { int num = 0, curr = i, time = 0; while (num < m) { if (cnt[curr]) { num += cnt[curr]; cnt[curr] = 0; } if (pos[curr] >= 0) { cnt[g[curr][pos[curr]]]++; pos[curr]--; } curr = next(curr); time++; } return time - 1; } int main() { scanf( %d , &n); scanf( %d , &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); } for (int i = 1; i <= n; i++) { tren = i; sort(g[i].begin(), g[i].end(), cmp); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cnt[j] = 0; pos[j] = g[j].size() - 1; } printf( %d , check(i)); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:28:59 05/19/2015
// Design Name: cpu_behav
// Module Name: C:/Users/joseph/Desktop/SPRAM/test_cpu.v
// Project Name: SPRAM
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cpu_behav
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cpu;
// Inputs
reg clk;
reg rst;
// Outputs
wire [15:0] prog_cnt;
wire [15:0] reg0;
// Instantiate the Unit Under Test (UUT)
cpu_behav uut (
.prog_cnt(prog_cnt),
.reg0(reg0),
.clk(clk),
.rst(rst)
);
always begin
clk = 1;
#10;
clk = 0;
#10;
$display($time,,,"Program Counter %d, Reg0: %d\n", prog_cnt, $signed(reg0));
end
initial begin
// Initialize Inputs
rst = 0;
#90 rst = 1;
#5 $display($time,,,"Reset Is Asserted\n");
// Add stimulus here
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 14:43:38 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_3_stub.v
// Design : zqynq_lab_1_design_auto_pc_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const double eps = 1e-9; const int maxn = 100000 + 10; int go[maxn][26], fail[maxn]; int I[maxn], F[maxn], S[maxn], FIN[maxn]; int total; void push(string &s, int index, int freq) { int u = 0; for (auto c : s) { int x = c - a ; if (!go[u][x]) go[u][x] = total++; u = go[u][x]; } I[u] = index, F[u] = freq, S[u] = s.length(), FIN[u] = u; } void build() { queue<pair<int, int> > q; for (int i = 0; i < 26; ++i) { if (go[0][i]) q.push({go[0][i], 0}); } while (!q.empty()) { auto x = q.front(); q.pop(); int u = x.first, f = x.second; fail[u] = f; if (!FIN[u]) FIN[u] = FIN[f]; for (int i = 0; i < 26; ++i) { if (go[u][i]) q.push({go[u][i], go[f][i]}); else go[u][i] = go[f][i]; } } } int ANSWER[maxn]; queue<int> deq[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); total = 1; string s; cin >> s; int q; cin >> q; for (int i = 1; i <= q; ++i) { int f; string t; cin >> f >> t; push(t, i, f); } build(); memset(ANSWER, 0x3f, sizeof ANSWER); for (int i = 0, u = 0; i < (int)s.length(); ++i) { u = go[u][s[i] - a ]; int v = FIN[u]; while (v) { int idx = I[v]; deq[idx].push(i); if (deq[idx].size() > F[v]) deq[idx].pop(); if (deq[idx].size() == F[v]) { int beg = deq[idx].front(); ANSWER[idx] = min(ANSWER[idx], i - beg + S[v]); } v = FIN[fail[v]]; } } for (int i = 1; i <= q; ++i) { if (ANSWER[i] == oo) cout << -1 << n ; else cout << ANSWER[i] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( unroll-loops ) #pragma GCC optimize( O2 ) constexpr int dx[] = {-1, 0, 1, 0, 1, 1, -1, -1}; constexpr int dy[] = {0, -1, 0, 1, 1, -1, 1, -1}; constexpr long long INF = 1999999999999999997; constexpr int inf = INT_MAX; constexpr int MAXSIZE = int(1e6) + 5; constexpr auto PI = 3.14159265358979323846L; constexpr auto oo = numeric_limits<int>::max() / 2 - 2; constexpr auto eps = 1e-6; constexpr auto mod = 1000000007; constexpr auto MOD = 1000000007; constexpr auto MOD9 = 1000000009; constexpr auto maxn = 100006; template <typename T, size_t N> int SIZE(const T (&t)[N]) { return N; } template <typename T> int SIZE(const T &t) { return t.size(); } string to_string(string s, int x1 = 0, int x2 = 1e9) { return + ((x1 < s.size()) ? s.substr(x1, x2 - x1 + 1) : ) + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(char c) { return string({c}); } template <size_t N> string to_string(bitset<N> &b, int x1 = 0, int x2 = 1e9) { string t = ; for (int __iii__ = min(x1, SIZE(b)), __jjj__ = min(x2, SIZE(b) - 1); __iii__ <= __jjj__; ++__iii__) { t += b[__iii__] + 0 ; } return + t + ; } template <typename A, typename... C> string to_string(A(&v), int x1 = 0, int x2 = 1e9, C... coords); int l_v_l_v_l = 0, t_a_b_s = 0; template <typename A, typename B> string to_string(pair<A, B> &p) { l_v_l_v_l++; string res = ( + to_string(p.first) + , + to_string(p.second) + ) ; l_v_l_v_l--; return res; } template <typename A, typename... C> string to_string(A(&v), int x1, int x2, C... coords) { int rnk = rank<A>::value; string tab(t_a_b_s, ); string res = ; bool first = true; if (l_v_l_v_l == 0) res += n ; res += tab + [ ; x1 = min(x1, SIZE(v)), x2 = min(x2, SIZE(v)); auto l = begin(v); advance(l, x1); auto r = l; advance(r, (x2 - x1) + (x2 < SIZE(v))); for (auto e = l; e != r; e = next(e)) { if (!first) { res += , ; } first = false; l_v_l_v_l++; if (e != l) { if (rnk > 1) { res += n ; t_a_b_s = l_v_l_v_l; }; } else { t_a_b_s = 0; } res += to_string(*e, coords...); l_v_l_v_l--; } res += ] ; if (l_v_l_v_l == 0) res += n ; return res; } void dbgs() { ; } template <typename Heads, typename... Tails> void dbgs(Heads H, Tails... T) { cout << to_string(H) << | ; dbgs(T...); } int main() { int n, d; cin >> n >> d; int m; cin >> m; while (m--) { int x, y; cin >> x >> y; if (x + y - d >= 0 && y + x - 2 * n + d <= 0 && y - x - d <= 0 && x - y - d <= 0) cout << YES << n ; else { cout << NO << n ; } } } |
module v7_emac_controller
(
// asynchronous reset
input glbl_rst,
// 200MHz clock input from board
input clkin200,
output phy_resetn,
//added SGMII serial data and reference clock ports
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// MDIO Interface
//---------------
input mdio_i,
output mdio_o,
output mdio_t,
output mdc,
// Receiver (AXI-S) Interface
//----------------------------------------
output rx_fifo_clk,
output rx_fifo_rstn,
output [7:0] rx_axis_fifo_tdata,
output rx_axis_fifo_tvalid,
input rx_axis_fifo_tready,
output rx_axis_fifo_tlast,
// Transmitter (AXI-S) Interface
//-------------------------------------------
output tx_fifo_clk,
output tx_fifo_rstn,
input [7:0] tx_axis_fifo_tdata,
input tx_axis_fifo_tvalid,
output tx_axis_fifo_tready,
input tx_axis_fifo_tlast,
input loop_back_en,
output o_tx_mac_count
);
endmodule |
/*
** Copyright (C) 2009 Onno Kortmann <>
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
**
*/
/* SPI slave Verilog example code. */
`timescale 1ns / 1ns
module SPIfrontend(nCS, CLK, MOSI, MISO,
inbyte, outbyte, out_valid);
input nCS;
input CLK;
input MOSI;
output MISO;
reg MISO;
input [7:0] inbyte;
output [7:0] outbyte;
reg [7:0] outbyte;
output out_valid;
reg [2:0] bitcnt;
assign out_valid = bitcnt==0;
always @(posedge nCS) begin // 'reset' condition
bitcnt<=0;
outbyte<=0;
end
always @(posedge CLK) if (!nCS) begin
MISO<=inbyte[bitcnt];
end // always @ (posedge CLK)
always @(negedge CLK) if (!nCS) begin
if (bitcnt)
outbyte[bitcnt]<=MOSI;
else
outbyte<=MOSI;
bitcnt<=bitcnt+1;
end
endmodule // SPIfrontend
module SPIslave(nCS, CLK, MOSI, MISO);
input nCS;
input CLK;
input MOSI;
output MISO;
reg [7:0] inbyte;
wire [7:0] outbyte;
wire out_valid;
reg [7:0] mem[0:65535];
reg [3:0] state;
reg [15:0] adr;
SPIfrontend front(nCS, CLK, MOSI, MISO,
inbyte, outbyte, out_valid);
always @(posedge nCS) begin
state<=0;
end
always @(posedge out_valid) if (!nCS) begin
$display("Received %d", outbyte);
case (state)
0: begin
adr[7:0]<=outbyte; state<=1;
end
1: begin
adr[15:8]<=outbyte; state<=2;
end
2: begin
if (outbyte) begin
state<=3;
end else begin
$display("Reading location 0x%x, which contains 0x%x", adr, mem[adr]);
inbyte<=mem[adr];
state<=4;
end
end
3: begin
mem[adr]<=outbyte;
$display("Writing location 0x%x with 0x%x", adr, outbyte);
state<=0;
end
4: begin
state<=0; // dummy state, this could be interleaved for more performance when reading
end
endcase // case(state)
end
endmodule
module test;
reg CLK;
wire nCS, SCK, MOSI;
wire MISO;
SPIslave sl(nCS, SCK, MOSI, MISO);
wire [7:0] pb;
wire [7:0] pc;
wire [7:0] pd;
assign MISO=pb[4];
assign MOSI=pb[3];
assign SCK=pb[5];
assign nCS=pb[2];
defparam avr.progfile="spi.elf";
ATmega8 avr(CLK, pb, pc, pd);
initial begin
$avr_trace("avr.trace");
$dumpfile("spi.vcd");
$dumpvars(0, test);
# $finish;
end // initial begin
always begin
#100 CLK<=0;
#100 CLK<=1;
end
endmodule
|
`timescale 1ns/1ps
module match(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
metadata_valid,
metadata,
action_valid,
action,
action_data_valid,
action_data
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output [31:0] localbus_data_out;
input metadata_valid;
input [107:0] metadata;
output action_valid;
output[15:0] action;
output action_data_valid;
output[351:0] action_data;
wire action_valid;
wire [15:0] action;
wire action_data_valid;
wire [351:0] action_data;
reg localbus_ack_n;
reg [31:0] localbus_data_out;
//---//
wire search_1_bv_valid,search_2_bv_valid,search_3_bv_valid,search_4_bv_valid;
wire [35:0] search_1_bv,search_2_bv,search_3_bv,search_4_bv;
//--reg--//
//reg localbus_cs_n_1,localbus_cs_n_2,localbus_cs_n_3,localbus_cs_n_4,localbus_cs_n_5;
reg localbus_ale_1,localbus_ale_2,localbus_ale_3,localbus_ale_4,localbus_ale_5;
wire localbus_ack_n_1,localbus_ack_n_2,localbus_ack_n_3,localbus_ack_n_4,localbus_ack_n_5;
wire [31:0] localbus_data_out_1,localbus_data_out_2,localbus_data_out_3,localbus_data_out_4,localbus_data_out_5;
//--state--//
reg [3:0] set_state;
parameter idle = 4'd0,
set_wait = 4'd1,
wait_back = 4'd3;
//---------------------------set_state--------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
localbus_data_out <= 32'b0;
localbus_ale_1 <= 1'b0;
localbus_ale_2 <= 1'b0;
localbus_ale_3 <= 1'b0;
localbus_ale_4 <= 1'b0;
localbus_ale_5 <= 1'b0;
localbus_ack_n <= 1'b1;
end
else
begin
case(set_state)
idle:
begin
if((localbus_ale == 1'b1) && (localbus_data[23] == 1'b0))
begin
case(localbus_data[19:16])
4'd0: localbus_ale_1 <= localbus_ale;
4'd1: localbus_ale_2 <= localbus_ale;
4'd2: localbus_ale_3 <= localbus_ale;
4'd3: localbus_ale_4 <= localbus_ale;
4'd4: localbus_ale_5 <= localbus_ale;
default: localbus_ale_5 <= localbus_ale;
endcase
set_state <= set_wait;
end
end
set_wait:
begin
localbus_ale_1 <= 1'b0;localbus_ale_2 <= 1'b0;localbus_ale_3 <= 1'b0;
localbus_ale_4 <= 1'b0;localbus_ale_5 <= 1'b0;
if((localbus_ack_n_1 == 1'b0) || (localbus_ack_n_2 == 1'b0) ||(localbus_ack_n_3 == 1'b0) ||
(localbus_ack_n_4 == 1'b0) ||(localbus_ack_n_5 == 1'b0))
begin
localbus_ack_n <= 1'b0;
set_state <= wait_back;
case({localbus_ack_n_1,localbus_ack_n_2,localbus_ack_n_3,
localbus_ack_n_4,localbus_ack_n_5})
5'b01111: localbus_data_out <= localbus_data_out_1;
5'b10111: localbus_data_out <= localbus_data_out_2;
5'b11011: localbus_data_out <= localbus_data_out_3;
5'b11101: localbus_data_out <= localbus_data_out_4;
5'b11110: localbus_data_out <= localbus_data_out_5;
default:
begin
localbus_data_out <= localbus_data_out_5;
end
endcase
end
end
wait_back:
begin
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
//---search_engine_1---//
search_engine search_engine_1(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[107:81]),
.bv_valid(search_1_bv_valid),
.bv(search_1_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_1),
.localbus_ack_n(localbus_ack_n_1),
.localbus_data_out(localbus_data_out_1)
);
//---search_engine_2---//
search_engine search_engine_2(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[80:54]),
.bv_valid(search_2_bv_valid),
.bv(search_2_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_2),
.localbus_ack_n(localbus_ack_n_2),
.localbus_data_out(localbus_data_out_2)
);
//---search_engine_3---//
search_engine search_engine_3(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[53:27]),
.bv_valid(search_3_bv_valid),
.bv(search_3_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_3),
.localbus_ack_n(localbus_ack_n_3),
.localbus_data_out(localbus_data_out_3)
);
//---search_engine_4---//
search_engine search_engine_4(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[26:0]),
.bv_valid(search_4_bv_valid),
.bv(search_4_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_4),
.localbus_ack_n(localbus_ack_n_4),
.localbus_data_out(localbus_data_out_4)
);
//----lookup_rule---//
lookup_rule lk_rule(
.clk(clk),
.reset(reset),
.bv_valid_1(search_1_bv_valid),
.bv_1(search_1_bv),
.bv_valid_2(search_2_bv_valid),
.bv_2(search_2_bv),
.bv_valid_3(search_3_bv_valid),
.bv_3(search_3_bv),
.bv_valid_4(search_4_bv_valid),
.bv_4(search_4_bv),
.action_valid(action_valid),
.action(action),
.action_data_valid(action_data_valid),
.action_data(action_data),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_5),
.localbus_ack_n(localbus_ack_n_5),
.localbus_data_out(localbus_data_out_5)
);
endmodule |
#include <bits/stdc++.h> using namespace std; long long a[2000000]; int main() { long long n, t, i; cin >> n; for (i = 0; i < n; i++) { scanf( %lld , &a[i]); } cin >> t; for (i = 0; i < t; i++) { long long x; scanf( %lld , &x); a[x - 1] = -a[x - 1]; } stack<long long> st; for (i = n - 1; i >= 0; i--) { if (a[i] < 0) { st.push(a[i]); } else { if (st.empty() || st.top() != -a[i]) { st.push(-a[i]); a[i] = -a[i]; } else { st.pop(); } } } if (st.empty()) { cout << YES n ; for (i = 0; i < n; i++) printf( %lld , a[i]); } else cout << NO n ; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
interface intf;
typedef logic [7:0] octet;
typedef octet [1:0] word;
octet [1:0] octets;
word [1:0] words;
endinterface
module t;
typedef logic [3:0] mc_t;
typedef mc_t tocast_t;
typedef logic [2:0] [7:0] two_dee_t;
typedef struct packed {
logic [15:0] data;
} packed_t;
typedef struct packed {
logic [31:0] data;
} packed2_t;
typedef enum [15:0] {
ONE = 1
} enum_t;
packed_t pdata;
packed_t pdata_reg;
packed2_t pdata2_reg;
assign pdata.data = 16'h1234;
logic [7:0] logic8bit;
assign logic8bit = $bits(logic8bit)'(pdata >> 8);
mc_t o;
enum_t e;
intf the_intf();
logic [15:0] allones = 16'hffff;
parameter FOUR = 4;
localparam two_dee_t two_dee = two_dee_t'(32'habcdef);
// bug925
localparam [6:0] RESULT = 7'((6*9+92)%96);
logic signed [14:0] samp0 = 15'h0000;
logic signed [14:0] samp1 = 15'h0000;
logic signed [14:0] samp2 = 15'h6000;
logic signed [11:0] coeff0 = 12'h009;
logic signed [11:0] coeff1 = 12'h280;
logic signed [11:0] coeff2 = 12'h4C5;
logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11));
// verilator lint_off WIDTH
logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
// verilator lint_on WIDTH
logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
(27'(coeff1 * samp1) >>> 11) +
(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
logic one = 1'b1;
logic [32:0] b33 = {32'(0), one};
logic [31:0] b32 = {31'(0), one};
logic [31:0] thirty_two_bits;
two_dee_t two_dee_sig;
initial begin
if (logic8bit != 8'h12) $stop;
if (4'shf > 4'sh0) $stop;
if (signed'(4'hf) > 4'sh0) $stop;
if (4'hf < 4'h0) $stop;
if (unsigned'(4'shf) < 4'h0) $stop;
if (const'(4'shf) !== 4'shf) $stop;
if (4'(allones) !== 4'hf) $stop;
if (6'(allones) !== 6'h3f) $stop;
if ((4)'(allones) !== 4'hf) $stop;
if ((4+2)'(allones) !== 6'h3f) $stop;
if ((4-2)'(allones) !== 2'h3) $stop;
if ((FOUR+2)'(allones) !== 6'h3f) $stop;
if (50 !== RESULT) $stop;
e = ONE;
if (e != 1) $stop;
if (e != ONE) $stop;
e = enum_t'(ONE);
if (e != ONE) $stop;
e = enum_t'(16'h1);
if (e != ONE) $stop;
pdata_reg.data = 1;
e = enum_t'(pdata_reg);
if (e != ONE) $stop;
o = tocast_t'(4'b1);
if (o != 4'b1) $stop;
the_intf.octets = 16'd1;
pdata_reg = packed_t'(the_intf.octets);
if (pdata_reg.data != 16'd1) $stop;
the_intf.words = 32'd1;
pdata2_reg = packed2_t'(the_intf.words);
if (pdata2_reg.data != 32'd1) $stop;
if (15'h6cec != outa) $stop;
if (27'h7ffecec != mida) $stop;
if (27'h7ffecec != midb) $stop;
if (b33 != 33'b1) $stop;
if (b32 != 32'b1) $stop;
if (two_dee[0] != 8'hef) $stop;
if (two_dee[1] != 8'hcd) $stop;
if (two_dee[2] != 8'hab) $stop;
thirty_two_bits = 32'h123456;
two_dee_sig = two_dee_t'(thirty_two_bits);
if (two_dee_sig[0] != 8'h56) $stop;
if (two_dee_sig[1] != 8'h34) $stop;
if (two_dee_sig[2] != 8'h12) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int inf = 1e9; int main() { int n, m; cin >> n >> m; vector<int> d(m), h(m); for (int i = 0; i < m; ++i) { cin >> d[i] >> h[i]; } int ans = max(h[0] + d[0] - 1, h.back() + (n - d.back())); for (int i = 0; i + 1 < m; ++i) { if (abs(h[i] - h[i + 1]) > d[i + 1] - d[i]) { ans = -1; break; } ans = max(ans, (d[i + 1] - d[i] - abs(h[i] - h[i + 1])) / 2 + max(h[i], h[i + 1])); } if (ans == -1) { cout << IMPOSSIBLE << endl; } else { cout << ans << endl; } } |
`timescale 1ns/10ps
module ROMMatrixSim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire out;
wire testrom_data_o;
wire [15:0] rommatrix_rom_addr;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`ROMMatrix_LDR,8'h02};
inst_en = 1;
#4 inst = {`ROMMatrix_LDC,8'h02};
inst_en = 1;
#4 inst = {`ROMMatrix_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`ROMMatrix_LDR,8'h0A};
inst_en = 0;
#4 inst = {`ROMMatrix_LDC,8'h01};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'h10};
inst_en = 1;
#4 inst = {`ROMMatrix_LDR,8'h0B};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`ROMMatrix_LDR,8'h03};
inst_en = 1;
#4 inst = {`ROMMatrix_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test reading from improper address.
#4 inst = {`ROMMatrix_LDR,8'h32};
inst_en = 1;
#4 inst = {`ROMMatrix_LDC,8'h34};
inst_en = 1;
#4 inst = {`ROMMatrix_NOP,8'bxxxxxxxx};
inst_en = 1;
end
ROMMatrixTestROM
testrom (.addr(rommatrix_rom_addr),
.data_o(testrom_data_o));
ROMMatrix #(.ROMRows(16),
.ROMCols(4),
.ROMDataSize(1))
rommatrix (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out(out),
.rom_addr(rommatrix_rom_addr),
.rom_data_o(testrom_data_o));
endmodule // ROMMatrixSim
|
#include <bits/stdc++.h> using namespace std; template <class T> using VV = vector<vector<T>>; template <class T> inline T SMIN(T& a, const T b) { return a = (a > b) ? b : a; } template <class T> inline T SMAX(T& a, const T b) { return a = (a < b) ? b : a; } template <class Iter> void dumpc(Iter begin, Iter end) { if (false) { for (; begin != end; ++begin) { cerr << *begin << , ; } cerr << endl; } } int Q; map<int, int> comp; int getid(int a) { if (comp.count(a)) return comp[a]; comp[a] = int((comp).size()); return comp[a]; } struct UF { public: int groupNum; vector<int> X; UF(int N) { uf = vector<int>(N); rank = vector<int>(N); X = vector<int>(N); for (int i = 0; i < N; ++i) uf[i] = i, rank[i] = 0; groupNum = N; } pair<int, int> find(int v) { int cur = 0; while (uf[v] != v) { cur ^= X[v]; v = uf[v]; } return {v, cur}; } bool same(int x, int y) { return find(x) == find(y); } void unite(int x, int y, int z) { auto px = find(x); auto py = find(y); if (px.first == py.first) return; groupNum--; x = px.first, y = py.first; z = px.second ^ py.second ^ z; if (rank[x] == rank[y]) { uf[x] = y; X[x] = z; rank[y]++; return; } if (rank[x] < rank[y]) { uf[x] = y; X[x] = z; } else { uf[y] = x; X[y] = z; if (rank[x] == rank[y]) ++rank[x]; } } private: vector<int> rank; vector<int> uf; }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> Q; UF uf(2 * Q + 10); int last = 0; while (Q--) { int t, l, r; cin >> t >> l >> r; l ^= last, r ^= last; if (l > r) swap(l, r); ++r; if (false) { cerr << l << = << (l) << , << r << = << (r) << , << getid(l) << = << (getid(l)) << , << getid(r) << = << (getid(r)) << endl; }; l = getid(l), r = getid(r); if (t == 1) { int x; cin >> x; x ^= last; uf.unite(l, r, x); } else { pair<int, int> p1 = uf.find(l), p2 = uf.find(r); if (false) { cerr << p1.first << = << (p1.first) << , << p2.first << = << (p2.first) << endl; }; if (p1.first != p2.first) { last = 1; fprintf(stdout, %d , -1), putchar( n ); ; } else { if (false) { cerr << Q << = << (Q) << , << p1.second << = << (p1.second) << , << p2.second << = << (p2.second) << endl; }; last = p1.second ^ p2.second; fprintf(stdout, %d , last), putchar( n ); ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; bool visited[10000]; int main() { ios::sync_with_stdio(false); ios_base::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); string input; int counter; while (cin >> input) { counter = 0; for (int i = 0; i < input.size() - 1; i++) if (input[i] == V && input[i + 1] == K ) counter++, visited[i] = visited[i + 1] = 1, i++; for (int i = 0; i < input.size() - 1; i++) if (!visited[i] && !visited[i + 1]) if ((input[i] == V && input[i + 1] == V ) || ((input[i] == K && input[i + 1] == K ))) { counter++; break; } } cout << counter << endl; return 0; } |
module membusif(
input wire clk,
input wire reset,
// Avalon Slave
input wire [1:0] s_address,
input wire s_write,
input wire s_read,
input wire [31:0] s_writedata,
output reg [31:0] s_readdata,
output wire s_waitrequest,
// Membus Master
output reg m_rq_cyc,
output reg m_rd_rq,
output reg m_wr_rq,
output wire [21:35] m_ma,
output wire [18:21] m_sel,
output reg m_fmc_select,
output wire [0:35] m_mb_write,
output wire m_wr_rs,
input wire [0:35] m_mb_read,
input wire m_addr_ack,
input wire m_rd_rs
);
reg [0:17] addr;
reg [0:35] word;
assign m_ma = addr[3:17];
assign m_sel = addr[0:3];
wire write_edge, read_edge;
edgedet e0(clk, reset, s_write, write_edge);
edgedet e1(clk, reset, s_read, read_edge);
reg waiting;
wire req = (write_edge|read_edge) & s_address == 2'h2;
assign s_waitrequest = req | waiting | (|waitcyc);
wire mb_write_pulse;
wire wr_rs = m_addr_ack & m_wr_rq;
bd mc_bd0(clk, ~reset, wr_rs, m_wr_rs);
bd2 mb_bd1(clk, ~reset, wr_rs, mb_write_pulse);
assign m_mb_write = mb_write_pulse ? word : 0;
reg [7:0] waitcyc;
always @(posedge clk or negedge reset) begin
if(~reset) begin
m_rq_cyc <= 0;
m_rd_rq <= 0;
m_wr_rq <= 0;
waiting <= 0;
addr <= 0;
m_fmc_select <= 0;
word <= 0;
waitcyc <= 0;
end else begin
if(write_edge) begin
case(s_address)
2'h0: begin
addr <= s_writedata[17:0];
m_fmc_select <= s_writedata[18];
end
2'h1: word[18:35] <= s_writedata[17:0];
2'h2: word[0:17] <= s_writedata[17:0];
endcase
end
if(req) begin
waiting <= 1;
m_rq_cyc <= 1;
if(s_write)
m_wr_rq <= 1;
else if(s_read) begin
m_rd_rq <= 1;
word <= 0;
end
end
// have to wait between cycles
// because fastmem can get stuck
if(waitcyc) begin
if(waitcyc == 'o14)
waitcyc <= 0;
else
waitcyc <= waitcyc + 1;
end
if(waiting & m_rd_rq)
word <= m_mb_read;
if(m_addr_ack) begin
m_rq_cyc <= 0;
waitcyc <= 1;
end
if(m_rd_rs) begin
m_rd_rq <= 0;
waiting <= 0;
end
if(m_wr_rs) begin
m_wr_rq <= 0;
waiting <= 0;
end
end
end
always @(*) begin
case(s_address)
2'h1: s_readdata <= { 14'b0, word[18:35] };
2'h2: s_readdata <= { 14'b0, word[0:17] };
default: s_readdata <= 32'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int par[200010]; bool isLeaf[200010]; vector<int> adj[200010]; long long f[200010], dp[200010], s[200010], ans = 0, n; void duyet(int u) { s[u] = 1; f[u] = 0; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (par[u] != v) { par[v] = u; duyet(v); s[u] += s[v]; f[u] += f[v]; } } f[u] += s[u]; } void cal(int u) { long long tong = 0; dp[u] = dp[par[u]] - 2 * s[u] + n; ans = max(ans, dp[u]); for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (par[u] != v) { cal(v); } } } void solve() { cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; par[i] = 0; adj[x].push_back(y); adj[y].push_back(x); } par[n] = 0; duyet(1); dp[1] = f[1]; for (int i = 0; i < adj[1].size(); i++) { int v = adj[1][i]; cal(v); } cout << ans << endl; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; struct square { int r1, c1, r2, c2; square(int R1, int C1, int R2, int C2) { r1 = R1; c1 = C1; r2 = R2; c2 = C2; } bool same(int R1, int C1, int R2, int C2) { if (R1 != r1) return false; if (C1 != c1) return false; if (R2 != r2) return false; if (C2 != c2) return false; return true; } bool in(int x, int y) { if (r1 <= x && x <= r2 && c1 <= y && y <= c2) return true; return false; } }; vector<square *> S; int main(void) { int n, m, q; scanf( %d %d %d , &n, &m, &q); while (q--) { int op; scanf( %d , &op); int r1, c1, r2, c2; scanf( %d %d %d %d , &r1, &c1, &r2, &c2); if (op == 1) { square *s = new square(r1, c1, r2, c2); S.push_back(s); } else if (op == 2) { int size = S.size(); for (int i = 0; i < size; i++) { square *s = S[i]; if (s->same(r1, c1, r2, c2)) { S.erase(S.begin() + i); break; } } } else if (op == 3) { bool find = false; for (square *s : S) if (s->in(r1, c1) != s->in(r2, c2)) { printf( No n ); find = true; break; } if (!find) printf( Yes n ); } } return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Sdram_RD_FIFO.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_RD_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [8:0] wrusedw;
wire sub_wire0;
wire [8:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [8:0] sub_wire4;
wire rdempty = sub_wire0;
wire [8:0] wrusedw = sub_wire1[8:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [8:0] rdusedw = sub_wire4[8:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; bool cmp(const pair<long long, long long> &a, const pair<long long, long long> &b) { return (a.second < b.second); } long long power(long long x, long long y) { long long res = 1; x = x; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x); y = y >> 1; x = (x * x); } return res; } int main() { long long t = 1, i, j, k, x, y, z, n, m; cin >> t; while (t--) { cin >> n; if (n == 1) { cout << 0 n ; continue; } long long p = 8; long long sum = 0; for (i = 1; i <= (n / 2); i++) { p = 8 * i; sum = sum + (p * i); } cout << sum << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int c[maxn], up[maxn], h[maxn]; bool visited[maxn]; set<int> s[maxn]; vector<int> g[maxn]; void dfs(int v, int par = -1) { c[v] = v; visited[v] = 1; up[v] = h[v]; int cnt = 0; for (auto u : g[v]) { if (u == par) cnt++; else if (!visited[u]) { h[u] = h[v] + 1; dfs(u, v); up[v] = min(up[v], up[u]); if (s[c[u]].size() > s[c[v]].size()) c[v] = c[u]; } else up[v] = min(up[v], h[u]); } if (cnt > 1) up[v] = min(up[v], h[v] - 1); for (auto u : g[v]) { if (h[u] == h[v] + 1 and c[u] != c[v]) { for (auto it : s[c[u]]) { if (s[c[v]].find(-it) != s[c[v]].end()) s[c[v]].erase(-it); else s[c[v]].insert(it); } s[c[u]].clear(); } } if (c[v] != v) { for (auto it : s[v]) { if (s[c[v]].find(-it) != s[c[v]].end()) s[c[v]].erase(-it); else s[c[v]].insert(it); } s[v].clear(); } if (up[v] < h[v]) return; if (s[c[v]].empty()) return; int minimum = *s[c[v]].begin(); auto it = s[c[v]].end(); it--; int maximum = *it; if (minimum < 0 and maximum > 0) { cout << No << endl; exit(0); } } int par[maxn]; int get_par(int v) { if (par[v] < 0) return v; return par[v] = get_par(par[v]); } void merge(int v, int u) { v = get_par(v), u = get_par(u); if (v == u) return; par[v] = u; } int main() { ios_base::sync_with_stdio(false); memset(par, -1, sizeof par); int n, m, q; cin >> n >> m >> q; for (int i = 0; i < m; i++) { int v, u; cin >> v >> u; g[v].push_back(u); g[u].push_back(v); merge(v, u); } string answer = Yes ; for (int i = 0; i < q; i++) { int v, u; cin >> v >> u; if (get_par(v) != get_par(u)) answer = No ; s[v].insert(i + 1); s[u].insert(-i - 1); } if (answer == No ) return cout << answer << endl, 0; for (int v = 1; v <= n; v++) if (!visited[v]) dfs(v); cout << Yes << endl; } |
#include <bits/stdc++.h> int main() { char s[100]; scanf( %s , s); int ans = 0; for (int i = 0; s[i]; ++i) { if (isalpha(s[i])) { if (s[i] <= Z ) ans += s[i] - A + 1; else ans -= s[i] - a + 1; } } printf( %d n , ans); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IBUFDS_GTE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 12/11/2012 - Initial version
// 03/22/2013 - Model added
// 03/25/2013 - Sync 5 YML & model update
// 04/12/2013 - Add attribute section
// 08/28/2013 - Add specify section
// 06/02/2014 - New simulation library message format.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_GTE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)(
output O,
output ODIV2,
input CEB,
input I,
input IB
);
// define constants
localparam MODULE_NAME = "IBUFDS_GTE3";
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL;
localparam [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [1:0] REFCLK_HROW_CK_SEL_BIN;
wire [1:0] REFCLK_ICNTL_RX_BIN;
wire i_in, ib_in, ceb_in;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_GTE3_dr.v"
`endif
assign i_in = I;
assign ib_in = IB;
assign ceb_in = CEB;
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG;
assign REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG;
reg ODIV2_out=0;
wire O_out;
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
initial begin
allEqual = 0;
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(*) begin
case (REFCLK_HROW_CK_SEL_BIN)
2'b00: ODIV2_out <= O_out;
2'b01: ODIV2_out <= allEqual;
2'b10: ODIV2_out <= 1'b0;
2'b11: ODIV2_out <= 1'b0;
default : ODIV2_out <= O_out;
endcase
end
// =====================
// Generate O
// =====================
assign O_out = (REFCLK_EN_TX_PATH_BIN | ceb_in) ? 1'b0 : i_in;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => ODIV2) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => ODIV2) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => ODIV2) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 7; vector<pair<int, int> > G[MAXN]; int n; int sz[MAXN]; long long MAX, MIN; void dfs(int u, int fa) { sz[u] = 1; for (pair<int, int> edge : G[u]) { int v = edge.first; if (v == fa) continue; dfs(v, u); sz[u] += sz[v]; } for (pair<int, int> edge : G[u]) { int v = edge.first, w = edge.second; if (v == fa) continue; if (sz[v] & 1) MIN += w; MAX += 1ll * w * min(sz[v], (n - sz[v])); } } int main() { int T; scanf( %d , &T); while (T--) { int k; scanf( %d , &k); n = 2 * k; for (int i = 1, u, v, w; i < n; i++) { scanf( %d%d%d , &u, &v, &w); G[u].push_back({v, w}); G[v].push_back({u, w}); } MAX = MIN = 0; dfs(1, 0); printf( %lld %lld n , MIN, MAX); for (int i = 1; i <= n; i++) G[i].clear(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/07/2017 08:59:22 AM
// Design Name:
// Module Name: mux_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux_sim();
// inputs
reg SEL;
reg IN_0;
reg IN_1;
// outputs
wire OUT;
// dut
mux_2_1 dut (
.M_SEL(SEL),
.M_IN_0(IN_0),
.M_IN_1(IN_1),
.M_OUT(OUT)
);
initial begin
IN_0 <= 0;
IN_1 <= 0;
SEL <= 0;
#100 IN_1 <= 1;
#100 IN_0 <= 1;
#100 IN_1 <= 0;
#100 IN_0 <= 0;
#300 SEL <= 1;
#100 IN_1 <= 1;
#100 IN_0 <= 1;
#100 IN_1 <= 0;
#100 IN_0 <= 0;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:56:12 06/23/2014
// Design Name: Top_Muliti_IOBUS
// Module Name: C:/Users/Deus/Windows Sync/Xilinx Workspace/Multi_Cycle_CPU/top.v
// Project Name: M_C_C
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top_Muliti_IOBUS
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top;
// Inputs
reg clk_50mhz;
reg [3:0] BTN;
reg [7:0] SW;
// Outputs
wire [7:0] LED;
wire [7:0] SEGMENT;
wire [3:0] AN_SEL;
// Instantiate the Unit Under Test (UUT)
Top_Muliti_IOBUS uut (
.clk_50mhz(clk_50mhz),
.BTN(BTN),
.SW(SW),
.LED(LED),
.SEGMENT(SEGMENT),
.AN_SEL(AN_SEL)
);
integer i;
initial begin
// Initialize Inputs
clk_50mhz = 0;
BTN = 0;
SW = 8'b00100001;
// Wait 100 ns for global reset to finish
#100;
BTN[3] = 1;
#10;
for( i = 0; i < 5; i = i+1) #10 clk_50mhz = ~clk_50mhz;
BTN[3] = 0;
// Add stimulus here
end
always #5 clk_50mhz = ~clk_50mhz;
endmodule
|
// Warning R1: No reset specified
// Created by fizzim.pl version $Revision: 5.0 on 2014:07:06 at 16:03:00 (www.fizzim.com)
module DE1_disp (
output reg [3:0] DISPn,
output reg [6:0] HEX,
input wire [6:0] HEX0,
input wire [6:0] HEX1,
input wire [6:0] HEX2,
input wire [6:0] HEX3,
input wire clk
);
// state bits
parameter
state0 = 3'b000,
state1 = 3'b001,
state2 = 3'b010,
state3 = 3'b011,
state4 = 3'b100,
state5 = 3'b101,
state6 = 3'b110,
state7 = 3'b111;
reg [2:0] state = state0;
reg [2:0] nextstate;
// comb always block
always @* begin
// Warning I2: Neither implied_loopback nor default_state_is_x attribute is set on state machine - defaulting to implied_loopback to avoid latches being inferred
nextstate = state; // default to hold value because implied_loopback is set
case (state)
state0: begin
begin
nextstate = state1;
end
end
state1: begin
begin
nextstate = state2;
end
end
state2: begin
begin
nextstate = state3;
end
end
state3: begin
begin
nextstate = state4;
end
end
state4: begin
begin
nextstate = state5;
end
end
state5: begin
begin
nextstate = state6;
end
end
state6: begin
begin
nextstate = state7;
end
end
state7: begin
begin
nextstate = state0;
end
end
endcase
end
// Assign reg'd outputs to state bits
// sequential always block
always @(posedge clk) begin
state <= nextstate;
end
// datapath sequential always block
always @(posedge clk) begin
begin
DISPn[3:0] <= "1111"; // default
HEX[6:0] <= ""; // default
case (nextstate)
state1: begin
DISPn[3:0] <= "1110";
HEX[6:0] <= HEX0[6:0];
end
state2: begin
DISPn[3:0] <= "1111";
HEX[6:0] <= "";
end
state3: begin
DISPn[3:0] <= "1101";
HEX[6:0] <= HEX1[6:0];
end
state4: begin
DISPn[3:0] <= "1111";
HEX[6:0] <= "";
end
state5: begin
DISPn[3:0] <= "1011";
HEX[6:0] <= HEX2[6:0];
end
state6: begin
DISPn[3:0] <= "1111";
HEX[6:0] <= "";
end
state7: begin
DISPn[3:0] <= "0111";
HEX[6:0] <= HEX3[6:0];
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using ll = long long int; using namespace std; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; bool printSub(int a[], int sum) { if (sum == 0) return true; if (sum < 0) return false; for (int i = 0; i < 3; ++i) { int rem = sum - a[i]; if (printSub(a, rem)) { cout << a[i] << ; return true; } } } void solve() { int n, ans = 0; cin >> n; int a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 30; i > 0; --i) { int sum = 0; for (int j = 0; j < n; ++j) { if (a[j] > i) { sum = 0; } else sum = max(a[j], sum + a[j]); ans = max(ans, sum - i); } } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char cell; short r, c, rr, cc, e; int res = 0, i, cat[100], cnt = 0; cin >> r >> c; rr = r; cc = c; for (i = 0; i < r; i++) { e = 0; for (int I = 0; I < c; I++) { cin >> cell; if (cell == S ) { e++; cat[cnt] = I; cnt++; } } if (e == 0) { res += c; rr--; } } cc -= cnt; sort(cat, cat + cnt); for (i = 1; i < cnt; i++) if (cat[i] == cat[i - 1]) cc++; res += cc * rr; cout << res; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long long mod = 1000000007; void solve() { int n, m, u, v; cin >> n >> m; vector<int> adj[n + 1]; for (int i = 0; i < m; i++) { cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } vector<pair<long long, long long> > hash, hash_orig; hash.reserve(n); long long p1 = 31, p2 = 53, h1, h2; long long pow_p1[n + 1], pow_p2[n + 1]; pow_p1[0] = pow_p2[0] = 1; for (int i = 1; i <= n; i++) { pow_p1[i] = pow_p1[i - 1] * p1 % mod; pow_p2[i] = pow_p2[i - 1] * p2 % mod; } for (int i = 1; i <= n; i++) { h1 = 0; h2 = 0; for (int &j : adj[i]) { h1 += pow_p1[j]; h2 += pow_p2[j]; } hash.push_back({h1, h2}); } hash_orig = hash; sort((hash).begin(), (hash).end()); long long ans = 0; int cnt = 1; for (int i = 1; i < n; i++) { if (hash[i] != hash[i - 1]) { ans += 1ll * cnt * (cnt - 1) / 2; cnt = 1; } else cnt++; } ans += 1ll * cnt * (cnt - 1) / 2; for (int i = 1; i <= n; i++) { hash_orig[i - 1].first += pow_p1[i]; hash_orig[i - 1].second += pow_p2[i]; } for (int i = 1; i <= n; i++) { for (int &j : adj[i]) { if (j < i || adj[i].size() != adj[j].size()) continue; if (hash_orig[i - 1] == hash_orig[j - 1]) ans++; } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> const int N = 5000 + 10; struct node { int l, r, id; }; node a[N]; bool pre[N], suf[N]; std::vector<node> vector; bool cmp(const node& i, const node& j) { if (i.r ^ j.r) return i.r < j.r; else return i.l < j.l; } bool cc(const node& i, const node& j) { return i.id < j.id; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { a[i].id = i; scanf( %d%d , &a[i].l, &a[i].r); } std::sort(a + 1, a + 1 + n, cmp); pre[0] = pre[1] = true; for (int i = 2; i <= n; ++i) if (pre[i - 1] && a[i].l >= a[i - 1].r) pre[i] = true; else break; suf[n + 1] = suf[n] = true; for (int i = n - 1; i >= 1; --i) if (suf[i + 1] && a[i].r <= a[i + 1].l) suf[i] = true; else break; for (int i = 1; i <= n; ++i) if (pre[i - 1] && suf[i + 1]) { if (i == 1 || i == n || a[i - 1].r <= a[i + 1].l) vector.push_back(a[i]); } std::sort(vector.begin(), vector.end(), cc); printf( %d n , vector.size()); for (int i = 0; i < vector.size(); ++i) { if (i) putchar( ); printf( %d , vector[i].id); } puts( ); return 0; } |
module pulse
#(parameter dly=3,
parameter len=2)
(input rstn,
input clk,
output reg pulse);
localparam width = $clog2(dly+len)+1;
reg [width-1:0] cnt;
always @(posedge clk or negedge rstn) begin
if (~rstn)
cnt <= 1'b0;
else if (cnt != dly+len)
cnt <= cnt + 1'b1;
end
always @(posedge clk or negedge rstn) begin
if (~rstn)
pulse <= 1'b0;
else if (cnt == dly)
pulse <= 1'b1;
else if (cnt == dly+len)
pulse <= 1'b0;
end
endmodule
module pulse_interclk
(input rstn,
input iclk,
input oclk,
input ipulse,
output opulse);
reg pulse0, pulse1, pulse2;
assign opulse = pulse1 & ~pulse2;
always @(posedge iclk or negedge rstn) begin
if (~rstn)
pulse0 <= 1'b0;
else if (ipulse)
pulse0 <= 1'b1;
end
always @(posedge oclk or negedge rstn) begin
if (~rstn) begin
pulse1 <= 1'b0;
pulse2 <= 1'b0;
end else begin
pulse1 <= pulse0;
pulse2 <= pulse1;
end
end
endmodule
module pulse_sim;
wire sys_clk;
sim_clk sysClk(sys_clk);
// ------------
reg rstn;
wire p[8:0];
initial rstn = 0;
initial #2 rstn = 1;
initial #65 rstn = 0;
pulse #(.dly(8), .len(0)) pulseI0(.rstn(rstn), .clk(sys_clk), .pulse(p[0]));
pulse #(.dly(8), .len(1)) pulseI1(.rstn(rstn), .clk(sys_clk), .pulse(p[1]));
pulse #(.dly(8), .len(1024)) pulseI2(.rstn(rstn), .clk(sys_clk), .pulse(p[2]));
pulse #(.dly(0), .len(1)) pulseI3(.rstn(rstn), .clk(sys_clk), .pulse(p[3]));
pulse #(.dly(1), .len(0)) pulseI4(.rstn(rstn), .clk(sys_clk), .pulse(p[4]));
pulse #(.dly(0), .len(0)) pulseI5(.rstn(rstn), .clk(sys_clk), .pulse(p[5]));
// ------------
wire slow_clk;
sim_clk #(.T(8)) slowClk(slow_clk);
wire fast_clk;
assign fast_clk = sys_clk;
wire pi[1:0];
reg po[1:0];
always @(posedge fast_clk, negedge rstn) begin
if (~rstn)
po[0] <= 1'b0;
else
po[0] <= 1'b1;
end
always @(posedge slow_clk, negedge rstn) begin
if (~rstn)
po[1] <= 1'b0;
else
po[1] <= 1'b1;
end
pulse_interclk pinterI0(.rstn(rstn), .iclk(fast_clk), .oclk(slow_clk), .ipulse(po[0]), .opulse(pi[0]));
pulse_interclk pinterI1(.rstn(rstn), .iclk(slow_clk), .oclk(fast_clk), .ipulse(po[1]), .opulse(pi[1]));
wire op;
reg op_flag;
always @(posedge fast_clk, negedge rstn) begin
if (~rstn)
op_flag <= 1'b0;
else if (~op_flag)
op_flag <= 1'b1;
else if (op)
op_flag <= 1'b0;
end
pulse_interclk pinterI2(.rstn(op_flag), .iclk(fast_clk), .oclk(fast_clk), .ipulse(1), .opulse(op));
// ------------
initial begin
$dumpfile(`VCD_PATH);
$dumpvars();
// $monitor("T=%t, clk=%d p[0]=%d p[1]=%d p[2]=%d p[3]=%d",
// $time, sys_clk,
// p[0],
// p[1],
// p[2],
// p[3])
#70 $finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:12:38 06/05/2016
// Design Name:
// Module Name: Prueba_Alarma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Prueba_Alarma(
input clk,
input got_data,
input [7:0] Tecla,
input [7:0] Segundos,
input [7:0] Minutos,
input [7:0] Horas,
input [7:0] Segundos_RTC,
input [7:0] Minutos_RTC,
input [7:0] Horas_RTC,
output [7:0] Flag_Pico,
output Flag_VGA
);
wire Salida_Reset;
wire [7:0] Salida_Estado_Cronometro;
wire [7:0] Salida_Guardar;
wire [7:0] Segundos_R;
wire [7:0] Minutos_R;
wire [7:0] Horas_R;
Registro_Estado_Cronometro F1 (
.Tecla(Tecla),
.clk(clk),
.reset(Salida_Reset),
.Salida_Estado_Cronometro(Salida_Estado_Cronometro)
);
Registro_Guardar F2 (
.Tecla(Tecla),
.clk(clk),
.reset(Salida_Reset),
.Salida_Guardar(Salida_Guardar)
);
Registro_Reset_Alarma F3 (
.Tecla(Tecla),
.clk(clk),
.got_data(got_data),
.Salida_Reset(Salida_Reset)
);
Registro_Contadores_Cronometro F4 (
.clk(clk),
.Segundos(Segundos),
.Minutos(Minutos),
.Horas(Horas),
.Tecla(Salida_Estado_Cronometro),
.Segundos_R(Segundos_R),
.Minutos_R(Minutos_R),
.Horas_R(Horas_R)
);
Banderas_Alarma F5 (
.Segundos(Segundos_R),
.Minutos(Minutos_R),
.Horas(Horas_R),
.Segundos_RTC(Segundos_RTC),
.Minutos_RTC(Minutos_RTC),
.Horas_RTC(Horas_RTC),
.Estado(Salida_Estado_Cronometro),
.Guardar(Salida_Guardar),
.clk(clk),
.reset(Salida_Reset),
.Flag_Pico(Flag_Pico),
.Flag_VGA(Flag_VGA)
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module sequencer_scc_sv_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 6
)
(
avl_writedata,
dqsi_phase,
dqs_phase,
dq_phase,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
output [2:0] dqsi_phase;
output [6:0] dqs_phase;
output [6:0] dq_phase;
output [5:0] dqse_phase;
reg [2:0] dqsi_phase;
reg [6:0] dqs_phase;
reg [6:0] dq_phase;
reg [5:0] dqse_phase;
always @ (*) begin
dqsi_phase = 3'b010;
dqs_phase = 7'b1110110;
dq_phase = 7'b0110100;
dqse_phase = 6'b000110;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 90, DQSE = 90
begin
dqs_phase = 7'b0010110;
dq_phase = 7'b1000110;
dqse_phase = 6'b000010;
end
5'b00001: // DQS = 225, DQ = 135, DQSE = 135
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b1100110;
dqse_phase = 6'b000011;
end
5'b00010: // DQS = 270, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b1010110;
dq_phase = 7'b0010110;
dqse_phase = 6'b000100;
end
5'b00011: // DQS = 315, DQ = 225, DQSE = 225
begin
dqs_phase = 7'b1110111;
dq_phase = 7'b0110110;
dqse_phase = 6'b000101;
end
5'b00100: // DQS = 360, DQ = 270, DQSE = 270
begin
dqs_phase = 7'b0000111;
dq_phase = 7'b1010110;
dqse_phase = 6'b000110;
end
5'b00101: // DQS = 405, DQ = 315, DQSE = 315
begin
dqs_phase = 7'b0100111;
dq_phase = 7'b1110111;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 450, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b1001000;
dq_phase = 7'b0000111;
dqse_phase = 6'b001000;
end
5'b00111: // DQS = 495, DQ = 405, DQSE = 405
begin
dqs_phase = 7'b1101000;
dq_phase = 7'b0100111;
dqse_phase = 6'b001001;
end
5'b01000: // DQS = 540, DQ = 450
begin
dqs_phase = 7'b0011000;
dq_phase = 7'b1001000;
end
5'b01001:
begin
dqs_phase = 7'b0111000;
dq_phase = 7'b1101000;
end
5'b01010:
begin
dqs_phase = 7'b1011000;
dq_phase = 7'b0011000;
end
5'b01011:
begin
dqs_phase = 7'b1111001;
dq_phase = 7'b0111000;
end
5'b01100:
begin
dqs_phase = 7'b0001001;
dq_phase = 7'b1011000;
end
5'b01101:
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b1111001;
end
5'b01110:
begin
dqs_phase = 7'b1001010;
dq_phase = 7'b0001001;
end
5'b01111:
begin
dqs_phase = 7'b1101010;
dq_phase = 7'b0101001;
end
5'b10000:
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b1001010;
end
5'b10001:
begin
dqs_phase = 7'b0111010;
dq_phase = 7'b1101010;
end
5'b10010:
begin
dqs_phase = 7'b1011010;
dq_phase = 7'b0011010;
end
5'b10011:
begin
dqs_phase = 7'b1111011;
dq_phase = 7'b0111010;
end
5'b10100:
begin
dqs_phase = 7'b0001011;
dq_phase = 7'b1011010;
end
5'b10101:
begin
dqs_phase = 7'b0101011;
dq_phase = 7'b1111011;
end
default : begin end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_1_V
`define SKY130_FD_SC_HS__MAJ3_1_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_1_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; const int MAX_N = 200004; char s[MAX_N], t[MAX_N]; int l[MAX_N], r[MAX_N]; vector<int> p[40]; int read() { int x; scanf( %d , &x); return x; } int num(char x) { return x - a ; } bool find(int x, int left, int right) { if (left > right) return false; int sz = int(p[x].size()); int l = 0, r = sz - 1; while (l <= r) { int mid = (l + r) / 2, t = p[x][mid]; if (t < left) l = mid + 1; else if (t > right) r = mid - 1; else return true; } return false; } int main() { scanf( %s%s , &s, &t); int n = strlen(s), m = strlen(t); if (n < m) { printf( No ); return 0; } for (int i = 0; i < int(m); ++i) p[num(t[i])].push_back((i)); if (s[0] == t[0]) l[0] = 0; else l[0] = -1; for (int i = int(1); i <= int(n - 1); ++i) { l[i] = l[i - 1]; if (l[i] < m - 1 && s[i] == t[l[i] + 1]) ++l[i]; } if (s[n - 1] == t[m - 1]) r[n - 1] = m - 1; else r[n - 1] = m; for (int i = int(n - 2); i >= int(0); --i) { r[i] = r[i + 1]; if (r[i] > 0 && s[i] == t[r[i] - 1]) --r[i]; } for (int i = 0; i < int(n); ++i) { if (find(num(s[i]), r[i], l[i]) == false) { printf( No ); return 0; } } printf( Yes ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n, k; cin >> n >> k; string s; cin >> s; int c = 0; if (k == 0) cout << s << endl; else if (n == 1) { cout << 0 << endl; } else if (k >= 1 && n > 1) { int x = s[0] - 0 ; if (x > 1) { s[0] = 1 ; k--; } for (int i = 1; i < n && k > 0; i++) { x = s[i] - 0 ; if (x > 0) { s[i] = 0 ; k--; } } cout << s << endl; } } |
#include <bits/stdc++.h> using namespace std; long long mcd(long long a, long long b) { if (b > a) swap(a, b); if (b == 0) return a; else return mcd(b, a % b); } long long i, j, n, m, q, a, l, r, b; int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); cin >> q; while (q--) { cin >> n; if (n == 1) cout << 3; else if (n == 2) cout << 2; else if (n & 1) cout << 1; else cout << 0; cout << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, l; cin >> n >> l; vector<int> v = vector<int>(n); for (int i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); int vals = 1; int prev = v[0]; vector<pair<int, int>> vp; vp.push_back(make_pair(prev, 1)); for (int i = 1; i < n; i++) { if (v[i] == prev) { vp[vp.size() - 1].second++; } else { prev = v[i]; vp.push_back(make_pair(prev, 1)); vals++; } } double t = log2(vals); int fs = t; if (t > fs) fs++; if (fs * n < l * 8) { cout << 0 << endl; return 0; } int max_log = (l * 8) / n; int distinct = 1 << max_log; int start_p = 0; int end_p = vp.size() - 1; vector<int> ps = vector<int>(vp.size() + 1, 0); ps[0] = 0; for (int i = 0; i < vp.size(); i++) ps[i + 1] = ps[i] + vp[i].second; vector<int> ss = vector<int>(vp.size() + 1, 0); ss[0] = 0; for (int i = 0; i < vp.size(); i++) { ss[i + 1] = ss[i] + vp[vp.size() - 1 - i].second; } int mn = n; for (int i = 0; i < vals - distinct; i++) { if (ps[i] + ss[vals - distinct - i] < mn) mn = ps[i] + ss[vals - distinct - i]; } cout << mn << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 5; const int MOD = 1e9 + 7; void solve() { int n, m; cin >> n >> m; vector<int> a(n), b(m + 1), la(m + 1); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 1; i < m + 1; ++i) cin >> b[i]; int mid = 0, l = 0, r = n - 1, ans = -1; while (l <= r) { mid = (l + r) / 2; for (int i = 0; i < m + 1; ++i) la[i] = -1; for (int i = 0; i < mid + 1; ++i) { if (a[i] != 0) la[a[i]] = i; } int p = 0, ctr = 0; for (int i = 0; i < mid + 1; ++i) { if (la[a[i]] != i) ctr++; else if (ctr >= b[a[i]]) { ctr -= b[a[i]]; p++; } else break; } if (p == m) { ans = mid + 1; r = mid - 1; } else { l = mid + 1; } } cout << ans; } int main() { int t = 1; while (t--) solve(); return 0; } |
module ITU_656_Decoder( // TV Decoder Input
iTD_DATA,
// Position Output
oTV_X,
oTV_Y,
oTV_Cont,
// YUV 4:2:2 Output
oYCbCr,
oDVAL,
// Control Signals
iSwap_CbCr,
iSkip,
iRST_N,
iCLK_27 );
input [7:0] iTD_DATA;
input iSwap_CbCr;
input iSkip;
input iRST_N;
input iCLK_27;
output [15:0] oYCbCr;
output [9:0] oTV_X;
output [9:0] oTV_Y;
output [31:0] oTV_Cont;
output oDVAL;
// For detection
reg [23:0] Window; // Sliding window register
reg [17:0] Cont; // Counter
reg Active_Video;
reg Start;
reg Data_Valid;
reg Pre_Field;
reg Field;
wire SAV;
reg FVAL;
reg [9:0] TV_Y;
reg [31:0] Data_Cont;
// For ITU-R 656 to ITU-R 601
reg [7:0] Cb;
reg [7:0] Cr;
reg [15:0] YCbCr;
assign oTV_X = Cont>>1;
assign oTV_Y = TV_Y;
assign oYCbCr = YCbCr;
assign oDVAL = Data_Valid;
assign SAV = (Window==24'hFF0000)&(iTD_DATA[4]==1'b0);
assign oTV_Cont= Data_Cont;
always@(posedge iCLK_27 or negedge iRST_N)
begin
if(!iRST_N)
begin
// Register initial
Active_Video<= 1'b0;
Start <= 1'b0;
Data_Valid <= 1'b0;
Pre_Field <= 1'b0;
Field <= 1'b0;
Window <= 24'h0;
Cont <= 18'h0;
Cb <= 8'h0;
Cr <= 8'h0;
YCbCr <= 16'h0;
FVAL <= 1'b0;
TV_Y <= 10'h0;
Data_Cont <= 32'h0;
end
else
begin
// Sliding window
Window <= {Window[15:0],iTD_DATA};
// Active data counter
if(SAV)
Cont <= 18'h0;
else if(Cont<1440)
Cont <= Cont+1'b1;
// Check the video data is active?
if(SAV)
Active_Video<= 1'b1;
else if(Cont==1440)
Active_Video<= 1'b0;
// Is frame start?
Pre_Field <= Field;
if({Pre_Field,Field}==2'b10)
Start <= 1'b1;
// Field and frame valid check
if(Window==24'hFF0000)
begin
FVAL <= !iTD_DATA[5];
Field <= iTD_DATA[6];
end
// ITU-R 656 to ITU-R 601
if(iSwap_CbCr)
begin
case(Cont[1:0]) // Swap
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cr};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cb};
endcase
end
else
begin
case(Cont[1:0]) // Normal
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cb};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cr};
endcase
end
// Check data valid
if( Start // Frame Start?
&& FVAL // Frame valid?
&& Active_Video // Active video?
&& Cont[0] // Complete ITU-R 601?
&& !iSkip ) // Is non-skip pixel?
Data_Valid <= 1'b1;
else
Data_Valid <= 1'b0;
// TV decoder line counter for one field
if(FVAL && SAV)
TV_Y<= TV_Y+1;
if(!FVAL)
TV_Y<= 0;
// Data counter for one field
if(!FVAL)
Data_Cont <= 0;
if(Data_Valid)
Data_Cont <= Data_Cont+1'b1;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; char inp[1005], ans[1005]; int n, p; bool possible(int pos, int ok) { if (pos == n) return ok; int start = ok ? 0 : inp[pos] - a ; int i; for (i = start; i < p; i++) { ans[pos] = i + a ; if (pos > 0 && ans[pos - 1] == ans[pos]) continue; if (pos > 1 && ans[pos - 2] == ans[pos]) continue; if (possible(pos + 1, ok | (i > start))) return true; } return false; } int main() { scanf( %d%d , &n, &p); scanf( %s , inp); bool ok = 0; int i; if (possible(0, 0)) { ans[n] = 0 ; printf( %s n , ans); } else printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std; struct node { int l, m, r; }; node t[3000005]; int arr[300005], n, m; long long a[300005]; int sign(long long x) { if (x > 0) return 1; if (x < 0) return -1; return 0; } void cal(int x, int l, int r) { int m = (l + r) / 2; t[x].m = max(t[x * 2].m, t[x * 2 + 1].m); t[x].l = t[x * 2].l; t[x].r = t[x * 2 + 1].r; if (!!a[m] && !!a[m + 1] && sign(a[m]) >= sign(a[m + 1])) { t[x].m = max(t[x].m, t[x * 2].r + t[x * 2 + 1].l); if (t[2 * x].m == m - l + 1) t[x].l = t[2 * x].l + t[2 * x + 1].l; if (t[2 * x + 1].m == r - m) t[x].r = t[2 * x].r + t[2 * x + 1].r; } } void build(int x, int l, int r) { if (l == r) { int tmp = !!a[l]; t[x] = {tmp, tmp, tmp}; return; } int m = (l + r) / 2; build(x * 2, l, m); build(x * 2 + 1, m + 1, r); cal(x, l, r); } void update(int x, int l, int r, int pos, int d) { if (l == r) { a[pos] += d; int tmp = !!a[pos]; t[x] = {tmp, tmp, tmp}; return; } int m = (l + r) / 2; if (pos <= m) update(x * 2, l, m, pos, d); else update(x * 2 + 1, m + 1, r, pos, d); cal(x, l, r); } int main() { cin >> n; for (int i = 0; i < n; i++) scanf( %d , &arr[i]); for (int i = 0; i + 1 < n; i++) a[i] = arr[i + 1] - arr[i]; if (n > 1) build(1, 0, n - 2); cin >> m; while (m--) { int l, r, d; scanf( %d%d%d , &l, &r, &d); if (n == 1) { printf( %d n , 1); continue; } if (l > 1) update(1, 0, n - 2, l - 2, d); if (r < n) update(1, 0, n - 2, r - 1, -d); printf( %d n , t[1].m + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000000 + 10, MOD = (int)1e+9 + 7; long long fac[MAXN], Ifac[MAXN], T; int k, w; long long Pow(long long a, long long b) { long long d = 1; for (; b; d = (b & 1) ? d * a % MOD : d, a = a * a % MOD, b /= 2) ; return d; } long long A(int x, int y) { return fac[x] * Ifac[x - y] % MOD; } int main() { cin >> k >> w; fac[0] = Ifac[0] = 1; for (int i = 1; i <= k; ++i) fac[i] = fac[i - 1] * i % MOD, Ifac[i] = Ifac[i - 1] * Pow(i, MOD - 2) % MOD; long long CC = 0, t = Pow(k, w - 2); for (int i = 1; i <= k; ++i) { if (i < w) CC = (CC + A(k, i) * A(k, i) % MOD * t % MOD * i % MOD) % MOD; else CC = (CC + A(k, i) * A(k + w - 1 - i, w - 1) % MOD * w) % MOD; if (i < k) { t = t * Pow(k, MOD - 2) % MOD; if (i + 2 <= w) CC = (CC + A(k, i) * A(k, i + 1) % MOD * t % MOD * i % MOD) % MOD; else CC = (CC + A(k, i + 1) * A(k - i + w - 2, w - 2) % MOD * (w - 1) % MOD) % MOD; } } cout << (CC + MOD) % MOD << endl; fclose(stdin); fclose(stdout); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_TB_V
`define SKY130_FD_SC_LS__A211OI_TB_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, arr[110], c1, c0; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &arr[i]), c1 += arr[i]; int out = 0; for (int i = 0; i < n; ++i) { c0 += (!arr[i]); out = max(out, c0 + c1); c1 -= arr[i]; } cout << out; } |
#include <bits/stdc++.h> using namespace std; const int di[] = {-1, -1, -1, 0, 1, 1, 1, 0, 0}, dj[] = {-1, 0, 1, 1, 1, 0, -1, -1, 0}; int st[20][20][20] = {}; bool fr[20][20][20 * 20] = {}; int n; void file_open() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } void xuli() { queue<int> q1, q2, q3; q1.push(7); q2.push(0); q3.push(0); while (!q1.empty()) { int u = q1.front(), v = q2.front(), k = q3.front() + 1, tK = k; if (k > 9) k = 9; q1.pop(); q2.pop(); q3.pop(); for (int i = 0; i < 9; ++i) { int d = u + di[i], e = v + dj[i]; if (d >= 0 && d < 8 && e >= 0 && e < 8) { if (st[d][e][k] == 0 && st[d][e][k - 1] == 0 && !fr[d][e][tK]) { fr[d][e][tK] = 1; q1.push(d); q2.push(e); q3.push(tK); if (d == 0 && e == 7) { printf( WIN ); return; } } } } } printf( LOSE ); } int main() { char c[20][20] = {}; for (int i = 0; i < 8; ++i) { for (int j = 0; j < 8; ++j) { scanf( %c , &c[i][j]); if (c[i][j] == S ) { int u = 0; while (u + i < 8) { st[i + u][j][u] = 1; ++u; } } } scanf( n ); } xuli(); return 0; } |
/* Copyright (c) 2015 Convey Computer Corporation
*
* This file is part of the OpenHT toolset located at:
*
* https://github.com/TonyBrewer/OpenHT
*
* Use and distribution licensed under the BSD 3-clause license.
* See the LICENSE file for the complete license text.
*/
module HtResetFlop1x2x (
input clkhx,
input clk1x,
input clk2x,
input i_reset,
output r_reset1x,
output r_reset2x
);
`ifdef CNY_PLATFORM_TYPE2
`ifdef CNY_ALTERA
(* noprune = 1 *)
(* syn_preserve = 1 *)
reg r_rsthx;
always @(posedge clkhx) begin
if (i_reset)
r_rsthx <= 1'b1;
else
r_rsthx <= 1'b0;
end
`else //!CNY_ALTERA
wire r_rsthx;
FDSE rst (.C(clkhx), .S(i_reset), .CE(r_rsthx), .D(!r_rsthx), .Q(r_rsthx));
`endif //!CNY_ALTERA
reg r_rst1x;
always @(posedge clk1x) begin
r_rst1x <= r_rsthx;
end
assign r_reset1x = r_rst1x;
reg r_rst2x;
always @(posedge clk2x) begin
r_rst2x <= r_rsthx;
end
assign r_reset2x = r_rst2x;
`else //!CNY_PLATFORM_TYPE2
`ifdef CNY_ALTERA
(* noprune = 1 *)
(* syn_preserve = 1 *)
reg r_rst1x;
always @(posedge clk1x) begin
if (i_reset)
r_rst1x <= 1'b1;
else
r_rst1x <= 1'b0;
end
`else //!CNY_ALTERA
wire r_rst1x;
FDSE rst (.C(clk1x), .S(i_reset), .CE(r_rst1x), .D(!r_rst1x), .Q(r_rst1x));
`endif //!CNY_ALTERA
assign r_reset1x = r_rst1x;
reg r_rst2x;
always @(posedge clk2x) begin
r_rst2x <= r_rst1x;
end
assign r_reset2x = r_rst2x;
`endif //!CNY_PLATFORM_TYPE2
endmodule
|
#include <bits/stdc++.h> using namespace std; void canhazfast() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } template <typename T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <typename T> T extgcd(T a, T b, T &x, T &y) { T x0 = 1, y0 = 0, x1 = 0, y1 = 1; while (b) { T q = a / b; a %= b; swap(a, b); x0 -= q * x1; swap(x0, x1); y0 -= q * y1; swap(y0, y1); } x = x0; y = y0; return a; } int ctz(unsigned x) { return __builtin_ctz(x); } int ctzll(unsigned long long x) { return __builtin_ctzll(x); } int clz(unsigned x) { return __builtin_clz(x); } int clzll(unsigned long long x) { return __builtin_clzll(x); } int popcnt(unsigned x) { return __builtin_popcount(x); } int popcntll(unsigned long long x) { return __builtin_popcountll(x); } int bsr(unsigned x) { return 31 ^ clz(x); } int bsrll(unsigned long long x) { return 63 ^ clzll(x); } map<int, long long> in[100016], out[100016]; void do_vertex(int u) { for (auto i = in[u].begin(), j = out[u].begin(); i != in[u].end() && j != out[u].end();) { int s, t; long long fs, ft; tie(s, fs) = *i; tie(t, ft) = *j; long long z = min(fs, ft); if (z > 0) { out[s][u] -= z; in[t][u] -= z; i->second -= z; j->second -= z; if (s != t) { out[s][t] += z; in[t][s] += z; } } if (i->second == 0) i = in[u].erase(i); if (j->second == 0) j = out[u].erase(j); } } int main() { canhazfast(); int n, m; vector<pair<pair<int, int>, long long>> ans; cin >> n >> m; for (int i = 0; i < m; ++i) { int u, v, w; cin >> u >> v >> w; out[u][v] += w; in[v][u] += w; } for (int i = 1; i <= n; ++i) do_vertex(i); for (int i = 1; i <= n; ++i) { for (const auto &x : out[i]) { if (!x.second || x.first == i) continue; ans.emplace_back(pair<int, int>(i, x.first), x.second); } } cout << ans.size() << n ; for (const pair<pair<int, int>, long long> e : ans) { cout << e.first.first << << e.first.second << << e.second << n ; } return 0; } |
`timescale 1ns/1ps
module I2C_testbench();
reg [6:0] address;
reg [7:0] register;
reg clk;
wire sys_clk;
wire refresh_clk;
reg mode;
reg en;
reg reset;
reg Start;
reg Stop;
reg repeat_start;
wire [7:0] out;
tri1 sda;
tri1 scl;
wire ack;
wire sda_master, sda_slave;
reg sda_master_reg, sda_slave_reg;
reg[7:0] measurement;
master u1 (address, register, refresh_clk, sys_clk, mode, en, reset, Start, Stop, repeat_start, out, ack, sda, scl);
slave u2 (address, measurement, en, reset, scl, sda);
clock_divider u3 (clk, reset, en, refresh_clk, sys_clk);
always
begin
#5 clk = ~clk;
end
initial
begin
address = 7'b1110001;
register = 8'b11111111;
measurement = 8'b11110000;
clk = 1;
mode = 1;
en = 0;
Stop = 0;
Start = 0;
reset = 1;
repeat_start = 0;
#1000
reset = 0;
#2000
reset = 1;
en = 1;
#5000
Start = 1;
#100000
Stop = 1;
#30000
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; long long a[n]; long long m = 1e9; long long sum = 0; for (long long i = 0; i < n; ++i) cin >> a[i], m = min(m, a[i]), sum += a[i]; for (long long i = 0; i < n; ++i) { if ((a[i] - m) % k != 0) { cout << -1; return 0; } } long long l = sum - m * n; cout << l / k; } |
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ()
`include "const.vh"
module RegisterFile #(
parameter LOG2_NUM_REGISTERS = 5,
parameter NUM_REGISTERS = 1 << (LOG2_NUM_REGISTERS)
)(
input clk,
input reset,
// NOTE(aryap): This should just be 4:0 for the initial code.
input [LOG2_NUM_REGISTERS-1:0] waddr,
input [`CPU_DATA_BITS-1:0] wdata,
input write_enable,
input [LOG2_NUM_REGISTERS-1:0] raddr0,
output [`CPU_DATA_BITS-1:0] rdata0,
input [LOG2_NUM_REGISTERS-1:0] raddr1,
output [`CPU_DATA_BITS-1:0] rdata1
);
// Integer registers.
reg [`CPU_DATA_BITS-1:0] registers[NUM_REGISTERS-1:0];
// Data read and propagate.
// TODO(aryap): This is combinational only. Data is not moved on a clock. We
// may need to add a cycle to read and straddle the S1/S2 boundary?
assign rdata0 = registers[raddr0];
assign rdata1 = registers[raddr1];
// TODO(aryap): Reset all registers to 0 on a 'rst' signal.
always @(posedge clk) begin
// Don't write to zero!
if (write_enable && waddr != 0) registers[waddr] <= wdata;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:23:37 11/08/2015
// Design Name:
// Module Name: Integradorv2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Integrador_vel(
input [15:0] a,
input [15:0] dt,
input enable,
input rst,
input clk,
output [31:0] v,
output reg busy
);
wire busy_mul;
reg en;
reg [63:0] acum;
reg [63:0] acum_d;
wire [31:0] varS;
reg rest;
localparam k_fac = 32'd20084;
localparam disp = 11;
assign v = acum[63:32];
booth_mult Multi(
.clk(clk),
.rst(rest),
.en(en),
.A(dt),
.B(a),
.busy(busy_mul),
.R(varS)
);
reg rest_2,en_2;
wire busy_mul_2;
wire [63:0] varS_2;
booth_mult_64 Multi64(
.clk(clk),
.rst(rest_2),
.en(en_2),
.A(varS),
.B(k_fac),
.busy(busy_mul_2),
.R(varS_2)
);
reg div1_rst;
reg div_en;
reg [63:0] div_A, div_A_d;
localparam div_B = 64'd100000;
wire div_busy;
wire [63:0] div_res;
div_64 divider (
.clk(clk),
.rst(div1_rst),
.init_in(div_en),
.A(div_A),
.B(div_B),
.Result(div_res),
.busy(div_busy)
);
initial begin
rest = 1'b1;
div1_rst = 1'b1;
acum = 64'd0;
acum_d = 64'd0;
div_A = 64'd0;
end
//--------------------------------Modulo states
localparam
reset = 5'd0,
ini = 5'd1,
mulv = 5'd2,
check_1 = 5'd3,
mulq = 5'd4,
check_3 = 5'd5,
div_1 = 5'd6,
check_2 = 5'd7,
afterv = 5'd8,
end_state = 5'd9;
// State Machine Regs
reg[4:0] state;
reg[4:0] next_state;
initial state = 0;
initial next_state = 0;
always @(posedge clk)begin
if(rst) state <= reset;
else state <= next_state;
end
always @(*)begin
case(state)
reset: begin
acum <= 32'd0;
busy <= 1'd1;
en <= 1'd0;
rest <= 1'd1;
rest_2 <= 1'b1;
en_2 <= 1'b0;
div_A <= 64'd0;
div1_rst <= 1'b1;
div_en <= 1'b0;
next_state <= ini;
end
ini: begin
busy <= 1'd0;
acum <= acum_d;
en <= 1'd0;
rest <= 1'd0;
rest_2 <= 1'b0;
en_2 <= 1'b0;
div_A <= 64'd0;
div1_rst <= 1'b0;
div_en <= 1'b0;
if (enable) next_state <= mulv;
else next_state <= ini;
end
mulv: begin
acum <= acum_d;
busy <= 1'd1;
en <= 1'b1;
rest <= 1'b0;
rest_2 <= 1'b0;
en_2 <= 1'b0;
div_A <= 64'd0;
div1_rst <= 1'b0;
div_en <= 1'b0;
if(busy_mul) next_state <= check_1;
else next_state <= mulv;
end
check_1: begin
acum <= acum_d;
busy <= 1'd1;
en <= 1'b0;
rest_2 <= 1'b0;
en_2 <= 1'b0;
rest <= 1'b0;
div_A <= 64'd0;
div1_rst <= 1'b0;
div_en <= 1'b0;
if (busy_mul) next_state <= check_1;
else next_state <= div_1;
end
mulq: begin
acum <= acum_d;
busy <= 1'd1;
en <= 1'b1;
rest <= 1'b0;
rest_2 <= 1'b0;
en_2 <= 1'b1;
div_A <= 64'd0;
div1_rst <= 1'b0;
div_en <= 1'b0;
if(busy_mul_2) next_state <= check_3;
else next_state <= mulq;
end
check_3: begin
acum <= acum_d;
busy <= 1'd1;
en <= 1'b1;
rest <= 1'b0;
rest_2 <= 1'b0;
en_2 <= 1'b1;
div_A <= varS_2<<19;
div1_rst <= 1'b0;
div_en <= 1'b0;
if(busy_mul_2) next_state <= check_3;
else next_state <= div_1;
end
div_1: begin
busy <= 1'd1;
en <= 1'b0;
rest <= 1'b0;
if(varS[31]) div_A <= (~varS)+1;
else div_A <= varS;
div1_rst <= 1'b0;
div_en <= 1'b1;
if(div_busy) next_state <= check_2;
else next_state <= div_1;
end
check_2: begin
busy <= 1'd1;
en <= 1'b0;
rest <= 1'b0;
div1_rst <= 1'b0;
div_en <= 1'b1;
if(div_busy) next_state <= check_2;
else next_state <= afterv;
end
afterv: begin
if(clk) begin
//if (varS == 0) acum <= acum_d;
if(varS[31]) acum <= acum_d + 1 + ~div_res;
else acum <= acum_d + div_res;
end
else acum <= acum_d;
busy <= 1'd1;
rest <= 1'b1;
en <= 1'd0;
next_state <= ini;
end
/*
end_state: begin
en <= 1'd0;
rest <=1'b1;
busy <= 1'd0;
if (!enable) next_state <= end_state;
else next_state <= ini;
end
*/
default: begin
acum <= acum_d;
en <= 1'd0;
rest <= 1'b1;
busy <= 1'd0;
next_state <= ini;
end
endcase
end
always @(negedge clk)begin
acum_d <= acum;
// A_d <= A;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int n, m, x, y; int p[100010], q[100010]; vector<int> t[100010], v[100010]; int mn[100010]; bool flag[100010]; inline int dist(int x, int y) { if (p[x] - q[y] >= 0) return p[x] - q[y]; else return q[y] - p[x]; } int main() { scanf( %d%d%d%d , &n, &m, &x, &y); memset(mn, 63, sizeof(mn)); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); for (int i = 1; i <= m; i++) scanf( %d , &q[i]); q[m + 1] = 1e9; q[0] = -1e9; int pos = 1; for (int i = 1; i <= n; i++) { while (pos <= m && q[pos] <= p[i]) pos++; pos--; if (dist(i, pos) == dist(i, pos + 1)) { t[i].push_back(pos); t[i].push_back(pos + 1); } else if (dist(i, pos) < dist(i, pos + 1)) { t[i].push_back(pos); } else { t[i].push_back(pos + 1); } } for (int i = 1; i <= n; i++) if (t[i].size() == 1) { int t1 = t[i][0]; v[t1].push_back(i); mn[t1] = min(mn[t1], dist(i, t1)); } for (int i = 1; i <= n; i++) if (t[i].size() == 1) { if (dist(i, t[i][0]) > mn[t[i][0]]) flag[i] = 1; } for (int i = 1; i <= n; i++) if (t[i].size() == 2) { bool flag1 = 0, flag2 = 0; int cnt1 = 0, cnt2 = 0; int t1 = t[i][0], t2 = t[i][1], d = dist(i, t1); for (int j = 0; j < v[t1].size(); j++) { if (dist(v[t1][j], t1) < d) flag1 = 1; if (d < dist(v[t1][j], t1)) if (flag[v[t1][j]] == 0) cnt1++; } for (int j = 0; j < v[t2].size(); j++) { if (dist(v[t2][j], t2) < d) flag2 = 1; if (d < dist(v[t2][j], t2)) if (flag[v[t2][j]] == 0) cnt2++; } if (cnt1 + flag1 <= cnt2 + flag2) { if (flag1) flag[i] = 1; for (int j = 0; j < v[t1].size(); j++) { if (d < dist(v[t1][j], t1)) if (flag[v[t1][j]] == 0) flag[v[t1][j]] = 1; } mn[t1] = min(mn[t1], dist(i, t1)); v[t1].push_back(i); } else { if (flag2) flag[i] = 1; for (int j = 0; j < v[t2].size(); j++) { if (d < dist(v[t2][j], t2)) if (flag[v[t2][j]] == 0) flag[v[t2][j]] = 1; } mn[t2] = min(mn[t2], dist(i, t2)); v[t2].push_back(i); } } int ans = 0; for (int i = 1; i <= n; i++) ans += flag[i]; printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.precision(10); int n; cin >> n; int m; cin >> m; std::vector<std::vector<long long> > re(n, std::vector<long long>(m, 0)); long long ta = 0; for (int i = 0; i < n; ++i) { cin >> re[i][0]; ta ^= re[i][0]; } long long tb = 0; long long a; for (int i = 0; i < m; ++i) { cin >> a; re[0][i] ^= a; tb ^= a; } if (tb != ta) { cout << NO ; exit(0); } re[0][0] ^= ta; cout << YES n ; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cout << re[i][j] << n [j != m - 1]; } |
#include <bits/stdc++.h> using namespace std; struct Edge { long long to, dis, next, cost; } edge[24050]; long long num = -1; bool vis[10010]; long long mincost; long long pre[10010], head[10010], cost[10010], last[10010], flow[10010], n, k, a[110], b[110], s, t, maxflow; long long to[110]; void add(long long f, long long t, long long dis, long long cost) { edge[++num].to = t; edge[num].dis = dis; edge[num].next = head[f]; edge[num].cost = cost; head[f] = num; edge[++num].to = f; edge[num].dis = 0; edge[num].cost = -cost; edge[num].next = head[t]; head[t] = num; } queue<long long> q; bool spfa(long long s, long long t) { memset(cost, 0x3f3f3f3f, sizeof cost); memset(flow, 0x3f3f3f3f, sizeof flow); memset(vis, 0, sizeof vis); q.push(s); vis[s] = 1; cost[s] = 0; pre[t] = -1; while (!q.empty()) { long long nowp = q.front(); q.pop(); vis[nowp] = 0; for (long long i = head[nowp]; i != -1; i = edge[i].next) { if (edge[i].dis > 0 && cost[edge[i].to] > cost[nowp] + edge[i].cost) { cost[edge[i].to] = cost[nowp] + edge[i].cost; pre[edge[i].to] = nowp; last[edge[i].to] = i; flow[edge[i].to] = min(flow[nowp], edge[i].dis); if (!vis[edge[i].to]) { vis[edge[i].to] = 1; q.push(edge[i].to); } } } } return pre[t] != -1; } void MCMF(long long s, long long t) { while (spfa(s, t)) { long long now = t; maxflow += flow[t]; mincost += flow[t] * cost[t]; while (now != s) { edge[last[now]].dis -= flow[t]; edge[last[now] ^ 1].dis += flow[t]; now = pre[now]; } } } signed main() { long long T; cin >> T; while (T--) { num = -1; memset(to, -1, sizeof to); memset(head, -1, sizeof head); cin >> n >> k; for (long long i = 1; i <= n; i++) cin >> a[i] >> b[i]; maxflow = mincost = 0; s = 0; t = 2 * n + 1; for (long long i = 1; i <= n; i++) add(s, i, 1, 0), add(i + n, t, 1, 0); for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { long long nc = 0; if (j <= k - 1) nc = a[i] + b[i] * (j - 1ll); else if (j != n) nc = b[i] * (k - 1ll); else nc = a[i] + b[i] * (k - 1ll); nc = 0x3f3f3f3f - nc; add(i, j + n, 1, nc); } } MCMF(s, t); long long nowi = -1; for (long long i = n * 4; i <= num; i += 2) { nowi++; if (edge[i].dis == 0) to[1 + nowi % n] = 1 + nowi / n; } cout << 2 * n - k << endl; for (long long i = 1; i <= k - 1; i++) cout << to[i] << ; for (long long i = k; i < n; i++) cout << to[i] << << -to[i] << ; cout << to[n]; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_SYMBOL_V
`define SKY130_FD_SC_HS__FILL_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int modpow(long long int a, long long int n, long long int temp) { long long int res = 1; while (n > 0) { res = (res * res) % temp; if (n & 1) res = (res * a) % temp; n /= 2; } return res; } long long int gcd(long long int a, long long int b) { if (a == 0) return (b); else return (gcd(b % a, a)); } void f(int a[][1001], int x, int y) { if (a[x][y] >= 4) { int t = a[x][y] / 4; a[x][y + 1] += t; a[x + 1][y] += t; a[x - 1][y] += t; a[x][y - 1] += t; a[x][y] = a[x][y] % 4; f(a, x + 1, y); f(a, x - 1, y); f(a, x, y + 1); f(a, x, y - 1); } } int main() { int a[1001][1001] = {0}; int n, q, x, y; cin >> n >> q; a[500][500] = n; f(a, 500, 500); while (q--) { cin >> x >> y; x += 500; y += 500; if (x > 1000 || y > 1000 || x < 0 || y < 0) cout << 0 << endl; else cout << a[x][y] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int i, temp, temp2, a[n + 1]; for (int i = 0; i < n + 1; i++) a[i] = 0; for (int i = 0; i < n - 1; i++) { cin >> temp >> temp2; a[temp]++; a[temp2]++; } int s = 0; for (int i = 0; i < n + 1; i++) { if (a[i] < 2) s++; } cout << s - 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[100000], outpalsz, inn, b[100000]; long long result; int inicount[100001], iniodd; int ccount[100001], codd; int main() { cin.sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1 - i && a[i] == a[n - 1 - i]; i++) outpalsz++; for (int i = outpalsz; i < n - outpalsz; i++) { inicount[a[i]]++; if (inicount[a[i]] % 2) iniodd++; else iniodd--; b[inn++] = a[i]; } if (inn <= 1) { cout << 1LL * n * (n + 1) / 2 << n ; return 0; } if (iniodd <= 1) result = 1LL * (outpalsz + 1) * (outpalsz + 1); for (int i = 0; i <= 100000; i++) ccount[i] = inicount[i]; codd = iniodd; for (int i = 0; i < inn; i++) { ccount[b[i]] -= 2; if (i * 2 + 1 == inn) ccount[b[i]]++; if (i > inn - 1 - i && b[i] == b[inn - 1 - i]) ccount[b[i]] += 2; if (ccount[b[i]] < 0) break; if (codd <= 1) result += outpalsz + 1; } for (int i = 0; i <= 100000; i++) ccount[i] = inicount[i]; codd = iniodd; for (int i = inn - 1; i >= 0; i--) { ccount[b[i]] -= 2; if (i * 2 + 1 == inn) ccount[b[i]]++; if (i < inn - 1 - i && b[i] == b[inn - 1 - i]) ccount[b[i]] += 2; if (ccount[b[i]] < 0) break; if (codd <= 1) result += outpalsz + 1; } cout << result << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > vec[2102100]; pair<int, int> tr[2102100]; int lz[2102100]; int id[2102100]; int l[2102100]; int r[2102200]; int b[2102100]; int path[2102100]; int st[2102100]; void build(int p, int l, int r) { tr[p] = {0, -1}; lz[p] = 0; if (l == r) { return; } int mid = l + r >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); } void pushup(int p) { tr[p] = max(tr[p << 1], tr[p << 1 | 1]); } void pushdown(int p) { if (lz[p]) { lz[p << 1] = lz[p << 1 | 1] = lz[p]; lz[p] = 0; tr[p << 1] = tr[p << 1 | 1] = tr[p]; } } pair<int, int> query(int p, int l, int r, int ll, int rr) { if (ll <= l && rr >= r) { return tr[p]; } pushdown(p); int mid = l + r >> 1; pair<int, int> res = {0, -1}; if (ll <= mid) res = max(query(p << 1, l, mid, ll, rr), res); if (rr > mid) res = max(query(p << 1 | 1, mid + 1, r, ll, rr), res); return res; } void update(int p, int l, int r, int ll, int rr, pair<int, int> res) { if (ll <= l && rr >= r) { tr[p] = res; lz[p] = 1; return; } pushdown(p); int mid = l + r >> 1; if (ll <= mid) update(p << 1, l, mid, ll, rr, res); if (rr > mid) update(p << 1 | 1, mid + 1, r, ll, rr, res); pushup(p); } int main() { int n, t; cin >> n >> t; for (int i = 1; i <= t; i++) { cin >> id[i] >> l[i] >> r[i]; b[i * 2 - 1] = l[i]; b[i * 2] = r[i]; } sort(b + 1, b + 1 + t * 2); int len = unique(b + 1, b + 1 + t * 2) - b - 1; build(1, 1, len); for (int i = 1; i <= t; i++) { l[i] = lower_bound(b + 1, b + 1 + len, l[i]) - b; r[i] = lower_bound(b + 1, b + 1 + len, r[i]) - b; vec[id[i]].push_back({l[i], r[i]}); } for (int i = 1; i <= n; i++) { pair<int, int> mx = {0, -1}; for (auto tt : vec[i]) { mx = max(mx, query(1, 1, len, tt.first, tt.second)); } mx.first++; path[i] = mx.second; mx.second = i; for (auto tt : vec[i]) { update(1, 1, len, tt.first, tt.second, mx); } } pair<int, int> ans = query(1, 1, len, 1, len); int u = ans.second; int aa = n; while (u != -1) { st[u] = 1; aa--; u = path[u]; } cout << aa << endl; for (int i = 1; i <= n; i++) { if (!st[i]) cout << i << ; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 10:19:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in1.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
|
//name : file_writer
//tag : c components
//input : input_a:16
//source_file : file_writer.c
///===========
///
///*Created by C2CHIP*
`timescale 1ns/1ps
module file_writer(input_a,input_a_stb,clk,rst,input_a_ack);
integer file_count;
integer output_file_0;
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
reg s_input_a_ack;
reg state;
reg [63:0] value;
initial
begin
output_file_0 = $fopen("resp_z");
$fclose(output_file_0);
end
always @(posedge clk)
begin
case(state)
0:
begin
s_input_a_ack <= 1'b1;
if (s_input_a_ack && input_a_stb) begin
value <= input_a;
s_input_a_ack <= 1'b0;
state <= 1;
end
end
1:
begin
output_file_0 = $fopena("resp_z");
$fdisplay(output_file_0, "%d", value[63:32]);
$fdisplay(output_file_0, "%d", value[31:0]);
$fclose(output_file_0);
state <= 0;
end
endcase
if (rst == 1'b1) begin
state <= 0;
s_input_a_ack <= 0;
end
end
assign input_a_ack = s_input_a_ack;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int arr[6], i, sum = 0; for (i = 0; i < 5; i++) { scanf( %d , &arr[i]); sum = sum + arr[i]; } if (sum == 0) { printf( -1 n ); } else if (sum % 5 == 0) { printf( %d , sum / 5); } else { printf( -1 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int MAXN = 2e5 + 51; long long int n, r; long long int prefix[MAXN], f[MAXN]; inline long long int read() { register long long int num = 0, neg = 1; register char ch = getchar(); while (!isdigit(ch) && ch != - ) { ch = getchar(); } if (ch == - ) { neg = -1; ch = getchar(); } while (isdigit(ch)) { num = (num << 3) + (num << 1) + (ch - 0 ); ch = getchar(); } return num * neg; } int main() { n = read(); for (register int i = 1; i <= n; i++) { prefix[i] = prefix[i - 1] + read(); } r = prefix[n]; for (register int i = n - 1; i >= 1; i--) { f[i] = r, r = max(r, prefix[i] - f[i]); } printf( %lld n , f[1]); } |
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_avm_to_ic #(
parameter integer DATA_W = 256,
parameter integer WRITEDATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter ADDR_SHIFT=1 // shift the address?
)
(
// AVM interface
input logic avm_enable,
input logic avm_read,
input logic avm_write,
input logic [WRITEDATA_W-1:0] avm_writedata,
input logic [BURSTCOUNT_W-1:0] avm_burstcount,
input logic [ADDRESS_W-1:0] avm_address,
input logic [BYTEENA_W-1:0] avm_byteenable,
output logic avm_waitrequest,
output logic avm_readdatavalid,
output logic [WRITEDATA_W-1:0] avm_readdata,
output logic avm_writeack, // not a true Avalon signal
// IC interface
output logic ic_arb_request,
output logic ic_arb_enable,
output logic ic_arb_read,
output logic ic_arb_write,
output logic [WRITEDATA_W-1:0] ic_arb_writedata,
output logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
output logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
output logic [BYTEENA_W-1:0] ic_arb_byteenable,
output logic [ID_W-1:0] ic_arb_id,
input logic ic_arb_stall,
input logic ic_wrp_ack,
input logic ic_rrp_datavalid,
input logic [WRITEDATA_W-1:0] ic_rrp_data
);
// The logic for ic_arb_request (below) makes a MAJOR ASSUMPTION:
// avm_write will never be deasserted in the MIDDLE of a write burst
// (read bursts are fine since they are single cycle requests)
//
// For proper burst functionality, ic_arb_request must remain asserted
// for the ENTIRE duration of a burst request, otherwise the burst may be
// interrupted and lead to all sorts of chaos. At this time, LSUs do not
// deassert avm_write in the middle of a write burst, so this assumption
// is valid.
//
// If there comes a time when this assumption is no longer valid,
// logic needs to be added to detect when a burst begins/ends.
assign ic_arb_request = avm_read | avm_write;
assign ic_arb_read = avm_read;
assign ic_arb_write = avm_write;
assign ic_arb_writedata = avm_writedata;
assign ic_arb_burstcount = avm_burstcount;
assign ic_arb_id = {ID_W{1'bx}};
assign ic_arb_enable = avm_enable;
generate
if(ADDR_SHIFT==1)
begin
assign ic_arb_address = avm_address[ADDRESS_W-1:$clog2(DATA_W / 8)];
end
else
begin
assign ic_arb_address = avm_address[ADDRESS_W-$clog2(DATA_W / 8)-1:0];
end
endgenerate
assign ic_arb_byteenable = avm_byteenable;
assign avm_waitrequest = ic_arb_stall;
assign avm_readdatavalid = ic_rrp_datavalid;
assign avm_readdata = ic_rrp_data;
assign avm_writeack = ic_wrp_ack;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 100005; long long t, l, i, j, k, p, q, u, v, n, color[1000005]; string s; vector<long long> zro; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> q; for (l = 1; l <= q; l++) { cin >> n >> k >> s; for (i = 0; i < n; i++) { if (s[i] == 0 ) zro.push_back(i); else color[i] = 1; } u = 0; v = 0; for (i = 0; i < zro.size(); i++) { if (u == n || k == 0) break; for (; u < n; u++) { if (zro[i] < u) break; if (color[u] == 1 && zro[i] - u <= k) { k -= (zro[i] - u); color[zro[i]] = 1; color[u] = 0; swap(s[u], s[zro[i]]); u++; break; } } } cout << s << endl; for (i = 0; i <= n; i++) color[i] = 0; zro.clear(); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:25:47 04/26/2015
// Design Name: register_file
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_register_file.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: register_file
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_register_file;
// Inputs
reg clock;
reg flush;
reg [2:0] read_adr_1;
reg [2:0] read_adr_2;
reg [15:0] write_data;
reg [2:0] write_adr;
reg write_en;
// Outputs
wire [15:0] data_out_1;
wire [15:0] data_out_2;
// Instantiate the Unit Under Test (UUT)
register_file uut (
.clock(clock),
.flush(flush),
.read_adr_1(read_adr_1),
.read_adr_2(read_adr_2),
.write_data(write_data),
.write_adr(write_adr),
.write_en(write_en),
.data_out_1(data_out_1),
.data_out_2(data_out_2)
);
initial begin
// Initialize Inputs
clock = 0;
flush = 0;
read_adr_1 = 0;
read_adr_2 = 0;
write_data = 0;
write_adr = 0;
write_en = 0;
// Wait 100 ns for global reset to finish
//#100;
#1;
write_en = 1;
write_adr = 0;
write_data = 16'h3131;
read_adr_1 = 0;
#2;
write_en = 1;
write_adr = 3;
write_data = 16'h6969;
#2;
write_en = 1;
write_adr = 5;
write_data = 16'h0ff0;
#2;
write_en = 0;
read_adr_1 = 2;
read_adr_2 = 3;
#2;
flush = 1;
#2;
flush = 0;
end
always #10 clock = !clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int OO = 1e9; const double EPS = 1e-9; template <class T> void _db(const char* dbStr, T e) { cout << dbStr << = << e << endl; } template <class T, class... L> void _db(const char* dbStr, T e, L... r) { while (*dbStr != , ) cout << *dbStr++; cout << = << e << , ; _db(dbStr + 1, r...); } template <class S, class T> ostream& operator<<(ostream& o, const map<S, T>& v) { o << [ ; int i = 0; for (const pair<S, T>& pr : v) o << (!i++ ? : , ) << { << pr.first << : << pr.second << } ; return o << ] ; } template <template <class, class...> class S, class T, class... L> ostream& operator<<(ostream& o, const S<T, L...>& v) { o << [ ; int i = 0; for (const auto& e : v) o << (!i++ ? : , ) << e; return o << ] ; } template <class S, class T> ostream& operator<<(ostream& o, const pair<S, T>& pr) { return o << ( << pr.first << , << pr.second << ) ; } ostream& operator<<(ostream& o, const string& s) { for (const char& c : s) o << c; return o; } template <class T> using V = vector<T>; template <class T> using VV = V<V<T>>; template <class T> using VVV = VV<V<T>>; using ll = long long; using pii = pair<int, int>; using vi = V<int>; using vii = V<pii>; using vvi = VV<int>; using mii = map<int, int>; using umii = unordered_map<int, int>; using si = set<int>; using usi = unordered_set<int>; const int MX = 2e5 + 5; int N, M; ll s[5]; vvi A, B; ll sumR[MX], sumC[MX]; int main() { ios::sync_with_stdio(false); cout.precision(10); cin.tie(0); cin >> N >> M; A.assign(N, vi(M)); for (int i = 0; i < N; ++i) { for (int j = 0; j < M; ++j) { cin >> A[i][j]; } } if (max(N, M) <= 2) { ll ans = 0; for (int i = 0; i < N; ++i) { for (int j = 0; j < M; ++j) { ans += A[i][j]; } } cout << ans << n ; return 0; } if (N > M) { B = A; A.assign(M, vi(N)); for (int i = 0; i < N; ++i) { for (int j = 0; j < M; ++j) { A[j][i] = B[i][j]; } } swap(N, M); } for (int i = 0; i < N; ++i) { for (int j = 0; j < M; ++j) { sumR[i] += A[i][j]; sumC[j] += A[i][j]; } } ll ans = 0; ll cand = 0; if (N >= 4) { for (int i = 0; i < N; ++i) { s[0] = sumR[i]; sort(s, s + 5); } for (int i = 1; i < 5; ++i) { cand += s[i]; } ans = max(ans, cand); } true; s[0] = s[1] = s[2] = s[3] = s[4] = 0; if (M >= 4) { for (int i = 0; i < M; ++i) { s[0] = sumC[i]; sort(s, s + 5); } cand = 0; for (int i = 1; i < 5; ++i) { cand += s[i]; } } ans = max(ans, cand); true; if (M >= 3) { for (int i = 0; i < N; ++i) { s[0] = s[1] = s[2] = s[3] = 0; for (int j = 0; j < M; ++j) { s[0] = sumC[j] - A[i][j]; sort(s, s + 4); } cand = 0; for (int j = 1; j < 4; ++j) { cand += s[j]; } ans = max(ans, sumR[i] + cand); } } true; if (N >= 3) { for (int i = 0; i < M; ++i) { s[0] = s[1] = s[2] = s[3] = 0; for (int j = 0; j < N; ++j) { s[0] = sumR[j] - A[j][i]; sort(s, s + 4); } cand = 0; for (int j = 1; j < 4; ++j) { cand += s[j]; } ans = max(ans, sumC[i] + cand); } } true; s[0] = s[1] = s[2] = 0; { for (int i = 0; i < N; ++i) { for (int j = i + 1; j < N; ++j) { s[0] = s[1] = s[2] = 0; cand = 0; for (int k = 0; k < M; ++k) { s[0] = sumC[k] - A[i][k] - A[j][k]; sort(s, s + 3); } ans = max(ans, sumR[i] + sumR[j] + s[1] + s[2]); } } } true; cout << ans << n ; return 0; } |
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