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#include <bits/stdc++.h> using namespace std; int a[105][105], t, m, n, ret, cnt, mn; int main(void) { cin >> t; for (int i = 0; i < t; i++) { ret = 0, cnt = 0, mn = 101; cin >> n >> m; for (int j = 0; j < n; j++) { for (int k = 0; k < m; k++) { cin >> a[j][k]; if (a[j][k] <= 0) cnt++; if (abs(a[j][k]) < mn) mn = abs(a[j][k]); } } for (int j = 0; j < n; j++) { for (int k = 0; k < m; k++) { ret += abs(a[j][k]); } } if (cnt % 2 == 1) ret -= 2 * mn; cout << ret << endl; } return 0; } |
/* A small simple asynchronous transmitter/receiver
For documentation see the wiki pages. */
/*
MIT License
Copyright (c) 2016 Baard Nossum
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
////////////////////////////////////////////////////////////////////////////////
module uartICE40
# (parameter SUBDIV16 = 0, // Examine rx line 16 or 8 times per bit
ADJUSTSAMPLEPOINT = 0 // Set to 1 when bitrate*8/clk < 2 (SUBDIV16 = 0),
) ( // or bitrate*16/clk < 2 (for SUBDIV16 = 1).
input clk, // System clock
input bitxce, // High 1 clock cycle 8 or 16 times per bit
input load, // Time to transmit a byte. Load transmit buffer
input [7:0] d, // Byte to load into transmit buffer
input rxpin, // Connect to receive pin of uart
output txpin, // Connect to INVERTED transmit pin of uart
output txbusy, // Status of transmit. When high do not load
output bytercvd, //Status receive. True 1 clock cycle only
output [1:0] rxst, // Testbench need access to receive state machine
output [7:0] q // Received byte from serial receive/byte buffer
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire loadORtxce; // From rxtxdiv_i of rxtxdiv_m.v
wire rxce; // From rxtxdiv_i of rxtxdiv_m.v
// End of automatics
uarttx_m uarttx_i (/*AUTOINST*/
// Outputs
.txpin (txpin),
.txbusy (txbusy),
// Inputs
.clk (clk),
.load (load),
.loadORtxce (loadORtxce),
.d (d[7:0]));
uartrx_m uartrx_i (/*AUTOINST*/
// Outputs
.bytercvd (bytercvd),
.rxst (rxst[1:0]),
.q (q[7:0]),
// Inputs
.clk (clk),
.rxce (rxce),
.rxpin (rxpin));
rxtxdiv_m #( .ADJUSTSAMPLEPOINT(ADJUSTSAMPLEPOINT),
.SUBDIV16(SUBDIV16))
rxtxdiv_i
(/*AUTOINST*/
// Outputs
.loadORtxce (loadORtxce),
.rxce (rxce),
// Inputs
.clk (clk),
.bitxce (bitxce),
.load (load),
.rxpin (rxpin),
.rxst (rxst[1:0]));
endmodule
////////////////////////////////////////////////////////////////////////////////
module uarttx_m
(
input clk,load,loadORtxce,
input [7:0] d,
output txpin,
output txbusy
);
genvar i;
wire c_txbusy,c_pp;
wire [9:0] c_a,a;
wire [10:1] cy;
SB_LUT4 #(.LUT_INIT(16'haaaa))
ff_i(.O(c_a[9]), .I3(1'b0), .I2(1'b0), .I1(1'b0), .I0(load));
SB_DFFE ff_r( .Q(a[9]), .C(clk), .E(loadORtxce), .D(c_a[9]));
generate
for ( i = 0; i < 9; i = i + 1 ) begin : blk
if ( i == 0 ) begin
SB_LUT4 #(.LUT_INIT(16'h55cc))
shcmb( .O(c_a[i]), .I3(load), .I2(1'b1), .I1(a[i+1]), .I0(1'b0));
SB_CARRY shcy(.CO(cy[i+1]), .CI(1'b0), .I1(1'b1), .I0(a[i+1]));
end else begin
SB_LUT4 #(.LUT_INIT(16'h55cc))
shcmb( .O(c_a[i]), .I3(load), .I2(1'b1), .I1(a[i+1]), .I0(d[i-1]));
SB_CARRY shcy(.CO(cy[i+1]), .CI(cy[i]), .I1(1'b1), .I0(a[i+1]));
end
SB_DFFE r( .Q(a[i]), .C(clk), .E(loadORtxce), .D(c_a[i]));
end
endgenerate
SB_LUT4 #(.LUT_INIT(16'hffaa))
txbusy_i( .O(c_txbusy), .I3(cy[9]), .I2(1'b1), .I1(1'b0), .I0(load));
SB_CARRY msbcy( .CO(cy[10]), .CI(cy[9]), .I1(1'b1), .I0(1'b0));
SB_DFFE txbusy_r( .Q(txbusy), .C(clk), .E(loadORtxce), .D(c_txbusy));
SB_LUT4 #(.LUT_INIT(16'hb888))
pp_i( .O(c_pp), .I3(cy[10]), .I2(a[0]), .I1(load), .I0(txpin));
SB_DFFE pp_r( .Q(txpin), .C(clk), .E(loadORtxce), .D(c_pp) );
endmodule
////////////////////////////////////////////////////////////////////////////////
module uartrxsm_m
(input clk,rxce,rxpin,lastbit,
output bytercvd,
output [1:0] rxst
);
wire [1:0] nxt_rxst;
SB_LUT4 #(.LUT_INIT(16'h5303))
stnxt1_i( .O(nxt_rxst[1]),.I3(rxst[1]),.I2(rxst[0]),.I1(rxpin),.I0(lastbit));
SB_LUT4 #(.LUT_INIT(16'hf300))
stnxt0_i( .O(nxt_rxst[0]), .I3(rxst[1]), .I2(rxst[0]), .I1(rxpin),.I0(1'b0));
SB_DFFE r_st0( .Q(rxst[0]), .C(clk), .E(rxce), .D(nxt_rxst[0]));
SB_DFFE r_st1( .Q(rxst[1]), .C(clk), .E(rxce), .D(nxt_rxst[1]));
SB_LUT4 #(.LUT_INIT(16'h0080))
bytercvd_i( .O(bytercvd), .I3(rxst[1]), .I2(rxst[0]), .I1(rxpin), .I0(rxce));
endmodule
////////////////////////////////////////////////////////////////////////////////
module uartrx_m
(
input clk,rxce,rxpin,
output bytercvd,
output [1:0] rxst,
output [7:0] q
);
genvar i;
wire [7:0] c_sh;
uartrxsm_m rxsm(// Inputs
.lastbit( q[0] ),
/*AUTOINST*/
// Outputs
.bytercvd (bytercvd),
.rxst (rxst[1:0]),
// Inputs
.clk (clk),
.rxce (rxce),
.rxpin (rxpin));
generate
for ( i = 0; i < 8; i = i + 1 ) begin : blk
localparam a = i == 7 ? 16'hbfb0 : 16'h8f80;
SB_LUT4 #(.LUT_INIT(a))
sh( .O(c_sh[i]), .I3(q[i]), .I2(rxst[1]), .I1(rxst[0]),
.I0(i==7 ? rxpin:q[i+1]));
SB_DFFE shreg( .Q(q[i]), .C(clk), .E(rxce), .D(c_sh[i]) );
end
endgenerate
endmodule
////////////////////////////////////////////////////////////////////////////////
module rxtxdiv_m
#( parameter ADJUSTSAMPLEPOINT = 0, SUBDIV16 = 0)
(input clk,bitxce,load,rxpin,
input [1:0] rxst,
output loadORtxce,rxce
);
localparam rstval_lsb = ADJUSTSAMPLEPOINT ? 16'haffa : 16'h0550;
localparam LOOPLIM = SUBDIV16 ? 4 : 3;
wire [LOOPLIM+1:0] cy,rxcy;
wire c_rxce,rst4;
wire [LOOPLIM-1:0] c_txcnt,txcnt,c_rxcnt,rxcnt;
genvar j;
assign cy[0] = 1'b0;
generate
for ( j = 0; j < LOOPLIM; j = j + 1 ) begin : blk0
SB_LUT4 #(.LUT_INIT(16'hc33c)) i_txcnt1(.O(c_txcnt[j]),
.I3(cy[j]), .I2(txcnt[j]), .I1(j==0 ? bitxce:1'b0), .I0(1'b0));
SB_CARRY i_cy1(.CO(cy[j+1]),
.CI(cy[j]), .I1(txcnt[j]), .I0(j==0 ? bitxce:1'b0));
SB_DFF reg1( .Q(txcnt[j]), .C(clk), .D(c_txcnt[j]));
if ( j == LOOPLIM-1 ) begin
SB_LUT4 #(.LUT_INIT(16'hfaaa))
i_txcnt3(.O(loadORtxce),
.I3(cy[j+1]),.I2(bitxce ), .I1(bitxce),.I0(load));
SB_CARRY i_cy3(.CO(rxcy[0]),
.CI(cy[j+1]),.I1(bitxce ), .I0(bitxce));
end
end
endgenerate
generate
for ( j = 0; j < LOOPLIM; j = j + 1 ) begin : blk1
if ( j != LOOPLIM-1) begin
SB_LUT4 #(.LUT_INIT(j == 0 ? rstval_lsb : 16'h0550)) i_rxcnt0
(.O(c_rxcnt[j]), .I3(rxcy[j]), .I2(rxcnt[j]),.I1(1'b0),.I0(rst4));
SB_CARRY i_cy4(.CO(rxcy[j+1]),.CI(rxcy[j]),.I1(rxcnt[j]),.I0(1'b0));
end else begin
SB_LUT4 #(.LUT_INIT(j == (LOOPLIM-1) ? 16'hcffc:16'h0550)) i_rxcntl
(.O(c_rxcnt[j]), .I3(rxcy[j]), .I2(rxcnt[j]),.I1(rst4),.I0(1'b0));
SB_CARRY i_cy4(.CO(rxcy[j+1]),.CI(rxcy[j]),.I1(rxcnt[j]),.I0(rst4));
end
SB_DFF reg4( .Q(rxcnt[j]), .C(clk), .D(c_rxcnt[j]));
if ( j == LOOPLIM-1 ) begin
SB_LUT4 #(.LUT_INIT(16'h0055)) i_rst
(.O(rst4), .I3(rxst[1]), .I2(1'b0),.I1(bitxce), .I0(rxst[0]));
SB_CARRY i_andcy
(.CO(rxcy[j+2]),.CI(rxcy[j+1]),.I1(1'b0),.I0(bitxce));
SB_LUT4 #(.LUT_INIT(16'hfe30)) i_rxce
(.O(c_rxce), .I3(rxcy[j+2]),.I2(rxpin),.I1(rxst[1]),.I0(rxst[0]));
SB_DFF regrxce( .Q(rxce), .C(clk), .D(c_rxce));
end
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "./fromrefdesign/" )
// verilog-library-files:("../../../PROJ/iCE_simlib/iCE_simlib.v" )
// verilog-library-extensions:(".v" )
// End:
|
/**
* Fill the screen ram with initial values.
*/
module screen_init(
clk,
reset,
address,
out,
load
);
input clk;
input reset;
output load;
output [12:0] address; // ram address to write the pixel data
output [15:0] out; // pixel values for ram address in the buffer
reg [15:0] data;
reg [13:0] buffer_addr;
reg [7:0] counter;
//reg [17:0] counter_divider;
reg wren;
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
end else begin
if (counter == 8'd16) begin
counter <= 0;
end
else begin
counter <= counter + 8'd1;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
buffer_addr <= 0;
wren <= 1;
end else if (buffer_addr == 14'd8192) begin
buffer_addr <= 0;
wren <= 0; // write no more
end
else if (counter == 8'd15) begin
buffer_addr <= buffer_addr + 14'd1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
data <= 0;
end
else begin
if (buffer_addr == 14'd0 || buffer_addr == 14'd31
|| buffer_addr == 14'd4111
|| buffer_addr == 14'd8160 || buffer_addr == 14'd8191) begin
//data <= 16'h00_00;
data <= 16'hFF_FF;
end else begin
data <= 16'h00_00;
//data <= 16'hFF_FF;
end
end
end
assign load = wren;
assign address = buffer_addr[12:0];
assign out = data;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_1_V
`define SKY130_FD_SC_HD__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_1_V
|
#include <bits/stdc++.h> using namespace std; int max(int a, int b) { return (a > b) ? a : b; } struct player { int i; int j; int pos; }; int main() { bool firstwon1 = false; bool secondwon1 = false; bool firstwon2 = false, firstwon3 = false, firstwon4 = false; bool secondwon2 = false, secondwon3 = false, secondwon4 = false; int won = 0; player a[2], b[2]; cin >> a[0].i >> a[0].j; cin >> a[1].i >> a[1].j; cin >> b[0].i >> b[0].j; cin >> b[1].i >> b[1].j; if (a[0].i > b[1].j && a[1].j > b[0].i) firstwon1 = true; if (a[0].i < b[1].j && a[1].j < b[0].i) secondwon1 = true; if (a[0].i > b[0].j && a[1].j > b[1].i) firstwon2 = true; if (a[0].i < b[0].j && a[1].j < b[1].i) secondwon2 = true; if (a[1].i > b[1].j && a[0].j > b[0].i) firstwon3 = true; if (a[1].i < b[1].j && a[0].j < b[0].i) secondwon3 = true; if (a[1].i > b[0].j && a[0].j > b[1].i) firstwon4 = true; if (a[1].i < b[0].j && a[0].j < b[1].i) secondwon4 = true; if ((firstwon1 == true && firstwon2 == true) || (firstwon3 == true && firstwon4 == true)) won = 1; if ((secondwon1 == true || secondwon2 == true) && (secondwon3 == true || secondwon4 == true)) won = 2; switch (won) { case 1: { cout << Team 1 n ; break; } case 2: { cout << Team 2 n ; break; } case 0: { cout << Draw n ; break; } } return 0; } |
module test;
parameter PVALUE = 12;
localparam LVALUE = 88;
enum byte unsigned { UVAL[256] } unsignedbyte_enum;
enum byte { SVAL[100] } signedbyte_enum;
enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM
enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM
enum { P[5] = PVALUE, Q, S[3] = LVALUE} par_enum;
enum reg [2:0] { state[8] } bin_enum;
enum integer {IDLE, XX='bx, XY='b01, YY='b10, XZ = 32'h1x2z3xxz} next_state;
int i;
initial begin
// 1. Default anonymous enum data type should be int
// don't know yet how to quickly check this
//
// 1. Checking initialisations
//
// a. If the first name is not assigned it should be zero
if (UVAL0 !== 8'h0 || SVAL0 !== 8'h0)
begin
$display ("FAILED - First un-assigned element of enum type was not zero");
$finish;
end
// b. Checking initials E1 and vr
if (ADD != 10 || REGISTER0 != 1)
begin
$display ("FAILED - First initialised elements of enums E1 and vr were not elaborated properly");
$finish;
end
// A name without a value is automatically assigned and increment of the value of the
// previous name (Section 4.10 LRM)
// c. checking initial values for SUB (0-4) in E1
if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15)
begin
$display ("FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly");
$finish;
end
// c. checking initial values for JMP (6-8) in E1
if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18)
begin
$display ("FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly");
$finish;
end
// c. checking initial values in vr
if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12)
begin
$display ("FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly");
$finish;
end
// c. checking hand-picked values in unsignedbyte_enum
if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207)
begin
$display ("FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly");
$display ("UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d", UVAL23, UVAL91, UVAL138, UVAL207);
$finish;
end
// c. checking hand-picked values in signedbyte_enum
if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87)
begin
$display ("FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly");
$display ("SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d", SVAL7, UVAL91, SVAL19, SVAL87);
$finish;
end
// c. checking final values in unsignedbyte_enum and signedbyte_enum
if (UVAL255 != 255 || SVAL99 != 99)
begin
$display ("FAILED - Initialised final values UVAL and SVAL did not elaborate properly");
$display ("UVAL255 = %0d, SVAL99 = %0d", UVAL255, SVAL99);
$finish;
end
// d. checking xz values in next_state
if (XX !== 'bx || XZ !== 32'h1x2z3xxz)
begin
$display ("FAILED - Initialised x,z values in next_state did not elaborate properly");
$finish;
end
// e. constants elaborated from parameter
if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5)
begin
$display ("FAILED - Initialised values P in par_enum were not elaborated properly");
$finish;
end
// f. constants elaborated from localparam
if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2)
begin
$display ("FAILED - Initialised values S in par_enum were not elaborated properly");
$finish;
end
#1;
// g. checking num method
if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 ||
E1.num != 9 || vr.num != 5 || par_enum.num != 9 )
begin
$display ("FAILED - The num method does not report as expected");
$finish;
end
// h. checking first method
if (unsignedbyte_enum.first != 0 || signedbyte_enum.first != 0 ||
E1.first != 10 || vr.first != 1 || par_enum.first != PVALUE )
begin
$display ("FAILED - The first method does not report as expected");
$finish;
end
// i. checking last method
if (unsignedbyte_enum.last != 255 || signedbyte_enum.last != 99 ||
E1.last != 18 || vr.last != 12 || par_enum.last != LVALUE+2 )
begin
$display ("FAILED - The last method does not report as expected");
$finish;
end
// checking the next method on unsignedbyte_enum
unsignedbyte_enum = unsignedbyte_enum.first;
for (i=1; i<=255; i=i+1) begin
unsignedbyte_enum = unsignedbyte_enum.next;
if (unsignedbyte_enum != i) begin
$display ("FAILED - The next method does not report as expected for unsignedbyte_enum");
$finish;
end
end
unsignedbyte_enum = unsignedbyte_enum.next;
// checking wrap to the first element for signedbyte_enum
if (unsignedbyte_enum != unsignedbyte_enum.first) begin
$display ("FAILED - The next method did not wrap to the first element for unsignedbyte_enum");
$finish;
end
// checking the next method on signedbyte_enum
signedbyte_enum = signedbyte_enum.first;
for (i=1; i<100; i=i+1) begin
signedbyte_enum = signedbyte_enum.next;
if (signedbyte_enum != i) begin
$display ("FAILED - The next method does not report as expected for signedbyte_enum");
$finish;
end
end
signedbyte_enum = signedbyte_enum.next;
// checking wrap to the first element for signedbyte_enum
if (signedbyte_enum != signedbyte_enum.first) begin
$display ("FAILED - The next method did not wrap to the first element for signedbyte_enum");
$finish;
end
// checking the next method on E1
E1 = E1.first;
for (i=E1.first; i<= E1.last; i=i+1) begin
if (E1 != i) begin
$display ("FAILED - The next method does not report as expected for E1");
$finish;
end
E1 = E1.next;
end
// checking wrap to the first element in E1
if (E1 != E1.first) begin
$display ("FAILED - The next method did not wrap to the first element for E1");
$finish;
end
// checking the next method on vr, manual walk
vr = vr.first;
vr = vr.next;
if (vr != 2) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER1");
$finish;
end
vr = vr.next;
if (vr != 10) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER2");
$finish;
end
vr = vr.next;
if (vr != 11) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER3");
$finish;
end
vr = vr.next;
if (vr != 12) begin
$display ("FAILED - The next method does not report as expected for vr in element REGISTER4");
$finish;
end
// checking wrap to the first element in vr
vr = vr.next;
if (vr != vr.first) begin
$display ("FAILED - The next method did not wrap to the first element for vr");
$finish;
end
// checking the next method for bin_enum
bin_enum = bin_enum.first;
for (i=bin_enum.first; i<= bin_enum.last; i = i+1) begin
if (bin_enum != i) begin
$display ("FAILED - The next method does not report as expected for bin_enum");
$finish;
end
bin_enum = bin_enum.next;
end
// checking wrap to the first element in bin_enum
if (bin_enum != bin_enum.first) begin
$display ("FAILED - The next method did not wrap to the first element for bin_enum");
$finish;
end
$display ("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; long long ans; ans = (n - 2) * (n - 2); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int to1[1000010], w[1000010], begin1[1000010], next1[1000010], v[1000010], p[1000010], d[1000010], e; void add(int x, int y, int z) { to1[++e] = y; next1[e] = begin1[x]; begin1[x] = e; w[e] = z; } void ins(int x) { int i; for (i = 30; i >= 0; i--) if ((x >> i) & 1) { if (!p[i]) { p[i] = x; break; } x ^= p[i]; } } void dfs(int x, int now) { int i; d[x] = now; v[x] = 1; for (i = begin1[x]; i; i = next1[i]) { if (!v[to1[i]]) dfs(to1[i], now ^ w[i]); else ins(now ^ w[i] ^ d[to1[i]]); } } int find(int x) { int i; for (i = 30; i >= 0; i--) if ((p[i] ^ x) < x) x = p[i] ^ x; return x; } int main() { int i, u, v, w, n, m; scanf( %d%d , &n, &m); for (i = 1; i <= m; i++) { scanf( %d%d%d , &u, &v, &w); add(u, v, w); add(v, u, w); } dfs(1, 0); printf( %d n , find(d[n])); } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:01 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_sim_netlist.v
// Design : RAT_Mux4x1_10_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Mux4x1_10_0_0,Mux4x1_10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Mux4x1_10,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Mux4x1_10_0_0
(A,
B,
C,
D,
SEL,
X);
input [9:0]A;
input [9:0]B;
input [9:0]C;
input [9:0]D;
input [1:0]SEL;
output [9:0]X;
wire [9:0]A;
wire [9:0]B;
wire [9:0]C;
wire [9:0]D;
wire [1:0]SEL;
wire [9:0]X;
RAT_Mux4x1_10_0_0_Mux4x1_10 U0
(.A(A),
.B(B),
.C(C),
.D(D),
.SEL(SEL),
.X(X));
endmodule
(* ORIG_REF_NAME = "Mux4x1_10" *)
module RAT_Mux4x1_10_0_0_Mux4x1_10
(X,
D,
B,
C,
SEL,
A);
output [9:0]X;
input [9:0]D;
input [9:0]B;
input [9:0]C;
input [1:0]SEL;
input [9:0]A;
wire [9:0]A;
wire [9:0]B;
wire [9:0]C;
wire [9:0]D;
wire [1:0]SEL;
wire [9:0]X;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[0]_INST_0
(.I0(D[0]),
.I1(B[0]),
.I2(C[0]),
.I3(SEL[1]),
.I4(A[0]),
.I5(SEL[0]),
.O(X[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[1]_INST_0
(.I0(D[1]),
.I1(B[1]),
.I2(C[1]),
.I3(SEL[1]),
.I4(A[1]),
.I5(SEL[0]),
.O(X[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[2]_INST_0
(.I0(D[2]),
.I1(B[2]),
.I2(C[2]),
.I3(SEL[1]),
.I4(A[2]),
.I5(SEL[0]),
.O(X[2]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[3]_INST_0
(.I0(D[3]),
.I1(B[3]),
.I2(C[3]),
.I3(SEL[1]),
.I4(A[3]),
.I5(SEL[0]),
.O(X[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[4]_INST_0
(.I0(D[4]),
.I1(B[4]),
.I2(C[4]),
.I3(SEL[1]),
.I4(A[4]),
.I5(SEL[0]),
.O(X[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[5]_INST_0
(.I0(D[5]),
.I1(B[5]),
.I2(C[5]),
.I3(SEL[1]),
.I4(A[5]),
.I5(SEL[0]),
.O(X[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[6]_INST_0
(.I0(D[6]),
.I1(B[6]),
.I2(C[6]),
.I3(SEL[1]),
.I4(A[6]),
.I5(SEL[0]),
.O(X[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[7]_INST_0
(.I0(D[7]),
.I1(B[7]),
.I2(C[7]),
.I3(SEL[1]),
.I4(A[7]),
.I5(SEL[0]),
.O(X[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[8]_INST_0
(.I0(D[8]),
.I1(B[8]),
.I2(C[8]),
.I3(SEL[1]),
.I4(A[8]),
.I5(SEL[0]),
.O(X[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[9]_INST_0
(.I0(D[9]),
.I1(B[9]),
.I2(C[9]),
.I3(SEL[1]),
.I4(A[9]),
.I5(SEL[0]),
.O(X[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_2_V
`define SKY130_FD_SC_LS__OR4BB_2_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4bb_2 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4bb_2 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_2_V
|
#include <bits/stdc++.h> using namespace std; int x, y, a, b, n; void init() { scanf( %d , &n); puts( YES ); for (int i = 1; i <= n; i++) { scanf( %d%d%d%d , &x, &y, &a, &b); printf( %d n , 2 * abs(x % 2) + abs(y % 2) + 1); } } int main() { init(); return 0; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [19:0] a;
wire [17:0] b;
wire [37:0] z;
assign a = (A_WIDTH == 20) ? A :
(A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} :
{{(20 - A_WIDTH){1'b0}}, A};
assign b = (B_WIDTH == 18) ? B :
(B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} :
{{(18 - B_WIDTH){1'b0}}, B};
dsp_t1_20x18x64 _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (4'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
assign Y = z;
endmodule
module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [ 9:0] a;
wire [ 8:0] b;
wire [18:0] z;
assign a = (A_WIDTH == 10) ? A :
(A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} :
{{(10 - A_WIDTH){1'b0}}, A};
assign b = (B_WIDTH == 9) ? B :
(B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} :
{{( 9 - B_WIDTH){1'b0}}, B};
dsp_t1_10x9x32 _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (2'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
assign Y = z;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 7050; int dp[2][maxn]; vector<int> g[2]; int state[2][maxn]; void dfs(int player, int cur, int n) { if (state[player][cur] == 1) return; state[player][cur] = 1; for (int i = 0; i < g[player].size(); i++) { int v = (cur + g[player][i]) % n; if (v == 0) { dp[player][cur] = 1; return; } } int cnt = 0; for (int i = 0; i < g[player].size(); i++) { int v = (cur + g[player][i]) % n; dfs(player ^ 1, v, n); if (dp[player ^ 1][v] == (-1)) { dp[player][cur] = 1; return; } if (dp[player ^ 1][v] == 1) { cnt++; } } if (cnt == g[player].size()) dp[player][cur] = (-1); return; } void WORK(int n) { for (int i = 0; i <= n; i++) dp[0][i] = dp[1][i] = 2; for (int k = 1; k <= 5; k++) { memset(state, 0, sizeof(state)); for (int i = n - 1; i >= 0; i--) { dfs(0, i % n, n); dfs(1, i % n, n); } } } int main() { int n; while (scanf( %d , &n) != EOF) { for (int i = 0; i < 2; i++) { g[i].clear(); int cnt; scanf( %d , &cnt); while (cnt--) { int x; scanf( %d , &x); g[i].push_back(x); } } WORK(n); for (int i = 0; i < 2; i++) { for (int j = 1; j < n; j++) { if (dp[i][j] == 1) printf( Win ); else if (dp[i][j] == (-1)) printf( Lose ); else printf( Loop ); } printf( n ); } } return 0; } |
//==================================================================================================
// Filename : tb_soc.v
// Created On : 2015-05-31 20:25:47
// Last Modified : 2015-05-31 20:50:46
// Revision : 0.1
// Author : Ángel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : SoC testbench
//
//
//==================================================================================================
`include "musb_defines.v"
`timescale 1ns / 100ps
`define cycle 20
`define MEM_ADDR_WIDTH 12
module tb_soc;
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
wire clk_core;
wire clk_bus;
wire rst;
wire halted;
wire [31:0] gpio_a_inout;
wire uart_tx;
wire uart_rx;
//--------------------------------------------------------------------------
// Assigns
//--------------------------------------------------------------------------
assign iport_error = 1'b0; // No errors
assign dport_error = 1'b0; // No errors
//--------------------------------------------------------------------------
// SoC
//--------------------------------------------------------------------------
musoc #(
.SIM_MODE ( "SIM" ),
.ENABLE_HW_MULT ( 1 ),
.ENABLE_HW_DIV ( 1 ),
.ENABLE_HW_CLO_Z ( 1 ),
.BUS_FREQ ( 100 ),
.MEM_ADDR_WIDTH ( 12 )
)
soc(
.clk ( clk_bus ),
.rst ( rst ),
.halted ( halted ),
.gpio_a_inout ( gpio_a_inout[31:0] ),
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
//--------------------------------------------------------------------------
// Monitor
//--------------------------------------------------------------------------
musb_monitor #(
.CORE("SoC")
)
monitor0(
.halt ( halted ),
.if_stall ( soc.musb_core0.if_stall ),
.if_flush ( soc.musb_core0.if_exception_flush ),
.id_stall ( soc.musb_core0.id_stall ),
.id_flush ( soc.musb_core0.id_exception_flush ),
.ex_stall ( soc.musb_core0.ex_stall ),
.ex_flush ( soc.musb_core0.ex_exception_flush ),
.mem_stall ( soc.musb_core0.mem_stall ),
.mem_flush ( soc.musb_core0.mem_exception_flush ),
.wb_stall ( soc.musb_core0.wb_stall ),
.mem_exception_pc ( soc.musb_core0.mem_exception_pc ),
.id_instruction ( soc.musb_core0.id_instruction ),
.wb_gpr_wa ( soc.musb_core0.wb_gpr_wa ),
.wb_gpr_wd ( soc.musb_core0.wb_gpr_wd ),
.wb_gpr_we ( soc.musb_core0.wb_gpr_we ),
.mem_address ( soc.musb_core0.mem_alu_result ),
.mem_data ( soc.musb_core0.mem_mem_store_data ),
.if_exception_ready ( soc.musb_core0.musb_cpzero0.if_exception_ready ),
.id_exception_ready ( soc.musb_core0.musb_cpzero0.id_exception_ready ),
.ex_exception_ready ( soc.musb_core0.musb_cpzero0.ex_exception_ready ),
.mem_exception_ready ( soc.musb_core0.musb_cpzero0.mem_exception_ready ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus ),
.rst ( rst )
);
endmodule
|
//`#start header` -- edit after this line, do not edit this line
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 04/23/2015 at 13:22
// Component: FIFO
module FIFO (
output drq,
input clk,
input [7:0] D,
input load
);
//`#start body` -- edit after this line, do not edit this line
cy_psoc3_dp #(.cy_dpconfig(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_PIN, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_ALU,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) dp(
/* input */ .reset(1'b0),
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(3'b0),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(load),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(drq),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0), // Carry in from previous stage
/* output */ .co(), // Carry out to next stage
/* input */ .sir(1'b0), // Shift in from right side
/* output */ .sor(), // Shift out to right side
/* input */ .sil(1'b0), // Shift in from left side
/* output */ .sol(), // Shift out to left side
/* input */ .msbi(1'b0), // MSB chain in
/* output */ .msbo(), // MSB chain out
/* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage
/* output [01:00] */ .ceo(), // Compare equal out to next stage
/* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage
/* output [01:00] */ .clo(), // Compare less than out to next stage
/* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage
/* output [01:00] */ .zo(), // Zero detect out to next stage
/* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage
/* output [01:00] */ .fo(), // 0xFF detect out to next stage
/* input [01:00] */ .capi(2'b0), // Software capture from previous stage
/* output [01:00] */ .capo(), // Software capture to next stage
/* input */ .cfbi(1'b0), // CRC Feedback in from previous stage
/* output */ .cfbo(), // CRC Feedback out to next stage
/* input [07:00] */ .pi(D), // Parallel data port
/* output [07:00] */ .po() // Parallel data port
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
#include <bits/stdc++.h> using namespace std; int max(int a, int b) { return a > b ? a : b; } pair<int, int> a[100], ans[1000], p; vector<pair<int, int>> v; int main() { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i + 1; } sort(a, a + n); int i = 0; while (i < k) { if (a[0].first - a[n - 1].first >= -1) break; a[0].first++; a[n - 1].first--; p.first = a[0].second; p.second = a[n - 1].second; v.push_back(p); sort(a, a + n); i++; } cout << a[n - 1].first - a[0].first << << i << endl; for (int k = 0; k < i; k++) { cout << v[k].second << << v[k].first << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_TB_V
`define SKY130_FD_SC_HDLL__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hdll__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_TB_V
|
// Full Adder rtl
module full_adder (a0, b0, c0, a1, b1, c_out, s_out, s2, s3);
// Inputs_top
input a0;
input b0;
input c0;
input a1;
input b1;
// End of inputs_top
// Outputs_top
output c_out;
output s_out;
output s2;
output d1;
output s3;
// End of outputs_top
// Wires
wire c1;
wire c2;
wire s1;
wire d1;
wire c3;
// Some assignments
assign carry_out = c1 | c2;
assign s_out = s1;
//assign d_out = d1;
// Instantiating two half-adders to make the circuit.
// Module instantiation
half_adder u1_half_adder (
// Inputs
.in_x(a0),
.in_y(b0),
// End of inputs
// Outputs
.out_sum(s0),
.out_carry(c1)
// End of outputs
);
// Module instantiation
half_adder u2_half_adder (
// Inputs
.in_x(s0),
.in_y(c0),
// End of inputs
// Outputs
.out_sum(s1),
.out_carry(c2)
// End of outputs
);
// Module instantiation
// Module instantiation
test2 test2 (
// Inputs
.in_1(d1),
.in_2(c3),
.in_3(b1),
// End of inputs
// Outputs
.out_1(s3)
// End of outputs
);
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_tap
*/
module test_axis_tap;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
reg [ID_WIDTH-1:0] tap_axis_tid = 0;
reg [DEST_WIDTH-1:0] tap_axis_tdest = 0;
reg [USER_WIDTH-1:0] tap_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
tap_axis_tdata,
tap_axis_tkeep,
tap_axis_tvalid,
tap_axis_tready,
tap_axis_tlast,
tap_axis_tid,
tap_axis_tdest,
tap_axis_tuser,
m_axis_tready
);
$to_myhdl(
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_tap.lxt");
$dumpvars(0, test_axis_tap);
end
axis_tap #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK)
)
UUT (
.clk(clk),
.rst(rst),
// AXI tap
.tap_axis_tdata(tap_axis_tdata),
.tap_axis_tkeep(tap_axis_tkeep),
.tap_axis_tvalid(tap_axis_tvalid),
.tap_axis_tready(tap_axis_tready),
.tap_axis_tlast(tap_axis_tlast),
.tap_axis_tid(tap_axis_tid),
.tap_axis_tdest(tap_axis_tdest),
.tap_axis_tuser(tap_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; template <typename T> using PQ = priority_queue<T>; template <typename T> using GPQ = priority_queue<T, vector<T>, greater<T>>; template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> p); template <class T> ostream& operator<<(ostream& os, vector<T> v) { os << [ ; for (auto vv : v) os << vv << , ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, set<T> v) { os << [ ; for (auto vv : v) os << vv << , ; return os << ] ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline T sq(T a) { return a * a; } template <typename T> T gcd(T a, T b) { if (a > b) return gcd(b, a); return a == 0 ? b : gcd(b % a, a); } template <typename T, typename U> T mypow(T b, U n) { if (n == 0) return 1; if (n == 1) return b; if (n % 2 == 0) { return mypow(b * b, n / 2); } else { return mypow(b, n - 1) * b; } } ll pcnt(ll b) { return __builtin_popcountll(b); } template <typename T> T iceil(T n, T d) { return (n + d - 1) / d; } map<char, int> hand = {{ R , 0}, { S , 1}, { P , 2}}; class BIT { public: explicit BIT(int N, int v) : V_NUM(N) { data.resize(N); fill(data.begin(), data.end(), v); } ll query(int i) { ll ret = 0; while (i > 0) { ret += data[i]; i -= (i & -i); } return ret; } void update(int i, int v) { while (i < V_NUM) { data[i] += v; i += (i & -i); } } int_fast32_t V_NUM; vector<int> data; }; int main() { int N, Q; string S; cin >> N >> Q >> S; S = $ + S; vector<BIT> bit(3, BIT(N + 1, 0)); vector<set<int>> pos(3); for (int i = 1; i <= N; ++i) { bit[hand[S[i]]].update(i, 1); pos[hand[S[i]]].insert(i); } for (int q = 0; q <= Q; ++q) { int lose = 0; int emp = 0; for (int h = 0; h < 3; ++h) { if (pos[h].empty()) ++emp; } if (emp == 1) { for (int h = 0; h < 3; ++h) { if (pos[h].empty() || pos[(h + 1) % 3].empty()) continue; lose = pos[(h + 1) % 3].size(); } } else if (emp == 0) { for (int h = 0; h < 3; ++h) { int w = (h + 1) % 3, l = (h + 2) % 3; int wpos = *(pos[w].begin()), lpos = *(pos[l].begin()); lose += max(0LL, bit[h].query(wpos) - bit[h].query(lpos)); wpos = *(--pos[w].end()), lpos = *(--pos[l].end()); lose += max(0LL, bit[h].query(lpos) - bit[h].query(wpos)); } } cout << N - lose << n ; if (q == Q) break; int p; char c; cin >> p >> c; bit[hand[S[p]]].update(p, -1); pos[hand[S[p]]].erase(p); bit[hand[c]].update(p, 1); pos[hand[c]].insert(p); S[p] = c; } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module read and write data to the 16x2 Character LCD on the DE2 *
* Board. *
* *
******************************************************************************/
module altera_up_character_lcd_communication (
// Inputs
clk,
reset,
data_in,
enable,
rs,
rw,
display_on,
back_light_on,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for minimum wait between consecutive communications
// if using a 50MHz Clk
parameter CLOCK_CYCLES_FOR_IDLE_STATE = 7'h7F; // Minimum 2500 ns
parameter IC = 7; // Number of bits for idle counter
parameter IDLE_COUNTER_INCREMENT = 7'h01;
parameter CLOCK_CYCLES_FOR_OPERATION_STATE = 3; // Minimum 40 ns
parameter CLOCK_CYCLES_FOR_ENABLE_STATE = 15; // Minimum 230 ns
parameter CLOCK_CYCLES_FOR_HOLD_STATE = 1; // Minimum 10 ns
parameter SC = 4; // Number of bits for states counter
parameter COUNTER_INCREMENT = 4'h1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input rs;
input rw;
input enable;
input display_on;
input back_light_on;
// Bidirectionals
inout [ 7: 0] LCD_DATA;
// Outputs
output reg LCD_ON;
output reg LCD_BLON;
output reg LCD_EN;
output reg LCD_RS;
output reg LCD_RW;
output reg [ 7: 0] data_out; // Stores data read from the LCD
output reg transfer_complete; // Indicates the end of the transfer
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter LCD_STATE_4_IDLE = 3'h4,
LCD_STATE_0_OPERATION = 3'h0,
LCD_STATE_1_ENABLE = 3'h1,
LCD_STATE_2_HOLD = 3'h2,
LCD_STATE_3_END = 3'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [ 7: 0] data_to_lcd;
reg [IC: 1] idle_counter;
reg [SC: 1] state_0_counter;
reg [SC: 1] state_1_counter;
reg [SC: 1] state_2_counter;
// State Machine Registers
reg [ 2: 0] ns_lcd;
reg [ 2: 0] s_lcd;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd <= LCD_STATE_4_IDLE;
else
s_lcd <= ns_lcd;
end
always @(*)
begin
ns_lcd = LCD_STATE_4_IDLE;
case (s_lcd)
LCD_STATE_4_IDLE:
begin
if ((idle_counter == CLOCK_CYCLES_FOR_IDLE_STATE) & enable)
ns_lcd = LCD_STATE_0_OPERATION;
else
ns_lcd = LCD_STATE_4_IDLE;
end
LCD_STATE_0_OPERATION:
begin
if (state_0_counter == CLOCK_CYCLES_FOR_OPERATION_STATE)
ns_lcd = LCD_STATE_1_ENABLE;
else
ns_lcd = LCD_STATE_0_OPERATION;
end
LCD_STATE_1_ENABLE:
begin
if (state_1_counter == CLOCK_CYCLES_FOR_ENABLE_STATE)
ns_lcd = LCD_STATE_2_HOLD;
else
ns_lcd = LCD_STATE_1_ENABLE;
end
LCD_STATE_2_HOLD:
begin
if (state_2_counter == CLOCK_CYCLES_FOR_HOLD_STATE)
ns_lcd = LCD_STATE_3_END;
else
ns_lcd = LCD_STATE_2_HOLD;
end
LCD_STATE_3_END:
begin
if (enable == 1'b0)
ns_lcd = LCD_STATE_4_IDLE;
else
ns_lcd = LCD_STATE_3_END;
end
default:
begin
ns_lcd = LCD_STATE_4_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
begin
LCD_ON <= 1'b0;
LCD_BLON <= 1'b0;
end
else
begin
LCD_ON <= display_on;
LCD_BLON <= back_light_on;
end
end
always @(posedge clk)
begin
if (reset)
begin
LCD_EN <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
data_out <= 8'h00;
transfer_complete <= 1'b0;
end
else
begin
if (s_lcd == LCD_STATE_1_ENABLE)
LCD_EN <= 1'b1;
else
LCD_EN <= 1'b0;
if (s_lcd == LCD_STATE_4_IDLE)
begin
LCD_RS <= rs;
LCD_RW <= rw;
data_to_lcd <= data_in;
end
if (s_lcd == LCD_STATE_1_ENABLE)
data_out <= LCD_DATA;
if (s_lcd == LCD_STATE_3_END)
transfer_complete <= 1'b1;
else
transfer_complete <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
idle_counter <= {IC{1'b0}};
else if (s_lcd == LCD_STATE_4_IDLE)
idle_counter <= idle_counter + IDLE_COUNTER_INCREMENT;
else
idle_counter <= {IC{1'b0}};
end
always @(posedge clk)
begin
if (reset)
begin
state_0_counter <= {SC{1'b0}};
state_1_counter <= {SC{1'b0}};
state_2_counter <= {SC{1'b0}};
end
else
begin
if (s_lcd == LCD_STATE_0_OPERATION)
state_0_counter <= state_0_counter + COUNTER_INCREMENT;
else
state_0_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_1_ENABLE)
state_1_counter <= state_1_counter + COUNTER_INCREMENT;
else
state_1_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_2_HOLD)
state_2_counter <= state_2_counter + COUNTER_INCREMENT;
else
state_2_counter <= {SC{1'b0}};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign LCD_DATA =
(((s_lcd == LCD_STATE_1_ENABLE) ||
(s_lcd == LCD_STATE_2_HOLD)) &&
(LCD_RW == 1'b0)) ? data_to_lcd : 8'hzz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 300000; vector<int> g[MAX_N]; int sz[MAX_N]; int x[MAX_N]; int p[MAX_N]; int N; int dfs(int v) { sz[v] = 1; p[v] = N; x[N++] = v; for (int i = 0; i < g[v].size(); i++) { sz[v] += dfs(g[v][i]); } return sz[v]; } int main() { int n, q, a, b; cin >> n >> q; for (int i = 1; i < n; i++) { cin >> a; g[a - 1].push_back(i); } for (int i = 0; i < n; i++) sort(g[i].begin(), g[i].end()); N = 0; dfs(0); for (int i = 0; i < q; i++) { cin >> a >> b; a--; if (sz[a] < b) cout << -1 << endl; else cout << x[p[a] + b - 1] + 1 << endl; } return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iodelay16 #(
parameter ODELAY_VALUE = 30
) (
/* pad -> fabric */
input [15:0] IDATAIN,
output [15:0] DATAOUT,
/* fabric -> pad */
input [15:0] T,
output [15:0] TOUT,
input [15:0] ODATAIN,
output [15:0] DOUT,
/* control pins */
input INC,
input CE,
input RST,
input CAL,
input CLK,
input IOCLK0,
input IOCLK1
);
genvar i;
generate
for(i=0;i<16;i=i+1)
IODELAY2 #(
.DELAY_SRC("IO"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR"),
.ODELAY_VALUE(ODELAY_VALUE)
) idelay (
.IDATAIN(IDATAIN[i]),
.DATAOUT(DATAOUT[i]),
.T(T[i]),
.TOUT(TOUT[i]),
.ODATAIN(ODATAIN[i]),
.DOUT(DOUT[i]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.CAL(CAL)
);
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; string bad; int k, ans = 0; struct node { node *edges[26]; node() { for (int i = 0; i < 26; i++) edges[i] = NULL; } }; void insert(node *trie, string s) { for (int i = 0; i < s.size(); i++) { if (trie->edges[s[i] - a ] == NULL) trie->edges[s[i] - a ] = new node(); trie = trie->edges[s[i] - a ]; } } void dfs(node *trie, int b) { if (b <= k) ans++; for (int i = 0; i < 26; i++) { if (trie->edges[i]) { int add = 0; if (bad[i] == 0 ) add++; dfs(trie->edges[i], b + add); } } } int main() { string s; cin >> s >> bad >> k; node *root = new node(); string t = ; for (int i = s.size() - 1; i >= 0; i--) { t = s[i] + t; insert(root, t); } dfs(root, 0); cout << ans - 1; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_20_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_20_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog wrapper for busdrivernovlp2 with size of 20 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlp2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdrivernovlp2_20 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busdrivernovlp2 base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdrivernovlp2_20 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busdrivernovlp2 base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_20_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_TB_V
`define SKY130_FD_SC_MS__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ms__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_TB_V
|
#include <bits/stdc++.h> using namespace std; int main(int argc, const char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); int c, m, t, r, i, W[301], tot, j; map<int, bool> used; map<int, bool> ends; map<int, bool> G; cin >> m >> t >> r; for (i = 0; i < m; i++) { cin >> W[i]; G[W[i]] = true; } if (r > t) { cout << -1 n ; return 0; } c = 0; tot = 0; for (i = 0; i <= W[m - 1]; i++) { if (G[i] == true) { if (c < r) { for (j = i - 1; j >= i - t && c < r; j--) { if (used[j] == false) { used[j] = true; ends[j + t] = true; c++; tot++; } } } if (c < r) { cout << -1 n ; return 0; } } if (ends[i] == true) c--; } cout << tot << n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; inline long long getint() { long long _x = 0, _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x *= 10, _x += (_tc - 0 ), _tc = getchar(); return _x * _tmp; } inline long long add(long long _x, long long _y, long long _mod = 1000000007LL) { _x += _y; return _x >= _mod ? _x - _mod : _x; } inline long long sub(long long _x, long long _y, long long _mod = 1000000007LL) { _x -= _y; return _x < 0 ? _x + _mod : _x; } inline long long mul(long long _x, long long _y, long long _mod = 1000000007LL) { _x *= _y; return _x >= _mod ? _x % _mod : _x; } long long mypow(long long _a, long long _x, long long _mod) { if (_x == 0) return 1LL; long long _ret = mypow(mul(_a, _a, _mod), _x >> 1, _mod); if (_x & 1) _ret = mul(_ret, _a, _mod); return _ret; } long long mymul(long long _a, long long _x, long long _mod) { if (_x == 0) return 0LL; long long _ret = mymul(add(_a, _a, _mod), _x >> 1, _mod); if (_x & 1) _ret = add(_ret, _a, _mod); return _ret; } inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } int __ = 1, _cs; struct Mat { int n, a[101][101]; Mat(int _n) { n = _n; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) a[i][j] = 0; } Mat operator*(const Mat& he) const { Mat ret(n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) ret.a[i][j] = add(ret.a[i][j], mul(a[i][k], he.a[k][j])); return ret; } Mat operator^(int tms) const { Mat ret(n), tmp(n); for (int i = 0; i < n; i++) { ret.a[i][i] = 1; for (int j = 0; j < n; j++) tmp.a[i][j] = a[i][j]; } while (tms > 0) { if (tms & 1) ret = ret * tmp; tmp = tmp * tmp; tms >>= 1; } return ret; } }; void build() {} int n, l, m, s[1010101], u[1010101], o[1010101]; void init() { n = getint(); l = getint(); m = getint(); for (int i = 0; i < n; i++) s[i] = getint(); for (int i = 0; i < n; i++) u[i] = getint(); for (int i = 0; i < n; i++) o[i] = getint(); } int cnt[111], sc[111], oc[111][111]; void solve() { Mat tmp(m); for (int i = 0; i < n; i++) cnt[u[i] % m]++; for (int i = 0; i < m; i++) for (int j = 0; j < m; j++) { int dlt = (i - j + m) % m; tmp.a[i][j] = cnt[dlt]; } for (int i = 0; i < n; i++) sc[s[i] % m]++; for (int i = 0; i < n; i++) oc[u[i] % m][o[i] % m]++; tmp = tmp ^ (l - 2); int ans = 0; for (int i = 0; i < m; i++) if (sc[i]) for (int j = 0; j < m; j++) for (int k = 0; k < m; k++) { if (oc[j][k] == 0) continue; int tar = (m - (i + j + k) % m) % m; ans = add(ans, mul(sc[i], mul(oc[j][k], tmp.a[tar][0]))); } printf( %d n , ans); } int main() { build(); while (__--) { init(); solve(); } } |
#include <bits/stdc++.h> using namespace std; int dp[5005][15], oo = 1e5; char str[5005]; int solve(int i, int s) { if (str[i] == 0 and s == 2) { return 0; } else if (str[i] == 0 and s != 2) { return oo; } else if (~dp[i][s]) { return dp[i][s]; } else { int ans = 0; if (s == 0) { if (str[i] == a ) { ans = min(solve(i + 1, s), solve(i + 1, 1)); } else { ans = min(solve(i + 1, s) + 1, solve(i + 1, 1)); } } else if (s == 1) { if (str[i] == b ) { ans = min(solve(i + 1, s), solve(i + 1, 2)); } else { ans = min(solve(i + 1, s) + 1, solve(i + 1, 2)); } } else if (s == 2) { if (str[i] == a ) { ans = solve(i + 1, s); } else { ans = solve(i + 1, s) + 1; } } return dp[i][s] = ans; } } int main() { scanf( %s , str); memset(dp, -1, sizeof dp); if (str[1] == 0) { printf( 1 n ); } else { printf( %d n , strlen(str) - solve(0, 0)); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int k, i; cin >> k; int a[12]; for (i = 0; i < 12; i++) cin >> a[i]; sort(a, a + 12); int sum = 0, c = 0; while (sum < k && i > 0) { i--; sum = sum + a[i]; c++; } if (sum >= k) cout << c; else cout << -1 ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_SYMBOL_V
`define SKY130_FD_SC_HS__TAPMET1_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_SYMBOL_V
|
// DEFINES
`define BITS 2 // Bit width of the operands
module bm_dag2_log_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= temp_a & temp_b;
out1 <= c_in & d_in;
end
endmodule
/*---------------------------------------------------------*/
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
out <= a_in & b_in;
end
endmodule
/*---------------------------------------------------------*/
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp2;
a my_a(clock, a_in, b_in, temp);
always @(posedge clock)
begin
temp2 <= a_in & b_in;
out <= a_in ^ temp;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; long double scal(long double x, long double y, long double x1, long double y1) { return x * y1 - x1 * y; } int n, m; int a[20][2], b[20][2]; int aa[20][10], bb[20][10]; int p[10]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i][0] >> a[i][1]; for (int i = 0; i < m; i++) cin >> b[i][0] >> b[i][1]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if ((a[i][0] == b[j][0] && a[i][1] == b[j][1]) || (a[i][1] == b[j][0] && a[i][0] == b[j][1])) continue; if (a[i][0] == b[j][0]) { aa[i][a[i][0]] = 1; bb[j][a[i][0]] = 1; } if (a[i][0] == b[j][1]) { aa[i][a[i][0]] = 1; bb[j][a[i][0]] = 1; } if (a[i][1] == b[j][1]) { aa[i][a[i][1]] = 1; bb[j][a[i][1]] = 1; } if (a[i][1] == b[j][0]) { aa[i][a[i][1]] = 1; bb[j][a[i][1]] = 1; } } } for (int i = 0; i < n; i++) for (int j = 1; j <= 9; j++) if (aa[i][j] == 1) p[j] = 1; int anss = 0; for (int i = 1; i <= 9; i++) anss += p[i]; if (anss == 1) { for (int i = 1; i <= 9; i++) if (p[i]) cout << i; return 0; } int ans1 = 1, ans2 = 1; for (int i = 0; i < n; i++) { int t = 0; for (int j = 1; j <= 9; j++) t += aa[i][j]; if (t > 1) ans1 = 0; } for (int i = 0; i < m; i++) { int t = 0; for (int j = 1; j <= 9; j++) t += bb[i][j]; if (t > 1) ans2 = 0; } if (ans1 && ans2) cout << 0; else cout << -1; } |
/* -----------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -----------------------------------------------------------------------------
*/
module LAG_router (i_flit_in, i_flit_out,
i_cntrl_in, i_cntrl_out,
i_input_full_flag,
clk, rst_n);
`include "LAG_functions.v"
parameter network_x = 4;
parameter network_y = 4;
parameter buf_len = 4;
parameter NT=5; // number of input-output trunks
parameter NPL=4; // number of pl in each trunk
parameter alloc_stages = 1;
// numbers of physical links on entry/exit to network?
parameter router_num_pls_on_entry = 1;
parameter router_num_pls_on_exit = 1;
//==================================================================
// FIFO rec. data from tile/core is full?
output [router_num_pls_on_entry-1:0] i_input_full_flag;
// link data and control
input flit_t i_flit_in [NT-1:0][NPL-1:0];
output flit_t i_flit_out [NT-1:0][NPL-1:0];
input chan_cntrl_t i_cntrl_in [NT-1:0];
output chan_cntrl_t i_cntrl_out [NT-1:0];
input clk, rst_n;
logic [NT-1:0][NPL-1:0] x_pl_status;
logic [NT-1:0][NPL-1:0] x_push;
logic [NT-1:0][NPL-1:0] x_pop;
flit_t x_flit_xbarin [NT-1:0][NPL-1:0];
flit_t x_flit_xbarout [NT-1:0][NPL-1:0];
flit_t x_flit_xbarin_ [NT*NPL-1:0];
flit_t x_flit_xbarout_ [NT*NPL-1:0];
flit_t routed [NT-1:0][NPL-1:0];
logic [NT-1:0][NPL-1:0] flits_out_tail;
logic [NT-1:0][NPL-1:0] flits_out_valid; //for any output channel of each output port
fifov_flags_t x_flags [NT-1:0][NPL-1:0];
logic [NPL-1:0] x_allocated_pl [NT-1:0][NPL-1:0];
logic [NT-1:0][NPL-1:0] x_allocated_pl_valid;
logic [NT-1:0][NPL-1:0][NPL-1:0] x_pl_new;
logic [NT-1:0][NPL-1:0] x_pl_new_valid;
output_port_t x_output_port [NT-1:0][NPL-1:0];
output_port_t x_output_port_reg [NT-1:0][NPL-1:0];
logic [NT*NPL-1:0][NT*NPL-1:0] xbar_select;
logic [NT-1:0][NPL-1:0] pl_request; // request for pl in out trunk from each input pl
logic [NT-1:0][NPL-1:0] allocated_pl_blocked;
flit_t flit_buffer_out [NT-1:0][NPL-1:0];
//
// unrestricted PL free pool/allocation
//
logic [NT-1:0][NPL-1:0] pl_alloc_status; // which output PLs are free to be allocated
logic [NT-1:0][NPL-1:0] pl_allocated; // indicates which PLs were allocated on this clock cycle
logic [NT-1:0][NPL-1:0][NPL-1:0] pl_requested; // which PLs were selected to be requested at each input PL?
//
logic [NT-1:0][NPL-1:0] pl_empty; // is downstream FIFO associated with PL empty?
genvar i,j,k,l;
// *******************************************************************************
// output ports
// *******************************************************************************
generate
for (i=0; i<NT; i++) begin:output_ports1
//
// Flow Control
//
LAG_pl_fc_out #(.num_pls(NPL),
.init_credits(buf_len))
fcout (.flits_valid(flits_out_valid[i]),
.channel_cntrl_in(i_cntrl_in[i]),
.pl_status(x_pl_status[i]),
.pl_empty(pl_empty[i]),
.clk, .rst_n);
//
// Free PL pools
//
if (i==`TILE) begin
//
// may have less than a full complement of PLs on exit from network
//
LAG_pl_free_pool #(.num_pls_local(router_num_pls_on_exit),
.num_pls_global(NPL)
) plfreepool
(.flits_tail(flits_out_tail[i]),
.flits_valid(flits_out_valid[i]),
.pl_alloc_status(pl_alloc_status[i]),
.pl_allocated(pl_allocated[i]),
.pl_empty(pl_empty[i]),
.clk, .rst_n);
end else begin
LAG_pl_free_pool #(.num_pls_local(NPL),
.num_pls_global(NPL)
) plfreepool
(.flits_tail(flits_out_tail[i]),
.flits_valid(flits_out_valid[i]),
.pl_alloc_status(pl_alloc_status[i]),
.pl_allocated(pl_allocated[i]),
.pl_empty(pl_empty[i]),
.clk, .rst_n);
end // else: !if(i==`TILE)
for (j=0; j<NPL; j++) begin:output_channels2
assign flits_out_tail[i][j] = x_flit_xbarout[i][j].control.tail;
assign flits_out_valid[i][j] = x_flit_xbarout[i][j].control.valid;
end
assign i_cntrl_out[i].credits = x_pop[i]; // if you want to register i_cntrl_out[i].credits, comment this line and uncomment lines below
always@(posedge clk) begin
if (!rst_n) begin
//i_cntrl_out[i].credits <= '0;
end else begin
//
// ensure 'credit' is registered before it is sent to the upstream router
//
// send credit corresponding to flit sent from this input port
//i_cntrl_out[i].credits <= x_pop[i];
end
end
end
endgenerate
// *******************************************************************************
// input trunks (pc buffers and PC registers)
// *******************************************************************************
generate
for (i=0; i<router_num_pls_on_entry; i++) begin:plsx
assign i_input_full_flag[i] = x_flags[`TILE][i].full; // TILE input FIFO[i] is full?
end
for (i=0; i<NT; i++) begin:input_ports
// input trunk 'i'
LAG_pl_input_trunk #(.num_pls(NPL),
.buffer_length(buf_len)) inport
(.push(x_push[i]),
.pop(x_pop[i]),
.data_in(i_flit_in[i]),
.data_out(flit_buffer_out[i]),
.flags(x_flags[i]),
.allocated_pl(x_allocated_pl[i]),
.allocated_pl_valid(x_allocated_pl_valid[i]),
.pl_new(x_pl_new[i]),
.pl_new_valid(x_pl_new_valid[i]),
.clk, .rst_n);
for (j=0; j<NPL; j++) begin:allpls2
LAG_route rfn (.flit_in(flit_buffer_out[i][j]), .flit_out(routed[i][j]), .clk, .rst_n);
assign x_push[i][j] = i_flit_in[i][j].control.valid;
assign x_output_port[i][j] = flit_buffer_out[i][j].control.head ? flit_buffer_out[i][j].data[NT-1:0] : x_output_port_reg[i][j];
end
for (j=0; j<NPL; j++) begin:allpls3
always@(posedge clk) begin
if (!rst_n) begin
x_output_port_reg[i][j] <= '0;
end else if (flit_buffer_out[i][j].control.head) begin
x_output_port_reg[i][j] <= flit_buffer_out[i][j].data[NT-1:0];
end
end
end
for (j=0; j<NPL; j++) begin:reqs
//
// PHYSIC-CHANNEL ALLOCATION REQUESTS
//
assign pl_request[i][j]= (LAG_route_valid_input_pl(i,j)) ?
!x_flags[i][j].empty & !x_allocated_pl_valid[i][j] : 1'b0;
assign x_pop[i][j] = !x_flags[i][j].empty & x_allocated_pl_valid[i][j] & ~allocated_pl_blocked[i][j];
end // block: reqs
for (j=0; j<NPL; j++) begin:flit_to_out_valid
always_comb begin
x_flit_xbarin[i][j] = flit_buffer_out[i][j].control.head ? routed[i][j] : flit_buffer_out[i][j];
x_flit_xbarin[i][j].control.valid = x_pop[i][j];
end
end
end // block: input_ports
LAG_pl_status #(.np(NT), .nv(NPL)) vstat (.output_port(x_output_port),
.allocated_pl(x_allocated_pl),
.allocated_pl_valid(x_allocated_pl_valid),
.pl_status(x_pl_status),
.pl_blocked(allocated_pl_blocked));
endgenerate
// ----------------------------------------------------------------------
// physical-channel allocation logic
// ----------------------------------------------------------------------
LAG_pl_allocator #(.buf_len(buf_len), .np(NT), .nv(NPL), .xs(network_x), .ys(network_y),
.alloc_stages(alloc_stages)
)
plalloc
(.req(pl_request),
.output_port(x_output_port),
.pl_new(x_pl_new),
.pl_new_valid(x_pl_new_valid),
.pl_allocated(pl_allocated),
.pl_alloc_status(pl_alloc_status),
.clk, .rst_n);
generate
for (i=0; i<NT; i++) begin: out_ports_xbar_select
for (j=0; j<NPL; j++) begin: out_channels_xbar_select
for (k=0; k<NT; k++) begin: in_ports_xbar_select
for (l=0; l<NPL; l++) begin: in_channels_xbar_select
assign xbar_select[i*NPL+j][k*NPL+l] = x_output_port_reg[k][l][i] & x_allocated_pl[k][l][j];
end
end
end
end
endgenerate
generate
for (i=0; i<NT; i++) begin: in_ports_xbar
for (j=0; j<NPL; j++) begin: in_channels_xbar
assign x_flit_xbarin_[i*NPL+j] = x_flit_xbarin[i][j];
end
end
endgenerate
generate
for (i=0; i<NT; i++) begin: out_ports_xbar
for (j=0; j<NPL; j++) begin: out_channels_xbar
assign x_flit_xbarout[i][j] = x_flit_xbarout_[i*NPL+j];
end
end
endgenerate
// ----------------------------------------------------------------------
// crossbar
// ----------------------------------------------------------------------
LAG_crossbar_oh_select #(.n(NT*NPL)) myxbar
(x_flit_xbarin_, xbar_select, x_flit_xbarout_);
// ----------------------------------------------------------------------
// output port logic
// ----------------------------------------------------------------------
generate
for (i=0; i<NT; i++) begin:outports
for (j=0; j<NPL; j++) begin:outchannels
assign i_flit_out[i][j] = x_flit_xbarout[i][j];
end //block: outchannels
end // block: outports
endgenerate
endmodule // simple_router
|
#include <bits/stdc++.h> using namespace std; int getValue(vector<int> &ai, int n, int sum) { int val = 0; int mval = ai[ai.size() - 1]; for (int i = 1; i <= mval; i++) { if (n * i >= sum) { val = i; break; } } return val; } int main() { int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int n; vector<int> ai; scanf( %d , &n); int sum = 0; for (int j = 0; j < n; j++) { int temp; scanf( %d , &temp); ai.push_back(temp); sum += temp; } sort(ai.begin(), ai.end()); int ret = getValue(ai, n, sum); printf( %d n , ret); } } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n; k = (20.0 + pow(1.0 + 3 * n, 0.5)) / 3.0; while (k--) { if (3 * k * k - 2 * k <= n) break; } n -= 3 * k * k - 2 * k; if (n - k <= 0) { cout << k - 2 * n << << 2 * k << endl; return 0; } n -= k; if (n - k <= 0) { cout << -k - n << << 2 * k - 2 * n << endl; return 0; } n -= k; if (n - k <= 0) { cout << -2 * k + n << << -2 * n << endl; return 0; } n -= k; if (n - k <= 0) { cout << -k + 2 * n << << -2 * k << endl; return 0; } n -= k; if (n - k - 1 <= 0) { cout << k + n << << -2 * k + 2 * n << endl; return 0; } n -= k + 1; cout << 2 * k + 1 - n << << 2 + 2 * n << endl; return 0; } |
`include "config.v"
module fx2_timetag(
fx2_clk,
fx2_flags,
fx2_slwr,
fx2_slrd,
fx2_sloe,
fx2_wu2,
fx2_pktend,
fx2_fd,
fx2_fifoadr,
ext_clk,
delta_chs,
strobe_in,
led
);
input fx2_clk;
input [2:0] fx2_flags;
output fx2_slwr;
output fx2_slrd;
output fx2_sloe;
output fx2_wu2;
output fx2_pktend;
inout [7:0] fx2_fd;
output [1:0] fx2_fifoadr;
input ext_clk;
input [3:0] strobe_in;
output [3:0] delta_chs;
output [1:0] led;
wire clk;
wire cmd_rdy;
wire [7:0] cmd;
wire sample_rdy;
wire [7:0] sample;
wire sample_ack;
wire reply_rdy;
wire [7:0] reply;
wire reply_ack;
wire reply_end;
`ifdef USE_EXT_CLK
wire pll_locked;
altpll0 b2v_inst2(
.inclk0(ext_clk),
.c0(clk),
.locked(pll_locked)
);
`else
assign clk = fx2_clk;
`endif
timetag tagger(
.fx2_clk(fx2_clk),
.data_rdy(sample_rdy),
.data(sample),
.data_ack(sample_ack),
.cmd_wr(cmd_rdy),
.cmd_in(cmd),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end),
.clk(clk),
.strobe_in(strobe_in),
.delta_chs(delta_chs)
);
fx2_bidir fx2_if(
.fx2_clk(fx2_clk),
.fx2_fd(fx2_fd),
.fx2_flags(fx2_flags),
.fx2_slrd(fx2_slrd),
.fx2_slwr(fx2_slwr),
.fx2_sloe(fx2_sloe),
.fx2_wu2(fx2_wu2),
.fx2_pktend(fx2_pktend),
.fx2_fifoadr(fx2_fifoadr),
.sample(sample),
.sample_rdy(sample_rdy),
.sample_ack(sample_ack),
.cmd(cmd),
.cmd_wr(cmd_rdy),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end)
);
led_blinker cmd_rdy_led(
.clk(fx2_clk),
.in(cmd_wr),
.out(led[0])
);
led_blinker sample_rdy_led(
.clk(fx2_clk),
.in(sample_rdy),
.out(led[1])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; std::vector<int> res; std::vector<int> adj[200005]; std::vector<int> DEPTH(200005); std::vector<int> NODENUM(200005); std::vector<int> funct(200005); vector<bool> taken(200005); vector<bool> visited(200005); int dfs(int v, int depth) { int nodeNum = 0; visited[v] = 1; DEPTH[v] = depth; for (int u : adj[v]) { if (!visited[u]) { nodeNum += dfs(u, depth + 1); } } NODENUM[v] = nodeNum; return NODENUM[v] + 1; } long long dfsV2(int v) { visited[v] = 1; long long ans = 0; for (int u : adj[v]) { if (!visited[u]) { if (taken[u]) { ans += (long long)(NODENUM[u] + 1) * DEPTH[u]; } else ans += (long long)dfsV2(u); } } return ans; } bool func(int x, int y) { if (funct[x] > funct[y]) return true; return false; } void solve() { int n, k, x, y, i; cin >> n >> k; for (i = 0; i < n - 1; i++) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } dfs(1, 0); for (i = 1; i <= n; i++) { funct[i] = DEPTH[i] - NODENUM[i]; res.push_back(i); } sort(res.begin(), res.end(), func); for (i = 0; i < k; i++) { taken[res[i]] = 1; } for (i = 0; i < n + 2; i++) { visited[i] = 0; } cout << dfsV2(1) << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 123; char res[maxn][maxn]; int a[maxn]; int n; int sumx, maxy, miny, nowy; int main() { scanf( %d , &n); sumx = maxy = miny = nowy = 0; int flag = 1; for (int i = 0; i < n; ++i) { scanf( %d , a + i); sumx += a[i]; nowy += flag * a[i]; flag = -flag; if (nowy > maxy) maxy = nowy; if (nowy < miny) miny = nowy; } for (int i = 0; i < maxy - miny; ++i) for (int j = 0; j < sumx; ++j) res[i][j] = ; int py = maxy - 1, px = 0; flag = 1; for (int i = 0; i < n; ++i) { for (int j = 0; j < a[i]; ++j) { if (flag == 1) res[py][px] = / ; else res[py][px] = ; px++; if (j != a[i] - 1) py -= flag; } flag = -flag; } for (int i = 0; i < maxy - miny; ++i, puts( )) for (int j = 0; j < sumx; ++j) putchar(res[i][j]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_TB_V
`define SKY130_FD_SC_HS__A222O_TB_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 C1 = 1'b1;
#280 C2 = 1'b1;
#300 VGND = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 C1 = 1'b0;
#440 C2 = 1'b0;
#460 VGND = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VGND = 1'b1;
#540 C2 = 1'b1;
#560 C1 = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VGND = 1'bx;
#700 C2 = 1'bx;
#720 C1 = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hs__a222o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__EINVN_PP_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_PP_BLACKBOX_V
|
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______123.073_____85.928
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________250.000____________0.010
`timescale 1ps/1ps
module clk_gen_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_gen),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_gen;
wire clkfbout_buf_clk_gen;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (4.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (4.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_gen),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_gen),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_gen),
.CLKIN1 (clk_in1_clk_gen),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_gen),
.I (clkfbout_clk_gen));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_gen));
endmodule
|
#include <bits/stdc++.h> #pragma optimization_level 3 #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; const long long N = 1e6 + 5; const long long mod = 1e+9 + 7; const long long INF = 0x7f7f7f7f7f7f7f7f; const int INFi = 0x7f7f7f7f; long long n, k; long long ch(long long first) { long long ans = first; while (first) { first /= k; ans += first; } return (ans >= n); } void bs() { long long l = 1; long long r = 1e9; while (l <= r) { long long mid = (l + r) / 2; if (ch(mid)) r = mid - 1; else l = mid + 1; } cout << (r + 1) << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed; cout << setprecision(10); ; cin >> n >> k; bs(); } |
#include <bits/stdc++.h> using namespace std; const int M = 100010; int n, m; struct road { int to, th; bool f; } in; struct dot { int come_road; int come_point; bool func; } r[M]; vector<road> work[M]; vector<road> not_work[M]; vector<road> rw[M]; vector<road> rnw[M]; bool vis[M]; int d[M]; int broken_road[M]; bool inq[M]; int tot, u; int input() { int ans = 0; char ch; while (1) { ch = getchar(); if (ch == || ch == n ) return ans; ans *= 10; ans += ch - 0 ; } return ans; } void output(int out) { if (out == 0) { putchar( 0 ); return; } char ans[10]; int cnt = 0; while (out) { ans[cnt++] = out % 10 + 0 ; out /= 10; } for (int i = cnt - 1; i >= 0; i--) putchar(ans[i]); } int main() { while (~scanf( %d%d , &n, &m)) { tot = 0; memset(broken_road, 0x3f, sizeof(broken_road)); memset(vis, 0, sizeof(vis)); memset(d, 0x3f, sizeof(d)); for (int i = 1; i <= n; i++) { work[i].clear(); not_work[i].clear(); rw[i].clear(); rnw[i].clear(); } int x, y, fun; getchar(); for (int i = 0; i < m; i++) { x = input(); y = input(); fun = input(); in.to = y; in.th = i; if (!fun) { in.f = 0; not_work[x].push_back(in); in.to = x; rnw[y].push_back(in); } else { tot++; in.f = 1; work[x].push_back(in); in.to = x; rw[y].push_back(in); } } memset(inq, 0, sizeof(inq)); inq[1] = 1; d[1] = 0; queue<int> q; q.push(1); broken_road[1] = 0; while (!q.empty()) { u = q.front(); q.pop(); inq[u] = 0; int v; for (int i = 0; i < work[u].size(); i++) { v = work[u][i].to; if (d[u] + 1 < d[v] || (d[u] + 1 == d[v] && broken_road[u] < broken_road[v])) { d[v] = d[u] + 1; r[v].come_point = u; r[v].come_road = work[u][i].th; r[v].func = 1; broken_road[v] = broken_road[u]; if (!inq[v]) { q.push(v); inq[v] = 1; } } } for (int i = 0; i < rw[u].size(); i++) { v = rw[u][i].to; if (d[u] + 1 < d[v] || (d[u] + 1 == d[v] && broken_road[u] < broken_road[v])) { d[v] = d[u] + 1; r[v].come_point = u; r[v].come_road = rw[u][i].th; r[v].func = 1; broken_road[v] = broken_road[u]; if (!inq[v]) { q.push(v); inq[v] = 1; } } } for (int i = 0; i < not_work[u].size(); i++) { v = not_work[u][i].to; if (d[u] + 1 < d[v] || (d[u] + 1 == d[v] && broken_road[u] + 1 < broken_road[v])) { d[v] = d[u] + 1; r[v].come_point = u; r[v].come_road = not_work[u][i].th; r[v].func = 0; broken_road[v] = broken_road[u] + 1; if (!inq[v]) { q.push(v); inq[v] = 1; } } } for (int i = 0; i < rnw[u].size(); i++) { v = rnw[u][i].to; if (d[u] + 1 < d[v] || (d[u] + 1 == d[v] && broken_road[u] + 1 < broken_road[v])) { d[v] = d[u] + 1; r[v].come_point = u; r[v].come_road = rnw[u][i].th; r[v].func = 0; broken_road[v] = broken_road[u] + 1; if (!inq[v]) { q.push(v); inq[v] = 1; } } } } int p = n; while (p != 1) { vis[r[p].come_road] = 1; if (r[p].func) tot--; else tot++; p = r[p].come_point; } output(tot); puts( ); for (int i = 1; i <= n; i++) { for (int j = 0; j < work[i].size(); j++) { if (!vis[work[i][j].th]) { output(i); putchar( ); output(work[i][j].to); putchar( ); puts( 0 ); } } for (int j = 0; j < not_work[i].size(); j++) { if (vis[not_work[i][j].th]) { output(i); putchar( ); output(not_work[i][j].to); putchar( ); puts( 1 ); } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long x, r, r1, s, s1, pos, pos1, nx = 0; int digits[19], index = 0; cin >> x; pos = 1; do { pos1 = pos; pos *= 10; r = x % pos; s = (x - r) / pos; r1 = r % pos1; s1 = (r - r1) / pos1; digits[index] = s1; index++; } while (s != 0); for (int i = index - 1; i >= 0; i--) { if (!(i == index - 1) || !(digits[i] == 9)) { if (digits[i] > 4) digits[i] = 9 - digits[i]; nx = nx + digits[i] * pos1; } else { nx = nx + digits[i] * pos1; } pos1 /= 10; } cout << nx << endl; return 0; } |
//
// 8192 bytes, 32bit interface
`timescale 1ns/1ps
module bb_ram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [12:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
wire [3:0] dip;
RAMB16_S9_altera ram0 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[7:0] ),
.rden ( en ),
.wren ( we[0] ),
.q ( data_out[7:0] )
);
defparam ram0.altsyncram_component.init_file = "bb_ram0.mif";
RAMB16_S9_altera ram1 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[15:8] ),
.rden ( en ),
.wren ( we[1] ),
.q ( data_out[15:8] )
);
defparam ram1.altsyncram_component.init_file = "bb_ram1.mif";
RAMB16_S9_altera ram2 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[23:16] ),
.rden ( en ),
.wren ( we[2] ),
.q ( data_out[23:16] )
);
defparam ram2.altsyncram_component.init_file = "bb_ram2.mif";
RAMB16_S9_altera ram3 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[31:24] ),
.rden ( en ),
.wren ( we[3] ),
.q ( data_out[31:24] )
);
defparam ram3.altsyncram_component.init_file = "bb_ram3.mif";
endmodule
|
#include <bits/stdc++.h> using namespace std; int stak1[200010], tot1, stak0[200010], tot0; int pre[200010], nex[200010]; char s[200010]; int a[200010]; int n, ans; int stak_ans[200010], tot_ans; int main() { int i, j, k; scanf( %s , s); n = strlen(s); for (i = 0; i < n; i++) a[i + 1] = s[i] == 1 ? 1 : 0; for (i = 1; i <= n; i++) if (a[i]) { if (!tot0) { printf( -1 n ); return 0; } nex[stak0[tot0]] = i; pre[i] = stak0[tot0]; tot0--; stak1[++tot1] = i; } else { if (tot1) { nex[stak1[tot1]] = i; pre[i] = stak1[tot1]; tot1--; } stak0[++tot0] = i; } if (tot1) { printf( -1 n ); return 0; } for (i = 1; i <= n; i++) if (!pre[i]) ans++; printf( %d n , ans); for (i = 1; i <= n; i++) if (!pre[i]) { j = i, tot_ans = 0; while (j) { stak_ans[++tot_ans] = j; j = nex[j]; } printf( %d , tot_ans); for (j = 1; j <= tot_ans; j++) printf( %d , stak_ans[j]); printf( n ); } return 0; } |
`default_nettype none
module gci_std_display_sequencer #(
//Area
parameter P_AREA_H = 640,
parameter P_AREA_V = 480,
parameter P_AREAA_HV_N = 19,
parameter P_MEM_ADDR_N = 23
)(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Req
input wire iIF_VALID,
output wire oIF_BUSY,
input wire [31:0] iIF_DATA,
//Out
output wire oIF_FINISH,
output wire oIF_VALID,
input wire iIF_BUSY,
output wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
output wire [23:0] oIF_DATA
);
/********************************************
Display Clear
********************************************/
localparam P_L_CLEAR_STT_IDLE = 2'h0;
localparam P_L_CLEAR_STT_CLEAR = 2'h1;
localparam P_L_CLEAR_STT_END = 2'h2;
reg [1:0] b_clear_state;
reg [7:0] b_clear_color_r;
reg [7:0] b_clear_color_g;
reg [7:0] b_clear_color_b;
reg [P_AREAA_HV_N-1:0] b_clear_counter;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_clear_state <= P_L_CLEAR_STT_IDLE;
b_clear_color_r <= 8'h0;
b_clear_color_g <= 8'h0;
b_clear_color_b <= 8'h0;
end
else if(iRESET_SYNC)begin
b_clear_state <= P_L_CLEAR_STT_IDLE;
b_clear_color_r <= 8'h0;
b_clear_color_g <= 8'h0;
b_clear_color_b <= 8'h0;
end
else begin
case(b_clear_state)
P_L_CLEAR_STT_IDLE:
begin
if(iIF_VALID)begin
b_clear_state <= P_L_CLEAR_STT_CLEAR;
{b_clear_color_r,
b_clear_color_g,
b_clear_color_b} <= iIF_DATA[23:0];
end
end
P_L_CLEAR_STT_CLEAR:
begin
if(b_clear_counter == (P_AREA_H*P_AREA_V))begin
b_clear_state <= P_L_CLEAR_STT_END;
end
end
P_L_CLEAR_STT_END:
begin
b_clear_state <= P_L_CLEAR_STT_IDLE;
end
default:
begin
b_clear_state <= P_L_CLEAR_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_clear_counter <= {P_AREAA_HV_N{1'b0}};
end
else if(iRESET_SYNC)begin
b_clear_counter <= {P_AREAA_HV_N{1'b0}};
end
else begin
if(b_clear_state == P_L_CLEAR_STT_CLEAR)begin
if(!iIF_BUSY)begin
b_clear_counter <= b_clear_counter + {{P_AREAA_HV_N-1{1'b0}}, 1'b1};
end
end
else begin
b_clear_counter <= {P_AREAA_HV_N{1'b0}};
end
end
end
assign oIF_BUSY = b_clear_state != P_L_CLEAR_STT_IDLE;
assign oIF_FINISH = b_clear_state == P_L_CLEAR_STT_END;
assign oIF_VALID = !iIF_BUSY && (b_clear_state == P_L_CLEAR_STT_CLEAR);
assign oIF_ADDR = b_clear_counter;
assign oIF_DATA = {b_clear_color_r, b_clear_color_g, b_clear_color_b};
endmodule
`default_nettype wire
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: lpm_mult_4_hybr_ref.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_mult_4_hybr_ref (
clock,
dataa,
datab,
result);
input clock;
input [8:0] dataa;
input [7:0] datab;
output [8:0] result;
wire [8:0] sub_wire0;
wire [8:0] result = sub_wire0[8:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 9,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 9;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "9"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "9"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> int n, from[300005], p[300005], dis[300005], a[300005], b[300005]; std::queue<int> que; std::set<int, std::greater<int>> l; void work(int now) { if (now != n) work(from[now]), std::cout << p[now] << ; } void print(int now) { std::cout << dis[now] + 1 << std::endl; work(now); std::cout << 0 << std::endl; exit(0); } signed main() { std::ios::sync_with_stdio(false); std::cin >> n; for (int i = 1; i <= n; ++i) std::cin >> a[i]; for (int i = 1; i <= n; ++i) std::cin >> b[i]; for (int i = 0; i <= n; ++i) l.insert(i); std::fill(dis, dis + n, INT_MAX); que.push(n); while (!que.empty()) { int now = que.front(); que.pop(); if (now - a[now] <= 0) print(now); for (std::set<int>::iterator i = l.lower_bound(now); i != l.end() && now - *i <= a[now]; l.erase(i++)) { int tmp = *i + b[*i]; if (dis[tmp] > dis[now] + 1) dis[tmp] = dis[now] + 1, p[tmp] = *i, from[tmp] = now, que.push(tmp); } } std::cout << -1 << std::endl; return 0; } |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: obc_lower.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module obc_lower (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:15:38 01/18/2017
// Design Name: left_barrel_shifter
// Module Name: /home/aaron/Git Repos/CSE311/lab1_reverse/left_barrel_shifter_tb.v
// Project Name: lab1_reverse
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: left_barrel_shifter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module left_barrel_shifter_tb;
// Inputs
reg [7:0] d_in;
reg [2:0] shift_amount;
// Outputs
wire [7:0] d_out;
// Instantiate the Unit Under Test (UUT)
left_barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
// Initialize Inputs
d_in = 0;
shift_amount = 0;
// Wait 100 ns for global reset to finish
#100;
// Test to shift left by 1
d_in = 8'b01000000;
shift_amount = 1'd1;
#100;
// New Test for shift left by 2
d_in = 8'b00010000;
shift_amount = 3'b010;
#100;
// Final Test to shift left by 4
d_in = 8'b00100000;
shift_amount = 3'b100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; int b[n]; vector<int> c; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } for (int i = 0; i < n; i++) { if (!b[i]) c.push_back(a[i]); } sort(c.rbegin(), c.rend()); int j = 0; for (int i = 0; i < n; i++) { if (b[i]) cout << a[i] << ; else cout << c[j++] << ; } cout << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31;
parameter DATA_DEPTH = 128;
parameter AW = 6;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
module Cosim_TB();
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// TODO
integer i;
initial begin
$display("hello world");
i = $hello(0);
//iverilog specific task for sim exit codes
$finish_and_return(0);
end
endmodule
|
/*
eTeak synthesiser for the Balsa language
Copyright (C) 2012- The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Mahdi Jelodari <> (and others, see AUTHORS)
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
module ectrl(
input iv_l,
output is_l,
output ov_r,
input os_r,
output Es,
output Em,
input clk,
input reset
);
wire ns_l ;
wire L_11 ;
wire L_12 ;
wire L_13 ;
wire L_14 ;
wire L_15 ;
wire L_16 ;
wire nL_14 ;
INV I0 (ns_l, is_l);
INV I1 (nL_14, L_14);
AND2 I2 (Em, iv_l, ns_l);
AND2 I3 (Es, L_12, nL_14);
AND2 I4 (L_13, os_r, ov_r);
AND2 I5 (L_16, L_12, L_14);
OR2 I6 (L_11, iv_l, is_l);
OR2 I7 (L_15, L_12, L_14);
SRLOR_L I8 (L_12, L_11, clk, reset);
SRLOR_L I9 (L_14, L_13, clk, reset);
SRLOR_H I10 (ov_r, L_15, clk, reset);
SRLOR_H I11 (is_l, L_16, clk, reset);
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } inline long long int GCD(long long int x, long long int y) { if (x < y) swap(x, y); if (x == 0) return y; if (y == 0) return x; return GCD(x % y, y); } long long int phi(long long int n) { long long int result = n; for (long long int i = 2; i * i <= n; i++) { if (n % i == 0) { while (n % i == 0) n /= i; result -= result / i; } } if (n > 1) result -= result / n; return result; } long long int power(long long int x, long long int n, long long int mod) { long long int res = 1; x %= mod; while (n) { if (n & 1) { res = ((res * x) % mod + mod) % mod; } x = ((x * x) % mod + mod) % mod; n >>= 1; } return res; } long long int A[105][105]; long long int row[105], col[105], fr[105] = {0}, fc[105] = {0}, cr = 0, cc = 0; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int n, m; cin >> n >> m; for (long long int i = 1; i <= n; i++) { for (long long int j = 1; j <= m; j++) { cin >> A[i][j]; row[i] += A[i][j]; col[j] += A[i][j]; } } while (1) { bool f = true; for (long long int i = 1; i <= n; i++) { if (row[i] < 0) { f = false; fr[i] ^= 1; cr--; if (fr[i]) cr += 2; for (long long int j = 1; j <= m; j++) { row[i] -= (2 * A[i][j]); col[j] -= (2 * A[i][j]); A[i][j] = -A[i][j]; } } } for (long long int j = 1; j <= m; j++) { if (col[j] < 0) { f = false; fc[j] ^= 1; cc--; if (fc[j]) cc += 2; for (long long int i = 1; i <= n; i++) { row[i] -= (2 * A[i][j]); col[j] -= (2 * A[i][j]); A[i][j] = -A[i][j]; } } } if (f) break; } cout << cr << ; for (long long int i = 1; i <= n; i++) { if (fr[i]) cout << i << ; } cout << endl; cout << cc << ; for (long long int j = 1; j <= m; j++) { if (fc[j]) cout << j << ; } cout << endl; } |
// Identifies the sequence 11101
// includes a overlap bit sequence as well
module jfsmMealyWithOverlap(dataout, clock, reset, datain);
output reg dataout;
input clock, reset, datain;
reg[2:0] cs, ns;
parameter a = 3'b000;
parameter b = 3'b001;
parameter c = 3'b010;
parameter d = 3'b011;
parameter e = 3'b100;
parameter f = 3'b101;
always @(posedge clock)
begin
if(reset)
cs <= a;
else
cs <= ns;
end
always @(cs, datain)
begin
case(cs)
a:
begin
if(datain)
ns <= b;
else
ns <= a;
end
b:
begin
if(datain)
ns <= c;
else
ns <= b;
end
c:
begin
if(datain)
ns <= d;
else
ns <= a;
end
d:
begin
if(datain)
ns <= d;
else
ns <= e;
end
e:
begin
if(datain)
ns <= b; // This has to be ns <= a; if we have to consider with overlap
else
ns <= a;
end
endcase
end
// This will assign the correct status to the dataout bit
always @(cs, datain)
begin
if ( cs == e && datain == 1 )
dataout <= 1;
else
dataout <= 0;
end
endmodule
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 3-State Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFTDS.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDS (O, OB, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O, OB;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 B1 (O, I, ts);
notif0 N1 (OB, I, ts);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFTDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
(T => OB) = (0:0:0, 0:0:0,
0:0:0, 0:0:0,
0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; string to_string(string s) { return + s + ; } string to_string(char s) { return string(1, s); } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A> string to_string(A); template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool f = 1; string r = { ; for (const auto& x : v) { if (!f) r += , ; f = 0; r += to_string(x); } return r + } ; } void debug_out() { cout << n ; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cout << << to_string(H); debug_out(T...); } const long long MOD = 1000000007; long long binpow(long long b, long long p) { long long ans = 1; while (p > 0) { if (p & 1) ans = (ans * b) % MOD; b = (b * b) % MOD; p >>= 1; } return ans; } long long modinv(long long x) { return binpow(x, MOD - 2); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, i, l, r; cin >> n >> m; vector<int> a(n), inc(n), dec(n); for (i = 0; i < n; i++) { cin >> a[i]; inc[i] = dec[i] = i; } for (i = n - 2; i >= 0; i--) { if (a[i] <= a[i + 1]) inc[i] = inc[i + 1]; if (a[i] >= a[i + 1]) dec[i] = dec[i + 1]; } while (m--) { cin >> l >> r; l--; r--; if (dec[inc[l]] >= r) cout << Yes n ; else cout << No n ; } } |
#include <bits/stdc++.h> using namespace std; template <class T> void chmin(T &t, T f) { if (t > f) t = f; } template <class T> void chmax(T &t, T f) { if (t < f) t = f; } int INF = (1 << 29); int n, m; int table[8][8]; void init() {} void input() { cin >> n >> m; for (int i = (0); i < (n); i++) for (int j = (0); j < (m); j++) cin >> table[i][j]; } void solve() { int mask = 1 << m; int crt[1 << 8], nxt[1 << 8]; for (int i = (0); i < (mask); i++) crt[i] = INF; crt[0] = 0; for (int i = (0); i < (n); i++) for (int j = (0); j < (m); j++) { for (int k = (0); k < (mask); k++) nxt[k] = INF; for (int k = (0); k < (mask); k++) { if (k & 1) chmin(nxt[k >> 1], crt[k]); if (!(k & 3) && j < m - 1) { int add = (table[i][j] == table[i][j + 1] ? 0 : 1); chmin(nxt[(k >> 1) | 1], crt[k] + add); } if (!(k & 1) && i < n - 1) { int add = (table[i][j] == table[i + 1][j] ? 0 : 1); chmin(nxt[(k >> 1) | (1 << (m - 1))], crt[k] + add); } } swap(crt, nxt); } cout << crt[0] << endl; } int main() { init(); input(); solve(); return 0; } |
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools
// 07/19/06 - Add else to handle x case for o_out (CR 234718).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS (O, I, IB);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
localparam MODULE_NAME = "IBUFDS";
output O;
input I, IB;
wire i_in, ib_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
assign O = o_out;
assign i_in = I;
assign ib_in = IB;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on %s instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", MODULE_NAME, CAPACITANCE);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", MODULE_NAME, IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", MODULE_NAME, IFD_DELAY_VALUE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> struct task { task() : pc(-1), indegree(0), outgoing() {} int pc; int indegree; std::vector<int> outgoing; }; int solve(int pc, std::vector<task> tasks) { std::queue<int> todo[3]; for (__decltype((tasks).begin()) t = (tasks).begin(), t_end = (tasks).end(); t != t_end; ++t) if (t->indegree == 0) todo[t->pc].push(t - tasks.begin()); int time = 0; for (std::size_t solved = 0; solved < tasks.size(); pc = (pc + 1) % 3) { while (!todo[pc].empty()) { int t = todo[pc].front(); for (__decltype((tasks[t].outgoing).begin()) n = (tasks[t].outgoing).begin(), n_end = (tasks[t].outgoing).end(); n != n_end; ++n) { if (--tasks[*n].indegree == 0) todo[tasks[*n].pc].push(*n); } todo[pc].pop(); ++time; ++solved; } ++time; } return time - 1; } int main() { int n; scanf( %d , &n); std::vector<task> tasks(n); for (int i = 0; i < n; ++i) { scanf( %d , &tasks[i].pc); --tasks[i].pc; } for (int i = 0; i < n; ++i) { int k; scanf( %d , &k); while (k--) { int a; scanf( %d , &a); --a; tasks[a].outgoing.push_back(i); ++tasks[i].indegree; } } printf( %d n , std::min(std::min(solve(0, tasks), solve(1, tasks)), solve(2, tasks))); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005, maxl = 200005, maxsg = 60; int n, f, SG, cnt, maxx; int p[maxl], c[maxl], sg[maxl], A[maxn], B[maxn]; bitset<maxl> ok, have[maxsg]; void sieve(int n) { c[1] = 1; for (int i = 2; i <= n; i++) { if (c[i] == 0) p[++cnt] = i, ok[i] = 1; for (int j = 1; j <= cnt; j++) { if (i * p[j] > n) break; c[i * p[j]] = 1; if (c[i] == 0) ok[i * p[j]] = 1; if (i % p[j] == 0) break; } } } int main() { scanf( %d%d , &n, &f); for (int i = 1; i <= n; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); A[i] = y - x - 1, B[i] = z - y - 1; maxx = max(maxx, max(A[i], B[i])); } sieve(maxx), ok[f] = 0, have[0] = ok; for (int i = 1; i <= maxx; i++) { while (have[sg[i]][i]) sg[i]++; have[sg[i]] |= (ok << i); } for (int i = 1; i <= n; i++) SG ^= sg[A[i]] ^ sg[B[i]]; if (SG == 0) puts( Bob nAlice ); else puts( Alice nBob ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x; cin >> x; cout << 25; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; char c; bool ch = false; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> c; if (c == C || c == M || c == Y ) { ch = true; break; } } } if (ch) { cout << #Color << endl; } else { cout << #Black&White << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:42:38 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int const MAX_N = 1e5 + 10; int n, p, l[MAX_N], r[MAX_N]; int get_count(int l, int r) { int ans = 0; if (l % p == 0) ++ans; l -= l % p; r -= r % p; ans += (r - l) / p; return ans; } double get_prob(int a, int b) { long long count = 0; count += 1LL * get_count(l[a], r[a]) * (r[b] - l[b] + 1 - get_count(l[b], r[b])); count += 1LL * get_count(l[b], r[b]) * (r[a] - l[a] + 1 - get_count(l[a], r[a])); count += 1LL * get_count(l[a], r[a]) * get_count(l[b], r[b]); return count * 1.0 / (1LL * (r[a] - l[a] + 1) * (r[b] - l[b] + 1)); } int main() { ios_base::sync_with_stdio(false); cout << fixed << setprecision(12); cin >> n >> p; for (int i = 0; i < n; ++i) cin >> l[i] >> r[i]; double ret = 0; for (int i = 0; i < n; ++i) { int j = (i + 1) % n; ret += 2000.0 * get_prob(i, j); } cout << ret << endl; return 0; } |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// General Round Robin Arbiter ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_conmax_arb.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: wb_conmax_arb.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2002/10/03 05:40:07 rudi
// Fixed a minor bug in parameter passing, updated headers and specification.
//
// Revision 1.1.1.1 2001/10/19 11:01:40 rudi
// WISHBONE CONMAX IP Core
//
//
//
//
//
//
//
`include "wb_conmax_defines.v"
module wb_conmax_arb(clk, rst, req, gnt, next);
input clk;
input rst;
input [7:0] req; // Req input
output [2:0] gnt; // Grant output
input next; // Next Target
///////////////////////////////////////////////////////////////////////
//
// Parameters
//
parameter [2:0]
grant0 = 3'h0,
grant1 = 3'h1,
grant2 = 3'h2,
grant3 = 3'h3,
grant4 = 3'h4,
grant5 = 3'h5,
grant6 = 3'h6,
grant7 = 3'h7;
///////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
reg [2:0] state, next_state;
///////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign gnt = state;
always@(posedge clk or posedge rst)
if(rst) state <= #1 grant0;
else state <= #1 next_state;
///////////////////////////////////////////////////////////////////////
//
// Next State Logic
// - implements round robin arbitration algorithm
// - switches grant if current req is dropped or next is asserted
// - parks at last grant
//
always@(state or req or next)
begin
next_state = state; // Default Keep State
case(state) // synopsys parallel_case full_case
grant0:
// if this req is dropped or next is asserted, check for other req's
if(!req[0] | next)
begin
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
end
grant1:
// if this req is dropped or next is asserted, check for other req's
if(!req[1] | next)
begin
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
end
grant2:
// if this req is dropped or next is asserted, check for other req's
if(!req[2] | next)
begin
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
end
grant3:
// if this req is dropped or next is asserted, check for other req's
if(!req[3] | next)
begin
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
end
grant4:
// if this req is dropped or next is asserted, check for other req's
if(!req[4] | next)
begin
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
end
grant5:
// if this req is dropped or next is asserted, check for other req's
if(!req[5] | next)
begin
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
end
grant6:
// if this req is dropped or next is asserted, check for other req's
if(!req[6] | next)
begin
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
end
grant7:
// if this req is dropped or next is asserted, check for other req's
if(!req[7] | next)
begin
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Adrian Wise
//bug1104
module t (input clk);
simple_bus sb_intf(clk);
simple_bus #(.DWIDTH(16)) wide_intf(clk);
mem mem(sb_intf.slave);
cpu cpu(sb_intf.master);
mem memW(wide_intf.slave);
cpu cpuW(wide_intf.master);
endmodule
interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
(input logic clk); // Define the interface
logic req, gnt;
logic [AWIDTH-1:0] addr;
logic [DWIDTH-1:0] data;
modport slave( input req, addr, clk,
output gnt,
input data);
modport master(input gnt, clk,
output req, addr,
output data);
initial begin
if (DWIDTH != 16) $stop;
end
endinterface: simple_bus
module mem(interface a);
logic avail;
always @(posedge a.clk)
a.gnt <= a.req & avail;
initial begin
if ($bits(a.data) != 16) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module cpu(interface b);
endmodule
|
`timescale 1ns / 1ns
`define HALT 5'h1F
module opctb();
reg [7:0] mem [ 2047:0 ];
reg clk, reset_b;
wire [10:0] addr;
wire rnw ;
wire ceb = 1'b0;
wire oeb = !rnw;
wire [7:0] data = ( !ceb & rnw & !oeb ) ? mem[ addr ] : 8'bz ;
// OPC CPU instantiation
opccpu dut0_u (.address(addr), .data(data), .rnw(rnw), .clk(clk), .reset_b(reset_b));
initial
begin
$dumpvars;
$readmemh("test.hex", mem); // Problems with readmemb - use readmemh for now
clk = 0;
reset_b = 0;
#1005 reset_b = 1;
#180000000 $finish;
end
// Simple negedge synchronous memory to avoid messing with delays initially
always @ (negedge clk)
if (!rnw && !ceb && oeb && reset_b)
mem[addr] <= data;
always
begin
#500 clk = !clk;
//$display("%4x %2x %x", dut0_u.PC_q, dut0_u.ACC_q, dut0_u.LINK_q);
end
// Always stop simulation on encountering the halt pseudo instruction
always @ (negedge clk)
if (dut0_u.IR_q== `HALT)
begin
$display("Simulation terminated with halt instruction at time", $time);
$writememh("test.vdump",mem);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 100000 + 5; int N; map<int, int> Numbers; int main(void) { scanf( %d , &N); if (N % 2) { printf( NO n ); return 0; } for (int i = 0; i < N; i++) { int Number; scanf( %d , &Number); Numbers[Number]++; } while (!Numbers.empty()) { while (!Numbers.begin()->second) Numbers.erase(Numbers.begin()); int Number = Numbers.begin()->first; if (N == 2) { if (Numbers[Number + 1] == 1) printf( YES n ); else printf( NO n ); return 0; } if (Numbers[Number + 1] < 2) { printf( NO n ); return 0; } Numbers[Number]--; Numbers[Number + 1]--; N -= 2; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_PP_V |
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for BfbOneWayCtrl
//defines for state names used internally
`define STATE_s_init 0
`define STATE_s_wait 1
`define STATE_s_green 2
`define STATE_s_green_count 3
`define STATE_s_yellow 4
`define STATE_s_yellow_count 5
`define STATE_s_red 6
`define STATE_s_red_count 7
module FB_BfbOneWayCtrl
(
input wire clk,
//input events
input wire Tick_eI,
input wire SpecialInstr_eI,
input wire BeginSeq_eI,
input wire PedStatusChange_eI,
//output events
output wire DoneSeq_eO,
output wire PedGrant_eO,
output wire LightCtrlChange_eO,
//input variables
input wire HoldGreen_I,
input wire PedRequest_I,
input wire PedRunning_I,
//output variables
output reg LightRed_O = 0,
output reg LightYellow_O = 0,
output reg LightGreen_O = 0,
input reset
);
////BEGIN internal copies of I/O
//input events
wire Tick;
assign Tick = Tick_eI;
wire SpecialInstr;
assign SpecialInstr = SpecialInstr_eI;
wire BeginSeq;
assign BeginSeq = BeginSeq_eI;
wire PedStatusChange;
assign PedStatusChange = PedStatusChange_eI;
//output events
reg DoneSeq;
assign DoneSeq_eO = DoneSeq;
reg PedGrant;
assign PedGrant_eO = PedGrant;
reg LightCtrlChange;
assign LightCtrlChange_eO = LightCtrlChange;
//input variables
reg HoldGreen = 0;
reg PedRequest = 0;
reg PedRunning = 0;
//output variables
reg LightRed = 0;
reg LightYellow = 0;
reg LightGreen = 0;
////END internal copies of I/O
////BEGIN internal vars
reg unsigned [31:0] d = 0;
reg unsigned [31:0] greenTicks = 15000000;
reg unsigned [31:0] yellowTicks = ;
reg unsigned [31:0] redTicks = ;
////END internal vars
//BEGIN STATE variables
reg [2:0] state = `STATE_s_init;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg s_green_alg0_alg_en = 1'b0;
reg s_green_count_alg0_alg_en = 1'b0;
reg s_yellow_alg0_alg_en = 1'b0;
reg s_yellow_count_alg0_alg_en = 1'b0;
reg s_red_alg0_alg_en = 1'b0;
reg s_red_count_alg0_alg_en = 1'b0;
reg LightsRed_alg_en = 1'b0;
reg LightsYellow_alg_en = 1'b0;
reg LightsGreen_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_s_init;
//reset I/O registers
DoneSeq = 1'b0;
PedGrant = 1'b0;
LightCtrlChange = 1'b0;
HoldGreen = 0;
PedRequest = 0;
PedRunning = 0;
LightRed = 0;
LightYellow = 0;
LightGreen = 0;
//reset internal vars
d = 0;
greenTicks = 15000000;
yellowTicks = ;
redTicks = ;
end else begin
//BEGIN clear output events
DoneSeq = 1'b0;
PedGrant = 1'b0;
LightCtrlChange = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
if(SpecialInstr) begin
HoldGreen = HoldGreen_I;
end
if(PedStatusChange) begin
PedRequest = PedRequest_I;
PedRunning = PedRunning_I;
end
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_s_init: begin
if(1) begin
state = `STATE_s_wait;
entered = 1'b1;
end
end
`STATE_s_wait: begin
if(BeginSeq) begin
state = `STATE_s_green;
entered = 1'b1;
end
end
`STATE_s_green: begin
if(1) begin
state = `STATE_s_green_count;
entered = 1'b1;
end
end
`STATE_s_green_count: begin
if(d > greenTicks && HoldGreen == 0 && PedRunning == 0) begin
state = `STATE_s_yellow;
entered = 1'b1;
end else if(Tick) begin
state = `STATE_s_green_count;
entered = 1'b1;
end
end
`STATE_s_yellow: begin
if(1) begin
state = `STATE_s_yellow_count;
entered = 1'b1;
end
end
`STATE_s_yellow_count: begin
if(d > yellowTicks) begin
state = `STATE_s_red;
entered = 1'b1;
end else if(Tick) begin
state = `STATE_s_yellow_count;
entered = 1'b1;
end
end
`STATE_s_red: begin
if(1) begin
state = `STATE_s_red_count;
entered = 1'b1;
end
end
`STATE_s_red_count: begin
if(d > redTicks) begin
state = `STATE_s_wait;
entered = 1'b1;
end else if(Tick) begin
state = `STATE_s_red_count;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
s_green_alg0_alg_en = 1'b0;
s_green_count_alg0_alg_en = 1'b0;
s_yellow_alg0_alg_en = 1'b0;
s_yellow_count_alg0_alg_en = 1'b0;
s_red_alg0_alg_en = 1'b0;
s_red_count_alg0_alg_en = 1'b0;
LightsRed_alg_en = 1'b0;
LightsYellow_alg_en = 1'b0;
LightsGreen_alg_en = 1'b0;
if(entered) begin
case(state)
`STATE_s_init: begin
end
`STATE_s_wait: begin
LightCtrlChange = 1'b1;
DoneSeq = 1'b1;
LightsRed_alg_en = 1'b1;
end
`STATE_s_green: begin
LightCtrlChange = 1'b1;
PedGrant = 1'b1;
LightsGreen_alg_en = 1'b1;
s_green_alg0_alg_en = 1'b1;
end
`STATE_s_green_count: begin
s_green_count_alg0_alg_en = 1'b1;
end
`STATE_s_yellow: begin
LightCtrlChange = 1'b1;
s_yellow_alg0_alg_en = 1'b1;
LightsYellow_alg_en = 1'b1;
end
`STATE_s_yellow_count: begin
s_yellow_count_alg0_alg_en = 1'b1;
end
`STATE_s_red: begin
LightCtrlChange = 1'b1;
s_red_alg0_alg_en = 1'b1;
LightsRed_alg_en = 1'b1;
end
`STATE_s_red_count: begin
s_red_count_alg0_alg_en = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
if(s_green_alg0_alg_en) begin
d = 0;
end
if(s_green_count_alg0_alg_en) begin
if (d <= greenTicks) begin
d = d + 1;
end
end
if(s_yellow_alg0_alg_en) begin
d = 0;
end
if(s_yellow_count_alg0_alg_en) begin
d = d + 1;
end
if(s_red_alg0_alg_en) begin
d = 0;
end
if(s_red_count_alg0_alg_en) begin
d = d + 1;
end
if(LightsRed_alg_en) begin
LightRed = 1;
LightYellow = 0;
LightGreen = 0;
end
if(LightsYellow_alg_en) begin
LightRed = 0;
LightYellow = 1;
LightGreen = 0;
end
if(LightsGreen_alg_en) begin
LightRed = 0;
LightYellow = 0;
LightGreen = 1;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(LightCtrlChange) begin
LightRed_O = LightRed;
LightYellow_O = LightYellow;
LightGreen_O = LightGreen;
end
//END update external output variables
end
end
endmodule |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef SMV
`ifdef SUBDIR
`include "std_ovl_defines.h"
`else
`include "ovl_ported/std_ovl_defines.h"
`endif
`else
`include "std_ovl_defines.h"
`endif
`module ovl_always_on_edge (clock, reset, enable, sampling_event, test_expr, fire, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter edge_type = `OVL_EDGE_TYPE_DEFAULT;
//OVL_POSEDGE = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input sampling_event, test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
output [`OVL_FIRE_WIDTH-1:0] fire_comb;
// Parameters that should not be edited
parameter assert_name = "OVL_ALWAYS_ON_EDGE";
`ifdef SMV
`ifdef SUBDIR
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_init.h"
`else
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_init.h"
`endif
`else
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_task.h"
`include "ovl_ported/std_ovl_init.h"
`endif
`ifdef OVL_VERILOG
`ifdef SMV
`ifdef SUBDIR
`include "vlog95/ovl_always_on_edge_logic2.v"
`else
`include "ovl_ported/vlog95/ovl_always_on_edge_logic2.v"
`endif
`else
`include "./vlog95/ovl_always_on_edge_logic2.v"
`endif
assign fire = {1'b0, 1'b0, fire_2state};
assign fire_comb = {1'b0, 1'b0, fire_2state_comb};
`endif
//(cks)2state means only 0/1, as opp to X.
//fire_2state is what we care about. properties should be how its affected.
//other 2 wires -used for simulation only. first 2 bits of hte wire for simulation of multi-value output. removed during synthesis.
`ifdef OVL_SVA
`include "./sva05/assert_always_on_edge_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_always_on_edge_psl_logic.v"
`else
`endmodule // ovl_always_on_edge
`endif
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_async_reg
*/
module test_wb_async_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg wbm_clk = 0;
reg wbm_rst = 0;
reg wbs_clk = 0;
reg wbs_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(
wbm_clk,
wbm_rst,
wbs_clk,
wbs_rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i
);
$to_myhdl(
wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o
);
// dump file
$dumpfile("test_wb_async_reg.lxt");
$dumpvars(0, test_wb_async_reg);
end
wb_async_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.wbm_clk(wbm_clk),
.wbm_rst(wbm_rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_clk(wbs_clk),
.wbs_rst(wbs_rst),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
module compact_matrix_vector_multiply #(
parameter C = 4,
parameter R = C
) (
input [C+R-2:0] matrix,
input [C-1:0] vector,
output [R-1:0] out
);
`include "matrix.vh"
matrix_vector_multiply #(C, R) u_mult(expand_matrix(matrix), vector, out);
endmodule
module compact_const_vector_multiply #(
parameter C = 4,
parameter [C-1:0] VECTOR = 0,
parameter R = C
) (
input [C+R-2:0] matrix,
output [R-1:0] out
);
`include "matrix.vh"
const_vector_multiply #(R, VECTOR, C) u_mult(expand_matrix(matrix), out);
endmodule
module compact_const_matrix_multiply #(
parameter C = 4,
parameter R = C,
parameter [C+R-2:0] MATRIX = 0
) (
input [C-1:0] vector,
output [R-1:0] out
);
`include "matrix.vh"
const_matrix_multiply #(.C(R), .MATRIX(expand_matrix(MATRIX)), .R(C)) u_mult(vector, out);
endmodule
module matrix_vector_multiplyT #(
parameter C = 4,
parameter R = C
) (
input [R*C-1:0] matrix,
input [R-1:0] vector,
output [C-1:0] out
);
`include "matrix.vh"
matrix_vector_multiply #(R, C) u_mult(rotate_matrix(matrix), vector, out);
endmodule
module matrix_vector_multiply #(
parameter C = 4,
parameter R = C
) (
input [C*R-1:0] matrix,
input [C-1:0] vector,
output [R-1:0] out
);
genvar i;
for (i = 0; i < R; i = i + 1) begin : mult
assign out[i] = ^(matrix[i*C+:C] & vector);
end
endmodule
/* Reducing terms shouldn't be necessary, but it helps under ISE */
/*
* Each column of the matrix is XOR'd to produce an output.
* Only row indexes with a non-zero vector index are used.
*/
module const_matrix_multiplyT #(
parameter C = 4,
parameter R = C,
parameter [R*C-1:0] MATRIX = 0
) (
input [C-1:0] vector,
output [R-1:0] out
);
`include "matrix.vh"
const_matrix_multiply #(.C(R), .MATRIX(rotate_matrix(MATRIX)), .R(C)) u_mult(vector, out);
endmodule
/*
* Each row of the matrix is XOR'd to produce an output.
* Only columns indexes with a non-zero vector index are used.
*/
module const_matrix_multiply #(
parameter C = 4,
parameter R = C,
parameter [C*R-1:0] MATRIX = 0
) (
input [R-1:0] vector,
output [C-1:0] out
);
parameter LOG2C = $clog2(C+1);
function integer degree;
input [LOG2C-1:0] row;
integer i;
integer c;
begin
c = 0;
for (i = 0; i < C; i = i + 1)
c = c + MATRIX[row*C+i];
degree = c;
end
endfunction
function [LOG2C*C-1:0] idx;
input [LOG2C-1:0] row;
input [LOG2C-1:0] max;
integer i;
integer c;
begin
c = 0;
for (i = 0; i < C; i = i + 1) begin
idx[LOG2C*i+:LOG2C] = c;
if (MATRIX[row*C+i] && c < max)
c = c + 1;
end
end
endfunction
genvar i, j;
for (i = 0; i < R; i = i + 1) begin : OUT
localparam DEGREE = degree(i);
if (DEGREE > 0) begin
localparam [LOG2C*C-1:0] IDXS = idx(i, DEGREE - 1);
wire [DEGREE-1:0] terms;
for (j = 0; j < C; j = j + 1) begin : TERMS
localparam IDX = IDXS[LOG2C*j+:LOG2C];
if (MATRIX[i*C+j])
assign terms[IDX] = vector[j];
end
assign out[i] = ^terms;
end else
assign out[i] = 0;
end
endmodule
/*
* Each column of the matrix is XOR'd to produce an output.
* Only row indexes with a non-zero vector index are used.
*/
module const_vector_multiplyT #(
parameter C = 4,
parameter R = C,
parameter [R-1:0] VECTOR = 0
) (
input [C*R-1:0] matrix,
output [C-1:0] out
);
`include "matrix.vh"
const_vector_multiply #(R, VECTOR, C) u_mult(rotate_matrix(matrix), out);
endmodule
/*
* Each row of the matrix is XOR'd to produce an output.
* Only columns indexes with a non-zero vector index are used.
*/
module const_vector_multiply #(
parameter C = 4,
parameter [C-1:0] VECTOR = 0,
parameter R = C
) (
input [C*R-1:0] matrix,
output [R-1:0] out
);
parameter LOG2C = $clog2(C+1);
function integer degree;
input dummy;
integer i;
integer c;
begin
c = 0;
for (i = 0; i < C; i = i + 1)
c = c + VECTOR[i];
degree = c;
end
endfunction
function [LOG2C*C-1:0] idx;
input [LOG2C-1:0] max;
integer i;
integer c;
begin
c = 0;
for (i = 0; i < C; i = i + 1) begin
idx[LOG2C*i+:LOG2C] = c;
if (VECTOR[i] && c < max)
c = c + 1;
end
end
endfunction
localparam DEGREE = degree(0);
localparam [LOG2C*C-1:0] IDXS = idx(DEGREE - 1);
if (DEGREE) begin
genvar i, j;
for (i = 0; i < R; i = i + 1) begin : ROWS
wire [DEGREE-1:0] terms;
for (j = 0; j < C; j = j + 1) begin : TERMS
localparam IDX = IDXS[LOG2C*j+:LOG2C];
if (VECTOR[j])
assign terms[IDX] = matrix[i*C+j];
end
assign out[i] = ^terms;
end
end else
assign out = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n; double a, d; double p[maxn], t[maxn], v[maxn], s[maxn]; int main() { scanf( %d %lf %lf , &n, &a, &d); for (int i = 0; i < n; i++) scanf( %lf%lf , &t[i], &v[i]), p[i] = t[i] + v[i] / a; s[0] = t[0] + v[0] / a + (d - 0.5 * a * v[0] / a * v[0] / a) / v[0]; if (0.5 * a * v[0] / a * v[0] / a > d) s[0] = min(s[0], t[0] + sqrt((d * 2) / a)); for (int i = 1; i < n; i++) { s[i] = t[i] + v[i] / a + (d - 0.5 * a * v[i] / a * v[i] / a) / v[i]; if (0.5 * a * v[i] / a * v[i] / a > d) s[i] = min(s[i], t[i] + sqrt((d * 2) / a)); s[i] = max(s[i], s[i - 1]); } for (int i = 0; i < n; i++) printf( %.6f n , s[i]); } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int mod = 998244353; void reduce(int &a) { a += a >> 31 & mod; } int Mod(int x) { return x >= mod ? x - mod : x; } long long read() { long long x = 0; int f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) x = x * 10 + (ch ^ 48); return x * f; } void print(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } int qpow(int a, int b) { int ans = 1; for (; b; b >>= 1, a = (long long)a * a % mod) if (b & 1) ans = (long long)ans * a % mod; return ans; } const int N = 800010, G = 3, Gi = 332748118, inv2 = 499122177, img = 86583718; int rev[N], ul[N], gg[20][N]; int G_init() { for (int i = 0; i < 20; i++) { int *G = gg[i]; G[0] = 1; const int gi = G[1] = qpow(3, (mod - 1) / (1 << i + 1)); for (int j = 2; j < (1 << i); j++) G[j] = (long long)G[j - 1] * gi % mod; } return 0; } int I = G_init(); void NTT(int *a, const int n, const int type) { for (int i = 0; i < n; i++) if (i < rev[i]) swap(a[i], a[rev[i]]); int lim = log(n) / log(2) + 0.5; for (int k = 1; k <= lim; k++) { const int l = 1 << k, m = l >> 1, *G = gg[k - 1]; for (int *p = a; p != a + n; p += l) for (int i = 0; i < m; i++) { const int t = (long long)p[i + m] * G[i] % mod; reduce(p[i + m] = p[i] - t), reduce(p[i] += t - mod); } } if (~type) return; const int inv = qpow(n, mod - 2); for (int i = 0; i < n; i++) a[i] = (long long)a[i] * inv % mod; reverse(a + 1, a + n); } void calc_rev(int &n, int &lim, const int m) { n = 1, lim = 0; while (n < m) n <<= 1, lim++; for (int i = 1; i < n; i++) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << lim - 1); } void Mul(const int *a, const int *b, int *c, const int m1, const int m2) { static int x[N], y[N]; int n, lim; calc_rev(n, lim, m1 + m2); for (int i = 0; i < m1; i++) x[i] = a[i]; for (int i = m1; i < n; i++) x[i] = 0; for (int i = 0; i < m2; i++) y[i] = b[i]; for (int i = m2; i < n; i++) y[i] = 0; NTT(x, n, 1), NTT(y, n, 1); for (int i = 0; i < n; i++) c[i] = (long long)x[i] * y[i] % mod; NTT(c, n, -1); for (int i = m1 + m2 - 1; i < n; i++) c[i] = 0; } void Inv(const int *a, int *b, const int len) { static int c[N]; if (len == 1) { b[0] = qpow(a[0], mod - 2); return; } Inv(a, b, len + 1 >> 1); int n, lim; calc_rev(n, lim, len << 1); for (int i = 0; i < n; i++) c[i] = a[i]; for (int i = len; i < n; i++) c[i] = 0; NTT(c, n, 1), NTT(b, n, 1); for (int i = 0; i < n; i++) b[i] = (2 - (long long)c[i] * b[i] % mod + mod) * b[i] % mod; NTT(b, n, -1); for (int i = len; i < n; i++) b[i] = 0; } void Der(const int *a, int *b, const int len) { for (int i = 1; i < len; i++) b[i - 1] = (long long)a[i] * i % mod; b[len - 1] = 0; } void Inte(const int *a, int *b, const int len) { for (int i = len - 1; i; i--) b[i] = (long long)a[i - 1] * qpow(i, mod - 2) % mod; b[0] = 0; } void Ln(const int *a, int *b, const int len) { static int c[N], inv[N]; memset(inv, 0, len << 4); Der(a, c, len), Inv(a, inv, len); Mul(c, inv, c, len, len), Inte(c, b, len); } void Exp(const int *a, int *b, const int len) { static int c[N]; if (len == 1) { b[0] = 1; return; } Exp(a, b, len + 1 >> 1); int lim, n; calc_rev(n, lim, len << 1); Ln(b, c, len); for (int i = 0; i < len; i++) reduce(c[i] = a[i] - c[i]); c[0]++; for (int i = len; i < n; i++) c[i] = 0; Mul(b, c, b, len, len); for (int i = len; i < n; i++) b[i] = 0; } void Power(const int *a, int *b, const int len, const char *k, int m = -1) { int m1 = 0, m2 = 0, m3 = 0; if (~m) m1 = m2 = m3 = m; else { int l = strlen(k); for (int i = 0; i < l; i++) { m1 = ((long long)m1 * 10 + (k[i] ^ 48)) % mod; m2 = ((long long)m2 * 10 + (k[i] ^ 48)) % (mod - 1); } for (int i = 0; i < min(6, l); i++) m3 = m3 * 10 + (k[i] ^ 48); if (a[0] == 0 && m3 >= len) { for (int i = 0; i < len; i++) b[i] = 0; return; } } static int x[N], c[N]; long long t = 0; while (!a[t]) t++; for (int i = 0; i < len; i++) x[i] = a[i + t]; t = t * m1; const int res = qpow(x[0], m2), inv = qpow(x[0], mod - 2); for (int i = 0; i < len; i++) x[i] = (long long)x[i] * inv % mod; Ln(x, b, len); for (int i = 0; i < len; i++) b[i] = (long long)b[i] * m1 % mod; Exp(b, c, len); for (int i = 0; i < len; i++) c[i] = (long long)c[i] * res % mod; for (int i = 0; i < t; i++) b[i] = 0; for (long long i = t; i < len; i++) b[i] = c[i - t]; } int fac[N], ifac[N]; void init(int n) { fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (long long)fac[i - 1] * i % mod; ifac[n] = qpow(fac[n], mod - 2); for (int i = n; i; i--) ifac[i - 1] = (long long)ifac[i] * i % mod; } int n, m, t1[N], t2[N], S[N]; int H[N], H1[N], H2[N], inv[N]; int ans[N]; int main() { n = read(), m = n + 2; init(n + 2); for (int i = 0; i < n + 1; i++) t1[i] = mod - ifac[i + 2]; Inv(t1, S, n + 1); for (int i = 0; i < n; i++) S[i] = S[i + 1]; memset(t1, 0, sizeof(t1)); t1[0] = t1[1] = 1; Ln(t1, t2, m + 2); for (int i = 0; i < m + 1; i++) t1[i] = t2[i + 1]; Inv(t1, H, m + 1); Power(H, H1, m + 1, , n + 1); Der(H, t1, m + 1); Mul(t1, H1, H2, m + 1, m + 1); for (int i = 0; i < m; i++) t1[i] = mod - H[i + 1]; Inv(t1, inv, m); Mul(H1, inv, H1, m, m), Mul(H2, inv, H2, m, m), Mul(H2, inv, H2, m + 1, m); int invn = qpow(n + 1, mod - 2); for (int k = 0; k < n; k++) { int m = n - k + 1; reduce(S[k] -= ((long long)H1[n - m + 2] * m + H2[n - m + 2]) % mod * invn % mod); } S[0]--; memset(t1, 0, sizeof(t1)), memset(t2, 0, sizeof(t2)); for (int i = 0; i < n; i++) if (i & 1) t1[n - i - 1] = mod - ifac[i]; else t1[n - i - 1] = ifac[i]; for (int i = 0; i < n; i++) t2[i] = (long long)S[i] * fac[i] % mod; Mul(t1, t2, ans, n, n); for (int i = 0; i < n; i++) print((long long)ans[i + n - 1] * ifac[i] % mod * fac[n] % mod), putchar( ); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 0 ), c = getchar(); return x * f; } const int N = 505, mod = 1e9 + 7; inline int inc(int x, int y) { x += y - mod; return x + (x >> 31 & mod); } inline int mul(int x, int y) { return 1ll * x * y % mod; } inline void Inc(int &x, int y) { x = inc(x, y); } int n, a[N], f[N][N]; int main() { n = read(); for (int i = 1; i <= n; i++) a[i] = read(), f[i][i] = 1; for (int i = 1; i <= n + 1; i++) f[i][i - 1] = 1; for (int len = 2; len < n; len++) for (int l = 1; l <= n - len + 1; l++) { int r = l + len - 1; f[l][r] = f[l + 1][r]; for (int k = l + 1; k <= r; k++) if (a[k] > a[l]) Inc(f[l][r], mul(f[l + 1][k - 1], f[k][r])); } printf( %d n , f[2][n]); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:21 03/23/2015
// Design Name:
// Module Name: serial_interface
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serial_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
//Serial Signals
output tx,
input rx,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(rst),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(rst),
.tx(tx),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct edge { int v, to, cap, scap; edge(int a, int b, int c) { v = a, to = b, cap = c, scap = c; } edge() {} }; struct rect { int x1, y1, x2, y2; }; struct tri { int y1, y2, x; }; bool operator<(const tri &a, const tri &b) { return a.y1 < b.y1; }; const int N = 1e6 + 7; const int INF = 1e9 + 7; vector<edge> e; vector<int> g[N]; int us[N]; int usbs = 1; int d[N]; int q[N]; int ded[N]; int ptr[N]; vector<rect> fget[N]; int after_bfs = 1; int visb = 1; long long ans = 0; int qh, qt; int s, t; int l; bool bfs() { qh = qt = 0; us[s] = usbs; q[qt++] = s; d[s] = 0; while (qh < qt) { int v = q[qh++]; for (auto c : g[v]) { if (us[e[c].to] != usbs && e[c].cap > 0) { d[e[c].to] = d[v] + 1; us[e[c].to] = usbs; q[qt++] = e[c].to; } } } return (us[t] == usbs++); } int dfs(int v = s, int c = 1e9) { if (!c) { return 0; } if (v == t) { ans += c; return c; } if (ded[v] != after_bfs) { ded[v] = after_bfs; ptr[v] = 0; } for (; ptr[v] < (int)g[v].size(); ptr[v]++) { int ind = g[v][ptr[v]]; if (e[ind].cap > 0 && d[e[ind].to] == d[v] + 1) { int x = dfs(e[ind].to, min(c, e[ind].cap)); if (x) { e[ind].cap -= x; e[ind ^ 1].cap += x; return x; } } } return 0; } void add_edge(int u, int v, int cap) { g[u].push_back(e.size()); e.push_back({u, v, cap}); g[v].push_back(e.size()); e.push_back({v, u, 0}); } long long dinic(int a, int b) { s = a, t = b; while (bfs()) { after_bfs++; while (dfs()) { continue; } } return ans; } vector<int> inds; int lel(int v, int l, int r, int i) { if (r - l == 1) { return v; } else { int m = (l + r) / 2; if (i < m) { return lel(v * 2 + 1, l, m, i); } else { return lel(v * 2 + 2, m, r, i); } } } void get(int v, int l, int r, int tl, int tr) { if (tl >= r || tr <= l) { return; } if (tl >= l && tr <= r) { inds.push_back(v); } else { int tm = (tl + tr) / 2; get(v * 2 + 1, l, r, tl, tm); get(v * 2 + 2, l, r, tm, tr); } } void build(int v, int l, int r, int ax, int bx, int n) { if (r - l == 1) { add_edge(l, ax + v, 1); add_edge(bx + v, n + l, 1); } else { int m = (l + r) / 2; build(v * 2 + 1, l, m, ax, bx, n); build(v * 2 + 2, m, r, ax, bx, n); add_edge(ax + v * 2 + 1, ax + v, INF); add_edge(ax + v * 2 + 2, ax + v, INF); add_edge(bx + v, bx + v * 2 + 1, INF); add_edge(bx + v, bx + v * 2 + 2, INF); } } int main() { vector<rect> fre; int n, q; cin >> n >> q; for (int i = 0; i < q; i++) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; x1--, y1--, x2--, y2--; fget[x2].push_back({x1, y1, x2, y2}); } set<tri> s; s.insert({0, n - 1, 0}); for (int i = 0; i < n; i++) { for (auto c : fget[i]) { auto it = s.lower_bound({c.y1, -1, -1}); vector<tri> gt; if (it != s.begin()) { it--; gt.push_back(*it); it++; } bool b = false; while (it != s.end() && (it->y2 <= c.y2 || !b)) { gt.push_back(*it); it++; if (it != s.end()) { if (it->y2 > c.y2) { gt.push_back(*it); b = true; } } } for (auto d : gt) { if (max(d.y1, c.y1) > min(d.y2, c.y2)) { continue; } s.erase(d); if (c.y1 <= d.y1 && d.y2 <= c.y2) { int a = d.x, b = c.x1 - 1; if (a <= b) { fre.push_back({a, d.y1, b, d.y2}); } } else { if (d.y1 <= c.y1 && c.y2 <= d.y2) { auto was = d; was.y2 = c.y1 - 1; if (was.y1 <= was.y2) { s.insert(was); } was = d; was.y1 = c.y2 + 1; if (was.y1 <= was.y2) { s.insert(was); } int a = d.x, b = c.x1 - 1; if (a <= b) { fre.push_back({a, c.y1, b, c.y2}); } } else if (d.y2 > c.y2) { auto was = d; was.y1 = c.y2 + 1; s.insert(was); int a = d.x, b = c.x1 - 1; if (a <= b) { fre.push_back({a, d.y1, b, c.y2}); } } else if (d.y1 < c.y1) { auto was = d; was.y2 = c.y1 - 1; s.insert(was); int a = d.x, b = c.x1 - 1; if (a <= b) { fre.push_back({a, c.y1, b, d.y2}); } } } } if (c.x2 != n - 1) { s.insert({c.y1, c.y2, c.x2 + 1}); } } } for (auto c : s) { fre.push_back({c.x, c.y1, n - 1, c.y2}); } inds.clear(); get(0, n - 1, n, 0, n); int cnt = inds[0] + 1; for (auto c : fre) { int x1 = c.x1, y1 = c.y1, x2 = c.x2, y2 = c.y2; inds.clear(); get(0, x1, x2 + 1, 0, n); vector<int> a = inds; inds.clear(); get(0, y1, y2 + 1, 0, n); vector<int> b = inds; for (auto c : a) { for (auto d : b) { add_edge(n + n + c, n + n + cnt + d, INF); } } } build(0, 0, n, n + n, n + n + cnt, n); int st = n + n + cnt + cnt, en = n + n + cnt + cnt + 1; for (int i = 0; i < n; i++) { add_edge(st, i, 1); add_edge(i + n, en, 1); } cout << dinic(st, en) << endl; } |
#include <bits/stdc++.h> using namespace std; struct node { long long l, r; int now; vector<pair<int, int> > v; } st[250005 * 4]; int pi, ri, n, N; int p[250005], m[250005]; long long r, sp[250005]; pair<long long, int> d[250005]; queue<int> q; vector<long long> rr; bool vis[250005]; void init(int id, int l, int r) { if (l == r) { st[id].l = rr[l - 1] + 1; st[id].r = rr[l]; int L = lower_bound(d + 2, d + n + 2, make_pair(rr[l - 1] + 1, 0)) - d; int R = upper_bound(d + 2, d + n + 2, make_pair(rr[l], 1000000000)) - d; for (int i = L; i < R; i++) { st[id].v.push_back(make_pair(m[d[i].second], d[i].second)); } sort(st[id].v.begin(), st[id].v.end()); return; } int mid = l + r >> 1; init(id * 2, l, mid); init(id * 2 + 1, mid + 1, r); st[id].l = st[id * 2].l; st[id].r = st[id * 2 + 1].r; st[id].v.insert(st[id].v.begin(), st[id * 2].v.begin(), st[id * 2].v.end()); st[id].v.insert(st[id].v.end(), st[id * 2 + 1].v.begin(), st[id * 2 + 1].v.end()); sort(st[id].v.begin(), st[id].v.end()); } void query(int id, int l, int r, long long L, long long R, int p) { if (R < st[id].l || st[id].r < L) return; if (L <= st[id].l && st[id].r <= R) { int len = st[id].v.size(); while (st[id].now < len && st[id].v[st[id].now].first <= p) { if (!vis[st[id].v[st[id].now].second]) q.push(st[id].v[st[id].now].second); vis[st[id].v[st[id].now].second] = 1; st[id].now++; } return; } int mid = l + r >> 1; query(id * 2, l, mid, L, R, p); query(id * 2 + 1, mid + 1, r, L, R, p); } int main() { long long x, y, xi, yi; scanf( %I64d%I64d%d%I64d%d , &xi, &yi, &p[1], &r, &n); r *= r; sp[1] = r; rr.push_back(r); for (int i = 2; i <= n + 1; i++) { scanf( %I64d%I64d%d%d%I64d , &x, &y, &m[i], &p[i], &r); x -= xi; y -= yi; d[i].first = x * x + y * y; d[i].second = i; r *= r; sp[i] = r; rr.push_back(r); } rr.push_back(0); sort(rr.begin(), rr.end()); rr.resize(unique(rr.begin(), rr.end()) - rr.begin()); N = rr.size() - 1; sort(d + 2, d + n + 2); init(1, 1, N); q.push(1); while (!q.empty()) { int now = q.front(); q.pop(); query(1, 1, N, 1, sp[now], p[now]); } int cnt = 0; for (int i = 2; i <= n + 1; i++) { if (vis[i]) { cnt++; } } printf( %d n , cnt); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int ch = 0, nch = 0; int x; int b; if (n >= m) { b = m; } else { b = n; } for (int i = 0; i < n; i++) { cin >> x; if (x % 2 == 0) { ch++; } else { nch++; } } for (int i = 0; i < m; i++) { cin >> x; if (x % 2 == 0) { ch++; } else { nch++; } } if (nch > ch) { if (ch < b) { cout << ch << endl; } else { cout << b << endl; } } else { if (nch < b) { cout << nch << endl; } else { cout << b << endl; } } return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int main() { int n; cin >> n; vector<vector<int> > xy(n, vector<int>(2)); for (int i = 0; i < n; i++) { cin >> xy[i][0] >> xy[i][1]; } int k = 0; for (int i = 0; i < n - 2; i++) { if (xy[i][0] == xy[i + 1][0]) { if (xy[i][1] < xy[i + 1][1]) { if (xy[i + 1][0] > xy[i + 2][0]) k++; } if (xy[i][1] > xy[i + 1][1]) { if (xy[i + 1][0] < xy[i + 2][0]) k++; } } if (xy[i][1] == xy[i + 1][1]) { if (xy[i][0] < xy[i + 1][0]) { if (xy[i + 1][1] < xy[i + 2][1]) k++; } if (xy[i][0] > xy[i + 1][0]) { if (xy[i + 1][1] > xy[i + 2][1]) k++; } } } cout << k; return 0; } |
module spi
#(parameter N=8,
parameter tope=50000)
(
input [N-1:0] datain,
input en,
input reset,
input clk,
input miso,
output reg [N-1:0] dataout,
output reg done,
output reg mosi,
output reg cs,
output reg sclk
);
integer countd=0;
integer div=0;
reg [N-1:0] datase=0;
reg [N-1:0] datare=0;
reg run=0;
always @(posedge clk)
begin
if(reset)
begin
countd<=0;
sclk<=0;
run<=0;
div<=0;
cs<=1;
done<=0;
dataout<=0;
datase<=0;
datare<=0;
end
else if(en)
begin
run<=1;
cs<=0;
if(done)
begin
run<=0;
dataout<=datare;
end
else if(run)
if(div==tope)
begin
sclk<=~sclk;
div<=0;
if(sclk)
begin
countd<=countd+1;
mosi<=datase[N-1];
if(countd==7)
begin
countd<=0;
done<=1;
end
end
else if(~sclk)
begin
datare<={miso,datare[N-1:1]};
datase<={datase[N-2:0],1'b1};
end
end
else
div<=div+1;
end
else if(~en)
begin
countd<=0;
sclk<=0;
run<=0;
div<=0;
cs<=1;
done<=0;
datase<=datain;
mosi<=datase[N-1];
end
end
endmodule
|
// megafunction wizard: %LPM_AND%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_and
// ============================================================
// File Name: gl_and20.v
// Megafunction Name(s):
// lpm_and
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gl_and20 (
data0,
data1,
data10,
data11,
data12,
data13,
data14,
data15,
data16,
data17,
data18,
data19,
data2,
data3,
data4,
data5,
data6,
data7,
data8,
data9,
result);
input data0;
input data1;
input data10;
input data11;
input data12;
input data13;
input data14;
input data15;
input data16;
input data17;
input data18;
input data19;
input data2;
input data3;
input data4;
input data5;
input data6;
input data7;
input data8;
input data9;
output result;
wire [0:0] sub_wire0;
wire sub_wire22 = data19;
wire sub_wire21 = data18;
wire sub_wire20 = data17;
wire sub_wire19 = data16;
wire sub_wire18 = data15;
wire sub_wire17 = data14;
wire sub_wire16 = data13;
wire sub_wire15 = data12;
wire sub_wire14 = data11;
wire sub_wire13 = data10;
wire sub_wire12 = data9;
wire sub_wire11 = data8;
wire sub_wire10 = data7;
wire sub_wire9 = data6;
wire sub_wire8 = data5;
wire sub_wire7 = data4;
wire sub_wire6 = data3;
wire sub_wire5 = data2;
wire sub_wire4 = data1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire result = sub_wire1;
wire sub_wire2 = data0;
wire [19:0] sub_wire3 = {sub_wire22, sub_wire21, sub_wire20, sub_wire19, sub_wire18, sub_wire17, sub_wire16, sub_wire15, sub_wire14, sub_wire13, sub_wire12, sub_wire11, sub_wire10, sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire2};
lpm_and lpm_and_component (
.data (sub_wire3),
.result (sub_wire0));
defparam
lpm_and_component.lpm_size = 20,
lpm_and_component.lpm_type = "LPM_AND",
lpm_and_component.lpm_width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
// Retrieval info: PRIVATE: GateFunction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: InputAsBus NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WidthInput NUMERIC "1"
// Retrieval info: PRIVATE: nInput NUMERIC "20"
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_AND"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
// Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
// Retrieval info: USED_PORT: data10 0 0 0 0 INPUT NODEFVAL data10
// Retrieval info: USED_PORT: data11 0 0 0 0 INPUT NODEFVAL data11
// Retrieval info: USED_PORT: data12 0 0 0 0 INPUT NODEFVAL data12
// Retrieval info: USED_PORT: data13 0 0 0 0 INPUT NODEFVAL data13
// Retrieval info: USED_PORT: data14 0 0 0 0 INPUT NODEFVAL data14
// Retrieval info: USED_PORT: data15 0 0 0 0 INPUT NODEFVAL data15
// Retrieval info: USED_PORT: data16 0 0 0 0 INPUT NODEFVAL data16
// Retrieval info: USED_PORT: data17 0 0 0 0 INPUT NODEFVAL data17
// Retrieval info: USED_PORT: data18 0 0 0 0 INPUT NODEFVAL data18
// Retrieval info: USED_PORT: data19 0 0 0 0 INPUT NODEFVAL data19
// Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL data2
// Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL data3
// Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL data4
// Retrieval info: USED_PORT: data5 0 0 0 0 INPUT NODEFVAL data5
// Retrieval info: USED_PORT: data6 0 0 0 0 INPUT NODEFVAL data6
// Retrieval info: USED_PORT: data7 0 0 0 0 INPUT NODEFVAL data7
// Retrieval info: USED_PORT: data8 0 0 0 0 INPUT NODEFVAL data8
// Retrieval info: USED_PORT: data9 0 0 0 0 INPUT NODEFVAL data9
// Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
// Retrieval info: CONNECT: @data 0 0 1 0 data0 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 1 data1 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 2 data2 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 3 data3 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 4 data4 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 5 data5 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 6 data6 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 7 data7 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 8 data8 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 9 data9 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 10 data10 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 11 data11 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 12 data12 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 13 data13 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 14 data14 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 15 data15 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 16 data16 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 17 data17 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 18 data18 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 19 data19 0 0 0 0
// Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_and20.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_and20.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_and20.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_and20.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_and20_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gl_and20_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_PP_BLACKBOX_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__EDFXBP_PP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_PP_SYMBOL_V
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module splits video in streams for the DE-series boards. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Video_Stream_Splitter (
// Inputs
clk,
reset,
sync_ready,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready_0,
stream_out_ready_1,
stream_select,
// Bidirectional
// Outputs
sync_data,
sync_valid,
stream_in_ready,
stream_out_data_0,
stream_out_startofpacket_0,
stream_out_endofpacket_0,
stream_out_empty_0,
stream_out_valid_0,
stream_out_data_1,
stream_out_startofpacket_1,
stream_out_endofpacket_1,
stream_out_empty_1,
stream_out_valid_1
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 23; // Frame's data width
parameter EW = 1; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input sync_ready;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready_0;
input stream_out_ready_1;
input stream_select;
// Bidirectional
// Outputs
output reg sync_data;
output reg sync_valid;
output stream_in_ready;
output reg [DW: 0] stream_out_data_0;
output reg stream_out_startofpacket_0;
output reg stream_out_endofpacket_0;
output reg [EW: 0] stream_out_empty_0;
output reg stream_out_valid_0;
output reg [DW: 0] stream_out_data_1;
output reg stream_out_startofpacket_1;
output reg stream_out_endofpacket_1;
output reg [EW: 0] stream_out_empty_1;
output reg stream_out_valid_1;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire enable_setting_stream_select;
// Internal Registers
reg between_frames;
reg stream_select_reg;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
sync_data <= 1'b0;
sync_valid <= 1'b0;
end
else if (enable_setting_stream_select)
begin
sync_data <= stream_select;
sync_valid <= 1'b1;
end
else if (sync_ready)
sync_valid <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
begin
stream_out_data_0 <= 'h0;
stream_out_startofpacket_0 <= 1'b0;
stream_out_endofpacket_0 <= 1'b0;
stream_out_empty_0 <= 'h0;
stream_out_valid_0 <= 1'b0;
end
else if (stream_in_ready & ~stream_select_reg)
begin
stream_out_data_0 <= stream_in_data;
stream_out_startofpacket_0 <= stream_in_startofpacket;
stream_out_endofpacket_0 <= stream_in_endofpacket;
stream_out_empty_0 <= stream_in_empty;
stream_out_valid_0 <= stream_in_valid;
end
else if (stream_out_ready_0)
stream_out_valid_0 <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
begin
stream_out_data_1 <= 'h0;
stream_out_startofpacket_1 <= 1'b0;
stream_out_endofpacket_1 <= 1'b0;
stream_out_empty_1 <= 'h0;
stream_out_valid_1 <= 1'b0;
end
else if (stream_in_ready & stream_select_reg)
begin
stream_out_data_1 <= stream_in_data;
stream_out_startofpacket_1 <= stream_in_startofpacket;
stream_out_endofpacket_1 <= stream_in_endofpacket;
stream_out_empty_1 <= stream_in_empty;
stream_out_valid_1 <= stream_in_valid;
end
else if (stream_out_ready_1)
stream_out_valid_1 <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
between_frames <= 1'b1;
else if (stream_in_ready & stream_in_endofpacket)
between_frames <= 1'b1;
else if (stream_in_ready & stream_in_startofpacket)
between_frames <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
stream_select_reg <= 1'b0;
else if (enable_setting_stream_select)
stream_select_reg <= stream_select;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = (stream_select_reg) ?
stream_in_valid & (~stream_out_valid_1 | stream_out_ready_1) :
stream_in_valid & (~stream_out_valid_0 | stream_out_ready_0);
// Internal Assignments
assign enable_setting_stream_select =
(stream_in_ready & stream_in_endofpacket) |
(~(stream_in_ready & stream_in_startofpacket) & between_frames);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* I expect the following statistics results:
* 0 x 0 x x x
* 1 x 1 x 0 0
* 2 1 2 x 1 0
* 3 1 3 x 2 1
* 2 1 3 3 2 2
* 2 1 3 3 3 2
* 3 1 3 3 4 2
* 1 1 3 3 1 3
* 0 1 3 2 x 3
* 1 2 3 2 0 2
* 0 2 3 1 x 3
* 1 3 3 1 0 2
* 2 2 3 1 1 2
* 3 2 3 1 2 2
*
* x implies there is no defined value for that statistic.
*/
module top;
reg pass;
integer res, status, value, value2;
integer id, job, item;
initial begin
pass = 1'b1;
id = 1;
// Use id = 1, type = 1 (FIFO) and a size of 5.
$display("----- INIT -----");
$q_initialize(id, 1, 5, status);
if (status !== 0) begin
$display("Failed to initialize queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
// Add an element to the queue.
job = 1;
item = 10;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a second element to the queue.
job = 1;
item = 20;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a third element to the queue.
job = 1;
item = 30;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1
print_stats(id);
#1;
// Add a fourth element to the queue.
job = 1;
item = 30;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove two elements from the queue.
$display("----- REMOVE TWO -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element (1) from the queue, got %d", status);
pass = 1'b0;
end
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element (2) from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a fifth element to the queue.
job = 1;
item = 50;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Remove an element from the queue.
$display("----- REMOVE -----");
$q_remove(id, value, value2, status);
if (status !== 0) begin
$display("Failed to remove element from the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#7;
// Add a sixth element to the queue.
job = 1;
item = 60;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a seventh element to the queue.
job = 1;
item = 70;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
#1;
// Add a eight element to the queue.
job = 1;
item = 80;
$display("----- ADD -----");
$q_add(id, job, item, status);
if (status !== 0) begin
$display("Failed to add element to the queue, got %d", status);
pass = 1'b0;
end
print_stats(id);
if (pass) $display("PASSED");
end
task print_stats;
input id;
integer id;
integer len, inter, max, short, long, avg, status;
// Icarus uses a status code of 10 to indicate no statistics available.
begin
len = 32'bx;
inter = 32'bx;
max = 32'bx;
short = 32'bx;
long = 32'bx;
avg = 32'bx;
$display("Queue statistics at time %0d", $time);
// Get the queue length.
$q_exam(id, 1, len, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the length, status %0d", status);
pass = 1'b0;
end
// Get the mean inter-arrival time.
$q_exam(id, 2, inter, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the inter-arrival, status %0d", status);
pass = 1'b0;
end
// Get the maximum length.
$q_exam(id, 3, max, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the maximum length, status %0d", status);
pass = 1'b0;
end
// Get the shortest wait time.
$q_exam(id, 4, short, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the shortest wait time, status %0d", status);
pass = 1'b0;
end
// Get the longest wait time.
$q_exam(id, 5, long, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the longest wait time, status %0d", status);
pass = 1'b0;
end
// Get the average wait time.
$q_exam(id, 6, avg, status);
if ((status !== 0) && (status !== 10)) begin
$display(" Failed to get the average wait time, status %0d", status);
pass = 1'b0;
end
$display(" %0d, %0d, %0d, %0d, %0d, %0d",
len, inter, max, short, long, avg);
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; long long i; cin >> n >> m; long long cnt = 0; for (i = 1; i <= n; i++) { cnt += (m + i) / 5 - i / 5; } cout << cnt; return 0; } |
#include <bits/stdc++.h> using namespace std; int ts, kk = 1; template <class T> inline T _sq(T a) { return a * a; } template <class T, class X> inline T _pow(T a, X y) { T z = 1; for (int i = 1; i <= y; i++) { z *= a; } return z; } template <class T> inline T _gcd(T a, T b) { a = _abs(a); b = _abs(b); if (!b) return a; return _gcd(b, a % b); } template <class T> inline T _lcm(T a, T b) { a = _abs(a); b = _abs(b); return (a / _gcd(a, b)) * b; } template <class T> inline T _extended(T a, T b, T &x, T &y) { a = _abs(a); b = _abs(b); T g, x1, y1; if (!b) { x = 1; y = 0; g = a; return g; } g = _extended(b, a % b, x1, y1); x = y1; y = x1 - (a / b) * y1; return g; } template <class T, class X> inline bool getbit(T a, X i) { T t = 1; return ((a & (t << i)) > 0); } template <class T, class X> inline T setbit(T a, X i) { T t = 1; return (a | (t << i)); } template <class T, class X> inline T resetbit(T a, X i) { T t = 1; return (a & (~(t << i))); } template <class T, class X> inline T togglebit(T a, X i) { T t = 1; return (a ^ (t << i)); } template <class T, class X, class Y> inline T _bigmod(T n, X m, Y mod) { unsigned long long ret = 1, a = n % mod; while (m) { if (m & 1) ret = (ret * a) % mod; m >>= 1; a = (a * a) % mod; } ret %= mod; return (T)ret; } template <class T, class Y> inline T _modinv(T n, Y mod) { return _bigmod(n, mod - 2, mod); } int main() { int n, cnt = 0; ; double x, tot = 0.0, ans, add; cin >> n; for (int i = 1; i <= n + n; i++) { cin >> x; add = (x - (int)x); tot += add; if (add == 0.0) cnt++; } tot -= n; while (cnt-- > 0 && tot < -.5) tot += 1.0; tot = fabs(tot); cout << setprecision(3) << fixed << tot << endl; return 0; } |
// NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.0sp1 232 at 2015.10.21.10:55:06
`timescale 1 ps / 1 ps
module NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [0:0] CS_N, // .CS_N_out
output wire [3:0] ByteEnable_N, // .ByteEnable_N_out
output wire [0:0] OutputEnable_N, // .OutputEnable_N_out
output wire [0:0] Write_N, // .Write_N_out
output wire [31:0] data, // .data_out
input wire [31:0] data_in, // .data_in
output wire data_outen, // .data_outen
output wire [18:0] addr, // .addr_out
output wire [0:0] rst_N, // .rst_N_out
output wire [0:0] begin_N, // .begin_N_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [0:0] tcs0_chipselect_n_out, // .chipselect_n_out
input wire [3:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [31:0] tcs0_data_out, // .data_out
output wire [31:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [18:0] tcs0_address_out, // .address_out
input wire [0:0] tcs0_reset_n_out, // .reset_n_out
input wire [0:0] tcs0_begintransfer_n_out // .begintransfer_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_SRAM_tcm -> arbiter:sink0_valid
NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.CS_N (CS_N), // .CS_N_out
.ByteEnable_N (ByteEnable_N), // .ByteEnable_N_out
.OutputEnable_N (OutputEnable_N), // .OutputEnable_N_out
.Write_N (Write_N), // .Write_N_out
.data (data), // .data_out
.data_in (data_in), // .data_in
.data_outen (data_outen), // .data_outen
.addr (addr), // .addr_out
.rst_N (rst_N), // .rst_N_out
.begin_N (begin_N), // .begin_N_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_reset_n_out (tcs0_reset_n_out), // .reset_n_out
.tcs0_tcm_begintransfer_n_out (tcs0_begintransfer_n_out), // .begintransfer_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_SRAM_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule
|
#include <bits/stdc++.h> using namespace std; double PI = acos(-1); double EPS = 1e-7; int INF = 1000000000; int MOD = 1000000007; int MAXINT = 2147483647; long long INFLL = 1000000000000000000LL; long long MAXLL = 9223372036854775807LL; int mx[8] = {-1, 1, 0, 0, -1, -1, 1, 1}; int my[8] = {0, 0, -1, 1, -1, 1, -1, 1}; int rem[1000005]; int lol[1000005]; int pos[1000005]; int nx[1000005][20]; int bit[1000005]; int n, m; void build() { memset(bit, 0, sizeof(bit)); for (int(a) = (1); (a) <= (n); (a)++) { pos[lol[a]] = a; nx[a][0] = lol[a]; if (rem[lol[a]]) nx[a][0] = INF; } for (int(k) = (1); (k) <= (19); (k)++) { for (int(a) = (1); (a) <= (n - (1 << k) + 1); (a)++) { nx[a][k] = min(nx[a][k - 1], nx[a + (1 << (k - 1))][k - 1]); } } } int query(int pos, int lim) { int ret = 0; for (int(a) = (19); (a) >= (0); (a)--) { if (pos + (1 << a) - 1 <= n && nx[pos][a] > lim) { pos += (1 << a); ret += (1 << a); } } return ret; } void update(int bit[], int x, int v) { for (int i = x; i <= n; i += (i & -i)) { bit[i] += v; } } int query(int bit[], int x) { int res = 0; for (int i = x; i >= 1; i -= (i & -i)) { res += bit[i]; } return res; } int query(int bit[], int l, int r) { return query(bit, r) - query(bit, l - 1); } long long calc() { build(); long long ans = 0; for (int(v) = (1); (v) <= (n); (v)++) { int a = pos[v]; if (rem[v] == 1) { int tmp = query(a + 1, lol[a]); ans += tmp; ans -= query(bit, a + 1, a + tmp); update(bit, a, 1); } } return ans; } int main() { scanf( %d%d , &n, &m); for (int(a) = (1); (a) <= (n); (a)++) { scanf( %d , &lol[a]); rem[a] = 1; } for (int(a) = (1); (a) <= (m); (a)++) { int k; scanf( %d , &k); rem[k] = 0; } long long ans = n - m; ans += calc(); reverse(lol + 1, lol + n + 1); ans += calc(); printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; vector<long long> arr; arr.push_back(0); int sz = 1; long long max_ele = -1; long long pre_ind = 0; while (q--) { int x; cin >> x; if (x == 1) { long long v; cin >> v; if (sz == 0) arr.push_back(v); else arr.push_back(v + arr[sz - 1]); sz++; max_ele = v; continue; } if (sz == 2) { cout << setprecision(10) << 0.0l << n ; continue; } long long pre_sum = arr[pre_ind]; long long pre_numer = (pre_ind)*max_ele - pre_sum; long double val = (long double)pre_numer / (pre_ind + 1); while (pre_ind + 1 <= sz - 2) { if ((long double)((pre_ind + 1) * max_ele - arr[pre_ind + 1]) / (pre_ind + 2) > val) { val = (long double)((pre_ind + 1) * max_ele - arr[pre_ind + 1]) / (pre_ind + 2); pre_ind++; } else break; } cout << setprecision(10) << val << n ; } return 0; } |
module main();
// Parameters
parameter PER=10;
// In this example we perform a 3x3 convolution of an 8x8 input image
// Therefore the window size here is (3-1)*8+3 = 19
parameter IMAGE_WIDTH = 8;
parameter KERNEL_WIDTH = 3;
// Line buffer parameters
parameter DATA_WIDTH = 8;
parameter DEPTH = 20; // (3-1)*8+3+1
parameter CNTR_WIDTH = 5; // floor(log(20)) + 1
parameter RD_WINDOW = 19; // (3-1)*8+3
parameter RD_ADVANCE = 1;
parameter RD_ADDR_WIDTH = 5; // floor(log(19)) + 1
parameter WR_WINDOW = 1;
parameter WR_ADVANCE = 1;
parameter WR_ADDR_WIDTH = 1;
// Clock & reset
reg clk;
reg rst;
// Read port inputs
reg read_advance;
reg [RD_ADDR_WIDTH-1:0] read_addr;
reg read_ready;
// Write port outputs
reg write_advance;
reg [DATA_WIDTH-1:0] write_data;
reg write_valid;
// Outputs
wire [DATA_WIDTH-1:0] read_data;
wire read_valid;
wire write_ready;
wire [CNTR_WIDTH-1:0] status_counter;
// Module instantiation
tvm_buffer #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH),
.CNTR_WIDTH(CNTR_WIDTH),
.RD_WINDOW(RD_WINDOW),
.RD_ADVANCE(RD_ADVANCE),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_WINDOW(WR_WINDOW),
.WR_ADVANCE(WR_ADVANCE),
.WR_ADDR_WIDTH(WR_ADDR_WIDTH)
) uut (
.clk(clk),
.rst(rst),
.read_advance(read_advance),
.read_data(read_data),
.read_addr(read_addr),
.read_ready(read_ready),
.read_valid(read_valid),
.write_advance(write_advance),
.write_data(write_data),
.write_addr({WR_ADDR_WIDTH{1'b0}}),
.write_ready(write_ready),
.write_valid(write_valid),
.status_counter(status_counter)
);
// clock generation
always begin
#(PER/2) clk =~ clk;
end
// read logic
localparam KERNEL_SIZE = KERNEL_WIDTH*KERNEL_WIDTH;
reg [3:0] read_counter;
always @(posedge clk) begin
if (rst) begin
read_counter <= KERNEL_SIZE-1;
read_advance <= 0;
read_addr <= -1;
read_ready <= 0;
end else begin
if (read_valid) begin
read_counter <= (read_counter+1)%KERNEL_SIZE;
read_ready <= 1;
// Only advance at the last inner loop iteration
if (read_counter==KERNEL_SIZE-2) begin
read_advance <= 1;
end else begin
read_advance <= 0;
end
// Read address should describe a loop
if (read_counter==KERNEL_SIZE-1) begin
read_addr <= 0;
end else if (read_counter%KERNEL_WIDTH==KERNEL_WIDTH-1) begin
read_addr <= read_addr+IMAGE_WIDTH-KERNEL_WIDTH+1;
end else begin
read_addr <= read_addr+1;
end
end else begin
read_counter <= read_counter;
read_advance <= 0;
read_addr <= read_addr;
read_ready <= 0;
end
end
end
// read_data_valid logic
reg read_data_valid;
always @(posedge clk) begin
if (rst)
read_data_valid <= 0;
else
read_data_valid <= read_ready;
end
initial begin
// This will allow tvm session to be called every cycle.
$tvm_session(clk);
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_denorm_3b.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Three bit comparison of two inputs when both will always have
// leading 0s.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_denorm_3b (
din1,
din2,
din2_din1_nz,
din2_din1_denorm
);
input [2:0] din1; // input 1- 3 bits
input [2:0] din2; // input 2- 3 bits
output din2_din1_nz; // input 1 and input 2 are not 0
output din2_din1_denorm; // input 1 is a denorm
wire [2:0] din2_din1_zero;
wire din2_din1_nz;
wire din2_din1_denorm;
assign din2_din1_zero[2:0]= (~(din1 | din2));
assign din2_din1_nz= (!(&din2_din1_zero[2:0]));
assign din2_din1_denorm= din2[2]
|| (din2_din1_zero[2] && din2[1])
|| ((&din2_din1_zero[2:1]) && din2[0]);
endmodule
|
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