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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_1_V
`define SKY130_FD_SC_HD__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by ____YOUR_NAME_HERE____.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test(/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int x; char s[100005]; bool flag[500]; int cnt[500]; vector<char> f; int main() { scanf( %d , &x); scanf( %s , s); int len = strlen(s); for (int i = 0; i < len; i++) cnt[s[i]]++; for (int i = a ; i <= z ; i++) { if (cnt[i] == 0) continue; flag[i] = 1; int pre = -1; bool tag = 0; f.push_back(char(i)); for (int j = 0; j < len; j++) { if (flag[s[j]]) { pre = j; continue; } int y = j - pre; if (y >= x) { tag = 1; break; } } if (tag) continue; else { cnt[i] = 0; flag[i] = 0; int pos = -1; int pre = -1; for (int j = 0; j < len; j++) { if (s[j] == i) { pos = max(pos, j); } if (flag[s[j]]) { pre = j; continue; } int y = j - pre; if (y >= x) { pre = pos; cnt[i]++; } } break; } } string ans = ; int p = f.size(); for (int i = 0; i < p; i++) { for (int j = 1; j <= cnt[f[i]]; j++) ans += f[i]; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a1, a2, a3, a4; cin >> a1 >> a2 >> a3 >> a4; int a[4]; a[0] = a1; a[1] = a2; a[2] = a3; a[3] = a4; sort(a, a + 4); if (a[0] + a[1] + a[2] == a[3]) { cout << YES ; } else if (a[0] + a[3] == a[1] + a[2]) { cout << YES ; } else if (a[0] + a[2] == a[1] + a[3]) { cout << YES ; } else { cout << NO ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void mex(string &s) { s.back()++; for(int i=s.length()-1;i>=1;i--) { if(s[i]> z ) { s[i]= a ; s[i-1]++; } } if(s[0]> z ) { s.push_back( a ); s[0]= a ; } } int main() { int t;cin>>t; while(t--) { int n;cin>>n; string s;cin>>s; string k= a ; while(s.find(k,0)!=string::npos) { mex(k); } cout<<k<<endl; } } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_always_on_edge (clock, reset, enable, sampling_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter edge_type = `OVL_NOEDGE;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input sampling_event, test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ALWAYS_ON_EDGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_always_on_edge_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_always_on_edge_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_always_on_edge_psl_logic.v"
`else
`endmodule // ovl_always_on_edge
`endif
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
//
// $Date: 2005/02/27 09:26:24 $
// $Revision: 1.11 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
//
// $Log: i2c_master_top.v,v $
//
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
//rsf `include "timescale.v"
// synopsys translate_on
//rsf `include "i2c_master_defines.v"
// I2C registers wishbone addresses
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
module oc_i2c_master(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl, sda );
// parameters
//rsf parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
//rsf define as bidir
inout scl;
wire scl_pad_i; // SCL-line input
wire scl_pad_o; // SCL-line output (always 1'b0)
wire scl_padoen_o; // SCL-line output enable (active low)
assign scl = (!scl_padoen_o) ? (scl_pad_o) : (1'bZ);
assign scl_pad_i = scl;
// i2c data line
inout sda;
wire sda_pad_i; // SDA-line input
wire sda_pad_o; // SDA-line output (always 1'b0)
wire sda_padoen_o; // SDA-line output enable (active low)
assign sda = (!sda_padoen_o) ? (sda_pad_o) : (1'bZ);
assign sda_pad_i = sda;
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i)
if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i)
if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i)
if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2009 www.xilinx.com
//
// XAPP xyz
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : dvi_encoder.v
//
// Description : dvi_encoder
//
// Date - revision : April 2009 - 1.0.0
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors makeand you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specificallydisclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does notwarrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designswill be
// uninterrupted or error free, or that defects in theDesigns
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results ofthe
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or forany
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on anytheory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure ofthe
// essential purpose of any limited remedies herein.
//
// Copyright © 2009 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1ps
module dvi_encoder_top (
input wire pclk, // pixel clock
input wire pclkx2, // pixel clock x2
input wire pclkx10, // pixel clock x2
input wire serdesstrobe, // OSERDES2 serdesstrobe
input wire rstin, // reset
input wire [7:0] blue_din, // Blue data in
input wire [7:0] green_din, // Green data in
input wire [7:0] red_din, // Red data in
input wire hsync, // hsync data
input wire vsync, // vsync data
input wire de, // data enable
output wire [3:0] TMDS,
output wire [3:0] TMDSB);
wire [9:0] red ;
wire [9:0] green ;
wire [9:0] blue ;
wire [4:0] tmds_data0, tmds_data1, tmds_data2;
wire [2:0] tmdsint;
//
// Forward TMDS Clock Using OSERDES2 block
//
reg [4:0] tmdsclkint = 5'b00000;
reg toggle = 1'b0;
always @ (posedge pclkx2 or posedge rstin) begin
if (rstin)
toggle <= 1'b0;
else
toggle <= ~toggle;
end
always @ (posedge pclkx2) begin
if (toggle)
tmdsclkint <= 5'b11111;
else
tmdsclkint <= 5'b00000;
end
wire tmdsclk;
serdes_n_to_1 #(
.SF (5))
clkout (
.iob_data_out (tmdsclk),
.ioclk (pclkx10),
.serdesstrobe (serdesstrobe),
.gclk (pclkx2),
.reset (rstin),
.datain (tmdsclkint));
OBUFDS TMDS3 (.I(tmdsclk), .O(TMDS[3]), .OB(TMDSB[3])) ;// clock
//
// Forward TMDS Data: 3 channels
//
serdes_n_to_1 #(.SF(5)) oserdes0 (
.ioclk(pclkx10),
.serdesstrobe(serdesstrobe),
.reset(rstin),
.gclk(pclkx2),
.datain(tmds_data0),
.iob_data_out(tmdsint[0])) ;
serdes_n_to_1 #(.SF(5)) oserdes1 (
.ioclk(pclkx10),
.serdesstrobe(serdesstrobe),
.reset(rstin),
.gclk(pclkx2),
.datain(tmds_data1),
.iob_data_out(tmdsint[1])) ;
serdes_n_to_1 #(.SF(5)) oserdes2 (
.ioclk(pclkx10),
.serdesstrobe(serdesstrobe),
.reset(rstin),
.gclk(pclkx2),
.datain(tmds_data2),
.iob_data_out(tmdsint[2])) ;
OBUFDS TMDS0 (.I(tmdsint[0]), .O(TMDS[0]), .OB(TMDSB[0])) ;
OBUFDS TMDS1 (.I(tmdsint[1]), .O(TMDS[1]), .OB(TMDSB[1])) ;
OBUFDS TMDS2 (.I(tmdsint[2]), .O(TMDS[2]), .OB(TMDSB[2])) ;
encode encb (
.clkin (pclk),
.rstin (rstin),
.din (blue_din),
.c0 (hsync),
.c1 (vsync),
.de (de),
.dout (blue)) ;
encode encg (
.clkin (pclk),
.rstin (rstin),
.din (green_din),
.c0 (1'b0),
.c1 (1'b0),
.de (de),
.dout (green)) ;
encode encr (
.clkin (pclk),
.rstin (rstin),
.din (red_din),
.c0 (1'b0),
.c1 (1'b0),
.de (de),
.dout (red)) ;
wire [29:0] s_data = {red[9:5], green[9:5], blue[9:5],
red[4:0], green[4:0], blue[4:0]};
convert_30to15_fifo pixel2x (
.rst (rstin),
.clk (pclk),
.clkx2 (pclkx2),
.datain (s_data),
.dataout ({tmds_data2, tmds_data1, tmds_data0}));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA WISHBONE Master Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:11:05 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_wb_mast(clk, rst,
wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait,
pt_sel, mast_pt_in, mast_pt_out
);
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// INTERNAL DMA INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg mast_cyc, mast_stb;
reg mast_we_r;
reg [3:0] mast_be;
reg [31:0] mast_dout;
////////////////////////////////////////////////////////////////////
//
// Pass-Through Interface
//
assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} =
pt_sel ? mast_pt_in :
{mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb};
assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i};
////////////////////////////////////////////////////////////////////
//
// DMA Engine Interface
//
// MSB: Eliminate 'x' propagation
// Source: bug tracker
always @(posedge clk or negedge rst)
if (!rst) mast_dout <= 32'h00000000;
else if(wb_ack_i) mast_dout <= #1 wb_data_i;
/*
always @(posedge clk)
if(wb_ack_i) mast_dout <= #1 wb_data_i;
*/
always @(posedge clk)
mast_be <= #1 4'hf;
always @(posedge clk)
mast_we_r <= #1 mast_we;
always @(posedge clk)
mast_cyc <= #1 mast_go;
always @(posedge clk)
mast_stb <= #1 mast_go & !mast_wait;
assign mast_drdy = wb_ack_i;
assign mast_err = wb_err_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); struct Comp { double re, im; Comp(double x = 0.0, double y = 0.0) : re(x), im(y) {} Comp operator+(const Comp& rhs) const { return Comp(re + rhs.re, im + rhs.im); } Comp operator-(const Comp& rhs) const { return Comp(re - rhs.re, im - rhs.im); } Comp operator*(const Comp& rhs) const { return Comp(re * rhs.re - im * rhs.im, re * rhs.im + im * rhs.re); } Comp operator/(double x) const { return Comp(re / x, im / x); } }; int fft_len, fft_lg; vector<int> r; void ensure_base(int deg) { fft_len = 2, fft_lg = 1; while (fft_len <= deg) fft_len <<= 1, fft_lg++; r = vector<int>(fft_len, 0); for (int i = 0; i < fft_len; ++i) r[i] = (r[i >> 1] >> 1) | ((i & 1) << (fft_lg - 1)); } void fft(vector<Comp>& A, int dft) { for (int i = 0; i < fft_len; ++i) if (i < r[i]) swap(A[i], A[r[i]]); for (int mid = 1; mid < fft_len; mid <<= 1) { Comp wn = Comp(cos(PI / mid), sin(PI / mid) * dft); for (int len = mid << 1, s = 0; s < fft_len; s += len) { Comp w(1, 0); for (int k = 0; k < mid; ++k, w = w * wn) { Comp x = A[s + k], y = w * A[s + k + mid]; A[s + k] = x + y; A[s + k + mid] = x - y; } } } if (dft == -1) for (int i = 0; i < fft_len; ++i) A[i] = A[i] / fft_len; } void fft_pmul(vector<Comp>& A, int degA, vector<Comp>& B, int degB) { ensure_base(degA + degB); A.resize(fft_len, 0), B.resize(fft_len, 0); fft(A, 1); fft(B, 1); for (int i = 0; i < fft_len; ++i) A[i] = A[i] * B[i]; fft(A, -1); } int p[26], q[26]; string s, t; int main() { ios::sync_with_stdio(false); for (int i = 0; i < 26; ++i) cin >> q[i], p[q[i] - 1] = i; cin >> t >> s; int n = s.length(), m = t.length(); reverse(t.begin(), t.end()); vector<Comp> ps1(n), ps2(n), ps3(n), pt1(m), pt2(m), pt3(m); vector<double> p0(n); for (int i = 0; i < n; ++i) { int v = s[i] - a ; ps3[i].re = -(2 * v + 2 * p[v]); ps2[i].re = v * v + 4 * v * p[v] + p[v] * p[v]; ps1[i].re = -2 * v * p[v] * (v + p[v]); p0[i] = v * v * p[v] * p[v]; if (i) p0[i] += p0[i - 1]; } double t4 = 0; for (int i = 0; i < m; ++i) { int v = t[i] - a ; pt3[i].re = v * v * v; pt2[i].re = v * v; pt1[i].re = v; t4 += v * v * v * v; } fft_pmul(ps3, n, pt3, m); fft_pmul(ps2, n, pt2, m); fft_pmul(ps1, n, pt1, m); for (int i = m - 1; i < n; ++i) { double res = t4 + ps3[i].re + ps2[i].re + ps1[i].re + p0[i] - (i - m < 0 ? 0 : p0[i - m]); putchar( 0 + (fabs(res) < 0.8)); } return 0; } |
module DramReader(
input fclk,
input rst_n,
//AXI port
output M2S_AXI_ACLK,
//
output reg M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output reg [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [63:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
//Control config
input rd_frame_valid,
output reg rd_frame_ready,
input [31:0] rd_FRAME_BYTES,
input [31:0] rd_BUF_ADDR,
output [1:0] debug_astate,
//RAM port
input dout_burst_ready,
input dout_ready,
output dout_valid,
output [63:0] dout
);
assign M2S_AXI_ACLK = fclk;
assign M2S_AXI_ARLEN = 4'b1111;
assign M2S_AXI_ARSIZE = 2'b11;
assign M2S_AXI_ARBURST = 2'b01;
reg [31:0] BUF_ADDR;
reg [31:0] FRAME_BYTES;
`REG(fclk, BUF_ADDR, 0, rd_frame_valid && rd_frame_ready ? rd_BUF_ADDR : BUF_ADDR)
`REG(fclk, FRAME_BYTES, 0, rd_frame_valid && rd_frame_ready ? rd_FRAME_BYTES : FRAME_BYTES)
wire frame_done;
assign frame_done = (M2S_AXI_ARADDR + 128)==(BUF_ADDR+FRAME_BYTES);
localparam A_IDLE = 0, A_FRAME_IDLE = 1, A_FRAME_WAIT=2;
//ADDR logic
reg [1:0] a_state;
//wire [1:0] debug_astate;
assign debug_astate = a_state;
always @(posedge fclk or negedge rst_n) begin
if (!rst_n) begin
a_state <= A_IDLE;
M2S_AXI_ARADDR <= 0;
M2S_AXI_ARVALID <= 0;
rd_frame_ready <= 0;
end
else begin
M2S_AXI_ARVALID <= 0;
rd_frame_ready <= 0;
case(a_state)
A_IDLE : begin
rd_frame_ready <= 1;
if (rd_frame_valid) begin
M2S_AXI_ARADDR <= rd_BUF_ADDR;
a_state <= A_FRAME_IDLE;
end
end
A_FRAME_IDLE : begin
if (dout_burst_ready && M2S_AXI_ARREADY) begin
a_state <= A_FRAME_WAIT ;
M2S_AXI_ARVALID <= 1 ;
end
end
A_FRAME_WAIT: begin
if (r_state == R_IDLE) begin
M2S_AXI_ARADDR <= M2S_AXI_ARADDR + 128; // Bursts are 128 bytes long
a_state <= frame_done ? A_IDLE : A_FRAME_IDLE ;
end
end
endcase
end
end
localparam R_IDLE=0, R_WAIT=1;
//READ logic
reg [3:0] b_count;
reg r_state;
assign M2S_AXI_RREADY = (r_state == R_WAIT) && dout_ready;
always @(posedge fclk or negedge rst_n) begin
if (rst_n == 0) begin
r_state <= R_IDLE;
b_count <= 0;
end else case(r_state)
R_IDLE: begin
if (a_state==A_FRAME_IDLE && dout_burst_ready && M2S_AXI_ARREADY) begin
b_count <= 4'd15;
r_state <= R_WAIT;
end
end
R_WAIT: begin
if (M2S_AXI_RVALID && dout_ready) begin
if(b_count == 4'h0) begin
r_state <= R_IDLE;
end
b_count <= b_count - 1'b1; // each valid cycle the bus provides 8 bytes
end
end
endcase
end
assign dout = M2S_AXI_RDATA;
assign dout_valid = M2S_AXI_RVALID && (r_state == R_WAIT);
endmodule : DramReader
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 2; bool vis[N]; int trie[N * 20][2], sz; void inser(int n) { int curr = 0; for (int i = 19; i >= 0; i--) { int dir = (n >> i) & 1; if (trie[curr][dir] == -1) trie[curr][dir] = ++sz; curr = trie[curr][dir]; } } int query(int n) { int curr = 0, ans = 0; for (int i = 19; i >= 0; i--) { int dir = (n >> i) & 1; if (trie[curr][dir] != -1) { curr = trie[curr][dir]; } else { ans += (1 << i); curr = trie[curr][1 ^ dir]; } } return ans; } int main() { memset(trie, -1, sizeof(trie)); int n, q; scanf( %d%d , &n, &q); while (n--) { int a; scanf( %d , &a); vis[a] = true; } for (int i = 0; i < N; i++) if (!vis[i]) inser(i); int xorval = 0; while (q--) { int x; scanf( %d , &x); xorval ^= x; printf( %d n , query(xorval)); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> edge[200002], col; int vis[200002]; queue<int> q; void bfs(int s) { vis[s] = 1; q.push(s); while (!q.empty()) { int x = q.front(); q.pop(); set<int> st; for (auto y : edge[x]) { if (vis[y]) { st.insert(col[y - 1]); } } if (col[x - 1] == -1) { int flag = 1; while (1) { if (st.find(flag) != st.end()) { flag++; } else { col[x - 1] = flag; break; } } } int start = col[x - 1] - 1, end = col[x - 1] + 1; for (auto y : edge[x]) { if (!vis[y]) { vis[y] = 1; q.push(y); int flag = 0; while (!flag) { if (start > 0) { if (st.find(start) != st.end()) { start--; } else { col[y - 1] = start; st.insert(start); start--; flag = 1; } } else { if (st.find(end) != st.end()) { end++; } else { col[y - 1] = end; st.insert(end); end++; flag = 1; } } } } } } } void solve() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; edge[x].push_back(y); edge[y].push_back(x); } col.assign(n, -1); for (int i = 1; i <= n; i++) { if (edge[i].size() > 1) { bfs(i); break; } } int mx = 1; for (auto x : col) { mx = max(x, mx); } cout << mx << n ; for (auto x : col) { cout << x << ; } cout << n ; } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; inline int read() { int x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 0 , ch = getchar(); return x; } int A[maxn], B[maxn], N, MOD, fir, d, len; int ksm(int x, int y) { int res = 1; for (; y; y >>= 1, x = (long long)x * x % MOD) if (y & 1) res = (long long)res * x % MOD; return res; } void Solve(int *P, int Len) { int kd = P[1] - P[0], cnt = 0; map<int, bool> vis; for (int i = 0; i < N; ++i) vis[P[i]] = true; for (int i = 0; i < N; ++i) if (!vis.count((P[i] + kd) % MOD)) ++cnt; d = (long long)kd * ksm(cnt, MOD - 2) % MOD; fir = -1; len = (MOD - d) % MOD; for (int i = 0; i < N; ++i) if (!vis.count((P[i] + d) % MOD)) if (~fir) { fir = -1; break; } else fir = P[i]; } int main() { MOD = read(); N = read(); for (int i = 0; i < N; ++i) A[i] = read(); if (N == 1 || N == MOD) printf( %d 1 n , A[0]); else { sort(A, A + N); if (2 * N < MOD) Solve(A, N); else { map<int, bool> vis; for (int i = 0; i < N; ++i) vis[A[i]] = true; N = 0; for (int i = 0; i < MOD; ++i) if (!vis.count(i)) B[N++] = i; Solve(B, N); if (~fir) (fir += (long long)len * N % MOD) %= MOD; } if (~fir) printf( %d %d n , fir, len); else puts( -1 ); } } |
#include <bits/stdc++.h> using namespace std; struct Point { double x, y; Point() {} Point(double _x, double _y) { x = _x; y = _y; } Point operator-(const Point &b) const { return Point(x - b.x, y - b.y); } double operator^(const Point &b) const { return x * b.y - y * b.x; } double operator*(const Point &b) const { return x * b.x + y * b.y; } void transXY(double B) { double tx = x, ty = y; x = tx * cos(B) - ty * sin(B); y = tx * sin(B) + ty * cos(B); } }; struct Line { Point s, e; Line() {} Line(Point _s, Point _e) { s = _s; e = _e; } }; Point PointToLine(Point P, Line L) { Point result; double t = ((P - L.s) * (L.e - L.s)) / ((L.e - L.s) * (L.e - L.s)); result.x = L.s.x + (L.e.x - L.s.x) * t; result.y = L.s.y + (L.e.y - L.s.y) * t; return result; } Point ver[1010]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> ver[i].x >> ver[i].y; ver[0] = ver[n]; ver[n + 1] = ver[1]; double ans = 1e12; for (int i = 1; i <= n; ++i) { Line l; l.s = ver[i - 1]; l.e = ver[i + 1]; Point p = PointToLine(ver[i], l); double len = sqrt((ver[i].x - p.x) * (ver[i].x - p.x) + (ver[i].y - p.y) * (ver[i].y - p.y)); ans = min(ans, len / 2); } printf( %.010lf n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; const int inf = 1000000007; int main() { int a, b, c; int x, y, z; cin >> a >> b >> c; cin >> x >> y >> z; int da = a - x; int db = b - y; int dc = c - z; int can = max(0, da / 2) + max(0, db / 2) + max(0, dc / 2); int needed = min(0, da) + min(0, db) + min(0, dc); cout << (can + needed >= 0 ? Yes : No ) << endl; return 0; } |
//---------------------------------------------------------------------//
// Name: am_put_fpga.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Top-level file for implementing the American Put in an FPGA.
//---------------------------------------------------------------------//
module amer_put(
clk_fast,
clk_slow,
nrst,
start_s1,
start_s2,
p_up,
p_down,
log_lambda_up,
log_lambda_down,
K_over_S,
result
);
input clk_fast;
input clk_slow;
input nrst;
input start_s1;
input start_s2;
input [63:0] p_up;
input [63:0] p_down;
input [63:0] log_lambda_up;
input [63:0] log_lambda_down;
input [63:0] K_over_S;
output [63:0] result;
//---------------------------------------------------------------------//
// Wires
//---------------------------------------------------------------------//
wire [63:0] c0_memout;
wire [63:0] c1_memout;
wire [63:0] c2_memout;
wire [63:0] c3_memout;
wire [63:0] c0_up;
wire [63:0] c1_up;
wire [63:0] c2_up;
wire [63:0] c3_up;
wire [63:0] c0_down;
wire [63:0] c1_down;
wire [63:0] c2_down;
wire [63:0] c3_down;
wire [63:0] c0_vex;
wire [63:0] c1_vex;
wire [63:0] c2_vex;
wire [63:0] c3_vex;
wire [63:0] c0_result;
wire [63:0] c1_result;
wire [63:0] c2_result;
wire [63:0] c3_result;
wire [9:0] rdaddr;
wire [9:0] wraddr;
wire [12:0] vexaddr;
wire done_init;
wire wren;
//---------------------------------------------------------------------//
// Assignments.
//---------------------------------------------------------------------//
assign result = c0_memout;
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
addrgen addrgen_inst(
.clk(clk_fast),
.nrst(nrst),
.start(done_s1),
.readout(start_s2),
.n(16'd4000),
.wraddr(wraddr),
.wren(wren),
.rdaddr(rdaddr),
.vexaddr(vexaddr)
);
value_membank value_membank_inst(
.clk(clk_fast),
.nrst(nrst),
.wren(wren),
.rdaddr(rdaddr),
.wraddr(wraddr),
.start_init(start_s1),
.done_init(done_init),
.c0_in(c0_result),
.c1_in(c1_result),
.c2_in(c2_result),
.c3_in(c3_result),
.c0_out(c0_memout),
.c1_out(c1_memout),
.c2_out(c2_memout),
.c3_out(c3_memout)
);
value_buffer value_buffer_inst(
.clk(clk_fast),
.c0_in(c0_memout),
.c1_in(c1_memout),
.c2_in(c2_memout),
.c3_in(c3_memout),
.c0_up(c0_up),
.c1_up(c1_up),
.c2_up(c2_up),
.c3_up(c3_up),
.c0_down(c0_down),
.c1_down(c1_down),
.c2_down(c2_down),
.c3_down(c3_down)
);
// Compute value at the current node.
eval_node c0_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c0_up),
.v_down(c0_down),
.v_ex(c0_vex),
.result(c0_result)
);
eval_node c1_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c1_up),
.v_down(c1_down),
.v_ex(c1_vex),
.result(c1_result)
);
eval_node c2_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c2_up),
.v_down(c2_down),
.v_ex(c2_vex),
.result(c2_result)
);
eval_node c3_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c3_up),
.v_down(c3_down),
.v_ex(c3_vex),
.result(c3_result)
);
// Vex Lookup.
vex vex_inst(
.clk_slow(clk_slow),
.clk_fast(clk_fast),
.nrst(nrst),
.start_s1(start_s1),
.start_s2(done_s1),
.log_lambda_up(log_lambda_up),
.log_lambda_down(log_lambda_down),
.K_over_S(K_over_S),
.chan0(c0_vex),
.chan1(c1_vex),
.chan2(c2_vex),
.chan3(c3_vex),
.done_s1(done_s1),
.vexaddr(vexaddr)
);
endmodule |
`timescale 1 ns / 1 ps
module averager_counter_tb();
parameter FAST_COUNT_WIDTH = 5;
parameter SLOW_COUNT_WIDTH = 10;
reg restart;
reg clken;
reg [FAST_COUNT_WIDTH-1:0] count_max;
reg clk;
reg avg_on;
wire clr_fback;
wire ready;
wire wen;
wire avg_on_out;
wire [SLOW_COUNT_WIDTH-1:0] n_avg;
wire [FAST_COUNT_WIDTH+1:0] address;
averager_counter #(.FAST_COUNT_WIDTH(FAST_COUNT_WIDTH),
.SLOW_COUNT_WIDTH(SLOW_COUNT_WIDTH))
DUT (
.restart(restart),
.clken(clken),
.count_max(count_max),
.clk(clk),
.avg_on(avg_on),
.clr_fback(clr_fback),
.ready(ready),
.wen(wen),
.n_avg(n_avg),
.avg_on_out(avg_on_out),
.address(address)
);
parameter CLK_PERIOD = 8;
initial begin
clk = 0;
restart = 0;
clken = 0;
count_max = 15;
avg_on = 1;
#(10*CLK_PERIOD) clken = 1;
#(40 *CLK_PERIOD) restart = 1;
#(1*CLK_PERIOD) restart = 0;
#(100*CLK_PERIOD) avg_on = 0;
#(500*CLK_PERIOD) restart = 1;
#(1*CLK_PERIOD) restart = 0;
#(1000*CLK_PERIOD)
$finish;
end
always #(CLK_PERIOD/2) clk = ~clk;
endmodule
|
module ps2 (
input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
reg [1:0] k;
reg init;
reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
k=0;
DoIt=1;
//NoDoIt=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
if(DoIt)
begin
k<=k+1;
end
if(k==3)
begin
DONE=0;
DoIt=0;
Rx_error=0;
end
if(!DoIt)
begin
k<=0;
end
if(i==9)
begin
DoIt=1;
end
else
begin
end
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if(!(j%2)&&(regis[8]))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init=0;
end
end
assign DATA=regis0;
endmodule
|
module shiftRegister(clk, peripheralClkEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut,peripheralClk8Edge);
parameter width = 8;
input clk;
input peripheralClkEdge;
input peripheralClk8Edge;
input parallelLoad;
output[width-1:0] parallelDataOut;
output serialDataOut;
input[width-1:0] parallelDataIn;
input serialDataIn;
reg[width-1:0] shiftRegisterMem;
assign serialDataOut=shiftRegisterMem[width-1];
assign parallelDataOut=shiftRegisterMem;
always @(posedge peripheralClkEdge) begin
shiftRegisterMem <= {shiftRegisterMem[width-2:0],serialDataIn};
#20
if(parallelLoad) shiftRegisterMem <= parallelDataIn;
end
endmodule
module testShiftRegister;
parameter width = 8;
reg clk;
reg peripheralClkEdge;
reg parallelLoad;
wire[width-1:0] parallelDataOut;
wire serialDataOut;
reg[width-1:0] parallelDataIn;
reg serialDataIn;
reg [4:0] sclk_temp;
shiftregister #(width) sr(clk, peripheralClkEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut);
initial begin clk=0; sclk_temp=0; end
always #10 clk=!clk;
initial parallelDataIn=16'hA5;
// serial clock
always #10 begin
sclk_temp=sclk_temp+1;
sclk_temp=sclk_temp % 10;
if (sclk_temp==1) peripheralClkEdge=1;
else peripheralClkEdge=0;
end
initial begin
parallelLoad=0;
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1;
parallelLoad=1; #20
parallelLoad=0; #180
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1;
//parallelLoad=0;
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=0;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=0;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//parallelLoad=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//parallelLoad=0;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0;
//$display("%b", parallelDataOut);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V |
`define WIDTH_P 2
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
An internal counter keeps track of the count which is compared with the
output of the DUT. This test continues for 2**WIDTH_P cycles and hence
tests the DUT exhaustively.
2. PARAMETERIZATION
A minimum set of tests might be WIDTH_P=1,2,..,8. Since the number of test
cases grows exponentially, tests with large WIDTH_P takes very long to
finish.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_lo_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display( "=============================================================\n"
, "testing with ...\n"
, "WIDTH_P: %d\n", width_p
);
end
logic [width_p-1:0] count, count_r;
wire [width_p-1:0] test_output;
always_ff @(posedge clk)
begin
if(reset)
count <= 0;
else
count <= count + 1;
//$display("count: %d, test_output: %d\n", count, test_output);///////////
count_r <= count;
end
always_ff @(posedge clk)
begin
if(!reset)
assert(count == test_output)
else $error("mismatch on clock cycle %x", count);
if(!(|count) & (&count_r)) // finish when count value returns to 0
begin
$display("=============================================================\n");
$finish;
end
end
bsg_cycle_counter #( .width_p(width_p)
) DUT
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(test_output)
);
/*bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (2)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%x")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i ({test_output,
count}
)
);*/
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long lcm(long long a, long long b) { return (a * (b / gcd(a, b))); } long long bigmod(long long b, long long p, long long m) { if (p == 0) return 1; if (p % 2 == 0) { long long temp = bigmod(b, p / 2, m); return (temp * temp) % m; } return (bigmod(b, p - 1, m) * (b % m)) % m; } char inp[10010]; string scan() { scanf( %s , inp); string s; for (int i = 0; inp[i]; i++) s += inp[i]; return s; } vector<vector<int> > v; vector<bool> visited; int visit[100]; void dfs(int node) { visit[node] = 1; for (int i = 0; i < (int)v[node].size(); i++) if (!visit[v[node][i]]) dfs(v[node][i]); } int connectedcomponenetscnt(int head) { int cnt = 0; for (int i = 1; i < 500; i++) { if (!visit[i]) { dfs(i); cnt++; } } return cnt; } int com(string s, string t) { for (int i = 0; i < min(s.length(), t.length()); i++) { if (s[i] > t[i]) return 1; if (s[i] < t[i]) return 0; } if (s.length() > t.length()) return 1; return 0; } int n, m, x; int a[1001]; int memo[1001][1001][2]; int dp(int i, int sum, int k) { if (sum % m == 0 && k) return 1; if (i == m) return 0; int &ret = memo[i][sum][k]; if (ret != -1) return ret; ret = 0; for (int j = 0; j <= a[i]; j++) { if (j > 0 || k) ret = ret + dp(i + 1, (sum + i * j) % m, 1); else ret = ret + dp(i + 1, (sum + i * j) % m, 0); } return ret; } int main() { memset(memo, -1, sizeof(memo)); memset(a, 0, sizeof(a)); cin >> n >> m; int yes = 0; for (int i = 0; i < n; i++) { scanf( %d , &x); x = x % m; if (x == 0) yes = 1; a[x]++; } for (int i = 1; i < m; i++) if (a[i] >= m) yes = 1; if (yes) cout << YES ; else if (dp(1, 0, 0)) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int d, m, n, x[25], a[30005]; vector<long long> ok; long long L, R; map<long long, vector<long long> > ans; map<long long, vector<long long> > zip; vector<long long> calc(long long lim) { if (zip.find(lim) != zip.end()) return zip[lim]; vector<long long> ret(m, 0); if (lim == 0) { ret[0] = 1; return ret; } for (int beg = 0; beg < d && beg <= lim; beg++) { long long nxt_lim = (lim - beg) / d; vector<long long> R = calc(nxt_lim); for (int i = 0; i < m; i++) { int a = (i + x[beg]); if (a >= m) a -= m; ret[a] += R[i]; } } return zip[lim] = ret; } void rec(long long lim, vector<long long> mask, bool F) { if (mask.size() == 1) { if (ans.find(lim) == ans.end()) { ans[lim] = vector<long long>(m, 0); } for (int i = 0; i < m; i++) { if (((mask[0] >> i) & 1LL)) { if (F) ans[lim][i]++; else ans[lim][i]--; } } return; } for (int beg = 0; beg < d && beg <= lim; beg++) { long long nxt_lim = (lim - beg) / d; vector<long long> vec; int zan = mask.size(); int bb = (d - beg); int xx = 1 + (zan - bb + d - 1) / d; vec.resize(xx, 0LL); long long B = (1LL << m) - 1; int cur = beg; int id = 0; for (int i = 0; i < mask.size(); i++) { int add = x[cur]; long long nw = 0; nw = (mask[i] >> add) | (mask[i] << (m - add)); B &= nw; if (cur == d - 1 || i == mask.size() - 1) { vec[id++] = B; B = (1LL << m) - 1; } cur++; if (cur == d) cur = 0; } assert(id == xx); rec(nxt_lim, vec, F); } } int main() { cin >> d >> m; for (int i = 0; i < d; i++) { cin >> x[i]; } cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; ok.push_back((2LL << a[i]) - 1LL); } cin >> L >> R; L--; R--; rec(R - n + 1, ok, true); if (L - 1 >= 0) rec(L - 1, ok, false); long long ret = 0; for (map<long long, vector<long long> >::iterator it = ans.begin(); it != ans.end(); it++) { vector<long long> tbl = calc(it->first); for (int i = 0; i < m; i++) { ret += tbl[i] * it->second[i]; } } cout << ret << endl; } |
module ula( opcode, // codigo da instrucao
data1, // operando 1
data2, // operando 2
out, // saida de dados
rflags // saida - registrador de flags do processador
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// entradas e saidas
input [OPCODE_WIDTH-1:0] opcode;
input signed [DATA_WIDTH-1:0] data1, data2;
output reg signed [DATA_WIDTH-1:0] out;
output reg [RFLAGS_WIDTH-1:0] rflags;
// variaveis auxiliares
reg xor_data12_sign;
reg signed [DATA_WIDTH-1:0] data2_aux;
always @(*) begin
// defina default das saidas
out = data1;
rflags = 0;
data2_aux = 0;
xor_data12_sign = data1[DATA_WIDTH-1] ^ data2[DATA_WIDTH-1];
// execute a operacao
if (opcode == ADD || opcode == SUB || opcode == CMP) begin
// neste caso, verificaremos se SUB e faremos o complemento de 2
data2_aux = (opcode == SUB || opcode == CMP ? (~ data2) + 1 : data2);
out = data1 + data2_aux;
// iremos verificar overflow agora
case(out[DATA_WIDTH-1])
1'b0: begin
// neste caso, sabemos que houve overflow pois ambos data1
// e data2 sao negativos e a saida out deu positiva
if (data1[DATA_WIDTH-1] == 1 && data2_aux[DATA_WIDTH-1] == 1) begin
rflags[4] = 1;
end
end
default: begin
// neste caso, sabemos que houve overflow pois ambos data1
// e data2 sao positivos e a saida out deu negativa
if (data1[DATA_WIDTH-1] == 0 && data2_aux[DATA_WIDTH-1] == 0) begin
rflags[4] = 1;
end
end
endcase
end else if (opcode == MUL) begin
out = data1 * data2;
// iremos verificar overflow agora
case(out[DATA_WIDTH-1])
1'b0: begin
// neste caso, sabemos que houve overflow pois ou data1
// ou data2 e negativo e a saida deveria ser negativa
// (porem e positiva)
if (xor_data12_sign == 1) begin
rflags[4] = 1;
end
end
default: begin
// neste caso, sabemos que houve overflow pois data1
// e data2 possuem mesmo sinal (positivo ou negativo)
// Logo a saida deveria ser positiva (porem e negativa)
if (xor_data12_sign == 0) begin
rflags[4] = 1;
end
end
endcase
end else if (opcode == DIV) begin
if (data2 != 0) begin
out = data1 / data2;
end else begin
// erro - divisao por zero
rflags[0] = 1;
end
// nao precisamos verificar overflow (divisao nao causa overflow)
end else if (opcode == AND) begin
out = data1 & data2;
end else if (opcode == OR) begin
out = data1 | data2;
end else if (opcode == NOT) begin
out = (data1 == 0 ? 1 : 0) ;
end
if (opcode == CMP) begin
if (out == 0) begin
// neste caso data1 == data2 pois data1-data2 == 0
rflags = 5'b00100;
end else if (xor_data12_sign) begin
// os dados possuem sinais diferentes
if (data1[DATA_WIDTH-1]) begin
// neste caso data1 < data2 pois data1 < 0 e data2 >= 0
rflags = 5'b00010;
end else begin
// neste caso data1 > data2 pois data1 >= 0 e data2 < 0
rflags = 5'b01000;
end
end else begin
// os dados possuem mesmo sinal
if (out[DATA_WIDTH-1]) begin
// neste caso data1 < data2 pois data1-data2 < 0
rflags = 5'b00010;
end else begin
// neste caso data1 > data2 pois data1-data2 > 0
rflags = 5'b01000;
end
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int x1, x2, x3; int Y1, y2, y3; int main() { cin >> x1 >> Y1 >> x2 >> y2; x3 = (x1 <= x2 ? x2 + 1 : x2 - 1); y3 = (Y1 <= y2 ? y2 + 1 : y2 - 1); int r = 0; if (x1 == x2 || Y1 == y2) r = 2; cout << r + 2 * abs(x1 - x3) + 2 * abs(Y1 - y3); return 0; } |
#include <bits/stdc++.h> using namespace std; unordered_map<int, int> mp; bool f(int mid) { if (mp.size() < mid) return false; int a = 0, b = 0; bool fl = 0; for (auto it = mp.begin(); it != mp.end(); it++) { if (it->second > mid) { a = mid; if (fl == 0) { b++; } else { b += 2; fl = 0; } } else if (it->second == mid) { if (a == 0) { a = mid; fl = 1; } else b++; } else if (it->second < mid) b++; } return a >= mid && b >= mid; } int main() { int test; cin >> test; for (int t = 1; t <= test; t++) { int n, ans = 0, imax = 0; cin >> n; mp.clear(); for (int i = 0; i < n; i++) { int temp; cin >> temp; mp[temp]++; imax = max(imax, mp[temp]); } int low = 1, high = imax; while (low <= high) { int mid = low + (high - low) / 2; if (f(mid)) { ans = mid; low = mid + 1; } else high = mid - 1; } cout << ans << endl; } } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Flag synchronizer from clock domain 0 to 1
* See http://www.fpga4fun.com/CrossClockDomain.html
*/
module aceusb_sync(
input clk0,
input flagi,
input clk1,
output flago
);
/* Turn the flag into a level change */
reg toggle;
initial toggle = 1'b0;
always @(posedge clk0)
if(flagi) toggle <= ~toggle;
/* Synchronize the level change to clk1.
* We add a third flip-flop to be able to detect level changes. */
reg [2:0] sync;
initial sync = 3'b000;
always @(posedge clk1)
sync <= {sync[1:0], toggle};
/* Recreate the flag from the level change into the clk1 domain */
assign flago = sync[2] ^ sync[1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_SYMBOL_V
`define SKY130_FD_SC_HD__FAH_SYMBOL_V
/**
* fah: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using li = long long; int get_num(string s) { istringstream is(s); int x; if ((is >> x) && to_string(x) == s) return x; return -1; } void solve(bool read) { int n; cin >> n; vector<pair<string, int>> s(n); int n_e = 0; for (int i = 0; i < n; i++) { cin >> s[i].first >> s[i].second; if (s[i].second) n_e++; } set<string> non_e, non_t, non_num_e, non_num_t; set<int> e_slots, t_slots; for (int i = 1; i <= n_e; i++) e_slots.insert(i); for (int i = n_e + 1; i <= n; i++) t_slots.insert(i); set<string> all_s; for (int i = 0; i < n; i++) { int num = get_num(s[i].first); all_s.insert(s[i].first); if (s[i].second == 1) { if (num >= 1 && num <= n_e) { e_slots.erase(num); continue; } if (num > n_e && num <= n) { non_e.insert(s[i].first); t_slots.erase(num); } else non_num_e.insert(s[i].first); } else { if (num > n_e && num <= n) { t_slots.erase(num); continue; } if (num >= 1 && num <= n_e) { non_t.insert(s[i].first); e_slots.erase(num); } else non_num_t.insert(s[i].first); } } string rnd = ; while (true) { rnd = ; for (int i = 0; i < 6; i++) rnd += a + rand() % 26; if (!all_s.count(rnd)) break; } vector<string> answer; if (e_slots.empty() && t_slots.empty()) { assert(non_num_t.empty() && non_num_e.empty()); if (!non_t.empty()) { assert(!non_e.empty()); string test = *non_t.begin(); non_t.erase(non_t.begin()); e_slots.insert(get_num(test)); answer.push_back( move + test + + rnd); non_num_t.insert(rnd); } } if (!e_slots.empty() || !t_slots.empty()) { while (!e_slots.empty() || !t_slots.empty()) { if (!e_slots.empty()) { if (!non_e.empty()) { answer.push_back( move + *non_e.begin() + + to_string(*e_slots.begin())); t_slots.insert(get_num(*non_e.begin())); non_e.erase(non_e.begin()); e_slots.erase(e_slots.begin()); continue; } if (!non_num_e.empty()) { answer.push_back( move + *non_num_e.begin() + + to_string(*e_slots.begin())); non_num_e.erase(non_num_e.begin()); e_slots.erase(e_slots.begin()); continue; } } if (!t_slots.empty()) { if (!non_t.empty()) { answer.push_back( move + *non_t.begin() + + to_string(*t_slots.begin())); e_slots.insert(get_num(*non_t.begin())); non_t.erase(non_t.begin()); t_slots.erase(t_slots.begin()); continue; } if (!non_num_t.empty()) { answer.push_back( move + *non_num_t.begin() + + to_string(*t_slots.begin())); non_num_t.erase(non_num_t.begin()); t_slots.erase(t_slots.begin()); continue; } } } assert(non_num_e.empty() && non_num_t.empty() && non_t.empty() && non_e.empty()); } printf( %d n , (int)answer.size()); for (string s : answer) printf( %s n , s.c_str()); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int nt = 1; for (int i = 0; i < nt; i++) solve(true); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; signed main() { cin.tie(0); std::ios_base::sync_with_stdio(0); long long n; cin >> n; long long cnt = 10; vector<long long> ans; ans.push_back(10); if (n < 2) { cout << 10; return 0; } ans.push_back(180); long long one_neigh = 1800, two_neighs = 810; for (long long ii = 2; ii < n; ++ii) { long long cnt = 1LL * one_neigh; cnt += 1LL * two_neighs * (ii - 1LL); one_neigh *= 10; two_neighs *= 10; two_neighs %= mod; one_neigh %= mod; cnt %= mod; ans.push_back(cnt); } for (long long ii = n - 1; ii >= 0; --ii) { cout << ans[ii] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int cho[30]; char str[1005]; int main() { int a, b, ans = 0; cin >> a >> b; for (int i = 0; i < a; i++) { cin >> str[i]; cho[str[i] - 96]++; } int tot = b; for (int i = 1; i <= 26; i++) { if (tot == 0) { break; } else if (tot != 0 && cho[i] >= 1) { if (cho[i - 1] != -1) { ans += i; tot--; cho[i] = -1; } } } if (tot == 0) cout << ans << endl; else if (tot > 0) cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[300005], pre[300005], L[300005], R[300005]; int st[300005][19], f[300005], ans; int Max(int l, int r) { int s = f[r - l]; return a[st[l][s]] > a[st[r - (1 << s)][s]] ? st[l][s] : st[r - (1 << s)][s]; } void solve(int l, int r) { if (l > r) return; if (l == r) { ans += a[l] == 1; return; } int k = Max(l, r); if (k - l < r - k) { for (int i = l; i <= k; i++) if (i + a[k] - 1 >= k && i + a[k] - 1 <= r && R[i] >= i + a[k] - 1) ans++; } else for (int i = k; i <= r; i++) if (i - a[k] + 1 <= k && i - a[k] + 1 >= l && L[i] <= i - a[k] + 1) ans++; solve(l, k - 1), solve(k + 1, r); } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) f[i] = f[i >> 1] + 1; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) st[i][0] = a[i] > a[i + 1] ? i : (i + 1); for (int i = 1; i <= n; i++) L[i] = max(L[i - 1], pre[a[i]] + 1), pre[a[i]] = i; for (int i = 1; i <= n; i++) pre[i] = n + 1; R[n] = n, pre[a[n]] = n; for (int i = n - 1; i >= 1; i--) R[i] = min(R[i + 1], pre[a[i]] - 1), pre[a[i]] = i; for (int i = 1; 1 << i < n; i++) for (int j = 1; j <= n - (1 << i); j++) st[j][i] = a[st[j][i - 1]] > a[st[j + (1 << i - 1)][i - 1]] ? st[j][i - 1] : st[j + (1 << i - 1)][i - 1]; solve(1, n); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> unsigned long long int p[64][2][2], m, pi[64]; void mul_matrix(int size, unsigned long long int (*a)[2], unsigned long long int (*b)[2], unsigned long long int (*dest)[2]) { int i, j, k; for (i = 0; i < size; i++) for (j = 0; j < 2; j++) { dest[i][j] = 0; for (k = 0; k < 2; k++) dest[i][j] = (dest[i][j] + (a[i][k] * b[k][j]) % m) % m; } } void init_mat() { int i; p[0][0][0] = p[0][0][1] = p[0][1][0] = 1; p[0][1][1] = 0; pi[0] = 2; for (i = 1; i < 64; i++) { mul_matrix(2, p[i - 1], p[i - 1], p[i]); pi[i] = (pi[i - 1] * pi[i - 1]) % m; } } int main() { unsigned long long int n, k, t, zero = 0, one = 1, ans = 1, l, i; unsigned long long int base1[1][2] = {0, 1}, base2[1][2] = {1, 0}, dest[1][2]; scanf( %lld %lld %lld %lld , &n, &k, &l, &m); init_mat(); for (i = 0, t = n - 1; t; t >>= 1, i++) { if (t & 1) { mul_matrix(1, base1, p[i], dest); memcpy(base1, dest, sizeof(dest)); mul_matrix(1, base2, p[i], dest); memcpy(base2, dest, sizeof(dest)); } } for (i = 0, t = n; t; t >>= 1, i++) if (t & 1) one = (one * pi[i]) % m; zero = ((base1[0][0] + base1[0][1]) % m + (base2[0][0] + base2[0][1]) % m) % m; one = ((one + m) - zero) % m; for (t = k, i = 0; i < l; t >>= 1, i++) { if (t & 1) ans = (ans * one) % m; else ans = (ans * zero) % m; } if (t) { printf( 0 ); return 0; } printf( %u , ans % m); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1000 * 1000]; int main() { int t; cin >> t; double s = 0; for (int i = 0; i < t; i++) { cin >> a[i]; s += a[i]; } vector<int> ind; for (int i = 0; i < t; i++) { double p = ((s - a[i]) / (t - 1)); if (a[i] == p) ind.push_back(i + 1); } cout << ind.size() << endl; for (int i = 0; i < ind.size(); i++) { cout << ind[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[5005], cnt, tmp, nxt, V[5005], j, n, i; long long dp[2][5005], ans; struct LS { int pos, val; } ls[5005]; inline bool cmp(LS aa, LS bb) { return aa.val < bb.val; } int main() { cin >> n; for (i = 1; i <= n; ++i) cin >> a[i], ls[i].val = a[i], ls[i].pos = i; sort(ls + 1, ls + n + 1, cmp); ls[0].val = -1000000001; for (i = 1; i <= n; ++i) { if (ls[i].val != ls[i - 1].val) ++cnt, V[cnt] = ls[i].val; a[ls[i].pos] = cnt; } for (i = 1; i <= a[1]; ++i) dp[0][i] = V[a[1]] - V[i]; for (i = a[1] + 1; i <= cnt; ++i) dp[0][i] = 0; for (i = 2; i <= n; tmp ^= 1, ++i) { nxt = tmp ^ 1; dp[nxt][0] = 1e16; for (j = 1; j <= cnt; ++j) dp[nxt][j] = min(dp[nxt][j - 1], dp[tmp][j] + abs(V[a[i]] - V[j])); } for (ans = 1e16, j = 1; j <= cnt; ++j) ans = min(ans, dp[tmp][j]); cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 85 - 69; long long int a[maxn], su[maxn], dp[maxn]; int n; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i < n; i++) cin >> a[i]; for (int i = n - 1; i > 0; i--) { su[i] = su[i + 1] + a[i] - (a[i] & 1); if (a[i] == 1) su[i] = 0; } dp[0] = 0; long long int sum = 0, ans = 0; for (int i = 1; i < n; i++) { sum += a[i] - (a[i] & 1); if (a[i] == 1) sum = 0; dp[i] = max(dp[i - 1] + a[i] - (a[i] % 2 == 0), sum); ans = max(ans, dp[i] + su[i + 1]); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const string ALICE = Alice , BOB = Bob ; void solve_case() { int N, K; cin >> N >> K; if (K % 3 != 0) { cout << (N % 3 != 0 ? ALICE : BOB) << n ; return; } N %= K + 1; cout << (N % 3 == 0 && N < K ? BOB : ALICE) << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int T; cin >> T; while (T-- > 0) solve_case(); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR4BB_BEHAVIORAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 30.06.2017 11:21:41
// Design Name:
// Module Name: memoryaccess
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: I'll design this hardware while imagining that it is for
// a pipelined processor. To make it single-cycle, I'll just instantiate each
// module without a register and use continuous assignment to connect the inputs
// with the outputs of the previous segment. This will make it easier to adapt
// code.
//
// Instantialising ALUResultsIn with A and also using CA to link ALUResultsOut
// and ALUResultsIn might not. I will have to edit if the implementation doesn't
// work and/or the simulation doesn't work.
//////////////////////////////////////////////////////////////////////////////////
module memoryaccess(
output [31:0] ReadDataM, ALUResultOut, PCBranchM2,
output [4:0] WriteRegM2,
output RegWriteM2, MemToRegM2, PCSrcM,
input [31:0] WriteDataM, ALUResultIn, PCBranchM1,
input [4:0] WriteRegM1,
input BranchM, MemWriteM, MemToRegM1, RegWriteM1, ZerowireM, clk
);
dmem dmem_mem(
.RD( ReadDataM ),
.A( ALUResultIn ),
.WD( WriteDataM ),
.WE( MemWriteM ),
.clk( clk )
);
assign PCSrcM = BranchM & ZerowireM;
//Send signals to next section
assign ALUResultOut = ALUResultIn;
assign WriteRegM2 = WriteRegM1;
assign PCBranchM2 = PCBranchM1;
assign MemToRegM2 = MemToRegM1;
assign RegWriteM2 = RegWriteM1;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &p) { os << { << p.first << , << p.second << } ; return os; } const int N = 3e5 + 5; const int oo = 1e9 + 7; vector<pair<int, pair<int, int> > > g[N]; int f[N]; int ans[N]; int x[N]; int y[N]; bool vis[N]; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int w; cin >> x[i] >> y[i] >> w; g[x[i]].push_back({i, {y[i], w}}); g[y[i]].push_back({i, {x[i], w}}); } for (int i = 2; i <= n - 1; i++) { for (auto p : g[i]) { f[i] += p.second.second; } assert(f[i] % 2 == 0); f[i] /= 2; } queue<int> q; q.push(1); vis[1] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (auto p : g[u]) { int i = p.first; int v = p.second.first; int w = p.second.second; if (vis[v]) continue; if (x[i] == u) ans[i] = 0; else ans[i] = 1; if (v == n) continue; f[v] -= w; if (f[v] == 0) { vis[v] = 1; q.push(v); } } } for (int i = 1; i <= m; i++) cout << ans[i] << n ; } |
`timescale 1ns / 1ps
//Source: http://www.bigmessowires.com/2009/06/21/fpga-pong/
//
// -----------------------------------------------
// updates the ball and paddle positions, and
// determines the output video image
// -----------------------------------------------
module game_module2015(input clk25, input Reset,
input [9:0] xpos,
input [9:0] ypos,
input rota,
input rotb,
output [2:0] red,
output [2:0] green,
output [1:0] blue);
// paddle movement
reg [8:0] paddlePosition;
reg [2:0] quadAr, quadBr;
always @(posedge clk25) quadAr <= {quadAr[1:0], rota};
always @(posedge clk25) quadBr <= {quadBr[1:0], rotb};
always @(posedge clk25)
if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1])
begin
if(quadAr[2] ^ quadBr[1]) begin
if(paddlePosition < 508) // make sure the value doesn't overflow
paddlePosition <= paddlePosition + 3'd4;
end
else begin
if(paddlePosition > 2'd3) // make sure the value doesn't underflow
paddlePosition <= paddlePosition - 3'd4;
end
end
// ball movement
reg [9:0] ballX;
reg [8:0] ballY;
reg ballXdir, ballYdir;
reg bounceX, bounceY;
wire endOfFrame = (xpos == 0 && ypos == 480);
always @(posedge clk25) begin
if (endOfFrame) begin // update ball position at end of each frame
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballX <= 480;
ballY <= 300;
end
else begin
if (ballXdir ^ bounceX)
ballX <= ballX + 2'd2;
else
ballX <= ballX - 2'd2;
if (ballYdir ^ bounceY)
ballY <= ballY + 2'd2;
else
ballY <= ballY - 2'd2;
end
end
end
// pixel color
reg [5:0] missTimer;
wire visible = (xpos < 640 && ypos < 480);
wire top = (visible && ypos <= 3);
wire bottom = (visible && ypos >= 476);
wire left = (visible && xpos <= 3);
wire right = (visible && xpos >= 636);
wire border = (visible && (left || right || top));
wire paddle = (xpos >= paddlePosition+4 && xpos <= paddlePosition+124 && ypos >= 440 && ypos <= 447);
wire ball = (xpos >= ballX && xpos <= ballX+7 && ypos >= ballY && ypos <= ballY+7);
wire background = (visible && !(border || paddle || ball));
wire checkerboard = (xpos[5] ^ ypos[5]);
wire missed = visible && missTimer != 0;
assign red = { missed || border || paddle, 2'b00 };
assign green = { !missed && (border || paddle || ball), 2'b00 };
assign blue = { !missed && (border || ball), background && checkerboard};
// ball collision
always @(posedge clk25) begin
if (!endOfFrame) begin
if (ball && (left || right))
bounceX <= 1;
if (ball && (top || bottom || (paddle && ballYdir)))
bounceY <= 1;
if (ball && bottom)
missTimer <= 63;
end
else begin
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballXdir <= 1;
ballYdir <= 1;
bounceX <= 0;
bounceY <= 0;
end
else begin
if (bounceX)
ballXdir <= ~ballXdir;
if (bounceY)
ballYdir <= ~ballYdir;
bounceX <= 0;
bounceY <= 0;
if (missTimer != 0)
missTimer <= missTimer - 1'b1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1010; long long c[2][2][MAXN][MAXN] = {0}; int n, m; long long val; int lowbit(int x) { return x & -x; } void add(int a, int b) { for (int i = a; i <= n; i += lowbit(i)) for (int j = b; j <= n; j += lowbit(j)) c[a & 1][b & 1][i][j] ^= val; } long long sum(int a, int b) { long long ans = 0; for (int i = a; i >= 1; i -= lowbit(i)) for (int j = b; j >= 1; j -= lowbit(j)) ans ^= c[a & 1][b & 1][i][j]; return ans; } int main() { scanf( %d%d , &n, &m); int x1, x2, y1, y2, op; long long ans; for (int i = 1; i <= m; i++) { scanf( %d , &op); if (op == 1) { scanf( %d%d%d%d , &x1, &y1, &x2, &y2); ans = sum(x2, y2) ^ sum(x2, y1 - 1) ^ sum(x1 - 1, y2) ^ sum(x1 - 1, y1 - 1); printf( %I64d n , ans); } else { scanf( %d%d%d%d%I64d , &x1, &y1, &x2, &y2, &val); add(x1, y1); add(x2 + 1, y1); add(x1, y2 + 1); add(x2 + 1, y2 + 1); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string arr[11] = { ABSINTH , BEER , BRANDY , CHAMPAGNE , GIN , RUM , SAKE , TEQUILA , VODKA , WHISKEY , WINE }; int n; cin >> n; int counter = 0; string str; int num_convert; for (int i = 0; i < n; i++) { str = ; cin >> str; if (isdigit(str.at(0))) { num_convert = stoi(str, nullptr, 10); if (num_convert < 18) { counter++; } } else { for (int i = 0; i < 11; i++) { if (str == arr[i]) { counter++; } } } } cout << counter; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 != 0) cout << -1 << endl; else { for (int i = 1; i <= n; i++) { if (i % 2 == 0) cout << i - 1 << ; else cout << i + 1 << ; } } return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 28370 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8,
w7,
w14336,
w14329,
w32,
w14297,
w112,
w14185,
w28370;
assign w1 = i_data0;
assign w112 = w7 << 4;
assign w14185 = w14297 - w112;
assign w14297 = w14329 - w32;
assign w14329 = w14336 - w7;
assign w14336 = w7 << 11;
assign w28370 = w14185 << 1;
assign w32 = w1 << 5;
assign w7 = w8 - w1;
assign w8 = w1 << 3;
assign o_data0 = w28370;
//multiplier_block area estimate = 6725.98062426471;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class X, class Y> void amax(X& x, const Y& y) { if (x < y) x = y; } template <class X, class Y> void amin(X& x, const Y& y) { if (x > y) x = y; } const int INF = 1e9 + 10; const long long INFL = (long long)1e18 + 10; const int MAX = 2e5 + 10; int n; long long l[MAX], r[MAX]; map<long long, long long> cnt, inc, ddec; void process() { cin >> n; for (int i = 1; i <= n; i++) cin >> l[i] >> r[i]; long long maxr = 0, minl = INFL; for (int i = 1; i <= n; i++) { inc[l[i]] = ddec[l[i]] = 0; inc[r[i]] = ddec[r[i]] = 0; amax(maxr, r[i]); amin(minl, l[i]); } ddec[maxr + 1] = 0; for (int i = 1; i <= n; i++) { inc[l[i]]++; auto p2 = ddec.find(r[i]); p2 = next(p2); p2->second++; } long long ppost = minl - 1; int psum = 0; for (auto p : inc) { psum -= ddec[p.first]; cnt[psum] += p.first - ppost - 1; psum += p.second; cnt[psum]++; ppost = p.first; } for (int i = 1; i <= n; i++) cout << cnt[i] << ; } int main() { ios_base::sync_with_stdio(false); process(); } |
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_9_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_9_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_9_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> int a[105], stor[105]; int main() { int n; scanf( %d , &n); int i; for (i = 0; i < n; i++) scanf( %d , &a[i]); int j, k = 0, max; max = a[2] - a[0]; for (i = 1; i < n - 1; i++) { if (i == 1) { max = a[2] - a[0]; for (j = 2; j < n - 1; j++) { if (a[j + 1] - a[j] > max) max = a[j + 1] - a[j]; } } else { max = a[1] - a[0]; for (j = 0; j < n; j++) { if (j == i) { if (a[j + 1] - a[j - 1] > max) max = a[j + 1] - a[j - 1]; } if (j + 1 == i) { if (a[j + 2] - a[j] > max) max = a[j + 2] - a[j]; } else if (a[j + 1] - a[j] > max) max = a[j + 1] - a[j]; } } stor[k++] = max; } int min = stor[0]; for (i = 0; i < k; i++) { if (stor[i] < min) min = stor[i]; } printf( %d , min); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, s, x, y, cur, pr, cans, tot, a[2005][2005], dp[4][2005][2005]; vector<pair<int, int> > all[10]; int ans[10][10]; int dist(int x2, int y2, int x3, int y3) { return abs(x2 - x3) + abs(y2 - y3); } int main() { ios_base::sync_with_stdio(0); cin >> n >> m >> k >> s; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> cur; a[i][j] = cur; all[cur].push_back({i, j}); } } for (int i = 1; i <= k; i++) { for (int j = 0; j < 4; j++) for (int z = 0; z <= n + 1; z++) { for (int zr = 0; zr <= m + 1; zr++) { dp[j][z][zr] = -1e9; } } for (int j = 1; j <= n; j++) { for (int z = 1; z <= m; z++) { dp[0][j][z] = max(dp[0][j][z - 1] + 1, dp[0][j - 1][z] + 1); if (a[j][z] == i) dp[0][j][z] = max(dp[0][j][z], 0); } } for (int j = n; j >= 1; j--) { for (int z = 1; z <= m; z++) { dp[1][j][z] = max(dp[1][j][z - 1] + 1, dp[1][j + 1][z] + 1); if (a[j][z] == i) dp[1][j][z] = max(dp[1][j][z], 0); } } for (int j = 1; j <= n; j++) { for (int z = m; z >= 1; z--) { dp[2][j][z] = max(dp[2][j][z + 1] + 1, dp[2][j - 1][z] + 1); if (a[j][z] == i) dp[2][j][z] = max(dp[2][j][z], 0); } } for (int j = n; j >= 1; j--) { for (int z = m; z >= 1; z--) { dp[3][j][z] = max(dp[3][j][z + 1] + 1, dp[3][j + 1][z] + 1); if (a[j][z] == i) dp[3][j][z] = max(dp[3][j][z], 0); } } for (int j = i; j <= k; j++) { cans = -1e9; for (int z = 0; z < all[j].size(); z++) { x = all[j][z].first; y = all[j][z].second; cans = max(cans, dp[0][x][y]); cans = max(cans, dp[1][x][y]); cans = max(cans, dp[2][x][y]); cans = max(cans, dp[3][x][y]); } ans[i][j] = cans; } } tot = -1e9; for (int i = 0; i < s; i++) { cin >> cur; if (i) { if (pr < cur) tot = max(tot, ans[pr][cur]); else tot = max(tot, ans[cur][pr]); } pr = cur; } cout << tot; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 5; long long int dp[N][102]; int main() { int n, k, m; scanf( %d%d%d , &n, &k, &m); for (int i = 1; i <= 9; i++) dp[1][i % k]++; long long int wynik = 0, p = 1; for (int x = 1; x <= n - 1; x++) { p = (p * 10) % k; wynik = (wynik * 10) % m; wynik += dp[x][0] % m; for (int i = 1; i < k; i++) { dp[x][i] %= m; for (int j = 0; j <= 9; j++) if (j || (x != n - 1)) dp[x + 1][(i + j * p) % k] += dp[x][i]; } for (int j = 1; j <= 9; j++) dp[x + 1][(j * p) % k]++; } wynik *= 9; wynik += dp[n][0]; printf( %lld n , wynik % m); } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T& x) { bool fu = 0; char c; for (c = getchar(); c <= 32; c = getchar()) ; if (c == - ) fu = 1, c = getchar(); for (x = 0; c > 32; c = getchar()) x = x * 10 + c - 0 ; if (fu) x = -x; }; template <class T> inline void read(T& x, T& y) { read(x); read(y); } template <class T> inline void read(T& x, T& y, T& z) { read(x); read(y); read(z); } inline char getc() { char c; for (c = getchar(); c <= 32; c = getchar()) ; return c; } const int N = 10010; const double pi = 2 * acos(0); const double eps = 1e-9; int w, h, n, m, i, j, st, g; double L0, R0, R; long long x[N], y[N]; double d[1010][1010], an[1010][1010]; int p[N]; double c[N]; double D(int i, int j) { return sqrt((1LL * (x[i] - x[j]) * (x[i] - x[j])) + (1LL * (y[i] - y[j]) * (y[i] - y[j]))); } double geta(int i, int j) { return atan2(y[j] - y[i], x[j] - x[i]); } bool same(double a, double b) { return abs(a - b) <= eps; } double ans; void add(double L, double R) { if (R > pi) { add(L, pi); add(-pi, R - 2 * pi); } else if (L < -pi) { add(L + 2 * pi, pi); add(-pi, R); } else c[++g] = L - 1e-15, c[++g] = R + 1e-15; } bool cmp(int x, int y) { return c[x] < c[y]; } bool ok(double R) { int i, j, k; double tt; g = 0; c[++g] = -pi; c[++g] = pi; if (x[st] < R) { tt = acos(x[st] / R); for (k = 1; k <= 2; k++) add(-pi - tt, -pi + tt); } if (w - x[st] < R) { tt = acos((w - x[st]) / R); for (k = 1; k <= 2; k++) add(-tt, tt); } if (y[st] < R) { tt = acos(y[st] / R); for (k = 1; k <= 2; k++) add(-pi / 2 - tt, -pi / 2 + tt); } if (h - y[st] < R) { tt = acos((h - y[st]) / R); for (k = 1; k <= 2; k++) add(pi / 2 - tt, pi / 2 + tt); } for (i = 1; i <= n; i++) if (i != st && d[st][i] < 2 * R && d[st][i] > eps) { tt = acos(d[st][i] / 2 / R); add(an[st][i] - tt, an[st][i] + tt); } for (i = 1; i <= g; i++) p[i] = i; sort(p + 1, p + 1 + g, cmp); int s = 0; for (i = 1; i <= g; i++) if ((s += (p[i] & 1 ? 1 : -1)) < 3 && i + 1 <= g && c[p[i + 1]] - c[p[i]] > eps) return 1; return 0; } int main() { read(w, h, n); for (i = 1; i <= n; i++) cin >> x[i] >> y[i]; for (i = 1; i <= n; i++) { int t = rand() % i + 1; swap(x[i], x[t]); swap(y[i], y[t]); } for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) d[i][j] = D(i, j), an[i][j] = geta(i, j); for (st = 1; st <= n; st++) if (ok(R)) { L0 = R; R0 = 2e6; while (L0 + eps < R0) { R = (L0 + R0) / 2; if (ok(R)) L0 = R; else R0 = R; } } cout << fixed << setprecision(10) << R << endl; scanf( n ); return 0; } |
/*
File: earb.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response),
arbitrates between the active channels, and forwards the result on to
the transmit channel.
The arbitration order is (fixed, highest to lowest)
1) read responses
2) read requests
3) writes
*/
module e_tx_arbiter (/*AUTOARG*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_rd_en, e_tx_access, e_tx_write,
e_tx_datamode, e_tx_ctrlmode, e_tx_dstaddr, e_tx_srcaddr,
e_tx_data,
// Inputs
clk, reset, emwr_rd_data, emwr_empty, emrq_rd_data, emrq_empty,
emrr_rd_data, emrr_empty, e_tx_rd_wait, e_tx_wr_wait, e_tx_ack
);
// tx clock
input clk;
input reset;
// from write request FIFO (slave)
input [102:0] emwr_rd_data;
output emwr_rd_en;
input emwr_empty;
// from read request fifo (slave port)
input [102:0] emrq_rd_data;
output emrq_rd_en;
input emrq_empty;
// from read response FIFO (master port)
input [102:0] emrr_rd_data;
output emrr_rd_en;
input emrr_empty;
// eMesh master port, to TX
output e_tx_access;
output e_tx_write;
output [1:0] e_tx_datamode;
output [3:0] e_tx_ctrlmode;
output [31:0] e_tx_dstaddr;
output [31:0] e_tx_srcaddr;
output [31:0] e_tx_data;
input e_tx_rd_wait;
input e_tx_wr_wait;
// Ack from TX protocol module
input e_tx_ack;
// Control bits inputs (none)
//############
//# Arbitrate & forward
//############
reg ready;
reg [102:0] fifo_data;
// priority-based ready signals
wire rr_ready = ~emrr_empty & ~emm_tx_wr_wait;
wire rq_ready = ~emrq_empty & ~emm_tx_rd_wait & ~rr_ready;
wire wr_ready = ~emwr_empty & ~emm_tx_wr_wait & ~rr_ready & ~rq_ready;
// FIFO read enables, when we're idle or done with the current datum
wire emrr_rd_en = rr_ready & (~ready | emtx_ack);
wire emrq_rd_en = rq_ready & (~ready | emtx_ack);
wire emwr_rd_en = wr_ready & (~ready | emtx_ack);
always @ (posedge clk) begin
if( reset ) begin
ready <= 1'b0;
fifo_data <= 'd0;
end else begin
if( emrr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrr_rd_data;
end else if( emrq_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrq_rd_data;
end else if( emwr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emwr_rd_data;
end else if( emtx_ack ) begin
ready <= 1'b0;
end
end // else: !if( reset )
end // always @ (posedge clock)
//#############################
//# Break-out the emesh signals
//#############################
assign e_tx_access = ready;
assign e_tx_write = fifo_data[102];
assign e_tx_datamode = fifo_data[101:100];
assign e_tx_ctrlmode = fifo_data[99:96];
assign e_tx_dstaddr = fifo_data[95:64];
assign e_tx_srcaddr = fifo_data[63:32];
assign e_tx_data = fifo_data[31:0];
endmodule // e_tx_arbiter
|
module count_hours(
twentyfour_mode,
manual_inc,
automatic_inc,
ones_digit,
tens_digit,
am,
pm,
count_out
);
// port declarations
input twentyfour_mode;
input manual_inc;
input automatic_inc;
output [3:0] ones_digit;
output [3:0] tens_digit;
output reg am;
output reg pm;
output reg count_out;
// wire declarations
wire carry;
reg module_reset;
reg pre_count;
reg increment;
// teh logikz
initial module_reset <= 0;
bcd_counter u1(
module_reset,
increment,
ones_digit,
carry
);
bcd_counter u2(
module_reset,
carry,
tens_digit,
);
always begin
// We handle manual increments by making it
if (manual_inc) begin
count_out <= 0;
increment <= 1;
// Since twelve hour mode cannot allow 0 hours (damn you, non computer
// - scientists / engineers!), we have to take care of the case in which
// - it becomes zero.
end else if (!twentyfour_mode && tens_digit == 4'h0 && ones_digit == 4'h0)
begin
increment <= 1;
#1 increment <= 0;
// I had to add this here to make it work; I don't know why.
increment <= automatic_inc;
// This is the general case.
end else begin
increment <= automatic_inc;
count_out <= module_reset;
end
module_reset <= (
!twentyfour_mode && tens_digit == 4'h1 && ones_digit == 4'h3
|| twentyfour_mode && tens_digit == 4'h2 && ones_digit == 4'h4
);
end
always @ (posedge module_reset) begin
if (!twentyfour_mode)
if (am) begin
pm <= 1;
am <= 0;
end else begin
am <= 1;
pm <= 0;
end
else begin
am <= 0;
pm <= 0;
end
end
endmodule
|
module ALU(clk, control, data_input1, data_input2, data_output, zero);
input clk;
input [3:0] control;
input signed [31:0] data_input1, data_input2;
output reg signed [31:0] data_output;
output reg zero;
// Control signal definitions, taken from textbook page 260
// High zero to indicate when output is zero (beq and sub)
always@(posedge clk)
begin
// R-type Add, Load word, Store word,
if (control == 4'b0010) begin
data_output = data_input1 + data_input2;
zero = 0;
end
// // R-type Subtract, Branch equal
else if (control == 4'b0110)
begin
data_output = data_input1 - data_input2;
if (data_output == 0)
zero = 1;
else
zero = 0;
end
// And
else if (control == 4'b0000) begin
data_output = data_input1 & data_input2;
zero = 0;
end
// Or
else if (control == 4'b0001) begin
data_output = data_input1 | data_input2;
zero = 0;
end
// Set less than
else if (control == 4'b0111) begin
if (data_input2 < data_input1)
data_output = 1;
else
data_output = 0;
zero = 0;
end
// Nor
else if (control == 4'b1100) begin
data_output = ~(data_input1 | data_input2);
zero =0;
end
else
begin
data_output = 0;
zero =0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND4_BEHAVIORAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_BEHAVIORAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sat Jun 03 23:38:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_overlay_0_0 -prefix
// system_vga_overlay_0_0_ system_vga_overlay_0_0_stub.v
// Design : system_vga_overlay_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_overlay,Vivado 2016.4" *)
module system_vga_overlay_0_0(clk, rgb_0, rgb_1, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_0[23:0],rgb_1[23:0],rgb[23:0]" */;
input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, k; int a[105]; map<int, bool> q; int main() { while (~scanf( %d %d , &n, &k)) { q.clear(); for (int i = 0; i < k; i++) scanf( %d , &a[i]); int t = 1; int t2 = n; for (int i = 0; i < k; i++) { int t3 = (a[i] %= t2); while (t3--) { t++; if (t > n) t = 1; if (q[t]) t3++; } printf( %d%c , t, i == k - 1 ? n : ); q[t] = 1; t++; if (t > n) t = 1; while (q[t]) { t++; if (t > n) t = 1; } t2--; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { if (x > y) swap(x, y); if (x <= 0) return y; if (y % x == 0) return x; return gcd(y % x, x); } int main() { vector<long long> a; long long b[400000]; bool c[400000]; for (long long i = 0; i < (long long)(400000); i++) { b[i] = 0; c[i] = false; } int n, k; long long g; long long x, y, z, xx, yy, zz; long long s, ans; bool v = true; ans = 0; scanf( %I64d %I64d %I64d , &z, &x, &y); g = gcd(x, y); a.push_back(0); c[0] = true; xx = 0; while (true) { if (xx >= y) xx -= y; else xx += x; if (c[xx]) break; else c[xx] = true; a.push_back(xx); } xx = 0; yy = 0; zz = 0; while (true) { if (xx < a[yy]) { b[xx] = yy; zz = max(zz, yy); xx++; } else yy++; if (yy >= a.size()) break; } ans = 0; if (z < (x + y - g)) { for (long long i = 0; i < (long long)(z + 1); i++) ans += b[i]; printf( %I64d n , ans); return 0; } for (long long i = 0; i < (long long)(x + y - g); i++) { ans += b[i]; } xx = (x + y) / g; yy = z / g; zz = (xx + yy) * (yy - xx + 1) / 2; zz *= g; ans += zz; zz = (z % g) + 1; zz *= ((z / g) + 1); ans += zz; printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct fastIO { inline fastIO operator>>(int& num) { num = 0; char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); bool foo = 0; if (c == - ) { foo = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } if (foo) num = -num; return *this; } inline fastIO operator>>(long long& num) { num = 0; char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); bool foo = 0; if (c == - ) { foo = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } if (foo) num = -num; return *this; } inline fastIO operator>>(float& num) { scanf( %f , &num); return *this; } inline fastIO operator>>(double& num) { scanf( %lf , &num); return *this; } inline fastIO operator>>(long double& num) { scanf( %Lf , &num); return *this; } inline fastIO operator>>(char& num) { num = getchar(); while (num == || num == n ) num = getchar(); return *this; } inline fastIO operator>>(char* num) { int cnt = 0; char c = getchar(); while (c == || c == n ) c = getchar(); while (c != && c != n ) { num[cnt++] = c; c = getchar(); } num[cnt] = 0; return *this; } inline fastIO operator>>(string& num) { cin >> num; return *this; } inline void printInt(const int& num) { if (num < 10) { putchar(num + 0 ); return; } printInt(num / 10); putchar((num % 10) + 0 ); } inline void printINT(const long long& num) { if (num < 10) { putchar(num + 0 ); return; } printINT(num / 10); putchar((num % 10) + 0 ); } inline fastIO operator<<(const int& num) { if (num < 0) putchar( - ), printInt(-num); else printInt(num); return *this; } inline fastIO operator<<(const long long& num) { if (num < 0) putchar( - ), printINT(-num); else printINT(num); return *this; } inline fastIO operator<<(const float& num) { printf( %.10f , num); return *this; } inline fastIO operator<<(const double& num) { printf( %.16lf , num); return *this; } inline fastIO operator<<(const long double& num) { printf( %.20Lf , num); return *this; } inline fastIO operator<<(const char& num) { putchar(num); return *this; } inline fastIO operator<<(const char* num) { for (int i = 0; num[i]; i++) putchar(num[i]); return *this; } inline fastIO operator<<(const string& num) { cout << num; return *this; } } fio; int n, m, k; int fuck[17][17]; int shit[17][17][17]; int dy[17]; int ans = 0; void dfs(int x, int y, int mx) { if (x == n) { for (int i = 1; i <= mx; i++) for (int j = i + 1; j <= mx; j++) if (dy[i] && dy[j] && dy[i] == dy[j]) return; int fri = 0, bb = k; for (int i = 1; i <= mx; i++) { if (!dy[i]) fri++; else bb--; } int fk = 1; for (int i = 0; i < fri; i++) { fk *= bb; bb--; } ans += fk; if (ans > 1000000007) ans -= 1000000007; return; } for (int i = 1; i <= mx + 1; i++) { if (shit[x][y][i]) continue; for (int ii = x; ii < n; ii++) for (int jj = y; jj < m; jj++) shit[ii][jj][i]++; bool fau = 1; if (fuck[x][y] && dy[i] && fuck[x][y] != dy[i]) fau = 0; if (fau) { bool dyed = 0; if (!dy[i]) { dy[i] = fuck[x][y]; dyed = 1; } if (y < m - 1) dfs(x, y + 1, min(max(mx, i), k - 1)); else dfs(x + 1, 0, min(max(mx, i), k)); if (dyed) dy[i] = 0; } for (int ii = x; ii < n; ii++) for (int jj = y; jj < m; jj++) shit[ii][jj][i]--; } } int main() { fio >> n >> m >> k; if (n + m - 1 > k) { fio << 0 n ; return 0; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) fio >> fuck[i][j]; dfs(0, 0, 0); fio << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T& x) { int f = 0, c = getchar(); x = 0; while (!isdigit(c)) f |= c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 48, c = getchar(); if (f) x = -x; } template <typename T, typename... Args> inline void read(T& x, Args&... args) { read(x); read(args...); } template <typename T> void write(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 48); } template <typename T> void writes(T x) { write(x); putchar( ); } template <typename T> void writeln(T x) { write(x); puts( ); } template <typename T> inline bool chkmin(T& x, const T& y) { return y < x ? (x = y, true) : false; } template <typename T> inline bool chkmax(T& x, const T& y) { return x < y ? (x = y, true) : false; } const int maxn = (int)3e5 + 10; const long long inf = (long long)1e18; const int mod = (int)1e9 + 7; int n, a[maxn]; long long ans; vector<int> v[maxn]; int main() { read(n); for (int i = (1); i < (2 * n + 1); i++) read(a[i]); for (int i = (1); i < (2 * n + 1); i++) { v[a[i]].push_back(i); } int now = 1; for (int i = (1); i < (n + 1); i++) { ans += abs(v[i][0] - now); now = v[i][0]; } now = 1; for (int i = (1); i < (n + 1); i++) { ans += abs(v[i][1] - now); now = v[i][1]; } write(ans); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: MossbauerLab
// Engineer: EvilLord666 (Ushakov MV)
//
// Create Date: 21:01:28 08/30/2017
// Design Name: messbauer_test_environment
// Module Name: messbauer_diff_discriminator_signals
// Project Name:
// Target Devices: Spartan 6
// Tool versions: ISE 14.7
// Description: ALINX AX309 MESSBAUER DIFF DISCRIMINATOR SIGNALS
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module messbauer_diff_discriminator_signals #
(
parameter GCLK_PERIOD = 20, // nanoseconds
parameter LOWER_THRESHOLD_DURATION = 3, // GCLK_PERIOD
parameter UPPER_THRESHOLD_DURATION = 1, // GCLK_PERIOD
parameter DISCRIMINATOR_IMPULSES_PAUSE = 10, // GCLK_PERIOD
parameter IMPULSES_PER_CHANNEL = 16,
parameter IMPULSES_FOR_SELECTION = 4 // number of impulses passes through diff disriminator MUST be smaller than IMPULSES_PER_CHANNEL
)
(
input wire aclk,
input wire areset_n,
input wire channel,
output reg lower_threshold,
output reg upper_threshold
);
localparam INITIAL_STATE = 0;
localparam LOWER_THRESHOLD_HIGH_PHASE = 1;
localparam UPPER_THRESHOLD_HIGH_PHASE = 2;
localparam UPPER_THRESHOLD_LOW_PHASE = 3;
localparam LOWER_THRESHOLD_LOW_PHASE = 4;
localparam FINAL_STATE = 5;
localparam PAUSE_DURATION = 4;
reg enable;
reg first_enable;
reg[15:0] clk_counter;
reg[15:0] impulse_counter;
reg[15:0] total_impulse_counter;
reg[2:0] state;
reg impulse_rejected;
reg period_done;
always @(posedge aclk)
begin
if(~areset_n)
begin
clk_counter <= 0;
impulse_counter <= 0;
total_impulse_counter <= 0;
state <= INITIAL_STATE;
lower_threshold <= 0;
upper_threshold <= 0;
first_enable <= 1;
impulse_rejected <= 1;
end
else
begin
if(first_enable || enable)
begin
clk_counter <= clk_counter + 1'b1;
case (state)
INITIAL_STATE:
begin
clk_counter <= 0;
state <= LOWER_THRESHOLD_HIGH_PHASE;
impulse_rejected <= 0;
period_done <= 0;
end
LOWER_THRESHOLD_HIGH_PHASE:
begin
lower_threshold <= 1;
if(clk_counter == 1)
begin
// check should we generate upper
if(impulse_counter <= IMPULSES_FOR_SELECTION)
state <= LOWER_THRESHOLD_LOW_PHASE;
else state <= UPPER_THRESHOLD_HIGH_PHASE;;
end
end
UPPER_THRESHOLD_HIGH_PHASE:
begin
impulse_rejected <= 1;
upper_threshold <= 1;
if(clk_counter == UPPER_THRESHOLD_DURATION + 1)
state <= UPPER_THRESHOLD_LOW_PHASE;
end
UPPER_THRESHOLD_LOW_PHASE:
begin
state <= LOWER_THRESHOLD_LOW_PHASE;
upper_threshold <= 0;
end
LOWER_THRESHOLD_LOW_PHASE:
begin
lower_threshold <= 0;
if(clk_counter >= LOWER_THRESHOLD_DURATION)
begin
if(impulse_rejected == 0)
impulse_counter <= impulse_counter + 1'b1;
total_impulse_counter <= total_impulse_counter + 1'b1;
if(total_impulse_counter < IMPULSES_PER_CHANNEL)
state <= INITIAL_STATE;
else state <= FINAL_STATE;
end
end
FINAL_STATE:
begin
impulse_counter <= 0;
total_impulse_counter <= 0;
period_done <= 1;
first_enable <= 0;
end
default:
begin
end
endcase
end
else state <= INITIAL_STATE;
end
end
always @(posedge channel or negedge areset_n)
begin
if(~areset_n)
enable = 0;
else
begin
if(period_done)
enable = ~enable;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void operator>>(istream& is, vector<T>& v) { for (auto& e : v) { is >> e; } } template <class T> void operator<<(ostream& os, const vector<T>& v) { for (const auto& e : v) { os << e << ; } os << n ; } long long LenToAns(long long len) { return len * (len + 1) / 2; } struct Node { int last; int first; int pref; int suff; int inf; int size; long long ans; }; vector<Node> tree; int n; int n_full; Node MakeNode(int v) { return {v, v, 1, 1, 1, 1, 1}; } Node MakeNeutral() { return {0, 0, 0, 0, 0, 0, 0}; } Node Merge(const Node& l, const Node& r) { Node res; res.first = l.first; res.last = r.last; res.pref = l.pref; res.suff = r.suff; res.inf = max(l.inf, r.inf); res.ans = l.ans + r.ans; if (l.last <= r.first) { res.inf = max(res.inf, l.suff + r.pref); res.ans += LenToAns(l.suff + r.pref); res.ans -= LenToAns(l.suff); res.ans -= LenToAns(r.pref); if (l.pref == l.size) { res.pref = l.size + r.pref; } if (r.pref == r.size) { res.suff = l.suff + r.size; } } res.size = l.size + r.size; return res; } void Init(const vector<int>& a) { n_full = 1; while (n_full < n) { n_full *= 2; } tree.resize(n_full * 2 - 1); for (int i = 0; i < n; i++) { tree[n_full + i - 1] = MakeNode(a[i]); } for (int i = n_full - 2; i >= 0; i--) { tree[i] = Merge(tree[2 * i + 1], tree[2 * i + 2]); } } void Set(int i, int v, int xi, int xl, int xr) { if (xl > i || i >= xr) { return; } if (xr - xl == 1) { tree[xi] = MakeNode(v); return; } int xm = (xl + xr) / 2; Set(i, v, xi * 2 + 1, xl, xm); Set(i, v, xi * 2 + 2, xm, xr); tree[xi] = Merge(tree[xi * 2 + 1], tree[xi * 2 + 2]); } void Set(int i, int v) { Set(i, v, 0, 0, n_full); } Node Sum(int l, int r, int xi, int xl, int xr) { if (xl >= r || l >= xr) { return MakeNeutral(); } if (l <= xl && xr <= r) { return tree[xi]; } int xm = (xl + xr) / 2; return Merge(Sum(l, r, xi * 2 + 1, xl, xm), Sum(l, r, xi * 2 + 2, xm, xr)); } long long Sum(int l, int r) { Node res = Sum(l, r, 0, 0, n_full); return res.ans; } int main() { int k; cin >> n >> k; vector<int> a(n); cin >> a; Init(a); while (k--) { int q; cin >> q; if (q == 1) { int i, v; cin >> i >> v; i--; Set(i, v); } else { int l, r; cin >> l >> r; l--; cout << Sum(l, r) << n ; } } } |
#include <bits/stdc++.h> using namespace std; using LL = long long; using PII = pair<int, int>; int main() { int n; scanf( %d , &n); LL ansx, ansy; ansx = ansy = 0; n *= 2; for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); ansx += x; ansy += y; } n /= 2; printf( %lld %lld n , ansx / n, ansy / n); return 0; } |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_adder.v
// Title : Integer adder / subtractor with comparison flag generation
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_adder (
// ----- Inputs -------
adder_op_x,
adder_op_x_n,
operand_0_x,
operand_1_x,
// ----- Outputs -------
adder_result_x,
adder_carry_n_x,
adder_overflow_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
input adder_op_x_n; // Inverted version of adder_op_x
input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
wire [`LM32_WORD_RNG] adder_result_x;
output adder_carry_n_x; // Inverted carry
wire adder_carry_n_x;
output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
reg adder_overflow_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire a_sign; // Sign (i.e. positive or negative) of operand 0
wire b_sign; // Sign of operand 1
wire result_sign; // Sign of result
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_addsub addsub (
// ----- Inputs -----
.DataA (operand_0_x),
.DataB (operand_1_x),
.Cin (adder_op_x),
.Add_Sub (adder_op_x_n),
// ----- Ouputs -----
.Result (adder_result_x),
.Cout (adder_carry_n_x)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Extract signs of operands and result
assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
// Determine whether an overflow occured when performing a subtraction
always @(*)
begin
// +ve - -ve = -ve -> overflow
// -ve - +ve = +ve -> overflow
if ( (!a_sign & b_sign & result_sign)
|| (a_sign & !b_sign & !result_sign)
)
adder_overflow_x = `TRUE;
else
adder_overflow_x = `FALSE;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_1_V
`define SKY130_FD_SC_HVL__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLXBP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_SCC_N_poe for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_SCC_N_poe
// Module Name: NPCG_Toggle_SCC_N_poe
// File Name: NPCG_Toggle_SCC_N_poe.v
//
// Version: v1.0.0
//
// Description: NFC power on reset
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_SCC_N_poe
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_NumOfData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [15:0] oPM_NumOfData ;
wire wModuleTriggered ;
localparam State_Idle = 3'b000;
localparam State_POECmdIssue = 3'b001;
localparam State_POEWait = 3'b011;
reg [2:0] rCurState ;
reg [2:0] rNextState ;
wire wTimerTrig;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_POECmdIssue:State_Idle;
State_POECmdIssue:
rNextState <= (iPM_Ready)?State_POEWait:State_POECmdIssue;
State_POEWait:
rNextState <= (oLastStep)?State_Idle:State_POEWait;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID[4:0] == 5'b00101 && iOpcode[5:0] == 6'b111110);
assign oCMDReady = (rCurState == State_Idle);
assign wTimerTrig = (rCurState == State_POECmdIssue);
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_POEWait) & iPM_LastStep[0];
assign oPM_PCommand[7:0] = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, wTimerTrig};
assign oPM_PCommandOption[2:0] = 3'b000;
assign oPM_NumOfData[15:0] = 16'd11000;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100000; const int D[4][2] = {{1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; set<pair<int, int> > s; set<pair<pair<int, int>, int> > vis; char dir[10]; int sx, sy, h, w, d, tar; inline void update(int& a, int b) { if (b < a) a = b; } int main() { scanf( %d%d%d%d%s , &h, &w, &sx, &sy, dir); tar = ((h + w) * 2 - 4) >> 1; if (dir[0] == U && dir[1] == L ) d = 3; else if (dir[0] == U && dir[1] == R ) d = 2; else if (dir[0] == D && dir[1] == L ) d = 1; else d = 0; --tar; s.insert(make_pair(sx, sy)); vis.insert(make_pair(make_pair(sx, sy), d)); long long ans = 1; pair<int, int> p1; pair<pair<int, int>, int> p2; while (tar > 0) { if ((D[d][0] == 1 && sx == h) || (D[d][0] == -1 && sx == 1)) d ^= 2; if ((D[d][1] == 1 && sy == w) || (D[d][1] == -1 && sy == 1)) d ^= 1; int g = 0x3f3f3f3f; if (D[d][0] == 1) update(g, h - sx); else update(g, sx - 1); if (D[d][1] == 1) update(g, w - sy); else update(g, sy - 1); ans += g; sx += D[d][0] * g; sy += D[d][1] * g; p1 = make_pair(sx, sy); if (s.find(p1) == s.end()) { --tar; s.insert(p1); } p2 = make_pair(p1, d); if (vis.find(p2) != vis.end()) { printf( -1 n ); return 0; } else vis.insert(p2); } printf( %I64d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_TB_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_TB_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkdlyinv3sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, i, j, k, m; char ss[111], c; bool a[111]; string s[111], t; bool eq(string a, string b) { for (int i = 0; i < a.length(); i++) if (a[i] <= Z ) a[i] = a[i] - A + a ; for (int i = 0; i < b.length(); i++) if (b[i] <= Z ) b[i] = b[i] - A + a ; return a == b; } int main() { scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , ss); s[i] = ss; } scanf( %s , ss); t = ss; m = t.length(); scanf( %s , ss); c = ss[0]; for (i = 0; i < m; i++) for (j = 0; j < n; j++) if (i + s[j].length() <= m && eq(s[j], t.substr(i, s[j].length()))) for (k = 0; k < s[j].length(); k++) a[i + k] = true; for (i = 0; i < m; i++) if (a[i]) { if (c == a ) { if (t[i] == c) t[i] = b ; else if (t[i] == A ) t[i] = B ; else if (t[i] <= Z ) t[i] = A ; else t[i] = a ; } else if (t[i] == c) t[i] = a ; else if (t[i] == c - a + A ) t[i] = A ; else if (t[i] <= Z ) t[i] = c - a + A ; else t[i] = c; } puts(t.c_str()); return 0; } |
// Verify that a zero width signal replication is handled correctly.
module top;
reg pass;
reg [31:0] in_full;
wire [31:0] pa_out_full, ca_out_full;
reg [29:0] in_part;
wire [31:0] pa_out_part, ca_out_part;
initial begin
pass = 1'b1;
in_full = {16{2'b10}};
in_part = {15{2'b01}};
#1;
if (pa_out_full !== 32'b10101010101010101010101010101010) begin
$display("Failed: pa_out_full, got %b", pa_out_full);
pass = 1'b1;
end
if (ca_out_full !== 32'b10101010101010101010101010101010) begin
$display("Failed: ca_out_full, got %b", ca_out_full);
pass = 1'b1;
end
if (pa_out_part !== 32'bxx010101010101010101010101010101) begin
$display("Failed: pa_out_part, got %b", pa_out_part);
pass = 1'b1;
end
if (ca_out_part !== 32'bzz010101010101010101010101010101) begin
$display("Failed: ca_out_part, got %b", ca_out_part);
pass = 1'b1;
end
if (pass) $display("PASSED");
end
param #(32) full(pa_out_full, ca_out_full, in_full);
param #(30) part(pa_out_part, ca_out_part, in_part);
endmodule
module param #(parameter width = 32) (
output reg [31:0] pa_out,
output wire [31:0] ca_out,
input [width-1:0] in);
wire z_pad = 1'bz;
wire x_pad = 1'bx;
assign ca_out = {{32-width{z_pad}}, in};
always @* pa_out = {{32-width{x_pad}}, in};
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Multiplication Module for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 64-bit Booth signed or unsigned multiply and //
// multiply-accumulate supported. It takes about 38 clock //
// cycles to complete an operation. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
// bit 0 go, bit 1 accumulate
// Command:
// 4'b01 : MUL - 32 bit multiplication
// 4'b11 : MLA - 32 bit multiply and accumulate
//
// 34-bit Booth adder
// The adder needs to be 34 bit to deal with signed and unsigned 32-bit
// multiplication inputs. This adds 1 extra bit. Then to deal with the
// case of two max negative numbers another bit is required.
//
module a23_multiply (
input i_clk,
input i_rst,
input [31:0] i_a_in, // Rds
input [31:0] i_b_in, // Rm
input [1:0] i_function,
input i_execute,
output [31:0] o_out,
output [1:0] o_flags, // [1] = N, [0] = Z
output o_done // goes high 2 cycles before completion
);
wire enable;
wire accumulate;
reg [31:0] product;
reg [3:0] count;
assign enable = i_function[0];
assign accumulate = i_function[1];
assign o_out = product;
assign o_flags = {o_out[31], o_out == 32'd0 };
assign o_done = 1'b1;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
product <= 32'b0;
count <= 4'b0;
end else if(enable) begin
count <= count + 1;
if (i_execute && count == 0) begin
product <= i_a_in*i_b_in;
end else if (i_execute && accumulate && count == 3) begin
product <= product + i_a_in;
end
end else begin
product <= 32'b0;
count <= 4'b0;
end
end
// wire [33:0] multiplier;
// wire [33:0] multiplier_bar;
// wire [33:0] sum;
// wire [33:0] sum34_b;
// reg [5:0] count;
// reg [5:0] count_nxt;
// reg [67:0] product;
// reg [67:0] product_nxt;
// reg [1:0] flags_nxt;
// wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition
// assign multiplier = { 2'd0, i_a_in} ;
// assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ;
// assign sum34_b = product[1:0] == 2'b01 ? multiplier :
// product[1:0] == 2'b10 ? multiplier_bar :
// 34'd0 ;
// // -----------------------------------
// // 34-bit adder - booth multiplication
// // -----------------------------------
// assign sum = product[67:34] + sum34_b;
// // ------------------------------------
// // 33-bit adder - accumulate operations
// // ------------------------------------
// assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
// always @*
// begin
// // Defaults
// count_nxt = count;
// product_nxt = product;
// // update Negative and Zero flags
// // Use registered value of product so this adds an extra cycle
// // but this avoids having the 64-bit zero comparator on the
// // main adder path
// flags_nxt = { product[32], product[32:1] == 32'd0 };
// if ( count == 6'd0 )
// product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ;
// else if ( count <= 6'd33 )
// product_nxt = { sum[33], sum, product[33:1]} ;
// else if ( count == 6'd34 && accumulate )
// begin
// // Note that bit 0 is not part of the product. It is used during the booth
// // multiplication algorithm
// product_nxt = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
// end
// // Multiplication state counter
// if (count == 6'd0) // start
// count_nxt = enable ? 6'd1 : 6'd0;
// else if ((count == 6'd34 && !accumulate) || // MUL
// (count == 6'd35 && accumulate) ) // MLA
// count_nxt = 6'd0;
// else
// count_nxt = count + 1'd1;
// end
// always @ ( posedge i_clk or posedge i_rst)
// if (i_rst) begin
// product <= 'd0;
// count <= 'd0;
// o_done <= 'd0;
// end else if (enable)
// begin
// if(i_execute) begin
// product <= product_nxt;
// end
// count <= count_nxt;
// o_done <= count == 6'd31;
// end
// Outputs
// assign o_out = product[32:1];
// assign o_flags = flags_nxt;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a[100005]; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { printf( %I64d , a[i] + a[i + 1]); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFXBP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int N, P[1005], D[1005]; int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { scanf( %d , &P[i]); } D[1] = 1; for (int i = 2; i <= N; i++) { int p = P[i]; D[i] = 1; for (int j = p; j < i; j++) { D[i] += D[j] + 1; D[i] %= 1000000007; } } int res = 0; for (int i = 1; i <= N; i++) { res += D[i] + 1; res %= 1000000007; } printf( %d n , res); return 0; } |
`include "../../../rtl/verilog/gfx/gfx_line.v"
module line_bench();
parameter point_width = 16;
parameter subpixel_width = 16;
reg clk_i;
reg rst_i;
reg signed [point_width-1:-subpixel_width] pixel0_x_i;
reg signed [point_width-1:-subpixel_width] pixel1_x_i;
reg signed [point_width-1:-subpixel_width] pixel0_y_i;
reg signed [point_width-1:-subpixel_width] pixel1_y_i;
reg [point_width-1:0] delta_major_i;
reg [point_width-1:0] delta_minor_i;
reg draw_line_i;
reg read_pixel_i;
reg x_major_i;
reg minor_slope_positive_i;
wire busy_o;
wire signed [point_width-1:0] major_o;
wire signed [point_width-1:0] minor_o;
wire x_major_o;
wire valid_o;
initial begin
$dumpfile("line.vcd");
$dumpvars(0,line_bench);
draw_line_i = 0;
clk_i = 0;
rst_i = 1;
read_pixel_i = 0;
// timing
#2 rst_i = 0;
pixel0_x_i = -(10 << subpixel_width);
pixel0_y_i = (10 << subpixel_width);
pixel1_x_i = (13 << subpixel_width);
pixel1_y_i = (15 << subpixel_width);
#2 draw_line_i = 1;
#2 draw_line_i = 0;
#112 pixel0_x_i = 10 << subpixel_width;
pixel0_y_i = 10 << subpixel_width;
pixel1_x_i = 20 << subpixel_width;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
#100 pixel0_x_i = 10 << subpixel_width;
pixel0_y_i = 10 << subpixel_width;
pixel1_x_i = 20 << subpixel_width;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
#100 pixel0_x_i = 10 << subpixel_width;
pixel0_y_i = 10 << subpixel_width;
pixel1_x_i = 20 << subpixel_width;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
#100 pixel0_x_i = 10 << subpixel_width;
pixel0_y_i = 10 << subpixel_width;
pixel1_x_i = 20 << subpixel_width;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
#100 pixel0_x_i = 10 << subpixel_width;
pixel0_y_i = 10 << subpixel_width;
pixel1_x_i = 20 << subpixel_width;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
#1000 $finish;
end
always begin
#1 clk_i = ~clk_i;
#1 read_pixel_i = valid_o;
end
bresenham_line #(point_width, subpixel_width) bresenham(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.pixel0_x_i ( pixel0_x_i ),
.pixel0_y_i ( pixel0_y_i ),
.pixel1_x_i ( pixel1_x_i ),
.pixel1_y_i ( pixel1_y_i ),
.draw_line_i ( draw_line_i ),
.read_pixel_i ( read_pixel_i ),
.busy_o ( busy_o ),
.x_major_o ( x_major_o ),
.major_o ( major_o ),
.minor_o ( minor_o ),
.valid_o ( valid_o )
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
//
// This implements a 4096:1 mux via two stages of 64:1 muxing.
// change these two parameters to see the speed differences
//`define DATA_WIDTH 12
//`define MUX2_SIZE 32
`define DATA_WIDTH 2
`define MUX2_SIZE 8
// if you change these, then the testbench will break
`define ADDR_WIDTH 12
`define MUX1_SIZE 64
// Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v
// End of automatics
reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
reg [`ADDR_WIDTH-1:0] addr;
// Mux: takes in addr and datai and outputs datao
mux4096 mux4096 (/*AUTOINST*/
// Outputs
.datao (datao[`DATA_WIDTH-1:0]),
// Inputs
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
.addr (addr[`ADDR_WIDTH-1:0]));
// calculate what the answer should be from datai. This is bit
// tricky given the way datai gets sliced. datai is in bit
// planes where all the LSBs are contiguous and then the next bit.
reg [`DATA_WIDTH-1:0] datao_check;
integer j;
always @(datai or addr) begin
for(j=0;j<`DATA_WIDTH;j=j+1) begin
/* verilator lint_off WIDTH */
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr);
/* verilator lint_on WIDTH */
end
end
// Run the test loop. This just increments the address
integer i, result;
always @ (posedge clk) begin
// initial the input data with random values
if (addr == 0) begin
result = 1;
datai = 0;
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin
/* verilator lint_off WIDTH */
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
/* verilator lint_on WIDTH */
end
end
addr <= addr + 1;
if (datao_check != datao) begin
result = 0;
$stop;
end
$write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao);
// only run the first 10 addresses for now
if (addr > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module mux4096
(input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output [`DATA_WIDTH-1:0] datao
);
// DATA_WIDTH instantiations of mux4096_1bit
mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0]
(.addr(addr),
.datai(datai),
.datao(datao)
);
endmodule
module mux4096_1bit
(input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output datao
);
// address decoding
wire [3:0] A = (4'b1) << addr[1:0];
wire [3:0] B = (4'b1) << addr[3:2];
wire [3:0] C = (4'b1) << addr[5:4];
wire [3:0] D = (4'b1) << addr[7:6];
wire [3:0] E = (4'b1) << addr[9:8];
wire [3:0] F = (4'b1) << addr[11:10];
wire [`MUX2_SIZE-1:0] data0;
// DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64
// first stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0]
(.A(A),
.B(B),
.C(C),
.datai(datai),
.datao(data0));
// DATA_WIDTH*MUX2_SIZE instantiations of mux64
// second stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2
(.A(D),
.B(E),
.C(F),
.datai(data0),
.datao(datao));
endmodule
module mux64
#(parameter MUX_SIZE=64)
(input [3:0] A,
input [3:0] B,
input [3:0] C,
input [MUX_SIZE-1:0] datai,
output datao
);
wire [63:0] colSelA = { 16{ A[3:0] }};
wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}};
wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}};
wire [MUX_SIZE-1:0] data_bus;
// Note each of these becomes a separate wire.
//.colSelA(colSelA[MUX_SIZE-1:0]),
//.colSelB(colSelB[MUX_SIZE-1:0]),
//.colSelC(colSelC[MUX_SIZE-1:0]),
drv drv[MUX_SIZE-1:0]
(.colSelA(colSelA[MUX_SIZE-1:0]),
.colSelB(colSelB[MUX_SIZE-1:0]),
.colSelC(colSelC[MUX_SIZE-1:0]),
.datai(datai),
.datao(data_bus)
);
assign datao = |data_bus;
endmodule
module drv
(input colSelA,
input colSelB,
input colSelC,
input datai,
output datao
);
assign datao = colSelC & colSelB & colSelA & datai;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int s; cin >> s; int k, ans = 0; for (k = 1; s > 0 && s >= k; k += 2) s -= k, ++ans; for (k = min(s, k - 1); s > 0 && k >= 1; k--) { ans += s / k; s -= (s / k) * k; } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int sz = (1 << 22); bool ar[sz], us[2][sz]; int n, m, bg; void dfs(int v, int t) { us[t][v] = 1; if (t == 0) { if (us[1][bg ^ v] == 0) dfs(bg ^ v, 1); } else { if (ar[v] and us[0][v] == 0) dfs(v, 0); for (int i = 0; i < n; i++) { if (v & (1 << i)) { int ne = v - (1 << i); if (us[1][ne] == 0) dfs(ne, 1); } } } } int main() { int an = 0; cin >> n >> m; bg = (1 << n) - 1; for (int a = 0; a < m; a++) { int x; scanf( %d , &x); ar[x] = 1; } for (int a = 0; a < (1 << n); a++) { if (ar[a] and us[0][a] == 0) { dfs(a, 0), an++; } } cout << an; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk;
input fastclk;
reg reset_l;
int cyc;
initial reset_l = 0;
always @ (posedge clk) begin
if (cyc==0) reset_l <= 1'b1;
else if (cyc==1) reset_l <= 1'b0;
else if (cyc==10) reset_l <= 1'b1;
end
t_clk t (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk (/*AUTOARG*/
// Inputs
clk, fastclk, reset_l
);
input clk;
input fastclk;
input reset_l;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK1 %x\n", $time, reset_l);
`endif
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
`ifdef TEST_VERBOSE
$write("[%0t] t_clk: Running\n", $time);
`endif
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
`endif
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
`endif
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK4 %x\n", $time, reset_l);
`endif
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk_flop (/*AUTOARG*/
// Outputs
q, q2,
// Inputs
clk, clk2, a
);
parameter WIDTH=8;
input clk;
input clk2;
input [(WIDTH-1):0] a;
output [(WIDTH-1):0] q;
output [(WIDTH-1):0] q2;
reg [(WIDTH-1):0] q;
reg [(WIDTH-1):0] q2;
always @ (posedge clk) q<=a;
always @ (posedge clk2) q2<=a;
endmodule
module t_clk_two (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
// verilator lint_off GENCLK
reg clk2;
// verilator lint_on GENCLK
reg [31:0] count;
t_clk_twob tb (.*);
wire reset_h = ~reset_l;
always @ (posedge fastclk) begin
if (reset_h) clk2 <= 0;
else clk2 <= ~clk2;
end
always @ (posedge clk2) begin
if (reset_h) count <= 0;
else count <= count + 1;
end
endmodule
module t_clk_twob (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
always @ (posedge fastclk) begin
// Extra line coverage point, just to make sure coverage
// hierarchy under inlining lands properly
if (reset_l) ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool done[1010]; int l[1010], r[1010], ans[1010]; int main() { int n, i, j, k; scanf( %d , &n); int rem = n; for (i = 0; i < n; i++) { scanf( %d , &l[i]); done[i] = 0; } for (i = 0; i < n; i++) scanf( %d , &r[i]); int maxx = n; while (1) { set<int> S; bool over = 1; for (i = 0; i < n; i++) { if (done[i] == 0) { over = 0; if (l[i] == 0 and r[i] == 0) { S.insert(i); } } } if (over) break; int sz = S.size(); if (sz == 0) { cout << NO << endl; return 0; } set<int>::iterator it; for (it = S.begin(); it != S.end(); it++) { int idx = *it; ans[idx] = maxx; for (j = idx - 1; j >= 0; j--) { if (done[j] == 0 and S.find(j) == S.end()) { if (r[j] == 0) { cout << NO << endl; return 0; } r[j]--; } } for (j = idx + 1; j < n; j++) { if (done[j] == 0 and S.find(j) == S.end()) { if (l[j] == 0) { cout << NO << endl; return 0; } l[j]--; } } } for (it = S.begin(); it != S.end(); it++) { done[*it] = 1; } maxx--; } cout << YES << endl; for (i = 0; i < n; i++) cout << ans[i] << ; cout << endl; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
(* X_CORE_INFO = "frequency_analyzer_manager,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_frequency_analyzer_manager_0_1,frequency_analyzer_manager,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_frequency_analyzer_manager_0_1,frequency_analyzer_manager,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=frequency_analyzer_manager,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=4}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_0_1 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(4)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> P[2]; int n; int mark[100011]; int cnt[100011]; int cor(int p, int n) { return 2 * n + p; } int main() { int k, x; cin >> n; for (int i = 0; i < 2; i++) { cin >> k; for (int j = 0; j < k; j++) { cin >> x; P[i].push_back(x); } } mark[cor(0, 0)] = mark[cor(1, 0)] = 2; queue<int> Q; Q.push(cor(0, 0)); Q.push(cor(1, 0)); while (Q.size()) { int v = Q.front(); Q.pop(); if (mark[v] == 2) { int p = v % 2; v /= 2; int val; for (auto x : P[1 - p]) { val = (v - x + 2 * n) % n; x = cor(1 - p, val); if (!mark[x]) { mark[x] = 1; Q.push(x); } } continue; } int p = v % 2; v /= 2; int val; for (auto x : P[1 - p]) { val = (v - x + 2 * n) % n; x = cor(1 - p, val); cnt[x]++; if (mark[x] == 0 and cnt[x] == P[x % 2].size()) { Q.push(x); mark[x] = 2; } } } for (int i = 1; i < n; i++) { x = mark[cor(0, i)]; if (x == 1) { cout << Win ; } else if (x == 2) { cout << Lose ; } else { cout << Loop ; } } cout << n ; for (int i = 1; i < n; i++) { x = mark[cor(1, i)]; if (x == 1) { cout << Win ; } else if (x == 2) { cout << Lose ; } else { cout << Loop ; } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__decap (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_FUNCTIONAL_PP_V |
//Device: Virtex-5 LXT
//Design Name: speed_neg_control
//Purpose:
// This module handles the SATA Gen1/Gen2 speed negotiation
/*
Speed negotiation is accomplished by changing the internal shared phase-locked loop (PLL)
divider settings of the GTP transceiver during runtime to eliminate the need for reconfiguration.
The dynamic reconfiguration port (DRP) allows access to the internal attributes of the GTP
transceiver through a simple bus interface.
Below are the DRP and setting for Gen1
Attribute DRP Address Value
PLL_RXDIVSEL_OUT_0[0] 0X46[[2] 1
PLL_RXDIVSEL_OUT_1[0] 0X0A[0] 1
PLL_TXDIVSEL_OUT_0[0] 0X45[15] 1
PLL_TXDIVSEL_OUT_1[0] 0X05[4] 1
Below are the DRP and setting for Gen2
Attribute DRP Address Value
PLL_RXDIVSEL_OUT_0[0] 0X46[[2] 0
PLL_RXDIVSEL_OUT_1[0] 0X0A[0] 0
PLL_TXDIVSEL_OUT_0[0] 0X45[15] 0
PLL_TXDIVSEL_OUT_1[0] 0X05[4] 0
*/
`timescale 1 ns / 1 ps
module speed_neg_control (
input wire clk, //clock
input wire reset, // reset
input wire link_reset,
output reg mgt_reset, //GTP reset request
input wire linkup, // SATA link established
output reg [6:0] daddr, //DRP address
output reg den, //DRP enable
output reg [15:0] di, //DRP data in
input wire [15:0] do, //DRP data out
input wire drdy, //DRP ready
output reg dwe, //DRP write enable
input wire gtp_lock, //GTP locked
output wire [4:0] state_out,
output reg gen_value
);
parameter [4:0] IDLE = 5'h00;
parameter [4:0] READ_GEN2 = 5'h01;
parameter [4:0] WRITE_GEN2 = 5'h02;
parameter [4:0] COMPLETE_GEN2 = 5'h03;
parameter [4:0] PAUSE1_GEN2 = 5'h04;
parameter [4:0] READ1_GEN2 = 5'h05;
parameter [4:0] WRITE1_GEN2 = 5'h06;
parameter [4:0] COMPLETE1_GEN2 = 5'h07;
parameter [4:0] RESET = 5'h08;
parameter [4:0] WAIT_GEN2 = 5'h09;
parameter [4:0] READ_GEN1 = 5'h0A;
parameter [4:0] WRITE_GEN1 = 5'h0B;
parameter [4:0] COMPLETE_GEN1 = 5'h0C;
parameter [4:0] PAUSE_GEN1 = 5'h0D;
parameter [4:0] READ1_GEN1 = 5'h0E;
parameter [4:0] WRITE1_GEN1 = 5'h0F;
parameter [4:0] COMPLETE1_GEN1 = 5'h10;
parameter [4:0] RESET_GEN1 = 5'h11;
parameter [4:0] WAIT_GEN1 = 5'h12;
parameter [4:0] LINKUP = 5'h13;
reg [4:0] state;
reg [31:0] linkup_cnt;
reg [15:0] drp_reg;
reg [15:0] reset_cnt;
reg [3:0] pause_cnt;
assign state_out = state;
always @ (posedge clk or posedge reset)
begin
if(reset)
begin
state <= IDLE;
daddr <= 7'b0;
di <= 8'b0;
den <= 1'b0;
dwe <= 1'b0;
drp_reg <= 16'b0;
linkup_cnt <= 32'h0;
gen_value <= 1'b1;
reset_cnt <= 16'b0000000000000000;
mgt_reset <= 1'b0;
pause_cnt <= 4'b0000;
end
else
begin
case(state)
IDLE: begin
if(gtp_lock)
begin
daddr <= 7'h46;
den <= 1'b1;
gen_value <= 1'b1; //GEN2
state <= READ_GEN2;
end
else
begin
state <= IDLE;
end
end
READ_GEN2: begin
if(drdy)
begin
drp_reg <= do;
den <= 1'b0;
state <= WRITE_GEN2;
end
else
begin
state <= READ_GEN2;
end
end
WRITE_GEN2: begin
di <= drp_reg ; //this actually takes care of all the bits that I should have to change.
di[2] <= 1'b0;
den <= 1'b1;
dwe <= 1'b1;
state <= COMPLETE_GEN2;
end
COMPLETE_GEN2: begin
if(drdy)
begin
dwe <= 1'b0;
den <= 1'b0;
state <= PAUSE1_GEN2;
end
else
begin
state <= COMPLETE_GEN2;
end
end
PAUSE1_GEN2: begin
if(pause_cnt == 4'b1111)
begin
dwe <= 1'b0;
den <= 1'b1;
daddr <= 7'h45;
pause_cnt <= 4'b0000;
state <= READ1_GEN2;
end
else
begin
pause_cnt <= pause_cnt + 1'b1;
state <= PAUSE1_GEN2;
end
end
READ1_GEN2: begin
if(drdy)
begin
drp_reg <= do;
den <= 1'b0;
state <= WRITE1_GEN2;
end
else
begin
state <= READ1_GEN2;
end
end
WRITE1_GEN2: begin
di <= drp_reg;
di[15] <= 1'b0;
den <= 1'b1;
dwe <= 1'b1;
state <= COMPLETE1_GEN2;
end
COMPLETE1_GEN2: begin
if(drdy)
begin
dwe <= 1'b0;
den <= 1'b0;
state <= RESET;
end
else
begin
state <= COMPLETE1_GEN2;
end
end
RESET: begin
if(reset_cnt == 16'b00001111)
begin
reset_cnt <= reset_cnt + 1'b1;
state <= RESET;
mgt_reset <= 1'b1;
end
else if(reset_cnt == 16'b0000000000011111)
begin
reset_cnt <= 16'b00000000;
mgt_reset <= 1'b0;
state <= WAIT_GEN2;
end
else
begin
reset_cnt <= reset_cnt + 1'b1;
state <= RESET;
end
end
WAIT_GEN2: begin //f
if(linkup)
begin
linkup_cnt <= 32'h0;
state <= LINKUP;
end
else
begin
if(gtp_lock)
begin
`ifdef SIM
if(linkup_cnt == 32'h000007FF) //for simulation only
`else
if(linkup_cnt == 32'h00080EB4) // Duration allows four linkup tries
`endif
begin
linkup_cnt <= 32'h0;
daddr <= 7'h46;
den <= 1'b1;
gen_value <= 1'b0; //this is Gen1
state <= READ_GEN1;
//state <= WAIT_GEN2; //MD don't switch back and forth to see if this improves the linkup situation
end
else
begin
linkup_cnt <= linkup_cnt + 1'b1;
state <= WAIT_GEN2;
end
end
else
begin
state <= WAIT_GEN2;
end
end
end
READ_GEN1: begin
if(drdy)
begin
drp_reg <= do;
den <= 1'b0;
state <= WRITE_GEN1;
end
else
begin
state <= READ_GEN1;
end
end
WRITE_GEN1: begin
di <= drp_reg; //this actually takes care of all the bits that I should have to change.//appears the comm doesn't change. changed bit 9 to never switch.
di[2] <= 1'b1;
den <= 1'b1;
dwe <= 1'b1;
state <= COMPLETE_GEN1;
end
COMPLETE_GEN1: begin
if(drdy)
begin
dwe <= 1'b0;
den <= 1'b0;
state <= PAUSE_GEN1;
end
else
begin
state <= COMPLETE_GEN1;
end
end
PAUSE_GEN1: begin
if(pause_cnt == 4'b1111)
begin
dwe <= 1'b0;
den <= 1'b1;
daddr <= 7'h45;
pause_cnt <= 4'b0000;
state <= READ1_GEN1;
end
else
begin
pause_cnt <= pause_cnt + 1'b1;
state <= PAUSE_GEN1;
end
end
READ1_GEN1: begin
if(drdy)
begin
drp_reg <= do;
den <= 1'b0;
state <= WRITE1_GEN1;
end
else
begin
state <= READ1_GEN1;
end
end
WRITE1_GEN1: begin
di <= drp_reg; //
di[15] <= 1'b1;
den <= 1'b1;
dwe <= 1'b1;
state <= COMPLETE1_GEN1;
end
COMPLETE1_GEN1: begin
if(drdy)
begin
dwe <= 1'b0;
den <= 1'b0;
state <= RESET_GEN1;
end
else
begin
state <= COMPLETE1_GEN1;
end
end
RESET_GEN1: begin
if(reset_cnt == 16'b00001111)
begin
reset_cnt <= reset_cnt + 1'b1;
state <= RESET_GEN1;
mgt_reset <= 1'b1;
end
else if(reset_cnt == 16'h001F)
begin
reset_cnt <= 16'b00000000;
mgt_reset <= 1'b0;
state <= WAIT_GEN1;
end
else
begin
reset_cnt <= reset_cnt + 1'b1;
state <= RESET_GEN1;
end
end
WAIT_GEN1: begin
if(linkup)
begin
linkup_cnt <= 32'h0;
state <= LINKUP;
end
else
begin
if(gtp_lock)
begin
`ifdef SIM
if(linkup_cnt == 32'h000007FF) //for simulation only
`else
if(linkup_cnt == 32'h00080EB4) //// Duration allows four linkup tries
`endif
begin
linkup_cnt <= 32'h0;
daddr <= 7'h46;
den <= 1'b1;
state <= READ_GEN2; // after elapsed time the linkup resumes to Gen2
end
else
begin
linkup_cnt <= linkup_cnt + 1'b1;
state <= WAIT_GEN1;
end
end
else
begin
state <= WAIT_GEN1;
end
end
end
LINKUP: begin
if (linkup)
state <= LINKUP;
else
begin
linkup_cnt <= 32'h0;
daddr <= 7'h46;
den <= 1'b1;
state <= READ_GEN2; // after elapsed time the linkup resumes to Gen2
end
end
default: begin
state <= IDLE;
daddr <= 7'b0;
di <= 8'b0;
den <= 1'b0;
dwe <= 1'b0;
drp_reg <= 16'b0;
linkup_cnt <= 32'h0;
gen_value <= 1'b1;
reset_cnt <= 8'b00000000;
mgt_reset <= 1'b0;
pause_cnt <= 4'b0000;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/**********************************************************************
* Felix Winterstein, Imperial College London
*
* File: fifo.v
*
* Revision 1.01
* Additional Comments: distributed under a BSD license, see LICENSE.txt
*
**********************************************************************/
module fifo
#(
parameter DATA_WIDTH = 8,
parameter LOG2_DEPTH = 3
)
(
input clk,
input rst_n,
input [DATA_WIDTH-1:0] din,
input wr_en,
input rd_en,
output reg [DATA_WIDTH-1:0] dout,
output full,
output empty,
output reg valid
);
parameter MAX_COUNT = 2**LOG2_DEPTH;
reg [LOG2_DEPTH-1 : 0] rd_ptr;
reg [LOG2_DEPTH-1 : 0] wr_ptr;
reg [DATA_WIDTH-1 : 0] mem[MAX_COUNT-1 : 0]; //memory size: 2**LOG2_DEPTH
reg [LOG2_DEPTH : 0] depth_cnt;
always @(posedge clk) begin
if(~rst_n) begin
wr_ptr <= 'h0;
rd_ptr <= 'h0;
end // end if
else begin
if(wr_en)
wr_ptr <= wr_ptr+1;
if(rd_en)
rd_ptr <= rd_ptr+1;
end //end else
end//end always
assign empty= (depth_cnt=='h0);
assign full = (depth_cnt==MAX_COUNT);
//comment if you want a registered dout
//assign dout = rd_en ? mem[rd_ptr]:'h0;
always @(posedge clk) begin
if (wr_en)
mem[wr_ptr] <= din;
end //end always
//uncomment if you want a registered dout
always @(posedge clk) begin
if (~rst_n) begin
dout <= 'h0;
valid <= 1'b0;
end else begin
if (rd_en)
valid <= 1'b1;
else
valid <= 1'b0;
dout <= mem[rd_ptr];
end
end
always @(posedge clk) begin
if (~rst_n)
depth_cnt <= 'h0;
else begin
case({rd_en,wr_en})
2'b10 : depth_cnt <= depth_cnt-1;
2'b01 : depth_cnt <= depth_cnt+1;
endcase
end //end else
end //end always
endmodule
|
module VGA_NIOS_CTRL ( // Host Side
iDATA,
oDATA,
iADDR,
iWR,
iRD,
iCS,
iRST_N,
iCLK, // Host Clock
// Export Side
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_SYNC,
VGA_BLANK,
VGA_CLK,
iCLK_25 );
parameter RAM_SIZE = 19'h4B000;
// Host Side
output [15:0] oDATA;
input [15:0] iDATA;
input [18:0] iADDR;
input iWR,iRD,iCS;
input iCLK,iRST_N;
reg [15:0] oDATA;
// Export Side
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output VGA_HS;
output VGA_VS;
output VGA_SYNC;
output VGA_BLANK;
output VGA_CLK;
input iCLK_25;
reg [3:0] mCursor_RGB_N;
reg [9:0] mCursor_X;
reg [9:0] mCursor_Y;
reg [9:0] mCursor_R;
reg [9:0] mCursor_G;
reg [9:0] mCursor_B;
reg [9:0] mON_R;
reg [9:0] mON_G;
reg [9:0] mON_B;
reg [9:0] mOFF_R;
reg [9:0] mOFF_G;
reg [9:0] mOFF_B;
wire [18:0] mVGA_ADDR;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mCursor_RGB_N <= 0;
mCursor_X <= 0;
mCursor_Y <= 0;
mCursor_R <= 0;
mCursor_G <= 0;
mCursor_B <= 0;
mON_R <= 0;
mON_G <= 0;
mON_B <= 0;
mOFF_R <= 0;
mOFF_G <= 0;
mOFF_B <= 0;
oDATA <= 0;
end
else
begin
if(iCS)
begin
if(iWR)
begin
case(iADDR)
RAM_SIZE+0 : mCursor_RGB_N <= iDATA;
RAM_SIZE+1 : mCursor_X <= iDATA;
RAM_SIZE+2 : mCursor_Y <= iDATA;
RAM_SIZE+3 : mCursor_R <= iDATA;
RAM_SIZE+4 : mCursor_G <= iDATA;
RAM_SIZE+5 : mCursor_B <= iDATA;
RAM_SIZE+6 : mON_R <= iDATA;
RAM_SIZE+7 : mON_G <= iDATA;
RAM_SIZE+8 : mON_B <= iDATA;
RAM_SIZE+9 : mOFF_R <= iDATA;
RAM_SIZE+10: mOFF_G <= iDATA;
RAM_SIZE+11: mOFF_B <= iDATA;
endcase
end
else if(iRD)
begin
case(iADDR)
RAM_SIZE+0 : oDATA <= mCursor_RGB_N ;
RAM_SIZE+1 : oDATA <= mCursor_X ;
RAM_SIZE+2 : oDATA <= mCursor_Y ;
RAM_SIZE+3 : oDATA <= mCursor_R ;
RAM_SIZE+4 : oDATA <= mCursor_G ;
RAM_SIZE+5 : oDATA <= mCursor_B ;
RAM_SIZE+6 : oDATA <= mON_R ;
RAM_SIZE+7 : oDATA <= mON_G ;
RAM_SIZE+8 : oDATA <= mON_B ;
RAM_SIZE+9 : oDATA <= mOFF_R ;
RAM_SIZE+10: oDATA <= mOFF_G ;
RAM_SIZE+11: oDATA <= mOFF_B ;
endcase
end
end
end
end
VGA_Controller u0 ( // Host Side
.iCursor_RGB_EN(mCursor_RGB_N),
.iCursor_X(mCursor_X),
.iCursor_Y(mCursor_Y),
.iCursor_R(mCursor_R),
.iCursor_G(mCursor_G),
.iCursor_B(mCursor_B),
.oAddress(mVGA_ADDR),
.iRed (mVGA_R),
.iGreen (mVGA_G),
.iBlue (mVGA_B),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
.oVGA_CLOCK(VGA_CLK),
// Control Signal
.iCLK_25(iCLK_25),
.iRST_N(iRST_N) );
VGA_OSD_RAM u1 ( // Read Out Side
.oRed(mVGA_R),
.oGreen(mVGA_G),
.oBlue(mVGA_B),
.iVGA_ADDR(mVGA_ADDR),
.iVGA_CLK(VGA_CLK),
// Write In Side
.iWR_DATA(iDATA),
.iWR_ADDR(iADDR),
.iWR_EN(iWR && (iADDR < RAM_SIZE) && iCS),
.iWR_CLK(iCLK),
// CLUT
.iON_R(mON_R),
.iON_G(mON_G),
.iON_B(mON_B),
.iOFF_R(mOFF_R),
.iOFF_G(mOFF_G),
.iOFF_B(mOFF_B),
// Control Signals
.iRST_N(iRST_N) );
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const long long inf = 1e18 + 10; long long dis[N], sid[N], mark[N], h[N], dp[N], c[N]; pair<pair<long long, long long>, long long> E[N]; vector<pair<long long, long long> > adj[N], jda[N], g[N]; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > pq; void dfs(long long v, long long id) { mark[v] = 1; dp[v] = inf; for (pair<long long, long long> e : g[v]) { long long u = e.first, ind = e.second; if (ind == id) continue; if (mark[u]) { dp[v] = min(dp[v], h[u]); } else { h[u] = h[v] + 1; dfs(u, ind); dp[v] = min(dp[v], dp[u]); if (h[v] < dp[u]) c[ind] = 1; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, s, t; cin >> n >> m >> s >> t; for (int i = 0; i < m; i++) { long long u, v, w; cin >> u >> v >> w; adj[u].push_back({v, w}); jda[v].push_back({u, w}); E[i] = {{u, v}, w}; } fill(dis, dis + N, inf); dis[s] = 0; pq.push({0, s}); while (!pq.empty()) { long long d = pq.top().first, v = pq.top().second; pq.pop(); if (d != dis[v]) continue; for (pair<long long, long long> e : adj[v]) { long long u = e.first, w = e.second; if (d + w < dis[u]) { dis[u] = d + w; pq.push({d + w, u}); } } } fill(sid, sid + N, inf); sid[t] = 0; pq.push({0, t}); while (!pq.empty()) { long long d = pq.top().first, v = pq.top().second; pq.pop(); if (d != sid[v]) continue; for (pair<long long, long long> e : jda[v]) { long long u = e.first, w = e.second; if (d + w < sid[u]) { sid[u] = d + w; pq.push({d + w, u}); } } } for (int i = 0; i < m; i++) { long long u = E[i].first.first, v = E[i].first.second, w = E[i].second; if (dis[u] + w + sid[v] == dis[t]) { g[u].push_back({v, i}); g[v].push_back({u, i}); } } dfs(s, -1); for (int i = 0; i < m; i++) { long long u = E[i].first.first, v = E[i].first.second, w = E[i].second; if (dis[u] + w + sid[v] == dis[t]) { if (c[i]) cout << YES n ; else if (1 < w) cout << CAN << << 1 << n ; else cout << NO n ; } else { long long cst = dis[u] + w + sid[v]; long long dif = cst - dis[t] + 1; if (dif < w) cout << CAN << << dif << n ; else cout << NO n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; void DBG() { cerr << ] << endl; } template <class H, class... T> void DBG(H h, T... t) { cerr << to_string(h); if (sizeof...(t)) cerr << , ; DBG(t...); } int main(void) { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); int n; cin >> n; vector<vector<long long>> a(n, vector<long long>(3)); for (int i = 0; i < n; ++i) { cin >> a[i][0] >> a[i][1] >> a[i][2]; } vector<bool> vis(n); for (int i = 0; i < n; ++i) { long long bonus = 0, cnt = 0; if (vis[i]) continue; for (int j = i + 1; j < n; ++j) { if (vis[j]) continue; a[j][2] -= max(0LL, (a[i][0] - cnt)); ++cnt; a[j][2] -= bonus; if (a[j][2] < 0) { vis[j] = true; bonus += a[j][1]; } } } vector<int> ans; for (int i = 0; i < n; ++i) { if (!vis[i]) { ans.push_back(i + 1); } } cout << ((int)(ans).size()) << n ; for (auto &A : ans) cout << A << ; } |
#include list #include <iostream> #include <utility> #include <vector> #include fstream #include <fstream> #include <map> #include algorithm #include <iomanip> #include cmath #include set #include <climits> #include queue #include complex #define all(x) (x).begin(), (x).end() #define ll long long using namespace std; long long mod = 1e9 + 7; void solve() { int n, k; cin >> n >> k; long long res = 1; for (int i = 0; i < k; ++i) { res *= n; res %= mod; } cout << res << endl; } signed main() { int n; cin >> n; while (n--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; int n; string rakh1, rakh2, rakh, ch, ch_min; while (test--) { cin >> n; cin >> ch; ch_min = ch; int pos = 1; for (int i = 1; i < (n - 1); i++) { rakh1 = ch.substr(0, i); rakh2 = ch.substr(i, n - 1); if ((n % 2 != 0 && i % 2 == 0) || (n % 2 == 0 && i % 2 != 0)) reverse(rakh1.begin(), rakh1.end()); rakh = rakh2 + rakh1; if (ch_min > rakh) { pos = i + 1; ch_min = rakh; } } reverse(ch.begin(), ch.end()); if (ch_min > ch) { pos = n; ch_min = ch; } cout << ch_min << endl; cout << pos << endl; } return 0; } |
#include <bits/stdc++.h> const int INF_INT = 0x3f3f3f3f; const long long INF_LL = 0x7f7f7f7f; const int MOD = 1e9 + 7; const double eps = 1e-10; const double pi = acos(-1); using namespace std; vector<int> g[100010]; int n; double ans; void dfs(int fa, int u, int cnt) { ans += 1.0 / cnt; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == fa) continue; dfs(u, v, cnt + 1); } } int main(int argc, char const *argv[]) { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } ans = 0.0; dfs(0, 1, 1); printf( %.12f n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD1_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD1_BLACKBOX_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD1_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; set<string> setao; string s; const int N = 10010; int pd[N][4], n; char solve(int k, int last) { if (k == n) return 1; if (n - k == 1 or k > n) return 0; if (pd[k][last] != -1) return pd[k][last]; string ant; for (int i = last; i >= 1; i--) { ant.push_back(s[k - i]); } string x; for (int i = 0; i < 2; i++) x.push_back(s[k + i]); char flag = 0; if (x != ant) { if (solve(k + 2, 2)) { setao.insert(x); flag = 1; } } if (n - k > 2) { x.push_back(s[k + 2]); if (x != ant) { if (solve(k + 3, 3)) { setao.insert(x); flag = 1; } } } return pd[k][last] = flag; } int main(void) { memset(pd, -1, sizeof pd); cin >> s; n = s.size(); for (int i = 5; i < n; i++) { solve(i, 0); } printf( %d n , (int)setao.size()); for (set<string>::iterator it = setao.begin(); it != setao.end(); it++) { cout << *it << endl; } return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
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//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
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