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// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
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// -- possibility of the same.
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// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_9_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_7_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T abs(T a) { return a > 0 ? a : -a; } int n; int m; int main() { int last; cin >> n >> last; if (n == 1) { if (last == 1) { cout << 0 << endl << T << endl; } else { cout << IMPOSSIBLE << endl; } return 0; } int ans = -1; int errans = 1e9; for (int i = 1; i <= last; i++) { int a = last, b = i; int err = 0, len = 0; while (b) { err += (a / b) - 1; len += a / b; a %= b; swap(b, a); } if (a != 1) continue; err--; if (len == n) { if (errans > err) { errans = err; ans = i; } } } if (ans < 0) { cout << IMPOSSIBLE << endl; return 0; } vector<int> res; int a = last, b = ans; while (b) { res.push_back(a / b); a %= b; swap(b, a); } reverse((res).begin(), (res).end()); res[0]--; cout << errans << endl; cout << T ; for (int i = 0; i < (((int)(res).size())); i++) for (int j = 0; j < (res[i]); j++) printf( %c , ((i + 1) % 2 ? B : T )); printf( n ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int a[100004]; int main() { int n, no; cin >> n >> a[0]; a[0] = (a[0] - 1) % 2; for (int i = 1; i < n; i++) { cin >> no; a[i] = (a[i - 1] + (no - 1)) % 2; } for (int i = 0; i < n; i++) { if (a[i] == 1) { cout << 1 n ; } else cout << 2 n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, c, d, e; int main() { cin >> a >> b >> c >> d >> e; int t = min(a, min(b, min(c / 2, min(d / 7, e / 4)))); cout << t << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using i64 = long long; struct SplayNode { using pSplayNode = SplayNode *; static pSplayNode root; int sz; pSplayNode fa, son[2]; int val, type, type1num; i64 sum; SplayNode(int _type, int _val) { sz = 1; fa = son[0] = son[1] = nullptr; type = _type; type1num = type; sum = val = _val; } void Pushup() { sz = (son[0] != nullptr ? son[0]->sz : 0) + (son[1] != nullptr ? son[1]->sz : 0) + 1; sum = (son[0] != nullptr ? son[0]->sum : 0) + (son[1] != nullptr ? son[1]->sum : 0) + val; type1num = (son[0] != nullptr ? son[0]->type1num : 0) + (son[1] != nullptr ? son[1]->type1num : 0) + type; } void Rotate() { if (fa == nullptr) return; pSplayNode x = this, y = fa, z = y->fa; int p = y->son[1] == x ? 1 : 0; y->son[p] = x->son[p ^ 1]; if (x->son[p ^ 1] != nullptr) x->son[p ^ 1]->fa = y; x->son[p ^ 1] = y; y->fa = x; x->fa = z; if (z != nullptr) z->son[y == z->son[1] ? 1 : 0] = x; y->Pushup(); x->Pushup(); } void Splay(pSplayNode goal = root) { if (this == goal) return; pSplayNode x = this, y, z; while ((y = x->fa) != goal) { z = y->fa; if (z != goal) ((z->son[0] == y) ^ (y->son[0] == x)) ? x->Rotate() : y->Rotate(); x->Rotate(); } x->Rotate(); if (goal == root) root = x; } pSplayNode GetKth(int k) { int _k = son[0] == nullptr ? 1 : son[0]->sz + 1; if (k == _k) return this; if (k < _k) return son[0]->GetKth(k); return son[1]->GetKth(k - _k); } pSplayNode Split(int l, int r) { root->GetKth(l)->Splay(); root->GetKth(r + 2)->Splay(root->son[1]); return root->son[1]->son[0]; } void Insert(pSplayNode x) { if (x->val > val || x->val == val && x->type < type) { if (son[0] == nullptr) { son[0] = x; x->fa = this; x->Splay(); } else son[0]->Insert(x); } else { if (son[1] == nullptr) { son[1] = x; x->fa = this; x->Splay(); } else son[1]->Insert(x); } } pSplayNode GetVal(int _t, int _v) { if (_v == val && _t == type) return this; if (_v > val || _v == val && _t < type) return son[0]->GetVal(_t, _v); return son[1]->GetVal(_t, _v); } void Delete() { Splay(); if (root->son[0] != nullptr) root->son[0]->fa = nullptr; if (root->son[1] != nullptr) root->son[1]->fa = nullptr; root = Union(root->son[0], root->son[1]); delete this; } pSplayNode Union(pSplayNode a, pSplayNode b) { if (a == nullptr) return b; auto c = Union(a->son[1], b); a->son[1] = c; if (c != nullptr) c->fa = a; a->Pushup(); return a; } } *SplayNode::root = nullptr, *&Root = SplayNode::root; int q, i, o, x, num1; i64 sumall; i64 Query() { if (num1 == 0) return sumall; auto rg = Root->Split(1, num1); if (rg->type1num < num1) return sumall + rg->sum; if (Root->sz - 2 == num1) return sumall + rg->sum - (Root->GetKth(num1 + 1)->val); return sumall + rg->sum - (Root->GetKth(num1 + 1)->val) + (Root->GetKth(num1 + 2)->val); } int main() { default_random_engine gen; Root = new SplayNode(0, numeric_limits<int>::max()); auto tmp = new SplayNode(0, numeric_limits<int>::min()); tmp->fa = Root; Root->son[1] = tmp; Root->Pushup(); scanf( %d , &q); for (i = 1; i <= q; ++i) { scanf( %d%d , &o, &x); sumall += x; if (x > 0) { num1 += o; Root->Insert(new SplayNode(o, x)); } else { num1 -= o; Root->GetVal(o, -x)->Delete(); } printf( %lld n , Query()); Root->GetKth(gen() % (Root->sz) + 1)->Splay(); } } |
#include <bits/stdc++.h> using namespace std; template <typename T> void chkmax(T &x, T y) { x = x > y ? x : y; } template <typename T> void chkmin(T &x, T y) { x = x > y ? y : x; } const int INF = 2139062143; template <typename T> void read(T &x) { x = 0; bool f = 1; char ch; do { ch = getchar(); if (ch == - ) f = 0; } while (ch > 9 || ch < 0 ); do { x = x * 10 + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); x = f ? x : -x; } template <typename T> void write(T x) { if (x < 0) x = ~x + 1, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } const int N = 1000 + 5; const int mod = 998244353; int n, k, ans, a[N], f[N][N], s[N][N]; int main() { read(n); read(k); for (int i = 1; i <= n; i++) read(a[i]); sort(a + 1, a + n + 1); a[0] = -INF; for (int v = 1; v * (k - 1) <= a[n]; v++) { f[0][0] = s[0][0] = 1; int now = 0; for (int i = 1; i <= n; i++) { while (a[i] - a[now] >= v) now++; f[i][0] = 0; s[i][0] = (s[i - 1][0] + f[i][0]) % mod; for (int j = 1; j <= k; j++) { f[i][j] = s[now - 1][j - 1]; s[i][j] = (s[i - 1][j] + f[i][j]) % mod; } } ans = (ans + 1ll * s[n][k]) % mod; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i, x = 0; cin >> n >> k; char a; for (i = 0; i < n; i++) { cin >> a; if (a == # ) { x++; if (x == k) break; } else x = 0; } cout << (x == k ? NO : YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> ans; struct item { int key, prior; item *left, *right; item() {} item(int key, int prior) : key(key), prior(prior), left(NULL), right(NULL) {} }; typedef item* pitem; void split(pitem temp, int key, pitem& left, pitem& right) { if (!temp) left = right = NULL; else if (key < temp->key) split(temp->left, key, left, temp->left), right = temp; else split(temp->right, key, temp->right, right), left = temp; } void insert(pitem& temp, pitem it) { if (!temp) temp = it; else if (it->prior > temp->prior) split(temp, it->key, it->left, it->right), temp = it; else insert(it->key < temp->key ? temp->left : temp->right, it); } void merge(pitem& temp, pitem left, pitem right) { if (!left || !right) temp = left ? left : right; else if (left->prior > right->prior) merge(left->right, left->right, right), temp = left; else merge(right->left, left, right->left), temp = right; } void erase(pitem& temp, int key) { if (temp->key == key) merge(temp, temp->left, temp->right); else erase(key < temp->key ? temp->left : temp->right, key); } pitem unite(pitem left, pitem right) { if (!left || !right) return left ? left : right; if (left->prior < right->prior) swap(left, right); pitem lt, rt; split(right, left->key, lt, rt); left->left = unite(left->left, lt); left->right = unite(left->right, rt); return left; } int getMin(pitem temp) { while (temp->left) temp = temp->left; return temp->key; } pitem eraseMin(pitem temp) { int minn = getMin(temp); erase(temp, minn); return temp; } void dfs(pitem temp) { ans.push_back(temp->key); if (temp->left) dfs(temp->left); if (temp->right) dfs(temp->right); } long long mass[200000]; vector<int> mass1[200000]; unordered_map<int, bool> prefs; int n; bool f(long long m, bool fin) { if (fin) { for (int i = 0; i < n; i++) { int now = 0; int last = -1; for (int u = mass1[i].size() - 1; u > -1; u--) { now *= 2; now += mass1[i][u]; if (prefs[now] == 0 && now <= m) last = now; } cout << last << ; prefs[last] = 1; } return 0; } else for (int i = 0; i < n; i++) { int now = 0; int last = -1; for (int u = mass1[i].size() - 1; u > -1; u--) { now *= 2; now += mass1[i][u]; if (now > m) break; if (prefs[now] == 0) last = now; } if (last == -1) return 0; else prefs[last] = 1; } return 1; } int main() { ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> mass[i]; sort(mass, mass + n); reverse(mass, mass + n); for (int i = 0; i < n; i++) { long long a = mass[i]; while (a) { mass1[i].push_back(a % 2); a /= 2; } } long long l = 1, r = 1e9; for (int b = 0; b < 30; b++) { prefs.clear(); long long mid = (l + r) / 2; if (f(mid, 0)) r = mid; else l = mid; } prefs.clear(); f(r, 1); return 0; } |
#include<bits/stdc++.h> #define ll long long using namespace std; ll T,n,k; void work(){ scanf( %lld%lld ,&n,&k); if(n<=k){printf( %lld n ,(long long)ceil((double)k*1.0/(double)n));return;} else{ if(n%k==0){ printf( %lld n ,1LL); return; } else printf( %lld n ,2LL); } return; } int main(){ scanf( %d ,&T); while(T--)work(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long fpow(long long a, int b, int mod) { long long res = 1; for (; b > 0; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res % mod; } const int mod = 1e9 + 7; const int N = 2e5 + 100; inline int read() { static char buf[1000000], *p1 = buf, *p2 = buf; register int x = false; register char ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; register bool sgn = false; while (ch != - && (ch < 0 || ch > 9 )) ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; if (ch == - ) sgn = true, ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; return sgn ? -x : x; } int mon[N]; int d[N]; int main() { int t; cin >> t; while (t--) { int n, m; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &mon[i]); scanf( %d , &m); for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); d[b] = max(a, d[b]); } for (int i = n; i >= 0; i--) d[i] = max(d[i + 1], d[i]); int ans = 0; for (int i = 1; i <= n;) { if (mon[i] > d[1]) { cout << -1 << endl; goto brk; } int j = 0; int MX = 0; for (; j <= n; j++) { MX = max(MX, mon[i + j]); if (d[j + 1] < MX) break; } ans++; i += j; } cout << ans << endl; brk:; for (int i = 0; i <= n; i++) d[i] = 0; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__FAHCIN_BEHAVIORAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( tune=native ) #pragma GCC optimize( unroll-loops ) using namespace std; using ll = long long; const int N = 120005; struct node_t { int tag, time, value, number; ll answer; } tree[N << 2]; int n, m, top_max, top_min, a[N], stack_max[N], stack_min[N]; vector<pair<int, int>> queries[N]; ll answer[N]; static void add_value(int x, int value) { tree[x].value += value; tree[x].tag += value; } static void add_time(int x, int value) { tree[x].time += value; tree[x].answer += (ll)value * tree[x].number; } static void push_up(int x) { tree[x].value = min(tree[x << 1].value, tree[x << 1 | 1].value); tree[x].answer = tree[x << 1].answer + tree[x << 1 | 1].answer; tree[x].number = 0; if (tree[x].value == tree[x << 1].value) { tree[x].number += tree[x << 1].number; } if (tree[x].value == tree[x << 1 | 1].value) { tree[x].number += tree[x << 1 | 1].number; } } static void push_down(int x) { if (tree[x].tag) { add_value(x << 1, tree[x].tag); add_value(x << 1 | 1, tree[x].tag); tree[x].tag = 0; } if (tree[x].time) { if (tree[x].value == tree[x << 1].value) { add_time(x << 1, tree[x].time); } if (tree[x].value == tree[x << 1 | 1].value) { add_time(x << 1 | 1, tree[x].time); } tree[x].time = 0; } } static void build(int x, int l, int r) { tree[x].value = l; tree[x].number = 1; if (l == r) { return; } int mid = (l + r) / 2; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); } static void modify(int x, int l, int r, int ql, int qr, int value) { if (l == ql && r == qr) { add_value(x, value); return; } int mid = (l + r) / 2; push_down(x); if (qr <= mid) { modify(x << 1, l, mid, ql, qr, value); } else if (ql > mid) { modify(x << 1 | 1, mid + 1, r, ql, qr, value); } else { modify(x << 1, l, mid, ql, mid, value); modify(x << 1 | 1, mid + 1, r, mid + 1, qr, value); } push_up(x); } static ll query(int x, int l, int r, int ql, int qr) { if (l == ql && r == qr) { return tree[x].answer; } int mid = (l + r) / 2; push_down(x); if (qr <= mid) { return query(x << 1, l, mid, ql, qr); } else if (ql > mid) { return query(x << 1 | 1, mid + 1, r, ql, qr); } else { return query(x << 1, l, mid, ql, mid) + query(x << 1 | 1, mid + 1, r, mid + 1, qr); } } void solve() { ios::sync_with_stdio(0); cin.tie(nullptr); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } cin >> m; for (int i = 1; i <= m; ++i) { int l, r; cin >> l >> r; queries[r].push_back(make_pair(l, i)); } build(1, 1, n); for (int i = 1; i <= n; ++i) { add_value(1, -1); while (top_max && a[stack_max[top_max]] < a[i]) { modify(1, 1, n, stack_max[top_max - 1] + 1, stack_max[top_max], a[i] - a[stack_max[top_max]]); --top_max; } stack_max[++top_max] = i; while (top_min && a[stack_min[top_min]] > a[i]) { modify(1, 1, n, stack_min[top_min - 1] + 1, stack_min[top_min], a[stack_min[top_min]] - a[i]); --top_min; } stack_min[++top_min] = i; add_time(1, 1); for (auto q : queries[i]) { answer[q.second] = query(1, 1, n, q.first, i); } } for (int i = 1; i <= m; ++i) { cout << answer[i] << n ; } } int main() { solve(); return 0; } |
`include "setseed.vh"
module top(input clk, din, stb, output dout);
reg [41:0] din_bits;
wire [78:0] dout_bits;
reg [41:0] din_shr;
reg [78:0] dout_shr;
always @(posedge clk) begin
if (stb) begin
din_bits <= din_shr;
dout_shr <= dout_bits;
end else begin
din_shr <= {din_shr, din};
dout_shr <= {dout_shr, din_shr[41]};
end
end
assign dout = dout_shr[78];
stuff stuff (
.clk(clk),
.din_bits(din_bits),
.dout_bits(dout_bits)
);
endmodule
module stuff(input clk, input [41:0] din_bits, output [78:0] dout_bits);
picorv32 picorv32 (
.clk(clk),
.resetn(din_bits[0]),
.mem_valid(dout_bits[0]),
.mem_instr(dout_bits[1]),
.mem_ready(din_bits[1]),
.mem_addr(dout_bits[33:2]),
.mem_wdata(dout_bits[66:34]),
.mem_wstrb(dout_bits[70:67]),
.mem_rdata(din_bits[33:2])
);
randluts randluts (
.din(din_bits[41:34]),
.dout(dout_bits[78:71])
);
endmodule
module randluts(input [7:0] din, output [7:0] dout);
localparam integer N = 250;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information of Xilinx, Inc.
// and is protected under U.S. and international copyright and other
// intellectual property laws.
//
// DISCLAIMER
//
// This disclaimer is not a license and does not grant any rights to the
// materials distributed herewith. Except as otherwise provided in a valid
// license issued to you by Xilinx, and to the maximum extent permitted by
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
// and (2) Xilinx shall not be liable (whether in contract or tort, including
// negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these
// materials, including for any direct, or any indirect, special, incidental,
// or consequential loss or damage (including loss of data, profits, goodwill,
// or any type of loss or damage suffered as a result of any action brought by
// a third party) even if such damage or loss was reasonably foreseeable or
// Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
//
// Xilinx products are not designed or intended to be fail-safe, or for use in
// any application requiring fail-safe performance, such as life-support or
// safety devices or systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any other
// applications that could lead to death, personal injury, or severe property
// or environmental damage (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and liability of any use of
// Xilinx products in Critical Applications, subject only to applicable laws
// and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
// AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : pcie_brams_s6.v
// Description: BlockRAM module for Spartan-6 PCIe Block
//
// Arranges and connects brams
// Implements address decoding, datapath muxing and
// pipeline stages
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_brams_s6 #(
// the number of BRAMs to use
// supported values are:
// 1,2,4,9
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
) (
input user_clk_i,
input reset_i,
input wen,
input [11:0] waddr,
input [35:0] wdata,
input ren,
input rce,
input [11:0] raddr,
output [35:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 36 :
(NUM_BRAMS == 2) ? 18 :
(NUM_BRAMS == 4) ? 9 :
4
);
localparam TCQ = 1;
//synthesis translate_off
initial begin
case (NUM_BRAMS)
1,2,4,9:;
default: begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default: begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default: begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default: begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
wire wen_int;
wire [11:0] waddr_int;
wire [35:0] wdata_int;
generate
if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_dly;
reg [11:0] waddr_dly;
reg [35:0] wdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
wen_dly <= #TCQ 1'b0;
waddr_dly <= #TCQ 12'b0;
wdata_dly <= #TCQ 36'b0;
end else begin
wen_dly <= #TCQ wen;
waddr_dly <= #TCQ waddr;
wdata_dly <= #TCQ wdata;
end
end
assign wen_int = wen_dly;
assign waddr_int = waddr_dly;
assign wdata_int = wdata_dly;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
wire ren_int;
wire [11:0] raddr_int;
wire [35:0] rdata_int;
generate
if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_dly;
reg [11:0] raddr_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
ren_dly <= #TCQ 1'b0;
raddr_dly <= #TCQ 12'b0;
end else begin
ren_dly <= #TCQ ren;
raddr_dly <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_dly;
assign raddr_int = raddr_dly;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate
if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [35:0] rdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
rdata_dly <= #TCQ 36'b0;
end else begin
rdata_dly <= #TCQ rdata_int;
end // else: !if(reset_i)
end
assign rdata = rdata_dly;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar i;
for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
pcie_bram_s6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
.wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
.ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
end
endgenerate
endmodule // pcie_brams_s6
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 200010, MaxB = 500, MaxA = 1000010, mod = 1000000007; struct Query { int l, r, id; bool operator<(const Query &a) const { return r < a.r; } } q[MaxN]; int n, m, a[MaxN]; vector<pair<int, int> > f[MaxN]; int last[MaxA]; int prime[MaxA], ptot, minp[MaxA]; int inv[MaxA]; bool notp[MaxA]; void init(int n) { for (int i = 2; i <= n; ++i) { if (!notp[i]) { prime[++ptot] = i; minp[i] = i; } for (int j = 1; j <= ptot && prime[j] * i <= n; ++j) { notp[prime[j] * i] = 1; minp[prime[j] * i] = prime[j]; if (i % prime[j] == 0) break; } } inv[1] = 1; for (int i = 2; i <= n; ++i) inv[i] = mod - 1ll * (mod / i) * inv[mod % i] % mod; } int ans[MaxN]; int c[MaxN]; void modify(int x, int v) { for (; x <= n; x += (x & -x)) c[x] = 1ll * c[x] * v % mod; } int query(int x) { int ret = 1; for (; x; x -= (x & -x)) ret = 1ll * ret * c[x] % mod; return ret; } int main() { scanf( %d , &n); int mx = 0; for (int i = 1; i <= n; ++i) { scanf( %d , a + i); mx = max(mx, a[i]); } init(mx); for (int i = 1; i <= n; ++i) { int x = a[i]; while (x != 1) { int prod = 1, t = minp[x]; while (x % t == 0) { x /= t; prod *= t; } f[i].push_back(make_pair(t, prod)); } } scanf( %d , &m); for (int i = 1; i <= m; ++i) { scanf( %d%d , &q[i].l, &q[i].r); q[i].id = i; } sort(q + 1, q + m + 1); for (int i = 0; i <= n; ++i) c[i] = 1; int node = 0; for (int i = 1; i <= n; ++i) { for (auto t : f[i]) { modify(1, t.second); modify(last[t.first] + 1, 1ll * (t.first - 1) * inv[t.first] % mod); modify(i + 1, inv[t.second / t.first * (t.first - 1)]); last[t.first] = i; } while (node < m && q[node + 1].r == i) { ++node; ans[q[node].id] = query(q[node].l); } } for (int i = 1; i <= m; ++i) printf( %d n , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDLXTP_PP_BLACKBOX_V
/**
* sdlxtp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_PP_BLACKBOX_V
|
// soc_design_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100000; int N, M, S; vector<pair<int, int> > b; vector<pair<pair<int, int>, int> > s; vector<pair<int, int> > b2; vector<pair<pair<int, int>, int> > s2; int ans[MAX_N + 1]; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > pq; bool chk(int x) { long long cost = 0; while (!b.empty()) b.pop_back(); while (!s.empty()) s.pop_back(); for (int i = 0; i < b2.size(); i++) { b.push_back(b2[i]); } for (int i = 0; i < s2.size(); i++) { s.push_back(s2[i]); } while (!pq.empty()) pq.pop(); while (!b.empty()) { while (!s.empty() && s.back().first.first >= b.back().first) { pq.push({s.back().first.second, s.back().second}); s.pop_back(); } if (pq.empty()) { return false; } pair<int, int> now = pq.top(); pq.pop(); cost += (long long)now.first; for (int i = 0; i < x; i++) { if (b.empty()) break; pair<int, int> p = b.back(); b.pop_back(); ans[p.second] = now.second; } } return cost <= (long long)S; } int main() { scanf( %d%d%d , &N, &M, &S); for (int i = 0; i < M; i++) { int x; scanf( %d , &x); b2.push_back({x, i}); } for (int i = 0; i < N; i++) { int x; scanf( %d , &x); s2.push_back({{x, 0}, i}); } for (int i = 0; i < N; i++) { int x; scanf( %d , &x); s2[i].first.second = x; } sort(b2.begin(), b2.end()); sort(s2.begin(), s2.end()); int st = 0, ed = 100000, m; while (st < ed) { m = (st + ed) / 2; if (chk(m)) ed = m; else st = m + 1; } if (chk(st)) { printf( YES n ); for (int i = 0; i < M; i++) { printf( %d , ans[i] + 1); } } else { printf( NO ); } return 0; } |
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
reg clk;
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
`ifdef SINGLE
parameter SW = 24;
`endif
`ifdef DOUBLE
parameter SW = 54;// */
`endif
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
wire [2*SW-1:0] FKOARES;
reg clk;
reg rst;
reg load_b_i;
`ifdef SINGLE
Simple_KOA_SW24
`endif
`ifdef DOUBLE
Simple_KOA_SW54
`endif
inst_Sgf_Multiplication (.clk(clk),.rst(rst),.load_b_i(load_b_i),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(FKOARES));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b, FKOARES, a*b);
end
initial begin
b = 1;
rst = 1;
a = 1;
load_b_i = 0;
#30;
rst = 0;
#15;
load_b_i = 1;
#100;
b = 2;
#5;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
// $Id: c_and_nto1.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// n-input bitwise AND
module c_and_nto1
(data_in, data_out);
// number of inputs
parameter num_ports = 2;
// width of each input
parameter width = 1;
// vector of inputs
input [0:width*num_ports-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:bit_positions
wire [0:num_ports-1] data;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:input_ports
assign data[j] = data_in[j*width+i];
end
assign data_out[i] = &data;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int _inf = 0xc0c0c0c0; const long long INF = 0x3f3f3f3f3f3f3f3f; const long long _INF = 0xc0c0c0c0c0c0c0c0; const long long mod = (int)1e9 + 7; const int N = 3e5 + 100; vector<int> vc[N], e[N]; int col[N]; int vis[N]; int mx = 0; void dfs(int o, int u) { for (int v : vc[u]) { vis[col[v]]++; } int b = 1; for (int v : vc[u]) { if (col[v]) continue; while (vis[b]) ++b; vis[b] = 1; col[v] = b; } mx = max(mx, b); for (int v : vc[u]) { vis[col[v]] = 0; } for (int v : e[u]) { if (v == o) continue; dfs(u, v); } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { int si, tv; scanf( %d , &si); for (int j = 1; j <= si; ++j) { scanf( %d , &tv); vc[i].push_back(tv); } } int u, v; for (int i = 1; i < n; ++i) { scanf( %d%d , &u, &v); e[u].push_back(v); e[v].push_back(u); } dfs(0, 1); printf( %d n , mx); for (int i = 1; i <= m; ++i) { if (!col[i]) col[i] = 1; printf( %d%c , col[i], n [i == m]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int K = 7; const int N = 2005; int a[K][N]; vector<int> s[N]; int d[N], n, k, p; void read() { cin >> n >> k; for (int i = 0; i < int(k); ++i) { for (int j = 0; j < int(n); ++j) { cin >> p; --p; if (i == 0) a[i][j] = p; else a[i][p] = j; } } } inline bool can_be_next(const vector<int>& a, const vector<int>& b) { assert(a.size() == b.size()); for (int i = 0; i < int(a.size()); ++i) { if (b[i] <= a[i]) return false; } return true; } void solve() { for (int i = 0; i < int(n); ++i) { s[i] = vector<int>(k - 1); for (int j = 1; j < k; ++j) s[i][j - 1] = a[j][a[0][i]]; } int res = 0; for (int i = 0; i < int(n); ++i) { d[i] = 1; for (int j = 0; j < int(i); ++j) if (can_be_next(s[j], s[i])) d[i] = max(d[j] + 1, d[i]); res = max(res, d[i]); } cout << res << endl; } int main() { read(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int N; double A[100001]; double dp[100001]; int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %lf , A + i); double ans = 0.0; for (int i = 1; i <= N; i++) ans += A[i] + 2 * (dp[i] = (dp[i - 1] + A[i - 1]) * A[i]); printf( %.9f n , ans); return 0; } |
/*
* async_fifo: asynchronous FIFO, 18 bits wide
*
* (C) Arlet Ottens <>
*/
module async_fifo(
input clka,
input [17:0] in,
input wr,
output full,
input clkb,
output [17:0] out,
input rd,
output empty );
reg [10:0] head_a = 0;
reg [10:0] head_a_b = 0;
reg [10:0] head_b = 0;
reg [10:0] tail_b = 0;
reg [10:0] tail_b_a = 0;
reg [10:0] tail_a = 0;
wire [10:0] size_a = (head_a - tail_a);
assign full = (size_a >= 11'h200);
assign empty = (tail_b == head_b);
RAMB16_S18_S18 mem(
.CLKA(clka),
.ADDRA(head_a[9:0]),
.DIA(in[15:0]),
.DIPA(in[17:16]),
.WEA(1'b1),
.ENA(wr & ~full),
.SSRA(1'b0),
.CLKB(clkb),
.ADDRB(tail_b[9:0]),
.DOB(out[15:0]),
.DOPB(out[17:16]),
.ENB(rd & ~empty),
.WEB(1'b0),
.SSRB(1'b0)
);
handshake handshake(
.clka(clka),
.clkb(clkb),
.sync_a(sync_a),
.sync_b(sync_b) );
/*
* clka domain
*/
always @(posedge clka)
if( wr & ~full )
head_a <= head_a + 1;
always @(posedge clka)
if( sync_a ) begin
head_a_b <= head_a;
tail_a <= tail_b_a;
end
/*
* clkb domain
*/
always @(posedge clkb)
if( sync_b ) begin
head_b <= head_a_b;
tail_b_a <= tail_b;
end
always @(posedge clkb)
if( rd & ~empty )
tail_b <= tail_b + 1;
endmodule
|
// We assume clock with frequency F = 100 MHz or period T = 10 ns
`timescale 1ns / 1ps
module moore_fsm_tb;
// Inputs (reg because they are assigned using procedural blocks)
reg clk;
reg rst;
reg inp;
// outputs
wire oup;
wire [2:0] current_state;
wire [2:0] next_state;
// Clock Constants
localparam CLK_PERIOD = 10; // in ns
// Input value enumerations (constants)
localparam i_val_a = 1'b0;
localparam i_val_b = 1'b1;
// State assignment (constants)
localparam STATE_U = 3'b000;
localparam STATE_V = 3'b001;
localparam STATE_W = 3'b010;
localparam STATE_X = 3'b011;
localparam STATE_Y = 3'b100;
localparam STATE_Z = 3'b101;
task expect;
input exp_current_state;
input exp_oup;
input exp_next_state;
if (exp_oup !== oup) begin
$display("TEST FAILED");
$display("k=%0d: s(k)=%0d, i(k)=%0b, o(k)=%0b, s(k+1)=%0d",
$time,
current_state,
inp,
oup,
next_state );
$display("Should be k=%0d: s(k)=%0d, i(k)=%0b, o(k)=%0b, s(k+1)=%0d",
$time,
exp_current_state,
inp,
exp_oup,
exp_next_state );
$finish;
end else begin
$display("k=%0d: s(k)=%0d, i(k)=%0b, o(k)=%0b, s(k+1)=%0d",
$time,
current_state,
inp,
oup,
next_state );
end
endtask
// Instantiate the Unit Under Test (UUT)
moore_fsm uut(.clk(clk),
.rst(rst),
.i_input(inp),
.o_output(oup),
.o_current_state(current_state),
.o_next_state(next_state));
// Clock and async reset stimulus
initial begin
clk = 1'b0;
rst = 1'b1;
// hold sync reset for next 2 cc
repeat(4) #(CLK_PERIOD/2) clk = ~clk;
// deassert reset
rst = 1'b0;
// clock forever
forever #(CLK_PERIOD/2) clk = ~clk;
end
// Stimulus and checker
initial begin
// Default value
inp = i_val_a;
// Observe effect of async reset
// input same as last
// expected s(k) = STATE_U, o(k)=1 , s(k+1) = STATE_Z
@(negedge clk);
expect(STATE_U, 1'b1, STATE_Z);
// Wait for reset to Deassert
@(negedge rst);
// input same as last
// expected s(k) = STATE_Z, o(k)=1 , s(k+1) = STATE_Y
@(negedge clk);
expect(STATE_Z, 1'b1, STATE_Y);
// input same as last
// expected s(k) = STATE_Y, o(k)=1 , s(k+1) = STATE_V
@(negedge clk);
expect(STATE_Y, 1'b1, STATE_V);
// input same as last
// expected s(k) = STATE_V, o(k)=0 , s(k+1) = STATE_Z
@(negedge clk);
expect(STATE_V, 1'b0, STATE_Z);
// wait for last state transition to complete
@(posedge clk);
// Change input
inp = i_val_b;
// expected s(k) = STATE_Z, o(k)=1 , s(k+1) = STATE_X
@(negedge clk);
expect(STATE_Z, 1'b1, STATE_X);
// input same as last
// expected s(k) = STATE_X, o(k)=0 , s(k+1) = STATE_X
@(negedge clk);
expect(STATE_X, 1'b0, STATE_X);
// wait for last state transition to complete
@(posedge clk);
// Change input
inp = i_val_a;
// expected s(k) = STATE_X, o(k)=0 , s(k+1) = STATE_Y
@(negedge clk);
expect(STATE_X, 1'b0, STATE_Y);
$display("TEST PASSED");
$finish;
end
endmodule // module moore_fsm_tb;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_TB_V
`define SKY130_FD_SC_HS__A21OI_TB_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1 = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1 = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1 = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1 = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__a21oi dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, a, b, k; const int MOD = 1000000007; int dp[5005][5005], sum[5005]; int main() { scanf( %d%d%d%d , &n, &b, &a, &k); for (int i = b; i <= n; i++) sum[i] = 1; dp[0][b] = 1; for (int i = 1; i <= k; i++) { for (int j = 1; j <= n; j++) { if (j == a) continue; if (j > a) dp[i][j] = ((sum[n] - sum[(a + j) / 2] + MOD) % MOD - dp[i - 1][j] + MOD) % MOD; else dp[i][j] = (sum[(a - 1 + j) / 2] - dp[i - 1][j] + MOD) % MOD; } sum[0] = 0; for (int j = 1; j <= n; j++) sum[j] = (sum[j - 1] + dp[i][j]) % MOD; } printf( %d n , sum[n]); return 0; } |
module testbench;
reg clk;
reg reset;
reg Compress;
reg Decompress;
initial
begin
clk = 1'b1;
reset = 1'b1;
Decompress = 1'b0;
#30 reset = 1'b0;
#50 Compress = 1'b1;
end
always
#5 clk = ~clk;
wire [17:0] oBufferIn;
BufferIn buffin(
.Clk(clk),
.InputBuffer(RequestInputBuffer),
.oBufferIn(oBufferIn),
.EndOfFile(EOF)
);
controller ctrl(
.clk(clk),
.reset(reset),
.StringLoadZero(StringLoadZero),
.StringLoadChar(StringLoadChar),
.StringLoadBuffer(StringLoadBuffer),
.ConcatenateChar(ConcatenateChars),
.StringShiftRight(StringShiftRight),
.ConcatenateStringSize(ConcatenateStringSize),
.LoadInsertPointer(LoadInsertPointer),
.UpdateInsertPointer(UpdateInsertPointer),
.CodeLoadZero(CodeLoadZero),
.CodeIncrement(CodeIncrement),
.NotFound(NotFound),
.Found(Found),
.CharLoadBuffer(CharLoadBuffer),
.BufferInitDicPointer(BufferInitDicPointer),
.LoadDicPointer(LoadDicPointer),
.DicPointerIncrement(DicPointerIncrement),
.LoadJumpAddress(JumpLoadAddress),
.DicPointerLoadInsert(DicPointerLoadInsert),
.StringRAMLoad(StringRAMLoad),
.StringRAMZero(StringRAMZero),
.StringRAMShift(StringRAMShift),
.SetJumpAddress(SetJumpAddress),
.RequestOutBuffer(RequestOutBuffer),
.CloseBuffer(CloseBuffer),
.RAMread(RAMread),
.RAMZeroData(oRAMzeroData),
.InitRAMCode(oInitRAMCode),
.WriteString(oWriteString),
//************************ Jump conditions******************************
.Compress(Compress), // 1100
.Decompress(Decompress), // 1011
.DicPointerEqualsINsertPoniter(DicPointerEqualsInsertPointer), // 1010
.StringRAMSizeEqualsStringSize(StringRAMSizeEqualsStringSize), // 1001
.DicPointerEqualsJumpAddress(DicPointerEqualsJumpAddress), // 1000
.StringRAMSizeEqualsZero(StringRAMSizeEqualsZero), // 0111
.StringRAMEqualsString(StringRAMEqualsString), // 0110
.CodeBigger128(CodeBigger128), // 0101
.CodeEqualsZero(CodeEqualsZero), // 0100
.EndOfFile(EOF), // 0011
.FoundStatus(FoundStatus) // 0010
// Inconditional jump // 0001
// No jump // 0000
);
wire [15:0] iRAMBuffer;
wire [11:0] outBuffer;
wire [7:0] ramCode;
wire [15:0] ramString;
wire [17:0] ramDicPointer;
Registers registers(
.Clk(clk),
.InBuffer(oBufferIn),
.iRAMBuffer(iRAMBuffer),
.outBuffer(outBuffer),
.RequestInBuffer(RequestInputBuffer),
// **************** Control for String *************************************
.StringLoadZero(StringLoadZero),
.StringLoadChar(StringLoadChar),
.StringLoadBuffer(StringLoadBuffer),
.ConcatenateChar(ConcatenateChars),
.StringShiftRight(StringShiftRight),
.ConcatenateStringSize(ConcatenateStringSize),
// **************** Control for Insert Pointer *************************
.LoadInsertPointer(LoadInsertPointer),
.UpdateInsertPointer(UpdateInsertPointer),
// **************** Control for Code ***********************************
.CodeLoadZero(CodeLoadZero),
.CodeIncrement(CodeIncrement),
// **************** Control for Found **********************************
.NotFound(NotFound),
.Found(Found),
// **************** Control for Char ***********************************
.CharLoadBuffer(CharLoadBuffer),
// **************** Control for Init Dictionary Pointer ****************
.BufferInitDicPointer(BufferInitDicPointer),
// **************** Control for Dictionary Pointer *********************
.LoadDicPointer(LoadDicPointer),
.DicPointerIncrement(DicPointerIncrement),
.LoadJumpAddress(JumpLoadAddress),
.DicPointerLoadInsert(DicPointerLoadInsert),
// **************** Control for StringRAM ******************************
.StringRAMLoad(StringRAMLoad),
.StringRAMZero(StringRAMZero),
.StringRAMShift(StringRAMShift),
// **************** Control for Jumping Address ************************
.SetJumpAddress(SetJumpAddress),
// ****************** Jump conditions **********************************
.DicPointerEqualsInsertPointer(DicPointerEqualsInsertPointer),
.StringRAMSizeEqualsStringSize(StringRAMSizeEqualsStringSize),
.DicPointerEqualsJumpAddress(DicPointerEqualsJumpAddress),
.StringRAMSizeEqualsZero(StringRAMSizeEqualsZero),
.StringRAMEqualsString(StringRAMEqualsString),
.CodeBigger128(CodeBigger128),
.CodeEqualsZero(CodeEqualsZero),
.FoundStatus(FoundStatus),
// ********************* Data to RAM ***********************************
.ramCode(ramCode),
.ramString(ramString),
.ramDicPointer(ramDicPointer)
);
wire [15:0] oRAMBuffer;
RAMBuffer ramBuffer(
.RAMread(RAMread),
.RAMZeroData(oRAMzeroData),
.InitRAMCode(oInitRAMCode),
.WriteString(oWriteString),
.ramCode(ramCode),
.ramString(ramString),
.ramDicPointer(ramDicPointer),
.oRAMBuffer(oRAMBuffer)
);
BufferOut BufferOut(
.Clk(clk),
.OutputBuffer(RequestOutBuffer),
.CloseBuffer(CloseBuffer),
.iBufferOut(outBuffer)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!(ch >= 0 && ch <= 9 )) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * f; } void chkmin(int &a, int b) { if (b < a) a = b; } const int N = 81; const int INF = 88888888; int n; int dp[N][N][N][3]; char s[N]; vector<int> V, K, O; int calc(int pos, int a, int b, int c) { int ret = 0; for (int i = 1; i <= pos - 1; i++) { if (s[i] == V ) { if (a) a--; else ++ret; } if (s[i] == K ) { if (b) b--; else ++ret; } if (s[i] != V && s[i] != K ) { if (c) c--; else ++ret; } } return ret; } int main() { n = read(); scanf( %s , s + 1); for (int i = 1; i <= n; i++) { if (s[i] == V ) V.push_back(i); else if (s[i] == K ) K.push_back(i); else O.push_back(i); } for (int a = 0; a <= n; a++) for (int b = 0; b <= n; b++) for (int c = 0; c <= n; c++) for (int d = 0; d <= 1; d++) dp[a][b][c][d] = INF; dp[0][0][0][0] = 0; for (int a = 0; a <= V.size(); a++) { for (int b = 0; b <= K.size(); b++) { for (int c = 0; c <= O.size(); c++) { for (int flag = 0; flag <= 1; flag++) { if (a < V.size()) chkmin(dp[a + 1][b][c][1], dp[a][b][c][flag] + calc(V[a], a, b, c)); if (b < K.size() && !flag) chkmin(dp[a][b + 1][c][0], dp[a][b][c][flag] + calc(K[b], a, b, c)); if (c < O.size()) chkmin(dp[a][b][c + 1][0], dp[a][b][c][flag] + calc(O[c], a, b, c)); } } } } printf( %d n , min(dp[V.size()][K.size()][O.size()][0], dp[V.size()][K.size()][O.size()][1])); return 0; } |
`define SC_IDLE 2'b00
`define SC_CVI 2'b01
`define SC_CVO 2'b10
module alt_vipitc131_IS2Vid_sync_compare(
input wire rst,
input wire clk,
// control signals
input wire [1:0] genlock_enable,
input wire serial_output,
input wire [13:0] h_total_minus_one,
input wire restart_count,
input wire [13:0] divider_value,
// control signals to is2vid
output reg sync_lines,
output reg sync_samples,
output reg remove_repeatn,
output reg [12:0] sync_compare_h_reset,
output reg [12:0] sync_compare_v_reset,
output reg genlocked,
// sync signals from CVI
input wire sof_cvi,
input wire sof_cvi_locked,
// sync signals from CVO
input wire sof_cvo,
input wire sof_cvo_locked);
parameter NUMBER_OF_COLOUR_PLANES = 0;
parameter COLOUR_PLANES_ARE_IN_PARALLEL = 0;
parameter LOG2_NUMBER_OF_COLOUR_PLANES = 0;
wire sof_cvi_int;
wire sof_cvo_int;
reg sof_cvi_reg;
reg sof_cvo_reg;
always @ (posedge rst or posedge clk) begin
if(rst) begin
sof_cvi_reg <= 1'b0;
sof_cvo_reg <= 1'b0;
end else begin
sof_cvi_reg <= sof_cvi;
sof_cvo_reg <= sof_cvo;
end
end
assign sof_cvi_int = sof_cvi & ~sof_cvi_reg;
assign sof_cvo_int = sof_cvo & ~sof_cvo_reg;
wire enable;
wire sclr;
wire sclr_frame_counter;
wire sclr_state;
assign enable = sof_cvi_locked & sof_cvo_locked & genlock_enable[1] & genlock_enable[0];
assign sclr = ~enable | restart_count;
assign sclr_frame_counter = sclr | sof_cvi_int | sof_cvo_int;
assign sclr_state = (sof_cvi_int & sof_cvo_int);
reg [13:0] h_count_repeat;
reg [13:0] h_count_remove;
reg [12:0] v_count_repeat;
reg [12:0] v_count_remove;
reg [1:0] next_state;
reg [1:0] state;
wire [13:0] h_count;
wire [12:0] v_count;
wire remove_lines_next;
wire [12:0] sync_compare_v_reset_next;
wire [12:0] sync_compare_h_reset_next;
wire valid;
reg v_count_remove_valid;
reg v_count_repeat_valid;
wire syncing_lines;
wire remove_samples_next;
// double register the outputs to allow register retiming
reg sync_lines0;
reg sync_samples0;
reg remove_repeatn0;
reg [13:0] sync_compare_h_reset0;
reg [12:0] sync_compare_v_reset0;
reg genlocked0;
reg sync_lines1;
reg sync_samples1;
reg remove_repeatn1;
reg [13:0] sync_compare_h_reset1;
reg [12:0] sync_compare_v_reset1;
reg genlocked1;
always @ (posedge rst or posedge clk) begin
if(rst) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= 1'b0;
v_count_remove <= 13'd0;
v_count_remove_valid <= 1'b0;
state <= `SC_IDLE;
sync_lines0 <= 1'b0;
sync_samples0 <= 1'b0;
sync_compare_v_reset0 <= 13'd0;
sync_compare_h_reset0 <= 14'd0;
remove_repeatn0 <= 1'b0;
genlocked0 <= 1'b0;
sync_lines1 <= 1'b0;
sync_samples1 <= 1'b0;
sync_compare_v_reset1 <= 13'd0;
sync_compare_h_reset1 <= 14'd0;
remove_repeatn1 <= 1'b0;
genlocked1 <= 1'b0;
sync_lines <= 1'b0;
sync_samples <= 1'b0;
sync_compare_v_reset <= 13'd0;
sync_compare_h_reset <= 14'd0;
remove_repeatn <= 1'b0;
genlocked <= 1'b0;
end else begin
if(sclr) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= 1'b0;
v_count_remove <= 13'd0;
v_count_remove_valid <= 1'b0;
state <= `SC_IDLE;
end else begin
if(sclr_state) begin
h_count_repeat <= 14'd0;
h_count_remove <= 14'd0;
v_count_repeat <= 13'd0;
v_count_repeat_valid <= (14'd0 == h_count_repeat) && (13'd0 == v_count_repeat);
v_count_remove <= 13'd0;
v_count_remove_valid <= (14'd0 == h_count_remove) && (13'd0 == v_count_remove);
end else begin
if(state == `SC_CVI && next_state == `SC_CVO) begin
h_count_remove <= h_count;
v_count_remove <= v_count;
v_count_remove_valid <= (h_count == h_count_remove) && (v_count == v_count_remove);
end
if(state == `SC_CVO && next_state == `SC_CVI) begin
h_count_repeat <= h_count;
v_count_repeat <= v_count;
v_count_repeat_valid <= (h_count == h_count_repeat) && (v_count == v_count_repeat);
end
end
state <= next_state;
end
if(sclr | ~valid) begin
sync_lines0 <= 1'b0;
sync_samples0 <= 1'b0;
sync_compare_v_reset0 <= 13'd0;
sync_compare_h_reset0 <= 14'd0;
genlocked0 <= 1'b0;
end else begin
if(syncing_lines) begin
sync_compare_v_reset0 <= sync_compare_v_reset_next;
sync_lines0 <= 1'b1;
sync_compare_h_reset0 <= sync_compare_h_reset_next;
sync_samples0 <= 1'b1;
genlocked0 <= 1'b0;
end else begin
sync_compare_v_reset0 <= 13'd0;
sync_lines0 <= 1'b0;
if(sync_compare_h_reset_next > divider_value) begin
sync_compare_h_reset0 <= sync_compare_h_reset_next;
sync_samples0 <= 1'b1;
genlocked0 <= 1'b0;
end else begin
sync_compare_h_reset0 <= 14'd0;
sync_samples0 <= 1'b0;
genlocked0 <= 1'b1;
end
end
end
remove_repeatn0 <= remove_samples_next;
sync_lines1 <= sync_lines0;
sync_samples1 <= sync_samples0;
remove_repeatn1 <= remove_repeatn0;
sync_compare_h_reset1 <= sync_compare_h_reset0;
sync_compare_v_reset1 <= sync_compare_v_reset0;
genlocked1 <= genlocked0;
sync_lines <= sync_lines1;
sync_samples <= sync_samples1;
remove_repeatn <= remove_repeatn1;
sync_compare_h_reset <= sync_compare_h_reset1;
sync_compare_v_reset <= sync_compare_v_reset1;
genlocked <= genlocked1;
end
end
assign valid = v_count_remove_valid & v_count_repeat_valid;
assign remove_lines_next = v_count_remove < v_count_repeat;
assign sync_compare_v_reset_next = (remove_lines_next) ? v_count_remove : v_count_repeat;
assign syncing_lines = sync_compare_v_reset_next > 13'd0;
assign remove_samples_next = (syncing_lines) ? remove_lines_next : h_count_remove < h_count_repeat;
assign sync_compare_h_reset_next = (remove_lines_next) ? h_count_remove : h_count_repeat;
always @ (state or sof_cvi_int or sof_cvo_int) begin
next_state = state;
case(state)
`SC_CVI: begin
if(sof_cvo_int & sof_cvi_int)
next_state = `SC_IDLE;
else if(sof_cvo_int)
next_state = `SC_CVO;
end
`SC_CVO: begin
if(sof_cvi_int & sof_cvo_int)
next_state = `SC_IDLE;
else if(sof_cvi_int)
next_state = `SC_CVI;
end
default: begin
if(sof_cvi_int & ~sof_cvo_int)
next_state = `SC_CVI;
else if(~sof_cvi_int & sof_cvo_int)
next_state = `SC_CVO;
end
endcase
end
alt_vipitc131_common_frame_counter frame_counter(
.rst(rst),
.clk(clk),
.sclr(sclr_frame_counter),
.enable(enable),
.hd_sdn(~serial_output),
.h_total(h_total_minus_one),
.v_total({13{1'b1}}),
.h_reset(14'd0),
.v_reset(13'd0),
.h_count(h_count),
.v_count(v_count));
defparam frame_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
frame_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
frame_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES,
frame_counter.TOTALS_MINUS_ONE = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int first; int second; } a[350030]; int cmp(node a, node b) { if (a.first == b.first) { return a.second < b.second; } else return a.first > b.first; } int main() { int n; while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) { scanf( %d , &a[i].first); a[i].second = i; } sort(a + 1, a + 1 + n, cmp); int L, R; L = R = a[1].second; int ans = 1000000000 + 7; for (int i = 2; i <= n; i++) { ans = min(ans, a[i].first / max(abs(a[i].second - L), abs(a[i].second - R))); L = min(L, a[i].second); R = max(R, a[i].second); } printf( %d n , ans); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:16:57 02/26/2016
// Design Name:
// Module Name: Register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register(
input clock_in,
input regWrite,
input [4:0] readReg1, //address to be read1
input [4:0] readReg2,
input [4:0] writeReg, //address to be write
input [31:0] writeData,
input reset,
output [31:0] readData1,
output [31:0] readData2,
output [31:0] reg1,
output [31:0] reg2
);
reg [31:0] regFile[31:0];
initial $readmemh("./src/regFile.txt",regFile);
assign readData1 = regFile[readReg1];
assign readData2 = regFile[readReg2];
assign reg1 = regFile[1];
assign reg2 = regFile[2];
always @(negedge clock_in)
begin
if(reset) $readmemh("./src/regFile.txt",regFile);
else if(regWrite) regFile[writeReg] = writeData;
else;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x; cin >> x; int a[x], i; for (i = 0; i < x; i++) { cin >> a[i]; } sort(a, a + x); int s = 0; int j = 0, m = 0; for (i = 0; i < x; i++) { while (j < x && a[j] - a[i] <= 5) { j++; s = max(s, j - i); } } cout << s; } |
`timescale 1ns/10ps
module VGA2InterfaceSim;
reg clock;
reg reset;
reg color_r;
reg color_g;
reg color_b;
wire [10:0] fb_addr_h;
wire [10:0] fb_addr_v;
wire vga_hsync;
wire vga_vsync;
wire vga_r;
wire vga_g;
wire vga_b;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0 color_r = 0;
color_g = 0;
color_b = 0;
#40 color_r = 1;
color_g = 0;
color_b = 0;
#40 color_r = 1;
color_g = 1;
color_b = 0;
#40 color_r = 0;
color_g = 1;
color_b = 0;
#40 color_r = 0;
color_g = 0;
color_b = 0;
#40 color_r = 0;
color_g = 0;
color_b = 1;
end // initial begin
VGA2Interface #(.HAddrSize(11),
.HVisibleArea(4),
.HFrontPorch(2),
.HSyncPulse(3),
.HBackPorch(2),
.VAddrSize(11),
.VVisibleArea(5),
.VFrontPorch(2),
.VSyncPulse(3),
.VBackPorch(2))
vgaint (.clock(clock),
.reset(reset),
.color_r(color_r),
.color_g(color_g),
.color_b(color_b),
.fb_addr_h(fb_addr_h),
.fb_addr_v(fb_addr_v),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // VGA2InterfaceSim
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:12 10/28/2015
// Design Name:
// Module Name: UART_echo_test_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_echo_test_module(
input clock,
input echo_test_rx,
input echo_test_reset,
output echo_test_tx
);
wire baud_rate_rx,
baud_rate_tx,
echo_test_rx_done,
echo_test_tx_done,
echo_test_tx_start,
read_next_tx,
echo_test_empty_flag_rx,
echo_test_not_empty_flag_rx,
echo_test_empty_flag_tx,
echo_test_not_empty_flag_tx;
// echo_test_full_flag_rx,
// echo_test_full_flag_tx;
wire [7:0] echo_test_data_rx;
wire [7:0] echo_test_data_tx;
wire [7:0] echo_test_data;
localparam echo_test_COUNT = 651;
UART_baud_rate_generator #(.COUNT(echo_test_COUNT)) rx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_rx)
);
UART_rx receptor(
.rx(echo_test_rx),
.s_tick(baud_rate_rx),
.clock(clock),
.reset(echo_test_reset),
.rx_done(echo_test_rx_done),
.d_out(echo_test_data_rx)
);
UART_fifo_interface fifo_rx(
.clock(clock),
.reset(echo_test_reset),
.write_flag(echo_test_rx_done),
.read_next(echo_test_not_empty_flag_rx),
.data_in(echo_test_data_rx),
.data_out(echo_test_data),
.empty_flag(echo_test_empty_flag_rx)
// .full_flag(echo_test_full_flag_rx)
);
UART_baud_rate_generator #(.COUNT(echo_test_COUNT*16)) tx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_tx)
);
UART_tx transmisor(
.clock(clock),
.reset(echo_test_reset),
.s_tick(baud_rate_tx),
.tx_start(echo_test_start_tx),
.data_in(echo_test_data_tx),
.tx(echo_test_tx),
.tx_done(echo_test_tx_done)
);
UART_fifo_interface fifo_tx(
.clock(clock),
.reset(echo_test_reset),
.write_flag(echo_test_not_empty_flag_rx),
.read_next(echo_test_not_empty_flag_tx),
.data_in(echo_test_data),
.data_out(echo_test_data_tx),
.empty_flag(echo_test_empty_flag_tx)
// .full_flag(echo_test_full_flag_tx)
);
// assign read_next_tx = echo_test_not_empty_flag_tx && echo_test_tx_done;
assign echo_test_start_tx = echo_test_empty_flag_tx;
assign echo_test_not_empty_flag_tx = ~echo_test_empty_flag_tx;
assign echo_test_not_empty_flag_rx = ~echo_test_empty_flag_rx;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_BLACKBOX_V
`define SKY130_FD_SC_MS__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); const int nmax = 2e5 + 5; int t, n, a[nmax], b[nmax], f[nmax], L[nmax], R[nmax], d[nmax]; long long ans; vector<int> v1[nmax], v2[nmax]; int main() { srand(time(NULL)); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { ans = 0; cin >> n; for (int i = 1; i <= n; i++) { v1[i].clear(); v2[i].clear(); f[i] = 0; d[i] = 0; } R[n + 1] = 0; for (int i = 1; i <= n; i++) { cin >> a[i] >> b[i]; f[b[i]]++; v1[a[i]].emplace_back(b[i]); v2[b[i]].emplace_back(a[i]); } for (int i = 1; i <= n; i++) L[i] = L[i - 1] + v2[i].size(); for (int i = n; i >= 1; i--) R[i] = R[i + 1] + v2[i].size(); for (int i = 2; i < n; i++) ans = ans + 1ll * v2[i].size() * L[i - 1] * R[i + 1]; for (int i = 1; i <= n; i++) L[i] = L[i - 1] + v1[i].size(); for (int i = n; i >= 1; i--) R[i] = R[i + 1] + v1[i].size(); for (int i = 2; i < n; i++) ans = ans + 1ll * v1[i].size() * L[i - 1] * R[i + 1]; for (int i = 1; i <= n; i++) sort(v1[i].begin(), v1[i].end()); for (int i = 1; i <= n; i++) if (v1[i].size() > 0) { int dem = 1; for (int j = 1; j < v1[i].size(); j++) if (v1[i][j] != v1[i][j - 1]) { int x = v1[i][j - 1]; ans = ans - 1ll * dem * (L[i - 1] - d[x]) * (R[i + 1] - (f[x] - d[x] - dem)); dem = 1; } else dem++; int x = v1[i][v1[i].size() - 1]; ans = ans - 1ll * dem * (L[i - 1] - d[x]) * (R[i + 1] - (f[x] - d[x] - dem)); for (auto p : v1[i]) d[p]++; } for (int i = 1; i <= n; i++) d[i] = 0; long long res = 0; for (int i = 1; i <= n; i++) if (v1[i].size() > 0) { int dem = 1; for (int j = 1; j < v1[i].size(); j++) if (v1[i][j] != v1[i][j - 1]) { int x = v1[i][j - 1]; res = res - 1ll * dem * d[x]; dem = 1; } else dem++; int x = v1[i][v1[i].size() - 1]; res = res - 1ll * dem * d[x]; ans = ans + 1ll * v1[i].size() * res; dem = 1; for (int j = 1; j < v1[i].size(); j++) if (v1[i][j] != v1[i][j - 1]) { int x = v1[i][j - 1]; res = res + 1ll * dem * (f[x] - d[x] - dem); dem = 1; } else dem++; x = v1[i][v1[i].size() - 1]; res = res + 1ll * dem * (f[x] - d[x] - dem); for (auto p : v1[i]) d[p]++; } for (int i = 1; i <= n; i++) d[i] = 0; for (int i = 1; i <= n; i++) if (v1[i].size() > 0) { int dem = 1; for (int j = 1; j < v1[i].size(); j++) if (v1[i][j] != v1[i][j - 1]) { int x = v1[i][j - 1]; ans = ans - 1ll * d[x] * (f[x] - d[x] - dem); dem = 1; } else dem++; int x = v1[i][v1[i].size() - 1]; ans = ans - 1ll * d[x] * (f[x] - d[x] - dem); for (auto p : v1[i]) d[p]++; } cout << ans << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> f, s; int main() { long long buf, sumf = 0, sums = 0; int last = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> buf; if (buf > 0) { f.push_back(buf); sumf += buf; last = 1; } else { s.push_back(-buf); sums -= buf; last = 2; } } if (sumf > sums) cout << first << endl; else if (sumf < sums) cout << second << endl; else { for (int i = 0; i < min(f.size(), s.size()); i++) { if (f[i] > s[i]) { cout << first << endl; return 0; } else if (f[i] < s[i]) { cout << second << endl; return 0; } } if (f.size() > s.size()) { cout << first << endl; } else if (f.size() < s.size()) { cout << second << endl; } else { if (last == 1) cout << first << endl; else cout << second << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimization( unroll-loops ) using namespace std; template <typename T> ostream& operator<<(ostream& out, vector<T>& a) { for (auto& p : a) out << p << ; return out; } template <typename T> istream& operator>>(istream& inp, vector<T>& a) { for (auto& p : a) inp >> p; return inp; } signed main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cout.precision(20); srand((signed)time(NULL)); long long n = 0, ans = 0; cin >> n; vector<pair<long long, long long>> arr(n); for (auto& p : arr) cin >> p.first >> p.second; map<long long, long long> gx, gy; for (long long i = 0; i < n; i++) { ans += gx[arr[i].first] + gy[arr[i].second]; gx[arr[i].first]++, gy[arr[i].second]++; } map<pair<long long, long long>, long long> gg; for (long long i = 0; i < n; i++) gg[arr[i]]++; for (auto& p : gg) ans -= p.second * (p.second - 1) / 2; cout << ans << n ; return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_way_CE_timer for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_way_CE_timer
// Module Name: NPCG_Toggle_way_CE_timer
// File Name: NPCG_Toggle_way_CE_timer.v
//
// Version: v1.0.0
//
// Description: Way chip enable timer
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_way_CE_timer
#
(
parameter NumberOfWays = 8
)
(
iSystemClock ,
iReset ,
iWorkingWay ,
ibCMDLast ,
ibCMDLast_SCC ,
iTargetWay ,
oCMDHold
);
input iSystemClock ;
input iReset ;
input [NumberOfWays - 1:0] iWorkingWay ;
input ibCMDLast ;
input ibCMDLast_SCC ;
input [NumberOfWays - 1:0] iTargetWay ;
output oCMDHold ;
wire wWay0_Deasserted ;
wire wWay1_Deasserted ;
wire wWay2_Deasserted ;
wire wWay3_Deasserted ;
wire wWay4_Deasserted ;
wire wWay5_Deasserted ;
wire wWay6_Deasserted ;
wire wWay7_Deasserted ;
reg [3:0] rWay0_Timer ;
reg [3:0] rWay1_Timer ;
reg [3:0] rWay2_Timer ;
reg [3:0] rWay3_Timer ;
reg [3:0] rWay4_Timer ;
reg [3:0] rWay5_Timer ;
reg [3:0] rWay6_Timer ;
reg [3:0] rWay7_Timer ;
wire wWay0_Ready ;
wire wWay1_Ready ;
wire wWay2_Ready ;
wire wWay3_Ready ;
wire wWay4_Ready ;
wire wWay5_Ready ;
wire wWay6_Ready ;
wire wWay7_Ready ;
wire wWay0_Targeted ;
wire wWay1_Targeted ;
wire wWay2_Targeted ;
wire wWay3_Targeted ;
wire wWay4_Targeted ;
wire wWay5_Targeted ;
wire wWay6_Targeted ;
wire wWay7_Targeted ;
assign wWay0_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[0];
assign wWay1_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[1];
assign wWay2_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[2];
assign wWay3_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[3];
assign wWay4_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[4];
assign wWay5_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[5];
assign wWay6_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[6];
assign wWay7_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[7];
assign wWay0_Ready = (rWay0_Timer[3:0] == 4'b1110); // 14 cycle -> 140 ns
assign wWay1_Ready = (rWay1_Timer[3:0] == 4'b1110);
assign wWay2_Ready = (rWay2_Timer[3:0] == 4'b1110);
assign wWay3_Ready = (rWay3_Timer[3:0] == 4'b1110);
assign wWay4_Ready = (rWay4_Timer[3:0] == 4'b1110);
assign wWay5_Ready = (rWay5_Timer[3:0] == 4'b1110);
assign wWay6_Ready = (rWay6_Timer[3:0] == 4'b1110);
assign wWay7_Ready = (rWay7_Timer[3:0] == 4'b1110);
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rWay0_Timer[3:0] <= 4'b1110;
rWay1_Timer[3:0] <= 4'b1110;
rWay2_Timer[3:0] <= 4'b1110;
rWay3_Timer[3:0] <= 4'b1110;
rWay4_Timer[3:0] <= 4'b1110;
rWay5_Timer[3:0] <= 4'b1110;
rWay6_Timer[3:0] <= 4'b1110;
rWay7_Timer[3:0] <= 4'b1110;
end else begin
rWay0_Timer[3:0] <= (wWay0_Deasserted)? 4'b0000:((wWay0_Ready)? (rWay0_Timer[3:0]):(rWay0_Timer[3:0] + 1'b1));
rWay1_Timer[3:0] <= (wWay1_Deasserted)? 4'b0000:((wWay1_Ready)? (rWay1_Timer[3:0]):(rWay1_Timer[3:0] + 1'b1));
rWay2_Timer[3:0] <= (wWay2_Deasserted)? 4'b0000:((wWay2_Ready)? (rWay2_Timer[3:0]):(rWay2_Timer[3:0] + 1'b1));
rWay3_Timer[3:0] <= (wWay3_Deasserted)? 4'b0000:((wWay3_Ready)? (rWay3_Timer[3:0]):(rWay3_Timer[3:0] + 1'b1));
rWay4_Timer[3:0] <= (wWay4_Deasserted)? 4'b0000:((wWay4_Ready)? (rWay4_Timer[3:0]):(rWay4_Timer[3:0] + 1'b1));
rWay5_Timer[3:0] <= (wWay5_Deasserted)? 4'b0000:((wWay5_Ready)? (rWay5_Timer[3:0]):(rWay5_Timer[3:0] + 1'b1));
rWay6_Timer[3:0] <= (wWay6_Deasserted)? 4'b0000:((wWay6_Ready)? (rWay6_Timer[3:0]):(rWay6_Timer[3:0] + 1'b1));
rWay7_Timer[3:0] <= (wWay7_Deasserted)? 4'b0000:((wWay7_Ready)? (rWay7_Timer[3:0]):(rWay7_Timer[3:0] + 1'b1));
end
end
assign wWay0_Targeted = iTargetWay[0];
assign wWay1_Targeted = iTargetWay[1];
assign wWay2_Targeted = iTargetWay[2];
assign wWay3_Targeted = iTargetWay[3];
assign wWay4_Targeted = iTargetWay[4];
assign wWay5_Targeted = iTargetWay[5];
assign wWay6_Targeted = iTargetWay[6];
assign wWay7_Targeted = iTargetWay[7];
assign oCMDHold = (wWay0_Targeted & (~wWay0_Ready)) |
(wWay1_Targeted & (~wWay1_Ready)) |
(wWay2_Targeted & (~wWay2_Ready)) |
(wWay3_Targeted & (~wWay3_Ready)) |
(wWay4_Targeted & (~wWay4_Ready)) |
(wWay5_Targeted & (~wWay5_Ready)) |
(wWay6_Targeted & (~wWay6_Ready)) |
(wWay7_Targeted & (~wWay7_Ready)) ;
endmodule
|
// TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_006.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_006 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_006_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; multiset<long long> A, B; for (long long i = 0; i < n; i++) { long long num; cin >> num; A.insert(-num); } for (long long i = 0; i < n; i++) { long long num; cin >> num; B.insert(-num); } long long ansa = 0, ansb = 0; while (!A.empty() || !B.empty()) { long long v1 = 0, v2 = 0; if (A.size() > 0) { v1 = -(*A.begin()); if (B.size() > 0) { v2 = -(*B.begin()); if (v2 >= v1) { auto it = B.begin(); B.erase(it); } else { auto it = A.begin(); A.erase(it); ansa += v1; } } else { auto it = A.begin(); A.erase(it); ansa += v1; } } else { if (B.size() > 0) { auto it = B.begin(); B.erase(it); } } v1 = 0, v2 = 0; if (B.size() > 0) { long long v1 = -(*B.begin()); if (A.size() > 0) { v2 = -(*A.begin()); if (v2 >= v1) { auto it = A.begin(); A.erase(it); } else { auto it = B.begin(); B.erase(it); ansb += v1; } } else { auto it = B.begin(); B.erase(it); ansb += v1; } } else { if (A.size() > 0) { auto it = A.begin(); A.erase(it); } } } cout << ansa - ansb; } |
#include <bits/stdc++.h> using namespace std; #define pb push_back #define ff first #define ss second #define lli long long int #define ll long long #define st string #define vi vector<int> #define vll vector<long long> #define tll tuple<ll,ll,ll> #define pii pair<int,int> #define pll pair<ll,ll> #define vpii vector<pii> #define vpll vector<pll> #define take(n) ll n;cin>>n; #define takeinp(arr,n) for(long long int i=0;i<n;i++) cin>>arr[i]; #define gcd(a,b) __gcd(a,b) #define mii map<int,int> #define mll map<ll,ll> #define all(x) x.begin(),x.end() #define allr(x) x.rbegin(),x.rend() #define mllitr mll::iterator itr; #define repm(itr,mp) for(itr=mp.begin();itr!=mp.end();itr++) #define rep(i,a,b) for(ll i=a;i<b;i++) #define repo(i,a,b) for(ll i=a;i>b;i--) //GL HF// void solve(){ string s;cin>>s; ll n=s.length()-1; // cout<<char( a +n)<< n ; if(n==0){ if(s[0]!= a ) {cout<< NO n ;return;} } while(n>=0){ char tmp = a +n; if(s[0]==tmp){ s.erase(s.begin()+0); }else if(s[n]==tmp){ s.erase(s.begin()+n); }else{ cout<< NO n ; return; } n--; } cout<< YES n ; // cout<< a +0<< n ; } int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll t=1; cin>>t; while(t--){ solve(); } } |
#include <bits/stdc++.h> using namespace std; const int N = 200; long long n, num[N], tmp; int main() { cin >> n; for (int i = 0, v; i < n; i++) cin >> v, num[v]++; for (int i = 1; i <= 100; i++) { for (int j = 1; j < i; j++) tmp = max(0ll, min(num[0] - num[j], num[i])), num[j] += tmp, num[i] -= tmp; tmp = num[i] - num[0]; int k = tmp % (i + 1); tmp = tmp / (i + 1); if (tmp > 0 || k > 0) for (int j = 0; j <= i; j++) { num[j] += tmp, num[i] -= tmp; if (j < k) num[j]++, num[i]--; } } cout << num[0] << endl; } |
#include <bits/stdc++.h> using namespace std; const int E9 = 1e9; const int E8 = 1e8; const int E7 = 1e7; const int E6 = 1e6; const int E5 = 1e5; const int E4 = 1e4; const int E3 = 1e3; const int N = 5e5 + 7; const int MOD = 1e9 + 7; const long long INF = 1e18; int n; bool dp[101][51][2][201]; string s; void calc(int com, int kol, int dir, int pos) { if (dp[com][kol][dir][pos]) { return; } dp[com][kol][dir][pos] = 1; if (com == (int)s.size()) { return; } for (int i = 0; i <= n - kol; i++) { if (i % 2 == 0) { if (s[com] == F ) { calc(com + 1, kol + i, dir, pos + (dir == 0 ? 1 : -1)); } else { calc(com + 1, kol + i, (dir ^ 1), pos); } } else { if (s[com] == T ) { calc(com + 1, kol + i, dir, pos + (dir == 0 ? 1 : -1)); } else { calc(com + 1, kol + i, (dir ^ 1), pos); } } } } int main() { cin >> s >> n; calc(0, 0, 0, 100); int sz = (int)s.size(); int mx = 0; for (int i = 0; i <= 200; i++) { if (dp[sz][n][0][i] || dp[sz][n][1][i]) { mx = max(mx, abs(i - 100)); } } cout << mx; } |
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_master_mux.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_master_mux.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus_master_mux(
//master 0
input wire [`WordAddrBus] m0_addr ,//30 address
input wire m0_as_n ,//01
input wire m0_rw ,//01
input wire [`WordDataBus] m0_wr_data ,//32 write data
input wire m0_grant_n ,//01
//master 1
input wire [`WordAddrBus] m1_addr ,//30 address
input wire m1_as_n ,//01
input wire m1_rw ,//01
input wire [`WordDataBus] m1_wr_data ,//32 write data
input wire m1_grant_n ,//01
//master 2
input wire [`WordAddrBus] m2_addr ,//30 address
input wire m2_as_n ,//01
input wire m2_rw ,//01
input wire [`WordDataBus] m2_wr_data ,//32 write data
input wire m2_grant_n ,//01
//master 3
input wire [`WordAddrBus] m3_addr ,//30 address
input wire m3_as_n ,//01
input wire m3_rw ,//01
input wire [`WordDataBus] m3_wr_data ,//32 write data
input wire m3_grant_n ,//01
//share
output reg [`WordAddrBus] s_addr ,//30
output reg s_as_n ,//01
output reg s_rw ,//01
output reg [`WordDataBus] s_wr_data //32
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
always @(*) begin : BUS_MASTER_MULTIPLEX
if(m0_grant_n == `ENABLE_N)
begin
s_addr = m0_addr;
s_as_n = m0_as_n;
s_rw = m0_rw;
s_wr_data = m0_wr_data;
end
else if(m1_grant_n == `ENABLE_N)
begin
s_addr = m1_addr;
s_as_n = m1_as_n;
s_rw = m1_rw;
s_wr_data = m1_wr_data;
end
else if(m2_grant_n == `ENABLE_N)
begin
s_addr = m2_addr;
s_as_n = m2_as_n;
s_rw = m2_rw;
s_wr_data = m2_wr_data;
end
else if(m3_grant_n == `ENABLE_N)
begin
s_addr = m3_addr;
s_as_n = m3_as_n;
s_rw = m3_rw;
s_wr_data = m3_wr_data;
end
else //default
begin
s_addr = `WORD_ADDR_W'h0;
s_as_n = `DISABLE_N;
s_rw = `READ;
s_wr_data = `WORD_DATA_W'h0;
end
end
//------------------------------------------------------------------------------------------------
// 3.2 the master owner control logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_TB_V
`define SKY130_FD_SC_HD__CLKINVLP_TB_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinvlp.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkinvlp dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_TB_V
|
module XorShift128Plus_tb ();
reg [127:0] seed;
reg clk;
reg rst;
reg seedStrobe;
reg read;
wire randomReady;
wire [63:0] randomValue;
integer i;
integer failures;
reg [63:0] testVector [0:99];
reg [63:0] testValue;
always #1 clk = ~clk;
initial begin
seed = {64'd2, 64'd1};
clk = 1'b0;
rst = 1'b1;
seedStrobe = 1'b0;
read = 1'b0;
#11 rst = 1'b0;
$readmemh("./math/test/testVector.txt", testVector);
@(posedge clk) seedStrobe = 1'b0;
@(posedge clk) seedStrobe = 1'b1;
@(posedge clk) seedStrobe = 1'b0;
@(posedge clk) seedStrobe = 1'b0;
failures = 0;
for (i=0; i<100; i=i+1) begin
wait(randomReady);
read = 1'b1;
testValue = testVector[i];
if (testValue != randomValue) failures = failures + 1;
@(posedge clk) read = 1'b1;
@(posedge clk) read = 1'b1;
end
if (failures == 0) begin
$display("PASSED");
end
else begin
$display("FAILED");
$display("Failures: %d / 100", failures);
end
$stop();
end
XorShift128Plus uut (
.clk(clk),
.rst(rst),
.seed(seed), ///< [127:0]
.seedStrobe(seedStrobe),
.read(read),
.randomReady(randomReady),
.randomValue(randomValue) ///< [63:0]
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int t[40008]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m, k, l, p; cin >> n; string s; map<string, string> ex; map<string, int> kol; map<string, int> wh; for (int u = 1; u <= n; u++) { cin >> s; for (int i = 0; i < s.length(); i++) { string q; for (int j = i; j < s.length(); j++) { q += s[j]; if (wh[q] == u) continue; if (kol[q] == 0) { ex[q] = s; } wh[q] = u; kol[q]++; } } } int kk; cin >> kk; for (int i = 0; i < kk; i++) { string s; cin >> s; int kko = kol[s]; cout << kko << ; if (kko == 0) { cout << - n ; } else { cout << ex[s] << n ; } } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05.10.2017 12:13:15
// Design Name:
// Module Name: control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control(Saltoincond,instru,clk,RegDest,SaltoCond,LeerMem,MemaReg,ALUOp,EscrMem,FuenteALU,EscrReg);
input [5:0]instru;
input clk;
output wire RegDest;
output wire SaltoCond;
output wire LeerMem;
output wire MemaReg;
output wire [1:0]ALUOp;
output wire EscrMem;
output wire FuenteALU;
output wire EscrReg;
output wire Saltoincond;
reg [9:0]aux;
always @ (*)
begin
case(instru)
6'b000_000: aux=10'b0100_100_010;
6'b100_011: aux=10'b00_1111_0000;//lectura
6'b101_011: aux=10'b0x1x001000;//carga
6'b000_100: aux=10'b0x0x000101;
6'b111_111: aux=10'b00_1010_0000;//not
6'b111_110: aux=10'b00_0000_0101;
default: aux=10'b00_1010_0000;
endcase
end
assign Saltoincond = aux[9];
assign RegDest = aux[8];
assign FuenteALU = aux[7];//
assign MemaReg = aux[6];
assign EscrReg = aux[5];
assign LeerMem = aux[4];//
assign EscrMem = aux[3];
assign SaltoCond = aux[2];
assign ALUOp = aux[1:0];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
// /___/ /\ Filename : SRL16E.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 05/07/08 - 468872 - Add negative setup/hold support
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 04/16/13 - 683925 - add invertible pin support.
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module SRL16E #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT = 16'h0000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
`ifdef XIL_TIMING
wire CE_dly;
wire CLK_dly;
wire D_dly;
`endif
reg [15:0] data = INIT;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
`ifdef XIL_TIMING
while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`else
while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`endif
deassign data;
end
`ifdef XIL_TIMING
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK_dly) begin
if (CE_dly == 1'b1 || CE_dly === 1'bz) begin // rv 1
data[15:0] <= {data[14:0], D_dly};
end
end
end else begin : generate_block1
always @(negedge CLK_dly) begin
if (CE_dly == 1'b1 || CE_dly === 1'bz) begin //rv 1
data[15:0] <= {data[14:0], D_dly};
end
end
end
endgenerate
`else
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK) begin
if (CE == 1'b1 || CE === 1'bz) begin //rv 1
data[15:0] <= {data[14:0], D};
end
end
end else begin : generate_block1
always @(negedge CLK) begin
if (CE == 1'b1 || CE === 1'bz) begin //rv 1
data[15:0] <= {data[14:0], D};
end
end
end
endgenerate
`endif
assign Q = data[{A3, A2, A1, A0}];
`ifdef XIL_TIMING
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_ce_clk_en_p;
wire sh_ce_clk_en_n;
always @(notifier)
data[0] = 1'bx;
assign sh_clk_en_p = ~IS_CLK_INVERTED;
assign sh_clk_en_n = IS_CLK_INVERTED;
assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED;
assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED;
`endif
specify
(A0 => Q) = (0:0:0, 0:0:0);
(A1 => Q) = (0:0:0, 0:0:0);
(A2 => Q) = (0:0:0, 0:0:0);
(A3 => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
`include "defines.v"
module serialcontrol(
input wire clk25,
input wire rst,
//Input
//Control from MMU
input wire[2:0] ramOp_i,
input wire mode_i, /* 0: data; 1: control */
input wire[7:0] storeData_i,
//Output
//Data to MMU
output wire[31:0] ramData_o,
//Interrupt
output wire serialInt_o,
//Physical circuit
input wire RxD,
output wire TxD
);
reg[7:0] buffer[0:15];
reg[3:0] readPos;
reg[3:0] recvPos;
wire data_ready;
wire[7:0] data_receive;
wire write_busy;
reg[7:0] ramData;
wire[3:0] nextRecvPos = (recvPos == 15) ? 0 : recvPos + 1;
wire[3:0] nextReadPos = (readPos == 15) ? 0 : readPos + 1;
wire bufferEmpty = (recvPos == readPos);
wire serialRead = (ramOp_i == `MEM_LW_OP && mode_i == 0);
wire serialWrite = (ramOp_i == `MEM_SW_OP && mode_i == 0);
wire[7:0] controlData = {6'h0, ~bufferEmpty, ~write_busy};
assign ramData_o = {24'h0, mode_i ? controlData : ramData};
assign serialInt_o = data_ready | !bufferEmpty;
//Simulation
always @(posedge clk25) begin
if (serialWrite) begin
$write("%c", storeData_i);
end
end
//Receive buffer
always @(posedge clk25) begin
if (rst == `Enable) begin
buffer[0] <= `ZeroByte;
buffer[1] <= `ZeroByte;
buffer[2] <= `ZeroByte;
buffer[3] <= `ZeroByte;
buffer[4] <= `ZeroByte;
buffer[5] <= `ZeroByte;
buffer[6] <= `ZeroByte;
buffer[7] <= `ZeroByte;
buffer[8] <= `ZeroByte;
buffer[9] <= `ZeroByte;
buffer[10] <= `ZeroByte;
buffer[11] <= `ZeroByte;
buffer[12] <= `ZeroByte;
buffer[13] <= `ZeroByte;
buffer[14] <= `ZeroByte;
buffer[15] <= `ZeroByte;
end else if (data_ready == `Enable) begin
buffer[recvPos] <= data_receive;
end
end
//Receive pointer
always @(posedge clk25) begin
if (rst == `Enable) begin
recvPos <= 0;
end else if (data_ready == `Enable) begin
recvPos <= nextRecvPos;
end
end
//Read pointer
always @(posedge clk25) begin
if (rst == `Enable) begin
readPos <= 0;
end else if (serialRead && !bufferEmpty) begin
readPos <= nextReadPos;
end
end
//Data output
always @(*) begin
//Data
ramData = `ZeroByte;
if (serialRead) begin
if (!bufferEmpty) begin
ramData = buffer[readPos];
end else if (data_ready) begin //Bypass
ramData = data_receive;
end
end
end
localparam clkFrequency = 12500000; //Clock frequency: 25MHz
// localparam clkFrequency = ;
localparam baudRate = 115200; //Baud Rate: 115.2KHz
//Transmitter
async_transmitter #(.ClkFrequency(clkFrequency), .Baud(baudRate)) transmitter(
.clk(clk25),
.TxD_start(serialWrite && !write_busy),
.TxD_data(storeData_i),
.TxD(TxD),
.TxD_busy(write_busy)
);
//Receiver
async_receiver #(.ClkFrequency(clkFrequency), .Baud(baudRate)) receiver(
.clk(clk25),
.RxD(RxD),
.RxD_data_ready(data_ready),
.RxD_data(data_receive)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp(int a, int b) { if ((a == 1 && b == 1) || b == 0) return 0; return dp(max(b + 1, a - 2), min(b + 1, a - 2)) + 1; } int main() { int n, m; cin >> n >> m; printf( %d , dp(max(n, m), min(n, m))); } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; int n, num[100], cnt[N]; long long a[N]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { long long temp = a[i]; while (temp && temp % 2 == 0) { cnt[i]++; temp /= 2; } num[cnt[i]]++; } int id = 0; for (int i = 1; i <= 63; i++) if (num[i] > num[id]) id = i; cout << n - num[id] << endl; for (int i = 1; i <= n; i++) if (cnt[i] != id) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct pkt { int x, y; }; int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; vector<string> p(n); for (int i = 0; i < n; ++i) cin >> p[i]; vector<vector<int> > a(n, vector<int>(m, -1)); for (int k = 0; k < n; ++k) { for (int l = 1; l < m; ++l) { if (p[k][l - 1] != . ) a[k][l] = l - 1; else a[k][l] = a[k][l - 1]; } } vector<vector<int> > b(n, vector<int>(m, -1)); for (int k = 0; k < n; ++k) { for (int l = m - 2; l >= 0; --l) { if (p[k][l + 1] != . ) b[k][l] = l + 1; else b[k][l] = b[k][l + 1]; } } vector<vector<int> > c(n, vector<int>(m, -1)); for (int l = 0; l < m; ++l) { for (int k = 1; k < n; ++k) { if (p[k - 1][l] != . ) c[k][l] = k - 1; else c[k][l] = c[k - 1][l]; } } vector<vector<int> > d(n, vector<int>(m, -1)); for (int l = 0; l < m; ++l) { for (int k = n - 2; k >= 0; --k) { if (p[k + 1][l] != . ) d[k][l] = k + 1; else d[k][l] = d[k + 1][l]; } } vector<vector<int> > L, P, G, D; L = a; P = b; G = c; D = d; int odp = 0, il = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (p[i][j] == . ) continue; int dl = 1; pkt akt = {i, j}; vector<pkt> z; while (true) { pkt nast; if (p[akt.x][akt.y] == L ) nast = {akt.x, L[akt.x][akt.y]}; else { if (p[akt.x][akt.y] == R ) nast = {akt.x, P[akt.x][akt.y]}; else { if (p[akt.x][akt.y] == U ) nast = {G[akt.x][akt.y], akt.y}; else { if (p[akt.x][akt.y] == D ) nast = {D[akt.x][akt.y], akt.y}; } } } if (nast.x == -1 || nast.y == -1) break; ++dl; pkt le = {akt.x, L[akt.x][akt.y]}; pkt pr = {akt.x, P[akt.x][akt.y]}; if (le.x != -1 && le.y != -1) P[le.x][le.y] = pr.y; if (pr.x != -1 && pr.y != -1) L[pr.x][pr.y] = le.y; pkt go = {G[akt.x][akt.y], akt.y}; pkt dol = {D[akt.x][akt.y], akt.y}; if (dol.x != -1 && dol.y != -1) G[dol.x][dol.y] = go.x; if (go.x != -1 && go.y != -1) D[go.x][go.y] = dol.x; akt = nast; z.push_back(le); z.push_back(pr); z.push_back(go); z.push_back(dol); } if (dl > odp) { odp = dl; il = 1; } else { if (dl == odp) ++il; } for (int k = 0; k < z.size(); ++k) { if (z[k].x == -1 || z[k].y == -1) continue; L[z[k].x][z[k].y] = a[z[k].x][z[k].y]; P[z[k].x][z[k].y] = b[z[k].x][z[k].y]; G[z[k].x][z[k].y] = c[z[k].x][z[k].y]; D[z[k].x][z[k].y] = d[z[k].x][z[k].y]; } } } cout << odp << << il; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, arr[206]; char str[206]; inline bool check1() { for (int i = 0; i < (n >> 1); ++i) { if (arr[i] >= arr[i + (n >> 1)]) return 0; } return 1; } inline bool check2() { for (int i = 0; i < (n >> 1); ++i) { if (arr[i] <= arr[i + (n >> 1)]) return 0; } return 1; } int main() { scanf( %d , &n); scanf( %s , str); n = strlen(str); for (int i = 0; i < n; ++i) arr[i] = (int)(str[i] - 0 ); sort(arr, arr + (n / 2)); sort(arr + (n / 2), arr + n); puts((check1() || check2()) ? YES : NO ); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eca_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eca_e.v,v 1.1 2004/04/06 10:50:28 wig Exp $
// $Date: 2004/04/06 10:50:28 $
// $Log: inst_eca_e.v,v $
// Revision 1.1 2004/04/06 10:50:28 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eca_e
//
// No `defines in this module
module inst_eca_e
//
// Generated module inst_eca
//
(
nreset,
nreset_s,
v_select
);
// Generated Module Inputs:
input nreset;
input nreset_s;
input [5:0] v_select;
// Generated Wires:
wire nreset;
wire nreset_s;
wire [5:0] v_select;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eca_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:00 04/23/2015
// Design Name:
// Module Name: modBigNumbers
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module modBigNumbers(input reset, input clk, input [63:0] exponent, input [31:0] number,
output reg [31:0] result, output reg isDone
);
reg [31:0] nextResult;
reg [31:0] dividend;
reg nextIsDone;
reg [12:0] bitIndex;
reg [12:0] nextBitIndex;
reg [31:0] nextDividend;
wire [31:0] remainder;
wire [31:0] quotient;
wire [31:0] memMod;
wire rfd;
initial begin
nextIsDone = 0;
isDone = 0;
bitIndex = 0;
nextBitIndex = 0;
dividend = 1;
nextDividend = 1;
result = 0;
nextResult = 0;
end
div_gen_v3_0 dviderModule (.clk(clk),.rfd(rfd),.dividend(dividend),.divisor(number), .quotient(quotient), .fractional(remainder));
always @(posedge clk) begin
result <= nextResult;
isDone <= nextIsDone;
bitIndex <= nextBitIndex;
dividend <= nextDividend;
end
always @(*) begin
if (rfd == 1) begin
nextBitIndex = bitIndex < 64 ? bitIndex + 1 : bitIndex;
if (bitIndex == 64) begin
if (reset == 1) begin
nextIsDone = 0;
nextBitIndex = 0;
nextDividend = 1;
nextResult = 0;
end
else begin
nextIsDone = 1;
nextDividend = dividend;
nextResult = remainder;
end
end
else begin
nextResult = result;
nextIsDone = 0;
if (exponent[bitIndex] == 1) begin
nextDividend = remainder * memMod;
end
else begin
nextDividend = dividend;
end
end
end
else begin
nextBitIndex = bitIndex;
nextDividend = dividend;
nextResult = result;
nextIsDone = isDone;
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
module transmision (input enable,
input wire [7:0] dout,
output busy,
output reg done,
input wire clk_div,
output reg tx);
parameter count = 8;
initial begin
tx <= 1'b1;
done=0;
end
parameter STATE_IDLE = 2'b00;
parameter STATE_START = 2'b01;
parameter STATE_DATA = 2'b10;
parameter STATE_STOP = 2'b11;
reg [7:0] data = 8'b11111111;
reg [2:0] bitpos = 0;
reg [1:0] state = STATE_IDLE;
always @(posedge clk_div) begin
case (state)
STATE_IDLE: begin
done<=0;
tx <= 1'b1;
if(enable)begin
state <= STATE_START;
data <= dout;
bitpos <= 0;
end
end
STATE_START: begin
tx <= 1'b0;
state <= STATE_DATA;
end
STATE_DATA: begin
if (bitpos == count-1)begin
tx<=data[bitpos];
state <= STATE_STOP;
end
else begin
tx<=data[bitpos];
bitpos <= bitpos + 1;
end
end
STATE_STOP: begin
tx <= 1'b1;
done<=1;
state <= STATE_IDLE;
end
default: begin
tx <= 1'b1;
state <= STATE_IDLE;
end
endcase
end
assign busy = (state != STATE_IDLE);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ll N, M; cin >> N >> M; if (N > M) swap(N, M); ll rem = 0; if (N == 1) { rem = min(M % 6, 6 - M % 6); } else { if (N % 2 == 1 && M % 2 == 1) { rem = 1; } else { if (M == 2) { rem = 4; } else if (M == 3 || M == 7) { rem = 2; } else { rem = 0; } } } cout << N * M - rem << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_PP_BLACKBOX_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// AD9510 Register Map (from datasheet Rev. A)
/* INSTRUCTION word format (16 bits)
* 15 Read = 1, Write = 0
* 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream
* 12:0 Address
*/
/* ADDR Contents Value (hex)
* 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate
* 04 A Counter
* 05-06 B Counter
* 07-0A PLL Control
* 0B-0C R Divider
* 0D PLL Control
* 34-3A Fine Delay
* 3C-3F LVPECL Outs
* 40-43 LVDS/CMOS Outs
* 45 Clock select, power down
* 48-57 Dividers
* 58 Func and Sync
* 5A Update regs
*/
module spi
(input reset,
input clk,
// SPI signals
output sen,
output sclk,
input sdi,
output sdo,
// Interfaces
input read_1,
input write_1,
input [15:0] command_1,
input [15:0] wdata_1,
output [15:0] rdata_1,
output reg done_1,
input msb_first_1,
input [5:0] command_width_1,
input [5:0] data_width_1,
input [7:0] clkdiv_1
);
reg [15:0] command, wdata, rdata;
reg done;
always @(posedge clk)
if(reset)
done_1 <= #1 1'b0;
always @(posedge clk)
if(reset)
begin
counter <= #1 7'd0;
command <= #1 20'd0;
end
else if(start)
begin
counter <= #1 7'd1;
command <= #1 {read,w,addr_data};
end
else if( |counter && ~done )
begin
counter <= #1 counter + 7'd1;
if(~counter[0])
command <= {command[22:0],1'b0};
end
wire done = (counter == 8'd49);
assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything
assign sclk = ~counter[0];
assign sdo = command[23];
endmodule // clock_control
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const long long Inf = 1e18; const int N = 2e6 + 10; const int mod = 1e9 + 7; int gi() { int x = 0, o = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } template <typename T> bool chkmax(T &a, T b) { return a < b ? a = b, 1 : 0; }; template <typename T> bool chkmin(T &a, T b) { return a > b ? a = b, 1 : 0; }; int add(int a, int b) { return a + b >= mod ? a + b - mod : a + b; } int sub(int a, int b) { return a - b < 0 ? a - b + mod : a - b; } void inc(int &a, int b) { a = (a + b >= mod ? a + b - mod : a + b); } void dec(int &a, int b) { a = (a - b < 0 ? a - b + mod : a - b); } int n, p[N], a[N], pw[N], cnt[N]; int pri[N], tot = 0, d[N]; bool vis[N]; void init() { const int n = 2e6; for (int i = 2; i <= n; i++) { if (!vis[i]) pri[++tot] = i, d[i] = i; for (int j = 1; j <= tot && i * pri[j] <= n; j++) { vis[i * pri[j]] = 1; d[i * pri[j]] = pri[j]; if (i % pri[j] == 0) break; } } } int qpow(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % mod; a = 1ll * a * a % mod; b >>= 1; } return ret; } int main() { init(); cin >> n; for (int i = 1; i <= n; i++) p[i] = gi(); sort(p + 1, p + n + 1); for (int i = n; i; i--) { if (!pw[p[i]]) pw[p[i]] = cnt[p[i]] = 1, a[i] = p[i]; else { int x = p[i] - 1; a[i] = p[i] - 1; while (x > 1) { int y = d[x], sum = 0; while (x % y == 0) x /= y, sum++; if (pw[y] < sum) pw[y] = sum, cnt[y] = 1; else if (pw[y] == sum) cnt[y]++; } } } int tag = 0; for (int i = n; i; i--) { int x = a[i], fl = 1; while (x > 1) { int y = d[x], sum = 0; while (x % y == 0) x /= y, sum++; if (sum == pw[y] && cnt[y] == 1) fl = 0; } tag |= fl; } int ans = 1; for (int i = 2; i <= 2000000; i++) ans = 1ll * ans * qpow(i, pw[i]) % mod; printf( %d n , add(ans, tag)); return 0; } |
module ER_CDE_Handler(ER_CDE, clk, HEX0, HEX1, HEX2, HEX3, HEX1DP);
input[7:0] ER_CDE;
input clk;
output reg[6:0] HEX0, HEX1, HEX2, HEX3;
output reg HEX1DP;
always @(posedge clk) begin
case (ER_CDE[7:0])
8'b00000000: begin //No Error
HEX0 = 7'b0000000;
HEX1 = 7'b0000000;
HEX2 = 7'b0000000;
HEX3 = 7'b0000000;
HEX1DP = 1'b0; end
8'b00000001: begin //Tried to load in stack range
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b0000110;
HEX1DP = 1'b1; end
8'b00000010: begin //Tried to store in stack range
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1011011;
HEX1DP = 1'b1; end
8'b00000011: begin //Tried to PUSH full stack (overflow)
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1001111;
HEX1DP = 1'b1; end
8'b00000100: begin //Tried to POP empty stack
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1100110;
HEX1DP = 1'b1; end
8'b00000101: begin //Tried to Return PC with empty stack
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1101101;
HEX1DP = 1'b1; end
8'b00000110: begin //Tried to Call with full stack
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1111101;
HEX1DP = 1'b1; end
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int SIGMA_SIZE = 26; const int MAXNODE = 1000010; struct AhoCorasickAutomata { int ch[MAXNODE][SIGMA_SIZE]; int f[MAXNODE]; int match[MAXNODE]; int mp[MAXNODE]; int sz; void init() { sz = 1; } int idx(char c) { if (c <= z && c >= a ) return c - a ; else return 0; } void insert(char *s, int v) { int u = 0, n = strlen(s); for (int i = 0; i < n; i++) { int c = idx(s[i]); if (!ch[u][c]) { ch[u][c] = sz++; } u = ch[u][c]; } match[u] = 1; mp[v] = u; } void getFail() { queue<int> q; f[0] = 0; for (int c = 0; c < SIGMA_SIZE; c++) { int u = ch[0][c]; if (u) { f[u] = 0; q.push(u); } } while (!q.empty()) { int r = q.front(); q.pop(); for (int c = 0; c < SIGMA_SIZE; c++) { int u = ch[r][c]; if (!u) { ch[r][c] = ch[f[r]][c]; continue; } q.push(u); int v = f[r]; while (v && !ch[v][c]) v = f[v]; f[u] = ch[v][c]; } } } }; AhoCorasickAutomata ac; vector<int> edge[MAXNODE]; char str[MAXNODE]; bool flag[MAXNODE]; int L[MAXNODE]; int R[MAXNODE]; int tot; struct node { int l, r; }; struct Segtree { int add[MAXNODE << 2], sum[MAXNODE << 2]; node seg[MAXNODE << 2]; void build(int o, int l, int r) { seg[o].l = l, seg[o].r = r; if (l == r) return; int m = (l + r) >> 1; build(o << 1, l, m); build(o << 1 | 1, m + 1, r); } void pushdown(int o) { if (add[o]) { int len = seg[o].r - seg[o].l + 1; add[o << 1] += add[o]; add[o << 1 | 1] += add[o]; sum[o << 1] += add[o] * (seg[o << 1].r - seg[o << 1].l + 1); sum[o << 1 | 1] += add[o] * (seg[o << 1 | 1].r - seg[o << 1 | 1].l + 1); add[o] = 0; } } void pushup(int o) { sum[o] = sum[o << 1] + sum[o << 1 | 1]; } void update(int o, int l, int r, int val) { if (l <= seg[o].l && seg[o].r <= r) { add[o] += val; sum[o] += val; return; } pushdown(o); int m = (seg[o].l + seg[o].r) >> 1; if (l <= m) update(o << 1, l, r, val); if (r > m) update(o << 1 | 1, l, r, val); pushup(o); } int query(int o, int pos) { if (seg[o].l == seg[o].r) return sum[o]; pushdown(o); int m = (seg[o].l + seg[o].r) >> 1; if (pos <= m) return query(o << 1, pos); if (pos > m) return query(o << 1 | 1, pos); } } tree; void dfs(int u) { L[u] = ++tot; for (int i = 0; i < edge[u].size(); i++) { int v = edge[u][i]; dfs(v); } R[u] = tot; } int main() { ios::sync_with_stdio(false); int n, k; while (cin >> n >> k) { ac.init(); for (int i = 0; i < k; i++) { cin >> str; ac.insert(str, i + 1); } ac.getFail(); memset(flag, 1, sizeof(flag)); for (int i = 1; i <= ac.sz; i++) edge[ac.f[i]].push_back(i); dfs(0); tree.build(1, 1, ac.sz); for (int i = 1; i <= ac.sz; i++) { if (ac.match[i]) { tree.update(1, L[i], R[i], 1); } } while (n--) { cin >> str; int len = strlen(str); if (str[0] == ? ) { int u = 0, ans = 0; for (int i = 1; i < len; i++) { int c = ac.idx(str[i]); u = ac.ch[u][c]; ans += tree.query(1, L[u]); } cout << ans << endl; } if (str[0] == + ) { int num = 0; for (int i = 1; i < len; i++) { num = num * 10 + str[i] - 0 ; } if (flag[num]) continue; flag[num] = 1; tree.update(1, L[ac.mp[num]], R[ac.mp[num]], 1); } if (str[0] == - ) { int num = 0; for (int i = 1; i < len; i++) { num = num * 10 + str[i] - 0 ; } if (!flag[num]) continue; flag[num] = 0; tree.update(1, L[ac.mp[num]], R[ac.mp[num]], -1); } } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s, sum = 0, big; cin >> n >> s; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } sort(arr, arr + n); big = arr[n - 1]; if (sum - big <= s) cout << YES ; else cout << NO ; return 0; } |
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Receiver for RPC network, protocol version 3
This module expects OUT_DATA_WIDTH to be equal to IN_DATA_WIDTH.
Network-side interface is standard RPCv3
Router-side interface is a FIFO.
space_available Asserted by router if it has at least one *packet* worth of buffer space.
packet_start Asserted by transceiver for one clock at start of message.
Asserted concurrently with first assertion of data_valid.
data_valid Asserted by transceiver if data should be processed.
Will be asserted constantly between packet_start and packet_done.
data One word of message data.
packet_done Asserted by transceiver for one clock at end of message.
Concurrent with last assertion of data_valid.
RESOURCE USAGE (XST A7 rough estimate)
Width FF LUT Slice
16 22 7 7
32 37 5 10
64 68 3 20
128 131 30 28
*/
module RPCv3RouterReceiver_buffering
#(
//Data width (must be one of 16, 32, 64, 128).
parameter OUT_DATA_WIDTH = 16,
parameter IN_DATA_WIDTH = 16
)
(
//Interface clock
input wire clk,
//Network interface, inbound side
input wire rpc_rx_en,
input wire[IN_DATA_WIDTH-1:0] rpc_rx_data,
output reg rpc_rx_ready = 0,
//Router interface, outbound side
input wire rpc_fab_rx_space_available,
output wire rpc_fab_rx_packet_start,
output reg rpc_fab_rx_data_valid = 0,
output reg[OUT_DATA_WIDTH-1:0] rpc_fab_rx_data = 0,
output reg rpc_fab_rx_packet_done = 0
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Synthesis-time sanity checking
initial begin
case(IN_DATA_WIDTH)
16: begin
end
32: begin
end
64: begin
end
128: begin
end
default: begin
$display("ERROR: RPCv3RouterReceiver_buffering IN_DATA_WIDTH must be 16/32/64/128");
$finish;
end
endcase
case(OUT_DATA_WIDTH)
16: begin
end
32: begin
end
64: begin
end
128: begin
end
default: begin
$display("ERROR: RPCv3RouterReceiver_buffering OUT_DATA_WIDTH must be 16/32/64/128");
$finish;
end
endcase
if(IN_DATA_WIDTH != OUT_DATA_WIDTH) begin
$display("ERROR: RPCv3RouterReceiver_buffering IN_DATA_WIDTH must be equal to OUT_DATA_WIDTH");
$finish;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Compute some useful values
//Number of clocks it takes to receive a message
localparam MESSAGE_CYCLES = 128 / IN_DATA_WIDTH;
localparam MESSAGE_MAX = MESSAGE_CYCLES - 1;
//Number of bits we need in the cycle counter
`include "../../synth_helpers/clog2.vh"
localparam CYCLE_BITS = clog2(MESSAGE_CYCLES);
localparam CYCLE_MAX = CYCLE_BITS ? CYCLE_BITS-1 : 0;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Main RX logic
//True if we are in the first cycle of an incoming message
wire rx_starting = (rpc_rx_en && rpc_rx_ready);
assign rpc_fab_rx_packet_start = rx_starting;
//Position within the message (in IN_DATA_WIDTH-bit units)
reg[2:0] rx_count = 0;
//True if a receive is in progress
wire rx_active = (rx_count != 0) || rx_starting;
//Register the output because our formal testbench doesn't know how to handle a zero-cycle-delay receiver.
//TODO: improve testbench to handle this better and cut our area down by a few FFs
always @(posedge clk) begin
rpc_fab_rx_data_valid <= rx_active;
if(IN_DATA_WIDTH == 128)
rpc_fab_rx_packet_done <= rx_active;
else
rpc_fab_rx_packet_done <= (rx_count == MESSAGE_MAX);
rpc_fab_rx_data <= rpc_rx_data;
end
always @(posedge clk) begin
//Process incoming data words
if(rx_active) begin
//Update word count as we move through the message
if(rx_starting)
rx_count <= 1;
else
rx_count <= rx_count + 1'h1;
//When we hit the end of the message, stop
if(rx_count == MESSAGE_MAX)
rx_count <= 0;
end
end
//Ready to receive if the fabric side is ready.
//Once we go ready, go un-ready when a message comes in.
reg rpc_rx_ready_ff = 0;
always @(posedge clk) begin
if(rpc_rx_en)
rpc_rx_ready_ff <= 0;
if(rpc_fab_rx_space_available && !rx_active)
rpc_rx_ready_ff <= 1;
end
always @(*) begin
rpc_rx_ready <= rpc_rx_ready_ff;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; if (s.size() == 1) { int a = s[0] - 48; if (a % 4 == 0) cout << 4; else cout << 0; } else { int a = (s[s.size() - 2] - 48) * 10 + (s[s.size() - 1] - 48); if (a % 4 == 0) cout << 4; else cout << 0; } return 0; } |
#include <bits/stdc++.h> int main() { int s = 0, ar[5], t = 0; for (int i = 0; i < 5; ++i) { scanf( %d , &ar[i]); s += ar[i]; } if (s % 5 || s == 0) printf( -1 n ); else { for (int i = 0; i < 5; ++i) if (ar[i] % 2) ++t; if ((((s / 5) % 2) && (t == 1 || t == 3 || t == 5)) || (!((s / 5) % 2) && (t == 0 || t == 2 || t == 4))) printf( %d n , s / 5); else printf( -1 n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O31AI_BEHAVIORAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_BEHAVIORAL_PP_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module sig1dualRAM (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [13 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [7 : 0] doutb;
blk_mem_gen_v8_3_3 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("sig1dualRAM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(11520),
.C_READ_DEPTH_A(11520),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(11520),
.C_READ_DEPTH_B(11520),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("3"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.53475 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(8'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const long long mod = 1e9 + 7; long long a[200010]; int main() { long long n, k; cin >> n >> k; long long i; for (i = 1; i <= n; i++) scanf( %d , &a[i]); long long sum = 0; for (i = 1; i <= n; i++) { long long temp = min(i, n - i + 1); temp = min(temp, n - k + 1); temp = min(temp, k); sum += temp * a[i]; } double ans = double(sum) / (n - k + 1); printf( %.10lf , ans); } |
// fpgaTop_kc705.v - the top-level Verilog for the Xilinx KC705 board
// Copyright (c) 2011-2012 Atomic Rules LLC - ALL RIGHTS RESERVED
//
module fpgaTop (
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire sys0_rst, // sys0 Reset (active high)
input wire sys1_clkp, // sys1 Clock +
input wire sys1_clkn, // sys1 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [3:0] pci_exp_txp, // PCIe lanes...
output wire [3:0] pci_exp_txn,
input wire [3:0] pci_exp_rxp,
input wire [3:0] pci_exp_rxn,
//input wire ppsExtIn, // PPS in
//output wire ppsOut, // PPS out
//
input wire [ 7:0] usr_sw, // dip-switches
output wire [ 7:0] led, // leds
output wire [ 3:0] lcd_db, // LCD databus
output wire lcd_e, // LCD enable
output wire lcd_rs, // LCD register-select
output wire lcd_rw, // LCD read-not-write
output wire [15:0] debug, // debug
output wire gmii_rstn, // Alaska GMII...
output wire gmii_gtx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire mdio_mdc, // Alaska MDIO...
inout wire mdio_mdd
//output wire [23:0] flash_addr,
//inout wire [15:0] flash_io_dq,
//input wire flash_wait,
//output wire flash_we_n,
//output wire flash_oe_n,
//output wire flash_ce_n
//inout wire [63:0] ddr3_dq, // DDR3 DRAM...
//output wire [12:0] ddr3_addr,
//output wire [2:0] ddr3_ba,
//output wire ddr3_ras_n,
//output wire ddr3_cas_n,
//output wire ddr3_we_n,
//output wire ddr3_reset_n,
//output wire [0:0] ddr3_cs_n,
//output wire [0:0] ddr3_odt,
//output wire [0:0] ddr3_cke,
//output wire [7:0] ddr3_dm,
//inout wire [7:0] ddr3_dqs_p,
//inout wire [7:0] ddr3_dqs_n,
//output wire [0:0] ddr3_ck_p,
//output wire [0:0] ddr3_ck_n
//output wire flp_com_sclk, // FMC150 in LPC Slot...
//output wire flp_com_sdc2m,
//input wire flp_cdc_sdm2c,
//input wire flp_mon_sdm2c,
//input wire flp_adc_sdm2c,
//input wire flp_dac_sdm2c,
//output wire flp_cdc_sen_n,
//output wire flp_mon_sen_n,
//output wire flp_adc_sen_n,
//output wire flp_dac_sen_n,
//output wire flp_cdc_rstn,
//output wire flp_cdc_pdn,
//output wire flp_mon_rstn,
//output wire flp_mon_intn,
//output wire flp_adc_rstn
);
// Instance and connect mkFTop...
mkFTop_kc705 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.sys0_rstn (!sys0_rst), // Invert to make active-low
.sys1_clkp (sys1_clkp),
.sys1_clkn (sys1_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.lcd_db (lcd_db),
.lcd_e (lcd_e),
.lcd_rs (lcd_rs),
.lcd_rw (lcd_rw),
//.gps_ppsSyncIn_x (ppsExtIn),
//.gps_ppsSyncOut (ppsOut),
.usr_sw_i (usr_sw),
.debug (debug),
.gmii_rstn (gmii_rstn),
.gmii_tx_txd (gmii_txd),
.gmii_tx_tx_en (gmii_tx_en),
.gmii_tx_tx_er (gmii_tx_er),
.gmii_rx_rxd_i (gmii_rxd),
.gmii_rx_rx_dv_i (gmii_rx_dv),
.gmii_rx_rx_er_i (gmii_rx_er),
.gmii_tx_tx_clk (gmii_gtx_clk),
.gmii_rx_clk (gmii_rx_clk),
.mdio_mdc (mdio_mdc),
.mdio_mdd (mdio_mdd)
//.flash_addr (flash_addr),
//.flash_io_dq (flash_io_dq),
//.flash_fwait_i (flash_wait),
//.flash_we_n (flash_we_n),
//.flash_oe_n (flash_oe_n),
//.flash_ce_n (flash_ce_n)
//.dram_io_dq (ddr3_dq),
//.dram_addr (ddr3_addr),
//.dram_ba (ddr3_ba),
//.dram_ras_n (ddr3_ras_n),
//.dram_cas_n (ddr3_cas_n),
//.dram_we_n (ddr3_we_n),
//.dram_reset_n (ddr3_reset_n),
//.dram_cs_n (ddr3_cs_n),
//.dram_odt (ddr3_odt),
//.dram_cke (ddr3_cke),
//.dram_dm (ddr3_dm),
//.dram_io_dqs_p (ddr3_dqs_p),
//.dram_io_dqs_n (ddr3_dqs_n),
//.dram_ck_p (ddr3_ck_p),
//.dram_ck_n (ddr3_ck_n)
//.flp_com_sclk (flp_com_sclk),
//.flp_com_sdc2m (flp_com_sdc2m),
//.flp_cdc_sdm2c (flp_cdc_sdm2c),
//.flp_mon_sdm2c (flp_mon_sdm2c),
//.flp_adc_sdm2c (flp_adc_sdm2c),
//.flp_dac_sdm2c (flp_dac_sdm2c),
//.flp_cdc_sen_n (flp_cdc_sen_n),
//.flp_mon_sen_n (flp_mon_sen_n),
//.flp_adc_sen_n (flp_adc_sen_n),
//.flp_dac_sen_n (flp_dac_sen_n),
//.flp_cdc_rstn (flp_cdc_rstn),
//.flp_cdc_pdn (flp_cdc_pdn),
//.flp_mon_rstn (flp_mon_rstn),
//.flp_mon_intn (flp_mon_intn),
//.flp_adc_rstn (flp_adc_rstn)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: mask_to_zero
// Description: Selects active region from input data, bit reverses and masks LS
// bits to zero depending on the position of the leading zero identified
// by lzd.v
//////////////////////////////////////////////////////////////////////////////////
module mask_to_zero(
input clk,
input [14:0] data_in,
input [5:0] lz_pos,
output [14:0] data_out
);
wire [14:0] data_in_rev;
reg [14:0] data_in_r = 15'd0;
reg [14:0] data = 15'd0;
assign data_in_rev = {data_in[0], data_in[1], data_in[2], data_in[3], data_in[4],
data_in[5], data_in[6], data_in[7], data_in[8], data_in[9],
data_in[10], data_in[11], data_in[12], data_in[13], data_in[14]};
always @ (posedge clk) begin
data_in_r <= data_in_rev;
case (lz_pos)
6'd61: data <= data_in_r & 15'b111111111111111;
6'd60: data <= data_in_r & 15'b011111111111111;
6'd59: data <= data_in_r & 15'b101111111111111;
6'd58: data <= data_in_r & 15'b110111111111111;
6'd57: data <= data_in_r & 15'b111011111111111;
6'd56: data <= data_in_r & 15'b111101111111111;
6'd55: data <= data_in_r & 15'b111110111111111;
6'd54: data <= data_in_r & 15'b111111011111111;
6'd53: data <= data_in_r & 15'b111111101111111;
6'd52: data <= data_in_r & 15'b111111110111111;
6'd51: data <= data_in_r & 15'b111111111011111;
6'd50: data <= data_in_r & 15'b111111111101111;
6'd49: data <= data_in_r & 15'b111111111110111;
6'd48: data <= data_in_r & 15'b111111111111011;
6'd47: data <= data_in_r & 15'b111111111111101;
6'd46: data <= data_in_r & 15'b111111111111110;
default: data <= data_in_r & 15'b111111111111111;
endcase
end
assign data_out = data;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int N; while (cin >> N) { int Store[31][31], i, j, SumR, SumC, Count = 0; vector<int> Row, Col; memset(Store, false, sizeof(Store)); for (i = 0; i < N; i++) for (j = 0; j < N; j++) cin >> Store[i][j]; for (i = 0; i < N; i++) { SumR = 0; SumC = 0; for (j = 0; j < N; j++) { SumR += Store[i][j]; SumC += Store[j][i]; } Row.push_back(SumR); Col.push_back(SumC); } for (i = 0; i < N; i++) { for (j = 0; j < N; j++) { if (Row[i] < Col[j]) Count++; } } cout << Count << endl; } } |
#include <bits/stdc++.h> using namespace std; int gcd(int u, int v) { int tmp; while (v) { tmp = v; v = u % v; u = tmp; } return u; } int main() { int a, b, t; cin >> a >> b; if (a > b) { swap(a, b); } if ((t = gcd(a, b)) == 1) { cout << NO << endl; return 0; } int flag = 1; for (int i = 1; i <= t; i++) { for (int j = i; j <= t; j++) { if (t * t == i * i + j * j) { flag = 0; cout << YES << endl; cout << 0 0 << endl; cout << i * a / t << << -j * a / t << endl; cout << j * b / t << << i * b / t << endl; return 0; } } } if (flag) cout << NO << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_BLACKBOX_V
`define SKY130_FD_SC_HD__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %Version
// \ \ Application: MIG
// / / Filename: circ_buffer.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:02 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Circular Buffer for synchronizing signals between clock domains. Assumes
// write and read clocks are the same frequency (but can be varying phase).
// Parameter List;
// DATA_WIDTH: # bits in data bus
// BUF_DEPTH: # of entries in circular buffer.
// Port list:
// rdata: read data
// wdata: write data
// rclk: read clock
// wclk: write clock
// rst: reset - shared between read and write sides
//Reference:
//Revision History:
// Rev 1.1 - Initial Checkin - jlogue 03/06/09
//*****************************************************************************
/******************************************************************************
**$Id: circ_buffer.v,v 1.1 2011/06/02 07:18:02 mishra Exp $
**$Date: 2011/06/02 07:18:02 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/circ_buffer.v,v $
******************************************************************************/
`timescale 1ps/1ps
module circ_buffer #
(
parameter TCQ = 100,
parameter BUF_DEPTH = 5, // valid values are 5, 6, 7, and 8
parameter DATA_WIDTH = 1
)
(
output[DATA_WIDTH-1:0] rdata,
input [DATA_WIDTH-1:0] wdata,
input rclk,
input wclk,
input rst
);
//***************************************************************************
// Local parameters
//***************************************************************************
localparam SHFTR_MSB = (BUF_DEPTH-1)/2;
//***************************************************************************
// Internal signals
//***************************************************************************
reg SyncResetRd;
reg [SHFTR_MSB:0] RdCEshftr;
reg [2:0] RdAdrsCntr;
reg SyncResetWt;
reg WtAdrsCntr_ce;
reg [2:0] WtAdrsCntr;
//***************************************************************************
// read domain registers
//***************************************************************************
always @(posedge rclk or posedge rst)
if (rst) SyncResetRd <= #TCQ 1'b1;
else SyncResetRd <= #TCQ 1'b0;
always @(posedge rclk or posedge SyncResetRd)
begin
if (SyncResetRd)
begin
RdCEshftr <= #TCQ 'b0;
RdAdrsCntr <= #TCQ 'b0;
end
else
begin
RdCEshftr <= #TCQ {RdCEshftr[SHFTR_MSB-1:0], WtAdrsCntr_ce};
if(RdCEshftr[SHFTR_MSB])
begin
if(RdAdrsCntr == (BUF_DEPTH-1)) RdAdrsCntr <= #TCQ 'b0;
else RdAdrsCntr <= #TCQ RdAdrsCntr + 1;
end
end
end
//***************************************************************************
// write domain registers
//***************************************************************************
always @(posedge wclk or posedge SyncResetRd)
if (SyncResetRd) SyncResetWt <= #TCQ 1'b1;
else SyncResetWt <= #TCQ 1'b0;
always @(posedge wclk or posedge SyncResetWt)
begin
if (SyncResetWt)
begin
WtAdrsCntr_ce <= #TCQ 1'b0;
WtAdrsCntr <= #TCQ 'b0;
end
else
begin
WtAdrsCntr_ce <= #TCQ 1'b1;
if(WtAdrsCntr_ce)
begin
if(WtAdrsCntr == (BUF_DEPTH-1)) WtAdrsCntr <= #TCQ 'b0;
else WtAdrsCntr <= #TCQ WtAdrsCntr + 1;
end
end
end
//***************************************************************************
// instantiate one RAM64X1D for each data bit
//***************************************************************************
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i = i+1) begin: gen_ram
RAM64X1D #
(
.INIT (64'h0000000000000000)
)
u_RAM64X1D
(.DPO (rdata[i]),
.SPO (),
.A0 (WtAdrsCntr[0]),
.A1 (WtAdrsCntr[1]),
.A2 (WtAdrsCntr[2]),
.A3 (1'b0),
.A4 (1'b0),
.A5 (1'b0),
.D (wdata[i]),
.DPRA0 (RdAdrsCntr[0]),
.DPRA1 (RdAdrsCntr[1]),
.DPRA2 (RdAdrsCntr[2]),
.DPRA3 (1'b0),
.DPRA4 (1'b0),
.DPRA5 (1'b0),
.WCLK (wclk),
.WE (1'b1)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int a[n], sum = 0; vector<int> v; vector<int> u; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; if (a[i] > 0) u.push_back(a[i]); else v.push_back(0 - a[i]); } if (sum > 0) cout << first ; else if (sum < 0) cout << second ; else { int f = 0, m = u.size(); if (m > v.size()) m = v.size(); for (int i = 0; i < m; i++) { if (v[i] < u[i]) { f = 1; break; } else if (v[i] > u[i]) { f = 2; break; } } if (!f) { if (u.size() > v.size()) f = 1; else if (u.size() < v.size()) f = 2; else { if (a[n - 1] > 0) f = 1; else f = 2; } } if (f == 1) cout << first ; else cout << second ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:32 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_gray_nxt;
reg [ASIZE:0] rd_gray;
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_gray;
reg [ASIZE:0] wr_gray_nxt;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
reg [ASIZE:0] wr_ptr, rd_ptr;
integer i,j,k;
// for design that use the same clock for both read and write
generate
if (SYNC == 1) begin: RDSYNC
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
end
endgenerate
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
generate
if (SYNC == 1) begin: WRSYNC
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
end
endgenerate
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr;
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
reg [ASIZE:0] rd_ptr_tmp;
// change the binary pointer to gray pointer
always @ (rd_ptr)
begin
// rd_gray_nxt[ASIZE] = rd_ptr_tmp[ASIZE];
// for (n=0; n < ASIZE; n=n+1)
// rd_gray_nxt[n] = rd_ptr_tmp[n] ^ rd_ptr_tmp[n+1];
rd_gray_nxt[ASIZE] = rd_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
rd_gray_nxt[n] = rd_ptr[n] ^ rd_ptr[n+1];
end
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_gray <= #TCQ 'b0;
end
else begin
if (rd_strobe)
rd_ptr <= #TCQ rd_ptr + 1;
rd_ptr_tmp <= #TCQ rd_ptr;
// change the binary pointer to gray pointer
rd_gray <= #TCQ rd_gray_nxt;
end
end
//generate empty signal
assign buf_filled = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
wr_gray <= #TCQ 'b0;
end
else begin
if (wr_en)
wr_ptr <= #TCQ wr_ptr + 1;
// change the binary pointer to gray pointer
wr_gray <= #TCQ wr_gray_nxt;
end
end
// change the write pointer to gray pointer
always @ (wr_ptr)
begin
wr_gray_nxt[ASIZE] = wr_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
wr_gray_nxt[n] = wr_ptr[n] ^ wr_ptr[n+1];
end
// calculate how many buf still available
assign buf_avail = (rd_capture_ptr + FIFO_DEPTH) - wr_ptr;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altpcierd_tx_ecrc_ctl_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Internal Build 134 08/15/2007 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcierd_tx_ecrc_ctl_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q);
input aclr;
input clock;
input [0:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [0:0] q;
wire sub_wire0;
wire sub_wire1;
wire [0:0] sub_wire2;
wire sub_wire3;
wire almost_full = sub_wire0;
wire empty = sub_wire1;
wire [0:0] q = sub_wire2[0:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.almost_empty (),
.sclr (),
.usedw ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 16,
scfifo_component.intended_device_family = "Stratix II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 1,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "16"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "16"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL data[0..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL q[0..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_tx_ecrc_ctl_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_4_V
`define SKY130_FD_SC_MS__O31A_4_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b, c; cin >> a >> b >> c; if (a[0] == c[2] && a[1] == c[1] && a[2] == c[0] && b[0] == b[2]) cout << YES << endl; else cout << NO << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_BEHAVIORAL_V
`define SKY130_FD_SC_HS__MUX4_BEHAVIORAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_4/sky130_fd_sc_hs__u_mux_4.v"
`celldefine
module sky130_fd_sc_hs__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
// Local signals
wire u_mux_40_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_4_2 u_mux_40 (u_mux_40_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_40_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BLACKBOX_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BLACKBOX_V
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_axi_spi_master_0_0 -prefix
// DemoInterconnect_axi_spi_master_0_0_ DemoInterconnect_axi_spi_master_0_0_stub.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
module DemoInterconnect_axi_spi_master_0_0(m_spi_mosi, m_spi_miso, m_spi_ss, m_spi_sclk,
s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata,
s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid,
s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready,
s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk,
s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="m_spi_mosi,m_spi_miso,m_spi_ss,m_spi_sclk,s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output m_spi_mosi;
input m_spi_miso;
output m_spi_ss;
output m_spi_sclk;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e3 + 5; const long long MOD = 1e9 + 7; long long nCr[N][N]; void precompute() { nCr[0][0] = 1; for (long long i = 1; i < N; i++) { nCr[i][0] = 1; for (long long j = 1; j <= i; j++) { nCr[i][j] = nCr[i - 1][j - 1] + nCr[i - 1][j]; nCr[i][j] %= MOD; } } } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; precompute(); long long n, m, k; cin >> n >> m >> k; long long ans = nCr[n - 1][2 * k] * nCr[m - 1][2 * k]; ans %= MOD; cout << ans; return 0; } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
module hf_compression (
input wire val_in,
output reg [3:0] hf_c,
output reg hf_c_valid,
input wire CLK,
input wire Reset
);
// parameter len = 4;
// The length of an uncompressed data amount
/* For constructing the Tree:
* the uncompressed length is 4
* that leaves 0 -> F
* Which is a total of 16 possibilities
* which means that the tree descriptor will need:
* The capacity to describe 16 possibilites
* which will need to say: this is 0, this is 1, this ....
* so any tree leaf will need 4 bits to describe the leaf's value
*/
// Because we have 16 symbols
// The worst case hf code length is 16 bits
// This can be reduced at the cost of compression
// Something like 6 - 8 might be an apropriate compromise
reg building_tree; // Building the tree
reg construct_tree; // Shifted in a page, construct a tree
reg import_tree; // tree constructed elsewhere, is being shifted in
reg [15:0] code;
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
end
else begin
end
end
reg [15:0] leaf_A_code;
reg [15:0] leaf_B_code;
reg [15:0] leaf_C_code;
reg [15:0] leaf_D_code;
reg [15:0] leaf_E_code;
reg [15:0] leaf_F_code;
reg [15:0] leaf_G_code;
reg [15:0] leaf_H_code;
reg [15:0] leaf_I_code;
reg [15:0] leaf_J_code;
reg [15:0] leaf_K_code;
reg [15:0] leaf_L_code;
reg [15:0] leaf_M_code;
reg [15:0] leaf_N_code;
reg [15:0] leaf_O_code;
reg [15:0] leaf_P_code;
reg [3:0] leaf_A_value;
reg [3:0] leaf_B_value;
reg [3:0] leaf_C_value;
reg [3:0] leaf_D_value;
reg [3:0] leaf_E_value;
reg [3:0] leaf_F_value;
reg [3:0] leaf_G_value;
reg [3:0] leaf_H_value;
reg [3:0] leaf_I_value;
reg [3:0] leaf_J_value;
reg [3:0] leaf_K_value;
reg [3:0] leaf_L_value;
reg [3:0] leaf_M_value;
reg [3:0] leaf_N_value;
reg [3:0] leaf_O_value;
reg [3:0] leaf_P_value;
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
leaf_A_code <= 16'b0;
leaf_B_code <= 16'b0;
leaf_C_code <= 16'b0;
leaf_D_code <= 16'b0;
leaf_E_code <= 16'b0;
leaf_F_code <= 16'b0;
leaf_G_code <= 16'b0;
leaf_H_code <= 16'b0;
leaf_I_code <= 16'b0;
leaf_J_code <= 16'b0;
leaf_K_code <= 16'b0;
leaf_L_code <= 16'b0;
leaf_M_code <= 16'b0;
leaf_N_code <= 16'b0;
leaf_O_code <= 16'b0;
leaf_P_code <= 16'b0;
leaf_A_value <= 4'b0;
leaf_B_value <= 4'b0;
leaf_C_value <= 4'b0;
leaf_D_value <= 4'b0;
leaf_E_value <= 4'b0;
leaf_F_value <= 4'b0;
leaf_G_value <= 4'b0;
leaf_H_value <= 4'b0;
leaf_I_value <= 4'b0;
leaf_J_value <= 4'b0;
leaf_K_value <= 4'b0;
leaf_L_value <= 4'b0;
leaf_M_value <= 4'b0;
leaf_N_value <= 4'b0;
leaf_O_value <= 4'b0;
leaf_P_value <= 4'b0;
end
else begin
if (building_tree) begin
end
else begin
leaf_A_code <= leaf_A_code;
leaf_B_code <= leaf_B_code;
leaf_C_code <= leaf_C_code;
leaf_D_code <= leaf_D_code;
leaf_E_code <= leaf_E_code;
leaf_F_code <= leaf_F_code;
leaf_G_code <= leaf_G_code;
leaf_H_code <= leaf_H_code;
leaf_I_code <= leaf_I_code;
leaf_J_code <= leaf_J_code;
leaf_K_code <= leaf_K_code;
leaf_L_code <= leaf_L_code;
leaf_M_code <= leaf_M_code;
leaf_N_code <= leaf_N_code;
leaf_O_code <= leaf_O_code;
leaf_P_code <= leaf_P_code;
leaf_A_value <= leaf_A_value;
leaf_B_value <= leaf_B_value;
leaf_C_value <= leaf_C_value;
leaf_D_value <= leaf_D_value;
leaf_E_value <= leaf_E_value;
leaf_F_value <= leaf_F_value;
leaf_G_value <= leaf_G_value;
leaf_H_value <= leaf_H_value;
leaf_I_value <= leaf_I_value;
leaf_J_value <= leaf_J_value;
leaf_K_value <= leaf_K_value;
leaf_L_value <= leaf_L_value;
leaf_M_value <= leaf_M_value;
leaf_N_value <= leaf_N_value;
leaf_O_value <= leaf_O_value;
leaf_P_value <= leaf_P_value;
end
end
end |
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
);
wire rst = ~rst_n; // make reset active high
wire [7:0] serial_data;
wire serial_new_data, tx_busy;
reg [7:0] tx_data_q, tx_data_d;
reg tx_new_data_q, tx_new_data_d;
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx), // FPGA tx goes to AVR rx
.rx(avr_tx),
.channel(4'd15), // invalid channel disables the ADC
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data_q),
.new_tx_data(tx_new_data_q),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(serial_data),
.new_rx_data(serial_new_data)
);
wire [31:0] rng_out;
xorshift rng (
.clk(clk),
.rst(rst),
.seed(128'h8de97cc56144a7eb653f6dee8b49b282), // From /dev/urandom, should be random.
.out(rng_out)
);
wire ready_to_read, best_distance_valid;
wire [31:0] best_distance;
wire [7:0] tsp_dbg;
tsp tsp(
.clk(clk),
.rst(rst),
.specdata(serial_data),
.has_specdata(serial_new_data),
.ready_to_read(ready_to_read),
.debug(tsp_dbg),
.best_distance(best_distance),
.best_distance_valid(best_distance_valid),
.rng(rng_out)
);
reg [31:0] printval_q, printval_d;
reg [27:0] cntdown_q, cntdown_d;
reg [4:0] digit_cnt_q, digit_cnt_d;
reg tx_hold_q, tx_hold_d;
always @(*) begin
tx_data_d = tx_data_q;
tx_new_data_d = 0;
printval_d = printval_q;
digit_cnt_d = digit_cnt_q;
tx_hold_d = 0;
cntdown_d = cntdown_q - 1;
if (serial_new_data) begin
if (serial_data == 114 && !tx_busy) begin
// Print the random value
if (digit_cnt_q == 0) begin
printval_d = rng_out;
digit_cnt_d = 8;
end
end else if (tx_busy || digit_cnt_q > 0 || !ready_to_read) begin
// We have to push this incoming character into the FIFO. But for now we ignore it.
end else begin
tx_data_d = serial_data;
tx_new_data_d = 1;
end
end
if (digit_cnt_q > 0 && !tx_busy && !tx_hold_q) begin
// Send the bottom 4 bits at a time
tx_new_data_d = 1;
if (printval_q[3:0] < 10) begin
tx_data_d = {4'b0,printval_q[3:0]} + 48;
end else begin
tx_data_d = {4'b0,printval_q[3:0]} + 87;
end
//tx_data_d = "a";
printval_d = printval_q >> 4;
digit_cnt_d = digit_cnt_q - 1;
tx_hold_d = 1;
end
if (best_distance_valid || cntdown_q == 0) begin
printval_d = best_distance;
digit_cnt_d = 8;
tx_data_d = "\r";
tx_new_data_d = 1;
cntdown_d = 100000000;
end
end
always @(posedge clk) begin
if (rst) begin
tx_new_data_q <= 0;
printval_q <= 0;
digit_cnt_q <= 0;
end else begin
tx_data_q <= tx_data_d;
tx_new_data_q <= tx_new_data_d;
printval_q <= printval_d;
digit_cnt_q <= digit_cnt_d;
tx_hold_q <= tx_hold_d;
cntdown_q <= cntdown_d;
end
end
assign led = best_distance[15:8];
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
//assign led = 8'b0;
endmodule |
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using vvi = vector<vi>; using ll = long long; using vll = vector<ll>; using vpi = vector<pair<int, int>>; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; int speedlim = 301; bool overtake = true; int speed = -1; int noovertakes = 0; vi speedsigns(302, 0); int ignore = 0; for (int i = 0; i < n; ++i) { int t; cin >> t; switch (t) { case 1: int newspeed; cin >> newspeed; assert(newspeed <= 300 && newspeed >= 1); if (newspeed > speed && newspeed > speedlim) { ignore += speedsigns[newspeed]; for (int i = newspeed + 1; i < speedsigns.size(); ++i) { speedsigns[i] -= speedsigns[newspeed]; } for (int i = 0; i <= newspeed; ++i) { speedsigns[i] = 0; } } speed = newspeed; break; case 2: if (!overtake) { ignore += noovertakes; noovertakes = 0; } break; case 3: int newspeedlim; cin >> newspeedlim; assert(newspeedlim <= 300 && newspeedlim >= 1); if (newspeedlim < speed) ++ignore; else { for (int i = 0; i <= newspeedlim; ++i) speedsigns[i] = 0; for (int i = newspeedlim + 1; i < speedsigns.size(); ++i) ++speedsigns[i]; } speedlim = newspeedlim; break; case 4: overtake = true; noovertakes = 0; break; case 5: speedlim = 301; for (int& si : speedsigns) si = 0; break; case 6: overtake = false; ++noovertakes; break; } } cout << ignore << n ; } |
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