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/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g_rgmii
*/
module test_eth_mac_1g_rgmii;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter USE_CLK90 = "TRUE";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg gtx_clk = 0;
reg gtx_clk90 = 0;
reg gtx_rst = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rgmii_rx_clk = 0;
reg [3:0] rgmii_rxd = 0;
reg rgmii_rx_ctl = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire rx_clk;
wire rx_rst;
wire tx_clk;
wire tx_rst;
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire rgmii_tx_clk;
wire [3:0] rgmii_txd;
wire rgmii_tx_ctl;
wire tx_error_underflow;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire [1:0] speed;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
gtx_clk,
gtx_clk90,
gtx_rst,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rgmii_rx_clk,
rgmii_rxd,
rgmii_rx_ctl,
ifg_delay
);
$to_myhdl(
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tready,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
rgmii_tx_clk,
rgmii_txd,
rgmii_tx_ctl,
tx_error_underflow,
rx_error_bad_frame,
rx_error_bad_fcs,
speed
);
// dump file
$dumpfile("test_eth_mac_1g_rgmii.lxt");
$dumpvars(0, test_eth_mac_1g_rgmii);
end
eth_mac_1g_rgmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.gtx_clk(gtx_clk),
.gtx_clk90(gtx_clk90),
.gtx_rst(gtx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(rgmii_rx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.speed(speed),
.ifg_delay(ifg_delay)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2B_PP_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; pair<int, pair<int, int> > A[2003 * 2003], B[2003 * 2003]; pair<int, int> a[2003], b[2003]; int m, n, r, s, x, y, i, j, asd; long long t1, t2, mn; bool h; int main() { cin >> m; for (i = 1; i <= m; i++) { cin >> a[i].first; t1 += a[i].first; a[i].second = i; } cin >> n; for (i = 1; i <= n; i++) { cin >> b[i].first; t2 += b[i].first; b[i].second = i; } for (i = 1; i <= m; i++) for (j = i + 1; j <= m; j++) A[++r] = make_pair(a[i].first + a[j].first, make_pair(i, j)); for (i = 1; i <= n; i++) for (j = i + 1; j <= n; j++) B[++s] = make_pair(b[i].first + b[j].first, make_pair(i, j)); sort(a + 1, a + m + 1); sort(b + 1, b + n + 1); sort(A + 1, A + r + 1); sort(B + 1, B + s + 1); if (t1 < t2) { h = 1; swap(t1, t2); swap(m, n); swap(r, s); swap(a, b); swap(A, B); } mn = t1 - t2; for (i = j = 1; i <= m; i++) { while (abs(t1 - a[i].first + b[j].first - (t2 - b[j].first + a[i].first)) > abs(t1 - a[i].first + b[j + 1].first - (t2 - b[j + 1].first + a[i].first)) && j < n) j++; if (mn > abs(t1 - a[i].first + b[j].first - (t2 - b[j].first + a[i].first))) { mn = abs(t1 - a[i].first + b[j].first - (t2 - b[j].first + a[i].first)); asd = 1; x = i; y = j; } } for (i = j = 1; i <= r && s; i++) { while (abs(t1 - A[i].first + B[j].first - (t2 - B[j].first + A[i].first)) > abs(t1 - A[i].first + B[j + 1].first - (t2 - B[j + 1].first + A[i].first)) && j < s) j++; if (mn > abs((t1 - A[i].first + B[j].first) - (t2 - B[j].first + A[i].first))) { mn = abs((t1 - A[i].first + B[j].first) - (t2 - B[j].first + A[i].first)); asd = 2; x = i; y = j; } } cout << mn << endl << asd << endl; if (asd == 1) { if (!h) cout << a[x].second << << b[y].second; else cout << b[y].second << << a[x].second; } else if (asd) { if (!h) { cout << A[x].second.first << << B[y].second.first << endl; cout << A[x].second.second << << B[y].second.second; } else { cout << B[y].second.first << << A[x].second.first << endl; cout << B[y].second.second << << A[x].second.second; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_TB_V
`define SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_TB_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_mux_2to1_n.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_hdll__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_TB_V
|
module adc_ltc2308(
clk, // max 40mhz
// start measure
measure_start, // posedge triggle
measure_ch,
measure_done,
measure_dataread,
// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);
input clk;
// start measure
input measure_start;
input [2:0] measure_ch;
output reg measure_done;
output [11:0] measure_dataread;
output ADC_CONVST;
output ADC_SCK;
output reg ADC_SDI;
input ADC_SDO;
/////////////////////////////////
// Timing definition
// using 40MHz clock
// to acheive fsample = 500KHz
// ntcyc = 2us / 25ns = 80
`define DATA_BITS_NUM 12
`define CMD_BITS_NUM 6
`define CH_NUM 8
`define tWHCONV 3 // CONVST High Time, min 20 ns
`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52
// set 64 for suite for 1.6 us max
// +12 //data
`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below
// If the source impedance of the driving circuit is low, the ADC inputs can be driven directly.
//Otherwise, more acquisition time should be allowed for a source with higher impedance.
// for acheiving 500KHz fmax. set n cyc = 80.
`define tCONVST_HIGH_START 0
`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV)
`define tCONFIG_START (`tCONVST_HIGH_END)
`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1)
`define tCLK_START (`tCONVST_HIGH_START+`tCONV)
`define tCLK_END (`tCLK_START+`DATA_BITS_NUM)
`define tDONE (`tCLK_END+`tHCONVST)
// create triggle message: reset_n
reg pre_measure_start;
always @ (posedge clk)
begin
pre_measure_start <= measure_start;
end
wire reset_n;
assign reset_n = (~pre_measure_start & measure_start)?1'b0:1'b1;
// tick
reg [15:0] tick;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
tick <= 0;
else if (tick < `tDONE)
tick <= tick + 1;
end
/////////////////////////////////
// ADC_CONVST
assign ADC_CONVST = (tick >= `tCONVST_HIGH_START && tick < `tCONVST_HIGH_END)?1'b1:1'b0;
/////////////////////////////////
// ADC_SCK
reg clk_enable; // must sync to clk in clk low
always @ (negedge clk or negedge reset_n)
begin
if (~reset_n)
clk_enable <= 1'b0;
else if ((tick >= `tCLK_START && tick < `tCLK_END))
clk_enable <= 1'b1;
else
clk_enable <= 1'b0;
end
assign ADC_SCK = clk_enable?clk:1'b0;
///////////////////////////////
// read data
reg [(`DATA_BITS_NUM-1):0] read_data;
reg [3:0] write_pos;
assign measure_dataread = read_data;
always @ (negedge clk or negedge reset_n)
begin
if (~reset_n)
begin
read_data <= 0;
write_pos <= `DATA_BITS_NUM-1;
end
else if (clk_enable)
begin
read_data[write_pos] <= ADC_SDO;
write_pos <= write_pos - 1;
end
end
///////////////////////////////
// measure done
wire read_ch_done;
assign read_ch_done = (tick == `tDONE)?1'b1:1'b0;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
measure_done <= 1'b0;
else if (read_ch_done)
measure_done <= 1'b1;
end
///////////////////////////////
// adc channel config
// pre-build config command
reg [(`CMD_BITS_NUM-1):0] config_cmd;
`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar
`define SLP_MODE 1'b0 //1: enable sleep
always @(negedge reset_n)
begin
if (~reset_n)
begin
case (measure_ch)
0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE};
1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE};
2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE};
3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE};
4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE};
5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE};
6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE};
7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE};
default : config_cmd <= {4'hF, 2'b00};
endcase
end
end
// serial config command to adc chip
wire config_init;
wire config_enable;
wire config_done;
reg [2:0] sdi_index;
assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0;
assign config_enable = (tick > `tCLK_START && tick <= `tCONFIG_END)?1'b1:1'b0; // > because this is negative edge triggle
assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0;
always @(negedge clk)
begin
if (config_init)
begin
ADC_SDI <= config_cmd[`CMD_BITS_NUM-1];
sdi_index <= `CMD_BITS_NUM-2;
end
else if (config_enable)
begin
ADC_SDI <= config_cmd[sdi_index];
sdi_index <= sdi_index - 1;
end
else if (config_done)
ADC_SDI <= 1'b0; //
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10, maxm = 2e6 + 10; const long long INF = 0x3f3f3f3f, mod = 1e9 + 7; int casn, n, m, k; namespace graph { vector<int> g[maxn]; int all, sz[maxn], root, maxt; bool vis[maxn]; int dfs_root(int now, int fa) { int cnt = 1; for (auto to : g[now]) { if (to == fa || vis[to]) continue; cnt += dfs_root(to, now); } int tmp = max(cnt - 1, all - cnt); if (maxt > tmp) maxt = tmp, root = now; return sz[now] = cnt; } int ans[maxn]; void dfs_col(int now, int fa, int c) { ans[now] = c; for (auto to : g[now]) if (to != fa && !vis[to]) dfs_col(to, now, c); } void dfs_dv(int now, int d = 0) { vis[now] = 1; dfs_col(now, now, d); for (auto to : g[now]) { if (vis[to]) continue; maxt = root = n + 1; all = sz[to]; dfs_root(to, now); dfs_dv(root, d + 1); } } void solve(int n) { all = maxt = root = n + 1; dfs_root(1, 1); all -= maxt; dfs_dv(root); } } // namespace graph using namespace graph; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 2; i <= n; ++i) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } solve(n); for (int i = 1; i <= n; ++i) cout << char(ans[i] + A ) << ; } |
#include <bits/stdc++.h> int main() { int n; printf( YES n ); scanf( %d , &n); for (int i = 0; i < n; i++) { int x1, y1, x2, y2; scanf( %d %d %d %d , &x1, &y1, &x2, &y2); printf( %d n , ((12 + 2 * (x1 % 2) + (y1 % 2)) % 4) + 1); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
integer cyc; initial cyc=1;
integer sum;
integer cpre;
always @ (posedge clk) begin
if (cyc!=0) begin
cpre = cyc;
cyc <= cyc + 1;
if (cyc==1) begin
if (mlog2(32'd0) != 32'd0) $stop;
if (mlog2(32'd1) != 32'd0) $stop;
if (mlog2(32'd3) != 32'd2) $stop;
sum <= 32'd0;
end
else if (cyc<90) begin
// (cyc) so if we trash the variable things will get upset.
sum <= mlog2(cyc) + sum * 32'd42;
if (cpre != cyc) $stop;
end
else if (cyc==90) begin
if (sum !== 32'h0f12bb51) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function integer mlog2;
input [31:0] value;
integer i;
begin
if(value < 32'd1) begin
mlog2 = 0;
end
else begin
value = value - 32'd1;
mlog2 = 0;
for(i=0;i<32;i=i+1) begin
if(value > 32'd0) begin
mlog2 = mlog2 + 1;
end
value = value >> 1;
end
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const int limit = 1000005; void die() { cout << NO << endl; exit(0); } void computereachable(int u, int code, vector<int> g[limit], int reachable[limit]) { if (reachable[u] & code) return; reachable[u] |= code; vector<int> &ar = g[u]; for (int i = 0; i < int(ar.size()); i++) computereachable(ar[i], code, g, reachable); } int n, m; vector<int> g[limit], ginv[limit]; int reachdir[limit]; int reachinv[limit]; int nsink; int nsour; int listsour[limit]; int norder; int order[limit]; int seen[limit]; void generatepostorder(int u) { if (seen[u]) return; seen[u] = 1; vector<int> &ar = ginv[u]; for (int i = 0; i < int(ar.size()); i++) generatepostorder(ar[i]); order[norder++] = u; } void traverse(int u) { if (seen[u]) return; seen[u] = 1; vector<int> &ar = g[u]; for (int i = 0; i < int(ar.size()); i++) traverse(ar[i]); } void checkalreadystrong() { for (int u = 1; u <= n; u++) generatepostorder(u); reverse(order, order + norder); for (int u = 1; u <= n; u++) seen[u] = 0; traverse(order[0]); for (int u = 1; u <= n; u++) if (not seen[u]) die(); cout << YES << endl; exit(0); } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; g[u].push_back(v); ginv[v].push_back(u); } for (int u = 1; u <= n; u++) { if (int(g[u].size()) == 0) { computereachable(u, 1 << (nsink++), ginv, reachinv); } if (int(ginv[u].size()) == 0) { computereachable(u, 1, g, reachdir); listsour[nsour++] = u; } } if (nsour == 0) checkalreadystrong(); for (int u = 1; u <= n; u++) if (not reachdir[u] or not reachinv[u]) die(); for (int c = 1; c < (1 << nsour) - 1; c++) { int creach = 0; for (int b = 0; b < nsour; b++) if (c & (1 << b)) creach |= reachinv[listsour[b]]; if (__builtin_popcount(creach) <= __builtin_popcount(c)) die(); } cout << YES << endl; } |
#include <bits/stdc++.h> using namespace std; long long ar[100005]; long long N; int main() { cin >> N; for (long long i = 0; i < N; i++) cin >> ar[i]; long long ans = 0ll; for (long long i = 0; i < N; i++) { long long lft = (i == 0 ? 0 : ar[i - 1]); if (ar[i] < lft) ans += (ar[i]) * (lft - ar[i]); if (ar[i] > lft) ans += (ar[i] - lft) * (N - ar[i] + 1); } cout << ans << endl; return (0); } |
module decoder (cx,d);
output [6:0] d;
input [11:0] cx;
reg [6:0] d;
reg [4:0] s;
reg [11:0] cx1;
parameter s0 = 5'b11110;
parameter s1 = 5'b10111;
parameter s2 = 5'b01000;
parameter s3 = 5'b00111;
parameter s4 = 5'b01000;
parameter s5 = 5'b11111;
parameter s6 = 5'b10111;
parameter s7 = 5'b10000;
parameter s8 = 5'b01000;
parameter s9 = 5'b00100;
parameter s10 = 5'b00010;
parameter s11 = 5'b00001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
cx1[11] = cx[11];
s[0]= cx[0]+ cx[1]+ cx[5]+ cx[6]+ cx[7];
s[1]= cx[0]+ cx[2]+ cx[4]+ cx[5]+ cx[8];
s[2]= cx[0]+ cx[1]+ cx[3]+ cx[5]+ cx[6]+ cx[9];
s[3]= cx[0]+ cx[1]+ cx[3]+ cx[5]+ cx[6]+ cx[10];
s[4]= cx[1]+ cx[3]+ cx[5]+ cx[6]+ cx[11];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
s11:
begin
if(cx[11]==1'b0)
begin
cx1[11]=1'b1;
end
else
begin
cx1[11]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
cx1[11]=cx[11];
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
d[3] = cx1[3];
d[4] = cx1[4];
d[5] = cx1[5];
d[6] = cx1[6];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, dp[30][30]; string s; long long ten[30]; string ans[30][30]; int main() { cin >> n >> s; reverse(s.begin(), s.end()); ten[0] = 1; for (int i = 1; i <= 20; i++) ten[i] = ten[i - 1] * 10; dp[0][0] = 0; dp[1][0] = s[0] - 0 ; ans[1][0] = M ; dp[0][1] = s[0] - 0 ; ans[0][1] = H ; for (int i = 2; i <= n; i++) { long long q = (int)s[i - 1] - 0 ; dp[i][0] = dp[i - 1][0] + q * ten[i - 1]; ans[i][0] = ans[i - 1][0]; ans[i][0] += M ; dp[0][i] = dp[0][i - 1] + q * ten[i - 1]; ans[0][i] = ans[0][i - 1]; ans[0][i] += H ; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { long long q = (int)s[i + j - 1] - 0 ; long long m = dp[i - 1][j] + q * ten[i - 1]; long long h = dp[i][j - 1] + q * ten[j - 1]; if (m <= h) { dp[i][j] = h; ans[i][j] = ans[i][j - 1]; ans[i][j] += H ; } else { dp[i][j] = m; ans[i][j] = ans[i - 1][j]; ans[i][j] += M ; } } s = ans[n][n]; reverse(s.begin(), s.end()); cout << s << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int ma[maxn]; int en[maxn]; int add = 0; int main() { std::ios::sync_with_stdio(false); int n, d; cin >> n >> d; int sum = 0; int mx = -40000000; int op = 0; for (int i = 0; i < n; i++) { int in; cin >> in; if (in != 0) { sum += in; mx = max(mx, sum); if (sum > d) { cout << -1 << endl; return 0; } } else { if (sum >= 0) continue; ma[op] = mx; en[op++] = sum; sum = 0; mx = -400000000; } } int cnt = 0; for (int i = 0; i < op; i++) { if (min(add, d - ma[i]) < abs(en[i])) { cnt++; add = d; } else { add = min(add, d - ma[i]) - abs(en[i]); } } cout << cnt << endl; } |
// W bus (main internal bus)
module bus_w(
input mwc, mwb, mwa,
input bwa, bwb,
input [0:15] ir,
input [0:15] kl,
input [0:15] rdt,
input [0:15] ki,
input [0:15] at,
input [0:15] ac,
input [0:15] a,
output [0:15] w
);
always @ (*) begin
case ({bwb, mwc, mwb, mwa})
4'b0000 : w[0:7] = a[0:7];
4'b0001 : w[0:7] = ac[0:7];
4'b0010 : w[0:7] = at[0:7];
4'b0011 : w[0:7] = ki[0:7];
4'b0100 : w[0:7] = 8'd0;
4'b0101 : w[0:7] = rdt[0:7];
4'b0110 : w[0:7] = kl[0:7];
4'b0111 : w[0:7] = ir[0:7];
default : w[0:7] = 8'd0; // bwb = 1 (blokuj lewy bajt)
endcase
case ({bwa, mwc, mwb, mwa})
4'b0000 : w[8:15] = a[8:15];
4'b0001 : w[8:15] = ac[8:15];
4'b0010 : w[8:15] = at[8:15];
4'b0011 : w[8:15] = ki[8:15];
4'b0100 : w[8:15] = ac[0:7];
4'b0101 : w[8:15] = rdt[8:15];
4'b0110 : w[8:15] = kl[8:15];
4'b0111 : w[8:15] = ir[8:15];
default : w[8:15] = 8'd0; // bwa = 1 (blokuj prawy bajt)
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; static inline void amin(int &a, int b) { if (a > b) a = b; } int main() { int N, M; scanf( %d%d , &N, &M); int A[N]; for (int i = 0; i < N; ++i) { scanf( %d , &A[i]); } pair<int, int> Q[M]; for (int i = 0; i < M; ++i) { scanf( %d%d , &Q[i].first, &Q[i].second); Q[i].first--; Q[i].second--; } int res = *max_element(A, A + N) - *min_element(A, A + N); list<int> res_q; int changes[N]; for (int mx = 0; mx < N; ++mx) { list<int> q; memset(changes, 0, sizeof changes); for (int i = 0; i < M; ++i) if (mx < Q[i].first || Q[i].second < mx) { q.push_back(i); for (int j = Q[i].first; j < Q[i].second + 1; ++j) changes[j]--; } int mn = numeric_limits<int>::max(); for (int i = 0; i < N; ++i) amin(mn, A[i] + changes[i]); if (res < A[mx] - mn) { res = A[mx] - mn; res_q = q; } } printf( %d n%d n , res, (int)res_q.size()); for (auto it : res_q) printf( %d , it + 1); printf( n ); return 0; } |
// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axis 'data' signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_0_util_axis2vector
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_vdma_v6_2_axis_infrastructure_v1_0_util_axis2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// inputs
input wire [C_TDATA_WIDTH-1:0] TDATA,
input wire [C_TDATA_WIDTH/8-1:0] TSTRB,
input wire [C_TDATA_WIDTH/8-1:0] TKEEP,
input wire TLAST,
input wire [C_TID_WIDTH-1:0] TID,
input wire [C_TDEST_WIDTH-1:0] TDEST,
input wire [C_TUSER_WIDTH-1:0] TUSER,
// outputs
output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_vdma_v6_2_axis_infrastructure_v1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA;
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB;
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP;
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST;
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID;
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST;
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER;
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2) { cout << contest n ; } else { cout << home n ; } } |
#include <bits/stdc++.h> using namespace std; int n, A[100], B[100], t, r, x; string s = ; int main() { cin >> n; for (int i = 0; i <= n; i++) { r = 0; for (int j = 0; j <= n; j++) { if ((t + r) == n) { x = 1; break; } r = r + 7; } if (x == 1) break; t = t + 4; } if (x == 1) { for (int i = 0; i < t / 4; i++) s += 4 ; for (int i = 0; i < r / 7; i++) s += 7 ; } else { s = -1 ; } cout << s; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Registro de solicitudes ////
//// ////
//// ////
//// Este archivo describe el comportamiento ////
//// del registro de solicitudes en Verilog ////
//// ////
//// Description ////
//// Este mòdulo se encarga de almacenar las solicitudes que el ////
//// usuario hace en los pisos. Debe registrar 2 bits por cada ////
//// uno de los 5 pisos. ////
//// ////
//// ////
//// ////
//// ////
//// Autor : ////
//// - Manuel Zumbado Corrales ////
//// - Arturo Salas Delgado ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
/// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module RegistroSolicitudes(
input _clk_,reset_in,
input solicitud_ps_clear_in, solicitud_p1_clear_in, solicitud_p2_clear_in, solicitud_p3_clear_in, solicitud_p4_clear_in,
input [1:0] solicitud_ps_in, solicitud_p1_in, solicitud_p2_in, solicitud_p3_in, solicitud_p4_in,
output [1:0] solicitud_ps_out, solicitud_p1_out, solicitud_p2_out, solicitud_p3_out, solicitud_p4_out
);
reg clear_ps, clear_p1, clear_p2, clear_p3, clear_p4=1;
Registro2Bits piso_s (
._clk_(_clk_),
.datos_i(solicitud_ps_in),
//.load_en(solicitud_ps_in[0]|solicitud_ps_in[1]),
.clear_i(clear_ps),
.salida_o(solicitud_ps_out));
Registro2Bits piso_1 (
._clk_(_clk_),
.datos_i(solicitud_p1_in),
//.load_en(solicitud_p1_in[0]|solicitud_p1_in[1]),
.clear_i(clear_p1),
.salida_o(solicitud_p1_out));
Registro2Bits piso_2 (
._clk_(_clk_),
//.load_en(solicitud_p2_in[0]|solicitud_p2_in[1]),
.datos_i(solicitud_p2_in),
.clear_i(clear_p2),
.salida_o(solicitud_p2_out));
Registro2Bits piso_3 (
._clk_(_clk_),
//.load_en(solicitud_p3_in[0]|solicitud_p3_in[1]),
.datos_i(solicitud_p3_in),
.clear_i(clear_p3),
.salida_o(solicitud_p3_out));
Registro2Bits piso_4 (
._clk_(_clk_),
//.load_en(solicitud_p4_in[0]|solicitud_p4_in[1]),
.datos_i(solicitud_p4_in),
.clear_i(clear_p4),
.salida_o(solicitud_p4_out));
always @( posedge _clk_ or posedge reset_in) begin
if(reset_in) begin
clear_ps<=1;
clear_p1<=1;
clear_p2<=1;
clear_p3<=1;
clear_p4<=1;
end else begin
clear_ps<=solicitud_ps_clear_in;
clear_p1<=solicitud_p1_clear_in;
clear_p2<=solicitud_p2_clear_in;
clear_p3<=solicitud_p3_clear_in;
clear_p4<=solicitud_p4_clear_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long linf = 1e18 + 5; const int mod = (int)1e9 + 7; const int logN = 17; const int inf = 1e9; const int N = 2e5 + 5; int s, n, m, h1[N], h, t, x, y, z; vector<int> v[N]; pair<int, int> e[N]; void print(int x, int y) { cout << YES n ; vector<int> com, h, t; for (__typeof(v[x].begin()) it = v[x].begin(); it != v[x].end(); it++) h1[*it]++; for (__typeof(v[y].begin()) it = v[y].begin(); it != v[y].end(); it++) h1[*it]++; for (__typeof(v[x].begin()) it = v[x].begin(); it != v[x].end(); it++) { if (*it == y) continue; if (h1[*it] == 1 && h.size() < ::h) h.push_back(*it); if (h1[*it] == 2) com.push_back(*it); } for (__typeof(v[y].begin()) it = v[y].begin(); it != v[y].end(); it++) { if (*it == x) continue; if (h1[*it] == 1 && t.size() < ::t) t.push_back(*it); } while (h.size() < ::h) { h.push_back(com.back()); com.pop_back(); } while (t.size() < ::t) { t.push_back(com.back()); com.pop_back(); } cout << x << << y << n ; for (__typeof(h.begin()) it = h.begin(); it != h.end(); it++) cout << *it << ; cout << n ; for (__typeof(t.begin()) it = t.begin(); it != t.end(); it++) cout << *it << ; cout << n ; } int main() { scanf( %d %d %d %d , &n, &m, &h, &t); int s = 0; for (int i = 1; i <= m; i++) { scanf( %d %d , &x, &y); e[++s] = make_pair(x, y); e[++s] = make_pair(y, x); v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= n; i++) { sort(v[i].begin(), v[i].end()); } for (int i = 1; i <= s; i++) { x = e[i].first; y = e[i].second; if (v[x].size() >= h + 1 && v[y].size() >= h + t + 1) { print(x, y); return 0; } if (v[x].size() >= h + t + 1 && v[y].size() >= t + 1) { print(x, y); return 0; } if (v[x].size() <= h || v[y].size() <= t) continue; int j = 0; int s1 = v[x].size() - 1, s2 = v[y].size() - 1, com = 0; for (int tt = 0; tt <= s1; tt++) { while (j < v[y].size() && v[y][j] < v[x][tt]) j++; if (j < v[y].size() && v[y][j] == v[x][tt]) com++; } if (s1 + s2 - com >= h + t) { print(x, y); return 0; } } cout << NO n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 1, -1, 0}; int dy[] = {1, 0, 0, -1}; long double PI = 3.14159265358979323846264338327950; pair<int, int> p[12000002]; int a[12000002], b[12000002]; int m, n, k; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> k; for (int i = 1, x; i <= n; i++) { cin >> x; a[x]++; if (a[x] > k) { cout << -1; return 0; } } for (int i = 1, x; i <= m; i++) { cin >> x; p[i] = {x, i}; } sort(p + 1, p + 1 + m); int ch = 0; int res = 0; for (int i = 1; i <= m; i++) { for (; a[ch] == k; ch++) ; if (ch > p[i].first) continue; else { res++; b[res] = p[i].second, a[ch]++; } } cout << res << n ; for (int i = 1; i <= res; i++) cout << b[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int i, save, left, right; string A; while (cin >> A) { left = 0; right = 0; for (i = 0; i < A.size(); i++) { if (A[i] == ^ ) { save = i; } } i = save; i--; while (i != -1) { if (A[i] >= 0 && A[i] <= 9 ) left += (A[i] - 0 ) * (save - i); i--; } int i = save; i++; while (i != A.size()) { if (A[i] >= 0 && A[i] <= 9 ) right += (A[i] - 0 ) * (i - save); i++; } if (left > right) cout << left << endl; else if (right > left) cout << right << endl; else cout << balance << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MAJ3_PP_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_PP_BLACKBOX_V
|
`include "mux2_1.sv"
`include "shiftll.v"
module shiftllTest ();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
// declare an instance of the module
shiftll shiftll (busADD, busA, busB);
// Running the GUI part of simulation
shiftlltester tester (busADD, busA, busB);
// file for gtkwave
initial
begin
$dumpfile("shiftlltest.vcd");
$dumpvars(1, shiftll);
end
endmodule
module shiftlltester (busADD, busA, busB);
input [31:0] busADD;
output reg [31:0] busA, busB;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t\t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t ", busADD, busA, busB, $time);
busA = 32'h01010101; busB = 32'h00000001;
#d;
busA = 32'h01010101; busB = 32'h00000002;
#d;
busA = 32'h01010101; busB = 32'h00000003;
#d;
busA = 32'h01010101; busB = 32'h00000004;
#d;
busA = 32'h01010101; busB = 32'h00000005;
#d;
busA = 32'h01010101; busB = 32'h00000006;
#d;
busA = 32'h01010101; busB = 32'h00000007;
#d;
busA = 32'h01010101; busB = 32'h0000000F;
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; long long k[n]; pair<long long, long long> dt[m]; for (int i = 0; i < n; i++) cin >> k[i]; for (int i = 0; i < m; i++) cin >> dt[i].first >> dt[i].second; long long total = 0; for (int i = 0; i < n; i++) total += k[i]; long long start = 1; long long end = 2 * total; long long ans = 2 * total; while (start <= end) { long long check = start + (end - start) / 2; pair<long long, long long> last[n]; for (int i = 0; i < n; i++) { last[i].first = LONG_MAX; last[i].second = i; } for (int i = 0; i < m; i++) { if (dt[i].first <= check) { if (last[dt[i].second - 1].first == LONG_MAX) last[dt[i].second - 1].first = dt[i].first; else last[dt[i].second - 1].first = max(dt[i].first, last[dt[i].second - 1].first); } } sort(last, last + n); int point = 0; long long money = 0; long long count = 0; for (int i = 1; i <= check; i++) { money++; while (last[point].first == i) { long long deduce = min(money, k[last[point].second]); count += deduce; money -= deduce; point++; } } money -= 2 * (total - count); if (money < 0) { start = check + 1; } else { ans = check; end = check - 1; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); string s; cin >> s; long long l = -1, r = -1; for (long long i = 0; i < s.length(); i++) { if (s[i] == [ ) { l = i; break; } } for (long long i = s.length(); i >= 0; i--) { if (s[i] == ] ) { r = i; break; } } if (l == -1 || r == -1 || r < l) cout << -1 << n , exit(0); s = s.substr(l, r - l + 1); l = -1; r = -1; for (long long i = 1; i < s.length() - 1; i++) { if (s[i] == : ) { l = i; break; } } for (long long i = s.length() - 2; i >= 1; i--) { if (s[i] == : ) { r = i; break; } } if (l == r || l == -1) cout << -1 n , exit(0); string v = s.substr(l, r - l + 1); long long ct = 0; for (auto it : v) { if (it == | ) ct++; } cout << ct + 4 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; int num[500005]; long long dp[500005]; int cnt[500005]; bool ok(int cost) { dp[0] = dp[1] = cnt[0] = cnt[1] = 0; for (int i = (2); i <= (n); i += (1)) { dp[i] = dp[i - 1]; cnt[i] = cnt[i - 1]; long long v = dp[i - 2] + num[i] - num[i - 1] - cost; int c = cnt[i - 2] + 1; if (v < dp[i] || v == dp[i] && c > cnt[i]) dp[i] = v, cnt[i] = c; } return (cnt[n] >= k); } int main() { scanf( %d %d , &k, &n); for (int i = (1); i <= (n); i += (1)) scanf( %d , &num[i]); sort(num + 1, num + n + 1); int l = 0, r = 1000000000; while (l <= r) { int m = (l + r) >> 1; if (ok(m)) r = m - 1; else l = m + 1; } ok(l); printf( %lld n , dp[n] + 1LL * l * k); return 0; } |
#include <bits/stdc++.h> using namespace std; long long f[200200], sum[200200]; long long n; void init() { f[0] = 1LL; for (int i = 1; i <= n; i++) f[i] = f[i - 1] * 10LL % 998244353; return; } void solve() { for (long long i = 1; i <= n; i++) { long long ans = 0; if (i == n) ans = 10; else if (i == n - 1) ans = 180; else { ans += (10LL * 9LL * 9LL * (n - i - 1) * f[n - i - 2]) % 998244353; ans += (10LL * 9LL * 2LL * f[n - i - 1]) % 998244353; ans %= 998244353; } printf( %lld , ans); if (i != n) printf( ); } return; } int main() { scanf( %lld , &n); init(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int solve(vector<int> &v, int pow) { if (pow == 20) { for (int j : v) { if (j) return 40; } return 0; } bool fnd = false; for (int i = 0; i < v.size(); i++) { if (v[i] % (1 << (pow + 1))) { fnd = true; } } if (!fnd) return solve(v, pow + 1); else { vector<int> v2(v); for (int i = 0; i < v.size(); i++) { if (v[i] % (1 << (pow + 1))) { v2[i] += (1 << pow); } } sort(v2.begin(), v2.end()); v2.erase(unique(v2.begin(), v2.end()), v2.end()); int tmp = 1 + solve(v2, pow + 1); v2.clear(); for (int i = 0; i < v.size(); i++) { v2.push_back(v[i]); } for (int i = 0; i < v.size(); i++) { if (v[i] % (1 << (pow + 1))) { v2[i] -= (1 << pow); } } sort(v2.begin(), v2.end()); v2.erase(unique(v2.begin(), v2.end()), v2.end()); return min(tmp, 1 + solve(v2, pow + 1)); } } int main() { int N; cin >> N; vector<int> v(N); for (int i = 0; i < N; i++) { cin >> v[i]; } int ans = solve(v, 0); cout << ans << endl; vector<int> lvl(v); int rank = 0; while (rank != 20) { bool fnd = false; for (int i = 0; i < v.size(); i++) { if (v[i] % (1 << (rank + 1))) { fnd = true; } } if (!fnd) { rank++; } else { vector<int> v2(v); vector<int> v3(v); for (int i = 0; i < v.size(); i++) { if (v[i] % (1 << (rank + 1))) { v2[i] += (1 << rank); } } sort(v2.begin(), v2.end()); v2.erase(unique(v2.begin(), v2.end()), v2.end()); int tmp = 1 + solve(v2, rank + 1); for (int i = 0; i < v.size(); i++) { if (v[i] % (1 << (rank + 1))) { v3[i] -= (1 << rank); } } sort(v3.begin(), v3.end()); v3.erase(unique(v3.begin(), v3.end()), v3.end()); int tmp2 = 1 + solve(v3, rank + 1); if (tmp < tmp2) { cout << -(1 << rank) << ; v = v2; } else { cout << (1 << rank) << ; v = v3; } rank++; } } cout << endl; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); int n, m, w, a, b, v; cin >> n >> m >> a >> b >> v; set<int> s; set<int> l; for (int i = 0; i < a; ++i) { int x; cin >> x; s.insert(x); } for (int i = 0; i < b; ++i) { int x; cin >> x; l.insert(x); } int q; cin >> q; for (int i = 0; i < q; ++i) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (y1 > y2) { swap(y1, y2); } if (x1 > x2) { swap(x1, x2); } int ans = INF; if (x1 == x2) { ans = y2 - y1; } auto it = s.lower_bound(y1); if (it != s.end()) { int y = *it; ans = min(ans, x2 - x1 + abs(y1 - y) + abs(y2 - y)); } if (it != s.begin()) { --it; int y = *it; ans = min(ans, x2 - x1 + abs(y1 - y) + abs(y2 - y)); } it = l.lower_bound(y1); if (it != l.end()) { int y = *it; ans = min(ans, abs(y1 - y) + abs(y2 - y) + (x2 - x1 + v - 1) / v); } if (it != l.begin()) { --it; int y = *it; ans = min(ans, abs(y1 - y) + abs(y2 - y) + (x2 - x1 + v - 1) / v); } cout << ans << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:26 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/menu_bg/menu_bg_stub.v
// Design : menu_bg
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module menu_bg(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [13:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:21 05/03/2016
// Design Name:
// Module Name: data_deal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_deal(
clk,
rst_n,
data_in,
data_in_sign,
data_out,
data_out_sign,
data_valid,
data_ok
);
input clk;
input rst_n;
input [6:0] data_in;
input data_in_sign;
output [6:0] data_out;
output data_out_sign;
input data_valid;
output data_ok;
reg [6:0] data_reg;
reg [3:0] data_regnum;
reg data_ok;
reg [6:0] data_out;
reg data_out_sign;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_reg <= 7'h0;
data_regnum <= 4'h0;
data_ok <= 1'h0;
end
else if(data_regnum == 4'h8) begin
data_ok <= ((data_reg == 7'd28)||
(data_reg== 7'd36))?1'b1:1'b0;
end
else begin
data_regnum <= data_in_sign ? data_regnum + 1'b1 : data_regnum;
data_reg <= data_reg + (data_in_sign ? data_in : 7'h0);
end
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_out_sign <= 1'b0;
data_out <= 'h0;
end
else if(data_regnum < 4'h7)begin
if(~data_out_sign & data_valid) data_out_sign <= 1'b1;
else data_out_sign <= 1'b0;
data_out <= ~data_out_sign & data_valid ? data_out + 1'b1 : data_out;
end
end
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) #pragma GCC optimize( O3 ) using namespace std; const long long N = 1e5 + 10; const long long mod = 1e9 + 7; const long long INF = 1e18; const long long inf = -1e18; const long long M = 1e6; int n, x, y, a[5 * N]; bool us[1000010]; int used[1000010]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> n >> x >> y; for (int i = 1; i <= n; i++) { cin >> a[i]; used[a[i]]++; } long long ans = INF; for (int i = 2; i <= 1000000; i++) { if (us[i] == 0) { long long s = used[i]; for (int j = i + i; j <= 1000000; j += i) { us[j] = 1; s += used[j]; } if ((n - s) * min(x, y) >= ans) continue; long long cnt = 0; for (int j = 1; j <= n; j++) { if (a[j] % i != 0) { long long t = a[j] % i; cnt += min(1ll * x, 1ll * (i - t) * y); } } ans = min(ans, 1ll * cnt); } } cout << ans; cin.get(), cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; int dfn[200002], low[200002], tot, head[200002], num, f[200002]; int p[20][200002]; int deep[200002], n, m, q, st[200002], top, dep[200002]; bool vis[200002]; inline long long rd() { long long x = 0; char c = getchar(); bool f = 0; while (!isdigit(c)) { if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return f ? -x : x; } struct edge { int n, to; } e[200002]; inline void add(int u, int v) { e[++tot].n = head[u]; e[tot].to = v; head[u] = tot; } vector<int> vec[200002]; void tarjan(int u, int fa) { dfn[u] = low[u] = ++dfn[0]; st[++top] = u; vis[u] = 1; for (vector<int>::iterator it = vec[u].begin(); it != vec[u].end(); ++it) { int v = *it; if (v == fa) continue; if (!dfn[v]) { tarjan(v, u); low[u] = min(low[u], low[v]); if (low[v] == dfn[u]) { ++num; add(u, num); int x = 0; while (x != v) { x = st[top]; add(num, x); vis[x] = 0; top--; } } if (low[v] > dfn[u]) { add(u, v); vis[st[top]] = 0; top--; } } else if (vis[v]) low[u] = min(low[u], dfn[v]); } } void dfs(int u, int fa) { for (int i = 1; (1 << i) <= deep[u]; ++i) p[i][u] = p[i - 1][p[i - 1][u]]; for (int i = head[u]; i; i = e[i].n) if (e[i].to != fa) { int v = e[i].to; f[v] = u; deep[v] = deep[u] + 1; p[0][v] = u; dep[v] = dep[u] + (v > n); dfs(v, u); } } inline int getlca(int u, int v) { if (deep[u] < deep[v]) swap(u, v); for (int i = 19; i >= 0; --i) if (deep[u] - (1 << i) >= deep[v]) u = p[i][u]; if (u == v) return u; for (int i = 19; i >= 0; --i) if (p[i][u] != p[i][v]) u = p[i][u], v = p[i][v]; return p[0][u]; } inline int dist(int u, int v) { int lca = getlca(u, v); return deep[u] + deep[v] - 2 * deep[lca] - (dep[u] + dep[v] - dep[lca] - dep[f[lca]]); } int main() { n = rd(); m = rd(); q = rd(); int u, v; for (int i = 1; i <= m; ++i) { u = rd(); v = rd(); vec[u].push_back(v); vec[v].push_back(u); } num = n; tarjan(1, 0); dfs(1, 0); while (q--) { u = rd(); v = rd(); printf( %d n , dist(u, v)); } return 0; } |
#include <bits/stdc++.h> int main() { int l, i, flag = 0; char s[50]; scanf( %s , s); l = strlen(s); for (i = 0; i < l; i++) { if (s[0] == s[i]) flag = flag + 1; } if (flag == l) { printf( %d , 0); return 0; } flag = 0; for (i = 0; i < (l / 2); i++) { if (s[i] != s[l - i - 1]) { flag = flag + 1; break; } } if (flag == 0) printf( %d , l - 1); else printf( %d , l); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 1; int n, sa[N], sb[N], a1[N], b1[N], suma, sumb, q[N]; struct nd { int w, id; } a[N], b[N]; bool cmp(nd a, nd b) { return a.w > b.w; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i].w), a[i].id = i, a1[i] = a[i].w, suma += a[i].w; for (int i = 1; i <= n; ++i) scanf( %d , &b[i].w), b[i].id = i, b1[i] = b[i].w, sumb += b[i].w; sort(a + 1, a + n + 1, cmp); q[++q[0]] = a[1].id; for (int i = 2; i < n; i += 2) { if (b1[a[i].id] > b1[a[i + 1].id]) q[++q[0]] = a[i].id; else q[++q[0]] = a[i + 1].id; } if (n % 2 == 0) q[++q[0]] = a[n].id; cout << n / 2 + 1 << endl; for (int i = 1; i <= q[0]; ++i) cout << q[i] << ; } |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: router_op_lut_regs.v
// Project: NF2.1
// Description: Demultiplexes, stores and serves register requests
//
///////////////////////////////////////////////////////////////////////////////
module router_op_lut_regs
#( parameter NUM_QUEUES = 5,
parameter ARP_LUT_DEPTH_BITS = 4,
parameter LPM_LUT_DEPTH_BITS = 4,
parameter FILTER_DEPTH_BITS = 4,
parameter UDP_REG_SRC_WIDTH = 2
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- interface to op_lut_process_sm
input pkt_sent_from_cpu, // pulsed: we've sent a pkt from the CPU
input pkt_sent_to_cpu_options_ver, // pulsed: we've sent a pkt to the CPU coz it has options/bad version
input pkt_sent_to_cpu_bad_ttl, // pulsed: sent a pkt to the CPU coz the TTL is 1 or 0
input pkt_sent_to_cpu_dest_ip_hit, // pulsed: sent a pkt to the CPU coz it has hit in the destination ip filter list
input pkt_forwarded , // pulsed: forwarded pkt to the destination port
input pkt_dropped_checksum, // pulsed: dropped pkt coz bad checksum
input pkt_sent_to_cpu_non_ip, // pulsed: sent pkt to cpu coz it's not IP
input pkt_sent_to_cpu_arp_miss, // pulsed: sent pkt to cpu coz we didn't find arp entry for next hop ip
input pkt_sent_to_cpu_lpm_miss, // pulsed: sent pkt to cpu coz we didn't find lpm entry for destination ip
input pkt_dropped_wrong_dst_mac, // pulsed: dropped pkt not destined to us
// --- interface to ip_lpm
output [LPM_LUT_DEPTH_BITS-1:0 ] lpm_rd_addr, // address in table to read
output lpm_rd_req, // request a read
input [31:0] lpm_rd_ip, // ip to match in the CAM
input [31:0] lpm_rd_mask, // subnet mask
input [NUM_QUEUES-1:0] lpm_rd_oq, // input queue
input [31:0] lpm_rd_next_hop_ip, // ip addr of next hop
input lpm_rd_ack, // pulses high
output [LPM_LUT_DEPTH_BITS-1:0] lpm_wr_addr,
output lpm_wr_req,
output [NUM_QUEUES-1:0] lpm_wr_oq,
output [31:0] lpm_wr_next_hop_ip, // ip addr of next hop
output [31:0] lpm_wr_ip, // data to match in the CAM
output [31:0] lpm_wr_mask,
input lpm_wr_ack,
// --- ip_arp
output [ARP_LUT_DEPTH_BITS-1:0] arp_rd_addr, // address in table to read
output arp_rd_req, // request a read
input [47:0] arp_rd_mac, // data read from the LUT at rd_addr
input [31:0] arp_rd_ip, // ip to match in the CAM
input arp_rd_ack, // pulses high
output [ARP_LUT_DEPTH_BITS-1:0] arp_wr_addr,
output arp_wr_req,
output [47:0] arp_wr_mac,
output [31:0] arp_wr_ip, // data to match in the CAM
input arp_wr_ack,
// --- interface to dest_ip_filter
output [FILTER_DEPTH_BITS-1:0] dest_ip_filter_rd_addr, // address in table to read
output dest_ip_filter_rd_req, // request a read
input [31:0] dest_ip_filter_rd_ip, // ip to match in the CAM
input dest_ip_filter_rd_ack, // pulses high
output [FILTER_DEPTH_BITS-1:0] dest_ip_filter_wr_addr,
output dest_ip_filter_wr_req,
output [31:0] dest_ip_filter_wr_ip, // data to match in the CAM
input dest_ip_filter_wr_ack,
// --- eth_parser
output [47:0] mac_0, // address of rx queue 0
output [47:0] mac_1, // address of rx queue 1
output [47:0] mac_2, // address of rx queue 2
output [47:0] mac_3, // address of rx queue 3
input clk,
input reset
);
// ------------- Wires/reg ------------------
wire reg_req_internal;
wire reg_ack_internal;
wire reg_rd_wr_L_internal;
wire [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_internal;
wire [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_internal;
wire [UDP_REG_SRC_WIDTH-1:0] reg_src_internal;
// ------------- Modules ------------------
router_op_lut_regs_non_cntr #(
.NUM_QUEUES (NUM_QUEUES),
.ARP_LUT_DEPTH_BITS (ARP_LUT_DEPTH_BITS),
.LPM_LUT_DEPTH_BITS (LPM_LUT_DEPTH_BITS),
.FILTER_DEPTH_BITS (FILTER_DEPTH_BITS),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
) router_op_lut_regs_non_cntr (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_internal),
.reg_ack_out (reg_ack_internal),
.reg_rd_wr_L_out (reg_rd_wr_L_internal),
.reg_addr_out (reg_addr_internal),
.reg_data_out (reg_data_internal),
.reg_src_out (reg_src_internal),
// --- interface to ip_lpm
.lpm_rd_addr (lpm_rd_addr), // address in table to read
.lpm_rd_req (lpm_rd_req), // request a read
.lpm_rd_ip (lpm_rd_ip), // ip to match in the CAM
.lpm_rd_mask (lpm_rd_mask), // subnet mask
.lpm_rd_oq (lpm_rd_oq), // input queue
.lpm_rd_next_hop_ip (lpm_rd_next_hop_ip), // ip addr of next hop
.lpm_rd_ack (lpm_rd_ack), // pulses high
.lpm_wr_addr (lpm_wr_addr),
.lpm_wr_req (lpm_wr_req),
.lpm_wr_oq (lpm_wr_oq),
.lpm_wr_next_hop_ip (lpm_wr_next_hop_ip), // ip addr of next hop
.lpm_wr_ip (lpm_wr_ip), // data to match in the CAM
.lpm_wr_mask (lpm_wr_mask),
.lpm_wr_ack (lpm_wr_ack),
// --- ip_arp
.arp_rd_addr (arp_rd_addr), // address in table to read
.arp_rd_req (arp_rd_req), // request a read
.arp_rd_mac (arp_rd_mac), // data read from the LUT at rd_addr
.arp_rd_ip (arp_rd_ip), // ip to match in the CAM
.arp_rd_ack (arp_rd_ack), // pulses high
.arp_wr_addr (arp_wr_addr),
.arp_wr_req (arp_wr_req),
.arp_wr_mac (arp_wr_mac),
.arp_wr_ip (arp_wr_ip), // data to match in the CAM
.arp_wr_ack (arp_wr_ack),
// --- interface to dest_ip_filter
.dest_ip_filter_rd_addr (dest_ip_filter_rd_addr), // address in table to read
.dest_ip_filter_rd_req (dest_ip_filter_rd_req), // request a read
.dest_ip_filter_rd_ip (dest_ip_filter_rd_ip), // ip to match in the CAM
.dest_ip_filter_rd_ack (dest_ip_filter_rd_ack), // pulses high
.dest_ip_filter_wr_addr (dest_ip_filter_wr_addr),
.dest_ip_filter_wr_req (dest_ip_filter_wr_req),
.dest_ip_filter_wr_ip (dest_ip_filter_wr_ip), // data to match in the CAM
.dest_ip_filter_wr_ack (dest_ip_filter_wr_ack),
// --- eth_parser
.mac_0 (mac_0), // address of rx queue 0
.mac_1 (mac_1), // address of rx queue 1
.mac_2 (mac_2), // address of rx queue 2
.mac_3 (mac_3), // address of rx queue 3
.clk (clk),
.reset (reset)
);
router_op_lut_regs_cntr #(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
) router_op_lut_regs_cntr (
.reg_req_in (reg_req_internal),
.reg_ack_in (reg_ack_internal),
.reg_rd_wr_L_in (reg_rd_wr_L_internal),
.reg_addr_in (reg_addr_internal),
.reg_data_in (reg_data_internal),
.reg_src_in (reg_src_internal),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- interface to op_lut_process_sm
.pkt_sent_from_cpu (pkt_sent_from_cpu),
.pkt_sent_to_cpu_options_ver (pkt_sent_to_cpu_options_ver),
.pkt_sent_to_cpu_bad_ttl (pkt_sent_to_cpu_bad_ttl),
.pkt_sent_to_cpu_dest_ip_hit (pkt_sent_to_cpu_dest_ip_hit),
.pkt_forwarded (pkt_forwarded),
.pkt_dropped_checksum (pkt_dropped_checksum),
.pkt_sent_to_cpu_non_ip (pkt_sent_to_cpu_non_ip),
.pkt_sent_to_cpu_arp_miss (pkt_sent_to_cpu_arp_miss),
.pkt_sent_to_cpu_lpm_miss (pkt_sent_to_cpu_lpm_miss),
.pkt_dropped_wrong_dst_mac (pkt_dropped_wrong_dst_mac),
.clk (clk),
.reset (reset)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, d, a, b, x, y; cin >> n >> d >> a >> b; pair<long long, long long> arr[n]; for (int i = 0; i < n; i++) { cin >> x >> y; x *= a; y *= b; arr[i] = {x + y, i + 1}; } sort(arr, arr + n); vector<int> vec; for (int i = 0; i < n; i++) { if (d >= arr[i].first) { d -= arr[i].first; vec.push_back(arr[i].second); } else break; } cout << vec.size() << endl; for (int i = 0; i < vec.size(); i++) cout << vec[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a == 0) { return b; } if (b == 0) { return a; } return gcd(b % a, a); } int main() { long long ra, la, ta, rb, lb, tb; cin >> la >> ra >> ta; cin >> lb >> rb >> tb; long long g = gcd(ta, tb); if (ta > tb) { long long j = la, k = ra, l = ta; la = lb; ra = rb; ta = tb; lb = j; rb = k; tb = l; } lb -= la; rb -= la; long long buff = ((lb + tb) % tb) - lb; lb += buff; rb += buff; ra -= la; la -= la; long long bdif = 0; long long nf = (lb % g) - lb; lb += nf; rb += nf; bdif = max(bdif, 1 + min(rb, ra) - max(lb, la)); long long nl = ((lb + g - 1) % g) - g + 1; long long df = nl - lb; lb += df; rb += df; bdif = max(bdif, 1 + min(rb, ra) - max(lb, la)); cout << bdif << endl; } |
#include <bits/stdc++.h> using namespace std; void __print(int first) { cerr << first; } void __print(long first) { cerr << first; } void __print(long long first) { cerr << first; } void __print(unsigned first) { cerr << first; } void __print(unsigned long first) { cerr << first; } void __print(unsigned long long first) { cerr << first; } void __print(float first) { cerr << first; } void __print(double first) { cerr << first; } void __print(long double first) { cerr << first; } void __print(char first) { cerr << << first << ; } void __print(const char *first) { cerr << << first << ; } void __print(const string &first) { cerr << << first << ; } void __print(bool first) { cerr << (first ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &first) { cerr << { ; __print(first.first); cerr << , ; __print(first.second); cerr << } ; } template <typename T> void __print(const T &first) { int f = 0; cerr << { ; for (auto &i : first) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } long long check(vector<long long> a, long long n, long long k) { long long ans = 0; for (long long i = 1; i < n + 1; i++) { long long req; if (a[i] < 0) { req = -1 * a[i]; ans += req; a[i + 1] -= req; } else { req = a[i] % k; if (req < k - req) { ans += req; a[i + 1] += req; } else { ans += k - req; a[i + 1] -= k - req; } } } return ans; } bool prime[1000010]; vector<long long> factors; void sieve(long long n) { memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } for (long long p = 2; p <= n; p++) if (prime[p]) factors.push_back(p); } int main() { sieve(1000000); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; vector<long long> a(n + 2); long long sum = 0; for (long long i = 1; i < n + 1; i++) { cin >> a[i]; sum += a[i]; }; vector<long long> prime_divisors; for (auto &factor : factors) { if (sum % factor == 0) { prime_divisors.push_back(factor); sum /= factor; } } if (sum != 1) prime_divisors.push_back(sum); long long ans = 1e18; ; for (auto &prime_divisor : prime_divisors) { ans = min(ans, check(a, n, prime_divisor)); ; } if (ans == 1e18) ans = -1; cout << ans << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRTP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long am[20]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<long long> a(n); for (int i = 0, ThxDem = n; i < ThxDem; ++i) { cin >> a[i]; for (int j = 0, ThxDem = 20; j < ThxDem; ++j) if (a[i] & (1 << j)) am[j]++; a[i] = 0; } for (int i = 0, ThxDem = n; i < ThxDem; ++i) { for (int j = 0, ThxDem = 20; j < ThxDem; ++j) if (am[j]) a[i] |= 1 << j, am[j]--; } long long ans = 0; for (int i = 0, ThxDem = n; i < ThxDem; ++i) ans += a[i] * a[i]; cout << ans << n ; } |
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
sys_clk_i, sys_rst_i,
miso, mosi, ss, sclk
);
input sys_clk_i, sys_rst_i,miso;
output mosi, ss, sclk;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:4]cs; // CHIP-SELECT
wire [15:0] sd_out;
// reg mosi;
// reg sclk;
// reg ss;
// wire miso;
// wire [15:0] dp_ram_dout;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_SD sd(.clk(sys_clk_i), .reset(sys_rst_i) , .d_in(j1_io_dout) , .cs(cs[1]) , .addr(j1_io_addr[3:0]) , .rd(j1_io_rd) , .wr(j1_io_wr), .d_out(sd_out), .sclk(sclk), .mosi(mosi), .miso(miso), .ss(ss) );
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 4'b1000; //SD
8'h68: cs= 4'b0100; //div
8'h70: cs= 4'b0001; //dp_ram
default: cs= 3'b000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
4'b1000: j1_io_din = sd_out;
4'b0001: j1_io_din = dp_ram_dout;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
module CPLD_RS485(CPU_RXD1,CPU_RTS1,CPU_TXD1,TXD0,TXD1,TXD2,TXD3,TXD4,TXD5,TXD6,TXD7,RXD0,
RXD1,RXD2,RXD3,RXD4,RXD5,RXD6,RXD7, ADD1,ADD2,ADD3,ADD4,RTS0,RTS1,RTS2,RTS3,RTS4,RTS5,RTS6,RTS7, CLK,NRST);
output CPU_RXD1,TXD0,TXD1,TXD2,TXD3,TXD4,TXD5,TXD6,TXD7,RTS0,RTS1,RTS2,RTS3,RTS4,RTS5,RTS6,RTS7;
input CPU_TXD1,RXD0,RXD1,RXD2,RXD3,RXD4,RXD5,RXD6,RXD7, ADD1,ADD2,ADD3,ADD4,CPU_RTS1,CLK,NRST;
assign CPU_RXD1=(!ADD1 &&!ADD2 &&!ADD3)&&RXD0+(!ADD1 && !ADD2 && ADD3) &&RXD1+
(!ADD1 &&ADD2 && ADD3)&&RXD2+(!ADD1 && ADD2 && ADD3)&&RXD3+
(ADD1 && !ADD2 && !ADD3)&&RXD4+(ADD1 && !ADD2 && ADD3)&&RXD5+
(ADD1 && ADD2 && !ADD3)&&RXD6+(ADD1 && ADD2 && ADD3)&&RXD7;
assign TXD0=CPU_TXD1+ ~(!ADD1 && !ADD2 && !ADD3); //000
assign TXD1=CPU_TXD1+~(!ADD1 && !ADD2 && ADD3); //001
assign TXD2=CPU_TXD1+~(!ADD1 && ADD2 && !ADD3); //010
assign TXD3=CPU_TXD1+~(!ADD1 && ADD2 && ADD3); //011
assign TXD4=CPU_TXD1+~(ADD1 && !ADD2 && !ADD3); //100
assign TXD5=CPU_TXD1+~(ADD1 && !ADD2 && ADD3); //101
assign TXD6=CPU_TXD1+~(ADD1 && ADD2 && !ADD3); //110
assign TXD7=CPU_TXD1+~(ADD1 && ADD2 && ADD3); //111
assign RTS0=CPU_RTS1+~(!ADD1 && !ADD2 && !ADD3);
assign RTS1=CPU_TXD1+~(!ADD1 && !ADD2 && ADD3);
assign RTS2=CPU_TXD1+~(!ADD1 && ADD2 && !ADD3);
assign RTS3=CPU_TXD1+~(!ADD1 && ADD2 && ADD3);
assign RTS4=CPU_TXD1+~( ADD1 && !ADD2 && !ADD3);
assign RTS5=CPU_TXD1+~(ADD1 && !ADD2 && ADD3);
assign RTS6=CPU_TXD1+~(ADD1 && ADD2 && !ADD3);
assign RTS7=CPU_TXD1+~(ADD1 && ADD2 && ADD3);
endmodule
|
module alucontrol(input [1:0] aluop, // alu op code
input [5:0] funct, // function code
output reg [2:0] alucontrol // generated control signals for the ALU
);
// FUNCT field definitions
parameter ADD = 6'b100000;
parameter SUB = 6'b100010;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter SLT = 6'b101010;
// The Synopsys full_case directives are given on each statement to tell the
// synthezizer that all the cases we care about are handled. This avoids
// needing a default that takes extra logic gate or implying a latch.
always @(*)
case (aluop) // synopsys full_case
2'b00: alucontrol = 3'b010; // add (for lb/sb/addi)
2'b01: alucontrol = 3'b110; // sub (for beq)
2'b10: case (funct) // synopsys full_case
ADD: alucontrol = 3'b010; // add (for add)
SUB: alucontrol = 3'b110; // sub (for sub)
AND: alucontrol = 3'b000; // logical and (for and)
OR: alucontrol = 3'b001; // logical or (for or)
SLT: alucontrol = 3'b111; // set on less (for slt)
// no other functions are legal (don't care)
endcase // case (funct)
// aluop = 11 is never given (don't care)
endcase // case (aluop)
endmodule // alucontrol
|
#include <bits/stdc++.h> using namespace std; vector<int> fibton; void Fib(int n) { int x = 0, y = 1, z = 0; fibton.push_back(0); for (int i = 0; i <= n; i++) { z = x + y; fibton.push_back(z); if (fibton[fibton.size() - 1] >= n) { break; } x = y; y = z; } } int main() { int n; cin >> n; Fib(n); for (int i = 0; i < fibton.size(); i++) { for (int j = i; j < fibton.size(); j++) { for (int k = j; k < fibton.size(); k++) { if ((fibton[i] + fibton[j] + fibton[k]) == n) { cout << fibton[i] << << fibton[j] << << fibton[k]; return 0; } } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_BLACKBOX_V
|
module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD, input [31:0] MEMDAT, output [7:0] MEMADD, output MFA,READ_WRITE,WORD_BYTE);
wire[31:0] IR;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;
wire [3:0] SRIN, _SRIN,SROUT;
wire SR29_OUT,S;
wire[31:0] _B;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SROUT);
always@(IR or CU)
begin
RSLCT = {CU,IR[15:8],IR[3:0], IR[19:16]};
end
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
//assign S = IR[20]&SRENABLED;
assign _SRIN = {SROUT[3],SR29_OUT,SROUT[1],SROUT[0]};
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,_B, opcode, _SRIN, Out,SRIN,IR[20],ALUSTORE);
//BarrelShifter(input [31] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,SROUT[3],SR29_OUT,_B);
//IR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register IRR( .IN(Out),
.Clk(Clk),
.Reset(Reset),
.Load(IRLOAD),
.OUT(IR));
//MBR
//Register2Buff(inout [31:0] IN,IN2,input Clk, Reset,Load,Load2,Store,Store2);
Register2Buff register(
.IN(Out),
.IN2(MEMDAT),
.Clk(Clk),
.Reset(Reset),
.Load(MBRLOAD),
.Load2(MEMLOAD),
.Store(MBRSTORE),
.Store2(MEMSTORE));
//MAR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register MAR( .IN(Out),
.Clk(Clk),
.Reset(Reset),
.Load(MARLOAD),
.OUT(MEMADD));
//SR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register SR( .IN(SRIN),
.Clk(Clk),
.Reset(Reset),
.Load(1),
.OUT(SROUT));
endmodule
//iverilog ARM_ALU.v BarrelShifter.v Buffer32_32.v controlunit2.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU.v |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__OR4B_FUNCTIONAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_FUNCTIONAL_V |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:19:07 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemTextures/MemTextures_stub.v
// Design : MemTextures
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module MemTextures(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[7:0],clk,spo[91:0]" */;
input [7:0]a;
input clk;
output [91:0]spo;
endmodule
|
#include <bits/stdc++.h> using namespace std; int fa[101000][20], h[101000], lev[101000], ans[101000]; int dp[101000]; struct EDGE { int to, nxt; } box[2 * 101000]; int top, K; void add(int u, int v) { box[top].to = v; box[top].nxt = h[u]; h[u] = top++; } void DFS(int u, int pre, int t) { lev[u] = lev[pre] + 1; fa[u][0] = pre; if (!t) for (int i = 1; i < 20; i++) fa[u][i] = fa[fa[u][i - 1]][i - 1]; for (int p = h[u]; p != -1; p = box[p].nxt) { int v = box[p].to; if (pre == v) continue; DFS(v, u, t); if (t) { dp[u] += dp[v]; ans[p / 2] = dp[v]; } } } int lca(int u, int v) { if (lev[u] < lev[v]) swap(u, v); int c = lev[u] - lev[v]; for (int i = 19; i >= 0; i--) { if (c & (1 << i)) { u = fa[u][i]; c -= (1 << i); } } if (u == v) return u; for (int i = 19; i >= 0; i--) { if (fa[u][i] != fa[v][i]) { u = fa[u][i]; v = fa[v][i]; } } return fa[u][0]; } int main() { int n, k; int a, b; scanf( %d , &n); memset(h, -1, sizeof(h)); for (int i = 1; i < n; i++) { scanf( %d%d , &a, &b); add(a, b); add(b, a); } DFS(1, 1, 0); scanf( %d , &k); for (int i = 0; i < k; i++) { scanf( %d%d , &a, &b); int c = lca(a, b); dp[a]++; dp[b]++; dp[c] -= 2; } DFS(1, 1, 1); for (int i = 0; i < n - 1; i++) { printf( %d%c , ans[i], i == n - 2 ? n : ); } } |
#include <bits/stdc++.h> using namespace std; void fastio() { ios_base::sync_with_stdio(false); cin.tie(NULL); } long long fre[1000000]; int32_t main() { fastio(); long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (long long i = 0; i < n; i++) { for (long long j = i + 1; j < n; j++) { fre[a[i] + a[j]]++; } } long long ans = 0; for (long long i = 0; i < 1000000; i++) { ans = max(ans, fre[i]); } cout << ans; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_stub.v
// Design : affine_block_ieee754_fp_adder_subtractor_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_adder_subtractor,Vivado 2016.4" *)
module affine_block_ieee754_fp_adder_subtractor_0_1(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; int T, n, m, a[N], b[N], cnt, res[N << 1], v[N << 1], t, c[N << 1], pr[N], sf[N], p[N]; long long ans; void add(int x, int y) { for (int i = x; i; i -= i & (-i)) c[i] += y; } int query(int x) { int ans = 0; for (int i = x; i <= t; i += i & (-i)) ans += c[i]; return ans; } void solve(int l, int r, int nl, int nr) { if (l > r || nl > nr) return; int mid = (l + r) / 2, ans = 1e9; pr[nl - 1] = sf[nr + 1] = 0; for (int i = nl; i <= nr; i++) pr[i] = pr[i - 1] + (a[i] > b[mid]); for (int i = nr; i >= nl; i--) sf[i] = sf[i + 1] + (a[i] < b[mid]); for (int i = nl; i <= nr; i++) if (ans > pr[i - 1] + sf[i]) ans = pr[i - 1] + sf[i], p[mid] = i; solve(l, mid - 1, nl, p[mid]), solve(mid + 1, r, p[mid], nr); } signed main() { scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m), cnt = ans = 0; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= m; i++) scanf( %d , &b[i]); sort(b + 1, b + 1 + m), solve(1, m + 1, 1, n + 1); for (int i = 1, j = 1; i <= n + 1; i++) { while (j <= m && p[j] <= i) res[++cnt] = b[j], j++; if (i <= n) res[++cnt] = a[i]; } for (int i = 1; i <= cnt; i++) v[i] = res[i]; sort(v + 1, v + 1 + cnt), t = unique(v + 1, v + 1 + cnt) - v - 1, fill(c + 1, c + 1 + t, 0); for (int i = 1; i <= cnt; i++) { res[i] = lower_bound(v + 1, v + 1 + t, res[i]) - v; ans += query(res[i] + 1), add(res[i], 1); } printf( %lld n , ans); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLRTN_PP_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, m, k; cin >> n >> m >> k; k = n * m / 2 - k; if (n % 2 == 1) { swap(n, m); k = n * m / 2 - k; } if (m % 2 == 1) { if ((k >= n / 2 && (k - n / 2) % (2) == 0)) { cout << YES << n ; continue; } else { cout << NO << n ; continue; } } else { if (k % 2 == 0) cout << YES << n ; else cout << NO << n ; } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t;
sub a (.inst(1));
sub b (.inst(2));
// Returns integer line number, or -1 for all ok
import "DPI-C" context function int dpix_run_tests();
export "DPI-C" task dpix_t_int;
task dpix_t_int(input int i, output int o); o = ~i; endtask
export "DPI-C" dpix_t_renamed = task dpix_t_ren;
task dpix_t_ren(input int i, output int o); o = i+2; endtask
export "DPI-C" function dpix_int123;
function int dpix_int123(); dpix_int123 = 32'h123; endfunction
export "DPI-C" function dpix_f_bit;
export "DPI-C" function dpix_f_bit15;
export "DPI-C" function dpix_f_int;
export "DPI-C" function dpix_f_byte;
export "DPI-C" function dpix_f_shortint;
export "DPI-C" function dpix_f_longint;
export "DPI-C" function dpix_f_chandle;
function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction
function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction
function int dpix_f_int (int i); dpix_f_int = ~i; endfunction
function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction
function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction
function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction
function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction
export "DPI-C" task dpix_t_bit95;
task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask
export "DPI-C" task dpix_t_bit96;
task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask
int lineno;
initial begin
lineno = dpix_run_tests();
if (lineno != -1) begin
$display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input int inst);
export "DPI-C" function dpix_sub_inst;
function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "viterbidec.v"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 410, MOD = 10007; char s[maxn]; int n, m, mat_s; typedef long long Mat[maxn][maxn]; void print(Mat A) { for (int i = 0; i < (mat_s); i++) { for (int j = 0; j < (mat_s); j++) { cout << A[i][j] << ; } cout << endl; } cout << endl; } void mat_mul(Mat A, Mat B, Mat res) { static Mat C; memset(C, 0, sizeof(C)); for (int i = 0; i < (mat_s); i++) for (int k = (i); k <= (mat_s - 1); k++) for (int j = (k); j <= (mat_s - 1); j++) { C[i][j] += A[i][k] * B[k][j]; } for (int i = 0; i < (mat_s); i++) for (int j = 0; j < (mat_s); j++) { C[i][j] %= MOD; } memcpy(res, C, sizeof(C)); } void mat_pow(Mat A, long long k, Mat res) { static Mat a, r; memcpy(a, A, sizeof(a)); memset(r, 0, sizeof(r)); for (int i = 0; i < (mat_s); i++) r[i][i] = 1; while (k) { if (k & 1) { mat_mul(r, a, r); } if (!(k >>= 1)) { break; } mat_mul(a, a, a); } memcpy(res, r, sizeof(r)); } int dp[210][210][210]; int rec(int l, int r, int n24) { int& res = dp[l][r][n24]; if (~res) { return res; } if (l == r) { return res = !n24; } if (s[l] == s[r]) { if (l + 1 == r) { return res = !n24; } return res = rec(l + 1, r - 1, n24); } else { if (n24 > 0) { return res = (rec(l + 1, r, n24 - 1) + rec(l, r - 1, n24 - 1)) % MOD; } else { return res = 0; } } } int n24, n25, n26, times; int mat_at(Mat A, int c24, int c25) { int i24 = n24 - c24; int i25 = n24 + c25 - 1; int i26 = i25 + n25; return A[i24][i26]; } int main() { scanf( %s%d , s, &n); m = strlen(s); n += m; times = (n + 1) >> 1; n24 = m - 1; n26 = n25 = (m + 1) >> 1; mat_s = n24 + n25 + n26; static Mat A, B; for (int i = 0; i < (mat_s); i++) { if (i < n24) { A[i][i] = 24; A[i][i + 1] = 1; } else if (i < n24 + n25) { A[i][i] = 25; if (i + 1 < n24 + n25) { A[i][i + 1] = 1; } A[i][i + n25] = 1; } else { A[i][i] = 26; } } mat_pow(A, times - 1, B); mat_mul(B, A, A); int ans = 0; memset(dp, -1, sizeof(dp)); for (int c24 = 0; c24 < (m); c24++) { int c25 = (m - c24 + 1) >> 1; if (times - c24 - c25 < 0) { continue; } int ways = rec(0, m - 1, c24); ans = (ans + ways * mat_at(A, c24, c25)) % MOD; if ((n & 1) && (!((m - c24) & 1))) { ans = (ans + MOD - ways * B[n24 - c24][n24 + c25 - 1] % MOD) % MOD; } } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND3B_PP_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[500005], inc[1002], n, q, d; vector<pair<long long, long long> > v[1002]; int main() { ios::sync_with_stdio(false); cin.tie(), cout.tie(); cin >> n >> q; d = sqrt(n); long long cnt = 1; for (int i = 1; i <= n; i++) { long long x; cin >> x; v[cnt].push_back({x, i}); if (i % d == 0) { sort(v[cnt].begin(), v[cnt].end()); cnt++; } } sort(v[cnt].begin(), v[cnt].end()); while (q--) { long long t, l, r, x; cin >> t; if (t == 1) { cin >> l >> r >> x; long long lower = ceil(l / (double)d); long long upper = ceil(r / (double)d); for (int i = 0; i < v[lower].size(); i++) { if (v[lower][i].second >= l && v[lower][i].second <= r) v[lower][i].first += x; } sort(v[lower].begin(), v[lower].end()); if (upper != lower) { for (int i = 0; i < v[upper].size(); i++) { if (v[upper][i].second >= l && v[upper][i].second <= r) v[upper][i].first += x; } sort(v[upper].begin(), v[upper].end()); } for (int i = lower + 1; i < upper; i++) inc[i] += x; } else { cin >> x; long long l = 1e18, r = -1e18; for (int i = 1; i <= cnt; i++) { x -= inc[i]; if (v[i].size() == 0) continue; long long lo = 0, hi = v[i].size() - 1; while (lo <= hi) { long long mid = (lo + hi) / 2; if (v[i][mid].first == x) { l = min(l, v[i][mid].second); hi = mid - 1; } else if (v[i][mid].first > x) hi = mid - 1; else lo = mid + 1; } lo = 0, hi = v[i].size() - 1; while (lo <= hi) { long long mid = (lo + hi) / 2; if (v[i][mid].first == x) { r = max(r, v[i][mid].second); lo = mid + 1; } else if (v[i][mid].first > x) hi = mid - 1; else lo = mid + 1; } x += inc[i]; } if (l == 1e18) cout << -1 << endl; else cout << r - l << endl; } } } |
//==================================================================================================
// Filename : memory_bram_dp.v
// Created On : 2014-09-24 20:12:03
// Last Modified : 2015-05-28 09:43:51
// Revision :
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Block RAM used for the Internal Memory
// WARNING: registered input address. Latency: 1 cycle.
//==================================================================================================
module memory_bram_dp #(
parameter data_size = 8, // Default: 8 bits
parameter addr_size = 8 // Default: 256 lines
)(
// Port A
input a_clk, // Port A clock
input a_wr, // 1 = write. 0 = Read
input [addr_size-1:0] a_addr, // Address
input [data_size-1:0] a_din, // Input data
output reg [data_size-1:0] a_dout, // Output data
// Port B
input b_clk, // Port A clock
input b_wr, // 1 = write. 0 = Read
input [addr_size-1:0] b_addr, // Address
input [data_size-1:0] b_din, // Input data
output reg [data_size-1:0] b_dout // Output data
);
//--------------------------------------------------------------------------
// Memory
//--------------------------------------------------------------------------
reg [data_size-1:0] mem [0:(2**addr_size)-1];
//--------------------------------------------------------------------------
// Port A
//--------------------------------------------------------------------------
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
//--------------------------------------------------------------------------
// Port B
//--------------------------------------------------------------------------
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module sig_337p(
input [6:0] t,
output reg [7:0] y
);
reg [6:0] temp;
reg [7:0] s;
reg [26:0] p;
always@(*) begin
if(t[6] == 1)
temp = ~t + 1'b1;
else
temp = t;
p[0] = temp[5] & temp[2];
p[1] = temp[5] & temp[4];
p[2] = temp[5];
p[3] = temp[5] & temp[3];
p[4] = temp[4] & ~temp[3] & ~temp[2] & ~temp[1] & ~temp[0];
p[5] = ~temp[4] & temp[3] & ~temp[2] & ~temp[1] & ~temp[0];
p[6] = ~temp[4] & ~temp[3] & temp[2] & temp[1] & ~temp[0];
p[7] = temp[3] & ~temp[2] & temp[1] & ~temp[0];
p[8] = temp[4] & temp[3] & temp[1] & temp[0];
p[9] = temp[4] & ~temp[3] & temp[1] & temp[0];
p[10] = temp[4] & temp[2] & temp[1];
p[11] = ~temp[4] & temp[3] & temp[1] & temp[0];
p[12] = temp[3] & temp[2] & temp[1];
p[13] = temp[3] & ~temp[1] & temp[0];
p[14] = temp[4] & temp[2] & temp[0];
p[15] = temp[4] & ~temp[3] & ~temp[2] & temp[1];
p[16] = ~temp[4] & ~temp[3] & ~temp[2] & temp[1];
p[17] = ~temp[4] & temp[3] & temp[2];
p[18] = temp[4] & temp[3] & temp[2];
p[19] = ~temp[3] & temp[2];
p[20] = ~temp[4] & temp[2] & temp[1] & temp[0];
p[21] = ~temp[4] & temp[2] & ~temp[1] & temp[0];
p[22] = temp[4] & ~temp[3] & temp[2] & ~temp[1];
p[23] = temp[4] & ~temp[2] & ~temp[1] & temp[0];
p[24] = ~temp[4] & ~temp[3] & ~temp[2] & temp[0];
p[25] = temp[4] & temp[3];
p[26] = temp[4] & temp[3] & ~temp[2] & ~temp[0];
s[7] = 1'b0;
s[6] = 1'b1;
s[5] = p[2] | p[4] | p[7] | p[9] | p[10] | p[11] | p[12] | p[13] |
p[14] | p[15] | p[17] | p[22] | p[23] | p[25];
s[4] = p[2] | p[4] | p[5] | p[9] | p[10] | p[14] | p[15] | p[19] |
p[23] | p[25];
s[3] = p[2] | p[5] | p[10] | p[12] | p[16] | p[17] | p[20] | p[25];
s[2] = p[2] | p[5] | p[6] | p[8] | p[11] | p[12] | p[15] | p[18] |
p[22] | p[24];
s[1] = p[2] | p[5] | p[6] | p[7] | p[11] | p[20] | p[21] | p[22] |
p[23] | p[26];
s[0] = p[0] | p[1] | p[3] | p[4] | p[6] | p[7] | p[9] | p[12] |
p[13] | p[14] | p[17] | p[21];
if(t[6] == 1)
y = 8'b10000000 - s;
else
y = s;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_ResetCatchAndSync(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [2:0] reset_n_catch_reg_io_d;
wire [2:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [1:0] T_6;
wire [2:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_36 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[2:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// ECC Encoder for error correction and detection memory //
// //
// //
// Description //
// Error correcting code generator //
// This module takes one word of data as input and generates //
// an error correcting code (ECC). //
// The ECC allows error detection and correction depending on //
// how it was generated and its size. //
// A write_enabled flag and an ECC are also taken as input so //
// that we can reuse this module for WRITE operations (only ECC //
// generation) and READ operations (compute difference between //
// the ECC coming from memory and the generated, aka syndrome). //
// //
// This module implements the (40,32) parity check matrix used //
// for IBM 8130. //
// Notes: this module is not parameterized because the parity //
// check matrix varies depending on input data width and //
// desired ECC width and must be 'hardcoded'. //
// Reference: Error-Correcting Codes for Semiconductor Memory //
// Applications: A State-of-the-Art Review //
// //
// Author(s): //
// - Jorge Bellon Castro, //
// - Carlos Diaz Suarez, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2014 Jorge Bellon Castro //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module edc_generator #() (
input [31:0] i_data, // Input data bus
input [7:0] i_ecc, // Input ECC (only relevant when write_enabled_i == 0)
input i_write_enabled, // Write enabled flag
output [7:0] o_ecc_syndrome // Generated ecc (write_enabled_i == 1) or Syndrome (write_enabled_i == 0)
);
wire [31:0] parity_check_matrix[0:7];
wire [7:0] generated_ecc;
// Parity check matrix definition
generate
// Parity check matrix
assign parity_check_matrix[7] = 40'b10101010_10101010_11000000_11000000;//10000000;
assign parity_check_matrix[6] = 40'b01010101_01010101_00110000_00110000;//01000000;
assign parity_check_matrix[5] = 40'b11111111_00000000_00001100_00001100;//00100000;
assign parity_check_matrix[4] = 40'b00000000_11111111_00000011_00000011;//00010000;
assign parity_check_matrix[3] = 40'b11000000_11000000_11111111_00000000;//00001000;
assign parity_check_matrix[2] = 40'b00110000_00110000_00000000_11111111;//00000100;
assign parity_check_matrix[1] = 40'b00001100_00001100_10101010_10101010;//00000010;
assign parity_check_matrix[0] = 40'b00000011_00000011_01010101_01010101;//00000001;
endgenerate
// ECC computation
genvar r,c;
generate
for (r=0; r<8; r=r+1) begin
// Compute the ECC as the 'sum-product' of all elements of the row by the elements of the word
// Product: logic AND; Sum (mod 2): logic XOR
assign generated_ecc[r] = ( ^ ( parity_check_matrix[r] & i_data ));
// Return either difference (XOR) between generated ecc and input ecc or just the generated one
// depending if we are performing a READ operation (first case) or a WRITE (second case).
assign o_ecc_syndrome[r] = i_write_enabled ? generated_ecc[r] : generated_ecc[r] ^ i_ecc[r];
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> vv; int main() { int t, n, x, c1, c2; scanf( %d , &t); vv.clear(); c1 = c2 = 0; for (int i = 0; i < t; i++) { scanf( %d , &n); for (int j = 0; j < n / 2; j++) { scanf( %d , &x); c1 += x; } if (n % 2) { scanf( %d , &x); vv.push_back(x); } for (int j = 0; j < n / 2; j++) { scanf( %d , &x); c2 += x; } } sort(vv.begin(), vv.end()); int flag = 1; for (int i = vv.size() - 1; i >= 0; i--) { if (flag == 1) c1 += vv[i]; else c2 += vv[i]; flag = -flag; } printf( %d %d n , c1, c2); return 0; } |
module memory(
// input
i_clk, i_reset_n,
i_address, i_write, i_read, i_writedata,
// output
o_readdata, o_waitrequest
);
input wire i_clk;
input wire i_reset_n;
input wire [17:0] i_address;
input wire i_write;
input wire i_read;
input wire [35:0] i_writedata;
output wire [35:0] o_readdata;
output wire o_waitrequest;
reg [35:0] mem[0:'o40000-1];
wire addrok = i_address[17:14] == 0;
wire [13:0] addr = i_address[13:0];
wire [35:0] memword = addrok ? mem[addr] : 0;
always @(posedge i_clk or negedge i_reset_n) begin
if(~i_reset_n) begin
end else begin
if(i_write & addrok) begin
mem[addr] <= i_writedata;
end
end
end
assign o_readdata = i_read ? memword : 0;
assign o_waitrequest = 0;
endmodule
module dlymemory(
// input
i_clk, i_reset_n,
i_address, i_write, i_read, i_writedata,
// output
o_readdata, o_waitrequest
);
input wire i_clk;
input wire i_reset_n;
input wire [17:0] i_address;
input wire i_write;
input wire i_read;
input wire [35:0] i_writedata;
output wire [35:0] o_readdata;
output wire o_waitrequest;
reg [35:0] mem[0:'o40000-1];
wire addrok = i_address[17:14] == 0;
wire [13:0] addr = i_address[13:0];
wire [35:0] memword = addrok ? mem[addr] : 0;
wire write_edge, read_edge;
reg [3:0] dly;
wire ready = dly == 0;
edgedet e0(i_clk, i_reset_n, i_write, write_edge);
edgedet e1(i_clk, i_reset_n, i_read, read_edge);
always @(posedge i_clk or negedge i_reset_n) begin
if(~i_reset_n) begin
dly <= 4;
end else begin
if(i_write & ready & addrok) begin
mem[addr] <= i_writedata;
end
if(~(i_write | i_read))
dly <= 4;
else if(dly)
dly <= dly - 1;
end
end
assign o_readdata = i_read ? memword : 0;
assign o_waitrequest = ~ready;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_controller_wb.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Wishbone interface responsible for comunication with core ////
//// ////
//// Author(s): ////
//// - Marek Czerski, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson () ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_controller_wb(
// WISHBONE slave
wb_clk_i,
wb_rst_i,
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
cmd_start,
data_int_rst,
cmd_int_rst,
argument_reg,
command_reg,
response_0_reg,
response_1_reg,
response_2_reg,
response_3_reg,
software_reset_reg,
cmd_timeout_reg,
data_timeout_reg,
block_size_reg,
controll_setting_reg,
cmd_int_status_reg,
cmd_int_enable_reg,
clock_divider_reg,
block_count_reg,
dma_addr_reg,
data_int_status_reg,
data_int_enable_reg
);
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output reg [31:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
input [7:0] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output reg wb_ack_o; // WISHBONE acknowledge output
output reg cmd_start;
//Buss accessible registers
output [31:0] argument_reg;
output [`CMD_REG_SIZE-1:0] command_reg;
input wire [31:0] response_0_reg;
input wire [31:0] response_1_reg;
input wire [31:0] response_2_reg;
input wire [31:0] response_3_reg;
output [0:0] software_reset_reg;
output [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
output [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
output [`BLKSIZE_W-1:0] block_size_reg;
output [0:0] controll_setting_reg;
input wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
output [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
output [7:0] clock_divider_reg;
input wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
output [`INT_DATA_SIZE-1:0] data_int_enable_reg;
//Register Controll
output reg data_int_rst;
output reg cmd_int_rst;
output [`BLKCNT_W-1:0]block_count_reg;
output [31:0] dma_addr_reg;
wire we;
parameter voltage_controll_reg = `SUPPLY_VOLTAGE_mV;
parameter capabilies_reg = 16'b0000_0000_0000_0000;
assign we = (wb_we_i && ((wb_stb_i && wb_cyc_i) || wb_ack_o)) ? 1'b1 : 1'b0;
byte_en_reg #(32) argument_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `argument, wb_sel_i, wb_dat_i, argument_reg);
byte_en_reg #(`CMD_REG_SIZE) command_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `command, wb_sel_i[(`CMD_REG_SIZE-1)/8:0], wb_dat_i[`CMD_REG_SIZE-1:0], command_reg);
byte_en_reg #(1) reset_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `reset, wb_sel_i[0], wb_dat_i[0], software_reset_reg);
byte_en_reg #(`CMD_TIMEOUT_W) cmd_timeout_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `cmd_timeout, wb_sel_i[(`CMD_TIMEOUT_W-1)/8:0], wb_dat_i[`CMD_TIMEOUT_W-1:0], cmd_timeout_reg);
byte_en_reg #(`DATA_TIMEOUT_W) data_timeout_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `data_timeout, wb_sel_i[(`DATA_TIMEOUT_W-1)/8:0], wb_dat_i[`DATA_TIMEOUT_W-1:0], data_timeout_reg);
byte_en_reg #(`BLKSIZE_W, `RESET_BLOCK_SIZE) block_size_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `blksize, wb_sel_i[(`BLKSIZE_W-1)/8:0], wb_dat_i[`BLKSIZE_W-1:0], block_size_reg);
byte_en_reg #(1) controll_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `controller, wb_sel_i[0], wb_dat_i[0], controll_setting_reg);
byte_en_reg #(`INT_CMD_SIZE) cmd_int_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `cmd_iser, wb_sel_i[(`INT_CMD_SIZE-1)/8:0], wb_dat_i[`INT_CMD_SIZE-1:0], cmd_int_enable_reg);
byte_en_reg #(8) clock_d_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `clock_d, wb_sel_i[0], wb_dat_i[7:0], clock_divider_reg);
byte_en_reg #(`INT_DATA_SIZE) data_int_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `data_iser, wb_sel_i[(`INT_DATA_SIZE-1)/8:0], wb_dat_i[`INT_DATA_SIZE-1:0], data_int_enable_reg);
byte_en_reg #(`BLKCNT_W) block_count_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `blkcnt, wb_sel_i[(`BLKCNT_W-1)/8:0], wb_dat_i[`BLKCNT_W-1:0], block_count_reg);
byte_en_reg #(32) dma_addr_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `dst_src_addr, wb_sel_i[3:0], wb_dat_i, dma_addr_reg);
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)begin
wb_ack_o <= 0;
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
end
else
begin
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
if ((wb_stb_i & wb_cyc_i) || wb_ack_o)begin
if (wb_we_i) begin
case (wb_adr_i)
`argument: cmd_start <= 1;//only msb triggers xfer
`cmd_isr: cmd_int_rst <= 1;
`data_isr: data_int_rst <= 1;
endcase
end
wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
end
end
always @(posedge wb_clk_i or posedge wb_rst_i)begin
if (wb_rst_i == 1)
wb_dat_o <= 0;
else
if (wb_stb_i & wb_cyc_i) begin //CS
case (wb_adr_i)
`argument: wb_dat_o <= argument_reg;
`command: wb_dat_o <= command_reg;
`resp0: wb_dat_o <= response_0_reg;
`resp1: wb_dat_o <= response_1_reg;
`resp2: wb_dat_o <= response_2_reg;
`resp3: wb_dat_o <= response_3_reg;
`controller: wb_dat_o <= controll_setting_reg;
`blksize: wb_dat_o <= block_size_reg;
`voltage: wb_dat_o <= voltage_controll_reg;
`reset: wb_dat_o <= software_reset_reg;
`cmd_timeout: wb_dat_o <= cmd_timeout_reg;
`data_timeout: wb_dat_o <= data_timeout_reg;
`cmd_isr: wb_dat_o <= cmd_int_status_reg;
`cmd_iser: wb_dat_o <= cmd_int_enable_reg;
`clock_d: wb_dat_o <= clock_divider_reg;
`capa: wb_dat_o <= capabilies_reg;
`data_isr: wb_dat_o <= data_int_status_reg;
`blkcnt: wb_dat_o <= block_count_reg;
`data_iser: wb_dat_o <= data_int_enable_reg;
`dst_src_addr: wb_dat_o <= dma_addr_reg;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 6031) #pragma warning(disable : 4101) using namespace std; const int INF = 1e9; const long long LINF = 1e18; const double PI = acos(-1); const int MAXN = 1000006; int n, m, v1, v2, Deg[MAXN], visited[MAXN]; vector<unordered_set<int>> G; vector<int> C; set<pair<int, int>> erased; void find_component(int v) { visited[v] = true; C.push_back(v); for (int c : G[v]) { if (!visited[c]) { find_component(c); } } } void eulerian_cycle(int v) { stack<int> S; vector<int> ans; S.push(v); while (!S.empty()) { int s = S.top(); if (G[s].empty()) { ans.push_back(s); S.pop(); } else { int c = *G[s].begin(); G[s].erase(G[s].begin()); G[c].erase(s); S.push(c); } } int ans_size = ((int)(ans).size()); for (int i = 1; i < ((int)(ans).size()); i += 2) { if (ans[i] != 0 && ans[i + 1] != 0) { if (ans[i - 1] != 0 && ans[(i + 2) % ans_size] != 0) { if (ans[i] < ans[i + 1]) { erased.erase({ans[i], ans[i + 1]}); } else { erased.erase({ans[i + 1], ans[i]}); } } } } } int main() { scanf( %d%d , &n, &m); G.resize(n + 1); while (m--) { scanf( %d%d , &v1, &v2); G[v1].insert(v2); G[v2].insert(v1); if (v1 < v2) { erased.insert({v1, v2}); } else { erased.insert({v2, v1}); } Deg[v1]++; Deg[v2]++; } for (int i = 1; i <= n; i++) { if (!visited[i]) { assert(G[0].empty()); C.clear(); find_component(i); if (((int)(C).size()) == 1) { continue; } for (int v : C) { if (Deg[v] % 2 == 1) { G[0].insert(v); G[v].insert(0); } } eulerian_cycle(C.front()); } } printf( %d n , ((int)(erased).size())); for (pair<int, int> p : erased) { printf( %d %d n , p.first, p.second); } return 0; } |
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
/* fdisplay1 - test $fwrite and $fdisplay system tasks without using $fopen
*
* NB: this may need a little tweaking, as I'm not sure that all verilogs
* have the predefined $fdisplay descriptors 2 and 3 matching what
* vpi_mcd_printf provides.
*/
module fdisplay1;
integer fp;
reg [7:0] a;
initial begin
$display("message to stdout (from $display)\n");
$fwrite(1, "another message (via fwrite) ");
$fdisplay(1,"to stdout\n (via fdisplay)");
#5
a = 8'h5a;
$fwrite(1, "a = %b at %0t\n", a, $time);
$finish(0);
end // initial begin
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_SYMBOL_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlpsleep (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n, m, c; cin >> n >> m >> c; vector<int> a(n), b(m); for (int i = 0; i < n; i++) cin >> a[i]; for (int j = 0; j < m; j++) cin >> b[j]; vector<int> beg(n); beg.assign(n, 0); vector<int> start(n), end(n); start.assign(n, 0); end.assign(n, 0); int max; if (n >= 2 * m) { for (int i = 0; i < m; ++i) { beg[i] = i + 1; start[i] = 0; end[i] = start[i] + beg[i]; } for (int i = m; i < n - m + 1; ++i) { beg[i] = m; start[i] = 0; end[i] = start[i] + beg[i]; } for (int i = n - m + 1; i < n; ++i) { beg[i] = n - i; start[i] = start[i - 1] + 1; end[i] = start[i] + beg[i]; } } else { for (int i = 0; i < n - m + 1; ++i) { beg[i] = i + 1; start[i] = 0; end[i] = start[i] + beg[i]; } for (int i = n - m + 1; i < m; ++i) { beg[i] = n - m + 1; start[i] = start[i - 1] + 1; end[i] = start[i] + beg[i]; } for (int i = m; i < n; ++i) { beg[i] = n - i; start[i] = start[i - 1] + 1; end[i] = start[i] + beg[i]; } } for (int i = 0; i < n; ++i) { for (int j = start[i]; j < end[i]; ++j) a[i] = (a[i] + b[j]) % c; cout << a[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char s[100000]; int n, m, x, y, i, sol, v[501][501]; int main() { cin >> n >> m >> x >> y; cin >> s; cout << 1 << ; int l = strlen(s); for (i = 0; i < l - 1; i++) { v[x][y] = 1; if (s[i] == R && y < m) y++; if (s[i] == L && y > 1) y--; if (s[i] == U && x > 1) x--; if (s[i] == D && x < n) x++; if (v[x][y] == 1) cout << 0 << ; else { cout << 1 << ; sol++; } } cout << n * m - sol - 1; return 0; } |
module gpio_ctrl (
clk,
reset_,
leds,
switches,
up,
down,
left,
right,
addr,
cs,
req,
rnw,
wr_data,
rd_data,
rdy
);
input clk;
input reset_;
output [7:0] leds; // 8 LEDs
input [6:0] switches; // 7 toggle switches (eighth is tied to reset_)
input up; // d-pad up
input down; // d-pad down
input left; // d-pad left
input right; // d-pad right
// This circuit provides general purpose IO control over the switches, LEDs
// and d-pad inputs. It provides three software-controllable registers,
// described below:
//
// LED control reg (read/write):
// [7:0] Each bit in this register corresponds with an LEDs state. A one
// in results in the LED assocaited with the bit position turning
// on. For example, 7'b0100_0110 reults in LEDs 1,2 and 6 on; the
// rest off.
//
// Switch control reg (read only):
// [6:0] Returns the state of each toggle switch (switch seven is
// configured as reset).
//
// D-Pad control reg (read only);
// [7] A one indicates that up was pressed. Write any value to clear.
// [6] A one indicates that down was pressed. Write any value to clear.
// [5] A one indicates that left was pressed. Write any value to clear.
// [4] A one indicates that right was pressed. Write any value to clear.
// [3] A one indicates that up was released. Write any value to clear.
// [2] A one indicates that down was released. Write any value to clear.
// [1] A one indicates that left was released. Write any value to clear.
// [0] A one indicates that right was released. Write any value to clear.
// Local IO bus
input [7:0] addr; // CPU address
input cs; // Chip select (when high, request is for this module)
input req; // CPU request
inout rnw; // Request is a read, not write.
input [7:0] wr_data; // Write data from CPU
output [7:0] rd_data; // Read data from this module to CPU
output rdy; // Ready (request is complete)
reg [7:0] dpads;
reg [7:0] leds;
reg rdy;
reg [7:0] rd_data;
wire up_debounced;
wire down_debounced;
wire left_debounced;
wire right_debounced;
wire wr_enable;
wire rd_enable;
wire up_released;
wire down_released;
wire left_released;
wire right_released;
wire up_pressed;
wire down_pressed;
wire left_pressed;
wire right_pressed;
reg [1:0] up_shift;
reg [1:0] down_shift;
reg [1:0] left_shift;
reg [1:0] right_shift;
// Software addressable registers
parameter LED_CTRL_REG = 8'd0;
parameter SWITCH_CTRL_REG = 8'd1;
parameter DPAD_CTRL_REG = 8'd2;
assign wr_enable = cs && !rnw && req;
assign rd_enable = cs && rnw && req;
// Press/release event indications
assign left_released = left_shift == 2'b10;
assign right_released = right_shift == 2'b10;
assign up_released = up_shift == 2'b10;
assign down_released = down_shift == 2'b10;
assign left_pressed = left_shift == 2'b01;
assign right_pressed = right_shift == 2'b01;
assign up_pressed = up_shift == 2'b01;
assign down_pressed = down_shift == 2'b01;
// LED control register write
always@ (posedge clk or negedge reset_)
if (!reset_)
leds <= 8'h00;
else if (addr == LED_CTRL_REG && wr_enable)
leds <= wr_data[7:0];
// Directional pad event register
always@ (posedge clk or negedge reset_)
if (!reset_)
dpads <= 8'd0;
else if (wr_enable && addr == DPAD_CTRL_REG)
dpads <= 8'd0;
else
dpads <= {dpads[7] || up_pressed,
dpads[6] || down_pressed,
dpads[5] || left_pressed,
dpads[4] || right_pressed,
dpads[3] || up_released,
dpads[2] || down_released,
dpads[1] || left_released,
dpads[0] || right_released};
// Register readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rd_data <= 8'h00;
else if (addr == LED_CTRL_REG && rd_enable)
rd_data <= leds;
else if (addr == SWITCH_CTRL_REG && rd_enable)
rd_data <= {switches[6:0], 1'b0};
else if (addr == DPAD_CTRL_REG && rd_enable)
rd_data <= dpads;
// Module ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
rdy <= 1'b0;
else
rdy <= req;
// Debounced up key shift register (to capture press/release events)
always@ (posedge clk or negedge reset_)
if (!reset_)
up_shift <= 2'd0;
else
up_shift <= {up_shift[0], up_debounced};
// Debounced down key shift register (to capture press/release events)
always@ (posedge clk or negedge reset_)
if (!reset_)
down_shift <= 2'd0;
else
down_shift <= {down_shift[0], down_debounced};
// Debounced left key shift register (to capture press/release events)
always@ (posedge clk or negedge reset_)
if (!reset_)
left_shift <= 2'd0;
else
left_shift <= {left_shift[0], left_debounced};
// Debounced right key shift register (to capture press/release events)
always@ (posedge clk or negedge reset_)
if (!reset_)
right_shift <= 2'd0;
else
right_shift <= {right_shift[0], right_debounced};
// D-pad key debouncer instantions
debouncer up_debouncer (
.clk(clk),
.reset_(reset_),
.raw(up),
.debounced(up_debounced)
);
debouncer down_debouncer (
.clk(clk),
.reset_(reset_),
.raw(down),
.debounced(down_debounced)
);
debouncer left_debouncer (
.clk(clk),
.reset_(reset_),
.raw(left),
.debounced(left_debounced)
);
debouncer right_debouncer (
.clk(clk),
.reset_(reset_),
.raw(right),
.debounced(right_debounced)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V |
module uart_system
#(
// SYSTEM_CLOCK must be set to the frequency of the sys_clk input
parameter SYSTEM_CLOCK = 144000000,
// UART_CLOCK can technically be anything that evenly divides the system clock
// but the receiving end needs to support that frequency. Standard speeds are
// 1200, 2400, 4800, 9600, 14400, 19200, 28800, 38400, 57600, and 115200
parameter UART_CLOCK = 115200,
// UART_CLOCK_MUL is the number of times the RX line is sampled, and should be
// a number 4 or larger. SYSTEM_CLOCK / (2 * UART_CLOCK * UART_CLOCK_MUL)
// must be a whole number to avoid any RX errors
parameter UART_CLOCK_MUL = 5,
// UART_INIT_DELAY specifies the number of UART_CLOCK cycles to keep the TX line
// idle after reset before sending any data. this number can probably be 0, but
// higher numbers make it easier for the other send to synchronise
parameter UART_INIT_DELAY = 200,
// STOPBITS can be 1 (1 stop bit), or 2 (2 stop bits). any other values will
// likely break things
parameter STOPBITS = 1,
// PARITY can be 0 (none), 1 (odd), or 2 (even).
parameter PARITY = 0,
// BITSIZE can be 5, 6, 7, or 8. the data buses remain 8 bits, but
// the least significant bits are used for bit sizes less than 8
parameter BITSIZE = 8
)
(
input reset_n,
input sys_clk,
output wire uart_clock,
// TX control
input [7:0] tx_data,
input tx_wren,
// RX control
input rx_accept,
output wire [7:0] rx_data,
output wire rx_data_ready,
// UART wires
input rx,
output wire tx,
// Status wires
output wire tx_led,
output wire rx_led,
output wire tx_fifo_full,
output wire rx_fifo_full
);
// These must be set to define the size of the two M9K RAM blocks
localparam RX_RAM_ADDRESS_BITS = 10;
localparam TX_RAM_ADDRESS_BITS = 10;
wire reset = ~reset_n;
wire uart_rx_clock;
uart_divider #(SYSTEM_CLOCK/(2*UART_CLOCK), UART_CLOCK_MUL) divider(
.reset(reset),
.sys_clk(sys_clk),
.outclk(uart_clock),
.outclk2(uart_rx_clock)
);
wire [7:0] tx_uart_data;
wire tx_uart_wren;
wire tx_accept;
wire [7:0] rx_uart_data;
wire rx_uart_data_ready;
uart #(UART_INIT_DELAY, UART_CLOCK_MUL, STOPBITS, PARITY, BITSIZE) u1(
.reset(reset),
.uart_clock(uart_clock),
.rx_clock(uart_rx_clock),
.tx_data(tx_uart_data),
.tx_wren(tx_uart_wren),
.tx_accept(tx_accept),
.tx(tx),
.tx_led(tx_led),
.rx_data(rx_uart_data),
.rx_data_ready(rx_uart_data_ready),
.rx(rx),
.rx_led(rx_led)
);
wire [7:0] tx_data_out;
wire tx_fifo_ram_wren;
wire [TX_RAM_ADDRESS_BITS-1:0] tx_fifo_ram_read_address;
wire [TX_RAM_ADDRESS_BITS-1:0] tx_fifo_ram_write_address;
wire [7:0] rx_data_out;
wire rx_fifo_ram_wren;
wire [RX_RAM_ADDRESS_BITS-1:0] rx_fifo_ram_read_address;
wire [RX_RAM_ADDRESS_BITS-1:0] rx_fifo_ram_write_address;
uart_fifo #(TX_RAM_ADDRESS_BITS, RX_RAM_ADDRESS_BITS) f1(
.reset(reset),
.sys_clk(sys_clk),
// FIFO input
.tx_wren(tx_wren),
.tx_data(tx_data),
.tx_out_wren(tx_uart_wren),
.tx_accept(tx_accept),
.rx_data(rx_uart_data),
.rx_data_ready(rx_uart_data_ready),
.rx_data_out_ready(rx_data_ready),
.rx_accept(rx_accept),
// TX ram
.tx_data_out(tx_data_out),
.tx_fifo_ram_read_address(tx_fifo_ram_read_address),
.tx_fifo_ram_write_address(tx_fifo_ram_write_address),
.tx_fifo_ram_wren(tx_fifo_ram_wren),
// RX ram
.rx_data_out(rx_data_out),
.rx_fifo_ram_read_address(rx_fifo_ram_read_address),
.rx_fifo_ram_write_address(rx_fifo_ram_write_address),
.rx_fifo_ram_wren(rx_fifo_ram_wren),
.tx_fifo_full(tx_fifo_full),
.rx_fifo_full(rx_fifo_full)
);
uart_fifo_dual_port_ram tx_ram(
.clock(sys_clk),
.data(tx_data_out),
.rdaddress(tx_fifo_ram_read_address),
.wraddress(tx_fifo_ram_write_address),
.wren(tx_fifo_ram_wren),
.q(tx_uart_data)
);
uart_fifo_dual_port_ram rx_ram(
.clock(sys_clk),
.data(rx_data_out),
.rdaddress(rx_fifo_ram_read_address),
.wraddress(rx_fifo_ram_write_address),
.wren(rx_fifo_ram_wren),
.q(rx_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int max_n = 3e5 + 10, inf = 1000111222; struct node { int p0, p1; int cnt; node() { p0 = p1 = 0; cnt = 0; } }; int root = 1; node A[max_n * 33]; int last_used = 1; int new_node() { return ++last_used; } int a[max_n]; long long cost_if_set[33][2]; void add_number(int a) { int cur = root; for (int i = 30; i >= 0; i--) { if (a & (1ll << i)) { if (A[cur].p0) { cost_if_set[i][0] += A[A[cur].p0].cnt; } if (!A[cur].p1) { A[cur].p1 = new_node(); } cur = A[cur].p1; A[cur].cnt++; } else { if (A[cur].p1) { cost_if_set[i][1] += A[A[cur].p1].cnt; } if (!A[cur].p0) { A[cur].p0 = new_node(); } cur = A[cur].p0; A[cur].cnt++; } } } int n; void calc_costs() { for (int i = n; i >= 1; i--) { add_number(a[i]); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } calc_costs(); long long ans = 0; int x = 0; for (int i = 0; i < 31; i++) { if (cost_if_set[i][0] <= cost_if_set[i][1]) { ans += cost_if_set[i][0]; } else { x |= (1ll << i); ans += cost_if_set[i][1]; } } cout << ans << << x << n ; } |
// part of NewGS project (c) 2007 NedoPC
//
// ramtest
module main(
clk_fpga, // clocks
clk_24mhz, //
clksel0, // clock selection
clksel1, //
warmres_n, // warm reset
d, // Z80 data bus
a, // Z80 address bus
iorq_n, // Z80 control signals
mreq_n, //
rd_n, //
wr_n, //
m1_n, //
int_n, //
nmi_n, //
busrq_n, //
busak_n, //
z80res_n, //
mema14, // memory control
mema15, //
mema16, //
mema17, //
mema18, //
ram0cs_n, //
ram1cs_n, //
ram2cs_n, //
ram3cs_n, //
romcs_n, //
memoe_n, //
memwe_n, //
zxid, // zxbus signals
zxa, //
zxa14, //
zxa15, //
zxiorq_n, //
zxmreq_n, //
zxrd_n, //
zxwr_n, //
zxcsrom_n, //
zxblkiorq_n, //
zxblkrom_n, //
zxgenwait_n, //
zxbusin, //
zxbusena_n, //
dac_bitck, // audio-DAC signals
dac_lrck, //
dac_dat, //
sd_clk, // SD card interface
sd_cs, //
sd_do, //
sd_di, //
sd_wp, //
sd_det, //
ma_clk, // control interface of MP3 chip
ma_cs,
ma_do,
ma_di,
mp3_xreset, // data interface of MP3 chip
mp3_req, //
mp3_clk, //
mp3_dat, //
mp3_sync, //
led_diag
);
// input-output description
input clk_fpga;
input clk_24mhz;
output clksel0; reg clksel0;
output clksel1; reg clksel1;
input warmres_n;
inout [7:0] d;// reg [7:0] d;
/////////////////////////////////////////////////////////// input [15:0] a;
output [15:0] a; wire [15:0] a;
input iorq_n;
input mreq_n;
input rd_n;
input wr_n;
input m1_n;
output int_n; wire int_n;
output nmi_n; wire nmi_n;
output busrq_n; wire busrq_n;
input busak_n;
output z80res_n; reg z80res_n;
output mema14; wire mema14;
output mema15; wire mema15;
output mema16; wire mema16;
output mema17; wire mema17;
output mema18; wire mema18;
output ram0cs_n; wire ram0cs_n;
output ram1cs_n; wire ram1cs_n;
output ram2cs_n; wire ram2cs_n;
output ram3cs_n; wire ram3cs_n;
output romcs_n; wire romcs_n;
output memoe_n; wire memoe_n;
output memwe_n; wire memwe_n;
inout [7:0] zxid; wire [7:0] zxid;
input [7:0] zxa;
input zxa14;
input zxa15;
input zxiorq_n;
input zxmreq_n;
input zxrd_n;
input zxwr_n;
input zxcsrom_n;
output zxblkiorq_n; wire zxblkiorq_n;
output zxblkrom_n; wire zxblkrom_n;
output zxgenwait_n; wire zxgenwait_n;
output zxbusin; wire zxbusin;
output zxbusena_n; wire zxbusena_n;
output dac_bitck; wire dac_bitck;
output dac_lrck; wire dac_lrck;
output dac_dat; wire dac_dat;
output sd_clk; wire sd_clk;
output sd_cs; wire sd_cs;
output sd_do; wire sd_do;
input sd_di;
input sd_wp;
input sd_det;
output ma_clk; wire ma_clk;
output ma_cs; wire ma_cs;
output ma_do; wire ma_do;
input ma_di;
output mp3_xreset; wire mp3_xreset;
input mp3_req;
output mp3_clk; wire mp3_clk;
output mp3_dat; wire mp3_dat;
output mp3_sync; wire mp3_sync;
output led_diag;
always @* clksel0 <= 1'b0;
always @* clksel1 <= 1'b0;
always @* z80res_n <= 1'b0;
assign busrq_n = 1'b1;
assign int_n = 1'b1;
assign nmi_n = 1'b1;
assign romcs_n = 1'b1;
assign zxid=8'bZZZZZZZZ;
assign zxblkrom_n=1'b1;
assign zxgenwait_n=1'b1;
assign zxbusin=1'b1;
assign zxbusena_n=1'b1;
assign dac_bitck = 1'b1;
assign dac_lrck = 1'b1;
assign dac_dat = 1'b1;
assign sd_clk = 1'b0;
assign sd_cs = 1'b1;
assign sd_do = 1'b0;
assign ma_clk = 1'b0;
assign ma_cs = 1'b1;
assign ma_do = 1'b0;
assign mp3_xreset = 1'b0;
assign mp3_clk = 1'b0;
assign mp3_dat = 1'b0;
assign mp3_sync= 1'b0;
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
wire rst_zx = (zxa[7:0]==8'h33) & (~zxiorq_n) & (~zxwr_n);
assign zxblkiorq_n = ~(zxa[7:0]==8'h33);
wire rst_n;
resetter myreset( .clk(clk_fpga), .rst_in_n( warmres_n & (~rst_zx) ), .rst_out_n(rst_n) );
wire sel0,sel1;
wire ramce;
mem_tester mytst( .clk(clk_fpga), .rst_n(rst_n), .led(led_diag),
.SRAM_DQ(d), .SRAM_ADDR( {sel1,sel0,mema18,mema17,mema16,mema15,mema14,a[13:0]} ),
.SRAM_WE_N( memwe_n ), .SRAM_OE_N( memoe_n ), .SRAM_CE_N( ramce ) );
defparam mytst.SRAM_ADDR_SIZE = 21;
assign ram0cs_n = ( {sel1,sel0}==2'd0 )?ramce:1'b1;
assign ram1cs_n = ( {sel1,sel0}==2'd1 )?ramce:1'b1;
assign ram2cs_n = ( {sel1,sel0}==2'd2 )?ramce:1'b1;
assign ram3cs_n = ( {sel1,sel0}==2'd3 )?ramce:1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int x, y, z; cin >> x >> y >> z; if (x > y) { if (x > y + z) cout << + ; else cout << ? ; } else if (x < y) { if (y > x + z) cout << - ; else cout << ? ; } else if (z != 0) cout << ? ; else cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MIN = numeric_limits<long long>::min(); class WindowHeap { public: WindowHeap() {} long long top() { if (_i >= _h.size()) return MIN; return _h[_i].first; } void erase(int idx) { if (!_h.empty() && _h[_i].second == idx) ++_i; } void insert(long long val, int idx) { if (val == MIN) return; while (!_h.empty() && val > _h.rbegin()->first) _h.pop_back(); if (_h.empty() || val < _h.rbegin()->first) _h.emplace_back(val, idx); else _h.rbegin()->second = idx; if (_i >= _h.size()) _i = _h.size() - 1; } private: vector<pair<long long, int>> _h; size_t _i; }; int main() { int n, k, x; cin >> n >> k >> x; vector<int> a(n); for (int& ai : a) cin >> ai; vector<long long> dp(n + 1, MIN); dp[0] = 0; for (int xi = 0; xi < x; ++xi) { WindowHeap wh; for (int i = n - 1; i > max(n - k, -1); --i) { wh.insert(dp[i], i); } for (int i = n; i > xi; --i) { if (i - k >= 0) wh.insert(dp[i - k], i - k); long long p = wh.top(); if (p > MIN) dp[i] = p + a[i - 1]; wh.erase(i - 1); } dp[xi] = MIN; } long long best = -1; for (int i = n; i > n - k; --i) best = max(best, dp[i]); cout << best << endl; return 0; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Altera_UP_Video_In_Dual_Clock_FIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_up_video_dual_clock_fifo (
// Inputs
wrclk,
wrreq,
data,
rdclk,
rdreq,
// Outputs
wrusedw,
wrfull,
q,
rdusedw,
rdempty
);
parameter DW = 18;
input wrclk;
input wrreq;
input [(DW-1):0] data;
input rdclk;
input rdreq;
output [6:0] wrusedw;
output wrfull;
output [(DW-1):0] q;
output [6:0] rdusedw;
output rdempty;
dcfifo dcfifo_component (
// Inputs
.wrclk (wrclk),
.wrreq (wrreq),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (q),
.rdusedw (rdusedw),
.rdempty (rdempty)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = DW,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL data[25..0]
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL q[25..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL rdusedw[6..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; void init() { freopen( input.txt , r , stdin); } int abs(int x) { if (x < 0) { return -x; } return x; } int main() { int n, m, x1, y1, x2, y2; cin >> n >> m >> x1 >> y1 >> x2 >> y2; n = abs(x1 - x2) + 1; m = abs(y1 - y2) + 1; if ((n >= 6) || (m >= 6)) { cout << Second ; return 0; } if ((n <= 4) && (m <= 4)) { cout << First ; return 0; } if (((n == 5) || (n == 4)) && ((m == 5) || (m == 4))) { cout << Second ; return 0; } cout << First << endl; return 0; } |
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//sd_host_platform_cocotb.v
`timescale 1 ns/1 ps
module sd_dev_platform_cocotb (
input clk,
input rst,
input ddr_en,
output o_sd_clk,
output o_sd_clk_x2,
//SD Stack Interface
output reg o_locked,
input i_sd_cmd_dir,
output o_sd_cmd_in,
input i_sd_cmd_out,
input i_sd_data_dir,
output reg [7:0] o_sd_data_in,
input [7:0] i_sd_data_out,
input i_phy_clk,
inout io_phy_sd_cmd,
inout [3:0] io_phy_sd_data
);
//Local Parameters
//Registers/Wires
reg prev_clk_edge;
wire [7:0] data_out;
reg [3:0] lock_count;
wire [7:0] sd_data_in;
reg [3:0] top_nibble;
wire [3:0] in_remap;
wire [3:0] out_remap;
//Submodules
//Asynchronous Logic
reg posedge_clk;
reg negedge_clk;
assign o_sd_clk = i_phy_clk;
assign o_sd_clk_x2 = clk;
assign io_phy_sd_cmd = i_sd_cmd_dir ? i_sd_cmd_out : 1'hZ;
assign o_sd_cmd_in = io_phy_sd_cmd;
assign io_phy_sd_data= i_sd_data_dir ? data_out: 8'hZ;
assign out_remap = posedge_clk ? { i_sd_data_out[0],
i_sd_data_out[1],
i_sd_data_out[2],
i_sd_data_out[3]} :
{ i_sd_data_out[4],
i_sd_data_out[5],
i_sd_data_out[6],
i_sd_data_out[7]};
assign data_out = out_remap;
assign in_remap = { io_phy_sd_data[3],
io_phy_sd_data[2],
io_phy_sd_data[1],
io_phy_sd_data[0]};
always @ (posedge clk) begin
posedge_clk <= 0;
negedge_clk <= 0;
if (i_phy_clk && !prev_clk_edge)
posedge_clk <= 1;
if (!i_phy_clk && prev_clk_edge)
negedge_clk <= 1;
prev_clk_edge <= i_phy_clk;
end
always @ (posedge clk) begin
if (rst) begin
o_sd_data_in <= 0;
top_nibble <= 0;
end
else begin
if (negedge_clk) begin
top_nibble <= in_remap;
end
if (posedge_clk) begin
o_sd_data_in <= {top_nibble, in_remap};
end
end
end
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_locked <= 0;
lock_count <= 0;
end
else begin
if (lock_count < 4'hF) begin
lock_count <= lock_count + 1;
end
else begin
o_locked <= 1;
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_tx.v
// Version : 1.11
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcie_7x_v1_11_0_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100001]; int main() { int n, x = 0; cin >> n; for (int i = 2; i <= n; i++) { if (a[i] == 0) { x++; a[i] = x; for (int j = i; j <= n; j += i) a[j] = x; } } for (int i = 2; i <= n; i++) cout << a[i] << ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_4_V
`define SKY130_FD_SC_LS__A211O_4_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211o_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O31A_PP_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> const int MAX_N = (int)1e5 + 123; const double eps = 1e-6; const int inf = (int)1e9 + 123; using namespace std; int n; vector<int> ans[MAX_N]; int k; int main() { cin >> n; ans[1].push_back(1), ans[2].push_back(1); for (int i = 3, now = 2;; i++) { if (n - now + 1 >= i - 1) { k = i; for (int j = 1; j < i; j++) { ans[j].push_back(now); ans[i].push_back(now); now++; } } else break; } cout << k << endl; for (int i = 1; i <= k; i++) { for (auto j : ans[i]) cout << j << ; cout << endl; } return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem1x
#(
parameter DEPTH_WORDS=1,
parameter WIDTH=32,
parameter MEM_LATENCY=3, // ONLY two values are allowed: 1 and 3
parameter RDW_MODE="DONT_CARE",
parameter RAM_OPERATION_MODE = "BIDIR_DUAL_PORT", // altsyncram's OPERATION_MODE parameter
parameter RAM_BLOCK_TYPE = "AUTO" // altsyncram's RAM_BLOCK_TYPE parameter
)
(
input wire clk,
input wire resetn,
input wire [WIDTH-1:0] avs_port1_writedata,
input wire [WIDTH-1:0] avs_port2_writedata,
input wire [WIDTH/8-1:0] avs_port1_byteenable,
input wire [WIDTH/8-1:0] avs_port2_byteenable,
input wire [$clog2(DEPTH_WORDS)-1:0] avs_port1_address,
input wire [$clog2(DEPTH_WORDS)-1:0] avs_port2_address,
input wire avs_port1_read,
input wire avs_port2_read,
input wire avs_port1_write,
input wire avs_port2_write,
output logic [WIDTH-1:0] avs_port1_readdata,
output logic [WIDTH-1:0] avs_port2_readdata,
output logic avs_port1_readdatavalid,
output logic avs_port2_readdatavalid,
output logic avs_port1_waitrequest,
output logic avs_port2_waitrequest
);
localparam LOG2DEPTH = $clog2( DEPTH_WORDS );
localparam LOW_LATENCY = MEM_LATENCY < 3 ? 1 : 0;
assign avs_port1_waitrequest=1'b0;
assign avs_port2_waitrequest=1'b0;
generate
if (LOW_LATENCY)
begin
always @(posedge clk or negedge resetn)
begin
if (!resetn)
begin
avs_port1_readdatavalid <= '0;
avs_port2_readdatavalid <= '0;
end
else
begin
avs_port1_readdatavalid <= avs_port1_read;
avs_port2_readdatavalid <= avs_port2_read;
end
end
end
else
begin
_acl_mem1x_shiftreg readatavalid_1(.D(avs_port1_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port1_readdatavalid));
defparam readatavalid_1.WIDTH = 1;
defparam readatavalid_1.DEPTH = 3;
_acl_mem1x_shiftreg readatavalid_2(.D(avs_port2_read), .clock(clk), .resetn(resetn), .enable(1'b1), .Q(avs_port2_readdatavalid));
defparam readatavalid_2.WIDTH = 1;
defparam readatavalid_2.DEPTH = 3;
end
endgenerate
localparam PREFERRED_WIDTH=128;
localparam NUM_RAMS=((WIDTH+PREFERRED_WIDTH-1)/PREFERRED_WIDTH);
genvar n;
generate
for(n=0; n<NUM_RAMS; n++)
begin : block_n
localparam MY_WIDTH=( (n==NUM_RAMS-1) ? (WIDTH-(NUM_RAMS-1)*PREFERRED_WIDTH) : PREFERRED_WIDTH );
reg [MY_WIDTH-1:0] r_port1_writedata;
reg [MY_WIDTH-1:0] r_port2_writedata;
reg [MY_WIDTH/8-1:0] r_port1_byteenable;
reg [MY_WIDTH/8-1:0] r_port2_byteenable;
reg [LOG2DEPTH-1:0] r_port1_address;
reg [LOG2DEPTH-1:0] r_port2_address;
reg r_port1_write;
reg r_port2_write;
wire [MY_WIDTH-1:0] port1_readdata;
wire [MY_WIDTH-1:0] port2_readdata;
if (LOW_LATENCY)
begin
assign r_port1_writedata = avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
assign r_port2_writedata = avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
assign r_port1_byteenable = avs_port1_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
assign r_port2_byteenable = avs_port2_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
assign r_port1_address = avs_port1_address;
assign r_port2_address = avs_port2_address;
assign r_port1_write = avs_port1_write;
assign r_port2_write = avs_port2_write;
end
else
begin
always @(posedge clk or negedge resetn)
begin
if (!resetn)
begin
r_port1_writedata <= 'x;
r_port2_writedata <= 'x;
r_port1_byteenable <= 'x;
r_port2_byteenable <= 'x;
r_port1_address <= 'x;
r_port2_address <= 'x;
r_port1_write <= 1'b0;
r_port2_write <= 1'b0;
end
else
begin
r_port1_writedata <= avs_port1_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
r_port2_writedata <= avs_port2_writedata[n*PREFERRED_WIDTH +: MY_WIDTH];
r_port1_byteenable <= avs_port1_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
r_port2_byteenable <= avs_port2_byteenable[n*PREFERRED_WIDTH/8 +: MY_WIDTH/8];
r_port1_address <= avs_port1_address;
r_port2_address <= avs_port2_address;
r_port1_write <= avs_port1_write;
r_port2_write <= avs_port2_write;
end
end
end
assign avs_port1_readdata[n*PREFERRED_WIDTH +: MY_WIDTH] = port1_readdata;
assign avs_port2_readdata[n*PREFERRED_WIDTH +: MY_WIDTH] = port2_readdata;
altsyncram altsyncram_component (
.clock0 (clk),
.wren_a (r_port1_write),
.wren_b (r_port2_write),
.address_a (r_port1_address),
.address_b (r_port2_address),
.data_a (r_port1_writedata),
.data_b (r_port2_writedata),
.q_a (port1_readdata),
.q_b (port2_readdata),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (r_port1_byteenable),
.byteena_b (r_port2_byteenable),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH_WORDS,
altsyncram_component.numwords_b = DEPTH_WORDS,
altsyncram_component.operation_mode = RAM_OPERATION_MODE,
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = LOW_LATENCY ? "UNREGISTERED" : "CLOCK0",
altsyncram_component.outdata_reg_b = LOW_LATENCY ? "UNREGISTERED" : "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = RDW_MODE,
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_b = "DONT_CARE",
altsyncram_component.widthad_a = LOG2DEPTH,
altsyncram_component.widthad_b = LOG2DEPTH,
altsyncram_component.width_a = MY_WIDTH,
altsyncram_component.width_b = MY_WIDTH,
altsyncram_component.width_byteena_a = MY_WIDTH/8,
altsyncram_component.width_byteena_b = MY_WIDTH/8,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.ram_block_type = RAM_BLOCK_TYPE;
end
endgenerate
endmodule
/*********************************************************************************
* Support components
*********************************************************************************/
module _acl_mem1x_shiftreg(D, clock, resetn, enable, Q);
parameter WIDTH = 32;
parameter DEPTH = 1;
input logic [WIDTH-1:0] D;
input logic clock, resetn, enable;
output logic [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
if (!resetn)
local_ffs <= '0;
else if (enable)
local_ffs <= {local_ffs[DEPTH-2:0], D};
assign Q = local_ffs[DEPTH-1];
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.1 (win64) Build Fri Apr 14 18:55:03 MDT 2017
// Date : Tue Aug 1 10:07:10 2017
// Host : ACER-BLUES running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v
// Design : blk_mem_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.1" *)
module blk_mem_gen_0(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[7:0],clkb,enb,addrb[8:0],doutb[63:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
input clkb;
input enb;
input [8:0]addrb;
output [63:0]doutb;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int iinf = 1 << 29; const long long llinf = 1ll << 60; const double PI = 3.14159265; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); long long mrand(long long B) { return (unsigned long long)rng() % B; } long long cross(pair<long long, long long> p1, pair<long long, long long> p2) { return p1.first * p2.second - p2.first * p1.second; } bool online(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c) { pair<long long, long long> p1{b.first - a.first, b.second - a.second}; pair<long long, long long> p2{c.first - a.first, c.second - a.second}; return cross(p1, p2) == 0; } void z_func(vector<int> &z, vector<int> &s, int n) { int L = 0, R = 0; for (int i = 1; i < n; i++) { if (i > R) { L = R = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } else { int k = i - L; if (z[k] < R - i + 1) z[i] = z[k]; else { L = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } } } } const int MXN = 1e5 + 1; int n, m; bool roots[MXN]; vector<int> g[MXN]; int listt[MXN]; vector<int> ans; void fail() { cout << -1 n ; exit(0); } int dfs(int node) { int request = -1; for (auto &v : g[node]) { int req = dfs(v); if (req != -1 && request != -1 && req != request) fail(); if (req != -1) request = req; } if (request != -1 && listt[node] != request) fail(); if (request == -1) { if (listt[node] == node) { ans.push_back(node); return -1; } else { return listt[node]; } } else { if (node == listt[node]) { ans.push_back(node); return -1; } return listt[node]; } } void work() { cin >> n >> m; for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; roots[v] = true; g[u].push_back(v); } for (int i = 1; i <= n; ++i) cin >> listt[i]; for (int i = 1; i <= n; ++i) if (!roots[i]) dfs(i); cout << ((int)(ans).size()) << n ; for (auto &e : ans) cout << e << n ; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); work(); return 0; } |
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
/* $Id$ */
`timescale 1ns/1ps
module secret_flow
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2
)
(
// --- data path interface
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
`LOG2_FUNC
//--------------------- Internal Parameter-------------------------
localparam NUM_STATES = 5;
localparam PROCESS_CTRL_HDR = 1;
localparam ETH_IP_HDR = 2;
localparam FINAL_UDP_HDR = 4;
localparam PAYLOAD = 8;
localparam PAYLOAD_NO_CRYPT = 15;
localparam IP_PROTOCOL_HDR_WORD = 3;
localparam FINAL_UDP_HDR_WORD = 6;
//---------------------- Wires and regs----------------------------
reg in_fifo_rd_en;
wire [CTRL_WIDTH-1:0] in_fifo_ctrl_dout;
wire [DATA_WIDTH-1:0] in_fifo_data_dout;
wire in_fifo_nearly_full;
wire in_fifo_empty;
wire [`CPCI_NF2_DATA_WIDTH-1:0] key;
reg [NUM_STATES-1:0] state;
reg [NUM_STATES-1:0] state_next;
reg [2:0] count;
reg [2:0] count_next;
//------------------------- Modules-------------------------------
fallthrough_small_fifo #(.WIDTH(DATA_WIDTH+CTRL_WIDTH), .MAX_DEPTH_BITS(2))
input_fifo
(.din ({in_ctrl,in_data}), // Data in
.wr_en (in_wr), // Write enable
.rd_en (in_fifo_rd_en), // Read the next word
.dout ({in_fifo_ctrl_dout, in_fifo_data_dout}),
.full (),
.nearly_full (in_fifo_nearly_full),
.empty (in_fifo_empty),
.reset (reset),
.clk (clk)
);
generic_regs
#(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (`SECRET_FLOW_BLOCK_ADDR),
.REG_ADDR_WIDTH (`SECRET_FLOW_REG_ADDR_WIDTH), // Width of block addresses
.NUM_COUNTERS (0), // How many counters
.NUM_SOFTWARE_REGS (1), // How many sw regs
.NUM_HARDWARE_REGS (0) // How many hw regs
) secret_flow_regs (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- counters interface
.counter_updates (),
.counter_decrement(),
// --- SW regs interface
.software_regs (key),
// --- HW regs interface
.hardware_regs (),
.clk (clk),
.reset (reset)
);
//----------------------- Logic -----------------------------
assign in_rdy = !in_fifo_nearly_full;
always @(*) begin
out_ctrl = in_fifo_ctrl_dout;
out_data = in_fifo_data_dout;
state_next = state;
count_next = count;
out_wr = 0;
in_fifo_rd_en = 0;
if (reset) begin
state_next = PROCESS_CTRL_HDR;
count_next = 'd1;
end
else begin
case(state)
PROCESS_CTRL_HDR: begin
if (!in_fifo_empty && out_rdy) begin
out_wr = 1;
in_fifo_rd_en = 1;
if (in_fifo_ctrl_dout == 'h0) begin
state_next = ETH_IP_HDR;
count_next = count + 1;
end
end
end // case: PROCESS_CTRL_HDR
ETH_IP_HDR: begin
if (!in_fifo_empty && out_rdy) begin
out_wr = 1;
in_fifo_rd_en = 1;
count_next = count + 1;
if (count == IP_PROTOCOL_HDR_WORD) begin
// UDP protocol test
if (in_fifo_data_dout[7:0] == 8'h11) begin
state_next = FINAL_UDP_HDR;
end
else state_next = PAYLOAD_NO_CRYPT;
end
end
end // case: ETH_IP_HDR
FINAL_UDP_HDR: begin
if (!in_fifo_empty && out_rdy) begin
out_wr = 1;
in_fifo_rd_en = 1;
count_next = count + 1;
if(count == FINAL_UDP_HDR_WORD) begin
out_data[63:48] = in_fifo_data_dout[63:48];
out_data[47:0] = in_fifo_data_dout[47:0] ^ {key[15:0], key};
state_next = PAYLOAD;
end
end
end // case: FINAL_IP_HDR
PAYLOAD: begin
if (!in_fifo_empty && out_rdy) begin
out_wr = 1;
in_fifo_rd_en = 1;
// Encrypt/decrypt the data
out_data = in_fifo_data_dout ^ {key, key};
if (in_fifo_ctrl_dout != 'h0) begin
state_next = PROCESS_CTRL_HDR;
count_next = 'd1;
end
end
end // case: PAYLOAD
PAYLOAD_NO_CRYPT: begin
if (!in_fifo_empty && out_rdy) begin
out_wr = 1;
in_fifo_rd_en = 1;
out_data = in_fifo_data_dout;
if (in_fifo_ctrl_dout != 'h0) begin
state_next = PROCESS_CTRL_HDR;
count_next = 'd1;
end
end
end // case: PAYLOAD_NO_CRYPT
endcase // case(state)
end // else
end // always @ (*)
always @(posedge clk) begin
state <= state_next;
count <= count_next;
end
endmodule // secret_flow
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void solve() { long long n; cin >> n; vector<long long> a(n), b; for (long long i = 0; i < n; i++) { cin >> a[i]; } b = a; sort(b.begin(), b.end()); b.resize(unique(b.begin(), b.end()) - b.begin()); for (long long i = 0; i < n; i++) { a[i] = lower_bound(b.begin(), b.end(), a[i]) - b.begin(); } vector<long long> dp(n, -1e9); dp[a[0]] = 1; for (long long i = 1; i < n; i++) { dp[a[i]] = 1; if (a[i]) dp[a[i]] = max(dp[a[i]], dp[a[i] - 1] + 1); } long long ans = n - *max_element(dp.begin(), dp.end()); cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long q; cin >> q; while (q--) { solve(); } } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//
//-------------------------------------------------------------------
//
// Filename : example.v
// Author : Huang Lei Lei
// Created : 2014-12-08
// Description : example for rtl
//
//-------------------------------------------------------------------
`define COST_WIDTH (`PIXEL_WIDTH+12)
`include "enc_defines.v"
module ime_decision (
// cost_i
cost_NxN_00_i ,
cost_NxN_01_i ,
cost_NxN_02_i ,
cost_NxN_03_i ,
cost_2NxN_0_i ,
cost_2NxN_1_i ,
cost_Nx2N_0_i ,
cost_Nx2N_1_i ,
cost_2Nx2N_i ,
// deci_o
partition_o ,
cost_best_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// cost_i
input [`COST_WIDTH-1 : 0] cost_NxN_00_i ;
input [`COST_WIDTH-1 : 0] cost_NxN_01_i ;
input [`COST_WIDTH-1 : 0] cost_NxN_02_i ;
input [`COST_WIDTH-1 : 0] cost_NxN_03_i ;
input [`COST_WIDTH-1 : 0] cost_2NxN_0_i ;
input [`COST_WIDTH-1 : 0] cost_2NxN_1_i ;
input [`COST_WIDTH-1 : 0] cost_Nx2N_0_i ;
input [`COST_WIDTH-1 : 0] cost_Nx2N_1_i ;
input [`COST_WIDTH-1 : 0] cost_2Nx2N_i ;
// deci_o
output reg [1 : 0] partition_o ; // it's wire
output reg [`COST_WIDTH-1 : 0] cost_best_o ; // it's wire
//*** WIRE & REG DECLARATION ***************************************************
wire [`COST_WIDTH-1 : 0] cost_NxN_w ;
wire [`COST_WIDTH-1 : 0] cost_2NxN_w ;
wire [`COST_WIDTH-1 : 0] cost_Nx2N_w ;
wire [`COST_WIDTH-1 : 0] cost_2Nx2N_w ;
wire is_NxN_bt_Nx2N ;
wire is_2NxN_bt_2Nx2N ;
wire is_former_bt ;
//*** MAIN BODY ****************************************************************
assign cost_NxN_w = cost_NxN_00_i + cost_NxN_01_i + cost_NxN_02_i + cost_NxN_03_i ;
assign cost_Nx2N_w = cost_Nx2N_0_i + cost_Nx2N_1_i ;
assign cost_2NxN_w = cost_2NxN_0_i + cost_2NxN_1_i ;
assign cost_2Nx2N_w = cost_2Nx2N_i ;
assign is_NxN_bt_Nx2N = cost_NxN_w < cost_Nx2N_w ;
assign is_2NxN_bt_2Nx2N = cost_2NxN_w < cost_2Nx2N_w ;
assign is_former_bt = ( is_NxN_bt_Nx2N ? cost_NxN_w : cost_Nx2N_w )
< ( is_2NxN_bt_2Nx2N ? cost_2NxN_w : cost_2Nx2N_w );
always @(*) begin
casex( {is_former_bt, is_NxN_bt_Nx2N ,is_2NxN_bt_2Nx2N} )
3'b0x0 : begin partition_o = 2'b00 ; cost_best_o = cost_2Nx2N_w ; end
3'b0x1 : begin partition_o = 2'b01 ; cost_best_o = cost_2NxN_w ; end
3'b10x : begin partition_o = 2'b10 ; cost_best_o = cost_Nx2N_w ; end
3'b11x : begin partition_o = 2'b11 ; cost_best_o = cost_NxN_w ; end
default : begin partition_o = 2'b00 ; cost_best_o = cost_2Nx2N_w ; end
endcase
end
//*** DEBUG ********************************************************************
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1000 + 10; int n, m; int px[] = {0, 1, -1, 0}; int py[] = {1, 0, 0, -1}; bool dig[10]; char a[N][N]; bool inside(int x, int y) { return x >= 0 && y >= 0 && x < n && y < m; } bool alone(int x, int y) { int k, x2, y2; for (k = 0; k < 4; k++) { x2 = x + px[k]; y2 = y + py[k]; if (!inside(x2, y2)) continue; if (a[x2][y2] == . ) return false; } return true; } void go(int x, int y) { a[x][y] = * ; int k, x2, y2; for (k = 0; k < 4; k++) { x2 = x + px[k]; y2 = y + py[k]; if (!inside(x2, y2)) continue; if (a[x2][y2] == X ) go(x2, y2); if (isdigit(a[x2][y2])) dig[a[x2][y2] - 0 ] = 1; } } char getColor(int x, int y) { memset(dig, 0, sizeof(dig)); go(x, y); int i; for (i = 0; i < 10; i++) if (dig[i] == 0) return 0 + i; assert(false); } void fill(int x, int y, char c) { a[x][y] = c; int k, x2, y2; for (k = 0; k < 4; k++) { x2 = x + px[k]; y2 = y + py[k]; if (!inside(x2, y2)) continue; if (a[x2][y2] == * ) fill(x2, y2, c); } } void print() { int i; for (i = 0; i < n; i++) printf( %s n , a[i]); printf( n n ); } int main() { scanf( %d%d , &n, &m); int i, j, k, t; for (i = 0; i < n; i++) scanf( %s , a[i]); int x[3], y[3]; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { if (a[i][j] != . ) continue; x[0] = i; y[0] = j; for (k = 0; k < 2; k++) { x[1] = x[0] + px[k]; y[1] = y[0] + py[k]; if (!inside(x[1], y[1])) continue; if (a[x[1]][y[1]] == . ) break; } if (k == 2) { printf( -1 n ); return 0; } a[x[0]][y[0]] = X ; a[x[1]][y[1]] = X ; for (t = 0; t < 2; t++) { for (k = 0; k < 4; k++) { x[2] = x[t] + px[k]; y[2] = y[t] + py[k]; if (!inside(x[2], y[2])) continue; if (a[x[2]][y[2]] != . ) continue; if (alone(x[2], y[2])) a[x[2]][y[2]] = X ; } } fill(x[0], y[0], getColor(x[0], y[0])); } for (i = 0; i < n; i++) printf( %s n , a[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << [ ; for (auto u : v) { os << u; os << , ; } os << ] << n ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& s) { os << { ; for (auto u : s) { os << u; if (u != *s.rbegin()) os << , ; } os << } << n ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& p) { os << { ; os << p.first << , << p.second; os << } << n ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& mp) { for (auto p : mp) os << p.first << : << p.second << n ; return os; } void boost() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed << setprecision(3); } int32_t main() { boost(); long long t = 1; while (t--) { long long a[3], d; cin >> a[0] >> a[1] >> a[2] >> d; sort(a, a + 3); if (a[1] >= a[0] + d && a[2] >= a[1] + d) cout << 0 << n ; else { if (a[1] >= a[0] + d) { if (a[2] >= a[0] + 2 * d) { long long get = a[2] - d; long long ans = a[1] - get; cout << ans << n ; } else { long long have = (a[1] + d) - a[2]; cout << have << n ; } } else if (a[2] >= a[1] + d) { if (a[2] >= a[0] + 2 * d) { long long get = a[0] + d; long long ans = get - a[1]; cout << ans << n ; } else { long long have = abs((a[1] - d) - a[0]); cout << have << n ; } } else { long long ans = abs(d - (a[1] - a[0])); ans = ans + abs(d - (a[2] - a[1])); cout << ans << n ; } } } return 0; } |
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