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(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (which mostly works), and
Scheme (a bit out of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
magic declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(** $Date: 2016-05-26 12:03:56 -0400 (Thu, 26 May 2016) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_PP_SYMBOL_V
|
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : USR_ACCESSE2.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module USR_ACCESSE2 (
CFGCLK,
DATA,
DATAVALID
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CFGCLK;
output DATAVALID;
output [31:0] DATA;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_7_b2s_incr_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
reg [11:0] axaddr_incr;
reg [8:0] axlen_cnt;
reg next_pending_r;
wire [3:0] axsize_shift;
wire [11:0] axsize_mask;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// calculate cmd_byte_addr
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
end
endgenerate
assign axsize_shift = (1 << axsize[1:0]);
assign axsize_mask = ~(axsize_shift - 1'b1);
// Incremented version of axaddr
always @(posedge clk) begin
if (sel_first) begin
if(~next) begin
axaddr_incr <= axaddr[11:0] & axsize_mask;
end else begin
axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
end
end else if (next) begin
axaddr_incr <= axaddr_incr + axsize_shift;
end
end
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen;
next_pending_r <= (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= ((axlen_cnt - 1) >= 1);
end else begin
axlen_cnt <= 9'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = ((axlen_cnt - 1) >= 1);
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int n, x, s, d, t, a, b, r[5000], l, res1, res2, k; int main() { cin >> n >> k; for (int i = 0; i < k; i++) { cin >> t; if (t == 1) { cin >> a >> b; r[a] = r[b] = 1; l += 2; } else { cin >> a; r[a] = 1; l++; } } res2 = n - 1 - l; for (int i = 1; i < n; i++) { if (r[i] == 0) { if ((i < n - 1) && (r[i + 1] == 0)) r[i] = r[i + 1] = 1, res1++; else res1++; } } cout << res1 << << res2 << endl; return 0; } |
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Register file
//
// Revision Information:
// Date Description
//
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
//
// *********************************************************************/
module spi_rf # (
parameter APB_DWIDTH = 8
)( //APB Access to registers
input pclk,
input presetn,
input [6:0] paddr,
input psel,
input pwrite,
input penable,
input [APB_DWIDTH-1:0] wrdata,
output [APB_DWIDTH-1:0] prdata,
output interrupt,
//Hardware Status
input tx_channel_underflow,
input rx_channel_overflow,
input tx_done,
input rx_done,
input rx_fifo_read,
input tx_fifo_read,
input tx_fifo_write,
input rx_fifo_full,
input rx_fifo_full_next,
input rx_fifo_empty,
input rx_fifo_empty_next,
input tx_fifo_full,
input tx_fifo_full_next,
input tx_fifo_empty,
input tx_fifo_empty_next,
input first_frame,
//input frames_done_fill,
//input frames_done_empty,
input ssel,
//input hw_txbusy,
//input hw_rxbusy,
input active,
input rx_pktend,
input rx_cmdsize,
// -----------------------------------------------
// AS: removed a bunch of flags
// -----------------------------------------------
//Static Configuration Outputs
output cfg_enable,
//output [1:0] cfg_mode,
output cfg_master,
//output cfg_spo,
//output cfg_sph,
//output cfg_sps,
//output reg [5:0] cfg_framesize,
//output cfg_clkmode,
//output reg [7:0] cfg_clkrate,
//output [15:0] cfg_framecnt,
output reg [7:0] cfg_ssel,
//output reg [1:0] cfg_fifosize,
output [2:0] cfg_cmdsize,
//output reg [5:0] cfg_pktsize,
output cfg_oenoff,
//Strobe Outputs, will change during operation
output reg clr_txfifo,
output reg clr_rxfifo,
//output reg auto_fill,
//output reg auto_empty,
//output reg auto_stall,
//output reg auto_txnow,
//output cfg_autopoll,
//output cfg_autostatus,
output cfg_frameurun
//output reg [1:0] cfg_userstatus,
//output reg clr_framecnt
);
reg [7:0] control1;
reg [7:0] control2;
wire [5:0] command;
wire [7:0] int_masked;
reg [7:0] int_raw;
wire [7:0] status_byte;
reg [1:0] sticky;
reg [APB_DWIDTH-1:0] rdata;
//wire cfg_disfrmcnt;
//wire cfg_bigfifo;
// -----------------------------------------------------------------------------------------------------------------------
// Registers with sticky bits (The interrupt register)
//interrupt generation
// AS: modified Masked Interrupt register (control 2 register)
//assign int_masked = { (1'b0 ),
// (1'b0 ),
// (int_raw[5] && control2[5]),
// (int_raw[4] && control2[4]),
// (int_raw[3] && control1[7]),
// (int_raw[2] && control1[6]),
// (int_raw[1] && control1[4]),
// (int_raw[0] && control1[5])
// };
assign int_masked = {
(int_raw[7] && control2[7]), // !tx_fifo_full
(int_raw[6] && control2[6]), // !rx_fifo_empty
(int_raw[5] && control2[5]), // ssend
(int_raw[4] && control2[4]), // cmdint
(int_raw[3] && control1[5]), // txunderrun
(int_raw[2] && control1[4]), // rxoverflow
(1'b0), //PL : added
// PL: Removed rx_done signal
//(int_raw[1] && control1[2]),
(int_raw[0] && control1[3]) // txdone
};
assign interrupt = int_masked[7] || int_masked[6] || int_masked[5] || int_masked[4] ||
int_masked[3] || int_masked[2] || int_masked[1] || int_masked[0] ;
// ############################################################################################################
// Create Register Values
assign status_byte = { active,
ssel,
int_raw[3],
int_raw[2],
tx_fifo_full,
rx_fifo_empty,
(sticky[0] && sticky[1]),
first_frame
};
// AS: command is now write-only
assign command = 8'h00;
// ############################################################################################################
// Writes.
integer i;
always @(posedge pclk or negedge presetn)
begin
if (!presetn)
begin
control1 <= 8'h00;
cfg_ssel <= 8'h00;
control2 <= 8'h00;
clr_rxfifo <= 1'b0;
clr_txfifo <= 1'b0;
int_raw <= 8'h00;
sticky <= 2'b00;
end
else
begin
//------------------------------------------------------------------------
// Hardware Events lower priority than CPU activities
clr_rxfifo <= 1'b0;
clr_txfifo <= 1'b0;
//clr_framecnt <= cfg_disfrmcnt;
//-----------------------------------------------------------------------
// CPU Writes
if (psel & pwrite & penable)
begin
case (paddr) //synthesis parallel_case
7'h00: begin
control1[7:0] <= wrdata[7:0];
end
7'h04: begin
for (i=0; i<8; i=i+1) if (wrdata[i]) int_raw[i] <= 1'b0;
end
7'h18: begin
control2 <= wrdata[7:0];
end
7'h1c: begin
clr_rxfifo <= wrdata[0];
clr_txfifo <= wrdata[1];
end
7'h24: cfg_ssel <= wrdata[7:0];
default: begin end
endcase
//if we were enabled dont allow various changes
end
//------------------------------------------------------------------------
// Hardware Events higher proirity than CPU activities
// Clear off the auto bits
// AS: removed auto bits
// if (frames_done_fill==1'b1) auto_fill <= 1'b0;
// if (cfg_master && frames_done_empty==1'b1) auto_empty <= 1'b0;
// if (!cfg_master && rx_pktend) auto_empty <= 1'b0;
// if (tx_fifo_read==1'b1) auto_stall <= 1'b0;
// if (tx_fifo_read==1'b1) auto_txnow <= 1'b0;
// Sticky Status Bits
if (tx_done) sticky[0] <= 1'b1;
if (rx_done) sticky[1] <= 1'b1;
if (tx_fifo_write) sticky[0] <= 1'b0;
if (rx_fifo_read) sticky[1] <= 1'b0;
// Interrupt Settings
if (tx_done) int_raw[0] <= 1'b1;
if (rx_done) int_raw[1] <= 1'b1;
if (rx_channel_overflow) int_raw[2] <= 1'b1;
if (tx_channel_underflow) int_raw[3] <= 1'b1;
if (rx_cmdsize) int_raw[4] <= 1'b1;
if (rx_pktend) int_raw[5] <= 1'b1;
if (!rx_fifo_empty) int_raw[6] <= 1'b1;
if (!tx_fifo_full) int_raw[7] <= 1'b1;
//Unused interrupts
// int_raw[7:6] <= 2'b00;
//------------------------------------------------------------------------
// Unused Control bits
// control2[7:6] <= 2'b00;
control2[3] <= 1'b0;
end
end
// 5:2 are interrupt enables
assign cfg_enable = control1[0];
assign cfg_master = control1[1];
assign cfg_frameurun = control1[6];
assign cfg_oenoff = control1[7];
assign cfg_cmdsize = control2[2:0];
// ############################################################################################################
// Reads, purely combinational of the PADDR.
localparam [APB_DWIDTH-1:0] ZEROS = {(APB_DWIDTH){1'b0}};
always @(*)
begin
if (psel)
begin
case (paddr) //synthesis parallel_case
7'h00: rdata[7:0] = control1[7:0]; // control register 1
7'h04: rdata[7:0] = 8'h00; // write-only
// 0x08 assigned elsewhere
7'h0C: rdata[7:0] = 8'h00; // write-only
7'h10: rdata[7:0] = int_masked[7:0]; // masked interrupt register
7'h14: rdata[7:0] = int_raw[7:0]; // raw interrupt register
7'h18: rdata[7:0] = control2[7:0]; // control register 2
7'h20: rdata[7:0] = status_byte[7:0]; // status register
7'h24: rdata[7:0] = cfg_ssel[7:0]; // slave select register
default: rdata = ZEROS;
endcase
end
else
rdata = ZEROS;
end
assign prdata = ( (psel && penable) ? rdata : ZEROS);
endmodule
|
// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0______126.455____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v5_1,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module design_1_clk_wiz_0_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
design_1_clk_wiz_0_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int a[500005], b[500005]; int main() { int i, j, k, l, x, y, z, m, n, t; cin >> t; while (t--) { cin >> x >> y >> z; while (x > 20 && y) { x = x / 2; x += 10; y--; } while (x >= 0 && z) { x = x - 10; z--; } x = max(0, x); if (x) cout << NO << endl; else cout << YES << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 3e4; long long lp[N], rp[N], l, r, first, second, m, so, k, n; char ch; int main() { cin >> n; for (long long i = (long long)1; i <= (long long)n; i++) { cin >> ch >> k; if (ch == ? ) { first = l - lp[k]; second = r - rp[k]; m = l + r; so = 1e15; if (rp[k]) { so = min(so, r - rp[k]); so = min(so, m - second - 1); } if (lp[k]) { so = min(so, l - lp[k]); so = min(so, m - first - 1); } cout << so << n ; } else { if (ch == L ) lp[k] = ++l; if (ch == R ) rp[k] = ++r; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SEDFXBP_PP_SYMBOL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sedfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> inline int getint() { int x = 0, p = 1; char c = getchar(); while (c <= 32) c = getchar(); if (c == 45) p = -p, c = getchar(); while (c > 32) x = x * 10 + c - 48, c = getchar(); return x * p; } using namespace std; const int N = 110; const int M = 25; int dp[N][M][M], n, k, res, tmp[N][M][M]; vector<int> G[N]; inline void add(int &x, int y) { x += y; if (x >= 1000000007) x -= 1000000007; } inline int mul(int x, int y) { long long ans = 1ll * x * y; return ans % 1000000007; } void go(int x, int p) { vector<int> v; for (int(i) = 0; (i) < (G[x].size()); (i)++) { int to = G[x][i]; if (to != p) { go(to, x); v.push_back(to); } } tmp[0][1][M - 1] = tmp[0][0][1] = 1; for (int(i) = 0; (i) < (v.size()); (i)++) { int x = v[i]; for (int(i0) = 0; (i0) < (M); (i0)++) for (int(i1) = 0; (i1) < (M); (i1)++) tmp[i + 1][i0][i1] = 0; for (int(i0) = 0; (i0) < (k + 2); (i0)++) for (int(i1) = 0; (i1) < (M); (i1)++) { for (int(i2) = 0; (i2) < (k + 2); (i2)++) for (int(i3) = 0; (i3) < (M); (i3)++) { int hh = mul(tmp[i][i0][i1], dp[x][i2][i3]); if ((!i2 || i1 + i2 - 1 <= k) && (!i0 || i0 + i3 - 1 <= k)) { add(tmp[i + 1][0][min(i1, i3 + 1)], hh); continue; } if (!i2 || i1 + i2 - 1 <= k) { add(tmp[i + 1][i0][min(i1, i3 + 1)], hh); continue; } if (!i0 || i0 + i3 - 1 <= k) { if (i2 <= k) add(tmp[i + 1][i2 + 1][min(i1, i3 + 1)], hh); continue; } if (i2 <= k) add(tmp[i + 1][max(i0, i2 + 1)][min(i1, i3 + 1)], hh); } } } for (int(i) = 0; (i) < (k + 2); (i)++) for (int(j) = 0; (j) < (M); (j)++) dp[x][i][j] = tmp[v.size()][i][j]; } int main() { n = getint(); k = getint(); for (int(i) = 0; (i) < (n - 1); (i)++) { int x = getint() - 1, y = getint() - 1; G[x].push_back(y); G[y].push_back(x); } go(0, -1); for (int i = 1; i <= k + 1; i++) if (dp[0][0][i] > 0) add(res, dp[0][0][i]); printf( %d n , res); return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:53:08 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_auto_pc_0_stub.v
// Design : DemoInterconnect_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[0:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_HD__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_BLACKBOX_V
|
// Icarus 0.6 AND snapshot 20020728
// -----------------------------
// (1) force to nets not supported
// (2) comment the force statement and the release statement will cause
// the compiler to fail silently (no messages, no a.out)
//
// Icarus snapshot 20020817
// ------------------------
// Runs fine IFF the whole of a bus is set, cannot force individual bits
// (Fails with a rather incomprehensible error)
//
// To run this, incant:
// iverilog tt.v
// (adding -Wall doesn't help)
// vvp a.out (if a.out is generated!)
//
//
// Veriwell
// ---------
// Runs fine IFF the whole of a bus is set, cannot force individual bits
// & crashes if a release of an individual bit is attempted.
//
// To run this, incant:
// veridos tt.v (or use the GUI)
//
module top ();
reg [31:0] ii;
reg fail;
reg [1:0] a;
wire [1:0] junk = a;
wire [1:0] junkbus = a;
initial begin
a = 2'b01;
#5; a = 2'b10;
#10; a = 2'b11;
end
initial begin
#2;
force junk = 0;
force junkbus[0] = 0;
#10;
release junk;
#5;
release junkbus[0];
end
initial begin
$display("");
$display("expecting junk,junkbus to be 1 at T=1");
$display("then changing to 0 at T=2");
$display("then junk is 0 from T=3 to T=11, while");
$display("junkbus changes to 2 at T=5 and remains 2 through to T=16");
$display("junk changes to 2 at T=12");
$display("then 2 from T=13 to T=14");
$display("then changing to 3 at T=15");
$display("then 3 from T=16 on");
$display("junkbus changes to 3 at T=17 and remains 3 from then on");
$display("");
for(ii = 0; ii < 20; ii = ii + 1) begin
#0; // avoid race
// junk
if((ii == 1) && (junk !== 1)) fail = 1;
if((ii > 2) && (ii < 12) && (junk !== 0)) fail = 1;
if((ii > 12) && (ii < 14) && (junk !== 2'b10)) fail = 1;
if((ii > 15) && (junk !== 2'b11)) fail = 1;
// junkbus
if((ii == 1) && (junkbus !== 2'b01)) fail = 1;
if((ii > 2) && (ii < 4) && (junkbus !== 2'b00)) fail = 1;
if((ii > 5) && (ii < 17) && (junkbus !== 2'b10)) fail = 1;
if((ii > 17) && (junkbus !== 2'b11)) fail = 1;
$display("time: %0t, a: %b, junk: %b, junkbus: %b",$time,a,junk,junkbus);
#1;
end
if(fail) $display("\n\t--------- force test failed ---------\n");
else $display("\n\t--------- force test passed ---------\n");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_BEHAVIORAL_PP_V |
`define Z 0
`define N 1
`define C 2
`define V 3
module CU(input wire [31:0] instruction, input wire [3:0] flags, input wire clock,
output reg PCSrc/*Done*/, output reg MemToReg/*Done*/, output reg MemWrite/*Done*/,
output reg [1:0] ALUControl/*Done*/, output reg ALUSrc/*Done*/, output reg [1:0] ImmSrc/*Done*/,
output reg RegWrite/*Done*/, output reg NoWrite /*Done*/);
reg [3:0] interalflags;
reg exec;
always @* begin
//check cond
exec = 0;
case (instruction[31:28])
4'b0000: if(interalflags[`Z]) exec = 1;
4'b0001: if(~interalflags[`Z]) exec = 1;
4'b0010: if(interalflags[`C]) exec = 1;
4'b0011: if(~interalflags[`C]) exec = 1;
4'b0100: if(interalflags[`N]) exec = 1;
4'b0101: if(~interalflags[`N]) exec = 1;
4'b0110: if(interalflags[`V]) exec = 1;
4'b0111: if(~interalflags[`V]) exec = 1;
4'b1000: if(~interalflags[`Z] & interalflags[`C]) exec = 1;
4'b1001: if(interalflags[`Z] | ~interalflags[`C]) exec = 1;
4'b1010: if(~(interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1011: if(interalflags[`N] ^ interalflags[`V]) exec = 1;
4'b1100: if(~interalflags[`Z] & ~(interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1101: if(interalflags[`Z] | (interalflags[`N] ^ interalflags[`V])) exec = 1;
4'b1110: exec = 1;
4'b1111: exec = 1'bx;
endcase
NoWrite = 0;
ALUControl = 0;
ALUSrc = 1;
MemToReg = 0;
MemWrite = 0;
RegWrite = 0;
case (instruction[27:26])
2'b00: begin
if (exec) begin
RegWrite = 1;
end
if (instruction[25]) begin
ImmSrc = 0;
end else begin
ALUSrc = 0;
ImmSrc = 2'bxx;
end
case(instruction[24:21])
4'b0100: ALUControl = 0;
4'b0010: ALUControl = 1;
4'b0000: ALUControl = 2;
4'b1100: ALUControl = 3;
4'b1010: begin
ALUControl = 1;
NoWrite = 1;
end
default : ALUControl = 2'bxx;
endcase
if ((instruction[15:12] == 4'b1111) && RegWrite && exec)
PCSrc = 1;
else
PCSrc = 0;
end
2'b01: begin
if(instruction[20])
MemToReg = 1;
if(exec)
RegWrite = 1;
else begin
MemToReg = 1'bx;
if(exec)
MemWrite = 1;
end
ImmSrc = 1;
if ((instruction[15:12] == 4'b1111) && RegWrite && exec)
PCSrc = 1;
else
PCSrc = 0;
end
2'b10: begin
ImmSrc = 2;
RegWrite = 0;
if (exec)
PCSrc = 1;
else
PCSrc = 0;
end
default: begin
PCSrc = 1'bx;
MemToReg = 1'bx;
MemWrite = 1'bx;
ALUControl = 2'bxx;
ALUSrc = 1'bx;
ImmSrc = 2'bxx;
RegWrite = 1'bx;
NoWrite = 1'bx;
end
endcase
end
always @(posedge clock)
//if((instruction[27:26] == 2'b0) && (instruction[20]))
if(!(|instruction[27:26]) & (instruction[20]))
interalflags = flags;
endmodule |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "viterbidec.v"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
*/
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; template <int V, class T = long long> class max_flow { static const T INF = numeric_limits<T>::max(); struct edge { int t, rev; T cap, f; }; vector<edge> adj[V]; int dist[V]; int ptr[V]; bool bfs(int s, int t) { memset(dist, -1, sizeof dist); dist[s] = 0; queue<int> q({s}); while (!q.empty() && dist[t] == -1) { int n = q.front(); q.pop(); for (auto& e : adj[n]) { if (dist[e.t] == -1 && e.cap != e.f) { dist[e.t] = dist[n] + 1; q.push(e.t); } } } return dist[t] != -1; } T augment(int n, T amt, int t) { if (n == t) return amt; for (; ptr[n] < adj[n].size(); ptr[n]++) { edge& e = adj[n][ptr[n]]; if (dist[e.t] == dist[n] + 1 && e.cap != e.f) { T flow = augment(e.t, min(amt, e.cap - e.f), t); if (flow != 0) { e.f += flow; adj[e.t][e.rev].f -= flow; return flow; } } } return 0; } public: void add(int u, int v, T cap = 1, T rcap = 0) { adj[u].push_back({v, (int)adj[v].size(), cap, 0}); adj[v].push_back({u, (int)adj[u].size() - 1, rcap, 0}); } T calc(int s, int t) { T flow = 0; while (bfs(s, t)) { memset(ptr, 0, sizeof(ptr)); while (T df = augment(s, INF, t)) flow += df; } return flow; } void clear() { for (int n = 0; n < V; n++) adj[n].clear(); } }; set<int> xsw; set<int> ysw; bool adj[105][105]; int x1arr[50]; int x2arr[50]; int y1arr[50]; int y2arr[50]; int xswa[105]; int yswa[105]; int main() { int n, m; cin >> n >> m; xsw.insert(0); xsw.insert(n); ysw.insert(0); ysw.insert(n); for (int i = 0; i < m; i++) { cin >> x1arr[i] >> y1arr[i] >> x2arr[i] >> y2arr[i]; xsw.insert(x1arr[i] - 1); xsw.insert(x2arr[i]); ysw.insert(y1arr[i] - 1); ysw.insert(y2arr[i]); } int idx = 0; for (auto x : xsw) { xswa[idx++] = x; } idx = 0; for (auto y : ysw) { yswa[idx++] = y; } for (int i = 0; i < m; i++) { int xmin = 0; for (int j = 0; j < xsw.size(); j++) { if (xswa[j] == x1arr[i] - 1) { xmin = j; break; } } int xmax = 0; for (int j = 0; j < xsw.size(); j++) { if (xswa[j] == x2arr[i]) { xmax = j; break; } } int ymin = 0; for (int j = 0; j < ysw.size(); j++) { if (yswa[j] == y1arr[i] - 1) { ymin = j; break; } } int ymax = 0; for (int j = 0; j < ysw.size(); j++) { if (yswa[j] == y2arr[i]) { ymax = j; break; } } for (int j = xmin; j < xmax; j++) { for (int k = ymin; k < ymax; k++) { adj[j][k] = true; } } } max_flow<500> network; for (int i = 0; i < xsw.size() - 1; i++) { network.add(0, i + 1, xswa[i + 1] - xswa[i]); } for (int i = 0; i < xsw.size() - 1; i++) { for (int j = 0; j < ysw.size() - 1; j++) { if (adj[i][j]) { network.add(i + 1, xsw.size() + j, n); } } } for (int j = 0; j < ysw.size() - 1; j++) { network.add(xsw.size() + j, xsw.size() + ysw.size(), yswa[j + 1] - yswa[j]); } cout << network.calc(0, xsw.size() + ysw.size()) << endl; } |
#include <bits/stdc++.h> using namespace std; struct segment { int pos; int len; int type; }; struct segmentByLength { segment seg; bool operator<(segmentByLength o) const { segment seg2 = o.seg; if (seg.len != seg2.len) return seg.len > seg2.len; else { return seg.pos < seg2.pos; } } }; struct segmentByPosition { segment seg; bool operator<(segmentByPosition o) const { segment seg2 = o.seg; return seg.pos < seg2.pos; } }; set<segmentByLength> lengthSet; set<segmentByPosition> positionSet; void add_segment(segment s) { lengthSet.insert({s}); positionSet.insert({s}); } void remove_segment(segment s) { lengthSet.erase({s}); positionSet.erase({s}); } int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } a.push_back(1000000001); int start = 0; for (int i = 0; i < a.size(); i++) { if (i > 0 and a[i] != a[i - 1]) { segment s = {start, (i - 1) - start + 1, a[i - 1]}; lengthSet.insert({{s}}); positionSet.insert({{s}}); start = i; } } int sol = 0; while (!lengthSet.empty()) { segment s = (*lengthSet.begin()).seg; segment left, right; bool leftExists = true, rightExists = true; auto lbIterator = positionSet.lower_bound({s}); if (lbIterator != positionSet.begin()) { --lbIterator; left = (*lbIterator).seg; } else { leftExists = false; } auto ubIterator = positionSet.upper_bound({s}); if (ubIterator != positionSet.end()) { right = (*ubIterator).seg; } else { rightExists = false; } remove_segment(s); if (leftExists and rightExists and left.type == right.type) { segment merged = {left.pos, left.len + right.len, left.type}; remove_segment(left); remove_segment(right); add_segment(merged); } sol++; } cout << sol << n ; return 0; } |
#include <bits/stdc++.h> const int mod = 1000000007; int dp[4][200005]; int main() { long long a, b; scanf( %I64d %I64d , &a, &b); long long t = sqrt(2 * (a + b)); while ((t * t + t > 2 * (a + b)) || ((t * t + 3 * t + 2) <= 2 * (a + b))) { --t; } long long sum = t * (t + 1) / 2; dp[0][0] = 1; dp[1][0] = 1; dp[1][1] = 1; int cur = 0; for (int i = 1; i <= t; ++i) { long long temp = i * (i + 1) / 2; for (int j = 0; j <= temp && j <= a; ++j) { cur = i % 3; if (j == 0) { dp[cur][j] = 1; continue; } int k = cur - 1; if (k < 0) k = k + 3; dp[cur][j] = dp[k][j]; if (j >= i) dp[cur][j] += dp[k][j - i]; if (dp[cur][j] >= mod) dp[cur][j] %= mod; } } long long result = 0; long long temp = sum - b; if (temp < 0) temp = 0; t = t % 3; for (int i = (int)temp; i <= a; ++i) { result += dp[t][i]; result %= mod; } printf( %I64d n , result); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18 + 123; const long double EPS = 1e-9; const int MX = 1e9 + 1; const int inf = 1e9 + 123; const int MOD = 1e9 + 7; const int N = 1e5 + 123; const int dx[] = {0, 0, 1, -1}; const int dy[] = {1, -1, 0, 0}; int n, m; long long dp[1001], a[13], b[13], c[13], d[13]; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m >> c[0] >> d[0]; for (int i = 1; i <= m; ++i) { cin >> a[i] >> b[i] >> c[i] >> d[i]; } for (int i = 1; i <= m; ++i) { for (int l = n; l >= 0; --l) { for (int j = 1; j <= a[i] / b[i]; ++j) { if (l + j * c[i] > n) { continue; } dp[l + j * c[i]] = max(dp[l + j * c[i]], dp[l] + j * d[i]); } } } for (int l = n; l >= 0; --l) { for (int j = 1; j <= n / c[0]; ++j) { if (l + j * c[0] > n) { continue; } dp[l + j * c[0]] = max(dp[l + j * c[0]], dp[l] + d[0] * j); } } long long ans = 0; for (int i = 1; i <= n; ++i) { ans = max(ans, dp[i]); } cout << ans; return 0; } |
#include <bits/stdc++.h> typedef struct { char name[20]; char phone[200][20]; int len[200]; int avai[200]; int cnt, now; } friends; friends frd[20]; int total; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { char tmp[20]; scanf( %s , tmp); int pos = -1; for (int j = 0; j < total; j++) { if (!strcmp(frd[j].name, tmp)) { pos = j; break; } } if (pos == -1) pos = total++; int num; scanf( %d , &num); for (int j = 0; j < num; j++) { char ph_num[20]; scanf( %s , ph_num); int l = strlen(ph_num), flag = 0; for (int k = 0; k < frd[pos].now; k++) { if (frd[pos].avai[k]) { if (frd[pos].len[k] >= l) { if (!strcmp(frd[pos].phone[k] + frd[pos].len[k] - l, ph_num)) { flag = 1; break; } } else { if (!strcmp(ph_num + l - frd[pos].len[k], frd[pos].phone[k])) { frd[pos].avai[k] = 0; frd[pos].cnt--; break; } } } } if (!flag) { strcpy(frd[pos].name, tmp); strcpy(frd[pos].phone[frd[pos].now], ph_num); frd[pos].len[frd[pos].now] = l; frd[pos].avai[frd[pos].now] = 1; frd[pos].cnt++; frd[pos].now++; } } } printf( %d n , total); for (int i = 0; i < total; i++) { printf( %s %d , frd[i].name, frd[i].cnt); for (int j = 0; j < frd[i].now; j++) { if (frd[i].avai[j]) printf( %s , frd[i].phone[j]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll llinf = (1ll << 61) - 1; const int inf = 1000000007; int TC = 1, CN, n, r, c[1 << 18 | 5]; signed main() { cin.tie(0)->sync_with_stdio(0); cin.exceptions(cin.failbit); cout.precision(11), cout.setf(ios::fixed); auto kase = [&]() -> void { cin >> n >> r; double sum = 0; for (int i = 0; i < 1 << n; i++) { cin >> c[i], sum += c[i]; } for (int i = 0; i < r; i++) { cout << sum / (1 << n) << n ; int z, g; cin >> z >> g; sum -= c[z], c[z] = g, sum += c[z]; } cout << sum / (1 << n) << n ; }; while (CN++ != TC) kase(); } |
#include <bits/stdc++.h> using namespace std; int mark[(10000000 >> 5) + 1]; void sieve() { register int i, j, k; (mark[1 >> 5] |= 1 << (1 & 31)); int n = 10000000; for (i = 2; i <= n; i++) { if (!(mark[i >> 5] >> (i & 31) & 1)) { for (k = n / i, j = i * k; k >= i; k--, j -= i) (mark[j >> 5] |= 1 << (j & 31)); } } } long long C(long long n, long long k) { if (k == 0) return 1; return (n * C(n - 1, k - 1)) / k; } long long modular_pow(long long budgetase, long long exponent, int modulus) { long long result = 1; while (exponent > 0) { if (exponent % 2 == 1) result = (result * budgetase) % modulus; exponent = exponent >> 1; budgetase = (budgetase * budgetase) % modulus; } return result; } long long binaryToDec(string number) { long long result = 0, pow = 1; for (int i = number.length() - 1; i >= 0; --i, pow <<= 1) result = (result + (number[i] - 0 ) * pow) % 1000003; return result; } long long GCD(long long a, long long b) { return b == 0 ? a : GCD(b, a % b); } int main() { double d, h, v, e; cin >> d >> h >> v >> e; double r = d / 2; double area = 3.1415926535897932384626433832795 * r * r; if (e * area > v || fabs(e * area - v) < 0.0000000001) { cout << NO << endl; return 0; } double vol = 3.1415926535897932384626433832795 * r * r * h; double p = e * 3.1415926535897932384626433832795 * r * r; double dif = fabs(p - v); cout << YES << endl; cout << setprecision(12) << fixed << (double)vol / dif << endl; } |
`include "../network_params.h"
module mult_adder_ctrl(
input clock,
input reset,
input start,
output [`X_COORD_BITWIDTH:0] x_coord,
output [`Y_COORD_BITWIDTH:0] y_coord,
output pixel_rdy // indicates valid data at end of tree/pipeline
);
// wire declarations
// reg declarations
reg buffer_rdy;
reg rdy_shift_reg [`RDY_SHIFT_REG_SIZE-1:0];
reg [`X_COORD_BITWIDTH:0] x_counter;
reg [`Y_COORD_BITWIDTH:0] y_counter;
// assign statments
assign pixel_rdy = rdy_shift_reg[0];
assign x_coord = x_counter;
assign y_coord = y_counter;
// set enable when buffer_rdy strobes, unset at x/y max
always@(posedge clock or negedge reset) begin
if(reset == 1'b0) begin
buffer_rdy <= 1'b0;
end else begin
if(start) begin
buffer_rdy <= 1'b1;
// extra - 1 to prevent counter overflow from being latched
end else if (x_counter == `X_COORD_MAX - 1 - 1 &
y_counter == `Y_COORD_MAX - 1) begin
buffer_rdy <= 1'b0;
end else begin
buffer_rdy <= buffer_rdy;
end
end // reset
end // always
// x and y counters for window selectors
always@(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
x_counter <= `X_COORD_WIDTH'd0;
y_counter <= `Y_COORD_WIDTH'd0;
end else if(buffer_rdy) begin
if(x_counter < `X_COORD_MAX - 1) begin
x_counter <= x_counter +`X_COORD_WIDTH'd1;
y_counter <= y_counter;
end else begin
x_counter <= `X_COORD_WIDTH'd0;
if(y_counter < `Y_COORD_MAX - 1)
y_counter <= y_counter + `Y_COORD_WIDTH'd1;
else
y_counter <= `Y_COORD_WIDTH'd0;
end
end else begin // buffer is not ready
x_counter <= `X_COORD_WIDTH'd0;
y_counter <= `Y_COORD_WIDTH'd0;
end // reset
end // always
// shift register to hold ready signal
genvar i;
generate
for (i=0; i < `RDY_SHIFT_REG_SIZE-1; i=i+1) begin : shift_reg_loop
always@(posedge clock) begin
rdy_shift_reg[i] <= rdy_shift_reg[i+1];
end // always
end // for
endgenerate
// connect input to shift reg
always@(posedge clock) begin
rdy_shift_reg[`RDY_SHIFT_REG_SIZE-1] <= buffer_rdy;
end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Arbiter
-- Description: Implementacion de algoritmo de arbitraje entre multiples
peticiones. En particular este modulo implementa el
algoritmo round-robin de 4 bits.
Despues de un reset, el modulo da priorida en orden
descendiente a las peticiones de: {PE, x+, y+, x-, y-}.
Despues de seleccionar un ganador, la maxima prioridad
durante el siguiente proceso de arbitraje se otorga al
puerto inmediato inferior al ganador de la ronda
anterior.
Ej. Si el ganador durante la ronda anterior fue la
peticion proveniente de 'x+', la siguiente ronda
las peticiones de 'y+' tendran la maxima
prioridad.
-- Dependencies: -- system.vh
-- Parameters: -- RQSX: Codificacion 'One-Hot' de peticiones.
Ej. Si los puertos validos para hacer
una peticion son: {x+, y+, x-, y-},
RQS0 tendria el valot 4'b0001
-- PTY_NEXT_RQSX: Codificacion en binario natural
de los numeros 3 a 0.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- 05 de Junio 2015: Creacion
-- 14 de Junio 2015: - Constantes RQSX y PTY_NEXT_RQSX pasan a
ser parametros locales en lugar de
`define en system.vh.
- rqs_priority_next pasa a tener longitud de
2 dos bits en lugar de 4.
- Se agrega un registro dedicado al
seguimiento de la prioridad siguiente.
- El algoritmo de RR utiliza la señal
registrada de rqs_priority_reg
*/
`include "system.vh"
module arbiter
(
input wire clk,
// -- inputs ------------------------------------------------- >>>>>
input wire [3:0] port_request_din,
input wire arbiter_strobe_din,
input wire clear_arbiter_din,
// -- output ------------------------------------------------- >>>>>
output wire [3:0] xbar_conf_vector_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam RQS0 = 4'b0001;
localparam RQS1 = 4'b0010;
localparam RQS2 = 4'b0100;
localparam RQS3 = 4'b1000;
localparam PTY_NEXT_RQS1 = 2'b01;
localparam PTY_NEXT_RQS2 = 2'b10;
localparam PTY_NEXT_RQS3 = 2'b11;
localparam PTY_NEXT_RQS0 = 2'b00;
// -- Declaracion Temprana de Señales ---------------------------- >>>>>
reg [3:0] xbar_conf_vector_reg = 4'b0000;
/*
-- Priority Encoder
-- Descripcion: Codificador de prioridad para la siguiente ronda de
arbitraje. Dependiendo de la peticion ganadora
(xbar_conf_vector_reg) se otorga prioridad para el
proximo proceso de arbitraje a la entrada inferior
inmediada en la jeraraquia.
Ej. jerarquia por default de puertos {PE, x+, y+, x-,
y-}. Si la ronda anterior la peticion de 'y+'
resulto ganadora, la siguiente ronda las peticiones
de 'x-' tienen la maxima prioridad.
La prioridad esta codificada en binario naturas
rqs_priority_reg.
*/
reg [1:0] rqs_priority_reg = 2'b00;
reg [1:0] rqs_priority_next;
// -- Elemento de memoria ------------------------------------ >>>>>
always @(posedge clk)
if (clear_arbiter_din)
rqs_priority_reg <= rqs_priority_next;
// -- Elemento de logica del siguiente estado ---------------- >>>>>
always @(*)
begin
rqs_priority_next = 2'b00;
case (xbar_conf_vector_reg)
RQS0: rqs_priority_next = PTY_NEXT_RQS1;
RQS1: rqs_priority_next = PTY_NEXT_RQS2;
RQS2: rqs_priority_next = PTY_NEXT_RQS3;
RQS3: rqs_priority_next = PTY_NEXT_RQS0;
endcase
end //(*)
/*
-- Round Robin
-- Descripcion: Codificacion de algoritmo Round Robin por medio de
tabla de verdad. Cada bit de 'grant_vector' es
mutuamente excluyente de sus vecinos.
*/
wire [3:0] grant_vector;
// -- Combinational RR ----------------------------------------------- >>>>>
assign grant_vector[0] = (port_request_din[0] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0]) |
(port_request_din[0] & ~rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[2] & ~port_request_din[1]) |
(port_request_din[0] & rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[2]) |
(port_request_din[0] & rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3]);
assign grant_vector[1] = (port_request_din[1] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[0]) |
(port_request_din[1] & ~rqs_priority_reg[1] & rqs_priority_reg[0]) |
(port_request_din[1] & rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[2] & ~port_request_din[0]) |
(port_request_din[1] & rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[0]);
assign grant_vector[2] = (port_request_din[2] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[1] & ~port_request_din[0]) |
(port_request_din[2] & ~rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[1]) |
(port_request_din[2] & rqs_priority_reg[1] & ~rqs_priority_reg[0] ) |
(port_request_din[2] & rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[1] & ~port_request_din[0]);
assign grant_vector[3] = (port_request_din[3] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[2] & ~port_request_din[1] & ~port_request_din[0]) |
(port_request_din[3] & ~rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[2] & ~port_request_din[1]) |
(port_request_din[3] & rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[2]) |
(port_request_din[3] & rqs_priority_reg[1] & rqs_priority_reg[0]);
// -- Registro de control para Crossbar -------------------------- >>>>>
always @(posedge clk)
if (clear_arbiter_din)
xbar_conf_vector_reg <= {4{1'b0}};
else
if (arbiter_strobe_din)
xbar_conf_vector_reg <= grant_vector;
// -- Salida de Modulo ------------------------------------------- >>>>>
assign xbar_conf_vector_dout = xbar_conf_vector_reg;
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
wire [3:0] xbar_conf_vector;
arbiter arbitro_round_robin
(
.clk(clk),
// -- inputs --------------------------------------------- >>>>>
.port_request_din (port_request_din),
.arbiter_strobe_din (arbiter_strobe_din),
.clear_arbiter_din (clear_arbiter_din)
// -- output --------------------------------------------- >>>>>
.xbar_conf_vector_dout (xbar_conf_vector)
);
*/ |
#include <bits/stdc++.h> typedef long long ll; #define f(i,a,b) for(i=a;i<b;i++) using namespace std; int main() { ll n,i,sum=0, count=0; cin>>n; vector<ll> a(n); f(i,0,n) cin>>a[i]; priority_queue <int, vector<int>, greater<int>> p; f(i,0,n){ if(a[i]>=0) sum+=a[i], count++; else{ if(sum+a[i]>=0){ sum+=a[i], count++; p.push(a[i]); } else{ if(!p.empty()&&p.top()<a[i]){ sum-=p.top(); p.pop(); sum+=a[i]; p.push(a[i]); } } } } cout<<count<<endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct arra { long long int d = 0, idx; } arr[200008]; bool comp(struct arra a, struct arra b) { return a.d > b.d; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k, a, temp, ans; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a; arr[a].d++; arr[a].idx = a; } sort(arr, arr + 200005, comp); long long int l = 1, r = 200008, mid; while (l <= r) { mid = (l + r) / 2; temp = 0; for (int i = 0; i < n; i++) { temp += arr[i].d / mid; } if (temp >= k) { ans = mid; l = mid + 1; } else r = mid - 1; } vector<long long> v; for (int i = 0; i < n; i++) { for (int j = 0; j < arr[i].d / ans; j++) { v.push_back(arr[i].idx); } } for (int i = 0; i < k; i++) cout << v[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); int n; cin >> n; int arr[5001] = {0}; int ans = 0; for (int i = 0; i < n; i++) { int x; cin >> x; arr[x]++; } for (int i = 1; i <= n; i++) { if (arr[i] >= 2) ans += arr[i] - 1; } for (int i = n + 1; i <= 5000; i++) ans += arr[i]; cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int N = 5005; template <class I> inline void ckMax(I& p, I q) { p = (p > q ? p : q); } template <class I> inline void ckMin(I& p, I q) { p = (p < q ? p : q); } template <class I> inline I Max(I& p, I q) { return p > q ? p : q; } template <class I> inline I Min(I& p, I q) { return p < q ? p : q; } template <class I> inline void sp(I& p, I& q) { I x = p; p = q, q = x; } int n, m, k, a[N]; long long f[N][N], ans; deque<int> q[N]; int main() { scanf( %d%d%d , &n, &k, &m); register int i, j; for (i = 1; i <= n; ++i) scanf( %d , &a[i]); q[0].push_back(0); for (i = 1; i <= n; ++i) for (j = m; j; --j) { while ((!q[j - 1].empty()) && q[j - 1].front() < i - k) q[j - 1].pop_front(); if (q[j - 1].empty()) continue; f[i][j] = f[q[j - 1].front()][j - 1] + a[i]; while ((!q[j].empty()) && f[q[j].back()][j] <= f[i][j]) q[j].pop_back(); q[j].push_back(i); } for (i = n - k + 1; i <= n; ++i) ckMax(ans, f[i][m]); printf( %lld , ans > 0 ? ans : -1ll); return 0; } |
/**
* bsg_nonsynth_ramulator_hbm.v
*
*/
`include "bsg_defines.v"
module bsg_nonsynth_ramulator_hbm
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter debug_p=0
, parameter init_mem_p=0 // zero out values in memory at the beginning
, parameter lg_num_channels_lp=`BSG_SAFE_CLOG2(num_channels_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
)
(
input clk_i
, input reset_i
, input [num_channels_p-1:0] v_i
, input [num_channels_p-1:0] write_not_read_i
, input [num_channels_p-1:0][channel_addr_width_p-1:0] ch_addr_i
, output logic [num_channels_p-1:0] yumi_o
, input [num_channels_p-1:0] data_v_i
, input [num_channels_p-1:0][data_width_p-1:0] data_i
, output logic [num_channels_p-1:0] data_yumi_o
, output logic [num_channels_p-1:0] data_v_o
, output logic [num_channels_p-1:0][data_width_p-1:0] data_o
, output logic [num_channels_p-1:0][channel_addr_width_p-1:0] ch_addr_o
);
// DPI
import "DPI-C" context function void init_hbm();
import "DPI-C" context function bit send_write_req(input longint addr);
import "DPI-C" context function bit send_read_req(input longint addr);
import "DPI-C" context function bit get_read_done(int ch);
import "DPI-C" context function longint get_read_done_addr(int ch);
import "DPI-C" context function void tick();
import "DPI-C" context function void finish_hbm();
initial begin
init_hbm();
end
// memory addr
logic [num_channels_p-1:0][lg_num_channels_lp+channel_addr_width_p-1:0] mem_addr;
for (genvar i = 0; i < num_channels_p; i++) begin
assign mem_addr[i] = {
ch_addr_i[i][channel_addr_width_p-1:byte_offset_width_lp],
(lg_num_channels_lp)'(i),
{byte_offset_width_lp{1'b0}}
};
end
// request yumi
logic [num_channels_p-1:0] yumi_lo;
for (genvar i = 0; i < num_channels_p; i++)
assign yumi_o[i] = yumi_lo[i] & v_i[i];
// read channel signal
logic [num_channels_p-1:0] read_done;
logic [num_channels_p-1:0][lg_num_channels_lp+channel_addr_width_p-1:0] read_done_addr;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] read_done_ch_addr;
for (genvar i = 0; i < num_channels_p; i++) begin
assign read_done_ch_addr[i] = {
read_done_addr[i][channel_addr_width_p+lg_num_channels_lp-1:byte_offset_width_lp+lg_num_channels_lp],
{byte_offset_width_lp{1'b0}}
};
end
assign ch_addr_o = read_done_ch_addr;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
read_done <= '0;
read_done_addr <= '0;
end
else begin
// getting read done
for (integer i = 0; i < num_channels_p; i++) begin
read_done[i] = get_read_done(i);
if (read_done[i])
read_done_addr[i] = get_read_done_addr(i);
end
// tick
tick();
end
end
always_ff @ (negedge clk_i) begin
if (reset_i) begin
yumi_lo <= '0;
end
else begin
// sending requests
for (integer i = 0; i < num_channels_p; i++) begin
if (v_i[i]) begin
if (write_not_read_i[i]) begin
if (data_v_i[i])
yumi_lo[i] <= send_write_req(mem_addr[i]);
else
yumi_lo[i] <= 1'b0;
end
else begin
yumi_lo[i] <= send_read_req(mem_addr[i]);
end
end
else begin
yumi_lo[i] <= 1'b0;
end
end
end
end
// channels
logic [num_channels_p-1:0] read_v_li;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] read_addr_li;
logic [num_channels_p-1:0] write_v_li;
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_nonsynth_test_dram_channel #(
.channel_addr_width_p(channel_addr_width_p)
,.data_width_p(data_width_p)
,.init_mem_p(init_mem_p)
) channel (
.clk_i(clk_i)
,.reset_i(reset_i)
,.read_v_i(read_v_li[i])
,.read_addr_i(read_addr_li[i])
,.write_v_i(write_v_li[i])
,.write_addr_i(ch_addr_i[i])
,.data_v_i(data_v_i[i])
,.data_i(data_i[i])
,.data_yumi_o(data_yumi_o[i])
,.data_v_o(data_v_o[i])
,.data_o(data_o[i])
);
assign read_v_li[i] = read_done[i];
assign read_addr_li[i] = read_done_ch_addr[i];
assign write_v_li[i] = v_i[i] & write_not_read_i[i] & yumi_o[i];
end
// debugging
integer file;
initial begin
if (debug_p) begin
file = $fopen("ramulator_access_trace.txt");
$fwrite(file, "request,time,channel,write_not_read,address\n");
end
end
always_ff @ (posedge clk_i) begin
if (~reset_i & debug_p) begin
for (integer i = 0; i < num_channels_p; i++) begin
if (yumi_o[i])
begin
$display("req sent: t=%012t, channel=%0d, write_not_read=%0b, addr=%032b", $time, i, write_not_read_i[i], ch_addr_i[i]);
$fwrite(file, "send,%t,%0d,%0b,%08h\n", $time, i, write_not_read_i[i], ch_addr_i[i]);
end
if (read_done[i])
begin
$display("read done: t=%012t, channel=%0d, addr=%32b", $time, i, read_done_ch_addr[i]);
$fwrite(file, "recv,%t,%0d,,%08h\n", $time, i, read_done_ch_addr[i]);
end
end
end
end
// final
final begin
finish_hbm();
$fclose(file);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_ramulator_hbm)
|
#include <bits/stdc++.h> using namespace std; const int len = 6020; int SIZE; const int inf = (int)1e9; int n; vector<int> in; vector<vector<int>> g; int flow[len][len], cost[len][len], pot[len]; int get_p(int u, int v) { return cost[u][v] + pot[u] - pot[v]; } int add_path(int from, int to) { vector<int> dist(SIZE, (int)1e9), prv(SIZE); vector<bool> check(SIZE, false); dist[from] = 0; check[from] = true; priority_queue<pair<int, int>> q; q.push(make_pair(0, from)); while (!q.empty()) { auto tmp = q.top(); tmp.first *= -1; q.pop(); if (dist[tmp.second] != tmp.first) { continue; } check[tmp.second] = true; for (auto i : g[tmp.second]) { if (flow[tmp.second][i] > 0 && dist[i] > dist[tmp.second] + get_p(tmp.second, i)) { dist[i] = dist[tmp.second] + get_p(tmp.second, i); prv[i] = tmp.second; q.push(make_pair(-dist[i], i)); } } } for (int i = 0; i < SIZE; i++) { pot[i] += dist[i]; } if (!check[to]) { return inf; } int ptr = to, cap = inf, sum = 0; while (ptr != from) { cap = min(cap, flow[prv[ptr]][ptr]); ptr = prv[ptr]; } ptr = to; while (ptr != from) { flow[prv[ptr]][ptr] -= cap; flow[ptr][prv[ptr]] += cap; sum += cost[prv[ptr]][ptr]; ptr = prv[ptr]; } return sum; } int solve(int from, int to) { int sum = 0, tmp; while ((tmp = add_path(from, to)) != inf) { sum -= tmp; } return sum; } void add(int from, int to, int in_flow, int in_cost) { g[from].push_back(to); g[to].push_back(from); flow[from][to] = in_flow; cost[from][to] = in_cost; cost[to][from] = -in_cost; } vector<int> super_cnt[100001]; vector<int> cnt[7]; int main() { cin >> n; SIZE = 2 * n + 3; in.resize(SIZE); for (int i = 0; i < n; i++) { cin >> in[i]; } g.resize(SIZE, vector<int>()); add(0, 1, 4, 0); for (int i = 0; i < n; i++) { add(2 * i + 3, 2 * i + 4, 1, -1); add(1, 2 * i + 3, 1, 0); add(2 * i + 4, 2, 1, 0); for (int j : cnt[in[i] % 7]) { add(2 * j + 4, 2 * i + 3, 1, 0); } for (int j : super_cnt[in[i] - 1]) { add(2 * j + 4, 2 * i + 3, 1, 0); } for (int j : super_cnt[in[i] + 1]) { add(2 * j + 4, 2 * i + 3, 1, 0); } cnt[in[i] % 7].push_back(i); super_cnt[in[i]].push_back(i); } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < i; j++) { if (flow[j][i] && pot[j] + cost[j][i] < pot[i]) { pot[i] = pot[j] + cost[j][i]; } } } cout << solve(0, 2); return 0; } |
#include <bits/stdc++.h> using namespace std; void sortLU(long long a[], long long n, long long b[]) { long long i, j; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (a[i] < a[j]) { swap(a[i], a[j]); swap(b[i], b[j]); } } } } int main() { long long p; cin >> p; long long a, s = 0, i; for (i = 0; i < p; i++) { cin >> a; s += a; } long long n; cin >> n; long long x[n], y[n]; for (i = 0; i < n; i++) { cin >> x[i] >> y[i]; } for (i = 0; i < n; i++) { if (s <= max(x[i], y[i])) { if (s <= min(x[i], y[i])) { cout << min(x[i], y[i]) << endl; return 0; } else { cout << s << endl; return 0; } } } cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; struct node { int x, p; } a[N]; int d, n, m, top, xx, nexttttt[N], last, q[N]; long long ans; bool cmp(node a, node b) { return a.x < b.x; } int main() { scanf( %d%d%d , &d, &n, &m); for (int i = 1; i <= m; i++) scanf( %d%d , &a[i].x, &a[i].p); sort(a + 1, a + m + 1, cmp); a[m + 1].x = d; a[m + 1].p = 0; for (int i = m + 1; i >= 0; i--) { if (a[i].x - a[i - 1].x > n) { puts( -1 ); return 0; } while (top && a[i].p < a[q[top]].p) top--; nexttttt[i] = q[top]; q[++top] = i; } for (int i = 0; i <= m; i++) { xx = max(0, min(a[nexttttt[i]].x - a[i].x, n) - last); ans += 1ll * xx * a[i].p; last -= a[i + 1].x - a[i].x - xx; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return x * f; } int n, f[5010][5010][2], out[5010], siz[5010], size, rt = 1; struct node { int u, v, nxt; } e[5010 << 1]; int head[5010], js; void add(int u, int v) { e[++js] = (node){u, v, head[u]}; head[u] = js; } void dfs1(int u, int pre) { for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].v; out[u]++; if (v == pre) continue; dfs1(v, u); } size += out[u] == 1; } void dfs2(int u, int pre) { if (out[u] == 1) { siz[u] = 1; f[u][0][0] = f[u][1][1] = 0; return; } else f[u][0][0] = f[u][0][1] = 0; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].v; if (v == pre) continue; dfs2(v, u); siz[u] += siz[v]; for (int j = siz[u]; j >= 0; j--) { int tmp0 = 0x7fffffff, tmp1 = 0x7fffffff; for (int k = 0; k <= siz[v]; k++) if (k <= j) { tmp0 = min(tmp0, f[u][j - k][0] + min(f[v][k][0], f[v][k][1] + 1)); tmp1 = min(tmp1, f[u][j - k][1] + min(f[v][k][1], f[v][k][0] + 1)); } f[u][j][0] = tmp0; f[u][j][1] = tmp1; } } } int main() { n = read(); memset(f, 63, sizeof f); for (int i = 1; i < n; i++) { int x = read(), y = read(); add(x, y), add(y, x); } dfs1(1, 0); while (out[rt] == 1) rt++; dfs2(rt, 0); printf( %d , min(f[rt][size >> 1][0], f[rt][size >> 1][1])); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int MOD = 1e9 + 7; vector<int> check(int n, vector<int> a, int x) { multiset<int> as; for (auto u : a) { as.insert(u); } vector<int> res; for (int i = 0; i < n; ++i) { auto it1 = as.end(); it1--; int y = x - *it1; as.erase(it1); auto it2 = as.find(y); if (it2 == as.end()) { return {}; } res.push_back(x - y); res.push_back(y); x = max(y, x - y); as.erase(it2); } return res; } const int N = 3505; int n, m, k; int arr[N]; int get(int p, int s) { int ans = (1 << 30); for (int j = p; j + s <= m - 1; j++) { ans = min(ans, max(arr[j], arr[n - (m - 1 - j) - 1])); } return ans; } int main() { int t; scanf( %d , &t); while (t--) { scanf( %d %d %d , &n, &m, &k); k = min(k, m - 1); int ans = 0; for (int i = 0; i < n; i++) scanf( %d , &arr[i]); for (int i = 0; i <= k; i++) ans = max(ans, get(i, k - i)); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 210, INF = 1 * 1000 * 1000 * 1000 + 10, maxm = 150, maxk = 10; int n, m, k, sar, now, par[maxn], x[maxk], c[maxn], d[maxn], f[maxn][maxn], dp[maxm][maxn], dx[4] = {-1, 1, 0, 0}, dy[4] = {0, 0, -1, 1}, cur, X, Y, save; vector<int> t[maxm][maxn], path[maxn][maxn]; queue<int> q; bool mark[maxn]; char ans[maxn][maxn]; inline bool valid(int &a, int &b) { return a >= 0 && a < n && b >= 0 && b < m; } inline void SPFA() { while (!q.empty()) { sar = q.front(); X = sar / m; Y = sar % m; q.pop(); mark[sar] = 0; for (int i = 0; i < 4; i++) { X += dx[i]; Y += dy[i]; save = X * m + Y; if (valid(X, Y) && d[save] > d[sar] + c[save]) { d[save] = d[sar] + c[save]; par[save] = sar; if (!mark[save]) { q.push(save); mark[save] = 1; } } X -= dx[i]; Y -= dy[i]; } } } int main() { ios::sync_with_stdio(0); cin >> n >> m >> k; for (int i = 0; i < n * m; i++) cin >> c[i]; for (int i = 0; i < n * m; i++) { for (int j = 0; j < n * m; j++) d[j] = INF; d[i] = 0; par[i] = -1; mark[i] = 1; q.push(i); SPFA(); for (int j = 0; j < n * m; j++) { f[i][j] = d[j]; now = j; while (par[now] != -1) { path[i][j].push_back(now); now = par[now]; } } } memset(dp, 63, sizeof dp); for (int i = 0; i < k; i++) { cin >> X >> Y; X--; Y--; x[i] = X * m + Y; for (int j = 0; j < n * m; j++) { dp[1 << i][j] = f[x[i]][j] + c[x[i]]; t[1 << i][j] = path[x[i]][j]; t[1 << i][j].push_back(x[i]); } } for (int i = 3; i < (1 << k); i++) { if (__builtin_popcount(i) > 1) { for (int j = 0; j < n * m; j++) { for (int sub = i; sub; sub = (sub - 1) & i) { if (sub == i) continue; cur = i ^ sub; for (int p = 0; p < n * m; p++) { if (dp[sub][p] + dp[cur][p] + f[p][j] - c[p] < dp[i][j]) { dp[i][j] = dp[sub][p] + dp[cur][p] + f[p][j] - c[p]; save = sub; X = p; } } } cur = i ^ save; t[i][j] = path[X][j]; for (int p = 0; p < ((int(t[save][X].size()))); p++) t[i][j].push_back(t[save][X][p]); for (int p = 0; p < ((int(t[cur][X].size()))); p++) { if (t[cur][X][p] != X) t[i][j].push_back(t[cur][X][p]); } } } } cout << dp[(1 << k) - 1][x[0]]; for (int i = 0; i < ((int(t[(1 << k) - 1][x[0]].size()))); i++) ans[t[(1 << k) - 1][x[0]][i] / m][t[(1 << k) - 1][x[0]][i] % m] = X ; for (int i = 0; i < n; i++) { cout << endl; for (int j = 0; j < m; j++) { if (ans[i][j] == X ) cout << ans[i][j]; else cout << . ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_PP_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxN = 50 + 10; long long dp[maxN]; int used[maxN]; int main() { int n; long long l; cin >> n >> l; dp[0] = 1; dp[1] = 1; for (int i = 2; i < maxN; i++) dp[i] = dp[i - 1] + dp[i - 2]; l--; for (int i = 0; i < n; i++) { int k = n - i; if (dp[k - 1] > l) cout << i + 1 << ; else { l -= dp[k - 1]; cout << i + 2 << << i + 1 << ; i++; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_SYMBOL_V
`define SKY130_FD_SC_HD__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, n, s, p, b, c; cin >> k >> n >> s >> p; float a = (n * 1.0) / s; b = ceil(a); c = b * k; float d = (c * 1.0) / p; int t = ceil(d); cout << t; } |
#include <bits/stdc++.h> using namespace std; long n, c[long(1e7 + 50)], cnt; void sieve() { c[1] = 1; for (long i = 2; i <= long(1e7); ++i) if (!c[i]) for (long j = 2; i * j <= long(1e7); ++j) c[i * j] = 1; } bool Prime(long x) { if (x < long(1e7)) { if (c[x]) return false; return true; } for (long i = 2; i <= trunc(sqrt(x)); ++i) if (!(x % i)) return false; return true; } int main() { scanf( %ld , &n); if (n <= 7) printf( 1 n%ld , n); else { printf( 3 n ); sieve(); n -= 3; for (long i = n; i >= 1; --i) if (Prime(i) && Prime(n - i)) { printf( %ld %ld %ld , i, n - i, 3); return 0; } } return 0; } |
// file: mmcm_mkid.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___128.008______0.000______50.0______116.987_____95.328
// CLK_OUT2___128.008_____90.000______50.0______116.987_____95.328
// CLK_OUT3___128.008____180.000______50.0______116.987_____95.328
// CLK_OUT4___128.008____270.000______50.0______116.987_____95.328
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________128.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "mmcm_mkid,clk_wiz_v3_6,{component_name=mmcm_mkid,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=7.812,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module mmcm_mkid
(// Clock in ports
input CLK_IN1,
input CLKFB_IN,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLKFB_OUT,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (90.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (180.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (8),
.CLKOUT3_PHASE (270.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (7.812),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (CLKFB_IN),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
assign CLKFB_OUT = clkfbout;
assign CLK_OUT1 = clkout0;
assign CLK_OUT2 = clkout1;
assign CLK_OUT3 = clkout2;
assign CLK_OUT4 = clkout3;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_axi_basic_tx.v
// Version : 1.11
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
PCIEBus_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
PCIEBus_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int query(int l, int r) { if (l < 1 || r > n) return false; string re; cout << 1 << << l << << r << endl; cin >> re; return re == TAK ; } int get(int l, int r) { if (l > r) return false; while (l < r) { int mid = (l + r) >> 1; if (query(mid, mid + 1)) r = mid; else l = mid + 1; } return l; } int main() { cin >> n >> k; int x, y; x = get(1, n); y = get(1, x - 1); if (!query(y, x)) y = get(x + 1, n); cout << 2 << << x << << y << endl; return 0; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_ac_ROM_no_ifdef_params (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter ROM_INIT_FILE_NAME = "AC_ROM.hex";
input clock;
input [31:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
//synthesis translate_off
.rden_a (1'b0),
//synthesis translate_on
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "AC_ROM.rif"
`else
altsyncram_component.init_file = ROM_INIT_FILE_NAME
`endif
,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 40,
altsyncram_component.numwords_b = 40,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2e5 + 5; long long int a[maxN], b[maxN]; int n; void solve() { cin >> n; set<pair<long long int, int>> s; int count = n; for (int i = 0; i < n; i++) { b[i] = 1; cin >> a[i]; s.insert({a[i], i}); } while (!s.empty()) { auto it1 = *(s.begin()); s.erase(s.begin()); if (s.empty()) break; auto it2 = *(s.begin()); if (it1.first == it2.first) { count--; s.erase(s.begin()); s.insert({2 * it2.first, it2.second}); a[it2.second] = 2 * it2.first; b[it1.second] = 0; } } cout << count << endl; for (int i = 0; i < n; i++) { if (b[i]) cout << a[i] << ; } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); int t = 1; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 2000; long long calcula(long long l, long long r, long long k) { long long d1 = -r; long long d2 = l - r; long long aum = d2 - d1; long long lim1 = d1; long long lim2 = d1 + (r * 1000000 - 1) * aum; if (lim1 <= k && k <= lim2 && (k - d1) % aum == 0) { long long num = (k - d1) / aum + 1; return num; } return -1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.precision(10); cout << fixed; long long k; cin >> k; for (long long i = 1; i <= N; i++) { for (long long j = 1; j <= N; j++) { if (i + j > N) break; long long aux = calcula(i, j, k); if (aux != -1) { cout << i + j << endl; for (long long a = 0; a < i - 1; a++) { cout << 0 << ; } cout << -1 << ; for (long long a = 0; a < j; a++) { cout << min(aux, 1000000ll) << ; aux -= min(aux, 1000000ll); } cout << endl; return 0; } } } cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int T, n, m; int t1, t2; bool w; map<pair<int, long long>, int> mex; int solve(int rem = 60, long long msk = (1 << 60) - 1) { if (mex.count({rem, msk})) { return mex[{rem, msk}]; } mex[{rem, msk}] = 0; int x = 0; set<int> s; for (int i = 1; i <= rem; ++i) { if ((msk >> i) & 1) s.insert( solve(rem - i, ((1ll << (rem - i + 1)) - 1) & (msk & ~(1ll << i)))); } while (s.count(x)) ++x; return mex[{rem, msk}] = x; } int main() { scanf( %d , &n); scanf( %d , &t1); T = solve(t1, (1ll << t1 + 1) - 1); for (int i = 1; i < n; ++i) { scanf( %d , &t1); T ^= solve(t1, (1ll << t1 + 1) - 1); } if (T) { printf( NO ); } else { printf( YES ); } printf( n ); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2222, mod = 998244353; int add(int x, int y) { x += y; return x >= mod ? x - mod : x; } int mul(int x, int y) { return 1ll * x * y % mod; } int qpow(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = mul(ans, a); a = mul(a, a), b >>= 1; } return ans; } int f[maxn][maxn], g[maxn], h[maxn], n, p, q, a, b, pp[maxn], pq[maxn], cc[maxn]; int main() { cin >> n >> a >> b; p = mul(a, qpow(b, mod - 2)); q = add(1, mod - p); for (int i = pp[0] = pq[0] = 1; i <= n; i++) pp[i] = mul(pp[i - 1], p), pq[i] = mul(pq[i - 1], q); f[0][0] = 1; for (int i = 0; i < n; i++) { for (int j = 0; j <= i; j++) { f[i + 1][j + 1] = add(f[i + 1][j + 1], mul(f[i][j], pq[i - j])); f[i + 1][j] = add(f[i + 1][j], mul(f[i][j], pp[j])); } } g[1] = 1, g[2] = 0; for (int i = 3; i <= n; i++) { g[i] = 1; for (int j = 1; j < i; j++) g[i] = add(g[i], mod - mul(g[j], f[i][j])); cc[i] = 1ll * i * (i - 1) / 2 % mod; } cc[2] = 1; h[1] = 0, h[2] = 1; for (int i = 3; i <= n; i++) { for (int j = 1; j < i; j++) { h[i] = add(h[i], mul(mul(f[i][j], g[j]), add(h[j], add(h[i - j], add(cc[i], mod - cc[i - j]))))); } h[i] = add(h[i], mul(g[i], cc[i])); h[i] = mul(h[i], qpow(add(1, mod - g[i]), mod - 2)); } cout << h[n]; return 0; } |
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
//Date : Tue Feb 14 01:36:24 2017
//Host : TheMosass-PC running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_4bits_tri_i,
leds_4bits_tri_io,
sws_4bits_tri_i);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [3:0]btns_4bits_tri_i;
inout [3:0]leds_4bits_tri_io;
input [3:0]sws_4bits_tri_i;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [3:0]btns_4bits_tri_i;
wire [0:0]leds_4bits_tri_i_0;
wire [1:1]leds_4bits_tri_i_1;
wire [2:2]leds_4bits_tri_i_2;
wire [3:3]leds_4bits_tri_i_3;
wire [0:0]leds_4bits_tri_io_0;
wire [1:1]leds_4bits_tri_io_1;
wire [2:2]leds_4bits_tri_io_2;
wire [3:3]leds_4bits_tri_io_3;
wire [0:0]leds_4bits_tri_o_0;
wire [1:1]leds_4bits_tri_o_1;
wire [2:2]leds_4bits_tri_o_2;
wire [3:3]leds_4bits_tri_o_3;
wire [0:0]leds_4bits_tri_t_0;
wire [1:1]leds_4bits_tri_t_1;
wire [2:2]leds_4bits_tri_t_2;
wire [3:3]leds_4bits_tri_t_3;
wire [3:0]sws_4bits_tri_i;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.btns_4bits_tri_i(btns_4bits_tri_i),
.leds_4bits_tri_i({leds_4bits_tri_i_3,leds_4bits_tri_i_2,leds_4bits_tri_i_1,leds_4bits_tri_i_0}),
.leds_4bits_tri_o({leds_4bits_tri_o_3,leds_4bits_tri_o_2,leds_4bits_tri_o_1,leds_4bits_tri_o_0}),
.leds_4bits_tri_t({leds_4bits_tri_t_3,leds_4bits_tri_t_2,leds_4bits_tri_t_1,leds_4bits_tri_t_0}),
.sws_4bits_tri_i(sws_4bits_tri_i));
IOBUF leds_4bits_tri_iobuf_0
(.I(leds_4bits_tri_o_0),
.IO(leds_4bits_tri_io[0]),
.O(leds_4bits_tri_i_0),
.T(leds_4bits_tri_t_0));
IOBUF leds_4bits_tri_iobuf_1
(.I(leds_4bits_tri_o_1),
.IO(leds_4bits_tri_io[1]),
.O(leds_4bits_tri_i_1),
.T(leds_4bits_tri_t_1));
IOBUF leds_4bits_tri_iobuf_2
(.I(leds_4bits_tri_o_2),
.IO(leds_4bits_tri_io[2]),
.O(leds_4bits_tri_i_2),
.T(leds_4bits_tri_t_2));
IOBUF leds_4bits_tri_iobuf_3
(.I(leds_4bits_tri_o_3),
.IO(leds_4bits_tri_io[3]),
.O(leds_4bits_tri_i_3),
.T(leds_4bits_tri_t_3));
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:42 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_stub.v
// Design : led_controller_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
module led_controller_design_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always release reg_lvalue ;
// D: No dependancy
module main ;
reg [3:0] value1 ;
initial
begin
#15;
if(value1 != 4'h5)
$display("FAILED - 3.1.3H always release rev_lvalue;\n");
else
begin
$display("PASSED\n");
$finish;
end
end
always release value1 ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND2_BEHAVIORAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); cout << 2 << endl; int prev = (n + n - 1) / 2; if ((n + n - 1) % 2 != 0) prev++; cout << n << << n - 1 << endl; for (int i = n - 2; i >= 1; i--) { int ad = 0; cout << i << << prev << endl; if ((i + prev) % 2 != 0) ad = 1; prev = (i + prev) / 2 + ad; } } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void gmin(T &x, const T &y) { x = x > y ? y : x; } template <class T> inline void gmax(T &x, const T &y) { x = x < y ? y : x; } template <class T> inline bool Gmin(T &x, const T &y) { return x > y ? x = y, 1 : 0; } template <class T> inline bool Gmax(T &x, const T &y) { return x < y ? x = y, 1 : 0; } const int BufferSize = 1 << 16; char buffer[BufferSize], *Bufferhead, *Buffertail; bool Terminal; inline char Getchar() { if (Bufferhead == Buffertail) { int l = fread(buffer, 1, BufferSize, stdin); if (!l) { Terminal = 1; return 0; } Buffertail = (Bufferhead = buffer) + l; } return *Bufferhead++; } template <class T> inline bool read(T &x) { x = 0; char c = Getchar(), rev = 0; while (c < 0 || c > 9 ) { rev |= c == - ; c = Getchar(); if (Terminal) return 0; } while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = Getchar(); if (c == . ) { c = Getchar(); double t = 0.1; while (c >= 0 && c <= 9 ) x = x + (c - 0 ) * t, c = Getchar(), t = t / 10; } x = rev ? -x : x; return 1; } template <class T1, class T2> inline bool read(T1 &x, T2 &y) { return read(x) & read(y); } template <class T1, class T2, class T3> inline bool read(T1 &x, T2 &y, T3 &z) { return read(x) & read(y) & read(z); } template <class T1, class T2, class T3, class T4> inline bool read(T1 &x, T2 &y, T3 &z, T4 &w) { return read(x) & read(y) & read(z) & read(w); } inline bool reads(char *x) { char c = Getchar(); while (c < 33 || c > 126) { c = Getchar(); if (Terminal) return 0; } while (c >= 33 && c <= 126) (*x++) = c, c = Getchar(); *x = 0; return 1; } template <class T> inline void print(T x, const char c = n ) { if (!x) { putchar( 0 ); putchar(c); return; } if (x < 0) putchar( - ), x = -x; int m = 0, a[20]; while (x) a[m++] = x % 10, x /= 10; while (m--) putchar(a[m] + 0 ); putchar(c); } const int inf = 0x3f3f3f3f; const int N = 25, M = 5005; int mod = 1e9 + 7; template <class T, class S> inline void ch(T &x, const S y) { x = (x + y) % mod; } inline int exp(int x, int y, const int mod = ::mod) { int ans = 1; while (y) { if (y & 1) ans = (long long)ans * x % mod; x = (long long)x * x % mod; y >>= 1; } return ans; } int cell[M], CNT; int c, c0, c1, c2, cnt, d, O, L = 2, R = 5001; inline int sum(int x, int y, int k = 0) { if (!k) k = ++L; printf( + %d %d %d n , x, y, k); ++CNT; cell[k] = (cell[x] + cell[y]) % mod; return k; } inline int power(int x, int k = 0) { if (!k) k = ++L; printf( ^ %d %d n , x, k); ++CNT; cell[k] = exp(cell[x], d); return k; } inline int zero() { int ans = --R, t = --R, y = mod - 1; while (y) { t = sum(t, t, t); y >>= 1; if (y & 1) ans = sum(ans, t); } return ans; } inline int multi(int x, int y) { int k = --R; int ans = sum(O, O, k), t = sum(x, O, --R); while (y) { if (y & 1) ans = sum(ans, t, ans); t = sum(t, t, t); y >>= 1; } return ans; } inline int neg(int x) { return multi(x, mod - 1); } inline int sub(int x, int y) { int t = neg(y); return sum(x, t, t); } inline int sqr(int x) { int a[N], b = ++L; b = multi(b, c); a[0] = multi(x, 1); for (int i = 1; i <= cnt; i++) a[i] = sum(a[i - 1], b); for (int i = 0; i <= cnt; i++) a[i] = power(a[i]); for (int i = 1; i <= cnt; i++) for (int j = 0; j <= cnt - i; j++) a[j] = sub(a[j + 1], a[j]); int t = ++L; a[0] = sub(a[0], sum(multi(x, c1), multi(++L, c0))); a[0] = multi(a[0], exp(c2, mod - 2)); return a[0]; } inline int find(int c, int &c2, int &c1, int &c0, int &cnt) { static int a[N], pw[N]; static int C[N][N]; for (int i = 0; i < d; i++) a[i] = 0; a[d] = 1; pw[0] = 1; for (int i = 1; i <= d; i++) pw[i] = (long long)pw[i - 1] * c % mod; for (int i = 0; i <= d; i++) { C[i][i] = C[i][0] = 1; for (int j = 1; j < i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } int m = d; cnt = 0; while (m > 2) { cnt++; for (int i = 0; i <= m; i++) { for (int j = 0; j < i; j++) ch(a[j], (long long)C[i][j] * a[i] % mod * pw[i - j]); a[i] = 0; } while (m >= 0 && !a[m]) m--; } if (m == 2) { c2 = a[2], c1 = a[1], c0 = a[0]; return 1; } return 0; } int main() { for (int i = 1; i <= 5000; i++) cell[i] = 1; scanf( %d%d , &d, &mod); int x = 1, y = 2; cell[x] = rand() % mod; cell[y] = rand() % mod; O = zero(); while (1) { c = rand() % mod; if (find(c, c2, c1, c0, cnt)) break; } int p1 = sqr(sum(x, y)), p2 = sqr(sub(x, y)); int g = sub(p1, p2), ans = multi(g, exp(4, mod - 2)); printf( f %d n , ans); if (cell[ans] ^ (1ll * cell[x] * cell[y] % mod)) fprintf(stderr, false ); cerr << CNT << = << CNT << endl; cerr << cnt << = << cnt << endl; return 0; } |
#include <bits/stdc++.h> inline int getint() { register char ch; while (!isdigit(ch = getchar())) ; register int x = ch ^ 0 ; while (isdigit(ch = getchar())) x = (((x << 2) + x) << 1) + (ch ^ 0 ); return x; } const long long mod = 1e9 + 7; const int N = 150001, M = 150002, K = 100001; void exgcd(const long long &a, const long long &b, long long &x, long long &y) { if (!b) { x = 1; y = 0; return; } exgcd(b, a % b, y, x); y -= a / b * x; } inline long long inv(const long long &x) { long long tmp, ret; exgcd(x, mod, ret, tmp); return (ret + mod) % mod; } long long f[2][M]; long long p[M], q[M]; long long fact[K], tcaf[K]; int k; inline long long calc(const int &x) { return fact[k] * tcaf[k - x] % mod * tcaf[x] % mod * p[x] % mod * q[k - x] % mod; } signed main() { int n = getint(), m = getint(); long long a = getint(), b = getint(); k = getint(); fact[0] = 1; for (register int i = 1; i <= k; i++) { fact[i] = fact[i - 1] * i % mod; } tcaf[k] = inv(fact[k]); for (register int i = k - 1; ~i; i--) { tcaf[i] = tcaf[i + 1] * (i + 1) % mod; } p[0] = q[0] = 1; p[1] = a * inv(b) % mod; q[1] = (b - a) * inv(b) % mod; for (register int i = 2; i <= k; i++) { p[i] = p[i - 1] * p[1] % mod; q[i] = q[i - 1] * q[1] % mod; } f[0][m] = 1; for (register int i = 1; i <= n; i++) { long long s1 = 0, s2 = 0; for (register int j = 0; j <= m; j++) { f[i & 1][j] = (s1 * (f[!(i & 1)][m] - f[!(i & 1)][m - j]) - s2) % mod * calc(m - j) % mod; s1 = (s1 + calc(j)) % mod; s2 = (s2 + f[!(i & 1)][j] * calc(j)) % mod; } for (register int j = 1; j <= m; j++) { f[i & 1][j] = (f[i & 1][j] + f[i & 1][j - 1]) % mod; } } printf( %I64d n , (f[n & 1][m] + mod) % mod); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == 9 || s[i] == H || s[i] == Q ) { cout << YES ; return 0; } } cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int ans[1009]; int main() { memset(ans, -1, sizeof(ans)); for (int i = 1; i <= 15; i += 2) { int x = (i * i + 1) / 2; int y = (i - 1) / 4 * 2; for (int j = 0; j <= y; j++) { for (int k = 0; k <= (x - 1 - 2 * y) / 4; k++) { for (int l = 0; l <= 1; l++) { if (x - 2 * j - 4 * k - l >= 0 && ans[x - 2 * j - 4 * k - l] == -1) ans[x - 2 * j - 4 * k - l] = i; } } } x = i * i - x; y = ((i - 1) / 2 + 1) / 2 * 2; for (int j = 0; j <= y; j++) for (int k = 0; k <= (x - 2 * y) / 4; k++) { if (x - 2 * j - 4 * k >= 0 && ans[x - 2 * j - 4 * k] == -1) ans[x - 2 * j - 4 * k] = i; } } int n; scanf( %d , &n); printf( %d , ans[n]); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 12:44:02 05/14/2016
// Design Name:
// Module Name: picture_hora
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module generador_imagenes
(
input wire video_on,//señal que indica que se encuentra en la región visible de resolución 640x480
input wire [9:0] pixel_x, pixel_y,
output wire pic_ring_on, pic_ringball_on,
output wire pic_on,
output wire [7:0] pic_RGB
);
//Declaración de constantes
//Imagen HORA
localparam pic_hora_XL = 9'd256; //Límite izquierdo
localparam pic_hora_XR = 9'd384; //Límite derecho
localparam pic_hora_Y = 7'd64; //Límite inferior
localparam hora_size = 14'd8192;//Cuantas líneas de texto se deben leer (valor se encuentra en Matlab, variable COLOR_HEX)
localparam pic_hora_XY = 7'd64;
//Imagen FECHA
localparam pic_fecha_XL = 8'd128; //Límite izquierdo
localparam pic_fecha_XR = 8'd208; //Límite derecho
localparam pic_fecha_YT = 9'd320; //Límite superior
localparam pic_fecha_YB = 9'd352; //Límite inferior
localparam pic_fecha_size = 12'd2560;// (80x32)
localparam pic_fecha_XY = 6'd32;
//Imagen TIMER
localparam pic_timer_XL = 9'd416; //Límite izquierdo
localparam pic_timer_XR = 9'd496; //Límite derecho
localparam pic_timer_YT = 9'd320; //Límite superior
localparam pic_timer_YB = 9'd352; //Límite inferior
localparam pic_timer_size = 12'd2560;// (80x32)
localparam pic_timer_XY = 6'd32;
//Imagen RING
localparam pic_ring_XL = 10'd512; //Límite izquierdo
localparam pic_ring_XR = 10'd639; //Límite derecho
localparam pic_ring_YT = 8'd128; //Límite superior
localparam pic_ring_YB = 8'd192; //Límite inferior
localparam pic_ring_size = 14'd8192;// (128x64)
localparam pic_ring_XY = 7'd64;
//Imagen RING ball
localparam pic_ringball_XL = 10'd544; //Límite izquierdo
localparam pic_ringball_XR = 10'd592; //Límite derecho
localparam pic_ringball_YT = 7'd64; //Límite superior
localparam pic_ringball_YB = 7'd112; //Límite inferior
localparam pic_ringball_size = 12'd2304;// (48x48)
localparam pic_ringball_XY = 6'd48;
//Imagen LOGO
localparam pic_logo_XL = 12'd0; //Límite derecho
localparam pic_logo_XR = 8'd128; //Límite derecho
localparam pic_logo_YT = 5'd0; //Límite inferior
localparam pic_logo_YB = 5'd16; //Límite inferior
localparam pic_logo_size = 12'd2048;// (128x16)
localparam pic_logo_XY = 5'd16;
//Declaración de señales
reg [7:0] colour_data_hora [0:hora_size-1]; //datos de los colores
reg [7:0] colour_data_fecha [0:pic_fecha_size-1]; //datos de los colores
reg [7:0] colour_data_timer [0:pic_timer_size-1]; //datos de los colores
reg [7:0] colour_data_ring [0:pic_ring_size-1]; //datos de los colores
reg [7:0] colour_data_ringball [0:pic_ringball_size-1]; //datos de los colores
reg [7:0] colour_data_logo [0:pic_logo_size-1]; //datos de los colores
wire [13:0] STATE_hora; //Bits dependen de hora_size
wire [11:0] STATE_fecha; //Bits dependen de hora_size
wire [11:0] STATE_timer; //Bits dependen de hora_size
wire [13:0] STATE_ring; //Bits dependen de hora_size
wire [11:0] STATE_ringball; //Bits dependen de hora_size
wire [11:0] STATE_logo; //Bits dependen de hora_size
wire pic_hora_on, pic_fecha_on, pic_timer_on, pic_logo_on;
reg [7:0] pic_RGB_aux;
//===================================================
// Imagen HORA
//===================================================
initial
$readmemh ("hora.list", colour_data_hora);
//Imprime la imagen de hora dentro de la región
assign pic_hora_on = (pic_hora_XL<=pixel_x)&&(pixel_x<=pic_hora_XR)&&(pixel_y<=pic_hora_Y);//Para saber cuando se está imprimiendo la imagen
assign STATE_hora = ((pixel_x-pic_hora_XL)*pic_hora_XY)+(pixel_y-pic_hora_Y); //Para generar el índice de la memoria
//===================================================
// Imagen FECHA
//===================================================
initial
$readmemh ("fecha.list", colour_data_fecha);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_fecha_on = (pic_fecha_XL<=pixel_x)&&(pixel_x<=pic_fecha_XR)&&(pic_fecha_YT<=pixel_y)&&(pixel_y<=pic_fecha_YB);//Para saber cuando se está imprimiendo la imagen
assign STATE_fecha = ((pixel_x-pic_fecha_XL)*pic_fecha_XY)+(pixel_y-pic_fecha_YT); //Para generar el índice de la memoria
//===================================================
// Imagen TIMER
//===================================================
initial
$readmemh ("timer.list", colour_data_timer);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_timer_on = (pic_timer_XL<=pixel_x)&&(pixel_x<=pic_timer_XR)&&(pic_timer_YT<=pixel_y)&&(pixel_y<=pic_timer_YB);//Para saber cuando se está imprimiendo la imagen
assign STATE_timer = ((pixel_x-pic_timer_XL)*pic_timer_XY)+(pixel_y-pic_timer_YT); //Para generar el índice de la memoria
//===================================================
// Imagen RING
//===================================================
initial
$readmemh ("ring.list", colour_data_ring);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_ring_on = (pic_ring_XL<=pixel_x)&&(pixel_x<=pic_ring_XR)&&(pic_ring_YT<=pixel_y)&&(pixel_y<=pic_ring_YB);//Para saber cuando se está imprimiendo la imagen
assign STATE_ring = ((pixel_x-pic_ring_XL)*pic_ring_XY)+(pixel_y-pic_ring_YT); //Para generar el índice de la memoria
//===================================================
// Imagen RING BALL
//===================================================
initial
$readmemh ("ring_ball_2.list", colour_data_ringball);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_ringball_on = (pic_ringball_XL<=pixel_x)&&(pixel_x<=pic_ringball_XR)&&(pic_ringball_YT<=pixel_y)&&(pixel_y<=pic_ringball_YB);//Para saber cuando se está imprimiendo la imagen
assign STATE_ringball = ((pixel_x-pic_ringball_XL)*pic_ringball_XY)+(pixel_y-pic_ringball_YT); //Para generar el índice de la memoria
//===================================================
// Imagen LOGO
//===================================================
initial
$readmemh ("logo.list", colour_data_logo);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_logo_on = (pixel_x<=pic_logo_XR)&&(pixel_y<=pic_logo_YB);//Para saber cuando se está imprimiendo la imagen
assign STATE_logo = ((pixel_x-pic_logo_XL)*pic_logo_XY)+(pixel_y-pic_logo_YT); //Para generar el índice de la memoria
//Multiplexa el RGB
always @*
begin
if(~video_on)
pic_RGB_aux = 8'b0;//fondo negro
else
if(pic_hora_on) pic_RGB_aux = colour_data_hora[{STATE_hora}];
else if (pic_fecha_on) pic_RGB_aux = colour_data_fecha[{STATE_fecha}];
else if (pic_timer_on) pic_RGB_aux = colour_data_timer[{STATE_timer}];
else if (pic_ring_on) pic_RGB_aux = colour_data_ring[{STATE_ring}];
else if (pic_ringball_on) pic_RGB_aux = colour_data_ringball[{STATE_ringball}];
else if (pic_logo_on) pic_RGB_aux = colour_data_logo[{STATE_logo}];
else pic_RGB_aux = 8'b0;//fondo negro
end
//assign pic_RGB = {pic_RGB_aux[7:5],1'b0,pic_RGB_aux[4:2],1'b0,pic_RGB_aux[1:0],2'b0}; //Rellena pic_RGB para pasar de 8 bits a 12 bits
assign pic_RGB = pic_RGB_aux;//Para 8 bits (Nexys 3)
assign pic_on = pic_hora_on | pic_timer_on | pic_fecha_on | pic_logo_on;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long u[11]; int main() { long long x, y, n, i, j, k = 0, l, arr[200009]; cin >> n; for (i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); for (i = 0, j = 1; i < n; i++) { if (arr[i] >= j) { k++; j++; } } cout << k << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; class ST { private: vector<long long> st; int n; int left(int p) { return p << 1; } int right(int p) { return left(p) + 1; } int query(int p, int L, int R, int i) { if (L > i) return 0; if (R <= i) return st[p]; return query(left(p), L, (L + R) >> 1, i) + query(right(p), ((L + R) >> 1) + 1, R, i); } int update(int p, int L, int R, int idx) { if (L > idx || R < idx) return st[p]; if (L == R) { return ++st[p]; } return st[p] = update(left(p), L, (L + R) >> 1, idx) + update(right(p), ((L + R) >> 1) + 1, R, idx); } public: ST(int _n) { n = _n; st.assign(4 * n, 0); } int query(int i) { int ret = query(1, 0, n - 1, i); update(i); return ret; } void update(int idx) { update(1, 0, n - 1, idx); } }; int main() { int n; map<long long, long long> mp; long long ans = 0; scanf( %I64d , &n); vector<long long> vec(n), vec2(n); for (long long i = 0; i < n; i++) scanf( %I64d , &vec[i]), vec2[i] = vec[i]; ST st(n); sort(vec2.begin(), vec2.end()); for (long long i = 0; i < n; i++) mp[vec2[i]] = i; for (long long i = 0; i < n - 1; i++) { long long q = st.query(mp[vec[i]]); ans += (i - q) * (mp[vec[i]] - q); } printf( %I64d , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFRTP_PP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> int n, m; char map[1010][1010], ans[1010][1010]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , map[i] + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) ans[i][j] = . ; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (map[i][j] != b ) continue; int c = a + 2 * ((i / 2 + j / 2) % 2) + i % 2; if (map[i - 1][j] == w && map[i + 1][j] == w ) ans[i - 1][j] = ans[i][j] = ans[i + 1][j] = c, map[i - 1][j] = map[i][j] = map[i + 1][j] = . ; else if (map[i][j - 1] == w && map[i][j + 1] == w ) ans[i][j - 1] = ans[i][j] = ans[i][j + 1] = c, map[i][j - 1] = map[i][j] = map[i][j + 1] = . ; } bool ok = true; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (map[i][j] != . ) ok = false; puts(ok ? YES : NO ); if (ok) for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) putchar(ans[i][j]); putchar( n ); } return 0; } |
// RX
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// RX module converts EPC Class 1 Gen 2 time domain protocol
// to a serial binary data stream
// Sample bitout on bitclk positive edges.
// TR cal measurement provided for TX clock calibration.
// RT cal for debugging purposes and possibly adjustment
// of oscillator frequency if necessary.
module rx (reset, clk, demodin, bitout, bitclk, rx_overflow_reset, trcal, rngbitout);
input reset, clk, demodin;
output bitout, bitclk, rx_overflow_reset, rngbitout;
output [9:0] trcal;
reg bitout, bitclk, rngbitout;
reg [9:0] trcal, rtcal;
// States
parameter STATE_DELIMITER = 5'd0;
parameter STATE_DATA0 = 5'd1;
parameter STATE_RTCAL = 5'd2;
parameter STATE_TRCAL = 5'd4;
parameter STATE_BITS = 5'd8;
reg [4:0] commstate;
parameter STATE_WAIT_DEMOD_LOW = 4'd0;
parameter STATE_WAIT_DEMOD_HIGH = 4'd1;
parameter STATE_EVAL_BIT = 4'd2;
parameter STATE_RESET_COUNTER = 4'd4;
reg [3:0] evalstate;
wire[9:0] count;
wire clkb;
assign clkb = ~clk;
reg counterreset, counterenable;
wire overflow;
wire counter_reset_in;
assign counter_reset_in = counterreset|reset;
counter10 counter (clkb, counter_reset_in, counterenable, count, overflow);
assign rx_overflow_reset = overflow | ((commstate == STATE_BITS) && (count > rtcal));
always @ (posedge clk or posedge reset) begin
if( reset ) begin
bitout <= 0;
bitclk <= 0;
rtcal <= 10'd0;
trcal <= 10'd0;
rngbitout <= 0;
counterreset <= 0;
counterenable <= 0;
commstate <= STATE_DELIMITER;
evalstate <= STATE_WAIT_DEMOD_LOW;
// process normal operation
end else begin
if(evalstate == STATE_WAIT_DEMOD_LOW) begin
if (demodin == 0) begin
evalstate <= STATE_WAIT_DEMOD_HIGH;
if(commstate != STATE_DELIMITER) counterenable <= 1;
else counterenable <= 0;
counterreset <= 0;
end
end else if(evalstate == STATE_WAIT_DEMOD_HIGH) begin
if (demodin == 1) begin
evalstate <= STATE_EVAL_BIT;
counterenable <= 1;
counterreset <= 0;
end
end else if(evalstate == STATE_EVAL_BIT) begin
counterreset <= 1;
evalstate <= STATE_RESET_COUNTER;
bitclk <= 0;
rngbitout <= count[0];
case(commstate)
STATE_DELIMITER: begin
commstate <= STATE_DATA0;
end
STATE_DATA0: begin
commstate <= STATE_RTCAL;
end
STATE_RTCAL: begin
rtcal <= count;
commstate <= STATE_TRCAL;
end
STATE_TRCAL: begin
if(count > rtcal) begin
trcal <= count;
end else if(count[8:0] > rtcal[9:1]) begin // divide rtcal by 2
bitout <= 1;
commstate <= STATE_BITS;
end else begin
bitout <= 0;
commstate <= STATE_BITS;
end
end
STATE_BITS: begin
if(count[8:0] > rtcal[9:1]) begin // data 1 (divide rtcal by 2)
bitout <= 1;
end else begin // data 0
bitout <= 0;
end
end
default: begin
counterreset <= 0;
commstate <= 0;
end
endcase // case(mode)
end else if(evalstate == STATE_RESET_COUNTER) begin
if(commstate == STATE_BITS) begin
bitclk <= 1;
end
counterreset <= 0;
evalstate <= STATE_WAIT_DEMOD_LOW;
end else begin // unknown state, reset.
evalstate <= 0;
end
end // ~reset
end // always @ clk
endmodule //
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [9:0] in = crc[9:0];
/*AUTOWIRE*/
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[9:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [9:0] in;
reg a [9:0];
integer ai;
always @* begin
for (ai=0;ai<10;ai=ai+1) begin
a[ai]=in[ai];
end
end
reg [1:0] b [9:0];
integer j;
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
for (j=0; j<10; j=j+1) begin
if (a[j])
b[i][j] <= 1'b0;
else
b[i][j] <= 1'b1;
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k, u = 0, ans1 = 0, ans2 = 0; cin >> n >> m >> k; bool a[n][m]; long long sum[n + 2][m]; memset(sum, 0, sizeof(sum)); for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { cin >> a[i][j]; sum[i][j] = (i ? sum[i - 1][j] : 0) + a[i][j]; if (i >= k) sum[i][j] -= a[u][j]; if (sum[i][j] > sum[n][j]) { sum[n][j] = sum[i][j]; sum[n + 1][j] = i - k + 1; } } u += (i >= k); } for (long long j = 0; j < m; j++) { ans1 += sum[n][j]; for (long long i = 0; i < sum[n + 1][j]; i++) ans2 += a[i][j]; } cout << ans1 << << ans2; return 0; } |
#include <bits/stdc++.h> const long long max9 = 10 + 1e9, max6 = 10 + 1e6, max12 = 10 + 1e12, max15 = 10 + 1e15; const long long min6 = -1 * max6, min9 = -1 * max9, min12 = -1 * max12, min15 = -1 * max15; const long long R = 7 + 1e9, NN = 10 + 1e5; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; bool a[n * k + 1]; memset(a, false, sizeof(a)); int t[k]; for (int i = (0); i < (k); ++i) cin >> t[i]; for (int i = (0); i < (k); ++i) { a[t[i] - 1] = true; } for (int i = (0); i < (k); ++i) { cout << t[i] << ; int o = 1; for (int j = (0); j < (n * k + 1); ++j) { if (!a[j]) { cout << j + 1 << ; o++; a[j] = true; } if (o == n) { cout << endl; break; } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A221O_PP_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_PP_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
//
// PS2-to-Kempston Mouse
// (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
////////////////////////////////////////////////////////////////////////////////
module mouse
(
input clk_sys,
input reset,
input [24:0] ps2_mouse,
input [2:0] addr,
output sel,
output [7:0] dout
);
assign dout = data;
assign sel = port_sel;
reg [1:0] button;
reg mbutton;
reg [11:0] dx;
reg [11:0] dy;
wire [11:0] newdx = dx + {{4{ps2_mouse[4]}},ps2_mouse[15:8]};
wire [11:0] newdy = dy + {{4{ps2_mouse[5]}},ps2_mouse[23:16]};
reg [1:0] swap;
reg [7:0] data;
reg port_sel;
always @* begin
port_sel = 1;
casex(addr)
3'b011: data = dx[7:0];
3'b111: data = dy[7:0];
3'bX10: data = ~{5'b00000,mbutton, button[swap[1]], button[~swap[1]]} ;
default: {port_sel,data} = 8'hFF;
endcase
end
always @(posedge clk_sys) begin
reg old_status;
old_status <= ps2_mouse[24];
if(reset) begin
dx <= 128; // dx != dy for better mouse detection
dy <= 0;
button <= 0;
swap <= 0;
end else begin
if(old_status != ps2_mouse[24]) begin
if(!swap) swap <= ps2_mouse[1:0];
{mbutton,button} <= ps2_mouse[2:0];
dx <= newdx;
dy <= newdy;
end
end
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module system_control_tb();
reg aux_clk, clk_fpga;
wire wb_clk, dsp_clk;
wire wb_rst, dsp_rst, rl_rst, proc_rst;
reg rl_done, clock_ready;
initial aux_clk = 1'b0;
always #25 aux_clk = ~aux_clk;
initial clk_fpga = 1'b0;
initial clock_ready = 1'b0;
initial
begin
@(negedge proc_rst);
#1003 clock_ready <= 1'b1;
end
always #7 clk_fpga = ~clk_fpga;
initial begin
$dumpfile("system_control_tb.vcd");
$dumpvars(0,system_control_tb);
end
initial #10000 $finish;
initial
begin
@(negedge rl_rst);
rl_done <= 1'b0;
#1325 rl_done <= 1'b1;
end
initial
begin
@(negedge proc_rst);
clock_ready <= 1'b0;
#327 clock_ready <= 1'b1;
end
system_control
system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
.dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
.ram_loader_rst_o(rl_rst),
.processor_rst_o(proc_rst),
.wb_rst_o(wb_rst),
.dsp_rst_o(dsp_rst),
.ram_loader_done_i(rl_done),
.clock_ready_i(clock_ready),
.debug_o());
endmodule // system_control_tb
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$PR_pp$PKG$s: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PKG$s (
Q ,
D ,
CLK ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_BLACKBOX_V
|
//Dummy tb for sound channel 4.
//Tb is only for debug this module.
`timescale 1ns / 1ps
`include "aDefinitions.v"
`include "collaterals.v"
`include "SoundControllerChannel2.v"
`include "SoundControllerOSC1.v"
`include "SoundControllerOSC2.v"
module tb;
reg clk;
wire clk64;
wire clk256;
wire clk131k;
wire clk262k;
reg rst;
wire [4:0] out;
reg [7:0] nr20;
reg [7:0] nr21;
reg [7:0] nr22;
reg [7:0] nr23;
reg [7:0] nr24;
always begin
#`CLOCK_CYCLE clk = ~clk;
end
osc1 o1
(
.iClock(clk),
.iReset(rst),
.oOut64(clk64),
.oOut256(clk256)
);
osc2 o2
(
.iClock(clk),
.iReset(rst),
.oOut131k(clk131k),
.oOut262k(clk262k)
);
SoundCtrlChannel2 # () scc2 (
.iClock(clk),
.iReset(rst),
.iOsc64(clk64),
.iOsc256(clk256),
.iOsc262k(clk262k),
.iNR21(nr21),
.iNR22(nr22),
.iNR23(nr23),
.iNR24(nr24),
.oOut(out)
);
initial begin
$dumpfile("dump_sound_channel2.vcd");
$dumpvars();
$display("tiempo \t\t out2");
$monitor ("%0d \t\t %0d",$time, out);
clk = 0;
rst = 1'b0;
#10 rst = 1'b1;
//test1
/*
nr21 = 8'h03; // length = $03 = 03.
nr22 = 8'hF4; // attenuate envelope, step time = 3. initial value = $F = 15.
nr23 = 8'hBC; // low fre = $BC.
nr24 = 8'h43; // high freq = $3, freq = $3BC = 956. timer enabled.
*/
//test2
/*
nr21 = 8'h50; // length = $1F = 31.
nr22 = 8'h1C; // amplify envelope, step time = 7. initial value = $2 = 2.
nr23 = 8'hBC; // low freq = $BC.
nr24 = 8'h03; // high freq = $3 , freq = $3BC = 956. time disabled.
*/
repeat (2) @ (negedge clk);
rst = 1'b0;
#50_000_000;
$finish;
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1, -1, -1, 1, 1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; template <class T> inline T biton(T n, T pos) { return n | ((T)1 << pos); } template <class T> inline T bitoff(T n, T pos) { return n & ~((T)1 << pos); } template <class T> inline T ison(T n, T pos) { return (bool)(n & ((T)1 << pos)); } template <class T> inline T gcd(T a, T b) { while (b) { a %= b; swap(a, b); } return a; } template <typename T> string NumberToString(T Number) { ostringstream second; second << Number; return second.str(); } inline int nxt() { int aaa; scanf( %d , &aaa); return aaa; } inline long long int lxt() { long long int aaa; scanf( %lld , &aaa); return aaa; } inline double dxt() { double aaa; scanf( %lf , &aaa); return aaa; } template <class T> inline T bigmod(T p, T e, T m) { T ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % m; p = (p * p) % m; } return (T)ret; } int ar[200010]; vector<int> v; map<int, int> mp; int main() { int c = 0; int i = 1; while (1) { if (c > 100000) break; c += i; v.push_back(c); mp[c] = i; i++; } int n = nxt(); if (n == 0) { cout << a << endl; return 0; } vector<int> ans; while (n) { for (int i = v.size() - 1; i >= 0; i--) { if (v[i] <= n) { ans.push_back(v[i]); n -= v[i]; } } } int t = 0; for (int i = 0; i < ans.size(); i++) { int x = ans[i]; int lagbe = mp[x]; for (int j = 0; j <= lagbe; j++) { printf( %c , t + a ); } t++; } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000010, P = 2000010; int f[P]; int n, t, a[N]; int d[N], g[N], r[P]; vector<int> q[P], v[N]; void init(int c, int p) { vector<int> z; int cv = a[c]; d[c] = d[p] + 1; g[c] = -1; if (c == 1) fill(r + 1, r + P, -1); for (int i = 0; i < q[cv].size(); i++) { int t = q[cv][i]; if (g[c] == -1 || d[r[t]] > d[g[c]]) g[c] = r[t]; z.push_back(r[t]); r[t] = c; } for (int i = 0; i < v[c].size(); i++) if (v[c][i] != p) init(v[c][i], c); for (int i = 0; i < q[cv].size(); i++) r[q[cv][i]] = z[i]; } int main() { scanf( %d %d , &n, &t); for (int i = 2; i < P; i++) if (!f[i]) for (int j = 1; i * j < P; j++) f[i * j] = i; for (int i = 2; i < P; i++) { int c = i / f[i]; if (f[c] != f[i]) q[i].push_back(f[i]); for (int j = 0; j < q[c].size(); j++) q[i].push_back(q[c][j]); } for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) { int x, y; scanf( %d %d , &x, &y); v[x].push_back(y); v[y].push_back(x); } init(1, 0); while (t--) { int k; scanf( %d , &k); if (k == 1) { int c; scanf( %d , &c); printf( %d n , g[c]); } else { int x, y; scanf( %d %d , &x, &y); a[x] = y; init(1, 0); } } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 22 19:34:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.v
// Design : system_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_0_0(clk_out1, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */;
output clk_out1;
output locked;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; void ASS(bool bb) { if (!bb) { ++*(int*)0; } } #pragma comment(linker, /STACK:106777216 ) int read() { int x; scanf( %d , &x); return x; } int main() { int k, b, n; k = read(); b = read(); n = read(); map<int, int> mp; int s = 0; int zer = 0; long long res = 0; for (int i = 0; i < (int)(n); i++) { ++mp[s]; int x = read(); s = (s + x) % (k - 1); if (x == 0) zer++; else zer = 0; if (b == 0) res += zer; else { res += mp[(s + k - 1 - b) % (k - 1)]; if (b == k - 1) res -= zer; } } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const int maxn = 1000000 + 5; const double PI = acos(-1.0); const double E = 2.718281828459; const double eps = 1e-7; int T, n, num[100005]; int main() { long k, n = 19, x = 0, m; scanf( %ld , &k); while (k - 1 > 0) { x = 0; n++; m = n; while (m > 0) { x += m % 10; m /= 10; } if (x == 10) { k--; } } printf( %ld n , n); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long x, y; cin >> x >> y; long long l = x - y; l = l < 0 ? -l : l; int r = l % 10; long long a = l / 10.0; if (r) a++; cout << a; cout << n ; } } |
#include <bits/stdc++.h> using namespace std; vector<int> E[1010000]; int n, m, T[1010000]; bool v[1010000]; void DFS(int a) { v[a] = true; int i; for (i = 0; i < E[a].size(); i++) { if (!v[E[a][i]]) DFS(E[a][i]); } } long long Res; int main() { int i, a, b, ck = 0, cc = 0; scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { scanf( %d%d , &a, &b); if (a == b) { cc++; T[a]++; } E[a].push_back(b); E[b].push_back(a); } Res = 1ll * cc * (m - cc) + 1ll * cc * (cc - 1) / 2; for (i = 1; i <= n; i++) { if (!E[i].empty()) { if (!v[i] && ck) { printf( 0 n ); return 0; } ck = 1; DFS(i); } } for (i = 1; i <= n; i++) { int t = E[i].size() - T[i] * 2; Res += 1ll * t * (t - 1) / 2; } printf( %lld n , Res); } |
#include <bits/stdc++.h> using namespace std; int n; int main() { scanf( %d , &n); if (n & 1) printf( %d n , (n - 1) / 2); else { int w = 1; while (w <= n) w *= 2; w /= 2; printf( %d n , (n - w) / 2); } return 0; } |
// file: OpenSSD2_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0_______81.410_____74.126
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module OpenSSD2_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset
);
// Input buffering
//------------------------------------
BUFG clkin1_bufg
(.O (clk_in1_OpenSSD2_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_OpenSSD2_clk_wiz_0_0;
wire clkfbout_buf_OpenSSD2_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (15.750),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (7.875),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_OpenSSD2_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_OpenSSD2_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_OpenSSD2_clk_wiz_0_0),
.CLKIN1 (clk_in1_OpenSSD2_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_OpenSSD2_clk_wiz_0_0),
.I (clkfbout_OpenSSD2_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_OpenSSD2_clk_wiz_0_0));
endmodule
|
`timescale 1ns / 1ps
`include "aDefinitions.v"
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ()
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
module pGB
(
input wire iClock,
`ifdef VGA_ENABLED
output wire [3:0] oVgaRed,
output wire [3:0] oVgaGreen,
output wire [3:0] oVgaBlue,
output wire oVgaHsync,
output wire oVgaVsync,
`endif
//IO input ports
//ASCII IMAGE BUTTON MATRIX
input wire [5:0] iButtonRegister, //Pressed button
`ifndef XILINX_IP
output wire oFrameBufferWe,
output wire [15:0] oFrameBufferData,
output wire [15:0] oFrameBufferAddr,
`endif
input wire iReset
);
wire [15:0] wdZCPU_2_MMU_Addr, wGPU_2_MCU_Addr;
wire [7:0] wdZCPU_2_MMU_WriteData, wMMU_ReadData;
wire wdZCPU_2_MMU_We, wdZCPU_2_MMU_ReadRequest;
wire[7:0] wGPU_2_MCU_LCDC;
wire[7:0] wGPU_2_MCU_STAT;
wire[7:0] wGPU_2_MCU_SCY;
wire[7:0] wGPU_2_MCU_SCX;
wire[7:0] wGPU_2_MCU_LY;
wire[7:0] wGPU_2_MCU_LYC;
wire[7:0] wGPU_2_MCU_DMA;
wire[7:0] wGPU_2_MCU_BGP;
wire[7:0] wGPU_2_MCU_OBP0;
wire[7:0] wGPU_2_MCU_OBP1;
wire[7:0] wGPU_2_MCU_WY;
wire[7:0] wGPU_2_MCU_WX, wGPU_RegData, wMMU_2_GPU_VmemReadData;
wire[7:0] wButtonRegister;
wire[15:0] wGpuAddr;
wire[3:0] wGpu_RegSelect;
wire wGpu_RegWe, wGPU_2_MCU_ReadRequest;
wire wIOInterruptTrigger;
dzcpu DZCPU
(
.iClock( iClock ),
.iReset( iReset ),
.iMCUData( wMMU_ReadData ),
.oMCUAddr( wdZCPU_2_MMU_Addr ),
.oMCUwe( wdZCPU_2_MMU_We ),
.oMCUData( wdZCPU_2_MMU_WriteData ),
.oMcuReadRequest( wdZCPU_2_MMU_ReadRequest )
);
assign wButtonRegister[7:6] = 2'b0;
//IO unit is in charge of marshalling the GameBoy push butons
io IO
(
.Clock( iClock ),
.Reset( iReset ),
.iP( iButtonRegister ),
.oP( wButtonRegister[5:0] ),
.oIE( wIOInterruptTrigger )
);
mmu MMU
(
.iClock( iClock ),
.iReset( iReset ),
//CPU
.iCpuReadRequest( wdZCPU_2_MMU_ReadRequest ),
.iGpuReadRequest( wGPU_2_MCU_ReadRequest ),
.iCpuAddr( wdZCPU_2_MMU_Addr ),
.iCpuWe( wdZCPU_2_MMU_We ),
.iCpuData( wdZCPU_2_MMU_WriteData ),
.oCpuData( wMMU_ReadData ),
//GPU
.oGpuVmemReadData( wMMU_2_GPU_VmemReadData ),
.iGpuAddr( wGPU_2_MCU_Addr ),
.oGPU_RegData( wGPU_RegData ),
.oGpu_RegSelect( wGpu_RegSelect ),
.oGpu_RegWe( wGpu_RegWe ),
.iGPU_LCDC( wGPU_2_MCU_LCDC ),
.iGPU_STAT( wGPU_2_MCU_STAT ),
.iGPU_SCY( wGPU_2_MCU_SCY ),
.iGPU_SCX( wGPU_2_MCU_SCX ),
.iGPU_LY( wGPU_2_MCU_LY ),
.iGPU_LYC( wGPU_2_MCU_LYC ),
.iGPU_DMA( wGPU_2_MCU_DMA ),
.iGPU_BGP( wGPU_2_MCU_BGP ),
.iGPU_OBP0( wGPU_2_MCU_OBP0 ),
.iGPU_OBP1( wGPU_2_MCU_OBP1 ),
.iGPU_WY( wGPU_2_MCU_WY ),
.iGPU_WX( wGPU_2_MCU_WX ),
//IO
.iButtonRegister( wButtonRegister )
);
`ifdef VGA_ENABLED
wire [15:0] wFramBufferWriteData, wVgaFBReadData, wVgaFBReadData_Pre, wFrameBufferReadAddress, wFramBufferWriteAddress;
wire [15:0] wVgaRow, wVgaCol;
wire [3:0] wVgaR, wVgaG, wVgaB;
wire [9:0] wVgaFBReadAddr;
wire [1:0] wVgaColor2Bits;
wire wFramBufferWe;
RAM_SINGLE_READ_PORT # ( .DATA_WIDTH(16), .ADDR_WIDTH(10), .MEM_SIZE(8192) ) FBUFFER
(
.Clock( iClock ), //TODO: Should we use graphic clock here?
.iWriteEnable( wFramBufferWe ),
//.iReadAddress0( {3'b0,wFrameBufferReadAddress[15:3]} ), //Divide by 8
.iReadAddress0( wFrameBufferReadAddress ), //Divide by 8
.iWriteAddress( wFramBufferWriteAddress ),
.iDataIn( wFramBufferWriteData ),
.oDataOut0( wVgaFBReadData_Pre )
);
assign wFrameBufferReadAddress = (wVgaRow << 5) + (wVgaCol >> 3);
MUXFULLPARALELL_3SEL_GENERIC # (2) MUX_COLOR (
.Sel( wVgaCol[2:0] ),
.I7( wVgaFBReadData_Pre[1:0]),
.I6( wVgaFBReadData_Pre[3:2]),
.I5( wVgaFBReadData_Pre[5:4]),
.I4( wVgaFBReadData_Pre[7:6]) ,
.I3( wVgaFBReadData_Pre[9:8]),
.I2( wVgaFBReadData_Pre[11:10]),
.I1( wVgaFBReadData_Pre[13:12]),
.I0( wVgaFBReadData_Pre[15:14]) ,
.O( wVgaColor2Bits )
);
wire [3:0] wRed,wGreen,wBlue;
MUXFULLPARALELL_2SEL_GENERIC # (12) MUX_COLOR_OUT (
.Sel( wVgaColor2Bits ),
.I0( {4'b0000, 4'b0000, 4'b0000 } ),
.I1( {4'b1111, 4'b0000, 4'b0000 } ),
.I2( {4'b0000, 4'b1111, 4'b0000 } ),
.I3( {4'b0000, 4'b0000, 4'b1111 }) ,
.O( {wRed,wGreen,wBlue} )
);
assign oVgaRed = ( wVgaRow >= 16'd255 || wVgaCol >= 255 ) ? 4'b0111 : wRed;
assign oVgaGreen = ( wVgaRow >= 16'd255 || wVgaCol >= 255 ) ? 4'b0111 : wGreen;
assign oVgaBlue = ( wVgaRow >= 16'd255 || wVgaCol >= 255 ) ? 4'b0111 : wBlue;
VgaController VGA
(
.Clock(iClock),
.Reset(iReset),
.oVgaVsync( oVgaVsync ),
.oVgaHsync( oVgaHsync ),
/*.oVgaRed( oVgaRed ),
.oVgaGreen( oVgaGreen ),
.oVgaBlue( oVgaBlue ),*/
.oRow( wVgaRow ),
.oCol( wVgaCol )
);
`ifndef XILINX_IP
assign oFrameBufferAddr = wFramBufferWriteAddress;
assign oFrameBufferData = wFramBufferWriteData;
assign oFrameBufferWe = wFramBufferWe;
`endif
`endif
gpu GPU
(
.iClock( iClock ),
.iReset( iReset ),
`ifndef VGA_ENABLED
.oFramBufferWe( oFrameBufferWe ),
.oFramBufferData( oFrameBufferData ),
.oFramBufferAddr( oFrameBufferAddr ),
`else
.oFramBufferWe( wFramBufferWe ),
.oFramBufferData( wFramBufferWriteData ),
.oFramBufferAddr( wFramBufferWriteAddress ),
`endif
.oMcuAddr( wGPU_2_MCU_Addr ),
.oMcuReadRequest( wGPU_2_MCU_ReadRequest ),
.iMcuRegSelect( wGpu_RegSelect),
.iMcuWriteData( wGPU_RegData ),
.iMcuReadData( wMMU_2_GPU_VmemReadData ),
.iMcuWe( wGpu_RegWe ),
.oSTAT( wGPU_2_MCU_STAT ),
.oLCDC( wGPU_2_MCU_LCDC ),
.oSCY( wGPU_2_MCU_SCY ),
.oSCX( wGPU_2_MCU_SCX ),
.oLY( wGPU_2_MCU_LY ),
.oLYC( wGPU_2_MCU_LYC ),
.oDMA( wGPU_2_MCU_DMA ),
.oBGP( wGPU_2_MCU_BGP ),
.oOBP0( wGPU_2_MCU_OBP0 ),
.oOBP1( wGPU_2_MCU_OBP1 ),
.oWY( wGPU_2_MCU_WY ),
.oWX( wGPU_2_MCU_WX )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > anom; long long int fact[200005]; long long int invfact[200005]; long long int MOD = 1000000007; long long int dp[2005][25]; long long int invmod(long long int i) { long long int ans = 1; long long int mult = i; long long int exp = MOD - 2; while (exp > 0) { if (exp % 2 == 1) { ans = (ans * mult) % MOD; } mult = (mult * mult) % MOD; exp /= 2; } return ans; } void precomp() { fact[0] = 1; invfact[0] = 1; for (long long int i = 1; i < 200005; i++) { fact[i] = (fact[i - 1] * i) % MOD; invfact[i] = (invfact[i - 1] * invmod(i)) % MOD; } } long long int comb(int a, int b) { long long int ans = (fact[a] * invfact[b]) % MOD; ans = (ans * invfact[a - b]) % MOD; return ans; } long long int paths(int a, int b, int c, int d) { if (a <= c && b <= d) { return comb(c - a + d - b, c - a); } return 0; } int main() { precomp(); int n, m, k, s; cin >> n >> m >> k >> s; if (k == 0) { cout << s << endl; return 0; } int limred = ceil(log2(s)) + 1; int a, b; for (int i = 0; i < k; i++) { cin >> a >> b; anom.push_back({a, b}); } sort(anom.begin(), anom.end()); bool beginanom = true; if (k > 0 && anom[k] != make_pair(1, 1)) { anom.push_back({1, 1}); beginanom = false; k++; } sort(anom.begin(), anom.end()); for (int i = k - 1; i >= 0; i--) { dp[i][0] = paths(anom[i].first, anom[i].second, n, m); for (int j = i + 1; j < k; j++) { dp[i][0] = (dp[i][0] - (dp[j][0] * paths(anom[i].first, anom[i].second, anom[j].first, anom[j].second)) % MOD + MOD) % MOD; } } for (int i = 1; i <= limred; i++) { for (int j = k - 1; j >= 0; j--) { dp[j][i] = paths(anom[j].first, anom[j].second, n, m); for (int p = j + 1; p < k; p++) { dp[j][i] = (dp[j][i] - (dp[p][i] * paths(anom[j].first, anom[j].second, anom[p].first, anom[p].second)) % MOD + MOD) % MOD; } for (int p = 0; p < i; p++) { dp[j][i] = (dp[j][i] - dp[j][p] + MOD) % MOD; } } } int prevs; long long int expsum = 0; long long int numways = 0; for (int i = 0; i <= limred; i++) { prevs = s; s = ceil(s / 2.0); if (beginanom) { expsum = (expsum + (s * dp[0][i]) % MOD) % MOD; } else { expsum = (expsum + (prevs * dp[0][i]) % MOD) % MOD; } numways = (numways + dp[0][i]) % MOD; } long long int leftways = paths(1, 1, n, m); leftways = (leftways - numways + MOD) % MOD; expsum = (expsum + leftways) % MOD; long long int ans = (expsum * invmod(comb(n + m - 2, n - 1))) % MOD; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; unordered_set<string> has_handle; unordered_set<string> is_new; unordered_map<string, string> handle; vector<string> handles_new; vector<string> handles_old; void solve(string old) { if (is_new.count(old)) return; handles_old.push_back(old); string temp; while (true) { temp = handle[old]; if (has_handle.count(temp) == 0) break; old = temp; } handles_new.push_back(temp); } int main() { int q; cin >> q; string old_handle[q], new_handle[q]; for (int i = 0; i < q; i++) { cin >> old_handle[i] >> new_handle[i]; has_handle.insert(old_handle[i]); is_new.insert(new_handle[i]); handle[old_handle[i]] = new_handle[i]; } for (int i = 0; i < q; i++) solve(old_handle[i]); int cnt = handles_new.size(); cout << cnt << endl; for (int i = 0; i < cnt; i++) cout << handles_old[i] << << handles_new[i] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2000000000; const int N = 1e5 + 5; const int TN = 1 << 18; const double PI = acos(-1); int n, m, k; long long tree[TN], lazy[TN] = {0}; void probagate(int l, int r, int p) { tree[p] |= lazy[p]; if (l != r) { lazy[p << 1] |= lazy[p]; lazy[(p << 1) | 1] |= lazy[p]; } lazy[p] = 0; } void update(int val, int ql, int qr, int l = 0, int r = n - 1, int p = 1) { probagate(l, r, p); if (ql > r || qr < l) return; if (ql <= l && r <= qr) { lazy[p] |= val; probagate(l, r, p); return; } int m = (l + r) >> 1; update(val, ql, qr, l, m, (p << 1)); update(val, ql, qr, m + 1, r, (p << 1) | 1); tree[p] = tree[(p << 1)] & tree[(p << 1) | 1]; } int get(int ql, int qr, int l = 0, int r = n - 1, int p = 1) { probagate(l, r, p); if (ql > r || qr < l) return (1LL << 31) - 1; if (ql <= l && r <= qr) { return tree[p]; } int m = (l + r) >> 1; return get(ql, qr, l, m, (p << 1)) & get(ql, qr, m + 1, r, (p << 1) | 1); } void print(int l = 0, int r = n - 1, int p = 1) { probagate(l, r, p); if (l == r) { printf( %d , tree[p]); return; } int m = (l + r) >> 1; print(l, m, (p << 1)); print(m + 1, r, (p << 1) | 1); } int main() { scanf( %d%d , &n, &m); vector<pair<pair<int, int>, int>> v; for (int i = 0; i < m; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); a--; b--; v.push_back({{a, b}, c}); update(c, a, b); } for (int i = 0; i < m; i++) { int a = v[i].first.first; int b = v[i].first.second; int c = v[i].second; if (get(a, b) != c) { return puts( NO ); } } puts( YES ); print(); } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_arb_mux
*/
module test_axis_arb_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_arb_mux_4.lxt");
$dumpvars(0, test_axis_arb_mux_4);
end
axis_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:57:43 05/19/2015
// Design Name: dilation3x3
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/tb_dilation3x3.v
// Project Name: vision
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: dilation3x3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_dilation3x3(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
// proccessing
reg [7:0] dilation_r;
reg [7:0] dilation_g;
reg [7:0] dilation_b;
wire dilation;
wire dilation_de;
wire dilation_vsync;
wire dilation_hsync;
dilation3x3 #
(
.H_SIZE(10'd83)
)
dilate3
(
.clk(rx_pclk),
.ce(1'b1),
.rst(1'b0),
.mask((rx_red == 8'hFF) ? 1'b1 : 1'b0),
.in_de(rx_de),
.in_vsync(rx_vsync),
.in_hsync(rx_hsync),
.dilated(dilation),
.out_de(dilation_de),
.out_vsync(dilation_vsync),
.out_hsync(dilation_hsync)
);
always @(posedge rx_pclk) begin
dilation_r = (dilation) ? 8'hFF : 8'h00;
dilation_g = (dilation) ? 8'hFF : 8'h00;
dilation_b = (dilation) ? 8'hFF : 8'h00;
end
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = dilation_de;
assign tx_hsync = dilation_hsync;
assign tx_vsync = dilation_vsync;
assign tx_red = dilation_r;
assign tx_green = dilation_g;
assign tx_blue = dilation_b;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
// Dummy simulations of Altera PLLs
`timescale 1ns/10ps
module pll1(input wire inclk0,
output wire c0,
output wire c1,
output wire locked,
output wire e0);
assign c0 = inclk0;
assign c1 = inclk0;
assign locked = 1;
assign e0 = inclk0;
endmodule
module pll2(input wire inclk0,
output wire c0,
output wire c1,
output wire locked,
output wire e0);
assign c0 = inclk0;
assign c1 = inclk0;
assign locked = 1;
assign e0 = inclk0;
endmodule
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module byteen_converter
#(
parameter IADDR = 32,
parameter OADDR = 32
)
(
input wire clk_sys,
input wire rst,
input wire [IADDR-1:0] addr_in,
input wire write_in,
input wire [31:0] writedata_in,
input wire read_in,
output reg [31:0] readdata_out,
output reg readdatavalid_out,
input wire [3:0] byteenable_in,
output wire waitrequest_out,
output wire [OADDR-1:0] addr_out,
output wire write_out,
output wire [7:0] writedata_out,
output wire read_out,
input wire [7:0] readdata_in,
input wire readdatavalid_in,
input wire waitrequest_in
);
function [2:0] cnt_bit;
input [3:0] data;
integer index;
begin
cnt_bit = 0;
for(index = 0; index < 4; index = index + 1)
if(data[index])
cnt_bit = cnt_bit + 1;
end
endfunction
// data
// data[8] = valid bit
reg [IADDR-1:0] addr0;
reg [8:0] data0; // not used
reg [8:0] data1; // data1
reg [8:0] data2; // data2
reg [8:0] data3; // data3
reg write_mode, read_mode;
assign addr_out = (data1[8]) ? addr0 | 1 :
(data2[8]) ? addr0 | 2 :
(data3[8]) ? addr0 | 3 :
(byteenable_in[0]) ? addr_in :
(byteenable_in[1]) ? addr_in | 1 :
(byteenable_in[2]) ? addr_in | 2 :
(byteenable_in[3]) ? addr_in | 3 : 0;
assign writedata_out = (data1[8] && write_mode) ? data1[7:0] :
(data2[8] && write_mode) ? data2[7:0] :
(data3[8] && write_mode) ? data3[7:0] :
(byteenable_in[0]) ? writedata_in[7:0] :
(byteenable_in[1]) ? writedata_in[15:8] :
(byteenable_in[2]) ? writedata_in[23:16] :
(byteenable_in[3]) ? writedata_in[31:24] : 0;
assign write_out = (!read_mode) && ((write_in && byteenable_in != 0) || write_mode);
assign read_out = (!write_mode) && ((read_in && byteenable_in != 0) || read_mode);
assign waitrequest_out = waitrequest_in || read_mode || write_mode;
always @(posedge clk_sys) begin
if(rst) begin
{data1, data2, data3} <= 0;
{write_mode, read_mode} <= 0;
end else if(data1[8]) begin
data1 <= 0;
write_mode <= write_mode && (data2[8] || data3[8]);
read_mode <= read_mode && (data2[8] || data3[8]);
end else if(data2[8]) begin
data2 <= 0;
write_mode <= write_mode && (data3[8]);
read_mode <= read_mode && (data3[8]);
end else if(data3[8]) begin
data3 <= 0;
write_mode <= 0;
read_mode <= 0;
end else if(cnt_bit(byteenable_in) > 1 && (write_in || read_in)) begin
write_mode <= write_in;
read_mode <= read_in;
addr0 <= addr_in;
data1[8] <= (byteenable_in[0] && byteenable_in[1]) ? 1 : 0;
data2[8] <= (byteenable_in[1:0] && byteenable_in[2]) ? 1 : 0;
data3[8] <= (byteenable_in[2:0] && byteenable_in[3]) ? 1 : 0;
data1[7:0] <= (byteenable_in[0] && byteenable_in[1]) ? writedata_in[15: 8] : 0;
data2[7:0] <= (byteenable_in[1:0] && byteenable_in[2]) ? writedata_in[23:16] : 0;
data3[7:0] <= (byteenable_in[2:0] && byteenable_in[3]) ? writedata_in[31:24] : 0;
end
end
/////////////////////////////////////////////////////////////////////////
reg [3:0] rflag;
always @(posedge clk_sys) begin
if(rst) begin
rflag <= 0;
readdata_out <= 0;
readdatavalid_out <= 0;
end else begin
if(rflag[0] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3:1], 1'b0};
readdata_out <= {readdata_out[31:8], readdata_in};
readdatavalid_out <= !(rflag[3:1]);
end else if(rflag[1] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3:2], 2'b0};
readdata_out <= {readdata_out[31:16], readdata_in, readdata_out[7:0]};
readdatavalid_out <= !(rflag[3:2]);
end else if(rflag[2] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3], 3'b0};
readdata_out <= {readdata_out[31:24], readdata_in[7:0], readdata_out[15:0]};
readdatavalid_out <= !(rflag[3]);
end else if(rflag[3] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : 0;
readdata_out <= {readdata_in[7:0], readdata_out[23:0]};
readdatavalid_out <= 1;
end else if(read_in && !waitrequest_out) begin
rflag <= byteenable_in;
readdatavalid_out <= 0;
end else begin
readdatavalid_out <= 0;
end
end
end
endmodule
|
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