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#include <bits/stdc++.h> using namespace std; int x[102], pile[102]; int MN(int a, int b) { return (a < b) ? a : b; } int main() { int n, i, sz, j, flag; while (scanf( %d , &n) != EOF) { for (i = 1; i <= n; i++) { scanf( %d , &x[i]); } sort(x + 1, x + n + 1); sz = 1; pile[sz] = 1; for (i = 2; i <= n; i++) { flag = 0; for (j = 1; j <= sz; j++) { if (pile[j] <= x[i]) { flag = 1; pile[j]++; break; } } if (flag == 0) pile[++sz] = 1; } printf( %d n , sz); } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[500100]; int n; vector<int> g[200100]; int d[200100]; int cnt = 1; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { int ind = lower_bound(d + 1, d + n + 1, a[i]) - d; d[ind - 1] = a[i]; g[ind - 1].push_back(a[i]); } for (int i = n; i >= 1; i--) { for (int j = 0; j < g[i].size(); j++) cout << g[i][j] << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; char a[25][25]; int dp[40][1 << 20], n; bool vis[40][1 << 20]; int f(int xx, int st) { if (vis[xx][st]) return dp[xx][st]; int &res = dp[xx][st]; vis[xx][st] = true; if (xx == n * 2 - 2) { res = 0; } else { if (xx & 1) res = -0x3f3f3f3f; else res = 0x3f3f3f3f; int mask[30]; memset(mask, 0, sizeof(mask)); int cnt = 0; for (int j = 0; j <= xx + 1; ++j) { int x = xx + 1 - j; int y = j; if (x >= n || y >= n) continue; mask[a[x][y] - a ] |= (1 << cnt); cnt++; } for (int i = 0; i < 26; ++i) { if (mask[i]) { int xt; if (xx + 1 < n) xt = (st | (st << 1)) & mask[i]; else xt = (st | (st >> 1)) & mask[i]; if (xt == 0) continue; int tmp = 0; if (i == 0) tmp = 1; else if (i == 1) tmp = -1; if (xx & 1) res = max(res, tmp + f(xx + 1, xt)); else res = min(res, tmp + f(xx + 1, xt)); } } } if (xx == 0) { if (a[0][0] == a ) res += 1; else if (a[0][0] == b ) res -= 1; } return res; } int main() { while (~scanf( %d , &n)) { for (int i = 0; i < n; ++i) scanf( %s , a[i]); memset(vis, 0, sizeof(vis)); int res = f(0, 1); if (res == 0) printf( DRAW n ); else if (res > 0) printf( FIRST n ); else printf( SECOND n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int D, m, x, y; vector<vector<long double>> e; const long double oo = 1e13; vector<long double> mns(vector<long double> a, vector<long double> b) { vector<long double> ret; ret.resize(D); for (int i = 0; i < D; i++) ret[i] = a[i] - b[i]; return ret; } vector<long double> tms(vector<long double> a, long double c) { for (int i = 0; i < D; i++) a[i] *= c; return a; } vector<long double> perp(vector<long double> a, vector<long double> b) { long double norma = 0, normb = 0, dot = 0; for (int i = 0; i < D; i++) { norma += a[i] * a[i]; normb += b[i] * b[i]; dot += a[i] * b[i]; } if (normb < 1e-9) return a; long double tmp = dot / normb; vector<long double> bb = tms(b, tmp); return mns(a, bb); } struct subspace { vector<vector<long double>> vectors; vector<vector<long long>> canon; subspace(vector<vector<long double>> _vectors) { int d = _vectors.size(); vectors = _vectors; for (int i = 0; i < d; i++) for (int j = 0; j < i; j++) vectors[i] = perp(vectors[i], vectors[j]); for (int i = 0; i < D; i++) { vector<long double> x = e[i]; for (int j = 0; j < d; j++) x = perp(x, vectors[j]); vector<long long> y(D); for (int i = 0; i < D; i++) { y[i] = llround(x[i] * oo); } canon.push_back(y); } } }; map<vector<vector<long long>>, int> mp; int cnt = 1; int main() { std::ios::sync_with_stdio(false); cin >> m >> D; e.resize(D); for (int i = 0; i < D; i++) { e[i].resize(D); e[i][i] = 1; } for (int i = 1; i <= m; i++) { vector<vector<long double>> tmp; cin >> x; for (int j = 0; j < x; j++) { vector<long double> v; for (int k = 0; k < D; k++) { cin >> y; v.push_back(y); } tmp.push_back(v); } auto c = subspace(tmp).canon; if (mp.count(c)) cout << mp[c] << ; else cout << (mp[c] = cnt++) << ; } cout << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; inline int readint() { int a; cin >> a; return a; } int toInt(string &s) { const static int Mod = 998244353; const static long long bas = 29; int res = 0; for (int i = 0, n = s.length(); i < n; ++i) res = (res * bas + s[i] - a + 1) % Mod; return res; } const int MaxN = 100005; vector<int> v[MaxN]; map<int, int> *dp[MaxN]; int siz[MaxN], son[MaxN]; void build(int x) { siz[x] = 1, son[x] = x; for (auto y : v[x]) { dp[y] = dp[x] + 1, build(y); if (siz[y] >= siz[son[x]]) son[x] = y; siz[x] += siz[y]; } } int val[MaxN]; void calc(int x, bool f) { if (f) dp[x][0][val[x]]++; else { dp[x][0][val[x]]--; if (dp[x][0][val[x]] == 0) dp[x][0].erase(val[x]); } for (auto y : v[x]) calc(y, f); } vector<pair<int, int> > query[MaxN]; int ans[MaxN]; void dfs(int x, bool f) { for (auto y : v[x]) if (y != son[x]) dfs(y, false); if (son[x] != x) dfs(son[x], true); for (auto y : v[x]) if (y != son[x]) calc(y, true); dp[x][0][val[x]]++; for (auto t : query[x]) { int dep = t.first; int id = t.second; ans[id] = dp[x][dep].size(); } if (not f) calc(x, false); } map<int, int> cnt[MaxN]; bool root[MaxN]; int main() { int n = readint(); string s; int fa; for (int i = 1; i <= n; ++i) { cin >> s >> fa; if (!fa) root[i] = true; else v[fa].push_back(i); val[i] = toInt(s); } for (int i = 1; i <= n; ++i) if (root[i]) dp[i] = cnt, build(i); int T = readint(); pair<int, int> p; for (int i = 1, a, b; i <= T; ++i) { a = readint(); b = readint(); if (dp[a] + b >= cnt + MaxN) continue; p.first = b; p.second = i; query[a].push_back(p); } for (int i = 1; i <= n; ++i) if (root[i]) dfs(i, false); for (int i = 1; i <= T; ++i) printf( %d n , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_SYMBOL_V
`define SKY130_FD_SC_LS__O31A_SYMBOL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long counter; long long n, r, l, x; vector<long long> a; long long sum, rr; bool cheake(long long mask) { long long nmax = -1; long long nmin = 10000000000; long long i = 0; rr = 0; sum = 0; while ((mask >> i) != 0) { if ((mask >> i) % 2 == 1) { rr++; sum = sum + a[i]; nmax = max(a[i], nmax); nmin = min(a[i], nmin); } i++; } if ((rr >= 2) && (sum >= l) && (sum <= r) && (nmax - nmin) >= x) return true; else return false; } void solv(long long i, long long mask) { if (i == n) return; solv(i + 1, mask); long long nmask = mask | (1 << i); solv(i + 1, nmask); if (cheake(nmask)) counter++; } int main() { long long k; cin >> n >> l >> r >> x; for (long long i = 0; i < n; i++) { cin >> k; a.push_back(k); } solv(0, 0); cout << counter; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 1e-11; int countbit(int n) { return (n == 0) ? 0 : 1 + countbit(n & (n - 1)); } int lowbit(int n) { return n & (n ^ (n - 1)); } string toString(long long v) { ostringstream sout; sout << v; return sout.str(); } string toString(int v) { ostringstream sout; sout << v; return sout.str(); } int Rand16() { return rand(); } int Rand32() { return rand() * rand(); } double DRand() { return (double)rand() / RAND_MAX; } int RandRange(int f, int r) { return f + (int)(DRand() * (r - f) + 0.5); } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int n; cin >> n; int i, j; int ans = 0; for (i = 2; i < n; i++) { int tmp = n; while (tmp) ans += tmp % i, tmp /= i; } int d = gcd(ans, n - 2); int A = ans / d; int B = (n - 2) / d; cout << A << / << B << endl; return 0; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Conversion_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module Conversion_ROM (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../ADC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../ADC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Conversion_ROM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e8; const int MX = 2e5 + 5; vector<int> vorder; int dup[MX], lc[MX], rc[MX], good[MX], seek[MX]; string labels, corder; void ino(int curr) { if (curr == -1) return; ino(lc[curr]); vorder.push_back(curr); corder += labels[curr]; ino(rc[curr]); } void dfs1(int curr) { if (curr == -1) return; seek[curr] = INF; dfs1(lc[curr]); dfs1(rc[curr]); if (lc[curr] != -1) seek[curr] = 1 + seek[lc[curr]]; if (good[curr]) seek[curr] = 1; } int dfs2(int curr, int k) { if (curr == -1) return k; if (seek[curr] <= k) { k--; dup[curr] = 1; k = dfs2(lc[curr], k); return dfs2(rc[curr], k); } return k; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; cin >> labels; for (int i = 0; i < n; i++) { cin >> lc[i] >> rc[i]; lc[i]--; rc[i]--; } ino(0); corder += @ ; char last; for (int i = n - 1; i >= 0; i--) { if (corder[i] != corder[i + 1]) last = corder[i + 1]; good[vorder[i]] = corder[i] < last; } memset(dup, 0, sizeof dup); dfs1(0); dfs2(0, k); for (int v : vorder) { if (dup[v]) cout << labels[v] << labels[v]; else cout << labels[v]; } cout << n ; } |
#include <bits/stdc++.h> using namespace std; stack<char> s; char c; int now = 1; int main() { while (cin >> c) { if (s.empty()) { s.push(c); } else { if (s.top() == c) { s.pop(); now = 3 - now; } else { s.push(c); } } } if (now == 2) { cout << Yes n ; } else { cout << No n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int n, a[200001], mp[200001], x, y; vector<int> to[200001], t2[200001]; int fa[200001], d[200001], sz[200001], son[200001]; int top[200001], dfn[200001], cnt; int f[200001], v[200001], p[200001], g[200001]; int st[200001], tp, s, sum, ans; bool in[200001]; inline int add(int x, int y) { return x + y < mod ? x + y : x + y - mod; } inline int sub(int x, int y) { return x < y ? x + mod - y : x - y; } inline int power(int a, int n) { int tp = 1; while (n) { if (n & 1) tp = 1ll * tp * a % mod; a = 1ll * a * a % mod, n >>= 1; } return tp; } inline bool cmp(int i, int j) { return dfn[i] < dfn[j]; } inline void dfs1(int i) { sz[i] = 1; dfn[i] = ++cnt; for (int j : to[i]) { if (j == fa[i]) continue; fa[j] = i, d[j] = d[i] + 1; dfs1(j); sz[i] += sz[j]; if (sz[son[i]] < sz[j]) son[i] = j; } } inline void dfs2(int i) { if (son[i]) top[son[i]] = top[i], dfs2(son[i]); for (int j : to[i]) if (j != fa[i] && j != son[i]) top[j] = j, dfs2(j); } inline int lca(int x, int y) { while (top[x] != top[y]) { if (d[top[x]] < d[top[y]]) swap(x, y); x = fa[top[x]]; } return d[x] < d[y] ? x : y; } inline int dfs(int i) { g[i] = 0; if (in[i]) g[i] = v[i]; int ans = 0; for (int j : t2[i]) { ans = add(ans, dfs(j)), g[i] = add(g[i], g[j]); ans = (ans + 1ll * (d[j] - d[i]) * g[j] % mod * sub(sum, g[j])) % mod; } return ans; } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d , a + i), mp[a[i]] = i; for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); to[x].push_back(y), to[y].push_back(x); } dfs1(1), top[1] = 1, dfs2(1); f[1] = 1; for (int i = 2; i <= n; i++) { if (f[i]) continue; f[i] = i - 1; for (int j = 2 * i; j <= n; j += i) { if ((j / i) % i) f[j] = f[i] * f[j / i]; else f[j] = i * f[j / i]; } } for (int i = 1; i <= n; i++) v[i] = f[a[i]]; for (int i = 1; i <= n; i++) f[i] = 1ll * i * power(f[i], mod - 2) % mod; for (int i = 1; i <= n; i++) for (int j = 2 * i; j <= n; j += i) f[j] = sub(f[j], f[i]); for (int t = 1; t <= n; t++) { sum = s = 0; for (int i = t; i <= n; i += t) p[++s] = mp[i], sum = add(sum, v[mp[i]]), in[mp[i]] = 1; sort(p + 1, p + s + 1, cmp); st[tp = 1] = p[1], t2[p[1]].clear(); for (int i = 2; i <= s; i++) { int x = lca(p[i], st[tp]), lt = 0; while (d[st[tp]] > d[x]) { if (lt) t2[st[tp]].push_back(lt); lt = st[tp--]; } if (st[tp] != x) st[++tp] = x, t2[x].clear(); if (lt) t2[x].push_back(lt); st[++tp] = p[i], t2[p[i]].clear(); } while (tp > 1) t2[st[tp - 1]].push_back(st[tp]), tp--; ans = (ans + 1ll * dfs(st[1]) * f[t]) % mod; for (int i = 1; i <= s; i++) in[p[i]] = 0; } cout << 2ll * ans * power(1ll * n * (n - 1) % mod, mod - 2) % mod; } |
/***************************************************************************************************
** fpga_nes/hw/src/vram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Video RAM module; implements 2KB of on-board VRAM as fpga block RAM.
***************************************************************************************************/
module vram
(
input wire clk_in, // system clock
input wire en_in, // chip enable
input wire r_nw_in, // read/write select (read: 0, write: 1)
input wire [10:0] a_in, // memory address
input wire [ 7:0] d_in, // data input
output wire [ 7:0] d_out // data output
);
wire vram_bram_we;
wire [7:0] vram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) vram_bram(
.clk(clk_in),
.we(vram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(vram_bram_dout)
);
assign vram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? vram_bram_dout : 8'h00;
endmodule
|
`timescale 1ns/1ps
module memcpy_engine #(
parameter ADDR_WIDTH = 64,
parameter DATA_WIDTH = 512
)
(
input clk ,
input rst_n ,
//---- memory copy parameters----
input [ADDR_WIDTH - 1:0] memcpy_src_addr,
input [ADDR_WIDTH - 1:0] memcpy_tgt_addr,
input [063:0] memcpy_len , // in terms of bytes
input memcpy_start ,
output memcpy_done ,
//---- write channel ----
input lcl_ibusy ,
output lcl_istart ,
output [ADDR_WIDTH - 1:0] lcl_iaddr ,
output [007:0] lcl_inum ,
input lcl_irdy ,
output reg lcl_den ,
output reg [DATA_WIDTH - 1:0] lcl_din ,
output reg lcl_idone ,
//---- read channel ----
input lcl_obusy ,
output lcl_ostart ,
output [ADDR_WIDTH - 1:0] lcl_oaddr ,
output [007:0] lcl_onum ,
input lcl_ordy ,
output reg lcl_rden ,
input lcl_dv ,
input [DATA_WIDTH - 1:0] lcl_dout ,
input lcl_odone
);
//--------------------------------------------
wire wr_on, rd_on;
reg [7:0] wr_cnt;
reg wr_end;
//--------------------------------------------
//---- data loopback ----
// read data request when
// 1) write & read burst in progress
// 2) read interface ready
// 3) write interface ready
always@(posedge clk or negedge rst_n)
if (~rst_n)
lcl_rden <= 1'b0;
else if (wr_on | rd_on)
begin
if ((lcl_odone) | // condition 1: current read burst done
((wr_cnt == lcl_inum - 8'd1) & lcl_rden)) // condition 2: current write burst done
lcl_rden <= 1'b0;
else
lcl_rden <= lcl_ordy & lcl_irdy;
end
else
lcl_rden <= 1'b0;
always@(posedge clk or negedge rst_n)
if (~rst_n)
begin
lcl_den <= 1'b0;
lcl_din <= 'd0;
end
else
begin
lcl_den <= lcl_dv;
lcl_din <= lcl_dout;
end
//---- control the read data number during write state ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
wr_cnt <= 8'd0;
else if (wr_on)
begin
if (lcl_rden)
wr_cnt <= wr_cnt + 8'd1;
end
else
wr_cnt <= 8'd0;
//---- current burst write done signal ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
begin
wr_end <= 1'b0;
lcl_idone <= 1'b0;
end
else
begin
wr_end <= ((wr_cnt == lcl_inum - 8'd1) & lcl_rden);
lcl_idone <= wr_end;
end
//---- memory read burst control ----
memcpy_statemachine mrd_st(
.clk (clk ),
.rst_n (rst_n ),
.memcpy_start (memcpy_start ),
.memcpy_len (memcpy_len ),
.memcpy_addr (memcpy_src_addr),
.burst_busy (lcl_obusy ),
.burst_start (lcl_ostart ),
.burst_len (lcl_onum ),
.burst_addr (lcl_oaddr ),
.burst_on (rd_on ),
.burst_done (lcl_odone ),
.memcpy_done (memcpy_rd_done )
);
//---- memory writing burst control ----
memcpy_statemachine mwr_st(
.clk (clk ),
.rst_n (rst_n ),
.memcpy_start (memcpy_start ),
.memcpy_len (memcpy_len ),
.memcpy_addr (memcpy_tgt_addr),
.burst_busy (lcl_ibusy ),
.burst_start (lcl_istart ),
.burst_len (lcl_inum ),
.burst_addr (lcl_iaddr ),
.burst_on (wr_on ),
.burst_done (lcl_idone ),
.memcpy_done (memcpy_wr_done )
);
//---- entire memory copy is done ----
assign memcpy_done = memcpy_wr_done && memcpy_rd_done;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; const long long M = 1e9 + 9; int n, x, y; pair<int, int> pos[N]; map<pair<int, int>, int> mp; set<int> q; long long ans; int children(int x, int y) { int ret = 0; for (int dx = -1; dx <= 1; dx++) { map<pair<int, int>, int>::iterator c = mp.find(make_pair(x + dx, y - 1)); if (c != mp.end()) ret++; } return ret; } void update(int x, int y) { map<pair<int, int>, int>::iterator p = mp.find(make_pair(x, y)); if (p == mp.end()) return; for (int dx = -1; dx <= 1; dx++) { map<pair<int, int>, int>::iterator c = mp.find(make_pair(x + dx, y + 1)); if (c != mp.end() && children(x + dx, y + 1) == 1) { q.erase(p->second); return; } } q.insert(p->second); } void insert(int x, int y, int z) { pos[z].first = x; pos[z].second = y; mp[make_pair(x, y)] = z; } void remove(int x, int y) { mp.erase(make_pair(x, y)); for (int dx = -1; dx <= 1; dx++) { update(x + dx, y + 1); update(x + dx, y - 1); } for (int dx = -2; dx <= 2; dx++) { update(x + dx, y); } } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; insert(x, y, i); } for (int i = 0; i < n; i++) { update(pos[i].first, pos[i].second); } for (int act = 0; !q.empty(); act++) { set<int>::iterator it; if ((act & 1) == 0) { it = --q.end(); } else { it = q.begin(); } ans = ans * n + (*it); ans %= M; remove(pos[*it].first, pos[*it].second); q.erase(it); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long n; cin >> n; long long int ans = 0, ans1, k, a1, a2, x, y, m, s = 0; vector<pair<long, pair<long, long>>> r; for (int i = 0; i < n; ++i) { cin >> k; s += k; cin >> a1 >> x >> y >> m; ans1 = 0; r.push_back(make_pair(0, make_pair(a1, i + 1))); for (int j = 1; j < k; ++j) { a2 = ((a1 * x) % m + y % m) % m; if (a2 < a1) ans1++; a1 = a2; if (r.size() <= 200000) r.push_back(make_pair(ans1, (make_pair(a2, i + 1)))); } ans = max(ans, ans1); } cout << ans << n ; sort(r.begin(), r.end()); if (s <= 200000) for (int i = 0; i < s; ++i) cout << r[i].second.first << << r[i].second.second << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O21BAI_BEHAVIORAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long long N = 2e5 + 10, alp = 26; const long double pi = 3.14159265358979; void solve() { long long n, m; cin >> n >> m; vector<vector<long long> > g1(n), rg1(n), g2(n), rg2(n); for (long long i = 0; i < m; ++i) { long long u, v, t; cin >> u >> v >> t; --u; --v; if (t) g1[u].push_back(v), rg1[v].push_back(u); else g2[u].push_back(v), rg2[v].push_back(u); } vector<long long> ans(n, -1), len(n, -1); ans[n - 1] = 0; len[n - 1] = 0; queue<long long> q; q.push(n - 1); while (q.size()) { long long u = q.front(); q.pop(); set<long long> s1, s2; for (long long to : rg1[u]) if (ans[to] == 1 && len[to] == -1) len[to] = len[u] + 1, q.push(to); for (long long to : rg2[u]) if (ans[to] == 2 && len[to] == -1) len[to] = len[u] + 1, q.push(to); for (long long to : rg1[u]) if (ans[to] == -1) s1.insert(to); for (long long to : rg2[u]) if (ans[to] == -1) s2.insert(to); for (long long x : s1) if (!s2.count(x)) ans[x] = 2; for (long long x : s2) if (!s1.count(x)) ans[x] = 1; for (long long x : s1) if (s2.count(x) && len[x] == -1) ans[x] = 1, len[x] = len[u] + 1, q.push(x); } cout << len[0] << n ; for (long long i = 0; i < n; ++i) cout << (ans[i] == 1 ? 1 : 0); } int32_t main() { ios_base::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); } |
module t_lint_pragma_protected_err;
// This part should see some failures
`pragma protect begin_protected
`pragma protect version="xx"
// should fail because value should be quoted
`pragma protect encrypt_agent=123
// should fail because no value given at all
`pragma protect encrypt_agent_info
`pragma protect data_method="AES128-CBC"
`pragma protect key_keyowner="BIG3#1"
`pragma protect key_keyname="AAAAAA"
`pragma protect key_method="RSA"
// expect error in key_block below, 64 bytes but expecting 65
// also expect "multiple `pragma encoding sections` error because number of
// bytes does not go down to 0 in the end of the section below due to the 64->65 change
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65)
`pragma protect key_block
ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg
KSAyMDA3IE==
`pragma protect key_keyowner="BIG3#2"
`pragma protect key_keyname="BBBBBB"
`pragma protect key_method="RSA"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv
cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs
bG93ZWQuCgoKICBUaGl=
`pragma protect key_keyowner="BIG3#3"
`pragma protect key_keyname="CCCCCCCC"
`pragma protect key_method="RSA"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g
MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg
YWRkaXRpb25hbCBwZXJ=
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295)
`pragma protect data_block
aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy
c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
ZCBXb3JrIGFzIG==
`pragma protect end_protected
// Should trigger unknown pragma warning, although in principle unknown pragmas should be safely ignored.
`pragma XXXXX
// Should trigger missing pragma warning
`pragma
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500005; const int mod = 998244353; const long long int inf = 10e17; const long double pi = 3.14159265359; mt19937_64 rang( chrono::high_resolution_clock::now().time_since_epoch().count()); int rng(int lim) { uniform_int_distribution<int> uid(0, lim - 1); return uid(rang); } void fastIO(void); void decimal(int); int modmulti(int, int); int modadd(int, int); int modpower(int, int); int gcd(int, int); int modinv(int); vector<int> parent, depth, heavy, head, pos, tin, tout; int cur_pos; int lazy1[4 * N], lazy2[8 * N]; int timer, l; vector<vector<int>> up; int dfs(int v, vector<vector<int>> const& g) { int size = 1; tin[v] = ++timer; up[v][0] = parent[v]; for (int i = 1; i < l + 1; i++) { up[v][i] = up[up[v][i - 1]][i - 1]; } int max_c_size = 0; for (int c : g[v]) { if (c != parent[v]) { parent[c] = v; depth[c] = depth[v] + 1; int c_size = dfs(c, g); if (c_size > max_c_size) { max_c_size = c_size; heavy[v] = c; } size += c_size; } } tout[v] = ++timer; return size; } bool is_ancestor(int u, int v) { return tin[u] <= tin[v] && tout[u] >= tout[v]; } int lca(int u, int v) { if (is_ancestor(u, v)) return u; if (is_ancestor(v, u)) return v; for (int i = l; i >= 0; --i) { if (!is_ancestor(up[u][i], v)) u = up[u][i]; } return up[u][0]; } void decompose(int v, int h, vector<vector<int>> const& g) { head[v] = h; pos[v] = cur_pos++; if (heavy[v] != -1) { decompose(heavy[v], h, g); } for (int c : g[v]) { if (c != parent[v] && c != heavy[v]) decompose(c, c, g); } } void init(vector<vector<int>> const& g) { int n = g.size(); parent = vector<int>(n); depth = vector<int>(n); heavy = vector<int>(n, -1); head = vector<int>(n); pos = vector<int>(n); tin = vector<int>(n); tout = vector<int>(n); timer = 0; l = ceil(log2(n)); up.assign(n, vector<int>(l + 1)); cur_pos = 0; dfs(0, g); decompose(0, 0, g); } void update1(int node, int l, int r, int st, int ed, int val) { if (l == st && r == ed) { lazy1[node] = val; return; } int m = (l + r) / 2; if (ed <= m) { update1(2 * node + 1, l, m, st, ed, val); return; } if (st > m) { update1(2 * node + 2, m + 1, r, st, ed, val); return; } update1(2 * node + 1, l, m, st, m, val); update1(2 * node + 2, m + 1, r, m + 1, ed, val); return; } void update2(int node, int l, int r, int st, int ed, int val) { if (l == st && r == ed) { lazy2[node] = val; return; } int m = (l + r) / 2; if (ed <= m) { update2(2 * node + 1, l, m, st, ed, val); return; } if (st > m) { update2(2 * node + 2, m + 1, r, st, ed, val); return; } update2(2 * node + 1, l, m, st, m, val); update2(2 * node + 2, m + 1, r, m + 1, ed, val); return; } void update(int b, int val, int n) { int a = 0; for (; head[a] != head[b]; b = parent[head[b]]) { if (depth[head[a]] > depth[head[b]]) swap(a, b); update1(0, 0, n - 1, pos[head[b]], pos[b], val); } update1(0, 0, n - 1, pos[a], pos[b], val); return; } int query1(int node, int l, int r, int pos) { if (l == r) { return lazy1[node]; } lazy1[2 * node + 1] = max(lazy1[node], lazy1[2 * node + 1]); lazy1[2 * node + 2] = max(lazy1[node], lazy1[2 * node + 2]); int m = (l + r) / 2; if (pos <= m) return query1(2 * node + 1, l, m, pos); return query1(2 * node + 2, m + 1, r, pos); } int query2(int node, int l, int r, int pos) { if (l == r) { return lazy2[node]; } lazy2[2 * node + 1] = max(lazy2[node], lazy2[2 * node + 1]); lazy2[2 * node + 2] = max(lazy2[node], lazy2[2 * node + 2]); int m = (l + r) / 2; if (pos <= m) return query2(2 * node + 1, l, m, pos); return query2(2 * node + 2, m + 1, r, pos); } int main() { fastIO(); int n; cin >> n; vector<vector<int>> g(n); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; u--; v--; g[u].push_back(v); g[v].push_back(u); } init(g); int m; cin >> m; int cnt = 0; for (int m1 = 1; m1 < m + 1; m1++) { int a, b; cin >> a >> b; b--; if (a == 1) { update2(0, 1, 2 * n, tin[b], tout[b], m1); } else if (a == 2) { update(b, m1, n); } else { cnt++; int q1, q2; q1 = query1(0, 0, n - 1, pos[b]); q2 = query2(0, 1, 2 * n, tin[b]); if (q1 >= q2) cout << 0 << n ; else cout << 1 << n ; } } } void fastIO(void) { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } void decimal(int n) { cout << fixed; cout << setprecision(n); } int modmulti(int a, int b) { return ((a % mod) * 1ll * (b % mod)) % mod; } int modadd(int a, int b) { a = a % mod; a = (a + mod) % mod; b = b % mod; b = (b + mod) % mod; return (a + b) % mod; } int modpower(int a, int n) { if (n == 0) return 1; if (n == 1) return a % mod; int b = modpower(a, n / 2); b = modmulti(b, b); if (n % 2 == 0) return b; return modmulti(a, b); } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int modinv(int a) { return modpower(a, mod - 2); } |
// Synchronous FIFO. 1024 x 32 bit words.
//
module fifo (
clk,
rstp,
din,
writep,
readp,
dout,
emptyp,
fullp);
input clk;
input rstp;
input [31:0] din;
input readp;
input writep;
output [31:0] dout;
output emptyp;
output fullp;
// Defines sizes in terms of bits.
//
parameter DEPTH = 1024; // 2 bits, e.g. 4 words in the FIFO.
parameter MAX_COUNT = 10'b1111111111; // topmost address in FIFO.
reg emptyp;
reg fullp;
// Registered output.
reg [31:0] dout;
// Define the FIFO pointers. A FIFO is essentially a circular queue.
//
reg [(DEPTH-1):0] tail;
reg [(DEPTH-1):0] head;
// Define the FIFO counter. Counts the number of entries in the FIFO which
// is how we figure out things like Empty and Full.
//
reg [(DEPTH-1):0] count;
// Define our regsiter bank. This is actually synthesizable!
//
reg [31:0] fifomem[0:MAX_COUNT];
// Dout is registered and gets the value that tail points to RIGHT NOW.
//
always @(posedge clk) begin
if (rstp == 1) begin
dout <= 16'h0000;
end
else begin
dout <= fifomem[tail];
end
end
// Update FIFO memory.
always @(posedge clk) begin
if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin
fifomem[head] <= din;
end
end
// Update the head register.
//
always @(posedge clk) begin
if (rstp == 1'b1) begin
head <= 2'b00;
end
else begin
if (writep == 1'b1 && fullp == 1'b0) begin
// WRITE
head <= head + 1;
end
end
end
// Update the tail register.
//
always @(posedge clk) begin
if (rstp == 1'b1) begin
tail <= 2'b00;
end
else begin
if (readp == 1'b1 && emptyp == 1'b0) begin
// READ
tail <= tail + 1;
end
end
end
// Update the count regsiter.
//
always @(posedge clk) begin
if (rstp == 1'b1) begin
count <= 2'b00;
end
else begin
case ({readp, writep})
2'b00: count <= count;
2'b01:
// WRITE
if (count != MAX_COUNT)
count <= count + 1;
2'b10:
// READ
if (count != 2'b00)
count <= count - 1;
2'b11:
// Concurrent read and write.. no change in count
count <= count;
endcase
end
end
// *** Update the flags
//
// First, update the empty flag.
//
always @(count) begin
if (count == 2'b00)
emptyp <= 1'b1;
else
emptyp <= 1'b0;
end
// Update the full flag
//
always @(count) begin
if (count == MAX_COUNT)
fullp <= 1'b1;
else
fullp <= 1'b0;
end
endmodule |
//-------------------------------------------------------------------------------------------------
// ng_MON.v - Monitor module
//
// In the original Pultorak desing, this Module was used to contain all the front panel switches
// and Display indicator LED's. In this FPGA experiment, most of that is not needed since the FPGA
// has adequate current drive capability to directly drive standard LED's (about 8ma) so this module
// Now basically is just providing switch debouncing and logic.
//-------------------------------------------------------------------------------------------------
module ng_MON(
input m_reset, // Master reset button input
input clk_mode, // Clock Mode selection
input step_mode, // Step Mode
input run_step, // Run Step selection
input standby, // Standby mode selector
input inst_step, // Instruction step button
input clock_step, // Clock Step button
input DBNCLK, // Debouncer Clock (200Hz) input
output NPURST, // Master reset, negative logic
output MCLK, // Manual Clock
output FCLK, // Fast Clock
output INST, // Instruction increment
output NRUN, // Run mode, negative logic
output NSA, // Standby allowed, negative logic
output NSTEP // Next Step, negative logic
);
// --------------------------------------------------------------------
// Reset Button Debouncer
// --------------------------------------------------------------------
Button_Debouncer u1(.clk(DBNCLK), .PB(!m_reset), .PB_state(NPURST));
// --------------------------------------------------------------------
// Direct Output assignments:
// Here all switches and buttons are SPST and have a weak pull up
// resistor tied to Vcc so the default state is high.
// --------------------------------------------------------------------
assign FCLK = !clk_mode; // Invert switch state
assign INST = !step_mode; // Instruction step mode
assign NRUN = !run_step; // Run or step mode
assign NSA = standby; // Standby mode selector switch
assign NSTEP = !Q1; // Step mode
assign MCLK = Q2; // Manual Clock output
//-------------------------------------------------------------------------------------------------
// NOTE: A D Flip Flop can be instantiated using the following code:
// always@(negedge CLK or negedge CLN or negedge PRN)
// if (!CLN) Q <= 0;
// else if(!PRN) Q <= 1;
// else Q <= D;
//-------------------------------------------------------------------------------------------------
reg Q1, Q2; // Clock Registers
always@(negedge DBNCLK or negedge NPURST) // Flip Flop 1
if(!NPURST) Q1 <= 1'b1; // Set to high
else Q1 <= !inst_step; // Load the switch state
always@(negedge DBNCLK or negedge NPURST) // Flip Flop 2
if(!NPURST) Q2 <= 1'b1; // Set to high
else Q2 <= !clock_step; // Load the switch state
//-------------------------------------------------------------------------------------------------
endmodule
//-------------------------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { string s[10] = { O-|-OOOO , O-|O-OOO , O-|OO-OO , O-|OOO-O , O-|OOOO- , -O|-OOOO , -O|O-OOO , -O|OO-OO , -O|OOO-O , -O|OOOO- }; string num; while (cin >> num) { int i = num.size(); while (i--) cout << s[num[i] - 0 ] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; string str; int main() { long long int i, j, t, n; cin >> t; while (t--) { cin >> str; int ar[4]; for (i = 0; i < 4; i++) { ar[i] = 0; } int l = str.length(); int count = 0; int mn = l + 1; for (i = 0, j = 0; i <= j && j < l; j++) { ar[str[j] - 1 ]++; if (ar[str[j] - 1 ] == 1) { count++; } if (count == 3) { if (j - i + 1 < mn) { mn = j - i + 1; } while (i <= j && count == 3) { ar[str[i] - 1 ]--; if (ar[str[i] - 1 ] == 0) { count--; } i++; if (count == 3 && j - i + 1 < mn) { mn = j - i + 1; } } } } if (mn > l) { cout << 0 << n ; } else { cout << mn << n ; } } return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Generates global and local ids for given set of group ids.
// Need one of these for each kernel instance.
module acl_id_iterator
#(
parameter WIDTH = 32 // width of all the counters
)
(
input clock,
input resetn,
input start,
// handshaking with work group dispatcher
input valid_in,
output stall_out,
// handshaking with kernel instance
input stall_in,
output valid_out,
// comes from group dispatcher
input [WIDTH-1:0] group_id_in[2:0],
input [WIDTH-1:0] global_id_base_in[2:0],
// kernel parameters from the higher level
input [WIDTH-1:0] local_size[2:0],
input [WIDTH-1:0] global_size[2:0],
// actual outputs
output [WIDTH-1:0] local_id[2:0],
output [WIDTH-1:0] global_id[2:0],
output [WIDTH-1:0] group_id[2:0]
);
// Storing group id vector and global id offsets vector.
// Global id offsets help work item iterators calculate global
// ids without using multipliers.
localparam FIFO_WIDTH = 2 * 3 * WIDTH;
localparam FIFO_DEPTH = 4;
wire last_in_group;
wire issue = valid_out & !stall_in;
reg just_seen_last_in_group;
wire [WIDTH-1:0] global_id_from_iter[2:0];
reg [WIDTH-1:0] global_id_base[2:0];
// takes one cycle for the work iterm iterator to register
// global_id_base. During that cycle, just use global_id_base
// directly.
wire use_base = just_seen_last_in_group;
assign global_id[0] = use_base ? global_id_base[0] : global_id_from_iter[0];
assign global_id[1] = use_base ? global_id_base[1] : global_id_from_iter[1];
assign global_id[2] = use_base ? global_id_base[2] : global_id_from_iter[2];
// Group ids (and global id offsets) are stored in a fifo.
acl_fifo #(
.DATA_WIDTH(FIFO_WIDTH),
.DEPTH(FIFO_DEPTH)
) group_id_fifo (
.clock(clock),
.resetn(resetn),
.data_in ( {group_id_in[2], group_id_in[1], group_id_in[0],
global_id_base_in[2], global_id_base_in[1], global_id_base_in[0]} ),
.data_out( {group_id[2], group_id[1], group_id[0],
global_id_base[2], global_id_base[1], global_id_base[0]} ),
.valid_in(valid_in),
.stall_out(stall_out),
.valid_out(valid_out),
.stall_in(!last_in_group | !issue)
);
acl_work_item_iterator #(
.WIDTH(WIDTH)
) work_item_iterator (
.clock(clock),
.resetn(resetn),
.start(start),
.issue(issue),
.local_size(local_size),
.global_size(global_size),
.global_id_base(global_id_base),
.local_id(local_id),
.global_id(global_id_from_iter),
.last_in_group(last_in_group)
);
// goes high one cycle after last_in_group. stays high until
// next cycle where 'issue' is high.
always @(posedge clock or negedge resetn) begin
if ( ~resetn )
just_seen_last_in_group <= 1'b1;
else if ( start )
just_seen_last_in_group <= 1'b1;
else if (last_in_group & issue)
just_seen_last_in_group <= 1'b1;
else if (issue)
just_seen_last_in_group <= 1'b0;
else
just_seen_last_in_group <= just_seen_last_in_group;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 18:38:26 09/18/2015
// Design Name: KeyEncoderAJM
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/Lab2-ManualKeypadScannerAndEncoder/KeyEncoderAJMTest.v
// Project Name: Lab2-ManualKeypadScannerAndEncoder
////////////////////////////////////////////////////////////////////////////////
module KeyEncoderAJMTest;
reg [3:0] Columns, Rows;
wire [4:0] KeyNumber;
KeyEncoderAJM uut(Columns, Rows, KeyNumber);
initial begin
Columns = 4'b0111; Rows = 4'b0111; #1;
Columns = 4'b1011; Rows = 4'b0111; #1;
Columns = 4'b1101; Rows = 4'b0111; #1;
Columns = 4'b0111; Rows = 4'b1011; #1;
Columns = 4'b1011; Rows = 4'b1011; #1;
Columns = 4'b1101; Rows = 4'b1011; #1;
Columns = 4'b0111; Rows = 4'b1101; #1;
Columns = 4'b1011; Rows = 4'b1101; #1;
Columns = 4'b1101; Rows = 4'b1101; #1;
Columns = 4'b1110; Rows = 4'b0111; #1;
Columns = 4'b1110; Rows = 4'b1011; #1;
Columns = 4'b1110; Rows = 4'b1101; #1;
Columns = 4'b1110; Rows = 4'b1110; #1;
Columns = 4'b0111; Rows = 4'b1110; #1;
Columns = 4'b1011; Rows = 4'b1110; #1;
Columns = 4'b1101; Rows = 4'b1110; #1;
Columns = 4'b1101; Rows = 4'b1010; #1;
$stop;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:11 11/29/2014
// Design Name:
// Module Name: FuncionActivacion
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FuncionActivacion #(parameter Width = 32, ConLimitador=0,Magnitud = 7, Precision = 24, Signo = 1, A00= 0,
A01= 1, A02 = 2, A03 = 3, A04 = 4, A05 = 5, A06 = 6, A07 = 7, A08 = 8, A09 = 9,
A10= 10, A11= 11, A12 = 12, A13 = 13, A14 = 14, A15 = 15, A16 = 16, A17 = 17, A18 = 18, A19 = 19,
A20= 20, A21= 21,A22 = 22, A23 = 23, A24 = 24, A25 = 25, A26 = 26, A27 = 27, A28 = 28, A29 = 29,
A30 = 30, M01= 1,
M02 = 2, M03 = 3, M04 = 4, M05 = 5, M06 = 6, M07 = 7, M08 = 8, M09 = 9,
M10= 10, M11= 11, M12 = 12, M13 = 13, M14 = 14, M15 = 15, M16 = 16, M17 = 17, M18 = 18, M19 = 19,
M20= 20, M21= 21,M22 = 22, M23 = 23, M24 = 24, M25 = 25, M26 = 26, M27 = 27, M28 = 28, M29 = 29,
M30 = 30,B01= 1,
B02 = 2, B03 = 3, B04 = 4, B05 = 5, B06 = 6, B07 = 7, B08 = 8, B09 = 9,
B10= 10, B11= 11, B12 = 12, B13 = 13, B14 = 14, B15 = 15, B16 = 16, B17 = 17, B18 = 18, B19 = 19,
B20= 20, B21= 21,B22 = 22, B23 = 23, B24 = 24, B25 = 25, B26 = 26, B27 = 27, B28 = 28, B29 = 29,
B30 = 30)
(Entrada,Enable,Error,Salida);
input signed [Width-1:0] Entrada;
input Enable;
output Error;
output signed [Width-1:0] Salida;
wire [4:0] SELMUX;
wire signed [Width-1:0] M,B,OutALU;
Comparador #( .Width(Width) , .A00(A00), .A01(A01),.A02(A02), .A03(A03), .A04(A04), .A05(A05),
.A06(A06), .A07(A07), .A08(A08), .A09(A09),.A10(A10), .A11(A11), .A12(A12), .A13(A13), .A14(A14),
.A15(A15), .A16(A16), .A17(A17), .A18(A18), .A19(A19),.A20(A20), .A21(A21),.A22(A22), .A23(A23),
.A24(A24), .A25(A25), .A26(A26), .A27(A27), .A28(A28), .A29(A29), .A30(A30))
COmparadorcopia (
.A(Entrada),
.OutComp(SELMUX)
);
multiplexor32a1 #(.Width(Width)) multiplexor32a1coeffPendientes (
.coeff00(32'sb00000000000000000000000000000000),
.coeff01(M01),
.coeff02(M02),
.coeff03(M03),
.coeff04(M04),
.coeff05(M05),
.coeff06(M06),
.coeff07(M07),
.coeff08(M08),
.coeff09(M09),
.coeff10(M10),
.coeff11(M11),
.coeff12(M12),
.coeff13(M13),
.coeff14(M14),
.coeff15(M15),
.coeff16(M16),
.coeff17(M17),
.coeff18(M18),
.coeff19(M19),
.coeff20(M20),
.coeff21(M21),
.coeff22(M22),
.coeff23(M23),
.coeff24(M24),
.coeff25(M25),
.coeff26(M26),
.coeff27(M27),
.coeff28(M28),
.coeff29(M29),
.coeff30(M30),
.coeff31(32'sb00000000000000000000000000000000),
.SEL(SELMUX),
.outMUX(M)
);
multiplexor32a1 #(.Width(Width)) multiplexor32a1coeffInterseccion (
.coeff00(32'sb00000000000000000000000000000000),
.coeff01(B01),
.coeff02(B02),
.coeff03(B03),
.coeff04(B04),
.coeff05(B05),
.coeff06(B06),
.coeff07(B07),
.coeff08(B08),
.coeff09(B09),
.coeff10(B10),
.coeff11(B11),
.coeff12(B12),
.coeff13(B13),
.coeff14(B14),
.coeff15(B15),
.coeff16(B16),
.coeff17(B17),
.coeff18(B18),
.coeff19(B19),
.coeff20(B20),
.coeff21(B21),
.coeff22(B22),
.coeff23(B23),
.coeff24(B24),
.coeff25(B25),
.coeff26(B26),
.coeff27(B27),
.coeff28(B28),
.coeff29(B29),
.coeff30(B30),
.coeff31(32'sb00000001000000000000000000000000),
.SEL(SELMUX),
.outMUX(B)
);
ALUfuncionActivacion #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
ALUfuncionActivacioncopia (
.SELMUX(SELMUX),
.Enable(Enable),
.M(M),
.B(B),
.In(Entrada),
.Out(OutALU),
.Error(Error)
);
generate
if (ConLimitador) begin: CodigoConLimitadoralaSalidaEntre0y1
LimitadorSalidaFuctActivacion #(.Width(Width)) LimitadorSalidaFuctActivacion1 (
.inData(OutALU),
.OutData(Salida)
);
end else begin: CodigoSinLimitadoralaSalidaEntre0y1
assign Salida = OutALU;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_SYMBOL_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputisolatch (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_TB_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_ps_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 SET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 SET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 SET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_TB_V
|
#include<bits/stdc++.h> #define inf 2000000000 #define eb emplace_back #define pb push_back #define fi first #define se second #define fastio ios::sync_with_stdio(false);cin.tie(NULL) #define rng_23 mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()) using namespace std; typedef long long ll; typedef pair<int,int> pii; typedef vector<int> vi; typedef vector<pair<int,int>> vii; typedef set<int> si; typedef multiset<int> msi; typedef map<int,int> mii; int ara[100][100],lcnt[100],wcnt[100]; int main() { int t; int i,j,k; int n,res; cin>>t; while(t--){ cin>>n; for(i=0;i<n;i++) for(j=0;j<n;j++) ara[i][j]=2; for(i=0;i<n;i++){ wcnt[i]=(n-1)/2; lcnt[i]=n-1-(n-1)/2; ara[i][i]=0; } if(n%2==0){ for(i=0;i<n;i++) lcnt[i]--; for(i=0;i<n;i+=2){ ara[i][i+1]=0; ara[i+1][i]=0; } } //for(i=0;i<n;i++){ // cout<<wcnt[i]<< <<lcnt[i]<<endl; //} for(i=0;i<n;i++){ //cout<<wcnt[i]<< <<lcnt[i]<<endl; for(j=0;j<n;j++){ if(ara[i][j]==2 && wcnt[i] && lcnt[j]){ wcnt[i]--; lcnt[j]--; ara[i][j]=1; ara[j][i]=-1; } } } for(i=0;i<n-1;i++){ for(j=i+1;j<n;j++){ cout<<ara[i][j]<< ; } } cout<< n ; } } |
#include <bits/stdc++.h> using namespace std; int n, bear, ans, a, aux, votes[128]; priority_queue<int> q; int Solution() { int ans = 0; while (bear <= q.top()) { aux = q.top(); if (bear <= aux) { bear++; aux--; q.pop(); q.push(aux); ans++; } } return ans; } int main() { scanf( %d , &n); scanf( %d , &bear); for (int i = 0; i < n - 1; ++i) { scanf( %d , &a); q.push(a); } ans = Solution(); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, x[101000], y[101000], fa[101000], sz[101000], tot[101000], u, v; map<int, vector<int> > xx, yy; map<int, vector<int> >::iterator it; long long ans = 1, er[202000]; int GF(int x) { return fa[x] == x ? x : fa[x] = GF(fa[x]); } void doit(vector<int> &the) { for (int i = 1; i < (int)the.size(); i++) if ((u = GF(the[i - 1])) != (v = GF(the[i]))) { sz[v] += sz[u]; tot[v] += tot[u]; fa[u] = v; } tot[GF(the[0])]++; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> x[i] >> y[i]; xx[x[i]].push_back(i); yy[y[i]].push_back(i); fa[i] = i; sz[i] = 1; } for (it = xx.begin(); it != xx.end(); it++) doit(it->second); for (it = yy.begin(); it != yy.end(); it++) doit(it->second); er[0] = 1; for (int i = 1; i < 202000; i++) er[i] = er[i - 1] * 2 % 1000000007; for (int i = 1; i <= n; i++) if (fa[i] == i) ans = ans * (er[tot[i]] - (tot[i] > sz[i])) % 1000000007; cout << (ans + 1000000007) % 1000000007; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 19:48:02 07/10/2010
// Design Name: Booth Multiplier
// Module Name: Booth_Multiplier.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// This module implements a parameterized multiplier which uses the Booth
// algorithm for its implementation. The implementation is based on the
// algorithm described in "Computer Organization", Hamacher et al, McGraw-
// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
//
// Dependencies:
//
// Revision:
//
// 0.01 10G10 MAM File Created
//
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
module Booth_Multiplier #(
parameter pN = 4 // Width = 2**pN: multiplicand & multiplier
)(
input Rst, // Reset
input Clk, // Clock
input Ld, // Load Registers and Start Multiplier
input [(2**pN - 1):0] M, // Multiplicand
input [(2**pN - 1):0] R, // Multiplier
output reg Valid, // Product Valid
output reg [(2**(pN+1) - 1):0] P // Product <= M * R
);
///////////////////////////////////////////////////////////////////////////////
//
// Local Parameters
//
///////////////////////////////////////////////////////////////////////////////
//
// Declarations
//
reg [2**pN:0] A; // Multiplicand w/ sign guard bit
reg [ pN:0] Cntr; // Operation Counter
reg [2**pN:0] S; // Adder w/ sign guard bit
reg [(2**(pN+1) + 1):0] Prod; // Double length product w/ guard bits
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
always @(posedge Clk)
begin
if(Rst)
Cntr <= #1 0;
else if(Ld)
Cntr <= #1 2**pN;
else if(|Cntr)
Cntr <= #1 (Cntr - 1);
end
// Multiplicand Register
// includes an additional bit to guard sign bit in the event the
// most negative value is provided as the multiplicand.
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Ld)
A <= #1 {M[2**pN - 1], M};
end
// Compute Upper Partial Product: (2**pN + 1) bits in width
always @(*)
begin
case(Prod[1:0])
2'b01 : S <= Prod[(2**(pN+1) + 1):(2**pN + 1)] + A;
2'b10 : S <= Prod[(2**(pN+1) + 1):(2**pN + 1)] - A;
default : S <= Prod[(2**(pN+1) + 1):(2**pN + 1)];
endcase
end
// Register Partial products and shift rigth arithmetically.
// Product register has guard bits on both ends.
always @(posedge Clk)
begin
if(Rst)
Prod <= #1 0;
else if(Ld)
Prod <= #1 {R, 1'b0};
else if(|Cntr)
Prod <= #1 {S[2**pN], S, Prod[2**pN:1]}; // Arithmetic Shift Right
end
// Assign the product less the two guard bits to the output port
always @(posedge Clk)
begin
if(Rst)
P <= #1 0;
else if(Cntr == 1)
P <= #1 {S[2**pN], S, Prod[2**pN:2]};
end
// Count the number of shifts
// This implementation does not use any optimizations to perform multiple
// bit shifts to skip over runs of 1s or 0s.
always @(posedge Clk)
begin
if(Rst)
Valid <= #1 0;
else
Valid <= #1 (Cntr == 1);
end
endmodule
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1'b0)
);
`include "bscan_common.v"
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/11/2015 05:46:30 PM
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timer(/*AUTOARG*/
// Outputs
timer_interrupt, timer_count_running,
// Inputs
clk, reset, timer_count, timer_enable, timer_interrupt_clear
);
input clk;
input reset;
input [31:0] timer_count;
input timer_enable;
input timer_interrupt_clear;
output timer_interrupt;
output [31:0] timer_count_running;
/*AUTOWIRE*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] timer_count_running;
reg timer_interrupt;
// End of automatics
//
// timer_count_done goes high if we have a running count that is greater
// or equal to the specified count and we are enabled.
//
wire timer_count_done = timer_enable & (timer_count_running >= (timer_count-1));
//
// On every clock edge, if we are done, reset the counter, because we have reached
// the specified count.
// If we are not done, but we are enabled, we are counting and witing until we are done
//
always @(posedge clk)
if (reset) begin
timer_count_running <= 16'b0;
end else if (timer_count_done) begin
timer_count_running <= 16'b0;
end else if (timer_enable) begin
timer_count_running <= timer_count_running +1;
end else begin
timer_count_running <= 16'b0;
end
//
// If the system indicated clear the interrupt, clear it.
// else if we are enabled and the timer_count is done, assert the interrupt.
// else if neither, keep the interrupt low since it is not time yet.
//
always @(posedge clk)
if (reset) begin
timer_interrupt <= 1'b0;
end else if (timer_interrupt_clear) begin
timer_interrupt <= 1'b0;
end else if (timer_enable) begin
timer_interrupt <= timer_count_done;
end else begin
timer_interrupt <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void func() { long long n; cin >> n; std::vector<pair<long long, long long> > v(n); for (long long i = 0; i < n; ++i) { cin >> v[i].first; } for (long long i = 0; i < n; ++i) { cin >> v[i].second; } sort(v.begin(), v.end()); multiset<long long> s; long long i = 0, ans = 0, sum = 0, cur = v[0].first; while (i < n || !s.empty()) { while (v[i].first == cur && i < n) { s.insert(v[i].second); sum += v[i].second; ++i; } if (!s.empty()) { long long x = *s.rbegin(); sum -= x; ans += sum; s.erase(s.find(x)); cur++; } else { cur = v[i].first; } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { func(); } } |
/*
* Copyright (C) 2007 Onno Kortmann <>
* Klaus Rudolph <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA..
*
*/
/* SimulavrXX glue code on the verilog side. */
/*
* Attention: Multiple assignment to a single wire with different strength will
* work only with up to date iverilog versions. Don't use any version below
* v10!
*/
/*
* FIXME: There are still open issues:
* simulavr itself runs a calculation on the connected nets on every pin.
* To fix that topic a new type of "pin" must be created ( verilog_pin ) which
* can be added to a simulavr "net". In the moment the simulation works
* only if simulavr drives only in to verilog and no other connected pins
* to a net inside the simulator itself. Adding multiple assignments in
* verilog works as expected.
*/
module avr_pin(conn);
parameter name="UNSPECIFIED";
inout conn;
wire out_value;
wire is_pulling;
integer val;
wire output_active;
assign output_active = (val<=2);
assign conn = output_active ? out_value : 1'bz;
assign ( pull1, pull0) conn = is_pulling ? out_value : 1'bz;
function avr2verilog;
input [4:0] apin;
begin
if (apin==0) // low
avr2verilog=1'b0;
else if (apin==1) // high
avr2verilog=1'b1;
else if (apin==2) // shorted
avr2verilog=1'bx;
else if (apin==3) // pull-up
avr2verilog=1'b1;
else if (apin==4) // tristate
avr2verilog=1'bz;
else if (apin==5) // pull-down ?? AVR Pin?
avr2verilog=1'b0;
else if (apin==6) // analog
avr2verilog=1'bx;
else if (apin==7) // analog, shorted
avr2verilog=1'bx;
end
endfunction // avr2verilog
function avr_port_is_pulling_only;
input [4:0] apin;
begin
if ( apin==3 ) // pull up
avr_port_is_pulling_only=1'b1;
else if ( apin==5 ) // pull down ( not used in avr core pins )
avr_port_is_pulling_only=1'b1;
else
avr_port_is_pulling_only=1'b0;
end
endfunction // avr_port_is_pulling_only
function verilog2avr;
input vpin;
if (vpin==1'bz)
verilog2avr=4; // tristate
else if (vpin==1'bx)
verilog2avr=2; // approximate as shorted
else if (vpin==1)
verilog2avr=1; // high
else if (vpin==0)
verilog2avr=0; // low
endfunction // verilog2avr
assign is_pulling=avr_port_is_pulling_only(val);
assign out_value=avr2verilog(val);
always @(posedge core.clk) begin
val<=$avr_get_pin(core.handle, name);
$avr_set_pin(core.handle, name, verilog2avr(conn));
end
endmodule // avr_pin
module avr_clock(clk);
output clk;
reg clk;
parameter FREQ=4_000_000;
initial begin
clk<=0;
end
always @(clk) begin
#(1_000_000_000/FREQ/2) clk<=~clk; //125000 -> 4MHz clock
end
endmodule // avr_clock
module AVRCORE(clk);
parameter progfile="UNSPECIFIED";
parameter name="UNSPECIFIED";
input clk;
integer handle;
integer PCw; // word-wise PC as it comes from simulavrxx
wire [16:0] PCb; // byte-wise PC as used in output from avr-objdump!
assign PCb=2*PCw;
initial begin
$display("Creating an AVR device.");
handle=$avr_create(name, progfile);
//$avr_reset(handle);
end
always @(posedge clk) begin
$avr_set_time($time);
$avr_tick(handle);
PCw=$avr_get_pc(handle);
end
endmodule // AVRCORE
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, k; cin >> n >> k; string s; cin >> s; if (k == 0) { cout << s; return; } if (n == 1) cout << 0 ; else { if (s[0] > 1 ) { s[0] = 1 ; k--; } for (long long int i = 1; i < n && k > 0; i++) { if (s[i] > 0 ) { s[i] = 0 ; k--; } } cout << s; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int t; t = 1; while (t--) { solve(); cout << n ; } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_rows_V_2_loc_channel1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_rows_V_2_loc_channel1_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_rows_V_2_loc_channel1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long double PI = acos((long double)-1); long long cnt[32][2]; class Node { public: Node* child[2]; long long cnt; Node() { child[0] = child[1] = NULL; cnt = 0; } }; class Trie { private: Node* root; public: Trie() { root = new Node(); } void insert(long long no) { Node* curr = root; for (long long i = 31; i >= 0; --i) { long long bit = (no >> i) & 1; if (!curr->child[bit]) { curr->child[bit] = new Node(); } if (curr->child[0] && curr->child[1]) { if (bit) { cnt[i][bit] += curr->child[0]->cnt; } else { cnt[i][bit] += curr->child[1]->cnt; } } curr = curr->child[bit]; ++curr->cnt; } } }; void solve() { long long n; cin >> n; Trie t; for (long long i = 1; i <= n; ++i) { long long x; cin >> x; t.insert(x); } long long x = 0; long long inv = 0; for (long long i = 31; i >= 0; --i) { if (cnt[i][1] < cnt[i][0]) { x += (1 << i); inv += cnt[i][1]; } else { inv += cnt[i][0]; } } cout << inv << << x << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int n; int res = 0; int r[10]; int v[10]; int main() { int t; cin >> t; while (t--) { long long x = 1; int n; cin >> n; for (int i = 3; i <= n * 2; i++) { x = x * i % mod; } cout << x << endl; } return 0; } |
// Answers are divided by 2.
module multiply_complex
#(
parameter WIDTH = 32
)
(
input wire clk,
input wire rst_n,
input wire signed [WIDTH-1:0] x,
input wire signed [WIDTH-1:0] y,
output wire signed [WIDTH-1:0] z
);
wire signed [WIDTH/2-1:0] x_re;
wire signed [WIDTH/2-1:0] x_im;
wire signed [WIDTH/2-1:0] y_re;
wire signed [WIDTH/2-1:0] y_im;
assign x_re = x[WIDTH-1:WIDTH/2];
assign x_im = x[WIDTH/2-1:0];
assign y_re = y[WIDTH-1:WIDTH/2];
assign y_im = y[WIDTH/2-1:0];
wire signed [WIDTH/2-1:0] xreyre;
wire signed [WIDTH/2-1:0] xreyim;
wire signed [WIDTH/2-1:0] ximyre;
wire signed [WIDTH/2-1:0] ximyim;
wire signed [WIDTH/2:0] z_re_l;
wire signed [WIDTH/2:0] z_im_l;
wire signed [WIDTH/2-1:0] z_re;
wire signed [WIDTH/2-1:0] z_im;
assign z_re_l = xreyre - ximyim;
assign z_im_l = xreyim + ximyre;
assign z_re = z_re_l >> 1;
assign z_im = z_im_l >> 1;
assign z = {z_re, z_im};
multiply #(WIDTH/2) multiply_0
(.clk(clk),
.rst_n(rst_n),
.x(x_re),
.y(y_re),
.z(xreyre)
);
multiply #(WIDTH/2) multiply_1
(.clk(clk),
.rst_n(rst_n),
.x(x_re),
.y(y_im),
.z(xreyim)
);
multiply #(WIDTH/2) multiply_2
(.clk(clk),
.rst_n(rst_n),
.x(x_im),
.y(y_re),
.z(ximyre)
);
multiply #(WIDTH/2) multiply_3
(.clk(clk),
.rst_n(rst_n),
.x(x_im),
.y(y_im),
.z(ximyim)
);
endmodule
|
module foo;
// syntaxify the unique keyword correctly please...
always_comb (*) begin
case (f)
1 : 2;
endcase // case (f)
unique case(vlcnum)
0 : unique case(in.value1)
0 : out = 1; 1 : out = 3; 2 : out = 3; 3 : out = 4;
4 : out = 4; 5 : out = 5; 6 : out = 5; 7 : out = 6;
8 : out = 6; 9 : out = 7; 10: out = 7; 11: out = 8;
12 : out = 8; 13: out = 9; 14: out = 9; 15: out = 9;
endcase
1 :
unique
case(in.value1)
0 : out = 3;
1 : out = 3;
2 : out = 3;
3 : out = 3;
4 : out = 3;
5 : out = 4;
6 : out = 4;
7 : out = 4;
8 : out = 4;
9 : out = 5;
10 : out = 5;
11 : out = 6;
12 : out = 6;
13 : out = 6;
14 : out = 6;
endcase // case (in.value1)
endcase // case (in.value1)
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int x, y, z; cin >> x >> y >> z; if (x != y && y != z && z != x) cout << NO << n ; else { int a = min(min(x, y), z); int c = max(max(x, y), z); int b = x + y + z - a - c; if (a == c || b == c) cout << YES << n << min(a, b) << << min(a, b) << << c << n ; else if (a == b) { if (b == c) cout << YES << n << a << << b << << c << n ; else cout << NO << n ; } } } } |
#include <bits/stdc++.h> const int N = 1005; int size[N], to[N << 1], edge, Next[N << 1], last[N], G, siz, cnt, w[N << 1], n, x, y, tag[N]; void add(int x, int y) { to[++edge] = y; Next[edge] = last[x]; last[x] = edge; } void dfs(int x, int fa) { size[x] = 1; int mx = 0; for (int i = last[x]; i; i = Next[i]) { int u = to[i]; if (u == fa) continue; dfs(u, x); size[x] += size[u]; mx = std::max(mx, size[u]); } mx = std::max(mx, n - size[x]); if (mx <= n / 2) G = x; } void dfs2(int x, int fa) { size[x] = 1; for (int i = last[x]; i; i = Next[i]) if (to[i] != fa) dfs2(to[i], x), size[x] += size[to[i]]; } void dfs3(int x, int fa, int t, int lstdis) { for (int i = last[x]; i; i = Next[i]) { int u = to[i]; if (u == fa) continue; ++cnt; w[i] = cnt * t - lstdis; dfs3(u, x, t, lstdis + w[i]); } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); add(x, y), add(y, x); } dfs(1, 0); dfs2(G, 0); siz = 0, cnt = 0; for (int i = last[G]; i; i = Next[i]) if (siz < n / 3 && siz + size[to[i]] <= 2 * n / 3) { tag[to[i]] = 1; siz += size[to[i]]; } for (int i = last[G]; i; i = Next[i]) if (tag[to[i]]) w[i] = ++cnt, dfs3(to[i], G, 1, cnt); cnt = 0; for (int i = last[G]; i; i = Next[i]) if (!tag[to[i]]) ++cnt, w[i] = cnt * (siz + 1), dfs3(to[i], G, siz + 1, cnt * (siz + 1)); for (int i = 1; i <= edge; i += 2) printf( %d %d %d n , to[i], to[i + 1], w[i] | w[i + 1]); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n = 0; cin >> n; int a[n], res[n]; for (int i = 0; i < n; i++) { cin >> a[i]; res[i] = 0; } for (int i = 0; i < n - 1; i++) { if (i) res[i] = res[i - 1]; while (a[i]) { int t = 0; for (t = 0; i + (1 << t) < n; t++) ; t--; a[i]--; a[i + (1 << t)]++; res[i]++; } } for (int i = 0; i < n - 1; i++) cout << res[i] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { long long l; long long r; long long s; node* ln; node* rn; void change(long long n, long long k) { if (l == r) s += k; else { if (n <= (l + r) / 2) { if (ln == 0) { ln = new node; *ln = {l, (l + r) / 2, 0}; } ln->change(n, k); } else { if (rn == 0) { rn = new node; *rn = {(l + r) / 2 + 1, r, 0}; } rn->change(n, k); } s = 0; if (ln != 0) s += ln->s; if (rn != 0) s += rn->s; } } long long query(long long a, long long b) { if (a == l && b == r) return s; if (b < l || a > r) return 0; long long v = 0; if (ln != 0) v += ln->query(a, min(b, (l + r) / 2)); if (rn != 0) v += rn->query(max(a, (l + r) / 2 + 1), b); return v; } }; int main() { cin.sync_with_stdio(false); cin.tie(0); int n; cin >> n; unordered_map<int, node> m; for (int i = 0; i < n; i++) { long long a, b, c; cin >> a >> b >> c; if (!m.count(c)) m[c] = {1, 1 << 30, 0}; if (a == 1) m[c].change(b, 1); else if (a == 2) m[c].change(b, -1); else cout << m[c].query(1, b) << n ; } } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 100010; int n, m, k, u, v, x, y, t, a, b, ans; string A[5]; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s; for (int i = 0; i < 5; i++) { cin >> A[i]; if (A[i][0] == s[0] || A[i][1] == s[1]) return cout << YES << n , 0; } return cout << NO << n , 0; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX = (int)1e5 + 5; int test; vector<int> con[MX]; int dp[MX], sz[MX], prv[MX]; void dfs(int u) { sz[u] = 1; for (int v : con[u]) { dp[v] = dp[u] + 1; dfs(v); sz[u] += sz[v]; } } int fst[MX], st[MX], en[MX], pn; void hld(int u, int hd) { fst[u] = hd; st[u] = ++pn; int w = 0; for (int v : con[u]) if (sz[w] < sz[v]) w = v; if (w) hld(w, hd); for (int v : con[u]) if (v != w) hld(v, v); en[u] = pn; } struct Node { int a, b, clr, len; Node(int a = 0, int b = 0, int clr = 0) : a(a), b(b), clr(clr) {} Node operator+(const Node &d) const { if (b >= d.a) return Node(a, b - d.a + d.b); else return Node(a + d.a - b, d.b); } void clear() { a = len, b = 0, clr = 1; } } node[1 << 20]; void push_down(int id) { if (node[id].clr) { node[id + id].clear(); node[id + id + 1].clear(); node[id].clr = 0; } } void push_up(int id) { node[id] = node[id + id] + node[id + id + 1]; node[id].len = node[id + id].len + node[id + id + 1].len; } void build(int id, int st, int en) { if (st == en) { node[id] = Node(1, 0, 0); node[id].len = 1; return; } int mid = st + en >> 1; build(id + id, st, mid); build(id + id + 1, mid + 1, en); push_up(id); } void add(int id, int st, int en, int pos, int val) { if (pos <= st && en <= pos) { node[id].b += val; return; } push_down(id); int mid = st + en >> 1; if (pos <= mid) add(id + id, st, mid, pos, val); if (pos > mid) add(id + id + 1, mid + 1, en, pos, val); push_up(id); } Node get(int id, int st, int en, int l, int r) { if (l <= st && en <= r) { return node[id]; } push_down(id); Node res = Node(0, 0); int mid = st + en >> 1; if (l <= mid) res = res + get(id + id, st, mid, l, r); if (r > mid) res = res + get(id + id + 1, mid + 1, en, l, r); push_up(id); return res; } vector<pair<int, int> > cur; int get_val(int u, int v, int n) { int fu, fv; Node res = Node(0, 0); cur.clear(); while (true) { fu = fst[u], fv = fst[v]; if (fu == fv) break; if (dp[fu] > dp[fv]) swap(u, v), swap(fu, fv); cur.push_back(make_pair(st[fv], st[v])); v = prv[fv]; } if (st[u] > st[v]) swap(u, v); cur.push_back(make_pair(st[u], st[v])); for (int i = cur.size() - 1; i >= 0; i--) res = res + get(1, 1, n, cur[i].first, cur[i].second); return res.b; } void clear(int id, int st, int en, int l, int r) { if (l <= st && en <= r) { node[id].clear(); return; } push_down(id); int mid = st + en >> 1; if (l <= mid) clear(id + id, st, mid, l, r); if (r > mid) clear(id + id + 1, mid + 1, en, l, r); push_up(id); } int main() { ios_base::sync_with_stdio(false); int n, q; cin >> n >> q; for (int i = 2; i <= n; i++) { int u; cin >> u; con[u].push_back(i); prv[i] = u; } dp[1] = 1; dfs(1); hld(1, 1); build(1, 1, n); while (q--) { int type, v; cin >> type >> v; if (type == 1) add(1, 1, n, st[v], 1); else { int val = get_val(v, 1, n); if (type == 3) cout << (val > 0 ? black : white ) << endl; else add(1, 1, n, st[v], -val), clear(1, 1, n, st[v] + 1, en[v]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> using vc = vector<T>; template <class T> using vvc = vc<vc<T>>; template <class T> void mkuni(vector<T>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } long long rand_int(long long l, long long r) { static mt19937_64 gen(chrono::steady_clock::now().time_since_epoch().count()); return uniform_int_distribution<long long>(l, r)(gen); } template <class T> void print(T x, int suc = 1) { cout << x; if (suc == 1) cout << n ; else cout << ; } template <class T> void print(const vector<T>& v, int suc = 1) { for (int i = 0; i < v.size(); i++) print(v[i], i == (int)(v.size()) - 1 ? suc : 2); } const int INF = 0x3f3f3f; const int maxn = 5e3 + 7; const int mod = 998244353; const int N = 1e7 + 7; int n; int dp[maxn][maxn]; int pre[maxn]; int sum[maxn]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; sort(a.begin(), a.end()); for (int i = 0; i < n; ++i) { pre[i + 1] = upper_bound(a.begin(), a.end(), (a[i]) / 2) - a.begin(); } dp[0][n + 1] = 1; for (int i = 0; i < n; ++i) { sum[n + 1] = dp[i][n + 1]; for (int k = n; k >= 1; --k) sum[k] = (sum[k + 1] + dp[i][k]) % mod; for (int j = 1; j <= n; ++j) { if (pre[n - j + 1] - i + 1 >= 0) dp[i + 1][j] = (dp[i + 1][j] + 1ll * dp[i][j] * (pre[n - j + 1] - i + 1) % mod) % mod; dp[i + 1][j] = (dp[i + 1][j] + sum[n - pre[n - j + 1] + 1]) % mod; } } cout << dp[n][1] << n ; return 0; } |
module sim_camera (
input i_cam_in_clk,
input i_cam_rst,
input i_flash,
output o_pix_clk,
output reg o_flash_strobe = 0,
output reg o_vsync = 0,
output reg o_hsync = 0,
output reg [7:0] o_pix_data = 0
);
//Local Parameters
localparam START = 4'h0;
localparam INIT = 4'h1;
localparam VBLANK = 4'h2;
localparam HBLANK = 4'h3;
localparam WRITE_ROW = 4'h4;
localparam VBLANK_COUNT = 100;
localparam HBLANK_COUNT = 20;
localparam ROW_COUNT = 32'h10;
localparam BYTE_COUNT = 32'h20;
//Registers/Wires
reg [31:0] r_vblank_count = 0;
reg [31:0] r_hblank_count = 0;
reg [31:0] r_byte_count = 0;
reg [31:0] r_row_count = 0;
reg [31:0] r_byte_index = 0;
reg [3:0] state = START;
wire w_vblank;
wire w_hblank;
reg [7:0] r_data = 8'h00;
//Submodules
//Asynchronous Logic
assign o_pix_clk = i_cam_in_clk;
assign w_vblank = (r_vblank_count < VBLANK_COUNT);
assign w_hblank = (r_hblank_count < HBLANK_COUNT);
//Synchronous Logic
always @ (posedge i_cam_in_clk) begin
if (!i_cam_rst) begin
o_flash_strobe <= 0;
o_vsync <= 0;
o_hsync <= 0;
o_pix_data <= 0;
r_vblank_count <= VBLANK_COUNT;
r_hblank_count <= HBLANK_COUNT;
r_row_count <= ROW_COUNT;
r_byte_count <= BYTE_COUNT;
state <= INIT;
r_data <= 0;
end
else begin
if (r_vblank_count < VBLANK_COUNT) begin
r_vblank_count <= r_vblank_count + 1;
end
if (r_hblank_count < HBLANK_COUNT) begin
r_hblank_count <= r_hblank_count + 1;
end
case (state)
START: begin
end
INIT: begin
o_vsync <= 0;
o_hsync <= 0;
r_vblank_count <= 0;
state <= VBLANK;
end
VBLANK: begin
o_vsync <= 0;
o_hsync <= 0;
r_data <= 0;
r_byte_count <= 0;
r_row_count <= 0;
if (!w_vblank) begin
state <= WRITE_ROW;
end
end
HBLANK: begin
o_vsync <= 1;
o_hsync <= 0;
r_data <= 0;
r_byte_count <= 0;
if (!w_hblank) begin
state <= WRITE_ROW;
end
end
WRITE_ROW: begin
o_vsync <= 1;
o_hsync <= 1;
if (r_byte_count < BYTE_COUNT) begin
//Send a byte
o_pix_data <= r_data;
r_data <= r_data + 1;
r_byte_count <= r_byte_count + 1;
end
else begin
//Still more rows to write
if (r_row_count < ROW_COUNT - 1) begin
r_hblank_count <= 0;
o_hsync <= 0;
state <= HBLANK;
r_row_count <= r_row_count + 1;
end
else begin
r_vblank_count <= 0;
o_vsync <= 0;
o_hsync <= 0;
state <= VBLANK;
end
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; void add(int &a, int b) { a += b; if (a >= M) a -= M; } int mypow(int x, int t) { int ans = 1, res = x; while (t) { if (t & 1) ans = (long long)ans * res % M; res = (long long)res * res % M, t >>= 1; } return ans; } int n; int fac[103], inv[103], p2[53], d[53], s1[53], s2[53], coef[53]; int f[53][53], g[53][103]; void init() { fac[0] = 1; for (int i = 1; i <= 100; i++) fac[i] = (long long)fac[i - 1] * i % M; inv[100] = mypow(fac[100], M - 2); for (int i = 99; ~i; i--) inv[i] = (long long)inv[i + 1] * (i + 1) % M; p2[0] = 1; for (int i = 1; i <= n; i++) p2[i] = (long long)p2[i - 1] * inv[2] % M; } int main() { scanf( %d , &n); init(); for (int i = 1; i <= n; i++) { scanf( %d , &d[i]); if (i > 1) { d[i]--; s1[i] = s1[i - 1], s2[i] = s2[i - 1]; if (d[i] == 1) s1[i]++; else s2[i]++; } } for (int s = 0; s <= n; s++) for (int p = 0; p * 2 <= s; p++) { int q = s - 2 * p, t = (long long)inv[p] * inv[q] % M; if ((p + q) & 1) add(coef[s], M - t); else add(coef[s], t); } f[1][d[1]] = 1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= 2 * n; j++) if (g[i][j]) for (int d = 0; d * 2 <= j; d++) add(f[i][j - d * 2], (long long)g[i][j] * inv[d] % M * p2[d] % M); for (int j = 1; i + j <= n; j++) if (f[i][j]) { int x = s1[i + j] - s1[i], y = s2[i + j] - s2[i]; int res = (long long)f[i][j] * fac[y] % M; for (int s = 0; s <= y; s++) add(g[i + j][x + 2 * y - 2 * s], (long long)res * coef[s] % M * fac[x + 2 * y - 2 * s] % M * inv[y - s] % M); } } int ans = f[n][0]; for (int i = 2; i <= n; i++) ans = (long long)ans * inv[d[i]] % M; printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; inline int inp() { return 0; } inline int inp(bool& A) { if (cin >> A) return 1; return -1; } inline int inp(char& A) { return scanf( %c , &A); } inline int inp(int& A) { return scanf( %d , &A); } inline int inp(float& A) { if (cin >> A) return 1; return -1; } inline int inp(long long& A) { return scanf( %I64d , &A); } inline int inp(double& A) { return scanf( %lf , &A); } inline int inp(char* A) { return scanf( %s , A); } inline int inp(string& A) { if (cin >> A) return 1; return -1; } template <class Front, class... Queue> inline int inp(Front& A, Queue&... B) { return inp(A) + inp(B...); } inline int oup() { return 0; } inline int oup(bool A) { if (cout << A) return 1; return -1; } inline int oup(char A) { return printf( %c , A); } inline int oup(int A) { return printf( %d , A); } inline int oup(float A) { if (cout << A) return 1; return -1; } inline int oup(long long A) { return printf( %I64d , A); } inline int oup(double A) { return printf( %lf , A); } inline int oup(char* A) { return printf(A); } inline int oup(const char* A) { return printf( %s , A); } inline int oup(string& A) { if (cout << A) return 1; return -1; } template <class Front, class... Queue> inline int oup(Front A, Queue... B) { return oup(A) + oup(B...); } template <class T> inline void remax(T& A, T B) { if (A < B) A = B; } template <class T> inline void remin(T& A, T B) { if (A > B) A = B; } string ToString(long long num) { string ret; do { ret += ((num % 10) + 0 ); num /= 10; } while (num); reverse(ret.begin(), ret.end()); return ret; } long long ToNumber(string s) { long long r = 0, p = 1; for (int i = s.size() - 1; i >= 0; --i) r += (s[i] - 0 ) * p, p *= 10; return r; } long long Gcd(long long a, long long b) { while (a %= b ^= a ^= b ^= a) ; return b; } long long Power(long long base, long long power) { long long ret = 1; while (power) { if (power & 1) ret *= base; power >>= 1; base *= base; } return ret; } long long PowerMod(long long base, long long power, long long mod) { if (!power) return 1; if (power & 1) return (base * PowerMod(base, power - 1, mod)) % mod; return PowerMod((base * base) % mod, power >> 1, mod); } int Log(long long num, long long base) { int ret = 0; while (num) { ++ret; num /= base; } return ret; } int Count(long long mask) { int ret = 0; while (mask) { if (mask & 1) ++ret; mask >>= 1; } return ret; } inline void run() { in:; int n, m, v; if (inp(n, m, v) != 3) return; if (m < n - 1) { oup( -1 n ); return; } if (m > (((n - 1) * (n - 2)) >> 1) + 1) { oup( -1 n ); return; } int tmp = 1; if (v == 1) ++tmp; for (int i = 1; i <= n; ++i) if (i != v) oup(i, , v, n ); m -= n - 1; for (int i = 1; i <= n && m; ++i) if (i != v && i != tmp) for (int j = i + 1; j <= n && m; ++j) if (j != v && j != tmp) { oup(i, , j, n ); --m; } goto in; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); run(); return 0; } |
#include <bits/stdc++.h> using namespace std; const char nl = n ; const int MAX_N = 100011; const long long INF = (1 << 29) + 123; const long long MOD = 998244353; const long double PI = 4 * atan((long double)1); template <typename T> bool ckmin(T& a, const T& b) { return a > b ? a = b, 1 : 0; } template <typename T> bool ckmax(T& a, const T& b) { return b > a ? a = b, 1 : 0; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << H << ; dbg_out(T...); } template <typename T> class SafeVector : public vector<T> { public: using vector<T>::vector; typename vector<T>::reference operator[](size_t n) { return vector<T>::at(n); } typename vector<T>::const_reference operator[](size_t n) const { return vector<T>::at(n); } }; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); const int MX = 2e5 + 5; long long a[MX][3]; vector<long long> x; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) for (int j = 0; j < 3; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) x.push_back(a[i][0]); long long dp[n]; for (int i = 0; i < n; i++) dp[i] = 0; long long pref[n + 1]; for (int i = 0; i < n + 1; i++) pref[i] = 0; dp[0] = a[0][0] - a[0][1]; pref[1] = dp[0]; for (int i = 1; i <= n - 1; i++) { int idx = lower_bound(x.begin(), x.end(), a[i][1]) - x.begin(); dp[i] = ((pref[i] - pref[idx]) % MOD + MOD + a[i][0] - a[i][1]) % MOD; pref[i + 1] = (pref[i] + dp[i]) % MOD; } long long ans = 0; for (int i = 0; i < n; i++) ans = ((a[i][2] * dp[i]) % MOD + ans) % MOD; cout << (ans + x[n - 1] + 1) % MOD << nl; return 0; } |
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 5;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("else1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("else1_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 3);
`assert(result_type, `i32);
`assert(result_empty, 0);
`assert(trap, `ENDED);
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
//
module some_module (
input wrclk
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge wrclk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (wrclk)
some_other_state <= 0;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin: a_generate_block
some_module
some_module
(
`ifdef BROKEN
.wrclk (i_clks[3])
`else
.wrclk (i_clk1)
`endif
);
end
endgenerate
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
assign the_clks[3] = i_clk1;
assign the_clks[2] = i_clk2;
assign the_clks[1] = i_clk1;
assign the_clks[0] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk1),
.i_clk2 (clk2),
.i_data (data_in)
);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: MULT.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MULT (
dataa,
datab,
result);
input [16:0] dataa;
input [16:0] datab;
output [33:0] result;
wire [33:0] sub_wire0;
wire [33:0] result = sub_wire0[33:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 17,
lpm_mult_component.lpm_widthb = 17,
lpm_mult_component.lpm_widthp = 34;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "17"
// Retrieval info: PRIVATE: WidthB NUMERIC "17"
// Retrieval info: PRIVATE: WidthP NUMERIC "34"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "17"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "17"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "34"
// Retrieval info: USED_PORT: dataa 0 0 17 0 INPUT NODEFVAL "dataa[16..0]"
// Retrieval info: USED_PORT: datab 0 0 17 0 INPUT NODEFVAL "datab[16..0]"
// Retrieval info: USED_PORT: result 0 0 34 0 OUTPUT NODEFVAL "result[33..0]"
// Retrieval info: CONNECT: @dataa 0 0 17 0 dataa 0 0 17 0
// Retrieval info: CONNECT: @datab 0 0 17 0 datab 0 0 17 0
// Retrieval info: CONNECT: result 0 0 34 0 @result 0 0 34 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; template <typename T> T id(T b) { return b; }; template <class It> bool all(It f, It l) { return std::all_of(f, l, id<bool>); } template <class It> bool any(It f, It l) { return std::any_of(f, l, id<bool>); } const int MAX_N = 2000, MAX_A = 1000000; int n, k, s; int a[MAX_N]; int main() { cin >> k; s = a[0] = -1; n = 1; while (s - n + 1 != k) { a[n] = min(k - (s - n), MAX_A); s += a[n]; n++; } cout << n << endl; for (int i = 0; i < n; i++) cout << a[i] << n [i + 1 == n]; return 0; } |
#include <bits/stdc++.h> using namespace std; long long sum(long long a[], long long n, long long s) { for (long long i = 0; i < n; i++) s += a[i]; return s; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } void solve() { long double a, b, x, y, z; cin >> a >> b; x = int((a + b) / (2 * b)); y = 2.0 * x; z = (1.0 * a + 1.0 * b) / y; if (a < b) { cout << -1 << endl; return; } cout << setprecision(12) << z << endl; return; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); long long t, T; T = 1; for (t = 1; t <= T; t++) { solve(); } return 0; } |
/*
A simplistic test for OBUFTDS. Two of them are instanciated and their outpus
are connected to LEDs. Data and tri-state inputs are controlled by switches.
Truth tables:
SW9 SW8 | LED3 LED2
0 0 | 1 0
0 1 | 0 1
1 0 | 0 0
1 1 | 0 0
SW11 SW10 | LED8 LED7
0 0 | 0 1
0 1 | 1 0
1 0 | 0 0
1 1 | 0 0
Couldn't use all switches and buttons at the same time as the differential
IOs use different IOSTANDARD than the single ended ones and have to be in
a separate bank.
*/
`default_nettype none
// ============================================================================
module top
(
input wire [11:8] sw,
output wire [1:0] diff_p,
output wire [1:0] diff_n
);
// ============================================================================
// OBUFTDS
wire [1:0] buf_i;
wire [1:0] buf_t;
OBUFTDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_0 (
.I(buf_i[0]),
.T(buf_t[0]),
.O(diff_p[0]), // LED2
.OB(diff_n[0]) // LED3
);
OBUFTDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_1 (
.I(buf_i[1]),
.T(buf_t[1]),
.O(diff_p[1]), // LED8
.OB(diff_n[1]) // LED7
);
// ============================================================================
assign buf_i[0] = sw[ 8];
assign buf_t[0] = sw[ 9];
assign buf_i[1] = sw[10];
assign buf_t[1] = sw[11];
endmodule
|
#include <bits/stdc++.h> using namespace std; int l_f, l_h; long long int dp[101][101][11][11]; int getans(int f, int h, int k1, int k2) { int x = 0, y = 0; if ((f + h) == 0) return 1; if (dp[f][h][k1][k2] != -1) return dp[f][h][k1][k2]; if (f > 0 && k1 > 0) x = getans(f - 1, h, k1 - 1, l_h); if (h > 0 && k2 > 0) y = getans(f, h - 1, l_f, k2 - 1); return dp[f][h][k1][k2] = (x + y) % 100000000; } int main() { int t = 1; while (t--) { int n1, n2; cin >> n1 >> n2 >> l_f >> l_h; memset(dp, -1, sizeof(dp)); int ans = getans(n1, n2, l_f, l_h); cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; char s1[1000], s2[1000], v[1000], s[1000]; int d[200][200][200]; int p[200][200][200][3]; int pp[1000]; int main() { int i, j, k, l1, l2, l, tmp, ans, bk, ti, tj, tk, m; scanf( %s%s%s , s1, s2, v); l1 = strlen(s1); l2 = strlen(s2); l = strlen(v); pp[0] = 0; pp[1] = 0; i = 0; j = 1; while (1) { if (j == l) break; pp[j] = i; while ((i > 0) && (v[i] != v[j])) i = pp[i]; if (v[i] == v[j]) { i++; j++; } else j++; } memset(d, -1, sizeof(d)); d[0][0][0] = 0; for (i = 0; i <= l1; i++) for (j = 0; j <= l2; j++) for (k = 0; k < l; k++) if (d[i][j][k] != -1) { if (i < l1) if (d[i][j][k] > d[i + 1][j][k]) { d[i + 1][j][k] = d[i][j][k]; p[i + 1][j][k][0] = i; p[i + 1][j][k][1] = j; p[i + 1][j][k][2] = k; } if (j < l2) if (d[i][j][k] > d[i][j + 1][k]) { d[i][j + 1][k] = d[i][j][k]; p[i][j + 1][k][0] = i; p[i][j + 1][k][1] = j; p[i][j + 1][k][2] = k; } if ((i < l1) && (j < l2) && (s1[i] == s2[j])) { tmp = k; while ((tmp > 0) && (v[tmp] != s1[i])) tmp = pp[tmp]; if (v[tmp] == s1[i]) tmp++; if (tmp < l) { if (d[i][j][k] + 1 > d[i + 1][j + 1][tmp]) { d[i + 1][j + 1][tmp] = d[i][j][k] + 1; p[i + 1][j + 1][tmp][0] = i; p[i + 1][j + 1][tmp][1] = j; p[i + 1][j + 1][tmp][2] = k; } } } } ans = -1; for (k = 0; k < l; k++) if (d[l1][l2][k] > ans) { ans = d[l1][l2][k]; bk = k; } if (ans == 0) printf( 0 n ); else { m = 0; ti = l1; tj = l2; tk = bk; while ((ti != 0) || (tj != 0)) { i = p[ti][tj][tk][0]; j = p[ti][tj][tk][1]; k = p[ti][tj][tk][2]; if ((i < ti) && (j < tj)) { s[m] = s1[i]; m++; } ti = i; tj = j; tk = k; } s[m] = 0 ; reverse(s, s + m); printf( %s n , s); } } |
// nios_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [28:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [28:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, h; cin >> n >> h; vector<pair<int, int>> zeros; int a, b; for (int i = 0; i < n; i++) { cin >> a >> b; zeros.push_back(make_pair(a, b)); } int sol = 0; int pa, pb, ib, c1; pa = zeros[0].first; pb = zeros[0].second; ib = 0; c1 = 0; while (c1 < h) { int d = h - c1; if (ib + 1 >= n) { pb = pb + d; c1 = h; break; } if (d <= zeros[ib + 1].first - pb) { pb = pb + d; c1 = h; break; } c1 += zeros[ib + 1].first - pb; pb = zeros[ib + 1].second; ib++; } sol = pb - pa; for (int i = 1; i < n; i++) { int ci1 = zeros[i].first - zeros[i - 1].second; pa = zeros[i].first; if (h < ci1) { pb = zeros[i].second; ib = i; c1 = 0; while (c1 < h) { int d = h - c1; if (ib + 1 >= n) { pb = pb + (h - c1); c1 = h; break; } if (d <= zeros[ib + 1].first - pb) { pb = pb + (h - c1); c1 = h; break; } c1 += zeros[ib + 1].first - pb; pb = zeros[ib + 1].second; ib++; } } else { c1 = h - ci1; while (c1 < h) { int d = h - c1; if (ib + 1 >= n) { pb = pb + (h - c1); c1 = h; break; } if (d <= zeros[ib + 1].first - pb) { pb = pb + (h - c1); c1 = h; break; } c1 += zeros[ib + 1].first - pb; pb = zeros[ib + 1].second; ib++; } } sol = max(sol, pb - pa); } cout << sol; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n; int seq[N]; vector<int> zli[N]; int res[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , seq + i); seq[i] = n - seq[i]; zli[seq[i]].push_back(i); } int rodzaj = 0; for (int ile = 1; ile <= n; ++ile) { if ((int)(zli[ile]).size() % ile) { puts( Impossible ); exit(0); } for (int i = 0; i < (int)(zli[ile]).size(); i += ile) { rodzaj++; for (int j = i; j < i + ile; ++j) { res[zli[ile][j]] = rodzaj; } } } puts( Possible ); for (int i = 1; i <= n; ++i) { printf( %d , res[i]); } puts( ); } |
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
output wire VGA_HSYNC,
output wire VGA_VSYNC,
output wire VGA_RED,
output wire VGA_GREEN,
output wire VGA_BLUE
);
wire [15:0] wIP,wIP_temp,wIP_return;
reg rWriteEnable,rBranchTaken,rReturn,rCall;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestinationPrev;
wire [15:0] wSourceData0,wSourceData1,wSourceData0_RAM,wSourceData1_RAM,wResultPrev,wIPInitialValue,wDestinationJump,wImmediateValue;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate,wPushAddr;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0_RAM ),
.oDataOut1( wSourceData1_RAM )
);
assign wDestinationJump = (rReturn) ? wIP_return : wDestination;
assign wIPInitialValue = (Reset) ? 8'b0 : wDestinationJump;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
/////////////////////////////////
// CALL RET //
// assign wPushAddr = (wInstruction[27:24] == `CALL);
//assign wPushAddr = (wOperation == `CALL);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FF_RET
(
.Clock(~Clock),
.Reset(Reset),
.Enable( rCall ),
.D( wIP_temp ),
.Q( wIP_return )
);
// //
/////////////////////////////////
//////////////////////////////
// VGA Controler and Memory //
VGA_Controller vga (
.Clock(Clock),
.Enable(1'b1),
.Reset(Reset),
.iPixel(`RED),
.oHorizontalSync(VGA_HSYNC),
.oVerticalSync(VGA_VSYNC),
.oRed(VGA_RED),
.oGreen(VGA_GREEN),
.oBlue(VGA_BLUE)
);
// Instanciar memoria aqui
// //
//////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b1;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b1;
rCall <= 1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
`WRITE_ROM :
begin
if (row <= 200){
}else if(row <= 400){
}else if (row <= 600) {
}else if(row <= 800) {}
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; int a[100000], k, i, n, j; char c; int main() { string s; cin >> k; i = 0; int p = 0; getline(cin, s); getline(cin, s); for (j = 0; j < s.length(); j++) { c = s[j]; p++; if (c == ? || c == . || c == ! ) { if (p > k) { cout << Impossible << endl; return 0; } a[i] = p; p = -1; i++; } } n = i; int g = 0, res = 0; for (i = 0; i < n; i++) { if (i == 0) { if (g + a[i] <= k) g += a[i]; } else if (g + a[i] + 1 <= k) g += (a[i] + 1); else { res++; g = a[i]; } } cout << res + 1 << endl; return 0; } |
/*
* Simple 8-bit wide GPIO module
*
* First byte is the GPIO I/O reg
* Second is the direction register
*
* Set direction bit to '1' to output corresponding data bit.
*
* Register mapping:
*
* adr 0: gpio data 7:0
* adr 1: gpio dir 7:0
*/
module gpio
(
input wb_clk,
input wb_rst,
input wb_adr_i,
input [7:0] wb_dat_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [7:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
input [7:0] gpio_i,
output reg [7:0] gpio_o,
output reg [7:0] gpio_dir_o
);
// GPIO dir register
always @(posedge wb_clk)
if (wb_rst)
gpio_dir_o <= 0; // All set to in at reset
else if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_adr_i == 1)
gpio_dir_o[7:0] <= wb_dat_i;
end
// GPIO data out register
always @(posedge wb_clk)
if (wb_rst)
gpio_o <= 0;
else if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_adr_i == 0)
gpio_o[7:0] <= wb_dat_i;
end
// Register the gpio in signal
always @(posedge wb_clk) begin
// Data regs
if (wb_adr_i == 0)
wb_dat_o[7:0] <= gpio_i[7:0];
// Direction regs
if (wb_adr_i == 1)
wb_dat_o[7:0] <= gpio_dir_o[7:0];
end
// Ack generation
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
assign wb_err_o = 0;
assign wb_rty_o = 0;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.8 2007/07/26 23:22:55 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Differential Signaling Input Clock Buffer
// /___/ /\ Filename : IBUFGDS.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 07/26/07 - Add else to handle x case for o_out (CR 424214).
// End Revision
`timescale 1 ps / 1 ps
module IBUFGDS (O, I, IB);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IOSTANDARD = "DEFAULT";
output O;
input I, IB;
reg o_out;
buf b_0 (O, o_out);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
end
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx && IB == 1'bx)
o_out <= 1'bx;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, n, ans, lcp[5009][5009], dp[5009]; char a[5009]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); scanf( %s , a + 1); ans = 0; for (int i = n; i >= 1; i--) for (int j = n; j >= 1; j--) lcp[i][j] = (a[i] == a[j]) ? (lcp[i + 1][j + 1] + 1) : 0; for (int i = 1; i <= n; i++) { dp[i] = n + 1 - i; for (int j = 1; j < i; j++) { int len = lcp[i][j]; if (a[j + len] < a[i + len]) dp[i] = max(dp[i], dp[j] + n + 1 - (i + len)); } ans = max(ans, dp[i]); } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, l, r, k, i, ans; int main() { scanf( %I64d%I64d%I64d%I64d , &n, &l, &r, &k); r = (r + n - l + 1) % n; if (k < r) { printf( -1 ); return 0; } if (2 * r >= k) { ans = min(k + n - r * 2 + 1, n); if (ans >= k - r) { printf( %I64d , ans); return 0; } } for (i = 1; i <= k; i++) { l = max((k - n * i - r - 1) / (i + 1), (k - n * i - r * 2 - 1) / i) + 1; ans = min(min((k - n * (i - 1) - r * 2 + 1) / (i + 1), (k - n * i - r) / i), n); if (ans >= l) { printf( %I64d , ans); return 0; } if (i * i >= k) break; } i = min(i, n); for (; i >= 0; i--) { l = k % (n + i) - r; if ((l <= min(i, r)) && (l >= max(i + r - n - 1, 0ll))) { if (n + i >= k) printf( %I64d , min(i + 1, n)); else printf( %I64d , i); return 0; } } printf( -1 ); } |
#include <bits/stdc++.h> using namespace std; int k; string s; vector<string> ans; bool all[26]; int main() { ios_base::sync_with_stdio(0); cin >> k >> s; string build = ; for (int i = 0; i < s.size(); ++i) if (!all[s[i] - a ]) { if (!build.empty()) ans.push_back(build); build = s[i]; all[s[i] - a ] = 1; } else build += s[i]; ans.push_back(build); if (ans.size() < k) cout << NO ; else { cout << YES << n ; while (ans.size() > k) { int last = ans.size() - 1; string s1 = ans[last], s2 = ans[last - 1]; ans.pop_back(); ans.pop_back(); ans.push_back(s2 + s1); } for (int i = 0; i < ans.size(); ++i) cout << ans[i] << n ; } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_response_handler (
input clk,
input resetn,
input bvalid,
output bready,
input [1:0] bresp,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] wait_id,
input sync_id,
input enable,
output reg enabled,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
parameter C_ID_WIDTH = 3;
`include "resp.v"
`include "inc_id.v"
assign resp_resp = bresp;
assign resp_eot = eot;
wire active = id != wait_id && enabled;
assign bready = active && resp_ready;
assign resp_valid = active && bvalid;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (wait_id == id)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
if ((bready && bvalid) ||
(sync_id && id != wait_id))
id <= inc_id(id);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int sigma = maxn; const int HASH_CNT = 2; int n; char s[maxn]; unsigned long long Prime_Pool[] = {1998585857ul, 23333333333ul}; unsigned long long Seed_Pool[] = {146527, 19260817}; unsigned long long Mod_Pool[] = {1000000009, 998244353}; unsigned long long has1[26], has2[26]; struct Hash { unsigned long long Seed, Mod; unsigned long long bas[maxn]; unsigned long long sum[26][maxn]; int perm[sigma]; void init(int seedIndex, int modIndex) { Seed = Seed_Pool[seedIndex]; Mod = Mod_Pool[modIndex]; bas[0] = 1; for (int i = 1; i <= n; i++) { bas[i] = bas[i - 1] * Seed % Mod; } for (int i = 1; i <= n; i++) { for (int j = 0; j < 26; j++) { sum[j][i] = (sum[j][i - 1] * Seed % Mod + (s[i] == j + a )) % Mod; } } } unsigned long long getHash(int ch, int l, int r) { return (sum[ch][r] - sum[ch][l - 1] * bas[r - l + 1] % Mod + Mod) % Mod; } } hasher[HASH_CNT]; bool check(int l1, int r1, int l2, int r2) { for (int i = 0; i < HASH_CNT; i++) { for (int j = 0; j < 26; j++) { has1[j] = hasher[i].getHash(j, l1, r1); has2[j] = hasher[i].getHash(j, l2, r2); } sort(has1, has1 + 26); sort(has2, has2 + 26); for (int j = 0; j < 26; j++) if (has1[j] != has2[j]) { return false; } } return true; } int main() { int m, x, y, len; scanf( %d%d , &n, &m); scanf( %s , s + 1); for (int i = 0; i < HASH_CNT; i++) hasher[i].init(i, i); while (m--) { scanf( %d%d%d , &x, &y, &len); if (check(x, x + len - 1, y, y + len - 1)) puts( YES ); else puts( NO ); } return 0; } |
// Copyright (c) 2001 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This module implements what essentially amounts to an array of DFF
* devices with output enable. This test checks the operation of the
* pmos and nmos devices.
*/
module grayGap (ad, clk, read, write);
output [31:0] ad;
input clk, read, write;
reg [15:0] regff;
pmos ad_drv [31:0] (ad, {16'b0, regff}, read);
always @(posedge clk)
if (write) regff = ad[15:0];
endmodule
module main;
wire [31:0] ad;
reg clk, read, write;
reg [31:0] ad_val;
reg ad_en;
nmos ad_drv[31:0] (ad, ad_val, ad_en);
grayGap test (ad, clk, read, write);
always #10 clk = ~clk;
initial begin
clk = 1;
read = 1;
write = 0;
$monitor($time, "ad=%b", ad);
// Set up to write a value into the grayGap register.
@(negedge clk)
ad_val = 32'haaaa_aaaa;
read = 1;
write = 1;
ad_en = 1;
// The posedge has passed, now set up to read that value
// out. Turn all the drivers off for a moment, to see that the
// line becomes tri-state...
@(negedge clk)
ad_en = 0;
write = 0;
// Now read the value.
#1 read = 0;
#1 $display("Wrote %h, got %h", ad_val, ad);
if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin
$display("FAILED -- ad is %b", ad);
$finish;
end
#2 read = 1;
$display("PASSED");
$finish;
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HD__SEDFXBP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, p, q; pair<int, int> pro[100010]; long long cross(int x1, int y1, int x2, int y2) { return x1 * (long long)y2 - x2 * (long long)y1; } double cross2(double x1, double y1, double x2, double y2) { return x1 * y2 - x2 * y1; } bool check(pair<int, int> c, pair<int, int> b, pair<int, int> a) { return cross(b.first - a.first, b.second - a.second, c.first - b.first, c.second - b.second) >= 0; } pair<int, int> st[100010]; int tp = -1; int main() { scanf( %d%d%d , &n, &p, &q); int maxa = 0, maxb = 0; for (int i = 1; i <= n; i++) { scanf( %d%d , &pro[i].first, &pro[i].second); maxa = max(maxa, pro[i].first); maxb = max(maxb, pro[i].second); } sort(pro + 1, pro + n + 1); st[++tp] = make_pair(0, maxb); for (int i = 1; i <= n; i++) { while (tp > 0 && check(pro[i], st[tp], st[tp - 1])) tp--; st[++tp] = pro[i]; } st[++tp] = make_pair(maxa, 0); int line; for (int i = 0; i < tp; i++) { if ((atan2(q, p) - atan2(st[i + 1].second, st[i + 1].first) >= -1e-9) && (atan2(st[i].second, st[i].first) - atan2(q, p) >= -1e-9)) line = i; } double lo = 0, hi = 1e6; while (lo < hi - 1e-9) { double mi = (lo + hi) / 2; if ((0 - cross2(p / mi - st[line].first, q / mi - st[line].second, p / mi - st[line + 1].first, q / mi - st[line + 1].second) >= -1e-9)) hi = mi; else lo = mi; } printf( %.10f n , lo); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void __print(int x) { cout << x; } void __print(long x) { cout << x; } void __print(long long x) { cout << x; } void __print(unsigned x) { cout << x; } void __print(unsigned long x) { cout << x; } void __print(unsigned long long x) { cout << x; } void __print(float x) { cout << x; } void __print(double x) { cout << x; } void __print(long double x) { cout << x; } void __print(char x) { cout << << x << ; } void __print(const char *x) { cout << << x << ; } void __print(const string &x) { cout << << x << ; } void __print(bool x) { cout << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cout << { ; __print(x.first); cout << , ; __print(x.second); cout << } ; } template <typename T> void __print(const T &x) { int first = 0; cout << { ; for (auto &i : x) cout << (first++ ? , : ), __print(i); cout << } ; } void _print() { cout << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cout << , ; _print(v...); } template <class T> void remdup(vector<T> &v) { sort((v).begin(), (v).end()); v.erase(unique((v).begin(), (v).end()), end(v)); } template <typename T> struct cmp { bool operator()(const T &p1, const T &p2) {} }; const long long N = 1e5 + 100; const long long mod = 1e9 + 7; const long long X = 2e5 + 100; long long dp[205][205][205], n, kk; string s, t; long long solve(long long nn, long long k, long long a) { if (nn == n) return 0; if (dp[nn][k][a] != -1) return dp[nn][k][a]; long long a1 = 0; long long a2 = 0; if (t[0] == s[nn]) a1++; if (t[1] == s[nn]) a2 = a; long long ans = a2 + solve(nn + 1, k, a + a1); for (long long i = (0); i < (2); ++i) { if (k == 0) break; a1 = 0, a2 = 0; if (t[i] == t[0]) a1++; if (t[i] == t[1]) a2 = a; ans = max(ans, a2 + solve(nn + 1, k - 1, a + a1)); } return dp[nn][k][a] = ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); ; memset(dp, -1, sizeof(dp)); cin >> n >> kk; cin >> s >> t; cout << solve(0, kk, 0); return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_rd_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_arready ,
input wire s_arvalid ,
input wire [7:0] s_arlen ,
output wire m_arvalid ,
input wire m_arready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_ready ,
// status signal for w_channel when command is written.
output wire a_push ,
output wire r_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] state_r1;
reg [1:0] next_state;
reg [7:0] s_arlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// register for timing
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
state_r1 <= SM_IDLE;
s_arlen_r <= 0;
end else begin
state <= next_state;
state_r1 <= state;
s_arlen_r <= s_arlen;
end
end
// Next state transitions.
always @( * ) begin
next_state = state;
case (state)
SM_IDLE:
if (s_arvalid & data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_EN:
///////////////////////////////////////////////////////////////////
// Drive m_arvalid downstream in this state
///////////////////////////////////////////////////////////////////
//If there is no fifo space
if (~data_ready & m_arready & next_pending) begin
///////////////////////////////////////////////////////////////////
//There is more to do, wait until data space is available drop valid
next_state = SM_CMD_ACCEPTED;
end else if (m_arready & ~next_pending)begin
next_state = SM_DONE;
end else if (m_arready & next_pending) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_ACCEPTED:
if (data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_DONE:
next_state = SM_IDLE;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_arvalid = (state == SM_CMD_EN);
assign next = m_arready && (state == SM_CMD_EN);
assign r_push = next;
assign a_push = (state == SM_IDLE);
assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE)) && (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Apr 21 20:32:54 2015"
module ALU_Cell_16bit(
A,
B,
FS,
Z,
C,
N,
V,
F
);
input wire [15:0] A;
input wire [15:0] B;
input wire [4:0] FS;
output wire Z;
output wire C;
output wire N;
output wire V;
output wire [15:0] F;
wire [15:0] F_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
assign V = 0;
assign SYNTHESIZED_WIRE_4 = 0;
ALU_Cell_4bit b2v_inst(
.C_in(SYNTHESIZED_WIRE_0),
.A_from_next_bit(A[4]),
.A(A[3:0]),
.B(B[3:0]),
.FS(FS),
.C_out(SYNTHESIZED_WIRE_1),
.F(F_ALTERA_SYNTHESIZED[3:0]));
ALU_Cell_4bit b2v_inst1(
.C_in(SYNTHESIZED_WIRE_1),
.A_from_next_bit(A[8]),
.A(A[7:4]),
.B(B[7:4]),
.FS(FS),
.C_out(SYNTHESIZED_WIRE_2),
.F(F_ALTERA_SYNTHESIZED[7:4]));
ALU_Cell_4bit b2v_inst2(
.C_in(SYNTHESIZED_WIRE_2),
.A_from_next_bit(A[12]),
.A(A[11:8]),
.B(B[11:8]),
.FS(FS),
.C_out(SYNTHESIZED_WIRE_3),
.F(F_ALTERA_SYNTHESIZED[11:8]));
ALU_Cell_4bit b2v_inst3(
.C_in(SYNTHESIZED_WIRE_3),
.A_from_next_bit(SYNTHESIZED_WIRE_4),
.A(A[15:12]),
.B(B[15:12]),
.FS(FS),
.C_out(C),
.F(F_ALTERA_SYNTHESIZED[15:12]));
Zero_Check b2v_inst5(
.F(F_ALTERA_SYNTHESIZED),
.Z(Z));
Cin_logic b2v_inst6(
.FS0(FS[0]),
.FS1(FS[1]),
.FS2(FS[2]),
.FS3(FS[3]),
.C0(SYNTHESIZED_WIRE_0));
assign N = F_ALTERA_SYNTHESIZED[15];
assign F = F_ALTERA_SYNTHESIZED;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Mod = 1e9 + 7; int qpow(long long a, long long b) { long long c = 1; while (b) { if (b & 1) c = c * a % Mod; if (b >>= 1) a = a * a % Mod; } return c; } int n; long long a; int p, q; int main() { scanf( %d , &n); bool minus = 1; q = 2; for (int i = 1; i <= n; i++) { scanf( %I64d , &a); if (!(a & 1)) minus = 0; q = qpow(q, a); } q = q * 500000004ll % Mod; if (minus) { p = q - 1; if (p < 0) p += Mod; } else p = q + 1; p = p * 333333336ll % Mod; printf( %d/%d n , p, q); return 0; } |
#include <bits/stdc++.h> int input[1001]; int ans[1001][2]; int main() { int n, i, answer; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d , &input[i]); ans[0][0] = 1; for (i = 1; i < n; i++) { if (input[i] >= input[i - 1]) ans[i][0] = 1 + ans[i - 1][0]; else ans[i][0] = 1; } ans[n - 1][1] = 1; for (i = n - 2; i >= 0; i--) { if (input[i] >= input[i + 1]) ans[i][1] = ans[i + 1][1] + 1; else ans[i][1] = 1; } answer = -1; for (i = 0; i < n; i++) answer = (answer > ans[i][0] + ans[i][1] ? (answer) : (ans[i][0] + ans[i][1])); printf( %d n , answer - 1); } |
#include <bits/stdc++.h> using namespace std; int main() { pair<int, int> k[3]; char cell[9][9]; int n; cin >> n; char c; int z = 0; while (n) { for (int i = 1; i < 9; i++) { for (int j = 1; j < 9; j++) { cin >> c; if (c == K ) { k[z].first = i; k[z].second = j; z++; } } } if (abs(k[0].first - k[1].first) == 4 || abs(k[0].first - k[1].first) == 0) { if (abs(k[0].second - k[1].second) == 4 || abs(k[0].second - k[1].second) == 0) { cout << YES n ; z = 0; n--; continue; } } cout << NO n ; z = 0; n--; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 105; int n, s, c[maxN], sum1, sum2; vector<int> d; bool cmp(int A, int B) { return A > B; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> s; for (int j = 1; j <= s; j++) cin >> c[j]; for (int j = 1; j <= s / 2; j++) sum1 += c[j]; for (int j = (s + 1) / 2 + 1; j <= s; j++) sum2 += c[j]; if (s % 2 == 1) d.push_back(c[(s + 1) / 2]); } sort(d.begin(), d.end(), cmp); for (int i = 0; i < d.size(); i++) if (i % 2 == 0) sum1 += d[i]; else sum2 += d[i]; cout << sum1 << << sum2; return 0; } |
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module soc_system_hps_only_master_b2p_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input [ 7: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel ;
// Suppress channels that are higher than the destination's max_channel.
if (in_channel > 0) begin
out_valid = 0;
// Simulation Message goes here.
end
end
endmodule
|
// This tests assigning value lists to packed arrays
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// parameters for array sizes
localparam WA = 4;
localparam WB = 4;
// 2D packed arrays
logic [WA-1:0] [WB-1:0] abg0, abg1, abg2, abg3, abg4, abg5, abg6, abg7, abg8, abg9; // big endian array
logic [0:WA-1] [0:WB-1] alt0, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, alt9; // little endian array
// error counter
bit err = 0;
initial begin
abg0 = '{ 3 ,2 ,1, 0 };
abg1 = '{0:4, 1:5, 2:6, 3:7};
abg2 = '{default:13};
abg3 = '{2:15, default:13};
abg4 = '{WA { {WB/2 {2'b10}} }};
abg5 = '{WA { {3'b101, {WB/2-1{2'b10}}} }};
abg6 = '{WA { {WB/2-1{2'b10}} }};
abg7 [WA/2-1:0 ] = '{WA/2{ {WB/2 {2'b10}} }};
abg8 [WA -1:WA/2] = '{WA/2{ {WB/2 {2'b01}} }};
abg9 = '{err+0, err+1, err+2, err+3};
// check
if (abg0 !== 16'b0011_0010_0001_0000) begin $display("FAILED -- abg0 = 'b%b", abg0); err=1; end
if (abg1 !== 16'b0111_0110_0101_0100) begin $display("FAILED -- abg1 = 'b%b", abg1); err=1; end
if (abg2 !== 16'b1101_1101_1101_1101) begin $display("FAILED -- abg2 = 'b%b", abg2); err=1; end
if (abg3 !== 16'b1101_1111_1101_1101) begin $display("FAILED -- abg3 = 'b%b", abg3); err=1; end
if (abg4 !== 16'b1010_1010_1010_1010) begin $display("FAILED -- abg4 = 'b%b", abg4); err=1; end
if (abg5 !== 16'b0110_0110_0110_0110) begin $display("FAILED -- abg5 = 'b%b", abg5); err=1; end
if (abg6 !== 16'b0010_0010_0010_0010) begin $display("FAILED -- abg6 = 'b%b", abg6); err=1; end
if (abg7 !== 16'bxxxx_xxxx_1010_1010) begin $display("FAILED -- abg7 = 'b%b", abg7); err=1; end
if (abg8 !== 16'b1010_1010_xxxx_xxxx) begin $display("FAILED -- abg8 = 'b%b", abg8); err=1; end
if (abg9 !== 16'b0000_0001_0010_0011) begin $display("FAILED -- abg9 = 'b%b", abg9); err=1; end
alt0 = '{ 3 ,2 ,1, 0 };
alt1 = '{0:4, 1:5, 2:6, 3:7};
alt2 = '{default:13};
alt3 = '{2:15, default:13};
alt4 = '{WA { {WB/2 {2'b10}} }};
alt5 = '{WA { {3'b101, {WB/2-1{2'b10}}} }};
alt6 = '{WA { {WB/2-1{2'b10}} }};
alt7 [0 :WA/2-1] = '{WA/2{ {WB/2 {2'b10}} }};
alt8 [WA/2:WA -1] = '{WA/2{ {WB/2 {2'b01}} }};
alt9 = '{err+0, err+1, err+2, err+3};
// check
if (alt0 !== 16'b0011_0010_0001_0000) begin $display("FAILED -- alt0 = 'b%b", alt0); err=1; end
if (alt1 !== 16'b0100_0101_0110_0111) begin $display("FAILED -- alt1 = 'b%b", alt1); err=1; end
if (alt2 !== 16'b1101_1101_1101_1101) begin $display("FAILED -- alt2 = 'b%b", alt2); err=1; end
if (alt3 !== 16'b1101_1101_1111_1101) begin $display("FAILED -- alt3 = 'b%b", alt3); err=1; end
if (alt4 !== 16'b1010_1010_1010_1010) begin $display("FAILED -- alt4 = 'b%b", alt4); err=1; end
if (alt5 !== 16'b0110_0110_0110_0110) begin $display("FAILED -- alt5 = 'b%b", alt5); err=1; end
if (alt6 !== 16'b0010_0010_0010_0010) begin $display("FAILED -- alt6 = 'b%b", alt6); err=1; end
if (alt7 !== 16'b1010_1010_xxxx_xxxx) begin $display("FAILED -- alt7 = 'b%b", alt7); err=1; end
if (alt8 !== 16'bxxxx_xxxx_1010_1010) begin $display("FAILED -- alt8 = 'b%b", alt8); err=1; end
if (alt9 !== 16'b0000_0001_0010_0011) begin $display("FAILED -- alt9 = 'b%b", alt9); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
#include <bits/stdc++.h> #define st first #define nd second #define pb push_back #define BOOST ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); #define PI 3.14159265359 using namespace std; typedef long long ll; constexpr ll MOD = 1000000007, sup = 29; constexpr ll MOD_1 = 1234567891, sup_1 = 1009; constexpr ll MOD_2 = 1000000009, sup_2 = 107; constexpr int MXN = 200000+10, CZAPA = (1<<18), INF = 1000000000; int n, m; struct tree{ pair<int, int> tab[2*CZAPA+10]; void add(int leaf, int x){ int v = leaf + CZAPA; tab[v] = {x, x}; v /= 2; while(v >= 1){ tab[v].st = min(tab[2*v].st, tab[2*v+1].st); tab[v].nd = max(tab[2*v].nd, tab[2*v+1].nd); v /= 2; } } pair<int, int> query(int a, int b, int v, int p, int q){ if(q < a || b < p) return {INF, -INF}; if(p >= a && q <= b) return tab[v]; int mid = (p+q)/2; pair<int, int> x = query(a, b, 2*v, p, mid), y = query(a, b, 2*v+1, mid+1, q); return {min(x.st, y.st), max(x.nd, y.nd)}; } pair<int, int> query(int a, int b){ return query(a+CZAPA, b+CZAPA, 1, CZAPA, 2*CZAPA-1); } }; tree T; int tab[MXN]; int main(){ BOOST; int t; cin>> t; T.add(0, 0); while(t--){ string s; cin>> n >> m >> s; for(int i=1; i<=n; i++){ tab[i] = tab[i-1]; if(s[i-1] == - ) tab[i]--; else tab[i]++; T.add(i, tab[i]); //cout<< tab[i] << ; } //cout<< n ; while(m--){ int a, b; cin>> a >> b; pair<int, int> x = T.query(0, a-1); int sum = tab[b] - tab[a-1]; pair<int, int> y = T.query(b+1, n); if(y.st == INF){ cout<< abs(x.st-x.nd)+1 << n ; continue; } y.st -= sum; y.nd -= sum; pair<int, int> ans = {min(x.st, y.st), max(x.nd, y.nd)}; cout<< abs(ans.st-ans.nd)+1 << n ; //cout<< x.st << ~ << x.nd << , << y.st << ~ << y.nd << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int ans[2020], cnt = 0, k; int main() { cin >> k; k++; ans[++cnt] = -1; while (k >= 1e6 - 1) { k -= 1e6 - 1; ans[++cnt] = 1e6 - 1 + 1; } ans[++cnt] = k + 1; cout << cnt << endl; for (int i = 1; i <= cnt; i++) cout << ans[i] << ; cout << endl; return 0; } |
// megafunction wizard: %LPM_BUSTRI%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_bustri
// ============================================================
// File Name: bustri.v
// Megafunction Name(s):
// lpm_bustri
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: BiDir NUMERIC "0"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
// Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
// Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
#include <bits/stdc++.h> const int N = 1e5 + 1, B = 128; int i, j, n, m, r, a[N], f[N][B]; int main() { for (scanf( %d , &n); ++i <= n; scanf( %d , a + i)) ; for (j = 1; j < B; ++j) for (i = n; i; --i) f[i][j] = i + j + a[i] > n ? 1 : f[i + j + a[i]][j] + 1; for (scanf( %d , &m); m--;) { scanf( %d%d , &i, &j); if (j < B) printf( %d n , f[i][j]); else { for (r = 0; i <= n; i += j + a[i]) ++r; printf( %d n , r); } } } |
#include <bits/stdc++.h> using namespace std; string solve1(string n) { string res(n.length(), 9 ); for (char c = 8 ; c >= 0 ; c--) { string t(n.length(), c); if (t >= n) res = t; } return res; } string solve2(string n) { string res = solve1(n); for (char a = 0 ; a <= 9 ; a++) for (char b = a + 1; b <= 9 ; b++) { bool n_ok = true; for (int i = 0; i < n.length(); i++) { if (n[i] < b) { string t = n; if (t[i] < a) t[i] = a; else t[i] = b; for (int j = i + 1; j < n.length(); j++) t[j] = a; if (res > t) res = t; } if (n[i] != a && n[i] != b) { n_ok = false; break; } } if (n_ok) return n; } return res; } string solve() { string n; int k; cin >> n >> k; if (k == 1) return solve1(n); else return solve2(n); } int main() { int t; cin >> t; while (t--) cout << solve() << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; cin >> s1 >> s2; int n = s1.length(), p = 0, a = 0, p2 = 0; for (int i = 0; i < n; i++) if (s1[i] == + ) p++; int m = n - p; for (int i = 0; i < n; i++) { if (s2[i] == ? ) a++; else if (s2[i] == + ) p2++; } int m2 = n - a - p2; if (abs(p2 - p) <= a && abs(m2 - m) <= a) { float y = abs(p2 - p), ans = 1; y = min(y, a - y); for (int i = a; i > a - y; i--) ans *= i; for (int i = 2; i <= y; i++) ans /= i; float s = pow(2, a); printf( %.9f , ans / s); } else cout << 0; return 0; } |
//**************************************************************************
// hp_bytequad.v - wrapper for 4 FIFOs in the host to parasite direction.
//
// COPYRIGHT 2010 Richard Evans, Ed Spittles
//
// This file is part of tube - an Acorn Tube ULA compatible system.
//
// tube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// tube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with tube. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
`timescale 1ns / 1ns
module hp_bytequad (
input h_rst_b,
input h_we_b,
input [3:0] h_selectData,
input h_phi2,
input [7:0] h_data,
input [3:0] p_selectData,
input p_phi2,
input p_rdnw,
input one_byte_mode,
output [7:0] p_data,
output [3:0] p_data_available,
output p_r3_two_bytes_available,
output [3:0] h_full
);
// Declare registers and wires
reg [7:0] p_datamux_r;
wire [3:0] h_full_pre_w;
wire [7:0] fifo0_w,
fifo1_w,
fifo2_w,
fifo3_w;
// assign primary IOs
assign p_data = p_datamux_r;
assign h_full = h_full_pre_w;
// Combinatorial code for the data output
always @ (fifo0_w or
fifo1_w or
fifo2_w or
fifo3_w or
p_selectData
)
casex (p_selectData)
4'bxxx1: p_datamux_r = fifo0_w;
4'bxx1x: p_datamux_r = fifo1_w;
4'bx1xx: p_datamux_r = fifo2_w;
4'b1xxx: p_datamux_r = fifo3_w;
default: p_datamux_r = 8'bx;
endcase // case p_selectData
// module instances
hp_byte reg1 (
.h_rst_b(h_rst_b),
.h_we_b(h_we_b),
.h_selectData(h_selectData[0]),
.h_phi2(h_phi2),
.h_data(h_data),
.p_selectData(p_selectData[0]),
.p_phi2(p_phi2),
.p_rdnw(p_rdnw),
.p_data(fifo0_w),
.p_data_available(p_data_available[0]),
.h_full(h_full_pre_w[0])
);
hp_byte reg2 (
.h_rst_b(h_rst_b),
.h_we_b(h_we_b),
.h_selectData(h_selectData[1]),
.h_phi2(h_phi2),
.h_data(h_data),
.p_selectData(p_selectData[1]),
.p_phi2(p_phi2),
.p_rdnw(p_rdnw),
.p_data(fifo1_w),
.p_data_available(p_data_available[1]),
.h_full(h_full_pre_w[1])
);
hp_reg3 reg3 (
.h_rst_b(h_rst_b),
.h_we_b(h_we_b),
.h_selectData( h_selectData[2]),
.h_phi2(h_phi2),
.h_data( h_data ),
.p_selectData( p_selectData[2]),
.p_phi2(p_phi2),
.p_rdnw(p_rdnw),
.one_byte_mode(one_byte_mode),
.p_data(fifo2_w),
.p_data_available(p_data_available[2]),
.p_two_bytes_available( p_r3_two_bytes_available),
.h_full(h_full_pre_w[2])
);
hp_byte reg4 (
.h_rst_b(h_rst_b),
.h_we_b(h_we_b),
.h_selectData(h_selectData[3]),
.h_phi2(h_phi2),
.h_data(h_data),
.p_selectData(p_selectData[3]),
.p_phi2(p_phi2),
.p_rdnw(p_rdnw),
.p_data(fifo3_w),
.p_data_available(p_data_available[3]),
.h_full(h_full_pre_w[3])
);
endmodule // hp_byte
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; int temp; long long sol = 0; cin >> s; if ((s[0] - 0 ) % 4 == 0) { sol++; } for (int a = s.length() - 1; a > 0; a--) { temp = (s[a] - 0 ) + 10 * (s[a - 1] - 0 ); if (temp % 4 == 0) { sol += a; } if ((s[a] - 0 ) % 4 == 0) { sol++; } } cout << sol << n ; cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize Ofast,omit-frame-pointer,inline using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; int mx = -INT_MAX; multiset<int> vs; for (int i = 0; i < n; i++) { int x; cin >> x; mx = max(mx, x); vs.insert(x); } mx += m; while (m--) { int p = *vs.begin(); vs.insert(p + 1); vs.erase(vs.begin()); } cout << (*vs.rbegin()) << << mx << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 40; const int M = 20; long long incident_mask[N]; vector<int> g[N]; int n, m, used[N]; long long ans = 0; long long cntmask[1 << M]; template <typename T> inline void chkmax(T &x, T y) { x = max(x, y); } template <typename T> inline void chkmin(T &x, T y) { x = min(x, y); } template <typename T> inline void read(T &x) { T f = 1; x = 0; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + c - 0 ; x *= f; } inline long long binpow(long long a, long long n) { long long res = 1; for (; n; n >>= 1, a = (long long)a * a) if (n & 1) res = (long long)res * a; return res; } inline void dfs(int x, int c) { if (used[x]) return; used[x] = c; for (int y : g[x]) dfs(y, 3 - c); } inline long long CountIsolated() { long long ans = 0; for (int i = 0; i < n; ++i) if (g[i].empty()) ++ans; return ans; } inline long long CountComponents() { memset(used, 0, sizeof(used)); long long ans = 0; for (int i = 0; i < n; ++i) if (!used[i]) { ++ans; dfs(i, 1); } return ans; } inline bool bipartite() { memset(used, 0, sizeof(used)); for (int i = 0; i < n; ++i) if (!used[i]) dfs(i, 1); for (int i = 0; i < n; ++i) for (int j : g[i]) if (used[i] == used[j]) return false; return true; } inline long long CountIndependentSets() { int m1 = min(n, 20); int m2 = n - m1; memset(cntmask, 0, sizeof(cntmask)); for (int i = 0; i < (1 << m1); ++i) { long long curmask = 0; bool good = true; for (int j = 0; j < m1; ++j) { if ((i & (1 << j)) == 0) continue; if (curmask & (1 << j)) good = false; curmask |= ((1 << j) | incident_mask[j]); } if (good) ++cntmask[curmask >> m1]; } for (int i = 0; i < m2; ++i) for (int j = 0; j < (1 << m2); ++j) if (j & (1 << i)) cntmask[j] += cntmask[j ^ (1 << i)]; long long ans = 0; for (int i = 0; i < (1 << m2); i++) { long long curmask = 0; bool good = true; for (int j = m1; j < n; j++) { if ((i & (1 << (j - m1))) == 0) continue; if (curmask & (1LL << j)) good = false; curmask |= (1LL << j) | incident_mask[j]; } if (good) ans += cntmask[(i ^ ((1 << m2) - 1))]; } return ans; } inline long long calc(int mask) { if (mask == 0) return binpow(2, n); if (mask == 1 || mask == 4) return CountIndependentSets(); if (mask == 2) return binpow(2, CountComponents()); if (mask == 3 || mask == 6) return binpow(2, CountIsolated()); if (mask == 5) return (bipartite() ? binpow(2, CountComponents()) : 0); if (mask == 7) return (m == 0 ? binpow(2, n) : 0); return 0; } int main() { read(n); read(m); for (int i = 0; i < m; ++i) { int u, v; read(u), read(v); --u, --v; g[u].emplace_back(v); g[v].emplace_back(u); incident_mask[u] ^= (1LL << v); incident_mask[v] ^= (1LL << u); } long long ans = 0; for (int i = 0; i < 8; ++i) if (__builtin_popcount(i) % 2 == 0) ans += calc(i); else ans -= calc(i); printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_1_V
`define SKY130_FD_SC_HS__NOR2B_1_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_1 (
Y ,
A ,
B_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_1 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_1_V
|
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