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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a; map<int, int> mp; int mx = 0; for (int i = 0; i < n; i++) { cin >> a; mp[a]++; } for (auto it : mp) { mx = max(mx, it.second); } cout << n - mx; } |
`define ADDER_WIDTH 005
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
#include <bits/stdc++.h> using namespace std; const int MN = 100000 + 1; int N; char buf[2000]; int main() { scanf( %d , &N); for (int i = 0; i < N; i++) { int a, b; scanf( %s%d%d , buf, &a, &b); if (a >= 2400 && b > a) { puts( YES ); return 0; } } puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1.0); const long long LINF = (long long)1e18 + 5; const int INF = (int)1e9 + 5; template <class T> T sqr(T x) { return x * x; } template <class T> T abs(T x) { return x < 0 ? -x : x; } template <class T> long long round(T x) { return x < 0 ? x - 0.5 : x + 0.5; } template <class T> bool chmin(T& x, const T& y) { if (y < x) { x = y; return true; } return false; } template <class T> bool chmax(T& x, const T& y) { if (x < y) { x = y; return true; } return false; } template <class P, class Q> ostream& operator<<(ostream& os, const pair<P, Q>& p) { return os << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& os, const vector<T>& v) { bool was = false; os << { ; for (typename vector<T>::const_iterator it = v.begin(); it != v.end(); it++) { if (was) { os << , ; } else { was = true; } os << *it; } os << } ; return os; } template <class T> ostream& operator<<(ostream& os, const set<T>& v) { bool was = false; os << { ; for (typename set<T>::const_iterator it = v.begin(); it != v.end(); it++) { if (was) { os << , ; } else { was = true; } os << *it; } os << } ; return os; } template <class T> ostream& operator<<(ostream& os, const multiset<T>& v) { bool was = false; os << { ; for (typename multiset<T>::const_iterator it = v.begin(); it != v.end(); it++) { if (was) { os << , ; } else { was = true; } os << *it; } os << } ; return os; } template <class P, class Q> ostream& operator<<(ostream& os, const map<P, Q>& v) { bool was = false; os << { ; for (typename map<P, Q>::const_iterator it = v.begin(); it != v.end(); it++) { if (was) { os << , ; } else { was = true; } os << *it; } os << } ; return os; } template <class T> T nextInt() { long long x = 0; bool p = false; char c; do { c = getchar(); } while (c <= 32); if (c == - ) { p = true; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return (p ? -x : x); } string nextToken() { static char str[200200]; scanf( %s , str); return str; } const int N = 300300; int n; long long t[N], w[N]; struct cmpByDiff { bool operator()(int i, int j) { return make_pair(w[i] - t[i], i) < make_pair(w[j] - t[j], j); } }; struct cmpByT { bool operator()(int i, int j) { return make_pair(t[i], i) > make_pair(t[j], j); } }; set<int, cmpByDiff> topSet; set<int, cmpByT> loserSet; void answer(int x) { printf( %d n , x); exit(0); } void solve() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld%lld , t + i, w + i); } long long curT = t[0]; for (int i = 1; i < n; i++) { if (t[i] > curT) { topSet.insert(i); } else { loserSet.insert(i); } } int best = (int)topSet.size() + 1; while (true) { best = min(best, (int)topSet.size() + 1); if (topSet.empty()) { answer(1); } int idx = *topSet.begin(); topSet.erase(idx); long long cost = w[idx] - t[idx] + 1; if (cost > curT) break; curT -= cost; while (!loserSet.empty()) { int jdx = *loserSet.begin(); loserSet.erase(jdx); if (t[jdx] > curT) { topSet.insert(jdx); } else { loserSet.insert(jdx); break; } } } answer(best); } int main() { srand(time(0)); int t = 1; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; const int step[2] = {-1, 1}, mn = 101000; int n, m, xs, ys, kx, ky, x, y, fx, fy, cnt; long long ans; string st; set<int> T[mn]; void fix(int x, int y, int& fx, int& fy) { if (x == 1) fx = 1; else if (x == n) fx = 0; if (y == 1) fy = 1; else if (y == m) fy = 0; } int run(int& x, int& y, int& fx, int& fy) { int l = n; if (fx == 0) l = min(l, x - 1); else l = min(l, n - x); if (fy == 0) l = min(l, y - 1); else l = min(l, m - y); x += l * step[fx], y += l * step[fy]; fix(x, y, fx, fy); return l; } int main() { cin >> n >> m >> xs >> ys >> st; kx = st[0] == D , ky = st[1] == R ; fix(xs, ys, kx, ky); x = xs, y = ys, fx = kx, fy = ky; ans = cnt = 1; T[x].insert(y); for (;;) { ans += run(x, y, fx, fy); if (!T[x].count(y)) { ++cnt; T[x].insert(y); } if (cnt == n + m - 2) break; if (x == xs && y == ys && fx == kx && fy == ky) break; } if (cnt == n + m - 2) cout << ans << endl; else cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n < 4) { cout << NO n ; return 0; } cout << YES n ; if (n >= 4 && !(n & 1)) { int ones = 0; for (int i = 5; i < n; i += 2) { printf( %d - %d = 1 n , i + 1, i); ones++; } cout << 1 * 4 = 4 n ; cout << 4 * 2 = 8 n ; cout << 8 * 3 = 24 n ; while (ones > 0) { cout << 24 * 1 = 24 n ; ones--; } return 0; } if (n > 4 && n & 1) { cout << 5 - 1 = 4 n ; cout << 4 - 2 = 2 n ; cout << 4 * 2 = 8 n ; cout << 8 * 3 = 24 n ; int ones = 0; for (int i = 6; i < n; i += 2) { printf( %d - %d = 1 n , i + 1, i); ones++; } while (ones > 0) { cout << 24 * 1 = 24 n ; ones--; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_4_V
`define SKY130_FD_SC_LS__A32OI_4_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32oi_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/22/2015 09:35:04 AM
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Enable signal is assumed to synchronous; if enable transitions low during pwm pulse,
// pulse will gracefully complete
//
//////////////////////////////////////////////////////////////////////////////////
module pwm (
input clk,
input enable,
input [31:0] clk_period,
input [31:0] pwm_period,
output out
);
reg clk_out=1'b0;
reg [31:0] counter = 32'b0;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
if (counter < pwm_period)
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
if (counter < (clk_period-1))
begin
clk_out <= 1'b0;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end //end if counter < pwm_period
end //end if(enable)
else
begin
if ((counter > 0) && (counter < pwm_period) ) //gracefully end the last pwm if it has begun
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end
end
assign out = clk_out;
endmodule |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { while (b) { swap(a %= b, b); } return a; } long long n, m, x, y, a, b, g; double dist1(long long curstep) { long long l1 = a / g * curstep; long long l2 = b / g * curstep; long long x1 = max(1ll, (x - (l1 - l1 / 2))); if (x1 + l1 > n) { x1 = n - l1; } long long x2 = x1 + l1; long long y1 = max(1ll, (y - (l2 - l2 / 2))); if (y1 + l2 > m) { y1 = m - l2; } long long y2 = y1 + l2; double c1 = (x1 + x2 + .0) / 2; double c2 = (y1 + y2 + .0) / 2; double tempdst = sqrt((c1 - x) * (c1 - x) + (c2 - y) * (c2 - y)); return tempdst; } int main() { cin >> n >> m >> x >> y >> a >> b; g = gcd(a, b); a /= g; b /= g; long long step = min(n / a, m / b); a *= step; b *= step; long long l1 = a; long long l2 = b; long long x1 = max(0ll, (x - (l1 - l1 / 2))); if (x1 + l1 > n) { x1 = n - l1; } long long x2 = x1 + l1; long long y1 = max(0ll, (y - (l2 - l2 / 2))); if (y1 + l2 > m) { y1 = m - l2; } long long y2 = y1 + l2; cout << x1 << ; cout << y1 << ; cout << x2 << ; cout << y2; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_TB_V
`define SKY130_FD_SC_LP__NAND3B_TB_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_lp__nand3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_BLACKBOX_V
`define SKY130_FD_SC_HD__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_BLACKBOX_V
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:40 EST 2017
//
// Method conflict info:
// Method: gen_grant_carry
// Conflict-free: gen_grant_carry
//
//
// Ports:
// Name I/O size props
// gen_grant_carry O 2
// gen_grant_carry_c I 1
// gen_grant_carry_r I 1
// gen_grant_carry_p I 1
//
// Combinational paths from inputs to outputs:
// (gen_grant_carry_c, gen_grant_carry_r, gen_grant_carry_p) -> gen_grant_carry
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module module_gen_grant_carry(gen_grant_carry_c,
gen_grant_carry_r,
gen_grant_carry_p,
gen_grant_carry);
// value method gen_grant_carry
input gen_grant_carry_c;
input gen_grant_carry_r;
input gen_grant_carry_p;
output [1 : 0] gen_grant_carry;
// signals for module outputs
wire [1 : 0] gen_grant_carry;
// value method gen_grant_carry
assign gen_grant_carry =
{ gen_grant_carry_r && (gen_grant_carry_c || gen_grant_carry_p),
!gen_grant_carry_r &&
(gen_grant_carry_c || gen_grant_carry_p) } ;
endmodule // module_gen_grant_carry
|
`timescale 1ns/1ns
module inport_basic_tb();
reg clka;
reg rsta;
reg [1:0] diff_pair_din;
reg [47:0] channel_din;
wire request_dout;
wire x_hit_dout;
wire y_hit_dout;
wire [3:0] x_addr_dout;
wire [3:0] y_addr_dout;
wire [39:0] payload_dout;
// clk generator
always
begin
#(10)
clka = ~clka;
end
inport UUT
(
.clka(clka),
.rsta(rsta),
.diff_pair_din(diff_pair_din),
.channel_din(channel_din),
.request_dout(request_dout),
.x_hit_dout(x_hit_dout),
.y_hit_dout(y_hit_dout),
.x_addr_dout(x_addr_dout),
.y_addr_dout(y_addr_dout),
.payload_dout(payload_dout)
); // inport
// stimuli
initial
begin
// initial values
clka = 1'b0;
rsta = 1'b1;
diff_pair_din = 2'b10;
channel_din = 0;
// stimuli
repeat (10)
@(negedge clka);
// out of reset
rsta = 1'b0;
repeat (10)
@(negedge clka);
diff_pair_din = 2'b01;
channel_din = 48'h02a987654321;
@(negedge clka);
channel_din = 48'h000000000000;
repeat (10)
@(negedge clka);
diff_pair_din = 2'b10;
channel_din = 48'h200b0073d000;
repeat (10)
@(negedge clka);
diff_pair_din = 2'b00;
channel_din = 48'h000000000000;
repeat (10)
@(negedge clka);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long dp[1020][600], mod = (1000000007); long long solve(int n, int m, int k) { if (n < 2 * k - 1 or m < 2 * k - 1) return 0; if (n <= 0 or m <= 0) return !k; if (!k) return 1; if (n == 2 * k - 1) { if (dp[m][k] != -1) return dp[m][k]; long long ans = 0; for (int dy = 1; dy <= m; dy++) { long long aux = (solve(2 * k - 3, dy - 2, k - 1) * (m - dy + 1)) % mod; ans += aux; if (ans > mod) ans -= mod; } return dp[m][k] = ans; } else if (m == 2 * k - 1) return dp[n][k] = solve(2 * k - 1, n, k); else return (solve(n, 2 * k - 1, k) * solve(2 * k - 1, m, k)) % mod; } int n, m, k; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; memset(dp, -1, sizeof dp); cout << solve(n - 2, m - 2, k) << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLRBP_PP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_PP_SYMBOL_V
|
// bsg_rp_clk_gen_coarse_delay_element
//
// (o is inverting on even start_tap_p
// worst_o is non-inverting)
//
// o contains controllably delayed signal
// worst_o contains worst-case delayed signal (for delay matching)
//
//
// we use sed to substitute parameters because the netlist reader
// does not like them, and we need the netlist reader for rp_groups
//
// module bsg_clk_gen_coarse_delay_element #(parameter `BSG_INV_PARAM(start_tap_p))
//
module bsg_rp_clk_gen_atomic_delay_tuner
(input i
, input sel_i
, input we_i
, input async_reset_neg_i
, output o
);
wire [1:0] sel_r;
wire [8:0] signal;
assign signal[0] = i;
// synopsys rp_group (bsg_clk_gen_adt)
// synopsys rp_fill (13 2 LX)
CLKINVX2 I1 (.A(signal[0]), .Y(signal[1]) );
CLKINVX2 I2 (.A(signal[1]), .Y(signal[2]) );
CLKINVX4 I2a (.A(signal[1]), .Y() );
CLKINVX2 I3 (.A(signal[2]), .Y(signal[3]) );
CLKINVX2 I4 (.A(signal[3]), .Y(signal[4]) );
CLKINVX4 I4a (.A(signal[3]), .Y() );
CLKINVX2 I4b (.A(signal[3]), .Y() ); // this is an extra gate because
// we are not attaching to the mux
// cap tries to match that of mux input
CLKINVX2 I5 (.A(signal[4]), .Y(signal[5]) );
CLKINVX2 I6 (.A(signal[5]), .Y(signal[6]) );
CLKINVX4 I6a (.A(signal[5]), .Y() );
CLKINVX2 I7 (.A(signal[6]), .Y(signal[7]) );
CLKINVX2 I8 (.A(signal[7]), .Y(signal[8]) );
CLKINVX4 I8a (.A(signal[7]), .Y() );
CLKINVX3 I8b (.A(signal[7]), .Y() ); // fudge factor capacitance
// synopsys rp_fill (0 1 RX)
wire zero_bit;
MXI4X4 M1 ( .A(signal[8])
,.B(signal[6])
,.C(zero_bit)
,.D(signal[0])
,.S0(sel_r[0])
,.S1(sel_r[1])
,.Y (o )
);
wire [1:0] mux_lo;
// synopsys rp_fill (0 0 RX)
// this gate picks input 01 when async reset is low, initializing the oscillator
NAND2BX2 NB (.AN(sel_r[0]), .B(async_reset_neg_i), .Y(sel_r[1]));
TIELO ZB (.Y(zero_bit));
wire sel_r_0_inv, sel_i_inv;
DFFRX4 sel_r_reg_0 (.D(mux_lo[0]), .CK(o) ,.RN(async_reset_neg_i), .Q(sel_r[0]), .QN(sel_r_0_inv));
CLKINVX2 I_MX (.A(sel_i), .Y(sel_i_inv));
// we invert both inputs of this mux to optimize the select-to-output path by 40 ps
MXI2X1 MX1 (.A(sel_r_0_inv) , .B(sel_i_inv) ,.S0(we_i), .Y(mux_lo[0]));
// synopsys rp_endgroup (bsg_clk_gen_adt)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_atomic_delay_tuner)
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2002 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================
// FILE DETAILS
// Project : PCI_EXP_X1_11
// File : tx_gear.v
// Title :
// Dependencies :
// Description : Rate conversion bridge for Tx path.
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Author(s) :
// Mod. Date : Jan 26, 2006
// Changes Made : Initial Creation
// =============================================================================
`timescale 1 ns / 1 ps
module tx_gear #(
parameter GWIDTH = 20
)
(
input wire clk_125 , // 125 Mhz clock.
input wire clk_250 , // 250 Mhz clock.
input wire rst_n , // asynchronous system reset.
input wire drate_enable, //Enable for Counters
input wire [GWIDTH-1:0] data_in , // Data In
output reg [GWIDTH/2-1:0] data_out // Data Out
);
// =============================================================================
reg [1:0] wr_pntr; // Write Pointer
reg [1:0] rd_pntr; // Read Pointer
reg rd_en; // Read Pointer Enable
wire [GWIDTH/2-1:0] rd_data0; // Read Data
wire [GWIDTH/2-1:0] rd_data1; // Read Data
integer i;
integer j;
// RAM's : Expected to inferred as distributed ram
reg [GWIDTH/2-1:0] rf_0[0:3] ;
reg [GWIDTH/2-1:0] rf_1[0:3] ;
reg drate_f0 /* synthesis syn_srlstyle="registers" */;
reg drate_f1 /* synthesis syn_srlstyle="registers" */;
reg drate_s0;
reg rd_enable;
reg[2:0] rd_cnt;
//synchronize drate_enable to 250mhz clock
always @(posedge clk_250, negedge rst_n) begin
if (!rst_n) begin
drate_f0 <= 1'b0;
drate_f1 <= 1'b0;
end
else begin
drate_f0 <= drate_enable;
drate_f1 <= drate_f0;
end
end
// delay drate_enable by a 125mhz clock
// to adjust synchronizer delay
always @(posedge clk_125, negedge rst_n) begin
if (!rst_n)
drate_s0 <= 1'b0;
else
drate_s0 <= drate_enable;
end
// =============================================================================
// Write 8 bits each into different memories out of incomming
// 16 bits data at 125 Mhz.
// Read 8 bits of data, alternatively from each memory at 250 Mhz.
// =============================================================================
// Write Pointer
always @(posedge clk_125, negedge rst_n) begin
if (!rst_n)
wr_pntr <= 2'b00;
else if(drate_s0)
wr_pntr <= wr_pntr + 2'b01;
else
wr_pntr <= wr_pntr;
end
// Read Pointer Enable for half-rate
always @(posedge clk_250, negedge rst_n) begin
if (!rst_n)
rd_en <= 1'b0;
else if(~drate_f1)
rd_en <= 1'b0;
else
rd_en <= ~rd_en;
end
// Read Pointer
always @(posedge clk_250, negedge rst_n) begin
if (!rst_n)
rd_pntr <= 2'b10;
else if (rd_en & drate_f1)
rd_pntr <= rd_pntr + 2'b01;
end
// Output Data Select
always @(posedge clk_250, negedge rst_n) begin
if (!rst_n)
data_out <= 0;
else begin
if(rd_enable)
data_out <= rd_en ? rd_data0 : rd_data1;
else
data_out <= 10'b1000000000; // Bit 9 is TxElecIdle
end
end
// =============================================================================
always @(posedge clk_125, negedge rst_n) begin
if (!rst_n)
for (i=0;i<=3;i=i+1)
rf_0[i] <= 0;
else
rf_0[wr_pntr] <= data_in[GWIDTH/2-1:0] ;
end
assign rd_data0 = rf_0[rd_pntr] ;
always @(posedge clk_125, negedge rst_n) begin
if (!rst_n)
for (j=0;j<=3;j=j+1)
rf_1[j] <= 0;
else
rf_1[wr_pntr] <= data_in[GWIDTH-1:GWIDTH/2] ;
end
assign rd_data1 = rf_1[rd_pntr] ;
// =============================================================================
// Avoid RESET data from Dist. Memory
// Take Read data after Writing, until then EI is HIGH
// Wait for 8 (250 Mhz) clks after enable
// =============================================================================
always @(posedge clk_250, negedge rst_n) begin
if (!rst_n) begin
rd_cnt <= 3'b000;
rd_enable <= 1'b0;
end
else begin
if(drate_f1)
rd_cnt <= rd_cnt + 3'b001;
else
rd_cnt <= 3'b000;
if(~drate_f1)
rd_enable <= 1'b0;
else if(rd_cnt == 3'b111)
rd_enable <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[3000]; long long h[200000], pw[200000]; string st, st1, st2; long l1, l2, l, ans, fl, g1[20000], g2[20000]; long long gethash(long a, long b) { return (h[b + 1] - h[a]) * pw[st.size() - b + 1]; } int main() { cin >> st; cin >> st1 >> st2; pw[0] = 1; for (int i = 1; i <= 3000; i++) pw[i] = pw[i - 1] * 29; for (int i = 1; i <= st.size(); i++) h[i] = h[i - 1] + st[i - 1] * pw[i]; l = st.size(); l1 = st1.size(); l2 = st2.size(); for (int i = 0; i <= l - l1; i++) { fl = 0; for (int j = 0; j < l1; j++) if (st1[j] != st[i + j]) { fl++; break; } if (fl == 0) g1[i] = 1; } for (int i = 0; i <= l - l2; i++) { fl = 0; for (int j = 0; j < l2; j++) if (st2[j] != st[i + j]) { fl++; break; } if (fl == 0) g2[i + l2 - 1] = 1; } long lll = max(l1, l2); for (int i = 0; i < l; i++) for (int j = i; j < l; j++) if (g1[i] && g2[j] && (j - i + 1 >= lll)) { v[j - i + 1].push_back(gethash(i, j)); } for (int i = 1; i <= l; i++) { sort(v[i].begin(), v[i].end()); if (v[i].size()) ans++; for (int j = 1; j < v[i].size(); j++) if (v[i][j] != v[i][j - 1]) ++ans; } cout << ans << endl; cin.get(); cin.get(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_20_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_20_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog wrapper for busdrivernovlp with size of 20 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdrivernovlp_20 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busdrivernovlp base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdrivernovlp_20 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busdrivernovlp base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_20_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_SYMBOL_V
/**
* udp_dff$PE_pp$PG: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PE_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DATA_EN,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; set<pair<int, int> > V; int p[102345]; int main() { int n, m, x, y; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &y); V.insert(make_pair(x, y)); V.insert(make_pair(y, x)); } for (int i = 0; i < n; i++) p[i] = i + 1; int tim = 16384; bool flag = false; while (tim && !flag) { random_shuffle(p, p + n); p[n] = p[0]; int cnt = 0; for (int i = 0; i < n; i++) { if (!V.count(pair<int, int>(p[i], p[i + 1]))) cnt++; if (cnt == m) { for (int i = 0; m > 0; i++) { if (!V.count(pair<int, int>(p[i], p[i + 1]))) { printf( %d %d n , p[i], p[i + 1]); m--; } } flag = true; break; } } tim--; } if (!flag) puts( -1 ); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : IBUFDS_GTE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 12/11/2012 - Initial version
// 03/22/2013 - Model added
// 03/25/2013 - Sync 5 YML & model update
// 04/12/2013 - Add attribute section
// 08/28/2013 - Add specify section
// 06/02/2014 - New simulation library message format.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_GTE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)(
output O,
output ODIV2,
input CEB,
input I,
input IB
);
// define constants
localparam MODULE_NAME = "IBUFDS_GTE3";
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
localparam [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL;
localparam [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX;
`endif
wire REFCLK_EN_TX_PATH_BIN;
wire [1:0] REFCLK_HROW_CK_SEL_BIN;
wire [1:0] REFCLK_ICNTL_RX_BIN;
wire i_in, ib_in, ceb_in;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_GTE3_dr.v"
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
assign i_in = I;
assign ib_in = IB;
assign ceb_in = CEB;
assign REFCLK_EN_TX_PATH_BIN = REFCLK_EN_TX_PATH_REG;
assign REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG;
assign REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG;
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_EN_TX_PATH_REG !== 1'b0) && (REFCLK_EN_TX_PATH_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] REFCLK_EN_TX_PATH attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, REFCLK_EN_TX_PATH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REFCLK_HROW_CK_SEL_REG < 2'b00) || (REFCLK_HROW_CK_SEL_REG > 2'b11))) begin
$display("Error: [Unisim %s-103] REFCLK_HROW_CK_SEL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, REFCLK_HROW_CK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_RX_REG < 2'b00) || (REFCLK_ICNTL_RX_REG > 2'b11))) begin
$display("Error: [Unisim %s-104] REFCLK_ICNTL_RX attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, REFCLK_ICNTL_RX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
reg ODIV2_out=0;
wire O_out;
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
initial begin
allEqual = 0;
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(*) begin
case (REFCLK_HROW_CK_SEL_BIN)
2'b00: ODIV2_out <= O_out;
2'b01: ODIV2_out <= allEqual;
2'b10: ODIV2_out <= 1'b0;
2'b11: ODIV2_out <= 1'b0;
default : ODIV2_out <= O_out;
endcase
end
// =====================
// Generate O
// =====================
assign O_out = (REFCLK_EN_TX_PATH_BIN | ceb_in) ? 1'b0 : i_in;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => ODIV2) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => ODIV2) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => ODIV2) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Verify task with I/O.
//
// D: Pass a task two values and modify a global variable.
//
module main();
reg [3:0] global_reg;
task inc_glob;
input [3:0] in_1;
input [3:0] in_2;
begin
global_reg = in_1 + in_2 ;
end
endtask
initial
begin
global_reg = 2;
inc_glob(global_reg,global_reg);
if(global_reg != 4)
begin
$display("FAILED - task didn't modify global_reg\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module master_0_timing_adt (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [ 7: 0] in_data,
// Interface: out
output reg out_valid,
output reg [ 7: 0] out_data,
input out_ready
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 7: 0] in_payload;
reg [ 7: 0] out_payload;
reg [ 0: 0] ready;
reg in_ready;
// synthesis translate_off
always @(negedge in_ready) begin
$display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
end
// synthesis translate_on
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data};
{out_data} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[0] = out_ready;
out_valid = in_valid;
out_payload = in_payload;
in_ready = ready[0];
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEV",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEV",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEV",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_TB_V
`define SKY130_FD_SC_HD__O2111A_TB_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o2111a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; vector<pair<int, int>> v; set<int> s; for (int i = 0; i < n; i++) { cin >> a[i]; v.push_back(make_pair(a[i], i)); s.insert(a[i]); } int m = s.size(); sort(v.begin(), v.end()); vector<int> r; for (auto i : s) { r.push_back(i); } if (n == 1) { cout << 1 << endl; cout << a[0] << << 0; } else { int x = 0; vector<vector<int>> p(m); for (int i = 0; i < n; i++) { if (i == 0 || v[i].first == v[i - 1].first) { p[x].push_back(v[i].second); } else { x++; p[x].push_back(v[i].second); } } vector<pair<int, int>> o; for (int i = 0; i < m; i++) { if (p[i].size() == 1) { o.push_back(make_pair(r[i], 0)); } else { bool f = true; int x = p[i][1] - p[i][0]; for (int j = 2; j < p[i].size(); j++) { if ((p[i][j - 1] + x) != p[i][j]) { f = false; break; } } if (f == true) { o.push_back(make_pair(r[i], x)); } } } cout << o.size() << endl; for (int i = 0; i < o.size(); i++) { cout << o[i].first << << o[i].second << endl; } } } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( -O3 ) int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int a1, a2, k1, k2, n; cin >> a1 >> a2 >> k1 >> k2 >> n; if (k1 > k2) { swap(a1, a2); swap(k1, k2); } if (n <= a1 * (k1 - 1) + a2 * (k2 - 1)) { cout << 0 ; } else { cout << n - (a1 * (k1 - 1) + a2 * (k2 - 1)) << ; } long long int ans = n / k1; n = n % k1; if (ans > a1) { n += (ans - a1) * k1; ans = a1; } ans += n / k2; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 5; vector<vector<pair<long long, long long> > > dis(maxn); long long flag[maxn]; long long c1, c2; bool ok; void dfs(long long index, long long p) { flag[index] = p; for (long long i = 0; i < dis[index].size(); i++) { if (flag[dis[index][i].first] != -1 && flag[dis[index][i].first] != (dis[index][i].second == p)) ok = false; if (flag[dis[index][i].first] == -1) { if (dis[index][i].second == p) { c1++; } else c2++; dfs(dis[index][i].first, dis[index][i].second == p); } } } signed main() { long long t; cin >> t; memset(flag, -1, sizeof(flag)); while (t--) { long long n, m; cin >> n >> m; long long x, y; string s; while (m--) { cin >> x >> y >> s; if (s[0] == c ) { dis[x].push_back({y, 1}); dis[y].push_back({x, 1}); } else { dis[x].push_back({y, 0}); dis[y].push_back({x, 0}); } } long long ans = 0; ok = true; for (long long i = 1; i <= n; i++) { if (flag[i] == -1) { c1 = 1, c2 = 0; dfs(i, 1); ans += max(c1, c2); } } for (long long i = 1; i <= n; i++) { dis[i].clear(); flag[i] = -1; } if (!ok) cout << -1 << endl; else cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, start, x; pair<int, int> ask(int v) { printf( ? %d n , v); fflush(stdout); int value, nxt; scanf( %d %d , &value, &nxt); return pair<int, int>(value, nxt); } const int RANDOM_Q = 1000; int main() { srand(time(NULL)); scanf( %d %d %d , &n, &start, &x); vector<int> v; for (int i = int(1); i < int(n + 1); i++) { v.push_back(i); } random_shuffle(v.begin(), v.end()); vector<int> randoms; for (int i = int(0); i < int(min(RANDOM_Q, (int)v.size())); i++) { randoms.push_back(v[i]); } int ans = (int)2e9; int possible_start = start, start_val = -1; for (auto &each : randoms) { pair<int, int> p = ask(each); if (p.first >= x && p.first < ans) { ans = p.first; } else if (p.first < x && p.first > start_val) { possible_start = p.second; start_val = p.first; } } int cur = possible_start; for (int i = 0; cur != -1 && i < 1999 - RANDOM_Q; i++) { pair<int, int> p = ask(cur); if (p.first >= x) { ans = p.first; break; } cur = p.second; } printf( ! %d n , ans == (int)2e9 ? -1 : ans); fflush(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; int n, p[N]; void solve(int n) { if ((n & 1) && (n - 1) % 4) { puts( -1 ); return; } if (!(n & 1) && n % 4) { puts( -1 ); return; } if (n & 1) p[(n + 1) >> 1] = (n + 1) >> 1; for (int i = (1); i < ((n >> 1) + 1); ++i) if (!p[i]) { p[i] = i + 1; p[i + 1] = n + 1 - i; p[n + 1 - i] = n - i; p[n - i] = i; } for (int i = (1); i < (n + 1); ++i) printf( %d%c , p[i], n [i == n]); } int main() { scanf( %d , &n); solve(n); return 0; } |
module wasca (
abus_slave_0_abus_address,
abus_slave_0_abus_chipselect,
abus_slave_0_abus_read,
abus_slave_0_abus_write,
abus_slave_0_abus_waitrequest,
abus_slave_0_abus_interrupt,
abus_slave_0_abus_addressdata,
abus_slave_0_abus_direction,
abus_slave_0_abus_muxing,
abus_slave_0_abus_disableout,
abus_slave_0_conduit_saturn_reset_saturn_reset,
altpll_0_areset_conduit_export,
altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export,
clk_clk,
external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n,
leds_conn_export,
sdram_clkout_clk,
switches_conn_export,
uart_0_external_connection_rxd,
uart_0_external_connection_txd);
input [9:0] abus_slave_0_abus_address;
input [2:0] abus_slave_0_abus_chipselect;
input abus_slave_0_abus_read;
input [1:0] abus_slave_0_abus_write;
output abus_slave_0_abus_waitrequest;
output abus_slave_0_abus_interrupt;
inout [15:0] abus_slave_0_abus_addressdata;
output abus_slave_0_abus_direction;
output [1:0] abus_slave_0_abus_muxing;
output abus_slave_0_abus_disableout;
input abus_slave_0_conduit_saturn_reset_saturn_reset;
input altpll_0_areset_conduit_export;
output altpll_0_locked_conduit_export;
output altpll_0_phasedone_conduit_export;
input clk_clk;
output [12:0] external_sdram_controller_wire_addr;
output [1:0] external_sdram_controller_wire_ba;
output external_sdram_controller_wire_cas_n;
output external_sdram_controller_wire_cke;
output external_sdram_controller_wire_cs_n;
inout [15:0] external_sdram_controller_wire_dq;
output [1:0] external_sdram_controller_wire_dqm;
output external_sdram_controller_wire_ras_n;
output external_sdram_controller_wire_we_n;
output [3:0] leds_conn_export;
output sdram_clkout_clk;
input [2:0] switches_conn_export;
input uart_0_external_connection_rxd;
output uart_0_external_connection_txd;
endmodule
|
// /**
// * This Verilog HDL file is used for simulation and synthesis in
// * the chaining DMA design example. It could be used by the software
// * application (Root Port) to retrieve the DMA Performance counter values
// * and performs single DWORD read and write to the Endpoint memory by
// * bypassing the DMA engines.
// */
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ecrc_gen_calc #( parameter AVALON_ST_128 = 0) (clk, rstn, crc_data, crc_valid, crc_empty, crc_eop, crc_sop,
ecrc, crc_ack);
input clk;
input rstn;
input[127:0] crc_data;
input crc_valid;
input[3:0] crc_empty;
input crc_eop;
input crc_sop;
output[31:0] ecrc;
input crc_ack;
wire[31:0] crc_int;
wire crc_valid_int;
wire open_empty;
wire open_full;
generate begin
if (AVALON_ST_128==1) begin
altpcierd_tx_ecrc_128 tx_ecrc_128 (
.clk(clk), .reset_n(rstn), .data(crc_data), .datavalid(crc_valid),
.empty(crc_empty), .endofpacket(crc_eop), .startofpacket(crc_sop),
.checksum(crc_int), .crcvalid(crc_valid_int)
);
end
end
endgenerate
generate begin
if (AVALON_ST_128==0) begin
altpcierd_tx_ecrc_64 tx_ecrc_64 (
.clk(clk), .reset_n(rstn), .data(crc_data[127:64]), .datavalid(crc_valid),
.empty(crc_empty[2:0]), .endofpacket(crc_eop), .startofpacket(crc_sop),
.checksum(crc_int), .crcvalid(crc_valid_int)
);
end
end
endgenerate
altpcierd_tx_ecrc_fifo tx_ecrc_fifo (
.aclr (~rstn),
.clock (clk),
.data (crc_int),
.rdreq (crc_ack),
.wrreq (crc_valid_int),
.empty (open_empty),
.full (open_full),
.q (ecrc)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline int Chkmax(T &a, T b) { return a < b ? a = b, 1 : 0; } template <typename T> inline int Chkmin(T &a, T b) { return a > b ? a = b, 1 : 0; } template <typename T> inline T read() { T sum = 0, fl = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) fl = -1; for (; isdigit(ch); ch = getchar()) sum = (sum << 3) + (sum << 1) + ch - 0 ; return sum * fl; } inline void proc_status() { ifstream t( /proc/self/status ); cerr << string(istreambuf_iterator<char>(t), istreambuf_iterator<char>()) << endl; } const int Maxn = 100000 + 100; int N, Stack[Maxn], top; pair<long long, long long> A[Maxn]; inline double get_slope(pair<long long, long long> a, pair<long long, long long> b) { return (double)(b.second - a.second) / (b.first - a.first); } inline void Solve() { sort(A + 1, A + N + 1); int tot = 0; A[N + 1].first = 1e7; for (int i = 1; i <= N; ++i) if (A[i].first != A[i + 1].first) A[++tot] = A[i]; for (int i = 1; i <= tot; ++i) { while (top >= 2 && get_slope(A[i], A[Stack[top]]) >= get_slope(A[i], A[Stack[top - 1]])) --top; Stack[++top] = i; } cout << top - 1 << endl; } inline void Input() { N = read<int>(); for (int i = 1; i <= N; ++i) A[i].first = read<long long>(), A[i].second = read<long long>() - A[i].first * A[i].first; } int main() { Input(); Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; void sove() {} int main() { int n; cin >> n; int nums[n]; for (int i = 0; i < n; ++i) { cin >> nums[i]; } for (int i = 0; i < n / 2; i += 2) { int temp = nums[i]; nums[i] = nums[n - i - 1]; nums[n - i - 1] = temp; } for (int num : nums) { cout << num << ; } } |
#include <bits/stdc++.h> using namespace std; namespace Dango { const int MAXN = 200005, INF = 0x3f3f3f3f; struct Edge { int from, to, dis, id; bool operator<(const Edge b) const { return dis < b.dis; } } e[MAXN]; struct tree { int l, r, data; bool tag; } t[MAXN << 2]; int n, m; int head[MAXN], to[MAXN * 2], dis[MAXN * 2], nxt[MAXN * 2]; int fa[MAXN]; int ans[MAXN]; int size[MAXN], maxson[MAXN], belong[MAXN], f[MAXN]; int id[MAXN], link[MAXN], tmp[MAXN], d[MAXN]; bool flag[MAXN]; int read() { int x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) { f |= (ch == - ); ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return f ? -x : x; } int ffind(int a) { return f[a] == a ? a : f[a] = ffind(f[a]); } void add(int u, int v, int w) { static int cnt; cnt++; to[cnt] = v; dis[cnt] = w; nxt[cnt] = head[u]; head[u] = cnt; } void dfs1(int u, int f) { size[u] = 1; fa[u] = f; d[u] = d[f] + 1; for (int i = head[u]; i; i = nxt[i]) { int v = to[i]; if (v == f) continue; tmp[v] = dis[i]; dfs1(v, u); size[u] += size[v]; if (size[v] > size[maxson[u]]) maxson[u] = v; } } void dfs2(int u, int f, int anc) { static int cnt; id[u] = ++cnt; link[cnt] = u; belong[u] = anc; if (maxson[u]) dfs2(maxson[u], u, anc); for (int i = head[u]; i; i = nxt[i]) { int v = to[i]; if (v == f || v == maxson[u]) continue; dfs2(v, u, v); } } void build(int a, int l, int r) { t[a].l = l; t[a].r = r; t[a].tag = false; if (l == r) { t[a].data = tmp[link[l]]; return; } int mid = (l + r) >> 1; build(a << 1, l, mid); build(a << 1 | 1, mid + 1, r); t[a].data = max(t[a << 1].data, t[a << 1 | 1].data); } void pushdown(int a) { int l = a << 1, r = a << 1 | 1; t[a].tag = false; t[l].data = min(t[l].data, t[a].data); t[r].data = min(t[r].data, t[a].data); t[l].tag = t[r].tag = true; } void update(int a, int l, int r, int data) { if (t[a].l >= l && t[a].r <= r) { t[a].data = min(t[a].data, data); t[a].tag = true; return; } if (t[a].tag) pushdown(a); int mid = (t[a].l + t[a].r) >> 1; if (l <= mid) update(a << 1, l, r, data); if (r > mid) update(a << 1 | 1, l, r, data); } int querymax(int a, int l, int r) { if (t[a].l >= l && t[a].r <= r) return t[a].data; if (t[a].tag) pushdown(a); int mid = (t[a].l + t[a].r) >> 1, res = 0; if (l <= mid) res = max(res, querymax(a << 1, l, r)); if (r > mid) res = max(res, querymax(a << 1 | 1, l, r)); return res; } int querymin(int a, int l, int r) { if (t[a].l >= l && t[a].r <= r) return t[a].data; if (t[a].tag) pushdown(a); int mid = (t[a].l + t[a].r) >> 1, res = INF; if (l <= mid) res = min(res, querymin(a << 1, l, r)); if (r > mid) res = min(res, querymin(a << 1 | 1, l, r)); return res; } int solve(int u, int v) { int res = 0; while (belong[u] != belong[v]) { if (d[belong[u]] < d[belong[v]]) swap(u, v); res = max(res, querymax(1, id[belong[u]], id[u])); u = fa[belong[u]]; } if (u != v) { if (d[u] > d[v]) swap(u, v); res = max(res, querymax(1, id[u] + 1, id[v])); } return res - 1; } void fix(int u, int v, int w) { while (belong[u] != belong[v]) { if (d[belong[u]] < d[belong[v]]) swap(u, v); update(1, id[belong[u]], id[u], w); u = fa[belong[u]]; } if (u != v) { if (d[u] > d[v]) swap(u, v); update(1, id[u] + 1, id[v], w); } } int solve2(int u, int v) { int res = INF; while (belong[u] != belong[v]) { if (d[belong[u]] < d[belong[v]]) swap(u, v); res = min(res, querymin(1, id[belong[u]], id[u])); u = fa[belong[u]]; } if (u != v) { if (d[u] > d[v]) swap(u, v); res = min(res, querymin(1, id[u] + 1, id[v])); } if (res == INF) res = 0; return res - 1; } int work() { n = read(); m = read(); for (int i = 1; i <= n; i++) f[i] = i; for (int i = 1; i <= m; i++) { e[i].from = read(); e[i].to = read(); e[i].dis = read(); e[i].id = i; } sort(e + 1, e + m + 1); for (int i = 1; i <= m; i++) { int u = e[i].from, v = e[i].to, w = e[i].dis; int a = ffind(u), b = ffind(v); if (a != b) { f[a] = b; add(u, v, w); add(v, u, w); } else flag[i] = true; } dfs1(1, 0); dfs2(1, 0, 1); build(1, 1, n); for (int i = 1; i <= m; i++) { if (!flag[i]) continue; ans[e[i].id] = solve(e[i].from, e[i].to); } memset(tmp, INF, sizeof(tmp)); build(1, 1, n); for (int i = 1; i <= m; i++) { if (!flag[i]) continue; fix(e[i].from, e[i].to, e[i].dis); } for (int i = 1; i <= m; i++) { if (flag[i]) continue; ans[e[i].id] = solve2(e[i].from, e[i].to); } for (int i = 1; i <= m; i++) printf( %d , ans[i]); return 0; } } // namespace Dango int main() { return Dango::work(); } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM pipeline bridge
//
// Optionally registers Avalon-MM command and response signals
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter RESPONSE_WIDTH = 2,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input clk,
input reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
output [RESPONSE_WIDTH-1:0] s0_response,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
input [RESPONSE_WIDTH-1:0] m0_response,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
// --------------------------------------
// Registers & signals
// --------------------------------------
reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
reg [DATA_WIDTH-1:0] cmd_writedata;
reg [HDL_ADDR_WIDTH-1:0] cmd_address;
reg cmd_write;
reg cmd_read;
reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
wire cmd_waitrequest;
reg cmd_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
reg [DATA_WIDTH-1:0] wr_writedata;
reg [HDL_ADDR_WIDTH-1:0] wr_address;
reg wr_write;
reg wr_read;
reg [BYTEEN_WIDTH-1:0] wr_byteenable;
reg wr_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
reg [DATA_WIDTH-1:0] wr_reg_writedata;
reg [HDL_ADDR_WIDTH-1:0] wr_reg_address;
reg wr_reg_write;
reg wr_reg_read;
reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
reg wr_reg_waitrequest;
reg wr_reg_debugaccess;
reg use_reg;
wire wait_rise;
reg [DATA_WIDTH-1:0] rsp_readdata;
reg rsp_readdatavalid;
reg [RESPONSE_WIDTH-1:0] rsp_response;
// --------------------------------------
// Command pipeline
//
// Registers all command signals, including waitrequest
// --------------------------------------
generate if (PIPELINE_COMMAND == 1) begin
// --------------------------------------
// Waitrequest Pipeline Stage
//
// Output waitrequest is delayed by one cycle, which means
// that a master will see waitrequest assertions one cycle
// too late.
//
// Solution: buffer the command when waitrequest transitions
// from low->high. As an optimization, we can safely assume
// waitrequest is low by default because downstream logic
// in the bridge ensures this.
//
// Note: this implementation buffers idle cycles should
// waitrequest transition on such cycles. This is a potential
// cause for throughput loss, but ye olde pipeline bridge did
// the same for years and no one complained. Not buffering idle
// cycles costs logic on the waitrequest path.
// --------------------------------------
assign s0_waitrequest = wr_reg_waitrequest;
assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
always @(posedge clk, posedge reset) begin
if (reset) begin
wr_reg_waitrequest <= 1'b1;
// --------------------------------------
// Bit of trickiness here, deserving of a long comment.
//
// On the first cycle after reset, the pass-through
// must not be used or downstream logic may sample
// the same command twice because of the delay in
// transmitting a falling waitrequest.
//
// Using the registered command works on the condition
// that downstream logic deasserts waitrequest
// immediately after reset, which is true of the
// next stage in this bridge.
// --------------------------------------
use_reg <= 1'b1;
wr_reg_burstcount <= 1'b1;
wr_reg_writedata <= 0;
wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}};
wr_reg_address <= 0;
wr_reg_write <= 1'b0;
wr_reg_read <= 1'b0;
wr_reg_debugaccess <= 1'b0;
end else begin
wr_reg_waitrequest <= cmd_waitrequest;
if (wait_rise) begin
wr_reg_writedata <= s0_writedata;
wr_reg_byteenable <= s0_byteenable;
wr_reg_address <= s0_address;
wr_reg_write <= s0_write;
wr_reg_read <= s0_read;
wr_reg_burstcount <= s0_burstcount;
wr_reg_debugaccess <= s0_debugaccess;
end
// stop using the buffer when waitrequest is low
if (~cmd_waitrequest)
use_reg <= 1'b0;
else if (wait_rise) begin
use_reg <= 1'b1;
end
end
end
always @* begin
wr_burstcount = s0_burstcount;
wr_writedata = s0_writedata;
wr_address = s0_address;
wr_write = s0_write;
wr_read = s0_read;
wr_byteenable = s0_byteenable;
wr_debugaccess = s0_debugaccess;
if (use_reg) begin
wr_burstcount = wr_reg_burstcount;
wr_writedata = wr_reg_writedata;
wr_address = wr_reg_address;
wr_write = wr_reg_write;
wr_read = wr_reg_read;
wr_byteenable = wr_reg_byteenable;
wr_debugaccess = wr_reg_debugaccess;
end
end
// --------------------------------------
// Master-Slave Signal Pipeline Stage
//
// One notable detail is that cmd_waitrequest is deasserted
// when this stage is idle. This allows us to make logic
// optimizations in the waitrequest pipeline stage.
//
// Also note that cmd_waitrequest is deasserted during reset,
// which is not spec-compliant, but is ok for an internal
// signal.
// --------------------------------------
wire no_command;
assign no_command = ~(cmd_read || cmd_write);
assign cmd_waitrequest = m0_waitrequest & ~no_command;
always @(posedge clk, posedge reset) begin
if (reset) begin
cmd_burstcount <= 1'b1;
cmd_writedata <= 0;
cmd_byteenable <= {BYTEEN_WIDTH{1'b1}};
cmd_address <= 0;
cmd_write <= 1'b0;
cmd_read <= 1'b0;
cmd_debugaccess <= 1'b0;
end
else begin
if (~cmd_waitrequest) begin
cmd_writedata <= wr_writedata;
cmd_byteenable <= wr_byteenable;
cmd_address <= wr_address;
cmd_write <= wr_write;
cmd_read <= wr_read;
cmd_burstcount <= wr_burstcount;
cmd_debugaccess <= wr_debugaccess;
end
end
end
end // conditional command pipeline
else begin
assign s0_waitrequest = m0_waitrequest;
always @* begin
cmd_burstcount = s0_burstcount;
cmd_writedata = s0_writedata;
cmd_address = s0_address;
cmd_write = s0_write;
cmd_read = s0_read;
cmd_byteenable = s0_byteenable;
cmd_debugaccess = s0_debugaccess;
end
end
endgenerate
assign m0_burstcount = cmd_burstcount;
assign m0_writedata = cmd_writedata;
assign m0_address = cmd_address;
assign m0_write = cmd_write;
assign m0_read = cmd_read;
assign m0_byteenable = cmd_byteenable;
assign m0_debugaccess = cmd_debugaccess;
// --------------------------------------
// Response pipeline
//
// Registers all response signals
// --------------------------------------
generate if (PIPELINE_RESPONSE == 1) begin
always @(posedge clk, posedge reset) begin
if (reset) begin
rsp_readdatavalid <= 1'b0;
rsp_readdata <= 0;
rsp_response <= 0;
end
else begin
rsp_readdatavalid <= m0_readdatavalid;
rsp_readdata <= m0_readdata;
rsp_response <= m0_response;
end
end
end // conditional response pipeline
else begin
always @* begin
rsp_readdatavalid = m0_readdatavalid;
rsp_readdata = m0_readdata;
rsp_response = m0_response;
end
end
endgenerate
assign s0_readdatavalid = rsp_readdatavalid;
assign s0_readdata = rsp_readdata;
assign s0_response = rsp_response;
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream broadcaster
*/
module axis_broadcast #
(
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
input wire [M_COUNT-1:0] m_axis_tready,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser
);
parameter CL_M_COUNT = $clog2(M_COUNT);
// datapath registers
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// // datapath control
reg store_axis_input_to_output;
reg store_axis_input_to_temp;
reg store_axis_temp_to_output;
assign s_axis_tready = s_axis_tready_reg;
assign m_axis_tdata = {M_COUNT{m_axis_tdata_reg}};
assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? {M_COUNT{m_axis_tlast_reg}} : {M_COUNT{1'b1}};
assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (s_axis_tready_reg) begin
// input is ready
if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || !m_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = {M_COUNT{s_axis_tvalid}};
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = s_axis_tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
// input is not ready, but output is ready
m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= {M_COUNT{1'b0}};
temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
end else begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis_tdata;
m_axis_tkeep_reg <= s_axis_tkeep;
m_axis_tlast_reg <= s_axis_tlast;
m_axis_tid_reg <= s_axis_tid;
m_axis_tdest_reg <= s_axis_tdest;
m_axis_tuser_reg <= s_axis_tuser;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_m_axis_tdata_reg <= s_axis_tdata;
temp_m_axis_tkeep_reg <= s_axis_tkeep;
temp_m_axis_tlast_reg <= s_axis_tlast;
temp_m_axis_tid_reg <= s_axis_tid;
temp_m_axis_tdest_reg <= s_axis_tdest;
temp_m_axis_tuser_reg <= s_axis_tuser;
end
end
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; vector<long long> blame(1002, 0); vector<bool> visited(1002, false); long long dfs(long long u) { if (visited[u]) return u; visited[u] = true; return dfs(blame[u]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; for (long long i = 1; i <= n; i++) { cin >> blame[i]; } for (long long i = 1; i <= n; i++) { cout << dfs(i) << ; fill(visited.begin(), visited.end(), false); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T scani(T &n) { n = 0; bool negative = false; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) negative = true; c = getchar(); } while (c >= 0 && c <= 9 ) { n = n * 10 + c - 48; c = getchar(); } if (negative) n = ~(n - 1); return n; } template <typename T> void write(T n, int type = true) { if (n < 0) { putchar( - ); n = -n; } if (!n) { putchar( 0 ); if (type == 32) putchar( ); else if (type) putchar( n ); return; } char buff[22]; int len = 0; while (n) buff[len++] = n % 10 + 48, n /= 10; for (int i = len - 1; i >= 0; i--) putchar(buff[i]); if (type == 32) putchar( ); else if (type) putchar( n ); } int scans(char *a) { int i = 0; char c = 0; while (c < 33) c = getchar(); while (c > 33) { a[i++] = c; c = getchar(); } a[i] = 0; return i; } const int N = 100005; int main() { int n, k; scani(n), scani(k); int ans; ans = (2 * n + k - 1) / k + (5 * n + k - 1) / k + (8 * n + k - 1) / k; write(ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300005; int n, k, i, a, b, da, db, u, v, head[N], Next[N * 2], adj[N * 2], j, dp[N], ans, dd, t; void Push(int u, int v) { Next[++k] = head[u]; head[u] = k; adj[k] = v; } void dfs(int i, int fa) { int j, mxx = 0; dp[i] = 0; for (j = head[i]; j; j = Next[j]) if (adj[j] != fa) { dfs(adj[j], i); if (dp[i] < dp[adj[j]] + 1) { mxx = max(mxx, dp[i]); dp[i] = dp[adj[j]] + 1; } else mxx = max(mxx, dp[adj[j]] + 1); } ans = max(ans, mxx + dp[i]); } void dis(int i, int fa, int d) { int j; for (j = head[i]; j; j = Next[j]) if (adj[j] != fa) dis(adj[j], i, d + 1); if (i == b) dd = d; } int main() { scanf( %d , &t); while (t--) { scanf( %d %d %d %d %d , &n, &a, &b, &da, &db); for (i = 1; i <= n; ++i) head[i] = 0; k = 0; for (i = 1; i < n; ++i) { scanf( %d %d , &u, &v); Push(u, v); Push(v, u); } if (db <= da * 2) { puts( Alice ); continue; } ans = 0; dfs(1, 0); dis(a, 0, 0); if (dd <= da || ans <= da * 2) puts( Alice ); else puts( Bob ); } } |
#include <bits/stdc++.h> using namespace std; int v1, v2, v3, vm; inline long long readll() { int sign = 1; char c; for (c = getchar(); !isdigit(c); c = getchar()) if (c == - ) sign = -sign; long long res = c - 0 ; for (c = getchar(); isdigit(c); c = getchar()) res = res * 10 + c - 0 ; return sign * res; } void writell(long long x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) writell(x / 10); putchar(x % 10 + 0 ); } void inp() { cin >> v1 >> v2 >> v3 >> vm; } void out() { if (vm < v2 && vm <= 2 * v3 && v3 <= 2 * vm) { writell(v1 * 2); putchar( n ); writell(v2 * 2); putchar( n ); writell(min(v3 * 2, vm * 2)); } else { putchar( - ); putchar( 1 ); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); inp(); out(); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_66x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_66x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [65:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [65:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire [65:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [6:0] usedw = sub_wire1[6:0];
wire empty = sub_wire2;
wire [65:0] q = sub_wire3[65:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.lpm_width = 66,
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_widthu = 7,
scfifo_component.intended_device_family = "Stratix",
scfifo_component.almost_full_value = 96,
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "66"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "96"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "66"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "96"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 66 0 INPUT NODEFVAL data[65..0]
// Retrieval info: USED_PORT: q 0 0 66 0 OUTPUT NODEFVAL q[65..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 66 0 data 0 0 66 0
// Retrieval info: CONNECT: q 0 0 66 0 @q 0 0 66 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_66x128_wave*.jpg FALSE
|
/*
* Copyright (c) 2001 Uwe Bonnes
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`define ADC_DATA_OFFSET 5
`define ADC_CHANELS 8*48
//`define ADC_CHANELS 348
module mymod (out1,out2,state,reset);
input [8:0] state;
input reset;
output out1,out2;
assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0;
assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset);
endmodule // mymod
module t;
reg [8:0] state;
reg reset;
wire out1,out2;
mymod m1 (out1,out2,state,reset);
initial
begin
//$timeformat(-9,0,"ns",5);
$display(" TIME:state:out1:out2");
$monitor("%7t:%5d:%3d:%3d",$time,state,out1,out2);
state =0;
reset = 0;
#10
reset=1;
#20
reset=0;
#5110
$finish;
end
always
begin
#10
if (reset)
state = 0;
else
state=state+1;
end
endmodule // t
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110; const int MOD = 1e9 + 7; long long n, k, dp[MAXN][MAXN][MAXN], local[MAXN][MAXN]; vector<int> adj[MAXN]; void add(long long& v, long long u) { v = (v + u) % MOD; } void dfs(int v, int par = -1) { dp[v][1][0] = dp[v][0][1] = 1; for (auto i : adj[v]) { if (i == par) continue; dfs(i, v); for (int w = 0; w < 23; w++) for (int j = 0; j < 50; j++) { local[w][j] = dp[v][w][j]; dp[v][w][j] = 0; } for (int a = 0; a <= (k + 1); a++) for (int b = 0; b <= (2 * k + 1); b++) for (int c = 0; c <= (k + 1); c++) for (int d = 0; d <= (2 * k + 1); d++) { int locala = 0; if (!d) locala = b; if (!b && d) locala = d + 1; if (b && d) locala = min(b, d + 1); int localb = a; if (localb && locala) { if ((localb - 1 + locala - 1) <= k) localb = 0; } int localc = c; if (localc) localc++; if (localc && locala) { if ((locala - 1 + localc - 1) <= k) localc = 0; } int locald = 0; if (!localc) locald = localb; if (!localb && localc) locald = localc; if (localb && localc) locald = max(localc, localb); if (locald <= (k + 1) && locala <= (2 * k + 3)) add(dp[v][locald][locala], local[a][b] * dp[i][c][d] % MOD); } } } int main() { ios::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1); long long answer = 0; for (int i = 0; i <= (2 * k + 3); i++) answer = (answer + dp[1][0][i]) % MOD; cout << answer << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; char s[maxn]; int vis[maxn]; pair<char, int> sta[maxn]; int main() { scanf( %s , s); int o = -1; for (int i = 0; s[i]; i++) { if (s[i] == 0 && o >= 0 && sta[o].first == 1 ) { vis[sta[o].second] = 1; o--; } else sta[++o] = make_pair(s[i], i); } for (int i = 0; s[i]; i++) printf( %d , vis[i]); } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Validation of assign construct
//
// D: Create a 32 bit vector and assign succesive values to
// D: the Right hand side expression. Verify the result is
// D: correct.
//
module main ();
wire [31:0] result;
reg [31:0] a,b ;
assign result = a | b;
initial // Excitation block
begin
a = 0;
b = 0;
# 5;
a = 32'haaaaaaaa ;
# 5;
b = 32'h55555555 ;
# 5 ;
end
initial // Validation block
begin
# 1;
if(result != 32'h0)
begin
$display("FAILED - result not initialized\n");
$finish ;
end
# 5;
if(result != 32'haaaaaaaa)
begin
$display("FAILED - result not updated\n");
$finish ;
end
# 5;
if(result != 32'hffffffff)
begin
$display("FAILED - result not updated\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; int ans = -1; for (int i = 0; i < s.size(); i++) { if (s[i] == R ) { ans = i + 1; break; } } if (ans == -1) { cout << s.size() + 1 << endl; continue; } else { int last = ans - 1; for (int i = ans; i < s.size(); i++) { if (s[i] == R ) { ans = max(i - last, ans); last = i; } } ans = max(ans, int(s.size()) - last); } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int tc, cs = 1; scanf( %lld , &tc); while (tc--) { long long a, b, c, d; scanf( %lld %lld , &a, &b); scanf( %lld %lld , &c, &d); if ((b - a) % (c + d) == 0) cout << (b - a) / (c + d) << endl; else cout << -1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); multiset<int> s; s.insert(0); int q; cin >> q; while (q--) { char c; int x; cin >> c >> x; if (c == + ) { s.insert(x); } else if (c == - ) { s.erase(s.find(x)); } else { int cur = 0; for (int i = 30; i >= 0; i--) { if (((1 << i) & x) == 0) { cur |= (1 << i); auto it = s.lower_bound(cur); if (it == s.end() || (cur >> i) != (*it >> i)) cur ^= (1 << i); } else { auto it = s.lower_bound(cur); if (it == s.end() || (cur >> i) != (*it >> i)) cur |= (1 << i); } } cout << (x ^ cur) << n ; } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
//Several simulators don't support this.
//typedef struct pack2; // Forward declaration
typedef struct packed { // [3:0]
bit b3;
bit b2;
bit b1;
bit b0;
} b4_t;
typedef struct packed { // [3:0]
b4_t x1;
b4_t x0;
} b4x2_t;
typedef union packed { // [3:0]
bit [3:0] quad0;
b4_t quad1;
} q4_t;
typedef struct packed { // [5:0]
bit msb;
q4_t four;
bit lsb;
} pack2_t;
typedef union packed { // [5:0]
pack2_t pack2;
bit [6:1] pvec;
// Vector not allowed in packed structure, per spec:
// bit vec[6];
// bit vec2d[2][3];
} pack3_t;
const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1};
// Cast to a pattern - note bits are tagged out of order
const b4_t b4_const_b = b4_t'{ b1 : 1'b0, b0 : 1'b1, b3 : 1'b1, b2 : 1'b0 };
wire b4_t b4_wire;
assign b4_wire = '{1'b1, 1'b0, 1'b1, 1'b0};
pack2_t arr[2];
initial begin
pack3_t tsu;
tsu = 6'b110110;
// 543210
if (tsu!=6'b110110) $stop;
if (tsu[5:4]!=2'b11) $stop;
if (tsu[5:4] == tsu[1:0]) $stop; // Not a good extraction test if LSB subtraction doesn't matter
if (tsu.pvec!=6'b110110) $stop;
if (tsu.pvec[6:5]!=2'b11) $stop;
if (tsu.pack2[5:1] != 5'b11011) $stop;
if (tsu.pack2.msb != 1'b1) $stop;
if (tsu.pack2.lsb != 1'b0) $stop;
if (tsu.pack2.four.quad0 != 4'b1011) $stop;
if (tsu.pack2.four.quad1.b0 != 1'b1) $stop;
if (tsu.pack2.four.quad1.b1 != 1'b1) $stop;
if (tsu.pack2.four.quad1.b2 != 1'b0) $stop;
if (tsu.pack2.four.quad1.b3 != 1'b1) $stop;
//
arr[0] = 6'b101010;
arr[1] = 6'b010101;
if (arr[0].four !== 4'b0101) $stop;
if (arr[1].four !== 4'b1010) $stop;
//
// Initialization
begin
b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0};
if (q != 4'b1100) $stop;
end
begin
b4_t q = '{3{1'b1}, 1'b0};
if (q != 4'b1110) $stop;
end
begin
b4_t q = '{4{1'b1}}; // Repeats the {}
if (q != 4'b1111) $stop;
end
begin
b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}};
if (m != 8'b10011011) $stop;
end
begin
b4_t q = '{default:1'b1};
if (q != 4'b1111) $stop;
end
begin
b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0};
if (q != 4'b1101) $stop;
end
begin
b4_t q = '{b2:1'b0, default:1'b1};
if (q != 4'b1011) $stop;
end
if (b4_const_a != 4'b1001) $stop;
if (b4_const_b != 4'b1001) $stop;
if (b4_wire != 4'b1010) $stop;
if (pat(4'b1100, 4'b1100)) $stop;
if (pat('{1'b1, 1'b0, 1'b1, 1'b1}, 4'b1011)) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
function pat(b4_t in, logic [3:0] cmp);
if (in !== cmp) $stop;
pat = 1'b0;
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INV_PP_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n; int a[109]; int ans; int s; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); s += a[i]; ans = max(ans, a[i]); } for (;; ans++) { if (ans * n - s > s) { printf( %d , ans); return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; void __print(long long x) { cerr << x; } void __print(long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { long long f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } long long Power(long long a, long long n, long long mod) { long long res = 1; while (n) { if (n % 2 != 0) { res = ((res % mod) * (a % mod)) % mod; n--; } else { a = ((a % mod) * (a % mod)) % mod; n /= 2; } } return res; } void AllPossibilities(vector<long long> &arr, vector<long long> &answers, long long index, long long sum) { if (index == arr.size()) { answers.push_back(sum); return; } AllPossibilities(arr, answers, index + 1, sum + arr[index]); AllPossibilities(arr, answers, index + 1, sum); } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long getSum(long long n) { long long sum = 0; while (n != 0) { sum = sum + n % 10; n = n / 10; } return sum; } long long myceil(long long n, long long x) { long long y; if (n % x == 0) { y = n / x; return y; } else { y = n / x + 1; return y; } } long long md = 1000000007; vector<long long> fact, inv; void inverse(long long n) { if (n >= inv.size()) { long long size = inv.size(); size = size == 0 ? 1 : size; inv.resize(n + 1); inv[0] = 1; for (long long i = size; i <= n; i++) inv[i] = Power(fact[i], md - 2, md); } } void factorial(long long n) { if (n >= fact.size()) { long long size = fact.size(); size = size == 0 ? 1 : size; fact.resize(n + 1); fact[0] = 1; for (long long i = size; i <= n; i++) fact[i] = (fact[i - 1] * i) % md; } } long long ncr(long long n, long long r) { return (((fact[n] * inv[r]) % md) * inv[n - r]) % md; } long long primes[1300000]; void Sieve() { bool IsPrime[1300000]; memset(IsPrime, true, sizeof(IsPrime)); for (long long p = 2; p * p < 1300000; p++) { if (IsPrime[p] == true) { for (long long i = p * p; i < 1300000; i += p) IsPrime[i] = false; } } long long index = 0; for (long long p = 2; p < 1300000; p++) if (IsPrime[p]) { primes[index] = p; index++; } } void q1(); void q2(); void q3(); void q4(); void q5(); void pr(vector<vector<long long>> v); int32_t main() { q1(); return 0; } void q1() { long long n; cin >> n; long long sum = 0; for (long long i = 0; i < n; i++) { long long x; cin >> x; sum += x; } long long resp = 0; for (long long i = 1; i <= 5; i++) if ((i + sum) % (n + 1) != 1) resp++; cout << resp; } void pr(vector<vector<long long>> v) {} void q2() { long long n; cin >> n; long long arr[n]; for (long long i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); bool set = true; for (long long i = 0; i < n - 1; i++) { if (arr[i] == arr[i + 1]) { set = false; break; } } if (set) cout << NO << n ; else { cout << YES << n ; } } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const long long mod = 1e9 + 7; const long long N = 1e5 + 5, K = 105; const int si = (1 << 20); const long long add = 1e4; const long long M = 100 + 5; const double INFdb = 1e10; int n; vector<int> v[N]; bool check[N]; int legs[N]; void dfs(int u, int par) { if (v[u].size() <= 2) { check[u] = 1; for (int x : v[u]) { if (x != par) { dfs(x, u); } } } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); cin >> n; for (int i = 1; i <= n - 1; ++i) { int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= n; ++i) { if ((int)v[i].size() == 1) dfs(i, 0); } for (int i = 1; i <= n; ++i) { for (int x : v[i]) { if (check[x]) { legs[i] = min(legs[i] + 1, 2); } } } for (int i = 1; i <= n; ++i) { if (!check[i]) { int cnt = 0; for (int x : v[i]) { if (!check[x] && v[x].size() - legs[x] > 1) { ++cnt; } } if (cnt > 2) { return cout << NO , 0; } } } cout << YES ; cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, x, y, k; cin >> n >> m; long long a[n], b[m]; cin >> x >> k >> y; for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < m; i++) cin >> b[i]; vector<long long> adj[n]; long long z[n]; long long ind = 0; for (long long i = 0; i < n; i++) { if (ind >= m) { adj[ind].push_back(a[i]); continue; } if (b[ind] == a[i]) { if (ind - 1 >= 0) z[ind] = max(b[ind], b[ind - 1]); else z[ind] = b[ind]; ind++; } else adj[ind].push_back(a[i]); } if (ind < m - 1) { cout << -1 n ; return 0; } z[ind] = b[m - 1]; ind = 0; long long ans = 0; int f = 0; for (auto &it : adj) { long long itl = it.size(); if (itl == 0) { ind++; continue; } long long mxv = -1; for (auto &it2 : it) mxv = max(mxv, it2); if (itl < k) { if (mxv < z[ind]) ans += itl * y; else { f = 1; break; } } else { if (x >= y * k) { if (mxv < z[ind]) ans += itl * y; else { ans = ans + (itl - k) * y + x; } } else { ans += (itl / k) * x + (itl % k) * y; } } ind++; } if (f == 1) cout << -1 n ; else cout << ans << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_BEHAVIORAL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int ans0[1000001]; int tail = 1; int a[1001]; int n, m; int ans = 0; int main() { int i, j, k; int id; int xx, yy; int temp; scanf( %d , &n); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { scanf( %d , &temp); if (i == j) { a[i] = temp; if (temp == 1) { ans = 1 - ans; } } } } scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d , &id); if (id == 1 || id == 2) { scanf( %d , &temp); ans = 1 - ans; a[temp] = 1 - a[temp]; } else { ans0[tail] = ans; tail++; } } for (i = 1; i <= tail - 1; i++) { printf( %d , ans0[i]); } printf( n ); return 0; } |
`include "bsg_nonsynth_dramsim3.svh"
`ifndef dram_pkg
`define dram_pkg bsg_nonsynth_dramsim3_hbm2_8gb_x128_pkg
`endif
module testbench ();
// clock
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(`dram_pkg::tck_ps))
clkgen
(.o(clk));
// reset
logic reset;
bsg_nonsynth_reset_gen
#(.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(20))
resetgen
(.clk_i(clk)
,.async_reset_o(reset));
// dramsim3
import `dram_pkg::*;
logic [num_channels_p-1:0] dramsim3_v_li;
logic [num_channels_p-1:0] dramsim3_write_not_read_li;
logic [num_channels_p-1:0] [channel_addr_width_p-1:0] dramsim3_ch_addr_li;
logic [num_channels_p-1:0] dramsim3_yumi_lo;
logic [num_channels_p-1:0] dramsim3_data_v_li;
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_li;
logic [num_channels_p-1:0] dramsim3_data_yumi_lo;
logic [num_channels_p-1:0] dramsim3_data_v_lo;
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_lo;
`dram_pkg::dram_ch_addr_s dramsim3_ch_addr_li_cast;
assign dramsim3_ch_addr_li_cast = dramsim3_ch_addr_li[0];
bsg_nonsynth_dramsim3
#(.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.trace_file_p(`BSG_STRINGIFY(`trace_file))
,.debug_p(1))
mem
(.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li)
,.write_not_read_i(dramsim3_write_not_read_li)
,.ch_addr_i(dramsim3_ch_addr_li)
,.yumi_o(dramsim3_yumi_lo)
,.data_v_i(dramsim3_data_v_li)
,.data_i(dramsim3_data_li)
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo)
,.data_v_o(dramsim3_data_v_lo)
,.data_o(dramsim3_data_lo)
,.read_done_ch_addr_o()
,.write_done_o()
,.write_done_ch_addr_o()
);
// trace replay
//
typedef struct packed {
logic write_not_read;
logic [channel_addr_width_p-1:0] ch_addr;
} dramsim3_trace_s;
localparam ring_width_p = $bits(dramsim3_trace_s);
localparam rom_addr_width_p=20;
dramsim3_trace_s [num_channels_p-1:0] tr_data_lo;
logic [num_channels_p-1:0] tr_v_lo;
logic [num_channels_p-1:0] tr_yumi_li;
logic [num_channels_p-1:0][4+ring_width_p-1:0] rom_data;
logic [num_channels_p-1:0][rom_addr_width_p-1:0] rom_addr;
logic [num_channels_p-1:0] ch_done;
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
//,.en_i(i == '0)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo[i])
,.data_o(tr_data_lo[i])
,.yumi_i(tr_yumi_li[i])
,.rom_addr_o(rom_addr[i])
,.rom_data_i(rom_data[i])
,.done_o(ch_done[i])
,.error_o()
);
bsg_nonsynth_test_rom #(
.data_width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`rom_file))
) rom0 (
.addr_i(rom_addr[i])
,.data_o(rom_data[i])
);
assign dramsim3_write_not_read_li[i] = tr_data_lo[i].write_not_read;
assign dramsim3_ch_addr_li[i] = tr_data_lo[i].ch_addr;
assign dramsim3_v_li[i] = tr_v_lo[i];
assign tr_yumi_li[i] = dramsim3_yumi_lo[i];
end
initial begin
# 10000000 $finish;
end
always_ff @(posedge clk) begin
if (~reset & dramsim3_v_li[0]) begin
if (dramsim3_write_not_read_li[0])
$display("write: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
dramsim3_ch_addr_li[0],
dramsim3_ch_addr_li_cast.ro,
dramsim3_ch_addr_li_cast.ba,
dramsim3_ch_addr_li_cast.bg,
dramsim3_ch_addr_li_cast.co,
dramsim3_ch_addr_li_cast.byte_offset);
else
$display("read: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
dramsim3_ch_addr_li[0],
dramsim3_ch_addr_li_cast.ro,
dramsim3_ch_addr_li_cast.ba,
dramsim3_ch_addr_li_cast.bg,
dramsim3_ch_addr_li_cast.co,
dramsim3_ch_addr_li_cast.byte_offset);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O41AI_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_BLACKBOX_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg4_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bg4_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bg4-new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg4-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg4-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<pair<int, int>> v; int row[1010] = {0}, col[1010] = {0}; char g[1010][1010]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> g[i][j]; if (g[i][j] == * ) row[i]++, col[j]++, v.push_back({i, j}); }; int mx_col = 0, mx_row = 0, max_covered = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (row[i] + col[j] - (g[i][j] == * ) > max_covered) mx_row = i, mx_col = j, max_covered = row[i] + col[j] - (g[i][j] == * ); for (auto i : v) if (i.first != mx_row && i.second != mx_col) { cout << NO ; return 0; } cout << YES << endl << mx_row + 1 << << mx_col + 1 << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; if (s == monday && (t == thursday || t == wednesday || t == monday )) cout << YES ; else if (s == tuesday && (t == friday || t == thursday || t == tuesday )) cout << YES ; else if (s == wednesday && (t == friday || t == saturday || t == wednesday )) cout << YES ; else if (s == thursday && (t == saturday || t == sunday || t == thursday )) cout << YES ; else if (s == friday && (t == sunday || t == monday || t == friday )) cout << YES ; else if (s == saturday && (t == monday || t == tuesday || t == saturday )) cout << YES ; else if (s == sunday && (t == tuesday || t == wednesday || t == sunday )) cout << YES ; else cout << NO ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_PP_BLACKBOX_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_sergate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : alu_puf
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This is an ALU based PUF. Implements two adders that operate on the same operands
// concurrently and produce results. The result signals are passed through pdl_puf
// for tuning assymetric routing delay using pdls and responses are computed based on
// which signal is faster for each bit of response.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module AluPuf(CHALLENGE, RESPONSE, trigger, reset, a, b);
output [15:0] RESPONSE;
input [127:0] CHALLENGE;
input trigger;
input reset;
input wire [15:0] a;
input wire [15:0] b;
wire [127:0] CHALLENGE;
wire [15:0] RESPONSE;
(* KEEP = "TRUE" *)
reg [15:0] a1;
reg [15:0] a2;
reg [15:0] b1;
reg [15:0] b2;
wire [15:0] c1;
wire [15:0] c2;
always @ (posedge trigger) begin
a1 <= a;
a2 <= a;
b1 <= b;
b2 <= b;
end
(* KEEP="TRUE" *)
assign c1 = (trigger==1)?(a1+b1):0;
assign c2 = (trigger==1)?(a2+b2):0;
(* KEEP_HIERARCHY="TRUE" *)
pdl_puf puf1 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[0]), .s2(c2[0]), .reset(reset), .o(RESPONSE[0]));
pdl_puf puf2 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[1]), .s2(c2[1]), .reset(reset), .o(RESPONSE[1]));
pdl_puf puf3 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[2]), .s2(c2[2]), .reset(reset), .o(RESPONSE[2]));
pdl_puf puf4 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[3]), .s2(c2[3]), .reset(reset), .o(RESPONSE[3]));
pdl_puf puf5 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[4]), .s2(c2[4]), .reset(reset), .o(RESPONSE[4]));
pdl_puf puf6 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[5]), .s2(c2[5]), .reset(reset), .o(RESPONSE[5]));
pdl_puf puf7 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[6]), .s2(c2[6]), .reset(reset), .o(RESPONSE[6]));
pdl_puf puf8 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[7]), .s2(c2[7]), .reset(reset), .o(RESPONSE[7]));
pdl_puf puf9 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[8]), .s2(c2[8]), .reset(reset), .o(RESPONSE[8]));
pdl_puf puf10 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[9]), .s2(c2[9]), .reset(reset), .o(RESPONSE[9]));
pdl_puf puf11 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[10]), .s2(c2[10]), .reset(reset), .o(RESPONSE[10]));
pdl_puf puf12 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[11]), .s2(c2[11]), .reset(reset), .o(RESPONSE[11]));
pdl_puf puf13 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[12]), .s2(c2[12]), .reset(reset), .o(RESPONSE[12]));
pdl_puf puf14 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[13]), .s2(c2[13]), .reset(reset), .o(RESPONSE[13]));
pdl_puf puf15 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[14]), .s2(c2[14]), .reset(reset), .o(RESPONSE[14]));
pdl_puf puf16 (.s_tp(CHALLENGE[63:0]), .s_btm(CHALLENGE[127:64]), .s1(c1[15]), .s2(c2[15]), .reset(reset), .o(RESPONSE[15]));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; template <typename T> void _dbg(const char* _s, T _h) { cerr << _s << = << _h << n ; } template <typename T, typename... Ts> void _dbg(const char* _s, T _h, Ts... _t) { int _b = 0; while (((_b += *_s == ( ) -= *_s == ) ) != 0 || *_s != , ) cerr << *_s++; cerr << = << _h << , ; _dbg(_s + 1, _t...); } const int64_t INF = static_cast<int64_t>(1e9) + 7; const int64_t LINF = INF * INF; const int MAXN = static_cast<int>(1e6) + 17; void solve() { int n; int64_t second; cin >> n >> second; vector<int> v(n); int64_t sum = 0; int right = INF; for (auto& el : (v)) { cin >> el; sum += el; right = min(right, el); } if (sum < second) { cout << -1 n ; return; } ++right; int left = 0; while (right - left > 1) { int mid = (left + right) / 2; int64_t amount = 0; for (int i = 0; i < n; ++i) { amount += v[i] - mid; } if (amount >= second) { left = mid; } else { right = mid; } } cout << left; } int main() { cin.tie(nullptr); cout.tie(nullptr); ios_base::sync_with_stdio(false); int q = 1; for (int i = 0; i < q; ++i) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int A[55]; int main() { int n; long long int m; cin >> n >> m; if (n == 1) { printf( %d n , 1); return 0; } long long int tot = 1LL << (n - 1); int l = 1; int r = n; for (int i = 1; i < n + 1; i++) { if (m > tot / 2) { A[r] = i; m -= tot / 2; r--; } else { A[l] = i; l++; } tot /= 2; } for (int i = 1; i < n + 1; i++) { printf( %d , A[i]); } return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
// 1.2 11/8/2010 Fixed the PRBS Address generation.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_cmd_prbs_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
function integer logb2;
input integer number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64)
begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
//endgenerate
//generate
else if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32)
begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1)
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
// BL8: 0,8
//BL4: incremnt by 4
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 0)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = 1'b0;// lfsr_q[i+1];
// 3 1
prbs[logb2(MEM_BURST_LEN)-3:0] = 'b0;//{logb2(MEM_BURST_LEN) -3{1'b0}};
// prbs[2:0] = {3{1'b0}};
end
end
end
//endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
//generate
// if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN")
else
begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin
prbs = {ZEROS[SEED_WIDTH - 1:6],lfsr_q[6:1]};
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
`timescale 1ns / 1ps
`include "bch_defs.vh"
module tb_mult_m();
`include "bch.vh"
parameter M = 8;
integer i;
integer j;
reg [M-1:0] s1 = 0;
reg [M-1:0] s2 = 0;
reg [M-1:0] p1 = 0;
reg [M-1:0] pd = 0;
reg [M-1:0] p2d = 0;
reg [M-1:0] p2 = 0;
wire smm_out;
wire smm_out1;
reg serial_s2 = 0;
wire [M-1:0] ssm_out;
wire [M-1:0] pmm_out;
reg [M-1:0] pmm_out_s;
wire [M-1:0] psm_out;
reg [M-1:0] smm_reg;
reg [M-1:0] smm_reg1;
reg [M-1:0] d = 0;
reg start = 0;
reg clk = 0;
integer error;
serial_mixed_multiplier #(M) smm(
.clk(clk),
.start(start),
.dual_in(d),
.standard_in(s2),
.dual_out(smm_out)
);
serial_mixed_multiplier_dss #(M) smm1(
.clk(clk),
.start(start),
.dual_in(d),
.standard_in(s2),
.standard_out(smm_out1)
);
parallel_mixed_multiplier #(M) pmm(
.dual_in(d),
.standard_in(s2),
.dual_out(pmm_out)
);
parallel_standard_multiplier #(M) psm(
.standard_in1(s1),
.standard_in2(s2),
.standard_out(psm_out)
);
serial_standard_multiplier #(M) ssm(
.clk(clk),
.reset(start),
.ce(1'b1),
.parallel_in(s1),
.serial_in(serial_s2),
.out(ssm_out)
);
initial begin
//$dumpfile("test.vcd");
//$dumpvars(0);
error = 0;
#5;
clk = 1;
for (i = 0; i < 5000; i = i + 1) begin
s1 = $random;
if (s1 == 0)
s1 = s1 + 1;
s2 = $random;
if (s2 == 0)
s2 = s2 + 1;
d = standard_to_dual(M, s1);
p1 = finite_mult(M, s1, s2);
p2d = fixed_mixed_multiplier(M, d, s2);
p2 = dual_to_standard(M, p2d);
#1;
if (p1 != p2) begin
$display("Mismatch! %b * %b = %b != %b", s1, s2, p1, p2);
error = 1;
end
if (p2d != pmm_out) begin
$display("Mismatch! %b * %b = %b != %b", s1, s2, p2d, pmm_out);
error = 1;
end
if (p1 != psm_out) begin
$display("Mismatch! %b * %b = %b != %b", s1, s2, p1, psm_out);
error = 1;
end
#1;
start = 1;
#4;
clk = 0;
#5;
clk = 1;
for (j = 0; j < M; j = j + 1) begin
#1;
start = 0;
#1;
smm_reg[j] = smm_out;
smm_reg1[M - j - 1] = smm_out1;
smm_reg2[M - j - 1] = smm_out2;
serial_s2 = s2[M - j - 1];
#3; clk = 0;
#4; clk = 1;
end
#4; clk = 0;
#4; clk = 1;
if (p1 != ssm_out) begin
$display("SSM Mismatch! %b * %b = %b != %b", s1, s2, p1, ssm_out);
error = 1;
end
if (p2d != smm_reg) begin
$display("SMM Mismatch! %b * %b = %b != %b", s1, s2, p2d, smm_reg);
error = 1;
end
if (p1 != smm_reg1) begin
$display("SMM1 Mismatch! %b * %b = %b != %b", s1, s2, p1, smm_reg1);
error = 1;
end
end
$display("%s (M = %d)", error ? "Failed" : "Success", M);
end
endmodule
module tb_mult();
// tb_mult_m #(8) test();
genvar i;
generate
for (i = 2; i <= `MAX_M; i = i + 1) begin : FOO
tb_mult_m #(i) test();
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; struct mat { int num[4][4]; }; mat m1 = {{{1, 1, 1, 0}, {1, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 0, 1}}}, m2 = {{{1, 1, 0, 1}, {1, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 0, 1}}}; mat mult(mat &a, mat &b) { mat ret; for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) { long long t = 0; for (int k = 0; k < 4; k++) t += 1ll * a.num[i][k] * b.num[k][j]; ret.num[i][j] = t % 1000000007; } return ret; } int cal(string &s, string &q) { int ret = 0; for (int i = 0; i + q.size() <= s.size(); i++) if (s.substr(i, q.size()) == q) ret++; return ret; } int query(long long n, string &q) { if (n == 1) { return q == a ? 1 : 0; } if (n == 2) { return q == b ? 1 : 0; } string s1 = a , s2 = b , s = b ; for (n -= 2; n && s1.size() < q.size(); n--, s1 = s2, s2 = s) s = s2 + s1; int f1 = cal(s1, q), f2 = cal(s, q); if (!n) return f2; s = s2.substr(s2.size() - q.size() + 1, q.size() - 1) + s2.substr(0, q.size() - 1); int t1 = cal(s, q); s = s1.substr(s1.size() - q.size() + 1, q.size() - 1) + s1.substr(0, q.size() - 1); int t2 = cal(s, q); mat res, t = mult(m2, m1); bool flag = 0; if (n % 2) res = m1, flag = 1; for (n /= 2; n; n >>= 1, t = mult(t, t)) if (n & 1) { if (!flag) res = t, flag = 1; else res = mult(res, t); } return (1ll * res.num[0][0] * f2 + 1ll * res.num[0][1] * f1 + 1ll * res.num[0][2] * t1 + 1ll * res.num[0][3] * t2) % 1000000007; } int main() { long long n, m; cin >> n >> m; string s; while (m--) cin >> s, cout << query(n, s) << endl; } |
#include <bits/stdc++.h> using namespace std; const int INFint = 2147483647; const long long INF = 9223372036854775807ll; const long long MOD = 1000000007ll; char f[2020][2020]; int n, m; bool c(int x, int y, int d, int cnt) { int cur = 0; cerr << x << << y << endl; if (x > 0 && y > 0 && x + d - 1 <= n && y + d - 1 <= m) { for (int i = x; i < x + d; i++) { cur += (f[i][y] == w ); cur += (f[i][y + d - 1] == w ); } for (int i = y + 1; i < y + d - 1; i++) { cur += (f[x][i] == w ); cur += (f[x + d - 1][i] == w ); } return (cur == cnt); } return 0; } int main() { ios_base::sync_with_stdio(0); int minx = INFint, miny = INFint, maxx = -INFint, maxy = -INFint; cin >> n >> m; int cnt = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> f[i][j]; if (f[i][j] == w ) { minx = min(minx, i); miny = min(miny, j); maxx = max(maxx, i); maxy = max(maxy, j); cnt++; } } } int d = max(maxx - minx + 1, maxy - miny + 1); cerr << d << endl; if (d == 1) { for (int it = 1; it <= n; it++) { for (int l = 1; l <= m; l++) cout << f[it][l]; cout << endl; } return 0; } int x[3] = {minx, maxx - d + 1, 1}; int y[3] = {miny, maxy - d + 1, 1}; for (int i = 0; i < 3; i++) cerr << x[i] << ; cerr << endl; for (int i = 0; i < 3; i++) cerr << y[i] << ; cerr << endl; for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) { if (c(x[i], y[j], d, cnt)) { for (int it = x[i]; it < x[i] + d; it++) { if (f[it][y[j]] != w ) f[it][y[j]] = + ; if (f[it][y[j] + d - 1] != w ) f[it][y[j] + d - 1] = + ; } for (int it = y[j]; it < y[j] + d; it++) { if (f[x[i]][it] != w ) f[x[i]][it] = + ; if (f[x[i] + d - 1][it] != w ) f[x[i] + d - 1][it] = + ; } for (int it = 1; it <= n; it++) { for (int l = 1; l <= m; l++) cout << f[it][l]; cout << endl; } return 0; } } cout << -1 << endl; fprintf(stderr, nTIME = %lf n , 1.0 * clock() / CLOCKS_PER_SEC); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V |
`include "defines.v"
`timescale 1ns/1ps
module tb(
);
wire injrd, injack;
reg clk, rst;
wire `control_w port0_co, port1_co, port2_co, port3_co, port4_co;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(144'h0), .port0_co(port1_co),
.port1_ci(144'h0), .port1_co(port1_co),
.port2_ci(144'h0), .port2_co(port2_co),
.port3_ci(144'h0), .port3_co(port3_co),
.port4_ci(144'h0), .port4_co(port4_co),
.port4_ready(injrd), .port4_ack(injack)
);
initial begin
$set_toggle_region(tb.r);
$toggle_start();
clk = 0;
rst = 0;
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$toggle_stop();
$toggle_report("./calf_backward_0.saif", 1.0e-9, "tb.r");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int ret = 0, f = 1; while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) ret = ret * 10 + ch - 0 , ch = getchar(); return ret * f; } const double inf = 1e30, eps = 1e-10; const int mx = 100005, md = 1e6; struct P { double x, y; bool operator<(const P& a) const { return x == a.x ? y < a.y : x < a.x; } bool operator==(const P& a) const { return fabs(x - a.x) < eps && fabs(y - a.y) < eps; } bool operator!=(const P& a) const { return fabs(x - a.x) > eps || fabs(y - a.y) > eps; } double operator*(const P& a) const { return x * a.y - y * a.x; } P operator-(const P& a) const { return (P){x - a.x, y - a.y}; } } t[mx], st, ed; int f[mx], s[mx][2], rt, tot; inline void rot(int x) { int y = f[x], z = f[y], p = y[s][0] == x; if (z) z[s][z[s][1] == y] = x; else rt = x; f[x] = z, f[y] = x, s[x][p][f] = y; s[y][p ^ 1] = s[x][p], s[x][p] = y; } inline void spl(int x, int o = 0) { for (int y = 0; f[x] ^ o; rot(x)) if (f[y = f[x]] ^ o) rot((s[y][0] == x) == (s[f[y]][0] == y) ? y : x); } inline int ins(P x) { int cu = rt, ls = 0; while (cu) { if (t[cu] == x) { spl(cu); return cu; } ls = cu, cu = s[cu][t[cu] < x]; } f[++tot] = ls, s[ls][t[ls] < x] = tot, t[tot] = x; spl(tot); return tot; } inline int fnd(P x) { int cu = rt; while (cu) { if (t[cu] == x) return cu; cu = s[cu][t[cu] < x]; } return -1; } inline int pre(int id) { spl(id); int cu = s[rt][0]; while (s[cu][1]) cu = s[cu][1]; return cu; } inline int nxt(int id) { spl(id); int cu = s[rt][1]; while (s[cu][0]) cu = s[cu][0]; return cu; } inline void del(int id) { int pr = pre(id), nx = nxt(id); spl(pr), spl(nx, rt), s[s[rt][1]][0] = 0; } inline void add(P a) { int id = ins(a); int pr = pre(id), nx = nxt(id), ppr, nnx; if (pr && nx && t[nx] != ed && ((t[pr] - a) * (t[nx] - a)) > 0) { del(fnd(a)); return; } while (1) { pr = pre(id); ppr = pre(pr); if (ppr && ((t[pr] - t[ppr]) * (a - t[ppr])) <= 0) del(pr); else break; } while (1) { nx = nxt(id); nnx = nxt(nx); if (t[nx] != ed && nnx && t[nnx] != ed && ((t[nx] - a) * (t[nnx] - a)) <= 0) del(nx); else break; } } inline int qry(double a) { int cu = rt, re = 0; t[0].x = -1; while (cu) { if (t[cu].x <= a + eps && t[re].x < t[cu].x) re = cu; cu = s[cu][t[cu].x <= a + eps]; } return re; } int n, ls; double m; int main() { cin >> n >> m; st = (P){0, 0}, ed = (P){inf, inf}; t[rt = tot = 1] = st; ins(ed); for (int i = 1; i <= n; i++) { int op = read(), a = (ls + read()) % md + 1, b = (ls + read()) % md + 1; if (op == 1) { add((P){(double)a, (double)b}); } else { double x = (double)b / a, y = (double)m / a; int po = qry(x), nx = nxt(po); if (fabs(t[po].x - x) < eps && t[po].y < y + eps) ls = i, printf( YES n ); else if (t[nx] == ed) printf( NO n ); else { double inc = t[po].y + (t[nx].y - t[po].y) / (t[nx].x - t[po].x) * (x - t[po].x); if (inc <= y + eps) ls = i, printf( YES n ); else printf( NO n ); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long sqr(long long x) { return (x * x); } inline long long dist(pair<long long, long long> a, pair<long long, long long> b) { return sqr(a.first - b.first) + sqr(a.second - b.second); } int main() { vector<pair<long long, pair<long long, long long> > > a; int d; double answer; int n; scanf( %d , &n); long long x, y, r; for (int i = 0; i < n; i++) { scanf( %I64d %I64d %I64d , &x, &y, &r); a.push_back(make_pair(r, make_pair(x, y))); } sort(a.begin(), a.end()); for (int i = 0; i < n; i++) { d = 0; for (int j = i + 1; j < n; j++) if (dist(a[i].second, a[j].second) <= sqr(a[j].first)) d++; answer += (double)acos(-1) * sqr(a[i].first) * ((!d || d & 1) ? 1 : -1); } printf( %.10lf n , answer); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int mxn = 0; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; while (t--) { long long int i, j, k, n, m, x; cin >> n >> x >> k; vector<long long int> a(n); for (i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); long long int ans = 0; for (i = 0; i < n; i++) { long long int l = a[i] / x; if (a[i] % x) { ans += lower_bound(a.begin(), a.end(), x * (l + k + 1)) - lower_bound(a.begin(), a.end(), max((l + k) * x, a[i])); } else { ans += lower_bound(a.begin(), a.end(), (l + k) * x) - lower_bound(a.begin(), a.end(), max((l + k - 1) * x, a[i])); } } cout << ans; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int k, l, m, n, d; int cont = 0; cin >> k >> l >> m >> n >> d; cont = d; if (k == 1 || l == 1 || m == 1 || n == 1) { cout << d << endl; } else { for (int i = 1; i <= d; i++) { if ((i % k != 0) && (i % l != 0) && (i % m != 0) && (i % n != 0)) cont--; } cout << cont << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int p, x, y; queue<int> q; int mmap[100000]; bool check(int s) { int i = s / 50 % 475; for (int j = 0; j < 25; ++j) { i = (i * 96 + 42) % 475; if (26 + i == p) return true; } mmap[s] = 1; return false; } int main() { cin >> p >> x >> y; q.push(0); while (!q.empty()) { int n = q.front(); q.pop(); int s = x + n * 100; while (s >= y) { if (mmap[s]) { s -= 50; continue; } if (check(s)) { cout << n << endl; return 0; } s -= 50; } q.push(n + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; while (cin >> n >> m) { vector<int> f(n); vector<int> v[100005]; vector<int> b(m); vector<int> a(m); vector<int> used(100005, 0); for (int i = 0; i < n; i++) { cin >> f[i]; v[f[i]].push_back(i + 1); } for (int i = 0; i < m; i++) cin >> b[i]; int sizeA = 0; int state = -1; for (int i = 0; i < m; i++) { if (v[b[i]].size()) { a[sizeA++] = v[b[i]][0]; used[b[i]]++; } else { sizeA = 0; break; } } if (sizeA < m) { cout << Impossible << endl; continue; } for (int i = 0; i < 100005 && state == -1; i++) { if (used[i] && v[i].size() > 1) { state = 1; } } if (state == 1 || sizeA > m) { cout << Ambiguity << endl; } else { cout << Possible << endl; for (int i = 0; i < m; i++) { if (i) cout << ; cout << a[i]; } cout << endl; } } } |
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module arbiter(rst, clk, cpu_daddr, cpu_bus_data, bus_cpu_data, cpu_drw, cpu_iaddr, bus_cpu_inst, int, int_ack, mod_leds_leds, mod_uart_txd, mod_uart_rxd, mod_switches_switches, mod_sseg_an, mod_sseg_display, cpu_stall, mod_sram_clk, mod_sram_adv, mod_sram_cre, mod_sram_ce, mod_sram_oe, mod_sram_we, mod_sram_lb, mod_sram_ub, mod_sram_data, mod_sram_addr, mod_vga_rgb, mod_vga_hs, mod_vga_vs, mod_gpio_gpio, i_button);
input clk, rst, int_ack;
output int;
/* cpu i/o */
input [1:0] cpu_drw; /* data read/write. cpu_drw = 00 is nop, 01 is write, 10 is read */
input [31:0] cpu_daddr, cpu_iaddr; /* word aligned */
input [31:0] cpu_bus_data; /* cpu data coming from the cpu */
output [31:0] bus_cpu_data, bus_cpu_inst; /* cpu data going to the cpu */
/* module i/o */
output [7:0] mod_leds_leds;
input mod_uart_rxd;
output mod_uart_txd;
input [7:0] mod_switches_switches;
output [3:0] mod_sseg_an;
output [7:0] mod_sseg_display;
output cpu_stall, mod_sram_clk, mod_sram_adv, mod_sram_cre, mod_sram_ce, mod_sram_oe, mod_sram_we, mod_sram_lb, mod_sram_ub;
inout [15:0] mod_sram_data;
output [23:1] mod_sram_addr;
output [7:0] mod_vga_rgb;
output mod_vga_hs, mod_vga_vs;
inout [15:0] mod_gpio_gpio;
input i_button;
/* inter-module interconnect */
wire [31:0] mod_vga_sram_addr;
wire [31:0] mod_vga_sram_data;
wire mod_vga_sram_read;
wire mod_vga_sram_rdy;
/* interrupt interconnect */
wire i_timer, i_uart;
/* pmc hardware interconnect */
wire pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D, pmc_uart_recv, pmc_uart_send;
/* effective address calculation for the modules */
wire [7:0] imod, dmod;
wire [31:0] ieff_addr, deff_addr;
mm imm(cpu_iaddr, imod, ieff_addr);
mm dmm(cpu_daddr, dmod, deff_addr);
/* instruction and data enable wires */
wire mod0_ie = imod == 0;
wire mod1_ie = imod == 1;
wire mod2_ie = imod == 2;
wire mod3_ie = imod == 3;
wire mod4_ie = imod == 4;
wire mod5_ie = imod == 5;
wire mod6_ie = imod == 6;
wire mod7_ie = imod == 7;
wire mod8_ie = imod == 8;
wire mod9_ie = imod == 9;
wire modA_ie = imod == 10;
wire modB_ie = imod == 11;
wire mod0_de = dmod == 0;
wire mod1_de = dmod == 1;
wire mod2_de = dmod == 2;
wire mod3_de = dmod == 3;
wire mod4_de = dmod == 4;
wire mod5_de = dmod == 5;
wire mod6_de = dmod == 6;
wire mod7_de = dmod == 7;
wire mod8_de = dmod == 8;
wire mod9_de = dmod == 9;
wire modA_de = dmod == 10;
wire modB_de = dmod == 11;
/* the bus muxes */
wire [31:0] mod0_inst, mod0_data;
wire [31:0] mod1_inst, mod1_data;
wire [31:0] mod2_inst, mod2_data;
wire [31:0] mod3_inst, mod3_data;
wire [31:0] mod4_inst, mod4_data;
wire [31:0] mod5_inst, mod5_data;
wire [31:0] mod6_inst, mod6_data;
wire [31:0] mod7_inst, mod7_data;
wire [31:0] mod8_inst, mod8_data;
wire [31:0] mod9_inst, mod9_data;
wire [31:0] modA_inst, modA_data;
wire [31:0] modB_inst, modB_data;
assign bus_cpu_inst =
mod0_ie ? mod0_inst :
mod1_ie ? mod1_inst :
mod2_ie ? mod2_inst :
mod3_ie ? mod3_inst :
mod4_ie ? mod4_inst :
mod5_ie ? mod5_inst :
mod6_ie ? mod6_inst :
mod7_ie ? mod7_inst :
mod8_ie ? mod8_inst :
mod9_ie ? mod9_inst :
modA_ie ? modA_inst :
modB_ie ? modB_inst : 0;
assign bus_cpu_data =
mod0_de ? mod0_data :
mod1_de ? mod1_data :
mod2_de ? mod2_data :
mod3_de ? mod3_data :
mod4_de ? mod4_data :
mod5_de ? mod5_data :
mod6_de ? mod6_data :
mod7_de ? mod7_data :
mod8_de ? mod8_data :
mod9_de ? mod9_data :
modA_de ? modA_data :
modB_de ? modB_data : 0;
/* module instantiations */
/* 0 */ mod_rom rom_t (rst, clk, mod0_ie, mod0_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod0_inst, mod0_data);
/* 1 */ mod_memory_hierarchy ram_t (rst, clk, mod1_ie, mod1_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod1_inst, mod1_data, cpu_stall, mod_sram_clk, mod_sram_adv, mod_sram_cre, mod_sram_ce, mod_sram_oe, mod_sram_we, mod_sram_lb, mod_sram_ub, mod_sram_data, mod_sram_addr, mod_vga_sram_data, mod_vga_sram_addr, mod_vga_sram_read, mod_vga_sram_rdy, pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D);
/* 2 */ mod_uart uart_t (rst, clk, mod2_ie, mod2_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod2_inst, mod2_data, mod_uart_txd, mod_uart_rxd, i_uart, pmc_uart_recv, pmc_uart_send);
/* 3 */ mod_switches switches_t (rst, clk, mod3_ie, mod3_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod3_inst, mod3_data, mod_switches_switches);
/* 4 */ mod_leds leds_t (rst, clk, mod4_ie, mod4_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod4_inst, mod4_data, mod_leds_leds);
/* 5 */ mod_gpio gpio_t (rst, clk, mod5_ie, mod5_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod5_inst, mod5_data, mod_gpio_gpio);
/* 6 */ mod_vga vga_t (rst, clk, mod6_ie, mod6_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod6_inst, mod6_data, mod_vga_rgb, mod_vga_hs, mod_vga_vs, mod_vga_sram_data, mod_vga_sram_addr, mod_vga_sram_read, mod_vga_sram_rdy);
/* 7 */ mod_plpid plpid_t (rst, clk, mod7_ie, mod7_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod7_inst, mod7_data);
/* 8 */ mod_timer timer_t (rst, clk, mod8_ie, mod8_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod8_inst, mod8_data, i_timer);
/* 9 */ mod_sseg sseg_t (rst, clk, mod9_ie, mod9_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, mod9_inst, mod9_data, mod_sseg_an, mod_sseg_display);
/* 10 */mod_interrupt interrupt_t (rst, clk, modA_ie, modA_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, modA_inst, modA_data, int, int_ack, i_timer, i_uart, i_button);
/* 11 */mod_pmc pmc_t (rst, clk, modB_ie, modB_de, ieff_addr, deff_addr, cpu_drw, cpu_bus_data, modB_inst, modB_data, int, pmc_cache_miss_I, pmc_cache_miss_D, pmc_cache_access_I, pmc_cache_access_D, pmc_uart_recv, pmc_uart_send);
endmodule
|
#include <bits/stdc++.h> using namespace std; char str1[200002], str2[200002]; const int K = 1024; int aw[200002]; int bw[200002]; char bit[1 << 16]; short cnt[200002 / K + 1][200002]; int main() { gets(str1); gets(str2); int l1 = strlen(str1), l2 = strlen(str2); for (int i = 0; i < l1; ++i) { unsigned int one = 1; for (int j = 0; j < 16 && i + j < l1; ++j) { if (str1[i + j] == 1 ) aw[i] |= one; one <<= 1; } } for (int i = 0; i < l2; ++i) { unsigned int one = 1; for (int j = 0; j < 16 && i + j < l2; ++j) { if (str2[i + j] == 1 ) bw[i] |= one; one <<= 1; } } bit[0] = 0; for (int i = 1; i < (1 << 16); ++i) { bit[i] = (i & 1) + bit[i >> 1]; } int IT = K >> 4; for (int i = 0; i + K <= l1; i += K) { int ind = i / K; for (int j = 0; j + K <= l2; ++j) { int p1 = i, p2 = j; for (int t = 0; t < IT; ++t) { cnt[ind][j] += bit[aw[p1] ^ bw[p2]]; p1 += 16; p2 += 16; } } } int q, p1, p2, len; scanf( %d , &q); while (q--) { scanf( %d%d%d , &p1, &p2, &len); int ans = 0; int pos = (p1 / K) * K, r = p1 + len - 1; while (pos < p1) pos += K; for (int i = p1; i < pos && i <= r; ++i) { ans += str1[i] != str2[p2]; ++p2; } if (pos <= r) { while (pos + K - 1 <= r) { ans += cnt[pos / K][p2]; pos += K; p2 += K; } for (int i = pos; i <= r; ++i) { ans += str1[i] != str2[p2]; ++p2; } } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:247474112 ) #pragma GCC optimize( Ofast ) using namespace std; const long long maxn = 2e5 + 10; long long mx[maxn], val[maxn], sum[maxn]; vector<long long> g[maxn]; long long pass[maxn]; bool ok = 0; long long ans = LLONG_MIN; void dfs(long long aa = 1, long long aaa = 0) { vector<long long> v; sum[aa] = val[aa]; for (long long a : g[aa]) { if (a == aaa) continue; dfs(a, aa); sum[aa] += sum[a]; v.push_back(pass[a]); } if (!v.empty()) { sort(v.begin(), v.end()); pass[aa] = max(v.back(), sum[aa]); if (v.size() >= 2) { ans = max(ans, v[v.size() - 1] + v[v.size() - 2]); } } else { pass[aa] = sum[aa]; } } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n; cin >> n; for (long long i = 1; i <= n; ++i) cin >> val[i]; for (long long i = 1; i <= n; ++i) mx[i] = LLONG_MIN; for (long long i = 1; i < n; ++i) { long long u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } for (long long i = 1; i <= n; ++i) pass[i] = LLONG_MIN; dfs(1); if (ans == LLONG_MIN) cout << Impossible ; else cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, x, y, ans; int p[100010], q[100010], mn[100010]; vector<int> t[100010], v[100010]; bool flag[100010]; inline int dist(int x, int y) { return abs(p[x] - q[y]); } int main() { scanf( %d%d%d%d , &n, &m, &x, &y); memset(mn, 63, sizeof(mn)); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); for (int i = 1; i <= m; i++) scanf( %d , &q[i]); q[m + 1] = 1e9; q[0] = -1e9; int pos = 1; for (int i = 1; i <= n; i++) { while (pos <= m && q[pos] <= p[i]) pos++; pos--; if (dist(i, pos) == dist(i, pos + 1)) { t[i].push_back(pos); t[i].push_back(pos + 1); } else if (dist(i, pos) < dist(i, pos + 1)) { t[i].push_back(pos); } else { t[i].push_back(pos + 1); } } for (int i = 1; i <= n; i++) if (t[i].size() == 1) { int t1 = t[i][0]; v[t1].push_back(i); mn[t1] = min(mn[t1], dist(i, t1)); } for (int i = 1; i <= n; i++) if (t[i].size() == 1) { int t1 = t[i][0]; if (dist(i, t1) > mn[t1]) flag[i] = 1; } for (int i = 1; i <= n; i++) if (t[i].size() == 2) { bool flag1 = 0, flag2 = 0; int cnt1 = 0, cnt2 = 0; int t1 = t[i][0], t2 = t[i][1], d = dist(i, t1); for (int j = 0; j < v[t1].size(); j++) { if (dist(v[t1][j], t1) < d) flag1 = 1; if (d < dist(v[t1][j], t1)) if (flag[v[t1][j]] == 0) cnt1++; } for (int j = 0; j < v[t2].size(); j++) { if (dist(v[t2][j], t2) < d) flag2 = 1; if (d < dist(v[t2][j], t2)) if (flag[v[t2][j]] == 0) cnt2++; } if (cnt1 + flag1 <= cnt2 + flag2) { flag[i] = flag1; for (int j = 0; j < v[t1].size(); j++) if (d < dist(v[t1][j], t1)) flag[v[t1][j]] = 1; mn[t1] = min(mn[t1], dist(i, t1)); v[t1].push_back(i); } else { flag[i] = flag2; for (int j = 0; j < v[t2].size(); j++) if (d < dist(v[t2][j], t2)) flag[v[t2][j]] = 1; mn[t2] = min(mn[t2], dist(i, t2)); v[t2].push_back(i); } } for (int i = 1; i <= n; i++) ans += flag[i]; printf( %d , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_M_V
`define SKY130_FD_SC_LP__O41AI_M_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_m (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_m (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_M_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 0; i < k; i++) { if (n % 10 == 0) { n /= 10; } else { n--; } } printf( %d n , n); } |
/**
# SmallBpf - 2-pole IIR Bandpass Filter #
Small 2-Pole IIR band-pass filter, made using just adders and bit shifts. Set
the frequency using the K0_SHIFT and K1_SHIFT parameters. It can be slowed down by
strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is alsways stable and is
immune to limit cycling.
Clamping is necessary if the full input range will be used. Clamping is
unnecessary if the input word will never go beyond '+/- (2^(WIDTH-2)-1)'. Keep
in mind that clamping will cause nonlinear distortion in high-amplitude signals.
## Design Equations ##
Let w0 be the desired center frequency in radians/second, let f_clk be the
filter run rate (defined by clk and en), and let Q be the desired quality
factor. Quality factor can be defined as the center frequency divided by the
bandwidth.
```
(w0/Q)*s
H(s) = -----------------------
s^2 + (w0/Q)*s + w0^2
w0 = 2*pi*f0
Q = f0 / f_bandwidth
K0_SHIFT = -log2(w0/Q / f_clk)
K1_SHIFT = -log2(w0*Q / f_clk)
w0/Q = 2^-K0_SHIFT * f_clk
w0*Q = 2^-K1_SHIFT * f_clk
w0 = sqrt(2^-K0_SHIFT * 2^-K1_SHIFT * f_clk^2)
Q = sqrt(2^-K1_SHIFT / 2^-K0_SHIFT)
```
Since the SHIFT parameters must be integers, the final filter will not perfectly
match the desired one. The true filter response will also be different from the
continuous-time approximation.
## Block Diagram ##
Key:
- ACCUM: accumulator
- SUB: subtract signal on bottom from the signal on the left
- 2^-X: Right arithmetic shift by X
```
dataIn --->(SUB)--->(SUB)--->[ACCUM]--->[2^-K0_SHIFT]--+--> dataOut
^ ^ |
| | |
| \----[2^-K1_SHIFT]<---[ACCUM]<---+
| |
\-----------------------------------------/
```
*/
module SmallBpf #(
parameter WIDTH = 16, ///< Data width
parameter K0_SHIFT = 10, ///< Gain on forward path accumulator
parameter K1_SHIFT = 18, ///< Gain on feedback path accumulator
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, active high and synchronous
input en, ///< Filter enable
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter output
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH+1:0] forwardIn;
wire signed [WIDTH-1:0] feedbackOut;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + forwardIn;
assign acc1In = acc1 + dataOut;
always @(posedge clk) begin
if (rst) begin
forwardIn <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardIn <= dataIn - dataOut - feedbackOut;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign dataOut = acc0 >>> K0_SHIFT;
assign feedbackOut = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
/*
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; if (n == 1 && t == 10) { cout << -1 << endl; return 0; } if (t == 10) { for (int i = 1; i < n; i++) cout << 1; cout << 0 << endl; return 0; } if (n == 1) { cout << t << endl; return 0; } cout << t; for (int i = 1; i < n - 1; i++) cout << 0; cout << t << endl; return 0; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Abel> struct BIT2D { vector<vector<Abel>> dat[4]; BIT2D(int h, int w) { for (int which = 0; which < 4; which++) dat[which].assign(h + 1, vector<Abel>(w + 1)); } inline void sub_add(int which, int a, int b, Abel x) { int h = dat[which].size(), w = dat[which][0].size(); for (int i = a; i < h; i += i & -i) for (int j = b; j < w; j += j & -j) dat[which][i][j] += x; } inline void add(int si, int sj, Abel x) { sub_add(0b00, si, sj, x * (si - 1) * (sj - 1)); sub_add(0b10, si, sj, -x * (si - 1)); sub_add(0b01, si, sj, -x * (sj - 1)); sub_add(0b11, si, sj, x); } inline void add(int si, int ti, int sj, int tj, Abel x) { add(si, sj, x), add(si, tj, -x), add(ti, sj, -x), add(ti, tj, x); } inline Abel sub_sum(int which, int a, int b) { Abel res = Abel(0); for (int i = a; i > 0; i -= i & -i) for (int j = b; j > 0; j -= j & -j) res += dat[which][i][j]; return res; } inline Abel sum(int si, int sj) { Abel res = Abel(0); res += sub_sum(0b00, si - 1, sj - 1); res += sub_sum(0b10, si - 1, sj - 1) * (sj - 1); res += sub_sum(0b01, si - 1, sj - 1) * (si - 1); res += sub_sum(0b11, si - 1, sj - 1) * (si - 1) * (sj - 1); return res; } inline Abel sum(int si, int ti, int sj, int tj) { return sum(ti, tj) - sum(si, tj) - sum(ti, sj) + sum(si, sj); } }; struct Xor { long long val; Xor(long long val_ = 0) : val(val_) {} Xor operator=(long long val_) { this->val = val_; return *this; } Xor operator-() { return val; } const Xor &operator+=(const Xor &x); const Xor &operator-=(const Xor &x); friend ostream &operator<<(ostream &os, const Xor &a) { return os << a.val; } }; Xor operator+(Xor x, Xor y) { return x.val ^ y.val; } Xor operator-(Xor x, Xor y) { return x.val ^ y.val; } Xor operator*(Xor x, int p) { return p & 1 ? x : 0; } const Xor &Xor::operator+=(const Xor &x) { return *this = *this + x; } const Xor &Xor::operator-=(const Xor &x) { return *this = *this - x; } int main() { cin.tie(nullptr); ios::sync_with_stdio(false); int n, m; cin >> n >> m; BIT2D<Xor> bit(n, n); while (m--) { int op; cin >> op; int si, sj, ti, tj; cin >> si >> sj >> ti >> tj; if (op == 1) { cout << bit.sum(si, ti + 1, sj, tj + 1) << endl; } if (op == 2) { long long v; cin >> v; bit.add(si, ti + 1, sj, tj + 1, v); } } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MOD = 1e9 + 7; int main() { cin.tie(0)->sync_with_stdio(0); int t; cin >> t; while (t--) { string s; cin >> s; vector<int> r; for (string t : { twone , one , two }) { for (size_t pos = 0; (pos = s.find(t, pos)) != string::npos;) { s[pos + t.length() / 2] = ? ; r.push_back(pos + t.length() / 2); } } cout << r.size() << endl; for (auto rr : r) cout << rr + 1 << ; cout << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_2_V
`define SKY130_FD_SC_LP__OR4_2_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_2_V
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
output wire Y
);
parameter [0:0] INV_A = 1'b0;
endmodule
module top(
input wire [1:0] di,
output wire [2:0] do
);
wire [1:0] d;
\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
box b0 (.A(d[0]), .Y(do[0]));
box b1 (.A(d[1]), .Y(do[1]));
assign do[0] = d[0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_8_V
`define SKY130_FD_SC_LP__NAND2_8_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_8_V
|
`include "elink_constants.vh"
module erx_clocks (/*AUTOARG*/
// Outputs
rx_lclk, rx_lclk_div4, rx_active, erx_nreset, erx_io_nreset,
// Inputs
sys_nreset, soft_reset, tx_active, sys_clk, rx_clkin
);
//Frequency Settings (Mhz)
parameter FREQ_RXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter RXCLK_PHASE = 0; // 270;
parameter PLL_VCO_MULT = 4; // RX
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Don't touch these! (derived parameters)
localparam real RXCLK_PERIOD = 1000.000000 / FREQ_RXCLK; //? Why is the period needed here?
localparam integer IREF_DIVIDE = PLL_VCO_MULT * FREQ_RXCLK / FREQ_IDELAY;
localparam integer RXCLK_DIVIDE = PLL_VCO_MULT; //1:1
//Input clock, reset, config interface
input sys_nreset; // active low system reset (hw)
input soft_reset; // rx enable signal (sw)
input tx_active; // tx active input
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
input rx_clkin; // input clk for RX only PLL
//RX Clocks
output rx_lclk; // rx high speed clock for DDR IO
output rx_lclk_div4; // rx slow clock for logic
//Reset
output rx_active; // rx active
output erx_nreset; // reset for rx core logic
output erx_io_nreset; // io reset (synced to high speed clock)
//############
//# WIRES
//############
//Idelay controller
wire idelay_reset;
wire idelay_ready; //ignore this?
wire idelay_ref_clk;
//pll outputs
wire rx_lclk_pll;
wire rx_lclk_div4_pll;
wire idelay_ref_clk_pll;
//PLL
wire rx_lclk_fb;
wire rx_nreset_in;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
wire pll_locked_sync;
reg [2:0] reset_state;
wire pll_reset;
reg rx_nreset;
wire pll_locked;
//Reset
assign rx_nreset_in = sys_nreset & tx_active;
//wrap around counter that generates a 1 cycle heartbeat
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
`define RX_RESET_ALL 3'b000
`define RX_START_PLL 3'b001
`define RX_ACTIVE 3'b010
//Reset sequence state machine
always @ (posedge sys_clk or negedge rx_nreset_in)
if(!rx_nreset_in)
reset_state[2:0] <= `RX_RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RX_RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `RX_START_PLL;
`RX_START_PLL :
if(pll_locked_sync & idelay_ready)
reset_state[2:0] <= `RX_ACTIVE;
`RX_ACTIVE:
if(soft_reset)
reset_state[2:0] <= `RX_RESET_ALL; //stay there until next reset
endcase // case (reset_state[2:0])
assign pll_reset = (reset_state[2:0]==`RX_RESET_ALL);
assign idelay_reset = (reset_state[2:0]==`RX_RESET_ALL);
//Reset for RX (pipeline to improve timing)
always @ (posedge sys_clk)
rx_nreset <= ~(reset_state[2:0] != `RX_ACTIVE);
//active indicator
assign rx_active = (reset_state[2:0] == `RX_ACTIVE);
//#############################
//#RESET SYNCING
//#############################
oh_rsync rsync_io (// Outputs
.nrst_out (erx_io_nreset),
// Inputs
.clk (rx_lclk),
.nrst_in (rx_nreset)
);
oh_rsync rsync_core (// Outputs
.nrst_out (erx_nreset),
// Inputs
.clk (rx_lclk_div4),
.nrst_in (rx_nreset)
);
generate
if(TARGET=="XILINX")
begin
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb),
.CLKFBOUT(rx_lclk_fb),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),//??
.DO(), //??
.LOCKED(pll_locked)
);
//Clock network
BUFG i_lclk_bufg (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG i_lclk_div4_bufg (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //(300Mhz/4)
BUFG i_idelay_bufg (.I(idelay_ref_clk_pll),.O(idelay_ref_clk));//idelay ctrl clock
//two clock synchronizer for lock signal
oh_dsync dsync (.dout (pll_locked_sync),
.clk (sys_clk),
.nreset (1'b1),
.din (pll_locked)
);
//###########################
// Idelay controller
//###########################
`define IDELAYCTRL_WONT_SYNTHESIZE
`ifdef IDELAYCTRL_WONT_SYNTHESIZE
assign idelay_ready = 'b1;
`else
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL
#(
.SIM_DEVICE("ULTRASCALE_PLUS_ES2")
) idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset)
);
`endif
end // if (TARGET=="XILINX")
endgenerate
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; long long i, x; vector<long long> v; for (i = 0; i < n; i++) { cin >> x; v.push_back(x); } long long ans = 0; for (long long i = 0; i < n; i++) { long long sum = 0; for (long long j = i; j < n; j++) { sum += v[j]; if (sum > 100 * (j - i + 1)) ans = max(ans, j - i + 1); } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e6 + 7; long long int a[N], b[N], c[N], tree[N], lazy[N], cnt, sum, s2, mx; vector<long long int> v, u; vector<pair<long long int, long long int>> vp; map<long long int, long long int> mp; bool vis[111111]; pair<long long int, long long int> p; set<pair<long long int, long long int>> ss; queue<long long int> q; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m = 0, d, i = 0, s1 = 0, s2 = 0, q = 5, x = 0, y, k, j; string s; cin >> n; if (n % 2 == 0) m = n / 2 - 1; else m = n / 2; double mx = 0.0; for (i = m; i > 0; i--) { map<long long int, long long int> mm; cnt = 0; for (j = 2; j <= i; j++) { if (i % j == 0) mm[j]++; } for (j = 2; j <= (n - i); j++) { if ((n - i) % j == 0 && mm[j] != 0) { cnt = 1; break; } } if (cnt == 0) return cout << i << << n - i, 0; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFXTP_PP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; void pre() {} void solve() { long long k, b, n; cin >> k >> b >> n; long long arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; map<long long, long long> m; long long curr = 0; long long ans = 0; m[0]++; if (b == k - 1) { long long cur = 0; for (int i = 0; i < n; i++) { cur = 0; while (i < n && arr[i] == 0) { cur++; i++; } if (cur != 0) { i--; } ans -= (cur * (cur + 1)) / 2; } } if (b == 0) { long long cur = 0; for (int i = 0; i < n; i++) { cur = 0; while (i < n && arr[i] == 0) { cur++; i++; } if (cur != 0) { i--; } ans += (cur * (cur + 1)) / 2; } cout << ans << n ; return; } b %= (k - 1); for (int i = 0; i < n; i++) { curr += arr[i]; curr %= (k - 1); ans += m[(curr - b + k - 1) % (k - 1)]; m[curr]++; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); pre(); solve(); } |
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979; const double PI2 = 6.28318530717958; const double PId2 = 1.570796326794895; inline long long pw(long long n, int p) { long long ans = 1; for (int i = 0; i < p; i++) ans *= n; return ans; } inline vector<int> ReadVI(int count) { vector<int> arrayname(count); for (int i = 0; i < int(count); i++) cin >> arrayname[i]; return arrayname; }; inline vector<long long> ReadVlong(int count) { vector<long long> arrayname(count); for (int i = 0; i < int(count); i++) cin >> arrayname[i]; return arrayname; }; inline vector<pair<int, int> > ReadVII(int count) { vector<pair<int, int> > arrayname(count); for (int i = 0; i < int(count); i++) { cin >> arrayname[i].first; arrayname[i].second = i; } return arrayname; }; const int MOD = 1000000007; const int MAXVALUE = 101; int main() { int f[5]; cin >> f[0] >> f[1] >> f[2] >> f[3] >> f[4]; int n; cin >> n; string a[5] = { S , M , L , XL , XXL }; int d[9] = {0, 1, -1, 2, -2, 3, -3, 4, -4}; string ts; int t; for (int i = 0; i < n; i++) { cin >> ts; t = 0; for (; t < 5; t++) if (a[t] == ts) break; for (int j = 0; j < 9; j++) { int k = t; k += d[j]; if (k < 0 || k > 4) continue; if (f[k]) { f[k]--; cout << a[k] << endl; break; } } } return 0; } |
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