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#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; long long mod = 1000000007; vector<long long> gr[200001]; vector<long long> grev[200001]; long long a[200005]; void solve() { long long n, d, a, b; cin >> n >> d >> a >> b; vector<pair<long long, long long> > ans; for (long long i = int(0); i < int(n); i++) { long long x, y; cin >> x >> y; long long val = x * a + y * b; ans.push_back({val, i + 1}); } sort(ans.begin(), ans.end()); long long val = 0; vector<long long> ind; long long i = 0; for (i = 0; i < n; i++) { val += ans[i].first; if (val <= d) ind.push_back(ans[i].second); else break; } cout << i << n ; for (long long i = int(0); i < int(ind.size()); i++) { cout << ind[i] << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; t = 1; while (t--) { solve(); } return 0; }
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/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the register file
module RegFileWW (rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
//if(rd1en && !((rd1addr==5'bxxxxx) || (rd1addr==5'bzzzzz)))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd1en)
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data<=128'b0;
end
//if(rd2en && (rd2addr!=5'bx) && (rd2addr!=5'bz))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd2en)
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data<=128'b0;
end
end
endmodule
|
// onchip_ram_256b_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module onchip_ram_256b_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 258,
parameter inUsePackets = 0,
parameter inDataWidth = 258,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 258,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [257:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [257:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 258)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 258)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 258)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
onchip_ram_256b_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Current.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_Current
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_Current
(
CLK_IN,
reset,
enb_1_2000_0,
Reest,
Err,
param_current_p_gain,
param_current_i_gain,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reest;
input signed [17:0] Err; // sfix18_En14
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [17:0] Out; // sfix18_En12
wire signed [35:0] Product2_out1; // sfix36_En24
wire signed [35:0] Convert_Data_Type1_out1; // sfix36_En23
wire signed [17:0] Constant2_out1; // sfix18_En31
wire signed [35:0] Product_out1; // sfix36_En33
wire signed [17:0] pre_integrator; // sfix18_En15
wire signed [35:0] pre_integrator_1; // sfix36_En29
wire signed [35:0] Constant_out1; // sfix36_En29
wire signed [35:0] u; // sfix36_En23
wire PI_Sat_out2;
wire Clamp_out1;
wire switch_compare_1;
wire signed [35:0] Switch_out1; // sfix36_En29
wire signed [31:0] I_term; // sfix32_En26
wire signed [36:0] Add_add_cast; // sfix37_En29
wire signed [36:0] Add_add_cast_1; // sfix37_En29
wire signed [36:0] Add_add_temp; // sfix37_En29
wire signed [31:0] Add_out1; // sfix32_En26
wire signed [39:0] Sum1_add_cast; // sfix40_En26
wire signed [39:0] Sum1_add_cast_1; // sfix40_En26
wire signed [39:0] Sum1_add_temp; // sfix40_En26
wire signed [35:0] u_sat; // sfix36_En23
wire signed [17:0] D_Data_Type_out1; // sfix18_En12
// Control Current
// <S7>/Product2
assign Product2_out1 = param_current_p_gain * Err;
// <S7>/Convert_Data_Type1
velocityControlHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(Product2_out1), // sfix36_En24
.Out1(Convert_Data_Type1_out1) // sfix36_En23
);
// <S7>/Constant2
assign Constant2_out1 = 18'sb010100111110001011;
// <S7>/Product
assign Product_out1 = param_current_i_gain * Constant2_out1;
// <S7>/Maintain_Range
velocityControlHdl_Maintain_Range u_Maintain_Range (.In1(Product_out1), // sfix36_En33
.Out1(pre_integrator) // sfix18_En15
);
// <S7>/Product1
assign pre_integrator_1 = Err * pre_integrator;
// <S7>/Constant
assign Constant_out1 = 36'sh000000000;
// <S7>/Clamp
velocityControlHdl_Clamp u_Clamp (.preIntegrator(pre_integrator_1), // sfix36_En29
.preSat(u), // sfix36_En23
.saturated(PI_Sat_out2),
.Clamp(Clamp_out1)
);
assign switch_compare_1 = (Clamp_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S7>/Switch
assign Switch_out1 = (switch_compare_1 == 1'b0 ? pre_integrator_1 :
Constant_out1);
// <S7>/Add
assign Add_add_cast = Switch_out1;
assign Add_add_cast_1 = {{2{I_term[31]}}, {I_term, 3'b000}};
assign Add_add_temp = Add_add_cast + Add_add_cast_1;
assign Add_out1 = ((Add_add_temp[36] == 1'b0) && (Add_add_temp[35:34] != 2'b00) ? 32'sb01111111111111111111111111111111 :
((Add_add_temp[36] == 1'b1) && (Add_add_temp[35:34] != 2'b11) ? 32'sb10000000000000000000000000000000 :
$signed(Add_add_temp[34:3])));
// <S7>/Reset_Delay
velocityControlHdl_Reset_Delay u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reest),
.In(Add_out1), // sfix32_En26
.Out(I_term) // sfix32_En26
);
// <S7>/Sum1
assign Sum1_add_cast = {Convert_Data_Type1_out1[35], {Convert_Data_Type1_out1, 3'b000}};
assign Sum1_add_cast_1 = I_term;
assign Sum1_add_temp = Sum1_add_cast + Sum1_add_cast_1;
assign u = Sum1_add_temp[38:3];
// <S7>/PI_Sat
velocityControlHdl_PI_Sat u_PI_Sat (.In1(u), // sfix36_En23
.Out1(u_sat), // sfix36_En23
.saturated(PI_Sat_out2)
);
// <S7>/D_Data_Type
assign D_Data_Type_out1 = u_sat[28:11];
assign Out = D_Data_Type_out1;
endmodule // velocityControlHdl_Control_Current
|
#include <bits/stdc++.h> using namespace std; double ans = 1111111111; int ap[111111], bp[111111], bt[111111], n, m, a, b, l, r, m1, m2, minap, minbp; double dist(double ax, double ay, double bx, double by) { return sqrt((bx - ax) * (bx - ax) + (by - ay) * (by - ay)); } double f(int i, int j) { return dist(0, 0, a, ap[i]) + dist(a, ap[i], b, bp[j]) + bt[j]; } int main() { scanf( %d%d%d%d , &n, &m, &a, &b); for (int i = 0; i < n; i++) scanf( %d , &ap[i]); for (int i = 0; i < m; i++) scanf( %d , &bp[i]); for (int i = 0; i < m; i++) { scanf( %d , &bt[i]); l = 0, r = n - 1; while (r - l >= 3) { m1 = l + (r - l) / 3; m2 = r - (r - l) / 3; if (f(m1, i) < f(m2, i)) r = m2; else l = m1; } for (int j = l; j <= r; j++) { if (f(j, i) < ans) ans = f(j, i), minap = j, minbp = i; } } printf( %d %d , minap + 1, minbp + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100 * 1000 + 5; int n, m, cnt; short int mark[N]; bool visited[N]; vector<int> in[N], out[N], comp[N]; void input() { cin.tie(0); cin >> n >> m; int v, u; for (int i = 0; i < m; i++) { cin >> v >> u; v--, u--; out[v].push_back(u); in[u].push_back(v); } return; } void getComp(int v) { visited[v] = true; for (int u : in[v]) if (!visited[u]) getComp(u); for (int u : out[v]) if (!visited[u]) getComp(u); comp[cnt].push_back(v); return; } bool isDAG(int v) { bool res = true; mark[v]++; for (int u : out[v]) if (!mark[u]) res &= isDAG(u); else if (mark[u] == 1) return false; mark[v]++; return res; } void solve() { for (int i = 0; i < n; i++) if (!visited[i]) { getComp(i); cnt++; } for (int i = 0; i < cnt; i++) { bool check = true; for (int v : comp[i]) if (!mark[v]) check &= isDAG(v); if (check) n--; } } int main() { ios::sync_with_stdio(false); input(); solve(); cout << n << endl; return 0; }
|
`include "sdio_defines.v"
module sdio_device_phy (
//input clk,
input rst,
//Configuration
input spi_phy,
input sd1_phy,
input sd4_phy,
//Data Link Interface
output cmd_phy_idle,
output reg cmd_phy,
output reg cmd_stb,
output reg cmd_crc_good_stb,
output reg [5:0] cmd,
output reg [31:0] cmd_arg,
input [127:0] rsps,
input [7:0] rsps_len,
input rsps_fail,
//XXX: Need to hook this up
input interrupt,
//XXX: Need to hook this up
input read_wait,
//FPGA Interface
output ddr_en,
input sdio_clk,
input sdio_cmd_in,
output reg sdio_cmd_out,
output reg sdio_cmd_dir,
//XXX: Need to hook this up
input [3:0] sdio_data_in,
output [3:0] sdio_data_out,
output sdio_data_dir
);
//Local Parameters
localparam IDLE = 4'h0;
localparam READ_COMMAND = 4'h1;
localparam RESPONSE_DIR_BIT = 4'h2;
localparam RESPONSE = 4'h3;
localparam RESPONSE_CRC = 4'h4;
localparam RESPONSE_FINISHED = 4'h5;
//Local Registers/Wires
reg [3:0] state;
reg [3:0] phy_mode;
reg [7:0] bit_count;
reg txrx_dir;
reg [7:0] cmd_crc;
wire [6:0] crc;
wire busy;
wire crc_bit;
reg crc_hold;
reg crc_rst;
reg [127:0] lcl_rsps;
//Submodules
crc7 crc_gen (
.clk (sdio_clk ),
.rst (crc_rst ),
.bit (crc_bit ),
.crc (crc ),
.hold (crc_hold )
);
//Asynchronous Logic
assign busy = ((state != IDLE) || !sdio_cmd_in);
assign crc_bit = sdio_cmd_dir ? sdio_cmd_out: sdio_cmd_in;
assign cmd_phy_idle = !busy;
//Synchronous Logic
//XXX: this clock should probably be sdio_clk
always @ (posedge sdio_clk) begin
if (rst) begin
//Start out in SPI mode
bit_count <= 0;
txrx_dir <= 0;
state <= IDLE;
cmd_stb <= 0;
cmd <= 0;
cmd_arg <= 0;
cmd_crc <= 0;
sdio_cmd_out <= 1;
sdio_cmd_dir <= 0;
crc_hold <= 0;
crc_rst <= 1;
lcl_rsps <= 0;
end
else begin
//strobes
cmd_stb <= 0;
cmd_crc_good_stb<= 0;
crc_rst <= 0;
//Incrementing bit count
if (busy) begin
bit_count <= bit_count + 1;
end
else begin
bit_count <= 0;
end
case (state)
IDLE: begin
sdio_cmd_out <= 1;
sdio_cmd_dir <= 0;
crc_hold <= 0;
crc_rst <= 1;
//Detect beginning of transaction when the command line goes low
if (!sdio_cmd_in) begin
//New Command Detected
state <= READ_COMMAND;
end
end
READ_COMMAND: begin
if (bit_count == `SDIO_C_BIT_TXRX_DIR)
txrx_dir <= sdio_cmd_in;
else if ((bit_count >= `SDIO_C_BIT_CMD_START) && (bit_count <= `SDIO_C_BIT_CMD_END))
cmd <= {cmd[4:0], sdio_cmd_in};
else if ((bit_count >= `SDIO_C_BIT_ARG_START) && (bit_count <= `SDIO_C_BIT_ARG_END))
cmd_arg <= {cmd_arg[30:0], sdio_cmd_in};
else if ((bit_count >= `SDIO_C_BIT_CRC_START) && (bit_count <= `SDIO_C_BIT_CRC_END))
cmd_crc <= {cmd_crc[5:0], sdio_cmd_in};
else begin //Last Bit
if (cmd_crc == crc)
cmd_crc_good_stb <= 1;
crc_rst <= 1;
cmd_stb <= 1;
bit_count <= 0;
sdio_cmd_dir <= 1;
sdio_cmd_out <= 0;
state <= RESPONSE_DIR_BIT;
end
end
RESPONSE_DIR_BIT: begin
sdio_cmd_out <= 0; //Direction From Device to Host
bit_count <= 0;
state <= RESPONSE;
lcl_rsps <= rsps;
end
RESPONSE: begin
sdio_cmd_out <= lcl_rsps[127];
lcl_rsps <= {lcl_rsps[126:0], 1'b0};
if (bit_count >= rsps_len) begin
state <= RESPONSE_CRC;
bit_count <= 0;
crc_hold <= 1;
end
end
RESPONSE_CRC: begin
sdio_cmd_out <= crc[6];
cmd_crc <= {crc[5:0], 1'b0};
if (bit_count >= 8'h7) begin
state <= RESPONSE_FINISHED;
end
end
RESPONSE_FINISHED: begin
sdio_cmd_out <= 1'b1;
state <= IDLE;
end
default: begin
sdio_cmd_dir <= 0;
state <= IDLE;
end
endcase
if (rsps_fail) begin
//Do not respond when we detect a fail
state <= IDLE;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename S, typename T> ostream& operator<<(ostream& out, pair<S, T> const& p) { out << ( << p.first << , << p.second << ) ; return out; } template <typename T> ostream& operator<<(ostream& out, vector<T> const& v) { long long l = v.size(); for (long long i = 0; i < l - 1; i++) out << v[i] << ; if (l > 0) out << v[l - 1]; return out; } template <typename T> void trace(const char* name, T&& arg1) { cout << name << : << arg1 << n ; } template <typename T, typename... Args> void trace(const char* names, T&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; trace(comma + 1, args...); } int n, m; int a[200], b[200]; vector<int> ans; bool check(int no) { for (int i = 0; i < n; i++) { if (a[i] <= no and b[i] >= no) { return true; } } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i] >> b[i]; } int c = 0; for (int i = 1; i <= m; i++) { if (check(i) == false) { c++; ans.push_back(i); } } cout << c << n ; cout << ans; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module pc2(
input [0:55] cd,
output [0:47] k
);
assign k = {cd[13], cd[16], cd[10], cd[23], cd[0], cd[4], cd[2], cd[27], cd[14], cd[5], cd[20], cd[9], cd[22], cd[18], cd[11], cd[3], cd[25], cd[7], cd[15], cd[6], cd[26], cd[19], cd[12], cd[1], cd[40], cd[51], cd[30], cd[36], cd[46], cd[54], cd[29], cd[39], cd[50], cd[44], cd[32], cd[47], cd[43], cd[48], cd[38], cd[55], cd[33], cd[52], cd[45], cd[41], cd[49], cd[35], cd[28], cd[31]};
endmodule
|
//# 3 inputs
//# 6 outputs
//# 14 D-type flipflops
//# 44 inverters
//# 75 gates (31 ANDs + 9 NANDs + 16 ORs + 19 NORs)
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s298(GND,VDD,CK,G0,G1,G117,G118,G132,G133,G2,G66,G67);
input GND,VDD,CK,G0,G1,G2;
output G117,G132,G66,G118,G133,G67;
wire G10,G29,G11,G30,G12,G34,G13,G39,G14,G44,G15,G56,G16,G86,G17,G92,G18,G98,
G19,G102,G20,G107,G21,G113,G22,G119,G23,G125,G28,G130,G38,G40,G45,G46,G50,
G51,G54,G55,G59,G60,G64,II155,II158,G76,G82,G87,G91,G93,G96,G99,G103,G108,
G112,G114,II210,II213,G120,G124,G121,II221,G126,G131,G127,II229,II232,
II235,II238,G26,G27,G31,G32,G33,G35,G36,G37,G42,G41,G48,G47,G49,G52,G57,
G61,G58,G65,G62,G63,G74,G75,G88,G89,G90,G94,G95,G100,G105,G104,G110,G109,
G111,G115,G122,G123,G128,G129,G24,G25,G68,G69,G70,G71,G72,G73,G77,G78,G79,
G80,G81,G83,G84,G85,G43,G97,G101,G106,G116,G53;
dff DFF_0(CK,G10,G29);
dff DFF_1(CK,G11,G30);
dff DFF_2(CK,G12,G34);
dff DFF_3(CK,G13,G39);
dff DFF_4(CK,G14,G44);
dff DFF_5(CK,G15,G56);
dff DFF_6(CK,G16,G86);
dff DFF_7(CK,G17,G92);
dff DFF_8(CK,G18,G98);
dff DFF_9(CK,G19,G102);
dff DFF_10(CK,G20,G107);
dff DFF_11(CK,G21,G113);
dff DFF_12(CK,G22,G119);
dff DFF_13(CK,G23,G125);
not NOT_0(G28,G130);
not NOT_1(G38,G10);
not NOT_2(G40,G13);
not NOT_3(G45,G12);
not NOT_4(G46,G11);
not NOT_5(G50,G14);
not NOT_6(G51,G23);
not NOT_7(G54,G11);
not NOT_8(G55,G13);
not NOT_9(G59,G12);
not NOT_10(G60,G22);
not NOT_11(G64,G15);
not NOT_12(II155,G16);
not NOT_13(G66,II155);
not NOT_14(II158,G17);
not NOT_15(G67,II158);
not NOT_16(G76,G10);
not NOT_17(G82,G11);
not NOT_18(G87,G16);
not NOT_19(G91,G12);
not NOT_20(G93,G17);
not NOT_21(G96,G14);
not NOT_22(G99,G18);
not NOT_23(G103,G13);
not NOT_24(G108,G112);
not NOT_25(G114,G21);
not NOT_26(II210,G18);
not NOT_27(G117,II210);
not NOT_28(II213,G19);
not NOT_29(G118,II213);
not NOT_30(G120,G124);
not NOT_31(G121,G22);
not NOT_32(II221,G2);
not NOT_33(G124,II221);
not NOT_34(G126,G131);
not NOT_35(G127,G23);
not NOT_36(II229,G0);
not NOT_37(G130,II229);
not NOT_38(II232,G1);
not NOT_39(G131,II232);
not NOT_40(II235,G20);
not NOT_41(G132,II235);
not NOT_42(II238,G21);
not NOT_43(G133,II238);
and AND2_0(G26,G28,G50);
and AND2_1(G27,G51,G28);
and AND3_0(G31,G10,G45,G13);
and AND2_2(G32,G10,G11);
and AND2_3(G33,G38,G46);
and AND3_1(G35,G10,G11,G12);
and AND2_4(G36,G38,G45);
and AND2_5(G37,G46,G45);
and AND2_6(G42,G40,G41);
and AND4_0(G48,G45,G46,G10,G47);
and AND3_2(G49,G50,G51,G52);
and AND4_1(G57,G59,G11,G60,G61);
and AND2_7(G58,G64,G65);
and AND4_2(G62,G59,G11,G60,G61);
and AND2_8(G63,G64,G65);
and AND3_3(G74,G12,G14,G19);
and AND3_4(G75,G82,G91,G14);
and AND2_9(G88,G14,G87);
and AND2_10(G89,G103,G96);
and AND2_11(G90,G91,G103);
and AND2_12(G94,G93,G13);
and AND2_13(G95,G96,G13);
and AND3_5(G100,G99,G14,G12);
and AND3_6(G105,G103,G108,G104);
and AND2_14(G110,G108,G109);
and AND2_15(G111,G10,G112);
and AND2_16(G115,G114,G14);
and AND2_17(G122,G120,G121);
and AND2_18(G123,G124,G22);
and AND2_19(G128,G126,G127);
and AND2_20(G129,G131,G23);
or OR4_0(G24,G38,G46,G45,G40);
or OR3_0(G25,G38,G11,G12);
or OR4_1(G68,G11,G12,G13,G96);
or OR2_0(G69,G103,G18);
or OR2_1(G70,G103,G14);
or OR3_1(G71,G82,G12,G13);
or OR2_2(G72,G91,G20);
or OR2_3(G73,G103,G20);
or OR4_2(G77,G112,G103,G96,G19);
or OR2_4(G78,G108,G76);
or OR2_5(G79,G103,G14);
or OR2_6(G80,G11,G14);
or OR2_7(G81,G12,G13);
or OR4_3(G83,G11,G12,G13,G96);
or OR3_2(G84,G82,G91,G14);
or OR3_3(G85,G91,G96,G17);
nand NAND3_0(G41,G12,G11,G10);
nand NAND3_1(G43,G24,G25,G28);
nand NAND4_0(G52,G13,G45,G46,G10);
nand NAND4_1(G65,G59,G54,G22,G61);
nand NAND4_2(G97,G83,G84,G85,G108);
nand NAND4_3(G101,G68,G69,G70,G108);
nand NAND2_0(G106,G77,G78);
nand NAND4_4(G109,G71,G72,G73,G14);
nand NAND4_5(G116,G79,G80,G81,G108);
nor NOR2_0(G29,G10,G130);
nor NOR4_0(G30,G31,G32,G33,G130);
nor NOR4_1(G34,G35,G36,G37,G130);
nor NOR2_1(G39,G42,G43);
nor NOR3_0(G44,G48,G49,G53);
nor NOR2_2(G47,G50,G40);
nor NOR2_3(G53,G26,G27);
nor NOR3_1(G56,G57,G58,G130);
nor NOR2_4(G61,G14,G55);
nor NOR4_2(G86,G88,G89,G90,G112);
nor NOR3_2(G92,G94,G95,G97);
nor NOR2_5(G98,G100,G101);
nor NOR2_6(G102,G105,G106);
nor NOR2_7(G104,G74,G75);
nor NOR2_8(G107,G110,G111);
nor NOR2_9(G112,G62,G63);
nor NOR2_10(G113,G115,G116);
nor NOR3_3(G119,G122,G123,G130);
nor NOR3_4(G125,G128,G129,G130);
endmodule
|
//
// Copyright (c) 2001 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - From PR 272 reported by Lennart Augustsson <>
module test;
reg clk;
reg [31:0] x;
reg [31:0] y;
reg error;
always@(posedge clk)
x <= -y;
always #2 clk = ~clk;
initial
begin
clk = 0;
error = 0;
y = 0;
#10;
if( x !== 32'h0)
begin
error = 1;
$display("FAILED - X should still be 0, and it's not");
end
#10;
y = 32'h11111111;
#10;
if(x !== 32'heeee_eeef)
begin
error = 1;
$display("FAILED - X should still be EEEE_EEEF, rather x=%h",x);
end
#10;
if(error == 0)
$display("PASSED");
$finish ;
end
endmodule
|
// Test mixed type/width case expressions inside a constant function
module constfunc13();
function [2:0] lookup1(input signed [2:0] value);
begin
case (value)
4'sb0100 : lookup1 = 1;
3'sb100 : lookup1 = 2;
2'sb10 : lookup1 = 3;
default : lookup1 = 4;
endcase
$display("case = %d", lookup1);
end
endfunction
function [2:0] lookup2(input signed [2:0] value);
begin
case (value)
4'b1100 : lookup2 = 1;
3'sb100 : lookup2 = 2;
2'sb10 : lookup2 = 3;
default : lookup2 = 4;
endcase
$display("case = %d", lookup2);
end
endfunction
function [2:0] lookup3(input real value);
begin
case (value)
4'b0001 : lookup3 = 1;
3'sb010 : lookup3 = 2;
2'sb11 : lookup3 = 3;
default : lookup3 = 4;
endcase
$display("case = %d", lookup3);
end
endfunction
function [2:0] lookup4(input signed [2:0] value);
begin
case (value)
4'b0110 : lookup4 = 1;
3'sb110 : lookup4 = 2;
-1.0 : lookup4 = 3;
default : lookup4 = 4;
endcase
$display("case = %d", lookup4);
end
endfunction
localparam res11 = lookup1(3'sb100);
localparam res12 = lookup1(3'sb110);
localparam res13 = lookup1(3'sb010);
localparam res21 = lookup2(3'sb100);
localparam res22 = lookup2(3'sb010);
localparam res23 = lookup2(3'sb110);
localparam res31 = lookup3( 1.0);
localparam res32 = lookup3( 2.0);
localparam res33 = lookup3(-1.0);
localparam res34 = lookup3( 1.5);
localparam res41 = lookup4(3'sb110);
localparam res42 = lookup4(3'sb111);
localparam res43 = lookup4(3'sb011);
reg failed = 0;
initial begin
$display("case = %d", res11); if (res11 != 2) failed = 1;
$display("case = %d", res12); if (res12 != 3) failed = 1;
$display("case = %d", res13); if (res13 != 4) failed = 1;
$display("");
$display("case = %d", res21); if (res21 != 2) failed = 1;
$display("case = %d", res22); if (res22 != 3) failed = 1;
$display("case = %d", res23); if (res23 != 4) failed = 1;
$display("");
$display("case = %d", res31); if (res31 != 1) failed = 1;
$display("case = %d", res32); if (res32 != 2) failed = 1;
$display("case = %d", res33); if (res33 != 3) failed = 1;
$display("case = %d", res34); if (res34 != 4) failed = 1;
$display("");
$display("case = %d", res41); if (res41 != 2) failed = 1;
$display("case = %d", res42); if (res42 != 3) failed = 1;
$display("case = %d", res43); if (res43 != 4) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<double, double> > a; pair<double, double> cur; double r; void findmax(pair<double, double> p) { double y = sqrt(2 * r * 2 * r - abs(p.first - cur.first) * abs(p.first - cur.first)); y += p.second; cur.second = max(cur.second, y); } void doit(double x) { for (double k = 0; k < a.size(); k++) { if (abs(x - a[k].first) <= 2 * r) findmax(a[k]); } a.push_back(cur); } int main() { double x, n; cin >> n >> r; for (double k = 0; k < n; k++) { cin >> x; cur.first = x; cur.second = r; doit(x); } for (double k = 0; k < a.size(); k++) cout << setprecision(17) << a[k].second << ; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 14:40:47 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_1_stub.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 4e18; const long double pai = acos(-1); int n, q, ans; set<pair<pair<int, int>, int> > s; int main() { scanf( %d%d , &n, &q); ans = n; s.insert({{1, n}, 1}); while (q--) { int l, r, x; scanf( %d%d%d , &l, &r, &x), x--; auto it = s.lower_bound({{l, -1}, -1}); if (it == s.end() || it->first.first > l) it--; vector<pair<pair<int, int>, int> > add; while (it != s.end()) { int L = it->first.first, R = it->first.second, old = it->second; if (L < l) add.push_back({{L, l - 1}, old}); if (R > r) add.push_back({{r + 1, R}, old}); it = s.erase(it); ans -= (R - L + 1) * old; if (it == s.end() || it->first.first > r) break; } for (auto u : add) { int L = u.first.first, R = u.first.second, old = u.second; ans += (R - L + 1) * old; s.insert(u); } s.insert({{l, r}, x}); ans += (r - l + 1) * x; printf( %d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const long long llinf = (long long)3e18; const int N = (int)1e6 + 111; const long double PI = (long double)acos(-1); int cnt1[N], cnt[N]; int main() { int t, x, mx = 0, len = 0, n, m; scanf( %d , &t); for (int i = 0; i < t; i++) { scanf( %d , &x); cnt[x]++; mx = max(mx, x); } n = mx; for (int i = 1; i < mx; i++) if (4 * i != cnt[i]) { len = i - 1; break; } for (n = 1; n * n <= t; n++) if (t % n == 0) { m = t / n; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (min(min(i, n - 1 - i), min(j, m - 1 - j)) == len && max(i, n - 1 - i) + max(j, n - 1 - j) == mx) { for (int cur = 0; cur <= mx; cur++) cnt1[cur] = 0; bool ok = true; for (int ii = 0; ii < n; ii++) for (int jj = 0; jj < m; jj++) cnt1[abs(i - ii) + abs(j - jj)]++; for (int cur = 0; cur <= mx; cur++) if (cnt1[cur] != cnt[cur]) ok = false; if (ok) { printf( %d %d n%d %d , n, m, i + 1, j + 1); return 0; } } } printf( -1 ); }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void Read(T &x) { int f = 1; char t = getchar(); while (t < 0 || t > 9 ) { if (t == - ) f = -1; t = getchar(); } x = 0; while (t >= 0 && t <= 9 ) { x = x * 10 + t - 0 ; t = getchar(); } x *= f; } template <class T> inline void chkmin(T &x, T y) { if (x > y) x = y; } template <class T> inline void chkmax(T &x, T y) { if (x < y) x = y; } const int maxn = 200005; const double inf = 2e18; const double pi = acos(-1.0); struct point { long double x, y; point() {} point(long double x, long double y) : x(x), y(y) {} void read() { cin >> x >> y; } }; point operator+(const point &a, const point &b) { return point(a.x + b.x, a.y + b.y); } point operator-(const point &a, const point &b) { return point(a.x - b.x, a.y - b.y); } point operator*(const point &a, long double v) { return point(a.x * v, a.y * v); } point operator/(const point &a, long double v) { return point(a.x / v, a.y / v); } long double operator^(const point &a, const point &b) { return a.x * b.y - a.y * b.x; } int n; point P, g[maxn]; long double dis(point &a, point &b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } long double maxr = -inf, minr = inf; void calc(point &a, point &b) { long double A = dis(a, P), B = dis(b, P), C = dis(a, b); long double area = (a - P) ^ (b - P); long double Height = area * area / C; if (A < B) swap(A, B); if (A > B + C) return; chkmax(maxr, Height); chkmin(minr, Height); } void input() { Read(n); P.read(); for (register int i = 1; i <= n; i++) g[i].read(); g[0] = g[n]; for (register int i = 1; i <= n; i++) calc(g[i], g[i - 1]); } void solve() { for (register int i = 1; i <= n; i++) { chkmax(maxr, dis(g[i], P)); chkmin(minr, dis(g[i], P)); } printf( %.18lf n , (double)(maxr - minr) * pi); } int main() { input(); solve(); return 0; }
|
/* Made by brandon for brandon.
* I guarantee absolutely nothing and am not liable for any damages.
*/
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0_Nano(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// EPCS //////////
EPCS_ASDO,
EPCS_DATA0,
EPCS_DCLK,
EPCS_NCSO,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// 2x13 GPIO Header //////////
GPIO_2,
GPIO_2_IN,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0,
GPIO_0_IN,
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
GPIO_1,
GPIO_1_IN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// EPCS //////////
output EPCS_ASDO;
input EPCS_DATA0;
output EPCS_DCLK;
output EPCS_NCSO;
//////////// Accelerometer and EEPROM //////////
output G_SENSOR_CS_N;
input G_SENSOR_INT;
output I2C_SCLK;
inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// 2x13 GPIO Header //////////
inout [12:0] GPIO_2;
input [2:0] GPIO_2_IN;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0;
inout [1:0] GPIO_0_IN;
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
// Stuff about more "natural" wires. ;)
wire [0:3] seconds;
wire [0:3] tens_seconds;
wire [0:3] minutes;
wire [0:3] tens_minutes;
wire [0:3] hours;
wire [0:3] tens_hours;
wire AM;
wire PM;
wire seconds_tick;
// What the wires actually are...
assign GPIO_0_IN[1] = seconds[0];
assign GPIO_0[1:3] = seconds[1:3];
assign GPIO_0[4:7] = tens_seconds[0:3];
assign GPIO_0[8:11] = minutes[0:3];
assign GPIO_0[12:15] = tens_minutes[0:3];
assign GPIO_0[16:19] = hours[0:3];
assign GPIO_0[20:23] = tens_hours[0:3];
assign GPIO_0[24] = AM;
assign GPIO_0[25] = PM;
assign GPIO_0[26] = seconds_tick;
//=======================================================
// Structural coding
//=======================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_SYMBOL_V
`define SKY130_FD_SC_MS__O31A_SYMBOL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct l { int index; int depth; int color; }; int a[100001]; struct BFSearch { vector<pair<l, vector<int> > > adj; queue<l> k; void clear1() { for (int i = 0; i < adj.size(); i++) { adj[i].first.color = 0; adj[i].first.depth = -1; } } void bfs(int i) { if (i > adj.size() - 1) return; l o; int p; adj[i].first.color = 0; adj[i].first.depth = 0; k.push(adj[i].first); while (k.size() != 0) { o = k.front(); k.pop(); for (int i = 0; i < adj[o.index].second.size(); i++) { p = adj[o.index].second[i]; if (adj[p].first.color == 0) { adj[p].first.color = 1; adj[p].first.depth = o.depth + 1; k.push(adj[p].first); } } adj[o.index].first.color = 2; } } }; int main() { pair<l, vector<int> > op; BFSearch k; int n, temp; l p; p.depth = -1; p.color = 0; cin >> n; vector<int> x; for (int i = 0; i < n; i++) { op.second = x; p.index = i; op.first = p; k.adj.push_back(op); } for (int i = 1; i < n; i++) { cin >> temp; k.adj[i].second.push_back(temp - 1); k.adj[temp - 1].second.push_back(i); } k.bfs(0); for (int i = 0; i < k.adj.size(); i++) { a[k.adj[i].first.depth]++; } long sum = 0; for (int i = 0; i < k.adj.size(); i++) { if (a[i] % 2 == 1) sum += 1; } cout << sum; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes a NTSC video stream. *
* *
******************************************************************************/
module altera_up_video_itu_656_decoder (
// Inputs
clk,
reset,
TD_DATA,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] TD_DATA;
input ready;
// Bidirectional
// Outputs
output [15: 0] data;
output startofpacket;
output endofpacket;
output valid;
//output reg [15: 0] data;
//output reg startofpacket;
//output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire timing_reference; // 4-Bytes: FF 00 00 XY
wire start_of_an_even_line;
wire start_of_an_odd_line;
wire [ 7: 0] last_data;
// Internal Registers
reg [ 7: 0] io_register;
reg [ 7: 0] video_shift_reg [ 5: 1];
reg possible_timing_reference;
reg [ 6: 1] active_video;
reg last_line;
reg [15: 0] internal_data;
reg internal_startofpacket;
reg internal_valid;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
io_register <= TD_DATA;
// Output Registers
/*
always @ (posedge clk)
data <= {video_shift_reg[5], video_shift_reg[4]};
always @ (posedge clk)
begin
if (~last_line & start_of_an_odd_line)
startofpacket <= 1'b1;
else if (last_line & start_of_an_even_line)
startofpacket <= 1'b1;
else if (valid)
startofpacket <= 1'b0;
end
always @(posedge clk)
begin
if (active_video[5])
valid <= valid ^ 1'b1;
else
valid <= 1'b0;
end
*/
// Internal Registers
always @ (posedge clk)
begin
for (i = 5; i > 1; i = i - 1)
video_shift_reg[i] <= video_shift_reg[(i - 1)];
video_shift_reg[1] <= io_register;
end
always @(posedge clk)
begin
if ((video_shift_reg[3] == 8'hFF) &&
(video_shift_reg[2] == 8'h00) &&
(video_shift_reg[1] == 8'h00))
possible_timing_reference <= 1'b1;
else
possible_timing_reference <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
active_video <= 6'h00;
else if (start_of_an_even_line | start_of_an_odd_line)
active_video <= {active_video[5:1], 1'b1};
else if (timing_reference == 1'b1)
active_video <= 6'h00;
else
active_video[6:2] <= active_video[5:1];
end
always @ (posedge clk)
begin
if (reset)
last_line <= 1'b0;
else if (start_of_an_odd_line)
last_line <= 1'b1;
else if (start_of_an_even_line)
last_line <= 1'b0;
end
always @ (posedge clk)
internal_data <= {video_shift_reg[5], video_shift_reg[4]};
always @ (posedge clk)
begin
if (~last_line & start_of_an_odd_line)
internal_startofpacket <= 1'b1;
else if (last_line & start_of_an_even_line)
internal_startofpacket <= 1'b1;
else if (valid)
internal_startofpacket <= 1'b0;
end
always @(posedge clk)
begin
if (active_video[5])
internal_valid <= internal_valid ^ 1'b1;
else
internal_valid <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign last_data = video_shift_reg[1];
assign timing_reference =
( possible_timing_reference &
( (last_data[5] ^ last_data[4]) == last_data[3]) &
( (last_data[6] ^ last_data[4]) == last_data[2]) &
( (last_data[6] ^ last_data[5]) == last_data[1]) &
( (last_data[6] ^ last_data[5] ^ last_data[4]) == last_data[0])
);
assign start_of_an_even_line = timing_reference &
last_data[6] & ~last_data[5] & ~last_data[4];
assign start_of_an_odd_line = timing_reference &
~last_data[6] & ~last_data[5] & ~last_data[4];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_decoder_add_endofpacket Add_EndofPacket (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (1'b0),
.stream_in_valid (internal_valid),
.stream_out_ready (ready),
// Bidirectional
// Outputs
.stream_in_ready (),
.stream_out_data (data),
.stream_out_startofpacket (startofpacket),
.stream_out_endofpacket (endofpacket),
.stream_out_valid (valid)
);
defparam
Add_EndofPacket.DW = 15;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string str, s = QWERTYUIOPASDFGHJKLZXCVBNM ; cin >> str; set<char> m; long long result = 1; for (int i = 0; i < str.size(); i++) { if (str[i] == ? ) { if (i == 0) { result *= 9; } else result *= 10; } else if (s.find(str[i]) != string::npos) { if (i == 0) { result *= 9; m.insert(str[i]); } else { if (m.find(str[i]) == m.end()) { result *= (10 - m.size()); m.insert(str[i]); } } } } cout << result << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_1_V
`define SKY130_FD_SC_HVL__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_1_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( constant) statement_1 else statement_2 ;
module main ;
reg [3:0] value1 ;
initial
begin
value1 = 0;
# 5 ;
if(value1 != 4'd4)
$display("FAILED - always 3.1.5C always if ( constant) statementelse ;");
else
$display("PASSED");
$finish;
end
always if( 1'b1) begin
# 1;
value1 = value1 + 1;
end
else value1 = 0 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, fl = 1; char st = getchar(); while (st < 0 || st > 9 ) { if (st == - ) fl = -1; st = getchar(); } while (st >= 0 && st <= 9 ) x = x * 10 + st - 0 , st = getchar(); return x * fl; } const int N = 1e6 + 10, mod = 1e9 + 9; int n, b, w; long long ans, fac[8005], invfac[8005]; inline long long ksm(long long x, long long y) { long long res = 1; while (y) { if (y & 1) res = res * x % mod; x = x * x % mod; y >>= 1; } return res; } inline long long C(int x, int y) { return fac[x] * invfac[y] % mod * invfac[x - y] % mod; } int main() { ans = 1; n = read(); w = read(); b = read(); fac[0] = 1; fac[1] = 1; for (int i = 2; i <= 8000; i++) fac[i] = fac[i - 1] * i % mod; invfac[0] = invfac[1] = 1; invfac[8000] = ksm(fac[8000], mod - 2); for (int i = 7999; i >= 2; i--) { invfac[i] = invfac[i + 1] * (i + 1) % mod; } ans = fac[w] * fac[b] % mod; ans = ans * (w - 1) % mod; ans = ans * C(w + b - 3, n - 3) % mod; printf( %lld , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1P_PP_SYMBOL_V
`define SKY130_FD_SC_LP__ISO1P_PP_SYMBOL_V
/**
* iso1p: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input KAPWR,
input VPB ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1P_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////
////
////
//// AES CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa,
//// Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module shift_rows
(
//OUTPUTS
output [127 : 0] data_out_enc, // Result after Shift Rows operation - enc
output [127 : 0] data_out_dec, // Result after Shift Rows operation - dec
//INPUTS
input [127 : 0] data_in // Input Bus
);
localparam integer BUS_WIDTH = 128; // Bus Width
localparam integer ST_WORD = 8; // Data Size of word in State MAtrix
localparam integer ST_LINE = 4; // Number of Lines of State Matrix
localparam integer ST_COL = 4; // Number of Columns of State Matrix
wire [ST_WORD - 1 : 0] state[0 : ST_LINE - 1][0 : ST_COL - 1];
wire [ST_WORD - 1 : 0] state_sft_l[0 : ST_LINE - 1][0 : ST_COL - 1];
wire [ST_WORD - 1 : 0] state_sft_r[0 : ST_LINE - 1][0 : ST_COL - 1];
//=====================================================================================
// State Matrix generation
//=====================================================================================
generate
genvar l,c;
for(l = 0; l < ST_LINE; l = l + 1)
begin:SMG
for(c = 0; c < ST_COL; c = c + 1)
begin:BLOCK
assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
end
end
endgenerate
//=====================================================================================
// Shift Row operation
//=====================================================================================
generate
genvar l1,c1;
for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
begin:SRO
for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
begin:BLOCK
assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
end
end
endgenerate
//=====================================================================================
// State Matrix to Bus Output Transformation
//=====================================================================================
generate
genvar l2,c2;
for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
begin:SMBOT
for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
begin:BLOCK
assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_V
|
`timescale 1 ns / 1 ps
`include "example_core_lite_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module example_core_lite_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Mod = 1000000007; int N; struct M { int a[250][250]; M() { memset(a, 0, sizeof(a)); } }; M I() { M res; for (int i = 0; i < N; i++) res.a[i][i] = 1; return res; } M operator*(const M& a, const M& b) { M ans; for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) for (int k = 0; k < N; k++) ans.a[i][j] = (ans.a[i][j] + 1ll * a.a[i][k] * b.a[k][j]) % Mod; return ans; } int k, m; int id(int x, int y) { return x * (1 << m) + y; } M fpow(M a, int b) { M ans = I(), t = a; while (b) { if (b & 1) ans = ans * t; t = t * t; b >>= 1; } return ans; } int cnt(int x) { int ans = 0; while (x) { ans += (x & 1); x >>= 1; } return ans; } int main() { int n; scanf( %d %d %d , &n, &k, &m); N = (k + 1) * (1 << m); M S, T; S.a[0][0] = 1; for (int c = 0; c <= k; c++) for (int s = 0; s < (1 << m); s++) { T.a[id(c, s)][id(c, s >> 1)]++; if (c < k) T.a[id(c, s)][id(c + 1, (s >> 1) | (1 << (m - 1)))] += cnt(s) + 1; } S = S * fpow(T, n); int ans = 0; for (int s = 0; s < (1 << m); s++) ans = (ans + S.a[0][id(k, s)]) % Mod; printf( %d n , ans); return 0; }
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_scan_mux.v
//
// *Module Description:
// Generic mux for scan mode
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_scan_mux (
// OUTPUTs
data_out, // Scan mux data output
// INPUTs
data_in_scan, // Selected data input for scan mode
data_in_func, // Selected data input for functional mode
scan_mode // Scan mode
);
// OUTPUTs
//=========
output data_out; // Scan mux data output
// INPUTs
//=========
input data_in_scan; // Selected data input for scan mode
input data_in_func; // Selected data input for functional mode
input scan_mode; // Scan mode
//=============================================================================
// 1) SCAN MUX
//=============================================================================
assign data_out = scan_mode ? data_in_scan : data_in_func;
endmodule // omsp_scan_mux
|
#include <bits/stdc++.h> long long prod_dig(long long n) { long long prod = 1; int a; while (n) { a = n % 10; if (a) { prod *= a; } n /= 10; } return prod; } int arr[10][1000000 + 1]; int main() { int t; for (int i = 1; i <= 1000000; i++) { t = i; while (t / 10) { t = prod_dig(t); } for (int j = 0; j < 10; j++) { arr[j][i] = arr[j][i - 1]; } arr[t][i]++; } int Q, l, r, x, key; scanf( %d , &Q); while (Q--) { scanf( %d%d%d , &l, &r, &key); printf( %d n , arr[key][r] - arr[key][l - 1]); } }
|
#include <bits/stdc++.h> using namespace std; int n, l, v1, v2, k; int main() { cin >> n >> l >> v1 >> v2 >> k; long double T = 0; long double S = l, t1, t2, d; int m = ((n + k - 1) / k); S = S / ((long double)(m) - ((long double)(m - 1) * (v2 - v1)) / (v2 + v1)); t1 = S / v2; t2 = (S * (v2 - v1)) / (v2 + v1) / v2; T = t1 * m + t2 * (m - 1); cout << fixed << setprecision(15) << T; }
|
module ADT7310 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_param="SPICounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPreset_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i({SPICounterPresetH_i, SPICounterPresetL_i})
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i(PeriodCounterPreset_i)
);
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of Instruction cache data rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_ram.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.6 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
//XLNX_MODIFIED change for block ram
//or1200_spram_2048x32 ic_ram0(
or1200_spram_2048x32_bw ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bomb.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bomb (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bomb.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bomb.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bomb.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include<bits/stdc++.h> using namespace std; const int P=1e9+7,N=209,iv=P+1>>1; int f[N][N],ans[N][N],d[N],sz[N],fa[N]; basic_string<int>g[N]; void dfs(int x,int y){ sz[x]=1,fa[x]=y; for(int i:g[x])if(i!=y)d[i]=d[x]+1,dfs(i,x),sz[x]+=sz[i]; } int qp(int a,int b){ int r=1; for(;b;b>>=1,a=a*1ll*a%P)if(b&1)r=r*1ll*a%P; return r; } int main(){ int n,i,j,k,u,w=0,o; scanf( %d ,&n); for(i=1;i<=n;++i){ memset(f,0,sizeof f); for(j=1;j<i;++j)f[0][j]=1,f[j][i+1]=0; for(j=1;j<i;++j)for(k=i-1;k>=j;--k)f[j][k]=(f[j-1][k]+f[j][k+1])*1ll*iv%P; for(j=1;j<i;++j)ans[i][j]=f[j][j]; ans[i][0]=1; } for(i=1;i<n;++i)scanf( %d%d ,&j,&k),g[j]+=k,g[k]+=j; for(i=1;i<=n;++i){ d[i]=0,dfs(i,0); for(j=1;j<i;++j){ u=d[j],k=j,o=sz[j]; while(1){ k=fa[k]; w=(w+(sz[k]-o)*1ll*ans[u][d[k]])%P; o=sz[k]; if(k==i)break; } } } printf( %lld ,w*1ll*qp(n,P-2)%P); return 0; }
|
`include "defines.v"
module regfile (
input wire rst,
input wire clk,
input wire we,
input wire[`RegAddrBus] waddr,
input wire[`RegBus] wdata,
input wire re1,
input wire[`RegAddrBus] raddr1,
output reg[`RegBus] rdata1,
input wire re2,
input wire[`RegAddrBus] raddr2,
output reg[`RegBus] rdata2
);
// 定义 32 * 32 的寄存器组
reg[`RegBus] regs[0 : `RegNum - 1];
// write
always @(posedge clk) begin
if (rst == `RstDisable) begin
// 0 号寄存器的值是 0，不能写入
if ((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
regs[waddr] <= wdata;
end
end
end
// read 1
always @(*) begin
// 读取的时候有很多的特殊状态
if (rst == `RstEnable) begin
rdata1 <= `ZeroWord;
end
else if (raddr1 == `RegNumLog2'b0) begin
rdata1 <= `ZeroWord;
end
else if ((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin
rdata1 <= wdata;
end
else if (re1 == `ReadEnable) begin
rdata1 <= regs[raddr1];
end
else begin
rdata1 <= `ZeroWord;
end
end
// read 2
always @(*) begin
if (rst == `RstEnable) begin
rdata2 <= `ZeroWord;
end
else if (raddr2 == `RegNumLog2'b0) begin
rdata2 <= `ZeroWord;
end
else if ((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `ReadEnable)) begin
rdata2 <= wdata;
end
else if (re2 == `ReadEnable) begin
rdata2 <= regs[raddr2];
end
else begin
rdata2 <= `ZeroWord;
end end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { unsigned long long int mino = LONG_MAX; unsigned long long int minc = LONG_MAX; unsigned long long int ans = 0; unsigned long long int n; cin >> n; unsigned long long int o[n], c[n]; for (unsigned long long int i = 0; i < n; i++) { unsigned long long int ora; cin >> ora; o[i] = ora; if (ora < mino) { mino = ora; } } for (unsigned long long int i = 0; i < n; i++) { unsigned long long int ca; cin >> ca; c[i] = ca; if (ca < minc) { minc = ca; } } for (unsigned long long int i = 0; i < n; i++) { unsigned long long int w = min(o[i] - mino, c[i] - minc); ans = ans + w; o[i] = o[i] - w; c[i] = c[i] - w; if (o[i] == mino) { ans = ans + c[i] - minc; } else { ans = ans + o[i] - mino; } } cout << ans << endl; } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module example_fadd_32ns_32ns_32_5_full_dsp
#(parameter
ID = 0,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
example_ap_fadd_3_full_dsp_32 example_ap_fadd_3_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, sum; int xx[10005], yy[10005], a[10005]; while (scanf( %d , &n) != EOF) { sum = 0; for (i = 0; i <= n; i++) { scanf( %d %d , &xx[i], &yy[i]); } for (i = 0; i < n; i++) { if (xx[i] == xx[i + 1] && yy[i + 1] > yy[i]) a[i] = 1; if (xx[i] < xx[i + 1] && yy[i + 1] == yy[i]) a[i] = 2; if (xx[i] == xx[i + 1] && yy[i + 1] < yy[i]) a[i] = 3; if (xx[i] > xx[i + 1] && yy[i + 1] == yy[i]) a[i] = 4; } for (i = 0; i < n - 1; i++) { if (a[i] > a[i + 1]) sum++; } printf( %d n , sum); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2_BLACKBOX_V
`define SKY130_FD_SC_LS__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2_BLACKBOX_V
|
#include <bits/stdc++.h> struct DSU { long long M[400005]; DSU(long long n) { for (long long i = 0; i < n; i++) { M[i] = i; } } long long find(long long x) { while (M[x] != x) { long long p = M[x]; M[x] = M[p]; x = p; } return x; } bool join(long long x, long long y) { long long xr = find(x); long long yr = find(y); if (xr == yr) { return false; } else { M[xr] = yr; return true; } } }; using namespace std; int main() { long long n, m, q; cin >> n >> m >> q; DSU dsu(n + m); long long z = n + m - 1; for (long long i = 0; i < q; i++) { long long r, c; cin >> r >> c; r--; c--; if (dsu.join(r, c + n)) z--; } cout << z; }
|
#include <bits/stdc++.h> const long long INF = 1e18; void swap(long long &a, long long &b) { long long temp; temp = a; a = b; b = temp; } using namespace std; void solve() { long long n, k, ans; cin >> n >> k; ans = n; for (long long i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i <= k) ans = min(ans, i); if (i <= k) ans = min(ans, n / i); } } cout << ans; } int main() { int t; cin >> t; while (t--) { solve(); cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_0_V
`define SKY130_FD_SC_LP__FA_0_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_0 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_0 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_0_V
|
#include <bits/stdc++.h> using namespace std; long long int arr[100005]; map<long long int, int> m; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %I64d , &arr[i]); } for (int i = 1; i <= n; i++) { arr[i] += arr[i - 1]; m[arr[i]]++; } int maxVal = 0; for (int i = 1; i <= n; i++) { maxVal = max(maxVal, m[arr[i - 1]]); } printf( %d , n - maxVal); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_PP_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRDLXTP_PP_SYMBOL_V
/**
* srdlxtp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; int node[101], h[101], perm[101], fav[101]; int getP(int c) { int p = node[c]; if (p < 0) return c; while (node[p] > 0) p = node[p]; return node[c] = p; } void join(int a, int b) { if (0) printf( join %d %d n , a, b); int pa = getP(a), pb = getP(b); if (pa == pb) { return; } if (h[pa] < h[pb]) { node[pa] = pb; h[pb] += h[pa]; } else { node[pb] = pa; h[pa] += h[pb]; } } void getNum() { int i; for (i = 0; i <= n; i++) { node[i] = -1; h[i] = 1; } for (i = 1; i <= n; i++) { if (i + fav[i] <= n) join(i, i + fav[i]); if (i - fav[i] > 0) join(i, i - fav[i]); } for (i = 1; i <= n; i++) if (getP(i) != getP(perm[i])) { if (0) printf( %d != %d n , i, perm[i]); printf( NO ); return; } printf( YES ); return; } int main() { int a, b, c; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &perm[i]); } for (int i = 1; i <= n; i++) scanf( %d , &fav[i]); getNum(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, q = 1, i, res = 1; cin >> n >> m; for (i = 0; i < m; i++) { q = (q << 1); q %= 1000000009; } q--; for (i = 0; i < n; i++) { res *= (q - i); if (res <= 0) { cout << 0 ; return 0; } res %= 1000000009; } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[1010]; int main() { int n; scanf( %d , &n); scanf( %s , s); int a0 = 0; int a1 = 0; int b0 = 0; int b1 = 0; for (int i = 0; i < n; i++) { if (s[i] == 0 ) { if (i % 2) b0++; else a0++; } else { if (i % 2) b1++; else a1++; } } int ans = min(a0 + b1, a1 + b0); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long a[300010], cnt[300010]; long long n, k, maxx; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 1; i <= n; ++i) { cin >> a[i]; maxx = max(maxx, a[i]); } int pos = 1, cnt = 0; while (a[pos] != maxx) { for (int i = pos + 1; i <= n; ++i) { if (a[pos] > a[i]) { cnt++; if (cnt >= k) { cout << a[pos]; return 0; } } else { cnt = 1; pos = i; break; } } } cout << maxx; return 0; }
|
module ad9777_spi(
output reg sdio,
output reg csb,
input rst,
input clk,
output reg spi_ok
);
wire [6:0] lut_index=7'd5;
////////////////////////////////////////////
function [15:0] lut_data;
input [5:0] addr;
begin
case(addr)////[15]:R/W=0,[14:13]:N1 N0=0,[12:8]:A4~A0,[7:0]:D7~D0
6'd0 :lut_data=16'b0_00_00000_0000_0100;//00
6'd1 :lut_data=16'b0_00_00001_0000_0000;//01
6'd2 :lut_data=16'b0_00_00101_0000_0001;//05
6'd3 :lut_data=16'b0_00_00110_0000_1111;//06
6'd4 :lut_data=16'b0_00_01001_0000_0000;//09
6'd5 :lut_data=16'b0_00_01010_0000_1111;//0A
endcase
end
endfunction
///////////////////////////////////////////
reg [5:0] addr;
reg [4:0] state;
reg [15:0] dout_reg;
reg [4:0] shift_reg;
always @ (negedge clk or negedge rst)
if(!rst)
begin
csb<=1'b1;
sdio<=1'b1;
state<=5'd0;
addr<=6'd0;
dout_reg<=16'd0;
shift_reg<=5'd0;
spi_ok<=1'b0;
end
else
begin
case(state)
5'd0:
begin
csb<=1'b1;
dout_reg<=lut_data(addr);
state<=5'd1;
end
5'd1:
begin
if(shift_reg<=5'd15)
begin
csb<=1'b0;
sdio<=dout_reg[15];
dout_reg<=dout_reg<<1;
shift_reg<=shift_reg+1'b1;
state<=5'd1;
end
else
begin
shift_reg<=5'd0;
csb<=1'b1;
sdio<=1'b1;
if(addr<lut_index)
begin
addr<=addr+1'b1;
state<=5'd0;
end
else
begin
addr<=6'd0;
state<=5'd2;
end
end
end
5'd2:
begin
spi_ok<=1'b1;
state<=5'd3;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; enum faces { Tetrahedron = 4, Cube = 6, Octahedron = 8, Dodecahedron = 12, Icosahedron = 20 }; int main() { int n; cin >> n; long long total = 0; for (int i = 0; i < n; ++i) { string s; cin >> s; if (s == Tetrahedron ) total += Tetrahedron; else if (s == Cube ) total += Cube; else if (s == Octahedron ) total += Octahedron; else if (s == Dodecahedron ) total += Dodecahedron; else if (s == Icosahedron ) total += Icosahedron; } cout << total; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_TB_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_TB_V
|
module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_fifo #(parameter WDT = 32, DEPTH = 8) (
input wire i_clk,
input wire i_reset,
input wire i_write_inhibit,
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
input wire i_stall_from_issue,
input wire i_stall_from_decode,
input wire i_clear_from_decode,
input wire [WDT-1:0] i_instr, // Instruction + other bits.
input wire i_valid, // Above is valid. Write enable basically.
output reg [WDT-1:0] o_instr, // Instruction output.
output reg o_valid, // Output valid.
output wire o_wb_stb,
output wire o_wb_cyc // Wishbone request.
);
reg clear, rd_en;
wire [WDT-1:0] instr;
wire valid;
assign o_wb_cyc = o_wb_stb;
always @*
begin
if ( i_clear_from_writeback ) clear = 1'd1;
else if ( i_data_stall ) clear = 1'd0;
else if ( i_clear_from_alu ) clear = 1'd1;
else if ( i_stall_from_shifter ) clear = 1'd0;
else if ( i_stall_from_issue ) clear = 1'd0;
else if ( i_stall_from_decode ) clear = 1'd0;
else if ( i_clear_from_decode ) clear = 1'd1;
else clear = 1'd0;
end
always @*
begin
if ( i_clear_from_writeback) rd_en = 1'd0;
else if ( i_data_stall ) rd_en = 1'd0;
else if ( i_clear_from_alu ) rd_en = 1'd0;
else if ( i_stall_from_shifter ) rd_en = 1'd0;
else if ( i_stall_from_issue ) rd_en = 1'd0;
else if ( i_stall_from_decode ) rd_en = 1'd0;
else if ( i_clear_from_decode ) rd_en = 1'd0;
else rd_en = 1'd1;
end
zap_sync_fifo #(.WIDTH(WDT), .DEPTH(DEPTH), .FWFT(1)) USF (
.i_clk (i_clk),
.i_reset (i_reset || clear),
.i_ack ( rd_en ),
.i_wr_en ( i_valid && !i_write_inhibit ),
.i_data (i_instr),
.o_data (instr),
.o_empty_n (valid),
.o_full_n (o_wb_stb),
.o_full_n_nxt (),
.o_empty (),
.o_data_nxt (),
.o_full ()
);
// Pipeline register.
always @ (posedge i_clk)
begin
if ( i_reset || clear )
begin
o_valid <= 1'd0;
end
else if ( rd_en )
begin
o_valid <= valid;
o_instr <= instr;
end
end
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:40:48 05/22/2016
// Design Name:
// Module Name: Decodificador_2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Decodificador_2(
input [3:0] Codigo_D,
output reg [7:0] catodo2
);
always @(*)
begin
case (Codigo_D)
4'h0: begin
catodo2 <= 8'b00000011;
end
4'h1: begin
catodo2 <= 8'b10011111;
end
4'h2: begin
catodo2 <= 8'b00100101;
end
4'h3: begin
catodo2 <= 8'b00001101;
end
4'h4: begin
catodo2 <= 8'b10011001;
end
4'h5: begin
catodo2 <= 8'b01001001;
end
4'h6: begin
catodo2 <= 8'b01000001;
end
4'h7: begin
catodo2 <= 8'b00011111;
end
4'h8: begin
catodo2 <= 8'b00000001;
end
4'h9: begin
catodo2 <= 8'b00011001;
end
4'hA: begin
catodo2 <= 8'b10011001;
end
4'hB: begin
catodo2 <= 8'b010010011;
end
4'hC: begin
catodo2 <= 8'b01000001;
end
4'hD: begin
catodo2 <= 8'b00011111;
end
4'hE: begin
catodo2 <= 8'b00000001;
end
4'hF: begin
catodo2 <= 8'b00011001;
end
default: begin
catodo2 <= 8'b10011111;
end
endcase
end
endmodule
|
/*
* keyboard.v - Keyboard interface for CPC
*
* Connects to the support CPU to set the appropriate keys.
* Note this is POSITIVE logic, rather than negative logic of the CPC keyboard
* Set a key bit to 1 to indictate 'down' or 0 for 'up'
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module keyboard (
output reg [79:0] keyboard_o,
// Bus signals
input busclk_i, // Clock for bus signals
input nreset_i,
input [3:0] A_i, // 10x8-bit registers, representing the 80 keys
input [7:0] D_i,
output reg [7:0] D_o,
input nWR_i,
input nRD_i
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [79:0] keyboard;
// Assignments ================================================================================
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
always @(posedge busclk_i)
begin
if( !nreset_i ) begin
keyboard <= 80'd0;
keyboard_o <= ~(80'd0);
end
else begin
if( !nRD_i ) begin
D_o <= (A_i == 4'd0) ? keyboard[7:0] :
(A_i == 4'd1) ? keyboard[15:8] :
(A_i == 4'd2) ? keyboard[23:16] :
(A_i == 4'd3) ? keyboard[31:24] :
(A_i == 4'd4) ? keyboard[39:32] :
(A_i == 4'd5) ? keyboard[47:40] :
(A_i == 4'd6) ? keyboard[55:48] :
(A_i == 4'd7) ? keyboard[63:56] :
(A_i == 4'd8) ? keyboard[71:64] :
(A_i == 4'd9) ? keyboard[79:72] :
8'd0;
end
if( !nWR_i ) begin
if( A_i > 4'd9 ) begin // Writing to other ports is the control reg
if( D_i[7] ) begin
keyboard <= 80'd0;
keyboard_o = ~(80'd0);
end
else
if( D_i[0] )
keyboard_o <= ~keyboard;
end
else
keyboard <= {
(A_i != 4'd9) ? keyboard[79:72] : D_i,
(A_i != 4'd8) ? keyboard[71:64] : D_i,
(A_i != 4'd7) ? keyboard[63:56] : D_i,
(A_i != 4'd6) ? keyboard[55:48] : D_i,
(A_i != 4'd5) ? keyboard[47:40] : D_i,
(A_i != 4'd4) ? keyboard[39:32] : D_i,
(A_i != 4'd3) ? keyboard[31:24] : D_i,
(A_i != 4'd2) ? keyboard[23:16] : D_i,
(A_i != 4'd1) ? keyboard[15:8] : D_i,
(A_i != 4'd0) ? keyboard[7:0] : D_i
};
end
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "qlf_k6n10f/cells_sim.v"
module tb();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#1 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Input data / reference
reg signed [19:0] A;
reg signed [17:0] B;
reg signed [37:0] C;
// Shift data change half a clock cycle
// to make registered inputs apparent
initial begin
forever begin
A = $random;
B = $random;
C <= A * B;
#1.5;
end
end
// UUT
wire signed [37:0] Z;
dsp_t1_sim # (
) uut (
.a_i (A),
.b_i (B),
.unsigned_a_i (1'h0),
.unsigned_b_i (1'h0),
.feedback_i (3'h0),
.register_inputs_i (1'h1),
.output_select_i (3'h0),
.clock_i (clk),
.z_o (Z)
);
// Error detection
reg [37:0] r_C;
initial r_C <= 0;
always @(posedge clk)
r_C <= C;
wire error = (Z !== r_C);
// Error counting
integer error_count;
initial error_count <= 0;
always @(posedge clk) begin
if (error) error_count <= error_count + 1;
end
// Simulation control / data dump
initial begin
$dumpfile(`VCD_FILE);
$dumpvars(0, tb);
#100 $finish_and_return( (error_count == 0) ? 0 : -1 );
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100; int gi() { int w = 0; bool q = 1; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) q = 0, c = getchar(); while (c >= 0 && c <= 9 ) w = w * 10 + c - 0 , c = getchar(); return q ? w : -w; } const int mod = 1e9 + 7; int f[N][N], g[N][N]; int inv[N]; inline void inc(int &x, int y) { (x += y) >= mod ? x -= mod : 0; } inline int C(int n, int m) { n += m - 1; int ans = 1; for (int i = 1; i <= m; i++) ans = 1LL * ans * (n - i + 1) % mod * inv[i] % mod; return ans; } int main() { int n = gi(), m = gi(), i, j, k, t, s, lim = n + 1; for (inv[0] = inv[1] = 1, i = 2; i < N; i++) inv[i] = mod - 1LL * (mod / i) * inv[mod % i] % mod; f[0][1] = 1; for (i = 0; i <= n; i++) for (j = 0; j <= lim; j++) { if (f[i][j]) for (k = 0; k <= i && k + i <= n; k++) for (t = 0; t <= lim; t++) { if (k == i) if (t < j) inc(g[i + k + 1][t], 2LL * f[i][j] * f[k][t] % mod); else if (t == j) inc(g[i + k + 1][j], 1LL * f[i][j] * f[k][t] % mod); else break; else inc(g[i + k + 1][min(j, t)], 2LL * f[i][j] * f[k][t] % mod); } if (g[i][j]) for (k = n - i; k >= 0; k--) for (t = lim - j; t >= 0; t--) if (f[k][t]) for (s = min((n - k) / i, (lim - t) / j); s; s--) inc(f[k + i * s][t + j * s], 1LL * f[k][t] * C(g[i][j], s) % mod); } printf( %d n , f[n][m]); return 0; }
|
module x;
reg [31:0] mb_reg_output;
// 16 registers max, register 15 is always the version number, so 15 are useable
// NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
parameter NUMBER_INTERFACE_REGS = 16;
parameter MB_REG_START = 3; // start at 4th register location 'h0010
parameter CMD_REG_0_ADDR = MB_REG_START;
parameter CMD_REG_1_ADDR = MB_REG_START+1;
parameter CMD_REG_2_ADDR = MB_REG_START+2;
parameter CMD_REG_3_ADDR = MB_REG_START+3;
parameter CMD_REG_4_ADDR = MB_REG_START+4;
parameter CMD_REG_5_ADDR = MB_REG_START+5;
parameter CMD_REG_6_ADDR = MB_REG_START+6;
parameter CMD_REG_7_ADDR = MB_REG_START+7;
parameter CMD_REG_8_ADDR = MB_REG_START+8;
parameter CMD_REG_9_ADDR = MB_REG_START+9;
parameter CMD_REG_10_ADDR = MB_REG_START+10;
// mode regs
parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
// Absolute register 14 is Error counter
parameter CMD_REG_14_ADDR = 14;
parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
// ------------ VERSION register is 15
parameter VERSION_REG_ADDR = 15;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
wire [31:0] interface_from_core_fp;
assign
mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
integer mb_loop;
always @(/*AUTOSENSE*/ /*memory or*/ interface_from_core_fp or mb_reg_rwn or mb_reg_select)
begin: MB_READ_WRITE_SEL_P
mb_reg_wr = 'h0;
mb_reg_rd = 'h0;
mb_reg_output = interface_from_core_fp;
for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
begin
if(mb_reg_select[mb_loop] == 1'b1)
begin
mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
mb_reg_output = mb_reg_out_w[mb_loop];
end
end
end
endmodule // x
|
(* An example showing that prop-extensionality is incompatible with
powerful extensions of the guard condition.
Unlike the example in guard2, it is not exploiting the fact that
the elimination of False always produces a subterm.
Example due to Cristobal Camarero on Coq-Club.
Adapted to nested types by Bruno Barras.
*)
Axiom prop_ext: forall P Q, (P<->Q)->P=Q.
Module Unboxed.
Inductive True2:Prop:= I2: (False->True2)->True2.
Theorem Heq: (False->True2)=True2.
Proof.
apply prop_ext. split.
- intros. constructor. exact H.
- intros. exact H.
Qed.
Fail Fixpoint con (x:True2) :False :=
match x with
I2 f => con (match Heq in _=T return T with eq_refl => f end)
end.
End Unboxed.
(* This boxed example shows that it is not enough to just require
that the return type of the match on Heq is an inductive type
*)
Module Boxed.
Inductive box (T:Type) := Box (_:T).
Definition unbox {T} (b:box T) : T := let (x) := b in x.
Inductive True2:Prop:= I2: box(False->True2)->True2.
Definition Heq: (False->True2) <-> True2 :=
conj (fun f => I2 (Box _ f)) (fun x _ => x).
Fail Fixpoint con (x:True2) :False :=
match x with
I2 f => con (unbox(match prop_ext _ _ Heq in _=T return box T with eq_refl => f end))
end.
End Boxed.
|
#include <bits/stdc++.h> using namespace std; long long ax, ay, bx, by, tx, ty; int n; long long x[110000]; long long y[110000]; long double solve(int cnt) { long double res = 0; int p = 0; long double v = sqrt((x[0] - ax) * (x[0] - ax) + (y[0] - ay) * (y[0] - ay)) - sqrt((x[0] - tx) * (x[0] - tx) + (y[0] - ty) * (y[0] - ty)); for (int i = 1; i < n; ++i) { long double cur = sqrt((x[i] - ax) * (x[i] - ax) + (y[i] - ay) * (y[i] - ay)) - sqrt((x[i] - tx) * (x[i] - tx) + (y[i] - ty) * (y[i] - ty)); if (cur < v) v = cur, p = i; } res += v; if (cnt == 1) return res; int q = 0; v = sqrt((x[0] - bx) * (x[0] - bx) + (y[0] - by) * (y[0] - by)) - sqrt((x[0] - tx) * (x[0] - tx) + (y[0] - ty) * (y[0] - ty)); for (int i = 1; i < n; ++i) { if (i == p) continue; long double cur = sqrt((x[i] - bx) * (x[i] - bx) + (y[i] - by) * (y[i] - by)) - sqrt((x[i] - tx) * (x[i] - tx) + (y[i] - ty) * (y[i] - ty)); if (cur < v || p == q) v = cur, q = i; } res += v; return res; } int main() { ios::sync_with_stdio(0); cin >> ax >> ay >> bx >> by >> tx >> ty; cin >> n; for (int i = 0; i < n; ++i) cin >> x[i] >> y[i]; if (n == 1) { long double v = sqrt((x[0] - tx) * (x[0] - tx) + (y[0] - ty) * (y[0] - ty)); cout << setprecision(10) << fixed << min(sqrt((x[0] - ax) * (x[0] - ax) + (y[0] - ay) * (y[0] - ay)), sqrt((x[0] - bx) * (x[0] - bx) + (y[0] - by) * (y[0] - by))) + v << n ; return 0; } long double ans = 0; for (int i = 0; i < n; ++i) ans += 2.0 * sqrt((x[i] - tx) * (x[i] - tx) + (y[i] - ty) * (y[i] - ty)); long double res = ans + solve(1); res = min(res, ans + solve(2)); swap(ax, bx); swap(ay, by); res = min(res, ans + solve(1)); res = min(res, ans + solve(2)); cout << setprecision(10) << fixed << res << n ; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// readUSBWireData.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// This module reads data from the differential USB data lines
//// and writes into a 4 entry FIFO. The data is read from
//// the fifo and output from the module when the higher level
//// state machine is ready to receive the data.
//// This module must recover the clock phase from the incoming
//// USB data. 'sampleCnt' is reset to zero whenever a RX data
//// edge is detected. Note that due to metastability the data
//// at the edge may not be registered correctly, but this does
//// not matter. All that matters is that an edge was detected. The
//// data will be accurately sampled in the middle of the USB bit
//// period without metastability issues.
//// After the edge detect, 'sampleCnt' is incremented at every clock
//// tick, and when it indicates the middle of a USB bit period
//// the RX data is sampled and written to the input buffer.
//// Single clock tick adjustments to 'sampleCnt' can be made at
//// every RX data edge detect without double sampling the incoming
//// data. However, the first RX data bit in a packet may cause
//// 'sampleCnt' to be adjusted by a value greater than a single
//// clock tick, and this can result in double sampling of the
//// first data bit a RX packet. This
//// double sampled data must be rejected by the higher level module.
//// This is achieved by
//// qualifying the outgoing data with 'RxWireActive'. Thus
//// the first data bit in a RX packet may be double sampled
//// as the clock recovery mechanism synchronizes to 'RxBitsIn'
//// but the double sampled data will be rejected by the higher
//// level module.
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
input [1:0] RxBitsIn;
output RxDataInTick;
input SIERxRdyIn;
input clk;
input fullSpeedRate;
input rst;
input TxWireActiveDrive;
output [1:0] RxBitsOut;
output SIERxWEn;
output noActivityTimeOut;
output RxWireActive;
input noActivityTimeOutEnable;
wire [1:0] RxBitsIn;
reg RxDataInTick;
wire SIERxRdyIn;
wire clk;
wire fullSpeedRate;
wire rst;
reg [1:0] RxBitsOut;
reg SIERxWEn;
reg noActivityTimeOut;
reg RxWireActive;
wire noActivityTimeOutEnable;
// local registers
reg [2:0]buffer0;
reg [2:0]buffer1;
reg [2:0]buffer2;
reg [2:0]buffer3;
reg [2:0]bufferCnt;
reg [1:0]bufferInIndex;
reg [1:0]bufferOutIndex;
reg decBufferCnt;
reg [4:0]sampleCnt;
reg incBufferCnt;
reg [1:0]oldRxBitsIn;
reg [1:0] RxBitsInReg;
reg [15:0] timeOutCnt;
reg [7:0] rxActiveCnt;
reg RxWireEdgeDetect;
reg RxWireActiveReg;
reg RxWireActiveReg2;
reg [1:0] RxBitsInSyncReg1;
reg [1:0] RxBitsInSyncReg2;
// buffer output state machine state codes:
`define WAIT_BUFFER_NOT_EMPTY 2'b00
`define WAIT_SIE_RX_READY 2'b01
`define SIE_RX_WRITE 2'b10
// re-synchronize incoming bits
always @(posedge clk) begin
RxBitsInSyncReg1 <= RxBitsIn;
RxBitsInSyncReg2 <= RxBitsInSyncReg1;
end
reg [1:0] bufferOutStMachCurrState;
always @(posedge clk) begin
if (rst == 1'b1)
begin
bufferCnt <= 3'b000;
end
else begin
if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
bufferCnt <= bufferCnt + 1'b1;
else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
bufferCnt <= bufferCnt - 1'b1;
end
end
//Perform line rate clock recovery
//Recover the wire data, and store data to buffer
always @(posedge clk) begin
if (rst == 1'b1)
begin
sampleCnt <= 5'b00000;
incBufferCnt <= 1'b0;
bufferInIndex <= 2'b00;
buffer0 <= 3'b000;
buffer1 <= 3'b000;
buffer2 <= 3'b000;
buffer3 <= 3'b000;
RxDataInTick <= 1'b0;
RxWireEdgeDetect <= 1'b0;
RxWireActiveReg <= 1'b0;
RxWireActiveReg2 <= 1'b0;
end
else begin
RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
RxBitsInReg <= RxBitsInSyncReg2;
oldRxBitsIn <= RxBitsInReg;
incBufferCnt <= 1'b0; //default value
if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then
sampleCnt <= 5'b00000;
RxWireEdgeDetect <= 1'b1; // flag receive activity
RxWireActiveReg <= 1'b1;
rxActiveCnt <= 8'h00;
end
else begin
sampleCnt <= sampleCnt + 1'b1;
RxWireEdgeDetect <= 1'b0;
rxActiveCnt <= rxActiveCnt + 1'b1;
//clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods
if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
|| (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) )
RxWireActiveReg <= 1'b0;
end
if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
begin
RxDataInTick <= !RxDataInTick;
if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
begin
incBufferCnt <= 1'b1;
bufferInIndex <= bufferInIndex + 1'b1;
case (bufferInIndex)
2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn};
2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
endcase
end
end
end
end
//read from buffer, and output to SIEReceiver
always @(posedge clk) begin
if (rst == 1'b1)
begin
decBufferCnt <= 1'b0;
bufferOutIndex <= 2'b00;
RxBitsOut <= 2'b00;
SIERxWEn <= 1'b0;
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
end
else begin
case (bufferOutStMachCurrState)
`WAIT_BUFFER_NOT_EMPTY:
begin
if (bufferCnt != 3'b000)
bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
end
`WAIT_SIE_RX_READY:
begin
if (SIERxRdyIn == 1'b1)
begin
SIERxWEn <= 1'b1;
bufferOutStMachCurrState <= `SIE_RX_WRITE;
decBufferCnt <= 1'b1;
bufferOutIndex <= bufferOutIndex + 1'b1;
case (bufferOutIndex)
2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
endcase
end
end
`SIE_RX_WRITE:
begin
SIERxWEn <= 1'b0;
decBufferCnt <= 1'b0;
bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
end
endcase
end
end
//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
//'noActivityTimeOut' pulse can only be generated when the host or slave getPacket
//process enables via 'noActivityTimeOutEnable' signal
//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if
//there has been a response time out.
always @(posedge clk) begin
if (rst) begin
timeOutCnt <= 16'h0000;
noActivityTimeOut <= 1'b0;
end
else begin
if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
timeOutCnt <= 16'h0000;
else
timeOutCnt <= timeOutCnt + 1'b1;
if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
|| (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
noActivityTimeOut <= 1'b1;
else
noActivityTimeOut <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string st[5050]; int fr[27]; int main() { memset(fr, 0, sizeof(fr)); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k; cin >> k >> n; for (int i = 0; i < k; i++) { cin >> st[i]; } string res = st[0]; memset(fr, 0, sizeof(fr)); bool du = false; for (int i = 0; i < n; i++) { fr[res[i] - a ]++; if (fr[res[i] - a ] > 1) { du = true; } } int ma = 0; int mi = 0; bool po = true; for (int i = 1; i < k; i++) { int df = 0; int ct[27] = {0}; for (int j = 0; j < n; j++) { ct[st[i][j] - a ]++; if (st[i][j] != res[j]) { df++; } } if (df > 4) { po = false; break; } for (int j = 0; j < 27; j++) { if (ct[j] != fr[j]) { po = false; break; } } if (df > ma) { ma = df; mi = i; } } if (!po) { cout << -1 << n ; return 0; } if (ma == 0) { swap(res[0], res[1]); cout << res << n ; return 0; } if (ma == 2) { if (!du) { cout << -1 << n ; return 0; cout << -1 << n ; return 0; } cout << res << n ; return 0; } int q[4]; int ctr = 0; for (int i = 0; i < n; i++) { if (res[i] != st[mi][i]) { q[ctr++] = i; } } po = false; int tr[2] = {0, 0}; for (int id = 0; id < 3; id++) { if (ma < 4) { q[3] = q[id]; } else if (id > 0) break; for (int i = 0; i < 4; i++) { for (int j = 0; j < 4; j++) { if (po) break; int md = 0; swap(res[q[i]], res[q[j]]); for (int c = 1; c < k; c++) { int df = 0; for (int l = 0; l < n; l++) { if (res[l] != st[c][l]) { df++; } } md = max(md, df); } swap(res[q[i]], res[q[j]]); if (md == 2) { po = true; tr[0] = i; tr[1] = j; } } } } if (po) { swap(res[q[tr[0]]], res[q[tr[1]]]); cout << res << n ; } else { cout << -1 << n ; } }
|
#include <bits/stdc++.h> using namespace std; int n = 8; struct point { int x; int y; }; bool f(point a, point b) { if (a.x != b.x) return a.x > b.x; return a.y > b.y; } int main() { point a[8]; for (int i = 0; i < n; i++) cin >> a[i].x >> a[i].y; int t1 = 0, t2 = 0; for (int i = 0; i < n; i += 2) { if (a[i].x == a[i + 1].x) { t1++; } else if (a[i].y == a[i + 1].y) t2++; else { cout << NO << endl; return 0; } } if (t1 != 2 || t2 != 2) { cout << NO << endl; return 0; } int t = 0; sort(a, a + n, f); if (a[1].x == a[2].x && a[1].y == a[2].y || a[3].x == a[4].x && a[3].y == a[4].y || a[5].x == a[6].x && a[5].y == a[6].y) { cout << NO << endl; return 0; } for (int i = 0; i < n; i += 2) { if (a[i].x == a[i + 1].x && a[i].y == a[i + 1].y) t++; else { cout << NO << endl; return 0; } } if (t == 4) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); long long n, m; cin >> n >> m; map<long long, set<long long>> adj; for (long long i = 0; i < m; i++) { long long a, b; cin >> a >> b; adj[a].insert(b); adj[b].insert(a); } long long mx = INT_MIN, v = 0; map<long long, long long> deg; for (auto i : adj) { deg[i.first] = i.second.size(); if (mx < i.second.size()) { mx = i.second.size(); v = i.first; } } deg[v] = 0; for (auto i : adj[v]) { deg[i]--; } long long f = 0; for (long long i = 1; i <= n; i++) { if (deg[i] > 0) { f = 1; break; } } if (!f) { cout << YES n ; return 0; } mx = INT_MIN, v = 0; for (long long i = 1; i <= n; i++) { if (mx < deg[i]) { mx = deg[i]; v = i; } } deg[v] = 0; for (auto i : adj[v]) { deg[i]--; } f = 0; for (long long i = 1; i <= n; i++) { if (deg[i] > 0) { f = 1; break; } } if (!f) { cout << YES n ; return 0; } cout << NO n ; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:64000000 ) using namespace std; const double PI = 2 * acos(0.0); const double eps = 1e-9; template <class T> T jog(T a, T b) { return a + b; } template <class T> T bog(T a, T b) { return a - b; } template <class T> T gon(T a, T b) { return a * b; } template <class T> T sq(T x) { return x * x; } template <class T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <class T> T lcm(T a, T b) { return (a / gcd(a, b)) * b; } template <class T> T power(T a, T p) { T res = 1, x = a; while (p) { if (p & 1) res = res * x; x = x * x; p >>= 1; } return res; } template <class T> T cordinatlenth(T a, T b, T c, T d) { return sqrt(sq(a - c) + sq(b - d)); } template <class T> string toString(T n) { ostringstream oss; oss << n; oss.flush(); return oss.str(); } int toInt(string s) { int r = 0; istringstream sin(s); sin >> r; return r; } long long bigmod(long long a, long long p, long long mod) { long long res = 1, x = a; while (p) { if (p & 1) res = (res * x) % mod; x = (x * x) % mod; p >>= 1; } return res; } int diraction1[] = {-1, 0, 0, 1, 1, -1, -1, 1}; int diraction2[] = {0, -1, 1, 0, 1, -1, 1, -1}; int horsed1[] = {-2, -2, -1, 1, 2, 2, 1, -1}; int horsed2[] = {1, -1, -2, -2, -1, 1, 2, 2}; void Input(); const int INF = 2147483647; const long long LINF = 9223372036854775807ll; bool isok(long long x); int n, in[100010], tmp[100010]; int main() { Input(); return 0; } void Input() { cin >> n; long long sum = 0; for (int i = 0; i < n; i++) cin >> in[i], sum += in[i]; long long ans = sum / (n - 1); ans += (bool)(sum % (n - 1)); for (int i = 0; i < n; i++) ans = ans < in[i] ? in[i] : ans; cout << ans << endl; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:41:24 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_system_ila_0_stub.v
// Design : zynq_design_1_system_ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_350b,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, SLOT_0_AXI_bready,
SLOT_0_AXI_araddr, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready, SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, SLOT_1_GPIO_tri_o,
SLOT_2_AXI_awid, SLOT_2_AXI_awaddr, SLOT_2_AXI_awlen, SLOT_2_AXI_awsize,
SLOT_2_AXI_awburst, SLOT_2_AXI_awlock, SLOT_2_AXI_awcache, SLOT_2_AXI_awprot,
SLOT_2_AXI_awqos, SLOT_2_AXI_awvalid, SLOT_2_AXI_awready, SLOT_2_AXI_wdata,
SLOT_2_AXI_wstrb, SLOT_2_AXI_wlast, SLOT_2_AXI_wvalid, SLOT_2_AXI_wready, SLOT_2_AXI_bid,
SLOT_2_AXI_bresp, SLOT_2_AXI_bvalid, SLOT_2_AXI_bready, SLOT_2_AXI_arid,
SLOT_2_AXI_araddr, SLOT_2_AXI_arlen, SLOT_2_AXI_arsize, SLOT_2_AXI_arburst,
SLOT_2_AXI_arlock, SLOT_2_AXI_arcache, SLOT_2_AXI_arprot, SLOT_2_AXI_arqos,
SLOT_2_AXI_arvalid, SLOT_2_AXI_arready, SLOT_2_AXI_rid, SLOT_2_AXI_rdata,
SLOT_2_AXI_rresp, SLOT_2_AXI_rlast, SLOT_2_AXI_rvalid, SLOT_2_AXI_rready, resetn,
TRIG_IN_trig, TRIG_IN_ack, TRIG_OUT_trig, TRIG_OUT_ack)
/* synthesis syn_black_box black_box_pad_pin="clk,SLOT_0_AXI_awaddr[8:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[8:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_GPIO_tri_o[7:0],SLOT_2_AXI_awid[11:0],SLOT_2_AXI_awaddr[15:0],SLOT_2_AXI_awlen[7:0],SLOT_2_AXI_awsize[2:0],SLOT_2_AXI_awburst[1:0],SLOT_2_AXI_awlock[0:0],SLOT_2_AXI_awcache[3:0],SLOT_2_AXI_awprot[2:0],SLOT_2_AXI_awqos[3:0],SLOT_2_AXI_awvalid,SLOT_2_AXI_awready,SLOT_2_AXI_wdata[31:0],SLOT_2_AXI_wstrb[3:0],SLOT_2_AXI_wlast,SLOT_2_AXI_wvalid,SLOT_2_AXI_wready,SLOT_2_AXI_bid[11:0],SLOT_2_AXI_bresp[1:0],SLOT_2_AXI_bvalid,SLOT_2_AXI_bready,SLOT_2_AXI_arid[11:0],SLOT_2_AXI_araddr[15:0],SLOT_2_AXI_arlen[7:0],SLOT_2_AXI_arsize[2:0],SLOT_2_AXI_arburst[1:0],SLOT_2_AXI_arlock[0:0],SLOT_2_AXI_arcache[3:0],SLOT_2_AXI_arprot[2:0],SLOT_2_AXI_arqos[3:0],SLOT_2_AXI_arvalid,SLOT_2_AXI_arready,SLOT_2_AXI_rid[11:0],SLOT_2_AXI_rdata[31:0],SLOT_2_AXI_rresp[1:0],SLOT_2_AXI_rlast,SLOT_2_AXI_rvalid,SLOT_2_AXI_rready,resetn,TRIG_IN_trig[0:0],TRIG_IN_ack[0:0],TRIG_OUT_trig[0:0],TRIG_OUT_ack[0:0]" */;
input clk;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_awready;
input [31:0]SLOT_0_AXI_wdata;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input SLOT_0_AXI_wready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input SLOT_0_AXI_bready;
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arvalid;
input SLOT_0_AXI_arready;
input [31:0]SLOT_0_AXI_rdata;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input SLOT_0_AXI_rready;
input [7:0]SLOT_1_GPIO_tri_o;
input [11:0]SLOT_2_AXI_awid;
input [15:0]SLOT_2_AXI_awaddr;
input [7:0]SLOT_2_AXI_awlen;
input [2:0]SLOT_2_AXI_awsize;
input [1:0]SLOT_2_AXI_awburst;
input [0:0]SLOT_2_AXI_awlock;
input [3:0]SLOT_2_AXI_awcache;
input [2:0]SLOT_2_AXI_awprot;
input [3:0]SLOT_2_AXI_awqos;
input SLOT_2_AXI_awvalid;
input SLOT_2_AXI_awready;
input [31:0]SLOT_2_AXI_wdata;
input [3:0]SLOT_2_AXI_wstrb;
input SLOT_2_AXI_wlast;
input SLOT_2_AXI_wvalid;
input SLOT_2_AXI_wready;
input [11:0]SLOT_2_AXI_bid;
input [1:0]SLOT_2_AXI_bresp;
input SLOT_2_AXI_bvalid;
input SLOT_2_AXI_bready;
input [11:0]SLOT_2_AXI_arid;
input [15:0]SLOT_2_AXI_araddr;
input [7:0]SLOT_2_AXI_arlen;
input [2:0]SLOT_2_AXI_arsize;
input [1:0]SLOT_2_AXI_arburst;
input [0:0]SLOT_2_AXI_arlock;
input [3:0]SLOT_2_AXI_arcache;
input [2:0]SLOT_2_AXI_arprot;
input [3:0]SLOT_2_AXI_arqos;
input SLOT_2_AXI_arvalid;
input SLOT_2_AXI_arready;
input [11:0]SLOT_2_AXI_rid;
input [31:0]SLOT_2_AXI_rdata;
input [1:0]SLOT_2_AXI_rresp;
input SLOT_2_AXI_rlast;
input SLOT_2_AXI_rvalid;
input SLOT_2_AXI_rready;
input resetn;
input [0:0]TRIG_IN_trig;
output [0:0]TRIG_IN_ack;
output [0:0]TRIG_OUT_trig;
input [0:0]TRIG_OUT_ack;
endmodule
|
`include "sccu_dataflow.v"
`include "cla32.v"
`include "alu.v"
`include "regfile.v"
module sccpu_dataflow(clock, resetn, inst, memout, pc, wmem, aluout, data2mem, reg_addr, reg_out );
input [31:0] inst, memout;
input clock, resetn;
output [31:0] pc, aluout, data2mem;
output wmem;
input [4:0]reg_addr;
output [31:0] reg_out;
wire [1:0] pcsource; //ÏÂÒ»ÌõÖ¸ÁîµÄµØÖ·Ñ¡ÔñÐźŠ00Ϊpc+4, 01ѡתÒƵØÖ·£¬10Ñ¡¼Ä´æÆ÷ÄڵĵØÖ·£¬11Ñ¡ÌøתµØÖ·
wire [3:0] aluc; //ALU¿ØÖƲÙ×÷
wire zero; //Áã±ê־λ beq,bnq
wire wmem; //дÈëÄÚ´ædmem£¬Îª1ʱдÈ룬·ñÔò²»Ð´£¬ÔÚlw£¬swÖ¸ÁîÖÐ
wire wreg; //д¼Ä´æÆ÷¶Ñ
wire regrt; //Ä¿µÄ¼Ä´æÆ÷Ñ¡Ôñ£¬Îª1ʱѡrt£¬Îª0ʱѡrd
wire m2reg; //´æ´¢Êý¾ÝдÈë¼Ä´æÆ÷£ºÎª1ʱѡÔñ´æ´¢Æ÷Êý¾Ý£¬Îª0ʱѡÔñALU½á¹û
wire shift; //ALU aʹÓÃÒÆλλÊý£ºÎª1ʱʹÓÃsa£¬·ñÔòʹÓüĴæÆ÷Êý¾Ý
wire aluimm; //ALU bÓÃÁ¢¼´Êý£ºÎª1ʱÓÃÁ¢¼´Êý£¬·ñÔòʹÓüĴæÆ÷Êý¾Ý
wire jal; //×Ó³ÌÐòµ÷ÓãºÎª1ʱ±íʾָÁîÊÇjal,·ñÔò²»ÊÇ
wire sext; //Á¢¼´Êý·ûºÅλÀ©Õ¹£ºÎª1ʱ·ûºÅÀ©Õ¹£¬·ñÔòÁãÀ©Õ¹
wire enable = 1; //ipдʹÄÜ
wire co, overflow, negative, carry;
wire [31:0] pcplus4out;
wire [31:0] pcplus8out;
wire [31:0] wpcout;
wire [31:0] alu1, alu2;
wire [31:0] rfouta;
wire [31:0] sa = {27'b0, inst[10:6]}; //ÒÆλָÁîÖеÄÒÆλλÊý ½«rtÖ¸¶¨¼Ä´æÆ÷ÖеÄÄÚÈÝÒƶ¯saλ£¬×¢Ò⣺instÖÐsaÖ»ÓÐ5룬´Ë´¦½«ËüÀ©Õ¹Îª32λ
wire e = sext & inst[15]; //Á¢¼´Êý·ûºÅ룬ÈôsextΪ0Ôò0À©Õ¹
wire [15:0] imm = {16{e} };
wire [31:0] immediate = {imm, inst[15:0]}; //·ûºÅλÀ©Õ¹ºóµÄÁ¢¼´Êý
wire [4:0] reg_dest;
wire [4:0] wn;
wire [31:0] offset = {imm[13:0], inst[15:0], 2'b00}; //beq.bnqÖÐÏà¶ÔתÒƵØÖ·
wire [31:0] bpc; //beq, bneÖеÄתÒƵØÖ·
wire [31:0] jpc = {pcplus4out[31:28], inst[25:0], 2'b00}; //jÖеÄתÒƵØÖ·
wire [31:0] data; //¼Ä´æÆ÷¶ÑÖÐҪдÈëµÄÊý¾Ý
wire [31:0] nextpcout;
wire [31:0] resultout;
sccu_dataflow cpu_cu (inst[31:26], inst[5:0], zero, wmem, rmem, wreg, regrt, m2reg, aluc, shift, aluimm, pcsource, jal, sext, wpc);
//ip£¬´æ·ÅÏÂÒ»ÌõÖ¸ÁîµØÖ·
dffe32 ip(nextpcout, clock, resetn, enable, pc);
cla32 pcplus4(pc, 32'h4, 1'b0, pcplus4out, co);
cla32 pcplus8(pc, 32'h8, 1'b0, pcplus8out, co);
mux2x5 reg_wn (inst[15:11], inst[20:16], regrt, reg_dest);
assign wn = reg_dest | {5{jal}}; //jal: r31 <-- pc+8, if jal == 1, wn = 31 else wn = reg_dest
mux2x32 pcorpc8(pc, pcplus8out, wpc, wpcout);
mux2x32 result(aluout, memout, m2reg, resultout);
mux2x32 rf_add(resultout, pcplus8out, jal, data);
regfile rf(inst[25:21], inst[20:16], data, wn, wreg, clock, resetn, rfouta, data2mem, reg_addr, reg_out );
mux2x32 alu_a(rfouta, sa, shift, alu1);
mux2x32 alu_b(data2mem, immediate, aluimm, alu2);
alu aluunit(alu1, alu2, aluc, aluout, zero, negative, overflow, carry);
cla32 beqbnepc(pc, offset, 1'b0, bpc, co);
mux4x32 nextpc(pcplus4out, bpc, rfouta , jpc, pcsource, nextpcout);
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace jumpmelon { long long divfloor(long long a, long long b) { long long k = a / b; if (k * b > a) k--; return k; } long long divceil(long long a, long long b) { long long k = a / b; if (k * b < a) k++; return k; } void work() { long long n, i_l, i_r, i_k; scanf( %lld%lld%lld%lld , &n, &i_l, &i_r, &i_k); long long d = i_l <= i_r ? i_r - i_l + 1 : i_r + n - i_l + 1; long long s = i_k - d, v = n - d + 1, ans = -1; if (n <= 1000000) { for (long long r = 0; r <= n; r++) { long long a = max(0LL, r - v), b = min(d, r); long long mink = max(0LL, divceil(s - b, n + r)); long long maxk = divfloor(s - a, n + r); if (mink <= maxk) ans = max(ans, r); } } else { for (long long k = 0; k * n <= s; k++) { long long t = s - k * n; long long minr = 0, maxr = n; if (k) maxr = min(maxr, divfloor(t, k)); maxr = min(maxr, divfloor(t + v, k + 1)); if (k) minr = max(minr, divceil(t - d, k)); else if (t > d) continue; minr = max(minr, divceil(t, k + 1)); if (minr <= maxr) ans = max(ans, maxr); } } printf( %lld n , ans); } } // namespace jumpmelon int main() { jumpmelon::work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mysqrt(long long x) { long long l = 0; long long r = 1; while (r * r <= x) r *= 2; while (r - l > 1) { long long m = (l + r) / 2; if (m * m <= x) l = m; else r = m; } return l; } int main() { long long n; cin >> n; long long a[n + 2][n + 2]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> a[i][j]; } } for (int i = 0; i < n; i++) { int j = (i + 1) % n; int k = (j + 1) % n; cout << mysqrt(1ll * a[i][j] * a[i][k] / a[j][k]) << n ; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode=0;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] mode_d1r;
reg [7:0] mode_d2r;
reg [7:0] mode_d3r;
// surefire lint_off ITENST
// surefire lint_off STMINI
// surefire lint_off NBAJAM
always @ (posedge clk) begin // filp-flops with asynchronous reset
if (0) begin
_mode <= 0;
end
else begin
_mode <= _mode + 1;
if (_mode==0) begin
$write("[%0t] t_blocking: Running\n", $time);
a <= 8'd0;
b <= 8'd0;
c <= 8'd0;
end
else if (_mode==1) begin
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd1;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==2) begin
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd2;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==3) begin
if (a !== 8'd1) $stop;
if (b !== 8'd2) $stop;
if (c !== 8'd1) $stop;
end
else if (_mode==4) begin
if (mode_d3r != 8'd1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
always @ (posedge clk) begin
mode_d3r <= mode_d2r;
mode_d2r <= mode_d1r;
mode_d1r <= _mode[7:0];
end
reg [14:10] bits;
// surefire lint_off SEQASS
always @ (posedge clk) begin
if (_mode==1) begin
bits[14:13] <= 2'b11;
bits[12] <= 1'b1;
end
if (_mode==2) begin
bits[11:10] <= 2'b10;
bits[13] <= 0;
end
if (_mode==3) begin
if (bits !== 5'b10110) $stop;
end
end
endmodule
|
`include "alu4bit.v"
module tb4alu;
reg [3:0] A, B;
reg CIN, BINV;
reg [1:0] OP;
wire COUT;
wire [3:0] Y;
alu4bit alu4bit00 (A, B, CIN, BINV, OP, COUT, Y);
initial begin
A = 4'b0000;
B = 4'b0000;
CIN = 1'b0;
BINV = 1'b0;
OP = 2'b00;
#10
A = 4'b0101;
B = 4'b1111;
OP = 2'b00;
#10
A = 4'b1010;
B = 4'b1111;
OP = 2'b00;
#10
A = 4'b0101;
B = 4'b0000;
OP = 2'b01;
#10
A = 4'b1010;
B = 4'b0000;
OP = 2'b01;
#10
A = 4'b0111;
B = 4'b0101;
CIN = 1'b0;
BINV = 1'b0;
OP = 2'b10;
#10
A = 4'b0100;
B = 4'b0010;
CIN = 1'b1;
BINV = 1'b0;
OP = 2'b10;
#10
A = 4'b0101;
B = 4'b0010;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b10;
#10
A = 4'b0100;
B = 4'b0101;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b10;
#10
A = 4'b0111;
B = 4'b0110;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b11;
#10
A = 4'b0011;
B = 4'b0111;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b11;
#10
$stop;
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 4, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output reg [575:0] out; /* to "f_permutation" module */
output out_ready; /* to "f_permutation" module */
input f_ack; /* from "f_permutation" module */
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
reg done; /* == 1: out_ready should be 0 */
reg [17:0] i; /* length of "out" buffer */
wire [31:0] v0; /* output of module "padder1" */
reg [31:0] v1; /* to be shifted into register "out" */
wire accept, /* accept user input? */
update;
assign buffer_full = i[17];
assign out_ready = buffer_full;
assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input
assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= {out[575-32:0], v1};
always @ (posedge clk)
if (reset)
i <= 0;
else if (f_ack | update)
i <= {i[16:0], 1'b1} & {18{~ f_ack}};
/* if (f_ack) i <= 0; */
/* if (update) i <= {i[16:0], 1'b1}; // increase length */
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
always @ (posedge clk)
if (reset)
done <= 0;
else if (state & out_ready)
done <= 1;
padder1 p0 (in, byte_num, v0);
always @ (*)
begin
if (state)
begin
v1 = 0;
v1[7] = v1[7] | i[16]; // "v1[7]" is the MSB of the last byte of "v1"
end
else if (is_last == 0)
v1 = in;
else
begin
v1 = v0;
v1[7] = v1[7] | i[16];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int nbVoyages, coutSimple, coutLiaison, maxCartes, coutCarte; map<pair<string, string>, int> routes; int main() { ios_base::sync_with_stdio(false); cin >> nbVoyages >> coutSimple >> coutLiaison >> maxCartes >> coutCarte; long long total = 0; string derFin = ; for (int iVoyage = 0; iVoyage < nbVoyages; iVoyage++) { string a, b; cin >> a >> b; string der = b, pre = a; if (b < a) swap(a, b); if (routes.find({a, b}) == routes.end()) routes[{a, b}] = 0; if (derFin == pre) { routes[{a, b}] += coutLiaison; total += coutLiaison; } else { routes[{a, b}] += coutSimple; total += coutSimple; } derFin = der; } vector<int> couts; for (pair<pair<string, string>, int> route : routes) { couts.push_back(route.second); } sort(couts.begin(), couts.end()); for (int iFois = 0; iFois < maxCartes; iFois++) { if (!couts.empty() && couts.back() > coutCarte) { total += coutCarte - couts.back(); couts.pop_back(); } } cout << total << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const long long INF = 1e17, LINF = 1e12; int n, m, q, x, y; vector<int> g[N], s[N]; int top[N], p[N], dp[N], son[N], sz, d[N]; int tin1[N], tin2[N], tout[N], timer, num[N]; pair<long long, int> og[N]; pair<long long, int> t[4 * N]; long long ob[4 * N]; void dfs(int v, int pr = 0, int depth = 0) { d[v] = depth; p[v] = pr; dp[v] = 1; for (int to : g[v]) { if (to != pr) { dfs(to, v, depth + 1); dp[v] += dp[to]; if (dp[to] > dp[son[v]]) { son[v] = to; } } } } void hld(int v, int pr = 0) { tin1[v] = ++timer; og[timer] = make_pair(INF, 0); for (auto it : s[v]) { timer++; og[timer] = make_pair(it, it); num[it] = timer; } tin2[v] = timer; if (son[v]) { top[son[v]] = top[v]; hld(son[v], v); } for (int to : g[v]) { if (to != pr && to != son[v]) { top[to] = to; hld(to, v); } } tout[v] = timer; } void build(int v, int l, int r) { if (l == r) { t[v] = og[l]; return; } int mid = (r + l) >> 1; build(v + v, l, mid); build(v + v + 1, mid + 1, r); t[v] = min(t[v + v], t[v + v + 1]); } inline void push(int v) { if (ob[v]) { ob[v + v] += ob[v]; ob[v + v + 1] += ob[v]; t[v + v].first += ob[v]; t[v + v + 1].first += ob[v]; ob[v] = 0; } } void update(int v, int l, int r, int tl, int tr, long long val) { if (l > r || l > tr || tl > r) { return; } if (tl <= l && r <= tr) { t[v].first += val; ob[v] += val; return; } push(v); int mid = (r + l) >> 1; update(v + v, l, mid, tl, tr, val); update(v + v + 1, mid + 1, r, tl, tr, val); t[v] = min(t[v + v], t[v + v + 1]); } pair<long long, int> get(int v, int l, int r, int tl, int tr) { if (l > r || l > tr || tl > r) { return make_pair(INF, 0); } if (tl <= l && r <= tr) { return t[v]; } push(v); int mid = (r + l) >> 1; return min(get(v + v, l, mid, tl, tr), get(v + v + 1, mid + 1, r, tl, tr)); } pair<long long, int> get(int x, int y) { pair<long long, int> mn = make_pair(INF, 1e9); while (top[x] != top[y]) { if (d[top[x]] > d[top[y]]) { mn = min(mn, get(1, 1, timer, tin1[top[x]], tin2[x])); x = p[top[x]]; } else { mn = min(mn, get(1, 1, timer, tin1[top[y]], tin2[y])); y = p[top[y]]; } } if (d[x] > d[y]) { swap(x, y); } mn = min(mn, get(1, 1, timer, tin1[x], tin2[y])); return mn; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> q; for (int i = 1; i < n; i++) { cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } for (int i = 1; i <= m; i++) { cin >> x; s[x].push_back(i); } dfs(1); top[1] = 1; hld(1); build(1, 1, timer); while (q--) { int t; cin >> t; if (t == 1) { int x, y, k; cin >> x >> y >> k; vector<int> ans; while (k) { auto it = get(x, y); if (it.first >= INF) { break; } k--; ans.push_back(it.second); update(1, 1, timer, num[it.second], num[it.second], INF); } cout << ans.size() << ; for (auto it : ans) { cout << it << ; } cout << n ; } else { int x, y; cin >> x >> y; update(1, 1, timer, tin1[x], tout[x], y); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_TB_V
`define SKY130_FD_SC_HD__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_TB_V
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
// CLK_OUT3___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (5),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_clk_wiz_0),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; void In() { cin >> n >> k; } void Solve() { k--; while (k--) { int largest = INT_MIN, smallest = INT_MAX; for (long long copy = n; copy; copy /= 10) { int r = copy % 10; largest = max(r, largest); smallest = min(r, smallest); } if (largest == 0 || smallest == 0) return; n += largest * smallest; } } void Out() { cout << n << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; cin >> t; while (t--) { In(); Solve(); Out(); } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int maxn = 300 + 10, maxm = 4e4 + 10; const int dir[4][2] = {0, 1, 0, -1, 1, 0, -1, 0}; const int INF = 0x3f3f3f3f; struct Graph { int ndn, edn, last[maxn]; int u[maxm], v[maxm], flw[maxm], cap[maxm], nxt[maxm]; void init(int _n) { ndn = _n; edn = 0; memset(last, -1, sizeof(last)); memset(flw, 0, sizeof(flw)); memset(cap, 0, sizeof(cap)); } void adde(int _u, int _v, int _c) { u[edn] = _u; v[edn] = _v; cap[edn] = _c; nxt[edn] = last[_u]; last[_u] = edn++; } }; struct Dinic { Graph *G; int S, T, dist[maxn], cur[maxn]; int BFS(); int DFS(int, int); int solve(Graph *, int, int); }; int N, T; char sci[15][15], cap[15][15]; int death[15][15], idsci[15][15], idcap[15][15]; int dist[15][15]; Graph G; Dinic dinic; bool judge(int x, int y) { return x < 0 || x >= N || y < 0 || y >= N || !isdigit(sci[x][y]); } int main() { int zx, zy; G.init(1); scanf( %d%d , &N, &T); for (int i = 0; i < N; i++) { scanf( %s , sci[i]); for (int j = 0; j < N; j++) { if (isdigit(sci[i][j]) && sci[i][j] >= 1 ) { idsci[i][j] = ++G.ndn; G.adde(0, G.ndn, sci[i][j] - 0 ); G.adde(G.ndn, 0, 0); } if (sci[i][j] == Z ) { zx = i; zy = j; } } } for (int i = 0; i < N; i++) { scanf( %s , cap[i]); for (int j = 0; j < N; j++) { if (isdigit(cap[i][j]) && cap[i][j] >= 1 ) { idcap[i][j] = ++G.ndn; G.adde(G.ndn, 1, cap[i][j] - 0 ); G.adde(1, G.ndn, 0); } } } queue<pair<int, int> > que; memset(death, 0x3f, sizeof(death)); death[zx][zy] = 0; que.push({zx, zy}); while (que.size()) { pair<int, int> u = que.front(); que.pop(); int d = death[u.first][u.second] + 1; for (int k = 0; k < 4; k++) { int x = u.first + dir[k][0]; int y = u.second + dir[k][1]; if (judge(x, y) || death[x][y] < INF) continue; death[x][y] = d; que.push({x, y}); } } for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) if (isdigit(sci[i][j]) && sci[i][j] >= 1 ) { while (que.size()) que.pop(); memset(dist, 0x3f, sizeof(dist)); dist[i][j] = 0; que.push({i, j}); while (que.size()) { pair<int, int> u = que.front(); que.pop(); if (idcap[u.first][u.second]) { G.adde(idsci[i][j], idcap[u.first][u.second], sci[i][j] - 0 ); G.adde(idcap[u.first][u.second], idsci[i][j], 0); } int d = dist[u.first][u.second] + 1; if (d > T || dist[u.first][u.second] >= death[u.first][u.second]) continue; for (int k = 0; k < 4; k++) { int x = u.first + dir[k][0]; int y = u.second + dir[k][1]; if (judge(x, y) || dist[x][y] < INF || death[x][y] < d) continue; dist[x][y] = d; que.push({x, y}); } } } printf( %d n , dinic.solve(&G, 0, 1)); return 0; } int Dinic::solve(Graph *g, int ts, int tt) { G = g; S = ts; T = tt; int res = 0; while (BFS()) { for (int i = 0; i <= G->ndn; i++) cur[i] = G->last[i]; res += DFS(S, 1e9); } return res; } int Dinic::BFS() { memset(dist, -1, sizeof(dist)); dist[S] = 0; queue<int> que; que.push(S); while (que.size()) { int u = que.front(); que.pop(); for (int e = G->last[u]; ~e; e = G->nxt[e]) { int v = G->v[e]; if (dist[v] == -1 && G->cap[e] > G->flw[e]) { dist[v] = dist[u] + 1; que.push(v); } } } return ~dist[T]; } int Dinic::DFS(int u, int tmin) { if (u == T || tmin == 0) return tmin; int nflw = 0, f; for (int &e = cur[u]; ~e; e = G->nxt[e]) { int v = G->v[e]; if (dist[u] + 1 == dist[v] && (f = DFS(v, min(tmin, G->cap[e] - G->flw[e]))) > 0) { G->flw[e] += f; G->flw[e ^ 1] -= f; nflw += f; tmin -= f; if (tmin == 0) break; } } return nflw; }
|
#include <bits/stdc++.h> using namespace std; int a[200005], b[200005]; int nx[500005]; int n, m; void getnext() { nx[0] = -1; int j = 0, k = -1; while (j < m) { if (k == -1 || b[j] == b[k]) nx[++j] = ++k; else k = nx[k]; } } int KMP() { int ret = 0; int i = 0, j = 0; for (i = 0; i < n; i++) { while (j > 0 && a[i] != b[j]) j = nx[j]; if (a[i] == b[j]) j++; if (j == m) { ret++; j = nx[j]; } } return ret; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; if (i != 0) a[i - 1] = a[i] - a[i - 1]; } for (int i = 0; i < m; i++) { cin >> b[i]; if (i != 0) b[i - 1] = b[i] - b[i - 1]; } if (m == 1) { cout << n << endl; return 0; } n--; m--; getnext(); cout << KMP() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int T, a[260]; int main() { scanf( %d , &T); while (T--) { int s = 0; int ct = 0; for (int i = 0; i < 250; i++) { scanf( %d , &a[i]); s += a[i]; } double ave = s / 250.0; for (int i = 0; i < 250; i++) { if (fabs(a[i] - ave) <= ave / 2) ct++; } if (ct > 250 * 0.75) printf( poisson n ); else printf( uniform n ); } return 0; }
|
//wb_bram.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x0000000E
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_bram
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x06
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x00
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:4096
*/
module wb_bram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 12,
parameter MEM_FILE = "NOTHING",
parameter MEM_FILE_LENGTH = 0
)(
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int
);
localparam RAM_SIZE = ADDR_WIDTH - 1;
localparam SLEEP_COUNT = 4;
wire [31:0] read_data;
reg [31:0] write_data;
reg [RAM_SIZE:0] ram_adr;
reg en_ram;
reg [3:0] ram_sleep;
bram#(
.DATA_WIDTH (DATA_WIDTH ),
.ADDR_WIDTH (ADDR_WIDTH ),
.MEM_FILE (MEM_FILE ),
.MEM_FILE_LENGTH (MEM_FILE_LENGTH )
)br(
.clk (clk ),
.rst (rst ),
.en (en_ram ),
.we (i_wbs_we ),
.write_address (ram_adr ),
.read_address (ram_adr ),
.data_in (write_data ),
.data_out (read_data )
);
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
ram_sleep <= SLEEP_COUNT;
ram_adr <= 0;
en_ram <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack & !i_wbs_stb)begin
o_wbs_ack <= 0;
en_ram <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
en_ram <= 1;
//ram_adr <= i_wbs_adr[RAM_SIZE + 2:2];
ram_adr <= i_wbs_adr[RAM_SIZE:0];
if (i_wbs_we) begin
//write request
//the bram module will handle all the writes
write_data <= i_wbs_dat;
// $display ("write a:%h, d:%h", i_wbs_adr[RAM_SIZE:0], i_wbs_dat);
end
else begin
//read request
o_wbs_dat <= read_data;
//i_wbs_dat <= i_wbs_adr;
// $display ("read a:%h, d:%h", i_wbs_adr[RAM_SIZE:0], read_data);
end
if (ram_sleep > 0) begin
ram_sleep <= ram_sleep - 1;
end
else begin
o_wbs_ack <= 1;
ram_sleep <= SLEEP_COUNT;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_FUNCTIONAL_V
`define SKY130_FD_SC_LP__AND4BB_FUNCTIONAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_FUNCTIONAL_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//
//-------------------------------------------------------------------
//
// Filename : fetch_db.v
// Author : Yufeng Bai
// Email :
// Created On : 2015-04-28
//
//-------------------------------------------------------------------
//
// Modified : 2014-08-18 by HLL
// Description : db supported
// Modified : 2015-09-02 by HLL
// Description : one more buffer added
// Modified : 2015-09-19 by HLL
// Description : load_db_chroma & store_db_chroma provided in the order of uvuvuv...
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fetch_db (
clk ,
rstn ,
sysif_start_i ,
db_wen_i ,
db_w4x4_x_i ,
db_w4x4_y_i ,
db_wprevious_i ,
db_done_i ,
db_wsel_i ,
db_wdata_i ,
db_ren_i ,
db_r4x4_i ,
db_ridx_i ,
db_rdata_o ,
ext_store_addr_i ,
ext_store_en_i ,
ext_store_ready_o ,
ext_store_data_o ,
ext_store_done_i ,
ext_ref_addr_i ,
ext_ref_en_i ,
ext_ref_data_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] sysif_start_i ; // system pipeline start
input [1-1:0] db_wen_i ; // db write enable
input [5-1:0] db_w4x4_x_i ; // db write 4x4 block index in x
input [5-1:0] db_w4x4_y_i ; // db write 4x4 block index in y
input [1-1:0] db_wprevious_i ; // db write previous lcu data
input [1-1:0] db_done_i ; // db write done
input [2-1:0] db_wsel_i ; // db write 4x4 block sel : 0x:luma, 10: u, 11:v
input [16*`PIXEL_WIDTH-1:0] db_wdata_i ; // db write 4x4 block data
input [1-1:0] db_ren_i ; // db read enable
input [5-1:0] db_r4x4_i ; // db_read 4x4 block index
input [2-1:0] db_ridx_i ; // db read pixel index in the block
output reg [4*`PIXEL_WIDTH-1:0] db_rdata_o ; // db read pixel data
input [8-1:0] ext_store_addr_i ; // read db_pixel ram address
input [1-1:0] ext_store_en_i ; // read db_pixel ram enable
output [1-1:0] ext_store_ready_o ; // previous lcu data ready : level
input [1-1:0] ext_store_done_i ; // read db_pixel data done : pulse
output reg [32*`PIXEL_WIDTH-1:0] ext_store_data_o ; // read db_pixel ram data
input [5-1:0] ext_ref_addr_i ; // write db_ref ram enable
input [1-1:0] ext_ref_en_i ; // write db_ref ram enable
input [16*`PIXEL_WIDTH-1:0] ext_ref_data_i ; // write db_ref ram data
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [1-1:0] ref_buf;
wire [1-1:0] ref_buf0_en, ref_buf1_en;
wire [5-1:0] ref_buf0_addr;
wire [5-1:0] ref_buf1_addr;
wire [16*`PIXEL_WIDTH-1 : 0] ref_buf0_data ;
wire [16*`PIXEL_WIDTH-1 : 0] ref_buf1_data ;
wire [16*`PIXEL_WIDTH-1 : 0] ref_data ;
wire [32*`PIXEL_WIDTH-1 : 0] ext_store_data_0 ;
wire [32*`PIXEL_WIDTH-1 : 0] ext_store_data_1 ;
wire [32*`PIXEL_WIDTH-1 : 0] ext_store_data_2 ;
reg [1 : 0] db_r4x4_r ;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
ref_buf <= 'd1;
end
else if (sysif_start_i) begin
ref_buf <= ~ref_buf;
end
end
//-----db_ref buffer-----------
assign ref_buf0_en = ext_ref_en_i & ~ref_buf;
assign ref_buf1_en = ext_ref_en_i & ref_buf;
assign ref_buf0_addr = ~ref_buf ? ext_ref_addr_i : ( db_ren_i ? ( db_r4x4_i[4] ? {1'b1,db_ridx_i[1:0],db_r4x4_i[2:1]} : {1'b0,db_r4x4_i[4],db_ridx_i,db_r4x4_i[3:2]} ) : 0 );
assign ref_buf1_addr = ref_buf ? ext_ref_addr_i : ( db_ren_i ? ( db_r4x4_i[4] ? {1'b1,db_ridx_i[1:0],db_r4x4_i[2:1]} : {1'b0,db_r4x4_i[4],db_ridx_i,db_r4x4_i[3:2]} ) : 0 );
assign ref_data = ref_buf ? ref_buf0_data : ref_buf1_data;
always @(posedge clk or negedge rstn ) begin
if( !rstn )
db_r4x4_r <= 0 ;
else if( db_r4x4_i[4] )
db_r4x4_r <= {db_r4x4_i[3],db_r4x4_i[0]} ;
else begin
db_r4x4_r <= db_r4x4_i[1:0] ;
end
end
always @(*) begin
db_rdata_o = 0 ;
case( db_r4x4_r )
0 : db_rdata_o = ref_data[16*`PIXEL_WIDTH-1:12*`PIXEL_WIDTH] ;
1 : db_rdata_o = ref_data[12*`PIXEL_WIDTH-1:08*`PIXEL_WIDTH] ;
2 : db_rdata_o = ref_data[08*`PIXEL_WIDTH-1:04*`PIXEL_WIDTH] ;
3 : db_rdata_o = ref_data[04*`PIXEL_WIDTH-1:00*`PIXEL_WIDTH] ;
endcase
end
//--- rotate logic -------------------------------
// wr_rotate
reg [1:0] wr_rotate ;
always @(posedge clk or negedge rstn ) begin
if( !rstn )
wr_rotate <= 0 ;
else if( db_done_i ) begin
if( wr_rotate == 2 )
wr_rotate <= 0 ;
else begin
wr_rotate <= wr_rotate + 1 ;
end
end
end
// rd_rotate
reg [1:0] rd_rotate ;
always @(posedge clk or negedge rstn ) begin
if( !rstn )
rd_rotate <= 0 ;
else if( ext_store_done_i ) begin
if( rd_rotate == 2 )
rd_rotate <= 0 ;
else begin
rd_rotate <= rd_rotate + 1 ;
end
end
end
// ext_store_data_o
always @(*) begin
ext_store_data_o = ext_store_data_0 ;
case( rd_rotate )
0 : ext_store_data_o = ext_store_data_0 ;
1 : ext_store_data_o = ext_store_data_1 ;
2 : ext_store_data_o = ext_store_data_2 ;
endcase
end
// post_rd
wire post_r_buf0_en ;
wire post_r_buf1_en ;
wire post_r_buf2_en ;
assign post_r_buf0_en = ext_store_en_i & ( rd_rotate==0 );
assign post_r_buf1_en = ext_store_en_i & ( rd_rotate==1 );
assign post_r_buf2_en = ext_store_en_i & ( rd_rotate==2 );
// post_wr
reg post_w_buf0_en ;
reg post_w_buf1_en ;
reg post_w_buf2_en ;
always @(*) begin
if( db_wprevious_i ) begin
post_w_buf0_en = db_wen_i & ( wr_rotate==1 );
post_w_buf1_en = db_wen_i & ( wr_rotate==2 );
post_w_buf2_en = db_wen_i & ( wr_rotate==0 );
end
else begin
post_w_buf0_en = db_wen_i & ( wr_rotate==0 );
post_w_buf1_en = db_wen_i & ( wr_rotate==1 );
post_w_buf2_en = db_wen_i & ( wr_rotate==2 );
end
end
// ********************************************
//
// Wrapper
//
// ********************************************
mem_bilo_db u_db_buf0 (
.clk ( clk ),
.rst_n ( rstn ),
.wen_i ( post_w_buf0_en ),
.wsel_i ( db_wsel_i ),
.w4x4_x_i ( db_w4x4_x_i[3:0] ),
.w4x4_y_i ( db_w4x4_y_i ),
.wdata_i ( db_wdata_i ),
.ren_i ( post_r_buf0_en ),
.raddr_i ( ext_store_addr_i ),
.rdata_o ( ext_store_data_0 )
);
mem_bilo_db u_db_buf1(
.clk ( clk ),
.rst_n ( rstn ),
.wen_i ( post_w_buf1_en ),
.wsel_i ( db_wsel_i ),
.w4x4_x_i ( db_w4x4_x_i[3:0] ),
.w4x4_y_i ( db_w4x4_y_i ),
.wdata_i ( db_wdata_i ),
.ren_i ( post_r_buf1_en ),
.raddr_i ( ext_store_addr_i ),
.rdata_o ( ext_store_data_1 )
);
mem_bilo_db u_db_buf2(
.clk ( clk ),
.rst_n ( rstn ),
.wen_i ( post_w_buf2_en ),
.wsel_i ( db_wsel_i ),
.w4x4_x_i ( db_w4x4_x_i[3:0] ),
.w4x4_y_i ( db_w4x4_y_i ),
.wdata_i ( db_wdata_i ),
.ren_i ( post_r_buf2_en ),
.raddr_i ( ext_store_addr_i ),
.rdata_o ( ext_store_data_2 )
);
ram_1p #(.Addr_Width(5), .Word_Width(`PIXEL_WIDTH*16))
u_ram0_1p_32x128 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.oen_i ( 1'b0 ),
.wen_i ( ~ref_buf0_en ),
.addr_i ( ref_buf0_addr ),
.data_i ( ext_ref_data_i),
.data_o ( ref_buf0_data )
);
ram_1p #(.Addr_Width(5), .Word_Width(`PIXEL_WIDTH*16))
u_ram1_1p_32x128 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.oen_i ( 1'b0 ),
.wen_i ( ~ref_buf1_en ),
.addr_i ( ref_buf1_addr ),
.data_i ( ext_ref_data_i),
.data_o ( ref_buf1_data )
);
endmodule
//
// 0 1 2 ... 14 15
// ------------------------> w_4x4_x
// 16 |
// 00 |
// 01 |
// .. |
// 14 |
// 15 |
// w_4x4_y
|
#include <bits/stdc++.h> using namespace std; long long int d[300002]; int safe[300002]; bool solve() { long long int n, k, l, i; cin >> n >> k >> l; for (i = 1; i <= n; i++) cin >> d[i]; int tide, dir, mtide; tide = k; dir = -1; for (i = 1; i <= n; i++) { if (d[i] + k <= l) tide = k, dir = -1; else if (d[i] > l) return false; else { mtide = l - d[i]; if (tide + dir <= mtide) { tide += dir; if (tide == 0) dir = 1; } else if (dir == -1 && mtide < tide - 1) { tide = mtide; if (tide == 0) dir = 1; } else return false; } } return true; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t, i; cin >> t; while (t--) { if (solve()) cout << Yes n ; else cout << No n ; } return 0; }
|
#include <bits/stdc++.h> const unsigned int M = 1000000007; long long power(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = x * res; y = y >> 1; x = x * x; } return res; } long long power(long long x, long long y, long long mod) { long long res = 1; while (y > 0) { if (y & 1) res = x * res % mod; y = y >> 1; x = x * x % mod; } return res; } using namespace std; void nik() { ios_base::sync_with_stdio(false); cin.tie(NULL); } signed main() { nik(); long long test = 1; cin >> test; while (test--) { long long one[100005] = {0}; string s; cin >> s; long long n = s.size(); s = + s; for (long long i = 1; i <= n; i++) { if (s[i] == 1 ) one[i] = one[i - 1] + 1; else one[i] = one[i - 1]; } long long ans = min(one[n], n - one[n]); if (ans == 0) { cout << ans << n ; continue; } for (long long i = 1; i <= n; i++) { ans = min(ans, i - one[i] + one[n] - one[i]); } long long b = ans; for (long long i = n; i >= 1; i--) { b = min(b, (n - i + 1) - (one[n] - one[i - 1]) + one[i - 1]); } cout << min(ans, b) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int n, t; int TM[maxn], wait, ans; priority_queue<int> in; int main() { scanf( %d%d , &n, &t); for (int i = 1; i <= n; ++i) scanf( %d , &TM[i]); for (int i = 1; i <= n + 1; ++i) { wait = t - i; if (wait < 0) break; while (!in.empty() && in.top() > wait) in.pop(); ans = max(ans, (int)in.size()); in.push(TM[i] - i); } printf( %d n , ans); return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: interrupt_controller.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Signals an interrupt on the Xilnx PCIe Endpoint
// interface. Supports single vector MSI or legacy based
// interrupts.
// When INTR is pulsed high, the interrupt will be issued
// as soon as possible. If using legacy interrupts, the
// initial interrupt must be cleared by another request
// (typically a PIO read or write request to the
// endpoint at some predetermined BAR address). Receipt of
// the "clear" acknowledgment should cause INTR_LEGACY_CLR
// input to pulse high. Thus completing the legacy
// interrupt cycle. If using MSI interrupts, no such
// acknowldegment is necessary.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_INTRCTLR_IDLE 3'd0
`define S_INTRCLTR_WORKING 3'd1
`define S_INTRCLTR_COMPLETE 3'd2
`define S_INTRCLTR_CLEAR_LEGACY 3'd3
`define S_INTRCLTR_CLEARING_LEGACY 3'd4
`define S_INTRCLTR_DONE 3'd5
`timescale 1ns/1ns
module interrupt_controller (
input CLK, // System clock
input RST, // Async reset
input INTR, // Pulsed high to request an interrupt
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
output INTR_DONE, // Pulsed high to signal interrupt sent
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output CFG_INTERRUPT_ASSERT, // Legacy interrupt message type
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [2:0] rState=`S_INTRCTLR_IDLE;
reg [2:0] rStateNext=`S_INTRCTLR_IDLE;
reg rIntr=0;
reg rIntrAssert=0;
assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
assign INTR_MSI_REQUEST = rIntr;
assign CFG_INTERRUPT_ASSERT = rIntrAssert;
// Control sending interrupts.
always @(*) begin
case (rState)
`S_INTRCTLR_IDLE : begin
if (INTR) begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
else begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
end
`S_INTRCLTR_WORKING : begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
`S_INTRCLTR_COMPLETE : begin
rIntr = 0;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
end
`S_INTRCLTR_CLEAR_LEGACY : begin
if (INTR_LEGACY_CLR) begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
else begin
rIntr = 0;
rIntrAssert = 1;
rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
end
end
`S_INTRCLTR_CLEARING_LEGACY : begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
`S_INTRCLTR_DONE : begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
default: begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
endcase
end
// Update the state.
always @(posedge CLK) begin
if (RST)
rState <= #1 `S_INTRCTLR_IDLE;
else
rState <= #1 rStateNext;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; vector<string> vec_splitter(string s) { s += , ; vector<string> res; while (!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out(vector<string> __attribute__((unused)) args, __attribute__((unused)) long long int idx, __attribute__((unused)) long long int LINE_NUM) { cout << n ; } template <typename Head, typename... Tail> void debug_out(vector<string> args, long long int idx, long long int LINE_NUM, Head H, Tail... T) { if (idx > 0) cout << , ; else cout << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cout << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } const long long int mod = 1000000007; const long long int inf = 1e18; const long long int N = 2e5 + 5; long long int dp[N][5]; string s; long long int n; string abc = abc ; long long int go(long long int idx, long long int pos) { if (pos > 3LL) { return 0; } if (idx == n) { return (pos == 3LL); } long long int &ans = dp[idx][pos]; if (ans != -1) return ans; ans = 0; if (s[idx] != ? ) { if (s[idx] == abc[pos]) { ans += go(idx + 1, pos + 1); ans %= mod; } ans += go(idx + 1, pos); ans %= mod; } else { for (char x = a ; x <= c ; x++) { if (x == abc[pos]) { ans += go(idx + 1, pos + 1); ans %= mod; } ans += go(idx + 1, pos); ans %= mod; } } return ans; } void HyperBeast() { memset(dp, -1, sizeof(dp)); cin >> n >> s; cout << go(0, 0); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int T = 1; for (long long int ti = 1; ti <= T; ti++) { HyperBeast(); cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; struct data { int val; int col; vector<int> vec; } arr[100005]; void connect(int a, int b) { arr[a].vec.push_back(b); arr[b].vec.push_back(a); } int goal[100005]; vector<int> ans; void dfs(int n, int fl, int flip, int flip1) { arr[n].col = 1; if (fl % 2 == 0) { if (flip % 2 == 0) { if (arr[n].val != goal[n]) { if (arr[n].val == 0) arr[n].val = 1; else arr[n].val = 0; ans.push_back(n); flip++; } else { } } else { if (arr[n].val == 0) arr[n].val = 1; else arr[n].val = 0; if (arr[n].val != goal[n]) { if (arr[n].val == 0) arr[n].val = 1; else arr[n].val = 0; ans.push_back(n); flip++; } } } else { if (flip1 % 2 == 0) { if (arr[n].val != goal[n]) { if (arr[n].val == 0) arr[n].val = 1; else arr[n].val = 0; ans.push_back(n); flip1++; } } else { if (arr[n].val == 0) arr[n].val = 1; else arr[n].val = 0; if (arr[n].val != goal[n]) { if (arr[n].val == 0) arr[n].val = 1; else arr[n].val = 0; ans.push_back(n); flip1++; } } } fl++; for (int i = 0; i < arr[n].vec.size(); i++) { if (arr[arr[n].vec[i]].col == 0) dfs(arr[n].vec[i], fl, flip, flip1); } return; } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 1; i < n; i++) { int aa, bb; cin >> aa >> bb; connect(aa, bb); } for (int i = 1; i <= n; i++) { int v; cin >> v; arr[i].val = v; arr[i].col = 0; } for (int i = 1; i <= n; i++) { cin >> goal[i]; } dfs(1, 0, 0, 0); int si = ans.size(); cout << si << endl; for (int i = 0; i < si; i++) { cout << ans[i] << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long a, s, d[500002][3], f, g, h, j, k, l, i, n, m; long long inf = 100000000000000000ll; pair<long long, int> p[500003], p1; int main() { cin >> n; for (i = 1; i <= n; i++) { scanf( %d , &a); d[i][0] = a; d[i][1] = i - 1; d[i][2] = i + 1; p[i] = {a, i}; } sort(p + 1, p + n + 1); i = 0; long long y = 0; int L = 1, R = n; while (n - i - 2 > 0) { p1 = p[i + 1]; if (p1.second == L || p1.second == R) { k += (p1.first - y) * (n - i - 2); y = p1.first; if (p1.second == L) L = d[p1.second][2]; else R = d[p1.second][1]; } else { k = k + min(d[d[p1.second][1]][0], d[d[p1.second][2]][0]) - y; d[d[p1.second][1]][2] = d[p1.second][2]; d[d[p1.second][2]][1] = d[p1.second][1]; } i++; } cout << k; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : HPIO_VREF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HPIO_VREF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter VREF_CNTR = "OFF"
)(
output VREF,
input [6:0] FABRIC_VREF_TUNE
);
// define constants
localparam MODULE_NAME = "HPIO_VREF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam VREF_CNTR_FABRIC_RANGE1 = 1;
localparam VREF_CNTR_FABRIC_RANGE2 = 2;
localparam VREF_CNTR_OFF = 0;
localparam [104:1] VREF_CNTR_REG = VREF_CNTR;
wire [1:0] VREF_CNTR_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire VREF_out = 1'b1;
wire VREF_delay;
wire [6:0] FABRIC_VREF_TUNE_in;
wire [6:0] FABRIC_VREF_TUNE_delay;
assign #(out_delay) VREF = VREF_delay;
// inputs with no timing checks
assign #(in_delay) FABRIC_VREF_TUNE_delay = FABRIC_VREF_TUNE;
assign VREF_delay = VREF_out;
assign FABRIC_VREF_TUNE_in = FABRIC_VREF_TUNE_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((VREF_CNTR_REG != "OFF") &&
(VREF_CNTR_REG != "FABRIC_RANGE1") &&
(VREF_CNTR_REG != "FABRIC_RANGE2"))) begin
$display("Error: [Unisim %s-101] VREF_CNTR attribute is set to %s. Legal values for this attribute are OFF, FABRIC_RANGE1 or FABRIC_RANGE2. Instance: %m", MODULE_NAME, VREF_CNTR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign VREF_CNTR_BIN =
(VREF_CNTR_REG == "OFF") ? VREF_CNTR_OFF :
(VREF_CNTR_REG == "FABRIC_RANGE1") ? VREF_CNTR_FABRIC_RANGE1 :
(VREF_CNTR_REG == "FABRIC_RANGE2") ? VREF_CNTR_FABRIC_RANGE2 :
VREF_CNTR_OFF;
always @ (FABRIC_VREF_TUNE_in) begin
$display("Info: [Unisim %s-1] Fabric Tune Value changed to %b. Instance: %m",MODULE_NAME, FABRIC_VREF_TUNE_in);
end
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int MOD = 1e9 + 7; long long dp[N][2]; void solve() { memset(dp, 0, sizeof(dp)); string a, b; cin >> a >> b; (a == b ? dp[0][1] = 1 : dp[0][0] = 1); int k; cin >> k; long long way_good = 0, way_bad = 0; string s = a; for (int i = 0; i < (int)(a).size(); i++) { (s == b ? ++way_good : ++way_bad); s = a.substr(i + 1, (int)(a).size() - i) + a.substr(0, i + 1); } for (int i = 1; i <= k; i++) { dp[i][1] = (((dp[i - 1][1] * (way_good - 1)) % MOD) + (dp[i - 1][0] * (way_good)) % MOD) % MOD; dp[i][0] = (((dp[i - 1][1] * (way_bad)) % MOD) + (dp[i - 1][0] * (way_bad - 1)) % MOD) % MOD; } cout << dp[k][1] % MOD << n ; return; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int res = 0, flag = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) flag = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { res = res * 10 + ch - 0 ; ch = getchar(); } return res * flag; } int r, c, n, k, p[3005][3005], x, y, cnt[3005], nxt[3005], lst[3005], tmp[3005]; long long ans; int main() { r = read(); c = read(); n = read(); k = read(); for (register int i = 1; i <= n; ++i) { x = read(); y = read(); p[x][++p[x][0]] = y; } for (register int i = 1; i <= r; ++i) sort(p[i] + 1, p[i] + p[i][0] + 1); for (register int i = r; i; --i) { int h = 1, t = 0, s = 0; long long now = 0; for (register int j = 1; j <= p[i][0]; ++j) ++cnt[p[i][j]]; while (1) { while (t < c && s < k) { ++t; s += cnt[t]; } if (s < k) break; while (h <= t && s >= k) { s -= cnt[h]; ++h; now += c - t + 1; } } nxt[0] = 1; lst[c + 1] = c; for (register int j = 1; j <= c; ++j) { nxt[j] = j + 1; lst[j] = j - 1; } for (register int j = 1; j <= c; ++j) if (!cnt[j]) { nxt[lst[j]] = nxt[j]; lst[nxt[j]] = lst[j]; } memcpy(tmp, cnt, sizeof(cnt)); for (register int j = r; j >= i; --j) { ans += now; for (register int u = 1; u <= p[j][0]; ++u) { h = t = p[j][u]; int s1 = tmp[h], s2 = 0; while (nxt[t] <= c && s1 + s2 + tmp[nxt[t]] <= k) { t = nxt[t]; s2 += tmp[t]; } while (1) { if (s1 + s2 == k) now -= (h - lst[h]) * (nxt[t] - t); h = lst[h]; s1 += tmp[h]; if (!h || s1 > k) break; while (s1 + s2 > k) { s2 -= tmp[t]; t = lst[t]; } } --tmp[p[j][u]]; if (!tmp[p[j][u]]) { nxt[lst[p[j][u]]] = nxt[p[j][u]]; lst[nxt[p[j][u]]] = lst[p[j][u]]; } } } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<long> v(n); long mul = 1; for (int i = 0; i < n; ++i) cin >> v[i]; if (n > 1000) { cout << 0 n ; return 0; } for (int i = 0; i < n - 1; ++i) for (int j = i + 1; j < n; ++j) mul = ((abs((v[j] - v[i])) % m) * (mul % m)) % m; cout << mul; return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_data_gen.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module contains the data generation logic for the synthesizable
// testbench.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_data_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0
)
(
input clk,
input rst,
input wr_data_en,
input rd_data_valid,
output app_wdf_wren,
output reg [APPDATA_WIDTH-1:0] app_wdf_data,
output reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [APPDATA_WIDTH-1:0] app_cmp_data
);
localparam WR_IDLE_FIRST_DATA = 2'b00;
localparam WR_SECOND_DATA = 2'b01;
localparam WR_THIRD_DATA = 2'b10;
localparam WR_FOURTH_DATA = 2'b11;
localparam RD_IDLE_FIRST_DATA = 2'b00;
localparam RD_SECOND_DATA = 2'b01;
localparam RD_THIRD_DATA = 2'b10;
localparam RD_FOURTH_DATA = 2'b11;
reg [APPDATA_WIDTH-1:0] app_wdf_data_r;
reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data_r;
wire app_wdf_wren_r;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_fall;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_rise;
wire rd_data_valid_r;
reg [1:0] rd_state;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
wire [APPDATA_WIDTH-1:0] wr_data;
reg wr_data_en_r;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_fall
/* synthesis syn_maxfan = 2 */;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_rise
/* synthesis syn_maxfan = 2 */;
wire [(APPDATA_WIDTH/8)-1:0] wr_mask_data;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_fall;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_rise;
reg [1:0] wr_state;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
always @(posedge clk) begin
app_wdf_data_r <= wr_data;
app_wdf_mask_data_r <= wr_mask_data;
app_wdf_data <= app_wdf_data_r;
app_wdf_mask_data <= app_wdf_mask_data_r;
end
// inst ff for timing
FDRSE ff_wdf_wren
(
.Q (app_wdf_wren_r),
.C (clk),
.CE (1'b1),
.D (wr_data_en_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_wren_r
(
.Q (app_wdf_wren),
.C (clk),
.CE (1'b1),
.D (app_wdf_wren_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_rd_data_valid_r
(
.Q (rd_data_valid_r),
.C (clk),
.CE (1'b1),
.D (rd_data_valid),
.R (1'b0),
.S (1'b0)
);
//***************************************************************************
// DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE
//***************************************************************************
assign wr_data = {wr_data_fall, wr_data_rise};
assign wr_mask_data = {wr_mask_data_fall, wr_mask_data_rise};
//*****************************************************************
// For now, don't vary data masks
//*****************************************************************
assign wr_mask_data_rise = {(APPDATA_WIDTH/8){1'b0}};
assign wr_mask_data_fall = {(APPDATA_WIDTH/8){1'b0}};
//*****************************************************************
// Write data logic
//*****************************************************************
// write data generation
//synthesis attribute max_fanout of wr_data_fall is 2
//synthesis attribute max_fanout of wr_data_rise is 2
always @(posedge clk) begin
if (rst_r1) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'bx}};
wr_data_fall <= {(APPDATA_WIDTH/2){1'bx}};
wr_state <= WR_IDLE_FIRST_DATA;
end else begin
case (wr_state)
WR_IDLE_FIRST_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
wr_data_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
wr_state <= WR_SECOND_DATA;
end
WR_SECOND_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_data_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_state <= WR_THIRD_DATA;
end
WR_THIRD_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_data_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_state <= WR_FOURTH_DATA;
end
WR_FOURTH_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
wr_data_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
wr_state <= WR_IDLE_FIRST_DATA;
end
endcase
end
end
always @(posedge clk)
if (rst_r1)
wr_data_en_r <= 1'b0;
else
wr_data_en_r <= wr_data_en;
//*****************************************************************
// Read data logic
//*****************************************************************
// read comparison data generation
always @(posedge clk)
if (rst_r1) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'bx}};
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'bx}};
rd_state <= RD_IDLE_FIRST_DATA;
end else begin
case (rd_state)
RD_IDLE_FIRST_DATA:
if (rd_data_valid_r)
begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
rd_state <= RD_SECOND_DATA;
end
RD_SECOND_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_state <= RD_THIRD_DATA;
end
RD_THIRD_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_state <= RD_FOURTH_DATA;
end
RD_FOURTH_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
rd_data_pat_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
rd_state <= RD_IDLE_FIRST_DATA;
end
endcase
end
//data to the compare circuit during read
assign app_cmp_data = {rd_data_pat_fall, rd_data_pat_rise};
endmodule
|
`include "bsg_mem_1r1w_sync_macros.vh"
module bsg_mem_1r1w_sync
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
(
input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
// TODO: Define more hardened macro configs here
`bsg_mem_1r1w_sync_macro(32,92,1) else
begin: notmacro
bsg_mem_1r1w_sync_synth #(
.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth (.*);
end
//synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
always_ff @(negedge clk_i)
if (w_v_i)
begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (w_addr_i < els_p))
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert ((reset_i === 'X) || (reset_i === 1'b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p))
else
begin
$error("X'ing matched read address %x (%m)",r_addr_i);
end
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync)
|
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