text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; long long gcd(long long n1, long long n2) { if (!n1) return n2; if (!n2) return n1; if (n1 % n2 == 0) return n2; return gcd(n2, n1 % n2); } long long powmod(long long base, long long exponent) { base %= 1000000007; long long ans = 1; while (exponent) { if (exponent & 1) ans = (ans * base) % 1000000007; base = (base * base) % 1000000007; exponent /= 2; } ans %= 1000000007; return ans; } vector<int> adj[1000100 + 1]; int level[1000100 + 1]; vector<int> temp; int freq[20 * 1000100 + 1]; int arr[1000100 + 1]; long long f(long long x) { return (x * (x - 1)) / 2; } void dfs(int node, int lv) { level[node] = lv; for (int i = 0; i < adj[node].size(); i++) dfs(adj[node][i], lv + 1); } int main() { int n, i, j, k; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &arr[i]); for (i = 2; i <= n; i++) { scanf( %d , &j); adj[j].push_back(i); } dfs(1, 1); int mx = 0, xr = 0; for (i = 1; i <= n; i++) mx = max(mx, level[i]); for (i = 1; i <= n; i++) { if ((mx & 1) == (level[i] & 1)) { temp.push_back(arr[i]); xr ^= arr[i]; } else freq[arr[i]]++; } long long answer = 0; k = temp.size(); if (!xr) answer = f(k) + f(n - k); for (i = 0; i < k; i++) answer += freq[(xr ^ temp[i])]; printf( %lld n , answer); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long r = 1000000007; int h[10]; int n, k, m, i, j; long long a[100001], b[100001]; long long ans, x, y, z, c1, c2; int main() { cin >> n >> k; for (i = 1; i <= n / k; i++) cin >> a[i]; for (i = 1; i <= n / k; i++) cin >> b[i]; h[0] = 1; for (i = 1; i <= 9; i++) h[i] = h[i - 1] * 10; ans = 1; for (i = 1; i <= n / k; i++) { x = 9; for (j = 2; j <= k; j++) x = x * 10 + 9; c1 = x / a[i] + 1; x = b[i] * h[k - 1]; z = x % a[i]; if (z > 0) x = x + (a[i] - z); y = b[i]; for (j = 2; j <= k; j++) y = y * 10 + 9; z = y % a[i]; if (z > 0) y = y - z; c2 = (y - x) / a[i] + 1; ans = ans * (c1 - c2) % r; } cout << ans << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9652_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
// internal registers
reg adc_valid_in = 'd0;
reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0;
// internal signals
wire [31:0] adc_pn_data_pn_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_valid_in <= ~adc_valid_in;
adc_pn_data_in <= {adc_pn_data_in[15:0], adc_data[15:0]};
if (adc_valid_in == 1'b1) begin
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Sat Jun 4 16:53:15 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.v
// Design : ClockDivider
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module ClockDivider
(clk,
clk_vga,
clk_cpu,
clk_2cpu);
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
(* IBUF_LOW_PWR *) wire clk;
wire clk_2cpu;
wire clk_cpu;
wire clk_vga;
ClockDivider_ClockDivider_clk_wiz inst
(.clk(clk),
.clk_2cpu(clk_2cpu),
.clk_cpu(clk_cpu),
.clk_vga(clk_vga));
endmodule
(* ORIG_REF_NAME = "ClockDivider_clk_wiz" *)
module ClockDivider_ClockDivider_clk_wiz
(clk,
clk_vga,
clk_cpu,
clk_2cpu);
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
wire clk;
wire clk_2cpu;
wire clk_2cpu_ClockDivider;
wire clk_ClockDivider;
wire clk_cpu;
wire clk_cpu_ClockDivider;
wire clk_vga;
wire clk_vga_ClockDivider;
wire clkfbout_ClockDivider;
wire clkfbout_buf_ClockDivider;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ClockDivider),
.O(clkfbout_buf_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk),
.O(clk_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_vga_ClockDivider),
.O(clk_vga));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_cpu_ClockDivider),
.O(clk_cpu));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk_2cpu_ClockDivider),
.O(clk_2cpu));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(54.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(120),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(60),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ClockDivider),
.CLKFBOUT(clkfbout_ClockDivider),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_ClockDivider),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_vga_ClockDivider),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_cpu_ClockDivider),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk_2cpu_ClockDivider),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//i2s_mem_controllerv
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "project_defines.v"
`timescale 1 ns/1 ps
module i2s_mem_controller (
input rst,
input clk,
//control
input enable,
input post_fifo_wave_en,
//clock divider
input i2s_clock,
//memory interface
output [23:0] wfifo_size,
output [1:0] wfifo_ready,
input [1:0] wfifo_activate,
input wfifo_strobe,
input [31:0] wfifo_data,
//i2s writer
input audio_data_request,
output reg audio_data_ack,
output reg [23:0] audio_data,
output reg audio_lr_bit
);
//registers/wires
//input side
wire starved;
//output side
reg read_strobe = 0;
wire read_ready;
reg read_activate = 0;
wire [23:0] read_size;
wire [31:0] read_data;
//i2s writer interface
reg [23:0] read_count = 0;
reg [3:0] state = 0;
//waveform
reg [31:0] write_count = 0;
reg [7:0] test_pre_pos = 0;
wire [7:0] test_pre_wavelength;
wire [15:0] test_pre_value;
reg [31:0] test_pre_data;
reg test_pre_write_strobe;
wire [31:0] fifo_data;
wire fifo_write_strobe;
reg [7:0] test_pos = 0;
wire [7:0] test_wavelength;
wire [15:0] test_value;
//parameters
parameter READ_STROBE = 4'h0;
parameter DELAY = 4'h1;
parameter READ = 4'h2;
//generate a Ping Pong FIFO to cross the clock domain
ppfifo #(
.DATA_WIDTH(32),
`ifndef SIMULATION
.ADDRESS_WIDTH(12)
//.ADDRESS_WIDTH(4)
`else
.ADDRESS_WIDTH(2)
`endif
)ping_pong (
.reset (rst || !enable ),
//write
.write_clock (clk ),
.write_ready (wfifo_ready ),
.write_activate (wfifo_activate ),
.write_fifo_size (wfifo_size ),
.write_strobe (wfifo_strobe ),
.write_data (wfifo_data ),
//.starved (starved ),
//read
.read_clock (i2s_clock ),
.read_strobe (read_strobe ),
.read_ready (read_ready ),
.read_activate (read_activate ),
.read_count (read_size ),
.read_data (read_data )
);
waveform wave_post (
.clk(clk),
.rst(rst),
.wavelength(test_wavelength),
.pos(test_pos),
.value(test_value)
);
//asynchronous logic
//prepare the data for the i2s writer
`ifdef SIMULATION
always @(posedge i2s_clock or posedge rst) begin
`else
always @(posedge i2s_clock) begin
`endif
read_strobe <= 0;
if (rst) begin
audio_data_ack <= 0;
audio_data <= 0;
audio_lr_bit <= 0;
read_count <= 0;
read_activate <= 0;
state <= READ_STROBE;
test_pos <= 0;
end
else if (enable) begin
//got an ack from the writer
if (~audio_data_request && audio_data_ack) begin
//de-assert the ack
audio_data_ack <= 0;
end
if (post_fifo_wave_en) begin
if (audio_data_request && ~audio_data_ack) begin
audio_lr_bit <= ~audio_lr_bit;
if (test_pos >= test_wavelength - 1) begin
test_pos <= 0;
end
else begin
test_pos <= test_pos + 1;
end
audio_data <= {test_value, 8'h0};
audio_data_ack <= 1;
end
end
else begin
if (read_ready && !read_activate) begin
read_count <= 0;
read_activate <= 1;
end
else if (read_activate) begin
if (read_count < read_size) begin
if (audio_data_request && !audio_data_ack) begin
audio_data <= read_data[23:0];
audio_lr_bit <= read_data[31];
audio_data_ack<= 1;
read_count <= read_count + 1;
read_strobe <= 1;
end
end
else begin
read_activate <= 0;
end
end
end
end
end
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_slave_axil_master
*/
module test_i2c_slave_axil_master;
// Parameters
parameter FILTER_LEN = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter STRB_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg m_axil_awready = 0;
reg m_axil_wready = 0;
reg [1:0] m_axil_bresp = 0;
reg m_axil_bvalid = 0;
reg m_axil_arready = 0;
reg [DATA_WIDTH-1:0] m_axil_rdata = 0;
reg [1:0] m_axil_rresp = 0;
reg m_axil_rvalid = 0;
reg enable = 0;
reg [6:0] device_address = 0;
// Outputs
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
wire [ADDR_WIDTH-1:0] m_axil_awaddr;
wire [2:0] m_axil_awprot;
wire m_axil_awvalid;
wire [DATA_WIDTH-1:0] m_axil_wdata;
wire [STRB_WIDTH-1:0] m_axil_wstrb;
wire m_axil_wvalid;
wire m_axil_bready;
wire [ADDR_WIDTH-1:0] m_axil_araddr;
wire [2:0] m_axil_arprot;
wire m_axil_arvalid;
wire m_axil_rready;
wire busy;
wire bus_addressed;
wire bus_active;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
i2c_scl_i,
i2c_sda_i,
m_axil_awready,
m_axil_wready,
m_axil_bresp,
m_axil_bvalid,
m_axil_arready,
m_axil_rdata,
m_axil_rresp,
m_axil_rvalid,
enable,
device_address
);
$to_myhdl(
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t,
m_axil_awaddr,
m_axil_awprot,
m_axil_awvalid,
m_axil_wdata,
m_axil_wstrb,
m_axil_wvalid,
m_axil_bready,
m_axil_araddr,
m_axil_arprot,
m_axil_arvalid,
m_axil_rready,
busy,
bus_addressed,
bus_active
);
// dump file
$dumpfile("test_i2c_slave_axil_master.lxt");
$dumpvars(0, test_i2c_slave_axil_master);
end
i2c_slave_axil_master #(
.FILTER_LEN(FILTER_LEN),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready),
.busy(busy),
.bus_addressed(bus_addressed),
.bus_active(bus_active),
.enable(enable),
.device_address(device_address)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1E-15; const int inf = int(1e9) + 7; const int maxN = 1000 + 5; int in[maxN], to[maxN], cs[maxN]; int n, m; int main() { scanf( %d%d , &n, &m); int a, b, c; for (int(i) = 0; (i) < (m); ++(i)) { scanf( %d%d%d , &a, &b, &c); to[a] = b; in[b] = 1; cs[a] = c; } int tot = 0; for (int(i) = (1); (i) < (n + 1); ++(i)) if (in[i] == 0 && to[i] != 0) tot++; printf( %d n , tot); for (int(i) = (1); (i) < (n + 1); ++(i)) if (in[i] == 0 && to[i] != 0) { int x = i, ans = inf; while (to[x]) { ans = min(ans, cs[x]); x = to[x]; } printf( %d %d %d n , i, x, ans); } return 0; }
|
// A simple circuit that can be used to detect brownouts and other hardware issues
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
reg [7:0] reset_counter = 0;
reg resetn = 0;
always @(posedge clk) begin
reset_counter <= reset_counter + 1;
resetn <= resetn | &reset_counter;
end
reg error, rdmode, rdfin;
reg [31:0] scratchpad [0:1023];
reg [31:0] xorshift32_state;
reg [9:0] index;
reg [31:0] next_xorshift32_state;
always @* begin
next_xorshift32_state = xorshift32_state ^ ( xorshift32_state << 13);
next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state >> 17);
next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state << 5);
end
always @(posedge clk) begin
xorshift32_state <= &index ? 123456789 : next_xorshift32_state;
index <= index + 1;
if (!resetn) begin
xorshift32_state <= 123456789;
index <= 0;
error <= 0;
rdmode <= 0;
rdfin <= 0;
end else
if (!rdmode) begin
scratchpad[index] <= xorshift32_state;
rdmode <= &index;
end else begin
if (scratchpad[index] != xorshift32_state) error <= 1;
rdfin <= rdfin || &index;
end
end
wire ok = resetn && rdfin && !error;
assign LED1 = 0, LED2 = error, LED3 = 0, LED4 = error, LED5 = ok;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long mod(long long n, long long m) { long long ret = n % m; if (ret < 0) ret += m; return ret; } long long gcd(long long a, long long b) { return (b == 0LL ? a : gcd(b, a % b)); } long long exp(long long a, long long b, long long m) { if (b == 0LL) return 1LL; if (b == 1LL) return mod(a, m); long long k = mod(exp(a, b / 2, m), m); if (b & 1LL) { return mod(a * mod(k * k, m), m); } else return mod(k * k, m); } long long k; bool ok(long long x, vector<long long>& v) { long long cur = 0; long long tot = 1; long long some = 0; for (long long i = 0; i < (long long)v.size(); i++) { if (tot > k) return 0; long long fim = (i == (long long)v.size() - 1) ? -1 : 0; if (cur + v[i] + fim <= x) { cur += v[i] + fim; } else { cur = v[i] + fim; if (cur > x) return 0; tot++; } } if (tot > k) return 0; return 1; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> k; vector<long long> v; string s; long long tot = 0; while (cin >> s) { long long tam = 0; for (long long i = 0; i < (long long)s.size();) { while (i < (long long)s.size() and s[i] != - ) { tam++; i++; } if (i < (long long)s.size()) { tam++; v.push_back(tam); tam = 0; i++; } } if (tam) v.push_back(tam + 1); } for (long long x : v) tot += x; long long l = 1, r = tot; long long ans = tot; while (l <= r) { long long mid = (l + r) / 2; if (ok(mid, v)) { ans = mid; r = mid - 1; } else l = mid + 1; } cout << ans << n ; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// Example module to create problem.
//
// generate a 64 bit value with bits
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
// all other bits zero.
module t_math_imm2 (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [4:0] LowMaskSel_Top, HighMaskSel_Top;
input [4:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]);
end
end
endgenerate
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt = -1; struct node { bool op; string val; int op1, op2; int type; node() { op = 0; val = ; type = 0; } } m[5020]; map<string, int> ind; inline int cti(char i) { return (int)(i - 0 ); } vector<string> vct; bool ansx[2020], ansm[2020]; int tb[5020]; int main() { int n, mm; string t, p; cin >> n >> mm; for (int i = 0; i < n; i++) { cin >> t; if (ind.find(t) == ind.end()) { ind[t] = ++cnt; } cin >> p; cin >> p; if (p[0] == 1 or p[0] == 0 ) { m[cnt].val = p; continue; } m[cnt].op = 1; if (p == ? ) m[cnt].op1 = -1; else m[cnt].op1 = ind[p]; cin >> p; if (p[0] == O ) m[cnt].type = 1; if (p[0] == A ) m[cnt].type = 2; if (p[0] == X ) m[cnt].type = 3; cin >> p; if (p == ? ) m[cnt].op2 = -1; else m[cnt].op2 = ind[p]; } int x0, x1, pic1, pic2; for (int i = 0; i < mm; i++) { x0 = x1 = 0; for (int k = 0; k < n; k++) { auto j = m[k]; if (j.op == 0) { x0 += cti(j.val[i]); tb[k] = cti(j.val[i]); } else { if (j.op1 == -1) pic1 = 0; else pic1 = tb[j.op1]; if (j.op2 == -1) pic2 = 0; else pic2 = tb[j.op2]; if (j.type == 1) { x0 += pic1 | pic2; tb[k] = pic1 | pic2; } else if (j.type == 2) { x0 += pic1 & pic2; tb[k] = pic1 & pic2; } else { x0 += pic1 ^ pic2; tb[k] = pic1 ^ pic2; } } } for (int k = 0; k < n; k++) { auto j = m[k]; if (j.op == 0) { x1 += cti(j.val[i]); tb[k] = cti(j.val[i]); } else { if (j.op1 == -1) pic1 = 1; else pic1 = tb[j.op1]; if (j.op2 == -1) pic2 = 1; else pic2 = tb[j.op2]; if (j.type == 1) { x1 += pic1 | pic2; tb[k] = pic1 | pic2; } else if (j.type == 2) { x1 += pic1 & pic2; tb[k] = pic1 & pic2; } else { x1 += pic1 ^ pic2; tb[k] = pic1 ^ pic2; } } } if (x0 > x1) { ansx[i] = 0; ansm[i] = 1; } if (x0 == x1) { ansx[i] = 0; ansm[i] = 0; } if (x0 < x1) { ansx[i] = 1; ansm[i] = 0; } } for (int i = 0; i < mm; i++) cout << ansm[i]; cout << endl; for (int i = 0; i < mm; i++) cout << ansx[i]; cout << endl; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire sys_clk_p,
input wire sys_clk_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// Clock and reset
wire sys_clk_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_ibufgds_inst(
.I(sys_clk_p),
.IB(sys_clk_n),
.O(sys_clk_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 450 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCM_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.100),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(sys_clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
wire ledu_int;
wire ledl_int;
wire ledd_int;
wire ledr_int;
wire ledc_int;
wire [7:0] led_int;
wire uart_rxd_int;
wire uart_txd_int;
wire uart_rts_int;
wire uart_cts_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_txd,
uart_rts}),
.out({uart_txd_int,
uart_rts_int})
);
assign ledu = ledu_int;
assign ledl = ledl_int;
assign ledd = ledd_int;
assign ledr = ledr_int;
assign ledc = ledc_int;
assign led = led_int;
assign uart_rxd = uart_rxd_int;
assign uart_cts = uart_cts_int;
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk_125mhz(clk_125mhz_int),
.rst_125mhz(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.ledu(ledu_int),
.ledl(ledl_int),
.ledd(ledd_int),
.ledr(ledr_int),
.ledc(ledc_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts_int)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, x, i; int reachable[1000000]; int need_to_convert[1000000]; int main(int argc, char **argv) { scanf( %d , &n); for (i = 0; i < n; ++i) { scanf( %d , &x); int trans_op_num = 0; while (x) { ++reachable[x]; need_to_convert[x] += trans_op_num; ++trans_op_num; x >>= 1; } } for (i = 1e5; i > 1 && reachable[i] != n; --i) ; x = need_to_convert[i]; while (true) { int y = reachable[i + i]; if (n > y + y) break; i = i + i; x = x - y + n - y; } printf( %d n , x); return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out4.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: ps2_keyboard.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ()
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
//
////////////////////////////////////////////////////////////////////////////////
module ps2_keyboard (
CLK,
RESET_N,
PS2_CLK,
PS2_DATA,
RX_PRESSED,
RX_EXTENDED,
RX_SCAN
);
input CLK;
input RESET_N;
input PS2_CLK;
input PS2_DATA;
output RX_PRESSED;
reg RX_PRESSED;
output RX_EXTENDED;
reg RX_EXTENDED;
output [7:0] RX_SCAN;
reg [7:0] RX_SCAN;
reg KB_CLK;
reg KB_DATA;
reg KB_CLK_B;
reg KB_DATA_B;
reg PRESSED_N;
reg EXTENDED;
reg [2:0] BIT;
reg [3:0] STATE;
reg [7:0] SCAN;
wire PARITY;
reg [10:0] TIMER;
reg KILLER;
wire RESET_X;
// Double buffer
always @ (posedge CLK)
begin
KB_CLK_B <= PS2_CLK;
KB_DATA_B <= PS2_DATA;
KB_CLK <= KB_CLK_B;
KB_DATA <= KB_DATA_B;
end
assign PARITY = ~(((SCAN[0]^SCAN[1])
^(SCAN[2]^SCAN[3]))
^((SCAN[4]^SCAN[5])
^(SCAN[6]^SCAN[7])));
assign RESET_X = RESET_N & KILLER;
always @ (negedge CLK or negedge RESET_N)
if(!RESET_N)
begin
KILLER <= 1'b1;
TIMER <= 11'h000;
end
else
case(TIMER)
11'h000:
begin
KILLER <= 1'b1;
if(STATE != 4'h0)
TIMER <= 11'h001;
end
11'h7FD:
begin
KILLER <= 1'b0;
TIMER <= 11'h7FE;
end
default:
if(STATE == 4'h0)
TIMER <= 11'h000;
else
TIMER <= TIMER + 1'b1;
endcase
always @ (posedge CLK or negedge RESET_X)
begin
if(!RESET_X)
begin
STATE <= 4'h0;
SCAN <= 8'h00;
BIT <= 3'b000;
RX_SCAN <= 8'h00;
RX_PRESSED <= 1'b0;
RX_EXTENDED <= 1'b0;
PRESSED_N <= 1'b0;
EXTENDED <= 1'b0;
end
else
begin
case (STATE)
4'h0: // Hunt for start bit
begin
BIT <= 3'b000;
RX_SCAN <= 8'h00;
RX_PRESSED <= 1'b0;
RX_EXTENDED <= 1'b0;
if(~KB_DATA & ~KB_CLK) //look for start bit
STATE <= 4'h1;
end
4'h1: // next bit
begin
if(KB_CLK)
STATE <= 4'h2;
end
4'h2: // Hunt for Bit
begin
if(~KB_CLK)
begin
SCAN[BIT] <= KB_DATA;
BIT <= BIT + 1'b1;
if(BIT == 3'b111)
STATE <= 4'h3;
else
STATE <= 4'h1;
end
end
4'h3: // Hunt for Bit
begin
if(KB_CLK)
STATE <= 4'h4;
end
4'h4: // Test parity
begin
if(~KB_CLK)
begin
if(KB_DATA == PARITY)
STATE <= 4'h5;
else
begin
PRESSED_N <= 1'b0;
EXTENDED <= 1'b0;
SCAN <= 8'h00;
STATE <= 4'hF;
end
end
end
4'h5: // Look for Stop bit
begin
if(KB_CLK)
STATE <= 4'h6;
end
4'h6: // Stop bit
begin
if(~KB_CLK)
STATE <= 4'h7;
end
4'h7:
begin
if(SCAN ==8'hE0)
begin
EXTENDED <= 1'b1;
STATE <= 4'hF;
end
else
if(SCAN == 8'hF0)
begin
PRESSED_N <= 1'b1;
STATE <= 4'hF;
end
else
begin
RX_SCAN <= SCAN;
RX_PRESSED <= ~PRESSED_N;
RX_EXTENDED <= EXTENDED;
PRESSED_N <= 1'b0;
EXTENDED <= 1'b0;
SCAN <= 8'h00;
STATE <= 4'hF;
end
end
4'h8:
begin
STATE <= 4'h9;
end
4'h9:
begin
STATE <= 4'hA;
end
4'hA:
begin
STATE <= 4'hB;
end
4'hB:
begin
STATE <= 4'hC;
end
4'hC:
begin
STATE <= 4'hD;
end
4'hD:
begin
STATE <= 4'hE;
end
4'hE:
begin
STATE <= 4'hF;
end
4'hF:
begin
if(KB_CLK)
STATE <= 4'h0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 10; int mx = 0; vector<int> g[N]; int n; int col[N]; int cnt[N][N]; void gen(int v) { if (v == n) { for (int i = 0; i < n; i++) for (int u : g[i]) { int t = col[i]; int z = col[u]; cnt[min(t, z)][max(t, z)] = 1; } int cur = 0; for (int i = 0; i < 6; i++) for (int j = 0; j < 6; j++) { cur += cnt[i][j]; cnt[i][j] = 0; } mx = max(mx, cur); return; } for (int i = 0; i < 6; i++) { col[v] = i; gen(v + 1); } } int solve() { if (!(cin >> n)) return 1; int m; cin >> m; for (int i = 0; i < n; i++) g[i].clear(); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; g[x].push_back(y); g[y].push_back(x); } mx = 0; gen(0); cout << mx << endl; return 0; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int TET = 1e9; for (int i = 1; i <= TET; i++) { if (solve()) break; cout << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__XOR3_BEHAVIORAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_BEHAVIORAL_V
|
module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, CLK, reset);
input[31:0] Xinport;
input[31:0] Yinport;
input[31:0] Uinport;
input[31:0] Aport;
input[31:0] DXport;
input CLK;
input reset;
output[31:0] Xoutport;
output[31:0] Youtport;
output[31:0] Uoutport;
reg[31:0] Xoutport;
reg[31:0] Youtport;
reg[31:0] Uoutport;
reg[31:0] x_var;
reg[31:0] y_var;
reg[31:0] u_var;
wire[31:0] temp;
reg looping;
assign temp = u_var * DXport;
always @(posedge CLK)
begin
if (reset == 1'b1)
begin
looping <= 1'b0;
x_var <= 0;
y_var <= 0;
u_var <= 0;
end
else
if (looping == 1'b0)
begin
x_var <= Xinport;
y_var <= Yinport;
u_var <= Uinport;
looping <= 1'b1;
end
else if (x_var < Aport)
begin
u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
y_var <= y_var + temp;//(u_var * DXport);
x_var <= x_var + DXport;
looping <= looping;
end
else
begin
Xoutport <= x_var ;
Youtport <= y_var ;
Uoutport <= u_var ;
looping <= 1'b0;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSlaveCyc2Wrap.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module wrapper.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbSlaveCyc2Wrap(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
irq,
usbClk,
USBWireVP,
USBWireVM,
USBWireOE_n,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
input clk_i;
input rst_i;
input [7:0] address_i;
input [7:0] data_i;
output [7:0] data_o;
input we_i;
input strobe_i;
output ack_o;
output irq;
input usbClk;
inout USBWireVP /* synthesis useioff=1 */;
inout USBWireVM /* synthesis useioff=1 */;
output USBWireOE_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire irq;
wire usbClk;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBFullSpeed;
//internal wiring
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = slaveSOFRxedIntOut | slaveResetEventIntOut |
slaveResumeIntOut | slaveTransDoneIntOut |
slaveNAKSentIntOut | slaveVBusDetIntOut;
assign USBWireDataIn = {USBWireVP, USBWireVM};
assign {USBWireVP, USBWireVM} = (USBWireCtrlOut == 1'b1) ? USBWireDataOut : 2'bzz;
assign USBWireOE_n = ~USBWireCtrlOut;
//Parameters declaration:
defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_ADDR_WIDTH = 6;
usbSlave usbSlaveInst (
.clk_i(clk_i),
.rst_i(rst_i),
.address_i(address_i),
.data_i(data_i),
.data_o(data_o),
.we_i(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
.slaveResetEventIntOut(slaveResetEventIntOut),
.slaveResumeIntOut(slaveResumeIntOut),
.slaveTransDoneIntOut(slaveTransDoneIntOut),
.slaveNAKSentIntOut(slaveNAKSentIntOut),
.slaveVBusDetIntOut(slaveVBusDetIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed),
.USBDPlusPullup(USBDPlusPullup),
.USBDMinusPullup(USBDMinusPullup),
.vBusDetect(vBusDetect)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1010; bool z[MAXN] = {0}; void prework() { for (int i = 2; i <= 1000; i++) { if (z[i]) continue; for (int k = i + i; k <= 1000; k += i) z[k] = true; } } struct node { char c; int n; bool operator<(node b) const { return n > b.n; } }; vector<int> v; int num[50] = {0}; string s; node a[27]; char ans[1010] = {0}; int main() { prework(); string s; cin >> s; int L = s.size(); int all = 0; for (int i = 2; i <= L; i++) { if (z[i]) continue; if (i * 2 <= L) continue; v.push_back(i); all++; } v.push_back(1); all++; for (string::iterator k = s.begin(); k != s.end(); k++) num[*k - a + 1]++; for (int i = 1; i <= 26; i++) { a[i].c = a + i - 1; a[i].n = num[i]; } sort(a + 1, a + 27); all = L - all; if (a[1].n < all) { cout << NO << endl; return 0; } a[1].n -= all; int now = 1; for (vector<int>::iterator k = v.begin(); k != v.end(); k++) { while (!a[now].n) now++; ans[*k] = a[now].c; a[now].n--; } for (int i = 1; i <= L; i++) if (!ans[i]) ans[i] = a[1].c; cout << YES << endl; string sss(ans + 1); cout << sss << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_TB_V
`define SKY130_FD_SC_HS__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_TB_V
|
#include <bits/stdc++.h> using namespace std; int nums[200]; int arr[200][200]; int counter; int line; int main() { int n; cin >> n; line = 0; counter = 0; int sum = 0; int nums[200]; int arr[200][200]; memset(arr, 0, sizeof arr); memset(nums, 0, sizeof nums); while (sum + (++counter) <= n) { sum += counter; } cout << counter << endl; counter--; int i; int ct = counter; int j; arr[0][0] = 1; arr[1][0] = 1; for (i = 1; i <= counter; i++) { arr[i][i] = arr[i - 1][i - 1] + ct; ct = ct - 1; arr[i + 1][i] = arr[i][i]; } for (i = 0; i <= counter; i++) { for (int j = i + 1; j < counter; j++) { arr[i][j] = arr[i][j - 1] + 1; arr[j + 1][i] = arr[i][j]; } } for (i = 0; i <= counter; i++) { for (j = 0; j < counter; j++) { cout << arr[i][j] << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, x, l, r, i, s, a[10179]; int main() { cin >> n >> m; for (i = 1; i <= n; i++) cin >> a[i]; while (m--) { cin >> l >> r >> x; for (s = 0, i = l; i <= r; i++) if (a[i] < a[x]) s++; if (s + l == x) cout << Yes n ; else cout << No n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { int n, i; cin >> n; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int ans = min(a[n - 1] - a[1], a[n - 2] - a[0]); cout << ans; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:00:21 05/08/2014
// Design Name:
// Module Name: multi_cycle_Cpu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Muliti_cycle_Cpu(
clk,
reset,
MIO_ready,
data_in,
gntInt,
Ireq,
Iack,
pc_out,
Inst,
mem_w,
Addr_out,
data_out,
CPU_MIO,
state,
cpu_stb_o,
intrrupt_en_o,
sel_o,
// Half_W,
Signext
);
input wire clk, reset, MIO_ready;
input wire [31: 0] data_in;
input wire [ 3: 0] gntInt; // INT grant
input wire Ireq; // INT request
output wire [31: 0] pc_out, Inst; //test
output wire [31: 0] Addr_out, data_out;
output wire [ 4: 0] state;
output wire mem_w, CPU_MIO;
output wire Signext;
output wire cpu_stb_o, Iack; // Bus requset and
output wire [31: 0] intrrupt_en_o; // Interrupt acknowlegement
output wire [3: 0] sel_o;
wire [31: 0] PC_Current;
wire [15: 0] imm;
wire [ 4: 0] InTcause; // Int cause, either syscall or INT
wire [ 3: 0] ALU_operation;
wire [ 1: 0] RegDst, ALUSrcB, ALUSrcA;
wire [ 2: 0] MemtoReg;
wire [ 2: 0] PCSource;
wire MemRead, MemWrite, IorD, IRWrite, RegWrite,
PCWrite, PCWriteCond, Beq, data2Mem, zero,
overflow, /*Signext,*/ WriteEPC, WriteCause,
WriteCp0, sysCause, WriteInt, Int_enm;
reg [ 3: 0] gntIntOut;
ctrl M1(
.clk (clk),
.reset (reset),
.Inst (Inst),
.MIO_ready (MIO_ready),
.MemRead (MemRead),
.MemWrite (MemWrite),
.CPU_MIO (CPU_MIO),
.IorD (IorD),
.IRWrite (IRWrite),
.RegDst (RegDst),
.RegWrite (RegWrite),
.MemtoReg (MemtoReg),
.data2Mem (data2Mem),
.ALUSrcA (ALUSrcA),
.ALUSrcB (ALUSrcB),
.PCSource (PCSource),
.PCWrite (PCWrite),
.PCWriteCond (PCWriteCond),
.Beq (Beq),
.ALU_operation (ALU_operation),
.state_out (state),
.zero (zero),
.overflow (overflow),
.Ireq (Ireq),
.Iack (Iack),
.Signext (Signext),
.WriteEPC (WriteEPC),
.WriteCause (WriteCause),
.WriteCp0 (WriteCp0),
.sysCause (sysCause),
.WriteIen (WriteIen),
.Int_en (Int_en),
.sel_o (sel_o)
//.Half_W (Half_W)
);
assign InTcause = {gntIntOut, sysCause}; // TODO: to be precise
always @(posedge clk) begin
gntIntOut <= gntInt & {4{Ireq}};
end
data_path M2(
.clk (clk),
.reset (reset),
.MIO_ready (MIO_ready),
.IorD (IorD),
.IRWrite (IRWrite),
.RegDst (RegDst),
.RegWrite (RegWrite),
.MemtoReg (MemtoReg),
.data2Mem (data2Mem),
.ALUSrcA (ALUSrcA),
.ALUSrcB (ALUSrcB),
.PCSource (PCSource),
.PCWrite (PCWrite),
.PCWriteCond (PCWriteCond),
.Beq (Beq),
.ALU_operation (ALU_operation),
.PC_Current (PC_Current),
.data2CPU (data_in),
.Inst_R (Inst),
.data_out (data_out),
.M_addr (Addr_out),
.zero (zero),
.overflow (overflow),
.Signext (Signext),
.WriteEPC (WriteEPC),
.WriteCause (WriteCause),
.WriteCp0 (WriteCp0),
.InTcause (InTcause),
.WriteIen (WriteIen),
.Int_en (Int_en),
.intrrupt_en_o (intrrupt_en_o)
);
assign mem_w = MemWrite && ~MemRead;
assign cpu_stb_o = MemWrite | MemRead; // Used for wishbone interface
assign pc_out = PC_Current;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; vector<int> pl; vector<int> sum; int a; int otv = 0; cin >> n; int m = pow(2, n + 1) - 2; pl.push_back(0); for (int i = 1; i <= m; ++i) { cin >> a; pl.push_back(a); } for (int j = n; j > 0; j--) for (int i = pow(2, j); i < pow(2, j + 1) - 1; i += 2) { pl[i / 2 - 1] += max(pl[i - 1], pl[i]); otv += abs(pl[i - 1] - pl[i]); } cout << otv; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[105]; int main() { int n, l, i, j, cnt, area, ans; scanf( %d%d , &n, &l); for (i = 1; i <= n; i++) scanf( %d , &a[i]); ans = 0; for (i = l; i <= 100; i++) { cnt = 0; for (j = 1; j <= n; j++) cnt += a[j] / i; area = cnt * i; ans = max(ans, area); } printf( %d n , ans); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// or1200_fpu_div ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// division entity for the division unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module or1200_fpu_div
(
clk_i,
dvdnd_i,
dvsor_i,
sign_dvd_i,
sign_div_i,
start_i,
ready_o,
qutnt_o,
rmndr_o,
sign_o,
div_zero_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk_i;
input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i;
input [FRAC_WIDTH+3:0] dvsor_i;
input sign_dvd_i;
input sign_div_i;
input start_i;
output ready_o;
output [FRAC_WIDTH+3:0] qutnt_o;
output [FRAC_WIDTH+3:0] rmndr_o;
output sign_o;
output div_zero_o;
parameter t_state_waiting = 1'b0,
t_state_busy = 1'b1;
reg [FRAC_WIDTH+3:0] s_qutnt_o;
reg [FRAC_WIDTH+3:0] s_rmndr_o;
reg [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_i;
reg [FRAC_WIDTH+3:0] s_dvsor_i;
reg s_sign_dvd_i, s_sign_div_i;
wire s_sign_o;
wire s_div_zero_o;
reg s_start_i;
reg s_ready_o;
reg s_state;
reg [4:0] s_count;
reg [FRAC_WIDTH+3:0] s_dvd;
// Input Register
always @(posedge clk_i)
begin
s_dvdnd_i <= dvdnd_i;
s_dvsor_i <= dvsor_i;
s_sign_dvd_i<= sign_dvd_i;
s_sign_div_i<= sign_div_i;
s_start_i <= start_i;
end
assign qutnt_o = s_qutnt_o;
assign rmndr_o = s_rmndr_o;
assign sign_o = s_sign_o;
assign ready_o = s_ready_o;
assign div_zero_o = s_div_zero_o;
assign s_sign_o = sign_dvd_i ^ sign_div_i;
assign s_div_zero_o = !(|s_dvsor_i) & (|s_dvdnd_i);
always @(posedge clk_i)
if (s_start_i)
begin
s_state <= t_state_busy;
s_count <= 26;
end
else if (!(|s_count) & s_state==t_state_busy)
begin
s_state <= t_state_waiting;
s_ready_o <= 1;
s_count <=26;
end
else if (s_state==t_state_busy)
s_count <= s_count - 1;
else
begin
s_state <= t_state_waiting;
s_ready_o <= 0;
end
wire [26:0] v_div;
assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd;
wire [26:0] v_div_minus_s_dvsor_i;
assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i;
always @(posedge clk_i)
begin
//Reset
if (s_start_i)
begin
s_qutnt_o <= 0;
s_rmndr_o <= 0;
end
else if (s_state==t_state_busy)
begin
if (v_div < s_dvsor_i)
begin
s_qutnt_o[s_count] <= 1'b0;
s_dvd <= {v_div[25:0],1'b0};
end
else
begin
s_qutnt_o[s_count] <= 1'b1;
s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0};
end
s_rmndr_o <= v_div;
end // if (s_state==t_state_busy)
end // always @ (posedge clk_i)
endmodule // or1200_fpu_div
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; vector<int> Pr = { 0, 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719, 727, 733, 739, 743, 751, 757, 761, 769, 773, 787, 797, 809, 811, 821, 823, 827, 829, 839, 853, 857, 859, 863, 877, 881, 883, 887, 907, 911, 919, 929, 937, 941, 947, 953, 967, 971, 977, 983, 991, 997, 1009, 1013, 1019, 1021, 1031, 1033, 1039, 1049, 1051, 1061, 1063, 1069, 1087, 1091, 1093, 1097, 1103, 1109, 1117, 1123, 1129, 1151, 1153, 1163, 1171, 1181, 1187, 1193, 1201, 1213, 1217, 1223, 1229, 1231, 1237, 1249, 1259, 1277, 1279, 1283, 1289, 1291, 1297, 1301, 1303, 1307, 1319, 1321, 1327, 1361, 1367, 1373, 1381, 1399, 1409, 1423, 1427, 1429, 1433, 1439, 1447, 1451, 1453, 1459, 1471, 1481, 1483, 1487, 1489, 1493, 1499, 1511, 1523, 1531, 1543, 1549, 1553, 1559, 1567, 1571, 1579, 1583, 1597, 1601, 1607, 1609, 1613, 1619, 1621, 1627, 1637, 1657, 1663, 1667, 1669, 1693, 1697, 1699, 1709, 1721, 1723, 1733, 1741, 1747, 1753, 1759, 1777, 1783, 1787, 1789, 1801, 1811, 1823, 1831, 1847, 1861, 1867, 1871, 1873, 1877, 1879, 1889, 1901, 1907, 1913, 1931, 1933, 1949, 1951, 1973, 1979, 1987, 1993, 1997, 1999, 2003, 2011, 2017, 2027, 2029, 2039, 2053, 2063, 2069, 2081, 2083, 2087, 2089, 2099, 2111, 2113, 2129, 2131, 2137, 2141, 2143, 2153, 2161, 2179, 2203, 2207, 2213, 2221, 2237, 2239, 2243, 2251, 2267, 2269, 2273, 2281, 2287, 2293, 2297, 2309, 2311, 2333, 2339, 2341, 2347, 2351, 2357, 2371, 2377, 2381, 2383, 2389, 2393, 2399, 2411, 2417, 2423, 2437, 2441, 2447, 2459, 2467, 2473, 2477, 2503, 2521, 2531, 2539, 2543, 2549, 2551, 2557, 2579, 2591, 2593, 2609, 2617, 2621, 2633, 2647, 2657, 2659, 2663, 2671, 2677, 2683, 2687, 2689, 2693, 2699, 2707, 2711, 2713, 2719, 2729, 2731, 2741, 2749, 2753, 2767, 2777, 2789, 2791, 2797, 2801, 2803, 2819, 2833, 2837, 2843, 2851, 2857, 2861, 2879, 2887, 2897, 2903, 2909, 2917, 2927, 2939, 2953, 2957, 2963, 2969, 2971, 2999, 3001, 3011, 3019, 3023, 3037, 3041, 3049, 3061, 3067, 3079, 3083, 3089, 3109, 3119, 3121, 3137, 3163, 3167, 3169, 3181, 3187, 3191, 3203, 3209, 3217, 3221, 3229, 3251, 3253, 3257, 3259, 3271, 3299, 3301, 3307, 3313, 3319, 3323, 3329, 3331, 3343, 3347, 3359, 3361, 3371, 3373, 3389, 3391, 3407, 3413, 3433, 3449, 3457, 3461, 3463, 3467, 3469, 3491, 3499, 3511, 3517, 3527, 3529, 3533, 3539, 3541, 3547, 3557, 3559, 3571, 3581, 3583, 3593, 3607, 3613, 3617, 3623, 3631, 3637, 3643, 3659, 3671, 3673, 3677, 3691, 3697, 3701, 3709, 3719, 3727, 3733, 3739, 3761, 3767, 3769, 3779, 3793, 3797, 3803, 3821, 3823, 3833, 3847, 3851, 3853, 3863, 3877, 3881, 3889, 3907, 3911, 3917, 3919, 3923, 3929, 3931, 3943, 3947, 3967, 3989, 4001, 4003, 4007, 4013, 4019, 4021, 4027, 4049, 4051, 4057, 4073, 4079, 4091, 4093, 4099, 4111, 4127, 4129, 4133, 4139, 4153, 4157, 4159, 4177, 4201, 4211, 4217, 4219, 4229, 4231, 4241, 4243, 4253, 4259, 4261, 4271, 4273, 4283, 4289, 4297, 4327, 4337, 4339, 4349, 4357, 4363, 4373, 4391, 4397, 4409, 4421, 4423, 4441, 4447, 4451, 4457, 4463, 4481, 4483, 4493, 4507, 4513, 4517, 4519, 4523, 4547, 4549, 4561, 4567, 4583, 4591, 4597, 4603, 4621, 4637, 4639, 4643, 4649, 4651, 4657, 4663, 4673, 4679, 4691, 4703, 4721, 4723, 4729, 4733, 4751, 4759, 4783, 4787, 4789, 4793, 4799, 4801, 4813, 4817, 4831, 4861, 4871, 4877, 4889, 4903, 4909, 4919, 4931, 4933, 4937, 4943, 4951, 4957, 4967, 4969, 4973, 4987, 4993, 4999}; int dist[5010][5010], pr[5010][5010], pr_mx[5010]; int c1[5010], c2[5010][710]; int n, k[1000010]; long long ans = (1ll << 60); void f(int st) { long long s1 = 0, s2 = 0, s3 = c1[st]; for (int i = 0; i <= 5000; i++) if (st != i) s1 += (long long)c1[i] * (dist[st][i] + dist[i][st]), s2 += c1[i]; for (int i = 0, j = st - 1, k = st + 1; i <= c2[st][669]; i++) { while (j >= 0 && dist[st][j] <= i) { s3 += c1[j]; s2 -= c1[j]; j--; } while (k <= 5000 && dist[st][k] <= i) { s3 += c1[k]; s2 -= c1[k]; k++; } ans = min(ans, s1); s1 += s3; s1 -= s2; } ans = min(ans, s1); } int main() { for (int i = 1; i <= 5000; i++) { for (int j = 669; j >= 1; j--) if (i % Pr[j] == 0) { pr_mx[i] = j; break; } } for (int i = 0; i <= 5000; i++) for (int j = i + 1; j <= 5000; j++) { pr[i][j] = max(pr[i][j - 1], pr_mx[j]); } for (int i = 1; i <= 5000; i++) for (int j = i, k = 1; k <= 669; k++) { c2[i][k] = c2[i - 1][k]; while (j % Pr[k] == 0) { j /= Pr[k]; c2[i][k]++; } } for (int i = 1; i <= 5000; i++) for (int j = 1; j <= 669; j++) c2[i][j] += c2[i][j - 1]; for (int i = 0; i <= 5000; i++) for (int j = i + 1; j <= 5000; j++) { if (!pr[i][j]) continue; dist[i][j] = c2[i][pr[i][j] - 1]; dist[j][i] = c2[j][pr[i][j]] - c2[i][pr[i][j]] + c2[i][pr[i][j] - 1]; } scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &k[i]); c1[k[i]]++; } for (int i = 0; i <= 5000; i++) if (c1[i]) f(i); printf( %lld n , ans); return 0; }
|
`default_nettype none
module execute_load_data(
input wire [3:0] iMASK,
input wire [1:0] iSHIFT,
input wire [31:0] iDATA,
output wire [31:0] oDATA
);
assign oDATA = func_load_fairing(
iMASK,
iSHIFT,
iDATA
);
function [31:0] func_load_fairing;
input [3:0] func_mask;
input [1:0] func_shift;
input [31:0] func_data;
reg [7:0] func_tmp0, func_tmp1, func_tmp2, func_tmp3;
begin
if(func_mask == 4'hf)begin
func_load_fairing = func_data;
end
else if(func_mask == 4'b0001)begin
func_load_fairing = {24'h0, func_data[31:24]};
end
else if(func_mask == 4'b0010)begin
func_load_fairing = {24'h0, func_data[23:16]};
end
else if(func_mask == 4'b0100)begin
func_load_fairing = {24'h0, func_data[15:8]};
end
else if(func_mask == 4'b1000)begin
func_load_fairing = {24'h0, func_data[7:0]};
end
else if(func_mask == 4'b0011)begin
func_load_fairing = {24'h0, func_data[31:16]};
end
else begin
//else if(func_mask == 4'b1100)begin
func_load_fairing = {24'h0, func_data[15:0]};
end
end
endfunction
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 7; const long long INF = (long long)1e18; int n; int m; vector<pair<int, int>> g[N]; long long dist[N]; int par[N]; int t[N]; int root(int x) { if (t[x] == x) { return x; } else { return t[x] = root(t[x]); } } void unite(int x, int y) { t[root(x)] = root(y); } struct T { int x; long long d; }; bool operator<(T a, T b) { return a.d > b.d; } struct edge { int x; int y; long long d; }; bool operator<(edge a, edge b) { return a.d < b.d; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y, z; cin >> x >> y >> z; g[x].push_back({y, z}); g[y].push_back({x, z}); } for (int i = 1; i <= n; i++) { t[i] = i; dist[i] = INF; } priority_queue<T> pq; int cnt; cin >> cnt; for (int i = 1; i <= cnt; i++) { int portal; cin >> portal; dist[portal] = 0; par[portal] = portal; pq.push({portal, 0}); } while (!pq.empty()) { int x = pq.top().x; long long d = pq.top().d; pq.pop(); if (d != dist[x]) { continue; } for (auto &it : g[x]) { int y = it.first; long long dy = dist[x] + it.second; if (dy < dist[y]) { dist[y] = dy; par[y] = par[x]; pq.push({y, dy}); } } } vector<edge> e; for (int i = 1; i <= n; i++) { for (auto &it : g[i]) { int j = it.first; int c = it.second; if (par[i] != par[j]) { e.push_back({par[i], par[j], c + dist[i] + dist[j]}); } } } long long sol = dist[1]; sort(e.begin(), e.end()); for (auto &it : e) { if (root(it.x) != root(it.y)) { unite(it.x, it.y); sol += it.d; } } cout << sol << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O211A_BEHAVIORAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int t = a[n - 1]; a[n - 1] = a[n - 2]; a[n - 2] = t; if (a[0] + a[n - 2] <= a[n - 1] || a[n - 1] + a[n - 3] <= a[n - 2]) { cout << NO ; return 0; } cout << YES << endl; for (int i = 0; i < n; i++) cout << a[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans1 = INT_MAX, ans = -198896785; cin >> n; int c = 0, d = 0; for (int i = 0; i < n; i++) { int a; cin >> a; if (a < 0) { c++; ans = max(a, ans); } if (a > 0) { d++; ans1 = min(a, ans1); } } n = (n + 1) / 2; if (d >= n) cout << ans1 << endl; else if (c >= n) cout << ans << endl; else cout << 0 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c = 0, n, t, i, j, flag = 0, sum, f; string s, s1, s2; cin >> t; while (t--) { cin >> n; c = 0, sum = 0, flag = 0, f = 0; int ara[n], ara1[n]; for (i = 0; i < n; i++) { cin >> ara[i]; } for (i = 0; i < n; i++) { cin >> ara1[i]; } for (i = 0; i < n; i++) { if (ara[i] != ara1[i]) { c = (ara1[i] - ara[i]); flag = 1; } if (flag) break; } for (i = 0; i < n; i++) { if (ara[i] == ara1[i]) sum++; else if (ara[i] < ara1[i] && f == 0) { if (ara[i] + c == ara1[i]) sum++; if (ara[i + 1] == ara1[i + 1]) f = 1; } } if (sum == n) cout << YES << n ; else cout << NO << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5009; struct edge { int to, nxt; } e[N * 2]; int hd[N], tot; void add(int u, int v) { e[++tot] = (edge){v, hd[u]}; hd[u] = tot; } int n, leaf, lcnt[N], l[N]; void dfs1(int u, int fa) { for (int i = hd[u], v; i; i = e[i].nxt) { l[u]++; if ((v = e[i].to) == fa) continue; dfs1(v, u); } leaf += (l[u] == 1); } int f[N][N][2], g[N][2]; void dfs2(int u, int fa) { if (l[u] == 1) { f[u][0][0] = f[u][1][1] = 0; lcnt[u] = 1; return; } bool vst = 0; for (int i = hd[u], v; i; i = e[i].nxt) { if ((v = e[i].to) == fa) continue; dfs2(v, u); if (!vst) { for (int k = 0; k <= lcnt[v]; k++) f[u][k][0] = min(f[v][k][0], f[v][k][1] + 1), f[u][k][1] = min(f[v][k][0] + 1, f[v][k][1]); } else { for (int j = 0; j <= min(lcnt[u], leaf / 2); j++) for (int k = 0; k < 2; k++) g[j][k] = f[u][j][k], f[u][j][k] = 0x3f3f3f3f; for (int j = 0; j <= min(lcnt[u], leaf / 2); j++) { for (int k = 0; k <= min(lcnt[v], leaf / 2 - j); k++) { f[u][j + k][0] = min(f[u][j + k][0], g[j][0] + min(f[v][k][0], f[v][k][1] + 1)); f[u][j + k][1] = min(f[u][j + k][1], g[j][1] + min(f[v][k][1], f[v][k][0] + 1)); } } } vst = 1; lcnt[u] += lcnt[v]; } } int main() { scanf( %d , &n); if (n == 2) return puts( 2 ), 0; for (int i = 1, u, v; i < n; i++) scanf( %d%d , &u, &v), add(u, v), add(v, u); dfs1(1, 0); memset(f, 0x3f, sizeof(f)); int root = 1; while (l[root] == 1) root++; dfs2(root, 0); printf( %d , min(f[root][leaf / 2][0], f[root][leaf / 2][1])); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); int runsum = 0; int pen = 0; int k = 0; while (runsum <= 350 && ((runsum + arr[k]) <= 710) && k < n) runsum += arr[k++]; if (runsum <= 350) { cout << k << 0 << endl; } else { runsum -= 350; pen += runsum; while ((runsum + arr[k]) <= 360 && k < n) { runsum += arr[k++]; pen += runsum; } cout << k << << pen << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> g[200005]; int par[19][200005]; int depth[200005]; int dp[200005]; char s[200005]; void dfs(int u, int p, int d, int val) { par[0][u] = p; depth[u] = d; dp[u] = val ^ (1 << (s[u] - a )); for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == p) continue; dfs(v, u, d + 1, dp[u]); } } int LCA(int a, int b) { if (depth[a] < depth[b]) swap(a, b); int diff = depth[a] - depth[b]; for (int i = 18; i >= 0; i--) { if ((diff >> i) & 1) a = par[i][a]; } if (a == b) return a; for (int i = 18; i >= 0; i--) { if (par[i][a] != par[i][b]) a = par[i][a], b = par[i][b]; } return par[0][a]; } int dist(int a, int b) { return dp[a] ^ dp[b] ^ (1 << (s[LCA(a, b)] - a )); } int nn = 0; int sub[200005]; bool vis[200005]; vector<pair<int, int> > edge[200005]; long long cnt[2000005]; long long ans[200005], add[200005]; void dfs1(int u, int p) { sub[u] = 1; nn++; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == p || vis[v]) continue; dfs1(v, u); sub[u] += sub[v]; } } int dfs2(int u, int p) { for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == p || vis[v]) continue; if (sub[v] > nn / 2) return dfs2(v, u); } return u; } void dfs3(int u, int p, int r, int idx) { int bits = dist(u, r); edge[idx].push_back(pair<int, int>(bits, u)); cnt[bits]++; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == p || vis[v]) continue; dfs3(v, u, r, idx); } } void dfs4(int u, int p) { for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == p || vis[v]) continue; dfs4(v, u); add[u] += add[v]; add[v] = 0; } ans[u] += add[u]; } void decompose(int u, int p) { nn = 0; dfs1(u, u); int centroid = dfs2(u, u); vis[centroid] = 1; for (int i = 0; i < g[centroid].size(); i++) { int v = g[centroid][i]; if (v == p || vis[v]) continue; edge[i].clear(); dfs3(v, centroid, centroid, i); } for (int i = 0; i < g[centroid].size(); i++) { int v = g[centroid][i]; if (v == p || vis[v]) continue; for (int j = 0; j < edge[i].size(); j++) cnt[edge[i][j].first]--; for (int j = 0; j < edge[i].size(); j++) { int bits = edge[i][j].first; int cur = edge[i][j].second; int tot = __builtin_popcount(bits); if (tot <= 1) add[centroid]++, add[cur]++; add[cur] += cnt[bits ^ (1 << (s[centroid] - a ))]; for (int j = 0; j < 20; j++) { add[cur] += cnt[bits ^ (1 << j) ^ (1 << (s[centroid] - a ))]; } } for (int j = 0; j < edge[i].size(); j++) cnt[edge[i][j].first]++; } for (int i = 0; i < g[centroid].size(); i++) { int v = g[centroid][i]; if (v == p || vis[v]) continue; for (int j = 0; j < edge[i].size(); j++) cnt[edge[i][j].first] = 0; } for (int i = 0; i < g[centroid].size(); i++) { int v = g[centroid][i]; if (v == p || vis[v]) continue; dfs4(v, centroid); add[centroid] += add[v]; add[v] = 0; } ans[centroid] += add[centroid] / 2; add[centroid] = 0; for (int i = 0; i < g[centroid].size(); i++) { int v = g[centroid][i]; if (v == p || vis[v]) continue; decompose(v, centroid); } } int main() { int n; scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d%d , &a, &b); g[a].push_back(b); g[b].push_back(a); } scanf( %s , s + 1); dfs(1, 0, 0, 0); for (int j = 1; j <= 18; j++) { for (int i = 1; i <= n; i++) { if (par[j - 1][i] != 0) par[j][i] = par[j - 1][par[j - 1][i]]; } } decompose(1, 0); for (int i = 1; i <= n; i++) printf( %lld , ans[i] + 1); }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the register file
module RegFileWW (rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
//if(rd1en && !((rd1addr==5'bxxxxx) || (rd1addr==5'bzzzzz)))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd1en)
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data<=128'b0;
end
//if(rd2en && (rd2addr!=5'bx) && (rd2addr!=5'bz))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd2en)
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data<=128'b0;
end
end
endmodule
|
module Control(
input [5:0] opcode,
input clk,
output reg reg_dst,
output reg jump,
output reg branch,
output reg ctrl_mem_read,
output reg mem_to_reg,
output reg ctrl_mem_write,
output reg alu_src,
output reg reg_write,
output reg [1:0] alu_op
);
// Control signals from FIgure 4.18, 4.22, & Ref Sheet
always@(posedge clk)
begin
// Initalize signals to 0 to reduce redundancy in if statements
{reg_dst, alu_src, mem_to_reg, reg_write, ctrl_mem_read, ctrl_mem_write, branch, jump, alu_op} = 10'b0000000000;
// R-type
if (opcode == 6'b000000) begin
reg_dst <= 1;
reg_write <= 1;
alu_op <= 2'b10;
end
// Load word
else if (opcode == 6'b100011) begin
alu_src <= 1;
mem_to_reg <= 1;
reg_write <= 1;
ctrl_mem_read <= 1;
end
// Store word
else if (opcode == 6'b101011) begin
alu_src <= 1;
ctrl_mem_write <= 1;
end
// Branch equal
else if (opcode == 6'b000100) begin
branch <= 1;
alu_op <= 2'b01;
end
// Addi
if (opcode == 6'b001000) begin
alu_src <= 1;
reg_write <= 1;
// alu_op <= 2'b10;
end
// Jump
else if (opcode == 6'b000010) begin
jump <= 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O41AI_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; void solve() { ll a, b, p; string s; cin >> a >> b >> p >> s; ll n = s.length(); s[n - 1] = s[n - 2]; vector<ll> cost(n, 0); if (s[n - 1] == A ) cost[n - 1] = a; else cost[n - 1] = b; for (int i = n - 2; i >= 0; i--) { if (s[i] != s[i + 1]) { if (s[i] == A ) cost[i] = cost[i + 1] + a; else cost[i] = cost[i + 1] + b; } else cost[i] = cost[i + 1]; } for (int i = 0; i < n; i++) if (cost[i] <= p) { cout << i + 1 << endl; return; } cout << n << endl; } int main() { int ___T; scanf( %d , &___T); for (int cs = 1; cs <= ___T; cs++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const long long INF = 1000000000; void solve() { long long n; string s; cin >> n; vector<long long> p(n); vector<long long> ans(n); for (int i = 0; i < n; i++) { long long x; cin >> x; p[--x] = i; } cin >> s; long long ones = 1; long long nuls = 1; for (long long i = 0; i < n; i++) if (s[i] == 0 ) ++nuls; for (long long i = 0; i < n; i++) { if (s[p[i]] == 0 ) { ans[p[i]] = ones; ++ones; } else { ans[p[i]] = nuls; ++nuls; } } for (long long i = 0; i < n; i++) cout << ans[i] << ; cout << endl; } int main(void) { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int n0 = 1 << 17; const long long inf = 1e18; int n, a[n0], q; long long d[n0], gaps; struct Node { int l = 0, r = 0; long long val[3]; Node() { val[0] = val[1] = val[2] = -inf; } void init(int pos) { l = r = pos; if (l < 2 || l > n - 1) { val[0] = val[1] = val[2] = -inf; return; } long long d1 = d[l - 1], d2 = d[l]; long long t = -abs(d1) - abs(d2); val[0] = d1 - d2 + t; val[1] = max(d1 + d2, -d1 - d2) + t; val[2] = -d1 + d2 + t; } void merge(Node &x, Node &y) { if (!x.l) { x = y; return; } l = x.l, r = y.r; for (int i = 0; i < 3; i++) val[i] = max(x.val[i], y.val[i]); } long long get(long long x) { return max({-2 * x + val[0], val[1], 2 * x + val[2]}); } }; struct Segtree { Node t[n0 << 1]; void build() { for (int i = (n0 << 1) - 1; i > 0; i--) { if (i >= n0) t[i].init(i - n0); else t[i].merge(t[i << 1], t[i << 1 | 1]); } } void upd(int x) { t[x + n0].init(x); for (x += n0; x > 1; x /= 2) t[x >> 1].merge(t[x], t[x ^ 1]); } Node get(int l, int r) { r++; Node res; for (l += n0, r += n0; l < r; l /= 2, r /= 2) { if (l & 1) res.merge(res, t[l++]); if (r & 1) res.merge(res, t[--r]); } return res; } }; Segtree st; void upd(int x, int y) { gaps -= abs(d[x]); d[x] += y; gaps += abs(d[x]); st.upd(x), st.upd(x + 1); } long long get(int l, int r, long long x) { long long res = st.get(l, r).get(x); if (l == 1) res = max(res, abs(d[1] + x) - abs(d[1])); if (r == n) res = max(res, abs(d[n - 1] - x) - abs(d[n - 1])); return gaps + res; } int main() { ios_base::sync_with_stdio(0), cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n - 1; i++) d[i] = a[i] - a[i + 1], gaps += abs(d[i]); st.build(); cin >> q; while (q--) { int t, l, r, x; cin >> t >> l >> r >> x; if (t == 1) { cout << get(l, r, x) << n ; } else { upd(l - 1, -x), upd(r, x); } } }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 500500, MOD = 1e9 + 7; long long Norm(long long x) { return ((x % MOD + MOD) % MOD); } int n; long long prefsumx[2 * MAX], prefsumy[2 * MAX]; long long prefpov[2 * MAX]; long long prefob[2 * MAX], prefprav[2 * MAX]; pair<int, int> tocke[2 * MAX]; long long UmToc(int a, int b) { return (long long)tocke[a].first * tocke[b].second - (long long)tocke[b].first * tocke[a].second; } long long Suma(long long polje[2 * MAX], int a, int b) { if (a > b) b += n; long long ret = polje[b]; if (a) ret -= polje[a - 1]; return ret; } long long Povrsina(int a, int b) { if (a == b || a + 1 == b) return 0; return Suma(prefpov, a, b - 1) + UmToc(b, a); } void GenPref() { for (int i = 0; i < 2 * n; i++) { prefpov[i] = UmToc(i, i + 1); prefsumx[i] = tocke[i].first; prefsumy[i] = tocke[i].second; if (i) { prefpov[i] += prefpov[i - 1]; prefsumx[i] += prefsumx[i - 1]; prefsumy[i] += prefsumy[i - 1]; } prefsumx[i] = Norm(prefsumx[i]); prefsumy[i] = Norm(prefsumy[i]); } } int main() { scanf( %d , &n); for (int i = n - 1; i >= 0; i--) scanf( %d%d , &tocke[i].first, &tocke[i].second); for (int i = n; i <= 2 * n; i++) tocke[i] = tocke[i % n]; GenPref(); long long summanj = 0; for (int i = 0, j = 1; i < n; i++) { j = max(j, i + 1); for (; Povrsina(i, j) <= Povrsina(j, i); j++) ; j--; if (Povrsina(i, j) == Povrsina(j, i) && i > (j % n)) j--; if (j == i + 1) continue; int kol = j - (i + 1); prefob[i] += kol; prefprav[i + 2]--; prefprav[j + 1]++; summanj = Norm(summanj + Norm(Suma(prefsumx, i + 2, j)) * tocke[i].second - Norm(Suma(prefsumy, i + 2, j)) * tocke[i].first); } long long tprav = 0, tsum = 0; for (int i = 0; i < 2 * n; i++) { tprav += prefprav[i]; tsum += prefob[i] + tprav; tsum = Norm(tsum); summanj = Norm(summanj + Norm(UmToc(i, i + 1)) * tsum); } long long rje = Norm(Norm((long long)n * (n - 3) / 2) * Norm(Povrsina(0, n - 1)) - 2 * summanj); printf( %lld n , rje); return 0; }
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2010,2011,2012
//
// top module for video output.
//
//
// note: the only bandwidths currently in use are 1/8 and 1/4.
module video_top(
input wire clk, // 28 MHz clock
// external video outputs
output wire [ 1:0] vred,
output wire [ 1:0] vgrn,
output wire [ 1:0] vblu,
output wire vhsync,
output wire vvsync,
output wire vcsync,
// aux video inputs
input wire [ 3:0] zxborder, // border zxcolor
// config inputs
input wire [ 1:0] pent_vmode, // 2'b00 - standard ZX
// 2'b01 - hardware multicolor
// 2'b10 - pentagon 16 colors
// 2'b11 - not defined yet
input wire [ 2:0] atm_vmode, // 3'b011 - zx modes (pent_vmode is active)
// 3'b010 - 640x200 hardware multicolor
// 3'b000 - 320x200 16 colors
// 3'b110 - 80x25 text mode
// 3'b??? (others) - not defined yet
input wire scr_page, // screen page (bit 3 of 7FFD)
input wire vga_on, // vga mode ON - scandoubler activated
// memory synchronization inputs
input wire cbeg,
input wire post_cbeg,
input wire pre_cend,
input wire cend,
// memory arbiter video port connection
input wire video_strobe,
input wire video_next,
output wire [20:0] video_addr,
input wire [15:0] video_data,
output wire [ 1:0] video_bw,
output wire video_go,
// atm palette write strobe adn data
input wire atm_palwr,
input wire [ 5:0] atm_paldata,
output wire int_start,
input wire [10:0] fnt_a,
input wire [ 7:0] fnt_d,
input wire fnt_wr,
output wire [ 5:0] palcolor, // for palette readback
output wire [ 7:0] fontrom_readback
);
// these decoded in video_modedecode.v
wire mode_atm_n_pent;
wire mode_zx;
wire mode_p_16c;
wire mode_p_hmclr;
wire mode_a_hmclr;
wire mode_a_16c;
wire mode_a_text;
wire mode_a_txt_1page;
wire mode_pixf_14;
// synchronization
wire hsync_start;
wire line_start;
wire hint_start;
wire vblank;
wire hblank;
wire vpix;
wire hpix;
wire vsync;
wire hsync;
wire vga_hsync;
wire scanin_start;
wire scanout_start;
wire fetch_start;
wire fetch_end;
wire fetch_sync;
wire [63:0] pic_bits;
wire [3:0] pixels;
wire [5:0] color;
wire [5:0] vga_color;
wire [2:0] typos;
// decode video modes
video_modedecode video_modedecode(
.clk(clk),
.pent_vmode(pent_vmode),
.atm_vmode (atm_vmode),
.mode_atm_n_pent (mode_atm_n_pent ),
.mode_zx (mode_zx ),
.mode_p_16c (mode_p_16c ),
.mode_p_hmclr (mode_p_hmclr ),
.mode_a_hmclr (mode_a_hmclr ),
.mode_a_16c (mode_a_16c ),
.mode_a_text (mode_a_text ),
.mode_a_txt_1page(mode_a_txt_1page),
.mode_pixf_14(mode_pixf_14),
.mode_bw(video_bw)
);
// vertical sync generator
video_sync_v video_sync_v(
.clk(clk),
.mode_atm_n_pent(mode_atm_n_pent),
.hsync_start(hsync_start),
.line_start(line_start),
.hint_start(hint_start),
.vblank(vblank),
.vsync(vsync),
.vpix(vpix),
.int_start(int_start)
);
// horizontal sync generator
video_sync_h video_sync_h(
.clk(clk),
.mode_atm_n_pent(mode_atm_n_pent),
.mode_a_text (mode_a_text),
.init(1'b0),
.pre_cend(pre_cend),
.cend (cend ),
.hblank(hblank),
.hsync(hsync),
.hpix(hpix),
.line_start(line_start),
.hsync_start(hsync_start),
.hint_start(hint_start),
.scanin_start(scanin_start),
.fetch_start(fetch_start),
.fetch_end (fetch_end )
);
// address generation
video_addrgen video_addrgen(
.clk(clk),
.video_addr(video_addr),
.video_next(video_next),
.line_start(hsync_start),
.int_start (int_start ),
.vpix (vpix ),
.scr_page(scr_page),
.typos(typos),
.mode_atm_n_pent (mode_atm_n_pent ),
.mode_zx (mode_zx ),
.mode_p_16c (mode_p_16c ),
.mode_p_hmclr (mode_p_hmclr ),
.mode_a_hmclr (mode_a_hmclr ),
.mode_a_16c (mode_a_16c ),
.mode_a_text (mode_a_text ),
.mode_a_txt_1page(mode_a_txt_1page)
);
// data fetch
video_fetch video_fetch(
.clk(clk),
.pre_cend (pre_cend),
.cend (cend ),
.vpix(vpix),
.fetch_start(fetch_start),
.fetch_end (fetch_end ),
.fetch_sync (fetch_sync ),
.video_data (video_data ),
.video_strobe(video_strobe),
.video_go (video_go ),
.pic_bits(pic_bits)
);
// render fetched data to pixels
video_render video_render(
.clk(clk),
.pic_bits(pic_bits),
.fetch_sync(fetch_sync),
.cbeg (cbeg ),
.post_cbeg(post_cbeg),
.pre_cend (pre_cend ),
.cend (cend ),
.int_start(int_start),
.mode_atm_n_pent(mode_atm_n_pent),
.mode_zx (mode_zx ),
.mode_p_16c (mode_p_16c ),
.mode_p_hmclr (mode_p_hmclr ),
.mode_a_hmclr (mode_a_hmclr ),
.mode_a_16c (mode_a_16c ),
.mode_a_text (mode_a_text ),
.mode_pixf_14 (mode_pixf_14 ),
.typos(typos),
.pixels(pixels),
.fnt_a (fnt_a ),
.fnt_d (fnt_d ),
.fnt_wr(fnt_wr),
.fontrom_readback(fontrom_readback)
);
// combine border and pixels, apply palette
video_palframe video_palframe(
.clk(clk),
.hblank(hblank),
.vblank(vblank),
.hpix(hpix),
.vpix(vpix),
.pixels(pixels),
.border(zxborder),
.atm_palwr (atm_palwr ),
.atm_paldata(atm_paldata),
.color(color),
.palcolor(palcolor) // palette readback
);
// VGA hsync doubling
video_vga_sync_h video_vga_sync_h(
.clk(clk),
.hsync_start(hsync_start),
.scanout_start(scanout_start),
.vga_hsync(vga_hsync)
);
// VGA scandoubling
video_vga_double video_vga_double(
.clk(clk),
.hsync_start (hsync_start ),
.scanout_start(scanout_start),
.scanin_start (scanin_start ),
.pix_in(color),
.pix_out(vga_color)
);
// final MUXing of VGA and TV signals
video_outmux video_outmux(
.clk(clk),
.vga_on(vga_on),
.tvcolor(color),
.vgacolor(vga_color),
.vga_hsync(vga_hsync),
.hsync (hsync ),
.vsync (vsync ),
.vred(vred),
.vgrn(vgrn),
.vblu(vblu),
.vhsync(vhsync),
.vvsync(vvsync),
.vcsync(vcsync)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps(1e-8); long long a[100]; long long f[100]; long long dp[100]; long long l, r; long long calc(long long i) { long long ret = 0; for (long long j = (1); j <= (i - 1); ++j) { if (i % j == 0) ret += f[j]; } return ret; } long long solve(long long n) { long long tmp = n; long long top = 0; while (tmp) { a[++top] = tmp % 2; tmp /= 2; } if (top == 1) return 0; long long ret = 0; for (long long i = (1); i <= (top - 1); ++i) ret += calc(i); for (long long i = (1); i <= (top - 1); ++i) if (top % i == 0) { long long now = a[top]; dp[i] = 0; for (long long j = (2); j <= (i); ++j) { if (a[top - j + 1]) dp[i] += 1 << (i - j); now = now * 2 + a[top - j + 1]; } long long tmp = now; for (long long j = (2); j <= (top / i); ++j) tmp = (tmp << i) + now; if (tmp <= n) dp[i]++; for (long long j = (1); j <= (i - 1); ++j) if (i % j == 0) dp[i] -= dp[j]; ret += dp[i]; } return ret; } void cal(long long n) { f[1] = 1; for (long long i = (2); i <= (n); ++i) { f[i] = 1 << (i - 1); for (long long j = (1); j <= (i - 1); ++j) if (i % j == 0) f[i] -= f[j]; } } int main() { cal(70); scanf( %I64d %I64d , &l, &r); printf( %I64d n , solve(r) - solve(l - 1)); }
|
#include <bits/stdc++.h> using namespace std; int ans = 123422412; int n, a, b, x, y; void dfs(int r, int x, int y, int ret) { if (x < 0 || y < 0) return; if (r < 0) return; if (x == 0 && y == 0) { ans = min(ans, ret); return; } dfs(r - a, x - 1, y, ret); dfs(n - a, x - 1, y, ret + 1); dfs(r - b, x, y - 1, ret); dfs(n - b, x, y - 1, ret + 1); } int main() { cin >> n >> a >> b; dfs(n, 4, 2, 1); cout << ans << endl; return 0; }
|
//-------------------------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------------------------------
// Filename : cabac_bae.v
// Author : chewein
// Created : 2014-09-03
// Description : HEVC binary arithmetic encoding
//-------------------------------------------------------------------------------------------
`include "enc_defines.v"
module cabac_bae_stage3(
low_i ,
shift_i ,
t_range_i ,
bin_eq_lps_i ,
bin_neq_mps_i ,
range_i ,
bae_ctx_pair_i ,
low_update_o ,
overflow_bits_num_o ,
overflow_bits_o ,
outstanding_flag_o
);
//-------------------------------------------------------------------------------------------
//
//-------------------------------------------------------------------------------------------
input [ 9:0] low_i ;
input [ 3:0] shift_i ; // regular mode : shift_i if bin==lps
input [ 8:0] t_range_i ; // regular mode : t_range calculated in stage 2
input bin_eq_lps_i ; // regular mode : bin == lps
input bin_neq_mps_i ; // regular mode : t_range >=256
input [ 8:0] range_i ;
input [ 9:0] bae_ctx_pair_i ;
output [ 9:0] low_update_o ;
output [ 2:0] overflow_bits_num_o ;
output [ 5:0] overflow_bits_o ;
output outstanding_flag_o ;
reg [ 9:0] low_update_o ;
reg [ 2:0] overflow_bits_num_o ;
reg [ 5:0] overflow_bits_o ;
reg outstanding_flag_o ;
//-------------------------------------------------------------------------------------------
// calculation low and bits_left: bypass mode
//-------------------------------------------------------------------------------------------
wire [15:0] low_bypass_update_w ;
wire [ 2:0] bypass_overflow_bits_num_w ;// numbers of bins
wire [15:0] low_bypass_w ;
wire [14:0] low_shift_bins_num_w ; // low_shift_bins_num_w = low_i << bins_num
reg [14:0] low_addr_r ; // low_addr_r = range * bins
reg outstanding_bypass_flag_r ;
assign low_shift_bins_num_w = (low_i << bae_ctx_pair_i[7:5]) ;
assign low_bypass_update_w = low_shift_bins_num_w + low_addr_r ;
assign bypass_overflow_bits_num_w= bae_ctx_pair_i[7:5] ;
always @* begin
case(bae_ctx_pair_i[7:5])
3'd1 : outstanding_bypass_flag_r = !(!low_bypass_update_w[15:11]) ;
3'd2 : outstanding_bypass_flag_r = !(!low_bypass_update_w[15:12]) ;
3'd3 : outstanding_bypass_flag_r = !(!low_bypass_update_w[15:13]) ;
3'd4 : outstanding_bypass_flag_r = !(!low_bypass_update_w[15:14]) ;
3'd5 : outstanding_bypass_flag_r = low_bypass_update_w[15 ] ;
default: outstanding_bypass_flag_r = 1'b0 ;
endcase
end
// calculation low_addr_r
always @* begin
case(bae_ctx_pair_i[4:0])
5'd0 : low_addr_r = 11'd0 ;
5'd1 : low_addr_r = (range_i );
5'd2 : low_addr_r = (range_i<<1);
5'd3 : low_addr_r = (range_i<<1) + (range_i) ;
5'd4 : low_addr_r = (range_i<<2) ;
5'd5 : low_addr_r = (range_i<<2) + (range_i) ;
5'd6 : low_addr_r = (range_i<<2) + (range_i<<1) ;
5'd7 : low_addr_r = (range_i<<2) + (range_i<<1)+ range_i ;
5'd8 : low_addr_r = (range_i<<3) ;
5'd9 : low_addr_r = (range_i<<3) + range_i ;
5'd10: low_addr_r = (range_i<<3) + (range_i<<1);
5'd11: low_addr_r = (range_i<<3) + (range_i<<1) + range_i ;
5'd12: low_addr_r = (range_i<<3) + (range_i<<2) ;
5'd13: low_addr_r = (range_i<<3) + (range_i<<2) + range_i ;
5'd14: low_addr_r = (range_i<<3) + (range_i<<2) +(range_i<<1) ;
5'd15: low_addr_r = (range_i<<3) + (range_i<<2) +(range_i<<1) + range_i;
5'd16: low_addr_r = (range_i<<4) ;
5'd17: low_addr_r = (range_i<<4) + (range_i );
5'd18: low_addr_r = (range_i<<4) + (range_i<<1);
5'd19: low_addr_r = (range_i<<4) + (range_i<<1)+ range_i ;
5'd20: low_addr_r = (range_i<<4) + (range_i<<2) ;
5'd21: low_addr_r = (range_i<<4) + (range_i<<2)+ range_i ;
5'd22: low_addr_r = (range_i<<4) + (range_i<<2)+ (range_i<<1) ;
5'd23: low_addr_r = (range_i<<4) + (range_i<<2)+ (range_i<<1) + range_i ;
5'd24: low_addr_r = (range_i<<4) + (range_i<<3) ;
5'd25: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i ) ;
5'd26: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i<<1) ;
5'd27: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i<<1) + range_i ;
5'd28: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i<<2) ;
5'd29: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i<<2) + range_i ;
5'd30: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i<<2) +(range_i<<1) ;
5'd31: low_addr_r = (range_i<<4) + (range_i<<3)+ (range_i<<2) +(range_i<<1) + range_i ;
endcase
end
//-------------------------------------------------------------------------------------------
// calculation low and bits_left : terminal mode
//-------------------------------------------------------------------------------------------
// calculation low
reg [15:0] low_terminal_update_r ;
reg [ 2:0] terminal_overflow_bits_num_r ;
// calculation bits_left
always @* begin
if(bae_ctx_pair_i[7]) begin // bin
low_terminal_update_r = (low_i + t_range_i) ;
terminal_overflow_bits_num_r = 3'd0 ;
end
else if(t_range_i[8]) begin // >=256
low_terminal_update_r = {6'b00_0000,low_i} ;
terminal_overflow_bits_num_r = 3'd0 ;
end
else begin
low_terminal_update_r = {5'b0_0000,low_i,1'b0} ;
terminal_overflow_bits_num_r = 3'd1 ;
end
end
//-------------------------------------------------------------------------------------------
// calculation low and bits_left: regular mode
//-------------------------------------------------------------------------------------------
// calculation low
reg [15:0] low_regular_update_r ;
reg [ 2:0] regular_overflow_bits_num_r ;
wire [10:0] low_m_w = low_i + t_range_i ;
always @* begin
if(bin_eq_lps_i) begin
low_regular_update_r =(low_m_w<<shift_i) ;
regular_overflow_bits_num_r = shift_i[2:0] ;
end
else if(bin_neq_mps_i) begin
low_regular_update_r = {6'b0,low_i} ;
regular_overflow_bits_num_r = 3'd0 ;
end
else begin
low_regular_update_r = {5'b0000_0,low_i,1'b0} ;
regular_overflow_bits_num_r= 3'd1 ;
end
end
//-------------------------------------------------------------------------------------------
// output
//-------------------------------------------------------------------------------------------
always @* begin
case(bae_ctx_pair_i[9:8])
2'b01: low_update_o = low_i ; // 1 : input unvalid
2'b00: low_update_o = low_regular_update_r[9:0] ; // 0 : regular mode
2'b10: low_update_o = low_bypass_update_w[9:0] ; // 2 : bypass mode
2'b11: low_update_o = low_terminal_update_r[9:0] ; // 3 : terminal mode
endcase
end
always @* begin
case(bae_ctx_pair_i[9:8])
2'b01: overflow_bits_num_o = 3'd0 ; // 1 : input unvalid
2'b00: overflow_bits_num_o = regular_overflow_bits_num_r ; // 0 : regular mode
2'b10: overflow_bits_num_o = bypass_overflow_bits_num_w ; // 2 : bypass mode
2'b11: overflow_bits_num_o = terminal_overflow_bits_num_r; // 3 : terminal mode
endcase
end
always @* begin
case(bae_ctx_pair_i[9:8])
2'b01: outstanding_flag_o = 1'b0 ; // 1 : input unvalid
2'b00: outstanding_flag_o = bin_eq_lps_i? low_m_w[10]:1'b0 ; // 0 : regular mode
2'b10: outstanding_flag_o = outstanding_bypass_flag_r ; // 2 : bypass mode
2'b11: outstanding_flag_o = bin_eq_lps_i ? !(!low_terminal_update_r[15:10]):1'b0; // 3 : terminal mode
endcase
end
always @* begin
case(bae_ctx_pair_i[9:8])
2'b01: overflow_bits_o = 6'b00_0000 ; // 1 : input unvalid
2'b00: overflow_bits_o = low_regular_update_r[15:10] ; // 0 : regular mode
2'b10: overflow_bits_o = low_bypass_update_w[15:10] ; // 2 : bypass mode
2'b11: overflow_bits_o = low_terminal_update_r[15:10] ; // 3 : terminal mode
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[9], aa[9]; int c[9], cc[9]; int n; int ans; void dfs(int u, int cnt, int self) { if (u == n) { ans = min(ans, cnt + (self > 1)); return; } dfs(u + 1, cnt + cc[u] + (c[u] != 1), self + 1); for (int i = u + 1; i < n; i++) if (aa[i] % a[u] == 0) { aa[i] /= a[u]; cc[i] -= c[u]; dfs(u + 1, cnt + cc[u] + (c[u] != 1), self); aa[i] *= a[u]; cc[i] += c[u]; } } int main() { int i, j; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %I64d , &a[i]); sort(a, a + n); for (i = 0; i < n; i++) { long long x = a[i]; long long m = sqrt(x + 0.5); for (j = 2; j <= m; j++) while (x % j == 0) { c[i]++; x /= j; } if (x > 1) c[i]++; aa[i] = a[i]; cc[i] = c[i]; } ans = 1e9; dfs(0, 0, 0); printf( %d n , ans); return 0; }
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931284189480;
wire exception_139931285570480;
wire exception_139931284422240;
wire exception_139931274882800;
wire exception_139931273553680;
wire exception_139931274599816;
wire exception_139931276868136;
wire exception_139931279337376;
wire exception_139931276957744;
wire exception_139931281004592;
wire exception_139931285454504;
wire exception_139931285455144;
wire exception_139931277549224;
wire exception_139931279225056;
wire exception_139931275538584;
wire exception_139931284222104;
main_0 main_0_139931284189480(
.clk(clk),
.rst(rst),
.exception(exception_139931284189480),
.input_eth_in(input_eth_rx),
.input_eth_in_stb(input_eth_rx_stb),
.input_eth_in_ack(input_eth_rx_ack),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_eth_out(output_eth_tx),
.output_eth_out_stb(output_eth_tx_stb),
.output_eth_out_ack(output_eth_tx_ack));
main_1 main_1_139931285570480(
.clk(clk),
.rst(rst),
.exception(exception_139931285570480),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931284422240(
.clk(clk),
.rst(rst),
.exception(exception_139931284422240),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931274882800(
.clk(clk),
.rst(rst),
.exception(exception_139931274882800),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931273553680(
.clk(clk),
.rst(rst),
.exception(exception_139931273553680),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_5 main_5_139931274599816(
.clk(clk),
.rst(rst),
.exception(exception_139931274599816),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_6 main_6_139931276868136(
.clk(clk),
.rst(rst),
.exception(exception_139931276868136),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_7 main_7_139931279337376(
.clk(clk),
.rst(rst),
.exception(exception_139931279337376),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_8 main_8_139931276957744(
.clk(clk),
.rst(rst),
.exception(exception_139931276957744),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_9 main_9_139931281004592(
.clk(clk),
.rst(rst),
.exception(exception_139931281004592),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_10 main_10_139931285454504(
.clk(clk),
.rst(rst),
.exception(exception_139931285454504),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_11 main_11_139931285455144(
.clk(clk),
.rst(rst),
.exception(exception_139931285455144),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_12 main_12_139931277549224(
.clk(clk),
.rst(rst),
.exception(exception_139931277549224),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_13 main_13_139931279225056(
.clk(clk),
.rst(rst),
.exception(exception_139931279225056),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_14 main_14_139931275538584(
.clk(clk),
.rst(rst),
.exception(exception_139931275538584),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_15 main_15_139931284222104(
.clk(clk),
.rst(rst),
.exception(exception_139931284222104),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931284189480 || exception_139931285570480 || exception_139931284422240 || exception_139931274882800 || exception_139931273553680 || exception_139931274599816 || exception_139931276868136 || exception_139931279337376 || exception_139931276957744 || exception_139931281004592 || exception_139931285454504 || exception_139931285455144 || exception_139931277549224 || exception_139931279225056 || exception_139931275538584 || exception_139931284222104;
endmodule
|
module ok2wbm(
// Wishbone master interface
input wire wb_clk_i,
input wire wb_rst_i,
input wire wb_ack_i,
input wire wb_int_i,
output reg wb_cyc_o,
output reg wb_stb_o,
output reg wb_we_o,
input wire [15:0] wb_data_i,
output reg [15:0] wb_data_o,
output wire [4:0] wb_addr_o,
output wire [1:0] wb_sel_o,
output reg [2:0] wb_cti_o,
// Status triggers and signals
output wire trg_irq,
output wire trg_done,
output wire busy,
// Transaction triggers and signals
input wire trg_sngl_rd,
input wire trg_sngl_wr,
input wire trg_brst_rd,
input wire trg_brst_wr,
input wire brst_rd,
input wire brst_wr,
// Address
input wire [15:0] addr_in,
// Single transaction data ports
input wire [15:0] sngl_data_in,
output reg [15:0] sngl_data_out,
// Burst transaction data ports
input wire [15:0] brst_data_in,
output wire [15:0] brst_data_out,
// Debug
output wire [15:0] debug_out
);
// DEBUG!
assign debug_out = sngl_data_out;
// May need to change in future - for now everything is 16bit wide
assign wb_sel_o = 2'b11;
// Start of Transaction (SOT) - both single and burst mdoes
wire sot;
assign sot = trg_sngl_rd | trg_sngl_wr | trg_brst_rd | trg_delay_wr[1];
// End of Transaction (EOT) - burst mode only
wire eot;
assign eot = wb_stb_o & ((wb_we_o & ~brst_wr) | (rd_burst_live & ~brst_rd));
// Delay the write trigger to get data to align with Opal Kelly BT Pipe
reg [1:0] trg_delay_wr;
always @(posedge wb_clk_i) begin
trg_delay_wr <= {trg_delay_wr[0], trg_brst_wr};
end
// Detect burst mode
reg rd_burst_live;
reg wr_burst_live;
always @(posedge wb_clk_i) begin
// Set by burst triggers or itself. Cleared by EOT or reset
rd_burst_live <= (trg_brst_rd | rd_burst_live) & ~(eot | wb_rst_i);
wr_burst_live <= (trg_delay_wr[1] | wr_burst_live) & ~(eot | wb_rst_i);
end
// Denote when the system is using burst-mode functionality
wire burst_mode;
assign burst_mode = rd_burst_live | wr_burst_live;
// End of Transation - both modes
assign trg_done = (wb_ack_i & ~burst_mode) | eot;
// Transaction type identification
always @(burst_mode or eot) begin
if (burst_mode & ~eot)
wb_cti_o = 3'b001; // Constant address
else if (burst_mode & eot)
wb_cti_o = 3'b111; // Last transaction of burst
else
wb_cti_o = 3'b000; // Classic transaction type
end
// Frame transaction
always @(posedge wb_clk_i) begin
// Set by SOT or itself, cleared by trg_done or RST
wb_cyc_o <= (sot | wb_cyc_o) & ~(trg_done | wb_rst_i);
wb_stb_o <= (sot | wb_stb_o) & ~(trg_done | wb_rst_i);
end
assign busy = wb_cyc_o;
// Put one clock delay on incoming data to align with WB control signals
always @(posedge wb_clk_i) begin
if (burst_mode)
wb_data_o <= brst_data_in;
else
wb_data_o <= sngl_data_in;
end
// Straight pass-throughs
assign wb_addr_o = addr_in[4:0];
assign irq = wb_int_i;
assign brst_data_out = wb_data_i;
// Read handling
always @(posedge wb_clk_i) begin
// Latch on ACK - qualify with STB and CYC
if (wb_ack_i && wb_stb_o && wb_cyc_o)
sngl_data_out <= wb_data_i;
else
sngl_data_out <= sngl_data_out; // Explicit latch
end
// Write enable
always @(posedge wb_clk_i) begin
// Set by single write, write burst live, or itself; cleared by trg_done or RST
wb_we_o <= (trg_sngl_wr | wr_burst_live | wb_we_o) & ~(trg_done | wb_rst_i);
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Parameter LE tells us if we are little-endian.
// Little-endian means send lower 16 bits first.
// Default is big endian (network order), send upper bits first.
module fifo36_to_fifo19
#(parameter LE=0)
(input clk, input reset, input clear,
input [35:0] f36_datain,
input f36_src_rdy_i,
output f36_dst_rdy_o,
output [18:0] f19_dataout,
output f19_src_rdy_o,
input f19_dst_rdy_i );
wire [18:0] f19_data_int;
wire f19_src_rdy_int, f19_dst_rdy_int;
wire [35:0] f36_data_int;
wire f36_src_rdy_int, f36_dst_rdy_int;
// Shortfifo on input to guarantee no deadlock
fifo_short #(.WIDTH(36)) head_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
.dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
.space(),.occupied() );
// Main fifo36_to_fifo19, needs shortfifos to guarantee no deadlock
wire [1:0] f36_occ_int = f36_data_int[35:34];
wire f36_sof_int = f36_data_int[32];
wire f36_eof_int = f36_data_int[33];
reg phase;
wire half_line = f36_eof_int & ((f36_occ_int==1)|(f36_occ_int==2));
assign f19_data_int[15:0] = (LE ^ phase) ? f36_data_int[15:0] : f36_data_int[31:16];
assign f19_data_int[16] = phase ? 0 : f36_sof_int;
assign f19_data_int[17] = phase ? f36_eof_int : half_line;
assign f19_data_int[18] = f19_data_int[17] & ((f36_occ_int==1)|(f36_occ_int==3));
assign f19_src_rdy_int = f36_src_rdy_int;
assign f36_dst_rdy_int = (phase | half_line) & f19_dst_rdy_int;
wire f19_xfer = f19_src_rdy_int & f19_dst_rdy_int;
wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int;
always @(posedge clk)
if(reset)
phase <= 0;
else if(f36_xfer)
phase <= 0;
else if(f19_xfer)
phase <= 1;
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(19)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
.dataout(f19_dataout), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
.space(),.occupied() );
endmodule // fifo36_to_fifo19
|
#include <bits/stdc++.h> using namespace std; inline int nxt() { int x; scanf( %d , &x); return x; } const int N = 55; int a[N][N]; char skdjflfsdj[N][N]; int score[N]; void add(int u, int v, int x) { a[u][v] += x; score[u] += x; } vector<int> all_out(int v, int n) { vector<char> used(n); vector<int> st = {v}; used[v] = 1; vector<int> par(n, -1); while (!st.empty()) { int u = st.back(); st.pop_back(); for (int i = 0; i < n; ++i) { if (!skdjflfsdj[i][u] && a[u][i]) { if (!used[i]) { used[i] = 1; par[i] = u; st.push_back(i); } } } } return par; } int main() { mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int n = nxt(), m = nxt(); for (int i = 0; i < m; ++i) { int u = nxt() - 1, v = nxt() - 1; add(u, v, 1); skdjflfsdj[u][v] = skdjflfsdj[v][u] = 1; } for (int i = 0; i < n; ++i) { for (int j = 0; j < i; ++j) { if (!skdjflfsdj[i][j]) { if (rng() % 2) { add(i, j, 1); } else { add(j, i, 1); } } } } while (true) { bool ok = false; for (int i = 0; i < n; ++i) { if (ok) { break; } auto par = all_out(i, n); for (int j = 0; j < n; ++j) { if (i != j && par[j] > -1 && score[j] < score[i] - 1) { for (int u = j; u != i; u = par[u]) { add(u, par[u], 1); add(par[u], u, -1); } ok = true; break; } } } if (!ok) { break; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cout << a[i][j]; } cout << n ; } return 0; }
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("select3.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("select3_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(trap, `TYPES_MISMATCH);
$finish;
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module combines two video streams by overlaying one onto the *
* other using alpha blending. The foreground image must include alpha *
* bits to be used in the blending formula: Cn = (1 - a)Cb + (a)Cf *
* Cn - new color *
* a - alpha *
* Cb - background colour *
* Cf - foreground colour *
* *
******************************************************************************/
module soc_system_vga_alpha (
// Inputs
clk,
reset,
background_data,
background_startofpacket,
background_endofpacket,
background_empty,
background_valid,
foreground_data,
foreground_startofpacket,
foreground_endofpacket,
foreground_empty,
foreground_valid,
output_ready,
// Bidirectionals
// Outputs
background_ready,
foreground_ready,
output_data,
output_startofpacket,
output_endofpacket,
output_empty,
output_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [29: 0] background_data;
input background_startofpacket;
input background_endofpacket;
input [ 1: 0] background_empty;
input background_valid;
input [39: 0] foreground_data;
input foreground_startofpacket;
input foreground_endofpacket;
input [ 1: 0] foreground_empty;
input foreground_valid;
input output_ready;
// Bidirectionals
// Outputs
output background_ready;
output foreground_ready;
output [29: 0] output_data;
output output_startofpacket;
output output_endofpacket;
output [ 1: 0] output_empty;
output output_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] new_red;
wire [ 9: 0] new_green;
wire [ 9: 0] new_blue;
wire sync_foreground;
wire sync_background;
wire valid;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign background_ready = (output_ready & output_valid) | sync_background;
assign foreground_ready = (output_ready & output_valid) | sync_foreground;
assign output_data = {new_red, new_green, new_blue};
assign output_startofpacket = foreground_startofpacket;
assign output_endofpacket = foreground_endofpacket;
assign output_empty = 2'h0;
assign output_valid = valid;
// Internal Assignments
assign sync_foreground = (foreground_valid & background_valid &
((background_startofpacket & ~foreground_startofpacket) |
(background_endofpacket & ~foreground_endofpacket)));
assign sync_background = (foreground_valid & background_valid &
((foreground_startofpacket & ~background_startofpacket) |
(foreground_endofpacket & ~background_endofpacket)));
assign valid = foreground_valid & background_valid &
~sync_foreground & ~sync_background;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_alpha_blender_simple alpha_blender (
// Inputs
.background_data (background_data),
.foreground_data (foreground_data),
// Bidirectionals
// Outputs
.new_red (new_red),
.new_green (new_green),
.new_blue (new_blue)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_1_V
`define SKY130_FD_SC_HD__O21BAI_1_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_1_V
|
`include "../source/alu.v"
module testALU;
task assert;
input cond;
begin
if (!cond) begin
$display("Error!");
$finish;
end
end;
endtask
reg[15:0] a;
reg[15:0] b;
reg[3:0] func;
reg ci;
wire[3:0] flags;
wire[15:0] y;
wire[15:0] toA;
alu alu1 (
.a (a),
.b (b),
.func (func),
.ci (ci),
.y (y),
.co (flags[3]),
.negative (flags[2]),
.zero (flags[1]),
.overflow (flags[0]),
.outToA (toA)
);
initial begin
$dumpfile ("../test.vcd");
$dumpvars;
end
/*initial begin
$display ("\t\ttime,\ta,\tb,\tfunc,\tata,\twe");
$monitor ( "%d,\t%b,\t%4h,\t%2h,\t%2h,\t%b",
$time, clk, addr, wdata, rdata, we);
end*/
initial begin
a = 0;
b = 0;
func = 4'b0000; // ADD
ci = 0;
#9 assert (y === 0 && flags === 4'b0010); #1
a = 15;
b = 25;
#9 assert (y === 40 && flags === 4'b0000); #1
a = -10;
b = 70;
#9 assert (y === 60 && flags === 4'b1000); #1
a = 16'h4000;
b = 16'h4000;
#9 assert (y === 16'h8000 && flags === 4'b0101); #1
a = 16'h8000;
b = 16'h8000;
#9 assert (y === 0 && flags === 4'b1011); #1
a = -1;
b = 1;
#9 assert (y === 0 && flags === 4'b1010); #1
func = 4'b0001; // ADC
a = -10;
b = 70;
#9 assert (y === 60 && flags === 4'b1000); #1
ci = 1;
#9 assert (y === 61 && flags === 4'b1000); #1
func = 4'b0010; // SUB
#9 assert (y === -16'd80 && flags === 4'b0100); #1
func = 4'b0011; // SBC
#9 assert (y === -16'd81 && flags === 4'b0100); #1
ci = 0;
func = 4'b0100; // MUL
a = 7; b = 6;
#9 assert (y === 42 && flags === 4'b0000); #1
a = 7; b = -6;
#9 assert (y === -16'd42 && flags === 4'b0100); #1
a = -7; b = -6;
#9 assert (y === 42 && flags === 4'b0000); #1
a = 256; b = 256;
#9 assert (y === 0 && toA === 1 && flags === 4'b0000); #1
func = 4'b0101; //MLL
a = 7; b = 6;
#9 assert (y === 42 && flags === 4'b0000); #1
a = 7; b = -6;
#9 assert (y === -16'd42 && flags === 4'b0100); #1
a = -7; b = -6;
#9 assert (y === 42 && flags === 4'b0000); #1
func = 4'b0111; //RAS
a = 15; b = 2;
#9 assert (y === 3 && flags === 4'b1000); #1
a = -15; b = 2;
#9 assert (y === -16'd4 && flags === 4'b0100); #1
func = 4'b1000; //LSH
a = 16'b100101; b = 1;
#9 assert (y === 16'b1001010 && flags === 4'b0000); #1
b = 2;
#9 assert (y === 16'b10010100 && flags === 4'b0000); #1
a = 2; b = 15;
#9 assert (y === 0); #1
func = 4'b1001; //RSH
a = 16'b100101; b = 1;
#9 assert (y === 16'b10010 && flags === 4'b1000); #1
b = 2;
#9 assert (y === 16'b1001 && flags === 4'b0000); #1
func = 4'b1010; //LRT
a = 16'b1000000000001010; b = 1;
#9 assert (y === 16'b10101 && flags === 4'b0000); #1
b = 2;
#9 assert (y === 16'b101010 && flags === 4'b0000); #1
func = 4'b1011; //RRT
b = 1;
#9 assert (y === 16'b0100000000000101 && flags === 4'b0000); #1
b = 2;
#9 assert (y === 16'b1010000000000010 && flags === 4'b0100); #1
func = 4'b1100; //AND
a = 16'b0011001100110011;
b = 16'b0101010101010101;
#9 assert (y === 16'b0001000100010001 && flags === 4'b0000); #1
func = 4'b1101; //OR
#9 assert (y === 16'b0111011101110111 && flags === 4'b0000); #1
func = 4'b1110; //XOR
#9 assert (y === 16'b0110011001100110 && flags === 4'b0000); #1
func = 4'b1111; //NOT
#9 assert (y === 16'b1100110011001100 && flags === 4'b0100); #1
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s, ans; bool flag = 0; int main() { cin >> s; for (int i = 0; i < s.length(); ++i) { if (s[i] == / ) { if (!flag) { ans += s[i]; flag = 1; } } else { ans += s[i]; flag = 0; } } if (ans.length() > 1 && ans[ans.length() - 1] == / ) ans = ans.substr(0, ans.length() - 1); cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long t; cin >> t; while (t--) { long long n; cin >> n; char c; cin >> c; string str; cin >> str; long long ctr = 0; long long k = 0; for (long long i = 0; i < n; i++) { if (str[i] != c) { ctr++; k = i; } } if (ctr == 0) { cout << 0; } else if (ctr == 1) { if (k == n - 1) { cout << 1 << n ; cout << k; } else { cout << 1 << n ; cout << k + 2; } } else { long long flag = 0; for (long long i = n - 1; i >= n / 2; i--) { if (str[i] == c) { flag = i; break; } } if (flag) { cout << 1 << n ; cout << flag + 1; } else { cout << 2 << n ; cout << n << << n - 1; } } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[111]; int main() { int n; scanf( %d , &n); for (int i = (0); i < (n); ++i) scanf( %d , &arr[i]); sort(arr, arr + n); int t = 10; int ans = 0; int qts = 0; for (int i = (0); i < (n); ++i) { t += arr[i]; if (t > 720) break; qts++; if (t > 360) ans += (t - 360); } printf( %d %d n , qts, ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<string> strs; int n = 0; int j = 0; int count = 0; cin >> n; for (int i = 0; i < n; i++) { if (i != 0) { string temp = ; cin >> temp; } string str1 = ; string str2 = ; string str3 = ; string str4 = ; string str5 = ; string str6 = ; cin >> str1 >> str2; str3 += str1.at(0); str3 += str1.at(1); str3 += str2.at(0); str3 += str2.at(1); str3 += str3; str4 += str2.at(0); str4 += str1.at(0); str4 += str2.at(1); str4 += str1.at(1); str4 += str4; str5 += str2.at(1); str5 += str2.at(0); str5 += str1.at(1); str5 += str1.at(0); str5 += str5; str6 += str1.at(1); str6 += str2.at(1); str6 += str1.at(0); str6 += str2.at(0); str6 += str6; if (i == 0) { strs.push_back(str3); strs.push_back(str4); strs.push_back(str5); strs.push_back(str6); count++; } else { bool check = false; for (int j = 0; j < strs.size(); j++) { if (!strs[j].find(str1 + str2)) { check = true; break; } } if (!check) { strs.push_back(str3); strs.push_back(str4); strs.push_back(str5); strs.push_back(str6); count++; } } } cout << count << endl; return 0; }
|
module \$__NX_PDP16K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_A = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'b0;
parameter _TECHMAP_BITS_CONNMAP_ = 8;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_CLK2_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_CLK3_ = 0;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR;
output [CFG_DBITS-1:0] B1DATA;
input B1EN;
// Address is left justified, in x18 and above lower bits are byte enables
localparam A_SHIFT =
(CFG_DBITS == 36) ? 5 :
(CFG_DBITS == 18) ? 4 :
(CFG_DBITS == 9) ? 3 :
(CFG_DBITS == 4) ? 2 :
(CFG_DBITS == 2) ? 1 :
0;
// Different primitives needed for single vs dual clock case
localparam SINGLE_CLOCK = (_TECHMAP_CONNMAP_CLK2_ == _TECHMAP_CONNMAP_CLK3_);
localparam WIDTH = $sformatf("X%d", CFG_DBITS);
wire [13:0] ra, wa;
wire [35:0] rd, wd;
assign ra = {B1ADDR, {A_SHIFT{1'b1}}};
generate
if (CFG_ENABLE_A > 1)
assign wa = {A1ADDR, {(A_SHIFT-CFG_ENABLE_A){1'b1}}, A1EN};
else
assign wa = {A1ADDR, {A_SHIFT{1'b1}}};
endgenerate
assign wd = A1DATA;
assign B1DATA = rd[CFG_DBITS-1:0];
wire wck, rck;
generate
if (CLKPOL2)
assign wck = CLK2;
else
INV wck_inv_i (.A(CLK2), .Z(wck));
if (CLKPOL3)
assign rck = CLK3;
else
INV wck_inv_i (.A(CLK3), .Z(rck));
endgenerate
wire we = |A1EN;
localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 4) ? 256 : 288;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
if (CFG_DBITS <= 4) begin
for (i = 0; i < 32; i = i + 1'b1)
permute_init[i * 10 +: 10] = {2'b00, chunk[i * 8 +: 8]};
end else begin
for (i = 0; i < 32; i = i + 1'b1)
permute_init[i * 10 +: 10] = {1'b0, chunk[i * 9 +: 9]};
end
end
endfunction
generate
if (SINGLE_CLOCK) begin
PDPSC16K #(
.DATA_WIDTH_W(WIDTH),
.DATA_WIDTH_R(WIDTH),
.OUTREG("BYPASSED"),
.ECC("DISABLED"),
.GSR("DISABLED"),
`include "brams_init.vh"
) _TECHMAP_REPLACE_ (
.CLK(wck), .RST(1'b0),
.DI(wd), .ADW(wa), .CEW(we), .CSW(3'b111),
.ADR(ra), .DO(rd), .CER(B1EN), .CSR(3'b111)
);
end else begin
PDP16K #(
.DATA_WIDTH_W(WIDTH),
.DATA_WIDTH_R(WIDTH),
.OUTREG("BYPASSED"),
.ECC("DISABLED"),
.GSR("DISABLED"),
`include "brams_init.vh"
) _TECHMAP_REPLACE_ (
.CLKW(wck), .CLKR(rck), .RST(1'b0),
.DI(wd), .ADW(wa), .CEW(we), .CSW(3'b111),
.ADR(ra), .DO(rd), .CER(B1EN), .CSR(3'b111)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> long long cacu(long long l, long long r) { return (r + l) / 2 * ((r - l) / 2 + 1); } int main() { int q, l, r; scanf( %d , &q); while (q--) { long long ans; scanf( %d%d , &l, &r); ans = cacu(l + (l & 1), r - (r & 1)); ans -= cacu(l | 1, r - !(r & 1)); printf( %lld n , ans); } return 0; }
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for iq_join
*/
module test_iq_join;
// Parameters
parameter WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_i_tdata = 0;
reg input_i_tvalid = 0;
reg [WIDTH-1:0] input_q_tdata = 0;
reg input_q_tvalid = 0;
reg output_tready = 0;
// Outputs
wire input_i_tready;
wire input_q_tready;
wire [WIDTH-1:0] output_i_tdata;
wire [WIDTH-1:0] output_q_tdata;
wire output_tvalid;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_i_tdata,
input_i_tvalid,
input_q_tdata,
input_q_tvalid,
output_tready);
$to_myhdl(input_i_tready,
input_q_tready,
output_i_tdata,
output_q_tdata,
output_tvalid);
// dump file
$dumpfile("test_iq_join.lxt");
$dumpvars(0, test_iq_join);
end
iq_join #(
.WIDTH(WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.input_i_tdata(input_i_tdata),
.input_i_tvalid(input_i_tvalid),
.input_i_tready(input_i_tready),
.input_q_tdata(input_q_tdata),
.input_q_tvalid(input_q_tvalid),
.input_q_tready(input_q_tready),
.output_i_tdata(output_i_tdata),
.output_q_tdata(output_q_tdata),
.output_tvalid(output_tvalid),
.output_tready(output_tready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_PP_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
module Board232 (
input mclk,
input [3:0] btn,
input [7:0] sw,
output [7:0] led,
output reg [6:0] seg,
output reg [3:0] an,
output dp,
output [2:1] OutBlue,
output [2:0] OutGreen,
output [2:0] OutRed,
output HS,
output VS
);
assign dp = 1'b1;
//assign led[7:2]=0;
initial begin
seg[6:0] = 7'b0111111;
an[3:0] = 4'b0000; // 7 segmentte hangi yerler yanacak
end
// YOU SHOULD CHANGE THESE
parameter INT4 = 8'b10000000;
parameter INT3 = 8'b00000000;
parameter INT2= 8'b00000000;
// adjust board clock
reg [26:0] mclk_counter;
initial mclk_counter<= 0;
always @(posedge mclk) mclk_counter = mclk_counter+1;
// select clock : 26->slower | 24->faster
reg clk;
initial clk = 1'b0;
always@(btn[3] or mclk_counter[25] or btn[0])
begin
if(btn[3])
clk = mclk_counter[25];
else
clk = btn[0];
end
reg tmp_digit;
wire READY;
wire [7:0] STREAM;
VBEncoder ins (clk,
INT4,INT3,INT2,sw[7:0],
btn[1],
READY,
led[7:0]
);
always @(mclk_counter[18:17])
begin
case (mclk_counter[18:17])
2'b00:
begin
an = 4'b1110;
tmp_digit = READY;
end
default:
begin
an = 4'b1111;
end
endcase
case (tmp_digit)
4'd0: seg <= ~7'h3F;
4'd1: seg <= ~7'h06;
4'd2: seg <= ~7'h5B;
4'd3: seg <= ~7'h4F;
4'd4: seg <= ~7'h66;
4'd5: seg <= ~7'h6D;
4'd6: seg <= ~7'h7D;
4'd7: seg <= ~7'h07;
4'd8: seg <= ~7'h7F;
4'd9: seg <= ~7'h6F;
4'd10: seg <= ~7'h77;
4'd11: seg <= ~7'h7C;
4'd12: seg <= ~7'h39;
4'd13: seg <= ~7'h5E;
4'd14: seg <= ~7'h79;
4'd15: seg <= ~7'h71;
default: seg <= ~7'b0000000;
endcase
end
// VGA
assign OutBlue = 0;
assign OutGreen = 0;
assign OutRed = 0;
assign HS = 0;
assign VS = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; while (cin >> n) { string s; cin >> s; long long a0 = 0, a1 = 0, a2 = 0; for (long long i = 0; i < s.size(); i++) { if (s[i] == 0 ) { a0++; } else if (s[i] == 1 ) { a1++; } else { a2++; } } long long d = s.size() / 3; long long x = 0, y = 0, z = 0; for (long long i = s.size() - 1; i >= 0; i--) { if (s[i] == 1 ) { if (a1 > d && a2 < d) { s[i] = 2 ; a2++; a1--; } } if (s[i] == 0 ) { if (a0 > d && a2 < d) { s[i] = 2 ; a2++; a0--; } } } for (long long i = 0; i < s.size(); i++) { if (s[i] == 1 ) { if (a1 > d && a0 < d) { s[i] = 0 ; a0++; a1--; } } if (s[i] == 2 ) { if (a2 > d && a0 < d) { s[i] = 0 ; a0++; a2--; } } } for (long long i = 0; i < s.size(); i++) { if (s[i] == 2 ) { if (a2 > d && a1 < d) { s[i] = 1 ; a1++; a2--; } } if (s[i] == 0 ) { if (a0 > d && a1 < d && x >= d) { s[i] = 1 ; a1++; a0--; } x++; } } cout << s << endl; } return 0; }
|
#include <bits/stdc++.h> template <typename T> inline void rd(T& x) { int si = 1; char c = getchar(); x = 0; while (!isdigit(c)) si = c == - ? -1 : si, c = getchar(); while (isdigit(c)) x = x * 10 + c - 48, c = getchar(); x *= si; } template <typename T, typename... Args> inline void rd(T& x, Args&... args) { rd(x); rd(args...); } const int kN = 4e5 + 5, kInf = 0x3f3f3f3f; const long long kMod = 998244353, kInfLL = 0x3f3f3f3f3f3f3f3fLL; long long QPow(long long a, long long b) { long long ans = 1, bas = a; for (; b; b >>= 1, bas = bas * bas % kMod) if (b & 1) ans = ans * bas % kMod; return ans; } struct Edge { int u, v, c; } E[kN]; int n, m, fa[kN], s[kN], col[kN], cnt[kN]; std::vector<int> pt[2]; bool flag = false; int Find(int x) { return fa[x] == x ? x : fa[x] = Find(fa[x]); } void Merge(int x, int y) { int fx = Find(x), fy = Find(y); if (fx == fy) return; s[fx] += s[fy]; fa[fy] = fx; } void Solve(int x) { memset(col, 0xff, sizeof(col)); for (int i = 1; i <= 2 * n; ++i) { fa[i] = i; s[i] = (i <= n); } for (int i = 1; i <= m; ++i) { int u = E[i].u, v = E[i].v, c = E[i].c ^ x; if (c) Merge(u, v), Merge(u + n, v + n); else Merge(u + n, v), Merge(u, v + n); } for (int i = 1; i <= n; ++i) if (Find(i) == Find(i + n)) return; flag = true; for (int i = 1; i <= n; ++i) if (col[Find(i)] == -1) { col[Find(i)] = (s[Find(i)] < s[Find(i + n)]); col[Find(i + n)] = !col[Find(i)]; } cnt[x] = 0; for (int i = 1; i <= n; ++i) if (col[Find(i)] == 1) { ++cnt[x]; pt[x].push_back(i); } } int main() { int T = 1; while (T--) { rd(n, m); cnt[0] = cnt[1] = kInf; for (int i = 1; i <= m; ++i) { char c[5]; rd(E[i].u, E[i].v); scanf( %s , c + 1); E[i].c = (c[1] == B ); } for (int i = 0; i < 2; ++i) Solve(i); if (flag) { if (cnt[0] < cnt[1]) { printf( %d n , cnt[0]); for (auto i : pt[0]) printf( %d , i); } else { printf( %d n , cnt[1]); for (auto i : pt[1]) printf( %d , i); } } else printf( -1 ); } return 0; }
|
// megafunction wizard: %LPM_MUX%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counterselect.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module counterselect (
data0x,
data1x,
data2x,
data3x,
sel,
result);
input [20:0] data0x;
input [20:0] data1x;
input [20:0] data2x;
input [20:0] data3x;
input [1:0] sel;
output [20:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: data0x 0 0 21 0 INPUT NODEFVAL "data0x[20..0]"
// Retrieval info: USED_PORT: data1x 0 0 21 0 INPUT NODEFVAL "data1x[20..0]"
// Retrieval info: USED_PORT: data2x 0 0 21 0 INPUT NODEFVAL "data2x[20..0]"
// Retrieval info: USED_PORT: data3x 0 0 21 0 INPUT NODEFVAL "data3x[20..0]"
// Retrieval info: USED_PORT: result 0 0 21 0 OUTPUT NODEFVAL "result[20..0]"
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
// Retrieval info: CONNECT: @data 0 0 21 0 data0x 0 0 21 0
// Retrieval info: CONNECT: @data 0 0 21 21 data1x 0 0 21 0
// Retrieval info: CONNECT: @data 0 0 21 42 data2x 0 0 21 0
// Retrieval info: CONNECT: @data 0 0 21 63 data3x 0 0 21 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: CONNECT: result 0 0 21 0 @result 0 0 21 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int solve(int t) { int a, b, c, rem = 0, sum = 0; while (t != 0) { rem = t % 10; sum += rem; t /= 10; } if (sum % 4 == 0) return 1; return 0; } int main() { int t, n, flag = 0; cin >> t; while (1) { flag = solve(t); if (flag == 1) { cout << t << n ; break; } else t++; } return 0; }
|
/*
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| eg_step_ram/ | | 3/3 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_step |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
*/
module eg_step_ram(
input [2:0] state_V,
input [5:0] rate_V,
input [2:0] cnt_V,
output reg step_V
);
localparam ATTACK=3'd0, DECAY1=3'd1, DECAY2=3'd2, RELEASE=3'd7, HOLD=3'd3;
reg [7:0] step_idx;
reg [7:0] step_ram;
always @(*)
case( { rate_V[5:4]==2'b11, rate_V[1:0]} )
3'd0: step_ram = 8'b00000000;
3'd1: step_ram = 8'b10001000; // 2
3'd2: step_ram = 8'b10101010; // 4
3'd3: step_ram = 8'b11101110; // 6
3'd4: step_ram = 8'b10101010; // 4
3'd5: step_ram = 8'b11101010; // 5
3'd6: step_ram = 8'b11101110; // 6
3'd7: step_ram = 8'b11111110; // 7
endcase
always @(*) begin : rate_step
if( rate_V[5:2]==4'hf && state_V == ATTACK)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
if( rate_V[5:2]==4'd0 && state_V != ATTACK)
step_idx = 8'b11111110; // limit slowest decay rate_IV
else
step_idx = step_ram;
// a rate_IV of zero keeps the level still
step_V = rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
end
endmodule // eg_step
|
#include <bits/stdc++.h> using namespace std; const bool debug = false; const int inf = 1000 * 1000 * 1000; const int MAKSN = 1000 + 13; const long long MOD = 123456789LL; int n, m, k, l, x, y, a, b, p; string s; vector<int> v; void readIn() { cin >> n >> m >> p; x = 0; for (int i = 0; i < (int)n; i++) { cin >> k; if (k % p != 0 && x == 0) { a = i; x = 1; } } for (int i = 0; i < (int)m; i++) { cin >> k; if (k % p != 0) { cout << a + i << n ; return; } } } void solve() {} int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); readIn(); solve(); return 0; }
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gthe3_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
output reg done_o,
input wire rst_i,
input wire [15:0] test_term_cnt_i,
input wire ref_clk_i,
input wire test_clk_i
);
//****************************************************************************
// Local Parameters
//****************************************************************************
localparam RESET_STATE = 0;
localparam MEASURE_STATE = 1;
localparam HOLD_STATE = 2;
localparam UPDATE_STATE = 3;
localparam DONE_STATE = 4;
//****************************************************************************
// Local Signals
//****************************************************************************
reg [17:0] testclk_cnt = 18'h00000;
reg [15:0] refclk_cnt = 16'h0000;
reg [3:0] testclk_div4 = 4'h1;
wire testclk_rst;
wire testclk_en;
reg [5:0] hold_clk = 6'd0;
reg [4:0] state = 5'd1;
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
//
// need to get testclk_rst into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
tstclk_rst_dly1 <= testclk_rst;
tstclk_rst_dly2 <= tstclk_rst_dly1;
end
//
// need to get testclk_en into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
testclk_en_dly1 <= testclk_en;
testclk_en_dly2 <= testclk_en_dly1;
end
always @(posedge test_clk_i)
begin
if (tstclk_rst_dly2 == 1'b1)
begin
testclk_div4 <= 4'h1;
end
else
begin
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
end
end
wire testclk_rst_sync;
gtwizard_ultrascale_v1_7_1_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
);
always @(posedge test_clk_i or posedge testclk_rst_sync)
begin
if (testclk_rst_sync == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end
/* always @(posedge test_clk_i or posedge testclk_rst)
begin
if (testclk_rst == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end */
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i)
done_o <= 1'b0;
else
done_o <= state[DONE_STATE];
end
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i) begin
state <= 0;
state[RESET_STATE] <= 1'b1;
end
else begin
state <= 0;
case (1'b1) // synthesis parallel_case full_case
state[RESET_STATE]:
begin
if (hold_clk == 6'h3F)
state[MEASURE_STATE] <= 1'b1;
else
state[RESET_STATE] <= 1'b1;
end
state[MEASURE_STATE]:
begin
if (refclk_cnt == test_term_cnt_i)
state[HOLD_STATE] <= 1'b1;
else
state[MEASURE_STATE] <= 1'b1;
end
state[HOLD_STATE]:
begin
if (hold_clk == 6'hF)
state[UPDATE_STATE] <= 1'b1;
else
state[HOLD_STATE] <= 1'b1;
end
state[UPDATE_STATE]:
begin
freq_cnt_o <= testclk_cnt;
state[DONE_STATE] <= 1'b1;
end
state[DONE_STATE]:
begin
state[DONE_STATE] <= 1'b1;
end
endcase
end
end
assign testclk_rst = state[RESET_STATE];
assign testclk_en = state[MEASURE_STATE];
always @(posedge ref_clk_i)
begin
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
hold_clk <= hold_clk + 1;
else
hold_clk <= 0;
end
always @(posedge ref_clk_i)
begin
if (state[MEASURE_STATE] == 1'b1)
refclk_cnt <= refclk_cnt + 1;
else
refclk_cnt <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const int N = 2e5 + 5; vector<pair<long long, long long> > v; long long n, m, k; void solve() { sort(v.rbegin(), v.rend()); long long sum = 0; vector<long long> index; for (long long i = 0; i < m * k; i++) { sum += v[i].first; index.push_back(v[i].second); } sort(index.begin(), index.end()); cout << sum << n ; for (int i = 0; i < k - 1; i++) cout << index[(i + 1) * m - 1] << ; } int main() { fast(); cin >> n >> m >> k; for (int i = 0; i < n; i++) { long long t; cin >> t; v.push_back(make_pair(t, i + 1)); } solve(); }
|
#include <bits/stdc++.h> using namespace std; struct matrix { long long a[100][100]; void init() { memset(a, 0, sizeof(a)); } friend matrix operator*(matrix x, matrix y) { matrix ans; ans.init(); for (int i = 0; i < 100; i++) for (int j = 0; j < 100; j++) { for (int k = 0; k < 100; k++) ans.a[i][j] += (x.a[i][k] * y.a[k][j]) % 1000000007; ans.a[i][j] %= 1000000007; } return ans; } friend matrix operator^(matrix x, long long y) { matrix ans; if (y == 0) { memset(ans.a, 0, sizeof(ans.a)); for (int i = 0; i < 100; i++) ans.a[i][i] = 1; return ans; } else while ((y & 1) == 0) y >>= 1, x = x * x; ans = x; y >>= 1; for (; y != 0; y >>= 1) { x = x * x; if ((y & 1) != 0) ans = ans * x; } return ans; } } x; int n, m, Mod, a[1000010]; int main() { x.init(); matrix h, t; h.init(); t.init(); scanf( %d%d%d , &n, &m, &Mod); for (int i = 1; i <= n; i++) { int v; scanf( %d , &v); h.a[0][v % Mod]++; } for (int i = 1; i <= n; i++) { int v; scanf( %d , &v); a[i] = v; for (int j = 0; j < Mod; j++) x.a[j][(j + v) % Mod]++; } matrix ans = h * (x ^ (m - 2)); for (int i = 1; i <= n; i++) { int v; scanf( %d , &v); int d = (Mod - (v + a[i]) % Mod) % Mod; t.a[d][0]++; } ans = ans * t; printf( %I64d n , ans.a[0][0]); }
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 06:23:47 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_50M_0_stub.v
// Design : design_1_rst_ps7_0_50M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 110; bool ls(string s1, string s2) { for (int i = 0; i < s1.size(); i++) if (s1[i] < s2[i]) return 1; else if (s1[i] > s2[i]) return 0; return 0; } int main() { string s, t, tmp; cin >> s; int pos = s.find( . ); for (int i = pos + 1; i < s.size(); i++) tmp += s[i]; t = 5 ; for (int i = 0; i < tmp.size() - 1; i++) t += 0 ; if (ls(tmp, t) && s[pos - 1] != 9 ) for (int i = 0; i < pos; i++) cout << s[i]; else if (!ls(tmp, t) && s[pos - 1] != 9 ) { for (int i = 0; i < pos - 1; i++) cout << s[i]; cout << char(s[pos - 1] + 1); } else cout << GOTO Vasilisa. ; return 0; }
|
#include <bits/stdc++.h> using namespace std; double p[210]; int a[210]; double dp[210][210][210]; int main(void) { int N, L, K, i, j, k; cin >> N >> L >> K; for ((i) = 0; (i) < (int)(N); (i)++) cin >> p[i]; for ((i) = 0; (i) < (int)(N); (i)++) cin >> a[i]; for ((i) = 0; (i) < (int)(N); (i)++) p[i] /= 100.0; dp[0][0][0] = 1.0; for ((i) = 0; (i) < (int)(N); (i)++) for ((j) = 0; (j) < (int)(i + 1); (j)++) for ((k) = 0; (k) < (int)(N + 1); (k)++) { int c = a[i] + 1; dp[i + 1][j + 1][min(k + c, N)] += dp[i][j][k] * p[i]; dp[i + 1][j][k] += dp[i][j][k] * (1.0 - p[i]); } double ans = 0.0; for ((i) = 0; (i) < (int)(N + 1); (i)++) for ((j) = 0; (j) < (int)(N + 1); (j)++) if (i >= L && K + j - i >= 0) ans += dp[N][i][j]; printf( %.9f n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_4_V
`define SKY130_FD_SC_LS__O31A_4_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_4_V
|
#include <bits/stdc++.h> using namespace std; long long grundy[1234]; int main() { long long idx = 1, i, j; for (i = 1; i <= 15; i++) { for (j = 1; j <= (i + 1); j++) { grundy[idx] = i; idx++; } } long long n; cin >> n; long long ans = 0; while (n--) { long long va; cin >> va; ans = ans ^ grundy[va]; } cout << ((ans == 0) ? YES : NO ); }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_select(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
i_controla, i_controla_valid, o_controla_stall,
i_controlb, i_controlb_valid, o_controlb_stall,
i_datasel, i_datasel_valid, o_datasel_stall,
o_dataout, o_dataout_valid, i_stall,
i_settings);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 64;
parameter CONFIG_WIDTH = 7;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_controla, i_controlb;
input i_datasel;
input i_dataa_valid, i_datab_valid, i_controla_valid, i_controlb_valid, i_datasel_valid;
output o_dataa_stall, o_datab_stall, o_controla_stall, o_controlb_stall, o_datasel_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
input [CONFIG_WIDTH-1:0] i_settings;
//bit 0: if controla is connected (default = 0)
//bit 1: if controla is conditional (default = 0)
//bit 2: the condition of controla (default = 0)
//bit 3: if controlb is connected (default = 0)
//bit 4: if controlb is conditional (default = 0)
//bit 5: the condition of controlb (default = 0)
//bit 6: 1 if this is a phi
wire [DATA_WIDTH-1:0] raw_dataa, dataa;
wire [DATA_WIDTH-1:0] raw_datab, datab;
wire raw_controla, raw_controlb;
wire is_raw_controla_valid, is_raw_controlb_valid;
wire datasel;
wire is_a_phi;
wire is_fifo_a_valid, is_raw_dataa_valid;
wire is_fifo_b_valid, is_raw_datab_valid;
wire is_fifo_sel_valid;
wire is_fifo_a_stalled, is_fifo_b_stalled;
wire is_fifo_sel_stalled;
wire is_raw_porta_stalled, is_raw_portb_stalled;
wire porta_data_valid, portb_data_valid;
wire fifo_a_stall, fifo_b_stall;
wire controla_stall, controlb_stall;
wire is_phi_sel_stalled;
wire is_phi_a_stalled, is_phi_b_stalled;
wire is_select_stalled;
wire is_phi_output_valid;
wire is_select_output_valid;
assign is_a_phi = i_settings[6];
// 3 FIFOs per input of the PHI: Port A
generate
if (DATA_WIDTH == 1)
begin
vfabric_buffered_fifo fifo_raw_dataa ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(raw_dataa), .valid_in(i_dataa_valid),
.valid_out( is_raw_dataa_valid ), .stall_in(is_raw_porta_stalled), .stall_out(o_dataa_stall) );
defparam fifo_raw_dataa.DATA_WIDTH = DATA_WIDTH;
defparam fifo_raw_dataa.DEPTH = 512; //FIFO_DEPTH;
defparam fifo_raw_dataa.IMPLEMENTATION_MODE = "MLAB";
end
else
begin
vfabric_buffered_fifo fifo_raw_dataa ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(raw_dataa), .valid_in(i_dataa_valid),
.valid_out( is_raw_dataa_valid ), .stall_in(is_raw_porta_stalled), .stall_out(o_dataa_stall) );
defparam fifo_raw_dataa.DATA_WIDTH = DATA_WIDTH;
defparam fifo_raw_dataa.DEPTH = 512; //FIFO_DEPTH;
defparam fifo_raw_dataa.IMPLEMENTATION_MODE = "RAM";
end
endgenerate
vfabric_buffered_fifo fifo_controla ( .clock(clock), .resetn(resetn),
.data_in( (is_a_phi) ? i_controla : 1'b1 ), .data_out(raw_controla),
.valid_in( (is_a_phi) ? i_controla_valid : i_dataa_valid ),
.valid_out( is_raw_controla_valid ),
.stall_in(is_raw_porta_stalled), .stall_out(controla_stall ) );
defparam fifo_controla.DATA_WIDTH = 1;
defparam fifo_controla.DEPTH = 512;//FIFO_DEPTH;
assign is_raw_porta_stalled = ~(is_raw_dataa_valid & is_raw_controla_valid & ~fifo_a_stall);
assign porta_data_valid = is_raw_dataa_valid & is_raw_controla_valid &
i_settings[0] & (~i_settings[1] | (raw_controla == i_settings[2]));
acl_mlab_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(raw_dataa), .data_out(dataa), .valid_in(porta_data_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_a_stalled), .stall_out(fifo_a_stall));
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
// 3 FIFOs per input of the PHI: Port B
generate
if (DATA_WIDTH == 1)
begin
vfabric_buffered_fifo fifo_raw_datab ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(raw_datab), .valid_in(i_datab_valid),
.valid_out( is_raw_datab_valid ), .stall_in(is_raw_portb_stalled), .stall_out(o_datab_stall) );
defparam fifo_raw_datab.DATA_WIDTH = DATA_WIDTH;
defparam fifo_raw_datab.DEPTH = 512; //FIFO_DEPTH;
defparam fifo_raw_datab.IMPLEMENTATION_MODE = "MLAB";
end
else
begin
vfabric_buffered_fifo fifo_raw_datab ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(raw_datab), .valid_in(i_datab_valid),
.valid_out( is_raw_datab_valid ), .stall_in(is_raw_portb_stalled), .stall_out(o_datab_stall) );
defparam fifo_raw_datab.DATA_WIDTH = DATA_WIDTH;
defparam fifo_raw_datab.DEPTH = 512; //FIFO_DEPTH;
defparam fifo_raw_datab.IMPLEMENTATION_MODE = "RAM";
end
endgenerate
vfabric_buffered_fifo fifo_controlb ( .clock(clock), .resetn(resetn),
.data_in( (is_a_phi) ? i_controlb : 1'b1 ), .data_out(raw_controlb),
.valid_in( (is_a_phi) ? i_controlb_valid : i_datab_valid ),
.valid_out( is_raw_controlb_valid ),
.stall_in(is_raw_portb_stalled), .stall_out(controlb_stall) );
defparam fifo_controlb.DATA_WIDTH = 1;
defparam fifo_controlb.DEPTH = 512; //FIFO_DEPTH;
assign is_raw_portb_stalled = ~(is_raw_datab_valid & is_raw_controlb_valid & ~fifo_b_stall);
assign portb_data_valid = is_raw_datab_valid & is_raw_controlb_valid &
i_settings[3] & (~i_settings[4] | (raw_controlb == i_settings[5]));
acl_mlab_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(raw_datab), .data_out(datab), .valid_in(portb_data_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_b_stalled), .stall_out(fifo_b_stall));
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign o_controla_stall = (is_a_phi) ? controla_stall : 1'b0;
assign o_controlb_stall = (is_a_phi) ? controlb_stall : 1'b0;
vfabric_buffered_fifo fifo_sel ( .clock(clock), .resetn(resetn),
.data_in(i_datasel), .data_out(datasel), .valid_in(i_datasel_valid),
.valid_out( is_fifo_sel_valid ), .stall_in(is_fifo_sel_stalled), .stall_out(o_datasel_stall) );
defparam fifo_sel.DATA_WIDTH = 1;
defparam fifo_sel.DEPTH = 512; //FIFO_DEPTH;
// this is the signal where they all drain at the same rate
assign is_select_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & is_fifo_sel_valid & ~i_stall);
assign is_phi_a_stalled = ~(is_fifo_a_valid & ~datasel & is_fifo_sel_valid & ~i_stall);
assign is_phi_b_stalled = ~(is_fifo_b_valid & datasel & is_fifo_sel_valid & ~i_stall);
assign is_phi_sel_stalled = is_fifo_sel_valid &
(( ~datasel & is_phi_a_stalled) | (datasel & is_phi_b_stalled));
assign is_fifo_a_stalled = is_a_phi ? is_phi_a_stalled : is_select_stalled;
assign is_fifo_b_stalled = is_a_phi ? is_phi_b_stalled : is_select_stalled;
assign is_fifo_sel_stalled = is_a_phi ? is_phi_sel_stalled : is_select_stalled;
wire [DATA_WIDTH-1:0] select_dataout, phi_dataout;
assign select_dataout = datasel ? dataa : datab;
assign phi_dataout = datasel ? datab : dataa;
assign o_dataout = is_a_phi ? phi_dataout : select_dataout;
assign is_select_output_valid = is_fifo_a_valid & is_fifo_b_valid & is_fifo_sel_valid;
assign is_phi_output_valid = is_fifo_sel_valid & ((is_fifo_a_valid & ~datasel) | (is_fifo_b_valid & datasel));
assign o_dataout_valid = is_a_phi ? is_phi_output_valid : is_select_output_valid;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_sincos(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataouta, o_dataouta_valid, i_dataouta_stall,
o_dataoutb, o_dataoutb_valid, i_dataoutb_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 37;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataouta, o_dataoutb;
output o_dataouta_valid, o_dataoutb_valid;
input i_dataouta_stall, i_dataoutb_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] datain;
wire is_fifo_in_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_in ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(datain), .valid_in(i_datain_valid),
.valid_out( is_fifo_in_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_in.DATA_WIDTH = DATA_WIDTH;
defparam fifo_in.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_in_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & (i_dataouta_stall | i_dataoutb_stall));
assign is_fifo_stalled = (shift_reg_valid[0] & (i_dataouta_stall | i_dataoutb_stall) ) | !(is_fifo_in_valid);
acl_fp_sincos_s5 sincos_unit(
.clock(clock), .resetn(resetn), .dataa(datain),
.result_a(o_dataouta), .result_b(o_dataoutb), .enable(~is_stalled));
assign o_dataouta_valid = shift_reg_valid[0];
assign o_dataoutb_valid = shift_reg_valid[0];
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 200010, LOG = 20; int n, m, k, u, v, x, y, t, a, b; long long A[MAXN]; int par[MAXN][LOG]; long long dist[MAXN][LOG]; int ans[MAXN]; vector<int> G[MAXN]; void dfs(int node) { for (int i = 1; i < LOG; i++) par[node][i] = par[par[node][i - 1]][i - 1]; for (int i = 1; i < LOG; i++) dist[node][i] = min(1ll * inf, dist[par[node][i - 1]][i - 1] + dist[node][i - 1]); for (int v : G[node]) { dfs(v); ans[node] += ans[v]; } ans[par[node][0]]++; long long v = node, tmp = A[node]; for (int i = LOG - 1; i >= 0; i--) if (dist[v][i] <= tmp) { tmp -= dist[v][i]; v = par[v][i]; } v = par[v][0]; ans[v]--; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> A[i]; for (int i = 2; i <= n; i++) { cin >> par[i][0] >> dist[i][0]; G[par[i][0]].push_back(i); } par[1][0] = 0; dfs(1); for (int i = 1; i <= n; i++) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[10], b[10]; vector<int> p; bool square(int i, int j) { double len = sqrt((a[j].first - a[i].first) * (a[j].first - a[i].first) + (a[j].second - a[i].second) * (a[j].second - a[i].second)); for (int t = i + 1; t <= j; t++) { double tmp = sqrt((a[t].first - a[t - 1].first) * (a[t].first - a[t - 1].first) + (a[t].second - a[t - 1].second) * (a[t].second - a[t - 1].second)); if (abs(len - tmp) > 0.000000001) return 0; } if (len * len > 0.000000001) { int x1 = a[i + 3].first - a[i].first, x2 = a[i + 1].first - a[i].first; int y1 = a[i + 3].second - a[i].second, y2 = a[i + 1].second - a[i].second; if (x1 * x2 + y1 * y2 == 0) return 1; else return 0; } } bool rect(int i, int j) { double len1 = sqrt((a[i].first - a[i + 1].first) * (a[i].first - a[i + 1].first) + (a[i].second - a[i + 1].second) * (a[i].second - a[i + 1].second)); double len2 = sqrt((a[i + 2].first - a[i + 1].first) * (a[i + 2].first - a[i + 1].first) + (a[i + 2].second - a[i + 1].second) * (a[i + 2].second - a[i + 1].second)); double len3 = sqrt((a[i + 2].first - a[i + 3].first) * (a[i + 2].first - a[i + 3].first) + (a[i + 2].second - a[i + 3].second) * (a[i + 2].second - a[i + 3].second)); double len4 = sqrt((a[i + 3].first - a[i].first) * (a[i + 3].first - a[i].first) + (a[i + 3].second - a[i].second) * (a[i + 3].second - a[i].second)); if (abs(len1 - len3) > 0.000000001 || abs(len2 - len4) > 0.000000001) return 0; else { int x1 = a[i + 3].first - a[i].first, x2 = a[i + 1].first - a[i].first; int y1 = a[i + 3].second - a[i].second, y2 = a[i + 1].second - a[i].second; if (x1 * x2 + y1 * y2 == 0) return 1; else return 0; } } bool check() { if (!square(0, 3)) return 0; if (!rect(4, 7)) return 0; return 1; } int main() { for (int i = 0; i < 8; i++) { cin >> a[i].first >> a[i].second; b[i] = a[i]; p.push_back(i); } while (true) { if (check()) { cout << YES n ; for (int i = 0; i <= 3; i++) cout << p[i] + 1 << ; cout << endl; for (int i = 4; i <= 7; i++) cout << p[i] + 1 << ; return 0; } if (!next_permutation(p.begin(), p.end())) break; for (int i = 0; i <= 7; i++) a[i] = b[p[i]]; } cout << NO ; return 0; }
|
#include <bits/stdc++.h> int d, n, m; int deq[200100]; int qs, qe; struct stt { int x, p; bool operator<(const stt& r) const { return x < r.x; } }; stt a[200100]; int main() { int i, j; long long int ans; scanf( %d%d%d , &d, &n, &m); for (i = 0; i < m; i++) { scanf( %d%d , &a[i].x, &a[i].p); } a[m].x = 0; a[m].p = 0; m++; a[m].x = d; a[m].p = 0; m++; std::sort(a, a + m); for (i = 1; i < m; i++) { if (a[i].x > a[i - 1].x + n) { printf( -1 ); return 0; } } qs = 0; qe = 0; j = 0; ans = 0; for (i = 0; i < m; i++) { while (qs < qe && a[deq[qs]].x + n < a[i].x) { ans += ((long long int)a[deq[qs]].x + n - j) * a[deq[qs]].p; j = a[deq[qs]].x + n; qs++; } ans += ((long long int)a[i].x - j) * a[deq[qs]].p; j = a[i].x; while (qs < qe && a[deq[qe - 1]].p > a[i].p) { qe--; } deq[qe] = i; qe++; } printf( %I64d , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR3_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool check(int x, int n, vector<int>& a) { vector<int> temp; int i = 0, j = x; int cnt = 0; bool ok = false; while (cnt < n) { if (ok) temp.push_back(a[i]), i++, ok = false; else temp.push_back(a[j]), j++, ok = true; cnt++; } cnt = 0; return cnt == x; } void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); int cnt = 0; vector<int> ans(n); for (int i = 1; i < n; i += 2) { ans[i] = a[cnt++]; } for (int i = 0; i < n; i += 2) ans[i] = a[cnt++]; cnt = 0; for (int i = 1; i < n - 1; i++) { if (ans[i] < ans[i - 1] && ans[i] < ans[i + 1]) cnt++; } cout << cnt << n ; for (int i = 0; i < n; i++) cout << ans[i] << ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int t = 1; while (t--) { solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> int allocator_pos = 0; char allocator_memory[(int)1e5]; inline void *operator new(size_t n) { char *res = allocator_memory + allocator_pos; allocator_pos += n; assert(allocator_pos <= (int)1e5); return (void *)res; } inline void operator delete(void *) noexcept {} template <class T = int> inline T readInt(); inline double readDouble(); inline int readUInt(); inline int readChar(); inline void readWord(char *s); inline bool readLine(char *s); inline bool isEof(); inline int getChar(); inline int peekChar(); inline bool seekEof(); inline void skipBlanks(); template <class T> inline void writeInt(T x, char end = 0, int len = -1); inline void writeChar(int x); inline void writeWord(const char *s); inline void writeDouble(double x, int len = 0); inline void flush(); static struct buffer_flusher_t { ~buffer_flusher_t() { flush(); } } buffer_flusher; static const int buf_size = 4096; static unsigned char buf[buf_size]; static int buf_len = 0, buf_pos = 0; inline bool isEof() { if (buf_pos == buf_len) { buf_pos = 0, buf_len = fread(buf, 1, buf_size, stdin); if (buf_pos == buf_len) return 1; } return 0; } inline int getChar() { return isEof() ? -1 : buf[buf_pos++]; } inline int peekChar() { return isEof() ? -1 : buf[buf_pos]; } inline bool seekEof() { int c; while ((c = peekChar()) != -1 && c <= 32) buf_pos++; return c == -1; } inline void skipBlanks() { while (!isEof() && buf[buf_pos] <= 32U) buf_pos++; } inline int readChar() { int c = getChar(); while (c != -1 && c <= 32) c = getChar(); return c; } inline int readUInt() { int c = readChar(), x = 0; while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getChar(); return x; } template <class T> inline T readInt() { int s = 1, c = readChar(); T x = 0; if (c == - ) s = -1, c = getChar(); else if (c == + ) c = getChar(); while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getChar(); return s == 1 ? x : -x; } inline double readDouble() { int s = 1, c = readChar(); double x = 0; if (c == - ) s = -1, c = getChar(); while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getChar(); if (c == . ) { c = getChar(); double coef = 1; while ( 0 <= c && c <= 9 ) x += (c - 0 ) * (coef *= 1e-1), c = getChar(); } return s == 1 ? x : -x; } inline void readWord(char *s) { int c = readChar(); while (c > 32) *s++ = c, c = getChar(); *s = 0; } inline bool readLine(char *s) { int c = getChar(); while (c != n && c != -1) *s++ = c, c = getChar(); *s = 0; return c != -1; } static int write_buf_pos = 0; static char write_buf[buf_size]; inline void writeChar(int x) { if (write_buf_pos == buf_size) fwrite(write_buf, 1, buf_size, stdout), write_buf_pos = 0; write_buf[write_buf_pos++] = x; } inline void flush() { if (write_buf_pos) { fwrite(write_buf, 1, write_buf_pos, stdout), write_buf_pos = 0; fflush(stdout); } } template <class T> inline void writeInt(T x, char end, int output_len) { if (x < 0) writeChar( - ), x = -x; char s[24]; int n = 0; while (x || !n) s[n++] = 0 + x % 10, x /= 10; while (n < output_len) s[n++] = 0 ; while (n--) writeChar(s[n]); if (end) writeChar(end); } inline void writeWord(const char *s) { while (*s) writeChar(*s++); } inline void writeDouble(double x, int output_len) { if (x < 0) writeChar( - ), x = -x; int t = (int)x; writeInt(t), x -= t; writeChar( . ); for (int i = output_len - 1; i > 0; i--) { x *= 10; t = std::min(9, (int)x); writeChar( 0 + t), x -= t; } x *= 10; t = std::min(9, (int)(x + 0.5)); writeChar( 0 + t); } #pragma GCC optimaze( O3,unroll-loops ) #pragma GCC target( sse4,sse3,sse2,sse ) using namespace std; int a[20005], b[20005], n, m, p; int dp1[3][20005], dp2[3][20005]; int f(int x, int y) { int r = a[x] + b[y]; if (r < p) return r; else return r - p; } void get_ans(int x1, int y1, int x2, int y2) { if (x1 == x2) { for (int i = y1; i < y2; i++) writeChar( S ); return; } if (y1 == y2) { for (int i = x1; i < x2; i++) writeChar( C ); return; } int mid = (x1 + y1 + x2 + y2) / 2; dp1[0][x2] = f(n - x2, m - y2); int x = 0, y = 0, i1, i2; for (i1 = x2 + y2, i2 = x1 + y1; i1 > mid && i2 < mid; i1--, i2++) { for (int j = max(x1, i1 - y2); j <= min(x2, i1 - y1); j++) { int z = i1 - j; if (j != x1) dp1[x ^ 1][j - 1] = max(dp1[x ^ 1][j - 1], dp1[x][j] + f(n - j + 1, m - z)); if (z != y1) dp1[x ^ 1][j] = max(dp1[x ^ 1][j], dp1[x][j] + f(n - j, m - z + 1)); dp1[x][j] = 0; } x ^= 1; for (int j = max(x1, i2 - y2); j <= min(x2, i2 - y1); j++) { int z = i2 - j; if (j != x2) dp2[y ^ 1][j + 1] = max(dp2[y ^ 1][j + 1], dp2[y][j] + f(n - j, m - z)); if (z != y2) dp2[y ^ 1][j] = max(dp2[y ^ 1][j], dp2[y][j] + f(n - j, m - z)); dp2[y][j] = 0; } y ^= 1; } if (i1 > mid) { for (int j = max(x1, i1 - y2); j <= min(x2, i1 - y1); j++) { int z = i1 - j; if (j != x1) dp1[x ^ 1][j - 1] = max(dp1[x ^ 1][j - 1], dp1[x][j] + f(n - j + 1, m - z)); if (z != y1) dp1[x ^ 1][j] = max(dp1[x ^ 1][j], dp1[x][j] + f(n - j, m - z + 1)); dp1[x][j] = 0; } x ^= 1; } if (i2 < mid) { for (int j = max(x1, i2 - y2); j <= min(x2, i2 - y1); j++) { int z = i2 - j; if (j != x2) dp2[y ^ 1][j + 1] = max(dp2[y ^ 1][j + 1], dp2[y][j] + f(n - j, m - z)); if (z != y2) dp2[y ^ 1][j] = max(dp2[y ^ 1][j], dp2[y][j] + f(n - j, m - z)); dp2[y][j] = 0; } y ^= 1; } int posx = -1, tek = -1; for (int i = max(x1, mid - y2); i <= min(x2, mid - y1); i++) { if (tek < dp1[x][i] + dp2[y][i]) posx = i, tek = dp1[x][i] + dp2[y][i]; dp1[x][i] = 0, dp2[y][i] = 0; } if (x1 == 1 && y1 == 1 && x2 == n && y2 == m) { writeInt(tek); writeChar( n ); } get_ans(posx, mid - posx, x2, y2); get_ans(x1, y1, posx, mid - posx); return; } int main() { n = readInt(); m = readInt(); p = readInt(); for (int i = 0; i < n; i++) { a[i] = readInt(); a[i] %= p; } for (int i = 0; i < m; i++) { b[i] = readInt(); b[i] %= p; } if (n == 1) { int ans = 0; for (int i = 0; i < m; i++) ans += f(0, i); writeInt(ans); writeChar( n ); for (int i = 1; i < m; i++) writeChar( S ); exit(0); } if (m == 1) { int ans = 0; for (int i = 0; i < n; i++) ans += f(i, 0); writeInt(ans); writeChar( n ); for (int i = 1; i < n; i++) writeChar( C ); exit(0); } get_ans(1, 1, n, m); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int maxn = 1e5 + 10, lg = 18; int n, m, q, cid[maxn], csize = 0, H[maxn], low[maxn], ok[maxn], par[maxn][lg], comp[maxn], c1; bool dp[maxn][lg]; vector<int> G[maxn]; bool mark[maxn]; void dfs1(int a, int p) { par[a][0] = p; for (int i = 1; i < lg; i++) { par[a][i] = par[par[a][i - 1]][i - 1]; } low[a] = H[a]; mark[a] = 1; for (int b : G[a]) { if (!mark[b]) { H[b] = H[a] + 1; comp[b] = comp[a]; dfs1(b, a); low[a] = min(low[a], low[b]); } else if (b != p) { low[a] = min(low[a], H[b]); } } } void dfs2(int a) { mark[a] = 1; for (int b : G[a]) { if (!mark[b]) { if (low[b] >= H[a]) { cid[b] = csize++; } else { cid[b] = cid[a]; } dfs2(b); } else if (H[a] > H[b]) { int dis = H[a] - H[b]; if ((dis & 1) == 0) { ok[cid[a]] = 1; } } } } void dfs3(int a) { mark[a] = 1; dp[a][0] = (ok[cid[a]]); for (int b : G[a]) { if (!mark[b]) { dfs3(b); } } } bool lca(int a, int b) { bool ans = 0; if (H[a] > H[b]) swap(a, b); for (int i = lg - 1; i >= 0; i--) { if (H[par[b][i]] >= H[a]) { ans |= dp[b][i]; b = par[b][i]; } } if (a == b) { return ans; } for (int i = lg - 1; i >= 0; i--) { if (par[b][i] != par[a][i]) { ans |= dp[a][i]; ans |= dp[b][i]; a = par[a][i]; b = par[b][i]; } } ans |= dp[a][0]; ans |= dp[b][0]; return ans; } int32_t main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int a, b; scanf( %d%d , &a, &b); a--, b--; G[a].push_back(b); G[b].push_back(a); } for (int i = 0; i < n; i++) { if (!mark[i]) { comp[i] = c1++; dfs1(i, i); } } fill(mark, mark + n, 0); for (int i = 0; i < n; i++) { if (!mark[i]) { cid[i] = csize++; dfs2(i); } } fill(mark, mark + n, 0); for (int i = 0; i < n; i++) { if (!mark[i]) { dfs3(i); } } for (int j = 0; j < lg - 1; j++) { for (int i = 0; i < n; i++) { dp[i][j + 1] = dp[i][j] | dp[par[i][j]][j]; } } scanf( %d , &q); while (q--) { int a, b; scanf( %d%d , &a, &b); a--, b--; if (H[a] > H[b]) swap(a, b); if (a == b || comp[a] != comp[b]) { printf( No n ); continue; } if ((H[b] - H[a]) & 1) { printf( Yes n ); continue; } bool ans = lca(a, b); printf(ans ? Yes n : No n ); } }
|
module heap_simulation;
// Inputs
reg mclk = 0;
reg core_stall = 0;
reg [31:0] memory_dout = 31'b0;
reg [7:0] switch = 7'b0;
reg [3:0] button = 4'b0;
// Outputs
wire memory_read;
wire memory_write;
wire [31:0] memory_address;
wire [31:0] memory_din;
wire [7:0] seg;
wire [3:0] digit;
wire hsync;
wire vsync;
wire [7:0] color;
reg[31:0] heap[0:16777216];
// Instantiate the Unit Under Test (UUT)
processor uut (
.mclk(mclk),
.core_stall(core_stall),
.memory_read(memory_read),
.memory_write(memory_write),
.memory_address(memory_address),
.memory_din(memory_din),
.memory_dout(memory_dout),
.switch(switch),
.button(button),
.seg(seg),
.digit(digit),
.hsync(hsync),
.vsync(vsync),
.color(color)
);
parameter state_idle = 2'b00;
parameter state_read = 2'b01;
parameter state_write = 2'b10;
reg[1:0] state = state_idle;
reg[31:0] address;
initial begin
// Initialize Inputs
mclk = 0;
core_stall = 0;
memory_dout = 0;
switch = 0;
button = 0;
address = 0;
$readmemh("HelloApp_heap.txt", heap);
#100;
end
always begin
#10 mclk = !mclk;
end
always @ (posedge mclk) begin
case(state)
/*state_read: begin
core_stall <= 0;
memory_dout <= heap[address];
state <= state_idle;
end
state_write: begin
core_stall <= 0;
heap[address] <= memory_din;
state <= state_idle;
end*/
default: begin
if(memory_read) begin
//core_stall <= 1;
//address <= memory_address;
//state <= state_read;
core_stall <= 0;
memory_dout <= heap[memory_address];
state <= state_idle;
end else if(memory_write) begin
//core_stall <= 1;
//address <= memory_address;
//state <= state_write;
core_stall <= 0;
heap[memory_address] <= memory_din;
state <= state_idle;
end
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int cnt[100005]; int cmax[10]; memset(cnt, 0, sizeof(cnt)); memset(cmax, 0, sizeof(cmax)); for (int i = 1; i <= n; i++) { int a; cin >> a; cnt[a]++; if (cnt[a] < 10) cmax[cnt[a]]++; } int t; cin >> t; while (t--) { char ch; int x; cin >> ch >> x; if (ch == + ) { cnt[x]++; if (cnt[x] < 10) cmax[cnt[x]]++; } else { if (cnt[x] < 10) cmax[cnt[x]]--; cnt[x]--; } if (cmax[8]) cout << YES << endl; else if (cmax[4] >= 2) cout << YES << endl; else if (cmax[4]) { if (cmax[2] >= 3) cout << YES << endl; else if (cmax[2] >= 2 && cmax[6]) cout << YES << endl; else cout << NO << endl; } else cout << NO << endl; } }
|
`timescale 1 ps / 1 ps
module myproj_top(
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output testled
);
myproj_bd_wrapper i_myproj_bd_wrapper(
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.clk_alive (testled)
);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_clamp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [10:0] tex_hres,
input [10:0] tex_vres,
input [10:0] dst_hres,
input [10:0] dst_vres,
output reg pipe_stb_o,
input pipe_ack_i,
output reg [10:0] dx_c,
output reg [10:0] dy_c,
output reg [16:0] tx_c,
output reg [16:0] ty_c
);
always @(posedge sys_clk) begin
if(sys_rst)
pipe_stb_o <= 1'b0;
else begin
if(pipe_ack_i)
pipe_stb_o <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= (~dx[11]) && (dx[10:0] < dst_hres)
&& (~dy[11]) && (dy[10:0] < dst_vres);
dx_c <= dx[10:0];
dy_c <= dy[10:0];
if(tx[17])
tx_c <= 17'd0;
else if(tx[16:0] > {tex_hres - 11'd1, 6'd0})
tx_c <= {tex_hres - 11'd1, 6'd0};
else
tx_c <= tx[16:0];
if(ty[17])
ty_c <= 17'd0;
else if(ty[16:0] > {tex_vres - 11'd1, 6'd0})
ty_c <= {tex_vres - 11'd1, 6'd0};
else
ty_c <= ty[16:0];
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool query = 0; struct line { long long m, b; mutable function<const line*()> succ; bool operator<(const line rhs) const { if (!query) return (m < rhs.m); const line* s = succ(); return s ? (b - s->b) < (rhs.m * (s->m - m)) : 0; } }; struct hull : multiset<line> { bool bad(iterator y) { auto z = next(y); if (y == begin()) { if (z == end()) return 0; return (y->m == z->m) && (y->b <= z->b); } auto x = prev(y); if (z == end()) return (y->m == x->m) && (y->b <= x->b); return (1.0) * (x->b - y->b) * (z->m - y->m) >= (1.0) * (y->b - z->b) * (y->m - x->m); } void add(long long m, long long b) { auto it = insert({m, b}); it->succ = [=] { return (next(it) == end()) ? 0 : &*next(it); }; if (bad(it)) { erase(it); return; } while (next(it) != end() && bad(next(it))) erase(next(it)); while (it != begin() && bad(prev(it))) erase(prev(it)); } long long eval(long long x) { query = 1; line l = *lower_bound({x, 0}); query = 0; return (l.m * x + l.b); } }; hull h; int N; int A[200005]; long long SumA[200005]; long long SumAi[200005]; long long Solve() { for (int i = 1; i <= N; i++) { SumA[i] = SumA[i - 1] + A[i]; SumAi[i] = SumAi[i - 1] + (1LL * A[i] * i); } long long Ans = -9e18; for (int i = 1; i <= N; i++) { h.add(-i, -SumA[i - 1]); Ans = max(Ans, h.eval(-A[i]) - 1LL * A[i] * i + SumA[i - 1] + SumAi[N]); } h.clear(); for (int i = N; i; i--) { h.add(i, -SumA[i]); Ans = max(Ans, h.eval(A[i]) - 1LL * A[i] * i + SumA[i] + SumAi[N]); } return Ans; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &A[i]); printf( %I64d n , Solve()); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 3; int n; int main() { cin >> n; cout << (int)log2(n) + 1; }
|
#include <bits/stdc++.h> using namespace std; int n, m; char name[2000], part[2000000]; int work() { int p = 0; for (int i = 0; i < m; i++) { if (part[i] == name[p]) p++; if (p == n) return i; } return m; } int main() { scanf( %s , name); scanf( %s , part); n = strlen(name), m = strlen(part); int x = work(); reverse(name, name + n); reverse(part, part + m); int y = work(); printf( %d n , max(0, m - y - x - 1)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 10; char scn[N][2]; int l, x, mem; string s; int main() { l = 1; x = 25; cin >> s; for (int i = 1; i <= 10000; i++) { scn[i][1] = . ; } mem = 0; l = 1; for (int i = 0; i < s.size(); i++) { while (mem != s[i]) { l++; scn[l][1] = X ; l++; mem--; if (mem < 0) { mem = 256 + mem; } } scn[l][1] = X ; l++; } for (int i = 1; i <= l; i++) { cout << scn[i][1] << . << n ; } return 0; }
|
module x;
always @(posedge piclk) begin
if (k_i_reset) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
idat_ICErrData_i3 <= 1'h0;
// End of automatics
end
else begin
idat_ICErrData_i3 <= idat_way0_i2[1*OPCWID-1:0*OPCWID];
end
end
// 2010-04-08
localparam MPND = 5;
always @(posedge usclk)
if (~sso_srst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rd_dat_s4 <= 1'h0;
sel_s3 <= 1'h0;
// End of automatics
end
else begin
sel_s3 <= adr_s2[MIDX];
rd_dat_s4 <= (sel_s3 == 1'h0 ? rd_dat0_s3[MPND:0]
: rd_dat1_s3[MPND:0]);
end
// 2010-04-15
integer i;
always @(posedge usclk)
if (~sso_srst_n) begin
for (int j=0; j<10; j++) blob[j] <= 0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
zsv <= 1'h0;
zz <= 1'h0;
// End of automatics
end
else begin
for (i=0; i<10; i++) blob[i] <= blob[i+1];
for (i=0; i<10; i++) zz <= 1;
for (int isv=0; isv<10; isv++) zsv <= 1;
end
always @(/*AS*/in) begin
for (i=0; i<10; i++) zz <= in;
for (int isv=0; isv<10; isv++) zsv <= in;
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.