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#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; long double EPS = 1e-9; long long binpow(long long b, long long p, long long mod) { long long ans = 1; b %= mod; for (; p; p >>= 1) { if (p & 1) ans = ans * b % mod; b = b * b % mod; } return ans; } void pre() {} long long arr[1010][1010]; int row[1010][1010][2]; int col[1010][1010][2]; void solve() { long long n, m; cin >> n >> m; for (long long i = 0; i < (n); ++i) { for (long long j = 0; j < (m); ++j) { cin >> arr[i][j]; } } for (long long i = 0; i < (n); ++i) { set<long long> st; vector<long long> temp; for (long long j = 0; j < (m); ++j) { st.insert(arr[i][j]); } temp = vector<long long>((st).begin(), (st).end()); for (long long j = 0; j < (m); ++j) { row[i][j][0] = lower_bound((temp).begin(), (temp).end(), arr[i][j]) - temp.begin(); row[i][j][1] = upper_bound((temp).begin(), (temp).end(), arr[i][j]) - temp.begin(); row[i][j][1] = (long long)(temp).size() - row[i][j][1]; } } for (long long j = 0; j < (m); ++j) { set<long long> st; vector<long long> temp; for (long long i = 0; i < (n); ++i) { st.insert(arr[i][j]); } temp = vector<long long>((st).begin(), (st).end()); for (long long i = 0; i < (n); ++i) { col[i][j][0] = lower_bound((temp).begin(), (temp).end(), arr[i][j]) - temp.begin(); col[i][j][1] = upper_bound((temp).begin(), (temp).end(), arr[i][j]) - temp.begin(); col[i][j][1] = (long long)(temp).size() - col[i][j][1]; } } for (long long i = 0; i < (n); ++i) { for (long long j = 0; j < (m); ++j) { cout << max(row[i][j][0], col[i][j][0]) + 1 + max(row[i][j][1], col[i][j][1]) << ; } cout << n ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); pre(); long long t = 1; for (long long i = 1; i <= t; i++) { solve(); } }
|
`ifndef _B_PREDICTOR_
`define _B_PREDICTOR_
module b_predictor (
input clk,
input rst,
input direct_mispredict,
input direct_resolved,
input branch_commit,
input [31:0] pc_head, // the pc of commit branch
input [31:0] pc_branch, // the pc of branch making predict
input [31:0] pc_resolved,
output logic branch_valid,
output logic [31:0] btb_pc_predict,
output logic direct_predict
);
logic [3:0] local_b [63:0];
logic [3:0] local_b_checkpoint [63:0];
logic [1:0] counters [15:0];
integer i;
logic [5:0] pc_head_index, pc_branch_index;
assign pc_head_index = pc_head[7:2];
assign pc_branch_index = pc_branch[7:2];
assign direct_predict = counters[local_b[pc_branch_index]] > 1;
//speculative local history, used for index counter
always @(posedge clk, negedge rst) begin
if (!rst) begin
for(i = 0; i < 64; i = i + 1) begin
local_b[i] <= 4'h0;
end
end
else begin
if (direct_mispredict) begin
//update history if mispredict
local_b[pc_head_index] <= (local_b_checkpoint[pc_head_index] << 1) | direct_resolved;
end
if (branch_valid) begin
//insert predicted direction to local branch history
local_b[pc_branch_index] <= (local_b[pc_branch_index] << 1) | (counters[local_b[pc_branch_index]] > 1 ? 4'h1 : 4'h0);
end
end
end // always @ (posedge clk, negedge rst)
// commited local history, used for counter update
always @(posedge clk, negedge rst) begin
if (!rst) begin
for(i = 0; i < 64; i = i + 1) begin
local_b_checkpoint[i] <= 4'h0;
end
end
else begin
if (branch_commit) begin
local_b_checkpoint[pc_head_index] <= (local_b_checkpoint[pc_head_index] << 1) | direct_resolved;
end
end
end // always @ (posedge clk, negedge rst)
//saturated counter 0:deep untaken, 1:untaken, 2:taken, 3:deep taken
always @(posedge clk, negedge rst) begin
if (!rst) begin
for(i = 0; i < 16; i = i + 1) begin
counters[i] <= 2'h1;
end
end
else begin
if (branch_commit) begin
if (direct_resolved) begin
if (counters[local_b_checkpoint[pc_head_index]] < 4'h3) begin
counters[local_b_checkpoint[pc_head_index]] <= counters[local_b_checkpoint[pc_head_index]] + 1;
end
end
else begin
if (counters[local_b_checkpoint[pc_head_index]] > 4'h0) begin
counters[local_b_checkpoint[pc_head_index]] <= counters[local_b_checkpoint[pc_head_index]] - 1;
end
end
end // if (branch_commit)
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
typedef struct packed{
bit [23:0] pc_branch_tag;
bit [31:0] btb_pc_predict;
bit bsy;
} btbStruct;
btbStruct btb_array[63:0];
//for simplicity, use pc indexed btb; should use associative one
//fixme: to implement replace policy
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < $size(btb_array); i = i + 1) begin
btb_array[i] <= {$size(btbStruct){1'b0}};
end
end
else begin
if (branch_commit) begin
btb_array[pc_head_index].bsy <= 1'b1;
btb_array[pc_head_index].pc_branch_tag <= pc_head[31:8];
//only updated target pc when it is actually taken
if (direct_resolved) begin
btb_array[pc_head_index].btb_pc_predict <= pc_resolved;
end
end
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
assign branch_valid = btb_array[pc_branch_index].bsy;
assign btb_pc_predict = (btb_array[pc_branch_index].bsy && btb_array[pc_branch_index].pc_branch_tag == pc_branch[31:8]) ? btb_array[pc_branch_index].btb_pc_predict : 32'h0;
endmodule // b_predictor
`endif // `ifndef _B_PREDICTOR_
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#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<long long, int> > vertices; bool cmp(pair<long long, int> x, pair<long long, int> y) { return x.first < y.first; } bool cmp2(pair<long long, pair<int, int> > x, pair<long long, pair<int, int> > y) { return x.first < y.first; } int lab[200010]; vector<pair<long long, pair<int, int> > > ed; void uni(int r1, int r2) { int x = lab[r1] + lab[r2]; if (lab[r1] < lab[r2]) { lab[r1] = x; lab[r2] = r1; } else { lab[r2] = x; lab[r1] = r2; } } int get(int x) { if (lab[x] < 0) return x; lab[x] = get(lab[x]); return lab[x]; } static int desyncIO = []() { std::ios::sync_with_stdio(false); std::cout.tie(nullptr); std::cin.tie(nullptr); return 0; }(); int main() { ios::sync_with_stdio(false); memset(lab, -1, sizeof(lab)); cin >> n >> m; for (int i = 1; i <= n; i++) { long long x; cin >> x; vertices.push_back(make_pair(x, i)); } sort(vertices.begin(), vertices.end(), cmp); for (int i = 1; i < n; i++) { int u = vertices[0].second; int v = vertices[i].second; long long w = vertices[0].first + vertices[i].first; ed.push_back(make_pair(w, make_pair(u, v))); } for (int i = 1; i <= m; i++) { int u, v; long long w; cin >> u >> v >> w; ed.push_back(make_pair(w, make_pair(u, v))); } sort(ed.begin(), ed.end(), cmp2); long long ret = 0; for (int i = 0; i < ed.size(); i++) { int u = ed[i].second.first; int v = ed[i].second.second; long long w = ed[i].first; int r1 = get(u); int r2 = get(v); if (r1 != r2) { ret += w; uni(r1, r2); } } cout << ret; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int INF = 0x3f3f3f3f; const int GRAPH_SIZE = 20010; int pin[GRAPH_SIZE], dep[GRAPH_SIZE], s = 0, t = GRAPH_SIZE - 1; struct EDGE { int u, v, c; }; vector<EDGE> e; vector<int> each[GRAPH_SIZE]; bool bfs() { queue<int> Q; Q.push(s); while (!Q.empty()) { int now = Q.front(); Q.pop(); for (auto it : each[now]) { int next = e[it].v; if (e[it].c) if (dep[next] > dep[now] + 1) { dep[next] = dep[now] + 1; Q.push(next); } } } return dep[t] != INF; } int dfs(int now, int flow) { if (now == t) { return flow; } for (int& i = pin[now]; i < each[now].size(); i++) { int it = each[now][i]; if (e[it].c && dep[e[it].v] == dep[now] + 1) { int tmp; if (tmp = dfs(e[it].v, min(flow, e[it].c))) { e[it].c -= tmp; e[it ^ 1].c += tmp; return tmp; } } } return 0; } int Dinic() { int max_flow = 0; for (int i = 0; i < GRAPH_SIZE; ++i) { dep[i] = INF; } dep[s] = 0; while (bfs()) { for (int i = 0; i < GRAPH_SIZE; ++i) { pin[i] = 0; } int tmp; while (tmp = dfs(s, INF)) { max_flow += tmp; } for (int i = 0; i < GRAPH_SIZE; ++i) { dep[i] = INF; } dep[s] = 0; } return max_flow; } void make_edge(int U, int V, int C) { EDGE tmp; tmp.u = U; tmp.v = V; tmp.c = C; e.push_back(tmp); each[U].push_back(e.size() - 1); swap(tmp.u, tmp.v); tmp.c = 0; e.push_back(tmp); each[V].push_back(e.size() - 1); } void init() { e.clear(); for (int i = 0; i < GRAPH_SIZE; ++i) { each[i].clear(); } } vector<pair<int, pair<int, int> > > edges; int n; int m; bool check(int x) { init(); for (int i = 1; i <= n; ++i) make_edge(s, i, 1); for (int i = 1; i <= n; ++i) make_edge(i + n, t, 1); for (int i = 0; i < x; ++i) { make_edge(edges[i].second.first, edges[i].second.second + n, 1); } if (Dinic() == n) return true; return false; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= m; ++i) { int u, v, d; cin >> u >> v >> d; edges.push_back(make_pair(d, make_pair(u, v))); } sort(edges.begin(), edges.end()); if (!check(m)) { cout << -1 << endl; return 0; } int l = 1, r = m; while (l < r) { int mid = (l + r) >> 1; if (check(mid)) { r = mid; } else { l = mid + 1; } } cout << edges[l - 1].first << endl; return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_transition (clock, reset, enable, test_expr, start_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr, start_state, next_state;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_TRANSITION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_transition_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_transition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_transition_psl_logic.v"
`else
`endmodule // ovl_transition
`endif
|
//-----------------------------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUtu_veD WITHOUT THE
// EXPRESSED WRITtu_veN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//------------------------------------------------------------------------------------------------
// Filename : db_qp.v
// Author : chewein
// Creatu_ved : 2014-04-18
// Description : modified the 8x8 cu qp of the current cu
// qp_flag_o = 1 means the qp of the current cu should be modified
//------------------------------------------------------------------------------------------------
module db_qp(
clk ,
rst_n ,
cbf_4x4_i ,
cbf_u_4x4_i ,
cbf_v_4x4_i ,
qp_left_i ,
qp_flag_o
);
// *************************************************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// *************************************************************************************************
input clk ;
input rst_n ;
input cbf_4x4_i ;
input cbf_u_4x4_i ;
input cbf_v_4x4_i ;
input qp_left_i ;//indicate the left 4x4 cu qp is modified or not
output qp_flag_o ;
reg qp_flag_o ;
//---------------------------------------------------------------------------------------------------
wire modified_flag = !(cbf_4x4_i ||cbf_u_4x4_i ||cbf_v_4x4_i );//4x4
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
qp_flag_o <= 1'b0 ;
else if(modified_flag)//all coeffs = 0
qp_flag_o <= qp_left_i ;//qp_flag=1:qp need to be modified
else
qp_flag_o <= 1'b0 ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_SYMBOL_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s15kapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_SYMBOL_V
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <>
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cin (
.I0(CI),
.I1(1'b1),
.CI(1'b0),
.CO(CIx)
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_i (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.O(Y[i]),
.CO(COx[i])
);
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(COx[i]),
.O(CO[i])
);
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> v, ans; void op(int i) { int x = v[i + 2]; v[i + 2] = v[i + 1]; v[i + 1] = v[i]; v[i] = x; if (ans.size() >= 2 && ans[ans.size() - 1] == i + 1 && ans[ans.size() - 2] == i + 1) ans.pop_back(), ans.pop_back(); else ans.push_back(i + 1); } void reach(int x, int y) { while (y > x + 1) op(y - 2), y -= 2; if (y == x + 1) op(y - 1), op(y - 1); } int main(int argc, char **argv) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, st = 0, temp = 0; ans.clear(); cin >> n; v.resize(n); vector<int> ar(501, -1); int val = -1, x, y; for (int i = 0; i < n; i++) { cin >> v[i]; if (ar[v[i]] != -1) val = v[i], x = ar[v[i]], y = i; ar[v[i]] = i; } if (val != -1) v[x] = v[y] = 2000; while (n - st > 3) { int mi = 1000, in; for (int j = st; j < n; j++) if (v[j] < mi) mi = v[j], in = j; reach(st, in); st++; } if (val == -1) { while (!(v[st] <= v[st + 1] && v[st + 1] <= v[st + 2])) { op(st), temp++; if (temp > 5) { cout << -1 << endl; goto brk; } } } else { while (v[st + 1] != 2000 || v[st + 2] != 2000) op(st); while (st >= 0 && val < v[st]) op(st), op(st), st--; } cout << ans.size() << endl; for (auto x : ans) cout << x << ; cout << endl; brk:; } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int n, s[3000 + 5], c[3000 + 5], f[3000 + 5][5]; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } int main() { n = read(); memset(f, inf, sizeof(f)); for (int i = 1; i <= n; i++) s[i] = read(); for (int i = 1; i <= n; i++) c[i] = read(); for (int i = 1; i <= n; i++) { f[i][1] = c[i]; for (int j = 1; j < i; j++) if (s[j] < s[i]) f[i][2] = min(f[j][1] + c[i], f[i][2]); for (int j = 1; j < i; j++) if (s[j] < s[i]) f[i][3] = min(f[j][2] + c[i], f[i][3]); } int ans = inf; for (int i = 1; i <= n; i++) if (f[i][3]) ans = min(ans, f[i][3]); if (ans == inf) cout << -1; else cout << ans; return 0; }
|
#include <bits/stdc++.h> const int MAXN = 5; const double eps = 1e-4; struct node { double x, y; node(double x = 0, double y = 0) : x(x), y(y) {} inline bool operator<(const node &rhs) const { if (fabs(x - rhs.x) >= eps) return x < rhs.x; if (fabs(y - rhs.y) >= eps) return y < rhs.y; return 0; } inline bool operator==(const node &rhs) const { return !(*this < rhs) && !(rhs < *this); } } p[MAXN * MAXN << 1]; struct circle { double a, b, r; circle(double a = 0, double b = 0, double r = 0) : a(a), b(b), r(r) {} } c[MAXN]; std::vector<node> ans; inline void getcircle_intersection(circle x, circle y) { if (x.r < y.r) std::swap(x, y); if (fabs((x.r + y.r) * (x.r + y.r) - (x.a - y.a) * (x.a - y.a) - (x.b - y.b) * (x.b - y.b)) < eps) { const double dx = (y.a - x.a), dy = (y.b - x.b), k = x.r / (x.r + y.r); ans.push_back(node(x.a + dx * k, x.b + dy * k)); return; } if (fabs(y.r + sqrt((x.a - y.a) * (x.a - y.a) + (x.b - y.b) * (x.b - y.b)) - x.r) < eps) { const double dx = (y.a - x.a), dy = (y.b - x.b), k = x.r / (x.r - y.r); ans.push_back(node(x.a + dx * k, x.b + dy * k)); return; } if ((x.r + y.r) * (x.r + y.r) < (x.a - y.a) * (x.a - y.a) + (x.b - y.b) * (x.b - y.b)) return; if (y.r + sqrt((x.a - y.a) * (x.a - y.a) + (x.b - y.b) * (x.b - y.b)) < x.r) return; const double lk = (x.a - y.a) / (y.b - x.b), lb = (x.r * x.r - y.r * y.r + y.a * y.a - x.a * x.a + y.b * y.b - x.b * x.b) / (2 * y.b - 2 * x.b); const double fa = lk * lk + 1, fb = 2 * lk * lb - 2 * x.a - 2 * x.b * lk, fc = x.a * x.a + x.b * x.b + lb * lb - 2 * x.b * lb - x.r * x.r; double dt = fb * fb - 4 * fa * fc; if (fabs(dt) > eps && dt < 0) return; dt = fabs(dt); const double ax1 = (-fb + sqrt(dt)) / (2 * fa), ax2 = (-fb - sqrt(dt)) / (2 * fa); ans.push_back(node(ax1, lk * ax1 + lb)); ans.push_back(node(ax2, lk * ax2 + lb)); } inline bool point_on_circle(const node &x, const circle &y) { return fabs((x.x - y.a) * (x.x - y.a) + (x.y - y.b) * (x.y - y.b) - y.r * y.r) <= eps; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { double a, b, r; scanf( %lf%lf%lf , &a, &b, &r); c[i].a = a * cos(233) + b * sin(233); c[i].b = -a * sin(233) + b * cos(233); c[i].r = r; } for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) getcircle_intersection(c[i], c[j]); std::sort(ans.begin(), ans.end()); int sz = std::unique(ans.begin(), ans.end()) - ans.begin(); int tot = 0; for (int i = 1; i <= n; i++) { int ptot = 0; for (unsigned j = 0; j < sz; j++) ptot += point_on_circle(ans[j], c[i]); tot += ptot + !ptot; } if (sz == 0) tot--; printf( %d n , tot - sz + 2); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_4_V
`define SKY130_FD_SC_LS__EINVN_4_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_1_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_1_V
|
module vgaSync(clk, rst, hsync, vsync, video_on, p_tick, pixel_x, pixel_y);
input clk, rst;
output hsync, vsync, video_on, p_tick;
output [9:0] pixel_x, pixel_y;
// constant declaration
// VGA 640-by-480 sync parameters
parameter HD = 640; // horizontal display area
parameter HF = 48; // h. front (left) border
parameter HB = 16; // h. back (right) border
parameter HR = 96; // h. retrace
parameter VD = 480; // vertical display area
parameter VF = 10; // v. front (top) border
parameter VB = 33; // v. back (bottom) border
parameter VR = 2; // v. retrace
// mod_2 counter
reg mod2;
wire mod2Next;
// sync counters
reg [9:0] h_count, h_countNext;
reg [9:0] v_count, v_countNext;
reg v_sync, h_sync;
wire v_syncNext, h_syncNext;
wire h_end, v_end, pixel_tick;
always @(posedge clk) begin
mod2 <= #1 mod2Next;
v_count <= #1 v_countNext;
h_count <= #1 h_countNext;
v_sync <= #1 v_syncNext;
h_sync <= #1 h_syncNext;
end
// mod2 circuit to generate 25 MHz enable tick
assign mod2Next = rst ? 0 : ~mod2;
assign pixel_tick = mod2;
// status signals
// end of horizontal counter (799)
assign h_end = (h_count == (HD+HF+HB+HR-1));
// end of vertical counter (524)
assign v_end = (v_count == (VD+VF+VB+VR-1));
// next-statelogic of mod-800 horizontal sync counter
always @(*) begin
h_countNext = h_count;
if(rst)
h_countNext = 0;
else if(pixel_tick) // 25 MHz pulse
if(h_end)
h_countNext = 0;
else
h_countNext = h_count + 1;
end
// next-state logic of mod-525 vertical sync counter
always @(*) begin
v_countNext = v_count;
if(rst)
v_countNext = 0;
else if(pixel_tick & h_end)
if(v_end)
v_countNext = 0;
else
v_countNext = v_count + 1;
end
// horizontal and vertical sync , buffered to avoid glitch
// h_svnc_next asserted between 656 and 751
assign h_syncNext = rst ? 0 : (h_count >= (HD+HB) && h_count <= (HD+HB+HR-1));
// v_syncNext asserted between 490 and 491
assign v_syncNext = rst ? 0 : (v_count >= (VD+VB) && v_count <= (VD+VB+VR-1));
// video on/off
assign video_on = (h_count < HD) && (v_count < VD);
// output
assign hsync = h_sync;
assign vsync = v_sync;
assign p_tick = mod2;
assign pixel_x = h_count;
assign pixel_y = v_count;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100010]; int b[15]; bool cmp(int x, int y) { if (x == 100 || y == 100) return x < y; else return x % 10 > y % 10; } int main() { int n, k; b[0] = 0; for (int i = 1; i <= 10; i++) b[i] = b[i - 1] + 10; while (scanf( %d%d , &n, &k) != EOF) { for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n; i++) { if (k <= 0) break; if (a[i] % 10 == 0 || a[i] == 100) continue; int pos = upper_bound(b + 1, b + 11, a[i]) - b; int num = b[pos] - a[i]; if (num > k) break; a[i] = b[pos]; k -= num; } int ans = 0, sum = 0; for (int i = 1; i <= n; i++) { ans += a[i] / 10; sum += 100 - a[i]; } printf( %d n , ans + min(sum, k) / 10); } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_PIO0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
irq,
readdata
)
;
inout [ 4: 0] bidir_port;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 4: 0] bidir_port;
wire clk_en;
reg [ 4: 0] d1_data_in;
reg [ 4: 0] d2_data_in;
reg [ 4: 0] data_dir;
wire [ 4: 0] data_in;
reg [ 4: 0] data_out;
reg [ 4: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 4: 0] edge_detect;
wire irq;
reg [ 4: 0] irq_mask;
wire [ 4: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({5 {(address == 0)}} & data_in) |
({5 {(address == 1)}} & data_dir) |
({5 {(address == 2)}} & irq_mask) |
({5 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[4 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[4 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[4 : 0];
end
assign irq = |(data_in & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; inline int get_power(int a, int n) { int res = 1; while (n > 0) { res = n & 1 ? 1ll * res * a % mod : res; a = 1ll * a * a % mod; n >>= 1; } return res; } inline int get_inv(int x) { return get_power(x, mod - 2); } inline int C2(int x) { return (x * (x - 1ll) >> 1) % mod; } const int max_n = 2e3 + 5; int power_p[max_n], power_q[max_n]; int f[max_n], g[max_n], h[max_n][max_n]; int main() { int n, a, b; scanf( %d%d%d , &n, &a, &b); int p = 1ll * a * get_inv(b) % mod; power_p[0] = power_q[0] = 1; for (int i = 1; i <= n; ++i) { power_p[i] = 1ll * power_p[i - 1] * p % mod; power_q[i] = power_q[i - 1] * (mod + 1ll - p) % mod; } h[1][0] = h[1][1] = 1; for (int i = 2; i <= n; ++i) for (int j = 0; j <= i; ++j) h[i][j] = (1ll * h[i - 1][j] * power_p[j] + (j > 0 ? 1ll * h[i - 1][j - 1] * power_q[i - j] : 0)) % mod; for (int i = 1; i <= n; ++i) { g[i] = 1; for (int j = 1; j <= i - 1; ++j) { g[i] -= 1ll * g[j] * h[i][j] % mod; g[i] += g[i] < 0 ? mod : 0; } } for (int i = 1; i <= n; ++i) { f[i] = 1ll * g[i] * h[i][i] % mod * C2(i) % mod; for (int j = 1; j <= i - 1; ++j) f[i] = (f[i] + 1ll * g[j] * h[i][j] % mod * (1ll * f[j] + f[i - j] + C2(i) - C2(i - j) + mod)) % mod; f[i] = 1ll * f[i] * get_inv(mod + 1 - 1ll * g[i] * h[i][i] % mod) % mod; } printf( %d n , f[n]); return 0; }
|
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[0:0] , crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------
module crc(
input [0:0] data_in,
input crc_en,
output [15:0] crc_out,
input rst,
input clk);
reg [15:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[15] ^ data_in[0];
lfsr_c[1] = lfsr_q[0];
lfsr_c[2] = lfsr_q[1] ^ lfsr_q[15] ^ data_in[0];
lfsr_c[3] = lfsr_q[2];
lfsr_c[4] = lfsr_q[3];
lfsr_c[5] = lfsr_q[4];
lfsr_c[6] = lfsr_q[5];
lfsr_c[7] = lfsr_q[6];
lfsr_c[8] = lfsr_q[7];
lfsr_c[9] = lfsr_q[8];
lfsr_c[10] = lfsr_q[9];
lfsr_c[11] = lfsr_q[10];
lfsr_c[12] = lfsr_q[11];
lfsr_c[13] = lfsr_q[12];
lfsr_c[14] = lfsr_q[13];
lfsr_c[15] = lfsr_q[14] ^ lfsr_q[15] ^ data_in[0];
end // always
always @(posedge clk, posedge rst) begin
if(rst) begin
lfsr_q <= {16{1'b0}};
end
else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc
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#include <bits/stdc++.h> using namespace std; long long n; int m; const long long mod = 1e9 + 7; struct Mat { long long mat[111][111]; } st, ed; long long stt[111][111]; void init() { memset(stt, 0, sizeof(stt)); stt[0][0] = stt[0][m - 1] = 1; for (int i = 1; i < m; ++i) stt[i][i - 1] = 1; for (int i = 0; i < m; ++i) for (int j = 0; j < m; ++j) st.mat[i][j] = stt[i][j]; } Mat mul(Mat a, Mat b) { Mat ret; for (int i = 0; i < m; ++i) for (int j = 0; j < m; ++j) { ret.mat[i][j] = 0; for (int k = 0; k < m; ++k) (ret.mat[i][j] += a.mat[i][k] * b.mat[k][j] % mod) %= mod; } return ret; } Mat pow(Mat a, long long b) { Mat ret; memset(ret.mat, 0, sizeof(ret.mat)); for (int i = 0; i < m; ++i) ret.mat[i][i] = 1; while (b) { if (b & 1) ret = mul(ret, a); a = mul(a, a); b >>= 1; } return ret; } int main() { cin >> n >> m; if (n < m) return 0 * puts( 1 ); init(); ed = pow(st, n - m + 1); long long ans = 0; for (int i = 0; i < m; ++i) (ans += ed.mat[0][i]) %= mod; cout << ans << ( n ); }
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#include <bits/stdc++.h> using namespace std; int x[1000 + 1], y[1000 + 1]; void solve() { int n; cin >> n; for (int i = 0; i < n + 1; i++) cin >> x[i] >> y[i]; int res = 0; for (int i = 1; i < n; i++) { double X = x[i], Y = y[i]; int cnt = 0; if (x[i - 1] == x[i]) { if (y[i] > y[i - 1]) Y += 0.2; else Y -= 0.2; for (int j = 0; j < n; j++) if (x[j] == x[j + 1] && x[j] < x[i] && min(y[j], y[j + 1]) < Y && Y < max(y[j], y[j + 1])) cnt++; if (cnt % 2 == 1) res++; } else { if (x[i] > x[i - 1]) X += 0.2; else X -= 0.2; for (int j = 0; j < n; j++) if (y[j] == y[j + 1] && y[j] < y[i] && min(x[j], x[j + 1]) < X && X < max(x[j], x[j + 1])) cnt++; if (cnt % 2 == 1) res++; } } cout << res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; inline int readint() { int x = 0; bool f = 0; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) { f = 1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } return f ? -x : x; } const int maxn = 4e5 + 5; int n, m, c[maxn]; vector<int> g[maxn]; int fa[maxn]; void dfs(int u) { for (int i = 0; i < (int)g[u].size(); i++) { int v = g[u][i]; if (v == fa[u]) continue; fa[v] = u; dfs(v); } } struct lct { int fa[maxn], ch[maxn][2], s[maxn], s2[maxn]; long long ss[maxn]; void init() { for (int i = 1; i <= n; i++) s[i] = 1; } void pushup(int x) { s[x] = s2[x] + 1; if (ch[x][0]) s[x] += s[ch[x][0]]; if (ch[x][1]) s[x] += s[ch[x][1]]; } bool isroot(int x) { return !fa[x] || (ch[fa[x]][0] != x && ch[fa[x]][1] != x); } void rotate(int x) { int y = fa[x], z = fa[fa[x]]; if (!isroot(y)) ch[z][ch[z][1] == y] = x; bool d = ch[y][1] == x; int k = ch[x][!d]; if (k) fa[k] = y; ch[y][d] = k; ch[x][!d] = y; fa[y] = x; fa[x] = z; pushup(y); pushup(x); } void splay(int x) { while (!isroot(x)) { int y = fa[x], z = fa[fa[x]]; if (!isroot(y)) { if ((ch[y][1] == x) ^ (ch[z][1] == y)) rotate(x); else rotate(y); } rotate(x); } } void access(int x) { int y = 0; while (x) { splay(x); if (ch[x][1]) { s2[x] += s[ch[x][1]]; ss[x] += 1ll * s[ch[x][1]] * s[ch[x][1]]; } ch[x][1] = y; if (y) { s2[x] -= s[y]; ss[x] -= 1ll * s[y] * s[y]; } y = x; x = fa[x]; } } int findroot(int x) { access(x); splay(x); while (ch[x][0]) x = ch[x][0]; splay(x); return x; } void link(int x, int y) { access(y); splay(y); splay(x); fa[x] = y; s2[y] += s[x]; ss[y] += 1ll * s[x] * s[x]; pushup(y); } void cut(int x, int y) { access(y); splay(y); splay(x); fa[x] = 0; s2[y] -= s[x]; ss[y] -= 1ll * s[x] * s[x]; pushup(y); } } t; vector<pair<int, int> > q[maxn]; bool c2[maxn]; long long query(int u) { int x = t.findroot(u); if (c2[x]) return 1ll * t.s[t.ch[x][1]] * t.s[t.ch[x][1]]; else return 1ll * t.s[x] * t.s[x]; } long long modify(int u) { c2[u] ^= 1; if (c2[u]) { if (u == 1) { t.access(1); return t.ss[1] - 1ll * t.s[1] * t.s[1]; } else { long long res = -query(u); t.cut(u, fa[u]); t.access(u); res += t.ss[u]; if (!c2[fa[u]]) res += query(fa[u]); return res; } } else { if (u == 1) { t.access(1); return 1ll * t.s[1] * t.s[1] - t.ss[1]; } else { t.access(u); long long res = -t.ss[u]; if (!c2[fa[u]]) res -= query(fa[u]); t.link(u, fa[u]); res += query(u); return res; } } } long long ans[maxn]; void solve(int c) { for (int i = 0; i < (int)q[c].size(); i++) ans[q[c][i].first] += modify(q[c][i].second); for (int i = (int)q[c].size() - 1; i >= 0; i--) modify(q[c][i].second); } int main() { n = readint(); m = readint(); for (int i = 1; i <= n; i++) c[i] = readint(); for (int i = 1; i < n; i++) { int u, v; u = readint(); v = readint(); g[u].push_back(v); g[v].push_back(u); } dfs(1); t.init(); for (int i = 2; i <= n; i++) t.link(i, fa[i]); for (int i = 1; i <= n; i++) q[c[i]].push_back(pair<int, int>(0, i)); for (int i = 1; i <= m; i++) { int u, x; u = readint(); x = readint(); q[c[u]].push_back(pair<int, int>(i, u)); q[c[u] = x].push_back(pair<int, int>(i, u)); } for (int i = 1; i <= n; i++) solve(i); for (int i = 1; i <= m; i++) ans[i] += ans[i - 1]; for (int i = 0; i <= m; i++) printf( %lld n , -ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; int cnt[26]; void sol() { int n; cin >> n; for (int i = 0; i < n; i++) { long long k, x; cin >> k >> x; cout << (x + (k - 1) * 9) << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) sol(); }
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#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { int arr[100005]; for (int i = 1; i <= n; i++) { cin >> arr[i]; } long long cnt = 0; for (int i = 1; i < n; i++) { long long x = log2(n - i); arr[i + (1 << x)] += arr[i]; cnt += arr[i]; arr[i] = 0; cout << cnt << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> typename T::value_type arr_sum(const T& v, int n) { typename T::value_type sum = 0; for (int i = 0; i < n; ++i) sum += v[i]; return sum; } struct Sync_stdio { Sync_stdio() { cin.tie(NULL); ios_base::sync_with_stdio(false); } } _sync_stdio; int n, m; vector<string> w(n); void print_square(int x1, int x2, int y1, int y2) { for (int i = x1; i < x2 + 1; ++i) { if (w[i][y1] != w ) { w[i][y1] = + ; } if (w[i][y2] != w ) { w[i][y2] = + ; } } for (int i = y1; i < y2 + 1; ++i) { if (w[x1][i] != w ) { w[x1][i] = + ; } if (w[x2][i] != w ) { w[x2][i] = + ; } } for (auto i : w) { cout << i << n ; } exit(0); } void check1(vector<pair<int, int> >& v) { int max1 = -1, min1 = 100001; int max2 = -1, min2 = 100001; for (int i = 0; i < v.size(); ++i) { max1 = max(max1, v[i].first); min1 = min(min1, v[i].first); max2 = max(max2, v[i].second); min2 = min(min2, v[i].second); } int left = 0, up = 0, right = 0, down = 0; for (int i = 0; i < v.size(); ++i) { if (v[i].first == min1 && min2 < v[i].second && v[i].second < max2) { up = 1; } if (v[i].first == max1 && min2 < v[i].second && v[i].second < max2) { down = 1; } if (v[i].second == min2 && min1 < v[i].first && v[i].first < max1) { left = 1; } if (v[i].second == max2 && min1 < v[i].first && v[i].first < max1) { right = 1; } if (min1 < v[i].first && v[i].first < max1 && min2 < v[i].second && v[i].second < max2) { cout << -1; exit(0); } } if (max1 == min1) { up = 0; down = 0; } if (min2 == max2) { left = 0; right = 0; } if (max1 - min1 == max2 - min2) { print_square(min1, max1, min2, max2); } if (up && down && left && right) { cout << -1; exit(0); } int diff = (max1 - min1) - (max2 - min2); if (diff > 0) { if (!left && max2 + (min1 - max1) >= 0) { print_square(min1, max1, max2 + (min1 - max1), max2); } if (!right && min2 + (max1 - min1) < m) { print_square(min1, max1, min2, min2 + (max1 - min1)); } if (!left && !right && max1 - min1 < m) { print_square(min1, max1, 0, max1 - min1); } } if (diff < 0) { if (!up && max1 + (min2 - max2) >= 0) { print_square(max1 + (min2 - max2), max1, min2, max2); } if (!down && min1 + (max2 - min2) < n) { print_square(min1, min1 + (max2 - min2), min2, max2); } if (!up && !down && max2 - min2 < n) { print_square(0, max2 - min2, min2, max2); } } cout << -1; exit(0); } int main() { cin >> n >> m; vector<pair<int, int> > v; for (int i = 0; i < n; ++i) { string t; cin >> t; w.push_back(t); for (int j = 0; j < m; ++j) { if (t[j] == w ) { v.push_back({i, j}); } } } check1(v); }
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#include <bits/stdc++.h> using namespace std; template <typename T> inline T read(register T& t) { register T f = 1; register char ch = getchar(); t = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -f; ch = getchar(); } while (ch >= 0 && ch <= 9 ) t = t * 10 + ch - 0 , ch = getchar(); t *= f; return t; } template <typename T, typename... Args> inline void read(T& t, Args&... args) { read(t); read(args...); } const long long p = 998244353; inline long long power(register long long x, register long long k = p - 2) { register long long re = 1; for (; k; k >>= 1, x = x * x % p) if (k & 1) re = re * x % p; return re; } long long n, m; long long a[300005]; long long g[300005], f[300005]; long long ans; int main() { read(n); for (int i = 1; i <= n; i++) read(a[i]), m += a[i]; g[0] = n - 1; for (int i = 1; i < m; i++) g[i] = (m * (n - 1) % p + g[i - 1] * (n - 1) % p * i % p) * power(m - i) % p; f[m] = 0; for (int i = m - 1; i >= 0; i--) f[i] = (f[i + 1] + g[i]) % p; ans = (p - f[0] * (n - 1) % p) % p; for (int i = 1; i <= n; i++) ans = (ans + f[a[i]]) % p; printf( %lld n , ans * power(n) % p); return 0; }
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { long long r; while (b != 0) { r = a % b; a = b; b = r; } return a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } int const nmax = 1010; int k, n; vector<pair<int, int> > st, pe; vector<int> ans[nmax]; bool dc[nmax]; long double p[nmax]; void solve() { memset(dc, 0, sizeof(dc)); cin >> k >> n; for (int i = 0; i < k; i++) { int c, t; cin >> c >> t; p[i] = c; if (t == 1) st.push_back(pair<int, int>(c, i)); else pe.push_back(pair<int, int>(c, i)); } sort(st.begin(), st.end()); sort(pe.begin(), pe.end()); int k = 0; while (!st.empty()) { if (k >= n) k = n - 1; dc[k] = 1; ans[k].push_back(st.back().second); st.pop_back(); k++; } for (int i = n - 1; i >= 0; i--) { if (int((ans[i]).size()) > 0) break; ans[i].push_back(pe.front().second); pe.erase(pe.begin()); } while (!pe.empty()) { if (k >= n) k = n - 1; ans[k].push_back(pe.back().second); pe.pop_back(); k++; } long double sum = 0; for (int i = 0; i < n; i++) { long double m = INT_MAX; for (int j = 0; j < int((ans[i]).size()); j++) { int k = ans[i][j]; sum += p[k]; m = ((m) > (p[k]) ? (p[k]) : (m)); } if (dc[i]) sum -= m / 2; } cout << fixed << setprecision(1) << sum << n ; for (int i = 0; i < n; i++) { cout << int((ans[i]).size()) << ; for (int j = 0; j < int((ans[i]).size()); j++) cout << ans[i][j] + 1 << ; cout << n ; } } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 + 10; const int MAXM = 10000 + 10; const int INF = 1000 * 1000 * 1000; int n, m, a[MAXM], b[MAXM], c[MAXM], q[MAXN], d[MAXN][MAXN], s, minimum[MAXN]; int main() { int check = 0; int sum = 0; int pt = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; minimum[i] = INF; } cin >> m; for (int i = 0; i < m; i++) { cin >> a[i] >> b[i] >> c[i]; d[a[i]][b[i]] = c[i]; minimum[b[i]] = min(c[i], minimum[b[i]]); } for (int i = 1; i <= n; i++) { if (minimum[i] != INF) { sum += minimum[i]; check++; } } if (check == n - 1) cout << sum; else cout << -1; cin >> s; return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axis_dma_rx (
// adc interface
adc_clk,
adc_rst,
// dma interface
dma_clk,
dma_rst,
dma_start,
dma_stream,
dma_count,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_VERSION = 32'h00050062;
parameter PCORE_ID = 0;
// adc interface
input adc_clk;
output adc_rst;
// dma interface
input dma_clk;
output dma_rst;
output dma_start;
output dma_stream;
output [31:0] dma_count;
input dma_ovf;
input dma_unf;
input dma_status;
input [31:0] dma_bw;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_dma_stream = 'd0;
reg up_dma_start = 'd0;
reg [31:0] up_dma_count = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dma_start_m1 = 'd0;
reg dma_start_m2 = 'd0;
reg dma_start_m3 = 'd0;
reg dma_start = 'd0;
reg dma_stream = 'd0;
reg [31:0] dma_count = 'd0;
reg [ 5:0] dma_xfer_cnt = 'd0;
reg dma_xfer_toggle = 'd0;
reg dma_xfer_ovf = 'd0;
reg dma_xfer_unf = 'd0;
reg dma_acc_ovf = 'd0;
reg dma_acc_unf = 'd0;
reg up_dma_xfer_toggle_m1 = 'd0;
reg up_dma_xfer_toggle_m2 = 'd0;
reg up_dma_xfer_toggle_m3 = 'd0;
reg up_dma_xfer_ovf = 'd0;
reg up_dma_xfer_unf = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_status_m1 = 'd0;
reg up_dma_status = 'd0;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire up_preset_s;
wire up_dma_xfer_toggle_s;
// decode block select
assign up_sel_s = (up_addr[13:8] == 6'h00) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_scratch <= 'd0;
up_resetn <= 'd0;
up_dma_stream <= 'd0;
up_dma_start <= 'd0;
up_dma_count <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h20)) begin
up_dma_stream <= up_wdata[1];
up_dma_start <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h21)) begin
up_dma_count <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'd0, up_resetn};
8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
8'h21: up_rdata <= up_dma_count;
8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status};
8'h23: up_rdata <= dma_bw;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// ADC CONTROL
FDPE #(.INIT(1'b1)) i_adc_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (adc_clk),
.Q (adc_rst));
// DMA CONTROL
FDPE #(.INIT(1'b1)) i_dma_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (dma_clk),
.Q (dma_rst));
// dma control transfer
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_start_m1 <= 'd0;
dma_start_m2 <= 'd0;
dma_start_m3 <= 'd0;
end else begin
dma_start_m1 <= up_dma_start;
dma_start_m2 <= dma_start_m1;
dma_start_m3 <= dma_start_m2;
end
dma_start <= dma_start_m2 & ~dma_start_m3;
if ((dma_start_m2 == 1'b1) && (dma_start_m3 == 1'b0)) begin
dma_stream <= up_dma_stream;
dma_count <= up_dma_count;
end
end
// dma status transfer
always @(posedge dma_clk) begin
dma_xfer_cnt <= dma_xfer_cnt + 1'b1;
if (dma_xfer_cnt == 6'd0) begin
dma_xfer_toggle <= ~dma_xfer_toggle;
dma_xfer_ovf <= dma_acc_ovf;
dma_xfer_unf <= dma_acc_unf;
end
if (dma_xfer_cnt == 6'd0) begin
dma_acc_ovf <= dma_ovf;
dma_acc_unf <= dma_unf;
end else begin
dma_acc_ovf <= dma_acc_ovf | dma_ovf;
dma_acc_unf <= dma_acc_unf | dma_unf;
end
end
assign up_dma_xfer_toggle_s = up_dma_xfer_toggle_m2 ^ up_dma_xfer_toggle_m3;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_xfer_toggle_m1 <= 'd0;
up_dma_xfer_toggle_m2 <= 'd0;
up_dma_xfer_toggle_m3 <= 'd0;
up_dma_xfer_ovf <= 'd0;
up_dma_xfer_unf <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_dma_xfer_toggle_m1 <= dma_xfer_toggle;
up_dma_xfer_toggle_m2 <= up_dma_xfer_toggle_m1;
up_dma_xfer_toggle_m3 <= up_dma_xfer_toggle_m2;
if (up_dma_xfer_toggle_s == 1'b1) begin
up_dma_xfer_ovf <= dma_xfer_ovf;
up_dma_xfer_unf <= dma_xfer_unf;
end
if (up_dma_xfer_ovf == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
end
if (up_dma_xfer_unf == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[1];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_status_m1 <= 'd0;
up_dma_status <= 'd0;
end else begin
up_dma_status_m1 <= dma_status;
up_dma_status <= up_dma_status_m1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <>
* updated to include Direct Cache Bus by Charley Picker <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_tagmem #(
parameter depth = 2,
parameter width = 2
) (
input sys_clk,
/* Primary port (read-write) */
input [depth-1:0] a,
input we,
input [width-1:0] di,
output [width-1:0] dout,
/* Secondary port (read-only) */
input [depth-1:0] a2,
output [width-1:0] do2
);
reg [width-1:0] tags[0:(1 << depth)-1];
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
a_r <= a;
a2_r <= a2;
end
always @(posedge sys_clk) begin
if(we)
tags[a] <= di;
end
assign dout = tags[a_r];
assign do2 = tags[a2_r];
// synthesis translate_off
integer i;
initial begin
for(i=0;i<(1 << depth);i=i+1)
tags[i] = 0;
end
// synthesis translate_on
endmodule
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Implements the "identity" (often abbreviated as ident) function for 8-bit
// inputs. That is, buffers up four bytes and then sends them back.
`include "xls/uncore_rtl/ice40/uart_receiver.v"
`include "xls/uncore_rtl/ice40/uart_transmitter.v"
module top(
input wire clk,
input wire rx_in,
output wire tx_out,
output wire clear_to_send_out_n
);
parameter ClocksPerBaud = `DEFAULT_CLOCKS_PER_BAUD;
localparam
StateIdle = 2'd0,
StateGotByte = 2'd1,
StateError = 2'd2;
localparam StateBits = 2;
wire rst_n;
assign rst_n = 1;
reg rx_byte_done = 0;
reg rx_byte_done_next;
reg [StateBits-1:0] state = StateIdle;
reg [StateBits-1:0] state_next;
reg [7:0] tx_byte = 8'hff;
reg [7:0] tx_byte_next;
reg tx_byte_valid = 0;
reg tx_byte_valid_next;
wire tx_byte_done;
wire [7:0] rx_byte;
wire rx_byte_valid;
wire clear_to_send;
assign clear_to_send_out_n = ~clear_to_send;
uart_receiver #(
.ClocksPerBaud (ClocksPerBaud)
) rx(
.clk (clk),
.rst_n (rst_n),
.rx (rx_in),
.rx_byte_out (rx_byte),
.rx_byte_valid_out(rx_byte_valid),
.rx_byte_done (rx_byte_done),
.clear_to_send_out(clear_to_send)
);
uart_transmitter #(
.ClocksPerBaud (ClocksPerBaud)
) tx(
.clk (clk),
.rst_n (rst_n),
.tx_byte (tx_byte),
.tx_byte_valid (tx_byte_valid),
.tx_byte_done_out(tx_byte_done),
.tx_out (tx_out)
);
// State manipulation.
always @(*) begin // verilog_lint: waive always-comb b/72410891
state_next = state;
case (state)
StateIdle: begin
if (rx_byte_valid) begin
state_next = tx_byte_done ? StateGotByte : StateError;
end
end
StateGotByte: begin
state_next = StateIdle;
end
endcase
end
// Non-state updates.
always @(*) begin // verilog_lint: waive always-comb b/72410891
rx_byte_done_next = rx_byte_done;
tx_byte_next = tx_byte;
tx_byte_valid_next = tx_byte_valid;
case (state)
StateIdle: begin
tx_byte_valid_next = 0;
end
StateGotByte: begin
tx_byte_next = rx_byte;
tx_byte_valid_next = 1;
rx_byte_done_next = 1;
end
endcase
end
// Note: our version of iverilog has no support for always_ff.
always @ (posedge clk) begin
rx_byte_done <= rx_byte_done_next;
state <= state_next;
tx_byte <= tx_byte_next;
tx_byte_valid <= tx_byte_valid_next;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int p, int q) { return q == 0 ? p : gcd(q, p % q); } char s[100100]; long long res[2][2]; int main() { cin >> s; int len = strlen(s); memset(res, 0, sizeof(res)); long long a = 0, b = 0; for (int i = 0; i < len; i++) { int temp = i & 1; res[s[i] - a ][temp]++; a += res[s[i] - a ][1 - temp]; b += res[s[i] - a ][temp]; } cout << a << << b << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int m = pow(10, 9) + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s, t; cin >> s >> t; int j = 0, l = -1, r = -1; for (int i = 0; i < t.length(); i++) { if (s[j] == t[i]) j++; if (j == s.length()) { l = i + 1; break; } } reverse(s.begin(), s.end()); j = 0; reverse(t.begin(), t.end()); for (int i = 0; i < t.length(); i++) { if (s[j] == t[i]) j++; if (j == s.length()) { r = t.length() - i; break; } } if (l >= r || l == -1 || r == -1) cout << 0 << endl; else cout << r - l << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if (k > n) cout << k; else for (int i = 2;; i++) { if (k * i > n) { cout << k * i; break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long mod = 1e9 + 7; const long long N = 1e5 + 10; inline long long add(long long x, long long y) { x += y; if (x >= mod) x -= mod; return x; } inline long long mul(long long x, long long y) { x = (1LL * x * y) % mod; return x; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n; cin >> n; n--; cout << 0 0 << endl; fflush(stdout); if (n == 0) { cout << 1 0 1 1 ; fflush(stdout); return 0; } string prev; cin >> prev; long long l = 0; long long r = 1e9; long long i = 1; while (i <= n) { long long m = (l + r) / 2; cout << m << << 0 << endl; fflush(stdout); string s; cin >> s; if (s == prev) { l = m; } else { r = m; } i++; } if (r - l < 2) { cout << r << 1 << (r + 1) << << (2 * (r + 1) - 2 * l - 1); fflush(stdout); return 0; } long long m = (l + r) / 2; cout << m << 0 << m << 1 ; fflush(stdout); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:08:01 02/19/2016
// Design Name: tp_final
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/tp_final_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: tp_final
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tp_final_tb;
// Inputs
reg clk;
reg reset;
reg rx;
// Outputs
wire tx;
//Para test
//wire [1:0] op;
wire ena_pip_test;
wire [31:0] pc_PC_out_test;
wire [31:0] instruction_IF_test;
wire [31:0] write_data_WB_out_test;
//wire stallF_HZ_out_test;
//wire [2:0] state_reg_test;
//wire rx_empty_test;
//wire rx_done_tick_test;
//wire [7:0] rx_data_out_test;
//wire [7:0] write_data_test;
//wire [3:0] byteN_test;
//wire [7:0] reg_0;
//wire [7:0] reg_1;
//wire [7:0] reg_2;
//wire [7:0] reg_3;
//wire tick_test;
integer ciclo;
//wire [7:0] fifo_data;
//wire fifo_full;
//wire [1:0] state_test;
wire [7:0] led;
// Instantiate the Unit Under Test (UUT)
tp_final uut (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx),
.led(led),
//.op(op),
.ena_pip_test(ena_pip_test),
.pc_incrementado_PC_out_test(pc_PC_out_test),
.instruction_IF_test(instruction_IF_test),
.write_data_WB_out_test(write_data_WB_out_test)
//.stallF_HZ_out_test(stallF_HZ_out_test)
//.state_reg_test(state_reg_test)
//.rx_empty_test(rx_empty_test),
//.btn_read_reg_test(btn_read_reg_test),
//.write_data_test(write_data_test),
//.byteN_test(byteN_test)
//.reg_0(reg_0),
//.reg_1(reg_1),
//.reg_2(reg_2),
//.reg_3(reg_3),
//.rx_done_tick_test(rx_done_tick_test),
//.rx_data_out_test(rx_data_out_test),
//.tick_test(tick_test),
//.fifo_data(fifo_data),
//.fifo_full(fifo_full),
//.state_test(state_test)
);
initial begin
// Initialize Inputs
clk = 0;
rx = 1;
reset = 0;
ciclo= 0;
// Wait 100 ns for global reset to finish
#1 reset = 1;
#1 reset = 0;
//1 byte 0000_0010
/*
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
*/
#8000
//0000_0010
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
//0000_0011
/*
#64 rx=0;
#64 rx=1;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
*/
//#10000 reset = 1'b1;
//#2 reset = 1'b0;
// Add stimulus here
end
always
begin
#1
clk=~clk;
#1
clk=~clk;
ciclo = ciclo + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[1001][1001], row[1001], col[1001]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int r = 1; r <= n; ++r) row[r] = r; for (int c = 1; c <= m; ++c) col[c] = c; for (int r = 1; r <= n; ++r) for (int c = 1; c <= m; ++c) scanf( %d , &p[r][c]); while (k--) { char s[2]; int x, y; scanf( %s%d%d , s, &x, &y); switch (s[0]) { case r : swap(row[x], row[y]); break; case c : swap(col[x], col[y]); break; case g : printf( %d n , p[row[x]][col[y]]); break; default: break; } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
reg signed [20:0] longp;
reg signed [20:0] longn;
reg signed [40:0] quadp;
reg signed [40:0] quadn;
reg signed [80:0] widep;
reg signed [80:0] widen;
initial begin
longp = 21'shbbccc;
longn = 21'shbbccc; longn[20] = 1'b1;
quadp = 41'sh1_bbbb_cccc;
quadn = 41'sh1_bbbb_cccc; quadn[40] = 1'b1;
widep = 81'shbc_1234_5678_1234_5678;
widen = 81'shbc_1234_5678_1234_5678; widen[40] = 1'b1;
// Display formatting
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
$time, longp, longp, longp, longp, longp, longp, longp, longp);
$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
$time, longn, longn, longn, longn, longn, longn, longn, longn);
$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
$time, quadp, quadp, quadp, quadp, quadp, quadp, quadp, quadp);
$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
$time, quadn, quadn, quadn, quadn, quadn, quadn, quadn, quadn);
$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p",
$time, widep, widep, widep, widep, widep, widep);
$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p",
$time, widen, widen, widen, widen, widen, widen);
$display;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module alu_slice(a, b, c, less, sel, cout, out);
input a, b, c, less;
input [2:0] sel;
output cout, out;
wire sum, cout, ANDresult,less, ORresult, b_inv;
reg out;
assign b_inv = sel[2] ^ b;
assign ANDresult = a & b;
assign ORresult = a | b;
fulladder f1(a, b_inv, c, sum, cout);
always @(a or b or c or less or sel)
begin
case(sel[1:0])
2'b00: out = ANDresult;
2'b01: out = ORresult;
2'b10: out = sum;
2'b11: out = less;
endcase
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int a, b, c, d, i, j, n, m, k, g, s; long long ans; pair<pair<int, int>, pair<int, int> > edges[50001]; vector<int> sm[201]; int cs[201][201]; pair<int, int> cur[201]; bool found; bool used[201]; inline void removeSm(int oa, int ob) { for (int _n(((int)((sm[oa]).size())) - 1), i(0); i <= _n; i++) { if (sm[oa][i] == ob) { swap(sm[oa][i], sm[oa].back()); sm[oa].pop_back(); return; } } } inline void replaceTreeEdge(int oa, int ob, int a, int b, int c) { removeSm(oa, ob); removeSm(ob, oa); sm[a].push_back(b); sm[b].push_back(a); cs[a][b] = cs[b][a] = c; cs[oa][ob] = cs[ob][oa] = cs[0][0]; for (int _n((k)-1), i(0); i <= _n; i++) { if ((cur[i].first == oa && cur[i].second == ob) || (cur[i].first == ob && cur[i].second == oa)) { cur[i] = make_pair(a, b); break; } } } void dfs(int v, int st, int en, int c, int cur = -1, int ca = -1, int cb = -1) { used[v] = 1; if (v == en) { found = 1; if (cur <= c) return; replaceTreeEdge(ca, cb, st, en, c); return; } for (int _n(((int)((sm[v]).size())) - 1), i(0); i <= _n; i++) { int w = sm[v][i]; if (used[w]) continue; int nx = cur, na = ca, nb = cb; if (cs[v][w] > nx) { nx = cs[v][w]; na = v; nb = w; } dfs(w, st, en, c, nx, na, nb); if (found) return; } } inline void addEdge(int a, int b, int c) { if (a == b) return; if (cs[a][b] <= 1000000000) { if (cs[a][b] <= c) return; cs[a][b] = cs[b][a] = c; return; } memset(used, 0, n); found = 0; dfs(a, a, b, c); if (!found) { cur[k++] = make_pair(a, b); cs[a][b] = cs[b][a] = c; sm[a].push_back(b); sm[b].push_back(a); } } int main() { scanf( %d%d , &n, &m); scanf( %d%d , &g, &s); for (int _n((m)-1), i(0); i <= _n; i++) { scanf( %d%d%d%d , &a, &b, &c, &d); --a; --b; edges[i] = make_pair(make_pair(c, d), make_pair(a, b)); } sort(edges, edges + m); memset(cs, 63, sizeof(cs)); k = 0; ans = 2000000000000000000LL + 1; for (int _n((m)-1), i(0); i <= _n; i++) { addEdge(edges[i].second.first, edges[i].second.second, edges[i].first.second); if (k == n - 1) { a = 0; for (int _n((n - 1) - 1), j(0); j <= _n; j++) if (cs[cur[j].first][cur[j].second] > a) a = cs[cur[j].first][cur[j].second]; if ((long long)a * s + (long long)g * edges[i].first.first < ans) ans = (long long)a * s + (long long)g * edges[i].first.first; } } if (ans > 2000000000000000000LL) ans = -1; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int ask(int i, int j) { cout << ? << i << << j << endl; fflush(stdout); int val; cin >> val; return val; } int main() { int n; cin >> n; int a[n + 1]; int index = 1, i, x, y; for (int i = 2; i <= n; i++) { x = ask(index, i); y = ask(i, index); if (x > y) { a[index] = x; index = i; } else if (y > x) { a[i] = y; } } a[index] = n; cout << ! ; for (i = 1; i <= n; i++) cout << a[i] << ; cout << n ; fflush(stdout); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; int a[107]; map<string, int> f; vector<pair<int, string>> b; bool cmp(pair<int, string> u, pair<int, string> v) { return u.first > v.first; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= m; i++) { string s; cin >> s; if (f[s] == 0) f[s] = 1; else f[s]++; } sort(a + 1, a + n + 1); for (map<string, int>::iterator it = f.begin(); it != f.end(); ++it) { b.push_back(make_pair(it->second, it->first)); } sort(b.begin(), b.end(), cmp); long long minP = 0, maxP = 0; for (int i = 0; i < b.size(); i++) { minP += b[i].first * a[i + 1]; maxP += b[i].first * a[n - i]; } cout << minP << << maxP << endl; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scbuf_fbd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "iop.h"
module scbuf_fbd
(/*AUTOARG*/
// Outputs
so, sctag_scbuf_fbrd_en_c3_v1, sctag_scbuf_fbrd_en_c3_v2,
sctag_scbuf_fbrd_en_c3_v3, sctag_scbuf_fbrd_en_c3_v4,
sctag_scbuf_fbrd_wl_c3_v1, sctag_scbuf_fbrd_wl_c3_v2,
sctag_scbuf_fbrd_wl_c3_v3, sctag_scbuf_fbrd_wl_c3_v4,
sctag_scbuf_fbwr_wen_r3, sctag_scbuf_fbwr_wren_r3_v4,
sctag_scbuf_fbwr_wren_r3_v3, sctag_scbuf_fbwr_wren_r3_v2,
sctag_scbuf_fbwr_wren_r3_v1, sctag_scbuf_fbwr_wl_r3_v1,
sctag_scbuf_fbwr_wl_r3_v2, sctag_scbuf_fbwr_wl_r3_v3,
sctag_scbuf_fbwr_wl_r3_v4, fb_array_din,
// Inputs
rclk, se, si, sctag_scbuf_fbrd_en_c3,
sctag_scbuf_fbrd_wl_c3, sctag_scbuf_fbwr_wen_r2,
sctag_scbuf_fbwr_wl_r2, sctag_scbuf_fbd_stdatasel_c3,
sctag_scbuf_stdecc_c3, dram_scbuf_data_r2, dram_scbuf_ecc_r2
) ;
input rclk;
input se, si;
input sctag_scbuf_fbrd_en_c3;
input [2:0] sctag_scbuf_fbrd_wl_c3;
input [15:0] sctag_scbuf_fbwr_wen_r2; // dram Fill or store in OFF mode.
input [2:0] sctag_scbuf_fbwr_wl_r2; // dram Fill entry.
input sctag_scbuf_fbd_stdatasel_c3; // select store data in OFF mode
input [77:0] sctag_scbuf_stdecc_c3; // store data goes to scbuf and scdata
input [127:0] dram_scbuf_data_r2; // fill data.
input [27:0] dram_scbuf_ecc_r2; // fill ecc
output so;
output sctag_scbuf_fbrd_en_c3_v1;
output sctag_scbuf_fbrd_en_c3_v2;
output sctag_scbuf_fbrd_en_c3_v3;
output sctag_scbuf_fbrd_en_c3_v4;
output [2:0] sctag_scbuf_fbrd_wl_c3_v1;
output [2:0] sctag_scbuf_fbrd_wl_c3_v2;
output [2:0] sctag_scbuf_fbrd_wl_c3_v3;
output [2:0] sctag_scbuf_fbrd_wl_c3_v4;
output [15:0] sctag_scbuf_fbwr_wen_r3; // dram Fill or store in OFF mode.
output sctag_scbuf_fbwr_wren_r3_v4;
output sctag_scbuf_fbwr_wren_r3_v3;
output sctag_scbuf_fbwr_wren_r3_v2;
output sctag_scbuf_fbwr_wren_r3_v1;
output [2:0] sctag_scbuf_fbwr_wl_r3_v1; // dram Fill entry.
output [2:0] sctag_scbuf_fbwr_wl_r3_v2;
output [2:0] sctag_scbuf_fbwr_wl_r3_v3;
output [2:0] sctag_scbuf_fbwr_wl_r3_v4;
output [623:0] fb_array_din; // FB read data
wire [ 77:0] sctag_scdata_stdecc_c4;
wire [155:0] btu_scbuf_decc_r2, btu_scbuf_decc_r3;
wire [623:0] ram_decc;
wire [623:0] sctag_decc;
wire [2:0] sctag_scbuf_fbwr_wl_r3;
////////////////////////////////////////////////////////////////////////////////
assign sctag_scbuf_fbrd_en_c3_v1 = sctag_scbuf_fbrd_en_c3 ;
assign sctag_scbuf_fbrd_en_c3_v2 = sctag_scbuf_fbrd_en_c3 ;
assign sctag_scbuf_fbrd_en_c3_v3 = sctag_scbuf_fbrd_en_c3 ;
assign sctag_scbuf_fbrd_en_c3_v4 = sctag_scbuf_fbrd_en_c3 ;
assign sctag_scbuf_fbrd_wl_c3_v1[2:0] = sctag_scbuf_fbrd_wl_c3[2:0] ;
assign sctag_scbuf_fbrd_wl_c3_v2[2:0] = sctag_scbuf_fbrd_wl_c3[2:0] ;
assign sctag_scbuf_fbrd_wl_c3_v3[2:0] = sctag_scbuf_fbrd_wl_c3[2:0] ;
assign sctag_scbuf_fbrd_wl_c3_v4[2:0] = sctag_scbuf_fbrd_wl_c3[2:0] ;
dff_s #(16) ff_fbwr_wen_r3
(.q (sctag_scbuf_fbwr_wen_r3[15:0]),
.din (sctag_scbuf_fbwr_wen_r2[15:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()
) ;
assign sctag_scbuf_fbwr_wren_r3_v4 = (sctag_scbuf_fbwr_wen_r3[6] |
sctag_scbuf_fbwr_wen_r3[4] |
sctag_scbuf_fbwr_wen_r3[2] |
sctag_scbuf_fbwr_wen_r3[0]) ;
assign sctag_scbuf_fbwr_wren_r3_v3 = (sctag_scbuf_fbwr_wen_r3[7] |
sctag_scbuf_fbwr_wen_r3[5] |
sctag_scbuf_fbwr_wen_r3[3] |
sctag_scbuf_fbwr_wen_r3[1]) ;
assign sctag_scbuf_fbwr_wren_r3_v2 = (sctag_scbuf_fbwr_wen_r3[14] |
sctag_scbuf_fbwr_wen_r3[12] |
sctag_scbuf_fbwr_wen_r3[10] |
sctag_scbuf_fbwr_wen_r3[8]) ;
assign sctag_scbuf_fbwr_wren_r3_v1 = (sctag_scbuf_fbwr_wen_r3[15] |
sctag_scbuf_fbwr_wen_r3[13] |
sctag_scbuf_fbwr_wen_r3[11] |
sctag_scbuf_fbwr_wen_r3[9]) ;
dff_s #(3) ff_fbwr_wl_r3
(.q (sctag_scbuf_fbwr_wl_r3[2:0]),
.din (sctag_scbuf_fbwr_wl_r2[2:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()
) ;
assign sctag_scbuf_fbwr_wl_r3_v1[2:0] = sctag_scbuf_fbwr_wl_r3[2:0] ;
assign sctag_scbuf_fbwr_wl_r3_v2[2:0] = sctag_scbuf_fbwr_wl_r3[2:0] ;
assign sctag_scbuf_fbwr_wl_r3_v3[2:0] = sctag_scbuf_fbwr_wl_r3[2:0] ;
assign sctag_scbuf_fbwr_wl_r3_v4[2:0] = sctag_scbuf_fbwr_wl_r3[2:0] ;
dff_s #(78) ff_sctag_scdata_stdecc_c4
(.q (sctag_scdata_stdecc_c4[77:0]),
.din (sctag_scbuf_stdecc_c3[77:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()
) ;
assign sctag_decc = {8{sctag_scdata_stdecc_c4[77:0]}} ;
assign btu_scbuf_decc_r2 = {dram_scbuf_data_r2[127:96], dram_scbuf_ecc_r2[27:21],
dram_scbuf_data_r2[ 95:64], dram_scbuf_ecc_r2[20:14],
dram_scbuf_data_r2[ 63:32], dram_scbuf_ecc_r2[13: 7],
dram_scbuf_data_r2[ 31: 0], dram_scbuf_ecc_r2[ 6: 0]} ;
dff_s #(156) ff_btu_scbuf_decc_r3
(.q (btu_scbuf_decc_r3[155:0]),
.din (btu_scbuf_decc_r2[155:0]),
.clk (rclk),
.se (1'b0), .si (), .so ()
) ;
assign ram_decc = {4{btu_scbuf_decc_r3[155:0]}} ;
dff_s #(1) ff_fbd_stdatasel_c4
(.q (sctag_scbuf_fbd_stdatasel_c4),
.din (sctag_scbuf_fbd_stdatasel_c3),
.clk (rclk),
.se (1'b0), .si (), .so ()
) ;
mux2ds #(624) mux_fb_array_din
(.dout (fb_array_din[623:0]),
.in0 (ram_decc[623:0]), .sel0 (~sctag_scbuf_fbd_stdatasel_c4),
.in1 (sctag_decc[623:0]), .sel1 (sctag_scbuf_fbd_stdatasel_c4)
) ;
endmodule
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//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_onestate
(
clk,
rst,
is_sticky,
delay_valid,
delay_cycles,
pred_valid,
pred_match,
pred_index,
act_input,
act_output,
act_index
);
input clk;
input rst;
input is_sticky;
input pred_valid;
input pred_match;
input [15:0] pred_index;
input delay_valid;
input [3:0] delay_cycles;
input act_input;
output reg act_output;
output reg [15:0] act_index;
reg activated;
reg [3:0] delay_cycles_reg;
reg [2+15:0] delay_shift;
always @(posedge clk ) begin
if (delay_valid==1) delay_cycles_reg <= delay_cycles;
if (rst) begin
act_output <= 0;
activated <= 0;
end
else
begin
delay_shift <= {delay_shift[14:2],act_input,2'b00};
activated <= (delay_cycles_reg>1) ? delay_shift[delay_cycles_reg] : act_input;
if (pred_valid) begin
if ((delay_cycles_reg==0 && act_input==1) || (delay_cycles_reg!=0 && activated==1) && pred_match==1) begin
act_output <= pred_match;
if (act_output==0) act_index <= pred_index;
end
else begin
if (is_sticky) begin
act_output <= act_output;
end else begin
act_output <= 0;
end
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function
//SINGLE PRECISION PARAMETERS
/*# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
Sgf_Multiplication #(.SW(SW+1)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}),
.Data_B_i({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-10; int n, q, t; double plc[500005], ans[500005]; struct Point { long double x, y; Point() {} Point(long double _x, long double _y) { x = _x, y = _y; } Point operator+(Point p) { return Point(x + p.x, y + p.y); } } P[500005], Q[500005]; struct Node { long double x, m, c; int d; Node() {} Node(long double _x, long double _m, long double _c, int _d) { x = _x, m = _m, c = _c, d = _d; } bool operator<(const Node &p) const { return x < p.x; } } V[500005]; void Add(Point a, Point b, int v) { if (abs(b.x - a.x) < eps) return; if (a.x > b.x) { swap(a, b); v *= -1; } long double m = (b.y - a.y) / (b.x - a.x), c = a.y - a.x * m; V[++t] = Node(a.x, v * m, v * c, 0); V[++t] = Node(b.x, -v * m, -v * c, 0); return; } Point Calc(Point a, Point b, Point p) { return Point((b.x - a.x) * (p.y - a.y) / (b.y - a.y) + a.x, p.y); } int main() { scanf( %d%d , &n, &q); int p = 0; for (int i = 0; i < n; i++) { int x, y; scanf( %d%d , &x, &y); P[i] = Point(x, y); if (P[i].y < P[p].y) p = i; } for (int i = 1; i <= q; i++) { double x; scanf( %lf , &x); plc[i] = x; V[i] = Node(x, -1, -1, i); } t = q; long double all = 0; for (int i = 0; i < n; i++) { all += P[i].x * P[(i + 1) % n].y - P[(i + 1) % n].x * P[i].y; if (P[i].y < P[(i + 1) % n].y) Add(P[i], P[(i + 1) % n], -1); else Add(P[(i + 1) % n], P[i], -1); } all = abs(all / 2); int s = 0; for (int i = p; i < n; i++) Q[s++] = P[i]; for (int i = 0; i < p; i++) Q[s++] = P[i]; for (int i = 0; i < n; i++) P[i] = Q[i]; int lf = 0, rg = 0; Point lst = P[0]; for (int i = 0; i < n - 1; i++) { int L = (lf + 1) % n, R = (rg + n - 1) % n; Point now; if (P[L].y < P[R].y) { Point tmp = Calc(P[rg], P[R], P[L]) + P[L]; now.x = tmp.x * 0.5, now.y = tmp.y * 0.5; lf = L; } else { Point tmp = Calc(P[lf], P[L], P[R]) + P[R]; now.x = tmp.x * 0.5; now.y = tmp.y * 0.5; rg = R; } Add(lst, now, 2); lst = now; } sort(V + 1, V + t + 1); long double a = 0.0, b = 0.0; for (int i = 1; i <= t; i++) { long double x = V[i].x, m = V[i].m, c = V[i].c; if (V[i].d > 0) ans[V[i].d] = all + (0.5 * a * x * x + b * x); else { all -= 0.5 * m * x * x + c * x; a += m, b += c; } } for (int i = 1; i <= q; i++) printf( %.10lf n , (double)ans[i]); }
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// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_sld_node (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter TCK_FREQ_MHZ = 20;
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
localparam IRWIDTH = 3;
input [IRWIDTH - 1:0] ir_out;
input tdo;
output reg [IRWIDTH - 1:0] ir_in;
output tck;
output reg tdi = 1'b0;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
// PHY Simulation signals
`ifndef ALTERA_RESERVED_QIS
reg simulation_clock;
reg sdrs;
reg cdr;
reg sdr;
reg e1dr;
reg udr;
reg [7:0] bit_index;
`endif
// PHY Instantiation
`ifdef ALTERA_RESERVED_QIS
sld_virtual_jtag_basic sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.tdi (tdi),
.tck (tck),
.ir_in (ir_in),
.virtual_state_cir (virtual_state_cir),
.virtual_state_pdr (virtual_state_pdr),
.virtual_state_uir (virtual_state_uir),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_e1dr (virtual_state_e1dr),
.virtual_state_e2dr (virtual_state_e2dr)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_mfg_id = 110,
sld_virtual_jtag_component.sld_type_id = 132,
sld_virtual_jtag_component.sld_version = 1,
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
sld_virtual_jtag_component.sld_sim_action = "",
sld_virtual_jtag_component.sld_sim_n_scan = 0,
sld_virtual_jtag_component.sld_sim_total_length = 0;
`endif
// PHY Simulation
`ifndef ALTERA_RESERVED_QIS
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
always
//#TCK_HALF_PERIOD_US simulation_clock = $random;
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
assign tck = simulation_clock;
assign virtual_state_cdr = cdr;
assign virtual_state_sdr = sdr;
assign virtual_state_e1dr = e1dr;
assign virtual_state_udr = udr;
task reset_jtag_state;
begin
simulation_clock = 0;
enter_data_mode;
clear_states_async;
end
endtask
task enter_data_mode;
begin
ir_in = DATA;
clear_states;
end
endtask
task enter_loopback_mode;
begin
ir_in = LOOPBACK;
clear_states;
end
endtask
task enter_debug_mode;
begin
ir_in = DEBUG;
clear_states;
end
endtask
task enter_info_mode;
begin
ir_in = INFO;
clear_states;
end
endtask
task enter_control_mode;
begin
ir_in = CONTROL;
clear_states;
end
endtask
task enter_mgmt_mode;
begin
ir_in = MGMT;
clear_states;
end
endtask
task enter_sdrs_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_cdr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_e1dr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_udr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
tdi = 1'b0;
@(posedge tck);
end
endtask
task clear_states;
begin
clear_states_async;
@(posedge tck);
end
endtask
task clear_states_async;
begin
{cdr, sdr, e1dr, udr} = 4'b0000;
end
endtask
task shift_one_bit;
input bit_to_send;
output reg bit_received;
begin
{cdr, sdr, e1dr, udr} = 4'b0100;
tdi = bit_to_send;
@(posedge tck);
bit_received = tdo;
end
endtask
task shift_one_byte;
input [7:0] byte_to_send;
output reg [7:0] byte_received;
integer i;
reg bit_received;
begin
for (i=0; i<8; i=i+1)
begin
bit_index = i;
shift_one_bit(byte_to_send[i], bit_received);
byte_received[i] = bit_received;
end
end
endtask
`endif
endmodule
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#include <bits/stdc++.h> using namespace std; const long long inf = 1LL << 28; const long long mod = 1LL; int arr[3 * 100010]; int main() { int n, k, i, ans, flag, j; while (scanf( %d %d , &n, &k) == 2) { for (i = 0; i < n; i++) { scanf( %d , &arr[i]); } sort(arr, arr + n); ans = arr[0]; while (true) { flag = true; for (i = 0; i < n; i++) { if (arr[i] % ans <= k) continue; flag = false; j = arr[i] / ans; j++; ans = arr[i] / j; } if (flag) break; } printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; string s; for (int i = 0; i < t; i++) { cin >> n; cin >> s; int k = 0; if (n % 2 == 0) { for (int i = 1; i < n; i += 2) if ((int(s[i]) - 48) % 2 == 0) { k = 1; cout << 2 << n ; break; } if (k == 0) cout << 1 << n ; } if (n % 2 == 1) { for (int i = 0; i < n; i += 2) if ((int(s[i]) - 48) % 2 == 1) { k = 1; cout << 1 << n ; break; } if (k == 0) cout << 2 << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const long long linf = (long long)1e18; const double eps = (double)1e-8; const int mod = (int)1e9 + 7; const int maxn = (int)3e5 + 5; int n, m; vector<int> a[maxn]; int fl; int c[maxn]; vector<int> ta, tb; set<pair<int, int> > roads; int equals(int v, int u) { ta.clear(); tb.clear(); if (a[v].size() != a[u].size()) return 0; for (int i = (0); i < (int)(a[v].size()); ++i) { if (a[v][i] == u) continue; ta.push_back(a[v][i]); } for (int i = (0); i < (int)(a[u].size()); ++i) { if (a[u][i] == v) continue; tb.push_back(a[u][i]); } if (ta.size() != tb.size()) return 0; for (int i = (0); i < (int)(ta.size()); ++i) { if (ta[i] != tb[i]) return 0; } return 1; } void dfs(int v, int pl) { int cnt = 0; for (int i = (0); i < (int)(a[v].size()); ++i) { int to; to = a[v][i]; if (c[to] != inf) { if (abs(c[v] - c[to]) > 1) { fl = 0; return; } continue; } if (equals(to, v)) { c[to] = c[v]; continue; } } for (int i = (0); i < (int)(a[v].size()); ++i) { int to; to = a[v][i]; if (c[to] != inf) { if (abs(c[v] - c[to]) > 1) { fl = 0; return; } continue; } ++cnt; if (cnt >= 2) { fl = 0; break; } c[to] = c[v] + pl; dfs(to, pl); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = (1); i <= (int)(m); ++i) { int x, y; cin >> x >> y; if (x > y) swap(x, y); if (x == y || roads.count(make_pair(x, y))) continue; roads.insert(make_pair(x, y)); a[x].push_back(y); a[y].push_back(x); } for (int i = (1); i <= (int)(n); ++i) { c[i] = inf; sort(a[i].begin(), a[i].end()); } int st, pl[2], upl; st = 1; pl[0] = 1; pl[1] = -1; upl = 0; c[st] = 0; fl = 1; for (int i = (0); i < (int)(a[st].size()); ++i) { int to; to = a[st][i]; if (c[to] != inf) { if (abs(c[st] - c[to]) > 1) { fl = 0; break; } continue; } if (equals(st, to)) { c[to] = c[st]; continue; } } for (int i = (0); i < (int)(a[st].size()); ++i) { int to; to = a[st][i]; if (c[to] != inf) { if (abs(c[st] - c[to]) > 1) { fl = 0; break; } continue; } if (upl == 2) { fl = 0; break; } c[to] = pl[upl]; dfs(to, pl[upl]); ++upl; } if (!fl) { cout << NO << n ; return 0; } int mn = 0; for (int i = (1); i <= (int)(n); ++i) { mn = min(mn, c[i]); } cout << YES << n ; for (int i = (1); i <= (int)(n); ++i) { cout << c[i] - mn + 1 << ; } cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 200100; const long long OO = 1e18; const int oo = 2e9; const int md = 998244353; set<int> st; set<int>::iterator ite; int sto, n, p[N], obr = 1, ans = 0, mul[N], q, psm[N]; bool mrk[N]; int mult(int x, int y) { return (1ll * x * y) % md; } int sum(int x, int y) { x += y; if (x >= md) x -= md; return x; } int sub(int x, int y) { x -= y; if (x < 0) x += md; return x; } int binpow(int x, int po) { int res = 1; while (po > 0) { if (po & 1) res = mult(res, x); x = mult(x, x); po >>= 1; } return res; } int calc(int l, int r) { int up = sub(psm[r - 1], (l - 2 < 0 ? 0 : psm[l - 2])); up = mult(up, binpow(mul[l - 1], md - 2)); int down = mult(mul[r], binpow(mul[l - 1], md - 2)); return mult(up, binpow(down, md - 2)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> q; sto = binpow(100, md - 2); mul[0] = 1; mrk[1] = 1; psm[0] = 1; for (int i = 1; i <= n; i++) { cin >> p[i]; p[i] = mult(p[i], sto); mul[i] = mult(mul[i - 1], p[i]); psm[i] = sum(psm[i - 1], mul[i]); } ans = calc(1, n); st.clear(); st.insert(1); st.insert(n + 1); for (; q; q--) { int ps; cin >> ps; if (!mrk[ps]) { st.insert(ps); ite = st.find(ps); int lf = *prev(ite); int rt = (*next(ite)) - 1; ans = sub(ans, calc(lf, rt)); ans = sum(ans, calc(lf, ps - 1)); ans = sum(ans, calc(ps, rt)); } else { ite = st.find(ps); int lf = *prev(ite); int rt = (*next(ite)) - 1; ans = sum(ans, calc(lf, rt)); ans = sub(ans, calc(lf, ps - 1)); ans = sub(ans, calc(ps, rt)); st.erase(ite); } mrk[ps] ^= 1; cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int order[3][4] = {{0, 1, 2, 3}, {0, 2, 3, 1}, {0, 3, 1, 2}}; long long solve(long long n) { long long four = 1; while (four * 4 <= n) { four *= 4; } int part = (n - 1) % 3; n -= four; n /= 3; long long res = four * (part + 1); while (n > 0) { res += order[part][n / four] * four; n %= four; four /= 4; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tc; long long n; cin >> tc; while (tc--) { cin >> n; long long ans = solve(n); cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long x; int n, d; int res[100010], a[100010], b[100010]; long long getNextX() { x = (x * 37 + 10007) % 1000000007; return x; } void initab() { for (int i = 0; i < n; i++) { a[i] = i + 1; } for (int i = 0; i < n; i++) { swap(a[i], a[getNextX() % (i + 1)]); } for (int i = 0; i < n; i++) { if (i < d) b[i] = 1; else b[i] = 0; } for (int i = 0; i < n; i++) { swap(b[i], b[getNextX() % (i + 1)]); } } void sol1() { for (int i = 0; i < n; i++) if (b[i]) { for (int j = i; j < n; j++) if (res[j] < a[j - i]) res[j] = a[j - i]; } } void sol2() { int k = n - sqrt(n); for (int i = 0; i < n; i++) if (a[i] >= k) { int l = n - i; for (int j = 0; j < l; j++) if (b[j] && res[j + i] < a[i]) res[j + i] = a[i]; } for (int i = 0; i < n; i++) if (!res[i]) { for (int j = 0; j <= i; j++) if (b[i - j] && res[i] < a[j]) res[i] = a[j]; } } int main() { cin >> n >> d >> x; initab(); int sd = sqrt(n) * 4; if (d <= sd) sol1(); else sol2(); for (int i = 0; i < n; i++) printf( %d n , res[i]); }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; int main() { int arr[4]; int t = 0; int s = 0; for (int i = 0; i < 4; i++) cin >> arr[i]; for (int m = 0; m < 4; m++) { for (int j = 0; j < 4; j++) { for (int k = 0; k < 4; k++) { if (arr[m] < arr[j] + arr[k] && arr[j] < arr[m] + arr[k] && arr[k] < arr[m] + arr[j] && m != j && j != k && k != m) { t += 1; } else if (arr[m] == arr[j] + arr[k] && m != j && j != k && k != m) { s += 1; } } } } if (t == 0 && s != 0) cout << SEGMENT ; else if (t != 0) cout << TRIANGLE ; else if (t == 0 && s == 0) cout << IMPOSSIBLE ; return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { int to, u, w; } edge[200000]; struct data { int x, y, w, d; } v[200010]; int k = 1, f[200000], low[200010], dfu[200010], n, m, ans[200010], head[200010], cnt, l; bool vis[200010]; void add(int x, int y, int z) { edge[k].u = y; edge[k].to = head[x]; edge[k].w = z; head[x] = k++; } int getfather(int x) { if (f[x] == x) return x; f[x] = getfather(f[x]); return f[x]; } void dfs(int now, int from) { low[now] = dfu[now] = cnt++; vis[now] = 1; for (int i = head[now]; i != -1; i = edge[i].to) { int u = edge[i].u; if (vis[u] == 1 && edge[i].w != from) low[now] = min(low[now], dfu[u]); else if (vis[u] != 1) { dfs(u, edge[i].w); low[now] = min(low[now], low[u]); if (dfu[now] < low[u]) ans[edge[i].w] = 2; } } } void add(int x, int y) { int xx = getfather(x); int yy = getfather(y); if (xx != yy) { dfu[x] = dfu[y] = dfu[xx] = dfu[yy] = 0; low[x] = low[y] = low[xx] = low[yy] = 0; vis[x] = vis[y] = vis[xx] = vis[yy] = 0; head[x] = head[y] = head[xx] = head[yy] = -1; f[xx] = yy; } } bool comp(data x, data y) { return x.w < y.w; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &v[i].x, &v[i].y, &v[i].w); v[i].d = i; } sort(v + 1, v + m + 1, comp); memset(head, -1, sizeof(head)); for (int i = 1; i <= n; i++) f[i] = i; l = 1; for (int i = 1; i <= m; i++) if (v[i].w != v[i + 1].w) { for (int j = l; j <= i; j++) { int xx = getfather(v[j].x); int yy = getfather(v[j].y); if (xx == yy) { ans[v[j].d] = 1; } else { add(xx, yy, v[j].d); add(yy, xx, v[j].d); } } for (int j = l; j <= i; j++) { int xx = getfather(v[j].x); int yy = getfather(v[j].y); if (xx != yy && vis[xx] == 0) dfs(xx, -1); if (xx != yy && vis[yy] == 0) dfs(yy, -1); } for (int j = l; j <= i; j++) { add(v[j].x, v[j].y); } l = i + 1; } for (int i = 1; i <= m; i++) if (ans[i] == 1) printf( %s n , none ); else if (ans[i] == 0) printf( %s n , at least one ); else printf( %s n , any ); }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); int maxar(int arr[], int n) { int res = arr[0]; for (int i = 0; i < n; i++) { res = max(res, arr[i]); } return res; } long long maxar(long long arr[], long long n) { long long res = arr[0]; for (long long i = 0; i < n; i++) { res = max(res, arr[i]); } return res; } long long minar(long long arr[], long long n) { long long res = arr[0]; for (long long i = 0; i < n; i++) { res = min(res, arr[i]); } return res; } int minar(int arr[], int n) { int res = arr[0]; for (int i = 0; i < n; i++) { res = min(res, arr[i]); } return res; } void inpar(int arr[], int n) { for (int i = 0; i < n; i++) { cin >> arr[i]; } } void inpar(long long arr[], long long n) { for (long long i = 0; i < n; i++) { cin >> arr[i]; } } template <typename T> inline T readInt() { T n = 0, s = 1; char p = getchar(); if (p == - ) s = -1; while ((p < 0 || p > 9 ) && p != EOF && p != - ) p = getchar(); if (p == - ) s = -1, p = getchar(); while (p >= 0 && p <= 9 ) { n = (n << 3) + (n << 1) + (p - 0 ); p = getchar(); } return n * s; } void solve() { int n = readInt<int>(); int a[n]; inpar(a, n); int res = 0; priority_queue<int> q; for (int i = 1; i < n; i++) { q.push(a[i]); } while (q.top() >= a[0]) { res++; a[0]++; int temp = q.top(); temp--; q.pop(); q.push(temp); } cout << res; } int32_t main() { int tc; tc = 1; while (tc--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:19:34 03/05/2017
// Design Name:
// Module Name: MUX32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX32(
input [31:0] in,
input [4:0] sel,
output out
);
wire [16:0] A;
wire [7:0] B;
wire [3:0] C;
wire [1:0] D;
generate
genvar i,j,k,l;
for (i=0; i < 16; i=i+1) begin: m0
MUX2 m(in[2*i+1:2*i], sel[0] , A[i]);
end
for (l=0; l < 8; l=l+1) begin: m1
MUX2 m(A[2*l+1:2*l], sel[1] , B[l]);
end
for (j=0; j < 4; j=j+1) begin: m2
MUX2 m(B[2*j+1:2*j], sel[2] , C[j]);
end
for (k=0; k < 2; k=k+1) begin: m3
MUX2 m(C[2*k+1:2*k], sel[3] , D[k]);
end
endgenerate
MUX2 m4(D, sel[4] , out);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_SHARED_CODE
reg window = 0;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (!window && start_event == 1'b1)
window <= 1'b1;
else if (window && end_event == 1'b1)
window <= 1'b0;
end
else begin
window <= 1'b0;
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
wire xzdetect_test_expr;
assign xzdetect_test_expr = ((^test_expr) ^ (^test_expr) == 1'b0);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_win_change_assert #(
.width(width))
assert_win_change_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.test_expr(test_expr),
.window(window),
.xzdetect_test_expr(xzdetect_test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_win_change_assume #(
.width(width))
assert_win_change_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.test_expr(test_expr),
.window(window),
.xzdetect_test_expr(xzdetect_test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_win_change_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_win_change_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.end_event(end_event),
.window(window));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_win_change.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_win_change_assert (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_win_change_assume (clk, reset_n, start_event, end_event, test_expr, window,
xzdetect_test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n, start_event, end_event, window;
input [width-1:0] test_expr;
input xzdetect_test_expr, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_win_change_cover (clk, reset_n, start_event, end_event, window);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, start_event, end_event, window;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int32_t M = 1e9 + 7; const int32_t MM = 998244353; long long m, n; void solve() { cin >> n >> m; bool visited[n + 5]; memset(visited, 0, sizeof(visited)); for (long long i = 0; i < m; i++) { long long a, b, c; cin >> a >> b >> c; visited[b] = 1; } long long node = -1; for (long long i = 1; i < n + 1; i++) if (!visited[i]) { node = i; break; } for (long long i = 1; i < n + 1; i++) { if (i == node) continue; cout << node << << i << n ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:49:40 01/18/2017
// Design Name: right_barrel_shifter
// Module Name: /home/aaron/Git Repos/CSE311/lab1/right_barrel_shifter_tb.v
// Project Name: lab1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: right_barrel_shifter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module right_barrel_shifter_tb;
// Inputs
reg [7:0] d_in;
reg [2:0] shift_amount;
// Outputs
wire [7:0] d_out;
// Instantiate the Unit Under Test (UUT)
right_barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
// Initialize Inputs
d_in = 0;
shift_amount = 0;
// Wait 100 ns for global reset to finish
#100;
// Test to shift right by 1
d_in = 8'b00000001;
shift_amount = 1'd1;
#100;
// New Test for shift right by 2
d_in = 8'b10000000;
shift_amount = 3'b010;
#100;
// Final Test to shift right by 4
d_in = 8'b00010000;
shift_amount = 3'b100;
end
endmodule
|
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
module VTAHostDPI #
( parameter ADDR_BITS = 8,
parameter DATA_BITS = 32
)
(
input clock,
input reset,
output logic dpi_req_valid,
output logic dpi_req_opcode,
output logic [ADDR_BITS-1:0] dpi_req_addr,
output logic [DATA_BITS-1:0] dpi_req_value,
input dpi_req_deq,
input dpi_resp_valid,
input [DATA_BITS-1:0] dpi_resp_bits
);
import "DPI-C" function void VTAHostDPI
(
output byte unsigned req_valid,
output byte unsigned req_opcode,
output byte unsigned req_addr,
output int unsigned req_value,
input byte unsigned req_deq,
input byte unsigned resp_valid,
input int unsigned resp_value
);
typedef logic dpi1_t;
typedef logic [7:0] dpi8_t;
typedef logic [31:0] dpi32_t;
dpi1_t __reset;
dpi8_t __req_valid;
dpi8_t __req_opcode;
dpi8_t __req_addr;
dpi32_t __req_value;
dpi8_t __req_deq;
dpi8_t __resp_valid;
dpi32_t __resp_bits;
// reset
always_ff @(posedge clock) begin
__reset <= reset;
end
// delaying outputs by one-cycle
// since verilator does not support delays
always_ff @(posedge clock) begin
dpi_req_valid <= dpi1_t ' (__req_valid);
dpi_req_opcode <= dpi1_t ' (__req_opcode);
dpi_req_addr <= __req_addr;
dpi_req_value <= __req_value;
end
assign __req_deq = dpi8_t ' (dpi_req_deq);
assign __resp_valid = dpi8_t ' (dpi_resp_valid);
assign __resp_bits = dpi_resp_bits;
// evaluate DPI function
always_ff @(posedge clock) begin
if (reset | __reset) begin
__req_valid = 0;
__req_opcode = 0;
__req_addr = 0;
__req_value = 0;
end
else begin
VTAHostDPI(
__req_valid,
__req_opcode,
__req_addr,
__req_value,
__req_deq,
__resp_valid,
__resp_bits);
end
end
endmodule
|
/********************************************/
/* qmem_bridge.v */
/* QMEM 32-to-16 bit async bridge */
/* */
/* 2013, */
/********************************************/
module qmem_bridge #(
parameter MAW = 22,
parameter MSW = 4,
parameter MDW = 32,
parameter SAW = 22,
parameter SSW = 2,
parameter SDW = 16
)(
// master
input wire m_clk,
input wire [MAW-1:0] m_adr,
input wire m_cs,
input wire m_we,
input wire [MSW-1:0] m_sel,
input wire [MDW-1:0] m_dat_w,
output reg [MDW-1:0] m_dat_r,
output reg m_ack = 1'b0,
output wire m_err,
// slave
input wire s_clk,
output reg [SAW-1:0] s_adr,
output reg s_cs,
output reg s_we,
output reg [SSW-1:0] s_sel,
output reg [SDW-1:0] s_dat_w,
input wire [SDW-1:0] s_dat_r,
input wire s_ack,
input wire s_err
);
// sync master cs
reg [ 3-1:0] cs_sync = 3'b000;
always @ (posedge s_clk) cs_sync <= #1 {cs_sync[1:0], m_cs};
// detect master cs posedge
wire cs_posedge;
assign cs_posedge = cs_sync[1] && !cs_sync[2];
// latch master data
reg [MAW-1:0] adr_d = {MAW{1'b0}};
reg we_d = 1'b0;
reg [MSW-1:0] sel_d = {MSW{1'b0}};
reg [MDW-1:0] dat_w_d = {MDW{1'b0}};
always @ (posedge s_clk) begin
if (cs_sync[1]) begin
adr_d <= #1 m_adr;
we_d <= #1 m_we;
sel_d <= #1 m_sel;
dat_w_d <= #1 m_dat_w;
end
end
// output state machine
reg [ 3-1:0] state = 3'b000;
localparam ST_IDLE = 3'b000;
localparam ST_U_SETUP = 3'b010;
localparam ST_U_WAIT = 3'b011;
localparam ST_L_SETUP = 3'b100;
localparam ST_L_WAIT = 3'b101;
localparam ST_A_WAIT = 3'b111;
reg [ 2-1:0] s_ack_sync = 2'b00;
reg done = 1'b0;
always @ (posedge s_clk) begin
case (state)
ST_IDLE : begin
if (cs_sync[2]) begin
state <= #1 ST_U_SETUP;
end
end
ST_U_SETUP : begin
s_cs <= #1 1'b1;
s_adr <= #1 {adr_d[22-1:2], 1'b0, 1'b0};
s_sel <= #1 sel_d[3:2];
s_we <= #1 we_d;
s_dat_w <= #1 dat_w_d[31:16];
state <= #1 ST_U_WAIT;
end
ST_U_WAIT : begin
if (s_ack) begin
s_cs <= #1 1'b0;
m_dat_r[31:16] <= #1 s_dat_r;
state <= #1 ST_L_SETUP;
end
end
ST_L_SETUP : begin
s_cs <= #1 1'b1;
s_adr <= #1 {adr_d[22-1:2], 1'b1, 1'b0};
s_sel <= #1 sel_d[1:0];
s_we <= #1 we_d;
s_dat_w <= #1 dat_w_d[15:0];
state <= #1 ST_L_WAIT;
end
ST_L_WAIT : begin
if (s_ack) begin
s_cs <= #1 1'b0;
m_dat_r[15: 0] <= #1 s_dat_r;
done <= #1 1'b1;
state <= #1 ST_A_WAIT;
end
end
ST_A_WAIT : begin
if (s_ack_sync[1]) begin
done <= #1 1'b0;
state <= #1 ST_IDLE;
end
end
endcase
end
// master ack
reg [ 3-1:0] m_ack_sync = 3'b000;
always @ (posedge m_clk) begin
m_ack_sync <= #1 {m_ack_sync[1:0], done};
end
wire m_ack_posedge;
assign m_ack_posedge = m_ack_sync[1] && !m_ack_sync[2];
always @ (posedge m_clk) begin
if (m_ack_posedge) m_ack <= #1 1'b1;
else if (m_ack) m_ack <= #1 1'b0;
end
always @ (posedge s_clk) begin
s_ack_sync <= #1 {s_ack_sync[0], m_ack_sync[2]};
end
// master err
assign m_err = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2e9 + 10; const int MOD = 1e9 + 7; const int N = 1e6 + 10; int n, k, m; string x, y, z; int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); cin >> x >> y; n = x.length(); int ans = 1; for (int i = 0; i < n; i++) { if (y[i] > x[i]) { cout << -1; return 0; } z += min(x[i], y[i]); } cout << z; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> tree[2010]; int cs[2010], ps[2010]; int numDesc(int node) { int descendants = 0; for (int x : tree[node]) { descendants += 1 + numDesc(x); } if (descendants < cs[node]) return 10000; return descendants; } void solve(int node, vector<int>& order) { ps[node] = order[cs[node]]; order.erase(order.begin() + cs[node]); for (int x : tree[node]) solve(x, order); } int main() { int n; cin >> n; int root; for (int i = 1; i <= n; i++) { int p, c; cin >> p >> c; cs[i] = c; if (p == 0) { root = i; continue; } tree[p].push_back(i); } if (numDesc(root) > 5000) cout << NO ; else { vector<int> order(n); order[0] = 1; for (int i = 1; i < n; i++) order[i] = order[i - 1] + 1; solve(root, order); cout << YES n ; for (int i = 1; i < n; i++) cout << ps[i] << ; cout << ps[n]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 151; const int inf = 0x7f7f7f7f; const int mod = (int)(1e9 + 7); const long long INF = 0x7f7f7f7f7f7f7f7fLL; const double eps = 1e-8; const double pi = acos(-1.0); const int mask = 65535; int a[maxn]; int b[maxn]; void handle(int a[], int n) { if (n == 1) { a[0] = 1; return; } if (n == 2) { a[0] = 3; a[1] = 4; return; } if (n & 1) { std::fill(a, a + maxn, 1); a[0] = 2; a[n - 1] = (n + 1) >> 1; } else { std::fill(a, a + maxn, 1); a[n - 1] = (n - 1) >> 1; } } int main() { ios::sync_with_stdio(false); int n, m; int i, j; cin >> n >> m; handle(a, n); handle(b, m); for (i = 0; i < n; ++i) { for (j = 0; j < m; ++j) { if (j) cout << ; cout << a[i] * b[j]; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; bool used[n]; for (int i = 0; i <= n - 1; i++) used[i] = false; int a = 0, b = n - 1; for (int i = 0; i <= k - 1; i++) { if (i & 1) used[b] = true; else used[a] = true; if (i & 1) cout << (1 + (b--)); else cout << (1 + (a++)); cout << ; } if (k & 1) { for (int i = 0; i <= n - 1; i++) { if (!used[i]) { cout << i + 1 << ; } } } else { for (int i = n - 1; i >= 0; --i) { if (!used[i]) { cout << i + 1 << ; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_1_V
`define SKY130_FD_SC_MS__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_1_V
|
#include <bits/stdc++.h> using namespace std; int a[200001]; bool b[200001]; int main() { string s1, s2; int n, i; cin >> s1 >> s2; n = s1.size(); for (i = 1; i <= n; i++) cin >> a[i]; int l, r, mid, pr = 0, j; l = 0; r = n; while (l != r) { mid = (l + r + 1) / 2; for (i = 0; i <= n; i++) b[i] = 1; for (i = 1; i <= mid; i++) b[a[i] - 1] = 0; j = 0; for (i = 0; i < n && j < s2.size(); i++) { if (b[i]) { if (s1[i] == s2[j]) j++; } } if (j == s2.size()) l = mid; else r = mid - 1; } cout << l << endl; return 0; }
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The module is to control the mask ROM
//
// ====================================================================
module sirv_mrom_top #(
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
// * Bus cmd channel
input rom_icb_cmd_valid, // Handshake valid
output rom_icb_cmd_ready, // Handshake ready
input [AW-1:0] rom_icb_cmd_addr, // Bus transaction start addr
input rom_icb_cmd_read, // Read or write
// * Bus RSP channel
output rom_icb_rsp_valid, // Response valid
input rom_icb_rsp_ready, // Response ready
output rom_icb_rsp_err, // Response error
output [DW-1:0] rom_icb_rsp_rdata,
input clk,
input rst_n
);
wire [DW-1:0] rom_dout;
assign rom_icb_rsp_valid = rom_icb_cmd_valid;
assign rom_icb_cmd_ready = rom_icb_rsp_ready;
assign rom_icb_rsp_err = ~rom_icb_cmd_read;
assign rom_icb_rsp_rdata = rom_dout;
sirv_mrom # (
.AW(AW),
.DW(DW),
.DP(DP)
)u_sirv_mrom (
.rom_addr (rom_icb_cmd_addr[AW-1:2]),
.rom_dout (rom_dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; int arr[N][N], n; vector<int> adj[N], revAdj[N]; bool visited[N]; vector<int> vec; void dfs(int v) { visited[v] = 1; for (auto i : revAdj[v]) if (!visited[i]) dfs(i); vec.push_back(v); } void dfs2(int v) { visited[v] = 1; for (auto i : adj[v]) if (!visited[i]) dfs2(i); } void func() { cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cin >> arr[i][j]; if (arr[i][j]) arr[i][j] = 1; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (j != i && arr[i][j]) { revAdj[j].push_back(i); adj[i].push_back(j); } } } for (int i = 1; i <= n; i++) if (!visited[i]) dfs(i); reverse(vec.begin(), vec.end()); for (int i = 1; i <= n; i++) visited[i] = 0; int cnt = 0; for (int i = 0; i < n; i++) { if (!visited[vec[i]]) { cnt++; if (cnt > 1) { cout << NO n ; return; } dfs2(vec[i]); } } cout << YES n ; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int ntc = 1; for (int i = 1; i <= ntc; i++) { func(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, num, maxs = INT_MIN, mins = INT_MAX, mins2 = INT_MAX; cin >> n >> m; vector<int> v1; vector<int> v2; for (int i = 0; i < n; i++) { cin >> num; v1.push_back(num); maxs = max(maxs, num); mins2 = min(mins2, num); } for (int i = 0; i < m; i++) { cin >> num; v2.push_back(num); if (num <= maxs) { cout << -1 ; return 0; } mins = min(mins, num); } for (int i = 0; i < n; i++) { if (2 * v1[i] <= maxs) { cout << maxs; return 0; } } for (int i = 0; i < n; i++) { if (2 * mins2 <= mins - 1) { cout << 2 * mins2; return 0; } if (2 * v1[i] <= mins - 1) { cout << mins - 1; return 0; } } cout << -1 ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_TB_V
`define SKY130_FD_SC_HDLL__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_hdll__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { string x; cin >> x; long long step[101]; step[0] = 1; for (int i = 1; i < 101; i++) step[i] = (step[i - 1] * 2) % ((int)1e9 + 7); long long ans = 0; for (int i = 0; i < x.size(); i++) if (x[i] == 1 ) ans = (ans + step[x.size() - i - 1]) % ((int)1e9 + 7); for (int i = 0; i < x.size() - 1; i++) ans = (ans * 2) % ((int)1e9 + 7); cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_4_V
`define SKY130_FD_SC_MS__O41A_4_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_4_V
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Memory Controller Host Interface
// File : mc_hst.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// Receives requests from the HBI block in the form of a active high hst_req
// signal. Requests will only be made when our hst_rdy output is asserted
// high. Address, read (data directions), and page count are captured with
// the request. They are then brought across the clock domains to mclock by
// the synchronized request signal. Once in mclock domain, the request is
// made to the RAM arbiter.
//
// In other interface modules, address translation may occur as part of the
// clock domain crossing, but we are already given a linear address from the
// host bus so no extra translation is necessary. Also in other interfaces,
// request may be of up to 32 pages. Requests to the RAM arbiter may only be
// 4 pages, read or write, so large request must be broken up. The HBI only
// ever requests 1 or 2 page writes and 4 page reads, so we don't have to
// break things up, although we must mask out read data so garbage doesn't
// get written for the unused write cycles.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_hst
(
input mclock,
input reset_n,
input hst_clock,
input hst_gnt, // Grant back from arbiter
input [22:0] hst_org, // Address for HBI request
input hst_read, // Read/write select for HBI request
input hst_req, // Request from HBI (sync to hst_clock)
input rc_push_en,
input rc_pop_en, /* Should also add a select bus so I know
who the push or pop is for. */
output reg [22:0] hst_arb_addr, // MC internal address to arbiter
output reg hst_pop, // Data increment for write data from HBI
output reg hst_push, // Write enable for read data back to HBI
output reg hst_rdy, /* Ready flag must be asserted before HBI
sends request */
output reg [1:0] hst_mw_addr, // The address to read from MW
output reg [1:0] hst_arb_page, // MC internal page count to arbiter
output reg hst_arb_read, // MC internal r/w select to arbiter
output hst_arb_req // MC internal request to arbiter
);
reg [22:0] capt_addr[1:0];
reg [1:0] capt_read;
reg input_select, output_select, capt_select;
reg [1:0] req_sync_1, req_sync_2, req_sync_3;
reg [1:0] hst_push_cnt;
reg [1:0] busy;
reg [1:0] clear_busy;
reg [1:0] clear_busy0;
reg [1:0] clear_busy1;
reg [1:0] avail_mc;
reg final_select;
reg [1:0] hst_arb_req_int;
assign hst_arb_req = |hst_arb_req_int;
// Implement asynchronous interface and capture registers.
// This process should be the only things that runs on hst_clock.
// It captures the request on hst_clock and generates synchronization logic
// to get back to hst_clock domain. It also generates the ready flag
always @ (posedge hst_clock or negedge reset_n) begin
if(!reset_n) begin
input_select <= 1'b0;
hst_rdy <= 1'b1;
capt_addr[0] <= 23'b0;
capt_addr[1] <= 23'b0;
capt_read <= 2'b0;
busy <= 2'b0;
clear_busy0 <= 2'b0;
clear_busy1 <= 2'b0;
end else begin // if (!reset_n)
clear_busy0 <= clear_busy;
clear_busy1 <= clear_busy0;
hst_rdy <= ~&busy;
// If we detect an edge on either clear, then clear the busy flag
if (clear_busy1[0] ^ clear_busy0[0]) busy[0] <= 1'b0;
if (clear_busy1[1] ^ clear_busy0[1]) busy[1] <= 1'b0;
// Capture registers grab necessary data whenever a new request is made
if (hst_req && ~&busy) begin
input_select <= ~input_select;
busy[input_select] <= 1'b1;
capt_addr[input_select] <= hst_org;
capt_read[input_select] <= hst_read;
hst_rdy <= 1'b0;
end
end // else: !if(!reset_n)
end // always @ (posedge hst_clock)
// This is the main mclock domain process.
// It implements synchronizers to move the request from hst_clock over to
// mclock domain. It also has all the mclock capture registers that forward
// the request on to the arbiter.
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
hst_arb_req_int<= 1'b0;
req_sync_1 <= 2'b0;
req_sync_2 <= 2'b0;
req_sync_3 <= 2'b0;
avail_mc <= 2'b0;
capt_select <= 1'b0;
output_select <= 1'b0;
clear_busy <= 2'b0;
final_select <= 1'b0;
end else begin
// Triple register the request toggle for clock synchronization
req_sync_1 <= busy;
req_sync_2 <= req_sync_1;
req_sync_3 <= req_sync_2;
if (~req_sync_3[0] && req_sync_2[0]) avail_mc[0] <= 1'b1;
if (~req_sync_3[1] && req_sync_2[1]) avail_mc[1] <= 1'b1;
// A rising or falling transition on the synchronized request toggle
// indicates a new request is in the capture registers. In that case it
// is moved to the arbiter request registers and the request signal to
// the arbiter is asserted.
if (avail_mc[output_select]) begin
// make a new request to the arbiter
output_select <= ~output_select;
hst_arb_req_int[output_select] <= 1'b1;
avail_mc[output_select] <= 1'b0;
end // if (req_sync_2 ^ req_sync_3)
hst_arb_read <= capt_read[capt_select];
hst_arb_page <= capt_read[capt_select] ? 2'h3 : 2'h1;
hst_arb_addr <= capt_addr[capt_select];
// When we get a grant from the arbiter, deassert arbiter request and
// generate the grant toggle that is used to reassert ready.
// I should never get a request and grant in the same cycle
if(hst_gnt) begin
capt_select <= ~capt_select;
hst_arb_req_int[capt_select] <= 1'b0;
end // if (hst_gnt)
if (&hst_push_cnt | hst_mw_addr[0]) begin
clear_busy[final_select] <= ~clear_busy[final_select];
final_select <= ~final_select;
end
end // else: !if(!reset_n)
end // always @ (posedge mclock or negedge reset_n)
// finally, we need a process to forward push's and pop's correctly, and to
// mask writes that are part of the burst, but we don't have any data for.
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
hst_push <= 1'b0;
hst_pop <= 1'b0;
hst_mw_addr <= 2'b0;
hst_push_cnt <= 2'b0;
end else begin
if (rc_push_en) begin
hst_push <= 1'b1;
hst_push_cnt <= hst_push_cnt + 2'b1;
end else hst_push <= 1'b0;
if (rc_pop_en) begin
hst_pop <= 1'b1;
hst_mw_addr <= hst_mw_addr + 2'b1;
end else hst_pop <= 1'b0;
end // else: !if(!reset_n)
end // always @ (posedge mclock)
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; char s[200]; int main() { int T; scanf( %d , &T); for (int t = 1; t <= T; t++) { bool num = 0, xx = 0, dx = 0; vector<int> res; scanf( %s , s + 1); int len = strlen(s + 1); for (int i = 1; i <= len; i++) { if (isdigit(s[i])) { if (!num) num = 1; else res.push_back(i); } if (isalpha(s[i])) { if (s[i] == tolower(s[i])) { if (!xx) xx = 1; else res.push_back(i); } else { if (!dx) dx = 1; else res.push_back(i); } } } int cnt = 1; if (num == 0) s[res.back()] = 1 , res.pop_back(); if (xx == 0) s[res.back()] = a , res.pop_back(); if (dx == 0) s[res.back()] = A , res.pop_back(); printf( %s n , s + 1); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVGND_PP_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog wrapper for sleep_sergate_plv with size of 28 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_28 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_28 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ls__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int used[550][550]; int main() { int x, y; int x0, y0; cin >> x >> y; cin >> x0 >> y0; string s; cin >> s; int cnt = 0; cout << 1 << ; int last = x * y - 1; for (int i = 0; i < s.size(); i++) { used[x0][y0] = 1; bool flag = false; if (s[i] == D ) { if (x0 < x) { if (!used[x0 + 1][y0]) flag = true; x0++; } } if (s[i] == U ) { if (x0 > 1) { if (!used[x0 - 1][y0]) flag = true; x0--; } } if (s[i] == L ) { if (y0 > 1) { if (!used[x0][y0 - 1]) flag = true; y0--; } } if (s[i] == R ) { if (y0 < y) { if (!used[x0][y0 + 1]) flag = true; y0++; } } if (i < s.size() - 1) { if (flag) { cnt++; last--; } cout << int(flag) << ; } } cout << last << endl; }
|
#include <bits/stdc++.h> using namespace std; struct node { string name; int id; int taxi, pizza, girl; } arr[105]; int cmp1(node a, node b) { if (a.taxi == b.taxi) return a.id < b.id; return a.taxi > b.taxi; } int cmp2(node a, node b) { if (a.pizza == b.pizza) return a.id < b.id; return a.pizza > b.pizza; } int cmp3(node a, node b) { if (a.girl == b.girl) return a.id < b.id; return a.girl > b.girl; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int m; cin >> m >> arr[i].name; arr[i].id = i; for (int j = 0; j < m; j++) { int a, b, c; scanf( %d-%d-%d , &a, &b, &c); if (a % 10 == a / 10 && a == b && b == c) arr[i].taxi++; else if (a / 10 > a % 10 && a % 10 > b / 10 && b / 10 > b % 10 && b % 10 > c / 10 && c / 10 > c % 10) arr[i].pizza++; else arr[i].girl++; } } sort(arr, arr + n, cmp1); printf( If you want to call a taxi, you should call: ); int first = 1; for (int i = 0; i < n; i++) { if (arr[i].taxi != arr[0].taxi) break; if (!first) cout << , ; cout << arr[i].name; first = 0; } cout << . << endl; sort(arr, arr + n, cmp2); printf( If you want to order a pizza, you should call: ); first = 1; for (int i = 0; i < n; i++) { if (arr[i].pizza != arr[0].pizza) break; if (!first) cout << , ; cout << arr[i].name; first = 0; } cout << . << endl; sort(arr, arr + n, cmp3); printf( If you want to go to a cafe with a wonderful girl, you should call: ); first = 1; for (int i = 0; i < n; i++) { if (arr[i].girl != arr[0].girl) break; if (!first) cout << , ; cout << arr[i].name; first = 0; } cout << . << endl; return 0; }
|
/*###########################################################################
# Function: Single port memory wrapper
# To run without hardware platform dependancy use:
# `define TARGET_CLEAN"
############################################################################
*/
module memory_sp(/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, en, wen, addr, din
);
parameter AW = 14;
parameter DW = 32;
parameter WED = DW/8; //one write enable per byte
parameter MD = 1<<AW;//memory depth
//write-port
input clk; //clock
input en; //memory access
input [WED-1:0] wen; //write enable vector
input [AW-1:0] addr;//address
input [DW-1:0] din; //data input
output [DW-1:0] dout;//data output
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
reg [DW-1:0] dout;
//read port
always @ (posedge clk)
if(en)
dout[DW-1:0] <= ram[addr[AW-1:0]];
//write port
generate
genvar i;
for (i = 0; i < WED; i = i+1) begin: gen_ram
always @(posedge clk)
begin
if (wen[i] & en)
ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= din[(i+1)*8-1:i*8];
end
end
endgenerate
endmodule // memory_dp
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
`include "elink_constants.v"
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
// Inputs
reset, tx_lclk, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access, tx_burst
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
//###########
//# reset, clocks
//##########
input reset; //sync reset for io
input tx_lclk; //fast clock for io
input tx_lclk90; //fast 90deg shifted lclk
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [PW-1:0] tx_packet;
input tx_access;
input tx_burst;
output tx_io_wait;
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [7:0] tx_pointer;
reg [15:0] tx_data16;
reg tx_access_reg;
reg tx_frame;
reg tx_io_wait_reg;
reg [PW-1:0] tx_packet_reg;
reg [63:0] tx_double;
reg [2:0] tx_state_reg;
reg [2:0] tx_state;
//############
//# WIRES
//############
wire new_tran;
wire access;
wire write;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [7:0] txo_data;
wire txo_frame;
wire txo_lclk90;
reg tx_io_wait;
//#############################
//# Transmit state machine
//#############################
`define IDLE 3'b000
`define CYCLE1 3'b001
`define CYCLE2 3'b010
`define CYCLE3 3'b011
`define CYCLE4 3'b100
`define CYCLE5 3'b101
`define CYCLE6 3'b110
`define CYCLE7 3'b111
always @ (posedge tx_lclk)
if(reset)
tx_state[2:0] <= `IDLE;
else
case (tx_state[2:0])
`IDLE : tx_state[2:0] <= tx_access ? `CYCLE1 : `IDLE;
`CYCLE1 : tx_state[2:0] <= `CYCLE2;
`CYCLE2 : tx_state[2:0] <= `CYCLE3;
`CYCLE3 : tx_state[2:0] <= `CYCLE4;
`CYCLE4 : tx_state[2:0] <= `CYCLE5;
`CYCLE5 : tx_state[2:0] <= `CYCLE6;
`CYCLE6 : tx_state[2:0] <= `CYCLE7;
`CYCLE7 : tx_state[2:0] <= tx_burst ? `CYCLE4 : `IDLE;
endcase // case (tx_state)
assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
//Creating wait pulse for slow clock domain
always @ (posedge tx_lclk)
if(reset | ~tx_access)
tx_io_wait <= 1'b0;
else if ((tx_state[2:0] ==`CYCLE4) & ~tx_burst)
tx_io_wait <= 1'b1;
else if (tx_state[2:0]==`CYCLE7)
tx_io_wait <= 1'b0;
//Create frame signal for output
always @ (posedge tx_lclk)
begin
tx_state_reg[2:0] <= tx_state[2:0];
tx_frame <= |(tx_state_reg[2:0]);
end
//#############################
//# 2 CYCLE PACKET PIPELINE
//#############################
always @ (posedge tx_lclk)
if (tx_access)
tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
packet2emesh p2e (.access_out (access),
.write_out (write),
.datamode_out (datamode[1:0]),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (tx_packet_reg[PW-1:0]));
always @ (posedge tx_lclk)
if (tx_new_frame)
tx_double[63:0] <= {16'b0,//16
~write,7'b0,ctrlmode[3:0],//12
dstaddr[31:0],datamode[1:0],write,access};//36
else if(tx_state[2:0]==`CYCLE4)
tx_double[63:0] <= {data[31:0],srcaddr[31:0]};
//#############################
//# SELECTING DATA FOR TRANSMIT
//#############################
always @ (posedge tx_lclk)
case(tx_state_reg[2:0])
//Cycle1
3'b001: tx_data16[15:0] <= tx_double[47:32];
//Cycle2
3'b010: tx_data16[15:0] <= tx_double[31:16];
//Cycle3
3'b011: tx_data16[15:0] <= tx_double[15:0];
//Cycle4
3'b100: tx_data16[15:0] <= tx_double[63:48];
//Cycle5
3'b101: tx_data16[15:0] <= tx_double[47:32];
//Cycle6
3'b110: tx_data16[15:0] <= tx_double[31:16];
//Cycle7
3'b111: tx_data16[15:0] <= tx_double[15:0];
default tx_data16[15:0] <= 16'b0;
endcase // case (tx_state[2:0])
//#############################
//# ODDR DRIVERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data[i]),
.C (tx_lclk),
.CE (1'b1),
.D1 (tx_data16[i+8]),
.D2 (tx_data16[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE ("SYNC"))
oddr_frame (
.Q (txo_frame),
.C (tx_lclk),
.CE (1'b1),
.D1 (tx_frame),
.D2 (tx_frame),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
//##############################
//# OUTPUT BUFFERS
//##############################
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data[7:0])
);
OBUFDS obufds_frame ( .O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame)
);
OBUFDS obufds_lclk ( .O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
//################################
//# Wait Input Buffers
//################################
generate
if(ETYPE==1)
begin
assign tx_wr_wait = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait));
end
endgenerate
//TODO: Come up with cleaner defines for this
//Parallella and other platforms...
`ifdef TODO
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; void computeLcp(string &s1, string &s2, int LCP[][5005]) { for (int i = ((int)s1.size()) - 1; i >= 0; i--) { for (int j = ((int)s2.size()) - 1; j >= 0; j--) { if (s1[i] == s2[j]) { LCP[i][j] = 1 + LCP[i + 1][j + 1]; } else { LCP[i][j] = 0; } } } } int lcp[5005][5005]; int mUA[5005]; int mUB[5005]; int main() { ios_base::sync_with_stdio(0); string A, B; cin >> A >> B; memset((lcp), (0), sizeof(lcp)); ; computeLcp(A, A, lcp); int ans = (1 << 30); for (int i = 0; i < ((int)A.size()); i++) { int minUniqueLength = 0; for (int j = 0; j < ((int)A.size()); j++) { if (i == j) continue; minUniqueLength = max(minUniqueLength, lcp[i][j]); } minUniqueLength++; mUA[i] = minUniqueLength; } memset((lcp), (0), sizeof(lcp)); ; computeLcp(B, B, lcp); for (int i = 0; i < ((int)B.size()); i++) { int minUniqueLength = 0; for (int j = 0; j < ((int)B.size()); j++) { if (i == j) continue; minUniqueLength = max(minUniqueLength, lcp[i][j]); } minUniqueLength++; mUB[i] = minUniqueLength; } memset((lcp), (0), sizeof(lcp)); ; computeLcp(A, B, lcp); for (int i = 0; i < ((int)A.size()); i++) { for (int j = 0; j < ((int)B.size()); j++) { if (lcp[i][j] >= max(mUA[i], mUB[j])) { ans = min(ans, max(mUA[i], mUB[j])); } } } if (ans >= (1 << 30)) ans = -1; cout << ans << endl; return 0; }
|
module IMUL
(
input wire [3:0] A,
input wire [3:0] B,
output reg [7:0] out
);
reg rC1, rC2, rC3; //registros para los llevos
reg [2:0] rT1, rT2; //registros temporales
always @ (*) begin
//R0
out[0] =A[0] & B[0];
//R1
{rC1, out[1]} = (A[0] & B[1]) + (A[1] & B[0]);
//R2
{rC1, rT1[0]} = (A[2] & B[0]) + (A[1] & B[1]) + rC1;
{rC2, out[2]} = (A[0] & B[2]) + rT1[0];
//R3
{rC1, rT1[1]} = (A[3] & B[0]) + (A[2] & B[1]) + rC1;
{rC2, rT2[0]} = (A[1] & B[2]) + rT1[1] + rC2;
{rC3, out[3]} = (A[0] & B[3]) + rT2[0];
//R4
{rC1, rT1[2]} = (A[3] & B[1]) + rC1;
{rC2, rT2[1]} = (A[2] & B[2]) + rT1[2] + rC2;
{rC3, out[4]} = (A[1] & B[3]) + rT2[1] + rC3;
//R5
{rC2, rT2[2]} = (A[3] & B[2]) + rC2 + rC1;
{rC3, out[5]} = (A[2] & B[3]) + rT2[2] + rC3;
//R6 y R7.
{out[7], out[6]} = (A[3] & B[3]) + rC2 + rC3;
end
endmodule
module testbench;
wire [7:0] Q;
reg [3:0] a,b;
IMUL im(a,b,Q);
initial begin
$dumpfile("imul.vcd");
$dumpvars;
a = 4'hF;
b = 4'h2;
#20;
a = 4'hA;
b = 4'h5;
#20;
a = 4'hB;
b = 4'hC;
#20 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; int lp[N + 1]; vector<int> pr; int i, j, p1, p2, x0, x1, x2, ans; int main() { for (i = 2; i <= N; i++) { if (lp[i] == 0) { lp[i] = i; pr.push_back(i); } for (j = 0; j < pr.size() && pr[j] <= lp[i] && i * pr[j] <= N; j++) lp[i * pr[j]] = pr[j]; } cin >> x2; for (i = pr.size() - 1; i >= 0; i--) if (x2 % pr[i] == 0) break; if (x2 == pr[i]) { cout << x2 << endl; return 0; } p2 = pr[i]; ans = x2 - p2 + 1; for (j = 0; j < pr.size() && pr[j] <= x2; j++) { p1 = pr[j]; x1 = ((x2 - p2) / p1 + 1) * p1; if (x1 > x2) continue; if (x1 == p1) x0 = p1; else x0 = x1 - p1 + 1; if (x0 >= 3) ans = min(ans, x0); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const int M = 1e9 + 7; long long a[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long d; cin >> a[0] >> a[1] >> a[2] >> d; sort(a, a + 3); cout << max(0ll, a[0] - a[1] + d) + max(0ll, a[1] + d - a[2]); }
|
#include <bits/stdc++.h> using namespace std; long long k, n, a, b, val; void solve() { cin >> k >> n >> a >> b; k -= a * n; if (k <= 0) { k *= -1, k++; val = (k + a - b - 1) / (a - b); if (val > n) { cout << -1 << endl; return; } n -= val; } cout << n << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<pair<string, int>> v(n); for (int i = 0; i < n; i++) { string s; cin >> s; v[i].first = s; v[i].second = i + 1; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (j % 2 == 1) { v[i].first[j] = (char)( Z - v[i].first[j]); } } } sort(v.begin(), v.end()); for (int i = 0; i < n; i++) { cout << v[i].second << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int p[111]; int main() { int n, a = 0, b = 0, c = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> p[i]; if (i < 3 && i == 1 || i % 3 == 1) { a = a + p[i]; } else if (i < 3 && i == 2 || i % 3 == 2) { b = b + p[i]; } else if (i % 3 == 0) { c = c + p[i]; } } if (max(a, max(b, c)) == a) { cout << chest ; } else if (max(a, max(b, c)) == b) { cout << biceps ; } else if (max(a, max(b, c)) == c) { cout << back ; } }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpciexpav_stif_p2a_addrtrans (
k_bar_i,
cb_p2a_avalon_addr_b0_i,
cb_p2a_avalon_addr_b1_i,
cb_p2a_avalon_addr_b2_i,
cb_p2a_avalon_addr_b3_i,
cb_p2a_avalon_addr_b4_i,
cb_p2a_avalon_addr_b5_i,
cb_p2a_avalon_addr_b6_i,
PCIeAddr_i,
BarHit_i,
AvlAddr_o
);
input [227:0] k_bar_i;
input [31:0] cb_p2a_avalon_addr_b0_i;
input [31:0] cb_p2a_avalon_addr_b1_i;
input [31:0] cb_p2a_avalon_addr_b2_i;
input [31:0] cb_p2a_avalon_addr_b3_i;
input [31:0] cb_p2a_avalon_addr_b4_i;
input [31:0] cb_p2a_avalon_addr_b5_i;
input [31:0] cb_p2a_avalon_addr_b6_i;
input [31:0] PCIeAddr_i;
input [6:0] BarHit_i;
output [31:0] AvlAddr_o;
reg [31:0] bar_parameter;
reg [31:0] avl_addr;
wire [31:0] bar0;
wire [31:0] bar1;
wire [31:0] bar2;
wire [31:0] bar3;
wire [31:0] bar4;
wire [31:0] bar5;
wire [31:0] exp_rom_bar;
assign bar0 = k_bar_i[31:0];
assign bar1 = k_bar_i[63:32];
assign bar2 = k_bar_i[95:64];
assign bar3 = k_bar_i[127:96];
assign bar4 = k_bar_i[159:128];
assign bar5 = k_bar_i[191:160];
assign exp_rom_bar = k_bar_i[223:192];
// mux to select the right BAR parameter to use.
// based on the BAR hit information, determined BAR paremeter
// is used for the address translation
always @(BarHit_i or bar0 or bar1 or bar2 or bar3 or bar4 or bar5 or exp_rom_bar)
begin
case (BarHit_i)
7'b0000001 : bar_parameter = bar0;
7'b0000010 : bar_parameter = bar1;
7'b0000100 : bar_parameter = bar2;
7'b0001000 : bar_parameter = bar3;
7'b0010000 : bar_parameter = bar4;
7'b0100000 : bar_parameter = bar5;
7'b1000000 : bar_parameter = exp_rom_bar;
default : bar_parameter = 32'h00000000;
endcase
end
// mux to select the right avalon address entry to use
// Based on the BAR hit information, select which entry in the table to
// be used for the address translation
always @(BarHit_i or cb_p2a_avalon_addr_b0_i or cb_p2a_avalon_addr_b1_i or
cb_p2a_avalon_addr_b2_i or cb_p2a_avalon_addr_b3_i or
cb_p2a_avalon_addr_b4_i or cb_p2a_avalon_addr_b5_i or
cb_p2a_avalon_addr_b6_i)
begin
case (BarHit_i )
7'b0000001 : avl_addr = cb_p2a_avalon_addr_b0_i;
7'b0000010 : avl_addr = cb_p2a_avalon_addr_b1_i;
7'b0000100 : avl_addr = cb_p2a_avalon_addr_b2_i;
7'b0001000 : avl_addr = cb_p2a_avalon_addr_b3_i;
7'b0010000 : avl_addr = cb_p2a_avalon_addr_b4_i;
7'b0100000 : avl_addr = cb_p2a_avalon_addr_b5_i;
7'b1000000 : avl_addr = cb_p2a_avalon_addr_b6_i;
default : avl_addr = 32'h00000000;
endcase
end
// address translation. The high order bits is from the corresponding
// entry of the table and low order is passed through unchanged.
assign AvlAddr_o = (PCIeAddr_i & ~({bar_parameter[31:4], 4'b0000})) |
(avl_addr & ({bar_parameter[31:4], 4'b0000})) ;
endmodule
|
#include <bits/stdc++.h> const int N = 1e6; const int M = 2e5 + 10; const int mod = 1e9 + 7; long long n, a[M], cnt[N], cnt2[N], sol[N]; long long brzo_stepenovanje(long long x, long long k) { if (k == 0) return 1; if (k == 1) return x; if (k % 2) return (x * brzo_stepenovanje((x * x) % mod, k / 2)) % mod; else return brzo_stepenovanje((x * x) % mod, k / 2) % mod; } int main() { scanf( %lld , &n); for (int i = 1; i <= n; i++) cnt[i] = 0, cnt2[i] = 0; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); cnt2[a[i]]++; } for (int i = 2; i <= N; i++) for (int j = i; j <= N; j += i) { cnt[i] += cnt2[j]; } for (int i = 1; i <= N; i++) sol[i] = 0; for (int i = 2; i <= N; i++) sol[i] = (cnt[i] * brzo_stepenovanje(2, cnt[i] - 1)) % mod; for (int i = N / 2; i >= 2; i--) for (int j = i + i; j <= N; j += i) { sol[i] -= sol[j]; if (sol[i] < 0) sol[i] += mod; } long long ans = 0; for (int i = 2; i <= N; i++) { ans += (sol[i] * i) % mod; ans %= mod; } printf( %lld , ans); return 0; }
|
`default_nettype none
module main (input wire clk,
input wire sw_in,
output wire sw_out);
//-- Configure the pull-up resistors for clk and rst inputs
wire sw_in2, sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(sw_in),
.D_IN_0(sw_in2)
);
//-- Sw is the signal from the switch-button, with standard logic and pull-ups
//-- activated
assign sw = ~sw_in2;
//-- Instanciate the debounce circuit
debounce d1 (
.clk(clk),
.sw_in(sw),
.sw_out(sw_out)
);
endmodule // main
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//-- Debug!!!
//assign sw_out = sw_in;
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
// Copyright (C) 2021 JacderZhang // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <https://www.gnu.org/licenses/>. #ifndef SCANNER_H_ #define SCANNER_H_ 1 #include <stdio.h> #include <stdlib.h> class Scanner { private: static const int BUFFER_SIZE = 1 << 18; char buff[BUFFER_SIZE]; char *buffPos, *buffLim; FILE *file; public: Scanner(FILE *file) { this->file = file; buffLim = buff + fread(buff, 1, BUFFER_SIZE, file); buffPos = buff; } private: inline void flushBuff() { buffLim = buff + fread(buff, 1, BUFFER_SIZE, file); if (buffLim == buff) { *buffLim++ = n ; } buffPos = buff; } inline bool isWS(char t) { return t <= ; } inline bool isDig(char t) { return t >= 0 && t <= 9 ; } inline void nextPos() { buffPos++; if (buffPos == buffLim) { flushBuff(); } } public: inline char getchar() { char ch = *buffPos; nextPos(); return ch; } inline void next(char* s) { while (isWS(*buffPos)) { nextPos(); } while (!isWS(*buffPos)) { *s = *buffPos; s++; nextPos(); } *s = 0 ; } inline void nextLine(char* s) { while (*buffPos != n ) { nextPos(); } if (*buffPos == n ) { nextPos(); } while (*buffPos != n ) { *s++ = *buffPos; nextPos(); } *s = 0 ; } inline int nextInt() { while (!isDig(*buffPos) && *buffPos != - ) { nextPos(); } int sign = (*buffPos == - ) ? nextPos(), -1 : 1; int res = 0; while (isDig(*buffPos)) { res = res * 10 + *buffPos - 0 ; nextPos(); } return res * sign; } inline long long nextLong() { while (!isDig(*buffPos) && *buffPos != - ) { nextPos(); } long long sign = (*buffPos == - ) ? nextPos(), -1 : 1; long long res = 0; while (isDig(*buffPos)) { res = res * 10 + *buffPos - 0 ; nextPos(); } return res * sign; } inline int n() { while (*buffPos < 0 || *buffPos > 9 ) { buffPos++; if (buffPos == buffLim) { flushBuff(); } } int res = 0; while (*buffPos >= 0 && *buffPos <= 9 ) { res = res * 10 + (*buffPos - 0 ); buffPos++; if (buffPos == buffLim) { flushBuff(); } } return res; } inline long long nl() { while (*buffPos < 0 || *buffPos > 9 ) { buffPos++; if (buffPos == buffLim) { flushBuff(); } } long long res = 0; while (*buffPos >= 0 && *buffPos <= 9 ) { res = res * 10 + (*buffPos - 0 ); buffPos++; if (buffPos == buffLim) { flushBuff(); } } return res; } inline long long nlm(const int MOD) { while (*buffPos < 0 || *buffPos > 9 ) { buffPos++; if (buffPos == buffLim) { flushBuff(); } } long long res = 0; while (*buffPos >= 0 && *buffPos <= 9 ) { res = (res * 10 + (*buffPos - 0 )) % MOD; buffPos++; if (buffPos == buffLim) { flushBuff(); } } return res; } inline double nextDouble() { while (isWS(*buffPos)) { nextPos(); } int sign = (*buffPos == - ) ? nextPos(), -1 : 1; double res = 0; while (isDig(*buffPos)) { res = res * 10 + *buffPos - 0 ; nextPos(); } if (*buffPos == . ) { nextPos(); double ep = 1; while (isDig(*buffPos)) { ep *= 0.1; res += ep * (*buffPos - 0 ); nextPos(); } } return sign * res; } inline char nextChar() { while (isWS(*buffPos)) nextPos(); char res = *buffPos; nextPos(); return res; } ~Scanner() { fclose(file); } }; #ifndef SCANNER_H_CUSTOM Scanner sc(stdin); #endif #endif /* SCANNER_H_ */ #ifndef LOG_H_ #define LOG_H_ 1 #include <iostream> #include <utility> #include <iterator> #include <string> std::string cout_list_sep = ; template<class IterateType, typename = decltype(std::declval<IterateType>().begin()), typename = decltype(std::declval<IterateType>().end()), typename = typename std::enable_if<std::is_convertible< typename std::iterator_traits< typename IterateType::iterator> ::iterator_category, std::input_iterator_tag> ::value> ::type, typename = typename std::enable_if<!std::is_same<std::string, typename std::decay<IterateType>::type>::value>::type, typename value_type = typename IterateType::value_type> std::ostream& operator<< (std::ostream& out, const IterateType& a) { for (const auto& i: a) out << i << cout_list_sep; return out; } template<class __TyFirst, class __TySecond> std::ostream& operator<<(std::ostream& out, const std::pair<__TyFirst, __TySecond>& o) { out << ( << o.first << , << o.second << ) ; return out; } #ifdef __LOCALE__ template<typename T> void __ses(const T& a) { std::cout << a << ; } template<typename T, typename... Args> void __ses(const T& a, Args... b) { std::cout << a << ; __ses(b...); } #define ses(...) { std::cout << #__VA_ARGS__ << = ; __ses(__VA_ARGS__); } #define see(...) { ses(__VA_ARGS__); std::cout << std::endl; } #define slog(format, ...) printf(format n , __VA_ARGS__) static constexpr char __log_space[] = ; template<typename _ForwardIterator> void logArray(_ForwardIterator __begin, _ForwardIterator __end, const char* __sep = 0) { if (__sep == 0) { __sep = __log_space; } while (__begin != __end) { std::cout << *__begin << *__sep; ++__begin; } std::cout << std::endl; } #else #define see(...) #define ses(...) #define slog(format, ...) template<typename _ForwardIterator> void logArray(_ForwardIterator, _ForwardIterator, const char* = 0) {} #endif #endif /* LOG_H_ */ #ifndef RANGE_H_ #define RANGE_H_ #include <stdexcept> #include <iterator> #include <type_traits> namespace Temps { template <typename _IntType> class RangeInt { static_assert(std::is_integral<_IntType>::value, RangeInt object must have integral value type ); public: class iterator : public std::iterator<std::input_iterator_tag, _IntType, _IntType, const _IntType*, _IntType> { _IntType val, step; public: using typename std::iterator<std::input_iterator_tag, _IntType, _IntType, const _IntType*, _IntType>::reference; explicit constexpr iterator(int val, int step) noexcept : val(val), step(step) {} constexpr iterator& operator++() noexcept { val += step; return *this; } constexpr iterator operator++(int) noexcept { iterator ret = *this; val += step; return ret; } constexpr bool operator== (const iterator& rhs) const noexcept { return val == rhs.val; } constexpr bool operator!= (const iterator& rhs) const noexcept { return val != rhs.val; } constexpr reference operator*() const { return val; } }; typedef _IntType value_type; typedef _IntType size_type; const value_type _begin, _step, _end; explicit constexpr RangeInt(const value_type end) noexcept : _begin(0), _step(1), _end(end>0 ? end : 0) {} explicit constexpr RangeInt(const value_type begin, const value_type end) noexcept : _begin(begin), _step(1), _end(end>begin ? end : begin) {} explicit constexpr RangeInt(const value_type begin, const value_type end, const value_type step) : _begin(begin), _step(step), _end( ((step>0&&end<=begin) || (step<0&&end>=begin)) ? begin : (step>0 ? begin+(end-begin+step-1)/step*step : begin+(begin-end-step-1)/(-step)*step)) {} constexpr iterator begin() const noexcept { return iterator(_begin, _step); } constexpr iterator end() const noexcept { return iterator(_end, _step); } constexpr size_type size() const noexcept { return (_end - _begin) / _step; } }; template <class IntType, typename = typename std::enable_if< std::is_integral<IntType>::value>::type> inline constexpr RangeInt<IntType> range(IntType arg1) { return RangeInt<IntType>(arg1); } template <class IntType, typename = typename std::enable_if< std::is_integral<IntType>::value>::type> inline constexpr RangeInt<IntType> range(IntType arg1, IntType arg2) { return RangeInt<IntType>(arg1, arg2); } template <class IntType, typename = typename std::enable_if< std::is_integral<IntType>::value>::type> inline constexpr RangeInt<IntType> range(IntType arg1, IntType arg2, IntType arg3) { return RangeInt<IntType>(arg1, arg2, arg3); } } /* namespace Temps */ using Temps::range; #endif #ifndef UTIL_H_ #define UTIL_H_ 1 #include <algorithm> #ifndef VECTOR_H_ #include <vector> #endif namespace Temps { template<class T> inline bool checkMin(T& a, T b) { return (b < a ? a = b, 1 : 0); } template<class T> inline bool checkMax(T& a, T b) { return (a < b ? a = b, 1 : 0); } template <class IntType, typename = typename std::enable_if<std::is_integral<IntType>::value>::type> IntType gcd(const IntType a, const IntType b) { return b == 0 ? a : gcd(b, a % b); } template <class ForwardIterator, class OutputIterator> void dissociate(ForwardIterator __begin, ForwardIterator __end, OutputIterator __dest) { #ifdef VECTOR_H_ Temps::Vector #else std::vector #endif <typename std::iterator_traits<ForwardIterator>::value_type> values(__begin, __end); std::sort(values.begin(), values.end()); std::unique(values.begin(), values.end()); while (__begin != __end) { *__dest = std::distance(values.begin(), std::lower_bound(values.begin(), values.end(), *__begin)); __dest++; __begin++; } } } using Temps::checkMin; using Temps::checkMax; #endif /* UTIL_H_ */ #ifndef VECTOR_H_ #define VECTOR_H_ #include <cstdlib> #include <utility> #include <iterator> #include <initializer_list> #include <type_traits> namespace Temps { template <class Type> class Vector { static_assert(std::is_trivial<Type>::value, Temps::Vector can only be used for trival types ); public: typedef Type value_type; typedef unsigned int size_type; typedef Type& reference; typedef const Type& const_reference; class iterator : public std::iterator<std::random_access_iterator_tag, value_type> { public: friend class Vector; using typename std::iterator<std::random_access_iterator_tag, value_type>::difference_type; using typename std::iterator<std::random_access_iterator_tag, value_type>::pointer; using typename std::iterator<std::random_access_iterator_tag, value_type>::reference; private: pointer ptr; iterator(pointer ptr) : ptr(ptr) {} public: bool operator== (const iterator rhs) const { return ptr == rhs.ptr; } bool operator!= (const iterator rhs) const { return ptr != rhs.ptr; } bool operator< (const iterator rhs) const { return ptr < rhs.ptr; } bool operator<= (const iterator rhs) const { return ptr <= rhs.ptr; } bool operator> (const iterator rhs) const { return ptr > rhs.ptr; } bool operator>= (const iterator rhs) const { return ptr >= rhs.ptr; } iterator operator++ () { return iterator(++ptr); } iterator operator++ (int) { return iterator(ptr++); } iterator operator-- () { return iterator(--ptr); } iterator operator-- (int) { return iterator(ptr--); } iterator operator+ (const difference_type dif) const { return iterator(ptr + dif); } iterator operator- (const difference_type dif) const { return iterator(ptr - dif); } iterator operator+= (const difference_type dif) { ptr += dif; return *this; } iterator operator-= (const difference_type dif) { ptr -= dif; return *this; } difference_type operator- (const iterator& rhs) const { return ptr - rhs.ptr; } operator pointer() { return ptr; } }; protected: value_type *a = nullptr; size_type _capacity=0, _size=0; void __grow_capacity(size_type least_size) { if (_capacity >= least_size) { return; } if (_capacity == 0) { _capacity = 1; } while (_capacity < least_size) { _capacity = _capacity * 2; } a = static_cast<value_type*>(realloc(a, sizeof(value_type) * _capacity)); } public: Vector() =default; explicit Vector(size_type size, const value_type& initial_value = value_type()) : _capacity(size), _size(size) { a = static_cast<value_type*>(malloc(sizeof(value_type) * _capacity)); value_type *__first = a, *const __last = a + _size; while (__first != __last) { *__first++ = initial_value; } } Vector(const Vector& rhs) : _capacity(rhs._size), _size(rhs._size) { a = static_cast<value_type*>(malloc(sizeof(value_type) * _capacity)); value_type *__first = a, *__r_p = rhs.a, *const __last = a + _size; while (__first != __last) { *__first++ = *__r_p++; } } Vector(Vector&& rhs) : _capacity(rhs._capacity), _size(rhs._size) { a = rhs.a; rhs.a = nullptr; } template <typename Container, typename = decltype(std::declval<Container>().begin(), std::declval<Container>().end())> Vector(const Container& list) : _capacity(std::distance(list.begin(), list.end())), _size(_capacity) { a = static_cast<value_type*>(malloc(sizeof(value_type) * _capacity)); value_type *p = a; for (const auto& i: list) { *p++ = i; } } template <typename _InputIterator, typename = typename std::enable_if<std::is_convertible<typename std::iterator_traits<_InputIterator>::iterator_category, std::input_iterator_tag>::value>::type> explicit Vector(_InputIterator __first, _InputIterator __last) { _size = _capacity = std::distance(__first, __last); a = static_cast<value_type*>(malloc(sizeof(value_type) * _capacity)); value_type *p = a; while (__first != __last) { *p++ = *__first++; } } inline bool empty() const { return _size == 0; } inline size_type size() const { return _size; } inline size_type capacity() const { return _capacity; } void reserve(size_type __capacity) { _capacity = __capacity; if (_size > _capacity) { _size = _capacity; } a = static_cast<value_type*>(realloc(a, sizeof(value_type) * _capacity)); } void resize(size_type __size) { if (_size > __size) { _size = __size; return; } __grow_capacity(__size); value_type *__un = a + _size, *const __ed = a + __size; while (__un != __ed) { *__un++ = value_type(); } _size = __size; } inline void clear() { resize(0); } Vector& operator= (const Vector& rhs) { __grow_capacity(rhs._size); _size = rhs._size; value_type *__first = a; const value_type *const __last = a+_size, *__r_p = rhs.a; while (__first != __last) { *__first++ = *__r_p++; } return *this; } Vector& operator= (Vector&& rhs) { _size = rhs._size; _capacity = rhs._capacity; free(a); a = rhs.a; rhs.a = nullptr; return *this; } value_type operator[] (const size_type id) const { return a[id]; } value_type& operator[] (const size_type id) { return a[id]; } value_type front() const { return a[0]; } value_type& front() { return a[0]; } value_type back() const { return a[_size - 1]; } value_type& back() { return a[_size - 1]; } void pop_back() { _size--; } Vector& push_back(const value_type& b) { __grow_capacity(_size + 1); a[_size] = b; _size++; return *this; } Vector& push_back(const Vector& rhs) { __grow_capacity(_size + rhs._size); for (const auto& i: rhs) { a[_size++] = i; } return *this; } Vector& push_back(const std::initializer_list<value_type>& rhs) { __grow_capacity(_size + rhs.size()); for (const auto& i: rhs) { a[_size++] = i; } return *this; } inline iterator begin() const { return iterator(a); } inline iterator end() const { return iterator(a + _size); } ~Vector() { free(a); } }; } /* namespace Temps */ using Temps::Vector; #endif /* VECTOR_H_ */ // #include /home/jack/code/creats/STree.h // #include /home/jack/code/creats/Tree.h // #include /home/jack/code/creats/Graph.h // #include /home/jack/code/creats/Intm.h // #include /home/jack/code/Math/Poly/main.h #include <bits/stdc++.h> #define MULTIPLE_TEST_CASES_WITH_T // #define MULTIPLE_TEST_CASES_WITHOUT_T #ifndef _BODY_MAIN #define _BODY_MAIN 1 #ifndef CUSTOM_MAIN void preInit(); void init(); void solve(); int32_t main() { preInit(); #ifdef MULTIPLE_TEST_CASES_WITH_T int T; #ifdef SCANNER_H_ T = sc.nextInt(); #else scanf( %d , &T); #endif /* SCANNER_H_ */ while (T--) { init(); solve(); } #else #ifdef MULTIPLE_TEST_CASES_WITHOUT_T while (1) { try { init(); } catch (bool t) { return 0; } solve(); } #else init(); solve(); #endif /* MULTIPLE_TEST_CASES_WITHOUT_T */ #endif /* MULTIPLE_TEST_CASES_WITH_T */ return 0; } #endif /* CUSTOM_MAIN */ #endif /* _BODY_MAIN */ // #define int long long /** My code begins here **/ const int kN = 5e5 + 5; int n, m, dg[kN], p[kN], q[kN], siz[kN], rt[kN], col[kN], col_cnt; std::vector <int> st_E[kN]; std::set <int> S, E[kN]; void Add(int u, int v) { E[u].insert(v); E[v].insert(u); ++dg[u]; ++dg[v]; } void AddTree(int u, int v) { st_E[u].push_back(v); st_E[v].push_back(u); } void Dfs(int u, int p) { for(auto v : S) if(!E[u].count(v)) AddTree(u, v); for(auto v : st_E[u]) if(v != p) S.erase(v); for(auto v : st_E[u]) if(v != p) Dfs(v, u); } void Dfs2(int u, int p) { bool flag = false; if(!col[u]) { for(auto v : st_E[u]) if(!col[v]) flag = true; if(flag) { col[u] = ++col_cnt; rt[col[u]] = u; siz[col[u]] = 1; for(auto v : st_E[u]) { if(!col[v]) { ++siz[col[u]]; col[v] = col[u]; } } } else { for(auto v : st_E[u]) if(col[v]) { if(rt[col[v]] == v) { ++siz[col[v]]; col[u] = col[v]; } else if(siz[col[v]] > 2) { col[u] = ++col_cnt; rt[col[u]] = u; siz[col[u]] = 2; --siz[col[v]]; col[v] = col[u]; } else { rt[col[v]] = v; col[u] = col[v]; ++siz[col[u]]; } break; } } } for(auto v : st_E[u]) if(v != p) Dfs2(v, u); } std::queue <int> que; std::vector <int> V_col[kN]; void preInit() {} void init() { col_cnt = 0; n = sc.n(); m = sc.n(); for(int i = 1; i <= n; ++i) { dg[i] = col[i] = siz[i] = p[i] = q[i] = 0; E[i].clear(); st_E[i].clear(); V_col[i].clear(); S.insert(i); } for(int i = 1; i <= m; ++i) { int u, v; u = sc.n(); v = sc.n(); Add(u, v); } for(int i = 1; i <= n; ++i) if(dg[i] == n - 1) { S.erase(i); que.push(i); } } void solve() { int tot = n; while(!que.empty()) { int u = que.front(); que.pop(); p[u] = q[u] = tot--; for(auto v : E[u]) { --dg[v]; if(S.count(v) && dg[v] >= tot - 1) { que.push(v); S.erase(v); } } } for(int i = 1; i <= n; ++i) if(S.count(i)) { S.erase(i); Dfs(i, 0); } for(int i = 1; i <= n; ++i) if(!p[i] && !col[i]) Dfs2(i, 0); for(int i = 1; i <= n; ++i) if(col[i]) V_col[col[i]].push_back(i); for(int i = 1, s = 1; i <= col_cnt; ++i, ++s) { q[rt[i]] = s; for(auto u : V_col[i]) { if(u != rt[i]) { p[u] = s; q[u] = ++s; } } p[rt[i]] = s; } for(int i = 1; i <= n; ++i) printf( %d , p[i]); printf( n ); for(int i = 1; i <= n; ++i) printf( %d , q[i]); printf( n ); }
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#include <bits/stdc++.h> using namespace std; signed main() { long long n, m; cin >> n >> m; string s[n], v[n], a[n], o[n], b[n]; bool t[n]; string buf; for (long long i = 0; i < n; i++) { cin >> s[i]; cin >> buf; cin >> buf; t[i] = isdigit(buf[0]); if (t[i]) v[i] = buf; else { a[i] = buf; cin >> o[i] >> b[i]; } } map<string, long long> ms; for (long long i = 0; i < n; i++) ms[s[i]] = i; ms[ ? ] = n; string ans, ans2; for (long long i = 0; i < m; i++) { long long tmp[2] = {}; long long res[n + 1]; memset(res, 0, sizeof(res)); for (long long k = 0; k < 2; k++) { res[n] = k; for (long long j = 0; j < n; j++) { if (t[j]) { res[j] = v[j][i] - 0 ; continue; } long long ba = res[ms[a[j]]], bb = res[ms[b[j]]]; if (o[j] == AND ) res[j] = ba & bb; if (o[j] == OR ) res[j] = ba | bb; if (o[j] == XOR ) res[j] = ba ^ bb; } for (long long j = 0; j < n; j++) tmp[k] += res[j]; } if (tmp[0] <= tmp[1]) ans += 0 ; else ans += 1 ; if (tmp[0] >= tmp[1]) ans2 += 0 ; else ans2 += 1 ; } cout << ans << endl << ans2 << endl; return 0; }
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// ======================================================================
// CBC-DES encryption/decryption
// algorithm according to FIPS 46-3 specification
// Copyright (C) 2013 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write:the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module cbctdes
(
input reset_i, // async reset
input clk_i, // clock
input start_i, // start cbc
input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
input [0:63] key1_i, // key input
input [0:63] key2_i, // key input
input [0:63] key3_i, // key input
input [0:63] iv_i, // iv input
input [0:63] data_i, // data input
input valid_i, // input key/data valid flag
output reg ready_o, // ready to encrypt/decrypt
output reg [0:63] data_o, // data output
output valid_o // output data valid flag
);
reg mode;
wire tdes_mode;
reg start;
reg [0:63] key;
wire [0:63] tdes_key1;
wire [0:63] tdes_key2;
wire [0:63] tdes_key3;
reg [0:63] key1;
reg [0:63] key2;
reg [0:63] key3;
reg [0:63] iv;
reg [0:63] datain;
reg [0:63] datain_d;
reg [0:63] tdes_datain;
wire validin;
wire [0:63] tdes_dataout;
reg [0:63] dataout;
wire tdes_ready;
always @(*) begin
if (~mode_i && start_i) begin
tdes_datain = iv_i ^ data_i;
end
else if (~mode && ~start_i) begin
tdes_datain = dataout ^ data_i;
end
else begin
tdes_datain = data_i;
end
end
always @(*) begin
if (mode && start) begin
data_o = iv ^ tdes_dataout;
end
else if (mode && ~start) begin
data_o = datain_d ^ tdes_dataout;
end
else begin
data_o = tdes_dataout;
end
end
assign tdes_key1 = start_i ? key1_i : key1;
assign tdes_key2 = start_i ? key2_i : key2;
assign tdes_key3 = start_i ? key3_i : key3;
assign validin = valid_i & ready_o;
// input register
always @(posedge clk_i, negedge reset_i) begin
if (~reset_i) begin
mode <= 0;
start <= 0;
key1 <= 0;
key2 <= 0;
key3 <= 0;
iv <= 0;
datain <= 0;
datain_d <= 0;
end
else begin
if (valid_i && ready_o) begin
start <= start_i;
datain <= data_i;
datain_d <= datain;
end
else if (valid_i && ready_o && start_i) begin
mode <= mode_i;
key1 <= key1_i;
key2 <= key2_i;
key3 <= key3_i;
iv <= iv_i;
end
end
end
// output register
always @(posedge clk_i, negedge reset_i) begin
if (~reset_i) begin
ready_o <= 1;
dataout <= 0;
end
else begin
if (valid_i && ready_o && tdes_ready) begin
ready_o <= 0;
end
else if (valid_o) begin
ready_o <= 1;
dataout <= tdes_dataout;
end
end
end
// des instance
tdes i_tdes (
.reset_i(reset_i),
.clk_i(clk_i),
.mode_i(tdes_mode),
.key1_i(tdes_key1),
.key2_i(tdes_key2),
.key3_i(tdes_key3),
.data_i(tdes_datain),
.valid_i(validin),
.data_o(tdes_dataout),
.valid_o(valid_o),
.ready_o(tdes_ready)
);
endmodule
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