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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, in[200005], a[200005], sta[200005], top, now, root, ans, flag; bool vis[200005], mark[200005]; int read() { int x, f = 1; char ch; while (!(isdigit(ch = getchar()))) ch == - ? f = -1 : f; x = ch - 48; while ((isdigit(ch = getchar()))) x = x * 10 + ch - 48; return f * x; } void Topology() { while (now < top) { now++; int tmp = sta[now]; vis[tmp] = 1; in[a[tmp]]--; if (!in[a[tmp]]) sta[++top] = a[tmp]; } } void dfs(int u) { vis[u] = 1; if (!vis[a[u]]) dfs(a[u]); } int main() { n = read(); for (int i = 1; i <= n; i++) { a[i] = read(); in[a[i]]++; if (a[i] == i) { flag = 1; root = i; } } for (int i = 1; i <= n; i++) if (!in[i]) sta[++top] = i; Topology(); for (int i = 1; i <= n; i++) { if (!vis[i]) { if (!root) root = i; ans++; dfs(a[i]); a[i] = root; mark[i] = 1; } } printf( %d n , ans - flag); for (int i = 1; i <= n; i++) { if (mark[i]) a[i] = root; printf( %d , a[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int64_t max(int32_t a, int64_t b) { return max((int64_t)a, b); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); pair<int64_t, int64_t> lc, rc; cin >> rc.second >> rc.first; lc.first = lc.second = 1; int64_t k; cin >> k; int64_t cnt = 0; int64_t ans = 0; int64_t cur = 1; while (cnt < k) { ans += (rc.first - lc.first + 1) * (rc.second - lc.second + 1); rc.first--; rc.second--; lc.second++; lc.first++; ans -= (rc.first - lc.first + 1) * (rc.second - lc.second + 1); cnt++; rc.first--; rc.second--; lc.second++; lc.first++; } cout << ans; }
|
#include <bits/stdc++.h> int main() { int a, i, b, k, temp; while (~scanf( %d , &a) && a >= 0) { temp = 0; while (a) { b = a; k = 0; while (b > 0) { if (k < b % 10) k = b % 10; b = b / 10; } a -= k; temp++; } printf( %d n , temp); } return 0; }
|
module scheduler1_multi(clk, reset, wen, enablein, datain, dataout, full, empty, enableout);
parameter data_width = 32;
//parameter data_width1 = 34;
parameter data_width1 = 36;
parameter address_width = 7;
parameter FIFO_depth = 128;
parameter number_mapper = 2;
input clk,reset,wen,enablein;
input [data_width-1:0] datain;
output [data_width1-1:0] dataout;
output full,empty;
output enableout;
reg[address_width-1:0] write_p,read_p;
reg[address_width:0] counter;
reg[data_width-1:0] dataout1;
wire[data_width1-1:0] dataout;
reg [data_width-1:0] memory[FIFO_depth-1:0];
reg[data_width-1:0] keywordnumber,textfilenumber;
reg enableout1;
reg[3:0] routeraddress;
reg wen1;
reg [data_width-1:0] datain1;
reg ren;
reg[5:0]counter2,counter1,counter3,counter4;
reg[3:0] mapper_p;
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
wen1=0;
else
if(wen)
wen1=1;
else
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
wen1=0;
else
wen1=wen1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
ren=0;
else
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
ren=1;
else
if(write_p==read_p&&write_p>3)
ren=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter1=0;
else
if(ren&&counter1<2)
counter1=counter1+1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
dataout1=dataout1+1;
else
dataout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
routeraddress=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
routeraddress=1;
else
if(ren&&(read_p<write_p)&&(write_p<FIFO_depth-1))
begin
if(mapper_p==1)
routeraddress=4'b1001;
else if(mapper_p==2)
routeraddress=4'b0110;
else if(mapper_p==3)
routeraddress=4;
else if(mapper_p==4)
routeraddress=5;
else if(mapper_p==5)
routeraddress=6;
else if(mapper_p==6)
routeraddress=7;
else if(mapper_p==7)
routeraddress=8;
else if(mapper_p==8)
routeraddress=9;
end
else
routeraddress=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
enableout1=0;
else
if(wen1)
enableout1=1;
else
if(ren&&(read_p<write_p-1))
enableout1=1;
else
enableout1=0;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
mapper_p=0;
else if(ren&&mapper_p<number_mapper)
begin
if(counter4<number_mapper+1)
begin
if(counter3==1)
mapper_p=mapper_p+1;
else
mapper_p=mapper_p;
end
else
mapper_p=mapper_p+1;
end
else
begin
if(counter4<number_mapper+1)
mapper_p=mapper_p;
else
mapper_p=1;
end
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter4=0;
else if(ren&&(counter3==1)&&(counter4<number_mapper+1))
counter4=counter4+1;
else
counter4=counter4;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter3=1;
else if(ren&&counter3<4)
counter3=counter3+1;
else
counter3=1;
end
always@(posedge clk,negedge reset)
begin
if(!ren)
counter2=0;
else if(ren&&counter2<(4*number_mapper))
counter2=counter2+1;
else
counter2=counter2;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
read_p=3;
else if(ren&&(read_p<write_p)&&(read_p<FIFO_depth)&&counter1==2)
begin
if(read_p<7)
read_p<=read_p+1;
else if(read_p==7&&(counter2!=(4*number_mapper)))
read_p=4;
else
read_p=read_p+1;
end
else
read_p=read_p;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else if(ren&&(read_p<=write_p)&&(enableout1==1)&&counter1==2)
dataout1=memory[read_p];
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
write_p=0;
else
if(enablein&&(write_p<FIFO_depth-1))
write_p=write_p+1;
else
write_p=write_p;
end
always@(posedge clk)
begin
if(wen1&&enablein==1)
memory[write_p]=datain;
datain1=datain;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter=0;
else if(wen1&&!ren&&(counter!=FIFO_depth))
counter=counter+1;
else if(ren&&!wen1&&(counter!=0))
counter=counter-1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
keywordnumber=0;
else if (write_p>=3)
keywordnumber=memory[2];
else
keywordnumber=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
textfilenumber=0;
else if (write_p>=4)
textfilenumber=memory[3];
else
textfilenumber=0;
end
//*************
reg end_f;
always@(posedge clk or negedge reset)
if(!reset)
end_f <= 0;
else if(datain == 32'hffffffff)
end_f <= 1'b1;
else
end_f <= end_f;
//*************
assign full=(counter==(FIFO_depth-1));
assign empty=(counter==0);
//
//assign dataout[31:0]=dataout1;
//assign dataout[33:32]=routeraddress;
assign dataout[35:4]=dataout1;
assign dataout[3:0]=routeraddress;
//
assign enableout=enableout1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100000 + 10]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { long long k; cin >> k; for (int i = 1; i <= k; i++) cin >> a[i]; sort(a + 1, a + k + 1); int ans = 1; for (int i = 1; i < k; i++) { if (a[i] != a[i + 1]) { ans++; continue; } } cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_SYMBOL_V
`define SKY130_FD_SC_LS__DFBBN_SYMBOL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_SYMBOL_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29442 $
// $Date: 2012-08-27 21:58:10 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module ResetToBool( RST, VAL);
input RST;
output VAL;
assign VAL = (RST == `BSV_RESET_VALUE);
endmodule
|
//----------------------------------------------------------------------------
// xps_icapi_core.vhd - module
//----------------------------------------------------------------------------
`timescale 1 ns / 1 ns
module xps_icapi_core #(
// -- DO NOT EDIT BELOW THIS LINE ------------------
parameter C_SPLB_NATIVE_DWIDTH = 128,
parameter C_MPLB_NATIVE_DWIDTH = 128,
parameter C_FAMILY = "virtex5",
// -- DO NOT EDIT ABOVE THIS LINE ------------------
// -- ADD USER PARAMETERS BELOW THIS LINE ----------
parameter C_MEM_BASEADDR = 'hffffffff,
parameter C_MEM_HIGHADDR = 'h00000000,
parameter C_RESIM = 1
// -- ADD USER PARAMETERS ABOVE THIS LINE ----------
)
(
// -- DO NOT EDIT BELOW THIS LINE ------------------
input Bus2IP_Clk,
input Bus2IP_Reset,
input [31:0] Bus2IP_Addr,
input Bus2IP_CS,
input Bus2IP_RNW,
input [C_SPLB_NATIVE_DWIDTH-1:0] Bus2IP_Data,
input [C_SPLB_NATIVE_DWIDTH/8-1:0] Bus2IP_BE,
input Bus2IP_Burst,
input [8:0] Bus2IP_BurstLength,
input Bus2IP_RdReq,
input Bus2IP_WrReq,
output IP2Bus_AddrAck,
output [C_SPLB_NATIVE_DWIDTH-1:0] IP2Bus_Data,
output IP2Bus_RdAck,
output IP2Bus_WrAck,
output IP2Bus_Error,
input Bus2IP_Mst_Clk,
input Bus2IP_Mst_Reset,
output IP2Bus_MstRd_Req,
output IP2Bus_MstWr_Req,
output [31:0] IP2Bus_Mst_Addr,
output [C_MPLB_NATIVE_DWIDTH/8-1:0] IP2Bus_Mst_BE,
output [11:0] IP2Bus_Mst_Length,
output IP2Bus_Mst_Type,
output IP2Bus_Mst_Lock,
output IP2Bus_Mst_Reset,
input Bus2IP_Mst_CmdAck,
input Bus2IP_Mst_Cmplt,
input Bus2IP_Mst_Error,
input Bus2IP_Mst_Rearbitrate,
input Bus2IP_Mst_Cmd_Timeout,
input [C_MPLB_NATIVE_DWIDTH-1:0] Bus2IP_MstRd_d,
input [C_MPLB_NATIVE_DWIDTH/8-1:0] Bus2IP_MstRd_rem,
input Bus2IP_MstRd_sof_n,
input Bus2IP_MstRd_eof_n,
input Bus2IP_MstRd_src_rdy_n,
input Bus2IP_MstRd_src_dsc_n,
output IP2Bus_MstRd_dst_rdy_n,
output IP2Bus_MstRd_dst_dsc_n,
output [C_MPLB_NATIVE_DWIDTH-1:0] IP2Bus_MstWr_d,
output [C_MPLB_NATIVE_DWIDTH/8-1:0] IP2Bus_MstWr_rem,
output IP2Bus_MstWr_sof_n,
output IP2Bus_MstWr_eof_n,
output IP2Bus_MstWr_src_rdy_n,
output IP2Bus_MstWr_src_dsc_n,
input Bus2IP_MstWr_dst_rdy_n,
input Bus2IP_MstWr_dst_dsc_n,
// -- DO NOT EDIT ABOVE THIS LINE ------------------
// -- ADD USER PORTS BELOW THIS LINE ---------------
input ICAP_Clk,
output IP2INTC_Irpt
// -- ADD USER PORTS ABOVE THIS LINE ---------------
); // xps_icapi_core
wire rc_start;
wire rc_bop;
wire [31:0] rc_baddr;
wire [31:0] rc_bsize;
wire rc_done;
wire ma_req;
wire xbm_gnt;
wire ma_select;
wire [31:0] ma_addr;
wire [31:0] ma_data;
wire ma_rnw;
wire [3:0] ma_be;
wire xbm_ack;
wire [31:0] xbm_data;
// ICAPI_REGS Instance
// -------------------------------------------------
icapi_regs #(
.C_DWIDTH ( C_SPLB_NATIVE_DWIDTH ),
.C_MEM_BASEADDR ( C_MEM_BASEADDR ),
.C_MEM_HIGHADDR ( C_MEM_HIGHADDR )
) icapi_regs_0 (
.Bus2IP_Clk ( Bus2IP_Clk ),
.Bus2IP_Reset ( Bus2IP_Reset ),
.Bus2IP_Addr ( Bus2IP_Addr ),
.Bus2IP_CS ( Bus2IP_CS ),
.Bus2IP_RNW ( Bus2IP_RNW ),
.Bus2IP_Data ( Bus2IP_Data ),
.Bus2IP_BE ( Bus2IP_BE ),
.Bus2IP_Burst ( Bus2IP_Burst ),
.Bus2IP_BurstLength ( Bus2IP_BurstLength ),
.Bus2IP_RdReq ( Bus2IP_RdReq ),
.Bus2IP_WrReq ( Bus2IP_WrReq ),
.IP2Bus_AddrAck ( IP2Bus_AddrAck ),
.IP2Bus_Data ( IP2Bus_Data ),
.IP2Bus_RdAck ( IP2Bus_RdAck ),
.IP2Bus_WrAck ( IP2Bus_WrAck ),
.IP2Bus_Error ( IP2Bus_Error ),
.rc_start ( rc_start ),
.rc_bop ( rc_bop ),
.rc_baddr ( rc_baddr ),
.rc_bsize ( rc_bsize ),
.rc_done ( rc_done ),
.IP2INTC_Irpt ( IP2INTC_Irpt )
);
// ICAPI_MASTERIF Instance
// -------------------------------------------------
xbus_masterif #(
.C_DWIDTH ( C_MPLB_NATIVE_DWIDTH )
) icapi_masterif_0 (
.Bus2IP_Mst_Clk ( Bus2IP_Mst_Clk ),
.Bus2IP_Mst_Reset ( Bus2IP_Mst_Reset ),
.IP2Bus_MstRd_Req ( IP2Bus_MstRd_Req ),
.IP2Bus_MstWr_Req ( IP2Bus_MstWr_Req ),
.IP2Bus_Mst_Addr ( IP2Bus_Mst_Addr ),
.IP2Bus_Mst_Length ( IP2Bus_Mst_Length ),
.IP2Bus_Mst_BE ( IP2Bus_Mst_BE ),
.IP2Bus_Mst_Type ( IP2Bus_Mst_Type ),
.IP2Bus_Mst_Lock ( IP2Bus_Mst_Lock ),
.IP2Bus_Mst_Reset ( IP2Bus_Mst_Reset ),
.Bus2IP_Mst_CmdAck ( Bus2IP_Mst_CmdAck ),
.Bus2IP_Mst_Cmplt ( Bus2IP_Mst_Cmplt ),
.Bus2IP_Mst_Error ( Bus2IP_Mst_Error ),
.Bus2IP_Mst_Rearbitrate ( Bus2IP_Mst_Rearbitrate ),
.Bus2IP_Mst_Cmd_Timeout ( Bus2IP_Mst_Cmd_Timeout ),
.Bus2IP_MstRd_d ( Bus2IP_MstRd_d ),
.Bus2IP_MstRd_rem ( Bus2IP_MstRd_rem ),
.Bus2IP_MstRd_sof_n ( Bus2IP_MstRd_sof_n ),
.Bus2IP_MstRd_eof_n ( Bus2IP_MstRd_eof_n ),
.Bus2IP_MstRd_src_rdy_n ( Bus2IP_MstRd_src_rdy_n ),
.Bus2IP_MstRd_src_dsc_n ( Bus2IP_MstRd_src_dsc_n ),
.IP2Bus_MstRd_dst_rdy_n ( IP2Bus_MstRd_dst_rdy_n ),
.IP2Bus_MstRd_dst_dsc_n ( IP2Bus_MstRd_dst_dsc_n ),
.IP2Bus_MstWr_d ( IP2Bus_MstWr_d ),
.IP2Bus_MstWr_rem ( IP2Bus_MstWr_rem ),
.IP2Bus_MstWr_sof_n ( IP2Bus_MstWr_sof_n ),
.IP2Bus_MstWr_eof_n ( IP2Bus_MstWr_eof_n ),
.IP2Bus_MstWr_src_rdy_n ( IP2Bus_MstWr_src_rdy_n ),
.IP2Bus_MstWr_src_dsc_n ( IP2Bus_MstWr_src_dsc_n ),
.Bus2IP_MstWr_dst_rdy_n ( Bus2IP_MstWr_dst_rdy_n ),
.Bus2IP_MstWr_dst_dsc_n ( Bus2IP_MstWr_dst_dsc_n ),
.ma_req ( ma_req ),
.xbm_gnt ( xbm_gnt ),
.ma_select ( ma_select ),
.ma_addr ( ma_addr ),
.ma_data ( ma_data ),
.ma_rnw ( ma_rnw ),
.ma_be ( ma_be ),
.xbm_ack ( xbm_ack ),
.xbm_data ( xbm_data )
);
// ICAPI Instance
// -------------------------------------------------
icapi #(
.C_DWIDTH ( 32 ),
.C_RESIM ( C_RESIM ),
.C_FAMILY ( C_FAMILY )
) icapi_0 (
.clk ( ICAP_Clk ), // TODO: cross-clock domain
.rstn ( ~Bus2IP_Reset ), // TODO: low-active reset
.rc_start ( rc_start ),
.rc_bop ( rc_bop ),
.rc_baddr ( rc_baddr ),
.rc_bsize ( rc_bsize ),
.rc_done ( rc_done ),
.ma_req ( ma_req ),
.xbm_gnt ( xbm_gnt ),
.ma_select ( ma_select ),
.ma_addr ( ma_addr ),
.ma_data ( ma_data ),
.ma_rnw ( ma_rnw ),
.ma_be ( ma_be ),
.xbm_ack ( xbm_ack ),
.xbm_data ( xbm_data )
);
endmodule
|
//-- //////////////////////////////////////////////////////////////////////////////
//-- /// Copyright (c) 2013, Jahanzeb Ahmad
//-- /// All rights reserved.
//-- ///
//-- /// Redistribution and use in source and binary forms, with or without modification,
//-- /// are permitted provided that the following conditions are met:
//-- ///
//-- /// * Redistributions of source code must retain the above copyright notice,
//-- /// this list of conditions and the following disclaimer.
//-- /// * Redistributions in binary form must reproduce the above copyright notice,
//-- /// this list of conditions and the following disclaimer in the documentation and/or
//-- /// other materials provided with the distribution.
//-- ///
//-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
//-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
//-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
//-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
//-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
//-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
//-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
//-- /// POSSIBILITY OF SUCH DAMAGE.
//-- ///
//-- ///
//-- /// * http://opensource.org/licenses/MIT
//-- /// * http://copyfree.org/licenses/mit/license.txt
//-- ///
//-- //////////////////////////////////////////////////////////////////////////////
module HeaderRam(d, waddr, raddr, we, clk, q);
output [7:0] q;
input [7:0] d;
input[9:0] raddr;
input[9:0] waddr;
input clk, we;
reg [9:0] read_addr;
reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;
initial $readmemh("..//hdl//jpeg_encoder//design//header.hex", mem);
assign q = mem[read_addr];
always @(posedge clk) begin
if (we)
mem[waddr] <= d;
read_addr <= raddr;
end
endmodule
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module maxi_test (/*AUTOARG*/
// Outputs
ERROR, DONE, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
m_axi_awvalid, m_axi_awqos, m_axi_wid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
m_axi_arcache, m_axi_arprot, m_axi_arvalid, m_axi_arqos,
m_axi_rready,
// Inputs
m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid
);
// Parameters (connect to DUT slave)
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter SSTW = 8; //Number of strobes
localparam DELAYSTART_W = 100;
localparam DELAYSTART_R = 200;
/*****************************/
/*TESTBENCH SIGNALS */
/*****************************/
output ERROR;
output DONE;
/*****************************/
/*AXI MASTER I/F */
/*****************************/
//Global signals
input m_axi_aclk; //clock source for axi master/slave interfaces
input m_axi_aresetn; //asynchronous reset signal, active low
//Write address channel
output [SIDW-1:0] m_axi_awid; //write address ID
output [SAW-1:0] m_axi_awaddr; //write address
output [3:0] m_axi_awlen; //burst length (number of data transfers)
output [2:0] m_axi_awsize; //burst size (size of each transfer)
output [1:0] m_axi_awburst; //burst type
output [1:0] m_axi_awlock; //lock type (atomic characteristics)
output [3:0] m_axi_awcache; //memory type
output [2:0] m_axi_awprot; //protection type
output m_axi_awvalid; //write address valid
output [3:0] m_axi_awqos; //quality of service default 4'b0000
input m_axi_awready; //write address ready
//Write data channel
output [SIDW-1:0] m_axi_wid; //write ID tag (supported only in AXI3)
output [SDW-1:0] m_axi_wdata; //write data
output [SSTW-1:0] m_axi_wstrb; //write strobes
output m_axi_wlast; //indicates last write transfer in burst
output m_axi_wvalid; //write valid
input m_axi_wready; //write ready
//Bufered write response channel
input [SIDW-1:0] m_axi_bid; //response ID tag
input [1:0] m_axi_bresp; //write response
input m_axi_bvalid; //write response valid
output m_axi_bready; //write ready
//Read address channel
output [SIDW-1:0] m_axi_arid; //read address ID
output [SAW-1:0] m_axi_araddr; //read address
output [3:0] m_axi_arlen; //burst length (number of data transfers)
output [2:0] m_axi_arsize; //burst size (size of each transfer)
output [1:0] m_axi_arburst; //burst type
output [1:0] m_axi_arlock; //lock type (atomic characteristics)
output [3:0] m_axi_arcache; //memory type
output [2:0] m_axi_arprot; //protection type
output m_axi_arvalid; //read address valid
output [3:0] m_axi_arqos; //quality of service default 4'b0000
input m_axi_arready; //read address ready
//Read data channel
input [SIDW-1:0] m_axi_rid; //read ID tag
input [SDW-1:0] m_axi_rdata; //read data
input [1:0] m_axi_rresp; //read response
input m_axi_rlast; //indicates last read transfer in burst
input m_axi_rvalid; //read valid
output m_axi_rready; //read ready
/***************************************/
/* Extend local resets by delay values */
/***************************************/
reg resetn_w;
reg resetn_r;
integer count;
always @ (posedge m_axi_aclk or negedge m_axi_aresetn) begin
if(~m_axi_aresetn) begin
resetn_w <= 1'b0;
resetn_r <= 1'b0;
count <= 0;
end else begin
count <= count + 1;
if(count == DELAYSTART_W)
resetn_w <= 1'b1;
if(count == DELAYSTART_R)
resetn_r <= 1'b1;
end
end
/******************************/
/* Write sequential addresses */
/******************************/
wire [SIDW-1:0] m_axi_awid = {SIDW{1'b0}}; // Fixed ID
reg [SAW-1:0] m_axi_awaddr; // Incrementing Address
wire [3:0] m_axi_awlen = 4'd0; // Single beat (no burst for now)
wire [2:0] m_axi_awsize = 3'd2; // 4 Bytes / beat
wire [1:0] m_axi_awburst = 2'd1; // Incrementing Burst Type
wire [1:0] m_axi_awlock = 2'b00; // Normal access (AXI4 uses only 1 bit?)
wire [3:0] m_axi_awcache = 4'b0011; // Modifiable, Bufferable, but not cacheable
wire [2:0] m_axi_awprot = 3'b010; // Data, Non-secure, Unprivileged
reg m_axi_awvalid; // Valid
wire [3:0] m_axi_awqos = 4'd0; // Default QoS
always @ (posedge m_axi_aclk or negedge resetn_w) begin
if(~resetn_w) begin
m_axi_awaddr <= {SAW{1'b0}};
m_axi_awvalid <= 1'b0;
end else begin
m_axi_awvalid <= 1'b1;
if(m_axi_awready)
m_axi_awaddr <= m_axi_awaddr + 4;
end
end // TODO: Add optional gaps between 'valid's
//Write data channel
wire [SIDW-1:0] m_axi_wid = {SIDW{1'b0}}; // Fixed ID
reg [SDW-1:0] m_axi_wdata; // Decrementing Data
wire [SSTW-1:0] m_axi_wstrb = {SSTW{1'b1}}; // Byte Lanes
wire m_axi_wlast = 1'b1; // Single beat per transfer, always last
reg m_axi_wvalid;
always @ (posedge m_axi_aclk or negedge resetn_w) begin
if(~resetn_w) begin
m_axi_wdata <= {SDW{1'b1}};
m_axi_wvalid <= 1'b0;
end else begin
m_axi_wvalid <= 1'b1;
if(m_axi_wready)
m_axi_wdata <= m_axi_wdata - 1;
end
end
//Buffered write response channel
wire m_axi_bready = 1'b1; // always ready for now
//Read address channel
wire [SIDW-1:0] m_axi_arid = {SIDW{1'b0}}; // ID unused
reg [SAW-1:0] m_axi_araddr;
wire [3:0] m_axi_arlen = 4'd0; // Single beat per transfer
wire [2:0] m_axi_arsize = 3'd2; // 4 bytes / beat
wire [1:0] m_axi_arburst = 2'd1; // Incrementing Burst Type
wire [1:0] m_axi_arlock = 2'b00; // Normal access (AXI4 uses only 1 bit?)
wire [3:0] m_axi_arcache = 4'b0011; // Modifiable, Bufferable, but not cacheable
wire [2:0] m_axi_arprot = 3'b010; // Data, Non-secure, Unprivileged
reg m_axi_arvalid; //read address valid
wire [3:0] m_axi_arqos = 4'd0; // Default QoS
always @ (posedge m_axi_aclk or negedge resetn_r) begin
if(~resetn_r) begin
m_axi_araddr <= {SAW{1'b0}};
m_axi_arvalid <= 1'b0;
end else begin
m_axi_arvalid <= 1'b1;
if(m_axi_arready)
m_axi_araddr <= m_axi_araddr + 8;
end
end // TODO: Add optional gaps between 'valid's
//Read data channel
wire m_axi_rready = 1'b1; // Always Ready for now
endmodule // maxi_test
// Local Variables:
// verilog-library-directories:("." "../elink" "../axi")
// End:
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
wr_data_gen #(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using vi = vector<int>; struct ele { int value, jj, index; }; bool ordena(ele a, ele b) { return a.value < b.value; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int k, n; cin >> k; vector<ele> arr; for (int i = 0; i < k; i++) { int v[200010], sum = 0; cin >> n; for (int j = 0; j < n; j++) { cin >> v[j]; sum += v[j]; } for (int j = 0; j < n; j++) { ele myele; myele.value = sum - v[j]; myele.jj = j; myele.index = i; arr.push_back(myele); } } sort(arr.begin(), arr.end(), ordena); for (int i = 0; i < arr.size() - 1; i++) { if (arr[i].value == arr[i + 1].value && arr[i].index != arr[i + 1].index) { cout << YES << n ; cout << arr[i].index + 1 << << arr[i].jj + 1 << n ; cout << arr[i + 1].index + 1 << << arr[i + 1].jj + 1 << n ; return 0; } } cout << NO << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; map<string, string> p; int ans = 0; string tmp = abcdef ; void doit(int n, string s) { if (n == 0) { int f = 0; while (true) { if (s.length() == 2) { if (p.find(s) == p.end()) { f = 1; break; } if (p[s] != a ) { f = 1; } break; } string s1 = s.substr(0, 2); string s2 = ; if (s.length() > 2) { s2 += s.substr(2, s.length() - 2); } if (p.find(s1) == p.end()) { f = 1; break; } else { s = p[s1] + s2; } } if (f == 0) ans++; return; } for (int i = 0; i < 6; i++) { string tmp1 = s; tmp1.push_back(tmp[i]); doit(n - 1, tmp1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, q; cin >> n >> q; for (int i = 0; i < q; i++) { string s1, s2; cin >> s1 >> s2; p.insert(make_pair(s1, s2)); } for (int i = 0; i < 6; i++) { string s; s.push_back(tmp[i]); doit(n - 1, s); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000000 + 10; int tot; vector<int> primes; int notP[N]; vector<long long> divisors[N]; map<pair<long long, int>, int> dp; int isP(long long x) { for (int i = 0; (long long)primes[i] * primes[i] <= x; ++i) { if (x % primes[i] == 0) return false; } return true; } int dfs(long long x, int cur) { if (dp.count(make_pair(x, cur))) { return dp[make_pair(x, cur)]; } int &ret = dp[make_pair(x, cur)]; if (cur == tot) { if (x == 1) { ret++; } else if (x > N) { ret += isP(x - 1); } return ret; } ret += dfs(x, cur + 1); for (int i = 0; i < divisors[cur].size(); ++i) { if (x % divisors[cur][i] == 0) { ret += dfs(x / divisors[cur][i], cur + 1); } } return ret; } void solve() { long long n; cin >> n; tot = 0; for (int i = 0; i < primes.size(); ++i) { int prime = primes[i]; int flag = false; for (long long tmp = prime; tmp < n; tmp *= prime) { if (n % (tmp + 1) == 0) { if (!flag) { flag = true; ++tot; } divisors[tot - 1].push_back(tmp + 1); } } } cout << dfs(n, 0) << endl; } int main() { for (int i = 2; i < N; ++i) { if (notP[i]) continue; primes.push_back(i); for (long long j = (long long)i * i; j < N; j += i) { notP[j] = true; } } solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_PP_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : MC Interface address generation
// File : de3d_tc_mem_if_addr.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_mem_if_addr
(
input [8:0] ul_store_x, /* UL x address */
input [8:0] ul_store_y, /* UL y address */
input [8:0] ll_store_x, /* LL x address */
input [8:0] ll_store_y, /* LL y address */
input [8:0] ur_store_x, /* UR x address */
input [8:0] ur_store_y, /* UR y address */
input [8:0] lr_store_x, /* LR x address */
input [8:0] lr_store_y, /* LR y address */
input [2:0] bank, /* Bank of ram that we are addressing */
input [2:0] bpt, /* Texture map size */
input tc_ready, /* Texture cache in read mode */
input [7:0] ram_addr, /* address for exact mode */
input [3:0] set_read, /* selects which set to read. */
output reg [7:0] addr_out /* address to specified RAM */
);
wire ul_lru_read = set_read[3];
wire ll_lru_read = set_read[2];
wire ur_lru_read = set_read[1];
wire lr_lru_read = set_read[0];
always @* begin
case (bpt) /* synopsys parallel_case */
/* access a memory location *********************************************/
/* 1 bpt ****************************************************************/
/* 2 bpt ****************************************************************/
/* 4 bpt ****************************************************************/
/* 8 bpt ****************************************************************/
3'h3: begin
if ({(ul_store_x[4] ^ ul_store_y[0]),ul_store_x[3:2]} == bank)
addr_out={ul_lru_read,ul_store_y[5:0],ul_store_x[5]};
else if ({(ll_store_x[4] ^ ll_store_y[0]),ll_store_x[3:2]} == bank)
addr_out={ll_lru_read,ll_store_y[5:0],ll_store_x[5]};
else if ({(ur_store_x[4] ^ ur_store_y[0]),ur_store_x[3:2]} == bank)
addr_out={ur_lru_read,ur_store_y[5:0],ur_store_x[5]};
else if ({(lr_store_x[4] ^ lr_store_y[0]),lr_store_x[3:2]} == bank)
addr_out={lr_lru_read,lr_store_y[5:0],lr_store_x[5]};
else addr_out = 8'hff;
end
/* 16 bpt ***************************************************************/
3'h4: begin
if ({(ul_store_x[3] ^ ul_store_y[0]),ul_store_x[2:1]} == bank)
addr_out={ul_lru_read,ul_store_y[4:0],ul_store_x[5:4]};
else if ({(ll_store_x[3] ^ ll_store_y[0]),ll_store_x[2:1]} == bank)
addr_out={ll_lru_read,ll_store_y[4:0],ll_store_x[5:4]};
else if ({(ur_store_x[3] ^ ur_store_y[0]),ur_store_x[2:1]} == bank)
addr_out={ur_lru_read,ur_store_y[4:0],ur_store_x[5:4]};
else if ({(lr_store_x[3] ^ lr_store_y[0]),lr_store_x[2:1]} == bank)
addr_out={lr_lru_read,lr_store_y[4:0],lr_store_x[5:4]};
else addr_out = 8'hff;
end
/* 32 bpt ***************************************************************/
default:
begin
if ({(ul_store_x[2] ^ ul_store_y[0]),ul_store_x[1:0]} == bank)
addr_out={ul_lru_read,ul_store_y[3:0],ul_store_x[5:3]};
else if ({(ll_store_x[2] ^ ll_store_y[0]),ll_store_x[1:0]} == bank)
addr_out={ll_lru_read,ll_store_y[3:0],ll_store_x[5:3]};
else if ({(ur_store_x[2] ^ ur_store_y[0]),ur_store_x[1:0]} == bank)
addr_out={ur_lru_read,ur_store_y[3:0],ur_store_x[5:3]};
else if ({(lr_store_x[2] ^ lr_store_y[0]),lr_store_x[1:0]} == bank)
addr_out={lr_lru_read,lr_store_y[3:0],lr_store_x[5:3]};
else addr_out = 8'hff;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A21BO_FUNCTIONAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21bo (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_8_V
`define SKY130_FD_SC_HDLL__OR2_8_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_8 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_8 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_8_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:11:00 12/11/2012
// Design Name: top
// Module Name: E:/Documents/FPGA/SPIloop/tb.v
// Project Name: SPIloop
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb;
// Inputs
reg clk;
reg rst;
reg [7:0] din;
reg wen;
reg rd;
// Outputs
wire [7:0] dout;
wire rdy;
// Instantiate the Unit Under Test (UUT)
top uut (
.clk(clk),
.rst(rst),
.din(din),
.wen(wen),
.dout(dout),
.rdy(rdy),
.rd(rd)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
din = 0;
wen = 0;
rd = 0;
// Wait 100 ns for global reset to finish
rst = 1;
#100;
rst = 0;
// Add stimulus here
din = 8'h65;
wen = 1;
#40;
wen = 0;
end
always begin
#20 clk = ~clk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_SYMBOL_V
`define SKY130_FD_SC_HD__AND4B_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; vector<int> a[maxn]; string s; int i, ma = -1, ans = 0, f = 1; int main() { cin >> s; for (i = 0; i < s.size(); i++) { if (s[i] == 0 ) a[++ans].push_back(i); else { if (ans == 0) { f = 0; break; } a[ans--].push_back(i); } ma = max(ans, ma); } if (ma != ans) f = 0; if (!f) { cout << -1; return 0; } else { cout << ma << n ; for (i = 1; i <= ma; i++) { cout << a[i].size() << ; for (int j = 0; j < a[i].size(); j++) { cout << a[i][j] + 1 << ; } cout << n ; } } }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_iobuf32(
input [31:0] T,
input [31:0] I,
output [31:0] O,
inout [31:0] IO
);
IOBUF iobuf0(
.T(T[0]),
.I(I[0]),
.O(O[0]),
.IO(IO[0])
);
IOBUF iobuf1(
.T(T[1]),
.I(I[1]),
.O(O[1]),
.IO(IO[1])
);
IOBUF iobuf2(
.T(T[2]),
.I(I[2]),
.O(O[2]),
.IO(IO[2])
);
IOBUF iobuf3(
.T(T[3]),
.I(I[3]),
.O(O[3]),
.IO(IO[3])
);
IOBUF iobuf4(
.T(T[4]),
.I(I[4]),
.O(O[4]),
.IO(IO[4])
);
IOBUF iobuf5(
.T(T[5]),
.I(I[5]),
.O(O[5]),
.IO(IO[5])
);
IOBUF iobuf6(
.T(T[6]),
.I(I[6]),
.O(O[6]),
.IO(IO[6])
);
IOBUF iobuf7(
.T(T[7]),
.I(I[7]),
.O(O[7]),
.IO(IO[7])
);
IOBUF iobuf8(
.T(T[8]),
.I(I[8]),
.O(O[8]),
.IO(IO[8])
);
IOBUF iobuf9(
.T(T[9]),
.I(I[9]),
.O(O[9]),
.IO(IO[9])
);
IOBUF iobuf10(
.T(T[10]),
.I(I[10]),
.O(O[10]),
.IO(IO[10])
);
IOBUF iobuf11(
.T(T[11]),
.I(I[11]),
.O(O[11]),
.IO(IO[11])
);
IOBUF iobuf12(
.T(T[12]),
.I(I[12]),
.O(O[12]),
.IO(IO[12])
);
IOBUF iobuf13(
.T(T[13]),
.I(I[13]),
.O(O[13]),
.IO(IO[13])
);
IOBUF iobuf14(
.T(T[14]),
.I(I[14]),
.O(O[14]),
.IO(IO[14])
);
IOBUF iobuf15(
.T(T[15]),
.I(I[15]),
.O(O[15]),
.IO(IO[15])
);
IOBUF iobuf16(
.T(T[16]),
.I(I[16]),
.O(O[16]),
.IO(IO[16])
);
IOBUF iobuf17(
.T(T[17]),
.I(I[17]),
.O(O[17]),
.IO(IO[17])
);
IOBUF iobuf18(
.T(T[18]),
.I(I[18]),
.O(O[18]),
.IO(IO[18])
);
IOBUF iobuf19(
.T(T[19]),
.I(I[19]),
.O(O[19]),
.IO(IO[19])
);
IOBUF iobuf20(
.T(T[20]),
.I(I[20]),
.O(O[20]),
.IO(IO[20])
);
IOBUF iobuf21(
.T(T[21]),
.I(I[21]),
.O(O[21]),
.IO(IO[21])
);
IOBUF iobuf22(
.T(T[22]),
.I(I[22]),
.O(O[22]),
.IO(IO[22])
);
IOBUF iobuf23(
.T(T[23]),
.I(I[23]),
.O(O[23]),
.IO(IO[23])
);
IOBUF iobuf24(
.T(T[24]),
.I(I[24]),
.O(O[24]),
.IO(IO[24])
);
IOBUF iobuf25(
.T(T[25]),
.I(I[25]),
.O(O[25]),
.IO(IO[25])
);
IOBUF iobuf26(
.T(T[26]),
.I(I[26]),
.O(O[26]),
.IO(IO[26])
);
IOBUF iobuf27(
.T(T[27]),
.I(I[27]),
.O(O[27]),
.IO(IO[27])
);
IOBUF iobuf28(
.T(T[28]),
.I(I[28]),
.O(O[28]),
.IO(IO[28])
);
IOBUF iobuf29(
.T(T[29]),
.I(I[29]),
.O(O[29]),
.IO(IO[29])
);
IOBUF iobuf30(
.T(T[30]),
.I(I[30]),
.O(O[30]),
.IO(IO[30])
);
IOBUF iobuf31(
.T(T[31]),
.I(I[31]),
.O(O[31]),
.IO(IO[31])
);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module dsp_t1_20x18x64 (
input [19:0] a_i,
input [17:0] b_i,
input [ 3:0] acc_fir_i,
output [37:0] z_o,
output [17:0] dly_b_o,
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
parameter [19:0] COEFF_1 = 20'd0;
parameter [19:0] COEFF_2 = 20'd0;
parameter [19:0] COEFF_3 = 20'd0;
QL_DSP2 # (
.COEFF_0 (COEFF_0),
.COEFF_1 (COEFF_1),
.COEFF_2 (COEFF_2),
.COEFF_3 (COEFF_3)
) _TECHMAP_REPLACE_ (
.a (a_i),
.b (b_i),
.acc_fir (acc_fir_i),
.z (z_o),
.dly_b (dly_b_o),
.clk (clock_i),
.reset (reset_i),
.feedback (feedback_i),
.load_acc (load_acc_i),
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b0), // No fracturation
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
.round (round_i),
.subtract (subtract_i),
.register_inputs (register_inputs_i)
);
endmodule
module dsp_t1_10x9x32 (
input [ 9:0] a_i,
input [ 8:0] b_i,
input [ 1:0] acc_fir_i,
output [18:0] z_o,
output [ 8:0] dly_b_o,
(* clkbuf_sink *)
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i,
input [ 9:0] coeff_0_i,
input [ 9:0] coeff_1_i,
input [ 9:0] coeff_2_i,
input [ 9:0] coeff_3_i
);
parameter [9:0] COEFF_0 = 10'd0;
parameter [9:0] COEFF_1 = 10'd0;
parameter [9:0] COEFF_2 = 10'd0;
parameter [9:0] COEFF_3 = 10'd0;
wire [37:0] z;
wire [17:0] dly_b;
QL_DSP2 # (
.COEFF_0 ({10'd0, COEFF_0}),
.COEFF_1 ({10'd0, COEFF_1}),
.COEFF_2 ({10'd0, COEFF_2}),
.COEFF_3 ({10'd0, COEFF_3})
) _TECHMAP_REPLACE_ (
.a ({10'd0, a_i}),
.b ({ 9'd0, b_i}),
.acc_fir ({ 2'd0, acc_fir_i}),
.z (z),
.dly_b (dly_b),
.clk (clock_i),
.reset (reset_i),
.feedback (feedback_i),
.load_acc (load_acc_i),
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b1), // Enable fractuation, Use the lower half
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
.round (round_i),
.subtract (subtract_i),
.register_inputs (register_inputs_i)
);
assign z_o = z[18:0];
assign dly_b_o = dly_b_o[8:0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
|
`include "../RF/reg_file2.v"
module test;
reg [4:0] readReg1, readReg2, writeReg;
reg [31:0] writeData;
reg regWrite, clk;
wire [31:0] readData1, readData2;
reg_file rf(.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.regWrite(regWrite),
.clk(clk),
.readData1(readData1),
.readData2(readData2));
initial begin
$dumpfile("reg_file_wave.vcd");
$dumpvars(0, test);
//$monitor($time, ": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d",
// readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
clk = 0;
#5 writeReg = 0; writeData = 10; regWrite = 1;
#5 writeReg = 5;
#5 writeReg = 6;
#5 writeReg = 17;
#5 writeReg = 18;
#5 writeReg = 19;
#5 writeReg = 20;
#5 writeReg = 21;
#5 writeReg = 22;
#5 writeReg = 23;
#5 writeReg = 24;
#5 writeReg = 25;
#5 writeReg = 26;
#5 writeReg = 27;
#5 writeReg = 28;
#5 writeReg = 29;
#5 writeReg = 30;
#5 writeReg = 31;
#5 readReg1 = 0; readReg2 = 2;
#5;
$display(": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d",
readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
$finish;
end
always #1 clk = ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_SYMBOL_V
`define SKY130_FD_SC_HS__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Dynamic DCM Controller. Derived from sources from TheSeven at:
// https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner
// Paul Mumby 2012
//////////////////////////////////////////////////////////////////////////////////
module dcm_controller (
clk,
data2,
midstate,
start,
dcm_prog_data,
dcm_prog_clk,
dcm_prog_done,
dcm_prog_en,
identify
);
//Parameters:
//================================================
parameter MAXIMUM_MULTIPLIER = 88;
parameter MINIMUM_MULTIPLIER = 20;
parameter INITIAL_MULTIPLIER = 60;
parameter INITIAL_DIVIDER = 10;
//IO Definitions:
//================================================
input clk;
input [255:0] midstate;
input [255:0] data2;
input start;
input dcm_prog_clk;
output dcm_prog_data;
output dcm_prog_en;
input dcm_prog_done;
output identify;
//Register/Wire Definitions:
//================================================
reg dcm_prog_data = 0;
reg dcm_prog_en = 0;
wire [31:0] cmd_trigger_timestamp;
wire cmd_trigger;
wire [7:0] cmd_prefix;
wire [7:0] cmd_id;
wire [7:0] cmd_data;
wire [7:0] cmd_validator;
wire cmd_valid;
reg busy = 0;
reg [7:0] cmd_latch_id = 8'd0;
reg [7:0] cmd_latch_data = 8'd0;
reg dcm_prog_ready = 0;
reg [7:0] dcm_multiplier = INITIAL_MULTIPLIER;
reg [7:0] current_dcm_multiplier = 8'd0;
reg [4:0] dcm_progstate = 5'd31;
reg [15:0] dcm_data = 16'd0;
wire [7:0] dcm_divider_s1;
wire [7:0] dcm_multiplier_s1;
reg dcm_prog_ready_b = 0;
wire dcm_prog_busy;
reg [7:0] dcm_multiplier_b = 8'd0;
reg identify = 0;
reg [2:0] nonce_dip_bits = 3'd0;
wire [12:0] fsm_state;
//Assignments:
//================================================
assign cmd_trigger_timestamp = data2[63:32];
assign cmd_prefix = data2[231:224]; //data2 byte 29 should always be 10110111 results in xor against 01011010 with id/data
assign cmd_id = data2[239:232]; //data2 byte 30
assign cmd_data = data2[247:240]; //data2 byte 31
assign cmd_validator = data2[255:248]; //data2 byte 32
assign cmd_trigger = (cmd_trigger_timestamp == 32'hffffffff) && (midstate == 256'd0);
assign cmd_valid = cmd_validator == (cmd_prefix ^ cmd_id ^ cmd_data ^ 8'b01101101);
assign dcm_prog_busy = (dcm_progstate != 5'd31);
assign dcm_divider_s1 = INITIAL_DIVIDER-1;
assign dcm_multiplier_s1 = dcm_multiplier_b - 8'd1;
assign fsm_state = {start,cmd_trigger,cmd_valid,busy,dcm_prog_busy,cmd_latch_id};
//Toplevel Logic:
//================================================
//Main command processor/validation state machine
always @(posedge clk)
begin
casex (fsm_state)
13'b1110xxxxxxxxx: begin //(start && cmd_trigger && cmd_valid && ~busy)
//We're not busy, and We've received the start (data in from uart)
//and trigger (appropriate malformed packet)
//And the command passes it's simple validation check
//So lets decode it, latch the data, and flag busy to handle the command
cmd_latch_id <= cmd_id;
cmd_latch_data <= cmd_data;
busy <= 1; //Flag we're busy
end
13'bxxx1000000000: begin //(busy && cmd_latch_id==8'd0 && ~dcm_prog_busy)
//COMMAND: Set Clock
if(cmd_latch_data > MAXIMUM_MULTIPLIER)
dcm_multiplier <= MAXIMUM_MULTIPLIER;
else if(cmd_latch_data < MINIMUM_MULTIPLIER)
dcm_multiplier <= MINIMUM_MULTIPLIER;
else
dcm_multiplier <= cmd_latch_data;
dcm_prog_ready <= 1;
busy <= 0;
end
13'bxxx1x00000001: begin //(busy && cmd_latch_id==8'd1)
//COMMAND: Identify
identify <= cmd_latch_data[0]; //Set identify flag to first bit of command data byte.
end
13'bxxx1x00000010: begin //(busy && cmd_latch_id==8'd2)
//COMMAND: Set Nonce_DIP_Bits
nonce_dip_bits <= cmd_latch_data[2:0]; //Set number of nonce msb bits to take from chip-specific DIP switches
end
default: begin //else
dcm_prog_ready <= 0; //stop asserting prog_ready, the programmer has grabbed it by now.
end
endcase
end
//DCM Programming logic
//Mostly copied from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner
//Adapted to our specific setup
always @(posedge dcm_prog_clk)
begin
//Clock crossing buffers:
dcm_prog_ready_b <= dcm_prog_ready;
dcm_multiplier_b <= dcm_multiplier;
if (dcm_multiplier_b != current_dcm_multiplier && dcm_progstate == 5'd31 && dcm_prog_ready_b)
begin
current_dcm_multiplier <= dcm_multiplier_b;
dcm_progstate <= 5'd0;
// DCM expects D-1 and M-1
dcm_data <= {dcm_multiplier_s1, dcm_divider_s1};
end
if (dcm_progstate == 5'd0) {dcm_prog_en, dcm_prog_data} <= 2'b11;
if (dcm_progstate == 5'd1) {dcm_prog_en, dcm_prog_data} <= 2'b10;
if ((dcm_progstate >= 5'd2 && dcm_progstate <= 5'd9) || (dcm_progstate >= 5'd15 && dcm_progstate <= 5'd22))
begin
dcm_prog_data <= dcm_data[0];
dcm_data <= {1'b0, dcm_data[15:1]};
end
if (dcm_progstate == 5'd10) {dcm_prog_en, dcm_prog_data} <= 2'b00;
if (dcm_progstate == 5'd11) {dcm_prog_en, dcm_prog_data} <= 2'b00;
if (dcm_progstate == 5'd12) {dcm_prog_en, dcm_prog_data} <= 2'b00;
if (dcm_progstate == 5'd13) {dcm_prog_en, dcm_prog_data} <= 2'b11;
if (dcm_progstate == 5'd14) {dcm_prog_en, dcm_prog_data} <= 2'b11;
if (dcm_progstate == 5'd23) {dcm_prog_en, dcm_prog_data} <= 2'b00;
if (dcm_progstate == 5'd24) {dcm_prog_en, dcm_prog_data} <= 2'b00;
if (dcm_progstate == 5'd25) {dcm_prog_en, dcm_prog_data} <= 2'b10;
if (dcm_progstate == 5'd26) {dcm_prog_en, dcm_prog_data} <= 2'b00;
if (dcm_progstate <= 5'd25) dcm_progstate <= dcm_progstate + 5'd1;
if (dcm_progstate == 5'd26 && dcm_prog_done)
dcm_progstate <= 5'd31;
end
endmodule
|
#include <bits/stdc++.h> int main() { int vis[5] = {0}; int dir[5][5] = {{4, 3, 2}, {1, 4, 3}, {2, 1, 4}, {3, 2, 1}}; int viss[5] = {0}; for (int i = 0; i < 4; i++) { for (int j = 0; j < 3; j++) { int a; scanf( %d , &a); if (a) { viss[dir[i][j]] = 1; viss[i + 1] = 1; } } int b; scanf( %d , &b); if (b) vis[i + 1] = 1; } int f = 0; for (int i = 1; i <= 4; i++) { if (vis[i] && viss[i]) { f = 1; break; } } if (f) printf( YES n ); else printf( NO n ); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t, n, i, j, k, h = 0; cin >> n; long long int a[n], b[n]; for (i = 0; i < n; ++i) { cin >> a[i] >> b[i]; } if (n == 1) cout << a[0] << endl; if (n > 1) { set<long long int> s1, s, s3; set<long long int>::iterator jt, it; j = a[0]; while (j % 2 == 0) { s.insert(2); j /= 2; } for (k = 3; k <= sqrt(j); k = k + 2) { while (j % k == 0) { s.insert(k); j /= k; } } if (j > 2) s.insert(j); j = b[0]; while (j % 2 == 0) { s.insert(2); j /= 2; } for (k = 3; k <= sqrt(j); k = k + 2) { while (j % k == 0) { s.insert(k); j /= k; } } if (j > 2) s.insert(j); j = a[1]; while (j % 2 == 0) { s1.insert(2); j /= 2; } for (k = 3; k <= sqrt(j); k = k + 2) { while (j % k == 0) { s1.insert(k); j /= k; } } if (j > 2) s1.insert(j); j = b[1]; while (j % 2 == 0) { s1.insert(2); j /= 2; } for (k = 3; k <= sqrt(j); k = k + 2) { while (j % k == 0) { s1.insert(k); j /= k; } } if (j > 2) s1.insert(j); for (it = s.begin(); it != s.end(); ++it) { for (jt = s1.begin(); jt != s1.end(); jt++) { if ((*jt) % (*it) == 0) { s3.insert(*it); } else if ((*it) % (*jt) == 0) s3.insert(*jt); } } s.clear(); for (i = 2; i < n; ++i) { for (it = s3.begin(); it != s3.end(); ++it) { if (a[i] % (*it) == 0) s.insert(*it); if (b[i] % (*it) == 0) s.insert(*it); } s3.clear(); for (it = s.begin(); it != s.end(); ++it) { s3.insert(*it); } s.clear(); } if (s3.size() > 0) { for (it = s3.begin(); it != s3.end(); ++it) { cout << *it << endl; break; } } else cout << -1 n ; } return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information of Xilinx, Inc.
// and is protected under U.S. and international copyright and other
// intellectual property laws.
//
// DISCLAIMER
//
// This disclaimer is not a license and does not grant any rights to the
// materials distributed herewith. Except as otherwise provided in a valid
// license issued to you by Xilinx, and to the maximum extent permitted by
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
// and (2) Xilinx shall not be liable (whether in contract or tort, including
// negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these
// materials, including for any direct, or any indirect, special, incidental,
// or consequential loss or damage (including loss of data, profits, goodwill,
// or any type of loss or damage suffered as a result of any action brought by
// a third party) even if such damage or loss was reasonably foreseeable or
// Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
//
// Xilinx products are not designed or intended to be fail-safe, or for use in
// any application requiring fail-safe performance, such as life-support or
// safety devices or systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any other
// applications that could lead to death, personal injury, or severe property
// or environmental damage (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and liability of any use of
// Xilinx products in Critical Applications, subject only to applicable laws
// and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
// AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : pcie_bram_s6.v
// Description: BlockRAM module for Spartan-6 PCIe Block
// The BRAM A port is the write port.
// The BRAM B port is the read port.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_s6 #(
parameter DOB_REG = 0, // 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36
) (
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [11:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [11:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 11 :
(WIDTH == 9) ? 10 :
(WIDTH == 18) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
5
);
localparam WRITE_MODE_INT = "NO_CHANGE";
//synthesis translate_off
initial begin
case (WIDTH)
4,9,18,36:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
wire [31:0] di_wire, do_wire;
wire [3:0] dip_wire, dop_wire;
generate
case (WIDTH)
36: begin : width_36
assign di_wire = wdata_i[31:0];
assign dip_wire = wdata_i[35:32];
assign rdata_o = {dop_wire, do_wire};
end
18: begin : width_18
assign di_wire = {16'd0, wdata_i[15:0]};
assign dip_wire = {2'd0, wdata_i[17:16]};
assign rdata_o = {dop_wire[1:0], do_wire[15:0]};
end
9: begin : width_9
assign di_wire = {24'd0, wdata_i[7:0]};
assign dip_wire = {3'd0, wdata_i[8]};
assign rdata_o = {dop_wire[0], do_wire[7:0]};
end
4: begin : width_4
assign di_wire = {28'd0, wdata_i[3:0]};
assign dip_wire = 4'd0;
assign rdata_o = do_wire[3:0];
end
endcase
endgenerate
RAMB16BWER #(
.DATA_WIDTH_A (WIDTH),
.DATA_WIDTH_B (WIDTH),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.WRITE_MODE_A (WRITE_MODE_INT),
.WRITE_MODE_B (WRITE_MODE_INT)
) ramb16 (
.CLKA (user_clk_i),
.RSTA (reset_i),
.DOA (),
.DOPA (),
.ADDRA ({waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b0}}}),
.DIA (di_wire),
.DIPA (dip_wire),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.REGCEA (1'b0),
.CLKB (user_clk_i),
.RSTB (reset_i),
.WEB (4'd0),
.DIB (32'd0),
.DIPB (4'd0),
.ADDRB ({raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b0}}}),
.DOB (do_wire),
.DOPB (dop_wire),
.ENB (ren_i),
.REGCEB (rce_i)
);
endmodule // pcie_bram_s6
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.size(); int pref = 0; int kol = 0; for (int i = 0; i < n; i++) { if (s[i] == # ) kol++; if (s[i] == ( ) pref++; else pref--; if (pref < 0) { cout << -1 ; return 0; } } string t; int sz = 0; int r = 0; while (sz < kol) { if (s[r] == # ) { sz++; t += ) ; if (sz == kol) { for (int j = 0; j < pref; j++) t += ) ; } } else { t += s[r]; } r++; } while (r < n) { t += s[r]; r++; } n = t.size(); int preff = 0; for (int i = 0; i < n; i++) { if (t[i] == ( ) preff++; else preff--; if (preff < 0) { cout << -1 ; return 0; } } for (int i = 0; i < kol - 1; i++) { cout << 1 << endl; } cout << pref + 1; }
|
#include <bits/stdc++.h> using namespace std; int n, m; long long data[100010], diff[100010], change[100010]; vector<vector<long long> > adj; vector<pair<long long, int> > vp; int main(void) { scanf( %d%d , &n, &m); adj.resize(n + 1, vector<long long>()); for (int i = 0; i < m; i++) scanf( %I64d , &data[i]); if (m == 1) { puts( 0 ); return 0; } for (int i = 0; i < m; i++) { if (i == 0 && data[i] != data[i + 1]) adj[data[i]].push_back(data[i + 1]); else if (i == m - 1 && data[i] != data[i - 1]) adj[data[i]].push_back(data[i - 1]); else if (i > 0 && i < m - 1) { if (data[i] != data[i - 1]) adj[data[i]].push_back(data[i - 1]); if (data[i] != data[i + 1]) adj[data[i]].push_back(data[i + 1]); } } for (int i = 1; i <= n; i++) { if (adj[i].empty()) continue; long long sum = 0; sort(adj[i].begin(), adj[i].end()); long long avg1 = adj[i][adj[i].size() / 2]; long long newMid = adj[i].size() / 2 - 1; if (newMid < 0) newMid = 0; long long avg2 = adj[i][newMid]; long long sum1 = 0, sum2 = 0; for (int j = 0; j < adj[i].size(); j++) sum += abs(adj[i][j] - i); for (int j = 0; j < adj[i].size(); j++) sum1 += abs(adj[i][j] - avg1); for (int j = 0; j < adj[i].size(); j++) sum2 += abs(adj[i][j] - avg2); if (sum1 < sum2) { vp.push_back(make_pair(sum - sum1, i)); change[i] = avg1; } else { vp.push_back(make_pair(sum - sum2, i)); change[i] = avg2; } } sort(vp.begin(), vp.end()); if (vp.empty()) { puts( 0 ); return 0; } int target = vp[vp.size() - 1].second; for (int i = 0; i < m; i++) if (data[i] == target) data[i] = change[target]; long long sol = 0; for (int i = 0; i < m - 1; i++) sol += abs(data[i] - data[i + 1]); printf( %I64d n , sol); }
|
/* lab3_part1.v - A gated D latch
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab3_part2 (SW,LEDR);
input [17:0] SW;
output [17:0] LEDR;
Dflop(SW[1],SW[0],LEDR[0]);
endmodule
module Dflop (Clk, D, Q);
input Clk, D;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
/* S_g truth table
+--+---+----+
| D|Clk|S_g |
| 0| 0 | 1 |
| 0| 1 | 1 |
| 1| 0 | 1 |
| 1| 1 | 0 |
+--+---+----+
*/
assign S_g = ((~D & ~Clk) | (~D & Clk) | (D & ~Clk));
/* R_g truth table
+--+---+----+
| D|Clk|R_g |
| 0| 0 | 1 |
| 0| 1 | 0 |
| 1| 0 | 1 |
| 1| 1 | 1 |
+--+---+----+
*/
assign R_g = ((~D & ~Clk) | (D & ~Clk) | (D & Clk));
assign Qa = (R_g & ~Qb);
assign Qb = (S_g & ~Qa);
assign Q = Qa;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_2_V
`define SKY130_FD_SC_MS__OR4B_2_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_2_V
|
#include <bits/stdc++.h> using namespace std; struct he { int ind; int val; he(int ind_ = 0, int val_ = 0) : ind(ind_), val(val_) {} bool operator<(const he oth) const { return val > oth.val; } }; int n, m, k; vector<int> p[200200], c[200200]; int minv[200200], maxv[200200]; int np[200200], nc[200200]; int ans[200200]; queue<int> q; priority_queue<he> d_cand, id_cand; int main() { cin >> n >> m >> k; for (int i = 1; i <= n; ++i) { int a; cin >> a; if (a == 0) { minv[i] = 0; maxv[i] = k + 1; } else { minv[i] = a; maxv[i] = a; } } for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; p[b].push_back(a); c[a].push_back(b); } for (int i = 1; i <= n; ++i) { np[i] = p[i].size(); if (np[i] == 0) { maxv[i] = min(k, maxv[i]); q.push(i); } } int reached = 0; while (!q.empty()) { int ind = q.front(); q.pop(); ++reached; for (int x : c[ind]) { maxv[x] = min(maxv[x], maxv[ind] - 1); --np[x]; if (np[x] == 0) q.push(x); } } if (reached < n) { cout << -1 n ; return 0; } for (int i = 1; i <= n; ++i) { nc[i] = c[i].size(); if (nc[i] == 0) { id_cand.push(he(i, minv[i])); } } for (int step = 1; step <= k; ++step) { while (!id_cand.empty() && id_cand.top().val <= step) { int x = id_cand.top().ind; id_cand.pop(); d_cand.push(he(x, maxv[x])); } if (d_cand.empty()) { cout << -1 n ; return 0; } int added = 0; while (!d_cand.empty() && d_cand.top().val == step) { ++added; int x = d_cand.top().ind; d_cand.pop(); ans[x] = step; for (int y : p[x]) { --nc[y]; minv[y] = max(minv[y], step + 1); if (nc[y] == 0) { id_cand.push(he(y, minv[y])); } } } if (added == 0) { int x = d_cand.top().ind; d_cand.pop(); if (maxv[x] < step) { cout << -1 n ; return 0; } ans[x] = step; for (int y : p[x]) { --nc[y]; minv[y] = max(minv[y], step + 1); if (nc[y] == 0) { id_cand.push(he(y, minv[y])); } } } } for (int i = 1; i <= n; ++i) { cout << ans[i] << ; } cout << endl; return 0; }
|
`ifndef _REGFILE
`define _REGFILE
module register_file(clk, out1, out2, readAdd1, readAdd2, write, writeAdd, in, reset);
output [15:0] out1, out2;
input [15:0] in;
input [2:0] readAdd1, readAdd2, writeAdd;
input write, clk, reset;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
wire [7:0] writeLinesInit, writeLines;
demux8 dem(writeAdd, writeLinesInit);
mux16x8 mux1(data0, data1, data2, data3, data4, data5, data6, data7, readAdd1, out1);
mux16x8 mux2(data0, data1, data2, data3, data4, data5, data6, data7, readAdd2, out2);
or a0(writeLines[0], write, ~writeLinesInit[0]);
or a1(writeLines[1], write, ~writeLinesInit[1]);
or a2(writeLines[2], write, ~writeLinesInit[2]);
or a3(writeLines[3], write, ~writeLinesInit[3]);
or a4(writeLines[4], write, ~writeLinesInit[4]);
or a5(writeLines[5], write, ~writeLinesInit[5]);
or a6(writeLines[6], write, ~writeLinesInit[6]);
or a7(writeLines[7], write, ~writeLinesInit[7]);
register16 r0(clk, data0, in, writeLines[0], reset);
register16 r1(clk, data1, in, writeLines[1], reset);
register16 r2(clk, data2, in, writeLines[2], reset);
register16 r3(clk, data3, in, writeLines[3], reset);
register16 r4(clk, data4, in, writeLines[4], reset);
register16 r5(clk, data5, in, writeLines[5], reset);
register16 r6(clk, data6, in, writeLines[6], reset);
register16 r7(clk, data7, in, writeLines[7], reset);
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_mem (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
parameter DW = 16;
parameter AW = 5;
input clka;
input wea;
input [AW-1:0] addra;
input [DW-1:0] dina;
input clkb;
input [AW-1:0] addrb;
output [DW-1:0] doutb;
reg [DW-1:0] m_ram[0:((2**AW)-1)];
reg [DW-1:0] doutb;
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
doutb <= m_ram[addrb];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1507 USA
module quad(clk, A, B, Z, zr, out);
parameter W=14;
input clk, A, B, Z, zr;
reg [(W-1):0] c, i; reg zl;
output [2*W:0] out = { zl, i, c };
// reg [(W-1):0] c, i; reg zl;
reg [2:0] Ad, Bd;
reg [2:0] Zc;
always @(posedge clk) Ad <= {Ad[1:0], A};
always @(posedge clk) Bd <= {Bd[1:0], B};
wire good_one = &Zc;
wire good_zero = ~|Zc;
reg last_good;
wire index_pulse = good_one && ! last_good;
wire count_enable = Ad[1] ^ Ad[2] ^ Bd[1] ^ Bd[2];
wire count_direction = Ad[1] ^ Bd[2];
always @(posedge clk)
begin
if(Z && !good_one) Zc <= Zc + 2'b1;
else if(!good_zero) Zc <= Zc - 2'b1;
if(good_one) last_good <= 1;
else if(good_zero) last_good <= 0;
if(count_enable)
begin
if(count_direction) c <= c + 1'd1;
else c <= c - 1'd1;
end
if(index_pulse) begin
i <= c;
zl <= 1;
end else if(zr) begin
zl <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long sz = 1e5 + 10; long long ara[sz], n, p; ; bool isValid(long long now) { long long ptr = 1; for (long long i = 1; i <= n; ++i) { while (ptr <= n && ara[ptr] <= now) ptr++; if (ptr - i >= p) return 0; now++; } return 1; } int main() { cin >> n >> p; for (long long i = 1; i <= n; ++i) scanf( %lld , &ara[i]); sort(ara + 1, ara + n + 1); long long start = 1, now = start; for (long long i = 1; i <= n; ++i) { if (now < ara[i]) { long long diff = ara[i] - now; now += diff, start += diff; } now++; } long long lo = start, hi = 1e9, stop = -1; while (lo <= hi) { long long mid = lo + hi >> 1; if (isValid(mid)) { stop = mid; lo = mid + 1; } else hi = mid - 1; } cout << max(0LL, stop - start + 1) << n ; for (long long i = start; i <= stop; i += 1) { if (i != start) printf( ); printf( %lld , i); } if (stop != -1) printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int MAXN = (int)3e5 + 3; const int infint = (int)1e9 + 3; const long long inf = (long long)2e18; struct node { int minf, tedf, mimm, tmimm, mipm, tmipm, min, max, lazymax, lazymin; node() { minf = infint, tedf = 0; mimm = infint, tmimm = 0; mipm = infint, tmipm = 0; min = infint, max = -infint; lazymax = -1, lazymin = -1; } } seg[4 * MAXN]; void updmax(int node, int st, int en, int x) { seg[node].max = x; seg[node].mipm = st + seg[node].max, seg[node].tmipm = 1; seg[node].minf = seg[node].mimm + seg[node].max, seg[node].tedf = seg[node].tmimm; seg[node].lazymax = x; return; } void updmin(int node, int st, int en, int x) { seg[node].min = x; seg[node].mimm = st - seg[node].min, seg[node].tmimm = 1; seg[node].minf = seg[node].mipm - seg[node].min, seg[node].tedf = seg[node].tmipm; seg[node].lazymin = x; } void shift(int node, int st, int en) { int mid = (st + en) >> 1; if (seg[node].lazymax != -1) updmax(node << 1, st, mid, seg[node].lazymax), updmax(node << 1 | 1, mid, en, seg[node].lazymax); if (seg[node].lazymin != -1) updmin(node << 1, st, mid, seg[node].lazymin), updmin(node << 1 | 1, mid, en, seg[node].lazymin); seg[node].lazymax = seg[node].lazymin = -1; } node merge(node a, node b) { node c; c.min = min(a.min, b.min); c.max = max(a.max, b.max); c.minf = a.minf, c.tedf = a.tedf; if (b.minf < c.minf) c.minf = b.minf, c.tedf = b.tedf; else if (b.minf == c.minf) c.tedf += b.tedf; c.mimm = a.mimm, c.tmimm = a.tmimm; if (b.mimm < c.mimm) c.mimm = b.mimm, c.tmimm = b.tmimm; else if (b.mimm == c.mimm) c.tmimm += b.tmimm; c.mipm = a.mipm, c.tmipm = a.tmipm; if (b.mipm < c.mipm) c.mipm = b.mipm, c.tmipm = b.tmipm; else if (b.mipm == c.mipm) c.tmipm += b.tmipm; c.lazymax = -1, c.lazymin = -1; return c; } void updatemax(int node, int st, int en, int l, int r, int x) { if (l >= en || st >= r) return; if (l <= st && en <= r) { updmax(node, st, en, x); return; } int mid = (st + en) >> 1; shift(node, st, en); updatemax(node << 1, st, mid, l, r, x); updatemax(node << 1 | 1, mid, en, l, r, x); seg[node] = merge(seg[node << 1], seg[node << 1 | 1]); } void updatemin(int node, int st, int en, int l, int r, int x) { if (l >= en || st >= r) return; if (l <= st && en <= r) { updmin(node, st, en, x); return; } int mid = (st + en) >> 1; shift(node, st, en); updatemin(node << 1, st, mid, l, r, x); updatemin(node << 1 | 1, mid, en, l, r, x); seg[node] = merge(seg[node << 1], seg[node << 1 | 1]); } node emp; node get(int node, int st, int en, int l, int r) { if (l >= en || st >= r) { emp.minf = infint, emp.tedf = 0; emp.mimm = infint, emp.tmimm = 0; emp.mipm = infint, emp.tmipm = 0; emp.min = infint, emp.max = -infint; emp.lazymax = -1, emp.lazymin = -1; return emp; } if (l <= st && en <= r) return seg[node]; int mid = (st + en) >> 1; shift(node, st, en); return merge(get(node << 1, st, mid, l, r), get(node << 1 | 1, mid, en, l, r)); } int n, a[MAXN], s[MAXN], g[MAXN]; int zero[MAXN], oc[MAXN], prv[MAXN]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < 4 * MAXN; i++) seg[i] = node(); for (int i = 0; i < n; i++) { cin >> a[i]; a[i]--; } for (int i = 0; i < n; i++) if (a[i] == 0) zero[i] = i; else if (i == 0) zero[i] = -1; else zero[i] = zero[i - 1]; memset(oc, -1, sizeof oc); for (int i = 0; i < n; i++) { prv[i] = oc[a[i]], oc[a[i]] = i; if (i) prv[i] = max(prv[i], prv[i - 1]); } for (int i = 0; i < n; i++) prv[i]++; stack<int> S; for (int i = 0; i < n; i++) { while (!S.empty() && a[S.top()] > a[i]) S.pop(); if (S.size()) s[i] = S.top(); else s[i] = -1; S.push(i); } while (S.size()) S.pop(); for (int i = 0; i < n; i++) { while (!S.empty() && a[S.top()] < a[i]) S.pop(); if (S.size()) g[i] = S.top(); else g[i] = -1; S.push(i); } long long ans = 0; for (int i = 0; i < n; i++) { updatemin(1, 0, n, s[i] + 1, i + 1, a[i]); updatemax(1, 0, n, g[i] + 1, i + 1, a[i]); if (prv[i] <= zero[i]) { node cur = get(1, 0, n, prv[i], zero[i] + 1); if (cur.minf == i) ans += cur.tedf; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> graph; vector<int> isBlack; vector<long long> dp[2]; long long previous[2]; void dfs(int curr) { dp[0][curr] = 1 - isBlack[curr]; dp[1][curr] = isBlack[curr]; for (int child : graph[curr]) { dfs(child); previous[0] = dp[0][curr]; previous[1] = dp[1][curr]; dp[0][curr] = 0; dp[1][curr] = 0; dp[1][curr] = (previous[1] * (dp[0][child] + dp[1][child]) % 1000000007) % 1000000007; if (isBlack[curr] == 0) { dp[0][curr] = (previous[0] * (dp[0][child] + dp[1][child]) % 1000000007) % 1000000007; dp[1][curr] = (dp[1][curr] + (previous[0] * dp[1][child]) % 1000000007) % 1000000007; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; graph.resize(n); isBlack.resize(n); dp[1].resize(n); dp[0].resize(n); for (int i = 0; i < n - 1; i++) { int p; cin >> p; graph[p].push_back(i + 1); } for (int i = 0; i < n; i++) { cin >> isBlack[i]; } dfs(0); cout << dp[1][0] << n ; return 0; }
|
(** * Extraction: Extracting ML from Coq *)
(* $Date: 2012-05-03 17:52:38 -0400 (Thu, 03 May 2012) $ *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
|
#include <bits/stdc++.h> using namespace std; class node { public: int lo, hi, value; node *left, *right; node(const int _lo, const int _hi) { left = right = NULL; lo = _lo, hi = _hi, value = 0; } void build() { if (lo == hi) return; const int mid = (lo + hi) >> 1; left = new node(lo, mid), left->build(); right = new node(mid + 1, hi), right->build(); } void update(const int idx) { if (lo > idx or hi < idx) return; if (lo == idx and hi == idx) { ++value; return; } left->update(idx); right->update(idx); value = left->value + right->value; } int query(const int _lo, const int _hi) { if (lo > _hi or hi < _lo) return 0; if (lo >= _lo and hi <= _hi) return value; int a = left->query(_lo, _hi); int b = right->query(_lo, _hi); return a + b; } int leftmost() { if (lo == hi) return lo; if (left->value) return left->leftmost(); return right->leftmost(); } int rightmost() { if (value == hi - lo + 1) return lo - 1; if (lo == hi) return lo; if (right->value < right->hi - right->lo + 1) return right->rightmost(); return left->rightmost(); } }; int main() { printf( 1 ); int n; scanf( %d , &n); node root = node(1, n); root.build(); for (int i = 0; i < n; ++i) { int x; scanf( %d , &x); root.update(x); printf( %d , root.query(root.leftmost(), root.rightmost()) + 1); } return !printf( n ); };
|
module crc
#(parameter BITS=8, parameter POLY=7, parameter INIT=0)
(input wire i_clk, input wire i_rst, input wire i_stb, input wire i_bit, output wire[BITS-1:0] o_crc);
//
// Сдвиговый регистр контрольной суммы.
reg[BITS-1:0] crcreg;
// Провода между регистрами.
wire[BITS-1:0] crcwires;
// Выходное значение CRC.
assign o_crc = crcreg;
initial begin
crcreg <= INIT[BITS-1:0];
end
// Выбор режима сдвига - с XOR или без.
assign sel = crcreg[BITS-1] ^ i_bit;
// Нулевой провод.
assign crcwires[0] = POLY[0] ? sel : 0;
genvar i;
generate
for(i = 1; i < BITS; i = i + 1) begin: gen_crc_wires
assign crcwires[i] = POLY[i] ? crcreg[i - 1] ^ sel : crcreg[i - 1];
end
endgenerate
// Процесс регистра.
always @(posedge i_clk or negedge i_rst) begin
if(!i_rst) begin
crcreg <= #1 INIT[BITS-1:0];
end else begin
if(i_stb) begin
crcreg <= #1 crcwires;
end else begin
crcreg <= #1 crcreg;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 500; int a[maxn]; int main(void) { int n, m; cin >> n >> m; int ans = 0; for (int i = 1; i <= m; i++) { int num; scanf( %d , &num); int x, temp; int flag = 0; scanf( %d , &x); temp = x; if (x == 1) flag = 1; for (int j = 2; j <= num; j++) { scanf( %d , &x); if (flag == 1 && x == temp + 1) { temp = x; continue; } if (x == 1) { temp = x; flag = 1; } else { flag = 0; ans++; } } } ans = ans + ans + m - 1; cout << ans << endl; }
|
//`timescale 1ns/1ps
module write_to_memory_testbench();
wire [6:0] slave_address; // 7 bit alave address
wire [7:0] byte_to_be_writen; // 8 bit value for write
wire I2C_mode; // use to select between read and write
wire I2C_start;
wire I2C_stop;
wire I2C_repeat_start;
wire [7:0] I2C_data_out;
wire ack;
tri1 sda;
tri1 scl;
wire [7:0] FIFO_data_out;
wire FIFO_empty;
wire FIFO_read;
wire full;
wire I2C_en; // used to enable the memory write to memory
wire reset_I2C; // used to reset the I2C machine
wire refresh_clk;
wire sys_clk;
reg clk;
reg write;
reg reset;
reg run;
reg [11:0] number_of_bytes;
reg [2:0] memory_number;
reg [14:0] memory_address;
reg [7:0] data_in;
reg [7:0] measurement;
reg en;
master u1 (slave_address, byte_to_be_writen, refresh_clk, sys_clk,
I2C_mode, I2C_en, reset_I2C, I2C_start, I2C_stop,
I2C_repeat_start, I2C_data_out, ack, sda, scl);
I2C_write_to_memory u2 (sys_clk, reset, run, number_of_bytes,
memory_address, FIFO_data_out, empty, ack, memory_number,
FIFO_read, slave_address, byte_to_be_writen, I2C_mode,
I2C_en, reset_I2C, I2C_start, I2C_stop, I2C_repeat_start,
sda);
FIFO_four u3 (sys_clk, reset, write, FIFO_read, data_in,
FIFO_data_out, full, FIFO_empty);
clock_divider u4 (clk, reset, en, refresh_clk, sys_clk);
slave u5 (slave_address, measurement, en, reset, scl, sda);
always
begin
#5 clk <= ~clk;
end
initial
begin
clk = 1;
reset = 1;
en = 1;
write = 0;
#200
reset = 0;
run = 0;
number_of_bytes = 5;
memory_address = 0;
memory_number = 2;
data_in = 0;
#4000
reset = 1;
#1400
while( !full )
begin
#1000
write = 1;
#1000
write = 0;
data_in = data_in + 3;
end
write = 0;
run = 1;
#30000
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace zyt { const int N = 1e6 + 10, CH = 20; int f[1 << CH], n; char s[N]; bool check(const int a, const int p) { return a & (1 << p); } int ctoi(const char c) { return c - a ; } void get_max(int &a, const int b) { a = max(a, b); } int work() { scanf( %s , s); n = strlen(s); for (int i = 0; i < n; i++) { int tmp = 0; for (int j = i; j < n; j++) if (check(tmp, ctoi(s[j]))) break; else get_max(f[tmp |= (1 << ctoi(s[j]))], j - i + 1); } for (int i = 0; i < (1 << CH); i++) for (int j = 0; j < CH; j++) if (check(i, j)) get_max(f[i], f[i ^ (1 << j)]); int ans = 0; for (int i = 1; i < (1 << CH); i++) get_max(ans, f[i] + f[~i & ((1 << CH) - 1)]); printf( %d , ans); return 0; } } // namespace zyt int main() { return zyt::work(); }
|
#include <bits/stdc++.h> using namespace std; long long maxi = LLONG_MAX; long long mini = LLONG_MIN; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); } long long a[] = {1, 1, 3}; void fn(long long n, long long x) { if (n <= 1) { for (long long i = 0; i < n; i++) { cout << x << ; } return; } long long t = (n) / 2; if (n == 3) { for (long long i = 0; i < 3; i++) { cout << x * a[i] << ; } return; } else { if (n % 2 == 1) cout << x << ; for (long long i = 0; i < t; i++) { cout << x << ; } } x *= 2; fn(t, x); } int main() { fast(); long long n; cin >> n; fn(n, 1); return 0; }
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic source synchronous DDR output
*/
module ssio_ddr_out #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock for transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire clk90,
input wire [WIDTH-1:0] input_d1,
input wire [WIDTH-1:0] input_d2,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire ref_clk = USE_CLK90 == "TRUE" ? clk90 : clk;
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(ref_clk),
.d1(1'b1),
.d2(1'b0),
.q(output_clk)
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(WIDTH)
)
data_oddr_inst (
.clk(clk),
.d1(input_d1),
.d2(input_d2),
.q(output_q)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> ostream& operator<<(ostream& os, const pair<T1, T2>& p) { os << ( << p.first << , << p.second << ) ; return os; } template <typename T1, typename T2, typename T3> ostream& operator<<(ostream& os, const tuple<T1, T2, T3>& t) { os << ( << get<0>(t) << , << get<1>(t) << , << get<2>(t) << ) ; return os; } template <typename T1, typename T2, typename T3, typename T4> ostream& operator<<(ostream& os, const tuple<T1, T2, T3, T4>& t) { os << ( << get<0>(t) << , << get<1>(t) << , << get<2>(t) << , << get<3>(t) << ) ; return os; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << [ ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << ] ; return os; } template <typename T, typename C> ostream& operator<<(ostream& os, const set<T, C>& v) { os << { ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << } ; return os; } template <typename T, typename C> ostream& operator<<(ostream& os, const unordered_set<T, C>& v) { os << { ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << } ; return os; } template <typename T, typename C> ostream& operator<<(ostream& os, const multiset<T, C>& v) { os << { ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << } ; return os; } template <typename T1, typename T2, typename C> ostream& operator<<(ostream& os, const map<T1, T2, C>& mp) { os << [ ; for (auto it = mp.begin(); it != mp.end(); it++) { if (it != mp.begin()) os << , ; os << it->first << : << it->second; } os << ] ; return os; } template <typename T1, typename T2, typename C> ostream& operator<<(ostream& os, const unordered_map<T1, T2, C>& mp) { os << [ ; for (auto it = mp.begin(); it != mp.end(); it++) { if (it != mp.begin()) os << , ; os << it->first << : << it->second; } os << ] ; return os; } template <typename T, typename T2> ostream& operator<<(ostream& os, const queue<T, T2>& orig) { queue<T, T2> que(orig); bool first = true; os << [ ; while (!que.empty()) { T x = que.front(); que.pop(); if (!first) os << , ; os << x; first = false; } return os << ] ; } template <typename T, typename T2> ostream& operator<<(ostream& os, const deque<T, T2>& orig) { deque<T, T2> que(orig); bool first = true; os << [ ; while (!que.empty()) { T x = que.front(); que.pop_front(); if (!first) os << , ; os << x; first = false; } return os << ] ; } template <typename T, typename T2, typename T3> ostream& operator<<(ostream& os, const priority_queue<T, T2, T3>& orig) { priority_queue<T, T2, T3> pq(orig); bool first = true; os << [ ; while (!pq.empty()) { T x = pq.top(); pq.pop(); if (!first) os << , ; os << x; first = false; } return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const stack<T>& st) { stack<T> tmp(st); os << [ ; bool first = true; while (!tmp.empty()) { T& t = tmp.top(); if (first) first = false; else os << , ; os << t; tmp.pop(); } os << ] ; return os; } ostream& operator<<(ostream& os, int8_t x) { os << (int32_t)x; return os; } template <class... Args> string dbgFormat(const char* fmt, Args... args) { size_t len = snprintf(nullptr, 0, fmt, args...); char buf[len + 1]; snprintf(buf, len + 1, fmt, args...); return string(buf); } template <class Head> void dbgLog(Head&& head) { cerr << head << endl; } template <class Head, class... Tail> void dbgLog(Head&& head, Tail&&... tail) { cerr << head << ; dbgLog(forward<Tail>(tail)...); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << setprecision(20); long long int n; cin >> n; const long long int big = 1e10; vector<long long int> ans(n + 1, big); long long int lim = 10; for (long long int t = 0; t < lim; t++) { ; auto doit = [&](long long int bit) -> void { vector<long long int> vec; for (long long int i = 1; i <= n; i++) { if (((i >> t) & 1) == bit) vec.push_back(i); }; long long int sz = vec.size(); if (sz == 0) return; cout << sz << endl; for (long long int i = 0; i < sz; i++) { if (i > 0) cout << ; cout << vec[i]; } cout << endl; for (long long int i = 1; i <= n; i++) { long long int v; cin >> v; if (((i >> t) & 1) != bit) { ans[i] = min(ans[i], v); ; } } }; doit(0); doit(1); } cout << -1 << endl; for (long long int i = 1; i <= n; i++) { if (i > 0) cout << ; cout << ans[i]; } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_LP_V
`define SKY130_FD_SC_LP__SDFXTP_LP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_lp (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_LP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:20:00 10/31/2016
// Module Name: MEM_tb
// Project Name: MIPS
// Description: Testing the MIPS MEMORY (MEM) pipeline stage.
//
// Dependencies: MEM.v
//
////////////////////////////////////////////////////////////////////////////////
module MEM_tb;
// Inputs
reg clk;
reg m_ctlout;
reg zero;
reg MemWrite;
reg MemRead;
reg [31:0] Write_data;
reg [1:0] control_wb_in;
reg [31:0] ALU_result_in;
reg [4:0] Write_reg_in;
// Outputs
wire PCSrc;
wire [1:0] mem_control_wb;
wire [31:0] Read_data;
wire [31:0] mem_ALU_result;
wire [4:0] mem_Write_reg;
// Instantiate the Unit Under Test (UUT)
MEM mem (
.clk(clk),
.m_ctlout(m_ctlout),
.zero(zero),
.MemWrite(MemWrite),
.MemRead(MemRead),
.Write_data(Write_data),
.control_wb_in(control_wb_in),
.ALU_result_in(ALU_result_in),
.Write_reg_in(Write_reg_in),
.PCSrc(PCSrc),
.mem_control_wb(mem_control_wb),
.Read_data(Read_data),
.mem_ALU_result(mem_ALU_result),
.mem_Write_reg(mem_Write_reg)
);
initial begin
// Initialize Inputs
clk = 0;
m_ctlout = 0;
zero = 0;
MemWrite = 0;
MemRead = 0;
Write_data = 0;
control_wb_in = 0;
ALU_result_in = 0;
Write_reg_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h002300AA;
control_wb_in = 0;
ALU_result_in = 32'h00230000;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h10654321;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h00100022;
control_wb_in = 0;
ALU_result_in = 32'h00100000;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h8C123456;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h8F123456;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'hAD654321;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h13012345;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'hAC654321;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;
Write_reg_in = Write_reg_in + 1;
#20;
m_ctlout = 1;
zero = 0;
MemWrite = 1;
MemRead = 0;
Write_data = 32'h12012345;
control_wb_in = 0;
ALU_result_in = 32'hA42ADFB0;
Write_reg_in = Write_reg_in + 1;
#20;
$finish;
end
initial begin
$monitor("INPUTS: m_ctlout = %b\tzero = %b\tMemWrite = %b\tMemRead = %b\t",
clk, m_ctlout, zero, MemWrite, MemRead,
"Write_data = %d\tcontrol_wb_in = %b\ALU_result_in = %d\tWrite_reg_in = %d\t",
Write_data, control_wb_in, ALU_result_in, Write_reg_in,
"OUTPUTS: PCSrc = %d\tmem_control_wb = %b\tRead_data = %d\tmem_ALU_result = %d\t",
PCSrc, mem_control_wb, Read_data, mem_ALU_result,
"mem_Write_reg = %d",
mem_Write_reg);
forever begin
#10 clk = ~clk;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); const long long MAXN = 1e6 + 5; long long n, m, t; struct NODE { long long a, b; } v[MAXN]; long long cmp1(NODE a, NODE b) { return a.a < b.a; } long long a[MAXN], b[MAXN]; long long q[MAXN]; int main() { cin >> t; while (t--) { cin >> m >> n; for (long long i = 1; i <= n; i++) cin >> v[i].a >> v[i].b; sort(v + 1, v + 1 + n, cmp1); for (long long i = 1; i <= n; i++) a[i] = v[i].a, b[i] = v[i].b, q[i] = q[i - 1] + a[i]; long long ans = 0; for (long long i = 1; i <= n; i++) { long long nowb = b[i]; long long index = lower_bound(a + 1, a + 1 + n, nowb) - a; if (index == n + 1) { ans = max(ans, a[i] + (m - 1) * b[i]); continue; } if (index <= i) { long long can = n - index + 1; if (can >= m) { ans = max(ans, q[n] - q[n - m]); continue; } ans = max(ans, q[n] - q[index - 1] + b[i] * (m - can)); } else { long long can = n - index + 1; if (can >= m - 1) { ans = max(ans, q[n] - q[n - m + 1] + a[i]); continue; } ans = max(ans, q[n] - q[index] + a[i] + b[i] * (m - can - 1) + max(b[i], a[index])); } } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int temp[100012], arr[100012], t[100012]; for (int i = 0; i < n; i++) { cin >> arr[i]; t[i] = arr[i]; } sort(t, t + n); int v = 0; for (int i = 0; i < n; i++) { if (t[i] != arr[i]) { v = 1; break; } } if (v == 0) { cout << n << endl; return 0; } int c = 0; for (int i = 0; i < n; i++) { if (arr[i] == i) c++; else { temp[i] = arr[i]; } } int f = 0; for (int i = 0; i < n; i++) { if (arr[i] != i) { if (i == temp[temp[i]]) { c += 2; f = 1; break; } } } if (f == 0) c += 1; if (c > n) c = n; cout << c << endl; }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n, k; cin >> n >> k; vector<long long> a(n); vector<long long> b(n); for (long long i = 0; i < n; i++) { cin >> a[i]; a[i]--; } for (long long i = 0; i < n; i++) { cin >> b[i]; } long long cntZero = 0; vector<long long> cnt(k); for (long long i = 0; i < n; i++) { cnt[a[i]]++; } for (long long i = 0; i < k; i++) { if (cnt[i] == 0) cntZero++; } set<pair<long long, long long>> s; for (long long i = 0; i < n; i++) { s.insert({b[i], i}); } long long ans = 0; while (cntZero) { auto pp = *s.begin(); s.erase(s.begin()); if (cnt[a[pp.second]] > 1) { cntZero--; cnt[a[pp.second]]--; ans += pp.first; } } cout << ans << endl; }
|
// tb201.v - A WCI::AXI test bench with BFM, DUT, and Monitor/Observer
// Copyright (c) 2010 Atomic Rules LLC - ALL RIGHTS RESERVED
//
// This testbench instances three components, and provides them with a common clock and reset
// These three components are connected together with the WCI0_ signal group
// 1. A BFM "Initiator" which initiates WCI cycles
// 2. A DUT "Taget" which completes WCI cycles
// 3. A Monitor/Observer which watches ober the WCI cycles
`timescale 1ns/1ps
module tb201 ();
reg CLK; // System Clock
reg RST_N; // System Reset (active-low)
always begin // Clock generation...
#5; CLK = 1'b0;
#5; CLK = 1'b1;
end
initial begin: initblock
integer i;
localparam resetCycles = 16;
#0 RST_N = 1'b0; $display("reset asserted, RST_N=0");
for (i=0;i<resetCycles;i=i+1) @(posedge CLK);
#0 RST_N = 1'b1; $display("reset released, RST_N=1");
end
// WCI0_ WCI::AXI Wires to interconnect the BFM, DUT and Monitor...
wire WCI0_ACLK = CLK; // Connect system clock to WCI0 Link
wire WCI0_ARESETn;
wire WCI0_AWVALID;
wire WCI0_AWREADY;
wire [31:0] WCI0_AWADDR;
wire [2:0] WCI0_AWPROT;
wire WCI0_WVALID;
wire WCI0_WREADY;
wire [31:0] WCI0_WDATA;
wire [3:0] WCI0_WSTRB;
wire WCI0_BVALID;
wire WCI0_BREADY;
wire [1:0] WCI0_BRESP;
wire WCI0_ARVALID;
wire WCI0_ARREADY;
wire [31:0] WCI0_ARADDR;
wire [2:0] WCI0_ARPROT;
wire WCI0_RVALID;
wire WCI0_RREADY;
wire [31:0] WCI0_RDATA;
wire [1:0] WCI0_RRESP;
mkWciAxiInitiator bfm ( // Instance the BFM Initiator...
.CLK (CLK),
.RST_N (RST_N),
.wciM0_ACLK (WCI0_ACLK),
.RST_N_wciM0_ARESETn (WCI0_ARESETn), // WCI0_MReset_n is the reset source for this WCI0 link
.wciM0_AWVALID (WCI0_AWVALID),
.wciM0_AWREADY (WCI0_AWREADY),
.wciM0_AWADDR (WCI0_AWADDR),
.wciM0_AWPROT (WCI0_AWPROT),
.wciM0_WVALID (WCI0_WVALID),
.wciM0_WREADY (WCI0_WREADY),
.wciM0_WDATA (WCI0_WDATA),
.wciM0_WSTRB (WCI0_WSTRB),
.wciM0_BVALID (WCI0_BVALID),
.wciM0_BREADY (WCI0_BREADY),
.wciM0_BRESP (WCI0_BRESP),
.wciM0_ARVALID (WCI0_ARVALID),
.wciM0_ARREADY (WCI0_ARVALID),
.wciM0_ARADDR (WCI0_ARADDR),
.wciM0_ARPROT (WCI0_ARPROT),
.wciM0_RVALID (WCI0_RVALID),
.wciM0_RREADY (WCI0_RREADY),
.wciM0_RDATA (WCI0_RDATA),
.wciM0_RRESP (WCI0_RRESP)
);
mkWciAxiTarget dut ( // Instance the DUT Target...
.wciS0_ACLK (WCI0_ACLK),
.wciS0_ARESETn (WCI0_ARESETn),
.wciS0_AWVALID (WCI0_AWVALID),
.wciS0_AWREADY (WCI0_AWREADY),
.wciS0_AWADDR (WCI0_AWADDR),
.wciS0_AWPROT (WCI0_AWPROT),
.wciS0_WVALID (WCI0_WVALID),
.wciS0_WREADY (WCI0_WREADY),
.wciS0_WDATA (WCI0_WDATA),
.wciS0_WSTRB (WCI0_WSTRB),
.wciS0_BVALID (WCI0_BVALID),
.wciS0_BREADY (WCI0_BREADY),
.wciS0_BRESP (WCI0_BRESP),
.wciS0_ARVALID (WCI0_ARVALID),
.wciS0_ARREADY (WCI0_ARVALID),
.wciS0_ARADDR (WCI0_ARADDR),
.wciS0_ARPROT (WCI0_ARPROT),
.wciS0_RVALID (WCI0_RVALID),
.wciS0_RREADY (WCI0_RREADY),
.wciS0_RDATA (WCI0_RDATA),
.wciS0_RRESP (WCI0_RRESP)
);
mkWciAxiMonitor mon( // Instance the Monitor/Observer...
.wciO0_ACLK (WCI0_ACLK),
.wciO0_ARESETn (WCI0_ARESETn),
.wciO0_AWVALID (WCI0_AWVALID),
.wciO0_AWREADY (WCI0_AWREADY),
.wciO0_AWADDR (WCI0_AWADDR),
.wciO0_AWPROT (WCI0_AWPROT),
.wciO0_WVALID (WCI0_WVALID),
.wciO0_WREADY (WCI0_WREADY),
.wciO0_WDATA (WCI0_WDATA),
.wciO0_WSTRB (WCI0_WSTRB),
.wciO0_BVALID (WCI0_BVALID),
.wciO0_BREADY (WCI0_BREADY),
.wciO0_BRESP (WCI0_BRESP),
.wciO0_ARVALID (WCI0_ARVALID),
.wciO0_ARREADY (WCI0_ARVALID),
.wciO0_ARADDR (WCI0_ARADDR),
.wciO0_ARPROT (WCI0_ARPROT),
.wciO0_RVALID (WCI0_RVALID),
.wciO0_RREADY (WCI0_RREADY),
.wciO0_RDATA (WCI0_RDATA),
.wciO0_RRESP (WCI0_RRESP)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 18; bool a[N]; vector<int> res; int x, n; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n >> x; res.push_back(0); a[0] = true; for (int i = 1; i <= int((1 << n) - 1); i++) { if (a[i ^ x]) continue; res.push_back(i); a[i] = true; } cout << res.size() - 1 << n ; for (int i = 1; i <= int(res.size() - 1); i++) { int t = res[i] ^ res[i - 1]; cout << t << ; } return 0; }
|
//name : arbiter
//tag : c components
//input : input_a:16
//input : input_b:16
//output : output_z:16
//source_file : test.c
///=======
///
///*Created by C2CHIP*
// Register Allocation
// ===================
// Register Name Size
// 0 arbiter return address 2
// 1 temporary_register 2
`timescale 1ns/1ps
module arbiter(input_a,input_b,input_a_stb,input_b_stb,output_z_ack,clk,rst,output_z,output_z_stb,input_a_ack,input_b_ack);
integer file_count;
input [15:0] input_a;
input [15:0] input_b;
input input_a_stb;
input input_b_stb;
input output_z_ack;
input clk;
input rst;
output [15:0] output_z;
output output_z_stb;
output input_a_ack;
output input_b_ack;
reg [15:0] timer;
reg [3:0] program_counter;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg write_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg write_enable_4;
reg [15:0] register_0;
reg [15:0] register_1;
reg [15:0] s_output_z_stb;
reg [15:0] s_output_z;
reg [15:0] s_input_a_ack;
reg [15:0] s_input_b_ack;
//////////////////////////////////////////////////////////////////////////////
// FSM IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a Finite State Machine (FSM) implementing
// the C process. In general execution is sequential, but the compiler will
// attempt to execute instructions in parallel if the instruction dependencies
// allow. Further concurrency can be achieved by executing multiple C
// processes concurrently within the device.
always @(posedge clk)
begin
//implement timer
timer <= 16'h0000;
case(program_counter)
16'd0:
begin
program_counter <= 16'd1;
program_counter <= 16'd3;
register_0 <= 16'd1;
end
16'd1:
begin
program_counter <= 16'd3;
program_counter <= program_counter;
end
16'd3:
begin
program_counter <= 16'd2;
register_1 <= 0;
register_1[0] <= input_a_stb;
end
16'd2:
begin
program_counter <= 16'd6;
if (register_1 == 0)
program_counter <= 4;
end
16'd6:
begin
program_counter <= 16'd7;
register_1 <= input_a;
program_counter <= 6;
s_input_a_ack <= 1'b1;
if (s_input_a_ack == 1'b1 && input_a_stb == 1'b1) begin
s_input_a_ack <= 1'b0;
program_counter <= 16'd7;
end
end
16'd7:
begin
program_counter <= 16'd5;
s_output_z <= register_1;
program_counter <= 7;
s_output_z_stb <= 1'b1;
if (s_output_z_stb == 1'b1 && output_z_ack == 1'b1) begin
s_output_z_stb <= 1'b0;
program_counter <= 5;
end
end
16'd5:
begin
program_counter <= 16'd4;
program_counter <= 16'd4;
end
16'd4:
begin
program_counter <= 16'd12;
register_1 <= 0;
register_1[0] <= input_b_stb;
end
16'd12:
begin
program_counter <= 16'd13;
if (register_1 == 0)
program_counter <= 10;
end
16'd13:
begin
program_counter <= 16'd15;
register_1 <= input_b;
program_counter <= 13;
s_input_b_ack <= 1'b1;
if (s_input_b_ack == 1'b1 && input_b_stb == 1'b1) begin
s_input_b_ack <= 1'b0;
program_counter <= 16'd15;
end
end
16'd15:
begin
program_counter <= 16'd14;
s_output_z <= register_1;
program_counter <= 15;
s_output_z_stb <= 1'b1;
if (s_output_z_stb == 1'b1 && output_z_ack == 1'b1) begin
s_output_z_stb <= 1'b0;
program_counter <= 14;
end
end
16'd14:
begin
program_counter <= 16'd10;
program_counter <= 16'd10;
end
16'd10:
begin
program_counter <= 16'd11;
program_counter <= 16'd3;
end
16'd11:
begin
program_counter <= 16'd9;
program_counter <= register_0;
end
endcase
if (rst == 1'b1) begin
program_counter <= 0;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T inline sqr(T x) { return x * x; } template <class T> inline void relaxMin(T &a, T b) { a = min(a, b); } template <class T> inline void relaxMax(T &a, T b) { a = max(a, b); } string str(int i) { char s[100]; sprintf(s, %d , i); return string(s); } inline int sign(int x) { return x > 0 ? 1 : (x < 0 ? -1 : 0); } inline int myAbs(int a) { return a > 0 ? a : -a; } const int mlen = (int)2e5 + 10; int n; char s[mlen]; int main() { gets(s); n = strlen(s); int i = 0; while (i < n && s[i] <= 32) i++; while (i < n) { char ch = s[i]; int l; if (ch == , ) l = 1; else if (ch == . ) l = 3; else l = n; while (l > 0 && i < n && isdigit(ch) == isdigit(s[i])) putchar(s[i++]), l--; while (i < n && s[i] <= 32) i++; if (i < n && (ch == , || s[i] == . || (isdigit(ch) && isdigit(s[i])))) putchar( ); } puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_1_V
`define SKY130_FD_SC_MS__NAND4B_1_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_1 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_1 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_1_V
|
#include <bits/stdc++.h> char s[1000000]; char ans[1000000]; int main() { int i, len, cnt; char max = 0; while (scanf( %s , s) != EOF) { max = 0; cnt = 1000000 - 1; len = strlen(s); for (i = len - 1; i >= 0; i--) { if (s[i] >= max) { max = s[i]; ans[cnt--] = s[i]; } } for (i = cnt + 1; i < 1000000; i++) printf( %c , ans[i]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; set<string> st; set<string>::iterator it1; vector<int> dp2(20000, 0), dp3(20000, 0); void solve(string s, int i, string prev) { if (i < 1) return; if (i == 1) { string a = s.substr(i - 1, 2); if (a != prev) st.insert(a); else return; } else { string temp; string a = s.substr(i - 1, 2); string b = s.substr(i - 2, 3); if (a != prev && !dp2[i]) { dp2[i] = 1; temp = a; solve(s, i - 2, temp); } if (b != prev && !dp3[i]) { dp3[i] = 1; temp = b; solve(s, i - 3, temp); } } return; } int main() { string str; cin >> str; if (str.size() < 7) { cout << 0; return 0; } string s(str.begin() + 5, str.end()); int n = s.size(); solve(s, n - 1, ); for (int i = 0; i < n; i++) { if (dp2[i]) st.insert(s.substr(i - 1, 2)); if (dp3[i]) st.insert(s.substr(i - 2, 3)); } cout << st.size() << endl; it1 = st.begin(); for (; it1 != st.end(); it1++) cout << *it1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Nmax = 2005; int n, k; pair<double, double> mij[Nmax * Nmax]; pair<int, int> a[Nmax]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i].first >> a[i].second; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) mij[++k] = {(double)(a[i].first + a[j].first) / 2, (double)(a[i].second + a[j].second) / 2}; sort(mij + 1, mij + k + 1); int cnt; long long sol = 0; cnt = 1; for (int i = 2; i <= k;) { while (i <= k && mij[i].first == mij[i - 1].first && mij[i].second == mij[i - 1].second) { i++; cnt++; } sol += (cnt * (cnt - 1)) / 2; cnt = 1; i++; } cout << sol << n ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 17:33:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_buffer_register_1_0 -prefix
// system_buffer_register_1_0_ system_buffer_register_0_0_stub.v
// Design : system_buffer_register_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "buffer_register,Vivado 2016.4" *)
module system_buffer_register_1_0(clk, val_in, val_out)
/* synthesis syn_black_box black_box_pad_pin="clk,val_in[31:0],val_out[31:0]" */;
input clk;
input [31:0]val_in;
output [31:0]val_out;
endmodule
|
// Copyright (c) 2000 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// This tests tasks being able to write to output parameters that
// are memory words. This is legal as val[0] is a valid l-value.
// In addition, it catches binding issues. Note the common name
// of the val parameter and the val memory.
module test;
reg [31:0] val[1:0], tmp;
task testT;
output [31:0] val;
begin
val = 1234;
end
endtask
initial begin
testT(val[0]);
if (val[0] === 1234)
$display("PASSED");
else
$display("FAILED -- val[0] == %b",val[0]);
end
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ForwardUnit(EX_RS, EX_RT, MEM_RD, WB_RD, MEM_WB, WB_WB, Forward_A, Forward_B);
input MEM_WB, WB_WB;
input [4:0] EX_RS, EX_RT, MEM_RD, WB_RD;
output [1:0] Forward_A, Forward_B;
reg [1:0] Forward_A, Forward_B;
always @(EX_RS or EX_RT)
begin
//Forward A Register
if (WB_WB && WB_RD && MEM_RD != WB_RD && WB_RD == EX_RS)
begin
assign Forward_A = 2'b01;
end
else if (MEM_WB && MEM_RD && MEM_RD == EX_RS)
begin
assign Forward_A = 2'b10;
end
else
begin
assign Forward_A = 2'b00;
end
//Forward B Register
if (WB_WB && WB_RD && MEM_RD != WB_RD && WB_RD == EX_RT)
begin
assign Forward_B = 2'b01;
end
else if (MEM_WB && MEM_RD && MEM_RD == EX_RT)
begin
assign Forward_B = 2'b10;
end
else
begin
assign Forward_B = 2'b00;
end
end
//initial begin
// assign Forward_A = 2'b00;
//assign Forward_B = 2'b00;
//end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_1_V
`define SKY130_FD_SC_HD__A311OI_1_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_1_V
|
#include <bits/stdc++.h> using namespace std; int n, arr[30010], book[30010]; bool judge() { int ps, gap; int t1 = 1, t2; while (t1 <= n && book[t1]) t1++; t2 = t1 + 1; if (t1 > n) return false; while (t2 <= n && book[t2]) t2++; if (t2 > n) return true; gap = arr[t2] - arr[t1]; ps = t2; for (int i = t2 + 1; i <= n; i++) if (!book[i]) { if (arr[i] - arr[ps] == gap) ps = i; else return false; } return true; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &arr[i]); if (n == 2) printf( %d n%d , arr[1], arr[2]); else { int x[3] = {arr[2] - arr[1], arr[3] - arr[2], arr[3] - arr[1]}; int flag = 0; for (int i = 0; i < 3; i++) { int st = 4, tmp = arr[3]; memset(book, 0, sizeof(book)); if (i == 0) { book[2] = book[1] = 1; st = 3; tmp = arr[2]; } else if (i == 1) book[2] = book[3] = 1; else book[1] = book[3] = 1; for (int ii = st; ii <= n; ii++) if (arr[ii] == tmp + x[i]) { book[ii] = 1; tmp = arr[ii]; } if (judge()) { flag = 1; break; } else { int p = n; while (!book[p]) p--; book[p] = 0; if (judge()) { flag = 1; break; } } } if (flag) { for (int i = 1; i <= n; i++) if (book[i]) printf( %d , arr[i]); printf( n ); for (int i = 1; i <= n; i++) if (!book[i]) printf( %d , arr[i]); } else printf( No solution ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_4_V
`define SKY130_FD_SC_LS__A31O_4_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_4_V
|
`timescale 1ns/1ns
// SIMULATION - UNUSED
// SNK "PCM" chip (in cartridge)
module pcm(
input CLK_68KCLKB,
input nSDROE, SDRMPX,
input nSDPOE, SDPMPX,
inout [7:0] SDRAD,
input [9:8] SDRA_L,
input [23:20] SDRA_U,
inout [7:0] SDPAD,
input [11:8] SDPA,
input [7:0] D,
output [23:0] A
);
reg [1:0] COUNT;
reg [7:0] RDLATCH;
reg [7:0] PDLATCH;
reg [23:0] RALATCH;
reg [23:0] PALATCH;
always @(posedge CLK_68KCLKB or negedge nSDPOE)
begin
if (!nSDPOE)
COUNT <= 0;
else
if (!COUNT[1]) COUNT <= COUNT + 1'b1;
end
assign SDRAD = nSDROE ? 8'bzzzzzzzz : RDLATCH;
always @*
if (COUNT[1]) RDLATCH <= D;
assign SDPAD = nSDPOE ? 8'bzzzzzzzz : PDLATCH;
always @*
if (!nSDPOE) PDLATCH <= D;
assign A = nSDPOE ? RALATCH[23:0] : PALATCH[23:0];
always @(posedge SDRMPX)
begin
RALATCH[7:0] <= SDRAD;
RALATCH[9:8] <= SDRA_L[9:8];
end
always @(negedge SDRMPX)
begin
RALATCH[17:10] <= SDRAD;
RALATCH[23:18] <= {SDRA_U[23:20], SDRA_L[9:8]};
end
always @(posedge SDPMPX)
begin
PALATCH[7:0] <= SDPAD;
PALATCH[11:8] <= SDPA[11:8];
end
always @(negedge SDPMPX)
begin
PALATCH[19:12] <= SDPAD;
PALATCH[23:20] <= SDPA[11:8];
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sync_cell.v
//
// *Module Description:
// Generic synchronizer for the openMSP430
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_sync_cell (
// OUTPUTs
data_out, // Synchronized data output
// INPUTs
clk, // Receiving clock
data_in, // Asynchronous data input
rst // Receiving reset (active high)
);
// OUTPUTs
//=========
output data_out; // Synchronized data output
// INPUTs
//=========
input clk; // Receiving clock
input data_in; // Asynchronous data input
input rst; // Receiving reset (active high)
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst)
if (rst) data_sync <= 2'b00;
else data_sync <= {data_sync[0], data_in};
assign data_out = data_sync[1];
endmodule // omsp_sync_cell
|
module cia_int
(
input clk, // clock
input clk7_en,
input wr, // write enable
input reset, // reset
input icrs, // intterupt control register select
input ta, // ta (set TA bit in ICR register)
input tb, // tb (set TB bit in ICR register)
input alrm, // alrm (set ALRM bit ICR register)
input flag, // flag (set FLG bit in ICR register)
input ser, // ser (set SP bit in ICR register)
input [7:0] data_in, // bus data in
output [7:0] data_out, // bus data out
output irq // intterupt out
);
reg [4:0] icr = 5'd0; // interrupt register
reg [4:0] icrmask = 5'd0; // interrupt mask register
// reading of interrupt data register
assign data_out[7:0] = icrs && !wr ? {irq,2'b00,icr[4:0]} : 8'b0000_0000;
// writing of interrupt mask register
always @(posedge clk)
if (clk7_en) begin
if (reset)
icrmask[4:0] <= 5'b0_0000;
else if (icrs && wr)
begin
if (data_in[7])
icrmask[4:0] <= icrmask[4:0] | data_in[4:0];
else
icrmask[4:0] <= icrmask[4:0] & (~data_in[4:0]);
end
end
// register new interrupts and/or changes by user reads
always @(posedge clk)
if (clk7_en) begin
if (reset)// synchronous reset
icr[4:0] <= 5'b0_0000;
else if (icrs && !wr)
begin// clear latched intterupts on read
icr[0] <= ta; // timer a
icr[1] <= tb; // timer b
icr[2] <= alrm; // timer tod
icr[3] <= ser; // external ser input
icr[4] <= flag; // external flag input
end
else
begin// keep latched intterupts
icr[0] <= icr[0] | ta; // timer a
icr[1] <= icr[1] | tb; // timer b
icr[2] <= icr[2] | alrm; // timer tod
icr[3] <= icr[3] | ser; // external ser input
icr[4] <= icr[4] | flag; // external flag input
end
end
// generate irq output (interrupt request)
assign irq = (icrmask[0] & icr[0])
| (icrmask[1] & icr[1])
| (icrmask[2] & icr[2])
| (icrmask[3] & icr[3])
| (icrmask[4] & icr[4]);
endmodule
|
// $Id: $
/////////////////////////////////////////////////////////////////////
// This file is part of the GOST 28147-89 CryptoCore project //
// //
// Copyright (c) 2014 Dmitry Murzinov () //
/////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ns
module tb ();
// clock generator settings:
parameter cycles_reset = 2; // rst active (clk)
parameter clk_period = 10; // clk period ns
parameter clk_delay = 0; // clk initial delay
reg clk; // clock
reg rst; // sync reset
reg mode; // 0 - encrypt, 1 - decrypt
//reg select; // if GOST_R_3411_BOTH defined: 0 - Using the GOST R 34.11-94 TestParameter S-boxes; 1 - Using the CryptoPro S-boxes
//reg load; // load plain text and start cipher cycles
//wire done; // cipher text ready for output read
//reg kload; // load cipher key
reg [255:0] key; // cipher key input
reg [63:0] pdata; // plain text input
reg pvalid;// plain text valid input
wire pready;// plain text ready handshake
wire [63:0] cdata; // cipher text output
wire cvalid;// cipher text valid (ready for output read)
reg cready;// cipher text ready handshake
reg [63:0] pdata_d; // plain text input
wire [63:0] cdata_d; // cipher text output
reg [63:0] reference_data; // reference data for verify
wire EQUAL = cdata == reference_data;
wire [8*4-1:0] STATUS = EQUAL ? "OK" : "FAIL";
wire [63:0] data = {u.a,u.b};
wire [63:0] data2 = {u.b,u.a};
// instance connect
gost28147
u (
.clk(clk), // Input clock signal
.rst(rst), // Syncronous Reset
.mode(mode), // 0 - encrypt, 1 - decrypt
.key(key), // cipher key
.pdata(pdata), // plain text data input
.pvalid(pvalid), // plain text valid input
.pready(pready), // plain text ready handshake
.cdata(cdata), // cipher text data output
.cvalid(cvalid), // cipher text valid (ready for output read)
.cready(cready) // cipher text ready handshake
);
reg [24:0] clk_counter; // just clock counter for debug
// Clock generation
always begin
# (clk_delay);
forever # (clk_period/2) clk = ~clk;
end
// Initial statement
initial begin
#0 clk = 1'b0;
mode = 0;
cready = 1;
pvalid = 0;
key = 256'h0;
pdata = 64'h0;
clk_counter = 0;
// Reset
#0 rst = 1'bX;
#0 rst = 1'b0;
# ( 2*clk_period *cycles_reset) rst = 1'b1;
# ( 2*clk_period *cycles_reset) rst = 1'b0;
// key load
@ ( posedge clk )
#1 key = swapkey(256'hBE5EC200_6CFF9DCF_52354959_F1FF0CBF_E95061B5_A648C103_87069C25_997C0672);
@ ( posedge clk )
// Crypt mode
@ ( posedge clk ) #1 mode = 0;
#1 pdata = swapdata(64'h0DF82802_B741A292); pvalid = 1;
#1 reference_data = swapdata(64'h07F9027D_F7F7DF89);
@ ( posedge clk )
// Decrypt mode
@ ( posedge cvalid );
@ ( posedge clk ) #1 mode = 1;
pdata = swapdata(64'h07F9027D_F7F7DF89); pvalid = 1;
reference_data = swapdata(64'h0DF82802_B741A292);
@ ( posedge clk )
//$finish;
@ ( posedge cvalid );
@ ( posedge clk )
#1 $stop;
end
always begin
@( posedge clk );
clk_counter <= clk_counter + 1;
end
always @( posedge cvalid )
if (mode == 0)
#1 $display("KEY: %H \nCRYPT IN: %H \t REFOUT: %H \t OUT: %H ....%s", key, pdata, reference_data, cdata, STATUS);
else if (mode == 1)
#1 $display("KEY: %H \nDECRYPT IN: %H \t REFOUT: %H \t OUT: %H ....%s", key, pdata, reference_data, cdata, STATUS);
always @(posedge clk)
#1 $display("FSM = %d i = %H pv=%b pr=%b cv=%b cr=%b \t data = %H | %H", u.state, u.i, u.pvalid, u.pready, u.cvalid, u.cready, data, data2);
/////////////// dumping ///////////////
initial begin
$dumpfile("gost28147.vcd");
$dumpvars(0,tb);
end
///////////////////////////////////////
// ======= swap4(x) =======
function [31:0] swap4( input [31:0] x );
begin
swap4 = {x[7:0],x[15:8],x[23:16],x[31:24]};
end
endfunction
// ======= swapdate(data) =======
function [63:0] swapdata( input [63:0] data );
begin
swapdata = {swap4(data[31:0]),swap4(data[63:32])};
end
endfunction
// ======= swapkey(key) =======
function [255:0] swapkey( input [255:0] key );
reg [31:0] K [0:7];
begin
K[0] = swap4(key[255:224]);
K[1] = swap4(key[223:192]);
K[2] = swap4(key[191:160]);
K[3] = swap4(key[159:128]);
K[4] = swap4(key[127:96]);
K[5] = swap4(key[95:64]);
K[6] = swap4(key[63:32]);
K[7] = swap4(key[31:0]);
swapkey = {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]};
end
endfunction
endmodule
// eof
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O31AI_BEHAVIORAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_BEHAVIORAL_V
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$_MUX8_ (
A,
B,
C,
D,
E,
F,
G,
H,
S,
T,
U,
Y
);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
mux8x0 _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.C (C),
.D (D),
.E (E),
.F (F),
.G (G),
.H (H),
.S0(S),
.S1(T),
.S2(U),
.Q (Y)
);
endmodule
module \$_MUX4_ (
A,
B,
C,
D,
S,
T,
U,
Y
);
input A, B, C, D, S, T, U;
output Y;
mux4x0 _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.C (C),
.D (D),
.S0(S),
.S1(T),
.Q (Y)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A> string to_string(A* ptr) { stringstream ss; ss << 0x << std::setw(16) << std::setfill( 0 ) << std::hex << (uint64_t)(uintptr_t)ptr; return ss.str(); } string to_string(char c) { return ((string) + c) + ; } template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } const int DIM = 6; pair<bool, vector<string>> solve2(const vector<string>& S) { pair<bool, vector<string>> NO_ANS = {false, {}}; const string& A = S[0]; const string& B = S[1]; const string& C = S[2]; const string& D = S[3]; const string& E = S[4]; const string& F = S[5]; if (A.size() + C.size() != B.size() + 1) return NO_ANS; if (D.size() + F.size() != E.size() + 1) return NO_ANS; if (A[0] != D[0]) return NO_ANS; if (A.back() != E[0]) return NO_ANS; if (B[0] != D.back()) return NO_ANS; if (B[A.size() - 1] != E[D.size() - 1]) return NO_ANS; if (B.back() != F[0]) return NO_ANS; if (C[0] != E.back()) return NO_ANS; if (C.back() != F.back()) return NO_ANS; string line; for (int i = 0; i < (int)B.size(); i++) line += . ; vector<string> R(E.size(), line); for (int i = 0; i < (int)A.size(); i++) R[0][i] = A[i]; for (int i = 0; i < (int)B.size(); i++) R[(int)D.size() - 1][i] = B[i]; for (int i = 0; i < (int)C.size(); i++) R[(int)E.size() - 1][i + (int)A.size() - 1] = C[i]; for (int j = 0; j < (int)D.size(); j++) R[j][0] = D[j]; for (int j = 0; j < (int)E.size(); j++) R[j][(int)A.size() - 1] = E[j]; for (int j = 0; j < (int)F.size(); j++) R[j + (int)D.size() - 1][(int)B.size() - 1] = F[j]; return {true, R}; } string solve(vector<string>& S) { sort(S.begin(), S.end()); pair<bool, vector<string>> result = {true, {}}; do { auto [ok, res] = solve2(S); result = min(result, {!ok, res}); } while (next_permutation(S.begin(), S.end())); if (result.first) return Impossible ; else { string ans = ; for (string s : result.second) ans += s + n ; return ans; } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int TT; TT = 1; for (int ttt = 0; ttt < TT; ttt++) { vector<string> S(DIM); for (string& s : S) cin >> s; cout << solve(S); } return 0; }
|
#include <bits/stdc++.h> const int MAXN = 100100; int st[20][MAXN]; char str[MAXN]; int n; void SparseTable() { for (int i = 0; i < n; i++) st[0][i] = i; for (int j = 1; (1 << j) < n; j++) for (int i = 0; i + (1 << (j - 1)) < n; i++) st[j][i] = (str[st[j - 1][i]] >= str[st[j - 1][i + (1 << (j - 1))]] ? st[j - 1][i] : st[j - 1][i + (1 << (j - 1))]); } int get(int x, int y) { int k = int(log(double(y - x + 1)) / log(2.0)); return (str[st[k][x]] >= str[st[k][y - (1 << k) + 1]] ? st[k][x] : st[k][y - (1 << k) + 1]); } int main() { scanf( %s , str); n = strlen(str); SparseTable(); int p = 0; while (p != n) { p = get(p, n - 1); printf( %c , str[p]); p++; } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int OO = 0x3f3f3f3f, NegOO = -1 * OO, N = 1e6 + 5, mod = 1e9 + 7; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } int main() { int t; cin >> t; while (t--) { int n, x, y, d; cin >> n >> x >> y >> d; if (x == y) { cout << 0 << n ; continue; } else if (x < y) { int mx = 1e9 + 5; int ans1 = mx, ans2 = mx, ans3 = mx; if ((y - x) % d == 0) ans1 = (y - x) / d; if ((y - 1) % d == 0) ans2 = (x - 1) / d + ((x - 1) % d != 0) + (y - 1) / d; if ((n - y) % d == 0) ans3 = (n - x) / d + ((n - x) % d != 0) + (n - y) / d; int ans = min(min(ans1, ans2), ans3); cout << ((ans != mx) ? ans : -1) << n ; } else { int mx = 1e9 + 5; int ans1 = mx, ans2 = mx, ans3 = mx; if ((x - y) % d == 0) ans1 = (x - y) / d; if ((y - 1) % d == 0) ans2 = (x - 1) / d + ((x - 1) % d != 0) + (y - 1) / d; if ((n - y) % d == 0) ans3 = (n - x) / d + ((n - x) % d != 0) + (n - y) / d; int ans = min(min(ans1, ans2), ans3); cout << ((ans != mx) ? ans : -1) << n ; } } return 0; }
|
module sm_hex_display
(
input [3:0] digit,
output reg [6:0] seven_segments
);
always @*
case (digit)
'h0: seven_segments = 'b0111111; // a b c d e f g
'h1: seven_segments = 'b0000110; // ;
'h2: seven_segments = 'b1011011; // --a--
'h3: seven_segments = 'b1001111; // | |
'h4: seven_segments = 'b1100110; // f b
'h5: seven_segments = 'b1101101; // | |
'h6: seven_segments = 'b1111101; // --g--
'h7: seven_segments = 'b0000111; // | |
'h8: seven_segments = 'b1111111; // e c
'h9: seven_segments = 'b1100111; // | |
'ha: seven_segments = 'b1110111; // --d--
'hb: seven_segments = 'b1111100; // ;
'hc: seven_segments = 'b0111001; // ;
'hd: seven_segments = 'b1011110; // ;
'he: seven_segments = 'b1111001; // ;
'hf: seven_segments = 'b1110001; // ;
endcase
endmodule
//--------------------------------------------------------------------
module sm_hex_display_digit
(
input [6:0] digit1,
input [6:0] digit2,
input [6:0] digit3,
input clkIn,
output reg [11:0] seven_segments
);
reg [9:0] count = 10'b0000000000;
always @(posedge clkIn)
begin
case (count[9:8])
2'b00 : seven_segments = {3'b110, digit1[0], digit1[1], digit1[2], digit1[3], digit1[4], digit1[5], digit1[6], 2'b00};
2'b11 : seven_segments = {3'b101, digit2[0], digit2[1], digit2[2], digit2[3], digit2[4], digit2[5], digit2[6], 2'b00};
2'b10 : seven_segments = {3'b011, digit3[0], digit3[1], digit3[2], digit3[3], digit3[4], digit3[5], digit3[6], 2'b00};
default: count <= count + 1'b0;
endcase
count <= count + 1'b1;
end
endmodule
//--------------------------------------------------------------------
module sm_hex_display_8
(
input clock,
input resetn,
input [31:0] number,
output reg [ 6:0] seven_segments,
output reg dot,
output reg [ 7:0] anodes
);
function [6:0] bcd_to_seg (input [3:0] bcd);
case (bcd)
'h0: bcd_to_seg = 'b1000000; // a b c d e f g
'h1: bcd_to_seg = 'b1111001;
'h2: bcd_to_seg = 'b0100100; // --a--
'h3: bcd_to_seg = 'b0110000; // | |
'h4: bcd_to_seg = 'b0011001; // f b
'h5: bcd_to_seg = 'b0010010; // | |
'h6: bcd_to_seg = 'b0000010; // --g--
'h7: bcd_to_seg = 'b1111000; // | |
'h8: bcd_to_seg = 'b0000000; // e c
'h9: bcd_to_seg = 'b0011000; // | |
'ha: bcd_to_seg = 'b0001000; // --d--
'hb: bcd_to_seg = 'b0000011;
'hc: bcd_to_seg = 'b1000110;
'hd: bcd_to_seg = 'b0100001;
'he: bcd_to_seg = 'b0000110;
'hf: bcd_to_seg = 'b0001110;
endcase
endfunction
reg [2:0] i;
always @ (posedge clock or negedge resetn)
begin
if (! resetn)
begin
seven_segments <= bcd_to_seg (0);
dot <= ~ 0;
anodes <= ~ 8'b00000001;
i <= 0;
end
else
begin
seven_segments <= bcd_to_seg (number [i * 4 +: 4]);
dot <= ~ 0;
anodes <= ~ (1 << i);
i <= i + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; long long binary_exp(long long a, long long b) { long long ans = 1; while (b > 0) { if (b & 1) { ans = (ans * a); } a = (a * a); b = b >> 1; } return ans; } int fn(int low, vector<int> &a, int p) { int k = low; for (int i = 0; i < a.size(); i++) { k = low + i; int j = upper_bound(a.begin(), a.end(), k) - a.begin(); if ((j - i) % p == 0) { return 0; } } return 1; } map<long long, long long> mp; int main() { ios::sync_with_stdio(false); cin.tie(0); long long T; T = 1; while (T--) { int n, p; cin >> n >> p; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a.begin(), a.end()); int low = max(a[0], a[n - 1] - n + 1); for (int i = 0; i < n; i++) { low = max(low, a[i] - i); } int high = a[n - 1]; if (!fn(low, a, p)) { cout << 0 << endl; cout << endl; continue; } int z = low; while (low < high) { int mid = (low + high) / 2; mid++; if (fn(mid, a, p)) { low = mid; } else { high = mid - 1; } } cout << low - z + 1 << endl; for (int i = z; i <= low; i++) { cout << i << ; } cout << endl; } return 0; }
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll100M" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:11:05:SJ cbx_altiobuf_bidir 2011:10:31:21:11:05:SJ cbx_altiobuf_in 2011:10:31:21:11:05:SJ cbx_altiobuf_out 2011:10:31:21:11:05:SJ cbx_altpll 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ VERSION_END
//CBXI_INSTANCE_NAME="dds_gen_pll100M_gen_100MHz_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module pll100M_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 1,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 2,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //pll100M_altpll
//VALID FILE
|
`define SMV
`define SUBDIR
`ifdef SUBDIR
`include "ovl_always_on_edge.v"
`else
`include "ovl_ported/ovl_always_on_edge.v"
`endif
`define OVL_INIT_REG
/*
* File: ovl_always_on_edge_tb.v
* Test bench for ovl_alwaysZ_on_edge.v
* Includes assertions for verification
* Created: 2013-10-10
*
* Verified for both vlog95/ovl_always_on_edge_logic.v and vlog95/ovl_always_on_edge_logic2.v.
*/
module main();
// Inputs to DUT
reg clk;
reg reset;
reg enable;
reg sampling_event;
reg test_expr;
// Outputs of DUT
//In the DUT module, this width is parameterized by OVL_FIRE_WIDTH-1.
wire [2:0] fire;
ovl_always_on_edge ovl_aoe_t(.clock(clk),
.reset(reset),
.enable(enable),
.sampling_event(sampling_event),
.test_expr(test_expr),
.fire(fire),
.edge_type(1),
.property_type(3),
.clock_edge(1),
.reset_polarity(0),
.gating_type(0),
.severity_level(3));
initial begin
clk = 0;
reset = 1;
enable = 0;
sampling_event = 0;
test_expr = 0;
end
always begin
clk = #5 !clk;
end
endmodule // main
/* ***************** SMV Assertions ******************
//SMV-Assertions
# The ovl_always_on_edge is an assertion module that checks if sampling_event has a rising edge, then test_expr will be high. The spec states that if this check fails, then ovl_always_on_edge will "fire" an event. i.e. "~(pos_edge_sampling_event -> test_expr) -> X(fire)". This can be rewritten "(pos_edge_sampling_event && ~test_expr) -> X(fire)".
# The first set of assertions verify that we correctly understand the semantics of the code. Using the variables in the "if" statement, these assertions verify that fire_2state is triggered exactly under the set of conditions that we expect.
# The code works as we expect. If the conditions of the "if" statement are satisfied, fire_2state is triggered.
\follow_code : assert ~\ovl_aoe_t .\reset_n -> X(G((\ovl_aoe_t .\reset_n && \ovl_aoe_t .\sampling_event && ~\ovl_aoe_t .\test_expr && ~\ovl_aoe_t .\sampling_event_prev && \ovl_aoe_t .\r_reset_n )-> X(\ovl_aoe_t .\fire_2state )));
# The code works as we epxect. fire_2state never fires without a rising edge of sampling event.
\never_fires_wo_rising_sampling_edge : assert ~\ovl_aoe_t .\reset_n -> X(G((\ovl_aoe_t .\sampling_event_prev || ~\ovl_aoe_t .\sampling_event ) -> X(~\ovl_aoe_t .\fire_2state )));
# The code works as we expect. fire_2state never fires without test_expr low.
\never_fires_wo_test_expr : assert ~\ovl_aoe_t .\reset_n -> X(G(\ovl_aoe_t .\test_expr -> X(~\ovl_aoe_t .\fire_2state )));
# The second set of assertions verify the code correctly implements the spec as given by the timing diagram "assert_always_on_edge" for a rising edge, pg 14 of assert_timing_diagram.pdf. These assertions use only the variables appearing in the timing diagram, plus reset.
# test_expr should always be high on a rising edge of sampling_event. If it is not, an event ("fire_2state") is triggered.
\trigger_if_low_test_and_rising_sampling_edge : assert reset -> X(G((~\reset && ~\sampling_event ) -> X((~\reset && \sampling_event && ~\test_expr ) -> X(\fire = 1))));
# Although not given in the spec, we would also like to verify that an event is triggered only when test_expr is low on a rising edge of sampling_event.
# An event is not triggered if there is no rising edge.
\never_fires_wo_rising_sampling_edge1 : assert reset -> X(G((~\sampling_event ) -> X(\fire = 0)));
\never_fires_wo_rising_sampling_edge2 : assert reset -> X(G((\sampling_event ) -> X(X(\fire = 0))));
# An event is not triggered if test_expr is high.
\never_fires_wo_test_expr1 : assert reset -> X(G(\test_expr -> X(\fire = 0)));
//SMV-Assertions
*/
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_r_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> std::mt19937 rng( (int)std::chrono::steady_clock::now().time_since_epoch().count()); const int ms = 110000; const int bs = 1000; const int MOD = 998244353; void add(int &a, int b) { a = a + b < MOD ? a + b : a + b - MOD; } int *pivot; bool comp(int x1, int x2) { return pivot[x1] < pivot[x2]; } int tmp[2][bs]; struct Bucket { Bucket() { dirty = size = 0; } void push_back(int x) { p[size] = size; lazy[size] = 0; dp[size] = x; values[size++] = 0; } void clean() { for (int i = size - 2; i >= 0; i--) { add(lazy[i], lazy[i + 1]); } for (int i = 0; i < size; i++) { add(dp[p[i]], lazy[i]); lazy[i] = 0; } if (dirty) { for (int i = 0; i < size; i++) { values[i] += dirty; } dirty = 0; } } void sort() { clean(); pivot = values; std::sort(p, p + size, comp); } int getID(int x) { if (x < values[p[0]] + dirty) { return -1; } int l = 0, r = size - 1; while (l != r) { int mid = (l + r + 1) / 2; if (values[p[mid]] + dirty <= x) { l = mid; } else { r = mid - 1; } } return l; } void upd(int x, int l, int r, int val) { if (l == 0 && r == size) { int id = getID(x); if (id != -1) { add(lazy[id], val); } } else { for (int i = l; i < r; i++) { if (values[i] + dirty <= x) { add(dp[i], val); } else { } } } } void upd2(int l, int r, int val) { if (l == 0 && r == size) { dirty += val; } else { for (int i = l; i < r; i++) { values[i] += val; } clean(); pivot = values; int s0 = 0, s1 = 0; for (int i = 0; i < size; i++) { if (l <= p[i] && p[i] < r) { tmp[0][s0++] = p[i]; } else { tmp[1][s1++] = p[i]; } } std::merge(tmp[0], tmp[0] + s0, tmp[1], tmp[1] + s1, p, comp); } } int values[bs], p[bs], lazy[bs], dp[bs]; int dirty; int size; }; Bucket b[ms / bs + 2]; std::vector<int> pos[ms]; int a[ms]; int pt[ms]; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); int n, k; std::cin >> n >> k; for (int i = 1; i <= n; i++) { pos[i].push_back(-1); } for (int i = 0; i < n; i++) { std::cin >> a[i]; pos[a[i]].push_back(i); b[i / bs].push_back(i == 0 ? 1 : 0); } b[n / bs].push_back(0); for (int i = 1; i <= n; i++) { pos[i].push_back(n); pos[i].push_back(n); } auto upd2 = [&](int l, int r, int val) { if (l >= r) return; int bl = l / bs, br = (r - 1) / bs; if (bl == br) { b[bl].upd2(l - bl * bs, r - bl * bs, val); return; } b[bl].upd2(l - bl * bs, bs, val); for (int i = bl + 1; i < br; i++) { b[i].upd2(0, bs, val); } b[br].upd2(0, r - br * bs, val); }; auto upd = [&](int l, int r, int val) { if (l >= r) return; int bl = l / bs, br = (r - 1) / bs; if (bl == br) { b[bl].upd(k, l - bl * bs, r - bl * bs, val); return; } b[bl].upd(k, l - bl * bs, bs, val); for (int i = bl + 1; i < br; i++) { b[i].upd(k, 0, bs, val); } b[br].upd(k, 0, r - br * bs, val); }; for (int i = 1; i <= n; i++) { upd2(pos[i][1] + 1, pos[i][2] + 1, 1); } for (int i = 0; i < n; i++) { b[i / bs].clean(); int dp = b[i / bs].dp[i % bs]; upd(i + 1, n + 1, dp); { int v = a[i]; upd2(pos[v][pt[v] + 1] + 1, pos[v][pt[v] + 2] + 1, -1); pt[v]++; upd2(pos[v][pt[v] + 1] + 1, pos[v][pt[v] + 2] + 1, 1); } } b[n / bs].clean(); std::cout << b[n / bs].dp[n % bs] << n ; }
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 1e6 + 100; const long long mod = 1e9 + 7; const long long inf = 1e18 + 12; vector<long long> arr(MAX); map<long long, long long> mm; int main() { ios_base::sync_with_stdio(false); cout.tie(NULL); cout.tie(NULL); ; long long tt = 1; while (tt--) { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long w = 0, b = 0; long long i = 0; while (i < n) { if (i % 2 == 0) { w += (a[i] + 1) / 2; b += (a[i]) / 2; } else { w += a[i] / 2; b += (a[i] + 1) / 2; } i++; } cout << min(w, b); } }
|
#include <iostream> #include <bits/stdc++.h> using namespace std; int main () { int t; cin >> t; for (int k=0; k<t;k++){ int n; cin >> n; int a[n]; for (int i=0; i<n; i++){ cin >> a[i]; } for (int j=n-1; j>=0; j--){ if(a[j]+j < n){ a[j] = a[j]+a[a[j]+j]; } } int max=0; for (int i=0; i<n; i++){ if(a[i]>max){ max=a[i]; } } cout << max << endl; } return 0; }
|
module test
(output reg [1:0] foo,
input wire [1:0] addr,
input wire in0, in1,
input wire en0, en1
/* */);
localparam foo_default = 2'b00;
always @*
begin
foo = foo_default;
case (addr)
0: if (en0) foo[0] = in0;
1: if (en1) foo[1] = in1;
2: foo = {in1, in0};
default: foo = 0;
endcase
end
endmodule // test
module main;
wire [1:0] foo;
reg [1:0] addr;
reg in0, in1;
reg en0, en1;
test dut(.foo(foo), .addr(addr), .in0(in0), .in1(in1), .en0(en0), .en1(en1));
initial begin
in0 = 1;
in1 = 1;
en0 = 1;
en1 = 1;
addr = 3;
#1 if (foo !== 2'b00) begin
$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
foo, in1, in0, en1, en0, addr);
$finish;
end
addr = 0;
#1 if (foo !== 2'b01) begin
$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
$finish;
end
addr = 1;
#1 if (foo !== 2'b10) begin
$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
$finish;
end
addr = 2;
#1 if (foo !== 2'b11) begin
$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
$finish;
end
en0 = 0;
en1 = 0;
addr = 3;
#1 if (foo !== 2'b00) begin
$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
foo, in1, in0, en1, en0, addr);
$finish;
end
addr = 0;
#1 if (foo !== 2'b00) begin
$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
foo, in1, in0, en1, en0, addr);
$finish;
end
addr = 1;
#1 if (foo !== 2'b00) begin
$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
$finish;
end
addr = 2;
#1 if (foo !== 2'b11) begin
$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
foo, in1, in0, en1, en0, addr);
$finish;
end
$display("PASSED");
end
endmodule // main
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e15; const int MOD = 1e9 + 7; const double EPS = 1e-7; const double PI = acos(-1.0); const int N = 3e5 + 5; long long n, a[N]; int main() { ios::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } long long ans = 0, left = 0; for (int i = 0; i < n; ++i) { if (i) { ans += min(a[i] / 2, left); long long tmp = left; left -= min(a[i] / 2, left); a[i] -= min(a[i] / 2 * 2, tmp * 2); } ans += a[i] / 3; a[i] -= a[i] / 3 * 3; left += a[i]; } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void rd(T &x) { x = 0; int f = 1; char c; while (!isdigit(c = getchar())) if (c == - ) f = -1; do { x = (x << 1) + (x << 3) + (c ^ 48); } while (isdigit(c = getchar())); x *= f; } const int N = 3e5 + 5; struct ANS { int l, r, d; }; struct node { int v, id; bool operator<(const node &x) const { return v < x.v; } } s[N]; vector<ANS> ans; int t[N], n; int main() { rd(n); for (int i = 1; i <= n; i++) rd(s[i].v), s[i].id = i; for (int i = 1; i <= n; i++) rd(t[i]); sort(s + 1, s + n + 1); sort(t + 1, t + n + 1); int i = 1, j = 2; while (1) { if (s[i].v > t[i]) return !printf( NO ); while (s[j].v <= t[j]) j++; while (s[i].v == t[i]) i++; if (j >= n + 1 || i > j) break; int tmp = min((s[j].v - s[i].v) >> 1, min(t[i] - s[i].v, s[j].v - t[j])); if (tmp) ans.push_back({s[i].id, s[j].id, tmp}), s[i].v += tmp, s[j].v -= tmp; } for (int i = 1; i <= n; i++) if (s[i].v != t[i]) return !printf( NO ); cout << YES << endl << ans.size() << endl; for (auto it : ans) cout << it.l << << it.r << << it.d << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 200010, INF = 1e9; int cnt[MAX]; int n, c, ans = INF; int mx[MAX], v[MAX]; bool f[MAX]; vector<int> a; bool ok(int x, int y) { if (x == 0) return 1; if (y == 0) return 0; x -= a[y] * min(cnt[a[y]], x / a[y]); if (mx[x] > y - 1) return ok(x, y - 1); else return f[x]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> c >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; cnt[x]++; } a.push_back(0); for (int i = 1; i <= c; i++) if (cnt[i]) a.push_back(i); a.push_back(c); int cur = c; for (int i = a.size() - 1; i >= 1; i--) cur -= a[i] * min(cnt[a[i]], cur / a[i]), v[i] = cur; memset(mx, -1, sizeof mx); for (int i = 0; i < a.size() - 1; i++) { for (int j = a[i]; j < a[i + 1]; j++) { mx[j] = i; f[j] = ok(j, i); } } for (int i = 0; i < a.size() - 1; i++) { for (int j = a[i]; j < a[i + 1]; j++) { if (v[i + 1] >= j && !ok(v[i + 1] - j, i)) ans = min(ans, j); } } if (ans != INF) cout << ans << endl; else cout << Greed is good << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:57:15 07/09/2015
// Design Name:
// Module Name: Serializer_10_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Serializer_10_1
( input [9:0] Data,
input Clk_10,
input Clk_2,
input Strobe,
output Out
);
reg Status;
reg [9:0] FullData; // Buffered Data in
reg [4:0] HalfData; // Buffered Data out
wire cascade_in;
wire cascade_out;
initial
begin
Status = 1'b0;
FullData[4:0] = 5'h000;
HalfData[4:0] = 5'h00;
end
always @(posedge Clk_2)
begin
if (Status == 1'b0)
begin
FullData[4:0] = Data[9:5];
HalfData[4:0] = Data[4:0];
Status = 1'b1;
end
else
begin
HalfData[4:0] = FullData[4:0];
Status = 1'b0;
end
end
OSERDES2 #(.DATA_RATE_OQ("SDR"),
.DATA_RATE_OT("SDR"),
.DATA_WIDTH(5),
.SERDES_MODE("MASTER")
) MasterSerDes(.CLK0(Clk_10),
.CLK1(1'b0),
.CLKDIV(Clk_2),
.IOCE(Strobe),
.D4(1'b0),
.D3(1'b0),
.D2(1'b0),
.D1(HalfData[4]),
.OCE(1'b1),
.RST(1'b0),
.T4(1'b0),
.T3(1'b0),
.T2(1'b0),
.T1(1'b0),
.TCE(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SHIFTIN3(cascade_in),
.SHIFTIN4(1'b0),
.TRAIN(1'b0),
.OQ(Out),
.TQ(),
.SHIFTOUT1(cascade_out),
.SHIFTOUT2(),
.SHIFTOUT3(),
.SHIFTOUT4());
OSERDES2 #(.DATA_RATE_OQ("SDR"),
.DATA_RATE_OT("SDR"),
.DATA_WIDTH(5),
.SERDES_MODE("SLAVE")
) SlaveSerDes(.CLK0(Clk_10),
.CLK1(1'b0),
.CLKDIV(Clk_2),
.IOCE(Strobe),
.D4(HalfData[3]),
.D3(HalfData[2]),
.D2(HalfData[1]),
.D1(HalfData[0]),
.OCE(1'b1),
.RST(1'b0),
.T4(1'b0),
.T3(1'b0),
.T2(1'b0),
.T1(1'b0),
.TCE(1'b0),
.SHIFTIN1(cascade_out),
.SHIFTIN2(1'b0),
.SHIFTIN3(1'b0),
.SHIFTIN4(1'b0),
.TRAIN(1'b0),
.OQ(),
.TQ(),
.SHIFTOUT1(),
.SHIFTOUT2(),
.SHIFTOUT3(cascade_in),
.SHIFTOUT4());
endmodule
|
module RegisterFile( output reg [15:0] A_Data, B_Data, input [15:0] D_Data, input [2:0] AA, BA, DA, input RW, CLK );
reg [15:0] REGS[7:0];
always@(posedge CLK)
if(RW)
case(DA)
3'b 000 : REGS[0] = D_Data;
3'b 001 : REGS[1] = D_Data;
3'b 010 : REGS[2] = D_Data;
3'b 011 : REGS[3] = D_Data;
3'b 100 : REGS[4] = D_Data;
3'b 101 : REGS[5] = D_Data;
3'b 110 : REGS[6] = D_Data;
3'b 111 : REGS[7] = D_Data;
endcase
always@(*)
begin
case(AA)
3'b 000 : A_Data = REGS[0];
3'b 001 : A_Data = REGS[1];
3'b 010 : A_Data = REGS[2];
3'b 011 : A_Data = REGS[3];
3'b 100 : A_Data = REGS[4];
3'b 101 : A_Data = REGS[5];
3'b 110 : A_Data = REGS[6];
3'b 111 : A_Data = REGS[7];
endcase
case(BA)
3'b 000 : B_Data = REGS[0];
3'b 001 : B_Data = REGS[1];
3'b 010 : B_Data = REGS[2];
3'b 011 : B_Data = REGS[3];
3'b 100 : B_Data = REGS[4];
3'b 101 : B_Data = REGS[5];
3'b 110 : B_Data = REGS[6];
3'b 111 : B_Data = REGS[7];
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int sum[1000000 + 5]; int n, k, maxnum, minnum; bool check(int p) { for (int i = 0; i < maxnum; i += p) { int l = i + k; int r = min(maxnum, i + p - 1); if (l < r && sum[r] - sum[l] > 0) return false; } return true; } int main() { scanf( %d%d , &n, &k); memset(sum, 0, sizeof(sum)); maxnum = 1; minnum = 1000000; for (int i = 1; i <= n; i++) { int p; scanf( %d , &p); sum[p] = 1; maxnum = max(maxnum, p); minnum = min(minnum, p); } for (int i = 2; i <= maxnum; i++) sum[i] += sum[i - 1]; for (int i = minnum; i >= 1; i--) if (check(i)) { printf( %d n , i); break; } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> vis; string s[1000009]; int n, m, i; bool dfs(int x, int y) { if (x == n - 1 && y == m - 1) return true; if (x < 0 || y < 0 || x >= n || y >= m || vis[y + x * m] == 1 || s[x][y] == # ) return false; if (x || y) { vis[y + x * m] = 1; } return dfs(x + 1, y) || dfs(x, y + 1); } int main() { cin >> n >> m; for (i = 0; i < n; i++) cin >> s[i]; if (dfs(0, 0) == false) { cout << 0 ; return 0; } if (dfs(0, 0) == false) { cout << 1 ; return 0; } cout << 2 ; }
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<long long, pair<long long, long long> > &a, const pair<long long, pair<long long, long long> > &b) { return (a.second.first < b.second.first); } bool sortbyth(const pair<long long, pair<long long, long long> > &a, const pair<long long, pair<long long, long long> > &b) { return (a.second.second < b.second.second); } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long min(long long a, long long b) { return a < b ? a : b; } long long max(long long a, long long b) { return a > b ? a : b; } long long max3(long long a, long long b, long long c) { return max(max(a, b), c); } long long max4(long long a, long long b, long long c, long long d) { return max(max(a, b), max(c, d)); } long long min3(long long a, long long b, long long c) { return min(min(a, b), c); } long long min4(long long a, long long b, long long c, long long d) { return min(min(a, b), min(c, d)); } long long po(long long x, long long n, long long mod = 1000000007) { if (n == 0) { return 1; } long long m = po(x, n / 2, mod); m *= m; m %= mod; if (n % 2) { m *= x; m %= mod; } return m; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); cin.tie(NULL); clock_t startTime = clock(); cout << fixed << setprecision(12); long long n; cin >> n; vector<long long> v(n); for (long long i = 0; i < n; i++) cin >> v[i]; set<long long> ans, s; for (long long i = 0; i < n; i++) { set<long long> temp; temp.insert(v[i]); auto it = s.begin(); while (it != s.end()) { temp.insert(*it | v[i]); it++; } ans.insert(temp.begin(), temp.end()); s = temp; } cout << ans.size() << n ; }
|
module ctrl (ins, branch, jump, regDst, aluSrc, aluCtr, regWr, memWr, extOp, memtoReg);
input [31:0] ins;
output reg [3:0] aluCtr;
output reg branch;
output reg jump;
output reg regDst;
output reg aluSrc;
output reg regWr;
output reg memWr;
output reg extOp;
output reg memtoReg;
wire [5:0] op;
wire [5:0] func;
assign op = ins[31:26];
assign func = ins[5:0];
// Operation code;
parameter R = 6'b000000,
LW = 6'b100011,
SW = 6'b101011,
BEQ = 6'b000100,
J = 6'b000010,
ORI = 6'b001101;
// Function code;
parameter ADD = 6'b100000,
ADDU = 6'b100001,
SUB = 6'b100010,
SUBU = 6'b100011,
AND = 6'b100100,
OR = 6'b100101,
SLT = 6'b101010,
SLTU = 6'b101011;
always @ ( * ) begin
case (op)
R: begin// R-Type Instructions;
branch = 0;
jump = 0;
regDst = 1;
aluSrc = 0;
memtoReg = 0;
regWr = 1;
memWr = 0;
case (func)
ADD: aluCtr = 4'b0001;
ADDU: aluCtr = 4'b0000;
SUB: aluCtr = 4'b1001;
SUBU: aluCtr = 4'b1000;
AND: aluCtr = 4'b0010;
OR: aluCtr = 4'b0011;
SLT: aluCtr = 4'b1011;
SLTU: aluCtr = 4'b1010;
endcase
end
LW: begin// Load word;
branch = 0;
jump = 0;
regDst = 0;
aluSrc = 1;
memtoReg = 1;
regWr = 1;
memWr = 0;
extOp = 1;
aluCtr = 4'b0001;// add;
end
SW: begin// Store word;
branch = 0;
jump = 0;
aluSrc = 1;
regWr = 0;
memWr = 1;
extOp = 1;
aluCtr = 4'b0001;// add;
end
BEQ: begin// Branch on equal;
branch = 1;
jump = 0;
aluSrc = 0;
regWr = 0;
memWr = 0;
end
J: begin// J-Type Instructions；
branch = 0;
jump = 1;
regWr = 0;
memWr = 0;
end
ORI: begin// Or immediate;
branch = 0;
jump = 0;
regDst = 0;
aluSrc = 1;
memtoReg = 0;
regWr = 1;
memWr = 0;
extOp = 0;
aluCtr = 4'b0011;
end
endcase
end
endmodule // Control;
|
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