text
stringlengths 59
71.4k
|
|---|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v11.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 11.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR311.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 7: 0] mem_dm;
inout [ 63: 0] mem_dq;
inout [ 7: 0] mem_dqs;
inout [ 7: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 31: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 7: 0] mem_dm;
wire [ 63: 0] mem_dq;
wire [ 7: 0] mem_dqs;
wire [ 7: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 31: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [255: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [255: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 31: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[7 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[7 : 0]),
.mem_dqsn (mem_dqsn[7 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[31 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< start europa
endmodule
|
#include <bits/stdc++.h> using namespace std; long long min(long long x, long long y) { return (x < y) ? x : y; } long long max(long long x, long long y) { return (x > y) ? x : y; } const int N = 100009; int x, y, n, m, i, u, w, z, sum, best, j, k, t, mx; int a[N]; string s, ans; int main() { ios_base::sync_with_stdio(false); cin >> s; n = s.size(); while (i < n) { if (s[i] == d && s[i + 1] == o && s[i + 2] == t && i != 0 && i != n - 3) { ans.push_back( . ); i += 2; } else if (s[i] == a && s[i + 1] == t && !x && i != 0 && i != n - 2) { x = 1; i++; ans.push_back( @ ); } else ans.push_back(s[i]); i++; } cout << ans; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary nand ~&(value)
//
// SJW - Make a version that uses behavioral code to implement ~&
module main;
reg [3:0] vect;
reg error;
reg result;
initial
begin
error = 0;
for(vect=4'b000;vect<4'b1111;vect = vect + 1)
begin
result = ~& vect;
if(result !== 1'b1)
begin
$display("FAILED - Unary nand ~&(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b1111;
result = ~& vect;
if(result !== 1'b0)
begin
$display("FAILED - Unary nand ~&(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T1, class T2> inline void gn(T1 &x1, T2 &x2) { gn(x1), gn(x2); } char S1[1000100], S2[1000100]; char B[1000100 * 3]; int fail[1000100 * 3]; void build_fail_function(char B[], int len) { int j = fail[0] = -1; for (int i = 1; i < len; i++) { while (j != -1 and B[j + 1] != B[i]) j = fail[j]; if (B[j + 1] == B[i]) j++; fail[i] = j; } } int main() { int n; gn(n); n--; scanf( %s %s , S1, S2); for (int i = 0; i < n; i++) { if (S1[i] == N ) S1[i] = S ; else if (S1[i] == S ) S1[i] = N ; else if (S1[i] == W ) S1[i] = E ; else S1[i] = W ; } int nn = 0; for (int i = 0; i < n; i++) B[nn++] = S1[n - i - 1]; B[nn++] = * ; for (int i = 0; i < n; i++) B[nn++] = S2[i]; build_fail_function(B, nn); if (fail[nn - 1] == -1) return puts( YES ); puts( NO ); }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long pow(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res = (res * x); x = (x * x); n >>= 1; } return res; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; long long x = n / 2; if (x % 2) { cout << NO << n ; continue; } cout << YES << n ; vector<long long> a; for (long long i = 0; i < n; i += 2) { a.push_back(i + 2); } long long c = a.size() / 2; for (long long i = 0; i < c; i++) { a.push_back(a[i] - 1); a.push_back(a[x - i - 1] + 1); } for (auto x : a) cout << x << ; cout << n ; } return 0; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build Thu Oct 30 16:30:39 MDT 2014
// Date : Wed Apr 8 23:17:41 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/parallella-hw/fpga/ip/xilinx/fifo_async_103x32/fifo_async_103x32_stub.v
// Design : fifo_async_103x32
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *)
module fifo_async_103x32(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[102:0],wr_en,rd_en,dout[102:0],full,empty,prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [102:0]din;
input wr_en;
input rd_en;
output [102:0]dout;
output full;
output empty;
output prog_full;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, a, ok, ans, occ[10]; int main() { scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &a); int total = k + 1; memset(occ, 0, sizeof(occ)); while (a) { if (!occ[a % 10] && (a % 10 <= k)) { total--; } occ[a % 10] = 1; a /= 10; } if (!total) { ans++; } } printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_NSR_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_NSR_SYMBOL_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$NSR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_NSR_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__INV_BEHAVIORAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_BEHAVIORAL_PP_V
|
`include "bch_defs.vh"
module xilinx_error_tmec #(
parameter T = 2,
parameter DATA_BITS = 5,
parameter BITS = 1,
parameter REG_RATIO = 1,
parameter PIPELINE_STAGES = 0,
parameter ACCUM = 1
) (
input clk_in,
input in,
output reg out = 0
);
`include "bch_params.vh"
localparam TCQ = 1;
localparam P = bch_params(DATA_BITS, T);
localparam IN = `BCH_SIGMA_SZ(P) + 1;
localparam OUT = 1 + BITS;
wire clk;
(* KEEP = "TRUE" *)
reg [IN-1:0] all_in;
(* KEEP = "TRUE" *)
reg [OUT-1:0] all_out;
wire start; /* Latch inputs, start calculating */
wire [`BCH_SIGMA_SZ(P)-1:0] sigma;
wire ready;
wire first; /* First valid output data */
wire [BITS-1:0] err;
(* KEEP = "TRUE" *)
reg in1 = 0, in2 = 0, out1 = 0;
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
assign start = all_in[0];
assign sigma = all_in >> 1;
always @(posedge clk) begin
in1 <= #TCQ in;
in2 <= #TCQ in1;
out <= #TCQ out1;
out1 <= #TCQ all_out[0];
all_in <= #TCQ (all_in << 1) | in2;
all_out <= #TCQ (all_out >> 1) ^ {first, err};
end
bch_error_tmec #(P, BITS, REG_RATIO, PIPELINE_STAGES, ACCUM) u_error_tmec(
.clk(clk),
.start(start),
.sigma(sigma),
.first(first),
.err(err)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:39:57 03/02/2016
// Design Name: Ctr
// Module Name: G:/ceshi/lab3c/test_for_Ctr.v
// Project Name: lab3c
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Ctr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_Ctr;
// Inputs
reg [5:0] opCode;
// Outputs
wire regDst;
wire aluSrc;
wire memToReg;
wire regWrite;
wire memRead;
wire memWrite;
wire branch;
wire [1:0] aluOp;
wire jump;
// Instantiate the Unit Under Test (UUT)
Ctr uut (
.opCode(opCode),
.regDst(regDst),
.aluSrc(aluSrc),
.memToReg(memToReg),
.regWrite(regWrite),
.memRead(memRead),
.memWrite(memWrite),
.branch(branch),
.aluOp(aluOp),
.jump(jump)
);
initial begin
// Initialize Inputs
opCode = 0;
// Wait 100 ns for global reset to finish
#100;
#100 opCode = 6'b000010;
#100 opCode=6'b000000;
#100 opCode=6'b100011;
#100 opCode=6'b101011;
#100 opCode=6'b000100;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFXBP_PP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:30:25 05/05/2013
// Design Name:
// Module Name: multplr
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multplr(input [5:0]X,Y, output reg [11:0] prdct );
wire [5:0] p1,p2,p3,p4,p5,p6;
partialprdct ppdct(X,Y,p1,p2,p3,p4,p5,p6);
/////////////////L0ha1s(lavel zero half adder 1 sum)
reg L0ha1s,L0ha1c,L0fa1s,L0fa1c,L0fa2s,L0fa2c,L0fa3s,L0fa3c,L0fa4s,L0fa4c,L0ha2s,L0ha2c;
/////////////////L1ha1s(lavel 1 half adder 1 sum)
reg L1ha1s,L1ha1c,L1fa1s,L1fa1c,L1fa2s,L1fa2c,L1fa3s,L1fa3c,L1fa4s,L1fa4c,L1ha2s,L1ha2c;
/////////////////L2ha1s(lavel 2 half adder 1 sum)
reg L2ha1s,L2ha1c,L2fa1s,L2fa1c,L2fa2s,L2fa2c,L2fa3s,L2fa3c,L2fa4s,L2fa4c,L2fa5s,L2fa5c;
/////////////////L3ha1s(lavel 3 half adder 1 sum)
reg L3ha1s,L3ha1c,L3ha2s,L3ha2c,L3fa1s,L3fa1c,L3fa2s,L3fa2c,L3fa3s,L3fa3c,L3ha3s,L3ha3c,L3ha4s,L3ha4c,L3ha5s,L3ha5c;
////////////////////ripple carry signals//////////
reg c1,c2,c3,c4,c5,c6,c7,c8;
///////////////////////Half Adders and Full Adders Layers//////////////////////////
////////////////////LAYER 0 adders///////////////////
always @* begin
hfaddr(p1[1],p2[0],L0ha1s,L0ha1c);
fuladdr( p1[2],p2[1],p3[0],L0fa1s,L0fa1c);
fuladdr( p1[3],p2[2],p3[1],L0fa2s,L0fa2c);
fuladdr( p1[4],p2[3],p3[2],L0fa3s,L0fa3c);
fuladdr(p1[5],p2[4],p3[3],L0fa4s,L0fa4c);
hfaddr(p2[5],p3[4],L0ha2s,L0ha2c);
////////////////////LAYER 1 adders///////////////////
hfaddr(p4[1],p5[0], L1ha1s,L1ha1c);
fuladdr( p4[2],p5[1],p6[0],L1fa1s,L1fa1c);
fuladdr( p4[3],p5[2],p6[1],L1fa2s,L1fa2c);
fuladdr( p4[4],p5[3],p6[2],L1fa3s,L1fa3c);
fuladdr( p4[5],p5[4],p6[3],L1fa4s,L1fa4c);
hfaddr(p5[5],p6[4],L1ha2s,L1ha2c);
////////////////////LAYER 2 adders///////////////////
hfaddr(L0ha1c,L0fa1s, L2ha1s,L2ha1c);
fuladdr( L0fa1c,L0fa2s,p4[0],L2fa1s,L2fa1c);
fuladdr( L0fa2c,L1ha1s,L0fa3s,L2fa2s,L2fa2c);
fuladdr( L0fa3c,L1fa1s,L0fa4s,L2fa3s,L2fa3c);
fuladdr( L0fa4c,L1fa2s,L0ha2s,L2fa4s,L2fa4c);
fuladdr( L0ha2c,L1fa3s,p3[5],L2fa5s,L2fa5c);
////////////////////LAYER 3 adders///////////////////
hfaddr(L2ha1c,L2fa1s, L3ha1s,L3ha1c);
hfaddr(L2fa1c,L2fa2s, L3ha2s,L3ha2c);
fuladdr( L2fa2c,L1ha1c,L2fa3s,L3fa1s,L3fa1c);
fuladdr( L2fa3c,L1fa1c,L2fa4s,L3fa2s,L3fa2c);
fuladdr( L2fa4c,L1fa2c,L2fa5s,L3fa3s,L3fa3c);
hfaddr(L2fa5c,L1fa4s, L3ha3s,L3ha3c);
hfaddr(L1fa4c,L1ha2s, L3ha4s,L3ha4c);
hfaddr(L1ha2c,p6[5], L3ha5s,L3ha5c);
//////Finally Carry propagate Adder//////////////////
prdct[0] = p1[0];
prdct[1] = L0ha1s;
prdct[2] = L2ha1s;
prdct[3] = L3ha1s;
hfaddr(L3ha1c,L3ha2s,prdct[4],c1);
fuladdr( c1,L3ha2c,L3fa1s,prdct[5],c2);
fuladdr( c2,L3fa1c,L3fa2s,prdct[6],c3);
fuladdr( c3,L3fa2c,L3fa3s,prdct[7],c4);
fuladdr( c4,L3fa3c,L3ha3s,prdct[8],c5);
fuladdr( c5,L3ha3c,L3ha4s,prdct[9],c6);
fuladdr( c6,L3ha4c,L3ha5s,prdct[10],c7);
hfaddr( c7,L3ha5c,prdct[11],c8);
end
/////////////////////half adder task////////////////////////
task hfaddr(input a,b,output x,y);
begin
x=a^b;
y=a&b;
end
endtask
/////////////////////Full Adder adder task////////////////////////
task fuladdr(input a,b,c,output x,y);
reg w1;
begin
w1 =(a^b);
x = w1^c;
y =(w1&c)|(a&b);
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m; long long side[300001]; vector<long long> edges[300001]; bool vis[300001]; bool res = 1; map<long long, long long> mp; long long dfs(long long u, long long s) { vis[u] = 1; side[u] = s; ++mp[s]; long long ret = 1; for (long long i = 0; i < edges[u].size(); ++i) { long long nxt = edges[u][i]; if (vis[nxt] && side[u] == side[nxt]) { res = 0; } else if (!vis[nxt]) { ret += dfs(nxt, -s); } } return ret; } int32_t main() { cin >> n >> m; for (long long i = 0; i < m; ++i) { long long a, b; cin >> a >> b; edges[a].emplace_back(b); edges[b].emplace_back(a); } long long big = 0; long long cnt = 0; for (long long i = 1; i <= n; ++i) { if (vis[i]) continue; long long x = dfs(i, i); if (x == 2) ++cnt; big = max(big, x); } if (big == 1) { cout << 3 << n * (n - 1) * (n - 2) / 6 << n ; } else if (big == 2) { cout << 2 << cnt * (n - 2) << n ; } else if (res == 1) { long long ans = 0; for (auto it = mp.begin(); it != mp.end(); ++it) { long long x = (*it).second; ans += x * (x - 1) / 2; } cout << 1 << ans << n ; } else { cout << 0 1 n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_PP_V
/**
* iso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepn;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, KAPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepn, sleepn, KAPWR, VGND );
and and0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_sleepn);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/23/2015 05:17:53 PM
// Design Name:
// Module Name: testcase_basic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
`include "packet_type.vh"
`include "system.vh"
module testcase_basic();
localparam X_WIDTH = 2;
localparam Y_WIDTH = 2;
// -- Instancia de harnes de pruebas ----------------------------- >>>>>
harness
#(
.X_WIDTH(X_WIDTH),
.Y_WIDTH(Y_WIDTH)
)
arnes
();
// -- variables de simulacion ------------------------------------ >>>>>
genvar index_x;
genvar index_y;
// -- Generadores de trafico ------------------------------------- >>>>>
// -- Generadores de puertos en X ---------------------------- >>>>>
generate
for(index_x = 0; index_x < Y_WIDTH; index_x = index_x + 1)
begin:xneg_generators
// -- Bloque de inyector para puertos XNEG ----------- >>>>>
initial
begin: xneg_injectors
integer packet_count;
integer seed;
@(negedge arnes.reset);
for (packet_count = 0; packet_count < 30; packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
seed = $stime;
arnes.xneg_ports[index_x].packet_generator.random_packet(packet_count, seed);
arnes.xneg_ports[index_x].source.send_packet(arnes.xneg_ports[index_x].packet_generator.packet);
end
//xneg = 1'b1;
end
// -- Bloque de inyector para puertos XPOS ----------- >>>>>
initial
begin: xpos_injectors
integer packet_count;
integer seed;
@(negedge arnes.reset);
for (packet_count = 0; packet_count < 30; packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
seed = $stime;
arnes.xpos_ports[index_x].packet_generator.random_packet(packet_count, seed);
arnes.xpos_ports[index_x].source.send_packet(arnes.xpos_ports[index_x].packet_generator.packet);
end
//xneg = 1'b1;
end
end
endgenerate
// -- Generadores de puertos en Y ---------------------------- >>>>>
generate
for(index_y = 0; index_y < X_WIDTH; index_y = index_y + 1)
begin:yneg_generators
// -- Bloque de inyector para puertos YNEG ----------- >>>>>
initial
begin: yneg_injectors
integer packet_count;
integer seed;
@(negedge arnes.reset);
for (packet_count = 0; packet_count < 30; packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
seed = $stime;
arnes.yneg_ports[index_y].packet_generator.random_packet(packet_count, seed);
arnes.yneg_ports[index_y].source.send_packet(arnes.yneg_ports[index_y].packet_generator.packet);
end
//xneg = 1'b1;
end
// -- Bloque de inyector para puertos YPOS ----------- >>>>>
initial
begin: ypos_injectors
integer packet_count;
integer seed;
@(negedge arnes.reset);
for (packet_count = 0; packet_count < 30; packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
seed = $stime;
arnes.ypos_ports[index_y].packet_generator.random_packet(packet_count, seed);
arnes.ypos_ports[index_y].source.send_packet(arnes.ypos_ports[index_y].packet_generator.packet);
end
//xneg = 1'b1;
end
end
endgenerate
initial
begin: ciclo_principal
arnes.sync_reset();
repeat(100)
@(negedge harness.clk);
end
endmodule
|
module ram_wb
(
// Inputs
wbm0_adr_i, wbm0_bte_i, wbm0_cti_i, wbm0_cyc_i, wbm0_dat_i, wbm0_sel_i,
wbm0_stb_i, wbm0_we_i,
// Outputs
wbm0_ack_o, wbm0_err_o, wbm0_rty_o, wbm0_dat_o,
// Inputs
wbm1_adr_i, wbm1_bte_i, wbm1_cti_i, wbm1_cyc_i, wbm1_dat_i, wbm1_sel_i,
wbm1_stb_i, wbm1_we_i,
// Outputs
wbm1_ack_o, wbm1_err_o, wbm1_rty_o, wbm1_dat_o,
// Inputs
wbm2_adr_i, wbm2_bte_i, wbm2_cti_i, wbm2_cyc_i, wbm2_dat_i, wbm2_sel_i,
wbm2_stb_i, wbm2_we_i,
// Outputs
wbm2_ack_o, wbm2_err_o, wbm2_rty_o, wbm2_dat_o,
// Clock, reset
wb_clk_i, wb_rst_i
);
// Bus parameters
parameter dw = 32;
parameter aw = 32;
// Memory parameters
parameter mem_size_bytes = 32'h0000_0400; // 1KBytes
parameter mem_adr_width = 10; //(log2(mem_span));
input [aw-1:0] wbm0_adr_i;
input [1:0] wbm0_bte_i;
input [2:0] wbm0_cti_i;
input wbm0_cyc_i;
input [dw-1:0] wbm0_dat_i;
input [3:0] wbm0_sel_i;
input wbm0_stb_i;
input wbm0_we_i;
output wbm0_ack_o;
output wbm0_err_o;
output wbm0_rty_o;
output [dw-1:0] wbm0_dat_o;
input [aw-1:0] wbm1_adr_i;
input [1:0] wbm1_bte_i;
input [2:0] wbm1_cti_i;
input wbm1_cyc_i;
input [dw-1:0] wbm1_dat_i;
input [3:0] wbm1_sel_i;
input wbm1_stb_i;
input wbm1_we_i;
output wbm1_ack_o;
output wbm1_err_o;
output wbm1_rty_o;
output [dw-1:0] wbm1_dat_o;
input [aw-1:0] wbm2_adr_i;
input [1:0] wbm2_bte_i;
input [2:0] wbm2_cti_i;
input wbm2_cyc_i;
input [dw-1:0] wbm2_dat_i;
input [3:0] wbm2_sel_i;
input wbm2_stb_i;
input wbm2_we_i;
output wbm2_ack_o;
output wbm2_err_o;
output wbm2_rty_o;
output [dw-1:0] wbm2_dat_o;
input wb_clk_i;
input wb_rst_i;
// Internal wires to actual RAM
wire [aw-1:0] wbs_ram_adr_i;
wire [1:0] wbs_ram_bte_i;
wire [2:0] wbs_ram_cti_i;
wire wbs_ram_cyc_i;
wire [dw-1:0] wbs_ram_dat_i;
wire [3:0] wbs_ram_sel_i;
wire wbs_ram_stb_i;
wire wbs_ram_we_i;
wire wbs_ram_ack_o;
wire wbs_ram_err_o;
wire wbs_ram_rty_o;
wire [dw-1:0] wbs_ram_dat_o;
reg [2:0] input_select, last_selected;
wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
// Wires allowing selection of new input
assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
// Master select logic
always @(posedge wb_clk_i)
if (wb_rst_i)
input_select <= 0;
else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
| (input_select[2] & !wbm2_cyc_i))
input_select <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
input_select <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
input_select <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
input_select <= 3'b100;
always @(posedge wb_clk_i)
if (wb_rst_i)
last_selected <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
last_selected <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
last_selected <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
last_selected <= 3'b100;
// Mux input signals to RAM (default to wbm0)
assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
(input_select[1]) ? wbm1_adr_i :
(input_select[0]) ? wbm0_adr_i : 0;
assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
(input_select[1]) ? wbm1_bte_i :
(input_select[0]) ? wbm0_bte_i : 0;
assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
(input_select[1]) ? wbm1_cti_i :
(input_select[0]) ? wbm0_cti_i : 0;
assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
(input_select[1]) ? wbm1_cyc_i :
(input_select[0]) ? wbm0_cyc_i : 0;
assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
(input_select[1]) ? wbm1_dat_i :
(input_select[0]) ? wbm0_dat_i : 0;
assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
(input_select[1]) ? wbm1_sel_i :
(input_select[0]) ? wbm0_sel_i : 0;
assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
(input_select[1]) ? wbm1_stb_i :
(input_select[0]) ? wbm0_stb_i : 0;
assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
(input_select[1]) ? wbm1_we_i :
(input_select[0]) ? wbm0_we_i : 0;
// Output from RAM, gate the ACK, ERR, RTY signals appropriately
assign wbm0_dat_o = wbs_ram_dat_o;
assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
assign wbm0_err_o = wbs_ram_err_o & input_select[0];
assign wbm0_rty_o = 0;
assign wbm1_dat_o = wbs_ram_dat_o;
assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
assign wbm1_err_o = wbs_ram_err_o & input_select[1];
assign wbm1_rty_o = 0;
assign wbm2_dat_o = wbs_ram_dat_o;
assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
assign wbm2_err_o = wbs_ram_err_o & input_select[2];
assign wbm2_rty_o = 0;
ram_wb_b3 ram_wb_b3_0
(
// Outputs
.wb_ack_o (wbs_ram_ack_o),
.wb_err_o (wbs_ram_err_o),
.wb_rty_o (wbs_ram_rty_o),
.wb_dat_o (wbs_ram_dat_o),
// Inputs
.wb_adr_i (wbs_ram_adr_i),
.wb_bte_i (wbs_ram_bte_i),
.wb_cti_i (wbs_ram_cti_i),
.wb_cyc_i (wbs_ram_cyc_i),
.wb_dat_i (wbs_ram_dat_i),
.wb_sel_i (wbs_ram_sel_i),
.wb_stb_i (wbs_ram_stb_i),
.wb_we_i (wbs_ram_we_i),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i));
defparam ram_wb_b3_0.aw = aw;
defparam ram_wb_b3_0.dw = dw;
defparam ram_wb_b3_0.mem_size_bytes = mem_size_bytes;
defparam ram_wb_b3_0.mem_adr_width = mem_adr_width;
endmodule // ram_wb
|
/***********************************************************************
Array access test cases
Copyright (C) 2001 Eric LaForest,
Licenced under GPL
***********************************************************************/
module wire_test_case (array_out, clock, reset);
output [15:0] array_out;
input clock, reset;
reg [3:0] readptr;
reg [15:0] body [15:0];
wire [15:0] array_out;
assign array_out = body[readptr];
// reg [15:0] array_out;
// always @(readptr or body[readptr]) begin
// array_out <= body[readptr];
// end
always @(posedge clock) begin
if (reset == 0) begin
readptr <= 16'h0000;
body[0] <= 16'h0001; // Fibonnacci
body[1] <= 16'h0002;
body[2] <= 16'h0003;
body[3] <= 16'h0005;
body[4] <= 16'h0008;
body[5] <= 16'h000D;
body[6] <= 16'h0015;
end
else begin
readptr <= readptr + 16'h0001;
end
end
endmodule
module always_test_case (array_out, clock, reset);
output [15:0] array_out;
input clock, reset;
reg [3:0] readptr;
reg [15:0] body [15:0];
// wire [15:0] array_out;
// assign array_out = body[readptr];
reg [15:0] array_out;
always @(readptr or body[readptr]) begin
array_out <= body[readptr];
end
always @(posedge clock) begin
if (reset == 0) begin
readptr <= 16'h0000;
body[0] <= 16'h0001; // Fibonnacci
body[1] <= 16'h0002;
body[2] <= 16'h0003;
body[3] <= 16'h0005;
body[4] <= 16'h0008;
body[5] <= 16'h000D;
body[6] <= 16'h0015;
end
else begin
readptr <= readptr + 16'h0001;
end
end
endmodule
module BENCH ();
wire [15:0] array_out1, array_out2;
reg clock, reset;
integer count;
integer errors;
wire_test_case usingwire (array_out1, clock, reset);
always_test_case usingalways (array_out2, clock, reset);
initial begin
// $dumpfile("waves.vcd");
// $dumpvars(0, BENCH);
clock <= 0;
reset <= 0;
count <= 0;
#1000;
if (errors == 0)
$display("PASSED");
$finish;
end
always begin
# 10 clock <= ~clock;
end
always @(posedge clock) begin
count <= count + 1;
case (count)
10: begin
reset <= 1;
end
endcase
end
initial errors = 0;
always @(negedge clock)
if (array_out1 !== array_out2)
begin
$display("FAILED: %b !== %b", array_out1, array_out2);
errors = errors + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int sieve_size = 5e6; void solve() { int n; cin >> n; vector<int> a(n); for (int &x : a) cin >> x; vector<int> primes; vector<bool> sieve(sieve_size); for (int i = 2; i < int((sieve).size()); i++) { if (sieve[i]) continue; primes.push_back(i); for (int j = i + i; j < int((sieve).size()); j += i) { sieve[j] = true; } } auto get_decomp = [](int x) { vector<int> decomp; for (int j = 2; j * j <= x; j++) { if (x % j == 0) { decomp.push_back(j); x /= j; while (x % j == 0) x /= j; } } if (x != 1) decomp.push_back(x); return decomp; }; set<int> occupied_primes; vector<int> b(n); bool a_coprime = true; for (int i = 0, primes_idx = 0; i < n; i++) { if (a_coprime) { vector<int> decomp = get_decomp(a[i]); for (int x : decomp) { if (occupied_primes.count(x)) { a_coprime = false; break; } } if (!a_coprime) { for (a[i]++;; a[i]++) { decomp = get_decomp(a[i]); bool ok = true; for (int x : decomp) { if (occupied_primes.count(x)) { ok = false; break; } } if (ok) break; } } for (int x : decomp) occupied_primes.insert(x); b[i] = a[i]; } else { while (occupied_primes.count(primes[primes_idx])) primes_idx++; b[i] = primes[primes_idx++]; } } for (int x : b) cout << x << ; } int main() { ios::sync_with_stdio(0), cin.tie(0); int tcs = 1; for (int tc = 1; tc <= tcs; tc++) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int num[1005]; char num0[1005]; int res1[1005]; int N; int query() { int res = 0; for (int i = 0; i < N; i++) { if (num[i] != 0) { res *= 10; res += num[i]; } else if (num[i] == 0) { res *= 10; } } return res >= 0 ? res : -res; } int move_1() { int t = num[0]; for (int i = 0; i < N - 1; i++) { num[i] = num[i + 1]; } num[N - 1] = t; return 0; } int up1() { for (int i = 0; i < N; i++) { if (num[i] == 9) { num[i] = 0; } else { num[i] += 1; } } return 0; } void print() { printf( num = ); for (int i = 0; i < N; i++) { printf( %d , num[i]); } puts( ); } void printres() { for (int i = 0; i < N; i++) { printf( %d , res1[i]); } puts( ); } int panduan() { char temp1[1005], temp2[1005]; for (int i = 0; i < N; i++) { temp1[i] = num[i] + 0 ; } for (int i = 0; i < N; i++) { temp2[i] = res1[i] + 0 ; } if (strcmp(temp1, temp2) < 0) { return 1; } else return 0; } int copy1() { for (int i = 0; i < N; i++) { num[i] = num0[i] - 0 ; } return 0; } int copy2() { for (int i = 0; i < N; i++) { res1[i] = num[i]; } return 0; } int main() { while (scanf( %d , &N) != EOF) { getchar(); for (int i = 0; i < N; i++) { scanf( %c , &num0[i]); } int res = 1e9; copy1(); copy2(); for (int i = 0; i < 10; i++) { for (int j = 1; j <= N; j++) { move_1(); if (panduan() > 0) { copy2(); } } up1(); } printres(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__HA_FUNCTIONAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; bitset<100015> A[4096]; int n, m, k, q, lp, S, a[12][100015], t[100015], x[100015], y[100015], p[100015]; int main() { int i, j, l; scanf( %d %d %d , &n, &k, &q); for (i = 0; i < k; i++) for (j = 1; j <= n; j++) scanf( %d , &a[i][j]); for (i = 1; i <= q; i++) { scanf( %d %d %d , &t[i], &x[i], &y[i]); if (t[i] <= 2) x[i]--, y[i]--; else x[i]--; } for (i = 0; i < (1 << k); i++) { m = k; for (j = 0; j < k; j++) A[i][j] = ((i >> j) & 1); for (j = 1; j <= q; j++) { if (t[j] == 1) A[i][m++] = (A[i][x[j]] | A[i][y[j]]); if (t[j] == 2) A[i][m++] = (A[i][x[j]] & A[i][y[j]]); } } for (i = 1; i <= q; i++) { if (t[i] != 3) continue; for (j = 0; j < k; j++) p[j] = a[j][y[i]]; sort(p, p + k); for (j = 0; j < k; j++) { for (l = S = 0; l < k; l++) if (a[l][y[i]] > p[j]) S |= (1 << l); if (!A[S][x[i]]) break; } printf( %d n , p[j]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> mp1, mp2; long long n, k; long long a[200001]; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; long long res = 0; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = n; i >= 1; --i) { res += mp1[a[i] * k]; if (a[i] % k == 0) mp1[a[i]] += mp2[a[i] * k]; if (a[i] % (k * k) == 0) ++mp2[a[i]]; } cout << res; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2014 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat progress (f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
reflexivity.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
#include <bits/stdc++.h> using namespace std; int main() { int t, s, x; scanf( %d%d%d , &t, &s, &x); if (x < t) { puts( NO ); return 0; } int temp = (x - t) % s; if (temp == 0 || temp == 1) { if (x == t + 1) puts( NO ); else puts( YES ); } else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int add(int x, int y) { return ((x + y) % 998244353 + 998244353) % 998244353; } int mul(int x, int y) { return (long long)x * y % 998244353; } int mypow(int x, int c) { int ret = 1; while (c > 0) { if (c & 1) { ret = mul(ret, x); } c /= 2; x = mul(x, x); } return ret; } int seg[200002 * 4], ad[200002 * 4], mm[200002 * 4]; void init(int pos, int l, int r) { mm[pos] = 1; if (l == r) { return; } int mid = (l + r) / 2; init(pos * 2, l, mid); init(pos * 2 + 1, mid + 1, r); } void push(int pos, int l, int r) { seg[pos] = mul(seg[pos], mm[pos]); seg[pos] = add(seg[pos], mul(r - l + 1, ad[pos])); if (l != r) { mm[pos * 2] = mul(mm[pos], mm[pos * 2]); mm[pos * 2 + 1] = mul(mm[pos], mm[pos * 2 + 1]); ad[pos * 2] = add(mul(ad[pos * 2], mm[pos]), ad[pos]); ad[pos * 2 + 1] = add(mul(ad[pos * 2 + 1], mm[pos]), ad[pos]); } mm[pos] = 1; ad[pos] = 0; } void update(int pos, int l, int r, int ql, int qr, int m, int a) { push(pos, l, r); if (r < ql || qr < l) { return; } if (ql <= l && r <= qr) { mm[pos] = mul(mm[pos], m); ad[pos] = add(mul(m, ad[pos]), a); push(pos, l, r); return; } int mid = (l + r) / 2; update(pos * 2, l, mid, ql, qr, m, a); update(pos * 2 + 1, mid + 1, r, ql, qr, m, a); seg[pos] = add(seg[pos * 2], seg[pos * 2 + 1]); } int query(int pos, int l, int r, int ql, int qr) { push(pos, l, r); if (r < ql || qr < l) { return 0; } if (ql <= l && r <= qr) { return seg[pos]; } int mid = (l + r) / 2; return add(query(pos * 2, l, mid, ql, qr), query(pos * 2 + 1, mid + 1, r, ql, qr)); } set<pair<int, int> > s[200002]; void solve() { int n, q; scanf( %d %d , &n, &q); init(1, 1, n); for (int i = n; i; --i) { s[i].insert({n + 2, 0}); } while (q--) { int type, l, r; scanf( %d %d %d , &type, &l, &r); if (type == 1) { int x; scanf( %d , &x); int ml = l, mr = r; int cur = l; set<pair<int, int> >::iterator it = s[x].lower_bound({l + 1, 0}); if (it != s[x].begin()) { it = prev(it); pair<int, int> t = *it; if (t.second + 1 >= l) { ml = min(ml, t.first); mr = max(mr, t.second); s[x].erase(it); update(1, 1, n, l, min(r, t.second), 2, 0); cur = t.second + 1; } } while (true) { set<pair<int, int> >::iterator it = s[x].lower_bound({cur, 0}); pair<int, int> tmp = *it; if (tmp.first <= r + 1) { if (cur < tmp.first) { update(1, 1, n, cur, min(r, tmp.first - 1), 1, 1); } if (tmp.first <= r) { update(1, 1, n, tmp.first, min(tmp.second, r), 2, 0); } cur = tmp.second + 1; mr = max(mr, tmp.second); s[x].erase(it); } else { if (cur <= r) { update(1, 1, n, cur, r, 1, 1); } break; } } s[x].insert({ml, mr}); } else { printf( %d n , query(1, 1, n, l, r)); } } } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; cin >> s1 >> s2; int flag = 0; for (int i = 0, j = s2.length() - 1; i < s1.length(), j >= 0; i++, j--) { if (s1[i] == s2[j]) { flag++; } } if (flag == s1.length()) cout << YES << endl; else cout << NO ; return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fei4_rx #(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter DSIZE = 10,
parameter DATA_IDENTIFIER = 0,
parameter ABUSWIDTH = 16,
parameter USE_FIFO_CLK = 0
) (
input wire RX_CLK,
input wire RX_CLK2X,
input wire DATA_CLK,
input wire RX_DATA,
output wire RX_READY,
output wire RX_8B10B_DECODER_ERR,
output wire RX_FIFO_OVERFLOW_ERR,
input wire FIFO_CLK,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire RX_FIFO_FULL,
output wire RX_ENABLED,
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
wire FIFO_CLK_INT;
generate
if (USE_FIFO_CLK == 0)
assign FIFO_CLK_INT = BUS_CLK;
else
assign FIFO_CLK_INT = FIFO_CLK;
endgenerate
fei4_rx_core #(
.DSIZE(DSIZE),
.DATA_IDENTIFIER(DATA_IDENTIFIER),
.ABUSWIDTH(ABUSWIDTH)
) i_fei4_rx_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.RX_CLK(RX_CLK),
.RX_CLK2X(RX_CLK2X),
.DATA_CLK(DATA_CLK),
.RX_DATA(RX_DATA),
.RX_READY(RX_READY),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR),
.FIFO_CLK(FIFO_CLK_INT),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.RX_FIFO_FULL(RX_FIFO_FULL),
.RX_ENABLED(RX_ENABLED)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string s[n + 1]; for (int i = 0; i < n; i++) { cin >> s[i]; } long long ans = 1; for (int i = 0; i < m; i++) { unordered_set<char> b; for (int j = 0; j < n; j++) { b.insert(s[j][i]); } ans = (ans * b.size()) % 1000000007; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int solve() { long long n; cin >> n; vector<long long int> a, b; long long x; for (long long int i = 0; i < n; i++) { cin >> x; if (x > 0) a.push_back(x); else b.push_back(x); } long long sum1 = accumulate(a.begin(), a.end(), (long long)0); long long sum2 = abs(accumulate(b.begin(), b.end(), (long long)0)); if (sum1 > sum2) cout << first ; else if (sum2 > sum1) cout << second ; else { long long s = min((long long int)a.size(), (long long int)b.size()); for (long long int i = 0; i < s; i++) { if (a[i] > abs(b[i])) { cout << first ; return 0; } else if (a[i] < abs(b[i])) { cout << second ; return 0; } } if (x > 0) cout << first ; else cout << second ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVGND2_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 700 + 7; const int MOD = 1e9 + 7; const int INF = 1e9 + 7; int a[maxn]; int g[maxn][maxn]; int n; struct as { int l, r, v; bool operator<(const as& b) const { if (l < b.l) return true; if (l > b.l) return false; if (r < b.r) return true; if (r > b.r) return false; return v < b.v; } }; map<as, bool> mp; int gcd(int x, int y) { return x == 0 ? y : gcd(y % x, x); } void get() { int i, j; for (i = 0; i <= n; i++) { for (j = 0; j <= n; j++) { if (i != j && gcd(a[i], a[j]) != 1) { g[i][j] = 1; } } } return; } bool solve(int l, int r, int pos) { if (l > r) return true; if (mp.count(as{l, r, pos})) { return mp[as{l, r, pos}]; } int i, j; for (i = l; i <= r; i++) { if (g[pos][i]) { if (solve(l, i - 1, i) && solve(i + 1, r, i)) { mp[as{l, r, pos}] = true; return true; } } } mp[as{l, r, pos}] = false; return false; } int main() { int i, j, m, t, z; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } get(); if (solve(1, n, 0)) { puts( Yes ); } else puts( No ); return 0; }
|
module main;
localparam BYTESIZE = 8;
localparam STRLEN = 4;
localparam [15:0] CHAR = "10";
function [STRLEN*BYTESIZE - 1 : 0] bits2text;
input [STRLEN-1:0] use_map;
integer idx;
begin
bits2text = 0;
for (idx = 0 ; idx < STRLEN ; idx = idx+1) begin
bits2text[(idx*BYTESIZE) +: BYTESIZE] = CHAR[BYTESIZE*use_map[idx] +: BYTESIZE];
end
end
endfunction
localparam [STRLEN*BYTESIZE - 1 : 0] str0010 = bits2text(4'b0010);
localparam [STRLEN*BYTESIZE - 1 : 0] str0100 = bits2text(4'b0100);
localparam [STRLEN*BYTESIZE - 1 : 0] str0011 = bits2text(4'b0011);
localparam [STRLEN*BYTESIZE - 1 : 0] str1100 = bits2text(4'b1100);
reg [STRLEN*BYTESIZE - 1 : 0] tmp;
initial begin
tmp = bits2text(4'b0010);
if (tmp !== str0010) begin
$display("FAILED -- str0010=%h, expect %h", str0010, tmp);
$finish;
end
tmp = bits2text(4'b0100);
if (tmp !== str0100) begin
$display("FAILED -- str0100=%h, expect %h", str0100, tmp);
$finish;
end
tmp = bits2text(4'b0011);
if (tmp !== str0011) begin
$display("FAILED -- str0011=%h, expect %h", str0011, tmp);
$finish;
end
tmp = bits2text(4'b1100);
if (tmp !== str1100) begin
$display("FAILED -- str1100=%h, expect %h", str1100, tmp);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
module top();
localparam width_lp = 32;
localparam debug_lp = 0;
// These declarations export the functions from the leaf
// modules. There may be a cleaner way to do this but I haven't
// found it yet.
logic ns_clk, ns_by2_clk, ns_reset, debug_o;
parameter lc_cycle_time_p = ;
bsg_nonsynth_dpi_clock_gen
#(.cycle_time_p(lc_cycle_time_p)
)
core_clk_gen
(.o(ns_clk));
bsg_nonsynth_dpi_clock_gen
#(.cycle_time_p(lc_cycle_time_p/2)
)
core_clk_gen2
(.o(ns_by2_clk));
bsg_nonsynth_reset_gen
#(
.num_clocks_p(1)
,.reset_cycles_lo_p(1)
,.reset_cycles_hi_p(2)
)
reset_gen
(
.clk_i(ns_clk)
,.async_reset_o(ns_reset)
);
int cycle = 0;
always @(posedge ns_by2_clk) begin
cycle <= cycle +1;
if(debug_o)
$display("BSG DBGINFO: top by2 -- Cycle %d", cycle);
end
always @(posedge ns_clk) begin
if(debug_o)
$display("BSG DBGINFO: top -- Cycle %d", cycle);
end
logic [width_lp-1:0] data_i;
logic [width_lp-1:0] data_o;
logic v_o, v_i, ready_o, yumi_i;
bsg_nonsynth_dpi_from_fifo
#(
.width_p (width_lp)
,.debug_p (debug_lp))
f2d_i
(
.yumi_o (yumi_i)
,.debug_o (debug_o)
,.clk_i (ns_clk)
,.reset_i (ns_reset)
,.v_i (v_o)
,.data_i (data_o));
bsg_nonsynth_dpi_to_fifo
#(
.width_p (width_lp)
,.debug_p (debug_lp))
d2f_i
(
.debug_o()
,.v_o(v_i)
,.data_o(data_i)
,.ready_i(ready_o)
,.clk_i(ns_clk)
,.reset_i(ns_reset));
bsg_fifo_1r1w_small_unhardened
#(.els_p(4)
,.width_p(width_lp)
)
fifo_i
(
.clk_i(ns_clk)
,.reset_i(ns_reset)
,.v_i(v_i)
,.ready_o(ready_o)
,.data_i(data_i)
,.v_o(v_o)
,.data_o(data_o)
,.yumi_i(yumi_i));
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; using ull = unsigned long long; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ll n; int k; cin >> n >> k; ll s = n * (n - 1) / 2; s %= n; ll t = 0; ll cnt = 0; for (int i = 0; i < k; i++) { ll a, b; cin >> a >> b; (t += a * b) %= n; cnt += b; } if (cnt < n) { cout << 1 n ; } else if (cnt > n) { cout << -1 n ; } else { if (s == t) { cout << 1 n ; } else { cout << -1 n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_2_V
`define SKY130_FD_SC_MS__NOR4B_2_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BLACKBOX_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, m, ans, x, i, j, s; double a[100], b[100]; map<double, pair<long long, long long> > mp; map<double, pair<long long, long long> >::iterator it, it2; long long num(long long x) { s = 0; while (x) { s++; x -= x & -x; } return s; } int main() { cin >> n >> m; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < m; i++) cin >> b[i]; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { mp[(a[i] + b[j]) / 2.0].first |= (1LL << i); mp[(a[i] + b[j]) / 2.0].second |= (1LL << j); } for (it = mp.begin(); it != mp.end(); it++) for (it2 = it; it2 != mp.end(); it2++) { x = num((*it).second.first | (*it2).second.first) + num((*it).second.second | (*it2).second.second); if (x > ans) ans = x; } cout << ans; return 0; }
|
// file: Clock48MHZ.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____48.031______0.000______50.0______108.043_____75.988
// CLK_OUT2___190.625______0.000______50.0_______84.594_____75.988
// CLK_OUT3___101.667______0.000______50.0_______94.528_____75.988
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock48MHZ,clk_wiz_v3_6,{component_name=Clock48MHZ,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=3,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module Clock48MHZ
(// Clock in ports
input CLK_100,
// Clock out ports
output CLK_48,
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_100));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (15.250),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (31.750),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (15),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_48),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT1),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT2),
.I (clkout2));
endmodule
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Log:
5/18/2013: Implemented new naming Scheme
*/
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
${PORTS}
);
${MEM_PARAMS}
${MEM_SELECT}
${DATA}
${ACK}
${INT}
${ASSIGN}
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_tb_top.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module is the synthesizable test bench for the memory interface.
// This Test bench is to compare the write and the read data and generate
// an error flag.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter ROW_WIDTH = 14,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter BURST_LEN = 4
)
(
input clk0,
input rst0,
input app_af_afull,
input app_wdf_afull,
input rd_data_valid,
input [APPDATA_WIDTH-1:0] rd_data_fifo_out,
input phy_init_done,
output app_af_wren,
output [2:0] app_af_cmd,
output [30:0] app_af_addr,
output app_wdf_wren,
output [APPDATA_WIDTH-1:0] app_wdf_data,
output [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output error,
output error_cmp
);
localparam BURST_LEN_DIV2 = BURST_LEN/2;
localparam TB_IDLE = 3'b000;
localparam TB_WRITE = 3'b001;
localparam TB_READ = 3'b010;
wire app_af_afull_r ;
wire app_af_afull_r1 ;
wire app_af_afull_r2;
reg app_af_not_afull_r;
wire [APPDATA_WIDTH-1:0] app_cmp_data;
wire app_wdf_afull_r;
wire app_wdf_afull_r1 ;
wire app_wdf_afull_r2;
reg app_wdf_not_afull_r ;
reg [2:0] burst_cnt;
reg phy_init_done_tb_r;
wire phy_init_done_r;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [2:0] state;
reg [3:0] state_cnt;
reg wr_addr_en ;
reg wr_data_en ;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//*****************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk0) begin
rst_r <= rst0;
rst_r1 <= rst_r;
end
// Instantiate flops for timing.
FDRSE ff_af_afull_r
(
.Q (app_af_afull_r),
.C (clk0),
.CE (1'b1),
.D (app_af_afull),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_af_afull_r1
(
.Q (app_af_afull_r1),
.C (clk0),
.CE (1'b1),
.D (app_af_afull_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_af_afull_r2
(
.Q (app_af_afull_r2),
.C (clk0),
.CE (1'b1),
.D (app_af_afull_r1),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_afull_r
(
.Q (app_wdf_afull_r),
.C (clk0),
.CE (1'b1),
.D (app_wdf_afull),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_afull_r1
(
.Q (app_wdf_afull_r1),
.C (clk0),
.CE (1'b1),
.D (app_wdf_afull_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_afull_r2
(
.Q (app_wdf_afull_r2),
.C (clk0),
.CE (1'b1),
.D (app_wdf_afull_r1),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_phy_init_done
(
.Q (phy_init_done_r),
.C (clk0),
.CE (1'b1),
.D (phy_init_done),
.R (1'b0),
.S (1'b0)
);
//***************************************************************************
// State Machine for writing to WRITE DATA & ADDRESS FIFOs
// state machine changed for low FIFO threshold values
//***************************************************************************
always @(posedge clk0) begin
if (rst_r1) begin
wr_data_en <= 1'bx;
wr_addr_en <= 1'bx;
state[2:0] <= TB_IDLE;
state_cnt <= 4'bxxxx;
app_af_not_afull_r <= 1'bx;
app_wdf_not_afull_r <= 1'bx;
burst_cnt <= 3'bxxx;
phy_init_done_tb_r <= 1'bx;
end else begin
wr_data_en <= 1'b0;
wr_addr_en <= 1'b0;
app_af_not_afull_r <= ~app_af_afull_r2;
app_wdf_not_afull_r <= ~app_wdf_afull_r2;
phy_init_done_tb_r <= phy_init_done_r;
case (state)
TB_IDLE: begin
state_cnt <= 4'd0;
burst_cnt <= BURST_LEN_DIV2 - 1;
// only start writing when initialization done
if (app_wdf_not_afull_r && app_af_not_afull_r && phy_init_done_tb_r)
state <= TB_WRITE;
end
TB_WRITE:
if (app_wdf_not_afull_r && app_af_not_afull_r) begin
wr_data_en <= 1'b1;
// When we're done with the current burst...
if (burst_cnt == 3'd0) begin
burst_cnt <= BURST_LEN_DIV2 - 1;
wr_addr_en <= 1'b1;
// Writes occurs in groups of 8 consecutive bursts. Once 8 writes
// have been issued, now issue the corresponding read back bursts
if (state_cnt == 4'd7) begin
state <= TB_READ;
state_cnt <= 4'd0;
end else
state_cnt <= state_cnt + 1;
end else
burst_cnt <= burst_cnt - 1;
end
TB_READ: begin
burst_cnt <= BURST_LEN_DIV2 - 1;
if (app_af_not_afull_r) begin
wr_addr_en <= 1'b1;
// if finished with all 8 reads, proceed to next 8 writes
if (state_cnt == 4'd7) begin
state <= TB_WRITE;
state_cnt <= 4'd0;
end else
state_cnt <= state_cnt + 1;
end
end
endcase
end
end
// Read data comparision
ddr2_tb_test_cmp #
(
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE)
)
u_tb_test_cmp
(
.clk (clk0),
.rst (rst0),
.phy_init_done (phy_init_done_tb_r),
.rd_data_valid (rd_data_valid),
.app_cmp_data (app_cmp_data),
.rd_data_fifo_in (rd_data_fifo_out),
.error (error),
.error_cmp (error_cmp)
);
// Command/Address and Write Data generation
ddr2_tb_test_gen #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_tb_test_gen
(
.clk (clk0),
.rst (rst0),
.wr_addr_en (wr_addr_en),
.wr_data_en (wr_data_en),
.rd_data_valid (rd_data_valid),
.app_af_wren (app_af_wren),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.app_cmp_data (app_cmp_data)
);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date: 03:34:47 07/25/2015
// Design Name: SAM Coupé clone
// Module Name: ram
// Project Name: SAM Coupé clone
// Target Devices: Spartan 6
// Tool versions: ISE 12.4
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ram_dual_port_turnos (
input wire clk,
input wire whichturn,
input wire [18:0] vramaddr,
input wire [18:0] cpuramaddr,
input wire cpu_we_n,
input wire [7:0] data_from_cpu,
output reg [7:0] data_to_asic,
output reg [7:0] data_to_cpu,
// Actual interface with SRAM
output reg [18:0] sram_a,
output reg sram_we_n,
inout wire [7:0] sram_d
);
assign sram_d = (cpu_we_n == 1'b0 && whichturn == 1'b0)? data_from_cpu : 8'hZZ;
always @* begin
data_to_cpu = 8'hFF;
data_to_asic = 8'hFF;
if (whichturn == 1'b1) begin // ASIC
sram_a = vramaddr;
sram_we_n = 1'b1;
data_to_asic = sram_d;
end
else begin
sram_a = cpuramaddr;
sram_we_n = cpu_we_n;
data_to_cpu = sram_d;
end
end
endmodule
module ram_dual_port (
input wire clk,
input wire whichturn,
input wire [18:0] vramaddr,
input wire [18:0] cpuramaddr,
input wire mreq_n,
input wire rd_n,
input wire wr_n,
input wire rfsh_n,
input wire [7:0] data_from_cpu,
output wire [7:0] data_to_asic,
output reg [7:0] data_to_cpu,
// Actual interface with SRAM
output reg [18:0] sram_a,
output reg sram_we_n,
inout wire [7:0] sram_d
);
parameter ASIC = 3'd0,
CPU1 = 3'd1,
CPU2 = 3'd2,
CPU3 = 3'd3,
CPU4 = 3'd4,
CPU5 = 3'd5,
CPU6 = 3'd6,
CPU7 = 3'd7;
reg [2:0] state = ASIC;
assign sram_d = (state == CPU5 || state == CPU6)? data_from_cpu : 8'hZZ;
assign data_to_asic = sram_d;
always @* begin
if (whichturn == 1'b1) begin
sram_a = vramaddr;
sram_we_n = 1'b1;
end
else begin
sram_a = cpuramaddr;
data_to_cpu = sram_d;
if (state == CPU6 || state == CPU5)
sram_we_n = 1'b0;
else
sram_we_n = 1'b1;
end
end
always @(posedge clk) begin
case (state)
ASIC:
begin
if (whichturn == 1'b0)
state <= CPU1;
end
CPU1:
begin
if (whichturn == 1'b1)
state <= ASIC;
else if (mreq_n == 1'b0 && rd_n == 1'b0)
state <= CPU2;
else if (mreq_n == 1'b0 && rd_n == 1'b1 && rfsh_n == 1'b1)
state <= CPU5;
end
CPU2:
begin
if (whichturn == 1'b1)
state <= ASIC;
else
state <= CPU3;
end
CPU3:
begin
if (whichturn == 1'b1)
state <= ASIC;
else
state <= CPU1;
end
CPU5:
begin
if (whichturn == 1'b1)
state <= ASIC;
else if (mreq_n == 1'b1)
state <= CPU1;
else if (wr_n == 1'b0)
state <= CPU6;
end
CPU6:
begin
state <= CPU7;
end
CPU7:
begin
if (whichturn == 1'b1)
state <= ASIC;
else if (mreq_n == 1'b1)
state <= CPU1;
end
default:
begin
if (whichturn == 1'b1)
state <= ASIC;
else
state <= CPU1;
end
endcase
end
endmodule
|
//
// Copyright (c) 2013 Colin Rothwell
// Copyright (c) 2014 A. Theodore Markettos
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
// intermediary between Bluespec, which outputs an enable signal,
// and Megawizard's verilog, which doesn't have that input
module doubleSqrtWrapper (
clock,
data,
result,
dummy_enable);
input clock;
input [63:0] data;
output [63:0] result;
input dummy_enable;
doubleSqrt doubleSqrt_component (
.clock(clock),
.data(data),
.result(result)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int const INF = 100 + (int)1e9; long long const INFL = 100 + (long long)1e18; long double const PI = 3.141592653589793238462643L; mt19937 tw(960172); bool is_prime(long long x) { for (long long y = 2; y * y <= x; ++y) if (x % y == 0) return 0; return x > 1; } long long rnd(long long x, long long y) { static uniform_int_distribution<long long> d; return d(tw) % (y - x + 1) + x; } long long sqr(int a) { return (long long)a * a; } template <class T> T sqr(T const& a) { return a * a; } long long gcd(long long a, long long b) { while (b > 0) { long long t = a % b; a = b; b = t; } return a; } void solve() { int n, k; cin >> n >> k; if (n <= 3 || k == 1 || k > 3 || (n == 4 && k == 2)) { cout << -1 << n ; return; } vector<pair<int, int>> edges; if (k == 2) { for (int i = 1; i < n; ++i) edges.emplace_back(i, i + 1); } else { edges.emplace_back(1, 2); edges.emplace_back(2, 3); edges.emplace_back(3, 4); for (int i = 5; i <= n; ++i) { edges.emplace_back(i, 1); edges.emplace_back(i, 3); if (i > 5) { edges.emplace_back(i, i - 1); if (i > 6) edges.emplace_back(i, 5); } } } cout << edges.size() << n ; for (auto e : edges) cout << e.first << << e.second << n ; } int main() { cout << setprecision(15) << fixed; int tcnt = 1; for (int test = 1; test <= tcnt; ++test) solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A211OI_FUNCTIONAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_FUNCTIONAL_PP_V
|
module deserializer(
clk, //serialized data proper clock
enable, //suspend while enable on low
reset, //set output to zero and reset counter to 0 on high
framesize, //number of bits to be deserialized - 1
in, //serialized data
out, //deserialized data
complete //reset counter to 0 and hold out's data while high
);
parameter BITS = 136; //size of deserializer
parameter BITS_COUNTER = 8; //size of counter, must be at least log2(BITS)
parameter COUNTER_MAX = 8'hFF; //max possible value
input clk, enable, reset, in;
input [BITS_COUNTER-1:0] framesize;
output reg complete;
output reg [BITS-1:0] out;
reg [BITS_COUNTER-1:0] counter; //we need to know which array item (out) to write on
always@(posedge reset) begin
out = 0;
counter = framesize;
complete = 0;
end
always@(posedge clk) begin
if(enable) begin
if(~complete) begin //as long there's not any reset state, count
out[counter] <= in;
counter = counter - 1; //next item
end
end else begin
complete = 0;
end
end
always@(counter) begin
if(counter == COUNTER_MAX) begin //all bits have been read
complete = 1;
end
end
always@(complete) begin
counter = framesize; //this way there's no need to reset every time we start a transaction (resetting all out bits consumes power)
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_BLACKBOX_V
/**
* udp_dff$PE_pp$PG: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PE_pp$PG (
Q ,
D ,
CLK ,
DATA_EN,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input DATA_EN;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_BLACKBOX_V
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
//Date : Tue Sep 19 00:28:00 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target bd_c3fe_wrapper.bd
//Design : bd_c3fe_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module bd_c3fe_wrapper
(SLOT_0_AXI_araddr,
SLOT_0_AXI_arready,
SLOT_0_AXI_arvalid,
SLOT_0_AXI_awaddr,
SLOT_0_AXI_awready,
SLOT_0_AXI_awvalid,
SLOT_0_AXI_bready,
SLOT_0_AXI_bresp,
SLOT_0_AXI_bvalid,
SLOT_0_AXI_rdata,
SLOT_0_AXI_rready,
SLOT_0_AXI_rresp,
SLOT_0_AXI_rvalid,
SLOT_0_AXI_wdata,
SLOT_0_AXI_wready,
SLOT_0_AXI_wstrb,
SLOT_0_AXI_wvalid,
clk,
resetn);
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arready;
input SLOT_0_AXI_arvalid;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awready;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_bready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input [31:0]SLOT_0_AXI_rdata;
input SLOT_0_AXI_rready;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input [31:0]SLOT_0_AXI_wdata;
input SLOT_0_AXI_wready;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input clk;
input resetn;
wire [8:0]SLOT_0_AXI_araddr;
wire SLOT_0_AXI_arready;
wire SLOT_0_AXI_arvalid;
wire [8:0]SLOT_0_AXI_awaddr;
wire SLOT_0_AXI_awready;
wire SLOT_0_AXI_awvalid;
wire SLOT_0_AXI_bready;
wire [1:0]SLOT_0_AXI_bresp;
wire SLOT_0_AXI_bvalid;
wire [31:0]SLOT_0_AXI_rdata;
wire SLOT_0_AXI_rready;
wire [1:0]SLOT_0_AXI_rresp;
wire SLOT_0_AXI_rvalid;
wire [31:0]SLOT_0_AXI_wdata;
wire SLOT_0_AXI_wready;
wire [3:0]SLOT_0_AXI_wstrb;
wire SLOT_0_AXI_wvalid;
wire clk;
wire resetn;
bd_c3fe bd_c3fe_i
(.SLOT_0_AXI_araddr(SLOT_0_AXI_araddr),
.SLOT_0_AXI_arready(SLOT_0_AXI_arready),
.SLOT_0_AXI_arvalid(SLOT_0_AXI_arvalid),
.SLOT_0_AXI_awaddr(SLOT_0_AXI_awaddr),
.SLOT_0_AXI_awready(SLOT_0_AXI_awready),
.SLOT_0_AXI_awvalid(SLOT_0_AXI_awvalid),
.SLOT_0_AXI_bready(SLOT_0_AXI_bready),
.SLOT_0_AXI_bresp(SLOT_0_AXI_bresp),
.SLOT_0_AXI_bvalid(SLOT_0_AXI_bvalid),
.SLOT_0_AXI_rdata(SLOT_0_AXI_rdata),
.SLOT_0_AXI_rready(SLOT_0_AXI_rready),
.SLOT_0_AXI_rresp(SLOT_0_AXI_rresp),
.SLOT_0_AXI_rvalid(SLOT_0_AXI_rvalid),
.SLOT_0_AXI_wdata(SLOT_0_AXI_wdata),
.SLOT_0_AXI_wready(SLOT_0_AXI_wready),
.SLOT_0_AXI_wstrb(SLOT_0_AXI_wstrb),
.SLOT_0_AXI_wvalid(SLOT_0_AXI_wvalid),
.clk(clk),
.resetn(resetn));
endmodule
|
#include <bits/stdc++.h> using namespace std; inline pair<int, int> best(pair<int, int> a, pair<int, int> b) { if ((a.first > b.first) || ((a.first == b.first) && (a.second < b.second))) return a; return b; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; string s; cin >> n; cin >> s; cin >> m; vector<vector<int> > ka(n, vector<int>(2)); vector<vector<int> > kb(n, vector<int>(2)); vector<int> kv(n); vector<int> preva(n, -1); if (s[0] == a ) { preva[0] = 0; ka[0][0] = 1; } if (s[0] == b ) kb[0][0] = 1; if (s[0] == ? ) kv[0] = 1, preva[0] = 0; for (int i = 1; i < n; i++) { ka[i][0] = ka[i - 1][0]; ka[i][1] = ka[i - 1][1]; if (s[i] == a ) ka[i][i % 2]++; kb[i][0] = kb[i - 1][0]; kb[i][1] = kb[i - 1][1]; if (s[i] == b ) kb[i][i % 2]++; if ((s[i] == a ) || (s[i] == ? )) preva[i] = i; else preva[i] = preva[i - 1]; kv[i] = kv[i - 1]; if (s[i] == ? ) kv[i]++; } vector<vector<pair<int, int> > > dp(n, vector<pair<int, int> >(2)); if (((s[0] == a ) || (s[0] == ? )) && (m <= n) && (kb[m - 1][0] == 0) && (ka[m - 1][1] == 0)) dp[0][1] = {1, kv[m - 1]}; for (int i = 1; i < n; i++) { dp[i][0] = best(dp[i - 1][0], dp[i - 1][1]); if (i + m - 1 >= n) continue; int bada = ka[i + m - 1][(i % 2) ^ 1] - ka[i - 1][(i % 2) ^ 1]; int badb = kb[i + m - 1][i % 2] - kb[i - 1][i % 2]; if ((bada != 0) || (badb != 0)) continue; if (i < m) { dp[i][1] = {1, kv[i + m - 1] - kv[i - 1]}; } else { int p = preva[i - m]; if (p < 0) { dp[i][1] = {1, kv[i + m - 1] - kv[i - 1]}; } else { dp[i][1] = best(dp[p][0], dp[p][1]); dp[i][1].first++; dp[i][1].second += kv[i + m - 1] - kv[i - 1]; } } } pair<int, int> rez = best(dp[n - 1][0], dp[n - 1][1]); cout << rez.second << n ; return 0; }
|
#include<bits/stdc++.h> using namespace std; typedef pair<int,int> pii; typedef pair<string,int> psi; typedef pair<int,string> pis; typedef array<int,2> aii; typedef array<int,3> aiii; typedef array<int,4> aiiii; typedef unsigned long long ull; typedef long long int ll; typedef array<ll,2> all; typedef array<ll,3> alll; typedef array<ll,4> allll; #define pb push_back #define ff first #define ss second #define MAX 200005 #define MOD 1000000007 #define INF 1e9 mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); vector<aiii>adj[MAX]; int xMove[] = { 0,1,0,-1,1,1,-1,-1, 2, 2, -2, -2, 1, 1, -1, -1 }; int yMove[] = { 1,0,-1,0,1,-1,1,-1, 1, -1, 1, -1, 2, -2, 2, -2 }; string s; int dp[MAX][2],n; int solve(int i, int p) { if(i==n) return 0; if(dp[i][p]!=-1) return dp[i][p]; int ans=0; if(s[i]== 1 ) { if(p==0) ans=1+solve(i+1,1); } else if(s[i]== 0 ) { if(p==1) ans=1+solve(i+1,0); } else { if(p==0) ans=1+solve(i+1,1); else ans=1+solve(i+1,0); } return dp[i][p]=ans; } int main() { //freopen( input.in , r ,stdin); //freopen( output.txt , w ,stdout); cin.tie(0),cout.tie(0); ios_base::sync_with_stdio(0); cout.setf(ios::fixed); cout.precision(10); int TC=1; int m,k,q; cin>>TC; for(int t1=1; t1<=TC; t1++) { cin>>s; n=s.size(); for(int i=0;i<s.size();i++) dp[i][0]=-1,dp[i][1]=-1; ll ans=0; for(int i=0;i<n;i++) { if(s[i]== 0 ) ans+=1+solve(i+1,0); else if(s[i]== 1 ) ans+=1+solve(i+1,1); else ans+=max(1+solve(i+1,0),1+solve(i+1,1)); } cout<<ans<< n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool within(int x1, int x2, int y1, int y2, int px, int py) { if (x1 <= px and px <= x2 and y1 <= py and py <= y2) { return true; } return false; } int main() { ios::sync_with_stdio(false); int y, x, v, n; cin >> y >> x >> v >> n; int py[v], px[v]; for (int i = 0; i < v; i++) { cin >> px[i] >> py[i]; py[i]--, px[i]--; } int res = 0; for (int x1 = 0; x1 < x; x1++) { for (int x2 = x1; x2 < x; x2++) { for (int y1 = 0; y1 < y; y1++) { for (int y2 = y1; y2 < y; y2++) { int found = 0; for (int i = 0; i < v; i++) { if (within(x1, x2, y1, y2, py[i], px[i])) { found++; } } if (found >= n) { res++; } } } } } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; int ABS(int a) { if (a < 0) return (-a); return a; } void input() {} int n, table; int a[55]; double dp[55][55][55][55]; int aim; double f(int idx, int sum, int k, int cnt) { if (idx == n) { if (sum != aim || cnt == 0) return 0; return (k * cnt * 1.0) / ((double)(n)-k); } double &res = dp[idx][sum][k][cnt]; if (res > -0.5) return res; double invK = (k + 1.0) / (idx + 1.0); double invNK = (idx - k + 1.0) / (idx + 1.0); res = 0.0; if (sum + a[idx] <= aim) { res += invK * f(idx + 1, sum + a[idx], k + 1, cnt); } if (aim + a[idx] > table) cnt++; res += invNK * f(idx + 1, sum, k, cnt); return res; } int main() { input(); cin >> n; int sum = 0; for (int i = (0); i < (n); ++i) { cin >> a[i]; sum += a[i]; } cin >> table; if (sum <= table) { printf( %d n , n); return 0; } double ans = 0.0; for (int i = (1); i < (table + 1); ++i) { for (int I = (0); I < (55); ++I) for (int j = (0); j < (55); ++j) for (int k = (0); k < (55); ++k) for (int l = (0); l < (55); ++l) dp[I][j][k][l] = -1.0; aim = i; ans += f(0, 0, 0, 0); } printf( %.12lf n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, q; std::vector<int> val(500005); std::map<int, pair<int, int> > edges; std::vector<pair<int, int> > query(500005); int vis[500005]; int par[500005]; set<pair<int, int> > ss[500005]; int sz[500005]; std::vector<pair<int, int> > changes[500005]; int st[500005], en[500005]; int getpar(int x) { if (par[x] == x) return x; else return getpar(par[x]); } void merge(int n1, int n2, int idx) { int p1 = getpar(n1); int p2 = getpar(n2); if (p1 == p2) return; if (sz[p1] > sz[p2]) swap(p1, p2); sz[p2] += sz[p1]; sz[p1] = 0; for (auto i : ss[p1]) { ss[p2].insert(i); } par[p1] = p2; if (idx != -1) { st[idx] = p1; en[idx] = p2; for (auto i : ss[p1]) { changes[idx].push_back(i); } } ss[p1].clear(); } int getans(int node) { int pp = getpar(node); pair<int, int> zz = *(ss[pp].rbegin()); cout << zz.first << n ; auto it = ss[pp].rbegin(); ss[pp].erase(zz); val[zz.second] = 0; ss[pp].insert({val[zz.second], zz.second}); return zz.first; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> q; for (int i = 1; i < n + 1; i++) { cin >> val[i]; sz[i] = 1; par[i] = i; ss[par[i]].insert({val[i], i}); } for (int i = 1; i < m + 1; i++) { int x, y; cin >> x >> y; edges[i] = {x, y}; } for (int i = 1; i < q + 1; i++) { cin >> query[i].first >> query[i].second; if (query[i].first == 2) { vis[query[i].second] = 1; } } for (int i = 1; i < m + 1; i++) { if (!vis[i]) { merge(edges[i].first, edges[i].second, -1); } } for (int i = q; i >= 1; i--) { if (query[i].first == 2) { merge(edges[query[i].second].first, edges[query[i].second].second, i); } } for (int i = 1; i < q + 1; i++) { if (query[i].first == 1) { getans(query[i].second); } else { int st1 = st[i]; int en1 = en[i]; ss[st1].clear(); for (auto j : changes[i]) { ss[st1].insert({val[j.second], j.second}); ss[en1].erase({val[j.second], j.second}); } par[st1] = st1; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int x = 0, y = 0, dp = 0, tmp; int sum = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == U ) { y++; if (x < y) { if (dp == 2) sum++; dp = 1; } } if (s[i] == R ) { x++; if (x > y) { if (dp == 1) sum++; dp = 2; } } } cout << sum << endl; }
|
/* qmem_decoder.v */
module qmem_decoder #(
parameter QAW = 32, // address width
parameter QDW = 32, // data width
parameter QSW = QDW/8, // byte select width
parameter SN = 2 // number of slaves
)(
// system
input wire clk,
input wire rst,
// slave port for requests from masters
input wire qm_cs,
input wire qm_we,
input wire [QAW-1:0] qm_adr,
input wire [QSW-1:0] qm_sel,
input wire [QDW-1:0] qm_dat_w,
output wire [QDW-1:0] qm_dat_r,
output wire qm_ack,
output wire qm_err,
// master port for requests to a slave
output wire [SN -1:0] qs_cs,
output wire [SN -1:0] qs_we,
output wire [SN*QAW-1:0] qs_adr,
output wire [SN*QSW-1:0] qs_sel,
output wire [SN*QDW-1:0] qs_dat_w,
input wire [SN*QDW-1:0] qs_dat_r,
input wire [SN -1:0] qs_ack,
input wire [SN -1:0] qs_err,
// one hot slave select signal
input wire [SN -1:0] ss
);
// this code is written for up to 8 slaves
wire [7:0] ss_a;
reg [7:0] ss_r;
generate if (SN == 1) assign ss_a = 0; endgenerate
generate if (SN == 2) assign ss_a = ss[1]?1:0; endgenerate
generate if (SN == 3) assign ss_a = ss[2]?2:ss[1]?1:0; endgenerate
generate if (SN == 4) assign ss_a = ss[3]?3:ss[2]?2:ss[1]?1:0; endgenerate
generate if (SN == 5) assign ss_a = ss[4]?4:ss[3]?3:ss[2]?2:ss[1]?1:0; endgenerate
generate if (SN == 6) assign ss_a = ss[5]?5:ss[4]?4:ss[3]?3:ss[2]?2:ss[1]?1:0; endgenerate
generate if (SN == 7) assign ss_a = ss[6]?6:ss[5]?5:ss[4]?4:ss[3]?3:ss[2]?2:ss[1]?1:0; endgenerate
generate if (SN == 8) assign ss_a = ss[7]?7:ss[6]?6:ss[5]?5:ss[4]?4:ss[3]?3:ss[2]?2:ss[1]?1:0; endgenerate
always @ (posedge clk)
if (qm_cs & (qm_ack | qm_err) & ~qm_we) ss_r <= #1 ss_a;
genvar i;
// master port for requests to a slave
generate for (i=0; i<SN; i=i+1) begin : loop_select
assign qs_cs [ i ] = qm_cs & ss [i];
assign qs_we [ i ] = qm_we;
assign qs_adr [QAW*(i+1)-1:QAW*(i+1)-QAW] = qm_adr;
assign qs_sel [QSW*(i+1)-1:QSW*(i+1)-QSW] = qm_sel;
assign qs_dat_w [QDW*(i+1)-1:QDW*(i+1)-QDW] = qm_dat_w;
end endgenerate
// slave port for requests from masters
assign qm_dat_r = qs_dat_r >> (QDW*ss_r);
assign qm_ack = qs_ack >> ss_a ;
assign qm_err = qs_err >> ss_a ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, i; cin >> n; string s; int ans = 0; cin >> s; for (i = 1; i < n; i++) { if (s[i] != s[0]) break; } if (i != n) { int c = 1; for (int j = i + 1; j != i; j = (j + 1) % n) { if ((j != 0 && s[j] == s[j - 1]) || (j == 0 && s[0] == s[n - 1])) { c++; } else { while (c >= 3) { ans++; c -= 3; } c = 1; } } while (c >= 3) { ans++; c -= 3; } } else { int c = n - 1; ans = 1; while (c >= 3) { ans++; c -= 3; } } cout << ans << endl; } }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/***************************
* This module issues the workitems within a workgroup while supporting multiple
* workgroups in flight
****************************/
//
// It is designed to be embedded inside the function implementation,
// a function's implementation, i.e. along side the basic blocks.
//
// It has three states:
//
// NEW: Prepared to issue items from the next work group
//
// ISSUE: Issuing items from a workgroup.
// In this state, a new item will be issued in the same cycle
// that both the following conditions hold:
// The downstream block can accept it, and
// The upstream function wrapper is ready to issue it.
//
// WAIT: Waiting for items to retire, to free up the next hw work group.
//
// All the work item intrinsic values are ready directly
// from the wrapper's register set.
// We have to take care to ensure that the linear_local_id_out and hw_group_sel
// are consistent with the same-cycle values for work item values
// provided by the wrapper.
//
// TODO
// Out-of-order work-group exit may result in a sub-optimal number of
// work-groups being issued
//
module acl_embedded_workgroup_issuer_complex (clock, resetn, valid_in, stall_out, valid_entry, stall_entry,
valid_exit, stall_exit, workgroup_size, linear_local_id_out, hw_wg_id_out, done_hw_wg_id_in,
global_id_in, local_id_in, group_id_in, global_id_out, local_id_out, group_id_out);
// Define module parameters
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2; // >0
parameter unsigned MAX_WORKGROUP_SIZE = ; // >0
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1);
localparam unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MAX_WORKGROUP_SIZE) : 1);
localparam unsigned WG_ID_BITS = (MAX_SIMULTANEOUS_WORKGROUPS > 1 ? $clog2(MAX_SIMULTANEOUS_WORKGROUPS) : 1);
input clock;
input resetn;
// Handshake for item entry into function.
input valid_in;
output stall_out;
// Handshake with entry basic block
output valid_entry;
input stall_entry;
// Observe threads exiting the function .
// This is asserted when items are ready to be retired from the workgroup.
input valid_exit;
// This is asserted when downstream is not ready to retire an item from
// the workgroup.
input stall_exit;
// Need workgroup_size to know when one workgroup ends
// and another begins.
input [WG_SIZE_BITS-1:0] workgroup_size;
// Linearized local id. In range of [0, workgroup_size - 1].
output [LLID_BITS - 1:0] linear_local_id_out;
// Hardware work-group id. In range of [0, MAX_SIMULTANEOUS_WORKGROUPS - 1].
output [WG_ID_BITS - 1:0] hw_wg_id_out;
// The hardware work-group id of the work-group that is exiting.
input [WG_ID_BITS - 1:0] done_hw_wg_id_in;
// Pass through global_id, local_id and group_id.
input [31:0] global_id_in[2:0];
input [31:0] local_id_in[2:0];
input [31:0] group_id_in[2:0];
output [31:0] global_id_out[2:0];
output [31:0] local_id_out[2:0];
output [31:0] group_id_out[2:0];
// States for state machine
// NEW - Prepare to issue new workgroup
// ISSUE - issue workitems in a workgroup (set valid high)
// WAIT - Check if ready to accept new workgroup or if all done
localparam [2:0] wg_STATE_NEW=3'd0;
localparam [2:0] wg_STATE_ISSUE=3'd1;
localparam [2:0] wg_STATE_WAIT=3'd2;
reg [2:0] present_state;
reg [2:0] next_state;
////// Issuing info
// Which hw group id should we assign to incoming workgroups?
reg [WG_ID_BITS-1:0] hw_group_sel;
reg [LLID_BITS-1:0] num_issued_in_wg; // 0..workgroup_size-1
////// Retiring info
// Will an item be retired from the accelerator?
wire retire = valid_exit & ~stall_exit;
// When a thread exits the accelerator, determine which hw group id
// it was associated with. Threads can exit in any order.
reg [WG_SIZE_BITS-1:0] num_items_not_done[MAX_SIMULTANEOUS_WORKGROUPS-1:0];
generate
if (MAX_SIMULTANEOUS_WORKGROUPS > 1)
begin
// Update when transitioning out of issue state. The scheduling is
// simple, rotate through available hw groups and stall if the next one isn't
// free (no bypassing).
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
hw_group_sel <= '0;
else if (present_state==wg_STATE_ISSUE && next_state==wg_STATE_WAIT)
begin
// Wrap-around if at the max. simultaneous workgroups value.
if (hw_group_sel == MAX_SIMULTANEOUS_WORKGROUPS - 1)
hw_group_sel <= '0;
else
hw_group_sel <= hw_group_sel + 'd1;
end
end
end
else
begin
always @(posedge clock) hw_group_sel=1'b0;
end
endgenerate
// Should we begin a new group? We will not issue a new item at least until the next cycle.
wire begin_group = (present_state == wg_STATE_NEW) & valid_in & (~stall_entry);
// Will we issue a new work item?
wire issue = (present_state == wg_STATE_ISSUE) & valid_in & (~stall_entry);
// Can consume items only when issuing state, and only when the downstream block
// is ready to consume.
assign stall_out = ~(present_state == wg_STATE_ISSUE) | stall_entry;
// Ready to send a new item along any time we're in issue state and we have
// a valid in.
assign valid_entry = (present_state == wg_STATE_ISSUE) & valid_in;
wire last_item_in_workgroup = (num_issued_in_wg == (workgroup_size - 'd1));
// Have we just finished sending an entire workgroup?
wire workgroup_sent = (present_state==wg_STATE_ISSUE) && issue && last_item_in_workgroup;
// Local id and work-group id outputs.
assign linear_local_id_out = num_issued_in_wg;
assign hw_wg_id_out = hw_group_sel;
// The ids (global, local and group) are simply passed through.
assign global_id_out = global_id_in;
assign local_id_out = local_id_in;
assign group_id_out = group_id_in;
// Update num_issued_in_wg.
// Its value is kept stable until the next hw workgroup starts
always @(posedge clock or negedge resetn) begin
if ( ~resetn )
num_issued_in_wg <= '0;
else if ( begin_group )
num_issued_in_wg <= '0;
else if ( issue )
num_issued_in_wg <= num_issued_in_wg + 1'b1;
else
num_issued_in_wg <= num_issued_in_wg;
end
// Check if next hw group is free to accept a new workgroup. WARNING: This
// signal is only valid in the WAIT state!
wire next_hw_group_free = ~(|num_items_not_done[hw_group_sel]);
// State machine
// NEW - Prepare to issue new workgroup
// ISSUE - issue workitems in a workgroup (set valid high)
// WAIT - Check if ready to accept new workgroup or if all done
always@*
begin
next_state = wg_STATE_NEW;
case (present_state)
wg_STATE_NEW:
next_state = (begin_group) ? wg_STATE_ISSUE : wg_STATE_NEW;
wg_STATE_ISSUE:
next_state = (workgroup_sent) ? wg_STATE_WAIT : wg_STATE_ISSUE;
wg_STATE_WAIT:
next_state = (next_hw_group_free) ? wg_STATE_NEW : wg_STATE_WAIT;
endcase
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
present_state <= wg_STATE_NEW;
else
present_state <= next_state;
end
// Compute num_items_not_done for each HW group
generate
genvar i;
for (i=0; i<MAX_SIMULTANEOUS_WORKGROUPS; i=i+1)
begin : numdone_gen
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
num_items_not_done[i] <= '0;
else
case (present_state)
wg_STATE_NEW:
if ( retire && (done_hw_wg_id_in==i) ) // retiring from hw group i
num_items_not_done[i] <= (num_items_not_done[i] - 2'b01);
wg_STATE_ISSUE:
// The trick is we might be issuing items into the same hw group that might be retiring an item
if ( ( issue && (hw_group_sel==i) ) // issuing into hw group i
&& ~( retire && (done_hw_wg_id_in==i) ) // not retiring from hw group i
)
num_items_not_done[i] <= (num_items_not_done[i] + 2'b01);
else if ( ~( issue && (hw_group_sel==i) ) // not issuing into hw group i
&& ( retire && (done_hw_wg_id_in==i) ) // retiring from hw group i
)
num_items_not_done[i] <= (num_items_not_done[i] - 2'b01);
wg_STATE_WAIT: // same as NEW
if ( retire && done_hw_wg_id_in==i ) // retiring from hw group i
num_items_not_done[i] <= (num_items_not_done[i] - 2'b01);
endcase
end
end
endgenerate
endmodule
// vim:set filetype=verilog:
|
#include <bits/stdc++.h> using namespace std; inline int setBit(int N, int pos) { return N = N | (1 << pos); } inline int resetBit(int N, int pos) { return N = N & ~(1 << pos); } inline bool checkBit(int N, int pos) { return (bool)(N & (1 << pos)); } int main() { long long n, k, x, sum = 0; scanf( %lld %lld , &n, &k); while (n--) { scanf( %lld , &x); sum += (x / k) + (bool)(x % k); } printf( %lld n , sum / 2 + (bool)(sum % 2)); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct rec { int l, r; }; rec f[2222][2223]; bool can[2222][2223]; int n, m, k, x, y, xx, yy; void del(int x, int y) { can[x][y] = false; for (int i = 1; i <= m; i++) { f[x][i].l = f[x][i - 1].l; if (can[x][i - 1]) f[x][i].l = i - 1; } for (int i = m; i >= 1; i--) { f[x][i].r = f[x][i + 1].r; if (can[x][i + 1]) f[x][i].r = i + 1; } return; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { f[i][j].l = j - 1; f[i][j].r = j + 1; can[i][j] = true; } for (int i = 1; i <= n; i++) { f[i][m + 1].r = m + m; } while (k--) { int ans = n + m + n + m; scanf( %d%d , &x, &y); for (int i = 1; i <= n; i++) { int u = abs(i - x); if (can[i][y]) { if (ans > u) { ans = u; xx = i; yy = y; } } else { if (f[i][y].l > 0 && ans > u + abs(f[i][y].l - y)) { ans = u + abs(f[i][y].l - y); xx = i; yy = f[i][y].l; } if (f[i][y].r < m + 1 && ans > u + abs(f[i][y].r - y)) { ans = u + abs(f[i][y].r - y); xx = i; yy = f[i][y].r; } } if (ans == 0) break; } printf( %d %d n , xx, yy); del(xx, yy); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ba (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 1005; string a[MaxN], start[MaxN], finish[MaxN], st[MaxN], Fans[MaxN]; int n, m, ind, Find; int b[MaxN]; void check() { int flag = 0, flag1 = 0, i, j; ind = 0; for (i = 1; i <= n; i++) { if (b[i] == 1) { ind++; st[ind] = a[i]; } } for (i = 1; i <= m; i++) { flag = 0; for (j = 1; j <= ind; j++) { if ((st[j] == start[i]) || (st[j] == finish[i])) { flag++; } } if (flag >= 2) { flag1 = 1; break; } } if ((flag1 == 0) && (ind > Find)) { for (i = 1; i <= ind; i++) { Fans[i] = st[i]; } Find = ind; } } void rec(int i) { if (i > n) { check(); return; } b[i] = 0; rec(i + 1); b[i] = 1; rec(i + 1); } int main() { int i, j; Find = 0; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> a[i]; } for (i = 1; i <= m; i++) { cin >> start[i] >> finish[i]; } rec(1); sort(Fans + 1, Fans + Find + 1); cout << Find << endl; for (i = 1; i <= Find; i++) { cout << Fans[i] << endl; } }
|
module soc_system (
clk_clk,
hps_0_f2h_sdram0_data_address,
hps_0_f2h_sdram0_data_burstcount,
hps_0_f2h_sdram0_data_waitrequest,
hps_0_f2h_sdram0_data_readdata,
hps_0_f2h_sdram0_data_readdatavalid,
hps_0_f2h_sdram0_data_read,
hps_0_f2h_sdram1_data_address,
hps_0_f2h_sdram1_data_burstcount,
hps_0_f2h_sdram1_data_waitrequest,
hps_0_f2h_sdram1_data_readdata,
hps_0_f2h_sdram1_data_readdatavalid,
hps_0_f2h_sdram1_data_read,
hps_0_f2h_sdram2_data_address,
hps_0_f2h_sdram2_data_burstcount,
hps_0_f2h_sdram2_data_waitrequest,
hps_0_f2h_sdram2_data_readdata,
hps_0_f2h_sdram2_data_readdatavalid,
hps_0_f2h_sdram2_data_read,
hps_0_f2h_sdram3_data_address,
hps_0_f2h_sdram3_data_burstcount,
hps_0_f2h_sdram3_data_waitrequest,
hps_0_f2h_sdram3_data_writedata,
hps_0_f2h_sdram3_data_byteenable,
hps_0_f2h_sdram3_data_write,
hps_0_f2h_sdram4_data_address,
hps_0_f2h_sdram4_data_burstcount,
hps_0_f2h_sdram4_data_waitrequest,
hps_0_f2h_sdram4_data_writedata,
hps_0_f2h_sdram4_data_byteenable,
hps_0_f2h_sdram4_data_write,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
hps_0_i2c1_scl_in_clk,
hps_0_i2c1_clk_clk,
hps_0_i2c1_out_data,
hps_0_i2c1_sda);
input clk_clk;
input [28:0] hps_0_f2h_sdram0_data_address;
input [7:0] hps_0_f2h_sdram0_data_burstcount;
output hps_0_f2h_sdram0_data_waitrequest;
output [63:0] hps_0_f2h_sdram0_data_readdata;
output hps_0_f2h_sdram0_data_readdatavalid;
input hps_0_f2h_sdram0_data_read;
input [28:0] hps_0_f2h_sdram1_data_address;
input [7:0] hps_0_f2h_sdram1_data_burstcount;
output hps_0_f2h_sdram1_data_waitrequest;
output [63:0] hps_0_f2h_sdram1_data_readdata;
output hps_0_f2h_sdram1_data_readdatavalid;
input hps_0_f2h_sdram1_data_read;
input [28:0] hps_0_f2h_sdram2_data_address;
input [7:0] hps_0_f2h_sdram2_data_burstcount;
output hps_0_f2h_sdram2_data_waitrequest;
output [63:0] hps_0_f2h_sdram2_data_readdata;
output hps_0_f2h_sdram2_data_readdatavalid;
input hps_0_f2h_sdram2_data_read;
input [28:0] hps_0_f2h_sdram3_data_address;
input [7:0] hps_0_f2h_sdram3_data_burstcount;
output hps_0_f2h_sdram3_data_waitrequest;
input [63:0] hps_0_f2h_sdram3_data_writedata;
input [7:0] hps_0_f2h_sdram3_data_byteenable;
input hps_0_f2h_sdram3_data_write;
input [28:0] hps_0_f2h_sdram4_data_address;
input [7:0] hps_0_f2h_sdram4_data_burstcount;
output hps_0_f2h_sdram4_data_waitrequest;
input [63:0] hps_0_f2h_sdram4_data_writedata;
input [7:0] hps_0_f2h_sdram4_data_byteenable;
input hps_0_f2h_sdram4_data_write;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
input hps_0_i2c1_scl_in_clk;
output hps_0_i2c1_clk_clk;
output hps_0_i2c1_out_data;
input hps_0_i2c1_sda;
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for delayed assignment statements.
module vhdl_delay_assign_test;
logic a, b, c;
int passed = 0;
vhdl_delay_assign dut(a, b, c);
always @(b)
begin
if($time == 10) begin
passed = passed + 1;
end else begin
$display("FAILED 1");
$finish();
end
end
always @(c)
begin
if($time == 10) begin
passed = passed + 1;
end else begin
$display("FAILED 2");
$finish();
end
end
initial begin
a = 1;
#11;
if(passed !== 2) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, k; int a[N]; void solve(int l, int r) { if (k <= 0) { return; } if (l == r - 1) { return; } int mid = (l + r) / 2; swap(a[mid - 1], a[mid]); --k; --k; solve(l, mid); solve(mid, r); } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) a[i] = i + 1; if (k % 2 == 0) { puts( -1 ); return 0; } if (k > ((n)*2 - 1)) { puts( -1 ); exit(0); } --k; solve(0, n); for (int i = 0; i < n; i++) printf( %d , a[i]); }
|
`define BigEndianCPU 1
module dm_4k (addr, din, byteExt, wEn, clk, dout);
input [11:0] addr;
input [31:0] din;
input [1:0] byteExt;
input [1:0] wEn;
input clk;
output reg [31:0] dout;
reg [31:0] dm [1023:0];// 32-bit*1024;
wire [1:0] byteSel;
wire [9:0] gpAddr;
reg [7:0] byteIn;
reg [31:0] tmpReg;
assign byteSel = addr[1:0] ^ 2'b11;// Big endian.
assign gpAddr = addr[11:2];
always @ ( * ) begin
if (byteExt == 2'b01 || byteExt == 2'b00) begin// Load byte.
case (byteSel)
2'b00: byteIn <= dm[gpAddr][7:0];
2'b01: byteIn <= dm[gpAddr][15:8];
2'b10: byteIn <= dm[gpAddr][23:16];
2'b11: byteIn <= dm[gpAddr][31:24];
endcase
case (byteExt)// Embedded extender.
2'b00: dout <= {{24{1'b0}}, byteIn};// Logical Cal;
2'b01: dout <= {{24{byteIn[7]}}, byteIn};// Arithmetic Cal;
endcase
end else begin
dout = dm[gpAddr][31:0];// Load word.
end
end
always @ ( posedge clk ) begin// Write;
if (wEn == 2'b01) begin
if (byteExt == 2'b10) begin// Store byte.
tmpReg = dm[gpAddr][31:0];
case (byteSel)
2'b00: tmpReg[7:0] = din[7:0];
2'b01: tmpReg[15:8] = din[7:0];
2'b10: tmpReg[23:16] = din[7:0];
2'b11: tmpReg[31:24] = din[7:0];
endcase
dm[gpAddr][31:0] = tmpReg[31:0];
end else begin// Store word.
dm[gpAddr][31:0] = din[31:0];
end
end
end
endmodule // 4K Data Memeory;
|
`include"axi2ocp.v"
/*
* AXI to OCP translation block test bench
* Author: Michael Walton
*
* This module validates the AXI to OCP translation block
*/
module axi2ocp_tb();
// Declarations/*{{{*/
// axi2ocp hookups
reg clk;
reg reset;
// AXI FIFO/*{{{*/
reg m_aclk;
wire s_aclk;
reg m_axis_tvalid;
wire m_axis_tready;
reg [`fifo_wdth - 1:0] m_axis_tdata;
reg [`data_wdth - 1:0] m_axis_tkeep;
reg m_axis_tlast;
wire s_axis_tvalid;
reg s_axis_tready;
wire [`fifo_wdth - 1:0] s_axis_tdata;
wire [`data_wdth - 1:0] s_axis_tkeep;
wire s_axis_tlast;
wire axis_overflow;
wire axis_underflow;
/*}}}*/
// OCP 2.2 Interface/*{{{*/
wire [`addr_wdth - 1:0] address;
wire enable;
wire [2:0] burst_seq;
wire burst_single_req;
wire [9:0] burst_length;
wire data_valid;
wire read_request;
wire ocp_reset;
wire sys_clk;
wire [`data_wdth - 1:0] write_data;
wire write_request;
wire writeresp_enable;
/*}}}*/
/*}}}*/
// AXI FIFO containing simulation data/*{{{*/
FIFO axi_rx_fifo (
.m_aclk(m_aclk),
.s_aclk(s_aclk),
.s_aresetn(reset),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.axis_overflow(axis_overflow),
.axis_underflow(axis_underflow)
);/*}}}*/
axi2ocp U0(/*{{{*/
.clk(clk),
.reset(reset),
// AXI FIFO/*{{{*/
.m_aclk(m_aclk),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.axis_underflow(axis_underflow),
/*}}}*/
// OCP 2.2 Interface/*{{{*/
.address(address),
.enable(enable),
.burst_seq(burst_seq),
.burst_single_req(burst_single_req),
.burst_length(burst_length),
.data_valid(data_valid),
.read_request(read_request),
.ocp_reset(ocp_reset),
.sys_clk(sys_clk),
.write_data(write_data),
.write_request(write_request),
.writeresp_enable(writeresp_enable)
/*}}}*/
);/*}}}*/
// Begin test stimuli/*{{{*/
initial begin
clk <= 0;
reset <= 1;
// FIFO initialization
m_aclk <= 1'b0;
m_axis_tvalid <= 1'b0;
m_axis_tdata <= `fifo_wdth'bx;
m_axis_tkeep <= `data_wdth'bx;
m_axis_tlast <= 1'b0;
forever begin
#10 clk <= ~clk;
end
end
initial begin
// Simulate an idle queue/*{{{*/
#20 reset <= 0;
// FIFO initialization
m_aclk <= 1'b0;
m_axis_tvalid <= 1'b0;
m_axis_tdata <= `fifo_wdth'bx;
m_axis_tkeep <= `data_wdth'bx;
m_axis_tlast <= 1'b0;/*}}}*/
// Simulate a read from a 64-bit address for 10 bytes worth of data/*{{{*/
// TLP consists of just a header, which will be in 4 parts we will
// need to pull from the FIFO.
// Fmt: 001 - 4 DW header, no data
// Type: 0 0000 - Memory read request
// Header 1: 00X0 0000 0000 0000 0000 0000 0000 0000
// Header 2 [ requester id ] [ tag ] [lbe][be]
// Header 3: eeee eeee eeee eeee eeee eeee eeee eeee Test addr1
// Header 4: ffff ffff ffff ffff ffff ffff ffff ffff Test addr2
// Header 1 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h20000000;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 2 of 4
// Fill in with 0xXXXXXXFF since request is greater than 1 DW
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'b0; // FILL IN WITH READ R INF
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 3 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'heeeeeeee;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 4 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hffffffff;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b1;
// Wait for bridge to finish translating the read request and for
// it to asseart m_axis_tready on the FIFO
#200/*}}}*/ // 20 unit clock period * 10 bytes
// Simulate a write to a 64-bit address for 13 bytes/*{{{*/
// TLP consists of just a header, which will be in 4 parts we will
// need to pull from the FIFO.
// Fmt: 001 - 4 DW header, no data
// Type: 0 0000 - Memory read request
// Header 1: 01X0 0000 0000 0000 0000 0000 0000 1101
// Header 2 [ requester id ] [ tag ] [lbe][be]
// Header 3: dddd dddd dddd dddd dddd dddd dddd dddd Test addr1
// Header 4: cccc cccc cccc cccc cccc cccc cccc cccc Test addr2
// Header 1 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h6000000d;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 2 of 4
#100 m_axis_tvalid <= 1'b1;
// Fill in with 0xXXXXXXFF since request is greater than 1 DW
m_axis_tdata <= `fifo_wdth'b0; // FILL IN WITH WRITE R INF
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 3 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hdddddddd;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Header 4 of 4
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hcccccccc;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 1 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hffffffff;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 2 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'heeeeeeee;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 3 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hdddddddd;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 4 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hcccccccc;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 5 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'hbbbbbbbb;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 6 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'haaaaaaaa;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 7 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h99999999;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 8 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h88888888;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 9 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h77777777;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 10 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h66666666;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 11 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h55555555;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 12 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h44444444;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b0;
// Data 13 of 13
#100 m_axis_tvalid <= 1'b1;
m_axis_tdata <= `fifo_wdth'h33333333;
m_axis_tkeep <= {`data_wdth{'b1}};
m_axis_tlast <= 1'b1;
#100/*}}}*/
// Finish test bench/*{{{*/
#100 m_aclk <= 1'b0;
m_axis_tvalid <= 1'b0;
m_axis_tdata <= `fifo_wdth'bx;
m_axis_tkeep <= `data_wdth'bx;
m_axis_tlast <= 1'b0;/*}}}*/
end/*}}}*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.14159265358979323; const double EPS = 1e-12; const int N = 1e6 + 5; const int MOD = 1e9 + 7; long long int n, m; long long int dp[2005][2005]; long long int ad(long long int a, long long int b) { return ((a % MOD + b % MOD) % MOD); } long long int go(long long int idx, long long int ct) { long long int res = 0; if (ct == m) { return 1; } if (dp[idx][ct] != -1) return dp[idx][ct]; for (int i = idx; i <= n; i += idx) { res = ad(res, go(i, ct + 1)); } dp[idx][ct] = res; return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); memset(dp, -1, sizeof(dp)); cin >> n >> m; cout << go(1, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; const int N = 1e5 + 5; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } vector<vector<int> > ans; void solve(int n) { int i = 1, j = 2, k = 3; while (k <= n) { ans.push_back({i, j, k}); i += 2; j += 2; k += 2; } i = 1, j = 2, k -= 2; while (j < n - 1) { ans.push_back({i, j, k}); i += 2, j += 2; } } void solve() { int n; cin >> n; long long a[n]; long long x = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; x ^= a[i]; } if (n % 2 == 0) { if (x) { cout << NO n ; return; } else { solve(n - 1); } } else { solve(n); } cout << YES n ; cout << ans.size() << n ; for (auto v : ans) { printf( %d %d %d n , v[0], v[1], v[2]); } } signed main() { int t = 1; for (long long i = 1; i < t + 1; i++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void setIO(const string &name = ) { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); if (name.length()) { freopen((name + .in ).c_str(), r , stdin); freopen((name + .out ).c_str(), w , stdout); } } template <typename T> void read(vector<T> &a) { for (auto &x : a) cin >> x; } template <typename T> void read(vector<T> &a, int n) { a.resize(n); for (auto &x : a) cin >> x; } template <class T, class U> ostream &operator<<(ostream &out, const pair<T, U> &v) { out << ( ; out << v.first << , << v.second; return out << ) ; } template <class T> ostream &operator<<(ostream &out, const vector<T> &v) { out << [ ; for (auto(i) = 0; (i) < ((int)(v).size()); (i)++) { if (i) out << , ; out << v[i]; } return out << ] ; } template <typename T> void print(vector<T> &a) { for (const auto &x : a) cout << x << ; cout << n ; } void MOD(int &x, int m = 1000000007) { x %= m; if (x < 0) x += m; } template <typename T> void dbg(const char *name, T &&arg1) { cout << name << : << arg1 << n ; } template <typename T, typename... U> void dbg(const char *names, T &&arg1, U &&...args) { const char *comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; dbg(comma + 1, args...); } template <class T> void read(T &x) { cin >> x; } template <class T, class... U> void read(T &t, U &...u) { read(t); read(u...); } template <class T> void tell(T &x) { cout << x; } template <class T, class... U> void tell(T &t, U &...u) { tell(t); if (sizeof...(u)) tell( ); tell(u...); } int gcd(int a, int b) { return !a ? b : gcd(b % a, a); } int n, m; vector<vector<int> > board; int dp[101][int(5e4) + 10 + int(5e4) + 10]; int32_t main() { setIO(); read(m, n); board.resize(n); for (auto &(c) : (board)) { read(c, m); } int ans = int(2e9) + 15; vector<int> ans_ar; for (int diff = -int(5e4) + 10 + 1; diff < int(5e4) + 10; diff++) { if (diff >= 0) { dp[n][diff + int(5e4) + 10] = 0; } else { dp[n][diff + int(5e4) + 10] = int(2e9) + 15; } } for (auto(i) = 0; (i) < (m - 1); (i)++) { for (int idx = n - 1; idx >= 0; idx--) { for (int diff = -int(5e4) + 10 + 1; diff < int(5e4) + 10; diff++) { int &res = dp[idx][diff + int(5e4) + 10]; res = int(2e9) + 15; res = min(res, dp[idx + 1][diff + int(5e4) + 10] + 1); if (diff + (board[idx][i] - board[idx][m - 1]) >= int(5e4) + 10) { res = 0; } else if (diff + (board[idx][i] - board[idx][m - 1]) <= -int(5e4) + 10) { res = int(2e9) + 15; } else { res = min(res, dp[idx + 1][diff + (board[idx][i] - board[idx][m - 1]) + int(5e4) + 10]); } } } if (ans > dp[0][int(5e4) + 10]) { ans = dp[0][int(5e4) + 10]; int cur_diff = 0; ans_ar.clear(); for (int idx = 0; idx < n; idx++) { const int &res = dp[idx][cur_diff + int(5e4) + 10]; if (res == dp[idx + 1][cur_diff + int(5e4) + 10] + 1) { ans_ar.emplace_back(idx + 1); continue; } else { if (cur_diff + (board[idx][i] - board[idx][m - 1]) >= int(5e4) + 10) { break; } else if (cur_diff + (board[idx][i] - board[idx][m - 1]) <= -int(5e4) + 10) { break; } else { cur_diff += (board[idx][i] - board[idx][m - 1]); } } } } } cout << ans << n ; print(ans_ar); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 101; int a[MAX_N]; int n; vector<vector<int>> ans; pair<int, int> pop(multiset<pair<int, int>, std::greater<pair<int, int>>> &s) { pair<int, int> x = *s.begin(); s.erase(s.begin()); return x; } bool check(int d) { ans.clear(); multiset<pair<int, int>, std::greater<pair<int, int>>> s; int sum = 0; for (int i = 0; i < n; i++) { if (a[i] < d) return false; s.insert({a[i] - d, i}); sum += a[i] - d; } if (sum % 2 == 1) { if (n < 3) return false; pair<int, int> x = pop(s), y = pop(s), z = pop(s); if (z.first == 0) return false; ans.push_back({x.second, y.second, z.second}); s.insert({x.first - 1, x.second}); s.insert({y.first - 1, y.second}); s.insert({z.first - 1, z.second}); sum -= 3; } while (sum > 0) { if (n < 2) return false; pair<int, int> x = pop(s), y = pop(s); if (y.first == 0) return false; ans.push_back({x.second, y.second}); s.insert({x.first - 1, x.second}); s.insert({y.first - 1, y.second}); sum -= 2; } return true; } void dummy() { ans.clear(); multiset<pair<int, int>, std::greater<pair<int, int>>> s; for (int i = 0; i < n; i++) { s.insert({a[i], i}); } while ((*s.begin()).first > 0) { pair<int, int> x = pop(s), y = pop(s); s.insert({(x.first > 1 ? x.first - 1 : 0), x.second}); s.insert({(y.first > 1 ? y.first - 1 : 0), y.second}); ans.push_back({x.second, y.second}); } } int main() { cin >> n; int r = MAX_N; for (int i = 0; i < n; i++) { cin >> a[i]; r = min(r, a[i]); } r++; int l = 0; while (l < r) { int m = l + (r - l) / 2; if (check(m)) { l = m + 1; } else { r = m; } } if (l == 0 || !check(l - 1)) { l = 1; dummy(); } cout << l - 1 << endl << ans.size() << endl; for (auto p : ans) { for (int i = 0; i < n; i++) { bool ok = 0; for (int x : p) { ok |= x == i; } cout << (ok ? 1 : 0 ); } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, x = 0, k = 0; cin >> t; while (t--) { int m, n, x, y = 0; cin >> m; cin >> n; x = m * n; int a[x]; for (int i = 0; i < x; i++) { cin >> a[i]; if (a[i] < 0) { a[i] = 0 - a[i]; k++; } y = y + a[i]; } sort(a, a + x); if (k % 2 == 0) cout << y << endl; else cout << y - 2 * a[0] << endl; k = 0; } return 0; }
|
// -- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
//-----------------------------------------------------------------------------
//
// File name: cdn_axi_bfm_1.v
//
// Description: Verilog wrapper for Cadence's "cdn_axi_bfm" module.
//
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
//-----------------------------------------------------------------------------
// The AXI4 Streaming Slave BFM Top Level Wrapper
//-----------------------------------------------------------------------------
module cdn_axi_bfm_1 (s_axis_aclk, s_axis_aresetn,
s_axis_tvalid, s_axis_tready, s_axis_tdata,
s_axis_tkeep,s_axis_tid,s_axis_tdest,s_axis_tuser, s_axis_tlast);
//-----------------------------------------------------------------------------
parameter C_S_AXIS_NAME = "cdn_axi_bfm_1";
parameter C_S_AXIS_TDATA_WIDTH = 24;
parameter C_S_AXIS_TID_WIDTH = 8;
parameter C_S_AXIS_TDEST_WIDTH = 4;
parameter C_S_AXIS_TUSER_WIDTH = 8;
parameter C_S_AXIS_MAX_PACKET_SIZE = 10;
parameter C_S_AXIS_MAX_OUTSTANDING_TRANSACTIONS = 8;
parameter C_INTERCONNECT_S_AXIS_WRITE_ACCEPTANCE = 8;
parameter C_S_AXIS_STROBE_NOT_USED = 1;
parameter C_S_AXIS_KEEP_NOT_USED = 0;
//------------------------------------------------------------------------
// Signal Definitions
//------------------------------------------------------------------------
// Global Clock Input. All signals are sampled on the rising edge.
input wire s_axis_aclk;
// Internal Clock created by delaying the input clock and used for sampling
// and driving input and output signals respectively to avoid race conditions.
//wire bfm_aclk;
// Global Reset Input. Active Low.
input wire s_axis_aresetn;
// Transfer Channel Signals.
input wire s_axis_tvalid; // Master Transfer Valid.
output wire s_axis_tready; // Slave Transfer Ready.
input wire [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata; // Master Transfer Data.
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1:0] s_axis_tkeep; // Master Transfer Keep.
input wire s_axis_tlast; // Master Transfer Last Flag.
input wire [C_S_AXIS_TID_WIDTH-1:0] s_axis_tid; // Master Transfer ID Tag.
input wire [C_S_AXIS_TDEST_WIDTH-1:0] s_axis_tdest; // Master Transfer Destination.
input wire [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser; // Master Transfer User Defined.
cdn_axi4_streaming_slave_bfm #(.NAME(C_S_AXIS_NAME),
.DATA_BUS_WIDTH(C_S_AXIS_TDATA_WIDTH),
.ID_BUS_WIDTH(C_S_AXIS_TID_WIDTH),
.DEST_BUS_WIDTH(C_S_AXIS_TDEST_WIDTH),
.USER_BUS_WIDTH(C_S_AXIS_TUSER_WIDTH),
.MAX_PACKET_SIZE(C_S_AXIS_MAX_PACKET_SIZE),
.MAX_OUTSTANDING_TRANSACTIONS(C_S_AXIS_MAX_OUTSTANDING_TRANSACTIONS),
.STROBE_NOT_USED(C_S_AXIS_STROBE_NOT_USED),
.KEEP_NOT_USED(C_S_AXIS_KEEP_NOT_USED)
)
cdn_axi4_streaming_slave_bfm_inst(.ACLK(s_axis_aclk),
.ARESETn(s_axis_aresetn),
.TVALID(s_axis_tvalid),
.TREADY(s_axis_tready),
.TDATA(s_axis_tdata),
.TSTRB(s_axis_tkeep),
.TKEEP(s_axis_tkeep),
.TID(s_axis_tid),
.TDEST(s_axis_tdest),
.TUSER(s_axis_tuser),
.TLAST(s_axis_tlast)
);
// These runtime parameters are set based on selection in GUI
// All these parameters can be changed during the runtime in the TB also
initial
begin
cdn_axi4_streaming_slave_bfm_inst.set_response_timeout(500);
cdn_axi4_streaming_slave_bfm_inst.set_disable_reset_value_checks(0);
cdn_axi4_streaming_slave_bfm_inst.set_stop_on_error(1);
cdn_axi4_streaming_slave_bfm_inst.set_channel_level_info(0);
cdn_axi4_streaming_slave_bfm_inst.set_task_call_and_reset_handling(0);
cdn_axi4_streaming_slave_bfm_inst.set_input_signal_delay(0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_TB_V
`define SKY130_FD_SC_HDLL__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_TB_V
|
#include <bits/stdc++.h> using namespace std; int n, d[22]; int f[22], g[22], L[22], memF[22]; void moveG(int n, int a, int b, int c) { if (n == 0) return; moveG(n - L[n], a, c, b); for (int i = 0; i < L[n]; i++) printf( %d %d n , a, c); moveG(n - L[n], b, a, c); } void moveF(int n, int a, int b, int c) { if (n == 0) return; if (memF[n] == 0) { moveG(n - 1, a, c, b); printf( %d %d n , a, c); moveG(n - 1, b, a, c); } else { int k = memF[n]; moveG(n - k, a, b, c); for (int i = 0; i < k; i++) printf( %d %d n , a, b); moveG(n - k, c, b, a); for (int i = 0; i < k; i++) printf( %d %d n , b, c); moveF(n - k, a, b, c); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &d[i]); reverse(d + 1, d + 1 + n); for (int i = 1; i <= n; i++) { L[i] = 1; while (i - L[i] >= 1 && d[i - L[i]] == d[i]) L[i]++; } for (int i = 1; i <= n; i++) { f[i] = 2 * g[i - 1] + 1; memF[i] = 0; for (int k = 1; k <= L[i]; k++) { int tmp = 2 * g[i - k] + f[i - k] + 2 * k; if (tmp < f[i]) f[i] = tmp, memF[i] = k; } g[i] = 2 * g[i - L[i]] + L[i]; } printf( %d n , f[n]); moveF(n, 1, 2, 3); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 1e6 + 10; int main() { int n; cin >> n; map<int, int> mc; for (int i = 1; i <= n; i++) { int x; cin >> x; mc[x] = i; } pair<int, int> ans = {INF, INF}; for (auto &p : mc) { pair<int, int> pp = p; swap(pp.first, pp.second); ans = min(ans, pp); } cout << ans.second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 501; int a[N][N], b[N][N]; void solve() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> b[i][j]; } } for (int i = 0; i < m; i++) { vector<int> comp1, comp2; int x = 0, y = i; while (x < n && y >= 0) { comp1.push_back(a[x][y]); comp2.push_back(b[x][y]); x++, y--; } sort(comp1.begin(), comp1.end()); sort(comp2.begin(), comp2.end()); if (comp1 != comp2) { cout << NO n ; return; } } for (int i = 1; i < n; i++) { vector<int> comp1, comp2; int x = i, y = m - 1; while (x < n && y >= 0) { comp1.push_back(a[x][y]); comp2.push_back(b[x][y]); x++, y--; } sort(comp1.begin(), comp1.end()); sort(comp2.begin(), comp2.end()); if (comp1 != comp2) { cout << NO n ; return; } } cout << YES n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1; for (int tt = 1; tt <= t; tt++) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; template <typename TYPE> inline TYPE sqr(const TYPE& a) { return a * a; } const long double EPS = 1e-9; const long double PI = 2 * acos(0.0); const int N = 300010; int a[N]; int main() { int n; scanf( %d , &n); long long s = 0; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); s += a[i]; } sort(a, a + n); long long ans = s; for (int i = 0; i + 1 < n; ++i) { ans += s; s -= a[i]; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct event { int x, size, val, ent; bool operator<(const event& rhs) const { if (x == rhs.x) return ent < rhs.ent; return x < rhs.x; } }; int main() { ios_base::sync_with_stdio(false), cin.tie(0); int n, x; cin >> n >> x; vector<event> v; for (int i = 0; i < n; i++) { int l, r, cost; cin >> l >> r >> cost; v.push_back({l, r - l + 1, cost, 0}); v.push_back({r, r - l + 1, cost, 1}); } sort(v.begin(), v.end()); int ans = 0x7fffffff; map<int, int> mp; for (const event& eve : v) { if (eve.ent == 0) { auto it = mp.find(x - eve.size); if (it == mp.end()) continue; else ans = min(ans, it->second + eve.val); } else { if (mp[eve.size] == 0) mp[eve.size] = eve.val; else mp[eve.size] = min(eve.val, mp[eve.size]); } } if (ans == 0x7fffffff) ans = -1; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int a[50]; int main() { int f = 2, ct[110]; ct[0] = 0; ct[1] = 0; ct[2] = 1; for (int i = 3; i <= 101; i++) { ct[i] = ct[i - 1] + f; f++; } string s; int n, m; cin >> n; for (int i = 0; i < n; i++) { cin >> s; m = s[0] - 96; a[m]++; } int sum = 0, dis, l; for (int i = 1; i <= 26; i++) { if (a[i] != 0) { dis = a[i] / 2; l = a[i] - dis; sum += (ct[l] + ct[dis]); } } cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> int x[1000], y[1000]; using namespace std; int main() { int n, counter = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; if (x[i] != y[i]) { cout << rated ; return 0; } } for (int i = 0; i < n; i++) { if (x[i] < x[i + 1]) { cout << unrated ; return 0; } } cout << maybe ; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct SuffixArray { char* T; int n; vector<int> RA, tempRA; vector<int> SA, tempSA, c; vector<int> phi, pLCP, LCP; SuffixArray(string& t) { n = t.length(); T = new char[n + n]; for (int i = 0; i < n; T[i] = t[i], i++) ; T[n++] = # , T[n] = 0 ; c.resize(max(300, n)); RA.resize(n), tempRA.resize(n); SA.resize(n), tempSA.resize(n); } void countingSort(int k) { fill(c.begin(), c.end(), 0); for (int i = 0; i < n; i++) c[i + k < n ? RA[i + k] : 0]++; for (int i = 0, sum = 0, lim = max(300, n); i < lim; i++) { int t = c[i]; c[i] = sum, sum += t; } for (int i = 0; i < n; i++) tempSA[c[SA[i] + k < n ? RA[SA[i] + k] : 0]++] = SA[i]; for (int i = 0; i < n; i++) SA[i] = tempSA[i]; } void buildSA() { for (int i = 0; i < n; SA[i] = i, i++) ; for (int i = 0; i < n; RA[i] = T[i], i++) ; for (int k = 1, r; k < n; k <<= 1) { countingSort(k); countingSort(0); tempRA[SA[0]] = r = 0; for (int i = 1; i < n; i++) { tempRA[SA[i]] = (RA[SA[i]] == RA[SA[i - 1]] and RA[SA[i] + k] == RA[SA[i - 1] + k] ? r : ++r); } for (int i = 0; i < n; RA[i] = tempRA[i], i++) ; if (RA[SA[n - 1]] == n - 1) break; } } void computeLCP() { phi.resize(n), pLCP.resize(n), LCP.resize(n); phi[SA[0]] = -1; for (int i = 1; i < n; phi[SA[i]] = SA[i - 1], i++) ; for (int i = 0, L = 0; i < n; i++) { if (phi[i] == -1) { pLCP[i] = 0; continue; } for (; T[i + L] == T[phi[i] + L]; L++) ; pLCP[i] = L; L = max(0, L - 1); } for (int i = 0; i < n; LCP[i] = pLCP[SA[i]], i++) ; } void print() { for (int i = 0; i + 1 < n; i++) { printf( %2d t%2d t%s n , SA[i], LCP[i], T + SA[i]); } } }; struct Node { int sum, lft, rgt; Node() : sum(0), lft(0), rgt(0) {} }; struct PersistantSegmentTree { int avail; vector<int> roots; vector<Node> tree; PersistantSegmentTree(int n) { avail = 0; roots.resize(n + 10, 0); tree.resize(n * 30, Node()); } int update(int last, int l, int r, int p) { int cur = ++avail; tree[cur] = tree[last]; if (l == r) { tree[cur].sum++; return cur; } int mid = l + (r - l) / 2; if (p <= mid) tree[cur].lft = update(tree[last].lft, l, mid, p); else tree[cur].rgt = update(tree[last].rgt, mid + 1, r, p); tree[cur].sum = tree[tree[cur].lft].sum + tree[tree[cur].rgt].sum; return cur; } int query(int cur, int l, int r, int L, int R) { if (l > R or r < L or L > R) return 0; if (l >= L and r <= R) return tree[cur].sum; int mid = l + (r - l) / 2; int pp = query(tree[cur].lft, l, mid, L, R); int qq = query(tree[cur].rgt, mid + 1, r, L, R); return pp + qq; } }; int main() { ios_base ::sync_with_stdio(0); cin.tie(0), cout.tie(0); int n; string s; cin >> n >> s; SuffixArray SA(s); SA.buildSA(); SA.computeLCP(); PersistantSegmentTree PSG(SA.n); vector<int> have; for (int i = n - 1; i >= 0; i--) { if (s[i] == ) ) { have.push_back(i); continue; } if (!have.empty()) { PSG.roots[i] = PSG.update(PSG.roots[have.back() + 1], 0, SA.n, have.back()); have.pop_back(); } } long long res = 0; for (int i = 1; i < SA.n; i++) { if (s[SA.SA[i]] == ) ) continue; int L = SA.SA[i]; int R = L + SA.LCP[i] - 1; int add = PSG.query(PSG.roots[L], 0, SA.n, L, SA.n); int bad = PSG.query(PSG.roots[L], 0, SA.n, L, R); res += (0, max(0, add - bad)); } cout << res << n ; }
|
//move some stuff to minitests/ncy0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_FF clb_FF (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
clb_OUT clb_OUT (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
endmodule
module clb_FF (input clk, input [7:0] din, output [7:0] dout);
wire o6;
//assign dout[0] = o6;
(* LOC="SLICE_X18Y100", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X18Y100", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule
module clb_OUT (input clk, input [7:0] din, output [7:0] dout);
wire o6;
assign dout[0] = o6;
(* LOC="SLICE_X18Y101", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X18Y101", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule
|
/*
* Control Unit for simple 8-bit CPU.
* Copyright (C) 2015, 16 John Tzonevrakis.
* Licensed under the LGPL license. For more details, read the COPYING file.
*
*/
module control (input clk, reset, interrupt,
input [7:0] datamem_data, datamem_address, regfile_out1,
input [7:0] regfile_out2, alu_out, usermem_data_in,
output reg [3:0] alu_opcode,
output reg [7:0] regfile_data,usermem_data_out,
output reg [1:0] regfile_read1, regfile_read2, regfile_writereg,
output reg [7:0] usermem_address, pc_jmpaddr,
output reg rw, regfile_regwrite, pc_jump, pc_freeze);
/* Parameters */
parameter state0 = 3'h0;
parameter state1 = 3'h1;
parameter state2 = 3'h2;
parameter state3 = 3'h3;
parameter state4 = 3'h4;
parameter state5 = 3'h5;
parameter state6 = 3'h6;
/* Flags */
reg [2:0] stage;
reg [7:0] instruction_c;
reg [7:0] instruction;
reg [7:0] sp;
reg is_onecyc, is_alu;
reg eq;
/* Combinational logic goes here */
always @(*) begin
instruction_c <= datamem_data;
is_alu <= (instruction_c[7:4] <= 4'h7);
is_onecyc <= (instruction_c[7:4] <= 4'hd);
alu_opcode <= instruction_c[7:4];
regfile_read1 <= (stage == state0) ? instruction_c[3:2] : instruction[3:2];
regfile_read2 <= (stage == state0) ? instruction_c[1:0] : instruction[1:0];
regfile_writereg <= instruction[1:0];
eq <= (regfile_out1 == regfile_out2);
pc_freeze <= (stage >= state4) ? 1 : 0;
end
always @(posedge clk)
if(interrupt == 1)
begin
pc_jump <= 1;
pc_jmpaddr <= 8'hfd;
stage <= state2;
end
/* Check for reset*/
else if(reset == 1)
begin
sp <= 0;
{instruction, regfile_data, usermem_data_out, usermem_address} <= 8'b0;
{rw, regfile_regwrite} <= 1'b0;
pc_jump <= 1;
pc_jmpaddr <= 8'b0;
stage <= state2;
end
/* Stage 1: Fetch instruction, execute it in case it does not require an operand: */
else if (stage == state0)
begin
rw <= 0;
instruction <= datamem_data;
if (is_alu)
begin
rw <= 0;
regfile_regwrite <= 1;
regfile_data <= alu_out;
stage <= state0;
end
else if (is_alu == 0) begin
case (instruction_c[7:4])
4'h9 /* JMP/NOP */:
begin
pc_jmpaddr <= regfile_out2;
regfile_regwrite <= 0;
pc_jump <= 1;
stage <= state2;
end
4'ha /* CALL */:
begin
rw <= 1;
sp <= sp + 1;
usermem_address <= sp;
usermem_data_out <= datamem_address;
pc_jmpaddr <= regfile_out2;
regfile_regwrite <= 0;
pc_jump <= 1;
stage <= state2;
end
4'hb /* RTS */:
begin
if(instruction_c[3:0] == 4'h0) begin
pc_jump <= 1;
sp <= sp - 1;
usermem_address <= sp;
regfile_regwrite <= 0;
stage <= state4;
end
else if(instruction_c[3:0] == 4'h1) begin
/* STSP (b)*/
regfile_regwrite <= 1;
regfile_data <= sp;
stage <= state0;
end
else if(instruction_c[3:0] == 4'h2) begin
/* POP (c) */
sp <= sp - 1;
usermem_address <= sp;
regfile_regwrite <= 1;
regfile_regwrite <= 0;
stage <= state6;
end
else if(instruction_c[3:0] == 4'h4) begin
/* LDSP (b) */
regfile_regwrite <= 0;
sp <= regfile_out1;
stage <= state0;
end
else if(instruction_c[3:0] == 4'h8) begin
/* PUSH (c) */
rw <= 1;
sp <= sp + 1;
usermem_address <= sp + 1;
usermem_data_out <= regfile_out1;
stage <= state0;
end
end
4'hc /* IEQ */:
begin
regfile_regwrite <= 0;
if(eq)
begin
stage <= state3;
end
else
stage <= state0;
end
4'hd /* INE */:
begin
regfile_regwrite <= 0;
if(eq == 0)
begin
stage <= state3;
end
else
stage <= state0;
end
default: stage <= state1;
endcase
end
end
/* Stage 2: Fetch the operand and execute the relevant instruction: */
else if (stage == state1)
begin
case (instruction[7:4])
4'h8 /* LD */:
begin
rw <= 0;
regfile_regwrite <= 1;
regfile_data <= datamem_data;
stage <= state0;
end
4'he /* ST */:
begin
rw <= 1;
regfile_regwrite <= 0;
usermem_address <= datamem_data;
usermem_data_out <= regfile_out1;
stage <= state0;
end
4'hf /* LDUMEM */:
begin
rw <= 0;
usermem_address <= datamem_data;
regfile_regwrite <= 1;
stage <= state5;
end
endcase
end
else if(stage == state2)
begin
rw <= 0;
instruction <= datamem_data;
pc_jump <= 0;
stage <= state0;
end
else if(stage == state3)
begin
/* Skip an instruction */
if(is_onecyc)
stage <= state0;
else
stage <= state2;
end
else if(stage == state4)
begin
/* Execute RTS */
rw <= 0;
pc_jmpaddr <= usermem_data_in;
stage <= state2;
end
else if(stage == state5)
begin
/* LDUMEM */
instruction <= datamem_data;
regfile_data <= usermem_data_in;
stage <= state0;
end
else if(stage == state6)
begin
/* POP (c) */
instruction <= datamem_data;
regfile_data <= usermem_data_in;
stage <= state0;
end
endmodule //control
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction,wInstruction_Pre;
wire [3:0] wOperation,wOperationPost;
reg signed [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestination_Pre, wDestOpAnterior0, wDestOpAnterior1;
wire [15:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
reg [15:0] wRetrunPlace;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction_Pre[7:0] ),
.iReadAddress1( wInstruction_Pre[15:8] ),
.iWriteAddress( wDestination_Pre ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wSourceData0 = (wSourceAddr0 == wDestination) ? rResult : wSourceData0 ;
assign wSourceData1 = (wSourceAddr1 == wDestination) ? rResult : wSourceData1 ;
assign wInstruction_Pre[7:0] = (wOperation==`RET) ? 8'b7 :wInstruction ; //La direccion de lectura del primer dato
//assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
//assign wIPInitialValue = (wOperationPost==`RET) ? wSourceData0 : wDestination;
assign wIPInitialValue = (Reset) ? 8'b0 : ((wOperation==`RET) ? wSourceData0 : wDestination);
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
assign wDestination_Pre = (rFlagCALL) ? 8'd7 : wDestination ; //wDestination_Pre => iWriteAddress
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFDM // FF Mágico que atrasa un ciclo las operaciones.
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wOperation),
.Q(wOperationPost)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD0
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wIPInitialValue),
.Q(wRetrunPlace)
);
//FF que guarda la dirección de retorno siempre en wRetrunPlace
if(wOperation==`CALL) assign wIP = wSourceData0;
if(wOperation==`RET) assign wIP = wRetrunPlace;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1 ),
.Q( oLed )
);
reg rFlagCALL;
wire [7:0] rRmul1, rRmux1, rRmux4;
wire [15:0] rRgmul1;
arrayMUL mul1(wSourceData0,wSourceData1,rRmul1);
arrayMUL_GEN mg1(wSourceData0,wSourceData1,rRgmul1);
muxMUL mx1(wSourceData0,wSourceData1,rRmux1);
multiplicador4bits mx4 (wSourceData0,wSourceData1,rRmux4);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= wSourceData1 + wSourceData0;
//$display("%dns ADD %h + %h = %h",$time,wSourceData0,wSourceData1,rResult);
end
//-------------------------------------
`CMP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= -wSourceData1;
rFlagCALL <= 1'b0;
$display("%dns CMP %h = %h",$time,wSourceData1,rResult);
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
rFlagCALL <= 1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rFlagCALL <= 1'b0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rFlagCALL <= 1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rFlagCALL <= 1'b0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData0*wSourceData1;
rBranchTaken <= 1'b0;
rFlagCALL <= 1'b0;
end
//-------------------------------------
`IMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= rRmul1;
rFlagCALL <= 1'b0;
// arrayMUL mul1(wSourceData0,wSourceData1,rResult);
rBranchTaken <= 1'b0;
end
//-------------------------------------
`gIMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= rRgmul1;
// arrayMUL_GEN mg1(wSourceData0,wSourceData1,rResult);
rFlagCALL <= 1'b0;
rBranchTaken <= 1'b0;
$display("%dns gIMUL %h * %h = %h",$time,wSourceData0,wSourceData1,rResult);
end
//-------------------------------------
`IMUL2:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= rRmux1;
// muxMUL mx1(wSourceData0,wSourceData1,rRmux1);
end
//-------------------------------------
`IMUX4:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= rRmux4;
// multiplicador4bits mx4 (wSourceData0,wSourceData1,rRmux4);
end
//-------------------------------------
//**** tercer experimento
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= 0;
rFlagCALL <= 1'b1;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rFlagCALL <= 1'b0;
rBranchTaken <= 1'b1;
end
//****
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rFlagCALL <= 1'b0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct MaxFlow { int T; struct node { int to, nxt, cap; } ed[811 * 811 << 1]; int head[811], cur[811], cnt, ans; int h[811]; void addedge(int u, int v, int cap) { ed[cnt].to = v, ed[cnt].cap = cap, ed[cnt].nxt = head[u], head[u] = cnt++; ed[cnt].to = u, ed[cnt].cap = 0, ed[cnt].nxt = head[v], head[v] = cnt++; } bool bfs() { memset(h, -1, sizeof(h)); queue<int> q; h[1] = 0, q.push(1); while (!q.empty()) { int now = q.front(); q.pop(); for (int i = head[now]; ~i; i = ed[i].nxt) { if (ed[i].cap && h[ed[i].to] == -1) { h[ed[i].to] = h[now] + 1; q.push(ed[i].to); } } } return h[T] != -1; } int dfs(int x, int f) { if (x == T || f == 0) return f; int w, used = 0; for (int i = cur[x]; ~i; i = ed[i].nxt) { if (h[ed[i].to] == h[x] + 1) { w = f - used; w = dfs(ed[i].to, min(w, ed[i].cap)); ed[i].cap -= w; ed[i ^ 1].cap += w; if (ed[i].cap) cur[x] = i; used += w; if (used == f) return f; } } if (!used) h[x] = -1; return used; } void dinic() { while (bfs()) { for (int i = 1; i <= T; i++) { cur[i] = head[i]; } ans += dfs(1, 100000005); } } void init(int t) { memset(head, -1, sizeof(head)); ans = cnt = 0; T = t; } } flow; int dis[811][811], st[811]; int main() { int v, e, n, k; scanf( %d%d%d%d , &v, &e, &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &st[i]); for (int i = 1; i <= v; i++) for (int j = i + 1; j <= v; j++) dis[i][j] = dis[j][i] = 100000005; for (int i = 1; i <= e; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); dis[a][b] = min(dis[a][b], c); dis[b][a] = dis[a][b]; } for (int x = 1; x <= v; x++) { for (int i = 1; i <= v; i++) { for (int j = 1; j <= v; j++) { dis[i][j] = min(dis[i][x] + dis[x][j], dis[i][j]); } } } int l = 0, r = 1731311, ct = -1; while (l <= r) { int mid = l + r >> 1; flow.init(1 + n + v + 2); for (int i = 1; i <= n; i++) { flow.addedge(1, i + 1, 1); for (int j = 1; j <= v; j++) { if (dis[st[i]][j] <= mid) { flow.addedge(i + 1, 1 + j + n, 1); } } } for (int i = 1; i <= v; i++) flow.addedge(1 + i + n, 1 + v + n + 1, 1); flow.addedge(1 + v + n + 1, 1 + v + n + 2, k); flow.dinic(); if (flow.ans == k) { ct = mid; r = mid - 1; } else l = mid + 1; } printf( %d n , ct); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, f = 0; cin >> n; for (int i = 1; i < 50; i++) { if ((i * (i + 1)) / 2 == n) { f = 1; break; } if (i > n) break; } if (f) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 500005; int n; int a[Maxn]; long long L[Maxn], R[Maxn]; int delt[Maxn]; long long res; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); L[i] = L[i - 1] + a[i]; } if (L[n] % 3) printf( 0 n ); else { long long need = L[n] / 3; for (int i = n; i >= 1; i--) { R[i] = R[i + 1] + a[i]; delt[i] = delt[i + 1] + (R[i] == need); } for (int i = 1; i <= n; i++) if (L[i] == need) res += delt[i + 2]; printf( %I64d n , res); } return 0; }
|
#include <bits/stdc++.h> int main() { int n, k; int h[1001] = {0}; scanf( %d%d , &n, &k); int i, j; for (i = 1; i <= n; i++) scanf( %d , &h[i]); int min = 9999999, nn = 1; for (i = 1; i <= n; i++) { if (h[i] < 1 + k * (i - 1)) continue; int ans = 0; for (j = 1; j <= n; j++) if (h[j] != h[i] + k * (j - i)) ans++; if (ans < min) { min = ans; nn = i; } if (min == 0) break; } printf( %d n , min); for (i = 1; i <= n; i++) { if (h[i] > h[nn] + k * (i - nn)) printf( - %d %d n , i, h[i] - h[nn] - k * (i - nn)); else if (h[i] < h[nn] + k * (i - nn)) printf( + %d %d n , i, h[nn] + k * (i - nn) - h[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const int SINF = 0x7fffffff; const long long LINF = 0x3fffffffffffffff; const long long SLINF = 0x7fffffffffffffff; const long double DINF = pow(2, 100); const int MAXN = 1007; const int MOD = static_cast<int>(1e9 + 7); const long double EPS = 1e-11; struct cT { cT() : x(0), y(0) {} cT(long double _x, long double _y) : x(_x), y(_y) {} cT operator+(const cT &a) const { return cT(x + a.x, y + a.y); } cT operator-(const cT &a) const { return cT(x - a.x, y - a.y); } cT operator/(const int a) { return cT(x / a, y / a); } bool operator==(const cT &a) const { return ((((x - a.x) >= 0) ? (x - a.x) : (-(x - a.x))) < EPS && (((y - a.y) >= 0) ? (y - a.y) : (-(y - a.y))) < EPS); } bool operator!=(const cT &a) const { return !((*this) == a); } bool operator<(const cT &a) const { return ((((x - a.x) >= 0) ? (x - a.x) : (-(x - a.x))) > EPS) ? x < a.x : y < a.y - EPS; } long double getk() { return (((x) >= 0) ? (x) : (-(x))) < EPS ? DINF : (y / x); } long double x, y; } cr[MAXN]; struct dT { dT() : k(0) {} dT(cT _cr, long double _k) : cr(_cr), k(_k) {} bool operator<(const dT &a) const { return (cr != a.cr) ? cr < a.cr : k < a.k - EPS; } cT cr; long double k; } med[MAXN * MAXN]; int n; int km; void init(); void input(); void work(); int getans(int l, int r); int add(int x, int y) { x += y; if (x >= MOD) x -= MOD; return x; } void addv(int &x, int y) { x += y; if (x >= MOD) x -= MOD; } int dec(int x, int y) { x -= y; if (x < 0) x += MOD; return x; } void decv(int &x, int y) { x -= y; if (x < 0) x += MOD; } int main() { init(); input(); work(); } void init() { ios::sync_with_stdio(false); } void input() { scanf( %d , &n); int a, b, c, d; for (int i = 1; i <= n; ++i) { scanf( %d%d%d%d , &a, &b, &c, &d); cr[i].x = static_cast<long double>(a * b * d * d) / (a * a * d * d + b * b * c * c); cr[i].y = static_cast<long double>(c * d * b * b) / (a * a * d * d + b * b * c * c); } } void work() { for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { med[++km] = dT((cr[i] + cr[j]) / 2, (cr[j] - cr[i]).getk()); } } sort(med + 1, med + 1 + km); med[km + 1] = dT(cT(DINF, DINF), 1); int pre = 1, ans = 0; for (int i = 1; i <= km + 1; ++i) { if (med[i].cr != med[pre].cr) { addv(ans, getans(pre, i - 1)); pre = i; } } cout << ans << endl; } int getans(int l, int r) { int pre = l; int ans = 1; for (int i = l; i <= r; ++i) { if ((((med[i].k - med[pre].k) >= 0) ? (med[i].k - med[pre].k) : (-(med[i].k - med[pre].k))) > EPS) { ans = static_cast<long long>(ans) * (i - pre + 1) % MOD; pre = i; } } ans = static_cast<long long>(ans) * (r - pre + 2) % MOD; return dec(ans, r - l + 2); }
|
#include <bits/stdc++.h> using namespace std; const long long mx = 223456; long long n, a[mx], b[mx], sum1, sum2, ca, cb; int32_t main() { cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> b[i]; } sort(a, a + n); sort(b, b + n); ca = n - 1; cb = n - 1; for (long long i = 0; i < n * 2; i++) { long long y = 0; if (i % 2 == 0) { if (ca >= 0 && cb >= 0) { if (a[ca] > b[cb]) { sum1 += a[ca]; ca--; } else { cb--; } y = 1; } if (ca < 0 && y == 0) { cb--; y = 1; } if (cb < 0 && y == 0) { sum1 += a[ca]; ca--; y = 1; } } else { if (ca >= 0 && cb >= 0) { if (a[ca] < b[cb]) { sum2 += b[cb]; cb--; } else { ca--; } y = 1; } if (cb < 0 && y == 0) { ca--; y = 1; } if (ca < 0 && y == 0) { sum2 += b[cb]; cb--; y = 1; } } } cout << sum1 - sum2; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t , x , k; cin >> t; while(t--) { cin >> x; k = (int)(sqrt(8 * x + 1)) / 2; if((k * (k + 1) - 2 * x)!=2 && (k * (k + 1) - 2 * x) >= 0) cout << k << n ; else cout << k + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> struct node { int same, rev; } T[524288]; int N, Q, a[100001]; inline void down(int p) { if (T[p].same) { T[p << 1].same = T[p].same; T[p << 1 | 1].same = T[p].same; T[p << 1].rev = T[p << 1 | 1].rev = 0; T[p].same = 0; } else if (T[p].rev) { if (T[p << 1].same) T[p << 1].same = -T[p << 1].same; else T[p << 1].rev ^= 1; if (T[p << 1 | 1].same) T[p << 1 | 1].same = -T[p << 1 | 1].same; else T[p << 1 | 1].rev ^= 1; T[p].rev = 0; } } void P(int p, int l, int r, int L, int R, int w) { if (L <= l && r <= R) { T[p] = {w, 0}; return; } int m = l + r >> 1; down(p); if (L <= m) P(p << 1, l, m, L, R, w); if (R > m) P(p << 1 | 1, m + 1, r, L, R, w); } void REV(int p, int l, int r, int L, int R) { if (L <= l && r <= R) { if (T[p].same) T[p].same = -T[p].same; else T[p].rev ^= 1; return; } int m = l + r >> 1; down(p); if (L <= m) REV(p << 1, l, m, L, R); if (R > m) REV(p << 1 | 1, m + 1, r, L, R); } int G(int x) { int p = 1, l = -100000, r = 100000; while (l < r) { int m = l + r >> 1; down(p); if (x <= m) p <<= 1, r = m; else p = p << 1 | 1, l = m + 1; } return T[p].same; } int main() { scanf( %d%d , &N, &Q); for (int i = 1; i <= N; i++) scanf( %d , a + i); T[1] = {1, 0}; while (Q--) { char op[2]; int x; scanf( %s%d , op, &x); if (op[0] == < ) { if (x <= 0) { if (x != -100000) { P(1, -100000, 100000, -100000, x - 1, -1); P(1, -100000, 100000, -x + 1, 100000, 1); } } else { REV(1, -100000, 100000, -x + 1, x - 1); P(1, -100000, 100000, -100000, -x, -1); P(1, -100000, 100000, x, 100000, 1); } } else { if (x >= 0) { if (x != 100000) { P(1, -100000, 100000, x + 1, 100000, -1); P(1, -100000, 100000, -100000, -x - 1, 1); } } else { REV(1, -100000, 100000, x + 1, -x - 1); P(1, -100000, 100000, -100000, x, 1); P(1, -100000, 100000, -x, 100000, -1); } } } for (int i = 1; i <= N; i++) printf( %d%c , a[i] * G(a[i]), n [i == N]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool found; int n, x, nums[1000], smaller, larger, eq; void Naive() { int median = ((n + 1) / 2); sort(nums, nums + n); if (nums[--median] == x) { printf( 0 ); return; } if (found) { for (int i = 0; i < n && nums[i] <= x; i++) if (x == nums[i] && abs(smaller - median) > abs(i - median)) smaller = i; } larger = n - smaller - found; } void Smart() { larger = n - smaller - eq; if (found) { eq--; int diff = abs(smaller - larger); if (larger <= smaller) { if (diff <= eq) { larger = smaller; eq -= diff; larger += eq / 2 + (eq % 2); smaller += eq / 2; } else { larger += eq; eq = 0; } } else { if (diff <= eq) { smaller = larger; eq -= diff; larger += eq / 2 + (eq % 2); smaller += eq / 2; } else { smaller += eq; eq = 0; } } } } void Greedy() { Smart(); printf( %d , !found + abs(smaller - larger) - (larger > smaller)); } int main() { found = false; scanf( %d %d , &n, &x); for (int i = 0; i < n; i++) { scanf( %d , &nums[i]); smaller += (nums[i] < x); eq += (nums[i] == x); found |= (nums[i] == x); } Greedy(); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e15 + 696969; long long n, k; long long a[1LL << 20], b[1LL << 20]; long long opt[20][1LL << 20]; signed main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); memset(opt, -1, sizeof opt); cin >> n; for (long long i = 1; i < n; i <<= 1) k++; long long ok = false; for (long long i = 0; i < n; i++) { long long x; cin >> x; if (x == -1) ok = true; else if (!ok) a[i] = 0; else a[i - 1] = x; } n--; reverse(a, a + n); for (long long i = k - 1, j = 0; i > 0; i--) { j += 1 << i; b[i] = j; } for (long long i = 0; i < n; i++) { opt[0][i] = a[i]; } for (long long i = 1; i < k; i++) { long long mn = INF; for (long long j = n - 1; j >= 0; j--) { if (j > b[i]) opt[i][j] = INF; else { opt[i][j] = mn + a[j]; mn = min(mn, opt[i - 1][j]); } } } cout << opt[k - 1][0] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct edge { int u; int v; long long cost; edge() {} edge(int u, int v, long long c) : u(u), v(v), cost(c) {} }; long long comb2(long long n) { return (n * (n - 1)) / 2; } const int MAXN = 100100; int n; vector<int> G[MAXN]; edge es[MAXN]; int childNum[MAXN]; long long usedNum[MAXN]; int dfs(int v, int par) { if (childNum[v] >= 0) return childNum[v]; int ret = 1; for (int i = 0; i < (int)G[v].size(); i++) { int next = G[v][i]; if (next != par) ret += dfs(next, v); } return childNum[v] = ret; } int main(void) { cin >> n; for (int i = 0; i < n - 1; i++) { cin >> es[i].u >> es[i].v >> es[i].cost; G[es[i].u].push_back(es[i].v); G[es[i].v].push_back(es[i].u); } for (int i = 1; i <= n; i++) childNum[i] = -1; dfs(1, 0); double sum = 0; for (int i = 0; i < n - 1; i++) { int x = min(childNum[es[i].u], childNum[es[i].v]); usedNum[i] = 2 * (x * comb2(n - x) + (n - x) * comb2(x)); sum += (double)usedNum[i] * (double)es[i].cost; } int q; long long div = (long long)n * (long long)(n - 1) * (long long)(n - 2) / 6; cin >> q; while (q--) { int id; long long cost; cin >> id >> cost; id--; long long diff = es[id].cost - cost; es[id].cost = cost; sum -= (double)diff * (double)usedNum[id]; printf( %.10lf n , sum / (double)div); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n; int k; long long a[100050]; int main() { cin >> n >> k; for (int i = 1; i <= k; i++) cin >> a[i]; long long A = 1, B = 0, C = 0; for (int i = 1; i <= k; i++) { if (n - n % a[i] > C) { A = 1ll * i, B = n / a[i]; C = n - n % a[i]; } } cout << A << << B; return 0; }
|
/*
-- ============================================================================
-- FILE NAME : clk_gen.v
-- DESCRIPTION : ʱÖÓÉú³ÉÄ£¿é
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ´´½¨
-- 1.0.1 2014/06/27 zhangly
-- ============================================================================
*/
/********** ͨÓÃÍ·Îļþ **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** Ä£¿é **********/
module clk_gen (
/********** ʱÖÓÓ븴λ **********/
input wire clk_ref, // »ù±¾Ê±ÖÓ
input wire reset_sw, // È«¾Ö¸´Î»
/********** Éú³ÉʱÖÓ **********/
output wire clk, // ʱÖÓ
output wire clk_, // ·´ÏàʱÖÓ
/********** оƬ¸´Î» **********/
output wire chip_reset // оƬ¸´Î»
);
/********** ÄÚ²¿ÐźŠ**********/
wire locked; // Ëø¶¨ÐźÅ
wire dcm_reset; // dcm ¸´Î»
/********** ²úÉú¸´Î» **********/
// DCM¸´Î»
assign dcm_reset = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;
// оƬ¸´Î»
assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?
`RESET_ENABLE : `RESET_DISABLE;
/********** Xilinx DCM (Digitl Clock Manager) -> altera pll**********/
/* x_s3e_dcm x_s3e_dcm (
.CLKIN_IN (clk_ref), // »ù±¾Ê±ÖÓ
.RST_IN (dcm_reset), // DCM¸´Î»
.CLK0_OUT (clk), // ʱÖÓ
.CLK180_OUT (clk_), // ·´ÏàʱÖÓ
.LOCKED_OUT (locked) // Ëø¶¨
);
*/
altera_dcm x_s3e_dcm (
.inclk0 (clk_ref), // »ù±¾Ê±ÖÓ
.areset (dcm_reset), // DCM¸´Î»
.c0 (clk), // ʱÖÓ
.c1 (clk_), // ·´ÏàʱÖÓ
.locked (locked) // Ëø¶¨
);
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.