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/////////////////////////////////////////////////////////////////////
//// ////
//// simple_spi ('HC11 compatible) testbench ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: tst_bench_top.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
//
// $Date: 2004-02-28 16:01:47 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
`include "timescale.v"
module tst_bench_top();
//
// wires && regs
//
reg clk;
reg rstn;
wire [31:0] adr;
wire [ 7:0] dat_i, dat_o;
wire we;
wire stb;
wire cyc;
wire ack;
wire inta;
reg [1:0] cpol, cpha;
reg [2:0] e;
wire sck, mosi, miso;
reg [7:0] q;
parameter SPCR = 2'b00;
parameter SPSR = 2'b01;
parameter SPDR = 2'b10;
parameter SPER = 2'b11;
//
// Module body
//
integer n;
// generate clock
always #5 clk = ~clk;
// hookup wishbone master model
wb_master_model #(8, 32) u0 (
.clk (clk),
.rst (rstn),
.adr (adr),
.din (dat_i),
.dout(dat_o),
.cyc (cyc),
.stb (stb),
.we (we),
.sel (),
.ack (ack),
.err (1'b0),
.rty (1'b0)
);
// hookup spi core
simple_spi_top spi_top (
// wishbone interface
.clk_i (clk),
.rst_i (rstn),
.cyc_i (cyc),
.stb_i (stb),
.adr_i (adr[1:0]),
.we_i (we),
.dat_i (dat_o),
.dat_o (dat_i),
.ack_o (ack),
.inta_o(inta),
.sck_o (sck),
.mosi_o(mosi),
.miso_i(miso)
);
// hookup spi slave model
spi_slave_model spi_slave (
.csn(1'b0),
.sck(sck),
.di(mosi),
.do(miso)
);
initial
begin
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",tst_bench_top,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
// force spi_slave.debug = 1'b1; // enable spi_slave debug information
force spi_slave.debug = 1'b0; // disable spi_slave debug information
$display("\nstatus: %t Testbench started\n\n", $time);
// initially values
clk = 0;
// reset system
rstn = 1'b1; // negate reset
#2;
rstn = 1'b0; // assert reset
repeat(1) @(posedge clk);
rstn = 1'b1; // negate reset
$display("status: %t done reset", $time);
@(posedge clk);
//
// program core
//
for (cpol=0; cpol<=1; cpol=cpol+1)
for (cpha=0; cpha<=1; cpha=cpha+1)
for (e=0; e<=3; e=e+1)
begin
//set cpol/cpha in spi slave model
force spi_slave.cpol=cpol[0];
force spi_slave.cpha=cpha[0];
$display("cpol:%b, cpha:%b, e:%b", cpol[0],cpha[0],e[1:0]);
// program internal registers
// load control register
u0.wb_write(1, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
//verify control register
u0.wb_cmp (0, SPCR, {4'b0101,cpol[0],cpha[0],e[1:0]} );
// load extended control register
u0.wb_write(1,SPER,8'h0);
//verify extended control register
u0.wb_cmp (0,SPER,8'h0);
//fill memory
for(n=0;n<8;n=n+1) begin
u0.wb_write(1,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
//wait for transfer to finish
u0.wb_read(1,SPSR,q);
while(~q[7]) u0.wb_read(1,SPSR,q);
//clear 'spif' bit
u0.wb_write(1,SPSR,8'h80);
end
//verify memory
for(n=0;n<8;n=n+1) begin
u0.wb_write(1,SPDR,~n);
//wait for transfer to finish
u0.wb_read(1,SPSR,q);
while(~q[7]) u0.wb_read(1,SPSR,q);
//clear 'spif' bit
u0.wb_write(1,SPSR,8'h80);
//verify memory content
u0.wb_cmp(0,SPDR,{cpol[0],cpha[0],e[1:0],n[3:0]});
end
end
// check tip bit
// u0.wb_read(1, SR, q);
// while(q[1])
// u0.wb_read(1, SR, q); // poll it until it is zero
// $display("status: %t tip==0", $time);
#250000; // wait 250us
$display("\n\nstatus: %t Testbench done", $time);
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:08:07 06/04/2015
// Design Name: keymem
// Module Name: F:/Projects/Xilinx/Rijndael/test_memkey.v
// Project Name: Rijndael
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: keymem
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_memkey;
// Inputs
reg [3:0] add;
reg clock;
reg en;
// Outputs
wire [127:0] dout;
// Instantiate the Unit Under Test (UUT)
keymem uut (
.dout(dout),
.add(add),
.clock(clock),
.en(en)
);
always begin
clock = 0;
#10;
clock = 1;
#10;
end
initial begin
// Initialize Inputs
add = 0;
en = 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
#20 add = add + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sq = sqrt(n); if (n % sq == 0) { cout << sq << << n / sq; } else { int i = 0; while (++i) { if (n % (sq - i) == 0) { cout << sq - i << << n / (sq - i); break; } else if (n % (sq + i) == 0) { cout << sq + i << << n / (sq + i); break; } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_FUNCTIONAL_PP_V
|
// wasca_mm_interconnect_0_avalon_st_adapter_004.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 646
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_004 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File : de3d_tc_store.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_store
(
input de_clk, /* Drawing engine clock */
input de_rstn, /* Drawing engine reset */
input tc_ack, /* Texture cache acknowledge */
input [3:0] mipmap, /* incoming mipmap number */
input [209:0] lod_2, /* incoming mipmap number */
input [17:0] ul, /* Upper left texel address */
input [17:0] ur, /* Upper right texel address */
input [17:0] ll, /* Lower left texel address */
input [17:0] lr, /* Lower Right texel address */
input clamp_ul,
input clamp_ll,
input clamp_ur,
input clamp_lr,
input [2:0] bpt,
input [4:0] tfmt,
input pal_mode,
input [3:0] tc_op,
input [11:0] tptch,
input exact,
output reg [3:0] mipmap_store, /* Stored mipmap number */
output reg clamp_ul_r,
output reg clamp_ll_r,
output reg clamp_ur_r,
output reg clamp_lr_r,
output [8:0] ul_store_x,
output [8:0] ul_store_y,
output [8:0] ll_store_x,
output [8:0] ll_store_y,
output [8:0] ur_store_x,
output [8:0] ur_store_y,
output [8:0] lr_store_x,
output [8:0] lr_store_y,
output reg [2:0] bpt_r,
output reg [4:0] tfmt_r,
output reg pal_mode_r,
output reg exact_r,
output reg [3:0] tc_op_store,
output reg [20:0] tex_org,
output reg [11:0] tex_ptch
);
`include "define_3d.h"
reg [11:0] tex_ptch_r;
reg [17:0] ul_store; /* Store UL corner address */
reg [17:0] ur_store; /* Store UL corner address */
reg [17:0] ll_store; /* Store UL corner address */
reg [17:0] lr_store; /* Store UL corner address */
/* store the texel op. */
always @(posedge de_clk or negedge de_rstn)
begin
if (!de_rstn) tc_op_store <= 0;
else if (tc_ack) tc_op_store <= tc_op;
end
/* store texel information in pipe */
always @(posedge de_clk or negedge de_rstn)
begin
if (!de_rstn) mipmap_store <= 0;
else if (tc_ack) mipmap_store <= mipmap;
end
always @(posedge de_clk, negedge de_rstn)
begin
if (!de_rstn) begin
ul_store <= 18'h0;
ur_store <= 18'h0;
ll_store <= 18'h0;
lr_store <= 18'h0;
clamp_ur_r <= 1'b0;
clamp_ul_r <= 1'b0;
clamp_lr_r <= 1'b0;
clamp_ll_r <= 1'b0;
bpt_r <= 3'b000;
tfmt_r <= 5'h0;
pal_mode_r <= 1'b0;
exact_r <= 1'b0;
tex_org <= 21'h0;
end
else if (tc_ack)
begin
ul_store <= ul;
ur_store <= ur;
ll_store <= ll;
lr_store <= lr;
clamp_ur_r <= clamp_ur;
clamp_ul_r <= clamp_ul;
clamp_lr_r <= clamp_lr;
clamp_ll_r <= clamp_ll;
bpt_r <= bpt;
tfmt_r <= tfmt;
pal_mode_r <= pal_mode;
exact_r <= exact;
case(mipmap)
4'b0000: tex_org <= lod_2`LOD_0;
4'b0001: tex_org <= lod_2`LOD_1;
4'b0010: tex_org <= lod_2`LOD_2;
4'b0011: tex_org <= lod_2`LOD_3;
4'b0100: tex_org <= lod_2`LOD_4;
4'b0101: tex_org <= lod_2`LOD_5;
4'b0110: tex_org <= lod_2`LOD_6;
4'b0111: tex_org <= lod_2`LOD_7;
4'b1000: tex_org <= lod_2`LOD_8;
default: tex_org <= lod_2`LOD_9;
endcase
end
end
/* Generate addresses to be used by read controller */
assign ul_store_x = ul_store[17:9];
assign ul_store_y = ul_store[8:0];
assign ll_store_x = ll_store[17:9];
assign ll_store_y = ll_store[8:0];
assign ur_store_x = ur_store[17:9];
assign ur_store_y = ur_store[8:0];
assign lr_store_x = lr_store[17:9];
assign lr_store_y = lr_store[8:0];
always @(posedge de_clk) if(tc_ack) tex_ptch_r <= tptch;
always @* tex_ptch = tex_ptch_r >> mipmap_store; // divide by 2 for smaller LOD's
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = (1LL << 22) + 2; long long n, m; long long a[N]; bool vis[2][N]; void dfs(long long k, long long cur) { if (vis[cur][k]) return; vis[cur][k] = 1; if (cur == 1) return dfs(k, cur ^ 1); for (long long i = 0; i < n; i++) { if ((k & (1LL << i)) == 0) dfs(k | (1LL << i), 0); } dfs(((1LL << n) - 1) ^ k, 1); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (long long i = 0; i < N; i++) vis[1][i] = 1; for (long long i = 1; i <= m; i++) { cin >> a[i]; vis[1][a[i]] = 0; } long long ans = 0; for (long long i = 1; i <= m; i++) { if (vis[1][a[i]]) continue; ans++; dfs(a[i], 1); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); pair<int, int> home, uni; cin >> home.first >> home.second >> uni.first >> uni.second; int count; cin >> count; int solution = 0; int64_t a, b, c; for (int i = 0; i < count; i++) { cin >> a >> b >> c; bool h_p = a * home.first + b * home.second + c > 0; bool u_p = a * uni.first + b * uni.second + c > 0; if ((h_p && !u_p) || (!h_p && u_p)) { solution++; } } cout << solution << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int len, i, l = 0, r = 0, u = 0, d = 0, dif1, dif2; scanf( %d , &len); char str[101]; scanf( %s , str); for (i = 0; i < len; i++) { if (str[i] == L ) l++; else if (str[i] == R ) r++; else if (str[i] == U ) u++; else if (str[i] == D ) d++; } dif1 = l - r; if (dif1 < 0) dif1 = -dif1; dif2 = u - d; if (dif2 < 0) dif2 = -dif2; printf( %d n , (len - (dif1 + dif2))); return 0; }
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for casting a string to a vector type.
module sv_cast_string();
string str;
typedef logic [55:0] strbits;
strbits chars;
initial begin
int i;
str = "";
chars = strbits'(str);
if(chars != 56'h30313233343536)
begin
$display("FAILED 1 chars = %x", chars);
$finish();
end
str = "";
chars = strbits'(str);
if(chars != "")
begin
$display("FAILED 2 chars = %x", chars);
$finish();
end
str = "wrong string";
// Vector to string casting
str = string'(chars);
if(str != "")
begin
$display("FAILED 3 str = %s", str);
$finish();
end
$display("PASSED");
end
endmodule
|
// File: ./ex-target/DotProduct.v
// Generated by MyHDL 1.0dev
// Date: Tue Oct 6 16:32:07 2015
`timescale 1ns/10ps
module DotProduct (
y,
y_da_vec,
y_db_vec,
a_vec,
b_vec
);
// Vector dot product and derivative model using fixbv type.
//
// :param y: return dot(a_vec, b_vec) as fixbv
// :param y_da_vec: return d/da dot(a_vec, b_vec) as vector of fixbv
// :param y_db_vec: return d/db dot(a_vec, b_vec) as vector of fixbv
// :param a_vec: vector of fixbv
// :param b_vec: vector of fixbv
// :param dim: vector dimensionality
// :param fix_min: fixbv min value
// :param fix_max: fixbv max value
// :param fix_res: fixbv resolution
output signed [15:0] y;
reg signed [15:0] y;
output [47:0] y_da_vec;
wire [47:0] y_da_vec;
output [47:0] y_db_vec;
wire [47:0] y_db_vec;
output [47:0] a_vec;
wire [47:0] a_vec;
output [47:0] b_vec;
wire [47:0] b_vec;
wire signed [15:0] a_list [0:3-1];
wire signed [15:0] b_list [0:3-1];
assign b_vec[48-1:32] = None;
assign b_vec[32-1:16] = None;
assign b_vec[16-1:0] = None;
assign a_vec[48-1:32] = None;
assign a_vec[32-1:16] = None;
assign a_vec[16-1:0] = None;
always @(a_list[0], a_list[1], a_list[2], b_list[0], b_list[1], b_list[2]) begin: DOTPRODUCT_DOT
reg signed [32-1:0] y_sum;
integer j;
y_sum = fixbv(0.0);
for (j=0; j<3; j=j+1) begin
y_sum = (y_sum + (a_list[j] * b_list[j]));
end
y = fixbv(y_sum);
end
assign y_da_vec = b_vec;
assign y_db_vec = a_vec;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This module checks integer initialization syntax.
*/
module main;
integer i = 8;
time t = 0;
initial begin
#1 if (i !== 8) begin
$display("FAILED -- i == %b", i);
$finish;
end
if (t !== 0) begin
$display("FAILED -- t == %b", t);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for VVI_LRI
//defines for state names used internally
`define STATE_Start 0
`define STATE_Resting 1
`define STATE_LRI_Timer_Expired 2
`define STATE_VSense_Detected 3
module FB_VVI_LRI
(
input wire clk,
//input events
input wire VSense_eI,
input wire LRI_Timer_Timeout_eI,
//output events
output wire LRI_Timer_Start_eO,
output wire LRI_Timer_Stop_eO,
output wire VPace_eO,
//output variables
output reg signed [15:0] LRI_Timeout_Value_O ,
input reset
);
////BEGIN internal copies of I/O
//input events
wire VSense;
assign VSense = VSense_eI;
wire LRI_Timer_Timeout;
assign LRI_Timer_Timeout = LRI_Timer_Timeout_eI;
//output events
reg LRI_Timer_Start;
assign LRI_Timer_Start_eO = LRI_Timer_Start;
reg LRI_Timer_Stop;
assign LRI_Timer_Stop_eO = LRI_Timer_Stop;
reg VPace;
assign VPace_eO = VPace;
//output variables
reg signed [15:0] LRI_Timeout_Value ;
////END internal copies of I/O
////BEGIN internal vars
////END internal vars
//BEGIN STATE variables
reg [1:0] state = `STATE_Start;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg LRI_Set_Timeout_Value_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_Start;
//reset I/O registers
LRI_Timer_Start = 1'b0;
LRI_Timer_Stop = 1'b0;
VPace = 1'b0;
LRI_Timeout_Value = 0;
//reset internal vars
end else begin
//BEGIN clear output events
LRI_Timer_Start = 1'b0;
LRI_Timer_Stop = 1'b0;
VPace = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_Start: begin
if(1) begin
state = `STATE_Resting;
entered = 1'b1;
end
end
`STATE_Resting: begin
if(VSense) begin
state = `STATE_VSense_Detected;
entered = 1'b1;
end else if(LRI_Timer_Timeout) begin
state = `STATE_LRI_Timer_Expired;
entered = 1'b1;
end
end
`STATE_LRI_Timer_Expired: begin
if(1) begin
state = `STATE_Resting;
entered = 1'b1;
end
end
`STATE_VSense_Detected: begin
if(1) begin
state = `STATE_Resting;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
LRI_Set_Timeout_Value_alg_en = 1'b0;
if(entered) begin
case(state)
`STATE_Start: begin
end
`STATE_Resting: begin
LRI_Set_Timeout_Value_alg_en = 1'b1;
LRI_Timer_Start = 1'b1;
end
`STATE_LRI_Timer_Expired: begin
VPace = 1'b1;
end
`STATE_VSense_Detected: begin
LRI_Timer_Stop = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
if(LRI_Set_Timeout_Value_alg_en) begin
LRI_Timeout_Value = 800;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(LRI_Timer_Start) begin
LRI_Timeout_Value_O = LRI_Timeout_Value;
end
//END update external output variables
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 303; const int MOD = 1e9 + 7; long long ncr[MAX][MAX]; map<int, int> cnt; int tot[MAX]; long long dp[MAX][MAX]; vector<int> fin; int get(int a) { int ans = 1; for (int i = 2; (i * i) <= a; i++) { int k = 0; while ((a % i) == 0) { a /= i; k ^= 1; } if (k) { ans *= i; } } ans *= a; return ans; } int main() { for (int i = 0; i < MAX; i++) { ncr[i][0] = 1; for (int j = 1; j <= i; j++) { ncr[i][j] = (ncr[i - 1][j - 1] + ncr[i - 1][j]) % MOD; } } int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int a; scanf( %d , &a); cnt[get(a)]++; } for (auto x : cnt) { fin.push_back(x.second); } sort(fin.begin(), fin.end()); reverse(fin.begin(), fin.end()); int m = fin.size(); for (int i = 1; i <= m; i++) { tot[i] = tot[i - 1] + fin[i - 1]; } dp[1][fin[0] - 1] = 1; for (int i = 2; i <= m; i++) { int slots = tot[i - 1] + 1; for (int j = 0; j <= n; j++) { if (!dp[i - 1][j]) { continue; } for (int k = 1; k <= min(slots, fin[i - 1]); k++) { for (int l = 0; l <= min(j, k); l++) { dp[i][fin[i - 1] - k + j - l] += (((((dp[i - 1][j] * ncr[j][l]) % MOD) * ncr[fin[i - 1] - 1][k - 1]) % MOD) * ncr[slots - j][k - l]) % MOD; dp[i][fin[i - 1] - k + j - l] %= MOD; } } } } long long ans = dp[m][0]; for (int i = 0; i < m; i++) { for (int j = 1; j <= fin[i]; j++) { ans = (ans * j) % MOD; } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[40000005]; void oku() { int n; cin >> n; for (int i = 0; i < n; i++) a[i] = i; int l, k; for (k = 2, l = 0; k <= n; k++, l++) { int r = (n - 1) / k; a[n + l] = a[r * k + l]; for (; r > 0; r--) { a[r * k + l] = a[(r - 1) * k + l]; } } for (int i = l; i < l + n; i++) printf( %d , a[i] + 1); cout << endl; } void oku2() { int n; cin >> n; for (int i = 0; i < n; i++) a[i] = i; for (int i = 2; i <= n; i++) { for (int k = 0; i * k < n; k++) for (int j = i * k; j + 1 < min(n, i * (k + 1)); j++) swap(a[j], a[j + 1]); } for (int i = 0; i < n; i++) cout << a[i] << ; cout << endl; } int main() { oku(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; template <typename T> T gcd(T a, T b) { T c; while (b) { c = b; b = a % b; a = c; } return a; } template <typename T> T powmod(T a, T b) { T res = 1; a %= mod; while (b) { if (b & 1) res = res * (a % mod); a = a * (a % mod); b >>= 1; } return res; } void Solve() { int n, m; cin >> n >> m; char grid[120][120]; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> grid[i][j]; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (grid[i][j] == B ) { if (j + 1 == m) { cout << i + 1 << << j + 1 << n ; return; } else { int k; for (k = j + 1; k < m; ++k) { if (grid[i][k] != B ) break; } int a = k - j + 1; cout << i + (a / 2) << << j + (a / 2) << n ; return; } } } } } int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); Solve(); }
|
#include <bits/stdc++.h> int main() { int i; for (i = 0; i < 10; i++) { printf( ??%d>>%d?? n , i, i); } printf( ??>>? n ); for (i = 0; i < 9; i++) { printf( %d?<>%d n , i, i + 1); } printf( 9?>>?0 n?<>1 n>>?? n ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_4_V
`define SKY130_FD_SC_HD__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A21BO_BEHAVIORAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s, test = hello ; int c = 0; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == test[c]) { c++; } if (c == 5) { break; } } if (c == 5) { cout << YES << endl; } else { cout << NO << endl; } }
|
`timescale 1ns/1ns
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[10:0] , crc[4:0]=1+x^2+x^5;
//-----------------------------------------------------------------------------
// MQ 3/7/2015: invert output
module usb_crc5(
input [10:0] data_in,
input crc_en,
output [4:0] crc_out,
input rst,
input clk);
reg [4:0] lfsr_q,lfsr_c;
assign crc_out = ~lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[0] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[9] ^ data_in[10];
lfsr_c[1] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[4] ^ data_in[1] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[10];
lfsr_c[2] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[6] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[10];
lfsr_c[3] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[10];
lfsr_c[4] = lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[8] ^ data_in[9] ^ data_in[10];
end // always
always @(posedge clk, posedge rst) begin
if(rst) begin
lfsr_q <= {5{1'b1}};
end
else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc
`ifdef TEST_USB_CRC5
module tb();
reg [10:0] data_in;
reg crc_en;
wire [4:0] crc_out;
reg rst;
wire clk;
sim_clk #(125) clk_125_r(.clk(clk));
usb_crc5 dut(.*);
wire [4:0] to_wire = ~crc_out; //{ crc_out[0], crc_out[1], crc_out[2], crc_out[3], crc_out[4] };
initial begin
$dumpfile("crc5.lxt");
$dumpvars();
rst <= 1'b0;
crc_en <= 1'b0;
wait(clk);
wait(~clk);
rst <= 1'b1;
wait(clk);
wait(~clk);
rst <= 1'b0;
wait(clk);
wait(~clk);
data_in <= 11'b10000000000;
crc_en <= 1'b1;
wait(clk);
wait(~clk);
rst <= 1'b1;
crc_en <= 1'b0;
wait(clk);
wait(~clk);
rst <= 1'b0;
crc_en <= 1'b1;
data_in <= 11'b01000000000;
#1000;
$finish();
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; bool judge(int x) { for (int i = 2; i * i <= x; i++) { if (x % i == 0) return false; } return true; } int main() { int n; scanf( %d , &n); if (judge(n)) { printf( 1 n ); return 0; } if (n % 2) { if (judge(n - 2)) { printf( 2 n ); } else { printf( 3 n ); } return 0; } else { printf( 2 n ); return 0; } return 0; }
|
`timescale 1ns/1ps
`include "output/vlog_constants.v"
`include "../common/wishbone_test_master.v"
`define FIFO_FULL 16
`define FIFO_EMPTY 17
module main;
reg tsf_wr_req = 0;
wire tsf_wr_full;
wire tsf_wr_empty;
wire [7:0] tsf_wr_usedw;
reg [27:0] tsf_val_r;
reg [3:0] tsf_val_f;
reg [4:0] tsf_pid;
reg [15:0] tsf_fid;
reg memacc_rd_req = 0;
wire memacc_rd_full;
wire memacc_rd_empty;
wire [4:0] memacc_rd_usedw;
wire memacc_ad_sel ;
wire [31:0] memacc_ad ;
WB_TEST_MASTER WB();
wire clk = WB.wb_clk;
wire rst = WB.wb_rst;
wb_test_fifos
dut (
.rst_n_i (WB.wb_rst),
.wb_clk_i (WB.wb_clk),
.wb_addr_i (WB.wb_addr[2:0]),
.wb_data_i (WB.wb_data_o),
.wb_data_o (WB.wb_data_i),
.wb_cyc_i (WB.wb_cyc),
.wb_sel_i (WB.wb_bwsel),
.wb_stb_i (WB.wb_stb),
.wb_we_i (WB.wb_we),
.wb_ack_o (WB.wb_ack),
.ft_tsf_wr_req_i (tsf_wr_req),
.ft_tsf_wr_full_o (tsf_wr_full),
.ft_tsf_wr_empty_o (tsf_wr_empty),
.ft_tsf_wr_usedw_o (tsf_wr_usedw),
.ft_tsf_val_r_i (tsf_val_r),
.ft_tsf_val_f_i (tsf_val_f),
.ft_tsf_pid_i (tsf_pid),
.ft_tsf_fid_i (tsf_fid),
.ft_memacc_rd_req_i (memacc_rd_req),
.ft_memacc_rd_full_o (memacc_rd_full),
.ft_memacc_rd_empty_o (memacc_rd_empty),
.ft_memacc_rd_usedw_o (memacc_rd_usedw),
.ft_memacc_ad_sel_o (memacc_ad_sel),
.ft_memacc_ad_o (memacc_ad)
);
reg [31:0] memacc_prev_addr = 'hffffffff;
task wait_fifo_flag(input [31:0] cr_addr, input [31:0] flag, input value);
begin: fifo_full_body
reg [31:0] cr_val;
WB.read32(cr_addr, cr_val);
while(cr_val[flag] != value)
WB.read32(cr_addr, cr_val);
end
endtask
// writes from the host side to MEMACC fifo
task memacc_write( input [31:0] address,
input [31:0] data);
begin
if(memacc_prev_addr + 1 != address)
begin
wait_fifo_flag(`ADDR_FT_MEMACC_CSR, `FIFO_FULL, 0);
WB.write32(`ADDR_FT_MEMACC_R0, 0);
WB.write32(`ADDR_FT_MEMACC_R1, address);
end
wait_fifo_flag(`ADDR_FT_MEMACC_CSR, `FIFO_FULL, 0);
WB.write32(`ADDR_FT_MEMACC_R0, 1);
WB.write32(`ADDR_FT_MEMACC_R1, data);
memacc_prev_addr = address;
end
endtask // UNMATCHED !!
task ts_fifo_write
(
input [27:0] value_r,
input [3:0] value_f,
input [4:0] pid,
input [15:0] fid);
begin
while(tsf_wr_full) @(posedge clk);
tsf_val_r <= value_r;
tsf_val_f <= value_f;
tsf_pid <= pid;
tsf_fid <= fid;
tsf_wr_req <= 1;
@(posedge clk);
tsf_wr_req <= 0;
end
endtask // ts_fifo_write
task ts_fifo_read ( output [27:0] value_r,
output [3:0] value_f,
output [4:0] pid,
output [15:0] fid);
begin : TS_FIFO_READ_BODY
reg [31:0] rval;
wait_fifo_flag(`ADDR_FT_TSF_CSR, `FIFO_EMPTY, 0);
WB.read32(`ADDR_FT_TSF_R0, rval);
value_f = rval[31:28];
value_r = rval[27:0];
WB.read32(`ADDR_FT_TSF_R1, rval);
fid = rval[31:16];
pid = rval[4:0];
end
endtask // ts_fifo_read
integer i;
integer rd_val_f, rd_val_r, rd_pid, rd_fid;
initial begin
wait (WB.ready);
WB.monitor_bus(0);
WB.verbose(0);
for(i=0;i<10;i=i+1) memacc_write(i, 3*i);
for(i=0;i<5;i=i+1) begin
// ts_fifo_read(rd_val_r, rd_val_f, rd_pid, rd_fid);
// $display("TS FIFO READ: val_f %d val_r %d pid %d fid %d", rd_val_f, rd_val_r, rd_pid, rd_fid);
end
end
// MEMACC FIFO data sink
always @(memacc_rd_empty)
memacc_rd_req <= ~memacc_rd_empty;
reg memacc_rd_d0 = 0;
reg [31:0] memacc_addr = 0;
always @(posedge clk) begin
memacc_rd_d0 <= memacc_rd_req;
if(memacc_rd_d0) begin
if(!memacc_ad_sel) begin
$display("MEMACC_SetAddress: %x", memacc_ad);
memacc_addr <= memacc_ad;
end else begin
$display("MEMACC_Write: addr %x data %x", memacc_addr, memacc_ad);
memacc_addr <= memacc_addr + 1;
end
end
end
// write some data to the timestamping FIFO
integer j;
initial begin
wait(WB.ready);
// for(j=0;j<5;j=j+1)
// ts_fifo_write(j, j+10, j+20, j+30);
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_shift #(
parameter SPI_CHAR_LEN_BITS = 10
)(
input clk, // system clock
input rst, // reset
input [31:0] len, // data len in bits (minus one)
input lsb, // lbs first on the line
input go, // start stansfer
input pos_edge, // recognize posedge of sclk
input neg_edge, // recognize negedge of sclk
input rx_negedge, // s_in is sampled on negative edge
input tx_negedge, // s_out is driven on negative edge
output reg tip, // transfer in progress
output last, // last bit
input s_clk, // serial clock
input s_in, // serial in
output reg s_out, // serial out
output reg [SPI_MAX_CHAR-1:0] miso_data, // parallel out
input [SPI_MAX_CHAR-1:0] mosi_data // parallel out
);
localparam SPI_MAX_CHAR = 2 ** SPI_CHAR_LEN_BITS;
//Local Parameters
//Registers/Wires
reg [31:0] cnt; // data bit count
reg [SPI_MAX_CHAR-1:0] data; // shift register
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
//Submodules
//Asynchronous Logic
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
//Synchronous Logic
// Character bit counter
always @(posedge clk) begin
if(rst) begin
cnt <= 0;
end
else begin
if(tip) begin
cnt <= pos_edge ? (cnt - 1) : cnt;
end
else begin
//if len is zero then we put in the max
//else put in the number specified
cnt <= !(|len) ? {1'b1, {SPI_CHAR_LEN_BITS{1'b0}}} : len;
end
end
end
// Transfer in progress
always @(posedge clk) begin
if(rst) begin
tip <= 1'b0;
end
else begin
if(go && ~tip) begin
tip <= 1'b1;
end
else if(tip && last && pos_edge) begin
tip <= 1'b0;
end
end
end
// Sending bits to the line
always @(posedge clk) begin
if (rst) begin
s_out <= 1'b0;
data <= 0;
end
else begin
if (tx_clk && tip) begin
if (!lsb) begin
s_out <= data[(SPI_MAX_CHAR - 1)];
data <= {data[(SPI_MAX_CHAR - 2):0], 1'b1};
end
else begin
s_out <= data[0];
data <= {1'b1, data[(SPI_MAX_CHAR - 1):1]};
end
end
if (!tip) begin
data <= mosi_data;
end
end
end
// Receiving bits from the line
always @(posedge clk) begin
if (rst) begin
miso_data <= 0;
end
else begin
if (rx_clk) begin
//Clock data in on the receive clock
miso_data <= {miso_data[(SPI_MAX_CHAR - 2):0], s_in};
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A222O_PP_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, i, e, f, g, n, m, k, l, r; long long go(long long x) { k = 1; n = 0; m = 0; for (long long i = 1;; i++) { if (x <= 0) return ((m * (m + 1)) % 1000000007 + (n * n) % 1000000007) % 1000000007; if (i % 2 == 1) { n += min(k, x); n %= 1000000007; x -= k; } else { m += min(k, x); m %= 1000000007; x -= k; } k *= 2; } } int main() { cin >> l >> r; cout << (1000000007 + go(r) - go(l - 1)) % 1000000007; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:42:39 05/17/2015
// Design Name: clock_divider
// Module Name: E:/Workspaces/Xilinx/processor/test_clock_divider.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clock_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_clock_divider;
// Inputs
reg in_clk;
reg [31:0] divider_factor;
// Outputs
wire out_clk;
// Instantiate the Unit Under Test (UUT)
clock_divider uut (
.in_clk(in_clk),
.divider_factor(divider_factor),
.out_clk(out_clk)
);
initial begin
// Initialize Inputs
in_clk = 0;
divider_factor = 0;
#200;
divider_factor = 1;
#300;
divider_factor = 2;
end
always #10 in_clk = !in_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long m, n, q = 998244853, sum = 1, a = 1, b = 1, r = 0, x = 208513042, y, z; cin >> n >> m; if (n == 0) { cout << 0; return 0; } if (m == 0) { cout << n; return 0; } for (long long i = 1; i < min(m, n); i++) { a = (a * (m + n + 1 - i)) % q; b = (b * i) % q; r = ((a % b) + r * i) % q; sum = (sum + a / b) % q; } a = (a * (m + n + 1 - min(m, n))) % q; b = (b * min(m, n)) % q; r = (r * min(m, n)) % q; for (long long j = 1 + min(m, n); j <= 2000; j++) { a = (a * j) % q; b = (b * j) % q; r = (r * j) % q; } y = (r * x) % q; sum = (sum + y) % q; if (n > m) { y = (a * x) % q; z = (y * (n - m)) % q; sum = (sum + z) % q; } cout << sum; return 0; }
|
#include <bits/stdc++.h> const int dx[] = {1, 0, -1, 0}; const int dy[] = {0, 1, 0, -1}; using namespace std; const long long MOD = 1000000009; const int MAXM = 100010; int m; long long pow_mod[MAXM]; int X[MAXM], Y[MAXM]; map<pair<int, int>, int> ma; set<int> S; set<int> up[MAXM], down[MAXM]; void init() { pow_mod[0] = 1; for (int i = 1; i < m; i++) { pow_mod[i] = (pow_mod[i - 1] * m) % MOD; } } bool ok(int k) { for (auto el : up[k]) { if (down[el].size() <= 1) return false; } return true; } int main() { cin >> m; init(); for (int i = 0; i < m; i++) { cin >> X[i] >> Y[i]; ma.insert(make_pair(pair<int, int>(X[i], Y[i]), i)); } for (auto el : ma) { int y = el.first.second; int x = el.first.first; for (int d = -1; d <= 1; d++) { pair<int, int> tmp = pair<int, int>(x + d, y + 1); if (ma.count(tmp)) { up[el.second].insert(ma[tmp]); down[ma[tmp]].insert(el.second); } } } for (int i = 0; i < m; i++) if (ok(i)) S.insert(i); long long ret = 0; for (int i = 0; i < m; i++) { int er; if (i % 2 == 0) { er = *S.rbegin(); } else { er = *S.begin(); } ret += pow_mod[m - i - 1] * (long long)er % MOD; ret %= MOD; S.erase(er); for (auto el : up[er]) { down[el].erase(er); if (ok(el)) S.insert(el); else S.erase(el); for (auto ell : down[el]) { if (ok(ell)) S.insert(ell); else S.erase(ell); } } for (auto el : down[er]) { up[el].erase(er); if (ok(el)) S.insert(el); else S.erase(el); } } cout << ret << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; map<long long, int> cont; int n; int ans; int main() { while (~scanf( %d , &n)) { int a; long long num = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a); num += a; ans = max(ans, ++cont[num]); } printf( %d n , n - ans); } cont.clear(); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Sep 27 18:05:22 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_adder.v
// Title : Integer adder / subtractor with comparison flag generation
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_adder (
// ----- Inputs -------
adder_op_x,
adder_op_x_n,
operand_0_x,
operand_1_x,
// ----- Outputs -------
adder_result_x,
adder_carry_n_x,
adder_overflow_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
input adder_op_x_n; // Inverted version of adder_op_x
input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
wire [`LM32_WORD_RNG] adder_result_x;
output adder_carry_n_x; // Inverted carry
wire adder_carry_n_x;
output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
reg adder_overflow_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire a_sign; // Sign (i.e. positive or negative) of operand 0
wire b_sign; // Sign of operand 1
wire result_sign; // Sign of result
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_addsub addsub (
// ----- Inputs -----
.DataA (operand_0_x),
.DataB (operand_1_x),
.Cin (adder_op_x),
.Add_Sub (adder_op_x_n),
// ----- Ouputs -----
.Result (adder_result_x),
.Cout (adder_carry_n_x)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Extract signs of operands and result
assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
// Determine whether an overflow occured when performing a subtraction
always @(*)
begin
// +ve - -ve = -ve -> overflow
// -ve - +ve = +ve -> overflow
if ( (!a_sign & b_sign & result_sign)
|| (a_sign & !b_sign & !result_sign)
)
adder_overflow_x = `TRUE;
else
adder_overflow_x = `FALSE;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_1_V
`define SKY130_FD_SC_HVL__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_1_V
|
`timescale 1 ns / 1 ps
module pmod_io_switch_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire [7:0] sw2pl_data_in,
input wire [7:0] pl2sw_data_o,
input wire [7:0] pl2sw_tri_o,
input wire [7:0] pmod2sw_data_in,
output wire [7:0] sw2pmod_data_out,
output wire [7:0] sw2pmod_tri_out,
output wire pwm_i_in,
input wire pwm_o_in,
input wire pwm_t_in,
output wire cap0_i_in,
input wire gen0_o_in,
input wire gen0_t_in,
output wire spick_i_in,
input wire spick_o_in,
input wire spick_t_in,
output wire miso_i_in,
input wire miso_o_in,
input wire miso_t_in,
output wire mosi_i_in,
input wire mosi_o_in,
input wire mosi_t_in,
output wire ss_i_in,
input wire ss_o_in,
input wire ss_t_in,
output wire sda_i_in,
input wire sda_o_in,
input wire sda_t_in,
output wire scl_i_in,
input wire scl_o_in,
input wire scl_t_in,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
pmod_io_switch_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) pmod_io_switch_v1_0_S00_AXI_inst (
.sw2pl_data_in(sw2pl_data_in),
.pl2sw_data_o(pl2sw_data_o),
.pl2sw_tri_o(pl2sw_tri_o),
.pmod2sw_data_in(pmod2sw_data_in),
.sw2pmod_data_out(sw2pmod_data_out),
.sw2pmod_tri_out(sw2pmod_tri_out),
// timer
.pwm_i_in(pwm_i_in),
.pwm_o_in(pwm_o_in),
.pwm_t_in(pwm_t_in),
.cap0_i_in(cap0_i_in),
.gen0_o_in(gen0_o_in),
.gen0_t_in(gen0_t_in),
// SPI channel
.spick_i_in(spick_i_in),
.spick_o_in(spick_o_in),
.spick_t_in(spick_t_in),
.miso_i_in(miso_i_in),
.miso_o_in(miso_o_in),
.miso_t_in(miso_t_in),
.mosi_i_in(mosi_i_in),
.mosi_o_in(mosi_o_in),
.mosi_t_in(mosi_t_in),
.ss_i_in(ss_i_in),
.ss_o_in(ss_o_in),
.ss_t_in(ss_t_in),
// I2C channel
.sda_i_in(sda_i_in),
.sda_o_in(sda_o_in),
.sda_t_in(sda_t_in),
.scl_i_in(scl_i_in),
.scl_o_in(scl_o_in),
.scl_t_in(scl_t_in),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Sine DDS look up table
*/
module sine_dds_lut #
(
parameter OUTPUT_WIDTH = 16,
parameter INPUT_WIDTH = OUTPUT_WIDTH+2
)
(
input wire clk,
input wire rst,
/*
* AXI stream phase input
*/
input wire [INPUT_WIDTH-1:0] input_phase_tdata,
input wire input_phase_tvalid,
output wire input_phase_tready,
/*
* AXI stream sample output
*/
output wire [OUTPUT_WIDTH-1:0] output_sample_i_tdata,
output wire [OUTPUT_WIDTH-1:0] output_sample_q_tdata,
output wire output_sample_tvalid,
input wire output_sample_tready
);
localparam W = (INPUT_WIDTH-2)/2;
reg [INPUT_WIDTH-1:0] phase_reg = 0;
integer i;
// coarse sine and cosine LUTs
reg [OUTPUT_WIDTH-1:0] coarse_c_lut[2**(W+1)-1:0];
reg [OUTPUT_WIDTH-1:0] coarse_s_lut[2**(W+1)-1:0];
initial begin
for (i = 0; i < 2**(W+1); i = i + 1) begin
coarse_c_lut[i] = $cos(2*3.*i/2**(W+2))*(2**(OUTPUT_WIDTH-1)-1);
coarse_s_lut[i] = $sin(2*3.*i/2**(W+2))*(2**(OUTPUT_WIDTH-1)-1);
end
end
// fine sine LUT
reg [(OUTPUT_WIDTH/2)-1:0] fine_s_lut[2**W-1:0];
initial begin
for (i = 0; i < 2**W; i = i + 1) begin
fine_s_lut[i] = $sin(2*3.*(i-2**(W-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1);
end
end
reg [OUTPUT_WIDTH-1:0] sample_i_reg = 0;
reg [OUTPUT_WIDTH-1:0] sample_q_reg = 0;
wire SIGN = phase_reg[INPUT_WIDTH-1];
wire SLOPE = phase_reg[INPUT_WIDTH-2];
wire [W:0] A = phase_reg[INPUT_WIDTH-2:W];
wire [W-1:0] B = phase_reg[W-1:0];
reg sign_reg_1 = 0;
reg sign_reg_2 = 0;
reg sign_reg_3 = 0;
reg sign_reg_4 = 0;
reg [OUTPUT_WIDTH-1:0] ccs_reg_1 = 0, ccs_reg_2 = 0, ccs_reg_3 = 0;
reg [OUTPUT_WIDTH-1:0] css_reg_1 = 0, css_reg_2 = 0, css_reg_3 = 0;
reg [(OUTPUT_WIDTH/2)-1:0] fss_reg_1 = 0, fss_reg_2 = 0;
reg [(OUTPUT_WIDTH*2)-1:0] cp_reg_1 = 0;
reg [(OUTPUT_WIDTH*2)-1:0] sp_reg_1 = 0;
reg [OUTPUT_WIDTH-1:0] cs_reg_1 = 0;
reg [OUTPUT_WIDTH-1:0] ss_reg_1 = 0;
assign input_phase_tready = output_sample_tready;
assign output_sample_i_tdata = sample_i_reg;
assign output_sample_q_tdata = sample_q_reg;
assign output_sample_tvalid = input_phase_tvalid;
always @(posedge clk) begin
if (rst) begin
phase_reg <= 0;
end else begin
if (input_phase_tready & input_phase_tvalid) begin
phase_reg <= input_phase_tdata;
end
end
if (input_phase_tready & input_phase_tvalid) begin
// pipeline sits primarily in DSP slice
// sin(A+B) = sin(A) + cos(A)*sin(B)
// cos(A+B) = cos(A) - sin(A)*sin(B)
// read samples
sign_reg_1 <= SIGN;
ccs_reg_1 <= coarse_c_lut[A];
css_reg_1 <= coarse_s_lut[A];
fss_reg_1 <= fine_s_lut[B];
// pipeline
sign_reg_2 <= sign_reg_1;
ccs_reg_2 <= ccs_reg_1;
css_reg_2 <= css_reg_1;
fss_reg_2 <= fss_reg_1;
// multiply
sign_reg_3 <= sign_reg_2;
ccs_reg_3 <= ccs_reg_2;
css_reg_3 <= css_reg_2;
cp_reg_1 <= $signed(css_reg_2) * $signed(fss_reg_2);
sp_reg_1 <= $signed(ccs_reg_2) * $signed(fss_reg_2);
// add
sign_reg_4 <= sign_reg_3;
cs_reg_1 <= ccs_reg_3 - (cp_reg_1 >> (OUTPUT_WIDTH-1));
ss_reg_1 <= css_reg_3 + (sp_reg_1 >> (OUTPUT_WIDTH-1));
// negate output samples
sample_i_reg <= sign_reg_4 ? -cs_reg_1 : cs_reg_1;
sample_q_reg <= sign_reg_4 ? -ss_reg_1 : ss_reg_1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500005, mod = 1000000007; long long int a, b, c, d, e, f, g, h[N], arr[N]; string s; vector<long long int> v; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> a; long long int ans = 0, tek = 0, cift = 0; for (long long int i = 1; i <= a; i++) { cin >> arr[i]; ans += arr[i] / 2; if (i % 2 == 0) cift += arr[i] % 2; else tek += arr[i] % 2; if (tek and cift) tek--, cift--, ans++; } cout << ans << endl; }
|
// HERE IS THE TEST CASE
module bt (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [7:0] in;
output [7:0] out;
wire [7:0] out = ~in;
endmodule // bottm
module top (/*AUTOARG*/
// Outputs
outgo,
// Inputs
incom
);
input [31:0] incom;
output [31:0] outgo;
/* bt AUTO_TEMPLATE (
.in (incom[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
.out (outgo[@"(concat (int-to-string (+ (* 8 @) 7)) \":\" (int-to-string ( * 8 @)))"]));
*/
bt BT0 (/*AUTOINST*/
// Outputs
.out (outgo[7:0]), // Templated
// Inputs
.in (incom[7:0])); // Templated
bt BT1 (/*AUTOINST*/
// Outputs
.out (outgo[15:8]), // Templated
// Inputs
.in (incom[15:8])); // Templated
bt BT2 (/*AUTOINST*/
// Outputs
.out (outgo[23:16]), // Templated
// Inputs
.in (incom[23:16])); // Templated
bt BT3 (/*AUTOINST*/
// Outputs
.out (outgo[31:24]), // Templated
// Inputs
.in (incom[31:24])); // Templated
endmodule // top
|
`timescale 1ns/1ns
module sum_test;
reg clk;
wire [10:0] s;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
sum #(5, 8) sum (clk, {8'd10,8'd20,8'd30,8'd40,8'd50}, s);
initial begin
$display("Starting...");
repeat (50) @(posedge clk);
$display("sum = %d",s);
if (s !== 150)
$display("FAILED: expected 150, received %0d",s);
else
$display("PASSED");
$finish;
end
endmodule
module sum
#(
parameter n = 4,
parameter width = 8,
parameter log_n = $clog2(n)
)
(
input clk,
input [n*width-1:0]addends,
output reg [log_n+width-1:0] s
);
generate
if (n==1)
always @(*) s = addends;
else begin
wire [$clog2(n/2)+width-1:0] a1;
wire [$clog2(n-n/2)+width-1:0] a2;
sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1);
sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2);
always @(posedge clk) s <= a1 + a2;
end
endgenerate
endmodule // sum
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// Memory Buffer Arbiter ////
//// Arbitrates between the internal DMA and external bus ////
//// interface for the internal buffer memory ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_mem_arb.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_mem_arb.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.3 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.2 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:51 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:10:52 rudi
// Initial Release
//
//
`include "usbf_defines.v"
module usbf_mem_arb( phy_clk, wclk, rst,
// SSRAM Interface
sram_adr, sram_din, sram_dout, sram_re, sram_we,
// IDMA Memory Interface
madr, mdout, mdin, mwe, mreq, mack,
// WISHBONE Memory Interface
wadr, wdout, wdin, wwe, wreq, wack
);
parameter SSRAM_HADR = 14;
input phy_clk, wclk, rst;
output [SSRAM_HADR:0] sram_adr;
input [31:0] sram_din;
output [31:0] sram_dout;
output sram_re, sram_we;
input [SSRAM_HADR:0] madr;
output [31:0] mdout;
input [31:0] mdin;
input mwe;
input mreq;
output mack;
input [SSRAM_HADR:0] wadr;
output [31:0] wdout;
input [31:0] wdin;
input wwe;
input wreq;
output wack;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire wsel;
reg [SSRAM_HADR:0] sram_adr;
reg [31:0] sram_dout;
reg sram_we;
wire mack;
wire mcyc;
reg wack_r;
///////////////////////////////////////////////////////////////////
//
// Memory Arbiter Logic
//
// IDMA has always first priority
// -----------------------------------------
// Ctrl Signals
assign wsel = (wreq | wack) & !mreq;
// -----------------------------------------
// SSRAM Specific
// Data Path
always @(wsel or wdin or mdin)
if(wsel) sram_dout = wdin;
else sram_dout = mdin;
// Address Path
always @(wsel or wadr or madr)
if(wsel) sram_adr = wadr;
else sram_adr = madr;
// Write Enable Path
always @(wsel or wwe or wreq or mwe or mcyc)
if(wsel) sram_we = wreq & wwe;
else sram_we = mwe & mcyc;
assign sram_re = 1'b1;
// -----------------------------------------
// IDMA specific
assign mdout = sram_din;
assign mack = mreq;
assign mcyc = mack; // Qualifier for writes
// -----------------------------------------
// WISHBONE specific
assign wdout = sram_din;
assign wack = wack_r & !mreq;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) wack_r <= 1'b0;
//to the prefered high reset
if(rst) wack_r <= 1'b0;
else wack_r <= wreq & !mreq & !wack;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ans = 0; int n, u, r; vector<int> b, k; vector<int> p; void exec(vector<int> a, int type, int count) { if (count < u) { if (type == 0) { for (int i = 0; i < n; ++i) a[i] = a[i] ^ b[i]; exec(a, 1, count + 1); } else { vector<int> aa(n); for (int i = 0; i < n; ++i) aa[i] = a[p[i]] + r; int rest = u - count - 1; long long cur_cand = 0; if (rest & 1) { vector<int> aaa(n); for (int i = 0; i < n; ++i) aaa[i] = aa[i] ^ b[i]; cur_cand = inner_product(aaa.begin(), aaa.end(), k.begin(), 0LL); } else { cur_cand = inner_product(aa.begin(), aa.end(), k.begin(), 0LL); } ans = max(cur_cand, ans); exec(aa, 0, count + 1); exec(aa, 1, count + 1); } } else { long long cand = inner_product(a.begin(), a.end(), k.begin(), 0LL); ans = max(cand, ans); } } int main() { cin >> n >> u >> r; vector<int> a(n); b.resize(n); k.resize(n); p.resize(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; for (int i = 0; i < n; ++i) cin >> k[i]; for (int i = 0; i < n; ++i) { cin >> p[i]; --p[i]; } for (int i = 0; i < n; ++i) { ans += k[i] * (u & 1 ? a[i] ^ b[i] : a[i]); } exec(a, 1, 0); exec(a, 0, 0); cout << ans; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary or ^~(value)
//
module main;
reg [3:0] vect;
reg error;
wire result;
assign result = ^~(vect);
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
for(vect=4'b0011;vect<4'b0000;vect = vect << 1)
begin
#1;
if(result !== 1'b0)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
#1;
if(result !== 1'b1)
begin
$display("FAILED - Unary xnor ^~(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; inline int add(int a, int b, int m = 1000000007) { a += b; if (a >= m) a -= m; return a; } inline int mul(int a, int b, int m = 1000000007) { return (int)(((long long)a * (long long)b) % m); } inline int norm(int x, int m = 1000000007) { if (x >= m) x %= m; if (x < 0) x += m; return x; } inline int neg(int x, int m = 1000000007) { x = -x; return norm(x); } int c[501]; int dp[501][501]; int f(int i, int j) { if (i == j) return 1; if (i == j - 1) return 2 - (int)(c[i] == c[j]); int &ans = dp[i][j]; if (ans != -1) return ans; ans = 1000000007; for (int k = i; k <= j - 1; ++k) { ans = min(ans, f(i, k) + f(k + 1, j)); } if (c[i] == c[j]) ans = min(ans, f(i + 1, j - 1)); return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> c[i]; memset(dp, -1, sizeof(dp)); cout << f(1, n); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, a, b, c, num = 0; scanf( %d%d , &x, &y); a = b = c = y; while (a < x || b < x || c < x) { if (a <= b && a <= c) a = b + c - 1; else if (b <= a && b <= c) b = a + c - 1; else c = a + b - 1; num++; } printf( %d , num); }
|
`define bsg_dff_en_macro(bits,womp) \
if (harden_p && width_p==bits && (strength_p==womp)) \
begin: macro \
bsg_rp_tsmc_40_EDFD``womp``BWP_b``bits dff(.i0(data_i) \
,.i1({ width_p { en_i } }) \
,.i2({ width_p {clk_i} }) \
,.o(data_o) \
); \
end
module bsg_dff_en #(width_p="inv"
, harden_p=1
, strength_p=1
)
(input clk_i
,input [width_p-1:0] data_i
,input en_i
,output [width_p-1:0] data_o
);
`bsg_dff_en_macro(40,1) else
`bsg_dff_en_macro(39,1) else
`bsg_dff_en_macro(38,1) else
`bsg_dff_en_macro(37,1) else
`bsg_dff_en_macro(36,1) else
`bsg_dff_en_macro(35,1) else
`bsg_dff_en_macro(34,1) else
`bsg_dff_en_macro(33,1) else
`bsg_dff_en_macro(32,1) else
`bsg_dff_en_macro(31,1) else
`bsg_dff_en_macro(30,1) else
`bsg_dff_en_macro(29,1) else
`bsg_dff_en_macro(28,1) else
`bsg_dff_en_macro(27,1) else
`bsg_dff_en_macro(26,1) else
`bsg_dff_en_macro(25,1) else
`bsg_dff_en_macro(24,1) else
`bsg_dff_en_macro(23,1) else
`bsg_dff_en_macro(22,1) else
`bsg_dff_en_macro(21,1) else
`bsg_dff_en_macro(20,1) else
`bsg_dff_en_macro(19,1) else
`bsg_dff_en_macro(18,1) else
`bsg_dff_en_macro(17,1) else
`bsg_dff_en_macro(16,1) else
`bsg_dff_en_macro(15,1) else
`bsg_dff_en_macro(14,1) else
`bsg_dff_en_macro(13,1) else
`bsg_dff_en_macro(12,1) else
`bsg_dff_en_macro(11,1) else
`bsg_dff_en_macro(10,1) else
`bsg_dff_en_macro(9,1) else
`bsg_dff_en_macro(8,1) else
`bsg_dff_en_macro(7,1) else
`bsg_dff_en_macro(6,1) else
`bsg_dff_en_macro(5,1) else
`bsg_dff_en_macro(4,1) else
`bsg_dff_en_macro(3,1) else
`bsg_dff_en_macro(2,1) else
`bsg_dff_en_macro(1,1) else
`bsg_dff_en_macro(40,2) else
`bsg_dff_en_macro(39,2) else
`bsg_dff_en_macro(38,2) else
`bsg_dff_en_macro(37,2) else
`bsg_dff_en_macro(36,2) else
`bsg_dff_en_macro(35,2) else
`bsg_dff_en_macro(34,2) else
`bsg_dff_en_macro(33,2) else
`bsg_dff_en_macro(32,2) else
`bsg_dff_en_macro(31,2) else
`bsg_dff_en_macro(30,2) else
`bsg_dff_en_macro(29,2) else
`bsg_dff_en_macro(28,2) else
`bsg_dff_en_macro(27,2) else
`bsg_dff_en_macro(26,2) else
`bsg_dff_en_macro(25,2) else
`bsg_dff_en_macro(24,2) else
`bsg_dff_en_macro(23,2) else
`bsg_dff_en_macro(22,2) else
`bsg_dff_en_macro(21,2) else
`bsg_dff_en_macro(20,2) else
`bsg_dff_en_macro(19,2) else
`bsg_dff_en_macro(18,2) else
`bsg_dff_en_macro(17,2) else
`bsg_dff_en_macro(16,2) else
`bsg_dff_en_macro(15,2) else
`bsg_dff_en_macro(14,2) else
`bsg_dff_en_macro(13,2) else
`bsg_dff_en_macro(12,2) else
`bsg_dff_en_macro(11,2) else
`bsg_dff_en_macro(10,2) else
`bsg_dff_en_macro(9,2) else
`bsg_dff_en_macro(8,2) else
`bsg_dff_en_macro(7,2) else
`bsg_dff_en_macro(6,2) else
`bsg_dff_en_macro(5,2) else
`bsg_dff_en_macro(4,2) else
`bsg_dff_en_macro(3,2) else
`bsg_dff_en_macro(2,2) else
`bsg_dff_en_macro(1,2) else
`bsg_dff_en_macro(40,4) else
`bsg_dff_en_macro(39,4) else
`bsg_dff_en_macro(38,4) else
`bsg_dff_en_macro(37,4) else
`bsg_dff_en_macro(36,4) else
`bsg_dff_en_macro(35,4) else
`bsg_dff_en_macro(34,4) else
`bsg_dff_en_macro(33,4) else
`bsg_dff_en_macro(32,4) else
`bsg_dff_en_macro(31,4) else
`bsg_dff_en_macro(30,4) else
`bsg_dff_en_macro(29,4) else
`bsg_dff_en_macro(28,4) else
`bsg_dff_en_macro(27,4) else
`bsg_dff_en_macro(26,4) else
`bsg_dff_en_macro(25,4) else
`bsg_dff_en_macro(24,4) else
`bsg_dff_en_macro(23,4) else
`bsg_dff_en_macro(22,4) else
`bsg_dff_en_macro(21,4) else
`bsg_dff_en_macro(20,4) else
`bsg_dff_en_macro(19,4) else
`bsg_dff_en_macro(18,4) else
`bsg_dff_en_macro(17,4) else
`bsg_dff_en_macro(16,4) else
`bsg_dff_en_macro(15,4) else
`bsg_dff_en_macro(14,4) else
`bsg_dff_en_macro(13,4) else
`bsg_dff_en_macro(12,4) else
`bsg_dff_en_macro(11,4) else
`bsg_dff_en_macro(10,4) else
`bsg_dff_en_macro(9,4) else
`bsg_dff_en_macro(8,4) else
`bsg_dff_en_macro(7,4) else
`bsg_dff_en_macro(6,4) else
`bsg_dff_en_macro(5,4) else
`bsg_dff_en_macro(4,4) else
`bsg_dff_en_macro(3,4) else
`bsg_dff_en_macro(2,4) else
`bsg_dff_en_macro(1,4) else
begin : notmacro
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
if (en_i)
data_r <= data_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_en)
|
#include <bits/stdc++.h> using namespace std; const long long UNDEF = -1; const long long INF = 1e18; template <typename T> inline bool chkmax(T &aa, T bb) { return aa < bb ? aa = bb, true : false; } template <typename T> inline bool chkmin(T &aa, T bb) { return aa > bb ? aa = bb, true : false; } static char stdinBuffer[1024]; static char *stdinDataEnd = stdinBuffer + sizeof(stdinBuffer); static const char *stdinPos = stdinDataEnd; void readAhead(size_t amount) { size_t remaining = stdinDataEnd - stdinPos; if (remaining < amount) { memmove(stdinBuffer, stdinPos, remaining); size_t sz = fread(stdinBuffer + remaining, 1, sizeof(stdinBuffer) - remaining, stdin); stdinPos = stdinBuffer; stdinDataEnd = stdinBuffer + remaining + sz; if (stdinDataEnd != stdinBuffer + sizeof(stdinBuffer)) *stdinDataEnd = 0; } } int readInt() { readAhead(16); int x = 0; bool neg = false; while (*stdinPos == || *stdinPos == n ) ++stdinPos; if (*stdinPos == - ) { ++stdinPos; neg = true; } while (*stdinPos >= 0 && *stdinPos <= 9 ) { x *= 10; x += *stdinPos - 0 ; ++stdinPos; } return neg ? -x : x; } char readCh() { readAhead(16); while (*stdinPos == || *stdinPos == n ) ++stdinPos; char ans = *stdinPos; ++stdinPos; return ans; } inline int rri() { char c; while (c = getchar(), c <= ) ; bool sign = c == - ; if (sign) { c = getchar(); } int res = c - 0 ; while (c = getchar(), c >= 0 && c <= 9 ) { res = res * 10 + (c - 0 ); } return sign ? -res : res; } inline long long rrl() { char c; while (c = getchar(), c <= ) ; bool sign = c == - ; if (sign) { c = getchar(); } long long res = c - 0 ; while (c = getchar(), c >= 0 && c <= 9 ) { res = res * 10 + (c - 0 ); } return sign ? -res : res; } inline char rrc() { char c; while (c = getchar(), c <= ) ; return c; } inline int rrs(char *target) { char c; while (c = getchar(), c <= ) ; int idx = -1; target[++idx] = c; while (1) { c = getchar(); if (c <= ) { target[++idx] = 0 ; return idx; } target[++idx] = c; } } vector<vector<int> > matrixUnit(long long n) { vector<vector<int> > res(n, vector<int>(n)); for (long long i = 0; i < n; i++) res[i][i] = 1; return res; } vector<vector<int> > matrixMul(const vector<vector<int> > &a, const vector<vector<int> > &b) { long long n = a.size(); long long m = a[0].size(); long long k = b[0].size(); vector<vector<int> > res(n, vector<int>(k)); for (long long i = 0; i < n; i++) for (long long j = 0; j < k; j++) for (long long p = 0; p < m; p++) res[i][j] = (res[i][j] + (long long)a[i][p] * b[p][j]) % 1000000007LL; return res; } void matrixMult(vector<vector<int> > &res, const vector<vector<int> > &a, const vector<vector<int> > &b) { long long n = a.size(); long long m = a[0].size(); long long k = b[0].size(); for (long long i = 0; i < n; i++) for (long long j = 0; j < k; j++) { long long ans = 0; for (long long p = 0; p < m; p++) ans = (ans + (long long)a[i][p] * b[p][j]) % 1000000007LL; res[i][j] = ans; } } const int mn = 2004; bitset<mn> g[mn]; bool bf(int n) { vector<vector<int> > inp; inp.resize(n); for (int x = 0; x < n; x++) { inp[x].resize(n); for (int y = 0; y < n; y++) inp[x][y] = g[x][y]; } vector<vector<int> > a = inp; for (int k = 0; k < 500; k++) { bool ok = 1; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { if (a[i][j] == 0) { ok = 0; break; } } if (ok) return 1; a = matrixMul(a, inp); } return 0; } bitset<mn> h[mn]; bitset<mn> seen; bool solve2(int n) { queue<int> q; for (int x = 0; x < n; x++) { if (h[0][x]) q.push(x); } seen = h[0]; while (!q.empty()) { int x = q.front(); q.pop(); for (int y = 0; y < n; y++) { if ((!seen[y]) && h[x][y]) { q.push(y); seen[y] = true; } } } assert(seen.count() <= n); return (int)seen.count() == n; } bool solve(int n) { int spec = -1; for (int k = 0; k < n; k++) if (g[k][k]) spec = k; assert(spec != -1); for (int x = 0; x < n; x++) for (int y = 0; y < n; y++) { int sx = (x == spec || x == 0) ? x ^ spec : x; int sy = (y == spec || y == 0) ? y ^ spec : y; h[sx][sy] = g[x][y]; } assert(h[0][0]); if (!solve2(n)) return 0; for (int x = 0; x < n; x++) for (int y = 0; y < n; y++) { g[x][y] = h[y][x]; } for (int x = 0; x < n; x++) h[x] = g[x]; if (!solve2(n)) return 0; return 1; } void test() { srand(time(0) + clock() + rand()); for (int j = 0; j < 1000; j++) { int n = (rand() % 6) + 1; for (int x = 0; x < n; x++) { h[x].reset(); g[x].reset(); for (int y = 0; y < n; y++) g[x][y] = rand() & 1; } int k = rand() % n; g[k][k] = 1; bool b = bf(n); bool s = solve(n); if (b != s) { for (int x = 0; x < n; x++) { for (int y = 0; y < n; y++) printf( %d , (int)g[x][y]); printf( n ); } printf( b:%d s:%d n , b, s); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n = readInt(); for (int x = 0; x < n; x++) for (int y = 0; y < n; y++) { int t = readInt(); t = (t > 0) ? 1 : 0; g[x][y] = t; } bool final = solve(n); if (final) printf( YES n ); else printf( NO n ); }
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; while (t--) { long long int n = 0, m = 0, k = 0, i = 0, j = 0, p = 0, q = 0, x = 0, y = 0, z = 0, ans = 0, cnt = 0, l = 0, r = 0, mid = 0, lo = 0, hi = 0; string s; bool flag = false; cin >> n; for (i = 0; i <= n; i++) x = (i + 1) * (n - i), cnt = max(cnt, x); cout << cnt << endl; ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n, p; scanf( %d , &n); scanf( %d , &p); vector<pair<int, int> > ans; int edges = 2 * n + p; for (int i = int(1); i <= int(n); i++) { for (int j = int(i + 1); j <= int(n); j++) { if (edges) { ans.push_back(pair<int, int>(i, j)); edges--; } } } for (vector<pair<int, int> >::iterator it = (ans).begin(); it != (ans).end(); it++) printf( %d %d n , it->first, it->second); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 100, INF = 1e9; struct edge { long long to, cost, id; }; vector<edge> g[N]; long long d[N], cost[N], path[N], used[N]; pair<long long, long long> from[N]; long long n, m; void bfs() { fill(d, d + n, INF); d[0] = 0; queue<long long> q; q.push(0); while ((long long)q.size()) { long long v = q.front(); q.pop(); if (used[v]) continue; used[v] = 1; for (auto i : g[v]) { long long u = i.to; long long c = cost[v] + i.cost; if (d[v] + 1 < d[u] || (d[v] + 1 == d[u] && c < cost[u])) { d[u] = d[v] + 1; from[u] = {v, i.id}; cost[u] = c; q.push(u); } } } long long v = n - 1; while (v != 0) { long long id = from[v].second; path[id] = 1; v = from[v].first; } } signed main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m; vector<pair<pair<long long, long long>, long long>> ed(m); for (long long i = 0; i < m; i++) { long long a, b, c; cin >> a >> b >> c; a--; b--; ed[i] = {{a, b}, c}; c ^= 1; g[a].push_back({b, c, i}); g[b].push_back({a, c, i}); } bfs(); long long ans = 0; for (long long i = 0; i < m; i++) { if (path[i] && ed[i].second == 0 || (!path[i] && ed[i].second == 1)) ans++; } cout << ans << n ; for (long long i = 0; i < m; i++) { if (path[i] && ed[i].second == 0 || (!path[i] && ed[i].second == 1)) cout << ed[i].first.first + 1 << << ed[i].first.second + 1 << << (ed[i].second ^ 1) << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_2_V
`define SKY130_FD_SC_HS__A21BO_2_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_1_V
`define SKY130_FD_SC_MS__MAJ3_1_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__maj3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__maj3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_1_V
|
module ddr3_dma(
input clk,
input rst,
//Write Side
input write_enable,
input [63:0] write_addr,
input write_addr_inc,
input write_addr_dec,
output reg write_finished,
input [23:0] write_count,
input write_flush,
output [1:0] write_ready,
input [1:0] write_activate,
output [23:0] write_size,
input write_strobe,
input [31:0] write_data,
//Read Side
input read_enable,
input [63:0] read_addr,
input read_addr_inc,
input read_addr_dec,
output read_busy,
output read_error,
input [23:0] read_count,
input read_flush,
output read_ready,
input read_activate,
output [23:0] read_size,
output [31:0] read_data,
input read_strobe,
//Local Registers/Wires
output cmd_en,
output [2:0] cmd_instr,
output [5:0] cmd_bl,
output [29:0] cmd_byte_addr,
input cmd_empty,
input cmd_full,
output wr_en,
output [3:0] wr_mask,
output [31:0] wr_data,
input wr_full,
input wr_empty,
input [6:0] wr_count,
input wr_underrun,
input wr_error,
output rd_en,
input [31:0] rd_data,
input rd_full,
input rd_empty,
input [6:0] rd_count,
input rd_overflow,
input rd_error
);
//Local Parameters
//Registers/Wires
reg [23:0] local_write_size;
reg [23:0] local_write_count;
reg prev_edge_write_enable;
wire posedge_write_enable;
wire [27:0] cmd_word_addr;
//Sub Modules
//Submodules
ddr3_controller dc(
.clk (clk ),
.rst (rst ),
.write_en (write_enable ),
.write_address (write_addr[27:0] ),
.read_en (read_enable ),
.read_address (read_addr[27:0] ),
.if_write_strobe (write_strobe ),
.if_write_data (write_data ),
.if_write_ready (write_ready ),
.if_write_activate (write_activate ),
.if_write_fifo_size (write_size ),
//.if_starved (if_starved ),
.of_read_strobe (read_strobe ),
.of_read_ready (read_ready ),
.of_read_activate (read_activate ),
.of_read_size (read_size ),
.of_read_data (read_data ),
.cmd_en (cmd_en ),
.cmd_instr (cmd_instr ),
.cmd_bl (cmd_bl ),
.cmd_word_addr (cmd_word_addr ),
.cmd_empty (cmd_empty ),
.cmd_full (cmd_full ),
.wr_en (wr_en ),
.wr_mask (wr_mask ),
.wr_data (wr_data ),
.wr_full (wr_full ),
.wr_empty (wr_empty ),
.wr_count (wr_count ),
.wr_underrun (wr_underrun ),
.wr_error (wr_error ),
.rd_en (rd_en ),
.rd_data (rd_data ),
.rd_full (rd_full ),
.rd_empty (rd_empty ),
.rd_count (rd_count ),
.rd_overflow (rd_overflow ),
.rd_error (rd_error )
);
//Asynchroous Logic
assign read_busy = read_enable;
assign read_error = 0;
assign posedge_write_enable = !prev_edge_write_enable && write_enable;
assign cmd_byte_addr = {cmd_word_addr, 2'b0};
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
//local_write_size <= 0;
local_write_count <= 0;
write_finished <= 0;
prev_edge_write_enable <= 0;
end
else begin
if (write_count > 0) begin
if (write_strobe) begin
local_write_count <= local_write_count + 1;
end
if (local_write_count >= write_count) begin
write_finished <= 1;
end
end
else begin
write_finished <= 0;
local_write_count <= 0;
end
prev_edge_write_enable <= write_enable;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_SYMBOL_V
`define SKY130_FD_SC_LP__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; vector<bool> visited; vector<vector<int> > adj; void dfs(int node, long long &s0, long long &s1, int mod) { if (mod == 0) s0++; else s1++; visited[node] = true; for (int i = 0; i < adj[node].size(); i++) { if (!visited[adj[node][i]]) { dfs(adj[node][i], s0, s1, (mod + 1) % 2); } } } int main() { int t = 1; while (t--) { int n; cin >> n; adj = vector<vector<int> >(n + 1); visited = vector<bool>(n + 1, false); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } long long s0 = 0, s1 = 0; dfs(1, s0, s1, 0); cout << s0 * s1 - n + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const long long oo = 1e18; const long long mod = 1e9 + 7; const int INF = 1 << 30; vector<pair<pair<int, long long>, int>> adj[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); ios_base::sync_with_stdio(0); int n, m, k; cin >> n >> m >> k; map<pair<int, int>, long long> edges; for (int i = 0; i < m; i++) { int u, v; long long w; cin >> u >> v >> w; edges[{u, v}] = w; adj[u].push_back({{v, w}, 0}); adj[v].push_back({{u, w}, 0}); } int ans = 0; for (int i = 0; i < k; i++) { int s; long long y; cin >> s >> y; adj[1].push_back({{s, y}, 1}); } priority_queue<pair<pair<int, long long>, int>, vector<pair<pair<int, long long>, int>>, greater<pair<pair<int, long long>, int>>> q; long long dis[N]; bool anagetHenaBeTrain[N]; for (int i = 0; i < N; i++) dis[i] = INF; memset(anagetHenaBeTrain, false, sizeof(anagetHenaBeTrain)); dis[1] = 0; q.push({{dis[1], 1}, 0}); while (q.size()) { auto top = q.top(); q.pop(); long long cost = top.first.first; int node = top.first.second; int type = top.second; if (cost > dis[node]) continue; for (auto v : adj[node]) { if (v.first.second + cost < dis[v.first.first]) { dis[v.first.first] = v.first.second + cost; anagetHenaBeTrain[v.first.first] = v.second; q.push({{dis[v.first.first], v.first.first}, v.second}); } else if (v.first.second + cost == dis[v.first.first]) { if (anagetHenaBeTrain[v.first.first] == 1 && v.second == 0) { anagetHenaBeTrain[v.first.first] = 0; } } } } for (int i = 1; i <= n; i++) if (anagetHenaBeTrain[i] == 1) ans++; cout << k - ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(0) * 2; const double EPS = 1e-8; const long long MOD = 1e9 + 7; const int MAXN = 1e5 + 5; const int oo = 1e9; const double foo = 1e30; template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcounll(s); } template <class T> T sqr(T x) { return x * x; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } int d, n, m, vs[MAXN], cnt[4], has[MAXN][4]; vector<pair<int, int> > dX, dY; int main() { cin >> d; cin >> n >> m; for (int i = 0; i < d; i++) { int x, y; cin >> x >> y; dX.push_back(make_pair(x, i)); dY.push_back(make_pair(y, i)); cin >> x >> y; dX.push_back(make_pair(x, i)); dY.push_back(make_pair(y, i)); } for (int i = 0; i < 4; i++) cin >> cnt[i]; sort(dX.begin(), dX.end()); sort(dY.begin(), dY.end()); int pass = 0; memset(vs, 0, sizeof(vs)); int tot = 0; for (int i = 0; i < ((int)(dX).size()); i++) { if (i && dX[i].first != dX[i - 1].first) { tot += pass; pass = 0; } if (!vs[dX[i].second]) { pass++; vs[dX[i].second] = 1; has[dX[i].second][0] = max(has[dX[i].second][0], tot); } else { has[dX[i].second][0] = max(has[dX[i].second][0], tot - 1); } } pass = 0; memset(vs, 0, sizeof(vs)); tot = 0; for (int i = ((int)(dX).size()) - 1; i >= 0; i--) { if (i != ((int)(dX).size()) - 1 && dX[i].first != dX[i + 1].first) { tot += pass; pass = 0; } if (!vs[dX[i].second]) { pass++; vs[dX[i].second] = 1; has[dX[i].second][1] = max(has[dX[i].second][1], tot); } else { has[dX[i].second][1] = max(has[dX[i].second][1], tot - 1); } } pass = 0; memset(vs, 0, sizeof(vs)); tot = 0; for (int i = 0; i < ((int)(dY).size()); i++) { if (i && dY[i].first != dY[i - 1].first) { tot += pass; pass = 0; } if (!vs[dY[i].second]) { pass++; vs[dY[i].second] = 1; has[dY[i].second][2] = max(has[dY[i].second][2], tot); } else { has[dY[i].second][2] = max(has[dY[i].second][2], tot - 1); } } pass = 0; memset(vs, 0, sizeof(vs)); tot = 0; for (int i = ((int)(dY).size()) - 1; i >= 0; i--) { if (i != ((int)(dY).size()) - 1 && dY[i].first != dY[i + 1].first) { tot += pass; pass = 0; } if (!vs[dY[i].second]) { pass++; vs[dY[i].second] = 1; has[dY[i].second][3] = max(has[dY[i].second][3], tot); } else { has[dY[i].second][3] = max(has[dY[i].second][3], tot - 1); } } for (int i = 0; i < d; i++) { int check = 1; for (int j = 0; j < 4; j++) if (has[i][j] != cnt[j]) { check = 0; break; } if (check) { cout << i + 1; return 0; } } cout << -1; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long expr(long long n, long long e) { if (e == 0) return 1; if (e & 1) { return n * expr(n, e ^ 1); } else return expr(n, e >> 1) * expr(n, e >> 1); } int main() { long long n, l, r; scanf( %lld %lld %lld , &n, &l, &r); long long count = 0; long long root = 0.000001 + pow((double)r, 1.0 / ((double)n - 1.0)); if (n == 1) { printf( %lld n , r - l + 1); return 0; } if (n == 2) { printf( %lld n , (r - l + 1) * (r - l)); return 0; }; for (long long i = 1; i <= root; i++) { for (long long j = i + 1; j <= root; j++) { if (gcd(i, j) == 1) { long long maxb = r / expr(j, n - 1); long long minb = ceil((double)l / (double)expr(i, n - 1)); ; count += max(0ll, maxb - minb + 1); } } } printf( %lld n , 2 * count); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); long long int mx = n * n; for (int i = 1, j = mx; i < j; i++, j--) { cout << i << << j << endl; } }
|
#include <bits/stdc++.h> using namespace std; struct { int begin, end; } P1[60], P2[60]; int main() { int num1, num2, first, last; scanf( %d %d %d %d , &num1, &num2, &first, &last); int ans = 0; for (int i = 1; i <= num1; i++) scanf( %d %d , &P1[i].begin, &P1[i].end); for (int i = 1; i <= num2; i++) scanf( %d %d , &P2[i].begin, &P2[i].end); for (int i = first; i <= last; i++) { for (int j1 = 1; j1 <= num1; j1++) { bool flag = 1; for (int j2 = 1; j2 <= num2; j2++) { if ((P2[j2].begin + i >= P1[j1].begin && P2[j2].begin + i <= P1[j1].end) || (P2[j2].end + i >= P1[j1].begin && P2[j2].end + i <= P1[j1].end) || (P2[j2].begin + i <= P1[j1].begin && P2[j2].end + i >= P1[j1].end)) { ans++; flag = 0; break; } } if (!flag) break; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1000004]; int main() { int n, x; long long sum; int cnt; while (scanf( %d , &n) == 1) { sum = 0LL; cnt = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] % 2 == 1) cnt++; sum += a[i]; } if (sum % 2LL == 0LL) { if (cnt % 2 == 0 && cnt > 0) cout << First n ; else cout << Second n ; } else cout << First n ; } }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int n, a[100100], m, x, rs = 1e9; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= m; i++) cin >> x, a[x]++; for (int i = 1; i <= n; i++) rs = min(rs, a[i]); cout << rs; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_1_V
`define SKY130_FD_SC_HD__TAPVGND_1_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog wrapper for tapvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__tapvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tapvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_1_V
|
// File ../../vhdl/src/decoder.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 2001
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
`include "cpu_constants.vh"
`timescale 1ns/1ps
module decoder(
input wire clk,
input wire en,
input wire [15:0] instruction,
output wire [7:0] alu_control,
output wire [2:0] rD_sel,
output wire [2:0] rS_sel,
output wire [15:0] immediate,
output wire en_immediate,
output wire next_word,
output reg en_mem,
output reg mem_displacement,
output reg mem_byte,
output reg lr_is_input,
output reg [3:0] condition
);
reg [7:0] s_alu_control;
reg [2:0] s_rD_sel;
reg [2:0] s_rS_sel;
reg [15:0] s_immediate;
reg s_en_imm;
reg s_next_word;
wire [7:0] opcode;
assign opcode = instruction[15:8];
assign alu_control = s_alu_control;
assign rD_sel = s_rD_sel;
assign rS_sel = s_rS_sel;
assign immediate = s_immediate;
assign en_immediate = s_en_imm;
assign next_word = s_next_word;
always @(posedge clk) begin : P1
if(en == 1'b 1) begin
if((((opcode)) <= ((`OPC_MOVB_R7)) && ((opcode)) >= ((`OPC_MOVB_R0)))) begin
s_en_imm <= 1'b 1;
s_alu_control <= `OPC_MOV;
s_next_word <= 1'b 0;
s_immediate <= {8'h 00,instruction[7:0]};
case(opcode)
`OPC_MOVB_R0 : begin
s_rD_sel <= 3'b 000;
end
`OPC_MOVB_R1 : begin
s_rD_sel <= 3'b 001;
end
`OPC_MOVB_R2 : begin
s_rD_sel <= 3'b 010;
end
`OPC_MOVB_R3 : begin
s_rD_sel <= 3'b 011;
end
`OPC_MOVB_R4 : begin
s_rD_sel <= 3'b 100;
end
`OPC_MOVB_R5 : begin
s_rD_sel <= 3'b 101;
end
`OPC_MOVB_R6 : begin
s_rD_sel <= 3'b 110;
end
`OPC_MOVB_R7 : begin
s_rD_sel <= 3'b 111;
end
default : begin
end
endcase
end
else begin
s_alu_control <= {1'b 0,opcode[6:0]};
s_en_imm <= instruction[15];
s_next_word <= instruction[15];
s_rD_sel <= instruction[2:0];
s_immediate <= 16'h 0000;
if(opcode == `OPC_PUSH || opcode == `OPC_POP ||
opcode == `OPC_PUSHI || opcode == `OPC_PUSHLR) begin
s_rS_sel <= ~instruction[5:3];
//Stack pointer
end
else begin
s_rS_sel <= instruction[5:3];
end
end
if(opcode == `OPC_ST || opcode == `OPC_LD || opcode == `OPC_LDI ||
opcode == `OPC_STI || opcode == `OPC_PUSH || opcode == `OPC_PUSHI ||
opcode == `OPC_POP || opcode == `OPC_PUSHLR) begin
en_mem <= 1'b 1;
if(opcode == `OPC_ST || opcode == `OPC_LD ||
opcode == `OPC_LDI || opcode == `OPC_STI)
mem_byte <= instruction[7];
else
mem_byte <= 0;
end
else begin
mem_byte <= 1'b 0;
en_mem <= 1'b 0;
end
if(opcode == `OPC_LDI || opcode == `OPC_STI) begin
mem_displacement <= instruction[6];
end
else begin
mem_displacement <= 1'b 0;
end
if(opcode == `OPC_SPEC || opcode == `OPC_PUSHLR)
lr_is_input <= 1;
else
lr_is_input <= 0;
if(opcode == `OPC_JMP || opcode == `OPC_JMPI ||
opcode == `OPC_SET || opcode == `OPC_CALL ||
opcode == `OPC_CALLI ) begin
condition <= instruction[6:3];
end
else begin
condition <= 4'b 0000;
end
end
end
`ifdef FORMAL
assume property(en == 1);
reg [15:0] instr_prev = 0;
reg [7:0] opcode_prev = 0;
initial begin
assume(s_alu_control == 0);
assume(s_en_imm == 0);
assume(s_immediate == 0);
assume(opcode_prev == 0);
assume(s_next_word == 0);
end
always @(posedge clk) begin
instr_prev <= instruction;
opcode_prev <= opcode;
if(opcode_prev == `OPC_ADD) begin
assert(s_en_imm == 0);
assert(s_alu_control == `OPC_ADD);
end
if(opcode_prev[7] == 1) begin
assert(s_en_imm == 1);
assert(s_next_word == 1);
end
else if(opcode_prev >= `OPC_MOVB_R0 && opcode_prev <= `OPC_MOVB_R7) begin
assert(s_en_imm == 1);
assert(s_next_word == 0);
end
else if(opcode_prev[7] == 0) begin
assert(s_en_imm == 0);
assert(s_next_word == 0);
end
end
`endif
`ifdef FORMAL
initial begin
assume(instruction == 0);
assume(s_rD_sel == 0);
assume(s_rS_sel == 0);
end
always @(posedge clk) begin
if($initstate) begin
assume($past(instruction) == 0);
assume($past(opcode) == 0);
end
else begin
if($past(opcode) & 8'h80)
assert(s_next_word == 1);
else
assert(s_next_word == 0);
if($past(opcode) >= `OPC_MOVB_R0 && opcode_prev <= `OPC_MOVB_R7) begin
assert(s_next_word == 0);
assert(s_en_imm == 1);
assert(s_rD_sel == ($past(opcode) - `OPC_MOVB_R0 & 3'b111));
assert(s_immediate == ($past(instruction) & 8'hff));
end
else begin
assert(s_alu_control == ($past(opcode) & 8'h7f));
assert(s_rD_sel == ($past(instruction) & 3'b111));
if($past(opcode) != `OPC_PUSH && $past(opcode) != `OPC_POP &&
$past(opcode) != `OPC_PUSHI && $past(opcode) != `OPC_PUSHLR)
assert(s_rS_sel == (($past(instruction) & 6'b111000) >> 3));
else
assert(s_rS_sel == 3'b111);
end
if($past(opcode) == `OPC_SPEC) begin
assert (lr_is_input == 1);
end
end
end
`endif
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// This module facilitates a transition between two clock domains. We assume that the input
// is provided in the clock2x domain serially and is to be provided as a double-data element in
// the clock domain.
//
///////////////////////////////////////////////////////////////////////////////////////////////////
module acl_stream_to_vector_converter(
clock, clock2x, resetn,
dataa, y1, y2,
valid_in, valid_out, stall_in, stall_out);
parameter WIDTH = 32;
input clock, clock2x, resetn, valid_in, stall_in;
input [WIDTH-1:0] dataa;
output [WIDTH-1:0] y1;
output [WIDTH-1:0] y2;
output valid_out;
output stall_out;
// Add staging register at the input.
reg [WIDTH-1:0] dataa_sr /* synthesis preserve */;
reg sr_in_valid;
wire stall_sr;
always@(posedge clock2x or negedge resetn)
begin
if(~resetn)
begin
sr_in_valid <= 1'b0;
dataa_sr <= {WIDTH{1'bx}};
end
else
begin
if (~stall_sr)
sr_in_valid <= 1'b0;
else if (~sr_in_valid)
sr_in_valid <= valid_in;
if (~sr_in_valid)
dataa_sr <= dataa;
end
end
assign stall_out = sr_in_valid;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg sel, sel_ref /* synthesis preserve */;
initial
begin
sel = 1'b0;
sel_ref = 1'b0;
end
always@(posedge clock2x)
begin
sel <= ~sel;
end
// Register the data in the 'clock2x' domain.
reg [WIDTH-1:0] in_a2 /* synthesis preserve */;
reg [WIDTH-1:0] in_a1 /* synthesis preserve */;
reg valid_a2, valid_a1 /* synthesis preserve */;
wire stall_shift;
always@(posedge clock2x or negedge resetn)
begin
if (~resetn)
begin
valid_a2 <= 1'b0;
valid_a1 <= 1'b0;
in_a1 <= {WIDTH{1'bx}};
in_a2 <= {WIDTH{1'bx}};
end
else
begin
if (~valid_a2)
begin
valid_a2 <= sr_in_valid | valid_in;
in_a2 <= sr_in_valid ? dataa_sr : dataa;
valid_a1 <= 1'b0;
end
else if ((~valid_a1) & (sr_in_valid | valid_in))
begin
valid_a2 <= 1'b1;
in_a2 <= sr_in_valid ? dataa_sr : dataa;
valid_a1 <= valid_a2;
in_a1 <= in_a2;
end
else if (valid_a1 & valid_a2 & ~stall_shift)
begin
valid_a2 <= sr_in_valid | valid_in;
in_a2 <= sr_in_valid ? dataa_sr : dataa;
valid_a1 <= 1'b0;
end
end
end
assign stall_sr = valid_a1 & stall_shift;
reg [WIDTH-1:0] y2_r /* synthesis preserve */;
reg [WIDTH-1:0] y1_r /* synthesis preserve */;
reg valid_crossing /* synthesis preserve */;
wire stall_last;
wire w = (sel_ref == sel); // = 1 when just prior to positive edge of 'clock'
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
sel_ref <= 1'b0;
valid_crossing <= 1'b0;
y1_r <= {WIDTH{1'bx}};
y2_r <= {WIDTH{1'bx}};
end
else
begin
if (~valid_crossing | ~stall_last)
begin
y1_r <= in_a1;
y2_r <= in_a2;
valid_crossing <= valid_a1;
end
sel_ref <= sel;
end
end
assign stall_shift = ~w | valid_crossing & stall_last;
// Staging register
reg valid_out_sr;
reg [WIDTH-1:0] y1_sr /* synthesis preserve */;
reg [WIDTH-1:0] y2_sr /* synthesis preserve */;
assign stall_last = valid_out_sr;
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
valid_out_sr <= 1'b0;
y1_sr <= {WIDTH{1'bx}};
y2_sr <= {WIDTH{1'bx}};
end
else
begin
if (~stall_in)
valid_out_sr <= 1'b0;
else if (~valid_out_sr)
valid_out_sr <= valid_crossing;
if (~valid_out_sr)
begin
y1_sr <= y1_r;
y2_sr <= y2_r;
end
end
end
assign y1 = valid_out_sr ? y1_sr : y1_r;
assign y2 = valid_out_sr ? y2_sr : y2_r;
assign valid_out = valid_out_sr | valid_crossing;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = ~0U >> 1; const long long INF = (long long)1e18; const double pi = acos(-1.0); template <class T> inline T sqr(T a) { return a * a; } template <class T> inline T min(T a, T b, T c) { return min(min(a, b), c); } template <class T> inline T max(T a, T b, T c) { return max(max(a, b), c); } template <class T> inline void read(T &n) { char c; for (c = getchar(); !(c >= 0 && c <= 9 ); c = getchar()) ; n = c - 0 ; for (c = getchar(); c >= 0 && c <= 9 ; c = getchar()) n = n * 10 + c - 0 ; } int pw(int base, int n, int mo) { if (n == 0) return 1; if (n == 1) return base; int tmp = pw(base, n >> 1, mo); tmp = (long long)tmp * tmp % mo; if (n & 1) tmp = (long long)tmp * base % mo; return tmp; } const int maxn = 200000; int N, M, x, y, p[maxn], c[maxn], f[maxn], s[maxn]; long long ans; bool cmp(const int &a, const int &b) { return c[a] > c[b]; } vector<int> E[maxn]; int find(int x) { if (f[x] == x) return x; int t = find(f[x]); s[x] += s[f[x]]; return f[x] = t; } int main() { scanf( %d%d , &N, &M); for (int i = (1); i <= (N); ++i) scanf( %d , &c[i]); for (int i = (1); i <= (M); ++i) { scanf( %d%d , &x, &y); if (c[x] < c[y]) E[x].push_back(y); else E[y].push_back(x); } for (int i = (1); i <= (N); ++i) p[i] = i; sort(p + 1, p + N + 1, cmp); for (int i = (1); i <= (N); ++i) f[i] = i, s[i] = 1; for (int i = (1); i <= (N); ++i) { int S = p[i]; for (int j = 0; j < E[S].size(); ++j) { int x = find(S), y = find(E[S][j]); if (x != y) { ans += (long long)c[S] * s[x] * s[y]; f[x] = y; s[y] += s[x]; } } } double ret = ans * 2. / N / (N - 1); printf( %.10lf n , ret); return 0; }
|
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/11/2016
Founction: Send out capture value
Note:
****************************************************************************/
module captuer_tx(
clk,rst_n,tx_start,capture_ready,periodcounter,dutycyclecounter,tx_data,tx_complete,capture_tx_rst,tx_end,bps_start_t
);
input clk;
input rst_n;
input capture_ready;
input tx_complete;
input bps_start_t;
input capture_tx_rst;
input[31:0] periodcounter;
input[31:0] dutycyclecounter;
output tx_start;
output tx_end;
output [7:0] tx_data;
reg tx_start;
reg[15:0] tx_counter;
reg[3:0] tx_count;
reg[7:0] tx_data;
reg tx_end;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end
else if(capture_ready && (tx_counter >'d600))begin
case(tx_count)
4'b0000:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= periodcounter[7:0];
end
4'b0001:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= periodcounter[15:8];
end
4'b0010:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= periodcounter[23:16];
end
4'b0011:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= periodcounter[31:24];
end
4'b0100:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= dutycyclecounter[7:0];
end
4'b0101:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= dutycyclecounter[15:8];
end
4'b0110:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= dutycyclecounter[23:16];
end
4'b0111:begin
tx_start <= tx_start ? 1'b0:1'b1;
tx_data <= dutycyclecounter[31:24];
end
default:begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end
endcase
end
end
always @ (posedge tx_complete or negedge capture_tx_rst) begin
if (!capture_tx_rst)begin
tx_count <= 'h0;
tx_end <= 'h0;
end
else if(tx_complete && (tx_count<7)&&capture_ready)begin
tx_count <= tx_count + 1'b1;
end
else begin
tx_end <= 'h1;
end
end
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)begin
tx_counter <= 'h0;
end
else if(!bps_start_t)begin
tx_counter <= tx_counter + 1'b1;
end
else begin
tx_counter <= 'h0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> Left; vector<int> Right; map<pair<int, int>, int> excep; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(); cin >> n; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; Left.push_back(l); Right.push_back(r); excep[{l, r}] = 1; } sort(Left.begin(), Left.end(), greater<int>()); sort(Right.begin(), Right.end()); if (excep[{Left[0], Right[0]}] == 1) cout << max(0, Right[1] - Left[1]); else cout << max(0, max(Right[0] - Left[1], Right[1] - Left[0])); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/13/2015 09:44:53 AM
// Design Name:
// Module Name: SD_Card_Interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SD_Card_Interface(
input Clock, //200MHz
input Reset, //Active-High
input [7:0] Data_in,
input Write_in, //Active-High
input Clock_Speed, // 0 = 400KHz, 1 = 25MHz
output [7:0] Data_out,
output Data_Send_Complete,
output SD_Clock,
input MISO,
output MOSI);
SD_Clock_Gen ClockGen(
.clk (Clock),
.select (Clock_Speed),
.clock (SD_Clock));
SD_Out_FIFO_Wrapper Outgoing(
.clk (SD_Clock),
.srst (Reset),
.din (Data_in),
.wr_en (Write_in),
.dout (MOSI),
.empty (Data_Send_Complete));
SD_In_ShiftRegister Incoming(
.clk (SD_Clock),
.srst (Reset),
.din (MISO),
.dout (Data_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int N = 1e7 + 5; const long long INF = 9e18; const int M = 1e5 + 5; map<long long, vector<int> > f; long long p[N], ans1[M], a[M]; void solve() { for (int i = 2; i <= N; ++i) { if (i % 2 == 0) { p[i] = 2; continue; } if (p[i]) continue; p[i] = i; for (int j = i * 2; j <= N; j += i) { if (!p[j]) p[j] = i; } } int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) { long long x; cin >> x; a[i] = x; while (x > 1) { long long y = p[x]; while (x > 1 && x % y == 0) { f[y].push_back(i); x /= y; } } } for (int i = 1; i <= m; ++i) { ans1[i] = 1; long long x; cin >> x; while (x > 1) { long long y = p[x]; while (x > 1 && x % y == 0) { if ((int)f[y].size()) { a[f[y].back()] /= y; f[y].pop_back(); } else ans1[i] *= y; x /= y; } } } cout << n << << m << n ; for (int i = 1; i <= n; ++i) { cout << a[i] << ; } cout << n ; for (int i = 1; i <= m; ++i) { cout << ans1[i] << ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; vector<int> g[N]; void dfs(int u, vector<int>& dep, int par = -1, int h = 0) { dep[u] = h; for (int v : g[u]) { if (v == par) continue; dfs(v, dep, u, h + 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, x; cin >> n >> x; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } vector<int> dep_r(n + 1); vector<int> dep_x(n + 1); dfs(1, dep_r); dfs(x, dep_x); int mx = -1; for (int i = 1; i <= n; i++) { if (dep_x[i] < dep_r[i]) { mx = max(mx, dep_r[i] << 1); } } cout << mx << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_2_V
`define SKY130_FD_SC_LP__CLKBUFLP_2_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog wrapper for clkbuflp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuflp_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuflp_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_2_V
|
#include <bits/stdc++.h> using namespace std; long long nb, ns, nc, pb, ps, pc, ab, as, ac, money; bool solve(long long k) { long long cb = k * ab, cs = k * as, cc = k * ac; long long cost = 0; cost += max(cb - nb, 0LL) * pb; cost += max(cs - ns, 0LL) * ps; cost += max(cc - nc, 0LL) * pc; return cost <= money; } int main() { ios_base::sync_with_stdio(false); string s; cin >> s; for (int i = 0; i < s.size(); ++i) if (s[i] == B ) ab++; else if (s[i] == S ) as++; else ac++; cin >> nb >> ns >> nc >> pb >> ps >> pc; cin >> money; long long lo = 0, hi = 1e14, mid; while (lo < hi) { mid = (lo + hi + 1) / 2; if (solve(mid)) lo = mid; else hi = mid - 1; } cout << lo << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> int main() { long long int t, i = 0; long long ans = 0; scanf( %lld , &t); for (i = 0; i < t; i++) { long long int n; scanf( %lld , &n); ans = ans + i * (n - 1) + n; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; class UFDS { public: vector<int> p, rank; int count = 0; UFDS(int n) { p.resize(n); rank.resize(n); for (int i = 0; i < n; i++) p[i] = i; count = n; } int getParent(int i) { return (p[i] == i) ? i : (p[i] = getParent(p[i])); } void join(int i, int j) { int a = getParent(i), b = getParent(j); if (a == b) return; count -= 1; if (rank[a] > rank[b]) { p[b] = a; } else { p[a] = b; if (rank[a] == rank[b]) rank[b] += 1; } } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; set<int> ls, rss; vector<int> rs; vector<vector<int> > edges(m, vector<int>(4)); for (int i = 0; i < m; i++) { cin >> edges[i][2] >> edges[i][3] >> edges[i][0] >> edges[i][1]; ls.insert(edges[i][0]); if (!rss.count(edges[i][1])) { rss.insert(edges[i][1]); rs.push_back(edges[i][1]); } edges[i][2] -= 1; edges[i][3] -= 1; } sort(rs.begin(), rs.end()); sort(edges.begin(), edges.end()); int out = 0, prev = 0; for (auto l : ls) { int lo = prev, hi = rss.size(), ans = -1; while (lo < hi) { int idx = (lo + hi) / 2; int mid = rs[idx]; UFDS ufds(n); for (auto e : edges) { if (e[0] > l) break; if (e[1] >= mid) ufds.join(e[2], e[3]); } if (ufds.getParent(0) == ufds.getParent(n - 1)) { lo = idx + 1; ans = mid; prev = idx; } else { hi = idx; } } if (ans != -1) out = max(out, ans - l + 1); } if (out) cout << out; else cout << Nice work, Dima! ; cout << endl; return 0; }
|
`timescale 1ps/1ps
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______183.967____177.296
// CLK_OUT2___200.000______0.000______50.0______161.043____177.296
// CLK_OUT3___400.000______0.000______50.0______140.976____177.296
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000___________0.0005
//----------------------------------------------------------------------------
module pll_vfb6_400 ( CLKIN,
CLK1,
CLK2,
CLK4 );
input wire CLKIN;
output wire CLK1;
output wire CLK2;
output wire CLK4;
wire clkin1;
wire clkout0;
wire clkout1;
wire clkout2;
// input buffering
//------------------------------------
IBUFG clkin1_buf (
.O (clkin1),
.I (CLKIN));
wire locked;
wire clkfbout;
wire clkfbout_buf;
wire clkout3;
wire clkout4;
wire clkout5;
PLL_BASE
#(.BANDWIDTH ("HIGH"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (8),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (4),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (2),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (10.000),
.REF_JITTER (0.001))
pll_base_inst (
.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4),
.CLKOUT5 (clkout5),
.LOCKED (locked),
.RST (1'b0),
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// output buffering
//-----------------------------------
BUFG clkf_buf (
.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf (
.O (CLK1),
.I (clkout0));
BUFG clkout2_buf (
.O (CLK2),
.I (clkout1));
BUFG clkout3_buf (
.O (CLK4),
.I (clkout2));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[110][110]; int n, i, j; long long s = 0; cin >> n; if (n == 1) { cin >> i; cout << i; return 0; } for (i = 0; i < n; ++i) for (j = 0; j < n; ++j) { cin >> a[i][j]; if (i == j) s += a[i][j]; if (i + j == n - 1) s += a[i][j]; if (i == (n - 1) / 2 || j == (n - 1) / 2) s += a[i][j]; } cout << s - 2 * a[(n - 1) / 2][(n - 1) / 2]; return 0; }
|
#include <bits/stdc++.h> const int maxn = 2005; const int inf = 1e9; using namespace std; vector<pair<int, int>> G[maxn]; vector<int> C[maxn], v; bool critical[maxn * maxn]; vector<int> seen, sum, col, depth, up; void dfs(int node, int ind) { seen[node] = 1; int minFromSons = inf; up[node] = depth[node]; for (auto tmp : G[node]) { if (seen[tmp.first] && tmp.second != ind) up[node] = min(up[node], depth[tmp.first]); else if (!seen[tmp.first]) { depth[tmp.first] = depth[node] + 1; dfs(tmp.first, tmp.second); minFromSons = min(minFromSons, up[tmp.first]); } } up[node] = min(up[node], minFromSons); if (minFromSons >= depth[node] && ind != -1) { critical[ind] = 1; } } void dfsColor(int node, int color) { col[node] = color; v[color]++; for (auto tmp : G[node]) { if (critical[tmp.second] == 1 && col[tmp.first] == 0) continue; if (critical[tmp.second] == 1 && col[tmp.first]) { C[col[tmp.first]].push_back(color); C[color].push_back(col[tmp.first]); continue; } else if (col[tmp.first] == 0) dfsColor(tmp.first, color); } } void dfsSub(int node) { seen[node] = 1; sum[node] = v[node]; for (auto tmp : C[node]) if (!seen[tmp]) { dfsSub(tmp); sum[node] += sum[tmp]; } } int main() { ios_base ::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; G[a].push_back(make_pair(b, i)); G[b].push_back(make_pair(a, i)); } seen = vector<int>(n + 1, 0); depth = vector<int>(n + 1, 0); up = vector<int>(n + 1, 0); dfs(1, -1); int c = 0; col = vector<int>(n + 1, 0); v = vector<int>(n + 1, 0); int all = 0; for (int i = 1; i <= n; ++i) if (col[i] == 0) { ++c; dfsColor(i, c); all += v[c] * v[c]; } int ans = 0; for (int i = 1; i <= c; ++i) { seen = vector<int>(c + 1, 0); sum = vector<int>(c + 1, 0); dfsSub(i); int tmp = 0; for (int j = 1; j <= c; ++j) tmp += sum[j] * v[j]; vector<int> can(n + 1, 0); can[0] = 1; for (auto tmp : C[i]) { for (int j = n; j >= 0; --j) if (can[j] && j + sum[tmp] <= n) can[j + sum[tmp]] = 1; } int res = -1; for (int j = (n - v[i]) / 2; j >= 0; --j) if (can[j]) { res = j; break; } tmp += res * (n - v[i] - res); ans = max(ans, tmp); } cerr << all << n ; cout << ans << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_2_V
`define SKY130_FD_SC_HS__A2111OI_2_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111oi_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_dtl_uprcn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_dtl_uprcn(si_l ,so_l ,pad ,sclk ,vddo ,cbu ,above ,
clk ,se ,global_reset_n );
input [8:1] cbu ;
output so_l ;
output pad ;
output above ;
input si_l ;
input sclk ;
input vddo ;
input clk ;
input se ;
input global_reset_n ;
supply1 vdd ;
supply0 vss ;
wire net093 ;
wire net0103 ;
wire sclk1 ;
wire sclk2 ;
wire srcv ;
wire net0153 ;
wire bsr_dn_l ;
wire si ;
wire scan1 ;
wire net0130 ;
wire net0135 ;
wire net0139 ;
wire net051 ;
wire net056 ;
wire net059 ;
wire net062 ;
wire bsr_dn25_l ;
wire net067 ;
wire bsr_up ;
wire net073 ;
wire net0125 ;
wire net0126 ;
wire net0127 ;
wire net0129 ;
wire abvref ;
bw_io_dtl_drv_zctl I227 (
.cbu ({cbu } ),
.cbd ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.pad (pad ),
.sel_data_n (vss ),
.pad_up (net0135 ),
.pad_dn_l (net0125 ),
.pad_dn25_l (net0126 ),
.por (net0139 ),
.bsr_up (bsr_up ),
.bsr_dn_l (bsr_dn_l ),
.bsr_dn25_l (bsr_dn25_l ),
.vddo (vddo ) );
bw_io_dtlhstl_rcv I1 (
.out (abvref ),
.so (srcv ),
.pad (net0103 ),
.ref (net067 ),
.clk (clk ),
.pad_clk_en_l (net0127 ),
.cmsi_clk_en_l (net0153 ),
.cmsi_l (net0129 ),
.se_buf (net0130 ),
.vddo (vddo ) );
bw_u1_soff_4x I257 (
.q (sclk1 ),
.so (net093 ),
.ck (clk ),
.d (sclk ),
.se (se ),
.sd (srcv ) );
bw_u1_soffr_4x I260 (
.q (sclk2 ),
.so (scan1 ),
.ck (clk ),
.d (sclk1 ),
.se (se ),
.sd (net093 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I263 (
.q (above ),
.so (net073 ),
.ck (clk ),
.d (net062 ),
.se (se ),
.sd (scan1 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I268 (
.z (net051 ),
.a (sclk2 ) );
bw_u1_nand2_4x I269 (
.z (net062 ),
.a (net056 ),
.b (net059 ) );
bw_u1_nand2_4x I270 (
.z (net059 ),
.a (net051 ),
.b (above ) );
bw_u1_nand2_4x I271 (
.z (net056 ),
.a (abvref ),
.b (sclk2 ) );
bw_u1_inv_4x I304 (
.z (si ),
.a (si_l ) );
bw_u1_inv_4x I305 (
.z (so_l ),
.a (net073 ) );
bw_io_dtl_edgelogic I306 (
.pad_clk_en_l (net0127 ),
.cmsi_clk_en_l (net0153 ),
.bsr_dn25_l (bsr_dn25_l ),
.pad_dn_l (net0125 ),
.pad_dn25_l (net0126 ),
.bsr_up (bsr_up ),
.bsr_mode (vss ),
.bsr_data_to_core (vss ),
.por_l (vdd ),
.bsr_dn_l (bsr_dn_l ),
.se_buf (net0130 ),
.cmsi_l (net0129 ),
.por (net0139 ),
.reset_l (vdd ),
.sel_bypass (vss ),
.up_open (vss ),
.oe (vdd ),
.down_25 (vss ),
.clk (clk ),
.data (vdd ),
.se (se ),
.si (si ),
.pad_up (net0135 ) );
bw_io_ic_filter I310 (
.torcvr (net0103 ),
.topad (pad ),
.vddo (vddo ) );
bw_io_dtl_vref I313 (
.vref_impctl (net067 ),
.vddo (vddo ) );
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:21:59 11/06/2014
// Design Name: one_bit_adder_gate
// Module Name: /home/varun/Desktop/eld/ass9/fouraddergate/one_bit_adder_fixture.v
// Project Name: fouraddergate
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: one_bit_adder_gate
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module one_bit_adder_fixture;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire q;
wire cout;
// Instantiate the Unit Under Test (UUT)
one_bit_adder_gate uut (
.q(q),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, len; long long a, b, c, l; void solve() { long long tot = ((l + 3) * (l + 2) * (l + 1)) / 6; long long i; for (i = 0; i <= l; i++) { long long x = min(a - b - c + i, l - i); if (x < 0) continue; tot -= ((x + 2) * (x + 1)) >> 1; } for (i = 0; i <= l; i++) { long long x = min(b - a - c + i, l - i); if (x < 0) continue; tot -= ((x + 2) * (x + 1)) >> 1; } for (i = 0; i <= l; i++) { long long x = min(c - a - b + i, l - i); if (x < 0) continue; tot -= ((x + 2) * (x + 1)) >> 1; } cout << tot << n ; } int main() { long long i, j, k, t; ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> a >> b >> c >> l; solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[55]; long long int C[55][55]; double dp[55][55][55]; void precompute(int N) { for (int i = 0; i <= N; ++i) C[i][0] = 1; for (int i = 1; i <= N; ++i) for (int j = 1; j <= i; ++j) C[i][j] = C[i - 1][j] + C[i - 1][j - 1]; } double func(int n, int m, int q) { if (dp[n][m][q] >= 0.0) return dp[n][m][q]; dp[n][m][q] = 0; for (int t = 0; t <= n; t++) { dp[n][m][q] += (pow(1.0 / m, t) * pow(1.0 - 1.0 / m, n - t) * C[n][t] * func(n - t, m - 1, max(q, (t + (a[m] - 1)) / a[m]))); } return dp[n][m][q]; } int main() { int j, k, i, n, m; cin >> n >> m; precompute(n); for (i = 1; i <= m; i++) cin >> a[i]; for (int i = 0; i <= n; ++i) for (int j = 0; j <= m; ++j) for (int k = 0; k <= n; ++k) dp[i][j][k] = -1; for (j = 0; j <= m; j++) { for (k = 0; k <= n; k++) dp[0][j][k] = k; } for (i = 1; i <= n; i++) for (k = 0; k <= n; k++) dp[i][0][k] = 0; printf( %.15lf n , func(n, m, 0)); }
|
#include <bits/stdc++.h> using namespace std; int n, m, c[105]; int sum[105][10005], h[105][10005], f[105][10005]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &c[i]); sum[i][0] = 0; for (int j = 1; j <= c[i]; j++) { int x; scanf( %d , &x); sum[i][j] = sum[i][j - 1] + x; } for (int j = 1; j <= c[i]; j++) for (int k = 0; k <= j; k++) h[i][j] = max(h[i][j], sum[i][k] + sum[i][c[i]] - sum[i][c[i] - j + k]); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) for (int k = 0; k <= min(j, c[i]); k++) f[i][j] = max(f[i][j], f[i - 1][j - k] + h[i][k]); printf( %d n , f[n][m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1100010; const double pai = acos(-1.0); char s[maxn], t[maxn]; int n, m, a[maxn], b[maxn], ans[maxn], fa[maxn][6], rev[maxn], bin[1100010]; struct node { double a, b; node(double t0 = 0.0, double t1 = 0.0) { a = t0; b = t1; } } A[maxn], B[maxn]; node operator+(node a, node b) { node c; c.a = a.a + b.a; c.b = a.b + b.b; return c; } node operator-(node a, node b) { node c; c.a = a.a - b.a; c.b = a.b - b.b; return c; } node operator*(node a, node b) { node c; c.a = a.a * b.a - a.b * b.b; c.b = a.b * b.a + a.a * b.b; return c; } void FFT(node *t, int n, int id) { int len = bin[n]; for (int i = 0; i < n; i++) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (len - 1)); for (int i = 0; i < n; i++) if (i < rev[i]) swap(t[i], t[rev[i]]); for (int i = 1; i < n; i <<= 1) { node Wn; Wn.a = cos(pai / i); Wn.b = id * sin(pai / i); for (int j = 0; j < n; j += (i << 1)) { node W; W.a = 1; W.b = 0; for (int k = j; k < j + i; k++) { node t1 = t[k], t2 = t[k + i] * W; t[k] = t1 + t2; t[k + i] = t1 - t2; W = W * Wn; } } } } int find(int *f, int x) { if (f[x] == x) return x; return f[x] = find(f, f[x]); } void solve(int x, int y) { int len = 1; while (len <= 2 * (n + m)) len <<= 1; for (int i = 0; i < len; i++) A[i].a = A[i].b = B[i].a = B[i].b = 0; for (int i = 0; i < n; i++) if (s[i] - a == x) A[i].a = 1; for (int i = 0; i < m; i++) if (t[i] - a == y) B[i].a = 1; reverse(B, B + m); FFT(A, len, 1), FFT(B, len, 1); for (int i = 0; i < len; i++) A[i] = A[i] * B[i]; FFT(A, len, -1); for (int i = m - 1; i < n; i++) { int temp = (int)(A[i].a / len + 0.5); if (!temp) continue; if (find(fa[i], x) != find(fa[i], y)) { fa[i][fa[i][x]] = fa[i][y]; ans[i]++; } } } int main() { for (int i = 0; i <= 20; i++) bin[1 << i] = i; scanf( %s , s); scanf( %s , t); n = strlen(s); m = strlen(t); for (int i = 0; i < n; i++) for (int j = 0; j < 6; j++) fa[i][j] = j; for (int i = 0; i < 6; i++) for (int j = 0; j < 6; j++) if (i != j) solve(i, j); for (int i = m - 1; i < n; i++) printf( %d , ans[i]); return 0; }
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=10 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=5 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=comm_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_comm_pll_comm_pll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module comm_pll_altpll1
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 10,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 5,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 1,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //comm_pll_altpll1
//VALID FILE
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:dragster_configurator:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_dragster_configurator_0_0 (
clk,
reset_n,
miso,
mosi,
sclk,
ss_n
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset_n RST" *)
input wire reset_n;
input wire miso;
output wire mosi;
output wire sclk;
output wire [1 : 0] ss_n;
dragster_configurator inst (
.clk(clk),
.reset_n(reset_n),
.miso(miso),
.mosi(mosi),
.sclk(sclk),
.ss_n(ss_n)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x; int a[2] = {0}; char c; while (scanf( %c , &c) != -1) { a[c - x ]++; } if (a[0] > a[1]) { x = a[0] - a[1]; for (int i = 0; i < x; i++) { printf( %c , x ); } printf( n ); } else { x = a[1] - a[0]; for (int i = 0; i < x; i++) { printf( %c , y ); } printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_2_V
`define SKY130_FD_SC_LS__O221AI_2_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221ai_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_2_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mmio_if_pio_1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, oo = 0x3f3f3f3f; const long long M = 1e12 + 105; int dx[] = {1, 0, -1, 0}; int dy[] = {0, -1, 0, 1}; int main() { int c, r, ans = 0; scanf( %d %d , &r, &c); char second[r][c]; for (int i = 0; i < r; i++) scanf( %s , second[i]); for (int i = 0; i < r; i++) { int cc = 0; for (int j = 0; j < c; j++) if (second[i][j] == S ) break; else if (second[i][j] == . ) cc++; if (cc == c) { ans += cc; for (int j = 0; j < c; j++) second[i][j] = X ; } } for (int i = 0; i < c; i++) { bool ff = false; int cc = 0; for (int j = 0; j < r; j++) if (second[j][i] == S ) { ff = true; break; } else if (second[j][i] == . ) cc++, second[j][i] = X ; if (!ff) ans += cc; } printf( %d n , ans); return 0; }
|
module main;
reg [7:0] data_i;
reg [2:0] addr;
reg clk, rst, wr;
reg [7:0] data_o, buff[0:7];
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
begin
if (rst)
data_o <= 8'h0;
else if (wr) begin
buff[addr] <= data_i;
data_o <= data_i;
end else
data_o <= buff[addr];
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
rst = 1;
wr = 1;
addr = 0;
data_i = 8'hff;
#1 clk = 1;
#1 clk = 0;
if (data_o !== 8'h00) begin
$display("FAILED -- reset data_o=%b", data_o);
$finish;
end
rst = 0;
wr = 1;
for (addr = 0; addr < 7; addr = addr+1) begin
data_i = addr;
#1 clk = 1;
#1 clk = 0;
if (data_o !== data_i) begin
$display("FAILED -- write data_i=%h, data_o=%h", data_i, data_o);
$finish;
end
end
wr = 0;
data_i = 8'hff;
for (addr = 0 ; addr < 7; addr = addr+1) begin
#1 clk = 1;
#1 clk = 0;
if (data_o !== {5'b00000, addr}) begin
$display("FAILED -- read addr=%h, data_o=%h", addr, data_o);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
// SNES-Hook - A tiny 5V CPLD device to hijack reset on the SNES console
//
// Copyright (C) 2015 Evan Custodio
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////////
//
// Project Name: SNES-Hook
// Author: Evan Custodio (@defparam)
//
// Module Name: snes_bus_sync (Verilog)
//
// Interfaces: (1) SNES raw address bus and read/write enable signals
// (2) Synced address bus and databus outputs
// (3) Synced latch event signal during an address bus change
//
// Clock Domains: (1) 40 MHz (clk) - sourced on board clock
// (2) async RAW snes ports, (typically switches around 2MHz - 3MHz)
//
// Description: A bus access is defined as an SNES access to the address A bus.
// The difference here between this module and the port sync module is that the port
// sync module has read and write enable signals to help realize the bus access. This
// module just observe the address bus for "address switches". Once this module synchronizes
// an address bus "switch" then logic in the 40Mhz domain can safely analyse Address A bus
// accesses. We use this in SNES-Tap to help locate when the processor accesses the reset vector
// and the NMI vector.
module snes_bus_sync (
input clk, // clock (40 MHz and reset)
input rst_n,
input [7:0] PA, // RAW SNES addr bus
output event_latch // Bus change event (detects changes in PA)
);
parameter OUT_OF_SYNC = 1'b1;
parameter IN_SYNC = 1'b0;
reg [7:0] PA_store [0:1];
reg sync_state = IN_SYNC;
reg bus_latch = 0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
PA_store[0] <= 8'b0; // reset all regs
PA_store[1] <= 8'b0;
bus_latch <= 1'b0;
sync_state <= IN_SYNC;
end
else begin
PA_store[0] <= PA; // These registers are used for both metastability protection
PA_store[1] <= PA_store[0]; // and for address bus "change" detection (3 stages)
if (sync_state == IN_SYNC) begin // IN_SYNC state means the bus has settled and events/outputs have been reported
// The addr bus has been pipelined for 3 stages, move into the OUT_OF_SYNC state once a change in addr is detected
// we also ignore this check if 5 cycles haven't gone by on the previous check
if (((PA != PA_store[0]) || (PA_store[1] != PA_store[0]))) begin
sync_state <= OUT_OF_SYNC; // go to OUT_OF_SYNC
bus_latch <= 0; // initialize
end
end else if (sync_state == OUT_OF_SYNC) begin
bus_latch <= 0;
// The addr bus has under gone a change, detect when it has settled and move back into IN_SYNC
if ((PA == PA_store[0]) && (PA_store[1] == PA_store[0])) begin
bus_latch <= 1;
sync_state <= IN_SYNC;
end
end
end
end
// Report back safe synchronized bus events and data/addr
assign event_latch = bus_latch;
endmodule
// synopsys translate off
`timescale 1ns / 100ps
module snes_bus_sync_test ();
reg clk = 0;
reg cycle_clk = 0;
reg rst_n = 0;
reg [7:0] PA = 0;
reg [7:0] D = 0;
wire [7:0] PA_sync;
wire [7:0] D_sync;
wire event_latch;
reg PARD_n = 1;
snes_bus_sync bs (
.clk(clk), // clock (40 MHz and reset)
.rst_n(rst_n),
.PA(PA), // RAW SNES addr bus
.event_latch(event_latch) // Bus change event (detects changes in PA)
);
always #14.3 clk = ~clk;
always #139.6 cycle_clk = ~cycle_clk;
initial #1000 rst_n = 1;
always @(posedge cycle_clk) begin
if (PARD_n) PARD_n = $random % 2;
else PARD_n = 1;
D = $random; #2;
D = $random; #2;
D = $random; #2;
D = $random; #2;
D = $random; #2;
end
always @(posedge cycle_clk) begin
PA = $random; #2;
PA = $random; #2;
PA = $random; #2;
PA = $random; #2;
PA = $random; #2;
end
endmodule
// synopsys translate on
|
#include <bits/stdc++.h> using namespace std; const int N = 100009; int n; long long a[N]; void print_ans(int l, int r, vector<long long>& v) { cout << l << << r << n ; for (long long vv : v) { cout << vv << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } vector<long long> fst; fst.push_back(-a[0]); a[0] = 0; print_ans(1, 1, fst); if (n == 1) { vector<long long> zero = {0}; print_ans(1, 1, zero); print_ans(1, 1, zero); return 0; } vector<long long> scd; for (int i = 1; i < n; ++i) { long long md = a[i] % n; if (md < 0) md += n; long long nm = md * (n - 1); scd.push_back(nm); a[i] += nm; } print_ans(2, n, scd); vector<long long> all; for (int i = 0; i < n; ++i) { assert(a[i] % n == 0); all.push_back(-a[i]); } print_ans(1, n, all); return 0; }
|
// zhiyang ong
// andrew mattheisen
`timescale 1ns/10ps
`include "control.h"
module controltb;
reg [0:31] instr;
reg clk;
wire [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
wire [0:2] ppp, regop, memop;
wire [0:1] ww;
wire [0:20] maddr;
wire reginmuxop, aluinmuxop;
wire [0:15] wbyteen;
wire [0:31] immediate;
control control1(instr,
aluop, ppp, ww,
memop, maddr, wbyteen,
regop, rrdaddra, rrdaddrb, rwraddrd,
reginmuxop,
aluinmuxop,
immediate);
always
begin
#5 clk=0;
#5 clk=1;
end // always
initial
begin
#5;
//wadd
instr=32'b00010001101010100101100000000000; // ADD
#10;
instr=32'b00010001101010100101101001000000; // ADD
#10;
instr=32'b00010001101010100101110000000000; // ADD
#10;
instr=32'b00010001101010100101110001000000; // ADD
#10;
instr=32'b00010001101010100101110010000000; // ADD
#10;
instr=32'b00010001101010100101110010001001; // AND
#10;
instr=32'b00000101101000000000000000000001; // LD
#10;
instr=32'b00100001101010100000010010001001; // VMV
#10;
instr=32'b00010001101010100000010100001000; // NOT
#10;
instr=32'b00010001101010100101110101001010; // OR
#10;
instr=32'b00010001101010100101110100001100; // PRM
#10;
instr=32'b00010001101010100101110101010000; // SLL
#10;
instr=32'b00010001101010100111110110010001; // SLLI
#10;
instr=32'b00010001101010100101110110010110; // SRA
#10;
instr=32'b00010001101010100111110110010111; // SRAI
#10;
instr=32'b00010001101010100101110110010100; // SRL
#10;
instr=32'b00010001101010100111110110010101; // SRLI
#10;
instr=32'b00001001101000000000000000000001; // ST
#10;
instr=32'b00010001101010100101111001000001; // SUB
#10;
instr=32'b00010001101010100101111101001011; // XOR
#10;
instr=32'b00000001101010100101110110001011; // NOP
#10;
$finish;
end // intial
initial
begin
$shm_open("tb.shm");
$shm_probe("AC");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__XNOR2_PP_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)2e9; const long long INFL = (long long)9e18; const int MAXINT = ((~0) ^ (1 << 31)); const long long MAXLL = ((~0) ^ ((long long)1 << 63)); template <class T> inline T pow2(T a) { return a * a; } template <class T> inline bool mineq(T& a, T b) { return (a > b) ? (a = b, true) : false; } template <class T> inline bool maxeq(T& a, T b) { return (a < b) ? (a = b, true) : false; } const int maxn = 2e5; long long n, k, x, cnt; pair<long long, long long> p[maxn]; int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; i++) p[i] = {1e10, 0}; for (int i = 1; i <= k; i++) { cin >> x; p[x].first = min(p[x].first, (long long)i); p[x].second = max(p[x].second, (long long)i); } if (p[1].first > p[2].second && n != 1) { cnt++; } if (p[n].first > p[n - 1].second && n != 1) { cnt++; } if (p[1].second == 0) cnt++; if (p[n].second == 0 && n != 1) cnt++; for (int i = 2; i <= n - 1; i++) { if (p[i].second == 0) cnt++; if (p[i].first > p[i + 1].second) { cnt++; } if (p[i].first > p[i - 1].second) { cnt++; } } cout << cnt; }
|
#include <bits/stdc++.h> int n; double sum, tmp, ans; int main() { scanf( %d , &n); for (int div = 1; div <= n; div++) { scanf( %lf , &tmp); sum += tmp; if (sum / div > ans) ans = sum / div; } printf( %.20lf n , ans); }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { char ch; bool flag = false; while (!isdigit(ch = getchar())) flag |= ch == - ; for (x = ch ^ 48; isdigit(ch = getchar()); x = x * 10 + (ch ^ 48)) ; if (flag) x = -x; } inline int input() { int x; char ch; bool flag = false; while (!isdigit(ch = getchar())) flag |= ch == - ; for (x = ch ^ 48; isdigit(ch = getchar()); x = x * 10 + (ch ^ 48)) ; return flag ? -x : x; } const int mod = 1e9 + 7; inline int add(int x, int y) { x += y; return x >= mod ? x - mod : x; } inline void inc(int &x, int y) { x += y; x -= x >= mod ? mod : 0; } inline int Power(int x, int y) { int res = 1; while (y) { if (y & 1) res = (long long)res * x % mod; x = (long long)x * x % mod, y >>= 1; } return res; } template <class T> void chkmax(T &x, T y) { x = x > y ? x : y; } template <class T> void chkmin(T &x, T y) { x = x < y ? x : y; } template <class T> T gcd(T x, T y) { return !y ? x : gcd(x % y, y); } int n, a[300005]; int cnt[300005 << 1]; int lmax[300005], lmin[300005], rmax[300005], rmin[300005]; long long ans; void divide(int l, int r) { if (l == r) return void(); int mid = l + r >> 1; divide(l, mid), divide(mid + 1, r); rmin[mid] = INT_MAX, rmax[mid] = 0; lmin[mid + 1] = INT_MAX, lmax[mid + 1] = 0; for (int i = mid; i >= l; --i) { lmin[i] = min(lmin[i + 1], a[i]); lmax[i] = max(lmax[i + 1], a[i]); } for (int i = mid + 1; i <= r; ++i) { rmin[i] = min(rmin[i - 1], a[i]); rmax[i] = max(rmax[i - 1], a[i]); } for (int i = mid, lp = mid + 1, rp = mid + 1; i >= l; --i) { int pos = lmax[i] - lmin[i] + i; if (pos > mid && pos <= r && rmin[pos] > lmin[i] && rmax[pos] < lmax[i]) ++ans; while (lp <= r && rmax[lp] < lmax[i]) --cnt[300005 + rmax[lp] - lp], ++lp; while (rp <= r && rmin[rp] > lmin[i]) ++cnt[300005 + rmax[rp] - rp], ++rp; if (lp < rp) ans += cnt[300005 + lmin[i] - i]; } for (int i = mid + 1; i <= r; ++i) cnt[300005 + rmax[i] - i] = 0; for (int i = mid + 1, lp = mid, rp = mid; i <= r; ++i) { int pos = rmin[i] - rmax[i] + i; if (pos >= l && pos <= mid && lmin[pos] > rmin[i] && lmax[pos] < rmax[i]) ++ans; while (lp >= l && lmin[lp] > rmin[i]) ++cnt[lmax[lp] + lp], --lp; while (rp >= l && lmax[rp] < rmax[i]) --cnt[lmax[rp] + rp], --rp; if (lp < rp) ans += cnt[rmin[i] + i]; } for (int i = l; i <= mid; ++i) cnt[lmax[i] + i] = 0; } int main() { ios::sync_with_stdio(false); cin >> n, ans = n; for (int i = 1; i <= n; ++i) { int x, y; cin >> x >> y; a[x] = y; } divide(1, n); printf( %lld n , ans); return 0; }
|
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