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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:23:38 11/08/2013
// Design Name:
// Module Name: top_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_module(
input clock,
input reset,
output lrck,
output mclk,
output sdin,
output sclk,
output[15:0] left_data_o,
output [15:0] right_data_o
);
wire clock_50Mhz;
/** Genera un clock a 50MHz a partir del de 100MHz del de la spartan */
half_clock_divider half_divider(
.clock(clock),
.reset(reset),
.clock_out(clock_50Mhz)
);
/** Variables para el NCO */
wire[15:0] left_data;
wire[15:0] right_data;
assign left_data_o = left_data;
assign right_data_o = right_data;
/** Modulo que contiene la info del sonido */
sound_module sonido1 (
.reset(reset),
.left_data(left_data),
.right_data(right_data),
.lrck(lrck),
.sclk(sclk)
);
/** Modulo que produce la salida para el pmodi2s */
i2s_out i2s_generator (
.clock(clock_50Mhz),
.reset(reset),
.left_data(left_data),
.right_data(right_data),
.mclk(mclk),
.lrck(lrck),
.sclk(sclk),
.sdin(sdin)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; void rd() { cin >> s; if (s != start ) exit(0); } int q(int x, int y) { cout << ? << x << << y << endl; cin >> s; if (s[0] == x ) return 1; if (s[0] == y ) return 0; exit(0); } int main() { int i, l, r; while (1) { rd(); if (q(0, 1)) { cout << ! << 1 << endl; continue; } for (i = 1; 1; i <<= 1) if (q(i, i + i)) break; for (l = i + 1, r = i + i; l < r;) { i = ((long long)l + r) / 2; if (q(i, r)) l = i + 1; else r = i; } cout << ! << l << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Node { int idx, sum; int left, right; } tree[3000000]; int cnt; long long sumVal; char ch[10]; void addNode(int cur, int def, int h, int val) { if (tree[cur].idx == def) { tree[cur].sum += val; return; } tree[cur].sum += val; if ((1 << (h)) & def) { if (tree[cur].right == 0) { tree[cur].right = ++cnt; tree[cnt].idx = tree[cur].idx * 2 + 1; tree[cnt].sum = 0; tree[cnt].left = tree[cnt].right = 0; } addNode(tree[cur].right, def, h - 1, val); } else { if (tree[cur].left == 0) { tree[cur].left = ++cnt; tree[cnt].idx = tree[cur].idx * 2; tree[cnt].sum = 0; tree[cnt].left = tree[cnt].right = 0; } addNode(tree[cur].left, def, h - 1, val); } } void decayNode(int cur, int h, int maxVal) { if (h == 0) { sumVal += max(maxVal, tree[cur].sum); return; } int u = tree[cur].left, v = tree[cur].right; if (tree[u].sum > tree[v].sum) { long long t = max(maxVal, tree[cur].sum - tree[v].sum); sumVal += (long long)(1 << (h - 1)) * t; maxVal = max(maxVal, tree[cur].sum - tree[u].sum); decayNode(u, h - 1, maxVal); } else { long long t = max(maxVal, tree[cur].sum - tree[u].sum); sumVal += (long long)(1 << (h - 1)) * t; maxVal = max(maxVal, tree[cur].sum - tree[v].sum); decayNode(v, h - 1, maxVal); } } int main(int argc, char** argv) { int n, m, k, e; scanf( %d%d , &n, &m); cnt = 1; tree[1].idx = 1; tree[1].sum = 0; tree[0].sum = 0; tree[1].left = tree[1].right = 0; for (int i = 1; i <= m; i++) { scanf( %s , ch); if (ch[0] == d ) { sumVal = 0; decayNode(1, n, 0); double ans = (double)sumVal / (double)(1 << (n)); printf( %.8lf n , ans); } else { scanf( %d%d , &k, &e); int h = 0, p = k / 2; while (p) { p /= 2; h += 1; } addNode(1, k, h - 1, e); } } return (EXIT_SUCCESS); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 105; const int mod = 998244353; const double Pi = acos(-1.0); const long long INF = 1e18; const int G = 3, Gi = 332748118; long long qpow(long long a, long long b) { long long res = 1; while (b) { if (b) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int T, n, m; long long dp[105][105], a[105][105]; int main() { scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) scanf( %lld , &a[i][j]); } long long res = INF; for (int x = 1; x <= n; ++x) { for (int y = 1; y <= m; ++y) { for (int i = 0; i <= n; ++i) for (int j = 0; j <= m; ++j) dp[i][j] = INF; dp[1][0] = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { long long dis = abs(x - i) + abs(y - j); if (i <= x && j <= y && a[i][j] >= a[x][y] - dis) { dp[i][j] = min(dp[i - 1][j], dp[i][j - 1]) + a[i][j] - (a[x][y] - dis); } if (i >= x && j >= y && a[i][j] >= a[x][y] + dis) { dp[i][j] = min(dp[i - 1][j], dp[i][j - 1]) + a[i][j] - (a[x][y] + dis); } } } res = min(res, dp[n][m]); } } printf( %lld n , res); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_TB_V
`define SKY130_FD_SC_HD__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<int> out[1000]; int main() { int n; scanf( %d , &n); int ans; for (int i = 1; i * (i - 1) / 2 <= n; i++) { ans = i; } int id = 1; for (int i = 0; i < ans; i++) { for (int j = i + 1; j < ans; j++) { out[i].push_back(id); out[j].push_back(id); id++; } } printf( %d n , ans); for (int i = 0; i < ans; i++, puts( )) for (int j = 0; j < out[i].size(); j++) printf( %d , out[i][j]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 10000 + 10; int a[maxn]; int main() { int i, j, k, m, n; cin >> n; int sum = 0; while (n > 0) { if (n % 8 == 1) sum++; n /= 8; } cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; double pi = acos((double)-1); const int MOD = 1000000007; const int INF = 2147483647; int main() { clock_t tStart = clock(); int tests = 1; for (int test = 1; test <= tests; test++) { int n, m, dx, dy; cin >> n >> m >> dx >> dy; vector<int> xi(m, 0), yi(m, 0); for (int i = 0; i < m; i++) { cin >> xi[i] >> yi[i]; } vector<int> y(n, 0); int step_x = 0, step_y = 0; for (int i = 0; i < n; i++) { y[step_x] = step_y; step_x += dx; step_y += dy; step_x %= n; step_y %= n; } vector<int> groups_counter(n, 0); int groups_counter_max = 0; int groups_counter_index = 0; for (int i = 0; i < m; i++) { int k = (yi[i] - y[xi[i]] + n) % n; groups_counter[k]++; if (groups_counter[k] > groups_counter_max) { groups_counter_max = groups_counter[k]; groups_counter_index = k; } } cout << 0 << << groups_counter_index << endl; } }
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name: red_pitaya_iq_fgen_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_hpf_block #(
parameter ALPHABITS = 25,
parameter HIGHESTALPHABIT = 18,
parameter LPFBITS = 14
)
(
input clk_i,
input reset_i ,
input signed [HIGHESTALPHABIT-1:0] alpha_i,
input signed [LPFBITS-1:0] signal_i,
output signed [LPFBITS-1:0] signal_o
);
//reg signed [ALPHABITS-1:0] alpha;
reg signed [LPFBITS+ALPHABITS-1:0] y;
reg signed [LPFBITS+ALPHABITS-1:0] delta; //we need this cumbersome imperfect implementation with a delta buffer to introduce some delay so the code works at 125 MHZ
wire signed [LPFBITS+1-1:0] diff;
reg signed [LPFBITS-1:0] delta_out;
wire signed [LPFBITS-1:0] y_out;
assign y_out = y[ALPHABITS+LPFBITS-1:ALPHABITS];
assign diff = signal_i-y_out;
always @(posedge clk_i) begin
// alpha <= $signed(alpha_i);
if (reset_i == 1'b1) begin
y <= {ALPHABITS+LPFBITS{1'b0}};
delta <= {ALPHABITS+LPFBITS{1'b0}};
delta_out <= {LPFBITS{1'b0}};
end
else begin
delta <= diff * alpha_i;
y <= y + delta;
if (diff[LPFBITS:LPFBITS-1] == 2'b01)
delta_out <= {1'b0,{LPFBITS-1{1'b1}}};
else if (diff[LPFBITS:LPFBITS-1] == 2'b10)
delta_out <= {1'b1,{LPFBITS-1{1'b0}}};
else
delta_out <= diff[LPFBITS-1:0];
end
end
assign signal_o = delta_out;
endmodule
|
`define DEBOUNCE_VALUE 16'hf00f
module edge_detector (
iCLK,
iRST_n,
iTrigger_in,
oFalling_edge,
oRising_edge,
oDebounce_out,
rst_cnt
);
input iCLK;
input iRST_n;
input iTrigger_in;
output oFalling_edge;
output oRising_edge;
output reg oDebounce_out;
reg [1:0] in_delay_reg;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
in_delay_reg <= 0;
end
else
begin
in_delay_reg <= {in_delay_reg[0],iTrigger_in};
end
end
assign oFalling_edge = (in_delay_reg == 2'b01) ? 1'b1 : 1'b0;
assign oRISING_edge = (in_delay_reg == 2'b10) ? 1'b1 : 1'b0;
output reg [15:0] rst_cnt;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
rst_cnt <= 0;
end
else if (rst_cnt == `DEBOUNCE_VALUE)
rst_cnt <= 0;
else if (cnt_enable)
begin
rst_cnt <= rst_cnt + 1;
end
end
reg cnt_enable;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
cnt_enable <= 1'b0;
end
else if (oFalling_edge)
begin
cnt_enable <= 1'b1;
end
else if (rst_cnt == `DEBOUNCE_VALUE)
begin
cnt_enable <= 1'b0;
end
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oDebounce_out <= 1'b0;
end
else if (oFalling_edge && ~cnt_enable)
begin
oDebounce_out <= 1'b1;
end
else
oDebounce_out <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string rl; cin >> rl; vector<int> A(n, 0); for (int i = 0; i < n; i++) cin >> A[i]; int diff = 2147483647; int t; for (int i = 0; i < n - 1; i++) if (rl[i] == R && rl[i + 1] == L ) { t = (A[i + 1] - A[i]) / 2; diff = min(diff, t); } if (diff == 2147483647) diff = -1; cout << diff << n ; return 0; }
|
#include<bits/stdc++.h> using namespace std; int cumsum[200005]; int a[200005]; int main() { int t; scanf( %d ,&t); while(t--) { int n; scanf( %d ,&n); for(int i=0;i<n;i++) { scanf( %d ,&a[i]); } for(int i=0;i<n;i++) { cumsum[i] = 0; } for(int i=0;i<n;i++) { if(a[i] == 0) continue; cumsum[i+1]--; cumsum[max(0,i-a[i] + 1)]++; } for(int i=0;i<n;i++) { if(i != 0) cumsum[i]+=cumsum[i-1]; if(cumsum[i] == 0) { printf( 0 ); } else { printf( 1 ); } } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0; string x; cin >> n; for (int i = 1; i <= n; i++) { cin >> x; if (x == ABSINTH || x == BEER || x == BRANDY || x == CHAMPAGNE || x == GIN || x == RUM || x == SAKE || x == TEQUILA || x == VODKA || x == WHISKEY || x == WINE || x == 0 || x == 1 || x == 2 || x == 3 || x == 4 || x == 5 || x == 6 || x == 7 || x == 8 || x == 9 || x == 10 || x == 11 || x == 12 || x == 13 || x == 14 || x == 15 || x == 16 || x == 17 ) sum++; } cout << sum << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110, MAXK = 22, mod = 1000000007; struct edge { int adj, next; } e[MAXN << 1]; int n, k, f[MAXN][MAXK << 1]; int tot, head[MAXN], temp[MAXK << 1]; inline void AddEdge(int u, int v) { tot++; e[tot].adj = v, e[tot].next = head[u]; head[u] = tot; } inline void Init() { scanf( %d%d , &n, &k); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); AddEdge(u, v), AddEdge(v, u); } } void DFS(int u, int fa) { f[u][0] = f[u][k + 1] = 1; for (int i = head[u]; i; i = e[i].next) { int &v = e[i].adj; if (v == fa) continue; DFS(v, u); memset(temp, 0, sizeof(temp)); for (int i = 0; i <= 2 * k; i++) for (int j = 0; j <= 2 * k; j++) { if (i + j + 1 <= 2 * k + 1) temp[min(i, j + 1)] = (temp[min(i, j + 1)] + (long long)f[u][i] * f[v][j]) % mod; else temp[max(i, j + 1)] = (temp[max(i, j + 1)] + (long long)f[u][i] * f[v][j]) % mod; } memcpy(f[u], temp, sizeof(temp)); } } int main() { Init(); DFS(1, 0); int ans = 0; for (int i = 0; i <= k; i++) ans = (ans + f[1][i]) % mod; printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 6
-- Description: Sbox 6 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox6
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd12;
4'd1: sbox_dout = 4'd1;
4'd2: sbox_dout = 4'd10;
4'd3: sbox_dout = 4'd15;
4'd4: sbox_dout = 4'd9;
4'd5: sbox_dout = 4'd2;
4'd6: sbox_dout = 4'd6;
4'd7: sbox_dout = 4'd8;
4'd8: sbox_dout = 4'd0;
4'd9: sbox_dout = 4'd13;
4'd10: sbox_dout = 4'd3;
4'd11: sbox_dout = 4'd4;
4'd12: sbox_dout = 4'd14;
4'd13: sbox_dout = 4'd7;
4'd14: sbox_dout = 4'd5;
4'd15: sbox_dout = 4'd11;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd10;
4'd1: sbox_dout = 4'd15;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd2;
4'd4: sbox_dout = 4'd7;
4'd5: sbox_dout = 4'd12;
4'd6: sbox_dout = 4'd9;
4'd7: sbox_dout = 4'd5;
4'd8: sbox_dout = 4'd6;
4'd9: sbox_dout = 4'd1;
4'd10: sbox_dout = 4'd13;
4'd11: sbox_dout = 4'd14;
4'd12: sbox_dout = 4'd0;
4'd13: sbox_dout = 4'd11;
4'd14: sbox_dout = 4'd3;
4'd15: sbox_dout = 4'd8;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd9;
4'd1: sbox_dout = 4'd14;
4'd2: sbox_dout = 4'd15;
4'd3: sbox_dout = 4'd5;
4'd4: sbox_dout = 4'd2;
4'd5: sbox_dout = 4'd8;
4'd6: sbox_dout = 4'd12;
4'd7: sbox_dout = 4'd3;
4'd8: sbox_dout = 4'd7;
4'd9: sbox_dout = 4'd0;
4'd10: sbox_dout = 4'd4;
4'd11: sbox_dout = 4'd10;
4'd12: sbox_dout = 4'd1;
4'd13: sbox_dout = 4'd13;
4'd14: sbox_dout = 4'd11;
4'd15: sbox_dout = 4'd6;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd4;
4'd1: sbox_dout = 4'd3;
4'd2: sbox_dout = 4'd2;
4'd3: sbox_dout = 4'd12;
4'd4: sbox_dout = 4'd9;
4'd5: sbox_dout = 4'd5;
4'd6: sbox_dout = 4'd15;
4'd7: sbox_dout = 4'd10;
4'd8: sbox_dout = 4'd11;
4'd9: sbox_dout = 4'd14;
4'd10: sbox_dout = 4'd1;
4'd11: sbox_dout = 4'd7;
4'd12: sbox_dout = 4'd6;
4'd13: sbox_dout = 4'd0;
4'd14: sbox_dout = 4'd8;
4'd15: sbox_dout = 4'd13;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox6 sbox6
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array#(parameter SWR=26, parameter LEVEL=5)(
//INPUTS
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
//OUTPUTS
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (bit_shift_i),
.S (Data_o[j])
);
end
1'b0:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[sh]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
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#include <algorithm> #include <iostream> #include <sstream> #include <string> #include <vector> #include <queue> #include <set> #include <map> #include <cstdio> #include <cstdlib> #include <cctype> #include <cmath> #include <cstring> #include <list> #include <cassert> #include <climits> #include <bitset> #include <chrono> #include <random> using namespace std; #define PB push_back #define MP make_pair #define SZ(v) ((int)(v).size()) #define FOR(i,a,b) for(int i=(a);i<(b);++i) #define REP(i,n) FOR(i,0,n) #define FORE(i,a,b) for(int i=(a);i<=(b);++i) #define REPE(i,n) FORE(i,0,n) #define FORSZ(i,a,v) FOR(i,a,SZ(v)) #define REPSZ(i,v) REP(i,SZ(v)) std::mt19937 rnd((int)std::chrono::steady_clock::now().time_since_epoch().count()); typedef long long ll; ll gcd(ll a, ll b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 50; const int MOD = 998244353; void inc(int& a, int b) { if ((a += b) >= MOD) a -= MOD; } int n; int firstval; int deltaval[MAXN]; ll anslen; int answays; ll segfrom[MAXN], segto[MAXN]; vector<ll> special; vector<int> path; vector<vector<int>> C; vector<int> inv; int choose(ll n, int k) { int ret = 1; REP(i, k) ret = (ll)ret * ((n - i) % MOD) % MOD * inv[i + 1] % MOD; return ret; } int calctrans(int s, int t) { int npos = 0; FOR(i, s, t) if (path[i] == path[s] && path[i + 1] == path[t]) ++npos; int nneg = npos - 1; ll between = special[path[t]] - special[path[s]] - 1; int nbar = npos + nneg - 1; //printf( tnpos=%d nneg=%d between=%lld n , npos, nneg, between); int ret = 0; REPE(i, nneg) { // #times neg more than 1 ll rem = between - 2 * i; if (rem < 0) continue; int ways = (ll)choose(rem + nbar, nbar) * C[nneg][i] % MOD; //printf( t%d: %d (rem=%lld) n , i, ways, rem); if (i % 2 == 0) inc(ret, ways); else inc(ret, MOD - ways); } //printf( t->%d n , ret); return ret; } void solve() { REP(i, n) { segfrom[i] = i == 0 ? firstval : segto[i - 1]; segto[i] = segfrom[i] + deltaval[i]; } special.clear(); REP(i, n) special.PB(segfrom[i]), special.PB(segto[i]); sort(special.begin(), special.end()); special.erase(unique(special.begin(), special.end()), special.end()); //printf( special: ); REPSZ(i, special) printf( %lld , special[i]); puts( ); path.clear(); REP(i, n) { int fromidx = lower_bound(special.begin(), special.end(), segfrom[i]) - special.begin(); int toidx = lower_bound(special.begin(), special.end(), segto[i]) - special.begin(); if (i == 0) path.PB(fromidx); if (fromidx < toidx) FORE(j, fromidx + 1, toidx) path.PB(j); if (fromidx > toidx) for (int j = fromidx - 1; j >= toidx; --j) path.PB(j); } //printf( path: ); REPSZ(i, path) printf( %d , path[i]); puts( ); //printf( path: ); REPSZ(i, path) printf( %lld , special[path[i]]); puts( ); bool desc = true; FORSZ(i, 1, path) if (path[i] > path[i - 1]) desc = false; if (desc) { anslen = 1; answays = (special[path[0]] - special[path.back()] + 1) % MOD; return; } anslen = 0; REPSZ(i, path) FORSZ(j, i + 1, path) if (path[i] < path[j]) anslen = max(anslen, special[path[j]] - special[path[i]] + 1); assert(anslen > 0); C = vector<vector<int>>(SZ(path) + 1, vector<int>(SZ(path) + 1)); REPSZ(i, C) { C[i][0] = C[i][i] = 1; FOR(j, 1, i) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } inv = vector<int>(SZ(path) + 1); inv[1] = 1; FORSZ(i, 2, inv) inv[i] = (ll)(MOD - MOD / i) * inv[MOD % i] % MOD; answays = 0; vector<vector<int>> trans(SZ(path), vector<int>(SZ(path), 0)); REPSZ(i, path) FORSZ(j, i + 1, path) if (path[j] == path[i] + 1) trans[i][j] = calctrans(i, j); REPSZ(i, special) { vector<int> dp(SZ(path), 0); REPSZ(j, path) if (path[j] == i) inc(dp[j], 1); REPSZ(j, path) FORSZ(k, j + 1, path) dp[k] = (dp[k] + (ll)dp[j] * trans[j][k]) % MOD; REPSZ(j, path) if (special[path[j]] - special[i] + 1 == anslen) inc(answays, dp[j]); } } void run() { scanf( %d , &n); scanf( %d , &firstval); REP(i, n) scanf( %d , &deltaval[i]); solve(); printf( %lld %d n , anslen, answays); } int main() { run(); return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace std; vector<int> adj[100005]; vector<int>::iterator it; int con[100005]; bool visited[100005]; int bfs(int root) { int j, i, u, v, mn = 10000000, temp; queue<int> Q; Q.push(root); visited[root] = true; while (!Q.empty()) { u = Q.front(); Q.pop(); for (i = 0; i < adj[u].size(); i++) { v = adj[u][i]; if (!visited[v]) { Q.push(v); visited[v] = true; } else { for (j = 0; j < adj[u].size(); j++) { if (adj[u][j] != v) { it = lower_bound(adj[v].begin(), adj[v].end(), adj[u][j]); if (it != adj[v].end() && ((*it) == adj[u][j])) { temp = con[u] + con[v] + con[adj[u][j]] - 6; if (temp < mn) mn = temp; } } } } } } return mn; } int main() { int j, t, i, t1, t2, n, m, ans; t = 1; while (t--) { scanf( %d , &n); scanf( %d , &m); memset(visited, 0, sizeof(visited)); for (i = 0; i < m; i++) { scanf( %d%d , &t1, &t2); adj[t1].push_back(t2); adj[t2].push_back(t1); } for (i = 1; i <= n; i++) { sort(adj[i].begin(), adj[i].end()); } for (i = 1; i <= n; i++) { con[i] = adj[i].size(); } ans = 10000000; for (i = 1; i <= n; i++) { if (!visited[i]) { t1 = bfs(i); if (t1 < ans) ans = t1; } } if (ans == 10000000) printf( -1 n ); else printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int mo = 1e9 + 7; const int mx = 500010; int n, m, k, a[1010], c[1010], ans, sum; int jud[mx]; set<int> s[mx]; set<int>::iterator it; vector<int> vc[mx]; void dfs(int y, int pre) { vector<int> v; if (pre == -1) { int t = 1; for (it = s[y].begin(); it != s[y].end(); it++) { jud[*it] = t++; sum = max(sum, t - 1); } } else { for (it = s[y].begin(); it != s[y].end(); it++) { if (jud[(*it)]) v.push_back(jud[(*it)]); } int vn = v.size(); sort(v.begin(), v.end()); int f = 0, t = 1; for (it = s[y].begin(); it != s[y].end(); it++) { if (!jud[(*it)]) { while (f < vn && v[f] == t) { f++; t++; } jud[(*it)] = t++; } sum = max(sum, t - 1); } } int nm = vc[y].size(); for (int i = 0; i < nm; i++) { int vyi = vc[y][i]; if (vyi != pre) dfs(vyi, y); } } int dxy[8] = {1, 0, -1, 0, 0, 1, 0, -1}; int main() { ios::sync_with_stdio(false); int t, i, j, l, q, x, y, ss; int cas = 1, flag; cin >> n >> m; { l = max(n, m); for (i = 0; i <= l; i++) { vc[i].clear(); jud[i] = 0; } sum = 1; for (i = 1; i <= n; i++) { cin >> ss; for (j = 0; j < ss; j++) { cin >> x; s[i].insert(x); } } for (i = 0; i < n - 1; i++) { cin >> x >> y; vc[x].push_back(y); vc[y].push_back(x); } dfs(1, -1); cout << sum << endl; for (i = 1; i <= m; i++) { if (jud[i]) cout << jud[i]; else cout << 1 ; if (i != m) cout << ; else cout << endl; } } return 0; }
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/* Basic census transformation.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`ifndef CENSUS_CENSUS_V_
`define CENSUS_CENSUS_V_
`timescale 1ns/1ps
`include "dff.v"
// This census transform takes the output of line buffers, and performs the
// census transform over a window of pixels, as produced by the lib/line_buffer.
// The census transform is defined for each pixel in the window as:
// if (current_pixel > center_pixel) then 1 else 0
// It acts as a "signature" for the window that's independent of absolute
// differences between cameras, and is significantly smaller.
//
// It's parameterized in a few ways:
// WIDTH: Word size
// WINDOW_WIDTH: Width of the window
// WINDOW_HEIGHT: Height of the window
module census#(
parameter WIDTH=1,
parameter WINDOW_WIDTH=2,
parameter WINDOW_HEIGHT=2
) (
input wire clk,
input wire rst,
input wire [WIDTH*WINDOW_WIDTH*WINDOW_HEIGHT-1:0] inp,
output wire [WINDOW_WIDTH*WINDOW_HEIGHT-1:0] outp
);
localparam INP_WIDTH = WIDTH*WINDOW_WIDTH*WINDOW_HEIGHT;
localparam CENTER = (WINDOW_WIDTH*WINDOW_HEIGHT-1)/2;
wire [WINDOW_WIDTH*WINDOW_HEIGHT-1:0] outp_next;
wire [WIDTH-1:0] word[WINDOW_WIDTH*WINDOW_HEIGHT];
dff#(.WIDTH(WINDOW_WIDTH*WINDOW_HEIGHT)) out_ff(clk, rst, outp_next, outp);
// Unpack the individual words
genvar i;
generate
for (i = 0; i < WINDOW_WIDTH*WINDOW_HEIGHT; i++) begin
assign word[i] = inp[(INP_WIDTH-WIDTH*i-1):(INP_WIDTH-WIDTH*(i+1))];
end
endgenerate
// Compute the census transform.
genvar j;
generate
for (j = 0; j < WINDOW_WIDTH*WINDOW_HEIGHT; j++) begin
if (j == CENTER) begin
assign outp_next[j] = 0;
end else begin
assign outp_next[j] = word[j] > word[CENTER];
end
end
endgenerate
endmodule
`endif // CENSUS_CENSUS_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_BLACKBOX_V
`define SKY130_FD_SC_HS__DFRTN_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtn (
RESET_B,
CLK_N ,
D ,
Q
);
input RESET_B;
input CLK_N ;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long global = 0; void test_case(long long); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; int yes = 1; if (yes) cin >> t; else t = 1; for (long long T = 0; T < t; T++) { test_case(T); } return 0; } void test_case(long long T) { long long n, m; cin >> n >> m; vector<string> vec(n); for (long long(i) = 0; (i) < n; (i)++) { cin >> vec[i]; } vector<long long> x = {0, 1, 0, -1}, y = {1, 0, -1, 0}; long long g = 0; for (long long(i) = 0; (i) < n; (i)++) { for (long long(j) = 0; (j) < m; (j)++) { if (vec[i][j] == G ) g++; if (vec[i][j] == B ) { for (long long k = 0; k < 4; k++) { long long idx = i + x[k]; long long jdx = j + y[k]; if (idx >= 0 && idx < n && jdx >= 0 && jdx < m) { if (vec[idx][jdx] == G ) { cout << no << endl; return; } else if (vec[idx][jdx] == . ) { vec[idx][jdx] = # ; } } } } } } queue<pair<long long, long long>> q; q.push(pair<long long, long long>(n - 1, m - 1)); map<pair<long long, long long>, long long> v; v[pair<long long, long long>(n - 1, m - 1)]++; long long vg = 0; while (!q.empty()) { auto f = q.front(); q.pop(); if (vec[f.first][f.second] == G ) vg++; else if (vec[f.first][f.second] == # ) break; for (long long k = 0; k < 4; k++) { long long idx = f.first + x[k]; long long jdx = f.second + y[k]; if (idx >= 0 && idx < n && jdx >= 0 && jdx < m) { if (vec[idx][jdx] == # || vec[idx][jdx] == B ) continue; if (!v[pair<long long, long long>(idx, jdx)]) { v[pair<long long, long long>(idx, jdx)]++; q.push(pair<long long, long long>(idx, jdx)); } } } } if (vg == g) cout << yes << endl; else cout << no << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k = 0; string s; cin >> s >> n; vector<char> v, vv; int len = s.size(); if (len % n != 0) { cout << NO << endl; return 0; } int cnt = 0, c = 0, j; int m = len / n; for (int i = 0; i < n; i++) { v.clear(); vv.clear(); for (j = c; j < len; j++) { v.push_back(s[j]); vv.push_back(s[j]); cnt++; c++; if (cnt == m) break; } cnt = 0; int pnt = 0; reverse(vv.begin(), vv.end()); int ln = v.size(); for (int i = 0; i < ln; i++) { if (v[i] == vv[i]) pnt++; if (pnt == ln) { k++; } } v.clear(); vv.clear(); } if (k == n) { k = 0; cout << YES << endl; } else { k = 0; cout << NO << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_1_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_1_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog wrapper for tapvpwrvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapvpwrvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tapvpwrvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_1_V
|
#include <bits/stdc++.h> using namespace std; int n, a[10]; int MOD = 1000000007; long long C[101][101]; void comb(int lim) { int n, r; C[0][0] = 1; for (n = 1; n <= lim; n++) { C[n][0] = 1; for (r = 1; r <= n - 1; r++) { C[n][r] = (C[n - 1][r - 1] + C[n - 1][r]) % MOD; } C[n][n] = 1; } } int f[101][10]; int main() { comb(100); scanf( %d , &n); for (int i = 0; i < (10); i++) scanf( %d , &a[i]); long long r = 0; for (int l = 0; l <= n; l++) { f[l][9] = (l >= a[9]); for (int d = 8; d >= 1; d--) { for (int k = a[d]; k <= l; k++) { f[l][d] = (f[l][d] + C[l][k] * f[l - k][d + 1]) % MOD; } } for (int k = a[0]; k <= l; k++) { f[l][0] = (f[l][0] + C[l - 1][k] * f[l - k][1]) % MOD; } if (l >= 1) r = (r + f[l][0]) % MOD; } cout << r << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int INF = 98769876987698889LL; const int MOD = 1e9 + 7; const int dx8[] = {1, 1, 0, -1, -1, -1, 0, 1}; const int dy8[] = {0, 1, 1, 1, 0, -1, -1, -1}; const int dx4[] = {1, -1, 0, 0}; const int dy4[] = {0, 0, 1, -1}; const int N = 2e5 + 5; long long int dp1[N], a[N], f[N], dp2[N], s[N]; int n; vector<int> G[N]; void dfs(int x, int pa) { if (G[x].size() == 1 and G[x][0] == pa) { s[x] = a[x]; return; } s[x] = a[x]; for (auto k : G[x]) { if (k == pa) continue; dfs(k, x); s[x] += s[k]; } } void dfs2(int x, int pa) { if (G[x].size() == 1 and G[x][0] == pa) { f[x] = 0; return; } f[x] = 0; vector<long long int> v; for (auto k : G[x]) { if (k == pa) continue; dfs2(k, x); if (s[k] >= dp1[k]) { v.push_back(s[k]); } else { v.push_back(dp1[k]); } } sort(v.begin(), v.end()); dp1[x] = v[v.size() - 1]; if (v.size() > 1) { f[x] = 1; dp2[x] = v[v.size() - 2]; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 0; i < N; i++) { dp1[i] = -INF; dp2[i] = -INF; } for (int i = 2; i <= n; i++) { int x, y; cin >> x >> y; G[x].push_back(y); G[y].push_back(x); } if (n == 1) { cout << Impossible << endl; return 0; } dfs(1, 0); dfs2(1, 0); int fl = 0; for (int i = 1; i <= n; i++) { if (f[i]) fl = 1; } if (!fl) { cout << Impossible << endl; return 0; } long long int ans = -INF; for (int i = 1; i <= n; i++) { if (f[i]) { ans = max(ans, dp1[i] + dp2[i]); } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; map<long long, long long> Map; void modify(long long x, long long y) { map<long long, long long>::iterator it; long long c; scanf( %I64d , &c); while (x != y) { if (x < y) swap(x, y); it = Map.find(x); if (it != Map.end()) it->second += c; else Map[x] = c; x >>= 1; } } long long query(long long x, long long y) { map<long long, long long>::iterator it; long long ans = 0; while (x != y) { if (x < y) swap(x, y); it = Map.find(x); if (it != Map.end()) ans += it->second; x >>= 1; } return ans; } int main(int argc, char* argv[]) { int q = 0; for (; scanf( %d , &q) != EOF;) { Map.clear(); while (q--) { int od; long long x, y, c; scanf( %d%I64d%I64d , &od, &x, &y); if (od == 1) modify(x, y); else printf( %I64d n , query(x, y)); } } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int>> res, res2, res3; int x[10005], y[10005], id[35], b[35], vis[10005], r[10005]; bitset<35> c[35], d[35], tmp; int insert(int x, int y, bitset<35> now) { for (int i = 0; i <= 30; i++) if (x & (1 << i)) { if (!b[i]) { b[i] = x; id[i] = y; vis[y] = 1; d[i] = now; d[i][i] = 1; return i; } x ^= b[i]; now ^= d[i]; } return -1; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &x[i]), r[i] = insert(x[i], i, bitset<35>()); for (int i = 1; i <= n; i++) scanf( %d , &y[i]); for (int i = 1; i <= n; i++) { int now = y[i]; for (int j = 0; j <= 30; j++) if (now & (1 << j)) { now ^= b[j]; if (~r[i]) c[r[i]] ^= d[j]; } if (now) { puts( -1 ); return 0; } } for (int i = 1; i <= n; i++) if (!vis[i]) { int now = y[i] ^ x[i]; tmp.reset(); for (int j = 0; j <= 30; j++) if (now & (1 << j)) now ^= b[j], tmp ^= d[j]; for (int j = 0; j <= 30; j++) if (tmp[j]) res.push_back({i, id[j]}); } for (int i = 0; i <= 30; i++) { if (!c[i][i]) for (int j = 0; j <= 30; j++) if (c[j][i] && ((!c[j][j]) || j > i)) { res2.push_back({id[i], id[j]}); res2.push_back({id[j], id[i]}); res2.push_back({id[i], id[j]}); swap(c[i], c[j]); break; } if (!c[i][i]) continue; for (int j = 0; j <= 30; j++) if (i != j && c[j][i]) { c[j] ^= c[i]; res2.push_back({id[j], id[i]}); } } for (int i = 1; i <= 30; i++) for (int j = 0; j < i; j++) if (c[j][i]) res3.push_back({id[j], id[i]}); for (int i = 0; i <= 30; i++) if ((id[i]) && (!(c[i][i]))) res2.push_back({id[i], id[i]}); printf( %d n , (int)(res.size() + res2.size() + res3.size())); reverse(res2.begin(), res2.end()); for (auto i : res) printf( %d %d n , i.first, i.second); for (auto i : res3) printf( %d %d n , i.first, i.second); for (auto i : res2) printf( %d %d n , i.first, i.second); return 0; }
|
#include<bits/stdc++.h> #include<vector> #include<map> #include<queue> #define LL long long #define INF INT64_MAX #define MOD 1000000007 #define stree SegTree[root] #define lson SegTree[root << 1] #define rson SegTree[root << 1 | 1] using namespace std; const int N = 100005; LL a[N]; int main() { int t, n; cin>>t; LL Min = INF; int tt = 0; while(t--) { tt++; cin>>n; for(int i = 1;i <= n;i++) { cin>>a[i]; } LL ans = INF, tem = 0, m1 = INT_MAX, m2 = INT_MAX; for(int i = 1;i <= n;i++) { if(i&1) { m1 = min(m1, a[i]); ans = min(ans, tem + m1*(n-i/2) + m2*(n-i/2)); tem += a[i]; //printf( 1ans = %lld tem = %lld n , ans, tem); } else { m2 = min(m2, a[i]); ans = min(ans, tem + m2*(n-(i-1)/2) + m1*(n-i/2)); tem += a[i]; //printf( 2ans = %lld tem = %lld n , ans, tem); } } printf( %lld n , ans); } return 0; }
|
// $Id: c_prefix_arbiter.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// prefix tree based round-robin arbiter
//==============================================================================
module c_prefix_arbiter
(clk, reset, active, req_pr, gnt_pr, gnt, update);
`include "c_constants.v"
`include "c_functions.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
// store priorities in encoded form
parameter encode_state = 1;
// width of encoded arbiter state
localparam state_width = clogb(num_ports);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// vector of requests
input [0:num_priorities*num_ports-1] req_pr;
// vector of grants
output [0:num_priorities*num_ports-1] gnt_pr;
wire [0:num_priorities*num_ports-1] gnt_pr;
// merged vector of grants
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
// update port priorities
input update;
wire [0:num_priorities*num_ports-1] gnt_intm_pr;
wire [0:num_ports-1] prio_port;
genvar prio;
generate
for(prio = 0; prio < num_priorities; prio = prio + 1)
begin:prios
wire [0:num_ports-1] req;
assign req = req_pr[prio*num_ports:(prio+1)*num_ports-1];
wire [0:num_ports-1] gnt;
c_prefix_arbiter_base
#(.num_ports(num_ports))
gnt_ab
(.prio_port(prio_port),
.req(req),
.gnt(gnt));
assign gnt_intm_pr[prio*num_ports:(prio+1)*num_ports-1] = gnt;
end
if(encode_state)
begin
wire [0:state_width-1] next_state;
c_encode
#(.num_ports(num_ports),
.offset(1))
next_state_enc
(.data_in(gnt),
.data_out(next_state));
wire [0:state_width-1] state_s, state_q;
assign state_s = update ? next_state : state_q;
c_dff
#(.width(state_width),
.reset_type(reset_type))
stateq
(.clk(clk),
.reset(reset),
.active(active),
.d(state_s),
.q(state_q));
c_decode
#(.num_ports(num_ports))
prio_port_dec
(.data_in(state_q),
.data_out(prio_port));
end
else
begin
wire [0:num_ports-1] next_prio;
assign next_prio = {gnt[num_ports-1], gnt[0:num_ports-2]};
wire [0:num_ports-1] prio_s, prio_q;
assign prio_s = update ? next_prio : prio_q;
c_dff
#(.width(num_ports),
.reset_value({1'b1, {(num_ports-1){1'b0}}}),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.active(active),
.d(prio_s),
.q(prio_q));
assign prio_port = prio_q;
end
if(num_priorities == 1)
begin
assign gnt_pr = gnt_intm_pr;
assign gnt = gnt_intm_pr;
end
else if(num_priorities > 1)
begin
wire [0:num_priorities-1] any_req_pr;
c_reduce_bits
#(.num_ports(num_priorities),
.width(num_ports),
.op(`BINARY_OP_OR))
any_req_pr_rb
(.data_in(req_pr),
.data_out(any_req_pr));
wire [0:num_priorities-1] any_req_mod_pr;
assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
wire [0:num_priorities-1] sel_pr;
c_lod
#(.width(num_priorities))
sel_pr_lod
(.data_in(any_req_mod_pr),
.data_out(sel_pr));
c_gate_bits
#(.num_ports(num_priorities),
.width(num_ports),
.op(`BINARY_OP_AND))
gnt_pr_gb
(.select(sel_pr),
.data_in(gnt_intm_pr),
.data_out(gnt_pr));
c_select_1ofn
#(.num_ports(num_priorities),
.width(num_ports))
gnt_sel
(.select(sel_pr),
.data_in(gnt_intm_pr),
.data_out(gnt));
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long MAX_N = 1e6 + 5; using pii = pair<long long, long long>; struct edge { long long to, flow, cap, cost, rev; }; struct MinCostMaxFlow { long long nodes; vector<long long> prio, curflow, prevedge, prevnode, q, pot; vector<bool> inqueue; vector<vector<edge>> graph; MinCostMaxFlow() {} MinCostMaxFlow(long long n) : nodes(n), prio(n, 0), curflow(n, 0), prevedge(n, 0), prevnode(n, 0), q(n, 0), pot(n, 0), inqueue(n, 0), graph(n) {} void addEdge(long long source, long long to, long long capacity, long long cost) { edge a = {to, 0, capacity, cost, (long long)graph[to].size()}; edge b = {source, 0, 0, -cost, (long long)graph[source].size()}; graph[source].push_back(a); graph[to].push_back(b); } void bellman_ford(long long source, vector<long long> &dist) { fill(dist.begin(), dist.end(), INT_MAX); dist[source] = 0; long long qt = 0; q[qt++] = source; for (long long qh = 0; (qh - qt) % nodes != 0; qh++) { long long u = q[qh % nodes]; inqueue[u] = false; for (auto &e : graph[u]) { if (e.flow >= e.cap) continue; long long v = e.to; long long newDist = dist[u] + e.cost; if (dist[v] > newDist) { dist[v] = newDist; if (!inqueue[v]) { inqueue[v] = true; q[qt++ % nodes] = v; } } } } } pair<long long, long long> minCostFlow(long long source, long long dest, long long maxflow) { bellman_ford(source, pot); long long flow = 0; long long flow_cost = 0; while (flow < maxflow) { priority_queue<pair<long long, long long>, vector<pair<long long, long long>>, greater<pair<long long, long long>>> q; q.push({0, source}); fill(prio.begin(), prio.end(), INT_MAX); prio[source] = 0; curflow[source] = INT_MAX; while (!q.empty()) { long long d = q.top().first; long long u = q.top().second; q.pop(); if (d != prio[u]) continue; for (long long i = 0; i < graph[u].size(); i++) { edge &e = graph[u][i]; long long v = e.to; if (e.flow >= e.cap) continue; long long newPrio = prio[u] + e.cost + pot[u] - pot[v]; if (prio[v] > newPrio) { prio[v] = newPrio; q.push({newPrio, v}); prevnode[v] = u; prevedge[v] = i; curflow[v] = min(curflow[u], e.cap - e.flow); } } } if (prio[dest] == INT_MAX) break; for (long long i = 0; i < nodes; i++) pot[i] += prio[i]; long long df = min(curflow[dest], maxflow - flow); flow += df; for (long long v = dest; v != source; v = prevnode[v]) { edge &e = graph[prevnode[v]][prevedge[v]]; e.flow += df; graph[v][e.rev].flow -= df; flow_cost += df * e.cost; } } return {flow, flow_cost}; } }; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; MinCostMaxFlow network = MinCostMaxFlow(2 * n + 3); long long s = 0; long long t = 2 * n + 2; for (long long i = 0; i < n; i++) { network.addEdge(s, i + 1, 1, 0); network.addEdge(i + 1 + n, t, 1, 0); long long a, b, k; cin >> a >> b >> k; for (long long j = 0; j <= n; j++) { long long cc = max(0LL, a - min(k, j) * b); network.addEdge(i + 1, j + 1 + n, 1, -cc); } } network.addEdge(t - 1, t, 1, 0); cout << -network.minCostFlow(s, t, n + 1).second; return 0; }
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "uart_rx.v"
`include "uart.v"
module uart_tb;
integer i;
// transmit side
reg clk, transmit;
reg [23:0] tx_data;
wire txd, tx_empty;
// receive side
wire [7:0] rx_data;
wire rx_full;
reg rx_ack = 1; // insta-ack everything
// transmit uart to test my receiver
uart #(
.divide_count(20)
) test_uart(
.clock(clk),
.txd(txd),
.tx_data(tx_data),
.tx_empty(tx_empty),
.transmit(transmit)
);
uart_rx #(
.divide_count(5)
) test_uart_rx(
.clock(clk),
.rxd(txd), // attached to transmitter
.rx_data(rx_data),
.rx_full(rx_full),
.ack(rx_ack)
);
initial begin
clk = 1'b0;
forever #9 clk = ~clk;
end
initial begin
$display("running uart_tb");
$dumpfile("uart_rx_tb.vcd");
$dumpvars(0, uart_tb);
$display("start");
transmit = 0;
repeat(8) @(posedge clk);
$display("transmit");
tx_data = 24'b111111110000000010110010;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
$display("observe");
@(posedge tx_empty);
tx_data = 8'h00;
transmit = 1;
@(posedge clk);
#1 transmit = 0;
@(posedge tx_empty);
repeat(100) @(posedge clk);
$display("stop now");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace Flandle_Scarlet { int n; int a[51][51]; char tmp[51]; int s[51][51]; void Input() { cin >> n; for (int i = 1; i <= n; ++i) { scanf( %s , tmp); for (int j = 1; j <= n; ++j) { if (tmp[j - 1] == # ) a[i][j] = 1; else a[i][j] = 0; } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { s[i][j] = s[i][j - 1] + s[i - 1][j] - s[i - 1][j - 1] + a[i][j]; } } } int RSum(int a1, int b1, int a2, int b2) { return s[a2][b2] - s[a1 - 1][b2] - s[a2][b1 - 1] + s[a1 - 1][b1 - 1]; } int dp[51][51][51][51]; int DFS(int a1, int b1, int a2, int b2) { if (dp[a1][b1][a2][b2]) { return dp[a1][b1][a2][b2]; } if (a1 == a2 and b1 == b2) { dp[a1][b1][a2][b2] = a[a1][b1]; return dp[a1][b1][a2][b2]; } if (RSum(a1, b1, a2, b2) == 0) { return (dp[a1][b1][a2][b2] = 0); } dp[a1][b1][a2][b2] = max(a2 - a1 + 1, b2 - b1 + 1); for (int i = a1; i < a2; ++i) { int newans = DFS(a1, b1, i, b2) + DFS(i + 1, b1, a2, b2); dp[a1][b1][a2][b2] = min(dp[a1][b1][a2][b2], newans); } for (int i = b1; i < b2; ++i) { int newans = DFS(a1, b1, a2, i) + DFS(a1, i + 1, a2, b2); dp[a1][b1][a2][b2] = min(dp[a1][b1][a2][b2], newans); } return dp[a1][b1][a2][b2]; } void Soviet() { DFS(1, 1, n, n); printf( %d n , dp[1][1][n][n]); } void IsMyWife() { if (0) { freopen( , r , stdin); freopen( , w , stdout); } Input(); Soviet(); } }; // namespace Flandle_Scarlet int main() { Flandle_Scarlet::IsMyWife(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int C[1 << 12], A[1 << 12], B[1 << 12], LA[1 << 12], LB[1 << 12]; int main() { int i, s = 0; scanf( %d , &n); n = (1 << n); for (i = 0; i < n; i++) { scanf( %d , &C[i]); s ^= C[i]; } if (s) { puts( Fou ); return 0; } puts( Shi ); for (i = 0; i < n; i++) { A[i] = B[i] = i; LA[i] = LB[i] = i; } for (i = 0; i < n; i++) { int u = i; while (1) { if ((A[u] ^ B[u]) == C[u]) break; int v = LA[C[u] ^ B[u]]; swap(A[v], A[u]); swap(LA[A[v]], LA[A[u]]); if (v > i) break; swap(B[v], B[i + 1]); swap(LB[B[v]], LB[B[i + 1]]); u = v; } } for (i = 0; i < n; i++) printf( %d , A[i]); puts( ); for (i = 0; i < n; i++) printf( %d , B[i]); }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9234_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [63:0] adc_data_a;
output [63:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s3_s;
wire [15:0] adc_data_a_s2_s;
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s3_s;
wire [15:0] adc_data_b_s2_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = { adc_data_a_s3_s, adc_data_a_s2_s,
adc_data_a_s1_s, adc_data_a_s0_s};
assign adc_data_b = { adc_data_b_s3_s, adc_data_b_s2_s,
adc_data_b_s1_s, adc_data_b_s0_s};
// data multiplex
assign adc_data_a_s3_s = {rx_data[ 31: 24], rx_data[ 63: 56]};
assign adc_data_a_s2_s = {rx_data[ 23: 16], rx_data[ 55: 48]};
assign adc_data_a_s1_s = {rx_data[ 15: 8], rx_data[ 47: 40]};
assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[ 39: 32]};
assign adc_data_b_s3_s = {rx_data[ 95: 88], rx_data[127:120]};
assign adc_data_b_s2_s = {rx_data[ 87: 80], rx_data[119:112]};
assign adc_data_b_s1_s = {rx_data[ 79: 72], rx_data[111:104]};
assign adc_data_b_s0_s = {rx_data[ 71: 64], rx_data[103: 96]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, b; string a, c; int main() { cin >> n; int l = -2e9, r = 2e9; for (; n--;) { cin >> a >> b >> c; if (a == > && c == Y || a == <= && c == N ) l = max(l, b + 1); else if (a == >= && c == Y || a == < && c == N ) l = max(l, b); else if (a == < && c == Y || a == >= && c == N ) r = min(r, b - 1); else r = min(r, b); } if (l > r) puts( Impossible ); else printf( %d , l); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O311AI_PP_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_PP_SYMBOL_V
|
module buffer2axis #(
parameter DWIDTH = 32,
parameter WIDTH = 4,
parameter HEIGHT = 4
)(
// Control signals
clk,
rstn,
// Color conversion signals
alive_color,
dead_color,
// AXIS Connection
M_AXIS_TDATA,
M_AXIS_TVALID,
M_AXIS_TREADY,
M_AXIS_TLAST,
// Output to conware computation
in_data,
in_valid,
in_ready
);
// Port descriptions
input clk;
input rstn;
input [DWIDTH-1:0] alive_color;
input [DWIDTH-1:0] dead_color;
output [DWIDTH-1:0] M_AXIS_TDATA;
output M_AXIS_TVALID;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
input [WIDTH*HEIGHT-1:0] in_data;
input in_valid;
output in_ready;
// State params
reg state;
localparam Wait = 0;
localparam Write = 1;
// Internal values
reg [DWIDTH - 1:0] buffer [WIDTH*HEIGHT-1:0];
reg [31:0] counter;
assign M_AXIS_TVALID = (state == Write);
assign M_AXIS_TDATA = buffer[counter];
assign in_ready = (state == Wait);
// Write state machine
always @(posedge clk) begin
if (!rstn) begin
counter <= 32'h00000000;
state <= Wait;
end else begin
case (state)
Wait: begin
if (in_valid == 1) begin
state <= Write;
end else begin
state <= Wait;
end
end
Write: begin
if (M_AXIS_TREADY == 1) begin
if (counter == WIDTH*HEIGHT-1) begin
counter <= 0;
state <= Wait;
end else begin
counter <= counter + 1;
end
end else begin
counter <= counter;
end
end
endcase
end
end
// Color conversion to binary values because Veriloc can't pass 2D arrays as I/O
genvar i;
generate
for (i = 0; i < WIDTH*HEIGHT; i=i+1) begin : converter_block
always @(posedge clk) begin
if (state == Wait && in_valid == 1) begin
buffer[i] <= (in_data[i] == 1)? alive_color : dead_color;
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a[n + 1]; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); int ans = 0; for (int i = 1; i <= k; i++) ans += a[i]; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t; long long l, r; inline void solve() { cin >> t; while (t--) { cin >> l >> r; long long ans = l; for (int i = 0; i <= 62; ++i) { if (ans + (1ll << i) <= r && (ans & (1ll << i)) == 0) { ans += (1ll << i); } } cout << ans << endl; } } int main() { solve(); return 0; }
|
`define SNIFFER 3'b000
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
`define FAKE_READER 3'b101
`define FAKE_TAG 3'b110
`include "relay_mode.v"
`include "relay_decode.v"
`include "relay_encode.v"
module relay (
clk,
reset,
data_in,
hi_simulate_mod_type,
mod_type,
data_out,
relay_raw,
relay_encoded
);
input clk, reset, data_in;
input [2:0] hi_simulate_mod_type;
output [2:0] mod_type;
output data_out;
input relay_raw;
output relay_encoded;
wire [3:0] data_in_decoded;
reg [2:0] previous_mod_type;
wire mod_switched;
assign mod_switched = (previous_mod_type == `READER_MOD && mod_type == `READER_LISTEN) || (previous_mod_type == `TAGSIM_MOD && mod_type == `TAGSIM_LISTEN);
always @(posedge clk)
begin
previous_mod_type = mod_type;
end
relay_mode rm(
clk,
data_in_decoded,
data_in_available,
hi_simulate_mod_type,
mod_type,
data_out
);
relay_encode re(
clk,
reset || mod_switched,
(hi_simulate_mod_type == `FAKE_READER),
(mod_type != `TAGSIM_MOD && mod_type != `READER_MOD) & relay_raw,
relay_encoded
);
relay_decode rd(
clk,
reset || mod_switched,
(hi_simulate_mod_type == `FAKE_READER),
data_in,
data_in_decoded,
data_in_available
);
endmodule
|
module Datapath(
clock,
reset,
instrucao,
outALU,
);
input clock, reset;
output reg [31:0] outALU, instrucao;
always @ (*) begin
instrucao = instruction;
outALU = aluOut;
end
wire [31:0] instruction, outPC, outDataMemory, ioOut, mux2Out, muxRegisterBankOut, data;
wire signed [31:0] rsValue, rtValue, immediate22Extended, operand2, aluOut;
wire signed [21:0] immediate22;
wire [4:0] rsAddress, rtAddress, rdAddress, opcode, controlALU;
wire [1:0] muxPC, muxData, ioOp;
wire jump, branch, out, writeEnableRegs, writeEnable, readEnable;
PC instance_PC (
.clock(clock),
.reset(reset),
.branch(branch),
.jump(jump),
.muxPC(muxPC),
.outPC(outPC)
);
InstructionMemory instance_InstructionMemory(
.PCAddress(outPC),
.rsAddress(rsAddress),
.rtAddress(rtAddress),
.rdAddress(rdAddress),
.immediate22(immediate22),
.opcode(opcode),
.outInstruction(instruction)
);
ControlUnit instance_ControlUnit(
.clock(clock),
.reset(reset),
.muxPC(muxPC),
.muxData(muxData),
.muxOperand(muxOperand),
.controALU(controlALU),
.writeEnableRegs(writeEnableRegs),
.writeEnable(writeEnable),
.readEnable(readEnable),
.opcode(opcode),
.ioOp(ioOp)
);
RegisterBank instance_RegisterBank (
.clock(clock),
.rsAddress(rsAddress),
.rtAddress(rtAddress),
.rdAddress(rdAddress),
.data(muxRegisterBankOut),
.registerWrite(writeEnable),//Controle UC
.outData1(rsValue),
.outData2(rtValue)
);
Extender instance_Extender (
.in(immediate22),
.out(immediate22Extended)
);
muxOperand2 instance_muxOperand2 (
.mux(muxData), //Controle UC
.rt(rtValue),
.immediate22(immediate22Extended),
.out(operand2)
);
ALU instance_ALU (
.controlALU(controlALU), //Controle UC
.rs(rsValue),
.rt(operand2),
.outALU(aluOut),
.outBranch(branch)
);
muxRegisterBank instance_muxRegisterBank (
.mux(muxData),
.aluOut(aluOut),
.memOut(memOut),
.ioOut(ioOut),
.out(muxRegisterBankOut)
);
DataMemory instance_DataMemory (
.clock(clock),
.writeEnable(writeEnable),//Controle UC
.readEnable(readEnable),//Controle UC
.data(operand2),
.address(immediate22),
.outRead(outDataMemory)
);
IO instance_IO (
.ioOp(), //Controle UC
.regValue(rsValue),
.immediate22(immediate22),
.in(rsValue),
.ioOut(ioOut),
.out(out)
);
endmodule
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge reset, posedge wr, posedge rd)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, w = 1; register char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch ^ 48), ch = getchar(); return s * w; } long long n; string s; signed main() { n = read(); cin >> s; for (register long long i = 2; i <= n; i++) { if (n % i) continue; for (register long long j = 0; j < i / 2; j++) swap(s[j], s[i - j - 1]); } cout << s << endl; return 0; }
|
/*
* File: lsu_reg2mem.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Description: MUX for store data
* Task: [TBD] comment out unneccessary access pattern(same with default), to evaluate syn result
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module lsu_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [2:0] addr;
input [`LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// big-endian memory layout
//
reg [7:0] memdata_000; // byte address 000
reg [7:0] memdata_001; // byte address 001
reg [7:0] memdata_010; // byte address 010
reg [7:0] memdata_011; // byte address 011
reg [7:0] memdata_100; // byte address 100
reg [7:0] memdata_101; // byte address 101
reg [7:0] memdata_110; // byte address 110
reg [7:0] memdata_111; // byte address 111
//
//
//
assign memdata = {memdata_111, memdata_110, memdata_101, memdata_100, memdata_011, memdata_010, memdata_001, memdata_000};
// Mux to memdata[7:0]
// in the case statement, only valid addressed patterns are listed
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b000} : memdata_000 = regdata[7:0];
{`LSUOP_SH, 3'b000} : memdata_000 = regdata[7:0];
{`LSUOP_SW, 3'b000} : memdata_000 = regdata[7:0];
{`LSUOP_SD, 3'b000} : memdata_000 = regdata[7:0];
default : memdata_000 = regdata[7:0];
endcase
end
// Mux to memdata[15:8]
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b001} : memdata_001 = regdata[7:0];
{`LSUOP_SH, 3'b000} : memdata_001 = regdata[15:8];
{`LSUOP_SW, 3'b000} : memdata_001 = regdata[15:8];
{`LSUOP_SD, 3'b000} : memdata_001 = regdata[15:8];
default : memdata_001 = regdata[15:8];
endcase
end
// Mux to memdata[23:16]
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b010} : memdata_010 = regdata[7:0];
{`LSUOP_SH, 3'b010} : memdata_010 = regdata[7:0];
{`LSUOP_SW, 3'b000} : memdata_010 = regdata[23:16];
{`LSUOP_SD, 3'b000} : memdata_010 = regdata[23:16];
default : memdata_001 = regdata[23:16];
endcase
end
// Mux to memdata[31:24]
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b011} : memdata_011 = regdata[7:0];
{`LSUOP_SH, 3'b010} : memdata_011 = regdata[15:8];
{`LSUOP_SW, 3'b000} : memdata_011 = regdata[31:24];
{`LSUOP_SD, 3'b000} : memdata_011 = regdata[31:24];
default : memdata_001 = regdata[31:24];
endcase
end
// Mux to memdata[39:32]
// in the case statement, only valid addressed patterns are listed
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b100} : memdata_100 = regdata[7:0];
{`LSUOP_SH, 3'b100} : memdata_100 = regdata[7:0];
{`LSUOP_SW, 3'b100} : memdata_100 = regdata[7:0];
{`LSUOP_SD, 3'b000} : memdata_100 = regdata[39:32];
default : memdata_000 = regdata[7:0];
endcase
end
// Mux to memdata[15:8]
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b101} : memdata_101 = regdata[7:0];
{`LSUOP_SH, 3'b100} : memdata_101 = regdata[15:8];
{`LSUOP_SW, 3'b100} : memdata_101 = regdata[15:8];
{`LSUOP_SD, 3'b000} : memdata_101 = regdata[47:40];
default : memdata_101 = regdata[47:40];
endcase
end
// Mux to memdata[23:16]
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b110} : memdata_110 = regdata[7:0];
{`LSUOP_SH, 3'b110} : memdata_110 = regdata[7:0];
{`LSUOP_SW, 3'b100} : memdata_110 = regdata[23:16];
{`LSUOP_SD, 3'b000} : memdata_110 = regdata[55:48];
default : memdata_001 = regdata[55:48];
endcase
end
// Mux to memdata[31:24]
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[2:0]}) // synopsys parallel_case
{`LSUOP_SB, 3'b111} : memdata_111 = regdata[7:0];
{`LSUOP_SH, 3'b110} : memdata_111 = regdata[15:8];
{`LSUOP_SW, 3'b100} : memdata_111 = regdata[31:24];
{`LSUOP_SD, 3'b000} : memdata_111 = regdata[63:56];
default : memdata_001 = regdata[63:56];
endcase
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Test register module for RCN Bus
// 0x00 : Bus ID
// 0x04 : Test Progress Mark
// 0x08 : Test Fail
// 0x0C : Test Pass
//
module rcn_testregs
(
input clk,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
output [31:0] test_progress,
output [31:0] test_fail,
output [31:0] test_pass
);
parameter ADDR_BASE = 0;
wire cs;
wire wr;
wire [23:0] addr;
wire [31:0] wdata;
reg [31:0] rdata;
rcn_slave_fast #(.ADDR_MASK(24'hFFFFF0), .ADDR_BASE(ADDR_BASE)) rcn_slave
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(cs),
.wr(wr),
.mask(),
.addr(addr),
.wdata(wdata),
.rdata(rdata)
);
reg [7:0] id_seq;
always @ (posedge clk)
id_seq <= {rcn_in[65:60], rcn_in[33:32]};
reg [31:0] test_progress_reg;
reg [31:0] test_fail_reg;
reg [31:0] test_pass_reg;
assign test_progress = test_progress_reg;
assign test_fail = test_fail_reg;
assign test_pass = test_pass_reg;
always @ *
case (addr[3:0])
4'h0: rdata = {24'd0, id_seq};
4'h4: rdata = test_progress_reg;
4'h8: rdata = test_fail_reg;
default: rdata = test_pass_reg;
endcase
always @ (posedge clk or posedge rst)
if (rst)
begin
test_progress_reg <= 32'd0;
test_fail_reg <= 32'd0;
test_pass_reg <= 32'd0;
end
else if (cs && wr)
case (addr[3:0])
4'h0: ;
4'h4: test_progress_reg <= wdata;
4'h8: test_fail_reg <= wdata;
default: test_pass_reg <= wdata;
endcase
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module feedforward_ST_WandB_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 5040;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./feedforward_ST_WandB_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module feedforward_ST_WandB(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd5040;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
feedforward_ST_WandB_ram feedforward_ST_WandB_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; void print_err() { cerr << n ; } template <class T, class... Arg> void print_err(T x, Arg &&...args) { cerr << x << ; print_err(args...); } template <class T> void print_container(T &cont) { for (auto iter : cont) { cerr << iter << ; } cerr << n ; } int mod = 998244353; long long ceil(long long a, long long b) { return (a + b - 1) / b; } long long gcd(long long a, long long b) { if (b == 0) { return a; } return gcd(b, a % b); } vector<int> d4x{0, 0, 1, -1}; vector<int> d4y{-1, 1, 0, 0}; vector<int> d8x{0, 0, 1, -1, 1, 1, -1, -1}; vector<int> d8y{1, -1, 0, 0, -1, 1, 1, -1}; vector<long long> B(1e5 + 1, -1), C(1e5 + 1, -1); void solve(int test) { ; int n; cin >> n; vector<int> A(n); for (int &a : A) { cin >> a; } long long ans = 0; vector<long long> dp1, dp2; int j; long long val; for (int i = n - 1; i >= 0; --i) { for (auto iter : dp1) { j = iter; val = B[j]; if (val < 0) { ; } if (val > 0) { if (j >= A[i]) { if (C[A[i]] == -1) { dp2.push_back(A[i]); C[A[i]] = val; C[A[i]] %= mod; } else { C[A[i]] += val; C[A[i]] %= mod; } } else { if (C[A[i] / ceil(A[i], j)] == -1) { dp2.push_back(A[i] / ceil(A[i], j)); C[A[i] / ceil(A[i], j)] = val; ans += (i + 1) * (ceil(A[i], j) - 1) * val; ans %= mod; C[A[i] / ceil(A[i], j)] %= mod; } else { C[A[i] / ceil(A[i], j)] += val; ans += (i + 1) * (ceil(A[i], j) - 1) * val; ans %= mod; C[A[i] / ceil(A[i], j)] %= mod; } } } B[j] = -1; } dp1.clear(); swap(dp1, dp2); swap(B, C); if (B[A[i]] == -1) { dp1.push_back(A[i]); B[A[i]] = 1; } else { B[A[i]]++; B[A[i]] %= mod; } } for (int j : dp1) { B[j] = -1; } cout << ans << endl; } int main() { int i = 1; ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int test_cases; cin >> test_cases; for (i = 1; i <= test_cases; ++i) solve(i); return 0; }
|
#include <bits/stdc++.h> using namespace std; int H, M, S, X, Y; bool A, B; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> H >> M >> S >> X >> Y; A = 1; B = 1; H = H % 12; if (X > Y) { swap(X, Y); } if (S > 5 * X && S < 5 * Y) { B = 0; } else { A = 0; } if (60 * M + S > 300 * X && 60 * M + S < 300 * Y) { B = 0; } else { A = 0; } if (120 * H + M + S > 120 * X && 120 * H + M + S < 120 * Y) { B = 0; } else { A = 0; } if (A || B) { cout << yes n ; } else { cout << no n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); long long int t; cin >> t; while (t--) { long long int n; cin >> n; vector<long long int> a(n); vector<long long int> b(n); for (long long int i = 0; i < n; i++) cin >> a[i]; for (long long int i = 0; i < n; i++) cin >> b[i]; long long int suma[n], sumb[n]; for (long long int i = 0; i < n; i++) { suma[i] = sumb[i] = 0; } suma[0] = a[0]; sumb[0] = b[0]; for (long long int i = 1; i < n; i++) suma[i] += a[i] + suma[i - 1]; for (long long int i = 1; i < n; i++) sumb[i] += b[i] + sumb[i - 1]; long long int maxf = 1e17; long long int minmaxf = 1e17; for (long long int i = 0; i < n; i++) { if (i == 0) maxf = suma[n - 1] - suma[i]; else { if (suma[n - 1] - suma[i] < sumb[i - 1]) maxf = sumb[i - 1]; else maxf = suma[n - 1] - suma[i]; } if (maxf < minmaxf) minmaxf = maxf; } cout << minmaxf << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> arr; int dp[101][101][101][2]; int solve(int index, int even, int odd, int pre) { if (index == n + 1) return 0; if (dp[index][even][odd][pre] != -1) return dp[index][even][odd][pre]; if (arr[index] != 0) { int ans = solve(index + 1, even, odd, arr[index] % 2); if (pre != -1) { if ((arr[index] % 2) != pre) ans++; } return ans; } int ans = INT_MAX; if (even > 0) { ans = min(ans, solve(index + 1, even - 1, odd, 0) + (pre == 1)); } if (odd > 0) { ans = min(ans, solve(index + 1, even, odd - 1, 1) + (pre == 0)); } dp[index][even][odd][pre] = ans; return ans; } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(NULL); cin >> n; for (int i = 0; i < 101; i++) { for (int j = 0; j < 101; j++) { for (int k = 0; k < 101; k++) { dp[i][j][k][0] = dp[i][j][k][1] = -1; } } } arr.resize(n + 1); int even = n / 2; int odd = (n + 1) / 2; for (int i = 1; i <= n; i++) { cin >> arr[i]; if (arr[i] % 2) odd--; else if (arr[i]) even--; } int ans = solve(1, even, odd, -1); cout << ans << endl; return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: pizza.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pizza (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/pizza.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/pizza.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/pizza.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_BLACKBOX_V
/**
* udp_dff$PR_pp$PG: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PG (
Q ,
D ,
CLK ,
RESET,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_BLACKBOX_V
|
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("65.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("130.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_sld_node (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter TCK_FREQ_MHZ = 20;
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
localparam IRWIDTH = 3;
input [IRWIDTH - 1:0] ir_out;
input tdo;
output reg [IRWIDTH - 1:0] ir_in;
output tck;
output reg tdi = 1'b0;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
// PHY Simulation signals
`ifndef ALTERA_RESERVED_QIS
reg simulation_clock;
reg sdrs;
reg cdr;
reg sdr;
reg e1dr;
reg udr;
reg [7:0] bit_index;
`endif
// PHY Instantiation
`ifdef ALTERA_RESERVED_QIS
sld_virtual_jtag_basic sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.tdi (tdi),
.tck (tck),
.ir_in (ir_in),
.virtual_state_cir (virtual_state_cir),
.virtual_state_pdr (virtual_state_pdr),
.virtual_state_uir (virtual_state_uir),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_e1dr (virtual_state_e1dr),
.virtual_state_e2dr (virtual_state_e2dr)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_mfg_id = 110,
sld_virtual_jtag_component.sld_type_id = 132,
sld_virtual_jtag_component.sld_version = 1,
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
sld_virtual_jtag_component.sld_sim_action = "",
sld_virtual_jtag_component.sld_sim_n_scan = 0,
sld_virtual_jtag_component.sld_sim_total_length = 0;
`endif
// PHY Simulation
`ifndef ALTERA_RESERVED_QIS
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
always
//#TCK_HALF_PERIOD_US simulation_clock = $random;
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
assign tck = simulation_clock;
assign virtual_state_cdr = cdr;
assign virtual_state_sdr = sdr;
assign virtual_state_e1dr = e1dr;
assign virtual_state_udr = udr;
task reset_jtag_state;
begin
simulation_clock = 0;
enter_data_mode;
clear_states_async;
end
endtask
task enter_data_mode;
begin
ir_in = DATA;
clear_states;
end
endtask
task enter_loopback_mode;
begin
ir_in = LOOPBACK;
clear_states;
end
endtask
task enter_debug_mode;
begin
ir_in = DEBUG;
clear_states;
end
endtask
task enter_info_mode;
begin
ir_in = INFO;
clear_states;
end
endtask
task enter_control_mode;
begin
ir_in = CONTROL;
clear_states;
end
endtask
task enter_sdrs_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_cdr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_e1dr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_udr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
tdi = 1'b0;
@(posedge tck);
end
endtask
task clear_states;
begin
clear_states_async;
@(posedge tck);
end
endtask
task clear_states_async;
begin
{cdr, sdr, e1dr, udr} = 4'b0000;
end
endtask
task shift_one_bit;
input bit_to_send;
output reg bit_received;
begin
{cdr, sdr, e1dr, udr} = 4'b0100;
tdi = bit_to_send;
@(posedge tck);
bit_received = tdo;
end
endtask
task shift_one_byte;
input [7:0] byte_to_send;
output reg [7:0] byte_received;
integer i;
reg bit_received;
begin
for (i=0; i<8; i=i+1)
begin
bit_index = i;
shift_one_bit(byte_to_send[i], bit_received);
byte_received[i] = bit_received;
end
end
endtask
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; string ans; long cnt = 0; for (long i = 0; i < s.size(); i++) { if (s[i] == t[i]) ans += 1 ; else { if (cnt % 2) ans += s[i]; else ans += t[i]; cnt++; } } int d1 = 0, d2 = 0; for (int i = 0; i < s.size(); i++) { if (s[i] != ans[i]) d1++; if (t[i] != ans[i]) d2++; } if (d1 == d2) cout << ans << endl; else cout << impossible << endl; return 0; }
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module pixelq_op_Block_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv12_438 = 12'b10000111000;
parameter ap_const_lv12_780 = 12'b11110000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_20;
reg ap_sig_bdd_82;
reg [0:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_82)) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_82)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_82))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_bdd_82)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_82)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_82)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_return_0 = ap_const_lv12_438;
assign ap_return_1 = ap_const_lv12_438;
assign ap_return_2 = ap_const_lv12_780;
assign ap_return_3 = ap_const_lv12_780;
/// ap_sig_bdd_20 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_20 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_82 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_82 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
endmodule //pixelq_op_Block_proc
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#include <bits/stdc++.h> using namespace std; int table[20][20]; int A[20] = {0, 0, 4, 6, 8, 9, 11, 13, 15, 17}; int a[20][20]; int first_x, last_x, first_y, last_y; int n, m; int ans = 0, cur = 0; void solve(int x, int y) { if (x > last_x) { if (cur > ans) { ans = cur; for (int i = 0; i <= 15; i++) for (int j = 0; j <= 15; j++) table[i][j] = a[i][j]; } return; } if (y > last_y) { solve(x + 1, first_y); return; } if (A[last_x - x] + cur <= ans) return; if (!a[x][y] && !a[x][y + 1] && !a[x][y + 2] && !a[x + 1][y + 1] && !a[x + 2][y + 1]) { a[x][y] = a[x][y + 1] = a[x][y + 2] = a[x + 1][y + 1] = a[x + 2][y + 1] = cur + 1; cur++; solve(x, y + 1); cur--; a[x][y] = a[x][y + 1] = a[x][y + 2] = a[x + 1][y + 1] = a[x + 2][y + 1] = 0; } if (!a[x][y] && !a[x + 1][y] && !a[x + 2][y] && !a[x + 1][y - 1] && !a[x + 1][y - 2]) { a[x][y] = a[x + 1][y] = a[x + 2][y] = a[x + 1][y - 1] = a[x + 1][y - 2] = cur + 1; cur++; solve(x, y + 1); cur--; a[x][y] = a[x + 1][y] = a[x + 2][y] = a[x + 1][y - 1] = a[x + 1][y - 2] = 0; } if (!a[x][y] && !a[x + 1][y] && !a[x + 2][y] && !a[x + 2][y + 1] && !a[x + 2][y - 1]) { a[x][y] = a[x + 1][y] = a[x + 2][y] = a[x + 2][y + 1] = a[x + 2][y - 1] = cur + 1; cur++; solve(x, y + 1); cur--; a[x][y] = a[x + 1][y] = a[x + 2][y] = a[x + 2][y + 1] = a[x + 2][y - 1] = 0; } if (!a[x][y] && !a[x + 1][y] && !a[x + 2][y] && !a[x + 1][y + 1] && !a[x + 1][y + 2]) { a[x][y] = a[x + 1][y] = a[x + 2][y] = a[x + 1][y + 1] = a[x + 1][y + 2] = cur + 1; cur++; solve(x, y + 1); cur--; a[x][y] = a[x + 1][y] = a[x + 2][y] = a[x + 1][y + 1] = a[x + 1][y + 2] = 0; } solve(x, y + 1); } int main() { cin >> n >> m; first_x = 2, last_x = n + 1; first_y = 2, last_y = m + 1; for (int i = 0; i <= 15; i++) a[i][0] = a[i][1] = a[i][last_y + 1] = a[i][last_y + 2] = a[0][i] = a[1][i] = a[last_x + 1][i] = a[last_x + 2][i] = 1; solve(first_x, first_y); cout << ans << endl; for (int i = first_x; i <= last_x; i++, cout << endl) for (int j = first_y; j <= last_y; j++) { if (table[i][j] == 0) cout << . ; else cout << (char)( A + table[i][j] - 1); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c; cin >> a; b = a - 1; c = a - 2; if (a >= 3) { if (b % 2 != 0) { if (a % 3 == 0) { long long e = a * b * c / 2; long long r = a * b * (c - 1) / 3; long long t = a * b * (c - 2) / 2; long long y = a * b * (c - 3); long long h = (a - 1) * (b - 1) * (c - 1); cout << max(max(max(e, r), max(t, y)), h); } else { c--; cout << a * b * c; } } else { cout << a * b * c; } } else { b = 1; c = 1; cout << a * b * c; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k, p, i, j, max = 0; cin >> n >> k >> p; long long a[n + 1]; long long b[k + 1]; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= k; i++) cin >> b[i]; sort(a + 1, a + n + 1); sort(b + 1, b + k + 1); long long x; long long ans = INT_MAX; for (i = 1; i <= k - n + 1; i++) { max = 0; for (long long l = 1; l <= n; l++) { x = abs(b[i + l - 1] - p) + abs(a[l] - b[i + l - 1]); if (x > max) max = x; } if (max < ans) ans = max; } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; const int N = 110000; int x[N], y[N]; vector<int> vec[2]; int main() { int n; scanf( %d , &n); auto prv = [&n](int x) { return (x - 1 + n) % n; }; auto nxt = [&n](int x) { return (x + 1) % n; }; for (int i = 0; i < n; i++) scanf( %d%d , &x[i], &y[i]); for (int T = 0; T < 2; T++) { if (T) for (int i = 0; i < n; i++) swap(x[i], y[i]); int id, miy = 1e8; for (int i = 0; i < n; i++) if (miy > y[i]) miy = y[i], id = i; int lid = id, rid = id; while (y[prv(lid)] == miy) lid = prv(lid); while (y[nxt(rid)] == miy) rid = nxt(rid); vec[T].push_back(abs(x[lid] - x[rid]) + 1); int now_y = miy; while (1) { ++now_y; if (y[prv(lid)] == now_y) lid = prv(lid); if (y[nxt(rid)] == now_y) rid = nxt(rid); if (y[prv(lid)] <= y[lid]) { vec[T].push_back(abs(x[lid] - x[rid]) + 1); break; } double lx = (1.0 * x[lid] * (y[prv(lid)] - now_y) + 1.0 * x[prv(lid)] * (now_y - y[lid])) / (y[prv(lid)] - y[lid]); double rx = (1.0 * x[rid] * (y[nxt(rid)] - now_y) + 1.0 * x[nxt(rid)] * (now_y - y[rid])) / (y[nxt(rid)] - y[rid]); if (lx > rx) swap(lx, rx); vec[T].push_back(floor(rx) - ceil(lx) + 1); } } long long all = 0; for (auto &t : vec[0]) all += t; double ans = 0; for (int T = 0; T < 2; T++) { double sum0 = 0, sum1 = 0, sum2 = 0; int k = 0; for (auto &t : vec[T]) { sum0 += t; sum1 += 1.0 * k * t; sum2 += 1.0 * k * k * t; ++k; } ans += 2 * sum2 * sum0 - 2 * sum1 * sum1; } printf( %.10lf n , ans / all / (all - 1) / 2); }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; char s[maxn], t[maxn]; int pr, mod; const int prs[60] = { 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409}; const int mods[100] = { 998244521, 998244523, 998244529, 998244601, 998244617, 998244619, 998244631, 998244649, 998244673, 998244677, 998244679, 998244707, 998244713, 998244749, 998244761, 998244787, 998244799, 998244803, 998244839, 998244853, 998244889, 998244893, 998244899, 998244911, 998244943, 998244967, 998244991, 998245037, 998245063, 998245091, 998245097, 998245099, 998245109, 998245111, 998245141, 998245147, 998245153, 998245159, 998245169, 998245177, 998245189, 998245207, 998245211, 998245223, 998245247, 998245331, 998245349, 998245373, 998245403, 998245463, 998245481, 998245483, 998245487, 998245489, 998245531, 998245543, 998245553, 998245571, 998245613, 998245631, 998245639, 998245687, 998245697, 998245709, 998245711, 998245733, 998245739, 998245757, 998245777, 998245799, 998245837, 998245867, 998245877, 998245909, 998245943, 998245949, 998245981, 998246021, 998246047, 998246071, 998246077, 998246101, 998246129, 998246143, 998246177, 998246189, 998246191, 998246237, 998246251, 998246257, 998246261, 998246267, 998246279, 998246317, 998246363, 998246369, 998246371, 998246387, 998246399, 998246401}; int ht[maxn], pw[maxn]; vector<int> pos[2]; int hash_t(int l, int r) { if (l == 0) return ht[r]; return (ht[r] - pw[r - l + 1] * 1ll * ht[l - 1] % mod + mod) % mod; } int main() { srand(time(0) + clock()); pr = prs[rand() % 60], mod = mods[rand() % 100]; scanf( %s , s); scanf( %s , t); int n = strlen(s), m = strlen(t), c0 = 0, c1 = 0; if (s[0] == 1 ) { for (int i = 0; i < n; ++i) { if (s[i] == 0 ) s[i] = 1 ; else s[i] = 0 ; } } for (int i = 0; i < n; ++i) { if (s[i] == 0 ) ++c0; if (s[i] == 1 ) ++c1; pos[s[i] - 0 ].push_back(i); } if (pos[0].size() == 0 || pos[1].size() == 0) { puts( 0 ); return 0; } ht[0] = t[0]; for (int i = 1; i < m; ++i) ht[i] = (1ll * ht[i - 1] * pr + t[i]) % mod; pw[0] = 1; int ans = 0; for (int i = 1; i < maxn; ++i) pw[i] = pw[i - 1] * 1ll * pr % mod; for (int x = 1; x * c0 < m; ++x) { if ((m - x * c0) % c1 != 0) continue; int y = (m - x * c0) / c1; int hx = hash_t(0, x - 1); int hy = hash_t(pos[1][0] * x, pos[1][0] * x + y - 1); int real_t = 0; if (hx == hy) continue; for (int j = 0; j < n; ++j) { if (s[j] == 0 ) real_t = (real_t * 1ll * pw[x] + hx) % mod; else real_t = (real_t * 1ll * pw[y] + hy) % mod; } if (real_t == ht[m - 1]) ++ans; } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k, c; cin >> n >> k >> c; int p = ((n * k * c) / 100); int k1 = p / k; int k2 = p % k; for (int i = 0; i < n; i++) { if (i != 0) cout << ; if (i < k1) cout << k; else if (i == k1) cout << k2; else cout << 0; } cout << endl; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9643_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
// processor control signals
adc_ddr_edgesel,
adc_pin_mode,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [13:0] adc_data_a;
output [13:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
input adc_pin_mode;
// delay control signals
input up_clk;
input [14:0] up_dld;
input [74:0] up_dwdata;
output [74:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [13:0] adc_data_p = 'd0;
reg [13:0] adc_data_n = 'd0;
reg [13:0] adc_data_p_d = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or_p_d = 'd0;
reg [13:0] adc_data_mux_a = 'd0;
reg [13:0] adc_data_mux_b = 'd0;
reg adc_or_mux_a = 'd0;
reg adc_or_mux_b = 'd0;
reg [13:0] adc_data_a = 'd0;
reg [13:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
// internal signals
wire [13:0] adc_data_p_s;
wire [13:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
// two data pin modes are supported-
// mux - across clock edges (rising or falling edges),
// mux - within clock edges (lower 7 bits and upper 7 bits)
always @(posedge adc_clk) begin
adc_status <= 1'b1;
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_p_d <= adc_data_p;
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
adc_or_p_d <= adc_or_p;
end
always @(posedge adc_clk) begin
if (adc_ddr_edgesel == 1'b1) begin
adc_data_mux_a <= adc_data_p_d;
adc_data_mux_b <= adc_data_n;
adc_or_mux_a <= adc_or_p_d;
adc_or_mux_b <= adc_or_n;
end else begin
adc_data_mux_a <= adc_data_n;
adc_data_mux_b <= adc_data_p;
adc_or_mux_a <= adc_or_n;
adc_or_mux_b <= adc_or_p;
end
end
always @(posedge adc_clk) begin
if (adc_pin_mode == 1'b1) begin
adc_data_a <= adc_data_mux_a;
adc_data_b <= adc_data_mux_b;
adc_or_a <= adc_or_mux_a;
adc_or_b <= adc_or_mux_b;
end else begin
adc_data_a <= { adc_data_mux_b[13], adc_data_mux_a[13],
adc_data_mux_b[12], adc_data_mux_a[12],
adc_data_mux_b[11], adc_data_mux_a[11],
adc_data_mux_b[10], adc_data_mux_a[10],
adc_data_mux_b[ 9], adc_data_mux_a[ 9],
adc_data_mux_b[ 8], adc_data_mux_a[ 8],
adc_data_mux_b[ 7], adc_data_mux_a[ 7]};
adc_data_b <= { adc_data_mux_b[ 6], adc_data_mux_a[ 6],
adc_data_mux_b[ 5], adc_data_mux_a[ 5],
adc_data_mux_b[ 4], adc_data_mux_a[ 4],
adc_data_mux_b[ 3], adc_data_mux_a[ 3],
adc_data_mux_b[ 2], adc_data_mux_a[ 2],
adc_data_mux_b[ 1], adc_data_mux_a[ 1],
adc_data_mux_b[ 0], adc_data_mux_a[ 0]};
adc_or_a <= adc_or_mux_a;
adc_or_b <= adc_or_mux_b;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[14]),
.up_dwdata (up_dwdata[74:70]),
.up_drdata (up_drdata[74:70]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e9 + 8; const long double pi = 3.14159265359; template <class T> T fac(T n) { T res = 1, i; for (i = 2; i <= n; i++) res *= i; return res; } template <class T> T lcm(T a, T b) { return (a * b) / __gcd(a, b); } template <class T> T digitsum(T x) { T sum = 0; while (x) { sum += x % 10; x /= 10; } return sum; } string tostring(long long a) { string ans; while (a) { ans += char(a % 10 + 0 ); a /= 10; } return ans; } void nPermute(string str, long long n) { sort((str).begin(), (str).end()); long long i = 1; do { if (i == n) break; i++; } while (next_permutation(str.begin(), str.end())); cout << str << endl; } vector<long long> factors(long long n) { vector<long long> f; for (long long x = 2; x * x <= n; x++) { while (n % x == 0) { f.push_back(x); n /= x; } } if (n > 1) f.push_back(n); return f; } bool prime(long long n) { if (n < 2) return false; for (long long x = 2; x * x <= n; x++) if (n % x == 0) return false; return true; } long long ncr(long long n, long long k) { long long res = 1; if (k > n - k) k = n - k; for (long long i = 0; i < k; i++) { res *= (n - i); res /= (i + 1); } return res; } tuple<long long, long long, long long> Gcd(long long a, long long b) { if (b == 0) return {1, 0, a}; else { long long x, y, g; tie(x, y, g) = Gcd(b, a % b); return {y, x - (a / b) * y, g}; } } const long long mod = 1e5; long long binpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res % m; } void solve() { long double n, r; cin >> n >> r; long double ang1 = 1 / (tan(pi / (2 * n))), ang2 = 1 / (tan(pi / n)); long double ans = (n * r * r) / (ang1 + ang2); cout << fixed << setprecision(50) << ans << endl; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); solve(); cerr << Time elapsed : << 1.0 * clock() / CLOCKS_PER_SEC << sec n ; }
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#include <bits/stdc++.h> using namespace std; long long f[1000001][4][2]; string s; signed main() { cin >> s; for (long long lst = 0; lst < 4; lst++) f[s.length()][lst][0] = f[s.length()][lst][1] = 0; f[s.length()][0][0] = f[s.length()][1][0] = f[s.length()][3][0] = 1; for (long long i = s.length() - 1; i >= 0; --i) { for (long long lst = 0; lst < 4; lst++) { f[i][lst][0] = f[i][lst][1] = 0; if (s[i] == * ) f[i][lst][1] = (f[i + 1][3][1] + f[i + 1][3][0]) % 1000000007; else if (s[i] != ? ) { long long c = s[i] - 0 ; if (lst == 3) c--; if (c >= 0 && c < 2) f[i][lst][0] = f[i + 1][s[i] - 0 ][c]; } else { long long c = (lst == 3); f[i][lst][0] = (f[i + 1][c][0] + f[i + 1][c + 1][1]) % 1000000007; f[i][lst][1] = (f[i + 1][3][1] + f[i + 1][3][0]) % 1000000007; } } } cout << (f[0][0][0] + f[0][1][1]) % 1000000007; }
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`default_nettype none
`timescale 1ns / 1ps
`include "xrs.vh"
//
// Signal Descriptions
// ===================
//
// clk_i Processor clock (also Wishbone's clock).
// reset_i 1 to reset the circuit in the next cycle.
// 0 for normal operation.
//
// Inputs from execute stage:
//
// xrs_rd_i Destination register to write to (0 if none).
//
// addr_i Address to read from or write to in memory.
// Typically hardwired to the output of the ALU.
// This is a full-width integer for ease of testing.
//
// we_i 1 for write transaction; 0 for read. Ignored
// if no memory operation is requested; see
// mem_i below.
//
// nomem_i 1 if the value presented to addr_i is intended
// to be written back to the register file.
// Mutually exclusive with mem_i. The xrs_rwe_i
// signal determines transfer size and zero/sign-
// extension.
//
// mem_i 1 if the value presented to addr_i is a proper
// memory address, and a memory transaction is to
// occur. The xrs_rwe_i signal determines transfer
// size and zero/sign-extension.
//
// At least one of nomem_i or mem_i should be asserted every idle
// clock cycle. If none are asserted, the register write-back
// stage of the pipeline will receive a bubble in the next cycle.
//
// xrs_rwe_i One of the following values, indicating both the
// size of, and the signedness of, the register writeback.
//
// XRS_RWE_NO No register writeback. [1]
// XRS_RWE_S8 Signed, 8-bit transfer.
// XRS_RWE_S16 Signed, 16-bit transfer.
// XRS_RWE_S32 Signed, 32-bit transfer.
// XRS_RWE_S64 (Un)Signed, 64-bit transfer.
// XRS_RWE_U8 Unsigned, 8-bit transfer.
// XRS_RWE_U16 Unsigned, 16-bit transfer.
// XRS_RWE_U32 Unsigned, 32-bit transfer.
//
// Note 1: XRS_RWE_NO will cause additional undefined behavior
// when used with a memory access cycle.
//
// dat_i If mem_i signals the start of a Wishbone transaction, this
// signal contains the value to be written out over wbmdat_o.
// Ignored otherwise.
//
// Outputs to Register Write-Back Stage:
//
// rwe_o Pulsed for a single cycle when dat_o holds valid data.
// Responsibility for zero- or sign-extension lies with
// the next stage. See xrs_rwe_i signal above for values.
//
// dat_o In the absence of a Wishbone transaction, this reflects
// the addr_i input. For all Wishbone transactions, this
// signal holds the value read off of the Wishbone interconnect.
// dat_o is valid if, and only if, rwe_o is asserted.
//
// rd_o Destination register to write to.
//
// Outputs to Random Control Logic:
//
// busy_o Mirrors wbmcyc_o; indicates whether or not a bus transaction
// is in progress. This signal can be used to stall the
// integer pipeline until the transfer has been completed.
//
// Wishbone Master Signals:
//
// wbmcyc_o See Wishbone B.4 Pipelined Mode specifications.
// wbmadr_o
// etc.
//
module lsu(
input clk_i,
input reset_i,
input [63:0] addr_i,
input we_i,
input nomem_i,
input mem_i,
input [2:0] xrs_rwe_i,
input [63:0] dat_i,
input [4:0] xrs_rd_i,
output busy_o,
output [2:0] rwe_o,
output [63:0] dat_o,
output [4:0] rd_o,
output [63:0] wbmadr_o,
output [15:0] wbmdat_o,
output wbmwe_o,
output wbmstb_o,
output wbmcyc_o,
output [1:0] wbmsel_o,
input wbmstall_i,
input wbmack_i,
input [15:0] wbmdat_i
);
reg [63:0] dat_o;
reg [2:0] rwe_o, xrs_rwe_r;
reg we_r;
reg [1:0] sel_r;
reg byte_r, hword_r, word_r, dword_r, unsigned_r;
reg rd_o;
reg [63:0] dat_r;
// State machine for Wishbone B.4 bus.
// I truly hate having to use so many MUXes and other
// combinatorials. But, it's the only way I can keep
// the number of clock cycles consumed under control.
// This will slow the maximum speed of the pipeline,
// however.
//
// mt3..mt0 determines which cycle of the transfer the
// master is participating on; st3..st0 serve the same
// role for the slave.
//
// At the start of a cycle, mtX and stX are both set
// (0 <= X <= 3, depending upon the size of the transfer).
// Note that bytes are treated as special cases of half-
// words.
//
// send_XXX are convenience signals indicating which
// byte lanes are valid on the Wishbone bus. These are used
// to disambiguate byte transfers from real half-word trans-
// fers, as well as to perform byte-steering logic.
reg mt0, mt1, mt2, mt3; // Master timeslots
reg st0, st1, st2, st3; // Slave timeslots
wire send_low_byte = sel_r == 2'b01;
wire send_high_byte = sel_r == 2'b10;
wire send_hword = sel_r == 2'b11;
wire byte = (xrs_rwe_i == `XRS_RWE_S8) || (xrs_rwe_i == `XRS_RWE_U8);
wire hword = (xrs_rwe_i == `XRS_RWE_S16) || (xrs_rwe_i == `XRS_RWE_U16);
wire word = (xrs_rwe_i == `XRS_RWE_S32) || (xrs_rwe_i == `XRS_RWE_U32);
wire dword = (xrs_rwe_i == `XRS_RWE_S64);
wire [1:0] sel_i = byte ? {addr_i[0], ~addr_i[0]} : {2{hword | word | dword}};
wire next_mt0 = mem_i ? (hword | byte) : (~wbmstall_i ? mt1 : mt0);
wire next_mt1 = mem_i ? word : (~wbmstall_i ? mt2 : mt1);
wire next_mt2 = mem_i ? 0 : (~wbmstall_i ? mt3 : mt2);
wire next_mt3 = mem_i ? dword : (~wbmstall_i ? 0 : mt3);
wire next_st0 = mem_i ? (hword | byte) : (st0 & ~wbmack_i) | (st1 & wbmack_i);
wire next_st1 = mem_i ? word : (st1 & ~wbmack_i) | (st2 & wbmack_i);
wire next_st2 = mem_i ? 0 : (st2 & ~wbmack_i) | (st3 & wbmack_i);
wire next_st3 = mem_i ? dword : (st3 & ~wbmack_i);
wire [15:0] byte_data = {dat_r[7:0], dat_r[7:0]};
assign wbmadr_o = ((mt0 & send_low_byte) ? addr_i : 0)
| ((mt0 & send_high_byte) ? addr_i : 0)
| ((mt0 & send_hword) ? {addr_i[63:1], 1'b0} : 0)
| (mt1 ? {addr_i[63:2], 2'b10} : 0)
| (mt2 ? {addr_i[63:3], 3'b100} : 0)
| (mt3 ? {addr_i[63:3], 3'b110} : 0);
assign wbmdat_o = ((mt0 & send_low_byte) ? byte_data : 0)
| ((mt0 & send_high_byte) ? byte_data : 0)
| ((mt0 & send_hword) ? dat_r[15:0] : 0)
| (mt1 ? dat_r[31:16] : 0)
| (mt2 ? dat_r[47:32] : 0)
| (mt3 ? dat_r[63:48] : 0);
assign wbmstb_o = mt0 | mt1 | mt2 | mt3;
assign wbmwe_o = wbmstb_o ? we_r : 0;
assign wbmsel_o = wbmstb_o ? sel_r : 0;
assign wbmcyc_o = st0 | st1 | st2 | st3;
always @(posedge clk_i) begin
dat_o <= dat_o;
rwe_o <= 0;
we_r <= we_r;
sel_r <= sel_r;
xrs_rwe_r <= xrs_rwe_r;
rd_o <= rd_o;
mt0 <= next_mt0;
mt1 <= next_mt1;
mt2 <= next_mt2;
mt3 <= next_mt3;
st0 <= next_st0;
st1 <= next_st1;
st2 <= next_st2;
st3 <= next_st3;
if(reset_i) begin
{dat_o, sel_r, rd_o} <= 0;
{mt0, mt1, mt2, mt3, st0, st1, st2, st3, we_r} <= 0;
xrs_rwe_r <= 0;
end
else begin
if(nomem_i) begin
dat_o <= addr_i;
rwe_o <= xrs_rwe_i;
rd_o <= xrs_rd_i;
end
if(mem_i) begin
dat_o <= 0;
dat_r <= dat_i;
we_r <= we_i;
sel_r <= sel_i;
xrs_rwe_r <= xrs_rwe_i;
rd_o <= xrs_rd_i;
end
if(st0 & wbmack_i & send_low_byte) begin
dat_o[7:0] <= wbmdat_i[7:0];
we_r <= 0;
sel_r <= 0;
xrs_rwe_r <= `XRS_RWE_NO;
end
if(st0 & wbmack_i & send_high_byte) begin
dat_o[7:0] <= wbmdat_i[15:8];
we_r <= 0;
sel_r <= 0;
xrs_rwe_r <= `XRS_RWE_NO;
end
if(st0 & wbmack_i & send_hword) begin
dat_o[15:0] <= wbmdat_i;
we_r <= 0;
sel_r <= 0;
xrs_rwe_r <= `XRS_RWE_NO;
end
if(st1 & wbmack_i) begin
dat_o[31:16] <= wbmdat_i;
end
if(st2 & wbmack_i) begin
dat_o[47:32] <= wbmdat_i;
end
if(st3 & wbmack_i) begin
dat_o[63:48] <= wbmdat_i;
end
if(st0 & wbmack_i) begin
rwe_o <= xrs_rwe_r;
end
end
end
assign busy_o = wbmcyc_o;
endmodule
|
//==================================================================================================
// Filename : subRecursiveKOA_1c.v
// Created On : 2016-10-27 23:29:04
// Last Modified : 2016-10-28 08:14:58
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module csubRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
// input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
localparam integer STOP_CONT = `STOP_CONT;
generate
//assign i = Stop_I;
if (SW <= STOP_CONT) begin : GENSTOP
cmult #(.SW(SW))
inst_cmult (
// .clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
module maquina_TB;
integer a;
wire ledVerde, ledVermelho;
wire [6:0] HEX;
reg [4:0] val;
reg clock;
inicial i( a[4], a[3], a[2], a[1], a[0], ledVerde, ledVermelho, HEX, clock);
//Alterando clock
always begin
clock <= 0;
#25;
clock <= 1;
#25;
end
initial begin
$display("\tSistema Porta\n");
$display(" Estado | Entrada | LG | LR | HEX");
$display("----------------------------------");
//Estado Fechado
#50
a=0;#100 // a = 00000
$write( " Fechado | %x%x%x%x%x | %x | %x |", a[4], a[3], a[2], a[1], a[0], ledVerde, ledVermelho);
if( HEX == 7'b0001110 ) $display( " F" ); if( HEX == 7'b1000000 ) $display (" O" ); if( HEX == 7'b0001000 ) $display( " A" );
//Estado Abrindo
a=22;#100 // a = 10110
$write( " Abrindo | %x%x%x%x%x | %x | %x |", a[4], a[3], a[2], a[1], a[0], ledVerde, ledVermelho);
if( HEX == 7'b0001110 ) $display( " F" ); if( HEX == 7'b1000000 ) $display (" O" ); if( HEX == 7'b0001000 ) $display( " A" );
//Estado Aberto
a=18;#100 // a = 10010
$write( " Aberto | %x%x%x%x%x | %x | %x |", a[4], a[3], a[2], a[1], a[0], ledVerde, ledVermelho);
if( HEX == 7'b0001110 ) $display( " F" ); if( HEX == 7'b1000000 ) $display (" O" ); if( HEX == 7'b0001000 ) $display( " A" );
//Estado Fechando
a=11;#100 // a = 01011
$write( "Fechando | %x%x%x%x%x | %x | %x |", a[4], a[3], a[2], a[1], a[0], ledVerde, ledVermelho);
if( HEX == 7'b0001110 ) $display( " F" ); if( HEX == 7'b1000000 ) $display (" O" ); if( HEX == 7'b0001000 ) $display( " A" );
//Estado Fechado
#50
a=3;#100 // a = 00011
$write( " Fechado | %x%x%x%x%x | %x | %x |", a[4], a[3], a[2], a[1], a[0], ledVerde, ledVermelho);
if( HEX == 7'b0001110 ) $display( " F" ); if( HEX == 7'b1000000 ) $display (" O" ); if( HEX == 7'b0001000 ) $display( " A" );
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: boolean_lut
// Project Name: PYNQ_Interface
// Target Devices: Z7020
// Description: This module allows up to 5 variables function to be reconfigured
// dynamically. The reconfiguration takes place by shifting in 32 bits
// serially, MSB first, when ce input is asserted.
// The CFGLUT5 can be chained by connecting CDO of one to the CDI of
// the next. In this design, we are using only one CFGLUT5.
//////////////////////////////////////////////////////////////////////////////////
module boolean_lut(
input wire clk,
input wire ce,
input wire [4:0] data_in,
input wire CDI,
output wire result
);
CFGLUT5 #(
.INIT(32'h80000000) // Specify initial LUT contents
) CFGLUT5_0 (
.CDO(), // Reconfiguration cascade output
// .O5(result), // 4-LUT output
.O6(result), // 5-LUT output
.CDI(CDI), // Reconfiguration data input
.CE(ce), // Reconfiguration enable input
.CLK(clk), // Clock input
.I0(data_in[0]), // Logic data input
.I1(data_in[1]), // Logic data input
.I2(data_in[2]), // Logic data input
.I3(data_in[3]), // Logic data input
.I4(data_in[4]) // Logic data input
);
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
// local paramaters used as defines
parameter TIME_START = 1'b0;
parameter TIME_CHECK = 1'b1;
reg [31:0] i;
reg r_state;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=TIME_START;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
TIME_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_state <= TIME_CHECK;
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
TIME_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
`endif // OVL_ASSERT_ON
end
end
else
i <= i-1;
// Check that the property is true
`ifdef OVL_ASSERT_ON
if (test_expr != 1'b1 &&
!(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE within specified num_cks cycles from the start_event");
end
`endif // OVL_ASSERT_ON
// go to start state on last time check
// NOTE: i == 0 at end of current simulation
// timeframe due to non-blocking assignment!
// Hence, check i == 1.
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START))
begin
r_state <= TIME_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
end
end
endcase
end
else begin
r_state <= TIME_START;
i <= {32{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
|
#include<bits/stdc++.h> #define ll long long using namespace std; ll t1,n,a[500010],mn[500010][2],f[2],sum[2],z[2]; int main(){ ll i,j,op,flag; scanf( %lld ,&t1); while(t1--){ scanf( %lld ,&n); for(i=1;i<=n;i++)scanf( %lld ,&a[i]); mn[n+1][0]=mn[n+1][1]=1e18; for(i=n;i;i--){ mn[i][0]=mn[i+1][0];mn[i][1]=mn[i+1][1]; if(i%2==0){ mn[i][0]+=a[i];mn[i][1]-=a[i]; } else{ mn[i][0]-=a[i];mn[i][1]+=a[i]; } mn[i][i%2]=min(mn[i][i%2],a[i]); } //for(i=1;i<=n;i++)printf( %d %d %d n ,i,mn[i][0],mn[i][1]); sum[0]=sum[1]=0;z[0]=z[1]=0; for(i=1;i<=n;i++){ sum[i%2]+=a[i]; op=i%2; if(sum[op]-sum[op^1]<0)break; } sum[0]=sum[1]=0; for(j=1;j<=n;j++)z[j%2]+=a[j]; if(i>n&&z[0]==z[1]){ puts( YES );continue; } //z[0]=sum[0];z[0]=sum[1]; sum[0]=sum[1]=0;flag=0; //printf( ? %d %d %d n ,i,z[0],z[1]); for(j=1;j<=min(i,n-1);j++){ if(j%2==0){ f[0]=mn[j+2][0]-a[j]+a[j+1]; f[1]=mn[j+2][1]+a[j]-a[j+1]; f[0]=min(f[0],a[j+1]); f[1]=min(f[1],a[j]-a[j+1]); } else{ f[0]=mn[j+2][0]+a[j]-a[j+1]; f[1]=mn[j+2][1]-a[j]+a[j+1]; f[0]=min(f[0],a[j]-a[j+1]); f[1]=min(f[1],a[j+1]); } //printf( %d %d %d %d %d n ,j,f[0],f[1],sum[0],sum[1]); op=j%2; if(f[0]+sum[0]-sum[1]>=0&&f[1]+sum[1]-sum[0]>=0&&z[op]-a[j]+a[j+1]==z[op^1]+a[j]-a[j+1]){ flag=1;break; } sum[j%2]+=a[j]; } if(flag)puts( YES ); else puts( NO ); } }
|
module m;
bit [0:0] a, b, c;
covergroup g;
cp_ab: coverpoint {a,b} {
bins one = {1};
bins two = {2};
}
cp_ab_if_c: coverpoint {a,b} iff c {
bins one = {1};
bins two = {2};
}
cp_ab_if_c_slice: coverpoint {a,b} iff c[0] {
bins one = {1};
bins two = {2};
}
cp_a_if_bc: coverpoint {a,b} iff {b,c} {
bins one = {1};
bins two = {2};
}
cp_a_slice : coverpoint a[0] {
bins one = {1};
bins two = {2};
}
cp_a_slice_if_b : coverpoint a[0] iff b {
bins one = {1};
bins two = {2};
}
cp_a_if_b_slice : coverpoint a iff b[0] {
bins one = {1};
bins two = {2};
}
cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] {
bins one = {1};
bins two = {2};
}
endgroup
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_M_V
`define SKY130_FD_SC_LP__A21BOI_M_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_m (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_m (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_M_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double PI = acos(-1.0); int a[100005], s[100005], dp1[100005], dp2[100005], b[100005], ans[100005]; int main() { int n, i, maxlen, k; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]), b[n - i + 1] = -a[i]; for (i = 0; i <= n; i++) s[i] = 0x3f3f3f3f; maxlen = 0; for (i = 1; i <= n; i++) { k = lower_bound(s, s + n, a[i]) - s; s[k] = a[i]; dp1[i] = k + 1; maxlen = max(maxlen, dp1[i]); } for (i = 0; i <= n; i++) s[i] = 0x3f3f3f3f; for (i = 1; i <= n; i++) { k = lower_bound(s, s + n, b[i]) - s; s[k] = b[i]; dp2[n - i + 1] = k + 1; } k = 0; memset(ans, -1, sizeof(ans)); for (i = 1; i <= n; i++) { if (dp1[i] + dp2[i] - 1 < maxlen) ans[i] = 1; else s[k++] = dp1[i]; } sort(s, s + k); for (i = 1; i <= n; i++) { if (ans[i] == 1) printf( 1 ); else { if (upper_bound(s, s + k, dp1[i]) - lower_bound(s, s + k, dp1[i]) > 1) printf( 2 ); else printf( 3 ); } } puts( ); }
|
module modexp_2N_NN
#(
parameter N = 8, //number of bits
parameter CC = 2*N*N //2*N to 2*N*N
)
(
clk,
rst,
g_init, // {m}
e_init, // {e, n}
o // o = m^e mode n
);
input clk;
input rst;
input [N-1:0] g_init;
input [2*N-1:0] e_init;
output [N-1:0] o;
reg first_one;
reg mul_pow;
reg [CC/(2*N)-1:0] start_reg;
reg [N-1:0] ereg;
reg [N-1:0] creg;
reg [N-1:0] mreg;
reg [N-1:0] nreg;
wire [CC/(2*N)-1:0] start_in;
wire [CC/(2*N)-1:0] start_in_shift;
wire [N-1:0] ein;
wire [N-1:0] y;
wire [N-1:0] x;
wire [N-1:0] mod_mult_o;
wire [N-1:0] ereg_next;
wire [N-1:0] creg_next;
wire [N-1:0] w1, w2, w3;
assign o = creg_next;
assign start_in = start_reg;
assign ein = ereg;
generate
if(CC/(2*N) > 1)
begin
assign start_in_shift = {start_in[CC/(2*N)-2:0] , start_in[CC/(2*N)-1]};
end
else
begin
assign start_in_shift = {start_in[CC/(2*N)-1]};
end
endgenerate
assign creg_next = w1;
MUX
#(
.N(N)
)
MUX_4
(
.A(mod_mult_o),
.B(creg),
.S(((first_one & ein[N-1] & mul_pow)|(first_one & ~mul_pow))),
.O(w1)
);
assign ereg_next = w2;
MUX
#(
.N(N)
)
MUX_6
(
.A({ein[N-2:0], 1'b0}),
.B(ereg),
.S(mul_pow),
.O(w2)
);
always@(posedge clk or posedge rst)
begin
if(rst)
begin
mreg <= g_init;
creg <= g_init;
nreg <= e_init[N-1:0];
ereg <= e_init[2*N-1:N];
first_one <= 0;
mul_pow <= 0;
start_reg <= 1'b1;
end
else
begin
mreg <= mreg;
nreg <= nreg;
start_reg <= start_in_shift;
if(start_in[CC/(2*N)-1])
mul_pow <= ~mul_pow;
ereg <= ereg_next;
creg <= creg_next;
if(start_in[CC/(2*N)-1])
begin
if(ein[N-1] & mul_pow)
begin
first_one <= 1;
end
end
end
end
assign x = creg;
assign w3 = creg;
MUX
#(
.N(N)
)
MUX_9
(
.A(mreg),
.B(w3),
.S(mul_pow),
.O(y)
);
modmult
#(
.N(N),
.CC(CC/(2*N))
)
modmult_1
(
.clk(clk),
.rst(rst),
.start(start_in[0]),
.x(x),
.y(y),
.n(nreg),
.o(mod_mult_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[35][1005][5]; void preprocess() { int i, j, k, l; for (i = 0; i <= 1000; i++) f[0][i][0] = f[0][i][1] = f[0][i][2] = f[0][i][3] = 0; i = 0; f[0][i][0] = f[0][i][1] = f[0][i][2] = f[0][i][3] = 1; for (i = 1; i < 31; i++) { f[i][0][0] = 1; for (j = 1; j <= 1000; j++) f[i][j][0] = f[i - 1][j - 1][2]; for (k = 1; k <= 2; k++) for (j = 0; j <= 1000; j++) { f[i][j][k] = 0; for (l = 0; l <= j; l++) f[i][j][k] = (f[i][j][k] + (((long long int)f[i][l][k - 1] * f[i][j - l][k - 1]) % 7340033)) % 7340033; } } } int finddepth(int n) { int d = 0; while (n > 1 && n % 2 != 0) { n = (n - 1) / 2; d++; } return d; } int main() { int q; int n, k; preprocess(); cin >> q; while (q--) { cin >> n >> k; cout << f[finddepth(n)][k][0] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> cnt1, cnt2; const int maxn = 1e5 * 3; int x[maxn]; int y[maxn]; int main() { int n = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; cnt1[x[i] - y[i]]++; cnt2[x[i] + y[i]]++; } long long ans = 0; for (int i = 0; i < n; i++) { long long c1 = cnt1[x[i] - y[i]]; long long c2 = cnt2[x[i] + y[i]]; ans += c1 + c2 - 2; } cout << ans / 2; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 50; const long long oo = 1e9; const long long mod = 998244353; long long dp[2][510][510], cnt[501], p[501]; int main() { int n, k; scanf( %d%d , &n, &k); dp[0][0][0] = 1; for (int i = 0; i < n; i++) { int q = i % 2; memset(dp[!q], 0, sizeof(dp[!q])); for (int j = 0; j <= n; j++) { for (int k = 0; k <= n; k++) { dp[!q][j + 1][max(j + 1, k)] = (dp[!q][j + 1][max(j + 1, k)] + dp[q][j][k]) % mod; dp[!q][1][max(k, 1)] = (dp[!q][1][max(k, 1)] + dp[q][j][k]) % mod; } } } for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) cnt[i] = (cnt[i] + dp[n % 2][j][i]) % mod; for (int i = 0; i <= n; i++) { p[i + 1] = (p[i + 1] + p[i]) % mod; p[i + 1] = (p[i + 1] + cnt[i]) % mod; } long long ans = 0; for (int i = 1; i <= n; ++i) ans = (ans + (cnt[i] * p[min(n + 1, (k - 1) / i + 1)]) % mod) % mod; ans = (ans * ((mod + 1) / 2)) % mod; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int n; int t[60], v[60]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &t[i]); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); int nrOfStonesTakenAway = 0; for (int i = 1; i <= n; i++) { if (t[i] > v[i]) nrOfStonesTakenAway += (t[i] - v[i]); } for (int i = 1; i <= n; i++) if (t[i] < v[i]) { nrOfStonesTakenAway -= (v[i] - t[i]); } if (nrOfStonesTakenAway < 0) puts( No ); else puts( Yes ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int invmod(long long int x, long long int n, long long int mod) { if (n == 0) return 1 % mod; long long int half = invmod(x, n / 2, mod); half = (half * half) % mod; if (n % 2 == 1) half = (half * (x % mod)) % mod; return half; } long long int bin(long long int a[], long long int l, long long int r, long long int x) { if (l <= r) { long long int m = l + (r - l) / 2; if (a[m] == x) return m; else if (a[m] > x) return bin(a, l, m - 1, x); else return bin(a, m + 1, r, x); } else return -1; } long long int power(long long int b, long long int e, long long int m) { if (e == 0) return 1; if (e % 2) return b * power(b * b % m, (e - 1) / 2, m) % m; else return power(b * b % m, e / 2, m); } long long int power(long long int b, long long int e) { if (e == 0) return 1; if (e % 2) return b * power(b * b, (e - 1) / 2); else return power(b * b, e / 2); } long long int ncr(long long int n, long long int r, long long int x) { if (r == 0) return 1; long long int fac[n + 1]; fac[0] = 1; for (long long int i = 1; i <= n; i++) fac[i] = fac[i - 1] * i % x; return (fac[n] * power(fac[r], x - 2, x) % x * power(fac[n - r], x - 2, x) % x) % x; } long long int ncr(long long int n, long long int p) { long long int r = min(p, n - p), rf = 1, ln = 1; for (long long int i = 1; i <= r; i++) rf = rf * i; for (long long int i = 0; i < r; i++) ln = ln * (n - i); return ln / rf; } bool sbs(pair<long long int, long long int> &a, pair<long long int, long long int> &b) { return (a.second < b.second); } bool sbds(pair<long long int, long long int> &a, pair<long long int, long long int> &b) { return (a.second > b.second); } long long int SUM(long long int a[], long long int n) { long long int sum = 0; for (long long int i = 0; i < n; i++) sum += a[i]; return sum; } long long int chkprm(long long int n) { for (long long int i = 2; i <= sqrt(n); i++) if (n % i == 0) return 0; return 1; } long long int dp[2005][2005]; long long int solve(long long int a[], long long int l1, long long int r1, long long int h, long long int l, long long int r, long long int t) { if (l1 == r1) { if (((t + a[l1]) % h) >= l && ((t + a[l1]) % h) <= r) return 1; if (((t + a[l1] - 1) % h) >= l && ((t + a[l1] - 1) % h) <= r) return 1; return 0; } if (dp[l1][t] != -1) return dp[l1][t]; long long int x1 = 0, x2 = 0; if (((t + a[l1]) % h) >= l && ((t + a[l1]) % h) <= r) x1++; if (((t + a[l1] - 1) % h) >= l && ((t + a[l1] - 1) % h) <= r) x2++; dp[l1][t] = max(x1 + solve(a, l1 + 1, r1, h, l, r, (t + a[l1]) % h), x2 + solve(a, l1 + 1, r1, h, l, r, (t + a[l1] - 1) % h)); return dp[l1][t]; } void myth() { long long int n, h, l, r; cin >> n >> h >> l >> r; long long int a[n]; for (long long int xxx = 0; xxx < n; xxx++) cin >> a[xxx]; memset(dp, -1, sizeof(dp)); cout << solve(a, 0, n - 1, h, l, r, 0); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int test_case = 1; while (test_case--) { myth(); cout << n ; } return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_EP.v
// Version : 2.3
//--
//-- Description: Endpoint Programmed I/O module.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_EP #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
input clk,
input rst_n,
// AXIS TX
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [STRB_WIDTH-1:0] s_axis_tx_tstrb,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
//AXIS RX
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [STRB_WIDTH-1:0] m_axis_rx_tstrb,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output req_compl_o,
output compl_done_o,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
);
// Local wires
wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] wr_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl;
wire req_compl_wd;
wire compl_done;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire [12:0] req_addr;
//
// ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
//
PIO_EP_MEM_ACCESS EP_MEM (
.clk(clk), // I
.rst_n(rst_n), // I
// Read Port
.rd_addr_i(rd_addr), // I [10:0]
.rd_be_i(rd_be), // I [3:0]
.rd_data_o(rd_data), // O [31:0]
// Write Port
.wr_addr_i(wr_addr), // I [10:0]
.wr_be_i(wr_be), // I [7:0]
.wr_data_i(wr_data), // I [31:0]
.wr_en_i(wr_en), // I
.wr_busy_o(wr_busy) // O
);
//
// Local-Link Receive Controller
//
PIO_64_RX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) EP_RX (
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS RX
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tstrb( m_axis_rx_tstrb ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
// Handshake with Tx engine
.req_compl_o(req_compl), // O
.req_compl_wd_o(req_compl_wd), // O
.compl_done_i(compl_done), // I
.req_tc_o(req_tc), // O [2:0]
.req_td_o(req_td), // O
.req_ep_o(req_ep), // O
.req_attr_o(req_attr), // O [1:0]
.req_len_o(req_len), // O [9:0]
.req_rid_o(req_rid), // O [15:0]
.req_tag_o(req_tag), // O [7:0]
.req_be_o(req_be), // O [7:0]
.req_addr_o(req_addr), // O [12:0]
// Memory Write Port
.wr_addr_o(wr_addr), // O [10:0]
.wr_be_o(wr_be), // O [7:0]
.wr_data_o(wr_data), // O [31:0]
.wr_en_o(wr_en), // O
.wr_busy_i(wr_busy) // I
);
//
// Local-Link Transmit Controller
//
PIO_64_TX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
)EP_TX(
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS Tx
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tstrb( s_axis_tx_tstrb ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
// Handshake with Rx engine
.req_compl_i(req_compl), // I
.req_compl_wd_i(req_compl_wd), // I
.compl_done_o(compl_done), // 0
.req_tc_i(req_tc), // I [2:0]
.req_td_i(req_td), // I
.req_ep_i(req_ep), // I
.req_attr_i(req_attr), // I [1:0]
.req_len_i(req_len), // I [9:0]
.req_rid_i(req_rid), // I [15:0]
.req_tag_i(req_tag), // I [7:0]
.req_be_i(req_be), // I [7:0]
.req_addr_i(req_addr), // I [12:0]
// Read Port
.rd_addr_o(rd_addr), // O [10:0]
.rd_be_o(rd_be), // O [3:0]
.rd_data_i(rd_data), // I [31:0]
.completer_id_i(cfg_completer_id), // I [15:0]
.cfg_bus_mstr_enable_i(cfg_bus_mstr_enable) // I
);
assign req_compl_o = req_compl;
assign compl_done_o = compl_done;
endmodule // PIO_EP
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_SYMBOL_V
`define SKY130_FD_SC_LP__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, l, v1, v2, k; int main() { cin >> n >> l >> v1 >> v2 >> k; long long g = (n + k - 1) / k; double le = 0, ri = l / (double)v1; while ((ri - le) >= 5e-7) { double mid = (le + ri) / 2; double t = 0; for (int i = 1; i <= g; i++) { double x = ((double)l - v1 * mid) / (v2 - v1); t += x; if (i != g) { double y = x * (v2 - v1) / (v1 + v2); t += y; } } if (mid > t) ri = mid; else le = mid; } cout << setprecision(9) << le << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; void dump(const vector<int>& a) { for (int i = 0; i < a.size(); i++) { cerr << a[i] << ; } cerr << endl; } vector<pair<int, int>> factorise(long long m) { vector<pair<int, int>> res; for (long long i = 2; i * i <= m; i++) { if (m % i == 0) { int cnt = 0; while (m % i == 0) { cnt++; m /= i; } res.emplace_back(i, cnt); } } return res; }; using ll = long long; ll gcd(ll a, ll b, ll& x, ll& y) { if (a == 0) { x = 0; y = 1; return b; } ll x1, y1; ll d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } bool debug = false; using pii = pair<int, int>; using pll = pair<long long, long long>; const int magic = 3; const int INF = 1e9; void solve(); void init(); template <typename T, int N> void dump(const array<T, N>& a) { for (int i = 0; i < a.size(); i++) { cerr << a[i] << ; } cerr << endl; } int main(int argc, char** argv) { cout.precision(15); int t = 1; cin >> t; init(); for (int tt = 1; tt <= t; tt++) { solve(); } return 0; } const int MX = 100500; vector<int> delim[MX]; int p[MX]; long long troek[MX]; long long dvoek(long long n) { return n * (n + 1) / 2; } void go(int n) { auto& curr = delim[n]; int pr = p[n]; if (pr == 0) { if (n == 1) { curr = {1}; } else { curr = {1, n}; } return; } int cnt = 0; while (n % pr == 0) { n /= pr; cnt++; } curr.reserve((cnt + 1) * delim[n].size()); int mult = 1; for (int i = 0; i <= cnt; i++) { for (auto div : delim[n]) { curr.push_back(mult * div); } mult *= pr; } sort(curr.begin(), curr.end()); } void init() { for (int i = 1; i < MX; i++) { troek[i] = troek[i - 1] + dvoek(i); } for (int i = 2; i * i < MX; i++) { if (p[i] == 0) { for (int j = i; j * i < MX; j++) { p[i * j] = i; } } } for (int n = 1; n < MX; n++) { go(n); } for (int n = 1; n < MX; n++) { delim[n].push_back(int(1e9)); } } int cnt[10]; int cnt2[10]; int sum[10]; int sum2[10]; long long solve_true(int a, int b, int c) { vector<decltype(delim[a].cbegin())> x(3); x[0] = delim[a].begin(); x[1] = delim[b].begin(); x[2] = delim[c].begin(); memset(cnt, 0, sizeof(cnt)); while (true) { int z = *x[0]; for (int i = 1; i < 3; i++) { z = min(z, *x[i]); } if (z > MX) { break; } int mask = 0; for (int i = 0; i < 3; i++) { if (*x[i] == z) { mask |= 1 << i; x[i]++; } } cnt[mask]++; } for (int i = 1; i < 8; i++) { if (debug) cerr << cnt[i] << ; cnt2[i] = cnt[i] * cnt[i]; sum[i] = cnt[i] + sum[i - 1]; sum2[i] = cnt2[i] + sum2[i - 1]; } if (debug) cerr << endl; long long res = troek[cnt[7]]; res += dvoek(cnt[7]) * sum[6]; res += cnt[7] * (dvoek(cnt[3]) + dvoek(cnt[5]) + dvoek(cnt[6])); res += cnt[7] * (sum[6] * sum[6] - sum2[6]) / 2; for (int i = 0; i < 3; i++) { int bit = 1 << i; res += (cnt[bit | 1] + cnt[bit | 2] + cnt[bit | 4]) * dvoek(cnt[7 - bit]); } res += cnt[3] * cnt[5] * cnt[6]; res += (cnt[3] * cnt[5] + cnt[3] * cnt[6] + cnt[5] * cnt[6]) * (cnt[1] + cnt[2] + cnt[4]); res += (cnt[3] + cnt[5] + cnt[6]) * (cnt[1] * cnt[2] + cnt[1] * cnt[4] + cnt[2] * cnt[4]); res -= cnt[3] * cnt[1] * cnt[2] + cnt[5] * cnt[1] * cnt[4] + cnt[6] * cnt[2] * cnt[4]; res += cnt[1] * cnt[2] * cnt[4]; return res; } long long slow(int a, int b, int c) { set<vector<int>> s; for (int x = 1; x <= a; x++) { if (a % x) continue; for (int y = 1; y <= b; y++) { if (b % y) continue; for (int z = 1; z <= c; z++) { if (c % z) continue; vector<int> t = {x, y, z}; sort(begin(t), end(t)); s.insert(t); } } } return s.size(); } void stress(int n = 60) { debug = false; for (int a = 1; a <= n; a++) { for (int b = a; b <= n; b++) { for (int c = b; c <= n; c++) { if (slow(a, b, c) != solve_true(a, b, c)) { cerr << a << << b << << c << endl; cerr << slow(a, b, c) << << solve_true(a, b, c) << endl; } } } } } void solve() { int a, b, c; cin >> a >> b >> c; cout << solve_true(a, b, c) << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A32OI_PP_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_PP_BLACKBOX_V
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____33.333______0.000______50.0______165.726_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_wiz_0;
wire clk_in2_clk_wiz_0;
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_clk_wiz_0;
wire clk_out2_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clk_out5_clk_wiz_0;
wire clk_out6_clk_wiz_0;
wire clk_out7_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (30.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[102][102] = {0}; int main() { int n, m, a, b, sum = -1, minsum = -1; scanf( %d%d , &n, &m); int cost[n + 1]; for (int i = 1; i <= n; i++) { scanf( %d , &cost[i]); } for (int i = 1; i <= m; i++) { scanf( %d%d , &a, &b); arr[a][b] = arr[b][a] = 1; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { for (int k = 1; k <= n; k++) { if (sum == -1 && j != k && i != j && j != k && arr[i][j] == 1 && arr[j][k] == 1 && arr[k][i] == 1) minsum = sum = cost[i] + cost[j] + cost[k]; else if (j != k && i != j && j != k && arr[i][j] == 1 && arr[j][k] == 1 && arr[k][i] == 1) { sum = cost[i] + cost[j] + cost[k]; if (minsum > sum) minsum = sum; } } } } printf( %d n , minsum); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O311A_FUNCTIONAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long int infinity = 9e18; bool possible(long long int x1, long long int x2, long long int y1, long long int y2, long long int n, long long int m, string s, long long int dx, long long int dy) { long long int a = m / n; long long int b = m % n; x1 += a * dx; y1 += a * dy; for (int i = 0; i < b; i++) { if (s[i] == U ) y1++; if (s[i] == D ) y1--; if (s[i] == R ) x1++; if (s[i] == L ) x1--; } if ((abs(y1 - y2) + abs(x1 - x2)) <= m) return 1; return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int x1, x2, y1, y2, n; cin >> x1 >> y1 >> x2 >> y2 >> n; string s; cin >> s; long long int dx = 0, dy = 0; for (int i = 0; i < n; i++) { if (s[i] == U ) dy++; if (s[i] == D ) dy--; if (s[i] == R ) dx++; if (s[i] == L ) dx--; } long long int st = 0, end = 1e18; while (st < end) { long long int mid = (end + st) / 2; if (possible(x1, x2, y1, y2, n, mid, s, dx, dy)) { end = mid; } else { st = mid + 1; } } if (st == 1e18) cout << -1; else cout << st; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100050; struct str { int pre[26], suf[26], mx[26], len; str() {} void Build(char s[], int n) { len = n; for (int i = 0; i < 26; i++) pre[i] = suf[i] = mx[i] = 0; int len = 0; for (int i = 1; i <= n; i++) { if (i != 1 && s[i] == s[i - 1]) len++; else len = 1; mx[s[i] - a ] = max(mx[s[i] - a ], len); } for (int i = 0; i < 26; i++) { while (pre[i] < n && s[pre[i] + 1] == a + i) pre[i]++; while (suf[i] < n && s[n - suf[i]] == a + i) suf[i]++; } } } STR[N]; str operator*(str x, str y) { str ans; ans.len = y.len * (x.len + 1) + x.len; for (int i = 0; i < 26; i++) { if (y.pre[i] == y.len) { if (x.pre[i] == x.len) ans.pre[i] = ans.len; else ans.pre[i] = y.len * (x.pre[i] + 1) + x.pre[i]; if (x.suf[i] == x.len) ans.suf[i] = ans.len; else ans.suf[i] = y.len * (x.suf[i] + 1) + x.suf[i]; ans.mx[i] = y.len * (x.mx[i] + 1) + x.mx[i]; } else { ans.pre[i] = y.pre[i]; ans.suf[i] = y.suf[i]; if (x.mx[i] > 0) ans.mx[i] = y.pre[i] + y.suf[i] + 1; else ans.mx[i] = y.mx[i]; ans.mx[i] = max(ans.mx[i], y.mx[i]); } } return ans; } char s[N]; int main() { int n, len, i; scanf( %i , &n); for (i = 1; i <= n; i++) { scanf( %s , s + 1); len = strlen(s + 1); STR[i].Build(s, len); } for (i = 2; i <= n; i++) { STR[1] = STR[1] * STR[i]; } int ans = 0; for (i = 0; i < 26; i++) ans = max(ans, STR[1].mx[i]); printf( %i n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 15e4 + 4; const int MAXQ = MAXN; const int MAXK = 6 + 2; int n, k, q; int t[MAXN]; set<int, greater<int> > st; int main() { scanf( %d%d%d , &n, &k, &q); for (int i = 0; i < n; ++i) scanf( %d , t + i); while (q--) { int op, id; scanf( %d%d , &op, &id); --id; if (op == 1) { st.insert(t[id]); } else { if (!st.count(t[id])) { puts( NO ); continue; } int cnt = k; bool ok = false; for (auto it : st) { if (it == t[id]) { puts( YES ); ok = true; break; } --cnt; if (ok) break; if (cnt == 0) break; } if (!ok) puts( NO ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { double n, m; scanf( %lf %lf , &n, &m); printf( %.6lf , pow(1.000000011, m) * n); }
|
// Check assignment operations in constant functions.
module constfunc7();
function real i_to_r(input signed [3:0] value);
i_to_r = value + 0.5;
endfunction
function signed [3:0] r_to_i(input real value);
r_to_i = value;
endfunction
function real u_to_r(input [3:0] value);
u_to_r = value + 0.5;
endfunction
function [3:0] r_to_u(input real value);
r_to_u = value;
endfunction
function [3:0] i_to_u(input signed [3:0] value);
i_to_u = value;
endfunction
function signed [3:0] u_to_i(input [3:0] value);
u_to_i = value;
endfunction
function [5:0] si_to_lu(input signed [3:0] value);
si_to_lu = value;
endfunction
function signed [5:0] su_to_li(input [3:0] value);
su_to_li = value;
endfunction
function [3:0] li_to_su(input signed [5:0] value);
li_to_su = value;
endfunction
function signed [3:0] lu_to_si(input [5:0] value);
lu_to_si = value;
endfunction
localparam i_to_r_res1 = i_to_r(-9);
localparam i_to_r_res2 = i_to_r(-8);
localparam i_to_r_res3 = i_to_r( 7);
localparam i_to_r_res4 = i_to_r( 8);
localparam r_to_i_res1 = r_to_i(-8.5);
localparam r_to_i_res2 = r_to_i(-7.5);
localparam r_to_i_res3 = r_to_i( 6.5);
localparam r_to_i_res4 = r_to_i( 7.5);
localparam u_to_r_res1 = u_to_r(-1);
localparam u_to_r_res2 = u_to_r( 1);
localparam u_to_r_res3 = u_to_r(15);
localparam u_to_r_res4 = u_to_r(17);
localparam r_to_u_res1 = r_to_u(-0.5);
localparam r_to_u_res2 = r_to_u( 0.5);
localparam r_to_u_res3 = r_to_u(14.5);
localparam r_to_u_res4 = r_to_u(16.5);
localparam i_to_u_res1 = i_to_u(-9);
localparam i_to_u_res2 = i_to_u(-8);
localparam i_to_u_res3 = i_to_u( 7);
localparam i_to_u_res4 = i_to_u( 8);
localparam u_to_i_res1 = u_to_i(-1);
localparam u_to_i_res2 = u_to_i( 1);
localparam u_to_i_res3 = u_to_i(15);
localparam u_to_i_res4 = u_to_i(17);
localparam si_to_lu_res1 = si_to_lu(-9);
localparam si_to_lu_res2 = si_to_lu(-8);
localparam si_to_lu_res3 = si_to_lu( 7);
localparam si_to_lu_res4 = si_to_lu( 8);
localparam su_to_li_res1 = su_to_li(-1);
localparam su_to_li_res2 = su_to_li( 1);
localparam su_to_li_res3 = su_to_li(15);
localparam su_to_li_res4 = su_to_li(17);
localparam li_to_su_res1 = li_to_su(-9);
localparam li_to_su_res2 = li_to_su(-8);
localparam li_to_su_res3 = li_to_su( 7);
localparam li_to_su_res4 = li_to_su( 8);
localparam lu_to_si_res1 = lu_to_si(-1);
localparam lu_to_si_res2 = lu_to_si( 1);
localparam lu_to_si_res3 = lu_to_si(15);
localparam lu_to_si_res4 = lu_to_si(17);
reg failed;
initial begin
failed = 0;
$display("%0g", i_to_r_res1); if (i_to_r_res1 != 7.5) failed = 1;
$display("%0g", i_to_r_res2); if (i_to_r_res2 != -7.5) failed = 1;
$display("%0g", i_to_r_res3); if (i_to_r_res3 != 7.5) failed = 1;
$display("%0g", i_to_r_res4); if (i_to_r_res4 != -7.5) failed = 1;
$display("");
$display("%0d", r_to_i_res1); if (r_to_i_res1 !== 7) failed = 1;
$display("%0d", r_to_i_res2); if (r_to_i_res2 !== -8) failed = 1;
$display("%0d", r_to_i_res3); if (r_to_i_res3 !== 7) failed = 1;
$display("%0d", r_to_i_res4); if (r_to_i_res4 !== -8) failed = 1;
$display("");
$display("%0g", u_to_r_res1); if (u_to_r_res1 != 15.5) failed = 1;
$display("%0g", u_to_r_res2); if (u_to_r_res2 != 1.5) failed = 1;
$display("%0g", u_to_r_res3); if (u_to_r_res3 != 15.5) failed = 1;
$display("%0g", u_to_r_res4); if (u_to_r_res4 != 1.5) failed = 1;
$display("");
$display("%0d", r_to_u_res1); if (r_to_u_res1 !== 15) failed = 1;
$display("%0d", r_to_u_res2); if (r_to_u_res2 !== 1) failed = 1;
$display("%0d", r_to_u_res3); if (r_to_u_res3 !== 15) failed = 1;
$display("%0d", r_to_u_res4); if (r_to_u_res4 !== 1) failed = 1;
$display("");
$display("%0d", i_to_u_res1); if (i_to_u_res1 !== 7) failed = 1;
$display("%0d", i_to_u_res2); if (i_to_u_res2 !== 8) failed = 1;
$display("%0d", i_to_u_res3); if (i_to_u_res3 !== 7) failed = 1;
$display("%0d", i_to_u_res4); if (i_to_u_res4 !== 8) failed = 1;
$display("");
$display("%0d", u_to_i_res1); if (u_to_i_res1 !== -1) failed = 1;
$display("%0d", u_to_i_res2); if (u_to_i_res2 !== 1) failed = 1;
$display("%0d", u_to_i_res3); if (u_to_i_res3 !== -1) failed = 1;
$display("%0d", u_to_i_res4); if (u_to_i_res4 !== 1) failed = 1;
$display("");
$display("%0d", si_to_lu_res1); if (si_to_lu_res1 !== 7) failed = 1;
$display("%0d", si_to_lu_res2); if (si_to_lu_res2 !== 56) failed = 1;
$display("%0d", si_to_lu_res3); if (si_to_lu_res3 !== 7) failed = 1;
$display("%0d", si_to_lu_res4); if (si_to_lu_res4 !== 56) failed = 1;
$display("");
$display("%0d", su_to_li_res1); if (su_to_li_res1 !== 15) failed = 1;
$display("%0d", su_to_li_res2); if (su_to_li_res2 !== 1) failed = 1;
$display("%0d", su_to_li_res3); if (su_to_li_res3 !== 15) failed = 1;
$display("%0d", su_to_li_res4); if (su_to_li_res4 !== 1) failed = 1;
$display("");
$display("%0d", li_to_su_res1); if (li_to_su_res1 !== 7) failed = 1;
$display("%0d", li_to_su_res2); if (li_to_su_res2 !== 8) failed = 1;
$display("%0d", li_to_su_res3); if (li_to_su_res3 !== 7) failed = 1;
$display("%0d", li_to_su_res4); if (li_to_su_res4 !== 8) failed = 1;
$display("");
$display("%0d", lu_to_si_res1); if (lu_to_si_res1 !== -1) failed = 1;
$display("%0d", lu_to_si_res2); if (lu_to_si_res2 !== 1) failed = 1;
$display("%0d", lu_to_si_res3); if (lu_to_si_res3 !== -1) failed = 1;
$display("%0d", lu_to_si_res4); if (lu_to_si_res4 !== 1) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)
(uart_tx, ledout,
sys_clk_i, sys_rst_i,ledres,micLRSel,trigg,echo);
input sys_clk_i, sys_rst_i;
output uart_tx;
output ledout;
output ledres;
output micLRSel;
output trigg;
input echo;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:5]cs; // CHIP-SELECT
wire [15:0] mult_dout;
wire [15:0] div_dout;
wire uart_dout; // misma señal que uart_busy from uart.v
wire [15:0] dp_ram_dout;
wire [15:0] ultra_dout;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_mult per_m (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[2]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(mult_dout) );
peripheral_div per_d (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[3]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(div_dout));
peripheral_uart per_u (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(uart_dout), .uart_tx(uart_tx), .ledout(ledout));
peripheral_ultra per_ultra ( .clk(sys_clk_i) , .rst(sys_rst_i) , .d_in(j1_io_dout) , .cs(cs[1]) , .addr(j1_io_addr[3:0]) , .rd(j1_io_rd) , .wr(j1_io_wr), .d_out(ultra_dout), .trigg(trigg), .echo(echo) );
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[5]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h64: cs= 7'b10000; //ultra
8'h67: cs= 7'b01000; //mult
8'h68: cs= 7'b00100; //div
8'h69: cs= 7'b00010; //uart
8'h70: cs= 7'b00001; //dp_ram
default: cs= 3'b000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
5'b10000: j1_io_din = ultra_dout;
5'b0001000: j1_io_din = mult_dout;
5'b0000100: j1_io_din = div_dout;
5'b0000010: j1_io_din = uart_dout;
5'b0000001: j1_io_din = dp_ram_dout;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND2_BEHAVIORAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2 (
Y ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > a[100010]; vector<int> ans; string s, s1, s2; int n, m; int v, e, p, q; int main() { cin >> n; if (n == 2) { cout << 0; return 0; } int ans = n / 2 - 1; if (n % 2) ans++; cout << ans; }
|
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