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#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; int main(void) { int n, q, a, b; scanf( %d%d%d%d , &n, &q, &a, &b); vector<int> x(n); for (int i = 0; i < n; ++i) { scanf( %d , &x[i]); } vector<double> y(n); vector<int> from(n, -1); y[0] = x[0]; for (int i = 1; i < n; ++i) { double shiftSum = 0.0; shiftSum = 0.0; double curPos = x[i]; int j; double shift = 0.0; double maxShift = q - curPos; double minShift = 1.0 - curPos; for (j = i - 1; j >= 0; j--) { shift = max(minShift, min(maxShift, shiftSum / (i - j))); double pos = curPos + shift; if (pos >= y[j] + a - eps && pos <= y[j] + b + eps) break; if (pos >= y[j] + b) { curPos -= b; } else { curPos -= a; } minShift = max(minShift, 1.0 - curPos); shiftSum += x[j] - curPos; } shift = max(minShift, min(maxShift, shiftSum / (i - j))); y[i] = x[i] + shift; from[i] = j; } vector<double> ry(n); for (int i = n - 1; i >= 0;) { double shift = y[i] - x[i]; ry[i] = y[i]; for (int j = i - 1; j > from[i]; --j) { if (ry[j + 1] >= y[j] + b) ry[j] = ry[j + 1] - b; else ry[j] = ry[j + 1] - a; } i = from[i]; } double res = 0.0; for (int i = 0; i < n; ++i) { double d = ry[i] - x[i]; res += d * d; printf( %.9lf , ry[i]); } printf( n%.9lf n , res); }
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#include <bits/stdc++.h> using namespace std; const int N = 1e9 + 1; const long double pi = 3.1415926535897; void solve() { int n, ans(0); cin >> n; int a[n], b[5001] = {0}; for (int i = 0; i < n; i++) { cin >> a[i]; if (b[a[i]] == 0) b[a[i]] = 1; } for (int i = 1; i < n + 1; i++) if (!b[i]) ans++; cout << ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_TB_V
`define SKY130_FD_SC_LP__EBUFN_TB_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_TB_V
|
module FpuFpD_Mul(
/* verilator lint_off UNUSED */
clk,
enable,
srca,
srcb,
dst
);
input clk;
input enable;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
reg sgna;
reg sgnb;
reg sgnc;
reg[12:0] exa;
reg[12:0] exb;
reg[12:0] exc;
`ifdef PRECISE_FMUL
reg[105:0] tFracA;
reg[105:0] tFracB;
reg[105:0] tFracC1;
reg[63:0] tFracC;
`else
reg[63:0] tFracA;
reg[63:0] tFracB;
reg[63:0] tFracC;
`endif
reg[51:0] tFracC2;
//reg[41:0] tFracAL;
//reg[41:0] tFracBL;
//reg[41:0] tFracCL;
//reg[63:0] tFracCL2;
reg[63:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
sgna=srca[63];
sgnb=srcb[63];
exa[10:0]=srca[62:52];
exb[10:0]=srcb[62:52];
exa[12:11]=0;
exb[12:11]=0;
sgnc=sgna^sgnb;
`ifdef PRECISE_FMUL
tFracA[105:52]=1;
tFracB[105:52]=1;
`else
tFracA[63:52]=1;
tFracB[63:52]=1;
`endif
tFracA[51:0]=srca[51:0];
tFracB[51:0]=srcb[51:0];
`ifdef PRECISE_FMUL
tFracC1=tFracA*tFracB;
tFracC=tFracC1[105:42]+64'h3FF;
`else
// tFracC=(tFracA>>21)*(tFracB>>21);
tFracC=
{21'h0, tFracA[63:21]} *
{21'h0, tFracB[63:21]};
`endif
if(tFracC[63])
begin
tFracC2[51:0]=tFracC[62:11];
exc=exa+exb-1022;
end
else
begin
tFracC2[51:0]=tFracC[61:10];
exc=exa+exb-1023;
end
if(exc[12])
begin
tDst=0;
end
else
if(exc[11])
begin
tDst[63]=sgnc;
tDst[62:0]=63'h7FF0_0000_0000_0000;
end
else
begin
tDst[63]=sgnc;
tDst[62:52]=exc[10:0];
tDst[51: 0]=tFracC2[51:0];
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= #Tp 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= #Tp 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= #Tp 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= #Tp 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= #Tp 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= #Tp 1'b1;
else
TxCtrlEndFrm <= #Tp 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= #Tp 1'b1;
else
if(TxDoneIn)
CtrlMux <= #Tp 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= #Tp 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= #Tp 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= #Tp 1'b0;
else
TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= #Tp 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= #Tp 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= #Tp 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= #Tp ControlEnd;
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= #Tp 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= #Tp 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= #Tp 6'h0;
else
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= #Tp 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_P_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DFF_P_BLACKBOX_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int inf = INT_MAX; const long long int INF = LLONG_MAX; const long long int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int dp[151][10]; dp[1][0] = 1; dp[2][0] = 2; dp[3][0] = 3; dp[4][0] = 4; dp[5][0] = 5; dp[6][0] = 6; dp[7][0] = 7; dp[8][0] = 8; dp[9][0] = 9; dp[10][0] = 19; dp[11][0] = 29; dp[12][0] = 39; dp[13][0] = 49; dp[14][0] = 59; dp[15][0] = 69; dp[16][0] = 79; dp[17][0] = 89; dp[18][0] = 99; dp[19][0] = 199; dp[20][0] = 299; dp[21][0] = 399; dp[22][0] = 499; dp[23][0] = 599; dp[24][0] = 699; dp[25][0] = 799; dp[26][0] = 899; dp[27][0] = 999; dp[28][0] = 1999; dp[29][0] = 2999; dp[30][0] = 3999; dp[31][0] = 4999; dp[32][0] = 5999; dp[33][0] = 6999; dp[34][0] = 7999; dp[35][0] = 8999; dp[36][0] = 9999; dp[37][0] = 19999; dp[38][0] = 29999; dp[39][0] = 39999; dp[40][0] = 49999; dp[41][0] = 59999; dp[42][0] = 69999; dp[43][0] = 79999; dp[44][0] = 89999; dp[45][0] = 99999; dp[46][0] = 199999; dp[47][0] = 299999; dp[48][0] = 399999; dp[49][0] = 499999; dp[50][0] = 599999; dp[51][0] = 699999; dp[52][0] = 799999; dp[53][0] = 899999; dp[54][0] = 999999; dp[55][0] = 1999999; dp[56][0] = 2999999; dp[57][0] = 3999999; dp[58][0] = 4999999; dp[59][0] = 5999999; dp[60][0] = 6999999; dp[61][0] = 7999999; dp[62][0] = 8999999; dp[63][0] = 9999999; dp[64][0] = 19999999; dp[65][0] = 29999999; dp[66][0] = 39999999; dp[67][0] = 49999999; dp[68][0] = 59999999; dp[69][0] = 69999999; dp[70][0] = 79999999; dp[71][0] = 89999999; dp[72][0] = 99999999; dp[73][0] = 199999999; dp[74][0] = 299999999; dp[75][0] = 399999999; dp[76][0] = 499999999; dp[77][0] = 599999999; dp[78][0] = 699999999; dp[79][0] = 799999999; dp[80][0] = 899999999; dp[81][0] = 999999999; dp[82][0] = 1999999999; dp[83][0] = 2999999999; dp[84][0] = 3999999999; dp[85][0] = 4999999999; dp[86][0] = 5999999999; dp[87][0] = 6999999999; dp[88][0] = 7999999999; dp[89][0] = 8999999999; dp[90][0] = 9999999999; dp[91][0] = 19999999999; dp[92][0] = 29999999999; dp[93][0] = 39999999999; dp[94][0] = 49999999999; dp[95][0] = 59999999999; dp[96][0] = 69999999999; dp[97][0] = 79999999999; dp[98][0] = 89999999999; dp[99][0] = 99999999999; dp[100][0] = 199999999999; dp[101][0] = 299999999999; dp[102][0] = 399999999999; dp[103][0] = 499999999999; dp[104][0] = 599999999999; dp[105][0] = 699999999999; dp[106][0] = 799999999999; dp[107][0] = 899999999999; dp[108][0] = 999999999999; dp[109][0] = 1999999999999; dp[110][0] = 2999999999999; dp[111][0] = 3999999999999; dp[112][0] = 4999999999999; dp[113][0] = 5999999999999; dp[114][0] = 6999999999999; dp[115][0] = 7999999999999; dp[116][0] = 8999999999999; dp[117][0] = 9999999999999; dp[118][0] = 19999999999999; dp[119][0] = 29999999999999; dp[120][0] = 39999999999999; dp[121][0] = 49999999999999; dp[122][0] = 59999999999999; dp[123][0] = 69999999999999; dp[124][0] = 79999999999999; dp[125][0] = 89999999999999; dp[126][0] = 99999999999999; dp[127][0] = 199999999999999; dp[128][0] = 299999999999999; dp[129][0] = 399999999999999; dp[130][0] = 499999999999999; dp[131][0] = 599999999999999; dp[132][0] = 699999999999999; dp[133][0] = 799999999999999; dp[134][0] = 899999999999999; dp[135][0] = 999999999999999; dp[136][0] = 1999999999999999; dp[137][0] = 2999999999999999; dp[138][0] = 3999999999999999; dp[139][0] = 4999999999999999; dp[140][0] = 5999999999999999; dp[141][0] = 6999999999999999; dp[142][0] = 7999999999999999; dp[143][0] = 8999999999999999; dp[144][0] = 9999999999999999; dp[145][0] = 19999999999999999; dp[146][0] = 29999999999999999; dp[147][0] = 39999999999999999; dp[148][0] = 49999999999999999; dp[149][0] = 59999999999999999; dp[150][0] = 69999999999999999; dp[1][1] = 0; dp[2][1] = -1; dp[3][1] = 1; dp[4][1] = -1; dp[5][1] = 2; dp[6][1] = -1; dp[7][1] = 3; dp[8][1] = -1; dp[9][1] = 4; dp[10][1] = 9; dp[11][1] = 5; dp[12][1] = 19; dp[13][1] = 6; dp[14][1] = 29; dp[15][1] = 7; dp[16][1] = 39; dp[17][1] = 8; dp[18][1] = 49; dp[19][1] = 18; dp[20][1] = 59; dp[21][1] = 28; dp[22][1] = 69; dp[23][1] = 38; dp[24][1] = 79; dp[25][1] = 48; dp[26][1] = 89; dp[27][1] = 58; dp[28][1] = 189; dp[29][1] = 68; dp[30][1] = 289; dp[31][1] = 78; dp[32][1] = 389; dp[33][1] = 88; dp[34][1] = 489; dp[35][1] = 98; dp[36][1] = 589; dp[37][1] = 198; dp[38][1] = 689; dp[39][1] = 298; dp[40][1] = 789; dp[41][1] = 398; dp[42][1] = 889; dp[43][1] = 498; dp[44][1] = 989; dp[45][1] = 598; dp[46][1] = 1989; dp[47][1] = 698; dp[48][1] = 2989; dp[49][1] = 798; dp[50][1] = 3989; dp[51][1] = 898; dp[52][1] = 4989; dp[53][1] = 998; dp[54][1] = 5989; dp[55][1] = 1998; dp[56][1] = 6989; dp[57][1] = 2998; dp[58][1] = 7989; dp[59][1] = 3998; dp[60][1] = 8989; dp[61][1] = 4998; dp[62][1] = 9989; dp[63][1] = 5998; dp[64][1] = 19989; dp[65][1] = 6998; dp[66][1] = 29989; dp[67][1] = 7998; dp[68][1] = 39989; dp[69][1] = 8998; dp[70][1] = 49989; dp[71][1] = 9998; dp[72][1] = 59989; dp[73][1] = 19998; dp[74][1] = 69989; dp[75][1] = 29998; dp[76][1] = 79989; dp[77][1] = 39998; dp[78][1] = 89989; dp[79][1] = 49998; dp[80][1] = 99989; dp[81][1] = 59998; dp[82][1] = 199989; dp[83][1] = 69998; dp[84][1] = 299989; dp[85][1] = 79998; dp[86][1] = 399989; dp[87][1] = 89998; dp[88][1] = 499989; dp[89][1] = 99998; dp[90][1] = 599989; dp[91][1] = 199998; dp[92][1] = 699989; dp[93][1] = 299998; dp[94][1] = 799989; dp[95][1] = 399998; dp[96][1] = 899989; dp[97][1] = 499998; dp[98][1] = 999989; dp[99][1] = 599998; dp[100][1] = 1999989; dp[101][1] = 699998; dp[102][1] = 2999989; dp[103][1] = 799998; dp[104][1] = 3999989; dp[105][1] = 899998; dp[106][1] = 4999989; dp[107][1] = 999998; dp[108][1] = 5999989; dp[109][1] = 1999998; dp[110][1] = 6999989; dp[111][1] = 2999998; dp[112][1] = 7999989; dp[113][1] = 3999998; dp[114][1] = 8999989; dp[115][1] = 4999998; dp[116][1] = 9999989; dp[117][1] = 5999998; dp[118][1] = 19999989; dp[119][1] = 6999998; dp[120][1] = 29999989; dp[121][1] = 7999998; dp[122][1] = 39999989; dp[123][1] = 8999998; dp[124][1] = 49999989; dp[125][1] = 9999998; dp[126][1] = 59999989; dp[127][1] = 19999998; dp[128][1] = 69999989; dp[129][1] = 29999998; dp[130][1] = 79999989; dp[131][1] = 39999998; dp[132][1] = 89999989; dp[133][1] = 49999998; dp[134][1] = 99999989; dp[135][1] = 59999998; dp[136][1] = 199999989; dp[137][1] = 69999998; dp[138][1] = 299999989; dp[139][1] = 79999998; dp[140][1] = 399999989; dp[141][1] = 89999998; dp[142][1] = 499999989; dp[143][1] = 99999998; dp[144][1] = 599999989; dp[145][1] = 199999998; dp[146][1] = 699999989; dp[147][1] = 299999998; dp[148][1] = 799999989; dp[149][1] = 399999998; dp[150][1] = 899999989; dp[1][2] = -1; dp[2][2] = -1; dp[3][2] = 0; dp[4][2] = -1; dp[5][2] = -1; dp[6][2] = 1; dp[7][2] = -1; dp[8][2] = -1; dp[9][2] = 2; dp[10][2] = -1; dp[11][2] = -1; dp[12][2] = 3; dp[13][2] = -1; dp[14][2] = -1; dp[15][2] = 4; dp[16][2] = -1; dp[17][2] = -1; dp[18][2] = 5; dp[19][2] = -1; dp[20][2] = -1; dp[21][2] = 6; dp[22][2] = -1; dp[23][2] = -1; dp[24][2] = 7; dp[25][2] = -1; dp[26][2] = -1; dp[27][2] = 17; dp[28][2] = -1; dp[29][2] = -1; dp[30][2] = 27; dp[31][2] = -1; dp[32][2] = -1; dp[33][2] = 37; dp[34][2] = -1; dp[35][2] = -1; dp[36][2] = 47; dp[37][2] = -1; dp[38][2] = -1; dp[39][2] = 57; dp[40][2] = -1; dp[41][2] = -1; dp[42][2] = 67; dp[43][2] = -1; dp[44][2] = -1; dp[45][2] = 77; dp[46][2] = -1; dp[47][2] = -1; dp[48][2] = 87; dp[49][2] = -1; dp[50][2] = -1; dp[51][2] = 97; dp[52][2] = -1; dp[53][2] = -1; dp[54][2] = 197; dp[55][2] = -1; dp[56][2] = -1; dp[57][2] = 297; dp[58][2] = -1; dp[59][2] = -1; dp[60][2] = 397; dp[61][2] = -1; dp[62][2] = -1; dp[63][2] = 497; dp[64][2] = -1; dp[65][2] = -1; dp[66][2] = 597; dp[67][2] = -1; dp[68][2] = -1; dp[69][2] = 697; dp[70][2] = -1; dp[71][2] = -1; dp[72][2] = 797; dp[73][2] = -1; dp[74][2] = -1; dp[75][2] = 897; dp[76][2] = -1; dp[77][2] = -1; dp[78][2] = 997; dp[79][2] = -1; dp[80][2] = -1; dp[81][2] = 1997; dp[82][2] = -1; dp[83][2] = -1; dp[84][2] = 2997; dp[85][2] = -1; dp[86][2] = -1; dp[87][2] = 3997; dp[88][2] = -1; dp[89][2] = -1; dp[90][2] = 4997; dp[91][2] = -1; dp[92][2] = -1; dp[93][2] = 5997; dp[94][2] = -1; dp[95][2] = -1; dp[96][2] = 6997; dp[97][2] = -1; dp[98][2] = -1; dp[99][2] = 7997; dp[100][2] = -1; dp[101][2] = -1; dp[102][2] = 8997; dp[103][2] = -1; dp[104][2] = -1; dp[105][2] = 9997; dp[106][2] = -1; dp[107][2] = -1; dp[108][2] = 19997; dp[109][2] = -1; dp[110][2] = -1; dp[111][2] = 29997; dp[112][2] = -1; dp[113][2] = -1; dp[114][2] = 39997; dp[115][2] = -1; dp[116][2] = -1; dp[117][2] = 49997; dp[118][2] = -1; dp[119][2] = -1; dp[120][2] = 59997; dp[121][2] = -1; dp[122][2] = -1; dp[123][2] = 69997; dp[124][2] = -1; dp[125][2] = -1; dp[126][2] = 79997; dp[127][2] = -1; dp[128][2] = -1; dp[129][2] = 89997; dp[130][2] = -1; dp[131][2] = -1; dp[132][2] = 99997; dp[133][2] = -1; dp[134][2] = -1; dp[135][2] = 199997; dp[136][2] = -1; dp[137][2] = -1; dp[138][2] = 299997; dp[139][2] = -1; dp[140][2] = -1; dp[141][2] = 399997; dp[142][2] = -1; dp[143][2] = -1; dp[144][2] = 499997; dp[145][2] = -1; dp[146][2] = -1; dp[147][2] = 599997; dp[148][2] = -1; dp[149][2] = -1; dp[150][2] = 699997; dp[1][3] = -1; dp[2][3] = -1; dp[3][3] = -1; dp[4][3] = -1; dp[5][3] = -1; dp[6][3] = 0; dp[7][3] = -1; dp[8][3] = -1; dp[9][3] = -1; dp[10][3] = 1; dp[11][3] = -1; dp[12][3] = -1; dp[13][3] = -1; dp[14][3] = 2; dp[15][3] = 9; dp[16][3] = -1; dp[17][3] = -1; dp[18][3] = 3; dp[19][3] = 19; dp[20][3] = 8; dp[21][3] = -1; dp[22][3] = 4; dp[23][3] = 29; dp[24][3] = 18; dp[25][3] = 7; dp[26][3] = 5; dp[27][3] = 39; dp[28][3] = 28; dp[29][3] = 17; dp[30][3] = 6; dp[31][3] = 49; dp[32][3] = 38; dp[33][3] = 27; dp[34][3] = 16; dp[35][3] = 59; dp[36][3] = 48; dp[37][3] = 37; dp[38][3] = 26; dp[39][3] = 69; dp[40][3] = 58; dp[41][3] = 47; dp[42][3] = 36; dp[43][3] = 79; dp[44][3] = 68; dp[45][3] = 57; dp[46][3] = 46; dp[47][3] = 89; dp[48][3] = 78; dp[49][3] = 67; dp[50][3] = 56; dp[51][3] = 189; dp[52][3] = 88; dp[53][3] = 77; dp[54][3] = 66; dp[55][3] = 289; dp[56][3] = 188; dp[57][3] = 87; dp[58][3] = 76; dp[59][3] = 389; dp[60][3] = 288; dp[61][3] = 187; dp[62][3] = 86; dp[63][3] = 489; dp[64][3] = 388; dp[65][3] = 287; dp[66][3] = 96; dp[67][3] = 589; dp[68][3] = 488; dp[69][3] = 387; dp[70][3] = 196; dp[71][3] = 689; dp[72][3] = 588; dp[73][3] = 487; dp[74][3] = 296; dp[75][3] = 789; dp[76][3] = 688; dp[77][3] = 587; dp[78][3] = 396; dp[79][3] = 889; dp[80][3] = 788; dp[81][3] = 687; dp[82][3] = 496; dp[83][3] = 989; dp[84][3] = 888; dp[85][3] = 787; dp[86][3] = 596; dp[87][3] = 1989; dp[88][3] = 988; dp[89][3] = 887; dp[90][3] = 696; dp[91][3] = 2989; dp[92][3] = 1988; dp[93][3] = 987; dp[94][3] = 796; dp[95][3] = 3989; dp[96][3] = 2988; dp[97][3] = 1987; dp[98][3] = 896; dp[99][3] = 4989; dp[100][3] = 3988; dp[101][3] = 2987; dp[102][3] = 996; dp[103][3] = 5989; dp[104][3] = 4988; dp[105][3] = 3987; dp[106][3] = 1996; dp[107][3] = 6989; dp[108][3] = 5988; dp[109][3] = 4987; dp[110][3] = 2996; dp[111][3] = 7989; dp[112][3] = 6988; dp[113][3] = 5987; dp[114][3] = 3996; dp[115][3] = 8989; dp[116][3] = 7988; dp[117][3] = 6987; dp[118][3] = 4996; dp[119][3] = 9989; dp[120][3] = 8988; dp[121][3] = 7987; dp[122][3] = 5996; dp[123][3] = 19989; dp[124][3] = 9988; dp[125][3] = 8987; dp[126][3] = 6996; dp[127][3] = 29989; dp[128][3] = 19988; dp[129][3] = 9987; dp[130][3] = 7996; dp[131][3] = 39989; dp[132][3] = 29988; dp[133][3] = 19987; dp[134][3] = 8996; dp[135][3] = 49989; dp[136][3] = 39988; dp[137][3] = 29987; dp[138][3] = 9996; dp[139][3] = 59989; dp[140][3] = 49988; dp[141][3] = 39987; dp[142][3] = 19996; dp[143][3] = 69989; dp[144][3] = 59988; dp[145][3] = 49987; dp[146][3] = 29996; dp[147][3] = 79989; dp[148][3] = 69988; dp[149][3] = 59987; dp[150][3] = 39996; dp[1][4] = -1; dp[2][4] = -1; dp[3][4] = -1; dp[4][4] = -1; dp[5][4] = -1; dp[6][4] = -1; dp[7][4] = -1; dp[8][4] = -1; dp[9][4] = -1; dp[10][4] = 0; dp[11][4] = -1; dp[12][4] = -1; dp[13][4] = -1; dp[14][4] = -1; dp[15][4] = 1; dp[16][4] = -1; dp[17][4] = -1; dp[18][4] = -1; dp[19][4] = 9; dp[20][4] = 2; dp[21][4] = -1; dp[22][4] = -1; dp[23][4] = 8; dp[24][4] = 19; dp[25][4] = 3; dp[26][4] = -1; dp[27][4] = 7; dp[28][4] = 18; dp[29][4] = 29; dp[30][4] = 4; dp[31][4] = 6; dp[32][4] = 17; dp[33][4] = 28; dp[34][4] = 39; dp[35][4] = 5; dp[36][4] = 16; dp[37][4] = 27; dp[38][4] = 38; dp[39][4] = 49; dp[40][4] = 15; dp[41][4] = 26; dp[42][4] = 37; dp[43][4] = 48; dp[44][4] = 59; dp[45][4] = 25; dp[46][4] = 36; dp[47][4] = 47; dp[48][4] = 58; dp[49][4] = 69; dp[50][4] = 35; dp[51][4] = 46; dp[52][4] = 57; dp[53][4] = 68; dp[54][4] = 79; dp[55][4] = 45; dp[56][4] = 56; dp[57][4] = 67; dp[58][4] = 78; dp[59][4] = 89; dp[60][4] = 55; dp[61][4] = 66; dp[62][4] = 77; dp[63][4] = 88; dp[64][4] = 189; dp[65][4] = 65; dp[66][4] = 76; dp[67][4] = 87; dp[68][4] = 188; dp[69][4] = 289; dp[70][4] = 75; dp[71][4] = 86; dp[72][4] = 187; dp[73][4] = 288; dp[74][4] = 389; dp[75][4] = 85; dp[76][4] = 186; dp[77][4] = 287; dp[78][4] = 388; dp[79][4] = 489; dp[80][4] = 95; dp[81][4] = 286; dp[82][4] = 387; dp[83][4] = 488; dp[84][4] = 589; dp[85][4] = 195; dp[86][4] = 386; dp[87][4] = 487; dp[88][4] = 588; dp[89][4] = 689; dp[90][4] = 295; dp[91][4] = 486; dp[92][4] = 587; dp[93][4] = 688; dp[94][4] = 789; dp[95][4] = 395; dp[96][4] = 586; dp[97][4] = 687; dp[98][4] = 788; dp[99][4] = 889; dp[100][4] = 495; dp[101][4] = 686; dp[102][4] = 787; dp[103][4] = 888; dp[104][4] = 989; dp[105][4] = 595; dp[106][4] = 786; dp[107][4] = 887; dp[108][4] = 988; dp[109][4] = 1989; dp[110][4] = 695; dp[111][4] = 886; dp[112][4] = 987; dp[113][4] = 1988; dp[114][4] = 2989; dp[115][4] = 795; dp[116][4] = 986; dp[117][4] = 1987; dp[118][4] = 2988; dp[119][4] = 3989; dp[120][4] = 895; dp[121][4] = 1986; dp[122][4] = 2987; dp[123][4] = 3988; dp[124][4] = 4989; dp[125][4] = 995; dp[126][4] = 2986; dp[127][4] = 3987; dp[128][4] = 4988; dp[129][4] = 5989; dp[130][4] = 1995; dp[131][4] = 3986; dp[132][4] = 4987; dp[133][4] = 5988; dp[134][4] = 6989; dp[135][4] = 2995; dp[136][4] = 4986; dp[137][4] = 5987; dp[138][4] = 6988; dp[139][4] = 7989; dp[140][4] = 3995; dp[141][4] = 5986; dp[142][4] = 6987; dp[143][4] = 7988; dp[144][4] = 8989; dp[145][4] = 4995; dp[146][4] = 6986; dp[147][4] = 7987; dp[148][4] = 8988; dp[149][4] = 9989; dp[150][4] = 5995; dp[1][5] = -1; dp[2][5] = -1; dp[3][5] = -1; dp[4][5] = -1; dp[5][5] = -1; dp[6][5] = -1; dp[7][5] = -1; dp[8][5] = -1; dp[9][5] = -1; dp[10][5] = -1; dp[11][5] = -1; dp[12][5] = -1; dp[13][5] = -1; dp[14][5] = -1; dp[15][5] = 0; dp[16][5] = -1; dp[17][5] = -1; dp[18][5] = -1; dp[19][5] = -1; dp[20][5] = -1; dp[21][5] = 1; dp[22][5] = -1; dp[23][5] = -1; dp[24][5] = 9; dp[25][5] = -1; dp[26][5] = -1; dp[27][5] = 2; dp[28][5] = -1; dp[29][5] = -1; dp[30][5] = 7; dp[31][5] = -1; dp[32][5] = -1; dp[33][5] = 3; dp[34][5] = -1; dp[35][5] = -1; dp[36][5] = 5; dp[37][5] = -1; dp[38][5] = -1; dp[39][5] = 4; dp[40][5] = -1; dp[41][5] = -1; dp[42][5] = 15; dp[43][5] = -1; dp[44][5] = -1; dp[45][5] = 14; dp[46][5] = -1; dp[47][5] = -1; dp[48][5] = 25; dp[49][5] = -1; dp[50][5] = -1; dp[51][5] = 24; dp[52][5] = -1; dp[53][5] = -1; dp[54][5] = 35; dp[55][5] = -1; dp[56][5] = -1; dp[57][5] = 34; dp[58][5] = -1; dp[59][5] = -1; dp[60][5] = 45; dp[61][5] = -1; dp[62][5] = -1; dp[63][5] = 44; dp[64][5] = -1; dp[65][5] = -1; dp[66][5] = 55; dp[67][5] = -1; dp[68][5] = -1; dp[69][5] = 54; dp[70][5] = -1; dp[71][5] = -1; dp[72][5] = 65; dp[73][5] = -1; dp[74][5] = -1; dp[75][5] = 64; dp[76][5] = -1; dp[77][5] = -1; dp[78][5] = 75; dp[79][5] = -1; dp[80][5] = -1; dp[81][5] = 74; dp[82][5] = -1; dp[83][5] = -1; dp[84][5] = 85; dp[85][5] = -1; dp[86][5] = -1; dp[87][5] = 84; dp[88][5] = -1; dp[89][5] = -1; dp[90][5] = 185; dp[91][5] = -1; dp[92][5] = -1; dp[93][5] = 94; dp[94][5] = -1; dp[95][5] = -1; dp[96][5] = 285; dp[97][5] = -1; dp[98][5] = -1; dp[99][5] = 194; dp[100][5] = -1; dp[101][5] = -1; dp[102][5] = 385; dp[103][5] = -1; dp[104][5] = -1; dp[105][5] = 294; dp[106][5] = -1; dp[107][5] = -1; dp[108][5] = 485; dp[109][5] = -1; dp[110][5] = -1; dp[111][5] = 394; dp[112][5] = -1; dp[113][5] = -1; dp[114][5] = 585; dp[115][5] = -1; dp[116][5] = -1; dp[117][5] = 494; dp[118][5] = -1; dp[119][5] = -1; dp[120][5] = 685; dp[121][5] = -1; dp[122][5] = -1; dp[123][5] = 594; dp[124][5] = -1; dp[125][5] = -1; dp[126][5] = 785; dp[127][5] = -1; dp[128][5] = -1; dp[129][5] = 694; dp[130][5] = -1; dp[131][5] = -1; dp[132][5] = 885; dp[133][5] = -1; dp[134][5] = -1; dp[135][5] = 794; dp[136][5] = -1; dp[137][5] = -1; dp[138][5] = 985; dp[139][5] = -1; dp[140][5] = -1; dp[141][5] = 894; dp[142][5] = -1; dp[143][5] = -1; dp[144][5] = 1985; dp[145][5] = -1; dp[146][5] = -1; dp[147][5] = 994; dp[148][5] = -1; dp[149][5] = -1; dp[150][5] = 2985; dp[1][6] = -1; dp[2][6] = -1; dp[3][6] = -1; dp[4][6] = -1; dp[5][6] = -1; dp[6][6] = -1; dp[7][6] = -1; dp[8][6] = -1; dp[9][6] = -1; dp[10][6] = -1; dp[11][6] = -1; dp[12][6] = -1; dp[13][6] = -1; dp[14][6] = -1; dp[15][6] = -1; dp[16][6] = -1; dp[17][6] = -1; dp[18][6] = -1; dp[19][6] = -1; dp[20][6] = -1; dp[21][6] = 0; dp[22][6] = -1; dp[23][6] = -1; dp[24][6] = -1; dp[25][6] = -1; dp[26][6] = -1; dp[27][6] = -1; dp[28][6] = 1; dp[29][6] = -1; dp[30][6] = 9; dp[31][6] = -1; dp[32][6] = 8; dp[33][6] = -1; dp[34][6] = 7; dp[35][6] = 2; dp[36][6] = 6; dp[37][6] = 19; dp[38][6] = 5; dp[39][6] = 18; dp[40][6] = 4; dp[41][6] = 17; dp[42][6] = 3; dp[43][6] = 16; dp[44][6] = 29; dp[45][6] = 15; dp[46][6] = 28; dp[47][6] = 14; dp[48][6] = 27; dp[49][6] = 13; dp[50][6] = 26; dp[51][6] = 39; dp[52][6] = 25; dp[53][6] = 38; dp[54][6] = 24; dp[55][6] = 37; dp[56][6] = 23; dp[57][6] = 36; dp[58][6] = 49; dp[59][6] = 35; dp[60][6] = 48; dp[61][6] = 34; dp[62][6] = 47; dp[63][6] = 33; dp[64][6] = 46; dp[65][6] = 59; dp[66][6] = 45; dp[67][6] = 58; dp[68][6] = 44; dp[69][6] = 57; dp[70][6] = 43; dp[71][6] = 56; dp[72][6] = 69; dp[73][6] = 55; dp[74][6] = 68; dp[75][6] = 54; dp[76][6] = 67; dp[77][6] = 53; dp[78][6] = 66; dp[79][6] = 79; dp[80][6] = 65; dp[81][6] = 78; dp[82][6] = 64; dp[83][6] = 77; dp[84][6] = 63; dp[85][6] = 76; dp[86][6] = 89; dp[87][6] = 75; dp[88][6] = 88; dp[89][6] = 74; dp[90][6] = 87; dp[91][6] = 73; dp[92][6] = 86; dp[93][6] = 189; dp[94][6] = 85; dp[95][6] = 188; dp[96][6] = 84; dp[97][6] = 187; dp[98][6] = 83; dp[99][6] = 186; dp[100][6] = 289; dp[101][6] = 185; dp[102][6] = 288; dp[103][6] = 184; dp[104][6] = 287; dp[105][6] = 93; dp[106][6] = 286; dp[107][6] = 389; dp[108][6] = 285; dp[109][6] = 388; dp[110][6] = 284; dp[111][6] = 387; dp[112][6] = 193; dp[113][6] = 386; dp[114][6] = 489; dp[115][6] = 385; dp[116][6] = 488; dp[117][6] = 384; dp[118][6] = 487; dp[119][6] = 293; dp[120][6] = 486; dp[121][6] = 589; dp[122][6] = 485; dp[123][6] = 588; dp[124][6] = 484; dp[125][6] = 587; dp[126][6] = 393; dp[127][6] = 586; dp[128][6] = 689; dp[129][6] = 585; dp[130][6] = 688; dp[131][6] = 584; dp[132][6] = 687; dp[133][6] = 493; dp[134][6] = 686; dp[135][6] = 789; dp[136][6] = 685; dp[137][6] = 788; dp[138][6] = 684; dp[139][6] = 787; dp[140][6] = 593; dp[141][6] = 786; dp[142][6] = 889; dp[143][6] = 785; dp[144][6] = 888; dp[145][6] = 784; dp[146][6] = 887; dp[147][6] = 693; dp[148][6] = 886; dp[149][6] = 989; dp[150][6] = 885; dp[1][7] = -1; dp[2][7] = -1; dp[3][7] = -1; dp[4][7] = -1; dp[5][7] = -1; dp[6][7] = -1; dp[7][7] = -1; dp[8][7] = -1; dp[9][7] = -1; dp[10][7] = -1; dp[11][7] = -1; dp[12][7] = -1; dp[13][7] = -1; dp[14][7] = -1; dp[15][7] = -1; dp[16][7] = -1; dp[17][7] = -1; dp[18][7] = -1; dp[19][7] = -1; dp[20][7] = -1; dp[21][7] = -1; dp[22][7] = -1; dp[23][7] = -1; dp[24][7] = -1; dp[25][7] = -1; dp[26][7] = -1; dp[27][7] = -1; dp[28][7] = 0; dp[29][7] = -1; dp[30][7] = -1; dp[31][7] = -1; dp[32][7] = -1; dp[33][7] = -1; dp[34][7] = -1; dp[35][7] = -1; dp[36][7] = 1; dp[37][7] = 9; dp[38][7] = 8; dp[39][7] = 7; dp[40][7] = 6; dp[41][7] = 5; dp[42][7] = 4; dp[43][7] = 3; dp[44][7] = 2; dp[45][7] = 19; dp[46][7] = 18; dp[47][7] = 17; dp[48][7] = 16; dp[49][7] = 15; dp[50][7] = 14; dp[51][7] = 13; dp[52][7] = 12; dp[53][7] = 29; dp[54][7] = 28; dp[55][7] = 27; dp[56][7] = 26; dp[57][7] = 25; dp[58][7] = 24; dp[59][7] = 23; dp[60][7] = 22; dp[61][7] = 39; dp[62][7] = 38; dp[63][7] = 37; dp[64][7] = 36; dp[65][7] = 35; dp[66][7] = 34; dp[67][7] = 33; dp[68][7] = 32; dp[69][7] = 49; dp[70][7] = 48; dp[71][7] = 47; dp[72][7] = 46; dp[73][7] = 45; dp[74][7] = 44; dp[75][7] = 43; dp[76][7] = 42; dp[77][7] = 59; dp[78][7] = 58; dp[79][7] = 57; dp[80][7] = 56; dp[81][7] = 55; dp[82][7] = 54; dp[83][7] = 53; dp[84][7] = 52; dp[85][7] = 69; dp[86][7] = 68; dp[87][7] = 67; dp[88][7] = 66; dp[89][7] = 65; dp[90][7] = 64; dp[91][7] = 63; dp[92][7] = 62; dp[93][7] = 79; dp[94][7] = 78; dp[95][7] = 77; dp[96][7] = 76; dp[97][7] = 75; dp[98][7] = 74; dp[99][7] = 73; dp[100][7] = 72; dp[101][7] = 89; dp[102][7] = 88; dp[103][7] = 87; dp[104][7] = 86; dp[105][7] = 85; dp[106][7] = 84; dp[107][7] = 83; dp[108][7] = 82; dp[109][7] = 189; dp[110][7] = 188; dp[111][7] = 187; dp[112][7] = 186; dp[113][7] = 185; dp[114][7] = 184; dp[115][7] = 183; dp[116][7] = 92; dp[117][7] = 289; dp[118][7] = 288; dp[119][7] = 287; dp[120][7] = 286; dp[121][7] = 285; dp[122][7] = 284; dp[123][7] = 283; dp[124][7] = 192; dp[125][7] = 389; dp[126][7] = 388; dp[127][7] = 387; dp[128][7] = 386; dp[129][7] = 385; dp[130][7] = 384; dp[131][7] = 383; dp[132][7] = 292; dp[133][7] = 489; dp[134][7] = 488; dp[135][7] = 487; dp[136][7] = 486; dp[137][7] = 485; dp[138][7] = 484; dp[139][7] = 483; dp[140][7] = 392; dp[141][7] = 589; dp[142][7] = 588; dp[143][7] = 587; dp[144][7] = 586; dp[145][7] = 585; dp[146][7] = 584; dp[147][7] = 583; dp[148][7] = 492; dp[149][7] = 689; dp[150][7] = 688; dp[1][8] = -1; dp[2][8] = -1; dp[3][8] = -1; dp[4][8] = -1; dp[5][8] = -1; dp[6][8] = -1; dp[7][8] = -1; dp[8][8] = -1; dp[9][8] = -1; dp[10][8] = -1; dp[11][8] = -1; dp[12][8] = -1; dp[13][8] = -1; dp[14][8] = -1; dp[15][8] = -1; dp[16][8] = -1; dp[17][8] = -1; dp[18][8] = -1; dp[19][8] = -1; dp[20][8] = -1; dp[21][8] = -1; dp[22][8] = -1; dp[23][8] = -1; dp[24][8] = -1; dp[25][8] = -1; dp[26][8] = -1; dp[27][8] = -1; dp[28][8] = -1; dp[29][8] = -1; dp[30][8] = -1; dp[31][8] = -1; dp[32][8] = -1; dp[33][8] = -1; dp[34][8] = -1; dp[35][8] = -1; dp[36][8] = 0; dp[37][8] = -1; dp[38][8] = -1; dp[39][8] = -1; dp[40][8] = -1; dp[41][8] = -1; dp[42][8] = -1; dp[43][8] = -1; dp[44][8] = -1; dp[45][8] = 1; dp[46][8] = -1; dp[47][8] = -1; dp[48][8] = -1; dp[49][8] = -1; dp[50][8] = -1; dp[51][8] = -1; dp[52][8] = -1; dp[53][8] = -1; dp[54][8] = 11; dp[55][8] = -1; dp[56][8] = -1; dp[57][8] = -1; dp[58][8] = -1; dp[59][8] = -1; dp[60][8] = -1; dp[61][8] = -1; dp[62][8] = -1; dp[63][8] = 21; dp[64][8] = -1; dp[65][8] = -1; dp[66][8] = -1; dp[67][8] = -1; dp[68][8] = -1; dp[69][8] = -1; dp[70][8] = -1; dp[71][8] = -1; dp[72][8] = 31; dp[73][8] = -1; dp[74][8] = -1; dp[75][8] = -1; dp[76][8] = -1; dp[77][8] = -1; dp[78][8] = -1; dp[79][8] = -1; dp[80][8] = -1; dp[81][8] = 41; dp[82][8] = -1; dp[83][8] = -1; dp[84][8] = -1; dp[85][8] = -1; dp[86][8] = -1; dp[87][8] = -1; dp[88][8] = -1; dp[89][8] = -1; dp[90][8] = 51; dp[91][8] = -1; dp[92][8] = -1; dp[93][8] = -1; dp[94][8] = -1; dp[95][8] = -1; dp[96][8] = -1; dp[97][8] = -1; dp[98][8] = -1; dp[99][8] = 61; dp[100][8] = -1; dp[101][8] = -1; dp[102][8] = -1; dp[103][8] = -1; dp[104][8] = -1; dp[105][8] = -1; dp[106][8] = -1; dp[107][8] = -1; dp[108][8] = 71; dp[109][8] = -1; dp[110][8] = -1; dp[111][8] = -1; dp[112][8] = -1; dp[113][8] = -1; dp[114][8] = -1; dp[115][8] = -1; dp[116][8] = -1; dp[117][8] = 81; dp[118][8] = -1; dp[119][8] = -1; dp[120][8] = -1; dp[121][8] = -1; dp[122][8] = -1; dp[123][8] = -1; dp[124][8] = -1; dp[125][8] = -1; dp[126][8] = 91; dp[127][8] = -1; dp[128][8] = -1; dp[129][8] = -1; dp[130][8] = -1; dp[131][8] = -1; dp[132][8] = -1; dp[133][8] = -1; dp[134][8] = -1; dp[135][8] = 191; dp[136][8] = -1; dp[137][8] = -1; dp[138][8] = -1; dp[139][8] = -1; dp[140][8] = -1; dp[141][8] = -1; dp[142][8] = -1; dp[143][8] = -1; dp[144][8] = 291; dp[145][8] = -1; dp[146][8] = -1; dp[147][8] = -1; dp[148][8] = -1; dp[149][8] = -1; dp[150][8] = -1; dp[1][9] = -1; dp[2][9] = -1; dp[3][9] = -1; dp[4][9] = -1; dp[5][9] = -1; dp[6][9] = -1; dp[7][9] = -1; dp[8][9] = -1; dp[9][9] = -1; dp[10][9] = -1; dp[11][9] = -1; dp[12][9] = -1; dp[13][9] = -1; dp[14][9] = -1; dp[15][9] = -1; dp[16][9] = -1; dp[17][9] = -1; dp[18][9] = -1; dp[19][9] = -1; dp[20][9] = -1; dp[21][9] = -1; dp[22][9] = -1; dp[23][9] = -1; dp[24][9] = -1; dp[25][9] = -1; dp[26][9] = -1; dp[27][9] = -1; dp[28][9] = -1; dp[29][9] = -1; dp[30][9] = -1; dp[31][9] = -1; dp[32][9] = -1; dp[33][9] = -1; dp[34][9] = -1; dp[35][9] = -1; dp[36][9] = -1; dp[37][9] = -1; dp[38][9] = -1; dp[39][9] = -1; dp[40][9] = -1; dp[41][9] = -1; dp[42][9] = -1; dp[43][9] = -1; dp[44][9] = -1; dp[45][9] = 0; dp[46][9] = 1; dp[47][9] = 2; dp[48][9] = 3; dp[49][9] = 4; dp[50][9] = 5; dp[51][9] = 6; dp[52][9] = 7; dp[53][9] = 8; dp[54][9] = 9; dp[55][9] = 10; dp[56][9] = 11; dp[57][9] = 12; dp[58][9] = 13; dp[59][9] = 14; dp[60][9] = 15; dp[61][9] = 16; dp[62][9] = 17; dp[63][9] = 18; dp[64][9] = 19; dp[65][9] = 20; dp[66][9] = 21; dp[67][9] = 22; dp[68][9] = 23; dp[69][9] = 24; dp[70][9] = 25; dp[71][9] = 26; dp[72][9] = 27; dp[73][9] = 28; dp[74][9] = 29; dp[75][9] = 30; dp[76][9] = 31; dp[77][9] = 32; dp[78][9] = 33; dp[79][9] = 34; dp[80][9] = 35; dp[81][9] = 36; dp[82][9] = 37; dp[83][9] = 38; dp[84][9] = 39; dp[85][9] = 40; dp[86][9] = 41; dp[87][9] = 42; dp[88][9] = 43; dp[89][9] = 44; dp[90][9] = 45; dp[91][9] = 46; dp[92][9] = 47; dp[93][9] = 48; dp[94][9] = 49; dp[95][9] = 50; dp[96][9] = 51; dp[97][9] = 52; dp[98][9] = 53; dp[99][9] = 54; dp[100][9] = 55; dp[101][9] = 56; dp[102][9] = 57; dp[103][9] = 58; dp[104][9] = 59; dp[105][9] = 60; dp[106][9] = 61; dp[107][9] = 62; dp[108][9] = 63; dp[109][9] = 64; dp[110][9] = 65; dp[111][9] = 66; dp[112][9] = 67; dp[113][9] = 68; dp[114][9] = 69; dp[115][9] = 70; dp[116][9] = 71; dp[117][9] = 72; dp[118][9] = 73; dp[119][9] = 74; dp[120][9] = 75; dp[121][9] = 76; dp[122][9] = 77; dp[123][9] = 78; dp[124][9] = 79; dp[125][9] = 80; dp[126][9] = 81; dp[127][9] = 82; dp[128][9] = 83; dp[129][9] = 84; dp[130][9] = 85; dp[131][9] = 86; dp[132][9] = 87; dp[133][9] = 88; dp[134][9] = 89; dp[135][9] = 90; dp[136][9] = 181; dp[137][9] = 182; dp[138][9] = 183; dp[139][9] = 184; dp[140][9] = 185; dp[141][9] = 186; dp[142][9] = 187; dp[143][9] = 188; dp[144][9] = 189; dp[145][9] = 190; dp[146][9] = 281; dp[147][9] = 282; dp[148][9] = 283; dp[149][9] = 284; dp[150][9] = 285; int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; cout << dp[n][k] << endl; } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; return 0; }
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#include <bits/stdc++.h> using namespace std; struct point { long long x, y; }; long long cross(point a, point b, point c) { return (b.x - a.x) * (c.y - a.y) - (c.x - a.x) * (b.y - a.y); } int main() { point a, b, c; cin >> a.x >> a.y >> b.x >> b.y >> c.x >> c.y; long long ans = cross(a, b, c); if (ans > 0) cout << LEFT n ; else if (ans < 0) cout << RIGHT n ; else cout << TOWARDS n ; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_SYMBOL_V
`define SKY130_FD_SC_HD__OR2_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_SYMBOL_V
|
`define SIZE 2
`define FIFO_DEPTH_LOG2 2
`define FIFO_DEPTH (1<<`FIFO_DEPTH_LOG2)
module fifo(clk, reset, full, empty, item_in, item_out, write, read);
parameter routerid=-1;
input clk, reset, write, read;
output full, empty;
reg [`SIZE-1:0] mem [`FIFO_DEPTH-1:0];
reg [`FIFO_DEPTH_LOG2-1:0] read_ptr;
reg [`FIFO_DEPTH_LOG2-1:0] write_ptr;
wire [`FIFO_DEPTH_LOG2-1:0] read_ptr_p1; assign read_ptr_p1 = read_ptr + 1;
wire [`FIFO_DEPTH_LOG2-1:0] write_ptr_p1; assign write_ptr_p1 = write_ptr + 1;
reg [`FIFO_DEPTH_LOG2:0] count;
input [`SIZE-1:0] item_in;
output [`SIZE-1:0] item_out;
reg full, empty;
integer i;
always @(posedge clk or posedge reset) begin
if (reset) begin
read_ptr <= 0;
write_ptr <= 0;
empty <= 1;
full <= 0;
count <= 0;
for (i=0; i<`FIFO_DEPTH; i=i+1) begin
mem[i] <= 0;
end
end else begin
if (read & !empty) begin
full <= 0;
read_ptr <= read_ptr_p1;
if (read_ptr_p1 == write_ptr) empty <= 1;
//if (routerid > -1) $display("router %d fifo pop : %d", routerid, item_out);
end
if (write & !full) begin
mem [write_ptr] <= item_in;
//if (routerid > -1) $display("router %d fifo push : %d", routerid, item_in);
empty <= 0;
write_ptr <= write_ptr_p1;
if (read_ptr == write_ptr_p1) full <= 1;
end
if (actual_read & !actual_write)
count <= count-1;
else if (actual_write & !actual_read)
count <= count+1;
end
end
assign item_out = mem [read_ptr];
wire actual_read = read & !empty;
wire actual_write = write & !full;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { set<pair<pair<long long, long long>, pair<long long, long long> > > rem; long long xi = 0, yi = 0, xf = 0, yf = 0; string s; cin >> s; long long ans = 0; for (long long i = 0; i < (long long)(s.length()); ++i) { if (s[i] == N ) { yf++; } else if (s[i] == S ) { yf--; } else if (s[i] == E ) { xf++; } else { xf--; } if (rem.count({{xi, yi}, {xf, yf}})) { ans += 1; } else { ans += 5; rem.insert({{xi, yi}, {xf, yf}}); rem.insert({{xf, yf}, {xi, yi}}); } xi = xf; yi = yf; } cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_1_V
`define SKY130_FD_SC_HS__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtn_1 (
RESET_B,
D ,
GATE_N ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtn_1 (
RESET_B,
D ,
GATE_N ,
Q
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_1_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2e9 + 7; const int M = 1e6 + 10; const int N = 51; const int POW = 20; const long long MOD = 1000 * 1000 * 1000 + 7; int a[N]; int d[2][N][N][N][N]; void add(int &a, long long add) { a = ((long long)a + add) % MOD; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; if (a[0] == 3) { if (a[1] == 2) d[1][0][1][1][0] = 1; else d[1][0][1][0][1] = 1; } else { d[0][0][0][0][1] = 1; } for (int i = a[0] - 2; i < n - 1; ++i) { for (int s1 = 0; s1 < n + 1; ++s1) for (int s2 = 0; s2 < n + 1; ++s2) for (int t1 = 0; t1 < n + 1; ++t1) for (int t2 = 0; t2 < n + 1; ++t2) d[(i + 1) % 2][s1][s2][t1][t2] = 0; for (int s1 = 0; s1 < n + 1; ++s1) for (int s2 = 0; s2 < n + 1; ++s2) for (int t1 = 0; t1 < n + 1; ++t1) for (int t2 = 0; t2 < n + 1; ++t2) { if (d[i % 2][s1][s2][t1][t2] == 0) continue; assert(s1 < n && s2 < n && t1 < n && t2 < n); long long cur = d[i % 2][s1][s2][t1][t2]; if (s1 + s2 == 0) { if (t1) add(d[(i + 1) % 2][t1 - 1][t2][a[i + 1] == 2][a[i + 1] == 3], cur * t1); if (t2) add(d[(i + 1) % 2][t1 + 1][t2 - 1][a[i + 1] == 2] [a[i + 1] == 3], cur * t2); } if (s1) { add(d[(i + 1) % 2][s1 - 1][s2][t1 + (a[i + 1] == 2)] [t2 + (a[i + 1] == 3)], cur * s1); if (a[i + 1] == 2) { if (t1) add(d[(i + 1) % 2][s1 - 1][s2][t1 - 1][t2], cur * s1 * t1); if (t2) add(d[(i + 1) % 2][s1 - 1][s2][t1 + 1][t2 - 1], cur * s1 * t2); } else if (a[i + 1] == 3) { if (t1) add(d[(i + 1) % 2][s1 - 1][s2][t1][t2], cur * s1 * t1); if (t1 >= 2) add(d[(i + 1) % 2][s1 - 1][s2][t1 - 2][t2], cur * s1 * (t1 * (t1 - 1) / 2)); if (t2 >= 2) add(d[(i + 1) % 2][s1 - 1][s2][t1 + 2][t2 - 2], cur * s1 * (t2 * (t2 - 1) / 2)); if (t2) add(d[(i + 1) % 2][s1 - 1][s2][t1 + 2][t2 - 1], cur * s1 * t2); if (t1 && t2) add(d[(i + 1) % 2][s1 - 1][s2][t1][t2 - 1], cur * s1 * t1 * t2); } } if (s2) { add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1 + (int)(a[i + 1] == 2)] [t2 + (int)(a[i + 1] == 3)], cur * s2); if (a[i + 1] == 2) { if (t1) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1 - 1][t2], cur * s2 * t1); if (t2) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1 + 1][t2 - 1], cur * s2 * t2); } else if (a[i + 1] == 3) { if (t1) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1][t2], cur * s2 * t1); if (t1 >= 2) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1 - 2][t2], cur * s2 * (t1 * (t1 - 1) / 2)); if (t2 >= 2) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1 + 2][t2 - 2], cur * s2 * (t2 * (t2 - 1) / 2)); if (t2) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1 + 2][t2 - 1], cur * s2 * t2); if (t1 && t2) add(d[(i + 1) % 2][s1 + 1][s2 - 1][t1][t2 - 1], cur * s2 * t1 * t2); } } } } cout << d[(n + 1) % 2][0][0][0][0]; return 0; }
|
module clk_gen (
input clk,
input resetn,
output [0:0] clk_out
);
parameter CLK_CYCLES = 10;
reg [0:0] clk_out;
reg [$clog2(CLK_CYCLES):0] clk_counter;
always @(posedge clk) begin
if (!resetn) begin
clk_counter <= CLK_CYCLES-1;
clk_out <= 0;
end else begin
clk_counter <= clk_counter ? (clk_counter-1) : CLK_CYCLES-1;
clk_out <= !clk_counter;
end
end
`ifdef FORMAL
`timescale 1 ns / 100 ps
reg [$clog2(CLK_CYCLES):0] clk_counter_pre; // previus clk state
// integer counter = 0;
reg [10:0] _tst_counter = 0;
reg [0:0] clk = 0;
// reg [0:0] resetn = 0;
// wire [0:0] resetn;
initial begin
clk_counter_pre = 0;//CLK_CYCLES-1;
clk = 0;
// resetn = 0;
counter = 0;
// #10 resetn <= 1;
// # assert (0);
end
assign resetn = (_tst_counter>4);
always @(posedge clk) begin
_tst_counter = _tst_counter + 1;
if (_tst_counter == 5) begin
assert (0);
// resetn = 1;
end
if (!resetn) begin
clk_counter_pre <= CLK_CYCLES-1;
// if (counter != 0)
// assert (clk_out == 0);
end else begin
// assert (clk_counter < CLK_CYCLES);
assert (clk_counter >= 0);
if (clk_counter_pre == 0) begin
// assert (clk_out == 1);
// assert (clk_counter == CLK_CYCLES-1);
end else begin
assert (clk_out == 0);
assert (clk_counter == clk_counter_pre - 1);
end
end
clk_counter_pre <= clk_counter;
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; set<int> st; int main() { int t, i, j, k, n, m; scanf( %d , &n); for (i = 0; i < n; i++) { int x; scanf( %d , &x); st.insert(x); } int a, b; scanf( %d , &a); scanf( %d , &b); set<int>::iterator it, cit; int ans = 0; while (1) { if (a == b) { cout << ans << endl; return 0; } int mx = 1; for (it = st.begin(); it != st.end();) { int val = *it; cit = it; it++; if (a - (a % val) < b) { st.erase(cit); } else { mx = max(mx, a % val); } } ans++; a = a - mx; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[2 * 100000 + 10]; int n, m, k; bool find(int pos) { int m1 = 0; while (m1 < m && pos <= n) { int k1 = k; while (pos <= n && a[pos] <= k1) { k1 -= a[pos++]; } m1++; } return pos == n + 1 ? 1 : 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } int ans = 0; int l = 1, r = n; while (l <= r) { int mid = (l + r) / 2; if (find(mid)) { ans = max(ans, n - mid + 1); r = mid - 1; } else { l = mid + 1; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_SYMBOL_V
`define SKY130_FD_SC_MS__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_TB_V
`define SKY130_FD_SC_MS__DFRTP_TB_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtp.v"
module top();
// Inputs are registered
reg D;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__dfrtp dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; const int mod = 1000000007; int n, a, b, k; int dp[N][N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> a >> b >> k; for (long long i = 1; i <= n; ++i) { dp[0][i] = i; } for (int trip = 1; trip <= k; trip++) { for (int floor = 1; floor <= n; floor++) { int d = abs(b - floor); dp[trip][floor] = dp[trip - 1][min(n, floor + d - 1)] - dp[trip - 1][max(0, floor - d)] - dp[trip - 1][floor] + dp[trip - 1][floor - 1]; while (dp[trip][floor] < 0) dp[trip][floor] += mod; dp[trip][floor] %= mod; dp[trip][floor] = (dp[trip][floor] + dp[trip][floor - 1]) % mod; } } cout << (dp[k][a] - dp[k][a - 1] + mod) % mod; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mx = 1e6 + 1; int n, m; string s[3]; int dp[mx][8]; bool isok(int i, int j) { int cnt = 0; for (int k = 0; k < 2; k++) cnt += ((i >> k) & 1) + ((j >> k) & 1); if (cnt % 2 == 0) return false; if (n == 2) return true; cnt = 0; for (int k = 1; k < 3; k++) cnt += ((i >> k) & 1) + ((j >> k) & 1); return cnt & 1; } int solve(int idx, int msk) { if (idx == m) return 0; int &ans = dp[idx][msk]; if (~ans) return ans; ans = 1e9; for (int i = 0; i < (1 << n); i++) if (idx == 0 || isok(msk, i)) { int cur = 0; for (int j = 0; j < n; j++) cur += ((i >> j) & 1) != (s[j][idx] - 0 ); ans = min(ans, cur + solve(idx + 1, i)); } return ans; } int main() { cin.tie(nullptr); ios_base::sync_with_stdio(0); cin >> n >> m; if (n == 1) return cout << 0 , 0; if (n >= 4) return cout << -1 , 0; for (int i = 0; i < n; i++) cin >> s[i]; int ans = 1e9; memset(dp, -1, sizeof dp); for (int i = 0; i < (1 << n); i++) ans = min(ans, solve(0, i)); cout << ans; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Jie Xu.
//
// change these two parameters to see the speed differences
`define DATA_WIDTH 8
`define REP_COUNT4 `DATA_WIDTH/4
`define REP_COUNT2 `DATA_WIDTH/2
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] count4 = 0;
reg [1:0] count2 = 0;
reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}};
reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] res1;
reg [`DATA_WIDTH-1:0] res2;
reg [`DATA_WIDTH-1:0] res3;
reg [`DATA_WIDTH-1:0] res4;
drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1));
drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2));
drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3));
drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4));
always@(posedge clk)
begin
count2 <= count2 + 1;
count4 <= count4 + 1;
a <= {`REP_COUNT4{count4}};
b <= {`REP_COUNT4{count4}};
c <= {`REP_COUNT2{count2}};
d <= {`REP_COUNT2{count2}};
if (res1 != (a)) begin
$stop;
end
if (res2 != (a&b)) begin
$stop;
end
if (res3 != (a&b&c)) begin
$stop;
end
if (res4 != (a&b&c&d)) begin
$stop;
end
if (count4 > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module drv1
(input colSelA,
output datao
);
assign datao = colSelA;
endmodule
module drv2
(input colSelA,
input colSelB,
output datao
);
assign datao = colSelB & colSelA;
endmodule
module drv3
(input colSelA,
input colSelB,
input colSelC,
output datao
);
assign datao = colSelB & colSelA & colSelC;
endmodule
module drv4
(input colSelA,
input colSelB,
input colSelC,
input colSelD,
output datao
);
assign datao = colSelB & colSelA & colSelC & colSelD;
endmodule
|
#include <bits/stdc++.h> #define pb push_back #define mp make_pair #define fr first #define sc second #define MOD 1000000007 #define len(x) x.size() #define min3(a, b, c) min(a, min(b, c)) #define max3(a, b, c) max(a, max(b, c)) #define all(v) v.begin(), v.end() #define alla(a,n) a, a + n using namespace std; typedef long long ll; typedef unsigned long long ull; typedef pair<ll, ll> pll; typedef vector<ll> vll; typedef vector<pll> vpll; typedef vector<vll> vvll; typedef vector<string> vs; void run() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin) ; freopen( output.txt , w , stdout) ; #endif ios_base::sync_with_stdio(false); cin.tie(NULL) ; cout.tie(NULL) ; } void solve() { int t; cin >> t; while (t--) { int n, d; cin >> n >> d; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int flag = 0, min_val = 0; for (int i = 0; i < n; i++) { if (arr[i] > d) { flag = 1; } } if (flag == 0) { cout << YES << endl; } else { sort(arr, arr + n); // cout << arr[0] << arr[1]; min_val = arr[0] + arr[1]; if (min_val <= d) { cout << YES << endl; } else { cout << NO << endl; } } } } int32_t main() { run(); solve(); return 0 ; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 15: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 65536,
the_altsyncram.numwords_a = 65536,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CONB_SYMBOL_V
`define SKY130_FD_SC_HS__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CONB_SYMBOL_V
|
`timescale 1ns / 1ns
`define INT 3'd0
`define SHP 3'd1
`define CTD 3'd2
`define ADD 3'd3
`define SUB 3'd4
`define RDY 3'd5
module BoothController(input clk,input start,input[1:0] yLow, input[2:0] count,output reg ready,init,ldx,ldy,shift,cin,cntD);
reg [2:0] ps;
reg [2:0] ns;
initial ns = `RDY;
initial ps = `RDY;
always @(start,count,yLow,ps)
case(ps)
`RDY : ns = (start) ? `INT : `RDY;
`INT : ns = `CTD;
`CTD : ns = (count) ? (yLow[1]^yLow[0] ? (yLow[0] ? `ADD : `SUB) : `SHP) : `RDY;
`ADD : ns = `SHP;
`SUB : ns = `SHP;
`SHP : ns = `CTD;
endcase
always @(posedge clk)
ps = ns;
always @(ps)
begin
ready = 1'b0;
init = 1'b0;
ldx = 1'b0;
ldy = 1'b0;
shift = 1'b0;
cin = 1'b0;
cntD = 1'b0;
case(ps)
`INT :
begin
ldx = 1'b1;
ldy = 1'b1;
init = 1'b1;
end
`SHP :
shift = 1'b1;
`CTD :
cntD = 1'b1;
`ADD :
ldy = 1'b1;
`SUB :
begin
ldy = 1'b1;
cin = 1'b1;
end
`RDY :
ready = 1'b1;
endcase
end
endmodule
module YsTruthComplement(input[5:0] yIn , output[5:0] yOut);
assign yOut = yIn[5] ? ({yIn[5],!yIn[4],!yIn[3],!yIn[2],!yIn[1],!yIn[0]}+6'b1) : yIn;
endmodule
module XsTruthComplenet(input[3:0] xIn , output[3:0] xOut);
assign xOut = xIn[3] ? ({xIn[3],!xIn[2],!xIn[1],!xIn[0]}+4'b1) : xIn;
endmodule
module FourBitReg(input[3:0] in, input clk , input ld, output[3:0] out);
reg[3:0] q;
always @(posedge clk)
if(ld)
q = in;
assign out = q;
endmodule
module ElevenBitReg(input[10:0] in, input clk , input ld , input shift, output[10:0] out);
reg[10:0] q;
always @(posedge clk)
if(ld)
q = in;
else if(shift)
q = {q[10],q[10:1]};
assign out = q;
endmodule
module Summer(input[10:0] A, input[10:0] B , input cIn , output[10:0] out , output cOut);
assign {cOut,out} = A+B+cIn;
endmodule
module Counter(input clk , input enable , output reg[2:0] count);
initial count = 3'b110;
always @(posedge clk)
begin
if(enable)
count = count-1'b1;
if(count == 3'b111)
count = 3'b110;
end
endmodule
module BoothDataPath(input clk,input[3:0] x, input[5:0] y,input init,ldx,ldy,shift,cin,cntD,output[2:0] counterOut , output[1:0] yLow,output[9:0] out);
wire[5:0] yTCed;
wire[3:0] xTCed;
wire[3:0] xRegOut;
wire[10:0] yRegOut;
wire[10:0] sumOut;
YsTruthComplement yTC(y , yTCed);
XsTruthComplenet xTC(x , xTCed);
FourBitReg xReg(xTCed, clk , ldx, xRegOut);
ElevenBitReg yReg(init ? {4'b0,yTCed,1'b0} : sumOut, clk , ldy , shift, yRegOut);
Summer summer(cin ? {~xRegOut,7'b1111111} : {xRegOut,7'b0}, yRegOut , cin , sumOut,_);
Counter counter(clk , cntD , counterOut);
assign out = yRegOut[10:1];
assign yLow = yRegOut[1:0];
endmodule
module BoothAlgorithm(input clk,start,input[3:0] x,input[5:0] y,output[9:0] out,output ready);
wire init,ldx,ldy,shift,cin,cntD;
wire[2:0] countWire;
wire[1:0] yLow;
BoothController bCntr(clk,start,yLow,countWire,ready,init,ldx,ldy,shift,cin,cntD);
BoothDataPath bDP(clk,x, y,init,ldx,ldy,shift,cin,cntD,countWire,yLow,out);
endmodule
module BoothTest();
reg[5:0] y;
reg[3:0] x;
reg[9:0] expAns;
reg error,clk,start;
integer errorCount;
integer i,j;
wire [9:0] ans;
wire ready;
parameter delta = 5;
initial begin
$dumpfile("booth.vcd");
$dumpvars;
#90000 $finish;
end
initial begin clk = 0; forever #delta clk = ~clk; end
BoothAlgorithm UUT (clk,start,x,y,ans,ready);
initial begin
start = 0;
errorCount = 0;
#(2*delta) for (i=15; i>=0; i=i-1) begin
for (j=63;j>=0; j=j-1) begin
x = i;
y = j;
expAns = (i>7 ? (8-i) : i)*(j>31 ? (32-j) : j);
error = 0;
@(posedge clk) start = 1;
#delta start = 1'b1;
@(posedge ready) if (expAns-ans) error = 1;
errorCount = errorCount + error;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; auto start = std::chrono::high_resolution_clock::now(); long double crrtime() { auto stop = std::chrono::high_resolution_clock::now(); auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start); return ((long double)duration.count()) / ((long double)1e9); } mt19937 rng(2); int inline randn(int L, int R) { uniform_int_distribution<int> uid(L, R); return uid(rng); } int inline randn(int N) { uniform_int_distribution<int> uid(0, N - 1); return uid(rng); } const long long mod = 998244353; long long n; long long p[30]; long long a[30][26]; long long g[10000001]; long long h[10000001]; long long F[10000001]; void solve() { cin >> n; p[0] = 1; for (long long i = 1; i < 30; i++) p[i] = 2 * p[i - 1]; for (long long i = 0; i < n; i++) { string s; cin >> s; for (long long j = 0; j < 26; j++) a[i][j] = 0; for (char c : s) a[i][c - a ]++; } g[0] = 0; for (long long x = 1; x < p[n]; x++) { vector<long long> tmp(26, 100000); long long k = 0; h[x] = 0; for (long long i = 0; i < n; i++) { if (p[i] & x) { for (long long j = 0; j < 26; j++) tmp[j] = min(tmp[j], a[i][j]); k++; h[x]++; h[x] += i; } } long long cnt = 1; for (long long i = 0; i < 26; i++) cnt = (cnt * (tmp[i] + 1)) % mod; h[x] *= k; g[x] = cnt; if ((k & 1) == 0) g[x] = -cnt; } for (long long i = 0; i < (1 << n); ++i) F[i] = g[i]; for (long long i = 0; i < n; ++i) for (long long mask = 0; mask < (1 << n); ++mask) { if (mask & (1 << i)) F[mask] += F[mask ^ (1 << i)]; } long long ans = 0; for (long long i = 0; i < p[n]; i++) { F[i] %= mod; if (F[i] < 0) F[i] += mod; ans ^= (F[i] * h[i]); } cout << (ans) << n ; } signed main() { start = std::chrono::high_resolution_clock::now(); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long tt = 1; for (long long tc = 1; tc <= tt; ++tc) { solve(); } }
|
// ddrInput2.v
// Copyright (c) 2009-2010 Atomic Rules LLC, ALL RIGHTS RESERVED
//
// Transforms typ ddr250 (500Mb/lvds_pair/cycle) to 1/4 rate SDR (125 MHz)
//
// 2009-11-11 ssiegel Creation
// 2010-01-06 ssiegel Adapation to use V5 ISERDES_NODELAY, add IDELAY to clock
// 2010-01-07 ssiegel Fix delays on the data input; only adjust IODELAY on clock
// 2010-01-09 ssiegel Added ClkDlyVal and DataDlyVal paramaters
// 2010-01-11 ssiegel Tweak default delay; bitslip SDR by 1 click
// 2010-01-18 ssiegel Improved OSERDES Reset Synchronizer
// 2010-01-26 ssiegel Tie unused ISERDES CE2 to 1'b1 to quiet DRC check warning
// 2010-05-15 ssiegel Added the IODELAY_GRP paramater to set the IODELAY_GROUP attribute on IODELAYs
module ddrInput2#(
parameter ClockDlyVal = 0, // Number of 78.125 pS clicks of clock delay
parameter DataDlyVal = 18, // Number of 78.125 pS clicks of data delay
parameter ndb = 7,
parameter nsb = 2*ndb,
parameter IODELAY_GRP = "IODELAY_ADC") // Used to set the IODELAY_GROUP attribute on IODELAYs
( input ddrClk, // SE DDR clock ddr250 input_clock ddr
input[ndb-1:0] ddrDataP,ddrDataN, // DIFF DDR data ddr250 Bit#(7) Action
input psClk, // phase shift Control Clock c125 default_clock in
input psRstN, // reset to default delay c125 default_reset in
input psEna, // CE for Clock IDELAY up/down c125 Bool Action
input psInc, // Inc/Dec c125 Bool Action
output sdrClk, // SDR clock from BUFR sdr125 Clock sdrClk out
output[nsb-1:0] sdrData0, // SDR Data sdr125 First Bit#(14) Value
output[nsb-1:0] sdrData1 // SDR Data sdr125 Next Bit#(14) Value
);
wire ddrClkDly, rstSerdes;
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY # (
.DELAY_SRC("I"), // Port to be used, "I"=IDATAIN,"O"=ODATAIN,"DATAIN"=DATAIN,"IO"=Bi-directional
.HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
.IDELAY_TYPE("VARIABLE"), // "FIXED" or "VARIABLE"
.IDELAY_VALUE(ClockDlyVal), // 0 to 63 tap values
.ODELAY_VALUE(0), // 0 to 63 tap values
.REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
.SIGNAL_PATTERN("CLOCK") // Input signal type, "CLOCK" or "DATA"
) IODELAY_INST (
.DATAOUT(ddrClkDly), // 1-bit delayed data output
.C(psClk), // 1-bit clock input
.CE(psEna), // 1-bit clock enable input
.DATAIN(), // 1-bit internal data input
.IDATAIN(ddrClk), // 1-bit input data input (connect to port)
.INC(psInc), // 1-bit increment/decrement input
.ODATAIN(), // 1-bit output data input
.RST(!psRstN), // 1-bit active high, synch reset input
.T() // 1-bit 3-state control input
);
BUFIO bufio_i(.O(ddrIoClk),.I(ddrClkDly));
BUFR#(.BUFR_DIVIDE("2"),.SIM_DEVICE("VIRTEX5")) bufr_i(.O(sdrClk),.CE(1'b1),.CLR(1'b0),.I(ddrClkDly));
FDRSE#(.INIT(1'b0))
FRDSE_inst (.Q(rstSerdes), .C(sdrClk), .CE(1'b1), .D(!psRstN), .R(1'b0), .S(1'b0));
// The DDR/SDR Input datapath...
wire[ndb-1:0] ddrData;
wire[(ndb-1):0] ddrDataDly;
genvar i; generate
for (i=0;i<ndb;i=i+1) begin : DDR_g
IBUFDS#(.IOSTANDARD("LVDS_25")) ibufds_i(.O(ddrData[i]),.I(ddrDataP[i]),.IB(ddrDataN[i]));
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY # (
.DELAY_SRC("I"), // Port to be used, "I"=IDATAIN,"O"=ODATAIN,"DATAIN"=DATAIN,"IO"=Bi-directional
.HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
.IDELAY_TYPE("FIXED"), // "FIXED" or "VARIABLE"
.IDELAY_VALUE(DataDlyVal), // 0 to 63 tap values
.ODELAY_VALUE(0), // 0 to 63 tap values
.REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
.SIGNAL_PATTERN("DATA") // Input signal type, "CLOCK" or "DATA"
) IODELAY_INST (
.DATAOUT(ddrDataDly[i]), // 1-bit delayed data output
.C(1'b0), // 1-bit clock input
.CE(1'b0), // 1-bit clock enable input
.DATAIN(), // 1-bit internal data input
.IDATAIN(ddrData[i]), // 1-bit input data input (connect to port)
.INC(1'b0), // 1-bit increment/decrement input
.ODATAIN(), // 1-bit output data input
.RST(rstSerdes), // 1-bit active high, synch reset input
.T() // 1-bit 3-state control input
);
ISERDES_NODELAY #(
.BITSLIP_ENABLE("TRUE"), // "TRUE"/"FALSE" to enable bitslip controller
.DATA_RATE("DDR"), // Specify data rate of "DDR" or "SDR"
.DATA_WIDTH(4), // Specify data width -
.INTERFACE_TYPE("NETWORKING"), // Use model - "MEMORY" or "NETWORKING"
.NUM_CE(1), // Number of clock enables used, 1 or 2
.SERDES_MODE("MASTER") // Set SERDES mode to "MASTER" or "SLAVE"
) ISERDES_NODELAY_inst (
.Q1(), // 1-bit registered SERDES output
.Q2(sdrData1[(i*2)+1]), // 1-bit registered SERDES output (late sample, odd bit)
.Q3(sdrData1[(i*2)+0]), // 1-bit registered SERDES output (late sample, even bit)
.Q4(sdrData0[(i*2)+1]), // 1-bit registered SERDES output (early sample, odd bit)
.Q5(sdrData0[(i*2)+0]), // 1-bit registered SERDES output (early sample, even bit)
.Q6(), // 1-bit registered SERDES output
.SHIFTOUT1(), // 1-bit cascade Master/Slave output
.SHIFTOUT2(), // 1-bit cascade Master/Slave output
.BITSLIP(1'b0), // 1-bit Bitslip enable input
.CE1(1'b1), // 1-bit clock enable input
.CE2(1'b1), // 1-bit clock enable input
.CLK(ddrIoClk), // 1-bit master clock input
.CLKB(!ddrIoClk), // 1-bit secondary clock input for DATA_RATE=DDR
.CLKDIV(sdrClk), // 1-bit divided clock input
.D(ddrDataDly[i]), // 1-bit data input, connects to IODELAY or input buffer
.OCLK(), // 1-bit fast output clock input
.RST(rstSerdes), // 1-bit asynchronous reset input
.SHIFTIN1(1'b0), // 1-bit cascade Master/Slave input
.SHIFTIN2(1'b0) // 1-bit cascade Master/Slave input
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_4_V
`define SKY130_FD_SC_HD__SEDFXTP_4_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_4 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_4 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_4_V
|
/*
-- ============================================================================
-- FILE NAME : chip_top.v
-- DESCRIPTION : gbvW
[
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "gpio.h"
/********** W
[ **********/
module chip_top (
/********** NbN & Zbg **********/
input wire clk_ref, // îêNbN
input wire reset_sw // O[oZbg
/********** UART **********/
`ifdef IMPLEMENT_UART // UARTÀ
, input wire uart_rx // UARTóMM
, output wire uart_tx // UARTMM
`endif
/********** ÄpüoÍ|[g **********/
`ifdef IMPLEMENT_GPIO // GPIOÀ
`ifdef GPIO_IN_CH // üÍ|[gÌÀ
, input wire [`GPIO_IN_CH-1:0] gpio_in // üÍ|[g
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÀ
, output wire [`GPIO_OUT_CH-1:0] gpio_out // oÍ|[g
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÀ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // üoÍ|[g
`endif
`endif
);
/********** NbN & Zbg **********/
wire clk; // NbN
wire clk_; // ½]NbN
wire chip_reset; // `bvZbg
/********** NbNW
[ **********/
clk_gen clk_gen (
/********** NbN & Zbg **********/
.clk_ref (clk_ref), // îêNbN
.reset_sw (reset_sw), // O[oZbg
/********** ¶¬NbN **********/
.clk (clk), // NbN
.clk_ (clk_), // ½]NbN
/********** `bvZbg **********/
.chip_reset (chip_reset) // `bvZbg
);
/********** `bv **********/
chip chip (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.clk_ (clk_), // ½]NbN
.reset (chip_reset) // Zbg
/********** UART **********/
`ifdef IMPLEMENT_UART
, .uart_rx (uart_rx) // UARTóMg`
, .uart_tx (uart_tx) // UARTMg`
`endif
/********** ÄpüoÍ|[g **********/
`ifdef IMPLEMENT_GPIO
`ifdef GPIO_IN_CH // üÍ|[gÌÀ
, .gpio_in (gpio_in) // üÍ|[g
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÀ
, .gpio_out (gpio_out) // oÍ|[g
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÀ
, .gpio_io (gpio_io) // üoÍ|[g
`endif
`endif
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_dtl_impctl_pullup.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_dtl_impctl_pullup(rclk ,ctu_io_sscan_update ,ctu_global_snap ,
tclk ,ctu_io_sscan_se ,si ,we_csr ,from_csr ,se ,ctu_io_sscan_in ,
hard_reset_n ,clk_dis_l ,vddo ,z ,to_csr ,so_l ,imped_shadow_so ,
deltabit ,pad );
output [7:0] z ;
output [7:0] to_csr ;
input [7:0] from_csr ;
output so_l ;
output imped_shadow_so ;
output deltabit ;
input rclk ;
input ctu_io_sscan_update ;
input ctu_global_snap ;
input tclk ;
input ctu_io_sscan_se ;
input si ;
input we_csr ;
input se ;
input ctu_io_sscan_in ;
input hard_reset_n ;
input clk_dis_l ;
input vddo ;
inout pad ;
supply1 vdd ;
wire [7:0] z_post ;
wire [7:0] d ;
wire [7:0] net097 ;
wire [7:0] net47 ;
wire [7:0] net054 ;
wire clk ;
wire above ;
wire global_reset_n ;
wire sodr_l ;
wire bypass ;
wire updclk ;
wire sos ;
wire net0110 ;
wire clk_en_l ;
wire net081 ;
wire sclk ;
wire avgcntr_rst ;
bw_u1_inv_5x I44_0_ (
.z (net054[7] ),
.a (d[7] ) );
bw_u1_inv_5x I43_2_ (
.z (net097[5] ),
.a (net054[5] ) );
bw_u1_inv_4x I28_1_ (
.z (net47[6] ),
.a (z_post[6] ) );
bw_u1_inv_10x I29_7_ (
.z (z[7] ),
.a (net47[0] ) );
bw_u1_inv_5x I44_1_ (
.z (net054[6] ),
.a (d[6] ) );
bw_u1_inv_5x I43_3_ (
.z (net097[4] ),
.a (net054[4] ) );
bw_u1_inv_4x I28_2_ (
.z (net47[5] ),
.a (z_post[5] ) );
bw_u1_inv_10x I29_0_ (
.z (z[0] ),
.a (net47[7] ) );
bw_io_impctl_dtl_uprcn I241 (
.cbu ({net097[0] ,net097[1] ,net097[2] ,net097[3] ,
net097[4] ,net097[5] ,net097[6] ,net097[7] } ),
.si_l (net081 ),
.so_l (sodr_l ),
.pad (pad ),
.sclk (sclk ),
.vddo (vddo ),
.above (above ),
.clk (clk ),
.se (se ),
.global_reset_n (global_reset_n ) );
bw_u1_inv_5x I44_2_ (
.z (net054[5] ),
.a (d[5] ) );
bw_u1_inv_5x I43_4_ (
.z (net097[3] ),
.a (net054[3] ) );
bw_u1_inv_4x I28_3_ (
.z (net47[4] ),
.a (z_post[4] ) );
bw_u1_inv_10x I29_1_ (
.z (z[1] ),
.a (net47[6] ) );
bw_u1_inv_5x I44_3_ (
.z (net054[4] ),
.a (d[4] ) );
bw_u1_inv_5x I43_5_ (
.z (net097[2] ),
.a (net054[2] ) );
bw_u1_inv_4x I28_4_ (
.z (net47[3] ),
.a (z_post[3] ) );
bw_u1_inv_10x I29_2_ (
.z (z[2] ),
.a (net47[5] ) );
bw_u1_inv_5x I44_4_ (
.z (net054[3] ),
.a (d[3] ) );
bw_u1_inv_5x I43_6_ (
.z (net097[1] ),
.a (net054[1] ) );
bw_u1_inv_4x I28_5_ (
.z (net47[2] ),
.a (z_post[2] ) );
bw_u1_inv_10x I29_3_ (
.z (z[3] ),
.a (net47[4] ) );
bw_io_impctl_smachine_new I23 (
.z_post ({z_post } ),
.from_csr ({from_csr } ),
.to_csr ({to_csr } ),
.d ({d } ),
.deltabit (deltabit ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.updclk (updclk ),
.we_csr (we_csr ),
.l2clk (rclk ),
.ctu_io_sscan_in (ctu_io_sscan_in ),
.above (above ),
.bypass (bypass ),
.config_pmos (vdd ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.ctu_global_snap (ctu_global_snap ),
.sclk (sclk ),
.avgcntr_rst (avgcntr_rst ),
.so (sos ),
.se (se ),
.si_l (sodr_l ),
.io_ctu_sscan_out (imped_shadow_so ),
.tclk (tclk ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.clk_en_l (clk_en_l ) );
bw_io_impctl_dtl_clkgen I24 (
.se (se ),
.updclk (updclk ),
.clk (clk ),
.so_l (so_l ),
.si_l (sos ),
.synced_upd_imped (ctu_io_sscan_update ),
.avgcntr_rst (avgcntr_rst ),
.bypass (bypass ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.sclk (sclk ),
.reset_l (vdd ) );
bw_u1_inv_5x I44_5_ (
.z (net054[2] ),
.a (d[2] ) );
bw_u1_inv_5x I43_7_ (
.z (net097[0] ),
.a (net054[0] ) );
bw_u1_inv_4x I28_6_ (
.z (net47[1] ),
.a (z_post[1] ) );
bw_u1_inv_10x I29_4_ (
.z (z[4] ),
.a (net47[3] ) );
bw_u1_ckenbuf_14x I30 (
.clk (clk ),
.rclk (rclk ),
.en_l (clk_en_l ),
.tm_l (net0110 ) );
bw_u1_inv_10x I34 (
.z (clk_en_l ),
.a (clk_dis_l ) );
bw_u1_inv_5x I43_0_ (
.z (net097[7] ),
.a (net054[7] ) );
bw_u1_inv_5x I44_6_ (
.z (net054[1] ),
.a (d[1] ) );
bw_u1_inv_4x I28_7_ (
.z (net47[0] ),
.a (z_post[0] ) );
bw_u1_inv_10x I29_5_ (
.z (z[5] ),
.a (net47[2] ) );
bw_u1_inv_8x I41 (
.z (net081 ),
.a (si ) );
bw_u1_inv_4x I42 (
.z (net0110 ),
.a (se ) );
bw_u1_inv_5x I43_1_ (
.z (net097[6] ),
.a (net054[6] ) );
bw_u1_inv_5x I44_7_ (
.z (net054[0] ),
.a (d[0] ) );
bw_u1_inv_4x I28_0_ (
.z (net47[7] ),
.a (z_post[7] ) );
bw_u1_inv_10x I29_6_ (
.z (z[6] ),
.a (net47[1] ) );
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32, 64, or 96 bit received data into a 128 bit wide
// FIFO. Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_128 (
input CLK,
input RST,
input [127:0] DATA_IN, // Incoming data
input [2:0] DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [127:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg [2:0] rPackedCount=0, _rPackedCount=0;
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [223:0] rPackedData=224'd0, _rPackedData=224'd0;
reg [127:0] rDataIn=128'd0, _rDataIn=128'd0;
reg [2:0] rDataInEn=0, _rDataInEn=0;
reg [127:0] rDataMasked=128'd0, _rDataMasked=128'd0;
reg [2:0] rDataMaskedEn=0, _rDataMaskedEn=0;
assign PACKED_DATA = rPackedData[127:0];
assign PACKED_WEN = rPackedCount[2];
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data until 4 words are available, then writes 4 words out.
wire [127:0] wMask = {128{1'b1}}<<(32*rDataInEn);
wire [127:0] wDataMasked = ~wMask & rDataIn;
always @ (posedge CLK) begin
rPackedCount <= #1 (RST ? 3'd0 : _rPackedCount);
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rPackedData <= #1 (RST ? 224'd0 : _rPackedData);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 3'd0 : _rDataInEn);
rDataMasked <= #1 _rDataMasked;
rDataMaskedEn <= #1 (RST ? 3'd0 : _rDataMaskedEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
_rDataMasked = wDataMasked;
_rDataMaskedEn = rDataInEn;
// Count what's in our buffer. When we reach 4 words, 4 words will be written
// out. If flush is requested, write out whatever remains.
if (rPackedFlush && (rPackedCount[1] | rPackedCount[0]))
_rPackedCount = 4;
else
_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[2], 2'd0};
// Shift data into and out of our buffer as we receive and write out data.
if (rDataMaskedEn != 3'd0)
_rPackedData = ((rPackedData>>(32*{rPackedCount[2], 2'd0})) | (rDataMasked<<(32*rPackedCount[1:0])));
else
_rPackedData = (rPackedData>>(32*{rPackedCount[2], 2'd0}));
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int in() { int x, y; y = scanf( %d , &x); return x; } const int N = 2 * 100 * 1000 + 5; int a[N], ans[N]; vector<pair<int, int>> v; int seg[4 * N]; void add(int p, int s = 0, int e = N, int x = 1) { seg[x]++; if (e - s == 1) return; int mid = (s + e) / 2; if (p < mid) add(p, s, mid, 2 * x); else add(p, mid, e, 2 * x + 1); } int pth(int p, int s = 0, int e = N, int x = 1) { if (e - s == 1) return s; int mid = (s + e) / 2; if (seg[2 * x] >= p) return pth(p, s, mid, 2 * x); else return pth(p - seg[2 * x], mid, e, 2 * x + 1); } int main() { int n = in(); for (int i = 0; i < n; i++) { a[i] = in(); v.push_back({-a[i], i}); } sort(v.begin(), v.end()); vector<pair<pair<int, int>, int>> que; int m = in(); for (int i = 0; i < m; i++) { int k = in(), p = in(); que.push_back({{k, p}, i}); } sort(que.begin(), que.end()); int r = 0; for (auto q : que) { int k = q.first.first, p = q.first.second, t = q.second; while (r < k) { add(v[r++].second); } ans[t] = a[pth(p)]; } for (int i = 0; i < m; i++) cout << ans[i] << n ; return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_velocityControlHdl.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_velocityControlHdl
// Source Path: velocityControlHdl
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_velocityControlHdl
(
CLK_IN,
reset,
enb_1_2000_0,
reset_1,
command,
measured,
phase_currents_0,
phase_currents_1,
electrical_position,
param_velocity_p_gain,
param_velocity_i_gain,
param_current_p_gain,
param_current_i_gain,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
dq_currents_0,
dq_currents_1
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input reset_1;
input signed [17:0] command; // sfix18_En8
input signed [17:0] measured; // sfix18_En8
input signed [17:0] phase_currents_0; // sfix18_En15
input signed [17:0] phase_currents_1; // sfix18_En15
input signed [17:0] electrical_position; // sfix18_En14
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [19:0] phase_voltages_0; // sfix20_En12
output signed [19:0] phase_voltages_1; // sfix20_En12
output signed [19:0] phase_voltages_2; // sfix20_En12
output signed [17:0] dq_currents_0; // sfix18_En15
output signed [17:0] dq_currents_1; // sfix18_En15
wire signed [17:0] Control_Velocity_out1; // sfix18_En15
wire signed [17:0] sin_coefficient; // sfix18_En16
wire signed [17:0] cos_coefficient; // sfix18_En16
wire signed [17:0] d_current; // sfix18_En15
wire signed [17:0] q_current; // sfix18_En15
wire signed [17:0] d_voltage; // sfix18_En12
wire signed [17:0] q_voltage; // sfix18_En12
wire signed [17:0] Transform_dq_to_ABC_out1_0; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_1; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_2; // sfix18_En13
wire signed [19:0] Space_Vector_Modulation_out1_0; // sfix20_En12
wire signed [19:0] Space_Vector_Modulation_out1_1; // sfix20_En12
wire signed [19:0] Space_Vector_Modulation_out1_2; // sfix20_En12
// Velocity Control HDL
//
// Outer velocity control with inner loop current control.
// <Root>/Control_Velocity
velocityControlHdl_Control_Velocity u_Control_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(reset_1),
.velocity_command(command), // sfix18_En8
.velocity_measured(measured), // sfix18_En8
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.q_command(Control_Velocity_out1) // sfix18_En15
);
// <Root>/Sin_Cos1
velocityControlHdl_Sin_Cos1 u_Sin_Cos1 (.x(electrical_position), // sfix18_En14
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient) // sfix18_En16
);
// <Root>/Transform_ABC_to_dq
//
// <Root>/Mux
velocityControlHdl_Transform_ABC_to_dq u_Transform_ABC_to_dq (.phase_currents_0(phase_currents_0), // sfix18_En15
.phase_currents_1(phase_currents_1), // sfix18_En15
.sin_coefficient(sin_coefficient), // sfix18_En16
.cos_coefficient(cos_coefficient), // sfix18_En16
.d_current(d_current), // sfix18_En15
.q_current(q_current) // sfix18_En15
);
// Linear Current Controllers
//
// PID Blocks used for Control Design of Current Loop controllers.
//
// <Root>/Control_DQ_Currents
velocityControlHdl_Control_DQ_Currents u_Control_DQ_Currents (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(reset_1),
.q_current_command(Control_Velocity_out1), // sfix18_En15
.d_current_measured(d_current), // sfix18_En15
.q_current_measured(q_current), // sfix18_En15
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.d_voltage(d_voltage), // sfix18_En12
.q_voltage(q_voltage) // sfix18_En12
);
// <Root>/Transform_dq_to_ABC
velocityControlHdl_Transform_dq_to_ABC u_Transform_dq_to_ABC (.d(d_voltage), // sfix18_En12
.q(q_voltage), // sfix18_En12
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient), // sfix18_En16
.ABC_0(Transform_dq_to_ABC_out1_0), // sfix18_En13
.ABC_1(Transform_dq_to_ABC_out1_1), // sfix18_En13
.ABC_2(Transform_dq_to_ABC_out1_2) // sfix18_En13
);
// <Root>/Space_Vector_Modulation
velocityControlHdl_Space_Vector_Modulation u_Space_Vector_Modulation (.Vabc_Raw_0(Transform_dq_to_ABC_out1_0), // sfix18_En13
.Vabc_Raw_1(Transform_dq_to_ABC_out1_1), // sfix18_En13
.Vabc_Raw_2(Transform_dq_to_ABC_out1_2), // sfix18_En13
.phase_voltages_0(Space_Vector_Modulation_out1_0), // sfix20_En12
.phase_voltages_1(Space_Vector_Modulation_out1_1), // sfix20_En12
.phase_voltages_2(Space_Vector_Modulation_out1_2) // sfix20_En12
);
assign phase_voltages_0 = Space_Vector_Modulation_out1_0;
assign phase_voltages_1 = Space_Vector_Modulation_out1_1;
assign phase_voltages_2 = Space_Vector_Modulation_out1_2;
assign dq_currents_0 = d_current;
assign dq_currents_1 = q_current;
endmodule // velocityControlHdl_velocityControlHdl
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ac.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No user `defines in this module
module ent_ac
//
// Generated Module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; string s[n]; for (int i = 0; i < n; i++) cin >> s[i]; int ans = 0; for (int i = 0; i < m - 1; i++) { if (s[n - 1][i] == D ) ++ans; } for (int i = 0; i < n - 1; i++) { if (s[i][m - 1] == R ) ++ans; } cout << ans << endl; } int main() { int t; cin >> t; while (t--) { solve(); } }
|
`timescale 1ns / 1ps
module Freq_Count_Top(
input sys_clk_50m,ch_c,
output reg [63:0] freq_reg,
input sys_rst_n
);
reg Gate_1S; //1ÃëÖÓ¼ÆÊý´°¿Ú
wire Load;
reg EN_FT;
reg CLR;
//-----------------------------------------------------------------------
parameter HIGH_TIME_Gate_1S = 50_000_000;
parameter LOW_TIME_Gate_1S = 100_000_000;
//-----------------------------------------------------------------------
reg [31:0] count;
always@(posedge sys_clk_50m or negedge sys_rst_n)begin
if(!sys_rst_n)begin
count <= 32'b0;
Gate_1S <= 1'b0;
end
else begin
count <= count + 1'b1;
if(count == HIGH_TIME_Gate_1S)
Gate_1S <= 1'b0;
else if(count == LOW_TIME_Gate_1S)begin
count <= 32'b1;
Gate_1S <= 1'b1;
end
end
end
//-----------------------------------------------------------------------
always@(posedge ch_c)
CLR <= Gate_1S | EN_FT;
always@(posedge ch_c or negedge sys_rst_n)begin
if(!sys_rst_n)begin
EN_FT = 0;
end
else begin
EN_FT = Gate_1S;
end
end
assign Load = !EN_FT;
reg [63:0] FT_out;
always @(posedge ch_c or negedge CLR)begin
if(!CLR)begin
FT_out <= 64'b0;
end
else if(EN_FT)begin
FT_out <= FT_out + 1'b1;
end
end
// COUNTER_LOAD_MACRO #(
// .COUNT_BY(48'h000000000001),
// .DEVICE("7SERIES"),
// .WIDTH_DATA(48)
// ) freq_counter (
// .Q(FT_out),
// .CLK(ch_c),
// .CE(EN_FT),
// .DIRECTION(1'b1),
// .LOAD(CLR),
// .LOAD_DATA(32'b0),
// .RST(!sys_rst_n)
// );
always@(posedge Load)begin
//freq_reg <= {16'b0, FT_out};
freq_reg <= FT_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 305; string s[MAX_N][MAX_N], t[MAX_N][MAX_N]; int cnt0[MAX_N], cnt1[MAX_N]; int n, m; struct Move { int x_1, y_1, x_2, y_2; Move(int x_1_, int y_1_, int x_2_, int y_2_) : x_1(x_1_), y_1(y_1_), x_2(x_2_), y_2(y_2_) {} Move() {} }; vector<Move> ans; void go0(int i, int j) { if (i == 0 && j == 0) { ans.push_back(Move(0, 0, 0, m - 1)); ans.push_back(Move(0, m - 1, 0, 0)); } if (j != 0) ans.push_back(Move(0, 0, 0, j)); if (i != 0) ans.push_back(Move(0, j, i, j)); } void go1(int i, int j) { if (i == n - 1 && j == m - 1) { ans.push_back(Move(n - 1, m - 1, 0, m - 1)); ans.push_back(Move(0, m - 1, n - 1, m - 1)); } if (i != n - 1) ans.push_back(Move(n - 1, m - 1, i, m - 1)); if (j != m - 1) ans.push_back(Move(i, m - 1, i, j)); } int main() { scanf( %d%d , &n, &m); for (int i = 0; (i) < (n); ++i) { for (int j = 0; (j) < (m); ++j) cin >> s[i][j]; } for (int i = 0; (i) < (n); ++i) { for (int j = 0; (j) < (m); ++j) cin >> t[i][j]; } for (int i = (1); (i) < (n - 1); ++i) for (int j = 0; (j) < (m); ++j) { int len = (int)((s[i][j]).size()); for (int g = (len)-1; (g) >= 0; --g) { if (s[i][j][g] == 0 ) ans.push_back(Move(i, j, 0, j)), cnt0[j]++; else ans.push_back(Move(i, j, n - 1, j)), cnt1[j]++; } } for (int j = 0; (j) < (m); ++j) { int len = (int)((s[0][j]).size()); for (int g = (len)-1; (g) >= 0; --g) if (s[0][j][g] == 1 ) ans.push_back(Move(0, j, n - 1, j)), cnt1[j]++; else { if (j != 0) ans.push_back(Move(0, j, 0, 0)), cnt0[0]++; else ans.push_back(Move(0, 0, 0, m - 1)), cnt0[m - 1]++; } } for (int j = (m)-1; (j) >= 0; --j) { int len = (int)((s[n - 1][j]).size()); for (int g = (len)-1; (g) >= 0; --g) if (s[n - 1][j][g] == 0 ) ans.push_back(Move(n - 1, j, 0, j)), cnt0[j]++; else { if (j != m - 1) ans.push_back(Move(n - 1, j, n - 1, m - 1)), cnt1[m - 1]++; else ans.push_back(Move(n - 1, m - 1, n - 1, 0)), cnt1[0]++; } } for (int i = (1); (i) < (m); ++i) for (int g = 0; (g) < (cnt0[i]); ++g) ans.push_back(Move(0, i, 0, 0)); for (int i = 0; (i) < (m - 1); ++i) for (int g = 0; (g) < (cnt1[i]); ++g) ans.push_back(Move(n - 1, i, n - 1, m - 1)); vector<pair<int, int> > v; for (int i = (1); (i) < (n); ++i) for (int j = 0; (j) < (m - 1); ++j) { v.push_back(make_pair(i, j)); } for (int j = (1); (j) < (m - 1); ++j) v.push_back(make_pair(0, j)); for (int i = (1); (i) < (n - 1); ++i) v.push_back(make_pair(i, m - 1)); v.push_back(make_pair(0, 0)); v.push_back(make_pair(n - 1, m - 1)); v.push_back(make_pair(0, m - 1)); for (auto np : v) { int x = np.first, y = np.second; int len = (int)((t[x][y]).size()); for (int g = (len)-1; (g) >= 0; --g) { if (t[x][y][g] == 0 ) go0(x, y); else go1(x, y); } } printf( %d n , (int)((ans).size())); for (auto mov : ans) { printf( %d %d %d %d n , mov.x_1 + 1, mov.y_1 + 1, mov.x_2 + 1, mov.y_2 + 1); } return 0; }
|
`default_nettype none
`define CLKFREQ 48000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk
);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk
);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data // data
);
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s[1001], d[1001], i, a, S; cin >> n; for (i = 1; i <= n; i++) { cin >> s[i] >> d[i]; } S = s[1]; for (i = 2; i <= n; i++) { if (s[i] <= S) { int x = ((S - s[i]) / d[i]) + 1; S = s[i] + d[i] * x; } else S = s[i]; } cout << S; }
|
//**************************************************************************
module COUNTER(CLOCK_I, nARST_I, COUNT_O);
parameter CBITS = 3;
input CLOCK_I;
input nARST_I;
output[CBITS-1:0] COUNT_O;
reg[CBITS-1:0] COUNT_O;
always @(posedge CLOCK_I or negedge nARST_I)
if(nARST_I==1'b0)
COUNT_O <= {CBITS{1'b0}};
else
COUNT_O <= COUNT_O + 1;
endmodule
//--------------------------------------------------------------------------
module MULTIPLE_COUNTERS(CLOCK_I, nARST_I, COUNT_O);
parameter M = 3;
parameter CBITS = 4;
input CLOCK_I;
input nARST_I;
output[M*CBITS-1:0] COUNT_O;
COUNTER #(.CBITS(CBITS)) INST_COUNTER[M-1:0] (CLOCK_I, nARST_I, COUNT_O);
endmodule
//--------------------------------------------------------------------------
module TEST_COUNTER;
parameter M = 2;
parameter CBITS = 2;
reg CLOCK;
reg nARST;
reg CTRL_I;
wire[M*CBITS-1:0] COUNTS;
MULTIPLE_COUNTERS #(.M(M),
.CBITS(CBITS)) INST_MCTR(CLOCK, nARST, COUNTS);
initial CLOCK=1;
always #5 CLOCK=~CLOCK;
initial
begin
nARST=1;
#5 nARST=0;
#5 nARST=1;
#200 $display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int N = 52; int n, T; int t[N], x[N], c[5]; long long f[2][N][N][N * N + 50]; long long g[2][N][N * N]; long long cnt[N][N][N]; long long dp[N][N][N][4], fac[N]; int main() { fac[0] = 1; for (int i = 1; i < N; i++) fac[i] = 1LL * fac[i - 1] * i % MOD; scanf( %d%d , &n, &T); for (int i = 1; i <= n; i++) scanf( %d%d , &t[i], &x[i]), c[x[i]]++; f[0][0][0][0] = 1, g[0][0][0] = 1; for (int i = 1; i <= n; i++) { if (x[i] == 1 || x[i] == 2) { memset(f[1], 0, sizeof(f[1])); for (int j = 0; j <= c[1]; j++) { for (int k = 0; k <= c[2]; k++) { for (int s = 0; s <= 2500; s++) { if (s + t[i] <= 2500) { if (x[i] == 1) (f[1][j + 1][k][s + t[i]] += f[0][j][k][s]) %= MOD; if (x[i] == 2) (f[1][j][k + 1][s + t[i]] += f[0][j][k][s]) %= MOD; } (f[1][j][k][s] += f[0][j][k][s]) %= MOD; } } } for (int j = 0; j <= c[1]; j++) for (int k = 0; k <= c[2]; k++) for (int s = 0; s <= 2500; s++) f[0][j][k][s] = f[1][j][k][s]; } else { memset(g[1], 0, sizeof(g[1])); for (int j = 0; j <= c[3]; j++) { for (int s = 0; s <= 2500; s++) { (g[1][j + 1][s + t[i]] += g[0][j][s]) %= MOD; (g[1][j][s] += g[0][j][s]) %= MOD; } } for (int j = 0; j <= c[3]; j++) for (int s = 0; s <= 2500; s++) g[0][j][s] = g[1][j][s]; } } long long ans = 0; for (int j = 0; j <= c[1]; j++) { for (int k = 0; k <= c[2]; k++) { for (int s1 = 0; s1 <= T; s1++) { for (int l = 0; l <= c[3]; l++) { int s2 = T - s1; if (f[0][j][k][s1] && g[0][l][s2]) { (cnt[j][k][l] += 1LL * f[0][j][k][s1] * g[0][l][s2]) %= MOD; } } } } } dp[0][0][0][0] = 1; for (int i = 0; i <= c[1]; i++) { for (int j = 0; j <= c[2]; j++) { for (int k = 0; k <= c[3]; k++) { for (int l = i == 0 ? 0 : 1; l <= 3; l++) { if (i < c[1] && l != 1) (dp[i + 1][j][k][1] += dp[i][j][k][l]) %= MOD; if (j < c[2] && l != 2) (dp[i][j + 1][k][2] += dp[i][j][k][l]) %= MOD; if (k < c[3] && l != 3) (dp[i][j][k + 1][3] += dp[i][j][k][l]) %= MOD; } } } } for (int i = 0; i <= c[1]; i++) for (int j = 0; j <= c[2]; j++) for (int k = 0; k <= c[3]; k++) for (int l = 1; l <= 3; l++) { if (cnt[i][j][k] && dp[i][j][k][l]) { ans = ans + 1LL * dp[i][j][k][l] * cnt[i][j][k] % MOD * fac[i] % MOD * fac[j] % MOD * fac[k] % MOD; ans = ans % MOD; } } cout << ans << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND4BB_BEHAVIORAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9, MOD = 1e9 + 7; const int n_ = 1e5 + 1000; long long gcd(long long a, long long b) { return (a ? gcd(b % a, a) : b); } long long power(long long a, long long n) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; } n >>= 1; a *= a; } return p; } long long power(long long a, long long n, long long mod) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; p %= mod; } n >>= 1; a *= a; a %= mod; } return p % mod; } int main() { ios_base::sync_with_stdio(false); long long n, x, y, a; scanf( %lld %lld %lld , &n, &x, &y); a = y - n + 1; if (a > 0 && a * a + n - 1 >= x) { for (int(i) = 0; (i) < (n - 1); (i)++) puts( 1 ); printf( %lld n , a); } else { puts( -1 ); } return 0; }
|
// bsg_tag_master
//
// 8/30/2016
//
// Usage: send a stream of 0's to reset master node and/or noop.
// Then, send a single <1> followed by a packet:
// < id > < data_not_reset > < payload length > < payload >
// ****************************************************************************
// $clog2(els_p+1) 1 $clog2(max_payload_length+1) (variable size)
//
// To reset client nodes, set data_not_reset to 0, and payload to 1's.
//
//
`include "bsg_defines.v"
`include "bsg_tag.vh"
// will not build in verilator without this
// possibly resulting incorrect behavior :(
// verilator lint_off BLKANDNBLK
module bsg_tag_master_decentralized
import bsg_tag_pkg::bsg_tag_s;
// els_p is the maximum number of clients supported in system
// local_els_p is the number of clients to attach
// lg_width_p is the number of bits used to describe the payload size
#(`BSG_INV_PARAM(els_p)
,`BSG_INV_PARAM(local_els_p)
,`BSG_INV_PARAM(lg_width_p)
,debug_level_lp=1
,lg_els_lp=`BSG_SAFE_CLOG2(els_p)
,lg_local_els_lp=`BSG_SAFE_CLOG2(local_els_p)
)
(
// from pins
input clk_i
,input data_i
// node_id_offset_i is used to filter incoming packets.
// packets with nodeID < node_id_offset_i or nodeID >= node_id_offset_i+local_els_p
// will be ignored.
,input [lg_els_lp-1:0] node_id_offset_i
,output bsg_tag_s [local_els_p-1:0] clients_o
);
`declare_bsg_tag_header_s(els_p,lg_width_p)
localparam max_packet_len_lp = `bsg_tag_max_packet_len(els_p,lg_width_p);
localparam reset_len_lp = `bsg_tag_reset_len(els_p,lg_width_p);
// counts 0..max_packet_len_lp
localparam lg_max_packet_len_lp = `BSG_SAFE_CLOG2(max_packet_len_lp+1);
// synopsys translate_off
if (debug_level_lp > 2)
always @(negedge clk_i)
$display("## bsg_tag_master clients=%b (%m)",clients_o);
// synopsys translate_on
logic data_i_r;
always @(posedge clk_i)
data_i_r <= data_i;
// ***************************
// RESET LOGIC
// extra bit to detect carry out in counter
localparam ctr_width_lp = lg_max_packet_len_lp+1;
logic [ctr_width_lp-1:0] zeros_ctr_r;
wire tag_reset_req = zeros_ctr_r[ctr_width_lp-1];
// this self-clearing counter detects a certain number
// of consecutive 0's
// indicating a tag_master reset condition
//
bsg_counter_clear_up #(.max_val_p((1 << ctr_width_lp)-1)
,.init_val_p(0)
) bccu
(.clk_i (clk_i)
,.reset_i(1'b0)
// we clear the counter if we hit the limit
,.clear_i(data_i_r | tag_reset_req)
,.up_i (~data_i_r)
,.count_o(zeros_ctr_r)
);
// veri lator doesn't support -d
// synopsys translate_off
initial
$display("## %m instantiating bsg_tag_master_decentralized with els_p=%d, local_els_p=%d, lg_width_p=%d, max_packet_len_lp=%d, reset_zero_len=%d"
,els_p,local_els_p,lg_width_p,max_packet_len_lp,reset_len_lp);
// synopsys translate_on
//
// END RESET LOGIC
// ***************************
logic [lg_max_packet_len_lp-1:0] hdr_ptr_r, hdr_ptr_n;
bsg_tag_header_s hdr_r, hdr_n;
// sending
logic v_n;
// value to send
bsg_tag_s bsg_tag_n;
typedef enum logic [1:0] {eStart, eHeader, eTransfer, eStuck} state_e;
state_e state_r, state_n;
// synopsys sync_set_reset "tag_reset_req, data_i_r"
always_ff @(posedge clk_i)
// if we hit the counter AND (subtle bug) there is no valid incoming data that would get lost
if (tag_reset_req & ~data_i_r)
begin
// synopsys translate_off
if (debug_level_lp > 2) $display("## bsg_tag_master RESET time %t (%m)",$time);
// synopsys translate_on
state_r <= eStart;
// we put this here because DC did not currently infer "reset" logic
hdr_ptr_r <= 0;
end
else
begin
state_r <= state_n;
hdr_ptr_r <= hdr_ptr_n;
end
always_ff @(posedge clk_i)
hdr_r <= hdr_n;
// synopsys translate_off
always_ff @(negedge clk_i)
if (state_n != state_r)
if (debug_level_lp > 1) $display("## bsg_tag_master STATE CHANGE # %s --> %s #",state_r.name(),state_n.name());
// synopsys translate_on
always_comb
begin
state_n = state_r;
hdr_ptr_n = hdr_ptr_r;
hdr_n = hdr_r;
// outgoing
v_n = 1'b0;
bsg_tag_n.op = 1'b0;
bsg_tag_n.param = 1'b0;
case (state_r)
// first 1 after zero indicates beginning of packet
eStart:
begin
if (data_i_r)
state_n = eHeader;
hdr_ptr_n = 0;
hdr_n = 0;
end
eHeader:
begin
// synopsys translate_off
if (debug_level_lp > 1)
$display("## bsg_tag_master RECEIVING HEADER (%m) (%d) = %b",hdr_ptr_r,data_i_r);
// synopsys translate_on
hdr_n = { data_i_r, hdr_r[1+:($bits(bsg_tag_header_s)-1)] };
hdr_ptr_n = hdr_ptr_r + 1'b1;
// if we are at the next to last value
if (hdr_ptr_r == lg_max_packet_len_lp'($bits(bsg_tag_header_s)-1))
begin
if (hdr_n.len == 0)
begin
state_n = eStart;
// synopsys translate_off
$display("## bsg_tag_master NULL PACKET, len=0 (%m)");
// synopsys translate_on
end
else
begin
// synopsys translate_off
if (debug_level_lp > 1)
$display("## bsg_tag_master PACKET HEADER RECEIVED (length=%b,data_not_reset=%b,nodeID=%b) (%m) "
,hdr_n.len,hdr_n.data_not_reset,hdr_n.nodeID);
// synopsys translate_on
// if we have data to transfer go to transfer state
state_n = eTransfer;
end
end
end // case: eHeader
eTransfer:
begin
// transmit data
// if hdr_r.reset = 1, then we send <0,data> for hdr_r.len cycles
// otherwise we send <1,data> for hdr_r.len cycles
// typically for reset, we will send 1's.
v_n = 1'b1;
bsg_tag_n.op = hdr_r.data_not_reset;
bsg_tag_n.param = data_i_r;
// synopsys translate_off
if (debug_level_lp > 2)
$display("## bsg_tag_master PACKET TRANSFER op,param=<%b,%b> (%m)", bsg_tag_n.op, bsg_tag_n.param);
// synopsys translate_on
// finishing words
if (hdr_r.len== lg_width_p ' (1))
begin
state_n = eStart;
// synopsys translate_off
if (debug_level_lp > 1) $display("## bsg_tag_master PACKET END (%m)");
// synopsys translate_on
end
hdr_n.len = hdr_r.len - 1;
end
eStuck:
state_n = eStuck;
default:
begin
state_n = eStuck;
// synopsys translate_off
$display("## bsg_tag_master transitioning to error state; be sure to run gate-level netlist to avoid sim/synth mismatch (%m)");
// synopsys translate_on
end
endcase // case (state_r)
end // always_comb
genvar i;
// calculate local nodeID
// must have lg_els_lp bits to prevent overflow
// (underflow is okay in this case)
wire [lg_els_lp-1:0] local_node_id = hdr_r.nodeID - node_id_offset_i;
// demultiplex the stream to the target node
// use only lg_local_els_lp bits to simplify decoder logic
wire [local_els_p-1:0] clients_decode = (v_n << local_node_id[lg_local_els_lp-1:0]);
// determine if incoming packet is within the nodeID range
wire node_id_above_offset = (hdr_r.nodeID >= node_id_offset_i);
wire local_node_id_below_limit = (local_node_id < local_els_p);
wire node_id_match = (node_id_above_offset && local_node_id_below_limit);
// output to bsg_tag_clients directly without flops
for (i = 0; i < local_els_p; i=i+1)
begin: rof
assign clients_o[i].clk = clk_i;
assign clients_o[i].op = node_id_match & clients_decode[i] & bsg_tag_n.op;
assign clients_o[i].param = node_id_match & clients_decode[i] & bsg_tag_n.param;
assign clients_o[i].en = 1'b1;
end
endmodule // bsg_tag_master
`BSG_ABSTRACT_MODULE(bsg_tag_master_decentralized)
// verilator lint_on BLKANDNBLK
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_2_V
`define SKY130_FD_SC_HDLL__EINVP_2_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_2 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_2 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_2_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file virtex6_dmem.v when simulating
// the core, virtex6_dmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module virtex6_dmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex6"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("virtex6"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex6_dmem is "black_box"
endmodule
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=10000 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=5000 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK1" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=frame_rate" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="ON" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="ROM_frame_rate_frame_rate0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module frame_rate_altpll
(
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 10000,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 5000,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 1,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk1",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "on",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = wire_pll1_locked;
endmodule //frame_rate_altpll
//VALID FILE
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FIFO 4 entries deep ////
//// ////
//// Authors: Rudolf Usselmann, Richard Herveille ////
//// ////
//// ////
//// ////
//// Download from: http://www.opencores.org/projects/sasc ////
//// http://www.opencores.org/projects/simple_spi ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
//// www.asics.ws ////
//// , ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $
//
// $Date: 2002-12-22 16:07:14 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
// 4 entry deep fast fifo
module fifo4(clk, rst, clr, din, we, dout, re, full, empty);
parameter dw = 8;
input clk, rst;
input clr;
input [dw:1] din;
input we;
output [dw:1] dout;
input re;
output full, empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [dw:1] mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] wp_p2;
wire [1:0] rp_p1;
wire full, empty;
reg gb;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) wp <= #1 2'h0;
else
if(clr) wp <= #1 2'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;
always @(posedge clk or negedge rst)
if(!rst) rp <= #1 2'h0;
else
if(clr) rp <= #1 2'h0;
else
if(re) rp <= #1 rp_p1;
assign rp_p1 = rp + 2'h1;
// Fifo Output
assign dout = mem[ rp ];
// Fifo Input
always @(posedge clk)
if(we) mem[ wp ] <= #1 din;
// Status
assign empty = (wp == rp) & !gb;
assign full = (wp == rp) & gb;
// Guard Bit ...
always @(posedge clk)
if(!rst) gb <= #1 1'b0;
else
if(clr) gb <= #1 1'b0;
else
if((wp_p1 == rp) & we) gb <= #1 1'b1;
else
if(re) gb <= #1 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream fin( input.txt ); ofstream fout( output.txt ); int gcd(int a, int b) { while (a && b) a > b ? a %= b : b %= a; return a + b; } int val(char c) { if (c >= 0 && c <= 9 ) return (int)c - 0 ; else return (int)c - A + 10; } long long pows(int a, int b) { long long res = 1; for (int i = 0; i < b; ++i) { res *= a; } return res; } long long logx(long long base, long long num) { int cnt = 0; while (num != 1) { num /= base; ++cnt; } return cnt; } long long divisibles(long long a, long long b, long long m) { if (a % m == 0) return (b / m) - (a / m) + 1; else return (b / m) - (a / m); } vector<int> root(100001, 0); vector<int> size(100001, 0); int find(int x) { while (x != root[x]) x = root[x]; return x; } bool same(int a, int b) { return find(a) == find(b); } void unite(int a, int b) { a = find(a); b = find(b); if (size[a] < size[b]) swap(a, b); size[a] += size[b]; root[b] = a; } vector<int> vis(100001, 0); vector<int> adj[100001]; int main() { std::ios::sync_with_stdio(false); set<double> s; double n, x, y; cin >> n >> x >> y; for (int i = 0; i < n; ++i) { double a, b; cin >> a >> b; b = y - b; a = x - a; if (!a) { s.insert(INT_MAX); continue; } s.insert(b / a); } cout << s.size() << n ; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15.03.2016 14:21:56
// Design Name:
// Module Name: I_NORM_FLOAT_TO_FIXED
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module I_NORM_FLOAT_TO_FIXED(
input wire CLK, //system clock
input wire [31:0] F, //VALOR BINARIO EN COMA FLOTANTE
input wire RST_FF, //system reset
input wire Begin_FSM_FF, //INICIA LA CONVERSION
output wire ACK_FF,//INDICA QUE LA CONVERSION FUE REALIZADA
output wire [31:0] RESULT // RESULTADO FINAL
);
wire Exp_out;
wire [7:0] Exp;
wire EN_REG1;
wire LOAD;
wire MS_1;
wire EN_MS_1;
wire MS1_REG;
wire EN_REG2;
wire RST;
FF_D #(.P(1)) REG_MS1_I (
.CLK(CLK),
.RST(RST),
.EN(EN_MS_1),
.D(MS_1),
.Q(MS1_REG)
);
FSM_Convert_Float_To_Fixed FSM_CONVERT_FLOAT_FIXED(
.CLK(CLK), //system clock
.RST_FF(RST_FF), //system reset
.Exp_out(Exp_out),
.Begin_FSM_FF(Begin_FSM_FF), //inicia la maquina de estados
.Exp(Exp),
.EN_REG1(EN_REG1),
.LOAD(LOAD),
.MS_1(MS_1),
.ACK_FF(ACK_FF),
.EN_MS_1(EN_MS_1),
.EN_REG2(EN_REG2),
.RST(RST)
);
Convert_Float_To_Fixed CONVERT_FLOAT_FIXED(
.CLK(CLK),
.FLOAT(F),
.EN_REG1(EN_REG1),
.LOAD(LOAD),
.MS_1(MS1_REG),
.Exp_out(Exp_out),
.FIXED(RESULT),
.Exp(Exp),
.EN_REG2(EN_REG2),
.RST(RST)
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by John Stevenson.
package pkg;
typedef logic [31:0] unique_id_t;
typedef struct packed {
unique_id_t foo;
} inner_thing_t;
typedef struct packed {
inner_thing_t bar;
inner_thing_t baz;
} outer_thing_t;
endpackage
import pkg::*;
interface the_intf
#(parameter M=5);
outer_thing_t [M-1:0] things;
logic valid;
modport i (
output things,
output valid);
modport t (
input things,
input valid);
endinterface
module ThingMuxOH
#(
parameter NTHINGS = 1,
parameter M = 5 )
(
input logic [NTHINGS-1:0] select_oh,
the_intf.t things_in [NTHINGS-1:0],
the_intf.i thing_out
);
endmodule
module Thinker
#(
parameter M = 5,
parameter N = 2)
(
input logic clk,
input logic reset,
input unique_id_t uids[0:N-1],
the_intf.t thing_inp,
the_intf.i thing_out
);
the_intf #(.M(M)) curr_things [N-1:0] ();
the_intf #(.M(M)) prev_things [N-1:0] ();
the_intf #(.M(M)) curr_thing ();
the_intf #(.M(M)) prev_thing ();
logic [N-1:0] select_oh;
// 1st mux:
ThingMuxOH #(
.NTHINGS ( N ),
.M ( M ))
curr_thing_mux(
.select_oh( select_oh ),
.things_in( curr_things ),
.thing_out( curr_thing ));
// 2nd mux, comment this out and no problem:
ThingMuxOH #(
.NTHINGS ( N ),
.M ( M ))
prev_thing_mux(
.select_oh( select_oh ),
.things_in( prev_things ),
.thing_out( prev_thing ));
endmodule
module t
(
input logic clk,
input logic reset
);
localparam M = 5;
localparam N = 2;
unique_id_t uids[0:N-1];
the_intf #(.M(M)) thing_inp();
the_intf #(.M(M)) thing_out();
Thinker #(
.M ( M ),
.N ( N ))
thinker(
.clk ( clk ),
.reset ( reset ),
.uids ( uids ),
.thing_inp( thing_inp ),
.thing_out( thing_out ));
// Previously there was a problem in V3Inst if non-default parameters was used
localparam K = 2;
the_intf #(.M(K)) thing_inp2();
the_intf #(.M(K)) thing_out2();
Thinker #(
.M ( K ),
.N ( N ))
thinker2(
.clk ( clk ),
.reset ( reset ),
.uids ( uids ),
.thing_inp( thing_inp2 ),
.thing_out( thing_out2 ));
endmodule
|
module latch_ex_mem(
input clock ,
input reset ,
input [ 5:0] stall ,
input [31:0] ex_instruction ,
output reg [31:0] mem_instruction ,
input [ 7:0] ex_operator ,
output reg [ 7:0] mem_operator ,
input [31:0] ex_operand_a ,
output reg [31:0] mem_operand_a ,
input [31:0] ex_operand_b ,
output reg [31:0] mem_operand_b ,
input ex_register_write_enable ,
output reg mem_register_write_enable ,
input [ 4:0] ex_register_write_address ,
output reg [ 4:0] mem_register_write_address ,
input [31:0] ex_register_write_data ,
output reg [31:0] mem_register_write_data ,
input ex_register_hi_write_enable ,
output reg mem_register_hi_write_enable,
input [31:0] ex_register_hi_write_data ,
output reg [31:0] mem_register_hi_write_data ,
input ex_register_lo_write_enable ,
output reg mem_register_lo_write_enable,
input [31:0] ex_register_lo_write_data ,
output reg [31:0] mem_register_lo_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[3] == `STALL_ENABLE && stall[4] == `STALL_DISABLE)) begin
mem_instruction <= 32'b0 ;
mem_operator <= `OPERATOR_NOP ;
mem_operand_a <= 32'b0 ;
mem_operand_b <= 32'b0 ;
mem_register_write_enable <= `WRITE_DISABLE;
mem_register_write_address <= 5'b0 ;
mem_register_write_data <= 32'b0 ;
mem_register_hi_write_enable <= `WRITE_DISABLE;
mem_register_hi_write_data <= 32'b0 ;
mem_register_lo_write_enable <= `WRITE_DISABLE;
mem_register_lo_write_data <= 32'b0 ;
end
else if (stall[3] == `STALL_DISABLE) begin
mem_instruction <= ex_instruction ;
mem_operator <= ex_operator ;
mem_operand_a <= ex_operand_a ;
mem_operand_b <= ex_operand_b ;
mem_register_write_enable <= ex_register_write_enable ;
mem_register_write_address <= ex_register_write_address ;
mem_register_write_data <= ex_register_write_data ;
mem_register_hi_write_enable <= ex_register_hi_write_enable;
mem_register_hi_write_data <= ex_register_hi_write_data ;
mem_register_lo_write_enable <= ex_register_lo_write_enable;
mem_register_lo_write_data <= ex_register_lo_write_data ;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int MAXN = 100100; inline void add(int &a, int b) { a += b; if (a >= MOD) { a -= MOD; } } inline int mul(int a, int b) { return (a * 1LL * b) % MOD; } inline int fastPow(int a, int b) { int r = 1; while (b) { if (b & 1) { r = mul(r, a); } a = mul(a, a); b >>= 1; } return r; } inline int inverse(int a) { return fastPow(a, MOD - 2); } int f[MAXN]; int invf[MAXN]; int ten[MAXN]; inline int c(int n, int k) { if (k < 0) { return 0; } if (n < k) { return 0; } return mul(mul(f[n], invf[k]), invf[n - k]); } int main() { clock_t start_time = clock(); f[0] = invf[0] = 1; ten[0] = 1; for (int i = 1; i < MAXN; i++) { ten[i] = mul(ten[i - 1], 10); f[i] = mul(f[i - 1], i); invf[i] = inverse(f[i]); } int n, k; while (scanf( %d%d , &n, &k) == 2) { char ss[n + 1]; scanf( %s , ss); vector<int> s(n, 0); for (int i = 0; i < n; i++) { s[i] = ss[i] - 0 ; if (i > 0) { add(s[i], s[i - 1]); } } int ans = 0; for (int d = 0; d <= n - 2; d++) { int val = mul(ten[d], c(n - d - 2, k - 1)); val = mul(val, s[n - d - 2]); add(ans, val); } for (int i = 0; i < n; i++) { int val = mul(ten[n - i - 1], ss[i] - 0 ); val = mul(val, c(i, k)); add(ans, val); } printf( %d n , ans); } (void)42; ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6 + 100; char ch[maxn]; namespace Suffix_Array { int cntA[maxn], cntB[maxn], tsa[maxn], A[maxn], B[maxn]; int sa[maxn], rkrk[maxn], height[maxn]; void GetSa(char *ch, int n) { for (int i = 0; i < maxn; i++) cntA[i] = 0; for (int i = 1; i <= n; i++) cntA[ch[i]]++; for (int i = 1; i <= maxn; i++) cntA[i] += cntA[i - 1]; for (int i = n; i; i--) sa[cntA[ch[i]]--] = i; rkrk[sa[1]] = 1; for (int i = 2; i <= n; i++) { rkrk[sa[i]] = rkrk[sa[i - 1]]; if (ch[sa[i]] != ch[sa[i - 1]]) rkrk[sa[i]]++; } for (int l = 1; rkrk[sa[n]] < n; l <<= 1) { for (int i = 0; i < maxn; i++) cntA[i] = 0; for (int i = 0; i < maxn; i++) cntB[i] = 0; for (int i = 1; i <= n; i++) { cntA[A[i] = rkrk[i]]++; cntB[B[i] = (i + l <= n) ? rkrk[i + l] : 0]++; } for (int i = 1; i < maxn; i++) cntB[i] += cntB[i - 1]; for (int i = n; i; i--) tsa[cntB[B[i]]--] = i; for (int i = 1; i < maxn; i++) cntA[i] += cntA[i - 1]; for (int i = n; i; i--) sa[cntA[A[tsa[i]]]--] = tsa[i]; rkrk[sa[1]] = 1; for (int i = 2; i <= n; i++) { rkrk[sa[i]] = rkrk[sa[i - 1]]; if (A[sa[i]] != A[sa[i - 1]] || B[sa[i]] != B[sa[i - 1]]) rkrk[sa[i]]++; } } } }; // namespace Suffix_Array int sum[maxn]; struct Segment_Tree { int Min[maxn * 8]; void up(int x) { Min[x] = min(Min[x << 1], Min[x << 1 | 1]); } void build(int x, int l, int r) { if (l == r) { Min[x] = sum[l]; return; } int mid = l + r >> 1; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); up(x); } int query(int x, int l, int r, int L, int R) { if (l > R || L > r) return 0x3f3f3f3f; if (L <= l && r <= R) return Min[x]; int mid = l + r >> 1; return min(query(x << 1, l, mid, L, R), query(x << 1 | 1, mid + 1, r, L, R)); } } seg; int SUM; int n, N; bool check(int x) { int Min = seg.query(1, 1, N, x, x + n - 1); int begin = sum[x - 1]; if (SUM < 0) { begin += SUM; } if (Min >= begin) return 1; else return 0; } int main() { scanf( %s , ch + 1); n = strlen(ch + 1); for (int i = n + 1; i <= 2 * n; i++) { if (ch[i - n] == ( ) ch[i - n] = 0 ; else ch[i - n] = 1 ; ch[i] = ch[i - n]; } N = n << 1; Suffix_Array::GetSa(ch, N); for (int i = 1; i <= N; i++) { sum[i] = sum[i - 1]; if (ch[i] == 0 ) sum[i]++; else sum[i]--; } SUM = sum[n]; seg.build(1, 1, N); for (int i = 1; i <= N; i++) { int x = Suffix_Array::sa[i]; if (x > n) continue; if (check(x)) { if (SUM < 0) { for (int j = 0; j > SUM; j--) { printf( ( ); } } for (int j = x; j < x + n; j++) { if (ch[j] == 0 ) printf( ( ); else printf( ) ); } if (SUM > 0) { for (int j = 0; j < SUM; j++) { printf( ) ); } } puts( ); return 0; } } assert(0); return 0; }
|
#include <bits/stdc++.h> using namespace std; int r = 2, g = 5, b = 8, n, k; int h, j, p; int main() { cin >> n >> k; h = r * n; j = g * n; p = b * n; h = (h + k - 1) / k; j = (j + k - 1) / k; p = (p + k - 1) / k; cout << p + j + h; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: David Ariando
//
// Create Date: 22:22:00 01/31/2018
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: TF_CLS_PWM_Interval_Timer.v
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.1
// Description: CLS PWM Interval Timer Testbench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_CLS_PWM_Interval_Timer();
wire PWM_TICK;
reg CLOCK_50;
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
CLS_PWM_Interval_Timer
#(
.CLK_RATE_HZ (CLK_RATE_HZ), // Hz
.DUTY_RATE_HZ (1000) // Hz
)
uut
(
// Output Signals
.PWM_TICK (PWM_TICK),
// System Signals
.CLK (CLOCK_50)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void sdvig(char *c, int n) { int i; char s = c[0]; for (i = 0; i < n - 1; i++) { c[i] = c[i + 1]; } c[n - 1] = s; } int main() { int n; scanf( %d n , &n); char c[1010], cc[1010]; cin >> cc; int i, g, f, l = n - 1; int mmin = 1000000000, kol; bool fl; for (f = 0; f < n; f++) { kol = 0; for (i = 0; i < n; i++) { c[i] = cc[i]; } while (true) { i = 0; g = l; while (c[i] == H ) i++; while (c[g] == T ) g--; if (i < g) { swap(c[i], c[g]); kol++; } else { break; } } if (kol < mmin) mmin = kol; sdvig(cc, n); } cout << mmin; return 0; }
|
//This module exists to clean the main CPU module a bit and to allow for there to be
//more hard-wired combinational logic in the CPU. Future revisions will include even further
//hard-wiring so as to hopefully increase clockspeed potential.
module pipeBlockedU(
DAT1,
DAT2,
DAT3,
DAT4,
DAT5,
blocked
);
input [15:0] DAT1;
input [15:0] DAT2;
input [15:0] DAT3;
input [15:0] DAT4;
input [15:0] DAT5;
output blocked;
wire [6:0] o1;
wire [6:0] o2;
wire [6:0] o3;
wire [6:0] o4;
wire [6:0] o5;
assign o1=DAT1[15:9];
assign o2=DAT2[15:9];
assign o3=DAT3[15:9];
assign o4=DAT4[15:9];
assign o5=DAT5[15:9];
wire blocked1, blocked2, blocked3, blocked4, blocked5;
//Almost all operations beyond Store Stack Register and Load Stack Register should block:
//assign blocked1=o1>41&&o1~=50&&o1<64;
//assign blocked2=o2>41&&o2~=50&&o2<64;
//assign blocked3=o3>41&&o3~=50&&o3<64;
//Note, the additional ops to be excluded from blocking are pretty much all jumps.
//They really don't do anything harmful to the pipeline.
//assign blocked4=o4>41&&o4~=50&&o4<64&&o4~=51&&o4~=52&&o4~=53&&o4~=54;
//assign blocked5=o5>41&&o5~=50&&o5<64&&o4~=51&&o4~=52&&o4~=53&&o4~=54;
//This is a far finer grained, more efficient version.
assign blocked1=(o1>41 && o1<46) || (o1>50 && o1<55) || o1==60 || o1==61;// || o1==41;//o1==42||o1==43||o1==44||o1==45||o1==
assign blocked2=(o2>41 && o2<46) || (o2>50 && o2<55) || o2==60 || o2==61 || o2==41; //^LSR should make a 1 op bubble so that immediate pushes don't cause problems.
assign blocked3=(o3>41 && o3<46) || (o3>50 && o3<55) || o3==60 || o3==61 || o3==41;
assign blocked4=(o4>41 && o4<46) || (o4>50 && o4<55) || o4==60 || o4==61;// || o1==41;
assign blocked5=(o5==44 || o5==45);// || (o1>=51 && o1<=54) || o1==60 || o1=61;
assign blocked=blocked1||blocked2||blocked3||blocked4||blocked5;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_FUNCTIONAL_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_slvram_v7.v
// Version : v1.0
// Description: RAM instantiation.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_slvram_v7 #(
parameter C_FAMILY = "virtex7" ,
parameter C_DATAWIDTH = 64 ,
parameter C_SIZE = 1024 ,
parameter C_ADDR_WIDTH= 10 ,
parameter C_INITRAM_F = "NONE"
) (
input clk_a ,
input [C_DATAWIDTH/8-1:0] we_a ,
input [C_ADDR_WIDTH-1:0] addr_a ,
input [C_DATAWIDTH-1:0] wr_data_a,
output [C_DATAWIDTH-1:0] rd_data_a,
input clk_b ,
input [C_DATAWIDTH/8-1:0] we_b ,
input [C_ADDR_WIDTH-1:0] addr_b ,
input [C_DATAWIDTH-1:0] wr_data_b,
output [C_DATAWIDTH-1:0] rd_data_b
);
//generate
//if(C_DATAWIDTH == 32) begin: ram32b
axi_traffic_gen_v2_0_inferram #(
.C_FAMILY (C_FAMILY ),
.C_RAMINIT_F(C_INITRAM_F ),
.SIZE (C_SIZE ),
.ADDR_WIDTH (C_ADDR_WIDTH ),
.NB_COL (C_DATAWIDTH/8),
.COL_WIDTH (8 ),
.INFER_TYPE (1 )
) ram0 (
.clk(clk_a),
.wea(we_a),
.web(we_b),
.addra(addr_a),
.addrb(addr_b),
.dia(wr_data_a),
.dib(wr_data_b),
.doa(rd_data_a),
.dob(rd_data_b)
);
//end // block: ram32b
//endgenerate
//generate
//if(C_DATAWIDTH == 64) begin: ram64b
//axi_traffic_gen_v2_0_inferram #(
// .C_FAMILY (C_FAMILY ),
// .C_RAMINIT_F(C_INITRAM_F),
// .NB_COL (8 ),
// .COL_WIDTH (8 ),
// .INFER_TYPE (1 )
// )
// ram0 (
// .clk(clk_a),
// .wea(we_a),
// .web(we_b),
// .addra(addr_a),
// .addrb(addr_b),
// .dia(wr_data_a),
// .dib(wr_data_b),
// .doa(rd_data_a),
// .dob(rd_data_b)
// );
//
//end // block: ram64b
//endgenerate
/*
generate
if(C_DATAWIDTH == 32) begin: ram32b
RAMB36 #(
`RAMB_INIT0
.INIT_FILE (C_INITRAM_F ),
.SIM_COLLISION_CHECK("NONE"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.READ_WIDTH_A (36 ),
.READ_WIDTH_B (36 ),
.WRITE_WIDTH_A(36 ),
.WRITE_WIDTH_B(36 ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.SRVAL_A ('h0 ),
.SRVAL_B ('h0 )
)
ramb36i (
.CLKA (clk_a ),
.ADDRA ({1'b0,addr_a,5'h0}),
.ENA (1'b1 ),
.REGCEA(1'b0 ),
.WEA (we_a[3:0] ),
.SSRA (1'b0 ),
.DOA (rd_data_a[31:0] ),
.DIA (wr_data_a[31:0] ),
.DIPA (4'b0 ),
.CLKB (clk_b ),
.ADDRB ({1'b0,addr_b,5'h0}),
.ENB (1'b1 ),
.REGCEB(1'b0 ),
.WEB (we_b[3:0] ),
.SSRB (1'b0 ),
.DOB (rd_data_b[31:0] ),
.DIB (wr_data_b[31:0] ),
.DIPB (4'b0 )
);
end // block: ram32b
endgenerate
generate
if(C_DATAWIDTH == 64) begin: ram64b
RAMB36 #(
`RAMB_INIT0
.INIT_FILE (C_INITRAM_F ),
.SIM_COLLISION_CHECK("NONE"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.READ_WIDTH_A (36 ),
.READ_WIDTH_B (36 ),
.WRITE_WIDTH_A(36 ),
.WRITE_WIDTH_B(36 ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.SRVAL_A ('h0 ),
.SRVAL_B ('h0 )
)
ramb36i (
.CLKA (clk_a ),
.ADDRA ({1'b0,addr_a,5'h0}),
.ENA (1'b1 ),
.REGCEA(1'b0 ),
.WEA (we_a[3:0] ),
.SSRA (1'b0 ),
.DOA (rd_data_a[31:0] ),
.DIA (wr_data_a[31:0] ),
.DIPA (4'b0 ),
.CLKB (clk_b ),
.ADDRB ({1'b0,addr_b,5'h0}),
.ENB (1'b1 ),
.REGCEB(1'b0 ),
.WEB (we_b[3:0] ),
.SSRB (1'b0 ),
.DOB (rd_data_b[31:0] ),
.DIB (wr_data_b[31:0] ),
.DIPB (4'b0 )
);
RAMB36 #(
`RAMB_INIT0
.INIT_FILE (C_INITRAM_F ),
.SIM_COLLISION_CHECK("NONE"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.READ_WIDTH_A (36 ),
.READ_WIDTH_B (36 ),
.WRITE_WIDTH_A(36 ),
.WRITE_WIDTH_B(36 ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.SRVAL_A ('h0 ),
.SRVAL_B ('h0 )
)
ramb36ii (
.CLKA (clk_a ),
.ADDRA ({1'b0, addr_a,5'h0}),
.ENA (1'b1 ),
.REGCEA(1'b0 ),
.WEA (we_a[7:4] ),
.SSRA (1'b0 ),
.DOA (rd_data_a[63:32] ),
.DIA (wr_data_a[63:32] ),
.DIPA (4'b0 ),
.CLKB (clk_b ),
.ADDRB ({1'b0,addr_b,5'h0} ),
.ENB (1'b1 ),
.REGCEB(1'b0 ),
.WEB (we_b[7:4] ),
.SSRB (1'b0 ),
.DOB (rd_data_b[63:32] ),
.DIB (wr_data_b[63:32] ),
.DIPB (4'b0 )
);
end // block: ram64b
endgenerate
*/
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, n, i, j, money; cin >> a >> b >> c; cin >> n; int m[n]; money = 0; for (i = 0; i < n; i++) { cin >> m[i]; if (m[i] > b && m[i] < c) money = money + 1; } if (a > b && a < c) cout << money; else cout << 0; return 0; }
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module optest(clk, mode, u1, s1, u2, s2, y);
input clk;
input [6:0] mode;
input [3:0] u1, u2;
input signed [3:0] s1, s2;
output reg [7:0] y;
always @(posedge clk) begin
y <= 8'h42;
case (mode)
0: y <= u1 << u2;
1: y <= u1 << s2;
2: y <= s1 << u2;
3: y <= s1 << s2;
4: y <= u1 >> u2;
5: y <= u1 >> s2;
6: y <= s1 >> u2;
7: y <= s1 >> s2;
8: y <= u1 <<< u2;
9: y <= u1 <<< s2;
10: y <= s1 <<< u2;
11: y <= s1 <<< s2;
12: y <= u1 >>> u2;
13: y <= u1 >>> s2;
14: y <= s1 >>> u2;
15: y <= s1 >>> s2;
16: y <= u1 < u2;
17: y <= u1 < s2;
18: y <= s1 < u2;
19: y <= s1 < s2;
20: y <= u1 <= u2;
21: y <= u1 <= s2;
22: y <= s1 <= u2;
23: y <= s1 <= s2;
24: y <= u1 == u2;
25: y <= u1 == s2;
26: y <= s1 == u2;
27: y <= s1 == s2;
28: y <= u1 != u2;
29: y <= u1 != s2;
30: y <= s1 != u2;
31: y <= s1 != s2;
32: y <= u1 >= u2;
33: y <= u1 >= s2;
34: y <= s1 >= u2;
35: y <= s1 >= s2;
36: y <= u1 > u2;
37: y <= u1 > s2;
38: y <= s1 > u2;
39: y <= s1 > s2;
40: y <= u1 + u2;
41: y <= u1 + s2;
42: y <= s1 + u2;
43: y <= s1 + s2;
44: y <= u1 - u2;
45: y <= u1 - s2;
46: y <= s1 - u2;
47: y <= s1 - s2;
48: y <= u1 * u2;
49: y <= u1 * s2;
50: y <= s1 * u2;
51: y <= s1 * s2;
52: y <= u1 / u2;
53: y <= u1 / s2;
54: y <= s1 / u2;
55: y <= s1 / s2;
56: y <= u1 % u2;
57: y <= u1 % s2;
58: y <= s1 % u2;
59: y <= s1 % s2;
60: y <= 4'd2 ** u1;
61: y <= 4'd2 ** s1;
62: y <= 4'sd2 ** u1;
63: y <= 4'sd2 ** s1;
64: y <= +u1;
65: y <= -u1;
66: y <= ~u1;
67: y <= !u1;
68: y <= +s1;
69: y <= -s1;
70: y <= ~s1;
71: y <= !s1;
72: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 };
73: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 };
74: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] };
75: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] };
76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };
77: y <= {4{u1[1:0]}};
78: y <= {u1, u2} ^ {s1, s2};
79: y <= {u1, u2} & {s1, s2};
80: y <= u1[0] ? u1 : u2;
81: y <= u1[0] ? u1 : s2;
82: y <= u1[0] ? s1 : u2;
83: y <= u1[0] ? s1 : s2;
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; struct Data { int Value, Number; }; bool operator<(Data A, Data B) { return A.Value < B.Value; } int Get() { char c; while (c = getchar(), c < 0 || c > 9 ) ; int X = 0; while (c >= 0 && c <= 9 ) { X = X * 10 + c - 48; c = getchar(); } return X; } void Output(int X) { int Len = 0, Data[10]; while (X) { Data[Len++] = X % 10; X /= 10; } if (!Len) Data[Len++] = 0; while (Len--) putchar(Data[Len] + 48); } int main() { int N = Get(); static Data A[100000]; for (int i = 0; i < N; i++) { A[i].Value = Get(); A[i].Number = i; } sort(A, A + N); static int X[100000], Y[100000]; memset(X, 0, sizeof(X)); memset(Y, 0, sizeof(Y)); int K = (N - 1) / 3 + 1, T = N - K * 2; for (int i = 0; i < K; i++) { X[A[i].Number] = A[i].Value; Y[A[i + K].Number] = A[i + K].Value; } for (int i = K * 2; i < N; i++) { X[A[i].Number] = A[i].Value - N + i; Y[A[i].Number] = N - i; } printf( YES n ); for (int i = 0; i < N; i++) { Output(X[i]); putchar((i + 1 == N) ? n : ); } for (int i = 0; i < N; i++) { Output(Y[i]); putchar((i + 1 == N) ? n : ); } return 0; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_ecc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_ecc
// Description: This block performs the ecc check and correction as well as
// doing the w2 write port arbitration and the w2 ecc generation.
*/
module sparc_exu_ecc (/*AUTOARG*/
// Outputs
so, ecc_ecl_rs1_ce, ecc_ecl_rs1_ue, ecc_ecl_rs2_ce,
ecc_ecl_rs2_ue, ecc_ecl_rs3_ce, ecc_ecl_rs3_ue,
ecc_byp_ecc_result_m, exu_ifu_err_synd_m,
// Inputs
rclk, se, si, byp_ecc_rcc_data_e, ecl_ecc_rs1_use_rf_e,
byp_ecc_rs1_synd_d, byp_alu_rs2_data_e, ecl_ecc_rs2_use_rf_e,
byp_ecc_rs2_synd_d, byp_ecc_rs3_data_e, ecl_ecc_rs3_use_rf_e,
byp_ecc_rs3_synd_d, ecl_ecc_sel_rs1_m_l, ecl_ecc_sel_rs2_m_l,
ecl_ecc_sel_rs3_m_l, ecl_ecc_log_rs1_m, ecl_ecc_log_rs2_m,
ecl_ecc_log_rs3_m
) ;
input rclk;
input se;
input si;
input [63:0] byp_ecc_rcc_data_e;
input ecl_ecc_rs1_use_rf_e;
input [7:0] byp_ecc_rs1_synd_d;
input [63:0] byp_alu_rs2_data_e;
input ecl_ecc_rs2_use_rf_e;
input [7:0] byp_ecc_rs2_synd_d;
input [63:0] byp_ecc_rs3_data_e;
input ecl_ecc_rs3_use_rf_e;
input [7:0] byp_ecc_rs3_synd_d;
input ecl_ecc_sel_rs1_m_l;
input ecl_ecc_sel_rs2_m_l;
input ecl_ecc_sel_rs3_m_l;
input ecl_ecc_log_rs1_m;
input ecl_ecc_log_rs2_m;
input ecl_ecc_log_rs3_m;
output so;
output ecc_ecl_rs1_ce;
output ecc_ecl_rs1_ue;
output ecc_ecl_rs2_ce;
output ecc_ecl_rs2_ue;
output ecc_ecl_rs3_ce;
output ecc_ecl_rs3_ue;
output [63:0] ecc_byp_ecc_result_m;
output [6:0] exu_ifu_err_synd_m;
wire clk;
wire sel_rs1_m;
wire sel_rs2_m;
wire sel_rs3_m;
wire [7:0] rs1_ecc_e;
wire [6:0] rs1_err_e; // syndrome generated by checker
wire [6:0] rs1_err_m; // syndrome generated by checker
wire [7:0] rs2_ecc_e;
wire [6:0] rs2_err_e; // syndrome generated by checker
wire [6:0] rs2_err_m; // syndrome generated by checker
wire [7:0] rs3_ecc_e;
wire [6:0] rs3_err_e; // syndrome generated by checker
wire [6:0] rs3_err_m; // syndrome generated by checker
wire [6:0] err_m;
wire [63:0] ecc_datain_m;
wire [63:0] byp_ecc_rcc_data_m;
wire [63:0] byp_alu_rs2_data_m;
wire [63:0] exu_lsu_rs3_data_m;
wire [63:0] error_data_m;
assign clk = rclk;
// Pass along ecc parity bits from RF
dff_s #(8) rs1_ecc_d2e(.din(byp_ecc_rs1_synd_d[7:0]), .clk(clk), .q(rs1_ecc_e[7:0]),
.se(se), .si(), .so());
dff_s #(8) rs2_ecc_d2e(.din(byp_ecc_rs2_synd_d[7:0]), .clk(clk), .q(rs2_ecc_e[7:0]),
.se(se), .si(), .so());
dff_s #(8) rs3_ecc_d2e(.din(byp_ecc_rs3_synd_d[7:0]), .clk(clk), .q(rs3_ecc_e[7:0]),
.se(se), .si(), .so());
// Check the ecc for all 4 outputs from RF
zzecc_exu_chkecc2 chk_rs1(.d(byp_ecc_rcc_data_e[63:0]),
.vld(ecl_ecc_rs1_use_rf_e),
.p(rs1_ecc_e[7:0]),
.q(rs1_err_e[6:0]),
.ce(ecc_ecl_rs1_ce), .ue(ecc_ecl_rs1_ue), .ne());
zzecc_exu_chkecc2 chk_rs2(.d(byp_alu_rs2_data_e[63:0]),
.vld(ecl_ecc_rs2_use_rf_e),
.p(rs2_ecc_e[7:0]),
.q(rs2_err_e[6:0]),
.ce(ecc_ecl_rs2_ce), .ue(ecc_ecl_rs2_ue), .ne());
zzecc_exu_chkecc2 chk_rs3(.d(byp_ecc_rs3_data_e[63:0]),
.vld(ecl_ecc_rs3_use_rf_e),
.p(rs3_ecc_e[7:0]),
.q(rs3_err_e[6:0]),
.ce(ecc_ecl_rs3_ce), .ue(ecc_ecl_rs3_ue), .ne());
// Put results from checkers into flops
dff_s #(7) rs1_err_e2m(.din(rs1_err_e[6:0]), .clk(clk), .q(rs1_err_m[6:0]),
.se(se), .si(), .so());
dff_s #(7) rs2_err_e2m(.din(rs2_err_e[6:0]), .clk(clk), .q(rs2_err_m[6:0]),
.se(se), .si(), .so());
dff_s #(7) rs3o_err_e2m(.din(rs3_err_e[6:0]), .clk(clk), .q(rs3_err_m[6:0]),
.se(se), .si(), .so());
// Pass along RF data to M stage
dff_s #(64) rs1_data_e2m(.din(byp_ecc_rcc_data_e[63:0]), .clk(clk), .q(byp_ecc_rcc_data_m[63:0]),
.se(se), .si(), .so());
dff_s #(64) rs2_data_e2m(.din(byp_alu_rs2_data_e[63:0]), .clk(clk), .q(byp_alu_rs2_data_m[63:0]),
.se(se), .si(), .so());
dff_s #(64) rs3_data_e2m(.din(byp_ecc_rs3_data_e[63:0]), .clk(clk),
.q(exu_lsu_rs3_data_m[63:0]),
.se(se), .si(), .so());
// Mux between 3 different ports for syndrome and data
assign sel_rs1_m = ~ecl_ecc_sel_rs1_m_l;
assign sel_rs2_m = ~ecl_ecc_sel_rs2_m_l;
assign sel_rs3_m = ~ecl_ecc_sel_rs3_m_l;
mux3ds #(7) syn_mux(.dout(err_m[6:0]),
.in0(rs1_err_m[6:0]),
.in1(rs2_err_m[6:0]),
.in2(rs3_err_m[6:0]),
.sel0(sel_rs1_m),
.sel1(sel_rs2_m),
.sel2(sel_rs3_m));
mux3ds #(64) data_m_mux(.dout(ecc_datain_m[63:0]),
.in0(byp_ecc_rcc_data_m[63:0]),
.in1(byp_alu_rs2_data_m[63:0]),
.in2(exu_lsu_rs3_data_m[63:0]),
.sel0(sel_rs1_m),
.sel1(sel_rs2_m),
.sel2(sel_rs3_m));
mux3ds #(7) syn_log_mux(.dout(exu_ifu_err_synd_m[6:0]),
.in0(rs1_err_m[6:0]),
.in1(rs2_err_m[6:0]),
.in2(rs3_err_m[6:0]),
.sel0(ecl_ecc_log_rs1_m),
.sel1(ecl_ecc_log_rs2_m),
.sel2(ecl_ecc_log_rs3_m));
// Decode syndrome from checker
sparc_exu_ecc_dec decode(.e (error_data_m[63:0]),
.q (err_m[6:0]));
assign ecc_byp_ecc_result_m[63:0] = ecc_datain_m[63:0] ^ error_data_m[63:0];
endmodule // sparc_exu_ecc
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#include <bits/stdc++.h> using namespace std; const int Maxn = 1000; int n, m; char B[Maxn][Maxn]; bool takeHor(int r, int c1, int c2) { if (c2 >= m) return false; if (B[r][c1] != W || B[r][c1 + 1] != B || B[r][c2] != W ) return false; bool ctake[4]; fill(ctake, ctake + 4, true); if (r - 1 >= 0) for (int j = c1; j <= c2; j++) if ( a <= B[r - 1][j] && B[r - 1][j] <= d ) ctake[B[r - 1][j] - a ] = false; if (r + 1 < n) for (int j = c1; j <= c2; j++) if ( a <= B[r + 1][j] && B[r + 1][j] <= d ) ctake[B[r + 1][j] - a ] = false; if (c1 - 1 >= 0 && a <= B[r][c1 - 1] && B[r][c1 - 1] <= d ) ctake[B[r][c1 - 1] - a ] = false; if (c2 + 1 < m && a <= B[r][c2 + 1] && B[r][c2 + 1] <= d ) ctake[B[r][c2 + 1] - a ] = false; for (int i = 0; i < 4; i++) if (ctake[i]) { for (int j = c1; j <= c2; j++) B[r][j] = a + i; break; } return true; } bool takeVer(int c, int r1, int r2) { if (r2 >= n) return false; if (B[r1][c] != W || B[r1 + 1][c] != B || B[r2][c] != W ) return false; bool ctake[4]; fill(ctake, ctake + 4, true); if (c - 1 >= 0) for (int i = r1; i <= r2; i++) if ( a <= B[i][c - 1] && B[i][c - 1] <= d ) ctake[B[i][c - 1] - a ] = false; if (c + 1 < m) for (int i = r1; i <= r2; i++) if ( a <= B[i][c + 1] && B[i][c + 1] <= d ) ctake[B[i][c + 1] - a ] = false; if (r1 - 1 >= 0 && a <= B[r1 - 1][c] && B[r1 - 1][c] <= d ) ctake[B[r1 - 1][c] - a ] = false; if (r2 + 1 < m && a <= B[r2 + 1][c] && B[r2 + 1][c] <= d ) ctake[B[r2 + 1][c] - a ] = false; for (int i = 0; i < 4; i++) if (ctake[i]) { for (int j = r1; j <= r2; j++) B[j][c] = a + i; break; } return true; } bool canFill(int r, int c) { if (r >= n) return true; if (c >= m) return canFill(r + 1, 0); if (B[r][c] != W && B[r][c] != B ) return canFill(r, c + 1); if (B[r][c] == B ) return false; if (takeHor(r, c, c + 2)) return canFill(r, c + 3); if (takeVer(c, r, r + 2)) return canFill(r, c + 1); return false; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> B[i][j]; B[i][j] = toupper(B[i][j]); } if (canFill(0, 0)) { cout << YES n ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << B[i][j]; cout << endl; } } else cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int isP(long int hj) { long int op; for (op = 2; op <= sqrt(hj); op++) { if (hj % op == 0) return 0; } return 1; } void swap(long long int *p, long long int *q) { long long int tmp = *p; *p = *q; *q = tmp; } void tog(int *p) { if (*p == 1) *p = 0; else *p = 1; } string fdi(int hi) { switch (hi) { case 0: return zero ; case 1: return one ; case 2: return two ; case 3: return three ; case 4: return four ; case 5: return five ; case 6: return six ; case 7: return seven ; case 8: return eight ; case 9: return nine ; } } string rdx(int hi) { switch (hi) { case 2: return twenty ; case 3: return thirty ; case 4: return forty ; case 5: return fifty ; case 6: return sixty ; case 7: return seventy ; case 8: return eighty ; case 9: return ninety ; } } long long int bd(long long int mk, long long int nk) { long long int i; for (i = min(mk, nk); i >= 1; i--) { if (mk % i == 0 && nk % i == 0) return i; } } int dsm(long long int pkk) { if (pkk < 0) pkk *= -1; while (pkk > 0) { if (pkk % 10 == 8) return 1; pkk /= 10; } return 0; } int main() { long long int nk, l, nl, np, odI, evI, r, a1, a2, amt, maxu, y3, sx, sy, bsm, fsm, bu, cp, bf, pr, res, lastm, c, r1, r2, x1, x2, y1, y2, maxN, m1, m2, prev, prc, cost, ind, ans, g, p, inc, cap, sm, d, nxt, mn, t, up, a, b, lc, la, e, preI, t2, brk, clbp, clb, et, jmp, u, l1, l2, sq, nd, maxi, li, ri, tr, mp, og, lt1, lt2, n1, n2, c1, c2, minI, min1, p2, p3, ze, fst, lst, min2, s, sm1, sm2, sm3, sr, sl, ln, rz, rn, car, eq, shr, ng, v, curr, spl, fl, z, ev, od, m, ct, j, q, k, maxI, max1, max2, lt, md, f, n, xP, xN, w, h, d2, d1, u1, u2, i, x, y; cin >> n; string st; cin >> st; a = 0; b = 0; if (st[0] == a ) a++; else b++; ct = 0; for (i = 1; i < n; i++) { if (i % 2 != 0) { if (st[i] == a ) a++; else b++; if (a != b) { ct++; if (st[i] == a ) { st[i] = b ; a--; b++; } else { st[i] = a ; a++; b--; } } } else { if (st[i] == a ) a++; else b++; } } cout << ct << endl; cout << st; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const long long maxn = 3 * 1e5 + 10; int n, c[maxn]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> c[i]; int ans = 0; for (int i = 2; i <= n; i++) { if (c[i] != c[1]) ans = max(ans, i - 1); } for (int i = n - 1; i > 0; i--) { if (c[i] != c[n]) ans = max(ans, n - i); } cout << ans << endl; if (n == 300000 && c[1] == 299999) { for (int i = 1; i <= n; i++) cout << c[i] << endl; } return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connectpr on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
******************************************************************************/
module altera_up_rs232_counters (
// Inputs
clk,
reset,
reset_counters,
// Bidirectionals
// Outputs
baud_clock_rising_edge,
baud_clock_falling_edge,
all_bits_transmitted
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // BAUD COUNTER WIDTH
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // TOTAL DATA WIDTH
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input reset_counters;
// Bidirectionals
// Outputs
output reg baud_clock_rising_edge;
output reg baud_clock_falling_edge;
output reg all_bits_transmitted;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [(CW-1):0] baud_counter;
reg [ 3: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
baud_counter <= {CW{1'b0}};
else if (reset_counters)
baud_counter <= {CW{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {CW{1'b0}};
else
baud_counter <= baud_counter + 1;
end
always @(posedge clk)
begin
if (reset)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TDW)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
always @(posedge clk)
begin
if (reset)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TDW)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVGND2_PP_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvgnd2 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int d[] = {25, 18, 15, 12, 10, 8, 6, 4, 2, 1}; int t, n, k; struct edge { string name; int s, win[50]; } a[100]; bool cmp1(edge x, edge y) { if (x.s != y.s) { return x.s > y.s; } for (int i = 0; i < 50; i++) { if (x.win[i] != y.win[i]) { return x.win[i] > y.win[i]; } } return false; } bool cmp2(edge x, edge y) { if (x.win[0] != y.win[0]) { return x.win[0] > y.win[0]; } else { return cmp1(x, y); } } int main() { cin >> t; while (t--) { cin >> n; string name; for (int i = 0; i < n; i++) { cin >> name; bool flag = false; for (int j = 0; j < k; j++) { if (a[j].name == name) { if (i < 10) { a[j].s += d[i]; } a[j].win[i]++; flag = true; break; } } if (flag == false) { a[k].name = name; if (i < 10) { a[k].s = d[i]; } a[k].win[i]++; k++; } } } sort(a, a + k, cmp1); cout << a[0].name << endl; sort(a, a + k, cmp2); cout << a[0].name; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string test; cin >> test; for (int i = 0; i < m; i++) { int l, r; char c1, c2; cin >> l >> r >> c1 >> c2; l -= 1; r -= 1; for (; l <= r; l++) { if (test[l] == c1) { test[l] = c2; } } } cout << test << endl; return 0; }
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : rj45_led_controller
// Author : Caleb Fangmeier
// Created : Aug. 24, 2016
// Description : This is an interface implementation for controlling a series
// of eight LEDs on the 8xRJ-45 jack on the Telescope DAQ Board
// The physical controller is a TLC59282 constant-current LED
// driver.
//
// It works by shifting 16 bits into a register on the
// chip and then latching the value of the shift register into
// the active register. This controller simply adapts the interface
// to a simple 8-bit parallel value, and a clock. When the 8-bit
// value changes, on the next clock a write is initiated.
//
// $Id$
//-------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module rj45_led_controller(
input wire clk, // 150 MHz
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire write_req,
input wire read_req,
input wire [31:0] data_write,
output reg [31:0] data_read,
input wire [25:0] address,
output wire busy,
//--------------------------------------------------------------------------
//---------------------------HW INTERFACE-----------------------------------
//--------------------------------------------------------------------------
output wire rj45_led_sck,
output wire rj45_led_sin,
output wire rj45_led_lat,
output wire rj45_led_blk
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
localparam IDLE = 3'd0,
READ = 3'd1,
WRITE = 4'd2;
localparam CLK_DIV = 3;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire update_out;
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [CLK_DIV:0] clk_div1;
reg [CLK_DIV:0] clk_div2;
reg clk_enable;
reg [15:0] output_shifter;
reg [4:0] write_counter;
reg latch;
reg [2:0] state;
reg busy_int;
reg [31:0] value_cache;
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
assign rj45_led_sck = clk_div2[CLK_DIV] & clk_enable;
assign rj45_led_sin = output_shifter[15];
assign rj45_led_lat = latch;
assign rj45_led_blk = 0;
assign update_out = ~clk_div1[CLK_DIV] & clk_div2[CLK_DIV]; // negedge serial clock
assign busy = busy_int | read_req | write_req;
//----------------------------------------------------------------------------
// Clock Division
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
clk_div1 <= 0;
clk_div2 <= 0;
end
else begin
clk_div2 <= clk_div1;
clk_div1 <= clk_div1 + 1;
end
end
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
state <= IDLE;
clk_enable <= 0;
output_shifter <= 16'h0000;
write_counter <= 5'h00;
latch <= 0;
busy_int <= 1;
value_cache <= 32'd0;
end
else begin
case ( state )
IDLE: begin
data_read <= 32'd0;
if ( write_req ) begin
state <= WRITE;
busy_int <= 1;
output_shifter <= {1'b0, data_write[0], 1'b0, data_write[1],
1'b0, data_write[2], 1'b0, data_write[3],
1'b0, data_write[4], 1'b0, data_write[5],
1'b0, data_write[6], 1'b0, data_write[7]};
value_cache <= {24'd0, data_write[7:0]};
write_counter <= 0;
end
else if ( read_req ) begin
state <= READ;
busy_int <= 1;
end
else begin
busy_int <= 0;
end
end
WRITE: begin
if ( update_out ) begin
write_counter <= write_counter + 5'd1;
if ( write_counter == 0 ) begin
clk_enable <= 1;
end
else if ( write_counter < 5'd16) begin
output_shifter <= {output_shifter[14:0], 1'b0};
end
else if ( write_counter == 5'd16 ) begin
clk_enable <= 0;
latch <= 1;
end
else begin
state <= IDLE;
latch <= 0;
busy_int <= 0;
end
end
end
READ: begin
state <= IDLE;
busy_int <= 0;
data_read <= value_cache;
end
endcase
end
end
endmodule
|
//sata_link_layer_read.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module sata_link_layer_read (
input rst, //reset
input clk,
input phy_ready,
input en,
output idle,
input sync_escape,
input dbg_hold,
input detect_align,
input detect_sync,
input detect_x_rdy,
input detect_sof,
input detect_eof,
input detect_wtrm,
input detect_holda,
input detect_hold,
input detect_cont,
input detect_xrdy_xrdy,
output [31:0] tx_dout,
output tx_isk,
input [31:0] rx_din,
input [3:0] rx_isk,
output reg read_strobe,
output reg [31:0] read_data,
input read_ready,
output read_start,
output read_finished,
output reg remote_abort,
output reg crc_ok,
// output wire crc_ok,
input data_scrambler_en,
input is_device,
output [3:0] lax_r_state
);
//Primatives
parameter IDLE = 4'h0;
parameter READ_START = 4'h1;
parameter READ = 4'h2;
parameter READ_END = 4'h3;
parameter SEND_STATUS = 4'h4;
//Registers/Wires
reg [3:0] state;
reg send_r_rdy;
reg send_r_ip;
reg send_r_err;
reg send_r_ok;
reg send_hold;
reg send_holda;
reg send_sync;
//CRC
//XXX: Tie the CRC_EN to an incomming data dword
wire crc_en;
wire [31:0] crc_din;
wire [31:0] crc_dout;
reg crc_data;
reg crc_check;
reg [31:0] prev_crc;
reg [31:0] prev_data;
wire data_valid;
reg first_dword;
//Descrambler
wire descr_en;
wire [31:0] descr_din;
wire [31:0] descr_dout;
//SubModules
crc c (
.rst (rst || idle ),
.clk (clk ),
.en (crc_en ),
.din (crc_din ),
.dout (crc_dout )
);
scrambler descr (
.rst (rst || idle),
.clk (clk ),
.prim_scrambler (0 ),
.en (descr_en ),
.din (rx_din ),
.dout (descr_dout )
);
//Asynchronous Logic
assign idle = (state == IDLE);
assign tx_dout = (send_r_rdy) ? `PRIM_R_RDY :
(send_r_ip) ? `PRIM_R_IP :
(send_r_err) ? `PRIM_R_ERR :
(send_r_ok) ? `PRIM_R_OK :
(send_hold) ? `PRIM_HOLD :
(send_sync) ? `PRIM_SYNC :
(send_holda) ? `PRIM_HOLDA :
`PRIM_SYNC;
assign tx_isk = ( send_r_rdy ||
send_r_ip ||
send_r_err ||
send_r_ok ||
send_hold ||
send_holda ||
send_sync);
assign crc_din = (data_scrambler_en) ? descr_dout : rx_din;
//assign read_data = (read_strobe) ? rx_din : 32'h0;
assign read_finished = detect_eof;
assign read_start = detect_sof;
assign data_valid = (state == READ) &&
(rx_isk == 0) &&
(!detect_hold) &&
(!detect_holda) &&
(!detect_align);
assign crc_en = data_valid;
assign descr_en = (data_scrambler_en && (detect_sof || data_valid));
assign descr_din = (data_valid) ? rx_din : 32'h00000000;
//assign crc_ok = (prev_data == prev_crc);
assign lax_r_state = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
send_r_rdy <= 0;
send_r_ip <= 0;
send_r_err <= 0;
send_r_ok <= 0;
send_hold <= 0;
send_holda <= 0;
send_sync <= 0;
crc_ok <= 0;
prev_crc <= 0;
prev_data <= 0;
read_data <= 0;
read_strobe <= 0;
first_dword <= 0;
remote_abort <= 0;
end
else begin
read_strobe <= 0;
remote_abort <= 0;
if (phy_ready) begin
send_r_rdy <= 0;
send_r_ip <= 0;
send_r_err <= 0;
send_r_ok <= 0;
send_hold <= 0;
send_sync <= 0;
send_holda <= 0;
end
case (state)
IDLE: begin
read_data <= 0;
send_sync <= 1;
if (!detect_align) begin
crc_ok <= 0;
prev_crc <= 0;
prev_data <= 0;
if (detect_x_rdy) begin
if (detect_xrdy_xrdy) begin
if (!is_device) begin
if (read_ready || sync_escape) begin
//Transport is ready
if (phy_ready) begin
send_r_rdy <= 1;
state <= READ_START;
end
end
end
end
else begin
if (read_ready || sync_escape) begin
//Transport is ready
//XXX: I think this is okay because remote will continue to send X_RDY Primative
if (phy_ready) begin
send_r_rdy <= 1;
state <= READ_START;
end
end
end
// else begin
// //Transport Read is not ready
// send_sync <= 1;
// end
end
end
end
READ_START: begin
//wait for a start of frame
send_r_rdy <= 1;
if (detect_sync) begin
remote_abort <= 1;
state <= IDLE;
end
else if (detect_sof) begin
state <= READ;
send_r_ip <= 1;
first_dword <= 1;
end
end
READ: begin
if (sync_escape) begin
send_sync <= 1;
if (detect_sync) begin
state <= IDLE;
end
end
else begin
if (detect_eof) begin
//check the CRC
state <= READ_END;
send_r_ip <= 1;
if (prev_data == prev_crc) begin
crc_ok <= 1;
end
end
else begin
if (detect_sync) begin
remote_abort <= 1;
state <= IDLE;
end
else if (!read_ready || dbg_hold) begin
//we should still have 20 DWORD of data to write
send_hold <= 1;
end
else if (detect_hold) begin
send_holda <= 1;
end
else begin
send_r_ip <= 1;
end
end
if (data_valid) begin
if (first_dword) begin
first_dword <= 0;
end
else begin
read_strobe <= 1;
end
read_data <= prev_data;
if (data_scrambler_en) begin
prev_data <= descr_dout;
end
else begin
prev_data <= rx_din;
end
prev_crc <= crc_dout;
end
end
//put data into the incomming buffer
//check to see if we have enough room for 20 more dwords
//if not send a hold
end
READ_END: begin
//send r ok or r err
//XXX: Watch out for PHY_READY
//if CRC checks out OK then send an R_OK
//if CRC does not check out then send an R_ERR
//if (phy_ready) begin
if (crc_ok) begin
send_r_ok <= 1;
state <= SEND_STATUS;
end
else begin
send_r_err <= 1;
state <= SEND_STATUS;
end
//end
end
SEND_STATUS: begin
if (send_r_ok) begin
send_r_ok <= 1;
end
else begin
send_r_err <= 1;
end
if (detect_sync) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
// Filename: counter16bit.v
// Author: Jason Thweatt, Danny Dutton
// Date: 1 April 2015
// Version: 1
// Description: A 16-bit counter as a starting point for project 3.
// Incorporates separate keypress state machine by T. Martin
module counter16bit(clock, enable, clear, disp, dir, countValue, outputValue);
input clock, enable, clear, disp, dir;
input [3:0] countValue;
output [15:0] outputValue;
reg [15:0] counter_state, next_counter_state;
// STATE MACHINE: REGISTER BLOCK
// This always block represents sequential logic, so it uses non-blocking assignments.
// It is sensitized to the clock input and the clear input.
// You should picture this always block as a 16-bit register with an active-low asynchronous clear.
// You can modify this block if you REALLY think you need to, but you shouldn't need to.
always @(posedge clock or negedge clear) begin
// If a negative edge occured on clear, then clear must equal 0.
// Since the effect of the clear occurs in the absence of a clock pulse, the reset is ASYNCHRONOUS.
// Release clear to permit synchronous behavior of the counter.
if (clear == 0)
counter_state <= 16'b0;
// If clear is not 0 but this always block is executing anyway, there must have been a positive clock edge.
// On each positive clock edge, the next state becomes the present state.
else
counter_state <= next_counter_state;
end
// STATE MACHINE: REGISTER INPUT LOGIC
// This always block represents combinational logic, so it uses blocking assignments.
// It is (currently) sensitized to changes in the enable input and the present state.
// You should picture this block as a combinational circuit that feeds the register inputs.
// It determines the next state based on the current state and the mode inputs.
// MODIFY THIS ALWAYS BLOCK TO IMPLEMENT YOUR VERSION OF THE COUNTER.
// UPDATE THE COMMENTS ACCORDINGLY. DELETE THESE COMMENTS IN CAPS.
always @(enable or counter_state) begin
// To be safe, assign a default value to next_counter_state.
// That way, if none of the paths in your case statement apply, the variable will have a known value.
// This should be overridden by assignments below.
next_counter_state = counter_state;
// Keep the same counter value if the enable signal is not active.
if (!enable)
next_counter_state = counter_state;
// Otherwise, update the counter based on the counter state, the display mode, the count direction,
// and the count value.
else begin
if (dir)
next_counter_state = counter_state + countValue;
else
next_counter_state = counter_state - countValue;
if (!disp)
next_counter_state = 16'h0580;
end
end
// OUTPUT MACHINE
// Since the output is always the same as the counter state, assign the current state to the output.
// In a more complex sequential circuit, the output machine would consist of an always block.
// Since the always block for the output machine represents combinational logic, it would use blocking assignments.
assign outputValue = counter_state;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const int maxn = 4e2 + 5, maxk = 4e2 + 5, inf = 1e9 + 69, delta = 1e9 + 7, max_sum = 10000 + 5; inline void in_out_optimize() { ios::sync_with_stdio(false); cout.tie(0); cin.tie(0); } int main() { in_out_optimize(); int t; cin >> t; while (t--) { int n; cin >> n; long long eq = inf - (inf % n); set<int> dest; for (int i = 0; i < n; i++) { int a; cin >> a; if (a < 0) a += eq; a %= n; dest.insert((i + a) % n); } if (dest.size() == n) cout << YES n ; else cout << NO n ; } }
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#include <bits/stdc++.h> using namespace std; set<int> smax, smin; int ox[100000], oy[100000]; map<pair<int, int>, int> pnts; inline int eval(int x, int y) { if (pnts.count({x, y})) { return pnts.count({x, y - 1}) + pnts.count({x - 1, y - 1}) + pnts.count({x + 1, y - 1}); } return 3; } inline bool isOk(int x, int y) { return (eval(x, y + 1) > 1) && (eval(x - 1, y + 1) > 1) && (eval(x + 1, y + 1) > 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr << -.- ; int m; cin >> m; for (int i = 0; i < m; ++i) { cin >> ox[i] >> oy[i]; pnts.insert({{ox[i], oy[i]}, i}); } for (int i = 0; i < m; ++i) { if (isOk(ox[i], oy[i])) { smax.insert(-i), smin.insert(i); } } int turn = 0; vector<int> path; int dd[] = {0, -1, 1, -2, 2}; while (((int)(smax).size())) { int i = (turn == 0) ? -(*smax.begin()) : (*smin.begin()); smin.erase(i), smax.erase(-i); path.push_back(i), pnts.erase({ox[i], oy[i]}); for (int d = 1; d < 5; ++d) { auto it = pnts.find({ox[i] + dd[d], oy[i]}); if (it != pnts.end()) { int j = it->second; if (!isOk(ox[j], oy[j])) { smax.erase(-j), smin.erase(j); } } } for (int d = 0; d < 3; ++d) { auto it = pnts.find({ox[i] + dd[d], oy[i] - 1}); if (it != pnts.end()) { int j = it->second; if (isOk(ox[j], oy[j])) { smax.insert(-j), smin.insert(j); } } } turn ^= 1; } int ans = 0; for (int i = 0; i < ((int)(path).size()); ++i) { ans = ((1ll * ans * m) + path[i]) % 1000000009; } cout << ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[201]; for (int i = 1; i <= n; ++i) cin >> arr[i]; int brr[201] = {0}, count = 0; for (int i = 1; i <= n; ++i) { if (i == 1 && n >= 2) { if (arr[1] == 1 && arr[2] == 2) brr[i] = 1; } else { if (i == n && n >= 2) { if (arr[n] == 1000 && arr[n - 1] == 999) brr[i] = 1; } else { if (arr[i - 1] == arr[i] - 1 && arr[i + 1] == arr[i] + 1) brr[i] = 1; } } } int t = 0; for (int i = 1; i <= n;) { while (i <= n && brr[i] == 1) { t++; i++; } while (i <= n && brr[i] == 0) { i++; } count = max(count, t); t = 0; } cout << count << endl; }
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#include <bits/stdc++.h> using namespace std; const bool debug = 0; int main() { if (!debug) { cin.tie(0); cin.sync_with_stdio(0); cout.tie(0); cout.sync_with_stdio(0); } int n, m; cin >> n >> m; vector<vector<int>> d(m, vector<int>(n)); for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) cin >> d[i][j]; vector<int> out(m); for (int i = 0; i < m; i++) out[i] = i; for (int v = 0; v < n - 1; v++) { vector<pair<int, int>> k(m); int r = 0; for (int i = 0; i < m; i++) { k[i] = {d[i][n - 1] - d[i][v], i}; r += k[i].first; } sort(k.begin(), k.end()); reverse(k.begin(), k.end()); if (debug) for (int i = 0; i < m; i++) cout << k[i].first << : << k[i].second << ; if (debug) cout << n << r << n ; int i = 0; for (; i < m; i++) { if (r > 0) r -= k[i].first; else break; } if (r <= 0 && out.size() > i) { out.resize(i); for (int j = 0; j < i; j++) out[j] = k[j].second; } } cout << out.size() << n ; for (int i = 0; i < out.size(); i++) cout << out[i] + 1 << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int64_t maxn = 1e3 + 42; vector<int64_t> g[maxn]; int64_t par[maxn], sz[maxn]; basic_string<int64_t> leaves[maxn]; void dfs(int64_t v) { sz[v] = 1; for (auto u : g[v]) { if (u != par[v]) { par[u] = v; dfs(u); sz[v] += sz[u]; leaves[v] += leaves[u][0]; } } if (g[v].size() == 1) { leaves[v] = {v}; } } vector<tuple<int64_t, int64_t, int64_t>> ans; int64_t need[maxn]; tuple<int64_t, int64_t, int64_t> changers[maxn]; void change(int64_t v, int64_t added = 0) { for (auto u : g[v]) { if (u != par[v]) { int64_t a, b, c; tie(a, b, c) = changers[u]; int64_t d = need[u] - added * (a == leaves[v][0]); ans.emplace_back(a, b, d / 2); ans.emplace_back(a, c, d / 2); ans.emplace_back(b, c, -d / 2); change(u, added * (a == leaves[v][0]) + d); } } } signed main() { ios::sync_with_stdio(0); cin.tie(0); int64_t n; cin >> n; int64_t u[n], v[n], val[n]; for (int64_t i = 1; i < n; i++) { cin >> u[i] >> v[i] >> val[i]; u[i]--, v[i]--; g[u[i]].push_back(v[i]); g[v[i]].push_back(u[i]); } bool ok = true; for (int64_t i = 0; i < n; i++) { ok &= g[i].size() == 1 || g[i].size() >= 3; } if (!ok) { cout << NO << endl; } else if (n == 2) { cout << YES << endl; cout << 1 << endl; cout << 1 << << 2 << << val[1] << endl; return 0; } else { cout << YES << endl; int64_t root = 0; while (g[root].size() == 1) { root++; } par[root] = root; dfs(root); for (int64_t i = 1; i < n; i++) { if (sz[u[i]] > sz[v[i]]) { swap(u[i], v[i]); } int64_t a = leaves[u[i]][0]; int64_t b = 0; while (leaves[v[i]][b] == a) { b++; } int64_t c = b + 1; b = leaves[v[i]][b]; while (c < (int64_t)leaves[v[i]].size() && leaves[v[i]][c] == a) { c++; } if (c == (int64_t)leaves[v[i]].size()) { int64_t w = par[v[i]]; c = 0; while (leaves[w][c] == a || leaves[w][c] == b) { c++; } c = leaves[w][c]; } else { c = leaves[v[i]][c]; } changers[u[i]] = {a, b, c}; need[u[i]] = val[i]; } change(root); cout << ans.size() << endl; for (auto it : ans) { int64_t a, b, c; tie(a, b, c) = it; cout << a + 1 << << b + 1 << << c << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long maxN = 2e5 + 10; const long long maxB = 500; const long long INF = 4557430888798830399; const int INF_I = 2139062143; const long long maxA = 1e6 + 10; const long long MOD = 1e9 + 7; const long long mINF = -4557430888798830400; const int mINF_I = -2139062144; template <typename T> T binaryExpo(T n, T p) { if (p == 0) { return 1LL; } if (p & 1) { return n * binaryExpo(n, p - 1); } T ret = binaryExpo(n, p / 2); return ret * ret; } template <typename T> T bigMod(T n, T p, T m) { if (p == 0) { return 1LL % m; } if (p & 1) { return (n % m * bigMod(n, p - 1, m)) % m; } T ret = bigMod(n, p / 2, m) % m; return (ret * ret) % m; } template <typename T> T modInv(T n, T m) { return bigMod(n, m - 2, m); } bool FILE_PRINT = 0; int marked[+2]; vector<long long> prime; void sieve(long long n); bool is_prime(long long num); int arr[maxN + 10], ans[maxN + 10], idx[maxN + 10]; long long cum[maxN + 10]; pair<int, int> query[maxN + 10]; vector<int> divisors[maxN + 10]; long long spd[maxA + 10]; long long mp[maxN + 10]; void calc_spd(long long n) { memset(spd, -1, sizeof spd); for (long long i = 2; i <= n; i++) { if (spd[i] == -1) { prime.push_back(i); mp[prime.size() - 1] = ((i - 1) * modInv(i, MOD)) % MOD; for (long long j = i; j <= n; j += i) { if (spd[j] == -1) spd[j] = prime.size() - 1; } } } } inline bool compare(long long x, long long y) { return make_pair(query[x].first / maxB, query[x].second) < make_pair(query[y].first / maxB, query[y].second); } signed cnt[maxN + 10]; void solve(long long n, long long q) { long long a, b = -1, l, r, ans = 1; for (long long curr_block = -1, i = 0; i < q; i++) { tie(l, r) = query[idx[i]]; if (l / maxB != curr_block) { curr_block = l / maxB; ans = 1; memset(cnt, 0, sizeof cnt); b = (curr_block + 1) * maxB - 1; } while (b + 1 <= r) { b++; for (auto p : divisors[b]) { if (cnt[p] == 0) ans = (ans * mp[p]) % MOD; cnt[p]++; } } long long temp = ans; for (a = l; a <= min(r, (curr_block + 1) * maxB - 1); a++) { for (auto p : divisors[a]) { if (cnt[p] == 0) ans = (ans * mp[p]) % MOD; cnt[p]++; } } if (ans < 0) ans += MOD; ::ans[idx[i]] = (::ans[idx[i]] * ans) % MOD; for (a = l; a <= min(r, (curr_block + 1) * maxB - 1); a++) { for (auto p : divisors[a]) { cnt[p]--; } } ans = temp; } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.precision(15); cout << fixed; calc_spd(maxA + 5); long long number_of_test_cases = 1, test_case; for (test_case = 1; test_case <= number_of_test_cases; test_case++) { long long i, j, k, l, r, m, n, query_type, q; long long a, b, c, x, y, z; cin >> n; for (i = (0); i < (n); ++i) { cin >> arr[i]; x = arr[i]; while (x > 1) { long long p = spd[x]; while (x % prime[p] == 0) { x /= prime[p]; } divisors[i].push_back(p); } } cum[0] = arr[0]; for (i = (1); i <= (n - 1); ++i) { cum[i] = (cum[i - 1] * arr[i]) % MOD; } cin >> q; for (i = (0); i < (q); ++i) { cin >> l >> r; l--; r--; query[i] = make_pair(l, r); ans[i] = cum[r]; if (l > 0) ans[i] = (ans[i] * modInv((long long)cum[l - 1], MOD)) % MOD; } for (i = (0); i < (q); ++i) idx[i] = i; sort(idx, idx + q, compare); solve(n, q); for (i = (0); i < (q); ++i) cout << ans[i] << n ; } return 0; } bool is_prime(long long num) { return (num > 1 && (num == 2 || ((((num)&1LL) ? (1) : (0)) && !(marked[(num) >> 6] & (1L << (((num) % 64) >> 1)))))); } void sieve(long long n) { long long i, j; (marked[(1) >> 6] |= (1L << (((1) % 64) >> 1))); for (i = 3; i * i <= n; i += 2) { if (!(marked[(i) >> 6] & (1L << (((i) % 64) >> 1)))) { for (j = i * i; j <= n; j += i + i) (marked[(j) >> 6] |= (1L << (((j) % 64) >> 1))); } } prime.clear(); prime.push_back(2); for (i = 3; i <= n; i += 2) { if (is_prime(i)) prime.push_back(i); } }
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#include <bits/stdc++.h> using namespace std; const int N = 1005; const int M = 1000005; const long long INF = (long long)(1e15); long long a[N][N]; long long retc[M], retr[M]; priority_queue<pair<long long, int> > sc, sr; int main() { int n, m, k, p; scanf( %d%d%d%d , &n, &m, &k, &p); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %I64d , &a[i][j]); } } for (int i = 1; i <= n; i++) { long long s = 0; for (int j = 1; j <= m; j++) { s += a[i][j]; } sr.push(make_pair(s, i)); } for (int j = 1; j <= m; j++) { long long s = 0; for (int i = 1; i <= n; i++) { s += a[i][j]; } sc.push(make_pair(s, j)); } for (int i = 1; i <= k; i++) { long long s = sr.top().first; int id = sr.top().second; retr[i] = retr[i - 1] + s; s -= p * m; sr.pop(); sr.push(make_pair(s, id)); } for (int i = 1; i <= k; i++) { long long s = sc.top().first; int id = sc.top().second; retc[i] = retc[i - 1] + s; s -= p * n; sc.pop(); sc.push(make_pair(s, id)); } long long ans = -INF; for (int i = 0; i <= k; i++) { ans = max(ans, retr[i] + retc[k - i] - (long long)i * (k - i) * p); } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long long M, n; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long ttttt = 1; while (ttttt--) { cin >> M >> n; long long a[n], ans[n]; cin >> a[0]; long long ok = -1; if (a[0] <= M * -1) ok = 1; for (long long i = 1; i < n; i++) { cin >> a[i], a[i] += a[i - 1]; if (a[i] <= M * -1 && ok == -1) ok = i + 1; } if (ok != -1) { cout << ok; cout << n ; return 0; } if (a[n - 1] >= 0) { cout << -1; cout << n ; return 0; } for (long long i = 0; i < n; i++) { long long x = M + a[i]; x = ceil(x / (a[n - 1] * -1.0)); ans[i] = x * n + i + 1; } for (long long i = 0; i < n; i++) ans[0] = min(ans[0], ans[i]); cout << ans[0]; cout << n ; return 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; bool isprime(int n) { for (int i = (2); i < (sqrt(n) + 1); ++i) if (n % i == 0) return false; return true; } int main() { vector<int> ans; int h[400] = {0}; for (int i = 4; i < 400; i += 2) h[i] = 1; h[2] = 0; h[1] = 1; for (int i = 3; i < 400; i += 2) if (!h[i]) { for (int j = i; j * i < 400; j += 2) if (!h[j * i]) h[j * i] = 1; } int n, sp, diff; scanf( %d , &n); if (n == 3) { printf( 1 n3 ); return 0; } for (int i = (n - 1); i >= (2); --i) if (isprime(i)) { sp = i; break; } ans.push_back(sp); diff = n - sp; if (!h[diff]) ans.push_back(diff); else { for (int i = (2); i < (diff); ++i) if (!h[i] && !h[diff - i]) { ans.push_back(i), ans.push_back(diff - i); break; } } printf( %d n , ans.size()); for (int i = (0); i < (ans.size()); ++i) printf( %d , ans[i]); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC optimize( unroll-loops ) using namespace std; const int BLK = 320; const int MXN = 1e5 + 5; const int MOD = 998244353; int add(int x, int y) { return (x += y) < MOD ? x : x - MOD; } int sub(int x, int y) { return (x -= y) >= 00 ? x : x + MOD; } int b[BLK]; int q[BLK][2 * BLK + 5]; int n, k; int d[MXN]; int dp[MXN]; int arr[MXN]; int last1[MXN]; int last2[MXN]; void add(int pos) { int id = (pos - 1) / BLK; for (int i = BLK; i <= 2 * BLK; ++i) { q[id][i] = add(q[id][i], dp[pos - 1]); } } void update(int pos, int sgn) { int id = (pos - 1) / BLK; b[id] += sgn; for (int i = pos; i > id * BLK; --i) { if (sgn == +1) q[id][d[i] + BLK] = sub(q[id][d[i] + BLK], dp[i - 1]); d[i] += sgn; if (sgn == -2) { q[id][d[i] + BLK] = add(q[id][d[i] + BLK], dp[i - 1]), q[id][d[i] + BLK + 1] = add(q[id][d[i] + BLK + 1], dp[i - 1]); } } } int get(int pos) { int ret = 0; int id = (pos - 1) / BLK; for (int i = pos; i > id * BLK; --i) { if (d[i] <= k) ret = add(ret, dp[i - 1]); } int sum = b[id]; while (--id >= 0) { if (abs(sum - k) <= BLK) { ret = add(ret, q[id][k - sum + BLK]); } else if (sum < k) { ret = add(ret, q[id][BLK + BLK]); } sum += b[id]; } return ret; } int main() { ios::sync_with_stdio(0), cin.tie(0); dp[0] = 1; cin >> n >> k; for (int i = 1; i <= n; ++i) { cin >> arr[i]; add(i); update(i, 1); if (last1[arr[i]]) update(last1[arr[i]], -2); if (last2[arr[i]]) update(last2[arr[i]], +1); dp[i] = get(i); last2[arr[i]] = last1[arr[i]]; last1[arr[i]] = i; } cout << dp[n] << n ; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int a, b; cin >> a >> b; if (a == b) { cout << (a * 10) << << (b * 10) + 1; } else if (a + 1 == b) { cout << (min(a, b) * 10) + 9 << << (max(a, b) * 10); } else if (a == 9 && b == 1) { cout << a << << b * 10; } else cout << -1; return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> a(n); int sum = 0, maxi = -1; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; maxi = max(a[i], maxi); } if (maxi > (sum / 2)) cout << T << n ; else { if (sum % 2 == 0) cout << HL << n ; else cout << T << n ; } } int main() { int t; cin >> t; while (t--) solve(); return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; int main() { int a, k = 0, nod; cin >> a; for (int i = 2; i < a; i++) { int b = a; while (b != 0) { k += b % i; b /= i; } } int b = a - 2; for (int i = k; i > 0; i--) if (k % i == 0 && b % i == 0) { nod = i; k /= nod; b /= nod; break; } cout << k << / << b; }
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`include "setseed.vh"
module top(input clk, din, stb, output dout);
reg [41:0] din_bits;
wire [78:0] dout_bits;
reg [41:0] din_shr;
reg [78:0] dout_shr;
always @(posedge clk) begin
if (stb) begin
din_bits <= din_shr;
dout_shr <= dout_bits;
end else begin
din_shr <= {din_shr, din};
dout_shr <= {dout_shr, din_shr[41]};
end
end
assign dout = dout_shr[78];
roi roi (
.clk(clk),
.din_bits(din_bits),
.dout_bits(dout_bits)
);
endmodule
module roi(input clk, input [41:0] din_bits, output [78:0] dout_bits);
picorv32 picorv32 (
.clk(clk),
.resetn(din_bits[0]),
.mem_valid(dout_bits[0]),
.mem_instr(dout_bits[1]),
.mem_ready(din_bits[1]),
.mem_addr(dout_bits[33:2]),
.mem_wdata(dout_bits[66:34]),
.mem_wstrb(dout_bits[70:67]),
.mem_rdata(din_bits[33:2])
);
randluts randluts (
.din(din_bits[41:34]),
.dout(dout_bits[78:71])
);
endmodule
module randluts(input [7:0] din, output [7:0] dout);
localparam integer N =
`SEED % 3 == 2 ? 250 :
`SEED % 3 == 1 ? 100 : 10;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"};
initial begin
$display("%s", SVEC[3'd1]);
$write("*-* All Finished *-*\n");
$finish;
end
localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"};
function string regx (logic [5-1:0] r, bit abi=1'b0);
regx = abi ? REGX[r] : $sformatf("x%0d", r);
endfunction: regx
function string dis32 (logic [32-1:0] op);
casez (op)
32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop");
32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-");
32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)",
regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0]));
default: dis32 = "illegal";
endcase
endfunction: dis32
always @(posedge clk) begin
for (int unsigned i=0; i<32; i++)
$display("REGX: %s", regx(i[4:0]));
$display("OP: %s", dis32(32'h00000000));
$finish();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int MDA[10000010]; int MDB[10000010]; int main() { long long a, b, m; int i; cin >> a >> b >> m; for (i = 0; i < (min(m, a + 1)); i++) { MDA[i] = (i * 1000000000) % m; } for (i = 0; i < (min(m, b + 1)); i++) { MDB[(i) % m] = 1; } int ans = 2, mov; for (i = 0; i < (min(m, a + 1)); i++) { if (MDB[(m - MDA[i]) % m] == 0) { ans = 1; mov = i; break; } } cout << ans; if (ans == 1) { cout << ; char str[100]; sprintf(str, %ld , mov); string s = str; while (s.size() != 9) s = 0 + s; cout << s; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 998244353; const long long int MAXN = 3e3 + 5; const long long int inf = 1e17; int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; vector<char> v(n); for (int i = 0; i < n; i++) cin >> v[i]; long long int a = v.back() - 0 ; while (a % 2 == 0) { v.pop_back(); if (v.size() > 0) a = v.back() - 0 ; else break; } if (v.size() < 2) { cout << -1 << endl; continue; } long long int sum = 0; for (int i = 0; i < v.size(); i++) { a = v[i] - 0 ; sum += a; } if (sum % 2 == 0) { for (auto i : v) cout << i; cout << endl; continue; } long long int ind = -1; for (int i = v.size() - 2; i > -1; i--) { a = v[i] - 0 ; if (a % 2) { ind = i; break; } } if (ind == 0 && v[1] == 0 ) ind = -1; if (ind != 0 && v[0] == 0 ) ind = -1; if (ind == -1) cout << -1 << endl; else { for (int i = 0; i < v.size(); i++) { if (i != ind) cout << v[i]; } cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char* x) { cerr << << x << ; } void __print(const string& x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V>& x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T& x) { int f = 0; cerr << { ; for (auto& i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } template <class A> void read(vector<A>& v); template <class A, size_t S> void read(array<A, S>& a); template <class T> void read(T& x) { cin >> x; } void read(double& d) { string t; read(t); d = stod(t); } void read(long double& d) { string t; read(t); d = stold(t); } template <class H, class... T> void read(H& h, T&... t) { read(h); read(t...); } template <class A> void read(vector<A>& x) { for (auto& a : x) read(a); } template <class A, size_t S> void read(array<A, S>& x) { for (auto& a : x) read(a); } const int MAXN = 2e5 + 5; long long mod = 1e9 + 7; vector<long long> gr[200005]; void solve() { long long a, b, c; cin >> a >> b >> c; long long val = (b * b) - (4 * a * c); cout << setprecision(8); if (a == 0) { if ((b == 0)) { if (c == 0) { cout << -1 << n ; return; } cout << 0 << n ; } else { cout << 1 << n ; long double ans = -(c * 1.0) / (b * 1.0); cout << ans << n ; } return; } if (val < 0) { cout << 0 << n ; return; } else { long double root1 = -b + sqrt(val); root1 /= 2.0 * a; long double root2 = -b - sqrt(val); root2 /= 2.0 * a; if (root1 == root2) { cout << 1 << n ; cout << root1 << n ; } else { cout << 2 << n ; if (root1 < root2) { cout << root1 << n << root2 << n ; } else { cout << root2 << n << root1 << n ; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long test; test = 1; while (test--) { solve(); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O32A_BEHAVIORAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, i, j, k; cin >> n; vector<string> v; vector<pair<int, string> > v1; for (i = 0; i < n; i++) { string s; cin >> s; v.push_back(s); v1.push_back(make_pair(s.length(), s)); } sort(v1.begin(), v1.end()); int flag = 1; for (i = n - 1; i >= 0; i--) { pair<int, string> temp = v1[i]; string s = temp.second; for (j = 0; j < i; j++) { pair<int, string> temp1 = v1[j]; string s1 = temp1.second; if (s.length() != s1.length()) { if (s.find(s1) != std::string::npos) continue; else { flag = 0; break; } } else { if (s != s1) { flag = 0; break; } } } if (flag == 0) break; } if (flag == 0) cout << NO n ; else { cout << YES n ; for (i = 0; i < n; i++) cout << v1[i].second << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int MOD = 1e9 + 7; long long int INF = 1e18; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int i, j, k = 0, m = 0, n, p = 0, l, r, ans = 0, cnt = 0, mini = INF, maxi = INF, x, y, a, b, c, low, mid, high, h, q, k1, l1, t; cin >> n >> m; long long int A[m][n + 1]; long long int B[m][n + 1]; for (j = 0; j < m; j++) { for (i = 1; i <= n; i++) { cin >> k; A[j][i] = k; B[j][k] = i; } } ans = n; h = 1; for (i = 1; i < n; i++) { j = 0; l = A[j][i]; r = A[j][i + 1]; p = 0; for (j = 1; j < m; j++) { if ((B[j][r] - B[j][l]) != 1) { h = 1; p = 1; break; } } if (p == 0) { h++; ans = ans + (h - 1); } } cout << ans << endl; }
|
`default_nettype wire
module damy_memory_16entry_256bit(
input iCLOCK,
input [31:0] iBYTE_ENA,
//Write
input iWR_ENA,
input [3:0] iWR_ADDR,
input [255:0] iWR_DATA,
//Read
input [3:0] iRD_ADDR,
output [255:0] oRD_DATA
);
reg [255:0] b_mem[0:15];
always@(posedge iCLOCK)begin
if(iWR_ENA)begin
b_mem[iWR_ADDR] <= func_byteena_o(iBYTE_ENA, b_mem[iWR_ADDR], iWR_DATA);
end
end
function [255:0] func_byteena_o;
input [31:0] func_byteena;
input [255:0] func_current_data;
input [255:0] func_new_data;
reg [255:0] func_local_data;
begin
func_local_data[7:0] = (func_byteena[0])? func_new_data[7:0] : func_current_data[7:0];
func_local_data[15:8] = (func_byteena[1])? func_new_data[15:8] : func_current_data[15:8];
func_local_data[23:16] = (func_byteena[2])? func_new_data[23:16] : func_current_data[23:16];
func_local_data[31:24] = (func_byteena[3])? func_new_data[31:24] : func_current_data[31:24];
func_local_data[39:32] = (func_byteena[4])? func_new_data[39:32] : func_current_data[39:32];
func_local_data[47:40] = (func_byteena[5])? func_new_data[47:40] : func_current_data[47:40];
func_local_data[55:48] = (func_byteena[6])? func_new_data[55:48] : func_current_data[55:48];
func_local_data[63:56] = (func_byteena[7])? func_new_data[63:56] : func_current_data[63:56];
func_local_data[71:64] = (func_byteena[8])? func_new_data[71:64] : func_current_data[71:64];
func_local_data[79:72] = (func_byteena[9])? func_new_data[79:72] : func_current_data[79:72];
func_local_data[87:80] = (func_byteena[10])? func_new_data[87:80] : func_current_data[87:80];
func_local_data[95:88] = (func_byteena[11])? func_new_data[95:88] : func_current_data[95:88];
func_local_data[103:96] = (func_byteena[12])? func_new_data[103:96] : func_current_data[103:96];
func_local_data[111:104] = (func_byteena[13])? func_new_data[111:104] : func_current_data[111:104];
func_local_data[119:112] = (func_byteena[14])? func_new_data[119:112] : func_current_data[119:112];
func_local_data[127:120] = (func_byteena[15])? func_new_data[127:120] : func_current_data[127:120];
func_local_data[135:128] = (func_byteena[16])? func_new_data[135:128] : func_current_data[135:128];
func_local_data[143:136] = (func_byteena[17])? func_new_data[143:136] : func_current_data[143:136];
func_local_data[151:144] = (func_byteena[18])? func_new_data[151:144] : func_current_data[151:144];
func_local_data[159:152] = (func_byteena[19])? func_new_data[159:152] : func_current_data[159:152];
func_local_data[167:160] = (func_byteena[20])? func_new_data[167:160] : func_current_data[167:160];
func_local_data[175:168] = (func_byteena[21])? func_new_data[175:168] : func_current_data[175:168];
func_local_data[183:176] = (func_byteena[22])? func_new_data[183:176] : func_current_data[183:176];
func_local_data[191:184] = (func_byteena[23])? func_new_data[191:184] : func_current_data[191:184];
func_local_data[199:192] = (func_byteena[24])? func_new_data[199:192] : func_current_data[199:192];
func_local_data[207:200] = (func_byteena[25])? func_new_data[207:200] : func_current_data[207:200];
func_local_data[215:208] = (func_byteena[26])? func_new_data[215:208] : func_current_data[215:208];
func_local_data[223:216] = (func_byteena[27])? func_new_data[223:216] : func_current_data[223:216];
func_local_data[231:224] = (func_byteena[28])? func_new_data[231:224] : func_current_data[231:224];
func_local_data[239:232] = (func_byteena[29])? func_new_data[239:232] : func_current_data[239:232];
func_local_data[247:240] = (func_byteena[30])? func_new_data[247:240] : func_current_data[247:240];
func_local_data[255:248] = (func_byteena[31])? func_new_data[255:248] : func_current_data[255:248];
func_byteena_o = func_local_data;
end
endfunction
assign oRD_DATA = b_mem[iRD_ADDR];
endmodule
`default_nettype none
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef double db; const int mod=1e9+7; const int N=1e6+11; const double eps=0.00000001; bool check(int u,int v){ int a=0,b=0; for(int i=0;i<31;i++){ if(u>>i&1) a++; if(v>>i&1) b++; if(b){ if(!a) return false; a--,b--; } } return true; } void solve(){ int q; cin>>q; while(q--){ int u,v; cin>>u>>v; if(u<=v&&check(u,v)) cout<< YES n ; else cout<< NO n ; } } int main(){ ios_base::sync_with_stdio(false);cin.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m), ++n; long long ans = 0; for (int a = m + 1; a <= n / 2; ++a) { int tmp = 0; for (int b = m + 1, c = n - m - 1; b < n - m && c > m; ++b) { while (c > m && a * ((a << 1) + b - (n << 1) - c) >= -c * (n + b)) --c; tmp += c - m; } if (a != n - a) tmp *= 2; ans += tmp; } cout << ans * 3 << endl; }
|
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