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#include <bits/stdc++.h> using namespace std; int v[100005]; stack<pair<int, int> > S; vector<pair<int, int> > Q; int main() { int N; scanf( %d , &N); for (int i = 0; i < N; i++) scanf( %d , &v[i]); ++N; v[N] = 0; for (int i = 0; i < N; i++) { int a = v[i]; if (S.empty() && !a) continue; if (S.empty() || a > S.top().first) { int l = (S.empty() ? 0 : S.top().first); for (int j = l + 1; j <= a; j++) S.push(pair<int, int>(j, i)); } if (a < S.top().first) { int l = S.top().first; for (int j = l; j > a; j--) { Q.push_back(pair<int, int>(S.top().second, i)); S.pop(); } } } cout << Q.size() << endl; for (int i = 0; i < (int)Q.size(); i++) printf( %d %d n , Q[i].first + 1, Q[i].second); }
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#include <bits/stdc++.h> using namespace std; int main() { int n, s, i, h, m; cin >> n >> s; int a[110]; a[0] = 0; for (i = 1; i <= n; i++) { cin >> h >> m; a[i] = h * 60 + m; } if (a[1] - a[0] - 1 >= s) { cout << 0 0 ; return 0; } for (i = 2; i <= n; i++) { if (a[i] - a[i - 1] - 2 >= (2 * s)) { cout << (a[i - 1] + s + 1) / 60 << << (a[i - 1] + s + 1) % 60; return 0; } } cout << (a[n] + s + 1) / 60 << << (a[n] + s + 1) % 60; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 10; long long a[MAXN], dp[MAXN]; int main() { long long n, ans = 0; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = n - 2; i >= 0; i--) { dp[i] = dp[i + 1]; if (a[i + 1] == 0) dp[i]++; } for (int i = 0; i < n; i++) if (a[i] == 1) ans += dp[i]; cout << ans; }
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// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef DEBUG
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000;
`else
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
`endif
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0000; // stop1
//4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
// Output mux
reg muxbit;
always @( * )
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule
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module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFFE_PN1P_ (input D, C, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1'b1), .ADn(1'b0), .SLn(R), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1'b1), .ADn(1'b0), .SLn(R), .SD(1'b1), .LAT(1'b0), .Q(Q));
endmodule
module \$_DLATCH_PN0_ (input D, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule
module \$_DLATCH_PN1_ (input D, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
end else
if (WIDTH == 2) begin
CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
end else
if (WIDTH == 3) begin
CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
end else
if (WIDTH == 4) begin
CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif
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// zukonit14 - Kunal Raut #include<bits/stdc++.h> using namespace std; // #include ext/pb_ds/assoc_container.hpp // #include ext/pb_ds/tree_policy.hpp // using namespace __gnu_pbds; // template<class T> // using oset = tree<T, null_type, less<T>, rb_tree_tag, tree_order_statistics_node_update> ; // template<class key, class value, class cmp = std::less<key>> // using omap = tree<key, value, cmp, rb_tree_tag, tree_order_statistics_node_update>; // find_by_order(k) returns iterator to kth element starting from 0; // order_of_key(k) returns count of elements strictly smaller than k; /*/-----------------------------DEFINES----------------------------------/*/ #define ll long long #define ld long double #define pb push_back #define mp make_pair #define fi first #define se second #define pi 3.1415926535 #define all(v) v.begin(), v.end() #define allr(v) v.rbegin(), v.rend() #define ms(s, n) memset(s, n, sizeof(s)) #define prec(n) fixed<<setprecision(n) #define forci(p,n) for(ll i=p;i<(ll)n;i++) #define forcj(p,n) for(ll j=p;j<(ll)n;j++) #define forc(i,p,n) for(ll i=p;i<(ll)n;i++) #define bolt ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); #define bits(a) __builtin_popcountll(a) #define djokovic freopen( input00.txt , r , stdin);freopen( output00.txt , w , stdout); #define inrange(i,a,b) ((i>=min(a,b)) && (i<=max(a,b))) #define sz(a) (ll)a.size() #define sum(a) ( accumulate ((a).begin(), (a).end(), 0ll)) #define mine(a) (*min_element((a).begin(), (a).end())) #define maxe(a) (*max_element((a).begin(), (a).end())) #define mini(a) ( min_element((a).begin(), (a).end()) - (a).begin()) #define maxi(a) ( max_element((a).begin(), (a).end()) - (a).begin()) #define lowb(a, x) ( lower_bound((a).begin(), (a).end(), (x)) - (a).begin()) #define uppb(a, x) ( upper_bound((a).begin(), (a).end(), (x)) - (a).begin()) clock_t time_p = clock(); void rtime() {time_p = clock() - time_p; cout << nTime Taken : << fixed << (float)(time_p) / CLOCKS_PER_SEC << s n ;} /*/-----------------------------INLINE FUNCTIONS----------------------------------/*/ inline ll gcd(ll a, ll b) {if (b == 0) return a; return gcd(b, a % b);} inline ll lcm(ll a, ll b) {return (a / gcd(a, b) * b);} inline bool isprime(ll n) {ll i; for (i = 2; i <= sqrt(n); i++) {if (n % i == 0)return false;} return true;} inline ll ceil(ll num, ll den) {return ((num + den - 1) / den);} /*/-----------------------------TRACE FUNCTIONS----------------------------------/*/ template<class T> ostream& operator<<(ostream &os, string V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template<class T> ostream& operator<<(ostream &os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template<class T> ostream& operator<<(ostream &os, set<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template<class T> ostream& operator<<(ostream &os, multiset<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template<class T, class T1> ostream& operator<<(ostream &os, map<T, T1> S) { os << { ; for (auto s : S) os << ( << s.first << , << s.second << ) ; return os << } ; } template<class L, class R> ostream& operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } #define tracearr(a,n) {cout << #a<< : ;cout<< [ ;for (ll i = 0; i < n; i++) cout << a[i] << ;cout << ] n ;} #define TRACE #ifdef TRACE #define trace(...) __f(#__VA_ARGS__, __VA_ARGS__) template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } #else #define trace(...) #endif /*/-----------------------------MODULAR ARITHMETIC----------------------------------/*/ // const ll modx = 1e9 + 7; const ll modx = 998244353; const ll mod = modx; inline ll add(ll x, ll y, ll mod = modx) { x += y; if (x >= mod) return x - mod; return x % mod; } inline ll sub(ll x, ll y, ll mod = modx) { x -= y; if (x < 0) return x + mod; return x; } inline ll mul(ll x, ll y, ll mod = modx) { return (x * 1ll * y) % mod; } inline ll expo(ll x, ll y, ll mod = modx) { ll ans = 1; while (y) { if (y & 1) ans = mul(ans, x, mod); x = mul(x, x, mod); y >>= 1; } return ans % mod; } inline ll inv(ll x, ll mod = modx) { return expo(x, mod - 2, mod); } /*/-----------------------------CODE BEGINS----------------------------------/*/ #define int long long ll rr[] = {0, 1, 1, 1, 0, -1, -1, -1}; ll cc[] = {1, 1, 0, -1, -1, -1, 0, 1}; //x-y -> URDL , row-column -> RDLU; 0-based; const ll MAXN = 2e5 + 100, MAX2N = 2e3 + 10, LG = 20, INF = 2e18, base = 33; const int N = 1e5 + 5; ll n, m, k, q, x, y, z, a[MAXN], d[MAXN], p[MAXN], vis[MAXN]; vector<ll>g[MAXN]; ll dp[MAXN]; void fill() { for (ll i = 0; i <= n; i++) d[i] = -1, p[i] = -1, dp[i] = 0, g[i].clear(), vis[i] = 0; } void dijkstra(ll s) { d[s] = 0; queue<ll>q; q.push(s); while (!q.empty()) { ll v = q.front(); q.pop(); for (auto u : g[v]) { if (d[u] == -1) { d[u] = d[v] + 1; q.push(u); } } } } void dfs(ll s) { vis[s] = 1; dp[s] = d[s]; for (auto to : g[s]) { if (!vis[to] && d[s] < d[to]) { dfs(to); } if (d[s] < d[to]) dp[s] = min(dp[s], dp[to]); else dp[s] = min(dp[s], d[to]); } } void solve() { cin >> n >> m; fill(); for (ll i = 0; i < m; i++) { ll u, v; cin >> u >> v; --u, --v; g[u].pb(v); } dijkstra(0); dfs(0); for (ll i = 0; i < n; i++) cout << dp[i] << ; cout << n ; } signed main() { bolt; #ifndef ONLINE_JUDGE djokovic; #endif ll t; t = 1; cin >> t; for (ll i = 1; i <= t; i++) { //cout << Case # << i << : ; solve(); } //rtime(); }
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Sdram_WR_FIFO.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_WR_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [8:0] rdusedw;
output wrfull;
output [8:0] wrusedw;
wire sub_wire0;
wire [8:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [8:0] sub_wire4;
wire rdempty = sub_wire0;
wire [8:0] wrusedw = sub_wire1[8:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [8:0] rdusedw = sub_wire4[8:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3b (
VPWR,
VGND,
Y ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_TB_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_ls__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_TB_V
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// result_valid O 1
// result_value O 128 reg
// CLK I 1 clock
// RST_N I 1 reset
// put_args_x_is_signed I 1
// put_args_x I 64
// put_args_y_is_signed I 1
// put_args_y I 64
// EN_put_args I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIntMul_64(CLK,
RST_N,
put_args_x_is_signed,
put_args_x,
put_args_y_is_signed,
put_args_y,
EN_put_args,
result_valid,
result_value);
input CLK;
input RST_N;
// action method put_args
input put_args_x_is_signed;
input [63 : 0] put_args_x;
input put_args_y_is_signed;
input [63 : 0] put_args_y;
input EN_put_args;
// value method result_valid
output result_valid;
// value method result_value
output [127 : 0] result_value;
// signals for module outputs
wire [127 : 0] result_value;
wire result_valid;
// register m_rg_isNeg
reg m_rg_isNeg;
wire m_rg_isNeg$D_IN, m_rg_isNeg$EN;
// register m_rg_signed
reg m_rg_signed;
wire m_rg_signed$D_IN, m_rg_signed$EN;
// register m_rg_state
reg [1 : 0] m_rg_state;
wire [1 : 0] m_rg_state$D_IN;
wire m_rg_state$EN;
// register m_rg_x
reg [127 : 0] m_rg_x;
wire [127 : 0] m_rg_x$D_IN;
wire m_rg_x$EN;
// register m_rg_xy
reg [127 : 0] m_rg_xy;
wire [127 : 0] m_rg_xy$D_IN;
wire m_rg_xy$EN;
// register m_rg_y
reg [63 : 0] m_rg_y;
wire [63 : 0] m_rg_y$D_IN;
wire m_rg_y$EN;
// rule scheduling signals
wire CAN_FIRE_RL_m_compute,
CAN_FIRE_put_args,
WILL_FIRE_RL_m_compute,
WILL_FIRE_put_args;
// inputs to muxes for submodule ports
wire [127 : 0] MUX_m_rg_x$write_1__VAL_1,
MUX_m_rg_x$write_1__VAL_2,
MUX_m_rg_xy$write_1__VAL_2;
wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2;
// remaining internal signals
wire [127 : 0] x__h236, x__h338, xy___1__h262;
wire [63 : 0] _theResult___fst__h506,
_theResult___fst__h509,
_theResult___fst__h560,
_theResult___fst__h563,
_theResult___snd_fst__h555;
wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34;
// action method put_args
assign CAN_FIRE_put_args = 1'd1 ;
assign WILL_FIRE_put_args = EN_put_args ;
// value method result_valid
assign result_valid = m_rg_state == 2'd2 ;
// value method result_value
assign result_value = m_rg_xy ;
// rule RL_m_compute
assign CAN_FIRE_RL_m_compute = m_rg_state == 2'd1 ;
assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ;
// inputs to muxes for submodule ports
assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h506 } ;
assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ;
assign MUX_m_rg_xy$write_1__VAL_2 = (m_rg_y == 64'd0) ? x__h236 : x__h338 ;
assign MUX_m_rg_y$write_1__VAL_1 =
(put_args_x_is_signed && put_args_y_is_signed) ?
_theResult___fst__h563 :
_theResult___snd_fst__h555 ;
assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ;
// register m_rg_isNeg
assign m_rg_isNeg$D_IN =
(put_args_x_is_signed && put_args_y_is_signed) ?
put_args_x[63] != put_args_y[63] :
IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34 ;
assign m_rg_isNeg$EN = EN_put_args ;
// register m_rg_signed
assign m_rg_signed$D_IN = 1'b0 ;
assign m_rg_signed$EN = 1'b0 ;
// register m_rg_state
assign m_rg_state$D_IN = EN_put_args ? 2'd1 : 2'd2 ;
assign m_rg_state$EN =
WILL_FIRE_RL_m_compute && m_rg_y == 64'd0 || EN_put_args ;
// register m_rg_x
assign m_rg_x$D_IN =
EN_put_args ?
MUX_m_rg_x$write_1__VAL_1 :
MUX_m_rg_x$write_1__VAL_2 ;
assign m_rg_x$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 64'd0 || EN_put_args ;
// register m_rg_xy
assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ;
assign m_rg_xy$EN =
WILL_FIRE_RL_m_compute && (m_rg_y == 64'd0 || m_rg_y[0]) ||
EN_put_args ;
// register m_rg_y
assign m_rg_y$D_IN =
EN_put_args ?
MUX_m_rg_y$write_1__VAL_1 :
MUX_m_rg_y$write_1__VAL_2 ;
assign m_rg_y$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 64'd0 || EN_put_args ;
// remaining internal signals
assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d34 =
put_args_x_is_signed ?
put_args_x[63] :
put_args_y_is_signed && put_args_y[63] ;
assign _theResult___fst__h506 =
put_args_x_is_signed ? _theResult___fst__h509 : put_args_x ;
assign _theResult___fst__h509 = put_args_x[63] ? -put_args_x : put_args_x ;
assign _theResult___fst__h560 =
put_args_y_is_signed ? _theResult___fst__h563 : put_args_y ;
assign _theResult___fst__h563 = put_args_y[63] ? -put_args_y : put_args_y ;
assign _theResult___snd_fst__h555 =
put_args_x_is_signed ? put_args_y : _theResult___fst__h560 ;
assign x__h236 = m_rg_isNeg ? xy___1__h262 : m_rg_xy ;
assign x__h338 = m_rg_xy + m_rg_x ;
assign xy___1__h262 = -m_rg_xy ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (m_rg_state$EN)
m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN;
end
if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN;
if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN;
if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN;
if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN;
if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_isNeg = 1'h0;
m_rg_signed = 1'h0;
m_rg_state = 2'h2;
m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_rg_y = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkIntMul_64
|
#include <bits/stdc++.h> using namespace std; int arr[3000000]; long long fadd[3000000]; long long carry[3000000]; long long tot[3000000]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; int nsize = 2 * n + 1; for (int i = 0; i < nsize; i++) fadd[i] = carry[i] = tot[i] = 0; for (int i = 0; i < n; i++) { int k = i + 1; int x = arr[i]; fadd[n - k + 1] += x - 1; carry[n - k + 1] -= 1; carry[n - k + x] += 2; carry[2 * n - k] -= 1; fadd[2 * n - k + 1] += x - n; } long long ctot = 0; long long ccarry = 0; for (int i = 0; i < nsize; i++) { ctot += fadd[i] + ccarry; ccarry += carry[i]; tot[i] = ctot; if (i >= n) tot[i % n] += tot[i]; } long long ans = 1e12; int bval = 0; for (int i = 0; i < n; i++) { if (tot[i] < ans) { ans = tot[i]; bval = i; } } cout << ans << << bval << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; const long long INF = 1e9 + 19; const int LOG = 11; int n, m; int a[N][N]; int b[N][N]; int pref[N][N]; short table[LOG][LOG][N][N]; int deg[N]; void read() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); } int getSum(int x1, int y1, int x2, int y2) { return pref[x2][y2] - pref[x1][y2] - pref[x2][y1] + pref[x1][y1]; } bool isSquare(int x1, int y1, int x2, int y2) { return (x2 - x1) * (y2 - y1) == getSum(x1, y1, x2, y2); } int getMax(int x1, int y1, int x2, int y2) { int szX = x2 - x1; int szY = y2 - y1; int dx = deg[szX]; int dy = deg[szY]; int tmp = max(max(table[dx][dy][x1][y1], table[dx][dy][x2 - (1 << dx)][y1]), max(table[dx][dy][x1][y2 - (1 << dy)], table[dx][dy][x2 - (1 << dx)][y2 - (1 << dy)])); return tmp; } void solve() { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) pref[i + 1][j + 1] = pref[i + 1][j] + pref[i][j + 1] - pref[i][j] + a[i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int l = 0; int r = min(n - i, m - j) + 1; while (r - l > 1) { int mid = (l + r) / 2; if (isSquare(i, j, i + mid, j + mid)) l = mid; else r = mid; } b[i][j] = l; } for (int i = 2; i <= max(n, m); i++) deg[i] = deg[i / 2] + 1; for (int dx = 0; dx <= 10; dx++) for (int dy = 0; dy <= 10; dy++) for (int i = 0; i + (1 << dx) <= n; i++) for (int j = 0; j + (1 << dy) <= m; j++) { if (dx == 0 && dy == 0) { table[0][0][i][j] = b[i][j]; } else if (dx != 0) { table[dx][dy][i][j] = max(table[dx - 1][dy][i][j], table[dx - 1][dy][i + (1 << (dx - 1))][j]); } else table[dx][dy][i][j] = max(table[dx][dy - 1][i][j], table[dx][dy - 1][i][j + (1 << (dy - 1))]); } int t; scanf( %d , &t); for (int it = 0; it < t; it++) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); x1--; y1--; int l = 0; int r = min(x2 - x1, y2 - y1) + 1; while (r - l > 1) { int mid = (l + r) / 2; if (getMax(x1, y1, x2 - mid + 1, y2 - mid + 1) >= mid) l = mid; else r = mid; } printf( %d n , l); } } void stress() {} int main() { if (1) { int k = 1; for (int tt = 0; tt < k; tt++) { read(); solve(); } } else { stress(); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; using pii = pair<int, int>; const int MOD = 1e9 + 7, N = 2e3 + 10; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<pair<long long, long long>> v(n); for (long long i = 0; i < n; i++) { long long x; cin >> x; long long cm = -1; long long salary; for (long long i = 0; i < x; i++) { cin >> salary; if (salary > cm) cm = salary; } v[i].first = cm; v[i].second = x; } sort(v.begin(), v.end()); long long sum = 0; for (long long i = 0; i < n; i++) { sum += (v[n - 1].first - v[i].first) * v[i].second; } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; struct bottle { int number; double len; double lento; double diflen; } a[100005], b[100005]; int cmp(bottle a, bottle b) { if (a.diflen > b.diflen) return 1; return 0; } int main() { double x1, y1, x2, y2, c1, c2, x, y; scanf( %lf %lf %lf %lf %lf %lf , &x1, &y1, &x2, &y2, &c1, &c2); int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lf %lf , &x, &y); a[i].len = sqrt(pow(x1 - x, 2) + pow(y1 - y, 2)); b[i].len = sqrt(pow(x2 - x, 2) + pow(y2 - y, 2)); a[i].lento = sqrt(pow(x - c1, 2) + pow(y - c2, 2)); b[i].lento = sqrt(pow(x - c1, 2) + pow(y - c2, 2)); a[i].diflen = a[i].lento - a[i].len; b[i].diflen = b[i].lento - b[i].len; a[i].number = i; b[i].number = i; } sort(a, a + n, cmp); sort(b, b + n, cmp); double length = a[0].len + b[0].len + a[0].lento + b[0].lento; int mark1 = a[0].number, mark2 = b[0].number; if (a[0].diflen < 0 || b[0].diflen < 0) { if (a[0].diflen > b[0].diflen) { mark2 = -1; length = a[0].len + a[0].lento; } else { mark1 = -1; length = b[0].len + b[0].lento; } } if (a[0].number == b[0].number && mark1 != -1 && mark2 != -1) { if (a[1].diflen < 0 || b[1].diflen < 0) { if (a[1].diflen < 0 && b[1].diflen < 0) { if (a[0].diflen > b[0].diflen) { mark2 = -1; mark1 = a[0].number; length = a[0].len + a[0].lento; } else { mark1 = -1; mark2 = b[0].number; length = b[0].len + b[0].lento; } } else if (a[1].diflen < 0) { if ((a[0].diflen + b[1].diflen) > b[0].diflen) { mark1 = a[0].number; mark2 = b[1].number; length = a[0].len + b[1].len + a[0].lento + b[1].lento; } else { mark1 = -1; mark2 = b[0].number; length = b[0].len + b[0].lento; } } else if (b[1].diflen < 0) { if ((b[0].diflen + a[1].diflen) > a[0].diflen) { mark1 = a[1].number; mark2 = b[0].number; length = a[1].len + b[0].len + a[1].lento + b[0].lento; } else { mark1 = a[0].number; mark2 = -1; length = a[0].len + a[0].lento; } } } else if ((a[0].diflen + b[1].diflen) > (a[1].diflen + b[0].diflen)) { length = a[0].len + b[1].len + a[0].lento + b[1].lento; mark1 = a[0].number; mark2 = b[1].number; } else { length = a[1].len + b[0].len + a[1].lento + b[0].lento; mark1 = a[1].number; mark2 = b[0].number; } } for (int i = 0; i < n; i++) { if (a[i].number != mark1 && a[i].number != mark2) { length += a[i].lento * 2; } } printf( %.12lf n , length); }
|
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
//******************************************************************************
// Filename : ce_generator.v
// Description : This module generates CE signal
// in 3 different patterns,
// (1) Always asserted
// (2) Random assertion
// (3) Periodic assertion based on input period
//------------------------------------------------------------------------------
// Ver Date Modified by Modification
//------------------------------------------------------------------------------
// 1.0 20/05/11 Reinald Cruz Initial release.
// 1.1 24/05/11 Reinald Cruz Changed module interface names to *_in/*_out
// 1.2 04/11/11 Reinald Cruz Changed module interface & task input
//------------------------------------------------------------------------------
`timescale 1ns/1ns
//--------------------------------------------------
//-- Clock Enable Generator
//--------------------------------------------------
module ce_gen
(
input clk_in,
input sclr_in,
output reg ce_out
);
integer rseed = 0;
integer ce_period = 10;
integer ce_period_cnt = 0;
reg enable = 0;
reg [1:0] ce_pattern = 2'b00;
//----------------------------------------------------
// CE PATTERN :
// 2'b00 : CE is always asserted
// 2'b01 : CE is asserted periodically every ce_period
// 2'b10 : CE is asserted randomly
// 2'b11 : FORBIDDEN
//----------------------------------------------------
task start_random;
input [31:0] seed;
begin
rseed <= seed;
ce_pattern <= 2'b10;
enable <= 1;
$display("@%10t : CE Generator : Enabled (Random)", $time);
end
endtask
task start_periodic;
input [31:0] input_period;
begin
ce_period <= input_period;
ce_period_cnt <= 0;
ce_pattern <= 2'b01;
enable <= 1;
$display("@%10t : CE Generator : Enabled (Periodic) [%dns]", $time, input_period);
end
endtask
task start;
begin
ce_pattern <= 2'b00;
enable <= 1;
$display("@%10t : CE Generator : Enabled (always asserted)", $time);
end
endtask
task stop;
begin
enable <= 0;
$display("@%10t : CE Generator : Disabled.", $time);
end
endtask
// RESET DETECTION
always @ (posedge sclr_in)
begin
ce_out = 0;
ce_period_cnt = 0;
enable = 0;
end
// CE GENERATION
always @ (posedge clk_in)
begin
if (enable)
begin
case (ce_pattern)
2'b00 : begin
ce_out = 1;
end
2'b01 : begin
if (ce_period_cnt % (ce_period/2) == 0)
begin
ce_out = ~ce_out;
ce_period_cnt = 0;
end
ce_period_cnt = ce_period_cnt + 1;
end
2'b10 : begin
ce_out = {$random(rseed)}%2;
end
default : begin
$display("CE Generator : ERROR! ce_pattern[1:0] = 2'b11 IS NOT A VALID SETTING.");
$finish;
end
endcase
end
else
begin
ce_period_cnt <= 0;
ce_out <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 5; int parent[MAX]; int depth[MAX]; int get(int a) { while (a != parent[a]) a = parent[a]; return a; } void join(int a, int b) { a = get(a); b = get(b); if (a == b) return; if (depth[a] > depth[b]) swap(a, b); parent[a] = b; depth[b] += depth[a]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, q, a, b, w; cin >> n >> q; for (int i = 1; i <= n + 1; i++) { parent[i] = i; depth[i] = 1; } vector<pair<int, pair<int, int>>> vp; vector<long long> sol(MAX); long long cnt = 0; for (int i = 0; i < n - 1; i++) { cin >> a >> b >> w; vp.push_back({w, {a, b}}); } sort(vp.begin(), vp.end()); reverse(vp.begin(), vp.end()); for (int j = 1; j < MAX; j++) { while (!vp.empty() && vp.back().first <= j) { a = vp.back().second.first; b = vp.back().second.second; vp.pop_back(); a = get(a); b = get(b); if (a == b) continue; cnt -= 1ll * depth[a] * (depth[a] - 1) / 2; cnt -= 1ll * depth[b] * (depth[b] - 1) / 2; join(a, b); a = get(a); cnt += 1ll * depth[a] * (depth[a] - 1) / 2; } sol[j] = cnt; } while (q--) { cin >> w; cout << sol[w] << ; } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, a[600000], L, R, r, t, l, f; long long s; bool ok(long long x) { long long r = 0; for (long long i = 0; i < n; i++) if (a[i] > x) r += (a[i] - x); if (r <= t) return 1; return 0; } bool ok1(long long x) { long long r = 0; for (long long i = 0; i < n; i++) if (a[i] < x) r += (x - a[i]); if (r <= t) return 1; return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> t; L = 2e9; for (long long i = 0; i < n; i++) { cin >> a[i]; s += a[i]; L = min(L, a[i]); R = max(R, a[i]); } long long d1 = R, d2 = L; l = L; r = R; while (r - l > 10) { long long mid = (r + l) / 2; if (ok(mid)) r = mid; else l = mid + 1; } for (long long i = l; i <= r; i++) if (ok(i)) d1 = min(d1, i); l = L; r = R; while (r - l > 10) { long long mid = (r + l) / 2; if (ok1(mid)) l = mid; else r = mid - 1; } for (long long i = l; i <= r; i++) if (ok1(i)) d2 = max(d2, i); if (s % n == 0) f = 0; else f = 1; cout << max(f, d1 - d2); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
/********************************************************************
* TEST BENCH FOR PROTECTION CELLS *
********************************************************************
* Laboratory : Robotics and Embedded System Technology
* Engineer : Hanjara Cahya Adhyatma
* Create Date : 19/04/2017
* Project Name : FINAL PROJECT
* Target Devices: TEST BENCH SIM PROTECTION AND FPGA
* Tool versions : VERILOG 2001 RUN ON ICARUS 10
* Description : ??????????????
* Dependencies : ???
* Revision : ???
* Additional Comments: ???
********************************************************************
* INCLUDE MODULES *
*******************************************************************/
//`include "../module/protection.v"
/********************************************************************
* IO DEFINITIONS *
*******************************************************************/
module bridge_tb;
reg RST, CLK, ENA;
reg [7:0]OPT;
reg [7:0]RGA;
reg [7:0]RGB;
wire [7:0]RGZ;
reg [1:0]KEY;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvars(0, jemb);
$monitor($time, " REG A = %b REG Z = %b", RGA, RGZ);
end
/********************************************************************
* CLOCKING *
*******************************************************************/
initial
begin
CLK = 1'b1;
forever #5 CLK = ~CLK;
end
/********************************************************************
* RESET *
*******************************************************************/
initial
begin
RST = 1'b1;
#5 RST = 1'b0;
end
/********************************************************************
* DATAS INJECTION *
*******************************************************************/
initial
begin
RGA = 8'b00000000;
#10 RGA = 8'b00000111;
#10 RGA = 8'b00000101;
#10 RGA = 8'b00000110;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000011;
#10 RGA = 8'b00000100;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000000;
#10 RGA = 8'b00000111;
#10 RGA = 8'b00000100;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000001;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000101;
#10 RGA = 8'b00000011;
#10 RGA = 8'b00000100;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000111;
#10 RGA = 8'b00000011;
#10 RGA = 8'b00000000;
$finish;
end
/********************************************************************
* OPCODE *
*******************************************************************/
initial
begin
OPT = 8'b00000001;
#5 OPT = 8'b00000000;
end
initial
begin
KEY = 1'b1;
#5 KEY = 1'b1;
end
initial
begin
RGB = 1;
end
/********************************************************************
* MODULE IN TEST *
*******************************************************************/
bridge jemb(RGA, RGB, RGZ);
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This module checks that parameter bit select works
* in parameter assignment expressions.
*/
module main;
parameter value = 2'b10;
parameter x = 0;
parameter y = 1;
parameter pa = value[0];
parameter pb = value[1];
parameter px = value[x];
parameter py = value[y];
initial begin
if (pa !== value[0]) begin
$display("FAILED -- pa == %b", pa);
$finish;
end
if (pa !== 0) begin
$display("FAILED -- pa == %b", pa);
$finish;
end
if (pb !== value[1]) begin
$display("FAILED -- pb == %b", pb);
$finish;
end
if (pb !== 1) begin
$display("FAILED -- pb == %b", pb);
$finish;
end
if (px !== value[0]) begin
$display("FAILED -- px == %b", px);
$finish;
end
if (px !== 0) begin
$display("FAILED -- px == %b", px);
$finish;
end
if (py !== value[1]) begin
$display("FAILED -- py == %b", py);
$finish;
end
if (py !== 1) begin
$display("FAILED -- py == %b", py);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> #pragma GCC optimize( -O3 ) using namespace std; void _main(); int main() { cin.tie(0); ios::sync_with_stdio(false); _main(); } const int inf = INT_MAX / 2; const long long infl = 1LL << 60; template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (b < a) { a = b; return 1; } return 0; } string E; int P, M; struct Node { Node *left, *right; int value, id, cnt; }; int i = 0, idx = 0; Node *parse() { Node *n = new Node; n->id = idx; idx++; if (E[i] == ( ) { i++; n->left = parse(); i++; n->right = parse(); i++; n->value = -1; n->cnt = n->left->cnt + n->right->cnt + 1; } else { n->value = E[i] - 0 ; i++; n->cnt = 0; } return n; } int vis[4101][105]; pair<int, int> memo[4101][105]; pair<int, int> f(Node *n, int p) { int m = n->cnt - p; if (m < 0) return {inf, inf}; int id = n->id; if (vis[id][p]) return memo[id][p]; if (n->cnt == 0) return memo[id][p] = {n->value, n->value}; int mi = inf, ma = -inf; for (int pls = 0; pls < p; pls++) { auto le = f(n->left, pls); if (le.first == inf) continue; auto ri = f(n->right, p - pls - 1); if (ri.first == inf) continue; vector<int> a = {le.first, le.second}; vector<int> b = {ri.first, ri.second}; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { int res = a[i] + b[j]; chmin(mi, res); chmax(ma, res); } } for (int pls = 0; pls < p + 1; pls++) { auto le = f(n->left, pls); if (le.first == inf) continue; auto ri = f(n->right, p - pls); if (ri.first == inf) continue; vector<int> a = {le.first, le.second}; vector<int> b = {ri.first, ri.second}; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { int res = a[i] - b[j]; chmin(mi, res); chmax(ma, res); } } assert(mi != inf); vis[id][p] = 1; return memo[id][p] = {mi, ma}; } pair<int, int> g(Node *n, int p) { int m = n->cnt - p; if (m < 0) return {inf, inf}; int id = n->id; if (vis[id][p]) return memo[id][p]; if (n->cnt == 0) return memo[id][p] = {n->value, n->value}; int mi = inf, ma = -inf; for (int pls = 0; pls < p; pls++) { auto le = g(n->left, pls); if (le.first == inf) continue; auto ri = g(n->right, p - pls - 1); if (ri.first == inf) continue; vector<int> a = {le.first, le.second}; vector<int> b = {ri.first, ri.second}; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { int res = a[i] - b[j]; chmin(mi, res); chmax(ma, res); } } for (int pls = 0; pls < p + 1; pls++) { auto le = g(n->left, pls); if (le.first == inf) continue; auto ri = g(n->right, p - pls); if (ri.first == inf) continue; vector<int> a = {le.first, le.second}; vector<int> b = {ri.first, ri.second}; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { int res = a[i] + b[j]; chmin(mi, res); chmax(ma, res); } } assert(mi != inf); vis[id][p] = 1; return memo[id][p] = {mi, ma}; } void _main() { cin >> E >> P >> M; E += = ; Node *root = parse(); if (P <= M) { auto res = f(root, P); int ans = res.second; cout << ans << endl; } else { auto res = g(root, M); int ans = res.second; cout << ans << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> long int temp, i, j, k, T; long int ABS(int test) { if (test < 0) return test * -1; else return test; } int x8[] = {1, 1, 0, -1, -1, -1, 0, 1}; int y8[] = {0, 1, 1, 1, 0, -1, -1, -1}; int x4[] = {1, 0, -1, 0}; int y4[] = {0, 1, 0, -1}; long int arr[1000000]; long int buff[1000000]; long int memo[1000000]; using namespace std; int main() { char a[100001]; char b[100001]; int jawaban = 0, panjang, tujuh1 = 0, tujuh2 = 0, empat1 = 0, empat2 = 0; memset(memo, 0, sizeof memo); cin >> a; cin >> b; panjang = strlen(a); for (i = 0; i < panjang; i++) { if (a[i] == 7 ) tujuh1++; if (a[i] == 4 ) empat1++; if (b[i] == 7 ) tujuh2++; if (b[i] == 4 ) empat2++; } for (i = 0; i < panjang; i++) { if (a[i] == b[i]) { if (a[i] == 7 ) { tujuh1--; tujuh2--; } if (a[i] == 4 ) { empat1--; empat2--; } } } jawaban = max(tujuh1, tujuh2); cout << jawaban << endl; { fflush(stdin); getchar(); }; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 500 * 1000 + 10; vector<int> adj[MAX_N], vec[MAX_N]; int n, m, cnt; queue<int> q; set<int> s; void readInput() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--, v--; adj[u].push_back(v); adj[v].push_back(u); } for (int i = 0; i < n; i++) sort(adj[i].begin(), adj[i].end()), s.insert(i); } void solve() { while (!s.empty()) { q.push(*s.begin()), s.erase(s.begin()); while (!q.empty()) { int u = q.front(); q.pop(), vec[cnt].push_back(u); int cur = 0; vector<int> tmp; for (auto v : s) { while (cur < adj[u].size() && adj[u][cur] < v) cur++; if (cur == adj[u].size() || adj[u][cur] != v) tmp.push_back(v); } for (auto v : tmp) q.push(v), s.erase(v); } cnt++; } } void writeOutput() { cout << cnt << endl; for (int i = 0; i < cnt; i++) { cout << vec[i].size() << ; for (auto u : vec[i]) cout << u + 1 << ; cout << endl; } } int main() { ios_base ::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); readInput(), solve(), writeOutput(); return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_data_pipeline
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The TX Data pipeline module takes arbitrarily 32-bit aligned data
// from the WR_TX_DATA interface and shifts the data so that it is 0-bit
// aligned. This data is presented on a set of N fifos, where N =
// (C_DATA_WIDTH/32). Each fifo provides it's own VALID signal and is
// controlled by a READY signal. Each fifo also provides an independent DATA bus
// and additional END_FLAG signal which inidicates that the dword provided in this
// fifo is the last dword in the current payload. The START_FLAG signal indicates
// that the dword at index N = 0 is the start of a new packet.
//
// The TX Data Pipeline is built from two modules: tx_data_shift.v and
// tx_data_fifo.v. See these modules for more information.
//
// Author: Dustin Richmond (@darichmond)
//----------------------------------------------------------------------------
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_data_pipeline
#(
parameter C_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD = 256,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: WR TX DATA
input WR_TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
input WR_TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
output WR_TX_DATA_READY,
// Interface: TX DATA FIFOS
input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID
);
wire wRdTxDataValid;
wire wRdTxDataReady;
wire wRdTxDataStartFlag;
wire [C_DATA_WIDTH-1:0] wRdTxData;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
tx_data_shift
#(
.C_PIPELINE_OUTPUT (0),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_VENDOR (C_VENDOR))
tx_shift_inst
(
// Outputs
.WR_TX_DATA_READY (WR_TX_DATA_READY),
.RD_TX_DATA (wRdTxData),
.RD_TX_DATA_VALID (wRdTxDataValid),
.RD_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.RD_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.RD_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
// Inputs
.WR_TX_DATA (WR_TX_DATA[C_DATA_WIDTH-1:0]),
.WR_TX_DATA_VALID (WR_TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (WR_TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (WR_TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_READY (wRdTxDataReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Data Fifo
tx_data_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_PIPELINE_INPUT (1),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD (C_MAX_PAYLOAD),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH))
txdf_inst
(
// Outputs
.WR_TX_DATA_READY (wRdTxDataReady),
.RD_TX_DATA (RD_TX_DATA[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_START_FLAG (RD_TX_DATA_START_FLAG),
.RD_TX_DATA_WORD_VALID (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_END_FLAGS (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]),
// Inputs
.WR_TX_DATA (wRdTxData),
.WR_TX_DATA_VALID (wRdTxDataValid),
.WR_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.WR_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.WR_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
.RD_TX_DATA_WORD_READY (RD_TX_DATA_WORD_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
// soc_design_niosII_core.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_niosII_core (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire [3:0] d_burstcount, // .burstcount
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [26:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
output wire [3:0] i_burstcount, // .burstcount
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
soc_design_niosII_core_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_burstcount (d_burstcount), // .burstcount
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_burstcount (i_burstcount), // .burstcount
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long n, m, i, j, mn, mx; scanf( %ld %ld , &n, &m); long a[n][m]; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { scanf( %ld , &a[i][j]); } } mx = 0; for (i = 0; i < n; i++) { mn = LONG_MAX; for (j = 0; j < m; j++) { mn = min(a[i][j], mn); } mx = max(mn, mx); } printf( %ld , mx); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:32:43 09/11/2015
// Design Name: WB_intercon
// Module Name: Z:/share/ISE/CPUFly/tests/WB_intercon_test.v
// Project Name: CPUFly
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: WB_intercon
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module WB_intercon_test;
// Inputs
reg master_STB;
reg [31:0] master_DAT_I;
reg master_WE;
reg [31:0] master_ADDR;
reg [15:0] slave_ACK;
reg [511:0] slave_DAT_I;
// Outputs
wire [31:0] master_DAT_O;
wire master_ACK;
wire [15:0] slave_STB;
wire slave_WE;
wire [31:0] slave_DAT_O;
wire [31:0] slave_ADDR;
// Instantiate the Unit Under Test (UUT)
WB_intercon uut (
.master_STB(master_STB),
.master_DAT_I(master_DAT_I),
.master_DAT_O(master_DAT_O),
.master_ACK(master_ACK),
.master_WE(master_WE),
.master_ADDR(master_ADDR),
.slave_STB(slave_STB),
.slave_ACK(slave_ACK),
.slave_WE(slave_WE),
.slave_DAT_I(slave_DAT_I),
.slave_DAT_O(slave_DAT_O),
.slave_ADDR(slave_ADDR)
);
initial begin
// Initialize Inputs
master_STB = 0;
master_DAT_I = 0;
master_WE = 0;
master_ADDR = 0;
slave_ACK = 0;
slave_DAT_I = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
master_STB = 1;
master_DAT_I = 16'h2333;
master_WE = 1;
master_ADDR = 32'h10000000;
slave_ACK = 1;
slave_DAT_I = 32'h00002333;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long modex(long long a, long long p, long long m) { if (!p) return 1; if (p & 1) return a * modex(a, p - 1, m) % m; long long v = modex(a, p >> 1, m); return v * v % m; } namespace fft { struct cpx { double r, i; cpx(double r = 0, double i = 0) : r(r), i(i) {} cpx operator+(cpx b) { return {r + b.r, i + b.i}; } cpx operator-(cpx b) { return {r - b.r, i - b.i}; } cpx operator*(cpx b) { return {r * b.r - i * b.i, r * b.i + i * b.r}; } cpx operator/(double b) { return {r / b, i / b}; } inline cpx conj() { return {r, -i}; } }; const double PI = acos(-1); vector<int> rev(1, 0); vector<cpx> roots; int base = 0; void precompute(int nbase) { if (nbase <= base) return; rev.resize(1 << nbase); for (int i = 0; i < (1 << nbase); ++i) { rev[i] = rev[i >> 1] >> 1 | ((i & 1) << nbase - 1); } roots.resize(1 << nbase); for (; base < nbase; ++base) { int len = 1 << base; double angle = 2 * PI / (1 << (base + 1)); for (int i = 0; i < len; ++i) { double cur = angle * i; roots[len + i] = cpx(cos(cur), sin(cur)); } } } void fft(vector<cpx>& a, int n = -1) { if (n == -1) n = a.size(); assert((n & (n - 1)) == 0); int zeros = __builtin_ctz(n); precompute(zeros); int shift = base - zeros; for (int i = 0; i < n; ++i) { if (i < (rev[i] >> shift)) swap(a[i], a[rev[i] >> shift]); } for (int len = 1; len < n; len <<= 1) for (int i = 0; i < n; i += 2 * len) for (int j = 0; j < len; ++j) { cpx u = a[i + j], v = a[i + j + len] * roots[len + j]; a[i + j] = u + v; a[i + j + len] = u - v; } } vector<cpx> fa, fb; vector<long long> multiply(vector<int> a, vector<int> b) { if (a.empty() || b.empty()) return {}; int sz = a.size() + b.size() - 1; int n = sz == 1 ? 1 : 1 << (32 - __builtin_clz(sz - 1)); if (n > fa.size()) fa.resize(n); for (int i = 0; i < n; ++i) { int x = i < a.size() ? a[i] : 0; int y = i < b.size() ? b[i] : 0; fa[i] = cpx(x, y); } fft(fa, n); cpx r(0, -0.5 / n); for (int i = 0; i <= (n >> 1); ++i) { int j = (n - i) & (n - 1); cpx x = (fa[i] + fa[j].conj()) / 2; cpx y = (fa[i] - fa[j].conj()) * r; fa[i] = x * y; if (i != j) fa[j] = fa[i].conj(); } fft(fa, n); reverse(fa.begin() + 1, fa.end()); vector<long long> res(sz); for (int i = 0; i < sz; ++i) { res[i] = llround(fa[i].r); } return res; } vector<int> multiply(const vector<int>& a, const vector<int>& b, int m) { if (a.empty() || b.empty()) return {}; int eq = (a == b); int sz = a.size() + b.size() - 1; int n = sz == 1 ? 1 : 1 << (32 - __builtin_clz(sz - 1)); if (n > fa.size()) fa.resize(n); for (int i = 0; i < a.size(); ++i) { fa[i] = cpx(a[i] & ((1 << 15) - 1), a[i] >> 15); } fill(fa.begin() + a.size(), fa.begin() + n, cpx(0, 0)); fft(fa, n); if (n > fb.size()) fb.resize(n); if (eq) { copy(fa.begin(), fa.begin() + n, fb.begin()); } else { for (int i = 0; i < b.size(); ++i) { fb[i] = cpx(b[i] & ((1 << 15) - 1), b[i] >> 15); } fill(fb.begin() + b.size(), fb.begin() + n, cpx(0, 0)); } fft(fb, n); double ratio = 0.5 / n; cpx r2(0, -0.5); cpx r3(ratio, 0); cpx r4(0, -ratio); cpx r5(0, 1); for (int i = 0; i <= (n >> 1); ++i) { int j = (n - i) & (n - 1); cpx a1 = (fa[i] + fa[j].conj()) / 2; cpx a2 = (fa[i] - fa[j].conj()) * r2; cpx b1 = (fb[i] + fb[j].conj()) * r3; cpx b2 = (fb[i] - fb[j].conj()) * r4; cpx x = a1 * b1; cpx y = a2 * b2; fa[i] = x + y * r5; fb[i] = a1 * b2 + a2 * b1; if (i != j) { fa[j] = x.conj() + y.conj() * r5; fb[j] = fb[i].conj(); } } fft(fa, n); fft(fb, n); reverse(fa.begin() + 1, fa.end()); reverse(fb.begin() + 1, fb.end()); vector<int> res(sz); for (int i = 0; i < sz; ++i) { long long aa = llround(fa[i].r); long long bb = llround(fb[i].r); long long cc = llround(fa[i].i); assert(llround(fb[i].i) == 0); res[i] = (aa + ((bb % m) << 15) + ((cc % m) << 30)) % m; } return res; } }; // namespace fft namespace polynomial { int MOD = 998244353; template <typename T> vector<T> subtract(vector<T> a, const vector<T>& b) { if (a.size() < b.size()) { a.resize(b.size()); } for (int i = 0; i < b.size(); ++i) { a[i] -= b[i]; if (a[i] < 0) a[i] += MOD; } return a; } template <typename T> vector<T> inverse(const vector<T>& a) { assert(!a.empty() && a[0] != 0); int n = a.size(); vector<T> b = {modex(a[0], MOD - 2, MOD)}; for (int m = 2; b.size() < n; m <<= 1) { vector<T> aCut(a.begin(), a.begin() + min(a.size(), m)); auto x = fft::multiply(aCut, fft::multiply(b, b, MOD), MOD); b.resize(m); for (int i = 0; i < m; ++i) { b[i] += b[i] - x[i]; if (b[i] >= MOD) b[i] -= MOD; if (b[i] < 0) b[i] += MOD; } } b.resize(n); return b; } template <typename T> vector<T> divide(vector<T> a, vector<T> b) { assert(!b.empty() && b.back() != 0); int n = a.size(); int m = b.size(); if (n < m) return {}; reverse(a.begin(), a.end()); reverse(b.begin(), b.end()); b.resize(n - m + 1); a = multiply(a, inverse(b), MOD); a.erase(a.begin() + n - m + 1, a.end()); reverse(a.begin(), a.end()); return a; } template <typename T> vector<T> remainder(const vector<T>& a, const vector<T>& b) { return subtract(a, fft::multiply(b, divide(a, b), MOD)); } template <typename T> vector<T> integral(const vector<T>& a) { vector<T> ret(a.size() + 1); for (int i = 1; i < ret.size(); ++i) { ret[i] = a[i] * modex(i, MOD - 2, MOD) % MOD; } return ret; } template <typename T> vector<T> derivative(const vector<T>& a) { if (a.empty()) return a; vector<T> ret(a.size() - 1); for (int i = 0; i + 1 < a.size(); ++i) ret[i] = (long long)a[i + 1] * (i + 1) % MOD; return ret; } template <typename T> vector<T> logarithm(const vector<T>& a) { assert(!a.empty() && a[0] == 1); auto ret = integral(fft::multiply(derivative(a), inverse(a), MOD)); ret.resize(a.size()); return ret; } template <typename T> vector<T> exponent(const vector<T>& a) { assert(!a.empty() && a[0] == 0); int n = a.size(); vector<T> b = {1}; for (int m = 2; b.size() < n; m <<= 1) { vector<T> x(a.begin(), a.begin() + min(a.size(), m)); ++x[0]; if (x[0] >= MOD) x[0] -= MOD; auto oldB = b; b.resize(m); b = fft::multiply(oldB, subtract(x, logarithm(b)), MOD); b.resize(m); } b.resize(n); return b; } template <typename T> vector<T> multipoint(const vector<T>& a, vector<T> xs) { int n = xs.size(); vector<vector<T>> prods(2 * n - 1); function<void(int, int, int)> getProds = [&](int sn, int s, int e) { if (s == e) { prods[sn] = {(MOD - xs[s]) % MOD, 1}; return; } int m = (s + e) >> 1, lsn = sn + 1, rsn = sn + ((m - s + 1) << 1); getProds(lsn, s, m); getProds(rsn, m + 1, e); prods[sn] = fft::multiply(prods[lsn], prods[rsn]); }; getProds(0, 0, n - 1); function<void(int, int, int, vector<T>)> calc = [&](int sn, int s, int e, vector<T> f) { if (s == e) { xs[s] = f[0]; return; } int m = (s + e) >> 1, lsn = sn + 1, rsn = sn + ((m - s + 1) << 1); calc(lsn, s, m, remainder(f, prods[lsn])); calc(rsn, m + 1, e, remainder(f, prods[rsn])); }; calc(0, 0, n - 1, a); return xs; } template <typename T> vector<T> chirpz(vector<T> a, T g, int n) { int d = a.size(); int phi = MOD - 1; vector<long long> pw(phi + 1, 1); for (int i = 1; i <= phi; ++i) pw[i] = pw[i - 1] * g % MOD; auto chirpzEven = [&](const vector<T>& b, int m) { vector<T> u(d), v(m + d - 1); for (int i = 0; i < d; ++i) { u[i] = b[i] * pw[(long long)i * i % phi] % MOD; } for (int i = -(d - 1); i < m; ++i) { v[d - 1 + i] = pw[phi - (long long)i * i % phi]; } auto z = fft::multiply(u, v, MOD); vector<T> ret(m); for (int i = 0; i < m; ++i) { ret[i] = pw[(long long)i * i % phi] * z[d - 1 + i] % MOD; } return ret; }; auto even = chirpzEven(a, (n + 1) >> 1); for (int i = 0; i < d; ++i) a[i] = a[i] * pw[i] % MOD; auto odd = chirpzEven(a, n >> 1); vector<T> ret(n); for (int i = 0; i < n; ++i) { ret[i] = (i & 1) ? odd[i >> 1] : even[i >> 1]; } return ret; } }; // namespace polynomial using namespace polynomial; int primitiveRoot(int n) { vector<int> fact; int phi = n - 1, x = phi; for (int i = 2; i * i <= x; ++i) if (x % i == 0) { fact.push_back(i); while (x % i == 0) x /= i; } if (x > 1) fact.push_back(x); for (int res = 1; res <= n; ++res) { bool ok = true; for (int i = 0; i < fact.size() && ok; ++i) ok &= modex(res, phi / fact[i], n) != 1; if (ok) return res; } return -1; } char str[100005]; int main() { int n, m; scanf( %d%d , &n, &m); vector<int> poly(n); scanf( %s , str); for (int i = 0; i < n; ++i) { poly[i] += str[i] - a ; } scanf( %s , str); for (int i = 0; i < n; ++i) { poly[i] -= str[i] - a ; } const int MAXN = 300005; bitset<MAXN> notp; notp[1] = notp[0] = 1; for (int i = 2; i < MAXN; ++i) if (!notp[i]) for (int j = i + i; j < MAXN; j += i) notp[j] = 1; mt19937 rng(42); for (;;) { int p = m + n + rng() % 100000; if (notp[p]) continue; MOD = p; int g = primitiveRoot(p); auto z = poly; for (int i = 0; i < z.size(); ++i) z[i] = (z[i] % MOD + MOD) % MOD; auto res = chirpz(z, g, p - 1); long long pw = 1; for (int i = 0; i < p - 1; ++i) { if (1 < pw && pw < p - 1 && res[i] == 0) { long long z = 0; long long r = pw; for (int i = n - 1; i >= 0; --i) { z = (z * r + poly[i]) % MOD; } cerr << z << = << z << endl; printf( %d %lld n , MOD, r); return 0; } pw = pw * g % MOD; } } }
|
#include <bits/stdc++.h> const int N = 4e6 + 10; int idx[N], rank[N]; struct Point { int x, y; } A[N], Line[N]; inline double slope(Point a) { return double(A[a.x].y - A[a.y].y) / double(A[a.x].x - A[a.y].x); } inline long long area(Point A, Point B, Point C) { return fabs(1LL * (A.x - C.x) * (B.y - C.y) - 1LL * (B.x - C.x) * (A.y - C.y)); } inline int find1(int l, int r, int u, int v, long long s) { int res = -1; while (l <= r) { int mid = (l + r) >> 1; if (area(A[idx[mid]], A[u], A[v]) >= s) l = mid + 1, res = mid; else r = mid - 1; } return res != -1 && area(A[idx[res]], A[u], A[v]) == s ? res : -1; } inline int find2(int l, int r, int u, int v, long long s) { int res = -1; while (l <= r) { int mid = (l + r) >> 1; if (area(A[idx[mid]], A[u], A[v]) <= s) l = mid + 1, res = mid; else r = mid - 1; } return res != -1 && area(A[idx[res]], A[u], A[v]) == s ? res : -1; } inline int solve(int u, int v, int n, long long s) { if (rank[u] > rank[v]) std::swap(u, v); int res1 = find1(1, rank[u] - 1, u, v, s); if (res1 != -1) return res1; int res2 = find2(rank[v] + 1, n, u, v, s); if (res2 != -1) return res2; std::swap(rank[u], rank[v]), std::swap(idx[rank[u]], idx[rank[v]]); return 0; } int main() { int n, tot = 0; long long s; std::cin >> n >> s; s <<= 1; for (int i = 1; i <= n; ++i) std::cin >> A[i].x >> A[i].y, idx[i] = i, rank[i] = i; std::sort(A + 1, A + n + 1, [&](const Point &a, const Point &b) { return a.x < b.x || a.x == b.x && a.y < b.y; }); for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) Line[++tot] = Point{i, j}; std::sort(Line + 1, Line + tot + 1, [&](const Point &a, const Point &b) { int x1 = A[a.y].x - A[a.x].x, y1 = A[a.y].y - A[a.x].y; int x2 = A[b.y].x - A[b.x].x, y2 = A[b.y].y - A[b.x].y; return 1LL * x1 * y2 - 1LL * x2 * y1 > 0; }); for (int i = 1; i <= tot; ++i) { int res = solve(Line[i].x, Line[i].y, n, s); if (res) return printf( Yes n%d %d n%d %d n%d %d n , (A[Line[i].x]).x, (A[Line[i].x]).y, (A[Line[i].y]).x, (A[Line[i].y]).y, (A[idx[res]]).x, (A[idx[res]]).y), 0; } return puts( No ), 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_8_V
`define SKY130_FD_SC_HDLL__AND2_8_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_8 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_8 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_8_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
module processing_system7_bfm_v2_0_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXn = 2e5 + 3; const long long INF = 1e15 + 1; long long t[4 * MAXn], sum[MAXn], lazy[4 * MAXn]; int id[MAXn]; void Build(int v, int l, int r) { lazy[v] = 0; if (l == r) { t[v] = sum[l]; return; } int mid = (r + l) / 2; Build(v * 2, l, mid); Build(v * 2 + 1, mid + 1, r); t[v] = min(t[v * 2], t[v * 2 + 1]); return; } void Down(int v) { t[v * 2] += lazy[v]; lazy[v * 2] += lazy[v]; t[v * 2 + 1] += lazy[v]; lazy[v * 2 + 1] += lazy[v]; lazy[v] = 0; } void Update(int v, int l, int r, int L, int R, long long x) { if (r < L || R < l) return; if (L <= l && r <= R) { lazy[v] += x; t[v] += x; return; } int mid = (r + l) / 2; Down(v); Update(v * 2, l, mid, L, R, x); Update(v * 2 + 1, mid + 1, r, L, R, x); t[v] = min(t[v * 2], t[v * 2 + 1]); return; } long long get(int v, int l, int r, int L, int R) { if (r < L || R < l) return INF; if (L <= l && R >= r) return t[v]; int mid = (l + r) / 2; Down(v); return min(get(v * 2, l, mid, L, R), get(v * 2 + 1, mid + 1, r, L, R)); } int main() { int n; cin >> n; int val; for (int i = 1; i <= n; i++) { cin >> val; id[val] = i; } sum[0] = 0; long long p; for (int i = 1; i <= n; i++) { cin >> p; sum[i] = sum[i - 1] + p; } Build(1, 1, n - 1); long long ans = get(1, 1, n - 1, 1, n - 1); for (int val = 1; val <= n; val++) { if (id[val] > 1) Update(1, 1, n - 1, 1, id[val] - 1, sum[id[val]] - sum[id[val] - 1]); if (id[val] < n) { Update(1, 1, n - 1, id[val], n - 1, -sum[id[val]] + sum[id[val] - 1]); ans = min(ans, get(1, 1, n - 1, id[val], n - 1)); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; long long fac[1000006]; inline long long exp(long long x, long long n) { long long r = 1; x = x; while (n) { if (n % 2) r = (r * x) % 10000000000000007; x = (x * x) % 10000000000000007; n = n / 2; } return r; } inline long long mmi(long long a) { return exp(a, 10000000000000007 - 2) % 10000000000000007; } inline long long fact(long long n) { long long res = 1; for (long long i = 1; i < (n + 1); ++i) { res = (res * i) % 10000000000000007; } return res; } inline void fact_a() { fac[0] = 1; fac[1] = 1; for (long long i = 1; i < (105); ++i) { fac[i] = (fac[i - 1] * i) % 10000000000000007; } } inline long long inv_fact(long long n) { long long par = fac[n]; long long res = mmi(par); return res; } inline long long comb(long long n, long long r) { if (n == r && r == 0) return 1; if (n < r) return 0; return ((fac[n] * inv_fact(r)) % 10000000000000007 * inv_fact(n - r)) % 10000000000000007; } struct triplet { long long a, b, c; }; bool operator<(const triplet &t1, const triplet &t2) { if (t1.a < t2.a) return true; if (t1.a == t2.a && t1.b < t2.b) return true; if (t1.a == t2.a && t1.b == t2.b && t1.c < t2.c) return true; return false; } pair<long long, pair<long long, long long> > ex_gcd(long long a, long long b) { if (b == 0) { return make_pair(a, make_pair(1, 0)); } pair<long long, pair<long long, long long> > p = ex_gcd(b, a % b); long long gcd = p.first; long long x1 = p.second.first; long long y1 = p.second.second; long long x = y1; long long y = x1 - (a / b) * y1; return make_pair(gcd, make_pair(x, y)); } long long prime[3000006]; long long spf_prime[3000006]; void sieve() { prime[1] = 1; for (long long i = 2; i * i <= 3000000; i++) if (prime[i] == 0) for (long long j = i * i; j <= 3000000; j += i) prime[j] = 1; } void spf() { for (long long i = 2; i * i <= 3000000; i++) if (!spf_prime[i]) for (long long j = i * i; j <= 3000000; j += i) if (!spf_prime[j]) spf_prime[j] = i; for (long long i = 2; i <= 3000000; i++) if (!spf_prime[i]) spf_prime[i] = i; } long long getparent_BIT(long long idx) { return idx - (idx & -idx); } long long getnext_BIT(long long idx) { return idx + (idx & -idx); } long long getsum_BIT(long long idx, long long BIT[], long long n) { long long sum = 0; while (idx > 0) { sum += BIT[idx]; idx = getparent_BIT(idx); } return sum; } void update_BIT(long long idx, long long BIT[], long long val, long long n) { while (idx <= n) { BIT[idx] += val; idx = getnext_BIT(idx); } } void build_BIT(long long BIT[], long long a[], long long n) { for (long long i = 0; i < (n); ++i) { update_BIT(i, BIT, a[i], n); } } void comp_lps(string s, long long lps[], long long n) { long long i = 1, j = 0; while (i < n) { if (s[i] == s[j]) { lps[i++] = ++j; } else { if (j != 0) j = lps[j - 1]; else lps[i++] = 0; } } } void dfs_l(long long u, vector<vector<long long> > &adj, long long status[]) { if (status[u] == 1) return; status[u] = 1; for (long long i = 0; i < (adj[u].size()); ++i) dfs_l(adj[u][i], adj, status); } long long dij(long long u, long long n, vector<vector<pair<long long, long long> > > &adj, long long status[]) { long long dist[n]; for (long long i = 0; i < (n); ++i) dist[i] = 1000000000; dist[0] = 0; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > q; q.push(make_pair(0, 0)); while (!q.empty()) { pair<long long, long long> p; p = q.top(); q.pop(); long long x = p.second; long long w = p.first; if (status[x] == 1) continue; status[x] = 1; for (long long i = 0; i < (adj[x].size()); ++i) { long long ww = adj[x][i].first; long long y = adj[x][i].second; if (dist[x] + ww < dist[y]) { dist[y] = dist[x] + ww; q.push(make_pair(dist[y], y)); } } } if (dist[n - 1] >= 1000000000) return -1; return dist[n - 1]; } long long phi(long long n) { vector<long long> v; long long k = n; ; for (long long i = 2; i * i <= n; i++) { if (k % i == 0) { v.push_back(i); while (k % i == 0) k /= i; } } if (k > 1) v.push_back(k); long long ans = n; for (long long i = 0; i < (v.size()); ++i) ans -= (ans / v[i]); return ans; } struct trie { struct trie *left, *right; bool isend; }; trie *get_trie() { trie *ptr = new trie; ptr->left = NULL; ptr->right = NULL; ptr->isend = false; return ptr; } bool isempty(trie *root) { if (root->left == NULL && root->right == NULL) return true; return false; } void insert_trie(trie *root, string key) { trie *ptr = root; for (long long i = 0; i < (key.size()); ++i) { if (key[i] == 0 ) { if (ptr->left == NULL) { ptr->left = get_trie(); } ptr = ptr->left; } else { if (ptr->right == NULL) ptr->right = get_trie(); ptr = ptr->right; } } ptr->isend = true; } trie *remove_trie(trie *root, string key, long long idx = 0) { if (root == NULL) return NULL; if (idx == key.size()) { if (isempty(root)) { delete (root); root = NULL; } return root; } if (key[idx] == 0 ) root->left = remove_trie(root->left, key, idx + 1); else root->right = remove_trie(root->right, key, idx + 1); if (isempty(root)) { delete (root); root = NULL; } return root; } long long search_trie(trie *root, string key) { trie *ptr = root; string s = ; for (long long i = 0; i < (key.size()); ++i) { if (key[i] == 0 ) { if (ptr->right != NULL) { ptr = ptr->right; s += 1 ; } else { ptr = ptr->left; s += 0 ; } } else { if (ptr->left != NULL) { ptr = ptr->left; s += 1 ; } else { ptr = ptr->right; s += 0 ; } } } long long res = 0; reverse(s.begin(), s.end()); for (long long i = s.length() - 1; i >= (0); --i) res = res * 2 + (s[i] - 0 ); return res; } struct Comp { bool operator()(const std::pair<int, int> &a, const std::pair<int, int> &b) { if (a.first != b.first) { return a.first < b.first; } return a.second > b.second; } }; void dearr() { long long dar[1005]; dar[0] = 1; dar[1] = 0; dar[2] = 1; for (long long i = 3; i < (1002); ++i) { dar[i] = (i - 1) * (dar[i - 1] + dar[i - 2]); } } int main() { long long n; cin >> n; if (n % 2 == 0) { cout << white << n ; cout << 1 << << 2 << n ; } else cout << black << n ; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Dual Port 16x6
// File : dual_port_16x6.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module realizes a 16x6 dual port register bank
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module dual_port_16x6
(
input h_reset_n,
input we, // write enable (host)
input h_hclk,
input clk,
input clk_en,
input [3:0] addr1, // R/W Address (host)
input [3:0] addr2, // Read address 2 (other)
input [5:0] din, // data in (host)
output reg [5:0] dout1, // data out (host)
output reg [5:0] dout2 // data out (other)
);
reg [5:0] storage[15:0];
integer i;
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
for (i = 0; i < 16; i = i + 1) storage[i] <= 6'b0;
end else begin
if (we) storage[addr1] <= din;
dout1 <= storage[addr1];
end
always @(posedge clk or negedge h_reset_n)
if (!h_reset_n) dout2 <= 6'b0;
else if(clk_en) dout2 <= storage[addr2];
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// ,
//
// Create Date: 16:54:00 06/03/2014
// Design Name: signal_gen
// Module Name: signal_gen
// Project Name: Streaming Media on Null Convention Logic
// Description: Signal generation for gates test - for Testbench
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module signal_gen(clk, rst, req, stm_value, rsb, gnt);
parameter INPUT_PORTS = 3;
parameter RESET_PORT = 1; // 0: no reset, 1: has reset
parameter RESET_SENS = 0; // 0: Active Low, 1: Active High
parameter integer CNT_MAX = (INPUT_PORTS == 1) ? 2 :
((INPUT_PORTS == 2) ? 4 :
((INPUT_PORTS == 3) ? 8 :
((INPUT_PORTS == 4) ? 16 :
((INPUT_PORTS == 5) ? 32 :
0))));
input clk;
input rst;
input req;
output [INPUT_PORTS-1: 0] stm_value;
output rsb;
output gnt;
parameter PREV_HALF = 1;
parameter PREV_MAX = 2;
// for state-machine
parameter SIZE = 4;
parameter IDLE = 4'b0001;
parameter PREV = 4'b0010;
parameter CURR = 4'b0100;
parameter NEXT = 4'b1000;
wire [INPUT_PORTS-1: 0] stm_value;
wire rsb;
reg [INPUT_PORTS-1: 0] symb_value;
reg rsb_int;
reg gnt;
reg [SIZE-1:0] state;
// Internal Signals
integer prev_cnt;
integer curr_cnt;
integer next_cnt;
reg rst_invert;
assign stm_value = symb_value;
assign rsb = rsb_int;
always@(posedge clk)
begin: FSM
if(rst) begin
state <= #1 IDLE;
prev_cnt <= 0;
curr_cnt <= 0;
next_cnt <= 0;
symb_value <= 0;
gnt <= 1'b0;
if((RESET_PORT == 1) && (RESET_SENS == 0)) begin
rsb_int <= 1'b0;
end
else begin
rsb_int <= 1'b1;
end
rst_invert <= 1'b0;
end
else begin
case(state)
IDLE :
begin
rst_invert <= 1'b0;
if (req == 1'b1) begin
if((RESET_PORT == 1) && (RESET_SENS == 0)) begin
rsb_int <= 1'b0;
end
else begin
rsb_int <= 1'b1;
end
state <= #1 PREV;
end
else begin
gnt <= 1'b0;
state <= #1 IDLE;
end
end
PREV :
if (prev_cnt < (PREV_HALF)) begin
symb_value <= {INPUT_PORTS{1'b0}}; // All '0' input - NULL
state <= #1 CURR;
end
else if((prev_cnt >= (PREV_HALF)) && (prev_cnt < PREV_MAX)) begin
symb_value <= {INPUT_PORTS{1'b1}}; // All '1' input - DATA
state <= #1 CURR;
end
else begin
symb_value <= {INPUT_PORTS{1'b0}};
if((RESET_PORT == 1) && (RESET_SENS == 0)) begin
if(rst_invert == 1'b0) begin
rsb_int <= 1'b1;
rst_invert <= 1'b1;
prev_cnt <= 0; // Init
state <= #1 CURR;
end
else begin
rsb_int <= 1'b0;
rst_invert <= 1'b0;
gnt <= 1'b1;
state <= #1 IDLE;
end
end
else if((RESET_PORT == 1) && (RESET_SENS == 1)) begin
if(rst_invert == 1'b0) begin
rsb_int <= 1'b0;
rst_invert <= 1'b1;
prev_cnt <= 0; // Init
state <= #1 CURR;
end
else begin
rsb_int <= 1'b1;
rst_invert <= 1'b0;
gnt <= 1'b1;
state <= #1 IDLE;
end
end
else begin
rsb_int <= 1'b0;
gnt <= 1'b1;
state <= #1 IDLE; // finish signal generation
end
end
CURR :
if (curr_cnt < (CNT_MAX-1)) begin
symb_value <= curr_cnt;
state <= #1 NEXT;
end
else begin
symb_value <= curr_cnt;
state <= #1 NEXT;
end
NEXT :
if (next_cnt < (CNT_MAX-1)) begin
symb_value <= next_cnt;
next_cnt <= next_cnt + 1;
state <= #1 PREV;
end
else begin
symb_value <= next_cnt;
next_cnt <= 0; // Init
if (curr_cnt < (CNT_MAX-1)) begin
curr_cnt <= curr_cnt + 1;
end
else begin
curr_cnt <= 0; // Init
if(prev_cnt < PREV_MAX) begin
prev_cnt <= prev_cnt + 1;
end
else begin
prev_cnt <= 0; // Init
end
end
state <= #1 PREV;
end
default : state <= #1 IDLE;
endcase
end
end
endmodule
//////////////////////////////////////////////////////////
// Example
//////////////////////////////////////////////////////////
// TH22 - 2 Input Gate Singinal Generation Example
// Input => Integer number
// 0 0 => 0
// 0 1 => 1
// 1 0 => 2
// 1 1 => 3
// When Y`(Previous Value) is '0' case.
// Always initialze to the Null or Data before test the transion result
// Y Current Next Output(Y`)
// 0 -> 0 -> 0 => 0
// 0 -> 0 -> 1 => 0 - Hold
// 0 -> 0 -> 2 => 0 - Hold
// 0 -> 0 -> 3 => 1
// 0 -> 1 -> 0 => 0
// 0 -> 1 -> 1 => 0 - Hold - Hold
// 0 -> 1 -> 2 => 0 - Hold - Hold
// 0 -> 1 -> 3 => 1
// 0 -> 2 -> 0 => 0
// 0 -> 2 -> 1 => 0 - Hold - Hold
// 0 -> 2 -> 2 => 0 - Hold - Hold
// 0 -> 2 -> 3 => 1
// 0 -> 3 -> 0 => 0
// 0 -> 3 -> 1 => 1 - Hold
// 0 -> 3 -> 2 => 1 - Hold
// 0 -> 3 -> 3 => 1
// When Y`(Previous Value) is '1' case.
// Y Current Next Output(Y`)
// 1 -> 0 -> 0 => 0
// 1 -> 0 -> 1 => 0 - Hold
// 1 -> 0 -> 2 => 0 - Hold
// 1 -> 0 -> 3 => 0
// 1 -> 1 -> 0 => 0
// 1 -> 1 -> 1 => 1 - Hold - Hold
// 1 -> 1 -> 2 => 1 - Hold - Hold
// 1 -> 1 -> 3 => 1
// 1 -> 2 -> 0 => 0
// 1 -> 2 -> 1 => 1 - Hold - Hold
// 1 -> 2 -> 2 => 1 - Hold - Hold
// 1 -> 2 -> 3 => 1
// 1 -> 3 -> 0 => 0
// 1 -> 3 -> 1 => 1 - Hold
// 1 -> 3 -> 2 => 1 - Hold
// 1 -> 3 -> 3 => 1
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_1_V
`define SKY130_FD_SC_HDLL__DLRTP_1_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_1_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int n, m, num[40][40], len = 0, stat[20], sv[20], ans = 0; bool vis[10][10], vis2[10][10], usedr[10], have = false; string s[40]; vector<pair<int, int> > coo[400]; vector<int> pr[20]; bool stane = false; bool check(int pos) { map<pair<int, int>, int> mp; mp.clear(); for (int i = 0; i < pr[pos].size(); ++i) { int x = stat[pos], y = stat[pr[pos][i]]; if (vis[x][y] || mp[make_pair(x, y)]) return false; mp[make_pair(x, y)] = mp[make_pair(y, x)] = true; } return true; } void add(int pos, bool val) { for (int i = 0; i < pr[pos].size(); ++i) { int x = stat[pos], y = stat[pr[pos][i]]; vis[x][y] = vis[y][x] = val; } } void dfs(int pos, int curc) { if (pos == 14) { ++ans; if (!have) { have = true; for (int i = 0; i < 14; ++i) sv[i] = stat[i]; } return; } if (curc < 7) { stat[pos] = curc; if (check(pos)) { add(pos, true); dfs(pos + 1, curc + 1); add(pos, false); } } for (int i = 0; i < curc; ++i) { if (usedr[i]) continue; stat[pos] = i; if (check(pos)) { usedr[i] = true; add(pos, true); dfs(pos + 1, curc); usedr[i] = false; add(pos, false); } } } int main() { cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> s[i]; for (int j = 0; j < m; ++j) if (s[i][j] == A ) s[i][j] = z + 1; else if (s[i][j] == B ) s[i][j] = z + 2; } for (int i = 0; i < n + 5; ++i) for (int j = 0; j < m + 5; ++j) num[i][j] = -1; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) if ( a <= s[i][j] && s[i][j] <= z + 2) { coo[s[i][j]].push_back(make_pair(i, j)); if (num[i][j] == -1) { for (int k = i; k < i + 2; ++k) for (int p = j; p < j + 2; ++p) num[k][p] = len; ++len; } } for (int i = a ; i <= z + 2; ++i) { int x = coo[i][0].first, y = coo[i][0].second, xx = coo[i][1].first, yy = coo[i][1].second; pr[max(num[x][y], num[xx][yy])].push_back(min(num[x][y], num[xx][yy])); } dfs(0, 0); cout << ans * 5040 << endl; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (!( a <= s[i][j] && s[i][j] <= z + 2)) cout << . ; else cout << sv[num[i][j]]; } cout << endl; } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire [1:0] A,
input wire [1:0] B,
output wire Y
);
parameter [1:0] INV_A = 2'b00;
endmodule
module top(
input wire [3:0] di,
output wire do
);
wire [3:0] d;
\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
\$_NOT_ n2 (.A(di[2]), .Y(d[2]));
\$_NOT_ n3 (.A(di[3]), .Y(d[3]));
box #(.INV_A(2'b01)) the_box (
.A ({d[1], d[0]}),
.B ({d[3], d[2]}),
.Y (do)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int kN = int(2E5 + 10), kInf = int(1E9 + 10), kC = int(1E6 + 10); struct seg_tree { long long int val[kN << 2], flag[kN << 2]; void init() { memset(val, 0, sizeof(val)); memset(flag, 0, sizeof(flag)); return; } void addtag(int n, long long int x) { flag[n] += x; val[n] += x; } void push(int n) { if (flag[n]) { addtag(n << 1, flag[n]); addtag(n << 1 | 1, flag[n]); flag[n] = 0; } return; } void pull(int n) { val[n] = max(val[n << 1], val[n << 1 | 1]); return; } void fix(int n, int l, int r, int L, int R, long long int x) { if (L <= l && r <= R) addtag(n, x); else if (!(l > R || L > r)) { int mid = (l + r) >> 1; push(n); fix(n << 1, l, mid, L, R, x); fix(n << 1 | 1, mid + 1, r, L, R, x); pull(n); } return; } }; pair<int, int> wep[kN], eqi[kN]; pair<pair<int, int>, int> mon[kN]; int pos[kC]; seg_tree sg; int main() { int n, m, p, now = 1; long long int ans; scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; i++) scanf( %d%d , &wep[i].first, &wep[i].second); for (int i = 1; i <= m; i++) scanf( %d%d , &eqi[i].first, &eqi[i].second); for (int i = 1; i <= p; i++) scanf( %d%d%d , &mon[i].first.first, &mon[i].first.second, &mon[i].second); sort(wep + 1, wep + n + 1); sort(eqi + 1, eqi + m + 1); sort(mon + 1, mon + p + 1); sg.init(); for (int i = 1; i <= m; i++) sg.fix(1, 1, m, i, i, -eqi[i].second); for (int i = 0; i < kC; i++) { while (now <= m) { if (eqi[now].first <= i) now++; else break; } pos[i] = now; } ans = -wep[1].second - eqi[1].second; now = 1; for (int i = 1; i <= n; i++) { while (now <= p) { if (mon[now].first.first < wep[i].first) { if (pos[mon[now].first.second] <= m) sg.fix(1, 1, m, pos[mon[now].first.second], m, mon[now].second); now++; } else break; } ans = max(ans, sg.val[1] - wep[i].second); } printf( %lld n , ans); }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fei4_rx_core #(
parameter DSIZE = 10,
parameter DATA_IDENTIFIER = 0,
parameter ABUSWIDTH = 32
) (
input wire RX_CLK,
input wire RX_CLK2X,
input wire DATA_CLK,
input wire RX_DATA,
output reg RX_READY,
output reg RX_8B10B_DECODER_ERR,
output reg RX_FIFO_OVERFLOW_ERR,
input wire FIFO_CLK,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire RX_FIFO_FULL,
output wire RX_ENABLED,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 3;
// writing to register 0 asserts soft reset
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD == 0 && BUS_WR);
// reset sync
reg SOFT_RST_FF, SOFT_RST_FF2, BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
SOFT_RST_FF <= SOFT_RST;
SOFT_RST_FF2 <= SOFT_RST_FF;
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
// writing to register 1 asserts reset RX only
wire RX_RST;
assign RX_RST = (BUS_ADD==1 && BUS_WR);
reg RX_RST_FF, RX_RST_FF2;
always @(posedge BUS_CLK) begin
RX_RST_FF <= RX_RST;
RX_RST_FF2 <= RX_RST_FF;
end
wire SOFT_RST_FLAG;
assign SOFT_RST_FLAG = ~SOFT_RST_FF2 & SOFT_RST_FF;
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire RST_FLAG;
assign RST_FLAG = BUS_RST_FLAG | SOFT_RST_FLAG;
wire RX_RST_FLAG;
assign RX_RST_FLAG = ~RX_RST_FF2 & RX_RST_FF;
reg RECEIVER_RST;
always @(posedge BUS_CLK) begin
RECEIVER_RST <= RST_FLAG | RX_RST_FLAG;
end
// registers
// 0 - soft reset
// 1 - RX reset
// 2 - status
// 3-4 - fifo size
// 5 - 8b10b decoder error counter
// 6 - lost data counter
wire rx_ready_bus_clk;
reg [15:0] fifo_size_bus_clk; // BUS_ADD==3
reg [7:0] fifo_size_buf_read_bus_clk; // BUS_ADD==4
reg [7:0] decoder_err_cnt_bus_clk; // BUS_ADD==5
reg [7:0] lost_data_cnt_bus_clk; // BUS_ADD==6
reg [7:0] status_regs;
wire CONF_EN_INVERT_RX_DATA; // BUS_ADD==2 BIT==1
assign CONF_EN_INVERT_RX_DATA = status_regs[1];
wire CONF_EN_RX; // BUS_ADD==2 BIT==2
assign CONF_EN_RX = status_regs[2];
assign RX_ENABLED = CONF_EN_RX;
always @(posedge BUS_CLK) begin
if(RST_FLAG)
status_regs <= 8'b0000_0000; // disable Rx by default
else if(BUS_WR && BUS_ADD == 2)
status_regs <= BUS_DATA_IN;
end
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {status_regs[7:1], rx_ready_bus_clk};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= fifo_size_bus_clk[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= fifo_size_buf_read_bus_clk;
else if(BUS_ADD == 5)
BUS_DATA_OUT <= decoder_err_cnt_bus_clk;
else if(BUS_ADD == 6)
BUS_DATA_OUT <= lost_data_cnt_bus_clk;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire CONF_EN_INVERT_RX_DATA_FCLK;
three_stage_synchronizer conf_en_invert_rx_data_synchronizer_rx_clk (
.CLK(RX_CLK),
.IN(CONF_EN_INVERT_RX_DATA),
.OUT(CONF_EN_INVERT_RX_DATA_FCLK)
);
wire CONF_EN_RX_WCLK;
three_stage_synchronizer conf_en_rx_synchronizer_data_clk (
.CLK(DATA_CLK),
.IN(CONF_EN_RX),
.OUT(CONF_EN_RX_WCLK)
);
wire rec_sync_ready;
three_stage_synchronizer rx_ready_synchronizer_bus_clk (
.CLK(BUS_CLK),
.IN(rec_sync_ready),
.OUT(rx_ready_bus_clk)
);
always @(posedge DATA_CLK) begin
RX_READY <= rec_sync_ready;
end
wire [7:0] decoder_err_cnt;
always @(posedge DATA_CLK) begin
if(|decoder_err_cnt) begin
RX_8B10B_DECODER_ERR <= 1;
end else begin
RX_8B10B_DECODER_ERR <= 0;
end
end
wire [7:0] lost_data_cnt;
always @(posedge DATA_CLK) begin
if(|lost_data_cnt) begin
RX_FIFO_OVERFLOW_ERR <= 1;
end else begin
RX_FIFO_OVERFLOW_ERR <= 0;
end
end
wire [23:0] FE_DATA;
wire [7:0] DATA_HEADER;
assign DATA_HEADER = DATA_IDENTIFIER;
assign FIFO_DATA = {DATA_HEADER, FE_DATA};
wire [15:0] fifo_size;
reg [15:0] fifo_size_gray;
always @(posedge FIFO_CLK)
fifo_size_gray <= (fifo_size>>1) ^ fifo_size;
reg [15:0] fifo_size_cdc0, fifo_size_cdc1;
always @(posedge BUS_CLK) begin
fifo_size_cdc0 <= fifo_size_gray;
fifo_size_cdc1 <= fifo_size_cdc0;
end
integer gbi_fifo_size;
always @(*) begin
fifo_size_bus_clk[15] = fifo_size_cdc1[15];
for(gbi_fifo_size = 14; gbi_fifo_size >= 0; gbi_fifo_size = gbi_fifo_size - 1) begin
fifo_size_bus_clk[gbi_fifo_size] = fifo_size_cdc1[gbi_fifo_size] ^ fifo_size_bus_clk[gbi_fifo_size + 1];
end
end
always @(posedge BUS_CLK)
begin
if (BUS_ADD == 3 && BUS_RD)
fifo_size_buf_read_bus_clk <= fifo_size_bus_clk[15:8];
end
reg [7:0] decoder_err_cnt_gray;
always @(posedge DATA_CLK)
decoder_err_cnt_gray <= (decoder_err_cnt>>1) ^ decoder_err_cnt;
reg [7:0] decoder_err_cnt_cdc0, decoder_err_cnt_cdc1;
always @(posedge BUS_CLK) begin
decoder_err_cnt_cdc0 <= decoder_err_cnt_gray;
decoder_err_cnt_cdc1 <= decoder_err_cnt_cdc0;
end
integer gbi_decoder_err_cnt;
always @(*) begin
decoder_err_cnt_bus_clk[7] = decoder_err_cnt_cdc1[7];
for(gbi_decoder_err_cnt = 6; gbi_decoder_err_cnt >= 0; gbi_decoder_err_cnt = gbi_decoder_err_cnt - 1) begin
decoder_err_cnt_bus_clk[gbi_decoder_err_cnt] = decoder_err_cnt_cdc1[gbi_decoder_err_cnt] ^ decoder_err_cnt_bus_clk[gbi_decoder_err_cnt + 1];
end
end
reg [7:0] lost_data_cnt_gray;
always @(posedge DATA_CLK)
lost_data_cnt_gray <= (lost_data_cnt>>1) ^ lost_data_cnt;
reg [7:0] lost_data_cnt_cdc0, lost_data_cnt_cdc1;
always @(posedge BUS_CLK) begin
lost_data_cnt_cdc0 <= lost_data_cnt_gray;
lost_data_cnt_cdc1 <= lost_data_cnt_cdc0;
end
integer gbi_lost_data_cnt;
always @(*) begin
lost_data_cnt_bus_clk[7] = lost_data_cnt_cdc1[7];
for(gbi_lost_data_cnt = 6; gbi_lost_data_cnt >= 0; gbi_lost_data_cnt = gbi_lost_data_cnt - 1) begin
lost_data_cnt_bus_clk[gbi_lost_data_cnt] = lost_data_cnt_cdc1[gbi_lost_data_cnt] ^ lost_data_cnt_bus_clk[gbi_lost_data_cnt + 1];
end
end
receiver_logic #(
.DSIZE(DSIZE)
) ireceiver_logic (
.RESET(RECEIVER_RST),
.WCLK(DATA_CLK),
.FCLK(RX_CLK),
.FCLK2X(RX_CLK2X),
.BUS_CLK(BUS_CLK),
.RX_DATA(RX_DATA),
.read(FIFO_READ),
.data(FE_DATA),
.empty(FIFO_EMPTY),
.rx_fifo_full(RX_FIFO_FULL),
.rec_sync_ready(rec_sync_ready),
.lost_data_cnt(lost_data_cnt),
.decoder_err_cnt(decoder_err_cnt),
.fifo_size(fifo_size),
.invert_rx_data(CONF_EN_INVERT_RX_DATA_FCLK),
.enable_rx(CONF_EN_RX_WCLK),
.FIFO_CLK(FIFO_CLK)
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iodelay4 #(
parameter ODELAY_VALUE = 30
) (
/* pad -> fabric */
input [3:0] IDATAIN,
output [3:0] DATAOUT,
/* fabric -> pad */
input [3:0] T,
output [3:0] TOUT,
input [3:0] ODATAIN,
output [3:0] DOUT,
/* control pins */
input INC,
input CE,
input RST,
input CAL,
input CLK,
input IOCLK0,
input IOCLK1
);
IODELAY2 #(
.DELAY_SRC("IO"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR"),
.ODELAY_VALUE(ODELAY_VALUE)
) idelay0 (
.IDATAIN(IDATAIN[0]),
.DATAOUT(DATAOUT[0]),
.T(T[0]),
.TOUT(TOUT[0]),
.ODATAIN(ODATAIN[0]),
.DOUT(DOUT[0]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.CAL(CAL)
);
IODELAY2 #(
.DELAY_SRC("IO"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR"),
.ODELAY_VALUE(ODELAY_VALUE)
) idelay1 (
.IDATAIN(IDATAIN[1]),
.DATAOUT(DATAOUT[1]),
.T(T[1]),
.TOUT(TOUT[1]),
.ODATAIN(ODATAIN[1]),
.DOUT(DOUT[1]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.CAL(CAL)
);
IODELAY2 #(
.DELAY_SRC("IO"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR"),
.ODELAY_VALUE(ODELAY_VALUE)
) idelay2 (
.IDATAIN(IDATAIN[2]),
.DATAOUT(DATAOUT[2]),
.T(T[2]),
.TOUT(TOUT[2]),
.ODATAIN(ODATAIN[2]),
.DOUT(DOUT[2]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.CAL(CAL)
);
IODELAY2 #(
.DELAY_SRC("IO"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR"),
.ODELAY_VALUE(ODELAY_VALUE)
) idelay3 (
.IDATAIN(IDATAIN[3]),
.DATAOUT(DATAOUT[3]),
.T(T[3]),
.TOUT(TOUT[3]),
.ODATAIN(ODATAIN[3]),
.DOUT(DOUT[3]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.CAL(CAL)
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 13179 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w1024,
w1023,
w64,
w63,
w8064,
w9087,
w4092,
w13179;
assign w1 = i_data0;
assign w1023 = w1024 - w1;
assign w1024 = w1 << 10;
assign w13179 = w9087 + w4092;
assign w4092 = w1023 << 2;
assign w63 = w64 - w1;
assign w64 = w1 << 6;
assign w8064 = w63 << 7;
assign w9087 = w1023 + w8064;
assign o_data0 = w13179;
//multiplier_block area estimate = 6819.12002173677;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, k; cin >> n >> k; long long int ans = 1; while (k % 2 == 0) { k = k / 2; ans++; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int fre[26] = {0}; for (int i = 0; i < n; i++) { fre[s[i] - a ] = fre[s[i] - a ] + 1; } string ans = ; for (int i = 0; i < 26; i++) { for (int j = 0; j < fre[i]; j++) { ans = ans + char(97 + i); } } cout << ans; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx_arb_atomq.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
// USES srcq select signals; ignore qcount code in this file
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module ccx_arb_atomq(/*AUTOARG*/
// Outputs
q0_dataout, scan_out,
// Inputs
ctl_qsel1_a_l, ctl_qsel0_a, ctl_shift_a, atom_a, rclk, reset_d1
);
output q0_dataout; // pcx to destination pkt
output scan_out;
input ctl_qsel1_a_l; // queue write sel
input ctl_qsel0_a; // queue write sel
input ctl_shift_a;//grant signal
input atom_a; // spache to pcx data
input rclk;
//input tmb_l;
input reset_d1;
wire q0_datain_pa;
wire q1_datain_pa;
wire q1_dataout;
wire q1_data_out;
wire q0_data_out;
//HEADER SECTION
//DATAPATH SECTION
assign q1_datain_pa = ~ctl_qsel1_a_l ? atom_a : q1_dataout;
dff_s #(1) dff_pcx_atomin_q1(
.din (q1_datain_pa),
.q (q1_data_out),
.clk (rclk),
.se (1'b0),
.si (),
.so ());
assign q1_dataout = ~reset_d1 ? q1_data_out : 1'b0;
assign q0_datain_pa =
ctl_qsel0_a ? atom_a :
ctl_shift_a ? q1_dataout :
q0_dataout;
dff_s #(1) dff_pcx_atomin_q0(
.din (q0_datain_pa),
.q (q0_data_out),
.clk (rclk),
.se (1'b0),
.si (),
.so ());
assign q0_dataout = ~reset_d1 ? q0_data_out : 1'b0;
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_change (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_CHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_change_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_change_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_change_psl_logic.v"
`else
`endmodule // ovl_change
`endif
|
/*
*
* Copyright (c) 2013
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module ff_mul (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
output tx_done,
output [255:0] tx_c
);
wire mul_done;
wire [511:0] mul_result;
bn_mul uut (
.clk (clk),
.reset (reset),
.rx_a (rx_a),
.rx_b (rx_b),
.tx_done (mul_done),
.tx_r (mul_result)
);
reg reduce_reset = 1'b1;
ff_reduce_secp256k1 uut2 (
.clk (clk),
.reset (reset | reduce_reset),
.rx_a (mul_result),
.tx_done (tx_done),
.tx_a (tx_c)
);
always @ (posedge clk)
begin
if (reset)
reduce_reset <= 1'b1;
else if (mul_done)
reduce_reset <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, ans = 34343434; vector<long long> a; vector<long long> b; int main() { cin >> n; for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; if (x == 1) a.push_back(y); else b.push_back(y); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); for (int v = 0; v <= a.size(); v++) { for (int u = 0; u <= b.size(); u++) { long long width = v + u * 2, len = 0; for (int i = 0; i < a.size() - v; i++) len += a[i]; for (int i = 0; i < b.size() - u; i++) len += b[i]; if (width >= len) ans = min(ans, width); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; while (n) { if (n % 10 != 1 && n % 100 != 14 && n % 1000 != 144) { cout << NO ; return 0; } n /= 10; } cout << YES ; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_rptr_d.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_rptr_d(out21 ,out20 ,out19 ,out18 ,out17 ,out16 ,out15
,out14 ,out13 ,out12 ,out10 ,out9 ,out8 ,out6 ,out5 ,out4 ,out3 ,
out2 ,in21 ,in20 ,in19 ,in18 ,in17 ,in16 ,in15 ,in14 ,in13 ,in12 ,
out1 ,out0 ,in10 ,in22 ,out22 ,in24 ,out24 ,out25 ,vdd18 ,in25 ,in2
,in5 ,in1 ,in4 ,in9 ,out11 ,in3 ,in11 ,in0 ,in6 ,in8 );
output [8:1] out14 ;
output [8:1] out13 ;
output [1:0] out10 ;
output [1:0] out9 ;
output [1:0] out4 ;
output [4:0] out1 ;
output [7:0] out25 ;
input [8:1] in14 ;
input [8:1] in13 ;
input [1:0] in10 ;
input [7:0] in25 ;
input [4:0] in1 ;
input [1:0] in4 ;
input [1:0] in9 ;
output out21 ;
output out20 ;
output out19 ;
output out18 ;
output out17 ;
output out16 ;
output out15 ;
output out12 ;
output out8 ;
output out6 ;
output out5 ;
output out3 ;
output out2 ;
output out0 ;
output out22 ;
output out24 ;
output out11 ;
input in21 ;
input in20 ;
input in19 ;
input in18 ;
input in17 ;
input in16 ;
input in15 ;
input in12 ;
input in22 ;
input in24 ;
input vdd18 ;
input in2 ;
input in5 ;
input in3 ;
input in11 ;
input in0 ;
input in6 ;
input in8 ;
bw_u1_buf_30x I10_1_ (
.z (out9[1] ),
.a (in9[1] ) );
bw_u1_buf_30x I0 (
.z (out2 ),
.a (in2 ) );
bw_u1_buf_30x I1 (
.z (out3 ),
.a (in3 ) );
bw_u1_buf_30x I65_2_ (
.z (out1[2] ),
.a (in1[2] ) );
bw_u1_buf_30x I4 (
.z (out6 ),
.a (in6 ) );
bw_u1_buf_30x I5 (
.z (out5 ),
.a (in5 ) );
bw_u1_buf_30x I34_1_ (
.z (out13[1] ),
.a (in13[1] ) );
bw_u1_buf_30x I6 (
.z (out11 ),
.a (in11 ) );
bw_u1_buf_30x I35_7_ (
.z (out14[7] ),
.a (in14[7] ) );
bw_u1_buf_30x I7 (
.z (out12 ),
.a (in12 ) );
bw_u1_buf_30x I66 (
.z (out0 ),
.a (in0 ) );
bw_u1_buf_30x I65_3_ (
.z (out1[3] ),
.a (in1[3] ) );
bw_u1_buf_30x I34_2_ (
.z (out13[2] ),
.a (in13[2] ) );
bw_u1_buf_30x I35_8_ (
.z (out14[8] ),
.a (in14[8] ) );
bw_u1_buf_30x I65_4_ (
.z (out1[4] ),
.a (in1[4] ) );
bw_u1_buf_30x I34_3_ (
.z (out13[3] ),
.a (in13[3] ) );
bw_u1_buf_30x I35_1_ (
.z (out14[1] ),
.a (in14[1] ) );
bw_u1_buf_30x I9_0_ (
.z (out10[0] ),
.a (in10[0] ) );
bw_u1_buf_30x I11 (
.z (out8 ),
.a (in8 ) );
bw_u1_buf_30x I34_4_ (
.z (out13[4] ),
.a (in13[4] ) );
bw_u1_buf_30x I35_2_ (
.z (out14[2] ),
.a (in14[2] ) );
bw_u1_buf_30x I9_1_ (
.z (out10[1] ),
.a (in10[1] ) );
bw_u1_buf_30x I34_5_ (
.z (out13[5] ),
.a (in13[5] ) );
bw_u1_buf_30x I35_3_ (
.z (out14[3] ),
.a (in14[3] ) );
bw_u1_buf_30x I2_0_ (
.z (out4[0] ),
.a (in4[0] ) );
bw_u1_buf_30x I102 (
.z (out22 ),
.a (in22 ) );
bw_u1_buf_30x I34_6_ (
.z (out13[6] ),
.a (in13[6] ) );
bw_u1_buf_30x I35_4_ (
.z (out14[4] ),
.a (in14[4] ) );
bw_u1_buf_30x I36 (
.z (out15 ),
.a (in15 ) );
bw_u1_buf_30x I37 (
.z (out16 ),
.a (in16 ) );
bw_u1_buf_30x I38 (
.z (out17 ),
.a (in17 ) );
bw_u1_buf_30x I39 (
.z (out19 ),
.a (in19 ) );
bw_u1_buf_30x I110 (
.z (out24 ),
.a (in24 ) );
bw_u1_buf_30x I65_0_ (
.z (out1[0] ),
.a (in1[0] ) );
bw_u1_buf_30x I2_1_ (
.z (out4[1] ),
.a (in4[1] ) );
bw_u1_buf_30x I40 (
.z (out18 ),
.a (in18 ) );
bw_u1_buf_30x I41 (
.z (out20 ),
.a (in20 ) );
bw_u1_buf_30x I42 (
.z (out21 ),
.a (in21 ) );
bw_io_ddr_vref_rptr I115 (
.out ({out25 } ),
.in ({in25 } ),
.vdd18 (vdd18 ) );
bw_u1_buf_30x I34_7_ (
.z (out13[7] ),
.a (in13[7] ) );
bw_u1_buf_30x I35_5_ (
.z (out14[5] ),
.a (in14[5] ) );
bw_u1_buf_30x I10_0_ (
.z (out9[0] ),
.a (in9[0] ) );
bw_u1_buf_30x I65_1_ (
.z (out1[1] ),
.a (in1[1] ) );
bw_u1_buf_30x I34_8_ (
.z (out13[8] ),
.a (in13[8] ) );
bw_u1_buf_30x I35_6_ (
.z (out14[6] ),
.a (in14[6] ) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO1P_FUNCTIONAL_PP_V
/**
* lsbufiso1p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_SLEEP;
wire or0_out_X ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SLEEP, SLEEP, DESTPWR, VGND );
or or0 (or0_out_X , SLEEP, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , or0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long int N = 100001; bool ok; long long int n, q; long long int trie[6 * N][5], done[6 * N]; long long int nxt = 1; string s; void insert(string s) { long long int node = 0; for (char c : s) { if (trie[node][c - a ] == 0) { node = trie[node][c - a ] = nxt++; } else { node = trie[node][c - a ]; } } done[nxt - 1] = 1; } void dfs(long long int u, long long int idx, long long int f) { if (f >= 2) return; if (idx == s.length() - 1 && f == 1 && done[u]) { ok = 1; return; } if (idx == s.length() - 1 || done[u]) return; for (long long int i = 0; i < 3; i++) { if (trie[u][i] == 0) continue; if (s[idx + 1] == (char)(i + a )) dfs(trie[u][i], idx + 1, f); else dfs(trie[u][i], idx + 1, f + 1); } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> q; for (long long int i = 0; i < n; i++) { cin >> s; insert(s); } for (long long int i = 0; i < q; i++) { cin >> s; ok = 0; dfs(0, -1, 0); cout << (ok ? YES n : NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_PP_BLACKBOX_V
|
`default_nettype none
`define CLKFBOUT_MULT 2
// ============================================================================
module top
(
input wire clk,
input wire rst,
input wire [7:0] sw,
output wire [9:0] led,
inout wire io
);
localparam DATA_WIDTH = `DATA_WIDTH_DEFINE;
localparam DATA_RATE = `DATA_RATE_DEFINE;
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
wire CLK;
BUFG bufg(.I(clk), .O(CLK));
always @(posedge CLK)
if (rst)
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire RST = rst_sr[0];
// ============================================================================
// Clocks for ISERDES
wire PRE_BUFG_SYSCLK;
wire PRE_BUFG_CLKDIV;
wire PRE_BUFG_REFCLK;
wire SYSCLK;
wire CLKDIV;
wire REFCLK;
wire O_LOCKED;
wire clk_fb_i;
wire clk_fb_o;
localparam DIVIDE_RATE = DATA_RATE == "SDR" ? DATA_WIDTH : DATA_WIDTH / 2;
PLLE2_ADV #(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (`CLKFBOUT_MULT),
.CLKOUT0_DIVIDE (`CLKFBOUT_MULT * 4), // SYSCLK, 25MHz
.CLKOUT1_DIVIDE ((`CLKFBOUT_MULT * 4) * DIVIDE_RATE), // CLKDIV, 25MHz / DIVIDE RATE
.CLKOUT2_DIVIDE (`CLKFBOUT_MULT / 2), // REFCLK (IDELAYCTRL), 200 MHz
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1'd1)
)
pll
(
.CLKIN1 (CLK),
.CLKINSEL (1),
.RST (RST),
.PWRDWN (0),
.LOCKED (O_LOCKED),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (PRE_BUFG_SYSCLK),
.CLKOUT1 (PRE_BUFG_CLKDIV),
.CLKOUT2 (PRE_BUFG_REFCLK)
);
BUFG bufg_clk(.I(PRE_BUFG_SYSCLK), .O(SYSCLK));
BUFG bufg_clkdiv(.I(PRE_BUFG_CLKDIV), .O(CLKDIV));
BUFG bufg_refclk(.I(PRE_BUFG_REFCLK), .O(REFCLK));
// ============================================================================
// Test uints
wire [7:0] OUTPUTS;
wire [7:0] INPUTS = sw[7:0];
localparam MASK = DATA_WIDTH == 2 ? 8'b00000011 :
DATA_WIDTH == 3 ? 8'b00000111 :
DATA_WIDTH == 4 ? 8'b00001111 :
DATA_WIDTH == 5 ? 8'b00011111 :
DATA_WIDTH == 6 ? 8'b00111111 :
DATA_WIDTH == 7 ? 8'b01111111 :
/*DATA_WIDTH == 8*/ 8'b11111111;
wire [7:0] MASKED_INPUTS = INPUTS & MASK;
wire I_DAT;
wire O_DAT;
wire T_DAT;
IOBUF iobuf(.I(O_DAT), .O(I_DAT), .T(T_DAT), .IO(io));
serdes_test #
(
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE (DATA_RATE)
)
serdes_test
(
.SYSCLK (SYSCLK),
.REFCLK (REFCLK),
.CLKDIV (CLKDIV),
.RST (RST),
.OUTPUTS (OUTPUTS),
.INPUTS (MASKED_INPUTS),
.I_DAT (I_DAT),
.O_DAT (O_DAT),
.T_DAT (T_DAT)
);
wire [7:0] MASKED_OUTPUTS = OUTPUTS & MASK;
// ============================================================================
// I/O connections
reg [23:0] heartbeat_cnt;
always @(posedge SYSCLK)
heartbeat_cnt <= heartbeat_cnt + 1;
assign led[0] = heartbeat_cnt[22];
assign led[8:1] = MASKED_OUTPUTS;
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod = 998244353; long long a[300001]; long long n, m, k; int b[300001]; void solve() { cin >> n; for (int i = 0; i < n; ++i) { int x; cin >> x; a[x]++; b[a[x]] += a[x]; k = (b[a[x]] >= i && b[a[x]] != n) ? b[a[x]] : k; } cout << k + 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; bool odd = false, even = false; cin >> n >> k; if (n & 1) { if (k > (n / 2 + 1)) { even = true; k -= (n / 2 + 1); } else odd = true; } else { if (k > n / 2) { even = true; k -= (n / 2); } else odd = true; } if (odd) cout << 2 * k - 1 << endl; else cout << 2 * k << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, c = 1; cin >> n >> t; int mn = INT_MAX; for (int i = 1; i <= n; i++) { int s, d; cin >> s >> d; while (s < t) { s += d; } if (s < mn) { mn = s; c = i; } } cout << c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mxn = 1e5 + 5; int n, a[mxn], c[mxn]; bool vis[mxn]; int main() { scanf( %d , &n); for (int(i) = (int)(1); (i) <= (int)(n); ++(i)) scanf( %d , a + i); int cnt = 0; for (int(i) = (int)(n); (i) >= (int)(1); --(i)) { c[i] = c[i + 1] + (vis[a[i]] == 0); vis[a[i]] = 1; } long long ans = 0; memset(vis, 0, sizeof(vis)); for (int(i) = (int)(1); (i) <= (int)(n); ++(i)) if (!vis[a[i]]) { vis[a[i]] = 1; ans += c[i + 1]; } return 0 * printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; const long long MAX = -1000000000000000000; const long long MIN = 1000000000000000000; const long long inf = 1000000000; const long long KOK = 100000; const long long LOG = 30; const long long li = 500005; const long long mod = 1000000007; int n, m, b[li], a[li], k, flag, t, yes, say, ind, cev1, mn, cev2; int cev; string s; vector<int> v; int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> s; for (int i = 0; i < (int)s.size(); i++) { if (s[i] == # ) { say++; ind = i; } } for (int i = 0; i < (int)s.size(); i++) { if (ind == i) { if (cev <= 0) { printf( -1 n ); return 0; } a[1] = cev; cev = 0; continue; } if (i > ind) { if (s[i] == ( ) cev++; else if (s[i] == ) && cev > 0) { cev--; } else if (s[i] == ) && a[1] > 1) { a[1]--; } else { printf( -1 n ); return 0; } } else { if (s[i] == ( ) cev++; else cev--; if (cev < 0) { printf( -1 n ); return 0; } } } if (cev > 0) { printf( -1 n ); return 0; } for (int i = 1; i < say; i++) printf( 1 n ); printf( %d n , a[1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); using ll = long long; template <typename T> void DEBUG(string label, T value) { cerr << [ << label << = << value << ] n ; } map<string, int> encode; map<int, string> decode; int m, n; vector<vector<int>> adj; void solve() { cin >> m; n = 0; for (int i = 0; i < m; ++i) { string a, b; cin >> a >> b; if (encode.count(a) == 0) { encode[a] = n; decode[n] = a; n++; } if (encode.count(b) == 0) { encode[b] = n; decode[n] = b; n++; } while (adj.size() < n) { adj.push_back(vector<int>()); } adj[encode[a]].push_back(encode[b]); adj[encode[b]].push_back(encode[a]); } cout << n << n ; for (int i = 0; i < n; ++i) { vector<bool> vis(n); vis[i] = true; for (int nxt : adj[i]) { vis[nxt] = true; } vector<int> cnt(n); for (int nxt : adj[i]) { for (int k : adj[nxt]) { if (!vis[k]) { cnt[k]++; } } } int mx = *max_element(cnt.begin(), cnt.end()); int ans = 0; for (int j = 0; j < n; ++j) { ans += (!vis[j] && cnt[j] == mx); } cout << decode[i] << << ans << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; t = 1; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; for (long long i = 1; i <= n; i++) { long long s, f, t; cin >> s >> f >> t; if (s == f) { cout << t << endl; } else if (s < f) { long long t1 = s - 1; while (t1 < t) { t1 += (m - s) + (m - 1) + (s - 1); } t1 += (f - s); cout << t1 << endl; } else if (s > f) { long long t1 = (m - 1) + (m - s); while (t1 < t) { t1 += (m - 1) + (m - s) + (s - 1); } t1 += (s - f); cout << t1 << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n; int A[N]; int main() { int t; scanf( %d , &t); while (t--) { scanf( %d , &n); n *= 2; for (int i = 1; i <= n; i++) { scanf( %d , &A[i]); } sort(A + 1, A + 1 + n); n /= 2; printf( %d n , A[n + 1] - A[n]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int T, n; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> T; while (T--) { cin >> n; set<long long int> chk_div; vector<long long int> g; for (long long int i = 0, u; i < n; i++) cin >> u, g.push_back(u); sort(g.begin(), g.end()); long long int p = (g[0] * g[n - 1]); for (long long int i = 2; i * i <= p; i++) if (!(p % i)) chk_div.insert(i), chk_div.insert(p / i); set<long long int> div(g.begin(), g.end()); (chk_div == div) ? (cout << p << n ) : (cout << -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; char c[1005], s[55], t[55]; int ns[55], nt[55]; int tos[55][30], tot[55][30]; int lenc, lens, lent; int dp[1005][55][55]; void init() { lenc = strlen(c + 1), lens = strlen(s + 1), lent = strlen(t + 1); ns[1] = 0, nt[1] = 0; for (int i = 2, j = 0; i <= lens; i++) { while (j && s[j + 1] != s[i]) j = ns[j]; if (s[j + 1] == s[i]) j++; ns[i] = j; } for (int i = 2, j = 0; i <= lent; i++) { while (j && t[j + 1] != t[i]) j = nt[j]; if (t[j + 1] == t[i]) j++; nt[i] = j; } for (int i = 0; i <= lens; i++) { for (int k = 0; k < 26; k++) { int j = i; while (j && s[j + 1] != k + a ) j = ns[j]; if (s[j + 1] == k + a ) j++; tos[i][k] = j; } } for (int i = 0; i <= lent; i++) { for (int k = 0; k < 26; k++) { int j = i; while (j && t[j + 1] != k + a ) j = nt[j]; if (t[j + 1] == k + a ) j++; tot[i][k] = j; } } } int main() { scanf( %s%s%s , c + 1, s + 1, t + 1); init(); int n = strlen(c + 1); for (int i = 0; i <= n; i++) for (int j = 0; j <= 50; j++) for (int k = 0; k <= 50; k++) dp[i][j][k] = -1000000; dp[0][0][0] = 0; for (int i = 1; i <= n; i++) { if (c[i] == * ) { for (int j = 0; j <= lens; j++) { for (int k = 0; k <= lent; k++) { if (dp[i - 1][j][k] <= -1000000) continue; for (int q = 0; q < 26; q++) { int temp1 = tos[j][q], temp2 = tot[k][q]; dp[i][temp1][temp2] = max(dp[i][temp1][temp2], dp[i - 1][j][k] + (temp1 == lens) - (temp2 == lent)); } } } } else { for (int j = 0; j <= lens; j++) { for (int k = 0; k <= lent; k++) { if (dp[i - 1][j][k] <= -1000000) continue; int q = c[i] - a ; int temp1 = tos[j][q], temp2 = tot[k][q]; dp[i][temp1][temp2] = max(dp[i][temp1][temp2], dp[i - 1][j][k] + (temp1 == lens) - (temp2 == lent)); } } } } int res = -1000000; for (int i = 0; i <= lens; i++) for (int j = 0; j <= lent; j++) res = max(res, dp[n][i][j]); cout << res << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { static int n; static int a[300010], b[300010]; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &a[i], &b[i]); int cnt[2] = {}; for (int i = 1; i <= n; i++) { if (a[i] < b[i]) cnt[0]++; else cnt[1]++; } if (cnt[0] > cnt[1]) { vector<pair<int, int> > vec; for (int i = 1; i <= n; i++) { if (a[i] < b[i]) vec.push_back(pair<int, int>(-a[i], i)); } sort(vec.begin(), vec.end()); printf( %d n , cnt[0]); for (int i = 0; i < vec.size(); i++) { printf( %d%c , vec[i].second, (i + 1 == vec.size()) ? n : ); } } else { vector<pair<int, int> > vec; for (int i = 1; i <= n; i++) { if (a[i] > b[i]) vec.push_back(pair<int, int>(b[i], i)); } sort(vec.begin(), vec.end()); printf( %d n , cnt[1]); for (int i = 0; i < vec.size(); i++) { printf( %d%c , vec[i].second, (i + 1 == vec.size()) ? n : ); } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
|
#include <bits/stdc++.h> int main() { int i, cnt1 = 0, l, diff, a, c, fck; scanf( %d%d , &a, &c); l = a; diff = 0; while (l > 0) { if (l % 3) diff += (3 - (l % 3)) * pow(3, cnt1); l /= 3; cnt1++; } cnt1 = 0; l = 0; while (c || diff) { fck = c + diff; l += fck % 3 * pow(3, cnt1); cnt1++; c /= 3; diff /= 3; } printf( %d , l); }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:31 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_0_stub.v
// Design : zynq_design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_regfile_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 31: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 31: 0] data_out;
wire [ 31: 0] out_port;
wire [ 31: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
module spmc_sd_card(
//*** Connections to SpartanMC Core (do not change) ***
input wire clk_peri, //System-Clock
input wire [17:0] do_peri, //Data Bus from MC
output [17:0] di_peri, //Data Bus to MC
input wire [9:0] addr_peri, //Address Bus from MC
input wire access_peri, //Peripheral Access Signal
input wire wr_peri, //Write Enable Signal
//*** Connections to SpartanMC Core which can be changed ***
input wire reset, //Reset-Signal (could be external)
// BlockRAM interface
input mem_clk, //BRAM clk
input mem_access,
input store_access,
input store_access_low,
input store_access_high,
input [7:0] addr_high,
//*** io interface ***
input wire sd_miso,
output wire sd_mosi,
output wire sd_clk,
output wire sd_cs,
output wire ts_dummy
);
parameter BASE_ADR = 10'h0;
parameter DMA_BASE_ADR = 18'h19c00; //1024 addresses below IO ports
parameter CLOCK_FREQUENCY = 16000000;
assign ts_dummy = 1'b1;
wire [17:0] di_peri_dma;
wire select;
// Address decoder generates the select sinal out of the upper part of the peripheral address.
pselect iCSL (
.addr ( addr_peri[9:3] ),
.activ_peri ( access_peri ),
.select ( select )
);
defparam iCSL.ADDR_WIDTH = 7;
defparam iCSL.BASE_WIDTH = 7;
defparam iCSL.BASE_ADDR = BASE_ADR >> 3; //BASE_ADR has to be divisible by 8
//delay read signal by one cycle (for new pipeline), data is already generated in this cycle by sdcard module
reg reg_read;
always @(posedge clk_peri) begin
reg_read <= select & !wr_peri;
end
wire [17:0] sd_dat_out;
reg [17:0] sd_dat_out_last;
wire [17:0] sd_dat_out_spmc;
assign sd_dat_out_spmc = sd_dat_out_last;
assign di_peri = (reg_read ? sd_dat_out_spmc : 18'b0) | di_peri_dma;
always @(posedge clk_peri) begin
sd_dat_out_last <= sd_dat_out;
end
spiMaster sdcard(
.clk_i(clk_peri),
.rst_i(reset),
.address_i(addr_peri[2:0]),
.data_i(do_peri[17:0]),
.data_o(sd_dat_out),
.select(select),
.we_i(wr_peri),
// SPI logic clock
.spiSysClk(clk_peri),
//SPI bus
.spiClkOut(sd_clk),
.spiDataIn(sd_miso),
.spiDataOut(sd_mosi),
.spiCS_n(sd_cs),
.do_peri(do_peri),
.di_peri(di_peri_dma),
.addr_peri(addr_peri),
.mem_clk(mem_clk),
.mem_access(mem_access),
.store_access(store_access | store_access_low),
.addr_high(addr_high)
);
defparam sdcard.SDCARD_CLOCK = CLOCK_FREQUENCY;
defparam sdcard.u_readWriteSDBlock.SDCARD_CLOCK = CLOCK_FREQUENCY;
defparam sdcard.u_spiMasterSpmcBI.SDCARD_CLOCK = CLOCK_FREQUENCY;
defparam sdcard.DMA_ADR = DMA_BASE_ADR;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using dd = double; using pii = pair<int, int>; using pll = pair<ll, ll>; ll INFLL = (ll)2e18, MOD = 1e9 + 7; const int INF = 0x6f6f6f6f; vector<vector<ll>> adj; vector<int> vis; int dx8[] = {0, 1, 1, 1, 0, -1, -1, -1}, dy8[] = {1, 1, 0, -1, -1, -1, 0, 1}, dx4[] = {0, 1, 0, -1}, dy4[] = {1, 0, -1, 0}; inline ll mexp(ll x, ll n, ll m) { ll res = 1; while (n) { if (n & 1) res = (res * x) % m; n >>= 1; x = ((x % m) * (x % m)) % m; } return res; } inline bool ispow2(ll x) { return x && (!(x & (x - 1))); } inline ll gcd(ll x, ll y) { pll p{x, y}; while (p.second) p = {p.second, p.first % p.second}; return p.first; } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed; cerr << fixed; cout << setprecision(10); cerr << setprecision(3); mt19937 genr(chrono::high_resolution_clock::now().time_since_epoch().count()); int n; cin >> n; vector<int> seq(n + 1); map<int, int> m; for (int i = 0; i < n; ++i) { int t; cin >> t; m[t] = i + 1; } int ct = 1; for (auto& e : m) seq[e.second] = ct++; m.clear(); vector<ll> tree(n + 1, 0); auto sum = [&](int pos) { ll ret = 0; while (pos) { ret += tree[pos]; pos -= pos & -pos; } return ret; }; auto upd = [&](int pos, ll val) { while (pos <= n) { tree[pos] += val; pos += pos & -pos; } }; ll ans = 0; for (int i = 1; i <= n; ++i) { ll gr = sum(n) - sum(seq[i]); ll le = seq[i] - 1 - sum(seq[i] - 1); ans += gr * le; upd(seq[i], 1); } cout << ans << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND3B_FUNCTIONAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:57:32 09/24/2013
// Design Name: Debounce
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_debounce.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Debounce
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_debounce;
// Inputs
reg clock;
reg reset;
reg [1:0] write_data_selector;
// Outputs
wire reset_sync;
wire [1:0] write_data_selector_sync;
// Instantiate the Unit Under Test (UUT)
Debounce uut (
.clock(clock),
.reset(reset),
.write_data_selector(write_data_selector),
.reset_sync(reset_sync),
.write_data_selector_sync(write_data_selector_sync)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
write_data_selector = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char orz[500001]; int gg[500001]; int t; int main() { cin >> t; while (t--) { int n, q; scanf( %d%d , &n, &q); scanf( %s , orz + 1); int rrr = 1; for (int i = 1; i <= n; i++) { if (orz[i] == + ) gg[i] = gg[i - 1] + 1 * rrr; else gg[i] = gg[i - 1] - 1 * rrr; rrr *= -1; } while (q--) { int l, r; scanf( %d%d , &l, &r); int eee = abs(gg[r] - gg[l - 1]); if (eee != 0) { if (eee % 2 == 1) eee = 1; if (eee % 2 == 0) eee = 2; } cout << eee << endl << endl; } } }
|
#include <bits/stdc++.h> using namespace std; bool debug = false; int n, m, k; int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; long long ln, lk, lm; int a[10]; bool v[9], vv[9]; bool walk(int x) { v[x] = 1; if (a[x] == 1 || vv[a[x]]) return vv[x] = 1; if (v[a[x]]) return 0; return vv[x] = walk(a[x]); } bool ck() { for (int i = 2; i <= k; i++) { v[i] = 0; vv[i] = 0; } for (int i = 2; i <= k; i++) if (!v[i]) { if (!walk(i)) { return 0; } } return 1; } long long tmp; void dfs(int x) { if (x == k + 1) { if (ck()) tmp++; return; } for (int(i) = 1; (i) <= (int)(k); (i)++) if (i != x) { a[x] = i; dfs(x + 1); } } int main() { scanf( %d%d , &n, &k); long long ans = k; dfs(2); (ans *= tmp) %= 1000000007; m = n - k; for (int i = k + 1; i <= n; i++) { (ans *= m) %= 1000000007; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> int n, k, a[100001], is[100001], i, j, sum, ans; int main() { scanf( %d %d , &n, &k); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < n; i++) scanf( %d , &is[i]); for (i = 0; i < k; i++) sum += a[i]; for (i = k; i < n; i++) if (is[i]) sum += a[i]; ans = sum; for (i = 0; i < n - k + 1; i++) { if (is[i] == 0) sum -= a[i]; if (is[i + k] == 0) sum += a[i + k]; if (ans < sum) ans = sum; } printf( %d , ans); }
|
#include <bits/stdc++.h> char gb[65536], pb[65536], *gp = gb + 65536, *pp = pb, a[2][2005], s[2005]; int _5[65], n = 0, m = 0, f[2][2005][2005]; long long seed[2005]; inline void add(int &x, int y) { x += y; if (x >= 1e9 + 7) x -= 1e9 + 7; } inline int gline(char *b) { char c = getchar(); int len = 0; for (; !(((c)&64)); c = getchar()) ; for (; ((c)&64); b[++len] = c, c = getchar()) ; b[++len] = 0; return len - 1; } inline void init() { seed[0] = 1; for (int i = 1; i <= 2005; i++) seed[i] = seed[i - 1] * 31 % 19260817; } inline void reverse(char *str, int len) { if (!str) return; for (register int i = 0; i < (len >> 1); i++) { char temp = *(str + i); *(str + i) = *(str + len - 1 - i); *(str + len - 1 - i) = temp; } } struct hash { long long h[2005]; inline void make(int n, char *b) { h[0] = 0; for (register int i = 1; i <= n; i++) h[i] = (h[i - 1] * 31 + b[i] - a ) % 19260817; } inline void make_r(int n, char *b) { h[0] = 0; for (register int i = 1; i <= n; i++) h[i] = (h[i - 1] * 31 + b[n + 1 - i] - a ) % 19260817; } inline long long cut(int l, int r) { return (h[r] + 19260817 - h[l - 1] * seed[r - l + 1] % 19260817) % 19260817; } } pre[2], suf[2], ss; inline void __input() { n = gline(a[0]); pre[0].make(n, a[0]); suf[0].make_r(n, a[0]); n = gline(a[1]); pre[1].make(n, a[1]); suf[1].make_r(n, a[1]); m = gline(s); ss.make(m, s); } inline int solve(int flag) { int ret = 0; memset(f, 0, sizeof(f)); for (register int j = 1; j <= n; j++) { f[0][j][0] = f[1][j][0] = 1; for (int k = 2; k <= (((n - j + 1) < ((m >> 1))) ? (n - j + 1) : ((m >> 1))); k++) if (ss.cut(m - (k << 1) + 1, m - k) == pre[0].cut(j, j + k - 1) && ss.cut(m - k + 1, m) == suf[1].cut(n - (j + k) + 2, n - j + 1)) if ((k << 1) != m || flag) add(ret, f[0][j][m - (k << 1)]); for (int k = 2; k <= (((n - j + 1) < ((m >> 1))) ? (n - j + 1) : ((m >> 1))); k++) if (ss.cut(m - (k << 1) + 1, m - k) == pre[1].cut(j, j + k - 1) && ss.cut(m - k + 1, m) == suf[0].cut(n - (j + k) + 2, n - j + 1)) if ((k << 1) != m || flag) add(ret, f[1][j][m - (k << 1)]); for (int k = 2; k <= (((j) < ((m >> 1))) ? (j) : ((m >> 1))); k++) if (ss.cut(k + 1, (k << 1)) == pre[0].cut(j - k + 1, j) && ss.cut(1, k) == suf[1].cut(n - j + 1, n - (j - k))) if ((k << 1) != m || flag) add(f[0][j + 1][(k << 1)], 1); for (int k = 2; k <= (((j) < ((m >> 1))) ? (j) : ((m >> 1))); k++) if (ss.cut(k + 1, (k << 1)) == pre[1].cut(j - k + 1, j) && ss.cut(1, k) == suf[0].cut(n - j + 1, n - (j - k))) if ((k << 1) != m || flag) add(f[1][j + 1][(k << 1)], 1); for (int k = 0; k < m; k++) if (a[0][j] == s[k + 1]) { add(f[0][j + 1][k + 1], f[0][j][k]); if (k + 2 <= m && a[1][j] == s[k + 2]) add(f[1][j + 1][k + 2], f[0][j][k]); } for (int k = 0; k < m; k++) if (a[1][j] == s[k + 1]) { add(f[1][j + 1][k + 1], f[1][j][k]); if (k + 2 <= m && a[0][j] == s[k + 2]) add(f[0][j + 1][k + 2], f[1][j][k]); } add(ret, f[0][j + 1][m]); add(ret, f[1][j + 1][m]); } return ret; } int main() { init(); __input(); int register ans = 0; add(ans, solve(1)); if (m > 1) { reverse(s + 1, m); ss.make(m, s); add(ans, solve(0)); if (m == 2) for (int j = 1; j <= n; j++) for (int i = 0; i < 2; i++) if (a[i][j] == s[1] && a[i ^ 1][j] == s[2]) add(ans, 1e9 + 7 - 1); } printf( %d , ans); ; return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, map<int, int> > m; long long int lol(long long int a, long long int r) { if (a >= 0 && r <= 0) return a; if (a <= 0 && r >= 0) return a; return a % r; } int main() { long long int a, b; cin >> a >> b; string s; cin >> s; long x = 0; long y = 0; if (a == 0 && b == 0) { cout << Yes << endl; return 0; } for (long i = 0; i < s.size(); i++) { if (s[i] == L ) x--; if (s[i] == R ) x++; if (s[i] == U ) y++; if (s[i] == D ) y--; } long p = 2; long w = 0; long q = 0; int d = 0; for (long i = 0; i < s.size(); i++) { if (s[i] == L ) w--; if (s[i] == R ) w++; if (s[i] == U ) q++; if (s[i] == D ) q--; long long int u = a - w; long long int e = b - q; if (x != 0) { if (y != 0) { long long int v = u / x; long long int z = e / y; if (v == z && v >= 0 && u % x == 0 && e % y == 0) d = 1; } else { long long int v = a / x; if (e == 0 && v >= 0 && u % x == 0) d = 1; } } else { if (y != 0) { long long int z = e / y; if (z >= 0 && u == 0 && e % y == 0) d = 1; } else { if (u == 0 && e == 0) d = 1; } } } if (d == 1) cout << Yes << endl; else cout << No << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, k; cin >> n >> k; string s; cin >> s; string ss = s; int iter = 0; int total = 0; while (true) { int cnt = 0; for (int i = 1; i < n; i++) if (s[i - 1] == R && s[i] == L ) { s[i - 1] = L ; s[i] = R ; cnt++; i++; } if (cnt == 0) break; iter++; total += cnt; } if (k < iter || k > total) { cout << -1 << endl; return 0; } s = ss; int slow = k - iter; while (true) { int cnt = 0; vector<int> res; for (int i = 1; i < n; i++) if (s[i - 1] == R && s[i] == L ) { s[i - 1] = L ; s[i] = R ; cnt++; if (slow > 0) { slow--; cout << 1 << i << n ; } else { res.push_back(i); } i++; } if (cnt == 0) break; if (res.size() > 0) { cout << res.size(); for (int i = 0; i < res.size(); i++) cout << << res[i]; cout << n ; } else { slow++; } } cout.flush(); return 0; }
|
// Generated by altmemphy 11.0 [Altera, IP Toolbench 1.3.0 Build 208]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_s4_amphy_phy (
pll_ref_clk,
global_reset_n,
soft_reset_n,
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_doing_rd,
ctl_cal_req,
ctl_mem_clk_disable,
mem_err_out_n,
ctl_cal_byte_lane_sel_n,
oct_ctl_rs_value,
oct_ctl_rt_value,
dqs_offset_delay_ctrl,
dqs_delay_ctrl_import,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
pll_reconfig_enable,
pll_phasecounterselect,
pll_phaseupdown,
pll_phasestep,
hc_scan_enable_access,
hc_scan_enable_dq,
hc_scan_enable_dm,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_din,
hc_scan_update,
hc_scan_ck,
reset_request_n,
ctl_clk,
ctl_reset_n,
ctl_wlat,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
mem_ac_parity,
parity_error_n,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_reset_n,
dqs_delay_ctrl_export,
dll_reference_clk,
aux_half_rate_clk,
aux_full_rate_clk,
aux_scan_clk,
aux_scan_clk_reset_n,
dbg_rd_data,
dbg_waitrequest,
pll_phase_done,
hc_scan_dout,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqs_n);
input pll_ref_clk;
input global_reset_n;
input soft_reset_n;
input [1:0] ctl_dqs_burst;
input [1:0] ctl_wdata_valid;
input [31:0] ctl_wdata;
input [3:0] ctl_dm;
input [25:0] ctl_addr;
input [5:0] ctl_ba;
input [1:0] ctl_cas_n;
input [1:0] ctl_cke;
input [1:0] ctl_cs_n;
input [1:0] ctl_odt;
input [1:0] ctl_ras_n;
input [1:0] ctl_we_n;
input [1:0] ctl_rst_n;
input [1:0] ctl_doing_rd;
input ctl_cal_req;
input [0:0] ctl_mem_clk_disable;
input mem_err_out_n;
input [0:0] ctl_cal_byte_lane_sel_n;
input [13:0] oct_ctl_rs_value;
input [13:0] oct_ctl_rt_value;
input [5:0] dqs_offset_delay_ctrl;
input [5:0] dqs_delay_ctrl_import;
input dbg_clk;
input dbg_reset_n;
input [12:0] dbg_addr;
input dbg_wr;
input dbg_rd;
input dbg_cs;
input [31:0] dbg_wr_data;
input pll_reconfig_enable;
input [3:0] pll_phasecounterselect;
input pll_phaseupdown;
input pll_phasestep;
input hc_scan_enable_access;
input [7:0] hc_scan_enable_dq;
input [0:0] hc_scan_enable_dm;
input [0:0] hc_scan_enable_dqs;
input [0:0] hc_scan_enable_dqs_config;
input [0:0] hc_scan_din;
input [0:0] hc_scan_update;
input hc_scan_ck;
output reset_request_n;
output ctl_clk;
output ctl_reset_n;
output [4:0] ctl_wlat;
output [31:0] ctl_rdata;
output [1:0] ctl_rdata_valid;
output [4:0] ctl_rlat;
output ctl_cal_success;
output ctl_cal_fail;
output ctl_cal_warning;
output mem_ac_parity;
output parity_error_n;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_cas_n;
output [0:0] mem_cke;
output [0:0] mem_cs_n;
output [0:0] mem_dm;
output [0:0] mem_odt;
output mem_ras_n;
output mem_we_n;
output mem_reset_n;
output [5:0] dqs_delay_ctrl_export;
output dll_reference_clk;
output aux_half_rate_clk;
output aux_full_rate_clk;
output aux_scan_clk;
output aux_scan_clk_reset_n;
output [31:0] dbg_rd_data;
output dbg_waitrequest;
output pll_phase_done;
output [7:0] hc_scan_dout;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [7:0] mem_dq;
inout [0:0] mem_dqs;
inout [0:0] mem_dqs_n;
endmodule
|
`include "hglobal.v"
`default_nettype none
`define NS_NUM_TEST 12
`define NS_SEL_HALFBYTE(ii) ii*4 +: 4
module test_top
#(parameter
PSZ=`NS_PACKET_SIZE,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input i_clk,
input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4,
output io_PMOD_1,
output io_PMOD_2,
output io_PMOD_3,
output io_PMOD_4,
output io_PMOD_7,
output io_PMOD_8,
output io_PMOD_9,
output io_PMOD_10
);
wire w_Switch_1;
reg r_Switch_1 = `NS_OFF;
wire w_Switch_2;
reg r_Switch_2 = `NS_OFF;
wire w_Switch_3;
reg r_Switch_3 = `NS_OFF;
wire w_Switch_4;
reg r_Switch_4 = `NS_OFF;
localparam TOT_DEBOUNCE_CLICK = 250000; // 10 ms at 25 MHz
reg [0:0] reset = 0;
wire ready;
`NS_DECLARE_GLB_LINK(gch0)
assign gch0_clk = i_clk;
assign gch0_reset = reset;
`NS_DEBOUNCER_DBG_BUT(gch0, 1)
`NS_DEBOUNCER_DBG_BUT(gch0, 2)
`NS_DEBOUNCER_DBG_BUT(gch0, 3)
`NS_DEBOUNCER_DBG_BUT(gch0, 4)
wire w_Segment1_A;
wire w_Segment1_B;
wire w_Segment1_C;
wire w_Segment1_D;
wire w_Segment1_E;
wire w_Segment1_F;
wire w_Segment1_G;
wire w_Segment2_A;
wire w_Segment2_B;
wire w_Segment2_C;
wire w_Segment2_D;
wire w_Segment2_E;
wire w_Segment2_F;
wire w_Segment2_G;
localparam TOT_BITS_CNTR = 64;
reg [0:0] mul_clock = 0;
reg [TOT_BITS_CNTR - 1:0] tik_count = 0;
reg [TOT_BITS_CNTR - 1:0] lim_tiks_up = 64'h00_00_00_00_00_00_00_FF;
reg [TOT_BITS_CNTR - 1:0] lim_tiks_down = 64'h00_00_00_00_00_00_00_FF;
always @(posedge i_clk)
begin
if(mul_clock) begin
if(tik_count == lim_tiks_up) begin
tik_count <= 0;
mul_clock <= 0;
end
else begin
tik_count <= tik_count + 1;
end
end
else
begin
if(tik_count == lim_tiks_down) begin
tik_count <= 0;
mul_clock <= 1;
end
else begin
tik_count <= tik_count + 1;
end
end
end
wire sw1_ON = ((w_Switch_1 == `NS_ON) && (r_Switch_1 == `NS_OFF));
wire sw1_OFF = ((w_Switch_1 == `NS_OFF) && (r_Switch_1 == `NS_ON));
wire sw2_ON = ((w_Switch_2 == `NS_ON) && (r_Switch_2 == `NS_OFF));
wire sw2_OFF = ((w_Switch_2 == `NS_OFF) && (r_Switch_2 == `NS_ON));
wire sw3_ON = ((w_Switch_3 == `NS_ON) && (r_Switch_3 == `NS_OFF));
wire sw3_OFF = ((w_Switch_3 == `NS_OFF) && (r_Switch_3 == `NS_ON));
wire sw4_ON = ((w_Switch_4 == `NS_ON) && (r_Switch_4 == `NS_OFF));
wire sw4_OFF = ((w_Switch_4 == `NS_OFF) && (r_Switch_4 == `NS_ON));
reg [0:0] changing = 0;
reg [0:0] cicles_up = 0;
reg [3:0] up_byte_to_disp = 0;
reg [3:0] down_byte_to_disp = 0;
wire [3:0] byte_to_disp = (cicles_up)?(up_byte_to_disp):(down_byte_to_disp);
wire [3:0] byte_val_to_disp = (cicles_up)?(lim_tiks_up[`NS_SEL_HALFBYTE(byte_to_disp)]):(lim_tiks_down[`NS_SEL_HALFBYTE(byte_to_disp)]);
always @(posedge i_clk)
begin
r_Switch_1 <= w_Switch_1;
r_Switch_2 <= w_Switch_2;
r_Switch_3 <= w_Switch_3;
r_Switch_4 <= w_Switch_4;
// cnt_clk <= (cnt_clk << 1);
// lim_tiks_up <= lim_tiks_up + 1;
if(sw1_ON)
begin
if(! changing) begin
if(cicles_up) begin
up_byte_to_disp <= up_byte_to_disp + 1;
end
else
begin
down_byte_to_disp <= down_byte_to_disp + 1;
end
end
else
begin
if(cicles_up) begin
lim_tiks_up[`NS_SEL_HALFBYTE(up_byte_to_disp)] <= lim_tiks_up[`NS_SEL_HALFBYTE(up_byte_to_disp)] + 1;
end
else
begin
lim_tiks_down[`NS_SEL_HALFBYTE(down_byte_to_disp)] <= lim_tiks_down[`NS_SEL_HALFBYTE(down_byte_to_disp)] + 1;
end
end
end
else
if(sw2_ON) begin
if(! changing) begin
if(cicles_up) begin
up_byte_to_disp <= up_byte_to_disp - 1;
end
else
begin
down_byte_to_disp <= down_byte_to_disp - 1;
end
end
else
begin
if(cicles_up) begin
lim_tiks_up[`NS_SEL_HALFBYTE(up_byte_to_disp)] <= lim_tiks_up[`NS_SEL_HALFBYTE(up_byte_to_disp)] - 1;
end
else
begin
lim_tiks_down[`NS_SEL_HALFBYTE(down_byte_to_disp)] <= lim_tiks_down[`NS_SEL_HALFBYTE(down_byte_to_disp)] - 1;
end
end
end
else if(sw3_ON) begin
`ns_bit_toggle(cicles_up);
end
else if(sw4_ON) begin
`ns_bit_toggle(changing);
end
end
bin_to_disp disp_0(
.i_Clk(i_clk),
.i_Binary_Num(byte_to_disp),
.o_Segment_A(w_Segment1_A),
.o_Segment_B(w_Segment1_B),
.o_Segment_C(w_Segment1_C),
.o_Segment_D(w_Segment1_D),
.o_Segment_E(w_Segment1_E),
.o_Segment_F(w_Segment1_F),
.o_Segment_G(w_Segment1_G)
);
bin_to_disp disp1(
.i_Clk(i_clk),
.i_Binary_Num(byte_val_to_disp),
.o_Segment_A(w_Segment2_A),
.o_Segment_B(w_Segment2_B),
.o_Segment_C(w_Segment2_C),
.o_Segment_D(w_Segment2_D),
.o_Segment_E(w_Segment2_E),
.o_Segment_F(w_Segment2_F),
.o_Segment_G(w_Segment2_G)
);
assign o_Segment1_A = ~w_Segment1_A;
assign o_Segment1_B = ~w_Segment1_B;
assign o_Segment1_C = ~w_Segment1_C;
assign o_Segment1_D = ~w_Segment1_D;
assign o_Segment1_E = ~w_Segment1_E;
assign o_Segment1_F = ~w_Segment1_F;
assign o_Segment1_G = ~w_Segment1_G;
assign o_Segment2_A = ~w_Segment2_A;
assign o_Segment2_B = ~w_Segment2_B;
assign o_Segment2_C = ~w_Segment2_C;
assign o_Segment2_D = ~w_Segment2_D;
assign o_Segment2_E = ~w_Segment2_E;
assign o_Segment2_F = ~w_Segment2_F;
assign o_Segment2_G = ~w_Segment2_G;
assign o_LED_1 = cicles_up; // showing (#tiks up) VS showing (#tiks down)
assign o_LED_2 = changing; // changing current 'byte_val_to_disp' VS changing 'byte_to_disp'
assign o_LED_3 = 0;
assign o_LED_4 = 0;
assign io_PMOD_1 = mul_clock;
assign io_PMOD_2 = mul_clock;
assign io_PMOD_3 = mul_clock;
assign io_PMOD_4 = mul_clock;
assign io_PMOD_7 = 0;
assign io_PMOD_8 = 0;
assign io_PMOD_9 = 0;
assign io_PMOD_10 = 0;
endmodule
/*
PMOD pins looking from the front:
V3.2 GND p4 p3 p2 p1
V3.2 GND p10 p9 p8 p7
*/
|
#include <bits/stdc++.h> using namespace std; long long a[1000005] = {1, 1}, b[1000005], num; long long x2, ans = 100000000; void init() { long long i, j; for (i = 2; i <= 1000000; i++) { if (a[i]) continue; for (j = i * i; j <= 1000000; j += i) a[j] = 1; } for (i = 1; i <= 1000000; i++) if (a[i] == 0) b[++num] = i; } int main(void) { init(); scanf( %lld , &x2); long long x = x2, p = 0; for (long long i = 1; b[i] * b[i] <= x; i++) while (x % b[i] == 0) x /= b[i], p = b[i]; if (x != 1) p = x; for (long long i = x2 - p + 1; i <= x2; i++) { long long tmp = i; long long pp = p; for (long long j = 1; b[j] * b[j] <= tmp; j++) while (tmp % b[j] == 0) tmp /= b[j], pp = b[j]; if (tmp != 1) pp = tmp; if (pp == i) continue; ans = min(ans, i - pp + 1); } printf( %lld n , ans); return 0; }
|
`timescale 1 ns / 1 ps
`include "axi_i2s_adi_v1_2_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module axi_i2s_adi_v1_2_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; int inf = 1e9; double eps = 1e-6; int main() { int n, k; cin >> n >> k; vector<int> a; for (int i = 0; i < n; i++) { int t; cin >> t; a.push_back(t); } if (k == 1) { int ans = a[0]; for (int i = 1; i < n; i++) { ans = min(ans, a[i]); } cout << ans; } else if (k > 2) { int ans = a[0]; for (int i = 1; i < n; i++) { ans = max(ans, a[i]); } cout << ans; } else { int ans = INT_MIN; multiset<int> p; multiset<int> q; p.insert(a[0]); for (int i = 1; i < n; i++) { q.insert(a[i]); } ans = max(ans, max(*q.begin(), *p.begin())); for (int i = 1; i < n - 1; i++) { p.insert(a[i]); q.erase(q.find(a[i])); ans = max(ans, max(*q.begin(), *p.begin())); } cout << ans; } return 0; }
|
/**
* @module alu
* @author sabertazimi
* @email
* @param DATA_WIDTH data width
* @input srcA A port data
* @input srcB B port data
* @input aluop operation code
* @output aluout calculation result
* @output zero equal flag
* @output of signed overflow flag
* @output uof unsigned overflow flag
*/
module alu
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output reg [DATA_WIDTH-1:0] aluout,
output zero,
output of,
output uof
);
wire signed [DATA_WIDTH-1:0] signed_srcA;
wire signed [DATA_WIDTH-1:0] signed_srcB;
assign signed_srcA = $signed(srcA);
assign signed_srcB = $signed(srcB);
always @ ( * ) begin
case (aluop)
4'd0: aluout <= srcA << srcB;
4'd1: aluout <= signed_srcA >>> srcB;
4'd2: aluout <= srcA >> srcB;
4'd3: aluout <= srcA * srcB;
4'd4: aluout <= srcA / srcB;
4'd5: aluout <= srcA + srcB; // awesome tip
4'd6: aluout <= srcA - srcB;
4'd7: aluout <= srcA & srcB;
4'd8: aluout <= srcA | srcB;
4'd9: aluout <= srcA ^ srcB;
4'd10: aluout <= ~(srcA | srcB);
4'd11: aluout <= (signed_srcA < signed_srcB) ? 1 : 0;
4'd12: aluout <= (srcA < srcB) ? 1 : 0;
default: aluout <= 0;
endcase
end
alu_flags #(
.DATA_WIDTH(DATA_WIDTH)
) FLAGS (
.srcA(srcA),
.srcB(srcB),
.aluop(aluop),
.zero(zero),
.of(of),
.uof(uof)
);
endmodule // alu
|
//////////////////////////////////////////////////////////////////////
//// ////
//// or1200_fpu_pre_norm_addsub ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// pre-normalization entity for the addition/subtraction unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module or1200_fpu_pre_norm_addsub (
clk_i,
opa_i,
opb_i,
fracta_28_o,
fractb_28_o,
exp_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk_i;
input [FP_WIDTH-1:0] opa_i;
input [FP_WIDTH-1:0] opb_i;
// carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
output reg [FRAC_WIDTH+4:0] fracta_28_o;
output reg [FRAC_WIDTH+4:0] fractb_28_o;
output reg [EXP_WIDTH-1:0] exp_o;
reg [EXP_WIDTH-1 : 0] s_exp_o ;
wire [FRAC_WIDTH+4 : 0] s_fracta_28_o, s_fractb_28_o ;
wire [EXP_WIDTH-1 : 0] s_expa;
wire [EXP_WIDTH-1 : 0] s_expb ;
wire [FRAC_WIDTH-1 : 0] s_fracta;
wire [FRAC_WIDTH-1 : 0] s_fractb ;
wire [FRAC_WIDTH+4 : 0] s_fracta_28;
wire [FRAC_WIDTH+4 : 0] s_fractb_28 ;
wire [FRAC_WIDTH+4 : 0] s_fract_sm_28;
wire [FRAC_WIDTH+4 : 0] s_fract_shr_28 ;
reg [EXP_WIDTH-1 : 0] s_exp_diff ;
reg [5 : 0] s_rzeros ;
wire s_expa_eq_expb;
wire s_expa_gt_expb;
wire s_fracta_1;
wire s_fractb_1;
wire s_op_dn,s_opa_dn, s_opb_dn;
wire [1 : 0] s_mux_diff ;
wire s_mux_exp;
wire s_sticky;
assign s_expa = opa_i[30:23];
assign s_expb = opb_i[30:23];
assign s_fracta = opa_i[22:0];
assign s_fractb = opb_i[22:0];
always @(posedge clk_i)
begin
exp_o <= s_exp_o;
fracta_28_o <= s_fracta_28_o;
fractb_28_o <= s_fractb_28_o;
end
assign s_expa_eq_expb = (s_expa == s_expb);
assign s_expa_gt_expb = (s_expa > s_expb);
// '1' if fraction is not zero
assign s_fracta_1 = |s_fracta;
assign s_fractb_1 = |s_fractb;
// opa or Opb is denormalized
assign s_opa_dn = !(|s_expa);
assign s_opb_dn = !(|s_expb);
assign s_op_dn = s_opa_dn | s_opb_dn;
// Output larger exponent
assign s_mux_exp = s_expa_gt_expb;
always @(posedge clk_i)
s_exp_o <= s_mux_exp ? s_expa : s_expb;
// convert to an easy to handle floating-point format
assign s_fracta_28 = s_opa_dn ?
{2'b00, s_fracta, 3'b000} : {2'b01, s_fracta, 3'b000};
assign s_fractb_28 = s_opb_dn ?
{2'b00, s_fractb, 3'b000} : {2'b01, s_fractb, 3'b000};
assign s_mux_diff = {s_expa_gt_expb, s_opa_dn ^ s_opb_dn};
// calculate howmany postions the fraction will be shifted
always @(posedge clk_i)
begin
case(s_mux_diff)
2'b00: s_exp_diff <= s_expb - s_expa;
2'b01: s_exp_diff <= s_expb - (s_expa + 8'd1);
2'b10: s_exp_diff <= s_expa - s_expb;
2'b11: s_exp_diff <= s_expa - (s_expb + 8'd1);
endcase
end
assign s_fract_sm_28 = s_expa_gt_expb ? s_fractb_28 : s_fracta_28;
// shift-right the fraction if necessary
assign s_fract_shr_28 = s_fract_sm_28 >> s_exp_diff;
// count the zeros from right to check if result is inexact
always @(s_fract_sm_28)
casez(s_fract_sm_28) // synopsys full_case parallel_case
28'b???????????????????????????1: s_rzeros = 0;
28'b??????????????????????????10: s_rzeros = 1;
28'b?????????????????????????100: s_rzeros = 2;
28'b????????????????????????1000: s_rzeros = 3;
28'b???????????????????????10000: s_rzeros = 4;
28'b??????????????????????100000: s_rzeros = 5;
28'b?????????????????????: s_rzeros = 6;
28'b????????????????????10000000: s_rzeros = 7;
28'b???????????????????100000000: s_rzeros = 8;
28'b??????????????????: s_rzeros = 9;
28'b?????????????????10000000000: s_rzeros = 10;
28'b????????????????100000000000: s_rzeros = 11;
28'b???????????????1000000000000: s_rzeros = 12;
28'b??????????????10000000000000: s_rzeros = 13;
28'b?????????????100000000000000: s_rzeros = 14;
28'b????????????1000000000000000: s_rzeros = 15;
28'b???????????10000000000000000: s_rzeros = 16;
28'b??????????100000000000000000: s_rzeros = 17;
28'b?????????1000000000000000000: s_rzeros = 18;
28'b????????10000000000000000000: s_rzeros = 19;
28'b???????100000000000000000000: s_rzeros = 20;
28'b??????1000000000000000000000: s_rzeros = 21;
28'b?????10000000000000000000000: s_rzeros = 22;
28'b????100000000000000000000000: s_rzeros = 23;
28'b???1000000000000000000000000: s_rzeros = 24;
28'b??10000000000000000000000000: s_rzeros = 25;
28'b?100000000000000000000000000: s_rzeros = 26;
28'b1000000000000000000000000000: s_rzeros = 27;
28'b0000000000000000000000000000: s_rzeros = 28;
endcase // casex (s_fract_sm_28)
assign s_sticky = (s_exp_diff > {2'b00,s_rzeros}) & (|s_fract_sm_28);
assign s_fracta_28_o = s_expa_gt_expb ?
s_fracta_28 :
{s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])};
assign s_fractb_28_o = s_expa_gt_expb ?
{s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])} :
s_fractb_28;
endmodule // or1200_fpu_pre_norm_addsub
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_2_V
`define SKY130_FD_SC_HS__NOR4_2_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_2_V
|
#include <bits/stdc++.h> using namespace std; int dp[550005]; int main() { int n, d, c, i, j, x, flog; scanf( %d %d , &n, &d); dp[0] = 1; for (i = 0; i < n; i++) { scanf( %d , &c); for (j = 500000; j >= c; j--) { dp[j] |= dp[j - c]; } } int day = 0; x = 0; while (1) { flog = 0; for (j = x + d; j > x; j--) { if (dp[j]) { flog = 1; day++; x = j; break; } } if (!flog) break; } printf( %d %d n , x, day); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N8_M4_P4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N8_M4_P4(
input [7:0] in1,
input [7:0] in2,
output [8:0] res
);
wire [2:0] temp1, temp2, temp3, temp4;
wire carry_pred_1,carry_pred_2;
//C2
wire g0,g1,p0,p1;
wire p1g0;
wire c2;
and and_0(g0,in1[0],in2[0]);
and and_1(g1,in1[1],in2[1]);
xor xor_0(p0,in1[0],in2[0]);
xor xor_1(p1,in1[1],in2[1]);
and and_2(p1g0,p1,g0);
or or_1 (c2,g1,p1g0);
//C4
wire g2,g3,p2,p3;
wire p3g2;
wire c4,p3p2,p3p2c2;
and and_3(g2,in1[2],in2[2]);
and and_4(g3,in1[3],in2[3]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_3(p3,in1[3],in2[3]);
and and_5(p3g2,p3,g2);
or or_2 (c4,g3,p3g2);
and and_6(p3p2,p3,p2);
and and_7(p3p2c2,p3p2,c2);
or or_3 (carry_pred_1,c4,p3p2c2);
//C8
wire g4,g5,p4,p5;
wire p5g4;
wire c6,p5p4,p5p4c4;
and and_8(g4,in1[4],in2[4]);
and and_9(g5,in1[5],in2[5]);
xor xor_4(p4,in1[4],in2[4]);
xor xor_5(p5,in1[5],in2[5]);
and and_10(p5g4,p5,g4);
or or_4 (c6,g5,p5g4);
and and_11(p5p4,p5,p4);
and and_12(p5p4c4,p5p4,c4);
or or_5 (carry_pred_2,c6,p5p4c4);
// Results
assign temp1[2:0] = in1[1:0] + in2[1:0];
assign temp2[2:0] = in1[3:2] + in2[3:2] + c2;
assign temp3[2:0] = in1[5:4] + in2[5:4] + carry_pred_1;
assign temp4[2:0] = in1[7:6] + in2[7:6] + carry_pred_2;
assign res[8:0] = {temp4[2:0],temp3[1:0],temp2[1:0],temp1[1:0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVGND_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_SYMBOL_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "Test_AXI_Master_simple_v1_0_hw_1_concat_irq_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "Test_AXI_Master_simple_v1_0_hw_1_concat_irq_0,xlconcat,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=3,NUM_PORTS=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module Test_AXI_Master_simple_v1_0_hw_1_concat_irq_0 (
In0,
In1,
In2,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
input wire [0 : 0] In2;
output wire [2 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(3),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200001, MOD = 1000000007; int n, l, r; long long one = 0, two = 0, zero = 0, dp[MAXN][3]; int main() { cin >> n >> l >> r; for (; l % 3 != 0 && l <= r; l++) if (l % 3 == 1) one++; else if (l % 3 == 2) two++; for (; r % 3 != 0 && r >= l; r--) if (r % 3 == 1) one++; else if (r % 3 == 2) two++; if (l <= r) { one += r / 3 - l / 3; two += r / 3 - l / 3; zero += r / 3 - l / 3 + 1; } dp[1][0] = zero, dp[1][1] = one, dp[1][2] = two; for (int i = 2; i <= n; i++) { dp[i][0] = (dp[i - 1][0] * zero % MOD + dp[i - 1][1] * two % MOD + dp[i - 1][2] * one % MOD) % MOD; dp[i][1] = (dp[i - 1][0] * one % MOD + dp[i - 1][1] * zero % MOD + dp[i - 1][2] * two % MOD) % MOD; dp[i][2] = (dp[i - 1][0] * two % MOD + dp[i - 1][1] * one % MOD + dp[i - 1][2] * zero % MOD) % MOD; } cout << dp[n][0] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; } long long ar[3]; void solve() { long long x, y, ans = 0; cin >> x >> y; ar[0] = ar[1] = ar[2] = y; while (ar[0] < x || ar[1] < x || ar[2] < x) { sort(ar, ar + 3); ar[0] = ar[1] + ar[2] - 1; ans++; } cout << ans; }
|
`timescale 1 ns / 1 ps
module axis_interpolator #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_tvalid_reg, int_tvalid_next;
reg int_tready_reg, int_tready_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_reg <= 1'b0;
int_tready_reg <= 1'b0;
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
end
else
begin
int_tdata_reg <= int_tdata_next;
int_tvalid_reg <= int_tvalid_next;
int_tready_reg <= int_tready_next;
int_cntr_reg <= int_cntr_next;
end
end
always @*
begin
int_tdata_next = int_tdata_reg;
int_tvalid_next = int_tvalid_reg;
int_tready_next = int_tready_reg;
int_cntr_next = int_cntr_reg;
if(s_axis_tvalid & ~int_tvalid_reg)
begin
int_tdata_next = s_axis_tdata;
int_tvalid_next = 1'b1;
int_tready_next = 1'b1;
end
if(m_axis_tready & int_tvalid_reg)
begin
if(int_cntr_reg < cfg_data)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_tdata_next = s_axis_tdata;
int_tvalid_next = s_axis_tvalid;
int_tready_next = s_axis_tvalid;
end
end
if(s_axis_tvalid & int_tready_reg)
begin
int_tready_next = 1'b0;
end
end
assign s_axis_tready = int_tready_reg;
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
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