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// Library - static, Cell - thxor0, View - schematic
// LAST TIME SAVED: May 23 18:25:41 2014
// NETLIST TIME: May 23 18:27:37 2014
`timescale 1ns / 1ns
module thxor0 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "thxor0";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N14 ( .d(net037), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net45), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net037), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net037), .g(c), .s(net45), .b(cds_globals.gnd_));
nfet_b N10 ( .d(net037), .g(d), .s(net44), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net040), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net037), .g(a), .s(net040), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(c), .s(net036), .d(net045));
pfet_b P7 ( .b(cds_globals.vdd_), .g(d), .s(net036), .d(net045));
pfet_b P10 ( .b(cds_globals.vdd_), .g(y), .s(net045), .d(net037));
pfet_b P5 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net036));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net037));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net037);
endmodule
|
module testbench
();
`include "c_functions.v"
`include "c_constants.v"
parameter num_buffers = 8;
parameter data_width = 16;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter Tclk = 2;
parameter runtime = 1000;
parameter rate_in = 50;
parameter rate_out = 50;
parameter initial_seed = 0;
localparam addr_width = clogb(num_buffers);
reg clk;
reg reset;
wire push;
wire pop;
wire [0:addr_width-1] write_addr;
wire [0:addr_width-1] read_addr;
wire almost_empty;
wire empty;
wire almost_full;
wire full;
wire [0:1] ffc_errors;
c_fifo_ctrl
#(.depth(num_buffers),
.reset_type(reset_type))
ffc
(.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.write_addr(write_addr),
.read_addr(read_addr),
.almost_empty(almost_empty),
.empty(empty),
.almost_full(almost_full),
.full(full),
.errors(ffc_errors));
wire free;
wire free_early;
wire [0:1] ct_errors;
c_credit_tracker
#(.num_credits(num_buffers),
.reset_type(reset_type))
ct
(.clk(clk),
.reset(reset),
.debit(push),
.credit(pop),
.free(free),
.free_early(free_early),
.errors(ct_errors));
reg [0:data_width-1] write_data;
wire [0:data_width-1] read_data;
c_regfile
#(.width(data_width),
.depth(num_buffers))
rf
(.clk(clk),
.write_enable(push),
.write_address(write_addr),
.write_data(write_data),
.read_address(read_addr),
.read_data(read_data));
always
begin
clk <= 1'b1;
#(Tclk/2);
clk <= 1'b0;
#(Tclk/2);
end
wire [0:data_width-1] write_data_next;
assign write_data_next = reset ? {data_width{1'b0}} : (write_data + push);
reg drain;
reg flag_in, flag_out;
assign push = ~reset & flag_in & free;
assign pop = ~reset & flag_out & ~empty;
integer seed = initial_seed;
always @(posedge clk)
begin
flag_in <= ~drain && ($dist_uniform(seed, 0, 99) < rate_in);
flag_out <= ($dist_uniform(seed, 0, 99) < rate_out);
write_data <= write_data_next;
end
always @(negedge clk)
begin
if(push)
$display($time, " WRITE: %x=%x.", write_addr, write_data);
if(pop)
$display($time, " READ: %x=%x.", read_addr, read_data);
if(pop & (^read_data === 1'bx))
$display($time, " ERROR: read X value");
end
initial
begin
reset = 1'b1;
drain = 1'b0;
#(Tclk);
reset = 1'b0;
#(runtime*Tclk);
drain = 1'b1;
while(!empty)
#(Tclk);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; pair<int, int> s[n + 1]; for (int a = 0; a < n; a++) { int x, y; cin >> x >> y; s[a] = make_pair(max(x - y, 1), min(x + y, m)); } sort(s, s + n); int dp[m + 1]; dp[m] = 0; for (int a = m - 1; a >= 0; a--) { bool cover = 0; int minima = m - a; for (int b = 0; b < n; b++) { if (s[b].first <= (a + 1) && s[b].second >= (a + 1)) { cover = 1; break; } else if (s[b].first > (a + 1)) { minima = min(minima, dp[min(m, s[b].second + s[b].first - (a + 1))] + s[b].first - (a + 1)); } } if (cover) { dp[a] = dp[a + 1]; } else dp[a] = minima; } cout << dp[0]; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_0_V
`define SKY130_FD_SC_LP__A21OI_0_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_0 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_0_V
|
#include <bits/stdc++.h> using namespace std; char t[100][100]; int main(int argc, char* argv[]) { unsigned int n; cin >> n; for (unsigned int i = 0; i < n; ++i) for (unsigned int j = 0; j < n; ++j) cin >> t[i][j]; unsigned int r = 0; for (unsigned int i = 0; i < n; ++i) { for (unsigned int j = 0; j < n; ++j) { if (t[i][j] == . ) { ++r; break; } } } if (r < n) { unsigned int c = 0; for (unsigned int i = 0; i < n; ++i) { for (unsigned int j = 0; j < n; ++j) { if (t[j][i] == . ) { ++c; break; } } } if (c < n) cout << -1 << endl; else { for (unsigned int i = 0; i < n; ++i) { for (unsigned int j = 0; j < n; ++j) { if (t[j][i] == . ) { cout << j + 1 << << i + 1 << endl; break; } } } } } else { for (unsigned int i = 0; i < n; ++i) { for (unsigned int j = 0; j < n; ++j) { if (t[i][j] == . ) { cout << i + 1 << << j + 1 << endl; break; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; map<int, int> dic; int n, a[N + 10], ma[N + 10], ma2[N + 10]; int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; ma[1] = a[1]; ma2[1] = -1; for (int i = 2; i <= n; i++) { if (a[i] > ma[i - 1]) { ma2[i] = ma[i - 1]; ma[i] = a[i]; } else { ma[i] = ma[i - 1]; if (ma2[i - 1] < a[i]) { ma2[i] = a[i]; } else ma2[i] = ma2[i - 1]; } if (a[i] != ma[i] && a[i] == ma2[i]) { dic[ma[i]]++; } } int tot = -1e6, idx = -1; for (int i = 1; i <= n; i++) { int temp = dic[a[i]]; if (a[i] == ma[i]) temp--; if (temp > tot) { tot = temp; idx = a[i]; } else if (temp == tot) { idx = min(idx, a[i]); } } cout << idx << endl; return 0; }
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx Perfomance Counters Unit
Copyright (C) 2016 Authors
Author(s): Alexey Baturo <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_pcu
#(
parameter OPTION_PERFCOUNTERS_NUM = 7
)
(
input clk;
input rst;
// SPR Bus interface
input spr_access_i;
input spr_we_i;
input spr_re_i;
input [15:0] spr_addr_i;
input [31:0] spr_dat_i;
output spr_bus_ack;
output [31:0] spr_dat_o;
// Current cpu mode: user/supervisor
input spr_sys_mode_i;
// Events that can occur
input pcu_event_load_i; // track load insn
input pcu_event_store_i; // track store insn
input pcu_event_ifetch_i; // track insn fetch
input pcu_event_dcache_miss_i; // track data cache miss
input pcu_event_icache_miss_i; // track insn cache miss
input pcu_event_ifetch_stall_i; // track SOME stall
input pcu_event_lsu_stall_i; // track LSU stall
input pcu_event_brn_stall_i; // track brn miss
input pcu_event_dtlb_miss_i; // track data tlb miss
input pcu_event_itlb_miss_i; // track insn tlb miss
input pcu_event_datadep_stall_i; // track SOME stall
);
// Registers
reg [31:0] pcu_pccr[0:OPTION_PERFCOUNTERS_NUM];
reg [31:0] pcu_pcmr[0:OPTION_PERFCOUNTERS_NUM];
wire pcu_pccr_access;
wire pcu_pcmr_access;
// check if we access pcu
// TODO: generate this signals according to present units
assign pcu_pccr_access =
spr_access_i &
((`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR0_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR1_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR2_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR3_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR4_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR5_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR6_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR7_ADDR)));
assign pcu_pcmr_access =
spr_access_i &
((`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR0_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR1_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR2_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR3_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR4_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR5_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR6_ADDR)) |
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR7_ADDR)));
// put data on data bus
assign spr_bus_ack = spr_access_i;
assign spr_dat_o = (spr_access_i & pcu_pccr_access & spr_re_i) ? pcu_pccr[spr_addr_i[2:0]] :
(spr_access_i & pcu_pcmr_access & spr_re_i & spr_sys_mode_i) ? pcu_pcmr[spr_addr_i[2:0]] :
0;
genvar pcu_num;
generate
for(pcu_num = 0; pcu_num < OPTION_PERFCOUNTERS_NUM + 1; pcu_num = pcu_num + 1) begin: pcu_generate
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
pcu_pccr[pcu_num] = 32'd0;
pcu_pcmr[pcu_num] = 32'd0 | 1 << `OR1K_PCMR_CP;
end else begin
// we could write pcu registers only in system mode
if (spr_we_i && spr_sys_mode_i) begin
if (pcu_pccr_access)
pcu_pccr[spr_addr_i[2:0]] <= spr_dat_i;
// WPE are not implemented, hence we do not update WPE part
if (pcu_pcmr_access) begin
pcu_pcmr[spr_addr_i[2:0]][`OR1K_PCMR_DDS:`OR1K_PCMR_CISM] <=
spr_dat_i[`OR1K_PCMR_DDS:`OR1K_PCMR_CISM];
end
end else begin
if (((pcu_pcmr[pcu_num][`OR1K_PCMR_CISM] & spr_sys_mode_i) |
(pcu_pcmr[pcu_num][`OR1K_PCMR_CIUM] & ~spr_sys_mode_i))) begin
if (pcu_pcmr[pcu_num] & (pcu_event_load_i << `OR1K_PCMR_LA))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_store_i << `OR1K_PCMR_SA))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_ifetch_i << `OR1K_PCMR_IF))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_dcache_miss_i << `OR1K_PCMR_DCM))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_icache_miss_i << `OR1K_PCMR_ICM))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_ifetch_stall_i << `OR1K_PCMR_IFS))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_lsu_stall_i << `OR1K_PCMR_LSUS))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_brn_stall_i << `OR1K_PCMR_BS))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_dtlb_miss_i << `OR1K_PCMR_DTLBM))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_itlb_miss_i << `OR1K_PCMR_ITLBM))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
if (pcu_pcmr[pcu_num] & (pcu_event_datadep_stall_i << `OR1K_PCMR_DDS))
pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] + 1;
end
end
end
end
end
endgenerate
endmodule // mor1kx_pcu
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_intp2_2 (
clk,
data,
// outputs
intp2_0,
intp2_1);
input clk;
input [15:0] data;
// outputs
output [15:0] intp2_0;
output [15:0] intp2_1;
// internal registers
reg [15:0] data_s0 = 'd0;
reg [15:0] data_s1 = 'd0;
reg [15:0] data_s2 = 'd0;
reg [15:0] data_s3 = 'd0;
reg [15:0] data_s4 = 'd0;
reg [15:0] data_s5 = 'd0;
// delay registers
always @(posedge clk) begin
data_s0 <= data_s1;
data_s1 <= data_s2;
data_s2 <= data_s3;
data_s3 <= data_s4;
data_s4 <= data_s5;
data_s5 <= data;
end
// mac (fir filter)
ad_mac_1 i_mac_1 (
.clk (clk),
.data_s0 (data_s0),
.data_s1 (data_s1),
.data_s2 (data_s2),
.data_s3 (data_s3),
.data_s4 (data_s4),
.data_s5 (data_s5),
.mac_data_0 (intp2_0),
.mac_data_1 (intp2_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> #pragma 03 using namespace std; int mod = 998244353; int add(int a, int b) { a += b; if (a < 0) a += mod; if (a >= mod) a -= mod; return a; } int main() { int n, m; string s, t; cin >> n >> m >> s >> t; int pw = 1, res = 0, ans = 0; for (int i = 0; i < m; i++) { if (i < n && s[n - i - 1] == 1 ) res = add(res, pw); if (t[m - i - 1] == 1 ) ans = add(ans, res); pw = add(pw, pw); } cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int b, g, n; scanf( %d%d%d , &b, &g, &n); printf( %d n , min(b, n) - (n - min(g, n)) + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int x[110]; int y[110]; int d[110][2100]; int c[2010][2010]; int modd = 1000000007; int sum[10010]; int main() { int n, ans = 0, schet = 0; cin >> n; for (int i = 0; i < 1001; i++) { c[i][i] = 1; c[i][0] = 1; } for (int i = 1; i <= 1000; i++) for (int j = 1; j < i; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % modd; for (int i = 0; i < n; i++) { scanf( %d , &x[i]); schet += x[i]; } for (int i = 0; i < n; i++) scanf( %d , &y[i]); for (int i = n - 1; i >= 0; i--) if (i != n - 1) sum[i] = sum[i + 1] + x[i]; else sum[i] = x[i]; for (int i = x[0] + 1 - 1; i >= 0; i--) { if (i > y[0]) break; d[0][x[0] - i] += c[x[0]][i]; d[0][x[0] - i] %= modd; } for (int i = 1; i < n; i++) for (int j = 0; j < 1010; j++) for (int z = 0; z < 1010; z++) { if (z > y[i]) break; if (j - x[i] + z < 0) continue; d[i][j] += (1ll * d[i - 1][j - x[i] + z] * c[j + z][z]) % modd; d[i][j] %= modd; } ans = d[n - 1][0]; for (int i = 0; i < n; i++) ans = (1ll * ans * c[sum[i]][x[i]]) % modd; cout << ans; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate that an lvalue concat can receive an assignment.
//
// D: Validate that an lvalue can be a concatenation.
//
module main ();
reg a;
reg b;
reg working;
initial
begin
working = 1;
{a,b} = 2'b00 ;
if( (a != 0) & (b != 0))
begin
$display("FAILED {a,b} Expected 2'b00 - received %b%b",a,b);
working = 0;
end
{a,b} = 2'b01 ;
if( (a != 0) & (b != 1))
begin
$display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b);
working = 0;
end
{a,b} = 2'b10 ;
if( (a != 1) & (b != 0))
begin
$display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b);
working = 0;
end
{a,b} = 2'b11 ;
if( (a != 1) & (b != 1))
begin
$display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b);
working = 0;
end
if(working)
$display("PASSED\n");
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
always @ (posedge clk or negedge resetn) begin
// not in reset
if (resetn)
begin
case (state)
// Wake up processor and all B.C.
TASK0:
begin
c0_req_int <= 1;
state <= TX_WAIT;
end
// Querry nodes
TASK1:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_QUERRY, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h2
TASK2:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
// address should starts with 4'h2
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h2, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h3
TASK3:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h3, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h4
TASK4:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h4, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h5
TASK5:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h5, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// n0 -> 4'h2
// n1 -> 4'h3
// n2 -> 4'h4
// n3 -> 4'h5
// n1 -> n3 byte streamming using short address
TASK6:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
if (word_counter==2)
err_start <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
err_start <= 0;
end
end
if (n1_tx_fail)
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
err_start <= 0;
end
end
TASK7:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
// n1 -> n3 byte streamming using short address
TASK8:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
if (word_counter==2)
begin
err_start <= 1;
err_type <= 1;
end
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
err_start <= 0;
err_type <= 0;
end
end
if (n1_tx_fail)
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
err_start <= 0;
err_type <= 0;
end
end
// n1 -> n3, clk glitch after interrupt
TASK9:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
n1_tx_pend <= 0;
err_start <= 1;
err_type <= 2;
state <= TX_WAIT;
end
end
// n1 -> n3, missing clk edge after interrupt
TASK10:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
n1_tx_pend <= 0;
err_start <= 1;
err_type <= 3;
state <= TX_WAIT;
end
end
// All layers wake
TASK24:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_WAKE, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
endcase
end
end
|
#include <bits/stdc++.h> using namespace std; int main() { int a[4]; cin >> a[0] >> a[1] >> a[2] >> a[3]; int sum, i; sum = 0; string s; cin >> s; for (i = 0; i < s.length(); i++) { sum += a[((s[i]) - 0 ) - 1]; } cout << sum; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_BLACKBOX_V
`define SKY130_FD_SC_MS__OR3_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_TB_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_pwrgood_pp_p.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VPWR = 1'b0;
#60 UDP_IN = 1'b1;
#80 VPWR = 1'b1;
#100 UDP_IN = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 UDP_IN = 1'b1;
#180 VPWR = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_hvl__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_TB_V
|
#include <bits/stdc++.h> using namespace std; int SquareRoot(int n) { int l = 1, r = n + 1; while (l < r) { int mid = (l + r) / 2; if (n / mid < mid) { r = mid; } else { l = mid + 1; } } --l; if (l * l == n) { return l; } return -1; } int GCD(int a, int b) { while (b > 0) { int t = a % b; a = b; b = t; } return a; } int main() { int a = 0, b = 0; scanf( %d%d , &a, &b); int a2 = a * a; int b2 = b * b; bool found = false; for (int i = a - 1; i > 0; --i) { int j = SquareRoot(a2 - i * i); if (j < 0) { continue; } int gcd = GCD(i, j); int i_norm = i / gcd; int j_norm = j / gcd; int squ = i_norm * i_norm + j_norm * j_norm; if (b2 % squ != 0) { continue; } int mul = SquareRoot(b2 / squ); if (mul < 0) { continue; } found = true; int i2 = i_norm * mul; int j2 = j_norm * mul; if (i2 == j) { continue; } printf( YES n ); printf( 0 0 n ); printf( %d %d n , i, j); printf( %d %d n , -j2, i2); break; } if (!found) { printf( NO n ); } return 0; }
|
// -------------------------- testHarness.v -----------------------
`include "timescale.v"
module testHarness ();
reg rst;
reg clk;
reg i2cHostClk;
wire sda;
wire scl;
wire sdaOutEn;
wire sdaOut;
wire sdaIn;
wire [2:0] adr;
wire [7:0] masterDout;
wire [7:0] masterDin;
wire we;
wire stb;
wire cyc;
wire ack;
wire scl_pad_i;
wire scl_pad_o;
wire scl_padoen_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_padoen_o;
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testHarness);
end
i2cSlave u_i2cSlave(
.clk(clk),
.rst(rst),
.sda(sda),
.scl(scl),
.myReg0(),
.myReg1(),
.myReg2(),
.myReg3(),
.myReg4(8'h12),
.myReg5(8'h34),
.myReg6(8'h56),
.myReg7(8'h78)
);
i2c_master_top #(.ARST_LVL(1'b1)) u_i2c_master_top (
.wb_clk_i(clk),
.wb_rst_i(rst),
.arst_i(rst),
.wb_adr_i(adr),
.wb_dat_i(masterDout),
.wb_dat_o(masterDin),
.wb_we_i(we),
.wb_stb_i(stb),
.wb_cyc_i(cyc),
.wb_ack_o(ack),
.wb_inta_o(),
.scl_pad_i(scl_pad_i),
.scl_pad_o(scl_pad_o),
.scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i),
.sda_pad_o(sda_pad_o),
.sda_padoen_o(sda_padoen_o)
);
wb_master_model #(.dwidth(8), .awidth(3)) u_wb_master_model (
.clk(clk),
.rst(rst),
.adr(adr),
.din(masterDin),
.dout(masterDout),
.cyc(cyc),
.stb(stb),
.we(we),
.sel(),
.ack(ack),
.err(1'b0),
.rty(1'b0)
);
assign sda = (sda_padoen_o == 1'b0) ? sda_pad_o : 1'bz;
assign sda_pad_i = sda;
pullup(sda);
assign scl = (scl_padoen_o == 1'b0) ? scl_pad_o : 1'bz;
assign scl_pad_i = scl;
pullup(scl);
// ****************************** Clock section ******************************
//approx 48MHz clock
`define CLK_HALF_PERIOD 10
always begin
#`CLK_HALF_PERIOD clk <= 1'b0;
#`CLK_HALF_PERIOD clk <= 1'b1;
end
// ****************************** reset ******************************
task reset;
begin
rst <= 1'b1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
rst <= 1'b0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask
endmodule
|
//-----------------------------------------------------------------------------
// Title : CIC decimator with dynamically-adjustable decimator
// Project :
//-----------------------------------------------------------------------------
// File : cic_decim.v
// Author : danielot <>
// Company :
// Created : 2016-05-03
// Last update: 2016-05-03
// Platform :
// Standard : VHDL'93/02
//-----------------------------------------------------------------------------
// Description: CIC decimator with dinamically adjustable decimation rate
//-----------------------------------------------------------------------------
// Copyright (c) 2016
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author Description
// 2016-05-03 1.0 danielot Created
//-----------------------------------------------------------------------------
//
// Design based on code available on GNU Radio
// The CIC has a valid signal (act) pipeline that signals when the data is
// filling integrator and comb pipelines. When the decimation strobe
// comes (act_out_i), the data in the last integrator register is sampled
// to the comb stage. However, to allow the decimation strobe to happen in
// a different clock period from the valid input signal, the valid signal
// in the last register is marked as invalid during the decimation. The
// sampling only happens when this register is valid, avoiding data corruption
// from occasional spurious decimation strobes.
module cic_decim
#(
parameter DATAIN_WIDTH = 16,
parameter DATAOUT_WIDTH = DATAIN_WIDTH,
parameter M = 2,
parameter N = 5,
parameter MAXRATE = 64,
parameter BITGROWTH = 35, //N*log2(M*MAXRATE)
// Select 0 to use the default round to minus infinity (floor)
// or 1 to use convergent rounding
parameter ROUND_CONVERGENT = 0
)
(
input clk_i,
input rst_i,
input en_i,
input [DATAIN_WIDTH-1:0] data_i,
output [DATAOUT_WIDTH-1:0] data_o,
input act_i,
input act_out_i,
output val_o
);
localparam DATAOUT_FULL_WIDTH = DATAIN_WIDTH + BITGROWTH;
localparam DATAOUT_EXTRA_BITS = DATAOUT_FULL_WIDTH - DATAOUT_WIDTH;
wire [DATAOUT_FULL_WIDTH-1:0] datain_extended;
reg [DATAOUT_FULL_WIDTH-1:0] integrator [0:N-1];
reg [DATAOUT_FULL_WIDTH-1:0] diffdelay [0:N-1][0:M-1];
reg [DATAOUT_FULL_WIDTH-1:0] pipe [0:N-1];
wire[DATAOUT_FULL_WIDTH-1:0] data_int;
wire[DATAOUT_WIDTH-1:0] data_out;
reg [DATAOUT_WIDTH-1:0] data_out_reg;
reg [DATAOUT_FULL_WIDTH-1:0] sampler = {{1'b0}};
reg val_int = {{1'b0}};
wire val_out;
reg val_out_reg = {{1'b0}};
reg act_int [0:N-1];
reg act_samp;
reg act_comb [0:N-1];
integer i,j;
assign datain_extended = {{(BITGROWTH){data_i[DATAIN_WIDTH-1]}},data_i};
// Integrator sections
always @(posedge clk_i)
if (rst_i)
for (i=0; i<N; i=i+1) begin
integrator[i] <= {{1'b0}};
act_int[i] <= {{1'b0}};
end
else if (en_i) begin
if (act_i) begin
integrator[0] <= integrator[0] + datain_extended;
act_int[0] <= 1'b1;
for (i=1; i<N; i=i+1) begin
integrator[i] <= integrator[i] + integrator[i-1];
act_int[i] <= act_int[i-1];
end
end
else begin
// Clear the act_int flag only when the COMB section acknowledges it
if (act_out_i) begin
act_int[N-1] <= 1'b0;
end
end
end
// Comb sections
always @(posedge clk_i) begin
if (rst_i) begin
sampler <= {{1'b0}};
for (i=0; i<N; i=i+1) begin
pipe[i] <= {{1'b0}};
act_comb[i] <= {{1'b0}};
for (j=0; j<M; j=j+1)
diffdelay[i][j] <= {{1'b0}};
end
act_samp <= 1'b0;
val_int <= 1'b0;
end
else begin
if (en_i) begin
if (act_out_i && act_int[N-1]) begin
sampler <= integrator[N-1];
act_samp <= 1'b1;
diffdelay[0][0] <= sampler;
for (j=1; j<M; j=j+1)
diffdelay[0][j] <= diffdelay[0][j-1];
pipe[0] <= sampler - diffdelay[0][M-1];
act_comb[0] <= act_samp;
for (i=1; i<N; i=i+1) begin
diffdelay[i][0] <= pipe[i-1];
for (j=1; j<M; j=j+1)
diffdelay[i][j] <= diffdelay[i][j-1];
pipe[i] <= pipe[i-1] - diffdelay[i][M-1];
act_comb[i] <= act_comb[i-1];
end
if(N==1)
val_int <= act_samp;
else
val_int <= act_comb[N-2]; //same as act_comb[N-1]
end // if (act_out_i)
else begin
val_int <= 1'b0;
end // else: !if(act_out_i)
end // if (en_i)
end // else: !if(rst_i)
end // always @ (posedge clk_i)
assign data_int = pipe[N-1];
generate
if (DATAOUT_EXTRA_BITS==0) begin
assign data_out = data_int[DATAOUT_FULL_WIDTH-1:0];
end
// Round bits as selected data output width <= computed data output
// width
else if (DATAOUT_EXTRA_BITS > 0) begin
if (ROUND_CONVERGENT) begin
// Round convergent using the algorithm described in
// https://groups.google.com/forum/#!topic/comp.lang.verilog/sRt57P-FJEE
assign data_out = data_int[DATAOUT_FULL_WIDTH-1:DATAOUT_EXTRA_BITS] +
((data_int[DATAOUT_EXTRA_BITS-1:0] == {1'b1, {(DATAOUT_EXTRA_BITS-1){1'b0}}}) ?
data_int[DATAOUT_EXTRA_BITS] : data_int[DATAOUT_EXTRA_BITS-1]);
end
else begin
assign data_out = data_int[DATAOUT_FULL_WIDTH-1:DATAOUT_EXTRA_BITS];
end
end
// Sign-extend bits as selected data output width > computed data output
// width
else begin // DATAOUT_EXTRA_BITS < 0 means we need to sign-extend
assign data_out = {{(DATAOUT_WIDTH-DATAOUT_FULL_WIDTH){data_int[DATAOUT_FULL_WIDTH-1]}}, data_int};
end
endgenerate
assign val_out = val_int;
// Output stage
always @(posedge clk_i) begin
if (rst_i) begin
data_out_reg <= {{1'b0}};
val_out_reg <= {{1'b0}};
end
else begin
if (en_i) begin
data_out_reg <= data_out;
val_out_reg <= val_out;
end
end
end
assign data_o = data_out_reg;
assign val_o = val_out_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; vector<pair<long long, int> > v; vector<int> lef, rig; long long pitaj(int t, int a, int b, int c) { long long res; cout << 3 - t << << a << << b << << c << endl; cin >> res; return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; int ind = 2; for (int i = 3; i <= n; i++) { if (pitaj(1, 1, i, ind) == 1) ind = i; } for (int i = 2; i <= n; i++) { if (i == ind) continue; v.push_back({pitaj(2, 1, ind, i), i}); } sort(v.begin(), v.end()); for (int i = 1; i < v.size(); i++) { if (pitaj(1, 1, v[i - 1].second, v[i].second) == 1) { lef.push_back(v[i - 1].second); } else { rig.push_back(v[i - 1].second); } } lef.push_back(v.back().second); cout << 0 << << 1 << << ind << ; for (int i = 0; i < lef.size(); i++) cout << lef[i] << ; for (int i = (int)rig.size() - 1; i >= 0; i--) cout << rig[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool cmp(int a, int b) { return a > b; } int main() { long long a[100005]; long long b[100005]; int n; cin >> n; long long sum = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; } for (int i = 1; i <= n; i++) cin >> b[i]; if (n == 2) { cout << YES << endl; return 0; } if (n == 1 || n == 0) { cout << NO << endl; return 0; } sort(b + 1, b + n + 1, cmp); if (b[1] + b[2] >= sum) { cout << YES << endl; } else cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; int getint() { int s = 0, o = 1; char c; for (c = getchar(); c < 0 || c > 9 ; c = getchar()) if (c == - ) o = -1; for (; c >= 0 && c <= 9 ; c = getchar()) s *= 10, s += c - 0 ; return s * o; } const int mod = (int)1e9 + 7; struct Mat { int n; long long x; int a[31][31]; void operator*=(const Mat &p) { int c[31][31]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { long long r = 0; for (int k = 0; k < n; k++) r += (1ll * a[i][k] * p.a[k][j]) % mod; c[i][j] = r % mod; if (c[i][j] < 0) c[i][j] += mod; } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) a[i][j] = c[i][j]; } void write() { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) printf( %d , a[i][j]); printf( n ); } } } A[70][30], B[70][30]; long long n; int k; Mat I; Mat calc(int i, int j, long long n) { Mat r = I; if (n == 0) return r; for (int timer = 0; timer < k; timer++) { if (n >= A[i][j].x) r *= A[i][j]; else r *= calc(i - 1, j, n); n -= A[i][j].x; if (n <= 0) break; j = (j + 1) % k; } return r; } int main(int argc, char const *argv[]) { scanf( %I64d%d , &n, &k); I.n = k + 1; for (int i = 0; i < I.n; i++) for (int j = 0; j < I.n; j++) I.a[i][j] = i == j; for (int i = 0; i < k; i++) { Mat &M = A[0][i]; M.n = k + 1, M.x = 1; for (int t = 0; t < k + 1; t++) for (int s = 0; s < k + 1; s++) M.a[t][s] = (t == s || t == i); Mat &N = B[0][i]; N.n = k + 1, N.x = 1; for (int t = 0; t < k + 1; t++) for (int s = 0; s < k + 1; s++) { if (t == i) N.a[t][s] = -1; if (t == s) N.a[t][s] = 1; } } int i; for (i = 0;; i++) { long long _x = A[i][0].x * k; if (_x > n || _x < 0) break; Mat &M = A[i + 1][0]; M = A[i][0]; M.x = _x; for (int p = 1; p < k; ++p) M *= A[i][p]; for (int j = 1; j < k; ++j) { Mat &M = A[i + 1][j]; M = B[i][j - 1]; M *= A[i + 1][j - 1]; M *= A[i][j - 1]; M.x = _x; } Mat &N = B[i + 1][0]; N = B[i][k - 1]; N.x = _x; for (int p = k - 2; p >= 0; --p) N *= B[i][p]; for (int j = 1; j < k; ++j) { Mat &N = B[i + 1][j]; N = B[i][j - 1]; N *= B[i + 1][j - 1]; N *= A[i][j - 1]; N.x = _x; } } Mat res = calc(i, 0, n); long long r = 0; for (int i = 0; i < k + 1; i++) r += res.a[i][k]; printf( %I64d n , r % mod); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int32_t main() { int64_t t; cin >> t; for (int64_t i = 0; i < t; i++) { int64_t a, b; cin >> a >> b; if (a == b) { cout << 0 << endl; continue; } int64_t k = abs(b - a); int64_t ans = k / 5; k %= 5; ans += k / 2; k %= 2; ans += k; cout << ans << endl; } }
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#include <bits/stdc++.h> using namespace std; int a, b, c, d, e, n, m, t, kk, tt = 0, l[5007], r[5007], fa[5007], type[5007], ind[5007]; int y[5007] = {0}, qw[5007], tree[1000007], a1[5007], a2[5007], a3[5007], a4[5007]; vector<int> q[5007]; vector<short> w[5007]; void get(int x1, int l, int r, int tl, int tr, int k) { if (tree[k] == tt) return; if (l >= tl && r <= tr) { tree[k] = tt; for (int i = l; i <= r; i++) w[x1].push_back(i); return; } int m = (l + r) / 2; if (tl <= m) get(x1, l, m, tl, tr, k << 1); if (tr > m) get(x1, m + 1, r, tl, tr, (k << 1) + 1); } int sou(int x1) { t = 0; if (type[x1] == 0) for (int j = 1; j <= q[x1].size(); j++) w[x1].push_back(q[x1][j - 1]); else get(x1, 1, m, q[x1][0], q[x1][1], 1); for (int j = 1; j <= w[x1].size(); j++) if (!qw[fa[w[x1][j - 1]]]) { qw[fa[w[x1][j - 1]]] = 1; if (y[fa[w[x1][j - 1]]] == 0 || sou(y[fa[w[x1][j - 1]]])) { y[fa[w[x1][j - 1]]] = x1; w[x1].clear(); return 1; } } w[x1].clear(); return 0; } int main() { scanf( %d%d , &n, &m); kk = 1; for (int i = 1; i <= m; i++) fa[i] = i; int ans = 0, t3 = 0; for (int i = 1; i <= n; i++) { scanf( %d , &type[kk]); if (type[kk] == 0) { scanf( %d , &b); for (int j = 1; j <= b; j++) { scanf( %d , &c); q[kk].push_back(c); } ind[kk] = i; kk++; } else if (type[kk] == 1) { scanf( %d%d , &b, &c); ind[kk] = i; q[kk].push_back(b); q[kk++].push_back(c); } else { scanf( %d%d%d , &b, &c, &d); fa[c] = b; fa[d] = b; ans += 2; a1[++t3] = b, a2[t3] = c, a3[t3] = d, a4[t3] = i; } } for (int i = 1; i <= kk - 1; i++) { tt++; for (int j = 1; j <= m; j++) qw[j] = 0; if (sou(i)) ans++; } printf( %d n , ans); for (int i = 1; i <= t3; i++) { fa[a1[i]] = 0; fa[a2[i]] = 0; fa[a3[i]] = 0; int g = 0; if (y[a1[i]] == 0) { printf( %d %d n , a4[i], a1[i]); printf( %d %d n , a4[i], a2[i]); continue; } else if (type[y[a1[i]]] == 0) for (int j = 1; j <= q[y[a1[i]]].size(); j++) { if (q[y[a1[i]]][j - 1] == a1[i]) g = 1; if (q[y[a1[i]]][j - 1] == a2[i]) g = 2; if (q[y[a1[i]]][j - 1] == a3[i]) g = 3; } else for (int j = q[y[a1[i]]][0]; j <= q[y[a1[i]]][1]; j++) { if (j == a1[i]) g = 1; if (j == a2[i]) g = 2; if (j == a3[i]) g = 3; } if (g == 1) printf( %d %d n , ind[y[a1[i]]], a1[i]); else printf( %d %d n , a4[i], a1[i]); if (g == 2) printf( %d %d n , ind[y[a1[i]]], a2[i]); else printf( %d %d n , a4[i], a2[i]); if (g == 3) printf( %d %d n , ind[y[a1[i]]], a3[i]); else printf( %d %d n , a4[i], a3[i]); } for (int i = 1; i <= m; i++) if (y[i] && fa[i] == i) printf( %d %d n , ind[y[i]], i); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)5e5 + 9; const int maxm = (int)1e6 + 9; const long long mod = (long long)1e9 + 7; const double pi = acos(-1); const double eps = 1e-15; vector<pair<int, int> > to[maxn]; int fa[maxn]; int tobig[maxn]; int n, m; int e[maxn]; int e2[maxn]; int f[maxn]; int fe[maxn]; void init() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; to[a].emplace_back(i, b); to[b].emplace_back(i, a); e[i] = a; e2[i] = b; } memset(tobig, -1, sizeof(tobig)); } int vis[maxn]; void dfs(int u, int ft) { vis[u] = -1; for (int i = 0; i < to[u].size(); i++) { int v = to[u][i].second; if (ft == v) continue; fa[u] = i; if (vis[v] == 0) { dfs(v, u); } else if (vis[v] == -1) { int mn = maxn; int mx = -1; int tmp = v; vector<int> tot; do { int d = to[tmp][fa[tmp]].first; tot.push_back(d); mn = min(mn, d); mx = max(mx, d); tmp = to[tmp][fa[tmp]].second; } while (tmp != v); tobig[mn] = mx; int mxp, mnp; int len = tot.size(); for (int x = 0; x < len; x++) { if (mx == tot[x]) mxp = x; if (mn == tot[x]) mnp = x; } int fl = 0; for (int x = mxp; x != mnp; x = (x + 1) % len) { if (tot[x] < tot[(x + 1) % len]) { fl = 1; break; } } for (int x = mxp; x != mnp; x = (x + len - 1) % len) { if (tot[x] < tot[(x + len - 1) % len]) { fl = 1; break; } } if (fl) { tobig[mn] = -1; } } } vis[u] = 1; } int bcj[maxn]; int fd(int x) { return bcj[x] = bcj[x] == x ? x : fd(bcj[x]); } int main() { init(); dfs(1, -1); for (int i = 1; i <= n; i++) { bcj[i] = i; f[i] = 1; } for (int i = m - 1; i >= 0; i--) { int fu = fd(e[i]); int fv = fd(e2[i]); int tt = f[e[i]] + f[e2[i]]; if (fu == fv) { if (tobig[i] != -1) { tt -= fe[tobig[i]]; } } else { bcj[fu] = fv; } fe[i] = f[e[i]] = f[e2[i]] = tt; } for (int i = 1; i <= n; i++) { cout << f[i] - 1 << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; int a[maxn]; int ans[maxn << 1]; int vis1[maxn], vis[maxn]; int main() { int T; scanf( %d , &T); while (T--) { int n; scanf( %d , &n); int res = n; int p = 0; int mex; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); vis1[i] = 0; } while (res > 0) { for (int i = 0; i <= n; i++) vis[i] = 0; for (int i = 1; i <= n; i++) vis[a[i]] = 1; for (int i = 0;; i++) { if (!vis[i]) { mex = i; break; } } if (mex == 0) { for (int i = 1; i <= n; i++) { if (!vis1[i]) { a[i] = mex; ans[++p] = i; break; } } } else { ans[++p] = mex; a[mex] = mex; vis1[mex] = 1; res--; } } printf( %d n , p); for (int i = 1; i <= p; i++) printf( %d , ans[i]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> int B = 400; using namespace std; const long long inf = 1e8; int MOD = 1e9 + 7; const int mxn = 300010; const int N = 1000005; const double pi = 3.14159; int dx[] = {0, 1, 0, -1, 1, -1, 1, -1}; int dy[] = {1, 0, -1, 0, -1, 1, 1, -1}; int n, d, k; vector<int> g[mxn]; vector<pair<int, int> > q[mxn]; long long add[mxn]; long long ans[mxn]; void dfs(int v, int p = -1, int d = 1, long long cur = 0) { for (auto i : q[v]) { int d_ = i.first, val = i.second; cur += (long long)val; int tot = min(d + d_ + 1, mxn); add[tot] -= (long long)val; } cur += add[d]; ans[v] = cur; for (auto i : g[v]) { if (i == p) continue; dfs(i, v, d + 1, cur); } for (auto i : q[v]) { int d_ = i.first, val = i.second; int tot = min(d + d_ + 1, mxn); add[tot] += (long long)val; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; g[u].push_back(v), g[v].push_back(u); } int qn; cin >> qn; while (qn--) { int n, d, val; cin >> n >> d >> val; q[n].push_back({d, val}); } dfs(1); for (int i = 1; i <= n; i++) cout << ans[i] << ; }
|
#include <bits/stdc++.h> using namespace std; long long int getT(vector<vector<long long int>>&, int, int); void _dp(vector<vector<long long int>>& dp, int n) { for (int j = 0; j < n; j++) dp[0][j] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) for (int k = 0; k < i; k++) dp[i][j] += dp[k][j - 1] * dp[(i - 1) - k][j - 1]; } int main() { int n, h; scanf( %d %d , &n, &h); vector<vector<long long int>> dp(n + 1, vector<long long int>(n + 1, 0)); _dp(dp, n); cout << dp[n][n] - dp[n][h - 1] << endl; return 0; }
|
/*
* Copyright (c) 2002 Richard M. Myers
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 10 ns/ 10 ns
module top ;
reg clk ;
reg [11:0] x_os_integ, y_os_integ;
reg [5:0] x_os, y_os;
initial
begin
//$dumpfile("show_math.vcd");
//$dumpvars(1, top);
clk = 1'h0 ;
x_os = 6'h01;
y_os = 6'h3f;
x_os_integ = 12'h000;
y_os_integ = 12'h000;
end
initial
begin
#60;
forever #3 clk = ~clk ; // 16Mhz
end
always @( posedge clk )
begin
// Integration period set above depending on configured modem speed.
x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};
$display ("%x %x", x_os_integ, y_os_integ);
end
initial
begin
#200 $finish ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 3; int n; vector<int> G[N]; int h[N], cnt[N]; int res = 0; void dfs(int u, int p) { cnt[h[u]]++; for (int v : G[u]) if (v != p) { h[v] = h[u] + 1; dfs(v, u); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n - 1; ++i) { int x; cin >> x; G[x].push_back(i + 1); } h[1] = 1; dfs(1, 0); for (int i = 1; i <= n; ++i) res += (cnt[i] % 2); cout << res; }
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#include <bits/stdc++.h> using namespace std; struct fast_ios { fast_ios() { cin.tie(0); ios::sync_with_stdio(false); cout << fixed << setprecision(20); }; } fast_ios_; template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (auto &x : v) is >> x; return is; } template <typename T> ostream &operator<<(ostream &os, vector<T> &v) { for (long long i = 0; i < v.size(); i++) { cout << v[i]; if (i != v.size() - 1) cout << endl; }; return os; } template <typename T1, typename T2> ostream &operator<<(ostream &os, pair<T1, T2> p) { cout << ( << p.first << , << p.second << ) ; return os; } template <typename T> void Out(T x) { cout << x << endl; } template <typename T1, typename T2> void chOut(bool f, T1 y, T2 n) { if (f) Out(y); else Out(n); } using vec = vector<long long>; using mat = vector<vec>; using Pii = pair<long long, long long>; using v_bool = vector<bool>; using v_Pii = vector<Pii>; long long dx[4] = {1, 0, -1, 0}; long long dy[4] = {0, 1, 0, -1}; const long long mod = 1000000007; void imp() { Out( Not unique ); exit(0); } signed main() { long long n, m; cin >> n >> m; vector<string> s(n); cin >> s; queue<Pii> que; long long S = 0; for (long long i = (0); i < (n); i++) for (long long j = (0); j < (m); j++) if (s[i][j] == . ) { S++; long long cnt = 0; for (long long k = (0); k < (4); k++) { long long x = i + dx[k], y = j + dy[k]; if (x >= 0 && x < n && y >= 0 && y < m && s[x][y] == . ) cnt++; } if (cnt == 1) que.push(Pii(i, j)); } while (!que.empty()) { long long i = que.front().first, j = que.front().second; que.pop(); if (s[i][j] != . ) continue; long long k0 = -1; for (long long k = (0); k < (4); k++) { long long x = i + dx[k], y = j + dy[k]; if (x >= 0 && x < n && y >= 0 && y < m && s[x][y] == . ) { k0 = k; break; } } if (k0 == -1) imp(); long long i2 = i + dx[k0], j2 = j + dy[k0]; if (k0 == 0) s[i][j] = ^ , s[i2][j2] = v ; else if (k0 == 1) s[i][j] = < , s[i2][j2] = > ; else if (k0 == 2) s[i][j] = v , s[i2][j2] = ^ ; else if (k0 == 3) s[i][j] = > , s[i2][j2] = < ; S -= 2; for (long long k = (0); k < (4); k++) { long long i3 = i2 + dx[k], j3 = j2 + dy[k]; if (i3 >= 0 && i3 < n && j3 >= 0 && j3 < m && s[i3][j3] == . ) { long long cnt = 0; for (long long k3 = (0); k3 < (4); k3++) { long long x = i3 + dx[k3], y = j3 + dy[k3]; if (x >= 0 && x < n && y >= 0 && y < m && s[x][y] == . ) cnt++; } if (cnt == 1) que.push(Pii(i3, j3)); } } } if (S != 0) imp(); else Out(s); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-8; const double PI = acos(-1); int n, k, b, c, t[N]; pair<int, int> a[N]; long long ans = INF; long long cnt = 0; priority_queue<pair<long long, int> > que; long long solve(pair<int, int> *a, long long b, long long c) { while (!que.empty()) que.pop(); cnt = 0; long long ans = INF, ret = 0; for (int i = 1; i <= k; i++) { ret += a[i].second * c; ret += (a[i].first - a[i - 1].first) * cnt * b; que.push(make_pair(c * a[i].second + (a[1].first - a[i].first) * b, i)); cnt++; } ans = min(ans, ret); for (int i = k + 1; i <= n; i++) { int p = que.top().second; que.pop(); cnt--; ret -= a[p].second * c; ret -= (a[i - 1].first - a[p].first) * b; ret += (a[i].first - a[i - 1].first) * cnt * b; ret += a[i].second * c; que.push(make_pair(c * a[i].second + (a[1].first - a[i].first) * b, i)); cnt++; ans = min(ans, ret); } return ans; } int main() { scanf( %d%d%d%d , &n, &k, &b, &c); for (int i = 1; i <= n; i++) scanf( %d , &t[i]), t[i] += 1000000000; sort(t + 1, t + 1 + n); for (int i = 1; i <= n; i++) a[i].first = t[i], a[i].second = 0; ans = min(ans, solve(a, c, 0)); for (int j = 0; j < 5; j++) { for (int i = 1; i <= n; i++) { a[i].second = ((j - (t[i] % 5)) + 5) % 5; a[i].first = (t[i] + a[i].second) / 5; } ans = min(ans, solve(a, b, c)); } printf( %lld n , ans); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLXBP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_BLACKBOX_V
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#include<bits/stdc++.h> using namespace std; #define IOS ios_base::sync_with_stdio(false);cin.tie(0);cout.tie(0); #define int long long #define rep(i,a,b) for(int i=a;i<b;i++) #define repn(i,a,b) for(int i=a;i>=b;i--) #define ff first #define ss second #define lb lower_bound #define ub upper_bound #define pii pair<int,int> #define vi vector<int> #define vs vector<string> #define vii vector<pii> #define vvi vector<vector<int>> #define vvii vector<vector<pii>> #define pb push_back #define ppb pop_back #define pf push_front #define ppf pop_front #define sz(x) (int)x.size() #define all(v) (v).begin(), (v).end() #define ret(x) return cout<<x,0; #define rety return cout<< YES ,0; #define retn return cout<< NO ,0; #define fl fflush(stdout) #define hell 1000000007 #define hell2 998244353 #define pi 3.14159265358979323846 int solve(){ int n,m; cin >> n >> m; string s,a; cin >> s; a = s; for(int i = 0; i < min(m,n); i++){ int x{}; for(int j = 0; j < n; j++){ if(j == 0){ if(s[1] == 1 && s[0] == 0 ) a[0] = 1 ; x++; } else if(j == n-1){ if(s[n-1] == 0 && s[n-2] == 1 ) a[n-1] = 1 ; x++; } else{ if((s[j-1] == 1 && s[j+1] == 0 && s[j] == 0 ) || (s[j-1] == 0 && s[j+1] == 1 && s[j] == 0 )) a[j] = 1 ; x++; } } s = a; if(x == 0) break; } cout << s << endl; return 0; } signed main(){ IOS; int tp=1; cin>>tp; while(tp--){ solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; char a[n][m]; bool vis[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; vis[i][j] = false; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (i > 0 && i < n - 1 && j > 0 && j < m - 1) { bool flag = true; for (int k = -1; k <= 1; k++) { for (int l = -1; l <= 1; l++) { if (k == 0 && l == 0) continue; if (a[i + k][j + l] == . ) { flag = false; } } } if (flag == true) { for (int k = -1; k <= 1; k++) { for (int l = -1; l <= 1; l++) { if (k == 0 && l == 0) continue; vis[i + k][j + l] = true; } } } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == # && vis[i][j] == false) { cout << NO ; return 0; } } } cout << YES ; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// One-to-many fanout adaptor. Ensures that fanouts
// see the right number of valid_outs under all stall conditions.
module acl_multi_fanout_adaptor #(
parameter integer DATA_WIDTH = 32, // >=0
parameter integer NUM_FANOUTS = 2 // >0
)
(
input logic clock,
input logic resetn,
// Upstream interface
input logic [DATA_WIDTH-1:0] data_in, // not used if DATA_WIDTH=0
input logic valid_in,
output logic stall_out,
// Downstream interface
output logic [DATA_WIDTH-1:0] data_out, // not used if DATA_WIDTH=0
output logic [NUM_FANOUTS-1:0] valid_out,
input logic [NUM_FANOUTS-1:0] stall_in
);
genvar i;
logic [NUM_FANOUTS-1:0] consumed, true_stall_in;
// A downstream interface is truly stalled only if it has not already consumed
// the valid data.
assign true_stall_in = stall_in & ~consumed;
// Stall upstream if any downstream is stalling.
assign stall_out = |true_stall_in;
generate
if( DATA_WIDTH > 0 )
// Data out is just data in. Only valid if valid_out[i] is asserted.
assign data_out = data_in;
endgenerate
// Downstream output is valid if input is valid and the data has not
// already been consumed.
assign valid_out = {NUM_FANOUTS{valid_in}} & ~consumed;
// Consumed: a downstream interface has consumed its data if at least one
// downstream interface is stalling but not itself. The consumed state is
// only reset once all downstream interfaces have consumed their data.
//
// In the case where no downstream is stalling, the consumed bits are not
// used.
generate
for( i = 0; i < NUM_FANOUTS; i = i + 1 )
begin:c
always @( posedge clock or negedge resetn )
if( !resetn )
consumed[i] <= 1'b0;
else if( valid_in & (|true_stall_in) )
begin
// Valid data and there's at least one downstream interface
// stalling. Check if this interface is stalled...
if( ~stall_in[i] )
consumed[i] <= 1'b1;
end
else
consumed[i] <= 1'b0;
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; const int MAXN = 7007; const int MAXM = 300007; const int INF = 1 << 29; const int dir[][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; char reactor[15][15], rescue[15][15]; int N; int table[15][15]; bool isIn(int x, int y) { return x >= 1 && y >= 1 && x <= N && y <= N; } struct Edge { int u, v, cap, flow; Edge *next, *back; }; struct Graph { Edge *head[MAXN], adj[MAXM]; Edge *cur[MAXN], *path[MAXN]; int lev[MAXN]; int n, k; int S, T; void init(int nn) { S = 0, T = nn; n = nn, k = 0; for (int i = 0; i <= n; i++) head[i] = NULL; } void set(int s, int t) { S = s, T = t; } void addedge(int u, int v, int cap) { adj[k].u = u; adj[k].v = v; adj[k].flow = 0; adj[k].cap = cap; adj[k].next = head[u]; head[u] = adj + k++; } void add(int u, int v, int cap) { addedge(u, v, cap); addedge(v, u, 0); head[u]->back = head[v]; head[v]->back = head[u]; } bool bfs() { queue<int> q; fill(lev, lev + n + 1, -1); lev[S] = 0; q.push(S); int u, v; while (!q.empty()) { u = q.front(); q.pop(); for (Edge *f = head[u]; f; f = f->next) { if (f->flow == f->cap) continue; v = f->v; if (lev[v] == -1) { lev[v] = lev[u] + 1; q.push(v); if (v == T) return true; } } } return (lev[T] != -1); } int dinic() { int u, v, pt; int flow = 0; while (bfs()) { for (int i = 0; i <= n; i++) cur[i] = head[i]; pt = 0; u = S; while (true) { if (u == T) { int delta = INF, minI = 0; for (int i = 0; i < pt; i++) { if (delta > path[i]->cap - path[i]->flow) { delta = path[i]->cap - path[i]->flow; minI = i; } } for (int i = 0; i < pt; i++) { path[i]->flow += delta; path[i]->back->flow -= delta; } u = path[pt = minI]->u; flow += delta; } Edge *f; for (f = cur[u]; f; f = f->next) { if (f->cap == f->flow) continue; v = f->v; if (lev[v] == lev[u] + 1) break; } cur[u] = f; if (f) { path[pt++] = f; u = f->v; } else { lev[u] = -1; if (!pt) break; u = path[--pt]->u; } } } return flow; } } graph; void bfs(int sx, int sy, int t) { for (int i = 1; i <= N; i++) { fill(table[i], table[i] + N + 1, INF); } queue<pair<int, int> > q; q.push(pair<int, int>(sx, sy)); table[sx][sy] = 0; while (!q.empty()) { pair<int, int> cur = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int x = cur.first + dir[i][0]; int y = cur.second + dir[i][1]; if (!isIn(x, y) || !isdigit(reactor[x][y]) || table[x][y] != INF) { continue; } table[x][y] = table[cur.first][cur.second] + 1; q.push(pair<int, int>(x, y)); } } } int main() { int n, t; int S, T; scanf( %d%d , &n, &t); N = n; int sx, sy; for (int i = 1; i <= n; i++) { scanf( %s , reactor[i] + 1); for (int j = 1; j <= n; j++) { if (reactor[i][j] == Z ) { sx = i; sy = j; } } } bfs(sx, sy, t); for (int i = 1; i <= n; i++) { scanf( %s , rescue[i] + 1); } S = 0, T = (t + 1) * n * n + 1; graph.init(T); graph.set(S, T); for (int cur = 0; cur < t; cur++) { int add1 = cur * n * n; int add2 = (cur + 1) * n * n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (!isdigit(reactor[i][j])) continue; if (isdigit(rescue[i][j]) && rescue[i][j] != 0 ) { graph.add(add1 + (i - 1) * n + j, add2 + (i - 1) * n + j, rescue[i][j] - 0 ); if (cur >= table[i][j]) continue; } if (isdigit(reactor[i][j]) && cur < table[i][j]) { if (cur + 1 < table[i][j]) { graph.add(add1 + (i - 1) * n + j, add2 + (i - 1) * n + j, INF); } for (int k = 0; k < 4; k++) { int x = i + dir[k][0]; int y = j + dir[k][1]; if (!isIn(x, y) || !isdigit(reactor[x][y])) continue; if (cur + 1 < table[x][y] || table[x][y] == cur + 1 && isdigit(rescue[x][y])) graph.add(add1 + (i - 1) * n + j, add2 + (x - 1) * n + y, INF); } } } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (isdigit(reactor[i][j]) && reactor[i][j] != 0 ) { graph.add(S, (i - 1) * n + j, reactor[i][j] - 0 ); } if (isdigit(rescue[i][j]) && rescue[i][j] != 0 ) { graph.add(t * n * n + (i - 1) * n + j, T, rescue[i][j] - 0 ); } } } printf( %d n , graph.dinic()); return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file LVL_ROM.v when simulating
// the core, LVL_ROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module LVL_ROM(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [3 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("LVL_ROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3840),
.C_READ_DEPTH_B(3840),
.C_READ_WIDTH_A(4),
.C_READ_WIDTH_B(4),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3840),
.C_WRITE_DEPTH_B(3840),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(4),
.C_WRITE_WIDTH_B(4),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, u, r, i; bool flag = false; long long max_score = 0; vector<long long> a, b, k, p; inline long long score(vector<long long> a) { long long s = 0; for (i = (0); i < (n); ++i) { s += a[i] * k[i]; } return s; } vector<long long> permute(const vector<long long> &a) { vector<long long> temp(a.size()); for (i = (0); i < (n); ++i) { temp[i] = a[p[i] - 1] + r; } return temp; } void recurse(vector<long long> a, long long remain) { if (remain % 2 == 0) { long long sc = score(a); if (!flag || max_score < sc) { max_score = sc; flag = true; } } if (remain == 0) return; recurse(permute(a), remain - 1); remain--; for (i = (0); i < (n); ++i) { a[i] = a[i] ^ b[i]; } if (remain % 2 == 0) { long long sc = score(a); if (!flag || max_score < sc) { max_score = sc; flag = true; } } if (remain == 0) return; recurse(permute(a), remain - 1); } int main(int argc, char *argv[]) { cin >> n >> u >> r; a = vector<long long>(n); b = vector<long long>(n); p = vector<long long>(n); k = vector<long long>(n); for (i = (0); i < (n); ++i) { cin >> a[i]; } for (i = (0); i < (n); ++i) { cin >> b[i]; } for (i = (0); i < (n); ++i) { cin >> k[i]; } for (i = (0); i < (n); ++i) { cin >> p[i]; } recurse(a, u); cout << max_score << endl; return 0; }
|
`include "defines.v"
module mem_wb(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//À´×Էôæ½×¶ÎµÄÐÅÏ¢
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
input wire[`RegBus] mem_hi,
input wire[`RegBus] mem_lo,
input wire mem_whilo,
input wire mem_LLbit_we,
input wire mem_LLbit_value,
input wire mem_cp0_reg_we,
input wire[4:0] mem_cp0_reg_write_addr,
input wire[`RegBus] mem_cp0_reg_data,
//Ë͵½»Øд½×¶ÎµÄÐÅÏ¢
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata,
output reg[`RegBus] wb_hi,
output reg[`RegBus] wb_lo,
output reg wb_whilo,
output reg wb_LLbit_we,
output reg wb_LLbit_value,
output reg wb_cp0_reg_we,
output reg[4:0] wb_cp0_reg_write_addr,
output reg[`RegBus] wb_cp0_reg_data
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(flush == 1'b1 ) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `Stop && stall[5] == `NoStop) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
wb_cp0_reg_we <= `WriteDisable;
wb_cp0_reg_write_addr <= 5'b00000;
wb_cp0_reg_data <= `ZeroWord;
end else if(stall[4] == `NoStop) begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
wb_hi <= mem_hi;
wb_lo <= mem_lo;
wb_whilo <= mem_whilo;
wb_LLbit_we <= mem_LLbit_we;
wb_LLbit_value <= mem_LLbit_value;
wb_cp0_reg_we <= mem_cp0_reg_we;
wb_cp0_reg_write_addr <= mem_cp0_reg_write_addr;
wb_cp0_reg_data <= mem_cp0_reg_data;
end //if
end //always
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 400005; int tr[N << 2], lz[N << 2]; set<int> st[N]; inline void push(int v, int l, int r) { tr[v] += lz[v]; if (l != r) { lz[2 * v] += lz[v]; lz[2 * v + 1] += lz[v]; } lz[v] = 0; } void build(int v, int l, int r, int n) { lz[v] = 0; if (l == r) { tr[v] = l - 1; return; } int m = (l + r) / 2; build(2 * v, l, m, n); build(2 * v + 1, m + 1, r, n); tr[v] = max(tr[2 * v], tr[2 * v + 1]); } void update(int v, int s, int e, int l, int r, int x) { push(v, s, e); if (l <= s && e <= r) { tr[v] += x; if (s != e) { lz[2 * v] += x; lz[2 * v + 1] += x; } return; } if (r < s || e < l || l > r) return; int m = (s + e) / 2; update(2 * v, s, m, l, r, x); update(2 * v + 1, m + 1, e, l, r, x); tr[v] = max(tr[2 * v], tr[2 * v + 1]); } int query(int v, int s, int e, int l, int r) { push(v, s, e); if (l <= s && e <= r) return tr[v]; int m = (s + e) / 2; if (r <= m) return query(2 * v, s, m, l, r); if (m < l) return query(2 * v + 1, m + 1, e, l, r); return max(query(2 * v, s, m, l, r), query(2 * v + 1, m + 1, e, l, r)); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << setprecision(32); int n, k, m; cin >> n >> k >> m; int n2 = n << 1; build(1, 1, n2, n2); int x, y; map<int, int> mp; while (m--) { cin >> x >> y; y += abs(k - x); if (st[y].find(x) != st[y].end()) { update(1, 1, n2, 1, y, -1); st[y].erase(x); mp[y]--; if (!mp[y]) mp.erase(y); } else { update(1, 1, n2, 1, y, 1); st[y].insert(x); mp[y]++; } if (mp.empty()) { cout << 0 << n ; continue; } int mx = mp.rbegin()->first; cout << max(0, query(1, 1, n2, 1, mx) - n) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long x, y, u = 0, v = 0; vector<pair<long long, long long> > visited; void move(char c) { if (c == U ) v++; else if (c == D ) v--; else if (c == L ) u--; else u++; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> x >> y; if (x == 0 && y == 0) { cout << Yes ; return 0; } string s; cin >> s; for (long long i = 0; i < (long long)s.size(); ++i) { move(s[i]); if (u == x && v == y) { cout << Yes ; return 0; } visited.push_back(make_pair(u, v)); } if (u == 0 && v == 0) { cout << No ; return 0; } long long h_shift = u, v_shift = v; for (long long i = 0; i < (long long)s.size(); ++i) { move(s[i]); if (u == x && v == y) { cout << Yes ; return 0; } long long u_ref = x - visited[i].first; long long v_ref = y - visited[i].second; long long p = (h_shift ? u_ref % h_shift : u_ref); long long q = (v_shift ? v_ref % v_shift : v_ref); if (((u_ref < 0 && h_shift > 0) || (u_ref > 0 && h_shift < 0)) || ((v_ref < 0 && v_shift > 0) || (v_ref > 0 && v_shift < 0))) continue; if (p == 0 && q == 0 && (u_ref * v_shift == v_ref * h_shift)) { cout << Yes ; return 0; } } cout << No ; return 0; }
|
//This is essentially a 24h digital clock
//Clk is a 1hz clock that will add a second to the initial time set
//Load must be a key!! allows setting an initial value for the digital clock
//output current time: chour: cminute: csecond
module run_clock (nLoad, Clk, hour2, hour1, minute2, minute1, second2, second1,
chour2, chour1, cminute2, cminute1, csecond2, csecond1);
input Clk, nLoad;
input [3:0] hour2, hour1, minute2, minute1, second2, second1;
output reg [3:0] chour2, chour1, cminute2, cminute1, csecond2, csecond1;
always @ (posedge Clk, negedge nLoad)
//load initial values of the clock
//similar to a reset
begin
if (~nLoad)
begin
chour2 <= hour2; chour1 <= hour1; cminute2 <= minute2; cminute1 <= minute1; csecond2 <= second2; csecond1 <= second1;
end
//run the clock
else
begin
csecond1 <= csecond1 + 1;
//seconds
if (csecond1 > 8)
begin
csecond2 <= csecond2 + 1;
csecond1 <= 0;
end
if ((csecond2 == 5)&(csecond1 == 9))
begin
cminute1 <= cminute1 + 1;
csecond2 <= 0;
csecond1 <= 0;
end
//minutes
if ((cminute2 < 5) & (cminute1 == 9) & (csecond2 == 5) & (csecond1 == 9))
begin
cminute2 <= cminute2 + 1;
cminute1 <= 0;
end
if ((cminute2 == 5)&(cminute1 == 9)&(csecond2 == 5)&(csecond1 == 9))
begin
chour1 <= chour1 + 1;
cminute2 <= 0;
cminute1 <= 0;
end
//hours
if ((chour2 < 2) & (chour1 == 9) & (cminute2 == 5) & (cminute1 == 9) & (csecond2 == 5) & (csecond1 == 9))
begin
chour2 <= chour2 + 1;
chour1 <= 0;
end
if ((chour2 == 2)&(chour1 == 3)&(cminute2 == 5)&(cminute1 == 9)&(csecond2==5)&(csecond1==9))
begin
chour2 <= 0;
chour1 <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using vi = std::vector<long long int>; using vvi = std::vector<vi>; using pii = std::pair<long long int, long long int>; using vpii = std::vector<pii>; using vvpii = std::vector<vpii>; using namespace std; const long long int N = 2e6 + 10; const long long int inf = 1e18 + 10; const long double Pi = 3.14159265; long long int n; vi a; long long int f(vi &a) { long long int n = a.size(); if (a.empty() == 1) return 0; if (a.back() == 0) return a.size(); long long int hig = 0; for (long long int i = 0; i <= n - 1; i++) { hig = max(hig, (long long int)log2(a[i])); } vi l, r; for (long long int i = 0; i <= n - 1; i++) { if ((long long int)log2(a[i]) < hig) l.emplace_back(a[i]); else r.emplace_back(a[i] ^ (1 << (long long int)log2(a[i]))); } if (!(l.size() < r.size())) swap(l, r); a = vi(); if (l.size() == 0) return f(r); return 1 + max(f(l), f(r)); } void solve() { cin >> n; a.resize(n); for (long long int i = 1; i <= n; i++) cin >> a[i - 1]; sort(a.begin(), a.end()); cout << (a.size() - f(a)); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); return 0; long long int xx = 0; long long int t; cin >> t; while (t--) { ; solve(); cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_2_V
`define SKY130_FD_SC_MS__OR4BB_2_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4bb_2 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4bb_2 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_2_V
|
// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "simulation_includes.vh"
module uart_tasks;
// Configure WB UART in testbench
// 115200, 8N1
//
task uart_config;
begin
$display("\033[93mTASK: UART Configure\033[0m");
@(posedge `UART_CLK);
//Turn on receive data interrupt
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00010000);
@(posedge `UART_CLK);
//FIFO Control, interrupt for each byte, clear fifos and enable
`UART_MASTER0.wb_wr1(32'hFFFF0002, 4'h2, 32'h00000700);
@(posedge `UART_CLK);
//Line Control, enable writting to the baud rate registers
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000080);
@(posedge `UART_CLK);
//Baud Rate LSB
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h0000001A); //115200bps from 50 MHz
@(posedge `UART_CLK);
//Baud Rate MSB
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00000000);
@(posedge `UART_CLK);
//Line Control, 8 bits data, 1 stop bit, no parity
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000003);
end
endtask // uart_config
//
// Write a character to WB UART and catch with FPGA UART
//
task uart_write_char;
input [7:0] char;
begin
//
// Write the character to the WB UART to send to FPGA UART
//
@(posedge `UART_CLK);
$display("TASK: UART Write = %c @ %d", char, $time);
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h8, {char, 24'h000000});
end
endtask // uart_write_char
//
// Read a character with WB UART that was sent from FPGA UART
//
task uart_read_char;
input [7:0] expected;
begin
$display("Reading 0x%x @ %d", expected, $time);
if (!testbench.uart0_int)
@(posedge testbench.uart0_int);
`UART_MASTER0.wb_rd1(32'hFFFF0000, 4'h8, testbench.read_word);
$display("TASK: UART Read = %c @ %d", testbench.read_word[31:24], $time);
if (testbench.read_word[31:24] !== expected)
begin
$display("\033[1;31mFAIL: UART Read = 0x%h NOT 0x%h @ %d\033[0m", testbench.read_word[31:24], expected, $time);
`TEST_FAILED <= 1;
end
@(posedge testbench.wb_clk);
end
endtask // uart_read_char
endmodule // uart_tasks
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:29:53 10/26/2015
// Design Name: UART_tx
// Module Name: C:/Users/Ariel/Xilinx/Workspace/UART/TXTest.v
// Project Name: UART
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TXTest;
// Inputs
reg clock;
reg reset;
reg s_tick;
reg tx_start;
reg [7:0] data_in;
// Outputs
wire tx;
wire tx_done;
wire baud_rate_clock;
// Instantiate the Unit Under Test (UUT)
UART_tx uut (
.clock(clock),
.reset(reset),
.s_tick(baud_rate_clock),
.tx_start(tx_start),
.data_in(data_in),
.tx(tx),
.tx_done(tx_done)
);
// Instantiate the Unit Under Test (UUT)
UART_baud_rate_generator #(.COUNT(2608)) baud_rate (
.clock(clock),
.baud_rate_clock(baud_rate_clock)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
s_tick = 0;
tx_start = 1;
data_in = 48;
// Wait 100 ns for global reset to finish
#100;
reset=1;
#100;
reset=0;
// Add stimulus here
end
always begin
clock = ~clock;
#3;
end
always begin
#1000;
tx_start=0;
#1000;
tx_start=1;
#500000;
data_in=data_in+5;
#100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double pi = acos(-1); long long power(long long a, long long b) { long long p_res = 1; while (b > 0) { if (b % 2 == 1) { p_res *= a; b--; } a *= a; b /= 2; } return p_res; } int cc[300001]; int ans[300001]; set<pair<int, int> > ss; set<pair<int, int> >::iterator it; vector<int> adj[300001]; int n, q; int dfs(int here) { int res = 1; for (int i = 0; i < adj[here].size(); i++) { res += dfs(adj[here][i]); } cc[here] = res; return res; } void centroid(int here, int prev) { int mx = 0; for (int i = 0; i < adj[here].size(); i++) { int next = adj[here][i]; mx = max(mx, cc[next]); } if (2 * mx <= cc[here]) ans[here] = here; else ss.insert(make_pair(cc[here], here)); it = ss.lower_bound(make_pair(2 * mx, -1)); while (it != ss.end()) { int v = it->first; int i = it->second; if (v > 2 * cc[here]) break; if (2 * mx <= v && 2 * (v - cc[here]) <= v) { ans[i] = here; ss.erase(it++); } else it++; } for (int i = 0; i < adj[here].size(); i++) { centroid(adj[here][i], here); } } int main() { scanf( %d %d , &n, &q); for (int i = 2; i <= n; i++) { int v; scanf( %d , &v); adj[v].push_back(i); } dfs(1); centroid(1, -1); for (int i = 0; i < q; i++) { int v; scanf( %d , &v); printf( %d n , ans[v]); } return 0; }
|
#include <bits/stdc++.h> long long k, pa, pb, dp[1107][1107]; int main() { scanf( %lld%lld%lld , &k, &pa, &pb); long long invb = 1, base = pb; for (int t = 1000000007 - 2; t; t >>= 1, (base *= base) %= 1000000007) if (t & 1) (invb *= base) %= 1000000007; long long inva_b = 1; base = pa + pb; for (int t = 1000000007 - 2; t; t >>= 1, (base *= base) %= 1000000007) if (t & 1) (inva_b *= base) %= 1000000007; long long invab = pa * invb % 1000000007; pa *= inva_b; pa %= 1000000007; pb *= inva_b; pb %= 1000000007; for (int i = k; ~i; --i) for (int j = k; ~j; --j) if (i + j >= k) dp[i][j] = (i + j + invab) % 1000000007; else dp[i][j] = pa * dp[i + 1][j] % 1000000007 + pb * dp[i][i + j] % 1000000007, dp[i][j] %= 1000000007; printf( %lld n , dp[1][0]); return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: FIFO_WRITE.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_WRITE (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [7:0] q = sub_wire1[7:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=7,",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_WRITE_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; int M = 1000000007; map<string, long long int> b1; int main() { ios ::sync_with_stdio(false); cin.tie(0); long long int n, k; cin >> n >> k; long long int c = max(n - 2 * k, 0ll); long long int a = n * (n - 1) / 2 - c * (c - 1) / 2; cout << a << endl; }
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#include <bits/stdc++.h> using namespace std; long long int sum, max_lev; vector<pair<long long int, long long int>> level[5010]; vector<long long int> adj[5010]; vector<pair<long long int, long long int>> store[5010]; vector<pair<pair<long long int, long long int>, long long int>> v; long long int vis[5010]; void bfs(long long int s, long long int lev) { queue<pair<long long int, long long int>> q; q.push(make_pair(s, lev)); vis[s] = 1; while (!q.empty()) { s = q.front().first; lev = q.front().second; for (long long int i = 0; i < store[s].size(); i++) { level[lev].push_back(make_pair(store[s][i].first, store[s][i].second)); sum += store[s][i].first; } q.pop(); max_lev = max(lev, max_lev); for (long long int i = 0; i < adj[s].size(); i++) { if (vis[adj[s][i]] == 0) { vis[adj[s][i]] = 1; q.push(make_pair(adj[s][i], lev + 1)); } } } } bool check(long long int mid, long long int max_cost, long long int tot) { long long int cost = 0, curr = 0, p, rem, i, j; for (i = 0; i < v.size(); i++) { if (v[i].second > mid) continue; p = v[i].first.first * v[i].first.second; if (cost + p > max_cost) { rem = max_cost - cost; p = rem / v[i].first.first; curr += p; break; } curr += v[i].first.second; cost += p; } if (curr >= tot) return true; return false; } long long int bs(long long int low, long long int high, long long int max_cost, long long int tot) { long long int ans = -1; while (low <= high) { long long int mid = (low + high) / 2; if (check(mid, max_cost, tot)) { high = mid - 1; ans = mid; } else { low = mid + 1; } } return ans; } int main() { long long int n, m, a, b, i, w, c, k, p, q, g, r, j; ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (i = 1; i <= m; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } cin >> w; for (i = 1; i <= w; i++) { cin >> c >> k >> p; store[c].push_back(make_pair(k, p)); } cin >> q; while (q--) { sum = max_lev = 0; cin >> g >> r >> a; for (i = 0; i <= n; i++) level[i].clear(); v.clear(); memset(vis, 0, sizeof(vis)); bfs(g, 0); if (sum < r) { cout << -1 n ; continue; } for (i = 0; i <= max_lev; i++) { for (j = 0; j < level[i].size(); j++) { v.push_back( make_pair(make_pair(level[i][j].second, level[i][j].first), i)); } } sort(v.begin(), v.end()); cout << bs(0, max_lev, a, r) << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n; int head[N], Next[N << 1], ver[N << 1], size[N], edge[N << 1], w[N]; int tot; long long ans; void add(int x, int y, int z) { ver[++tot] = y; edge[tot] = z; Next[tot] = head[x]; head[x] = tot; } void dfs(int x, int fa) { size[x] = 1; for (int i = head[x]; i; i = Next[i]) { int y = ver[i]; if (y == fa) continue; dfs(y, x); size[x] += size[y]; } } void solve(int x, int fa, long long s) { for (int i = head[x]; i; i = Next[i]) { int y = ver[i], z = edge[i]; if (y == fa) continue; if (s + (long long)z > (long long)w[y]) ans += (long long)size[y]; else solve(y, x, max(0ll, s + (long long)z)); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &w[i]); for (int i = 2; i <= n; i++) { int p, c; scanf( %d%d , &p, &c); add(p, i, c); add(i, p, c); } dfs(1, 0); solve(1, 0, 0ll); printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long long power(long long base, long long exp) { long long res = 1; while (exp > 0) { if (exp % 2 == 1) res = (res * base); base = (base * base); exp /= 2; } return res; } long long mod(long long a, long long b) { return (a % b + b) % b; } long long powerm(long long base, long long exp, long long mod) { long long ans = 1; while (exp) { if (exp & 1) ans = (ans * base) % mod; exp >>= 1, base = (base * base) % mod; } return ans; } struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t; t = 1; while (t--) { string s; cin >> s; cout << s; for (long long i = s.size() - 1; i >= 0; i--) cout << s[i]; cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long sign(long long x) { return x < 0 ? -1 : 1; } pair<long long, long long> part(long long from, long long to, long long s, long long dir) { pair<long long, long long> res{dir, abs(to - from)}; if (to != from && sign(to - from) != sign(dir)) { res.first *= -1; res.second += 2 * abs(from - (dir == -1 ? 0 : s)); } return res; } long long solve(long long s, long long x1, long long x2, long long t1, long long t2, long long p, long long d) { auto toTram = part(p, x1, s, d); return min(part(x1, x2, s, sign(x2 - x1)).second * t2, (toTram.second + part(x1, x2, s, toTram.first).second) * t1); } void tests() { assert(7 == solve(10, 3, 8, 1, 2, 1, 1)); assert(9 == solve(10, 3, 8, 1, 2, 1, -1)); assert(10 == solve(10, 3, 8, 1, 2, 2, -1)); assert(12 == solve(10, 3, 8, 1, 5, 4, -1)); assert(24 == solve(10, 3, 8, 1, 5, 4, 1)); assert(20 == solve(10, 3, 8, 1, 4, 4, 1)); assert(15 == solve(10, 3, 8, 1, 3, 10, -1)); assert(18 == solve(10, 3, 8, 1, 4, 10, -1)); assert(19 == solve(10, 3, 8, 1, 4, 9, 1)); assert(20 == solve(10, 3, 8, 2, 4, 9, 1)); assert(5 == solve(10, 3, 8, 1, 4, 3, 1)); assert(11 == solve(10, 3, 8, 1, 4, 3, -1)); assert(20 == solve(10, 3, 8, 1, 5, 8, 1)); assert(16 == solve(10, 3, 8, 1, 4, 8, -1)); assert(5 + 4 + 5 == solve(10, 8, 3, 1, 4, 3, 1)); assert(6 + 5 + 4 + 5 == solve(10, 8, 3, 1, 5, 3, -1)); assert(4 + 5 == solve(10, 8, 3, 1, 4, 8, 1)); assert(5 == solve(10, 8, 3, 1, 4, 8, -1)); assert(8 == solve(4, 2, 4, 3, 4, 1, 1)); assert(7 == solve(5, 4, 0, 1, 2, 3, 1)); } int main() { tests(); long long s, x1, x2, t1, t2, p, d; while (cin >> s >> x1 >> x2 >> t1 >> t2 >> p >> d) { cout << solve(s, x1, x2, t1, t2, p, d) << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; vector<vector<vector<long long>>> g(n); vector<vector<long long>> store(m); for (long long i = 0; i < m; i++) { long long a, b, c; cin >> a >> b >> c; --a; b--; g[a].push_back({b, c}); g[b].push_back({a, c}); store[i] = {a, b, c}; } long long s; cin >> s; s--; vector<long long> d(n, LONG_LONG_MAX); vector<long long> parent(n), dd(n, LONG_LONG_MAX); for (long long i = 0; i < n; i++) { parent[i] = i; } d[s] = dd[s] = 0; set<pair<long long, long long>> q; q.insert({d[s], s}); while (!q.empty()) { long long v = q.begin()->second; q.erase(q.begin()); for (long long i = 0; i < g[v].size(); i++) { long long to = g[v][i][0], len = g[v][i][1]; if (d[v] + len < d[to]) { if (q.find({d[to], to}) != q.end()) { q.erase({d[to], to}); } parent[to] = v; d[to] = d[v] + len; dd[to] = len; q.insert(make_pair(d[to], to)); } else if (d[v] + len == d[to]) { if (dd[to] > len) { dd[to] = len; parent[to] = v; } } } } long long ans = 0; for (long long i = 0; i < n; i++) { ans += dd[i]; } cout << ans << endl; for (long long i = 0; i < m; i++) { long long a = store[i][0]; long long b = store[i][1]; if (parent[a] == b || parent[b] == a) { cout << i + 1 << ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { map<string, bool> vis; int n; scanf( %d , &n); while (n--) { string s; cin >> s; if (vis[s]) puts( YES ); else puts( NO ); vis[s] = 1; } return 0; }
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//
// 8192 bytes, 32bit interface
`timescale 1ns/1ps
module next_hop_ram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [12:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
wire [3:0] dip;
RAMB16_S9_altera ram0 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[7:0] ),
.rden ( en ),
.wren ( we[0] ),
.q ( data_out[7:0] )
);
defparam ram0.init_file = "next_hop_ram00.mif";
RAMB16_S9_altera ram1 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[15:8] ),
.rden ( en ),
.wren ( we[1] ),
.q ( data_out[15:8] )
);
defparam ram1.init_file = "next_hop_ram01.mif";
RAMB16_S9_altera ram2 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[23:16] ),
.rden ( en ),
.wren ( we[2] ),
.q ( data_out[23:16] )
);
defparam ram2.init_file = "next_hop_ram02.mif";
RAMB16_S9_altera ram3 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[31:24] ),
.rden ( en ),
.wren ( we[3] ),
.q ( data_out[31:24] )
);
defparam ram3.init_file = "next_hop_ram03.mif";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_SYMBOL_V
`define SKY130_FD_SC_HS__NAND2_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int LEN = 100009; int n; int a[LEN]; int ch = 0, nech = 0; int ans = 0; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (a[i] % 2 == 0) ch++; else nech++; } ans = min(ch, nech); while (nech > 1) { nech -= 2; ch++; ans = max(ans, min(ch, nech)); } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MX = 500005; const int MC = 2; int get(char c) { if (c == ( ) return 0; return 1; } struct Node { int l, r, pardp; Node *par, *sLink; Node *chd[MC]; bool isLeaf; int st; Node() { l = r = pardp = 0; par = sLink = NULL; st = 0; isLeaf = true; memset(chd, 0, sizeof chd); } int len() { return r - l; } int depth() { return pardp + len(); } bool inEdge(int pos) { return pos >= pardp && pos < depth(); } void setEdge(Node *child, int l, int r, char *S) { child->par = this; child->pardp = depth(); chd[get(S[l])] = child; child->l = l, child->r = r; isLeaf = false; } void print(char *S) { for (int i = l; i < r; i++) putchar(S[i]); puts( ); } }; struct Data { int l, r, x; Data(int l = 0, int r = 0, int x = 0) : l(l), r(r), x(x) {} bool operator<(const Data &b) const { return l < b.l; } }; vector<Data> que; struct STree { Node *root, *needSLink, *cur; int jj, m, size; bool needWalk; vector<Node> nodes; char *S; STree(char *str) { m = strlen(str); S = str; nodes.reserve(m * 2 + 10); jj = 1, size = 0; root = newNode(); cur = newNode(); root->setEdge(cur, 0, m, S); needSLink = NULL; needWalk = true; for (int i = 0; i < m - 1; i++) extend(i); } Node *newNode() { nodes.push_back(Node()); return &nodes[size++]; } Node *walk_down(Node *c, int j, int i) { if (i - j + 1 > 0) for (int h = j + c->depth(); !c->inEdge(i - j); h += c->len()) c = c->chd[get(S[h])]; return c; } void addSLink(Node *c) { if (needSLink) needSLink->sLink = c; needSLink = NULL; } void extend(int i) { char c = S[i + 1]; Node *leaf, *split; int k, pos; for (; jj <= i + 1; jj++) { if (needWalk) { if (!cur->sLink && cur->par) cur = cur->par; cur = (cur->sLink) ? cur->sLink : root; cur = walk_down(cur, jj, i); } needWalk = true; k = i + 1 - jj; if (cur->depth() == k) { addSLink(cur); if (cur->chd[get(c)]) { cur = cur->chd[get(c)]; needWalk = false; break; } else { leaf = newNode(); cur->setEdge(leaf, i + 1, m, S); } } else { pos = cur->l + k - cur->pardp; if (S[pos] == c) { addSLink(cur); needWalk = false; break; } else { leaf = newNode(); split = newNode(); cur->par->setEdge(split, cur->l, pos, S); split->setEdge(cur, pos, cur->r, S); split->setEdge(leaf, i + 1, m, S); addSLink(split); if (split->depth() == 1) split->sLink = root; else needSLink = split; cur = split; } } } } void calc(Node *c) { int bf = 0; int l = c->l - c->pardp, r = c->r; if (r) que.push_back(Data(l, r, 1)); for (int i = 0; i < MC; i++) if (c->chd[i]) { if (r) que.push_back(Data(l, r, -1)); calc(c->chd[i]); bf++; } } }; char A[MX]; int val[MX * 4], cnt[MX * 4], dn[MX * 4]; int p[MX]; void add(pair<int, int> &p, pair<int, int> q) { p.first = min(p.first, q.first); p.second += q.second; } void up(int u) { int l = u * 2, r = u * 2 + 1; val[u] = min(val[l], val[r]); cnt[u] = 0; if (val[u] == val[l]) cnt[u] += cnt[l]; if (val[u] == val[r]) cnt[u] += cnt[r]; } void renew(int u, int x) { val[u] += x; dn[u] += x; } void down(int u) { val[u] += dn[u]; renew(u * 2, dn[u]); renew(u * 2 + 1, dn[u]); dn[u] = 0; } void build(int u, int l, int r) { if (l == r) { val[u] = p[l]; cnt[u] = 1; dn[u] = 0; return; } int md = (l + r) / 2; build(u * 2, l, md); build(u * 2 + 1, md + 1, r); up(u); } void add(int u, int l, int r, int st, int en, int x) { if (st <= l && r <= en) { renew(u, x); return; } int md = (l + r) / 2; down(u); if (st <= md) add(u * 2, l, md, st, en, x); if (md < en) add(u * 2 + 1, md + 1, r, st, en, x); up(u); } int bf = false; pair<int, int> get(int u, int l, int r, int st, int en) { pair<int, int> ret(0, 0); if (st <= l && r <= en) { if (val[u] == 0) return pair<int, int>(val[u], cnt[u]); if (val[u] > 0) return pair<int, int>(val[u], 0); if (l == r) return pair<int, int>(val[u], 0); down(u); int md = (l + r) / 2; ret = get(u * 2, l, md, st, en); if (ret.first >= 0) { add(ret, get(u * 2 + 1, md + 1, r, st, en)); } up(u); return ret; } int md = (l + r) / 2; down(u); if (st <= md) ret = get(u * 2, l, md, st, en); if (md < en) if (ret.first >= 0) add(ret, get(u * 2 + 1, md + 1, r, st, en)); up(u); return ret; } int main() { int n; scanf( %d%s , &n, A); STree tr(A); int dp = 0; for (int i = 0; i < n; i++) { if (A[i] == ( ) dp++; else dp--; p[i + 1] = dp; } build(1, 1, n); tr.calc(tr.root); sort(que.begin(), que.end()); int lft = 0; long long ans = 0; for (int i = 0; i < que.size();) { while (lft < que[i].l) { if (A[lft] == ( ) add(1, 1, n, 1, n, -1); else add(1, 1, n, 1, n, 1); lft++; } while (i < que.size() && que[i].l == lft) { pair<int, int> ret = get(1, 1, n, lft + 1, que[i].r); ans += ret.second * que[i].x; i++; } } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long inf = 1e18 + 1; int n, ans[51], t[51]; long long k, fac[51], dp[51]; bool v[51]; long long mul(long long x, long long y) { return !x ? 0 : inf / x < y ? inf : x * y; } long long cal(int x) { return x < 2 ? 1 : fac[x - 2]; } void work(int l, int r) { for (auto i = (l); i <= (r); ++i) t[i] = i, v[i] = 0; ans[l] = r; v[r] = 1; swap(t[l], t[r]); for (auto i = (l + 1); i <= (r - 1); ++i) { for (auto j = (l); j <= (r); ++j) if (!v[j] && i != t[j]) { if (mul(fac[r - i - 1], dp[n - r]) >= k) { ans[i] = j; v[j] = 1; int x = t[i], y = t[j]; t[x] = y; t[y] = x; break; } else k -= mul(fac[r - i - 1], dp[n - r]); } } ans[r] = t[r]; } void sol() { scanf( %d%lld , &n, &k); if (dp[n] < k) return (void)printf( -1 n ); int nw = 1; while (nw <= n) for (auto i = (1); i <= (n - nw + 1); ++i) { if (mul(cal(i), dp[n - nw - i + 1]) >= k) { work(nw, nw + i - 1); nw += i; break; } else k -= mul(cal(i), dp[n - nw - i + 1]); } for (auto i = (1); i <= (n); ++i) printf( %d%c , ans[i], i == n ? n : ); } int main() { int t; fac[0] = 1; dp[0] = 1; for (auto i = (1); i <= (50); ++i) fac[i] = mul(fac[i - 1], i); for (auto i = (1); i <= (50); ++i) for (auto j = (1); j <= (i); ++j) dp[i] = min(inf, dp[i] + mul(dp[i - j], cal(j))); scanf( %d , &t); for (auto i = (1); i <= (t); ++i) sol(); }
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#include <bits/stdc++.h> using namespace std; char S[5000005], T[5000005]; int n, l = 1, tot = 0, R[5000005], st[5000005], ed[5000005]; void modify() { T[0] = $ , T[1] = # ; for (int i = 0; i < n; ++i) T[++l] = S[i], T[++l] = # ; T[++l] = 0 ; } void Manacher() { int p = 0, mx = 0; for (int i = 1; i < l; ++i) { R[i] = (mx > i) ? min(R[2 * p - i], mx - i) : 1; while (T[i - R[i]] == T[i + R[i]]) R[i]++; if (mx < i + R[i]) mx = i + R[i], p = i; st[i - R[i] + 1]++, st[i + 1]--; ed[i]++, ed[i + R[i]]--, tot = (tot + R[i] / 2) % 51123987; } tot = (1ll * tot * (tot - 1) / 2) % 51123987; } int main() { int i, ans = 0, sum = 0; scanf( %d%s , &n, S); modify(), Manacher(); for (i = 1; i < l; i++) { st[i] += st[i - 1]; ed[i] += ed[i - 1]; if (T[i] != # ) { ans = (ans + 1ll * sum * st[i] % 51123987) % 51123987; sum = (sum + ed[i]) % 51123987; } } printf( %d , (tot - ans + 51123987) % 51123987); return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long mmul(long long a, long long b) { return (a * b) % 998244353; } inline long long madd(long long a, long long b) { return (a + b) % 998244353; } long long mpow(long long a, long long p) { if (p == 0) return 1; long long halfPow = mpow(a, p / 2); return mmul(halfPow, p % 2 ? mmul(a, halfPow) : halfPow); } long long minv(long long a) { return mpow(a, 998244353 - 2); } long long mdiv(long long a, long long b) { return mmul(a, minv(b)); } vector<long long> _mfactMem(1, 1); long long mfact(long long a) { if (a >= 998244353) return 0; while (a >= _mfactMem.size()) _mfactMem.push_back(mmul(_mfactMem.size(), _mfactMem.back())); return _mfactMem[a]; } long long mcomb(long long n, long long k) { if (n == 0 && k == 0) return 1; long long ni = n % 998244353, ki = k % 998244353; if (ni < ki) return 0; long long comb = mmul(mfact(ni), mmul(minv(mfact(ki)), minv(mfact(ni - ki)))); return mcomb(n / 998244353, k / 998244353) * comb; } long long calc(int na, int nb) { long long cnt = 0; for (int i = 0; i <= min(na, nb); i++) { cnt = madd(cnt, mmul(mfact(i), mmul(mcomb(na, i), mcomb(nb, i)))); } return cnt; } int main() { int a, b, c; scanf( %d %d %d n , &a, &b, &c); int res = (int)mmul(calc(a, b), mmul(calc(b, c), calc(c, a))); printf( %d n , res); return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top RAT_slice_7_0_0 -prefix
// RAT_slice_7_0_0_ RAT_slice_7_3_0_stub.v
// Design : RAT_slice_7_3_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_slice_7_0_0(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[17:0],Dout[4:0]" */;
input [17:0]Din;
output [4:0]Dout;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : 2D Cache Top Level
// File : ded_ca_top.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_ca_top
#(parameter BYTES = 4)
(
input mclock,
input mc_push,
`ifdef BYTE16 input [2:0] mc_addr,
`elsif BYTE8 input [3:0] mc_addr,
`else input [4:0] mc_addr,
`endif
input hclock,
input hb_we,
input [4:0] hb_addr,
input [(BYTES*8)-1:0] hb_dout_ram,
`ifdef BYTE16 input [2:0] rad,
`elsif BYTE8 input [3:0] rad,
`else input [4:0] rad, `endif
`ifdef BYTE16 output [3:0] ca_enable,
`elsif BYTE8 output [1:0] ca_enable,
`else output ca_enable,
`endif
output [31:0] hb_dout,
output [4:0] hb_ram_addr,
output [4:0] ca_ram_addr0,
output [4:0] ca_ram_addr1
);
`ifdef BYTE16
wire [2:0] radp1;
assign radp1 = rad + 3'h1;
assign hb_dout = hb_dout_ram[hb_addr[1:0]*32 +: 32];
assign ca_enable[0] = hb_we & (hb_addr[1:0] == 2'd0);
assign ca_enable[1] = hb_we & (hb_addr[1:0] == 2'd1);
assign ca_enable[2] = hb_we & (hb_addr[1:0] == 2'd2);
assign ca_enable[3] = hb_we & (hb_addr[1:0] == 2'd3);
assign hb_ram_addr = {2'b0, hb_addr[4:2]};
assign ca_ram_addr0 = (mc_push) ? {2'b0, mc_addr} : {2'b0, rad};
assign ca_ram_addr1 = (mc_push) ? {2'b0, mc_addr} : {2'b0, radp1};
`elsif BYTE8
wire [3:0] radp1;
assign radp1 = rad + 1;
assign hb_dout = hb_dout_ram[hb_addr[0]*32 +: 32];
assign ca_enable[0] = hb_we & (hb_addr[0] == 1'b0);
assign ca_enable[1] = hb_we & (hb_addr[0] == 1'b1);
assign hb_ram_addr = {1'b0, hb_addr[4:1]};
assign ca_ram_addr0 = (mc_push) ? {1'b0, mc_addr} : {1'b0, rad};
assign ca_ram_addr1 = (mc_push) ? {1'b0, mc_addr} : {1'b0, radp1};
`else
wire [4:0] radp1;
assign radp1 = rad + 1;
assign hb_dout = hb_dout_ram[31:0];
assign ca_enable = hb_we;
assign hb_ram_addr = hb_addr[4:0];
assign ca_ram_addr0 = (mc_push) ? mc_addr : rad;
assign ca_ram_addr1 = (mc_push) ? mc_addr : radp1;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 20; const int Maxmask = (1 << 16); int out[Maxn][Maxn]; bool making[Maxn][Maxmask]; int n; int s; int a[Maxn * Maxn]; int mod; void input() { cin >> n; for (int i = 0; i < n * n; i++) { cin >> a[i]; s += a[i]; } s /= n; } void place() { for (int i = 0; i < n * n; i++) out[i / n][i % n] = a[i]; } bool is_true() { int t; for (int i = 0; i < n; i++) { t = 0; for (int j = 0; j < n; j++) t += out[i][j]; if (t != s) return false; t = 0; for (int j = 0; j < n; j++) t += out[j][i]; if (t != s) return false; } t = 0; for (int i = 0; i < n; i++) t += out[i][i]; if (t != s) return false; t = 0; for (int i = 0; i < n; i++) t += out[i][n - i - 1]; if (t != s) return false; return true; } bool found() { int b[] = {2, 7, 6, 9, 5, 1, 4, 3, 8}; for (int i = 0; i < n * n; i++) if (a[i] != b[i]) return false; return true; } void calc_3() { sort(a, a + n * n); while (1) { place(); if (is_true()) break; next_permutation(a, a + (n * n)); } } void output() { cout << s << n ; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cout << out[i][j] << ; cout << n ; } } int main() { input(); calc_3(); output(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int func(int n) { int sum = 1; if (n == 3) return 4; if (n == 2) return 2; if (n == 1) return 1; if (n % 2 == 0) { sum += 2 * (n / 2 - 1) + 1 + func(n - 2); } else { sum += 2 * (n - 1) / 2 + func(n - 2); } return sum; } int main() { { int n; int r = 1; int i = 0; cin >> n; cout << func(n); return 0; } }
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_vcc_0 (
dout
);
output wire [1-1 : 0] dout;
xlconstant #(
.CONST_VAL(1'd1),
.CONST_WIDTH(1)
) inst (
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A41OI_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool compare(int a, int b) { return a > b; } int main() { int n, a, index; cin >> n; vector<int> A; int temp; int count = 0; for (int i = 0; i < n; i++) { cin >> a; A.push_back(a); } for (int i = 0; i < n; i++) { if (A[i] == 1) { count++; index = i; break; } } for (int i = index + 1; i < n; i++) { if (A[i] == 1 && A[i - 1] == 1) count++; else if (A[i] == 1 && A[i - 1] == 0) count += 2; else continue; } cout << count; return 0; }
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#include <bits/stdc++.h> using namespace std; #define F first #define S second typedef pair<int, int> pi; typedef long long ll; const ll big = 1e6 + 9; ll GCD(ll a,ll b) { if(!b) return a; return GCD(b, a % b); } ll LCM(ll a,ll b) { return a*b/GCD(a,b); } int main() {ios_base::sync_with_stdio(0); cin.tie(0);cout.tie(0); ll t; cin >> t; while(t--) { string s, t; cin >> s >> t; ll n1 = s.size(), n2 = t.size(); ll lcm = LCM(n1,n2); ll k1 = lcm/n1, k2 = lcm/n2; k1--,k2--; string s1 = s, t1 = t; while(k1--) s += s1; while(k2--) t += t1; if(s == t) cout << s << n ; else cout << -1 n ; } return 0; }
|
// *****************************
// Luis F. Mora
// B24449
// Circuitos Digitales II
// Prof. Enrique Coen
// *****************************
module probador_dma(output reg reset,
output reg clk, // Señales de entrada del DMA
output reg TFC, // Senal del fifo (cuando system_address = data_address + length)
output reg cmd_reg_write, // Senal de inicio
output reg cmd_reg_read, // Senal de inicio
output reg Continue, // Senal de reanudacion
output reg TRAN, // Parte del descriptor address
output reg STOP, // Interrupt signal
output reg empty, // fifo empty
output reg full, // fifo full
output reg [63:0] data_address, // Posicion donde empieza el dato (Address Field del Address Descriptor)
output reg [15:0] length, // Tamano del dato en bytes (Length del Address Descriptor)
output reg [5:0] descriptor_index, // Descriptor table de 64 entradas -> 6 bits de indexacion
output reg act1, // Attribute[4]
output reg act2, // Attribute[3]
output reg END, // Attribute [2]
output reg valid, // Attribute[1]
output reg dir);
always begin // Señal de reloj del host
#5 clk =! clk;
end
initial begin
$dumpfile("testDMA.vcd");
$dumpvars(0,probador_dma);
// Inicializar variables
reset = 1;
clk = 0;
TFC = 0;
cmd_reg_write = 0; // luego se activa para iniciar el DMAC
cmd_reg_read = 0; // Senal de inicio
Continue = 0; // Senal de reanudacion / no aplica en este caso porque no se van a considerar interrupciones del cpu
TRAN = 0; // Parte del descriptor address
STOP = 0; // Siempre va a estar en cero porque no vamos a considerar interrupciones del cpu
empty = 1; // Asumir que el fifo esta vacio
full = 0; // Asumir que el fifo esta lleno
data_address = 0; // Posicion donde empieza el dato (Address Field del Address Descriptor)
length = 10; // Tamano del dato en bytes
descriptor_index = 0; // Leer la primera posicion del descritor table
act1 = 0; // Attribute[4]
act2 = 1; // Attribute[3] Asumir que se debe dar una transferencia
END = 1; // Attribute [2] Asumir que solo se va a procesar una hilera del descriptor table
valid = 1; // Attribute[1] Asumir que la hilera del descriptor table es valida
dir = 1; // Transmitir de memoria a SD
//Reset off
#50
reset = 0;
// Pasar a ST_FDS
#50
cmd_reg_write = 1;
$display("Fin del DMA test");
$finish(2);
end
endmodule
|
#include <bits/stdc++.h> template <typename Iter> long long maxsum(Iter begin, Iter end) { long long mins = 0, s = 0; long long maxs = 0; long long max = *begin; while (begin != end) { s += *begin; max = std::max(max, *begin); maxs = std::max(maxs, s - mins); mins = std::min(mins, s); ++begin; } return (maxs == 0 ? max : maxs); } int main() { int t; std::cin >> t; for (int ti = 0; ti < t; ++ti) { int n; std::cin >> n; std::vector<long long> a(n); for (auto &e : a) std::cin >> e; long long maxs = std::max(maxsum(a.begin(), a.end() - 1), maxsum(a.begin() + 1, a.end())); std::cout << (std::accumulate(a.begin(), a.end(), 0ll) > maxs ? YES : NO ) << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_SYMBOL_V
`define SKY130_FD_SC_HDLL__BUFBUF_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string str; while (cin >> str) { int len = str.size(); int times = 0; int c = 0, p = 0; char tmp; for (int i = int(0); i <= int(len - 1); i++) { c = 0, p = 0; tmp = str[i]; if (tmp == C ) { while (str[i] == tmp && i < len) { c++; if (c > 5) { break; } i++; } i--; times++; } if (tmp == P ) { while (str[i] == tmp && i < len) { p++; if (p > 5) { break; } i++; } i--; times++; } } cout << times << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void rd(T &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) x = x * 10 - 0 + c, c = getchar(); x *= f; } template <class T> inline void cmax(T &x, T y) { if (x < y) x = y; } const int N = (1 << 18) + 10; int f[N][2][2]; int vis[N]; void solve(int l, int r, int c) { if (l + 1 == r) { int x = vis[l], y = vis[r]; cmax(f[c][x][y], x | y); cmax(f[c][y][x], x | y); return; } int mid = l + r >> 1; solve(l, mid, c << 1), solve(mid + 1, r, c << 1 | 1); for (int lx = 0; lx < 2; ++lx) for (int ly = 0; ly < 2; ++ly) if (f[c << 1][lx][ly] >= 0) for (int rx = 0; rx < 2; ++rx) for (int ry = 0; ry < 2; ++ry) if (f[c << 1 | 1][rx][ry] >= 0) { for (int S = 0; S < 8; ++S) { int a = (S & 1 ? lx : rx); int b = (S & 2 ? ly : ry); int d = (S & 4 ? (lx ^ rx ^ a) : b); cmax(f[c][a][d], f[c << 1][lx][ly] + f[c << 1 | 1][rx][ry] + (lx | rx) + (ly | ry) + ((lx ^ rx ^ a) | b)); } } } int main() { int n, k; rd(n), rd(k); for (int i = 1, x; i <= k; ++i) rd(x), vis[x - 1] = 1; memset(f, -0x3f, sizeof(f)); solve(0, (1 << n) - 1, 1); int ans = -0x3f3f3f3f; for (int x = 0; x < 2; ++x) for (int y = 0; y < 2; ++y) cmax(ans, f[1][x][y] + (x | y)); printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char a[150], b[150]; int c, d, e, f, g, x, y, z; gets(a); gets(b); c = strlen(a); for (x = 0; x < c; x++) { if (a[x] >= A && a[x] <= Z ) a[x] = a[x] + ( a - A ); if (b[x] >= A && b[x] <= Z ) b[x] = b[x] + ( a - A ); } if (strcmp(a, b) == 0) cout << 0 << endl; else if (strcmp(a, b) > 0) cout << 1 << endl; else cout << -1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_TB_V
`define SKY130_FD_SC_LS__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_TB_V
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const int mod = inf + 7; const double eps = 1e-9; int a[100][100]; int n, x, y; bool u[400], u1[400]; vector<int> v; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i <= n * n; i++) { cin >> x >> y; if (!u[x] && !u1[y]) { u[x] = 1; u1[y] = 1; v.push_back(i); } } for (int i = 0; i < v.size(); i++) { cout << v[i] << ; } return 0; }
|
#include <bits/stdc++.h> const double EPS = 1e-9; const int INT_INF = 1 << 31 - 1; const long long I64_INF = 1ll << 63 - 1ll; const double PI = acos(-1.0); using namespace std; long long solve(int len) { if (len == 1 || len == 2) return 9LL; long long pow = 1LL; for (int i = 0; i < len - 2; i++) pow *= 10LL; return 9LL * pow; } long long go(long long r) { if (r <= 0) return 0; int len = 0; long long R = r; long long c[20]; while (R) c[len] = R % 10LL, len++, R /= 10LL; long long res = 0; for (int i = 1; i < len; i++) res += solve(i); for (int i = 0; i < (int)len / 2; i++) swap(c[i], c[len - i - 1]); long long pow = 1LL; for (int i = 0; i < len - 2; i++) pow *= 10LL; res += (c[0] - 1LL) * pow; long long mid = 0; for (int i = 1; i <= len - 2; i++) mid = mid * 10LL + 1LL * c[i]; if (c[0] <= c[len - 1]) res += mid + 1LL; else res += mid; return res; }; bool ok(int a) { int last = a % 10; int first; while (a) first = a % 10, a /= 10; return first == last; } long long l, r; int main() { cin >> l >> r; cout << go(r) - go(l - 1) << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire D nand0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n; vector<pair<int, int> > a; set<pair<int, int> > d; void solve(int l, int r) { if (r - l <= 1) return; int m = (l + r) / 2; solve(l, m); solve(m, r); for (int i = l; i < r; ++i) { d.insert({a[m].first, a[i].second}); } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; a.resize(n); for (int i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; d.insert(a[i]); } sort(a.begin(), a.end()); solve(0, n); cout << d.size() << n ; for (auto i : d) { cout << i.first << << i.second << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int ans = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) { int inp; cin >> inp; if (i == j || i + j == n - 1 || i == n / 2 || j == n / 2) ans += inp; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; vector<long long> g[100005]; long long vis[MAXN], s[MAXN], gc[MAXN]; long long n; void dfs(long long v) { vis[v] = 1; s[v] = 1; for (auto i : g[v]) { if (!vis[i]) { dfs(i); s[v] += s[i]; gc[v] = max(gc[v], s[i]); } } gc[v] = max(gc[v], n - s[v]); } int pa[MAXN], sz[MAXN]; long long find_pa(long long pos) { if (pa[pos] != pos) pa[pos] = find_pa(pa[pos]); return pa[pos]; } void join(int a, int b) { int x = find_pa(a), y = find_pa(b); if (x != y) { if (sz[x] >= sz[y]) sz[x] += sz[y], pa[y] = x; else sz[y] += sz[x], pa[x] = y; } } void dsu_init(long long n) { for (long long i = 0, ggdem = n; i < ggdem; ++i) pa[i] = i, sz[i] = 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { cin >> n; for (long long i = 0, ggdem = n - 1; i < ggdem; ++i) { long long u, v; cin >> u >> v; u--; v--; g[u].push_back(v); g[v].push_back(u); } dfs(0); long long mini = n; for (long long i = 0, ggdem = n; i < ggdem; ++i) { mini = min(mini, gc[i]); } vector<long long> v; for (long long i = 0, ggdem = n; i < ggdem; ++i) { if (gc[i] == mini) v.push_back(i); } assert(((int)v.size()) <= 2); sort(v.begin(), v.end()); if (((int)v.size()) == 1) { for (long long k = 0, ggdem = 2; k < ggdem; ++k) cout << 1 << << g[0][0] + 1 << n ; } else { assert(mini == n / 2 && n % 2 == 0); dsu_init(n); for (long long i = 0, ggdem = n; i < ggdem; ++i) { for (auto j : g[i]) { if (min(i, j) != v[0] || max(i, j) != v[1]) { join(i, j); } } } long long br = 0; for (long long i = 0, ggdem = n; i < ggdem; ++i) { if (((int)g[i].size()) == 1 && i != v[0] && find_pa(i) != find_pa(v[1])) { cout << i + 1 << << g[i][0] + 1 << n ; cout << i + 1 << << v[1] + 1 << n ; br++; break; } } assert(br); } for (long long i = 0, ggdem = n; i < ggdem; ++i) g[i].clear(); for (long long i = 0, ggdem = n; i < ggdem; ++i) vis[i] = 0, s[i] = 0, gc[i] = 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int getInt(); int getNegInt(); int T, N; int get_nearest(int p, int a, vector<vector<int> >& path, unordered_set<int>& me) { if (me.find(a) != me.end()) return a; for (auto b : path[a]) { if (b == p) continue; int tar = get_nearest(a, b, path, me); if (tar != -1) return tar; } return -1; } int main(int argc, char** argv) { int a, b, k1, k2; T = getInt(); while (T--) { unordered_set<int> me, he; N = getInt(); vector<vector<int> > path(N + 1, vector<int>()); for (int i = 1; i < N; i++) { scanf( %d%d , &a, &b); path[a].push_back(b); path[b].push_back(a); } k1 = getInt(); int start; for (int i = 1; i <= k1; i++) { a = getInt(); me.insert(a); } k2 = getInt(); for (int i = 1; i <= k2; i++) { b = getInt(); start = b; he.insert(b); } int ans = -1; for (int i = 1; i <= 1; i++) { cout << B << start << endl; fflush(stdout); int index = getInt(); if (me.find(index) != me.end()) { ans = index; break; } int nearest = get_nearest(index, index, path, me); cout << A << nearest << endl; fflush(stdout); index = getInt(); if (he.find(index) != he.end()) { ans = nearest; break; } } cout << C << ans << endl; fflush(stdout); } return 0; } int getInt() { int ret = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) ret *= 10, ret += c - 0 , c = getchar(); return ret; } int getNegInt() { int ret = 0, sign = 1; char c = getchar(); while ((c < 0 && c != - ) || c > 9 ) c = getchar(); if (c == - ) sign = -1, c = getchar(); while (c >= 0 && c <= 9 ) ret *= 10, ret += c - 0 , c = getchar(); return ret * sign; }
|
// DGS 3/2/2018
//
// Synchronous 1 read-port and 1 write port ram.
//
`define bsg_mem_1r1w_sync_macro(bits,words) \
if (els_p == words && width_p == bits) \
begin: macro \
saed90_``bits``x``words``_2P mem \
(.CE1 (clk_lo) \
,.OEB1 (1'b0) \
,.CSB1 (1'b0) \
,.A1 (r_addr_i) \
,.O1 (r_data_o) \
,.CE2 (clk_i) \
,.WEB2 (~w_v_i) \
,.CSB2 (1'b0) \
,.A2 (w_addr_i) \
,.I2 (w_data_i) \
); \
end
module bsg_mem_1r1w_sync #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(els_p)
,parameter addr_width_lp=$clog2(els_p)
,parameter read_write_same_addr_p=0
// whether to substitute a 1r1w
,parameter substitute_1r1w_p=1
,parameter harden_p = 1
,parameter enable_clock_gating_p=1'b0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
wire clk_lo;
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r_v_i )
,.bypass_i( ~enable_clock_gating_p )
,.gated_clock_o( clk_lo )
);
// TODO: ADD ANY NEW RAM CONFIGURATIONS HERE
`bsg_mem_1r1w_sync_macro (64, 512) else
begin: z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1rw synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w_sync #(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(1)
) mem
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r_v_i
,.r_addr_i
,.r_data_o
);
// register output data to convert sync to async
//always_ff @(posedge clk_i)
//data_o <= data_lo;
end // block: s1r1w
else
begin: notmacro
// Instantiate a synthesizable 1rw sync ram
bsg_mem_1r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p)) synth
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r_v_i
,.r_addr_i
,.r_data_o
);
end // block: notmacro
end // block: z
// synopsys translate_off
//initial
//begin
//$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p/**,substitute_1r1w_p**/);
//end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync)
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_g8j_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_g8j_rom.dat", ram0);
$readmemh("./Loop_loop_height_g8j_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_g8j(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_g8j_rom Loop_loop_height_g8j_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846264338327950288419716939937510582097494459230; void swaps(char *x, char *y) { char temp; temp = *x; *x = *y; *y = temp; } void swapi(int *a, int *b) { int temp; temp = *a; *a = *b; *b = temp; } unsigned long long gcd(unsigned long long a, unsigned long long b) { if (a == 0) return b; if (b == 0) return a; if (a == 1 || b == 1) return 1; if (a == b) return a; if (a > b) return gcd(b, a % b); else return gcd(a, b % a); } long long Tree[4000010]; int V[4000010]; int N; int Time; int Outtime[4000010]; int Intime[4000010]; int Lvl[4000010]; int maxval; bool vis[4000010]; std::vector<std::vector<int> > Edge(2000010); void Add(int idx, int val) { for (int i = idx; i <= maxval; i += (i & -i)) Tree[i] += val; } long long Query(int idx) { long long S = 0; for (int i = idx; i > 0; i -= (i & -i)) S += Tree[i]; return S; } void dfs(int idx) { vis[idx] = true; Intime[idx] = ++Time; vis[idx] = true; for (int i = 0; i < Edge[idx].size(); i++) { if (vis[Edge[idx][i]]) continue; Lvl[Edge[idx][i]] = Lvl[idx] + 1; dfs(Edge[idx][i]); } Outtime[idx] = ++Time; } int main() { int Cases = 1; for (int Case = 0; Case < Cases; Case++) { int u, v, opt, node, Q; cin >> N >> Q; for (int i = 1; i <= N; i++) cin >> V[i]; for (int i = 0; i < N - 1; i++) { cin >> u >> v; Edge[u].push_back(v); Edge[v].push_back(u); } dfs(1); maxval = Outtime[1]; for (int i = 0; i < Q; i++) { cin >> opt; opt -= 1; if (opt == 0) { cin >> node >> v; if (Lvl[node] % 2) { Add(Intime[node], -v); Add(Outtime[node], v); } else { Add(Intime[node], v); Add(Outtime[node], -v); } } else { cin >> node; if (Lvl[node] % 2) cout << V[node] - Query(Intime[node]) << endl; else cout << V[node] + Query(Intime[node]) << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 10000; int n; set<pair<int, int> > a; set<pair<int, int> >::iterator it; pair<int, int> b[MAX]; void dive(int s, int e) { if (e - s == 1) return; int mid = s + e; mid /= 2; dive(s, mid); dive(mid, e); for (int i = s; i < e; i++) a.insert(make_pair(b[mid].first, b[i].second)); } int main() { cin >> n; int x, y; for (int i = 0; i < n; i++) { cin >> b[i].first >> b[i].second; a.insert(b[i]); } sort(b, b + n); dive(0, n); cout << a.size() << endl; for (it = a.begin(); it != a.end(); it++) cout << it->first << << it->second << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__TAP_BEHAVIORAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_BEHAVIORAL_PP_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: digilentinc.com:ip:pmod_bridge:1.0
// IP Revision: 7
(* X_CORE_INFO = "pmod_concat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "PmodNAV_pmod_bridge_0_0,pmod_concat,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PmodNAV_pmod_bridge_0_0 (
in_bottom_bus_I,
in_bottom_bus_O,
in_bottom_bus_T,
in0_I,
in1_I,
in2_I,
in3_I,
in0_O,
in1_O,
in2_O,
in3_O,
in0_T,
in1_T,
in2_T,
in3_T,
out0_I,
out1_I,
out2_I,
out3_I,
out4_I,
out5_I,
out6_I,
out7_I,
out0_O,
out1_O,
out2_O,
out3_O,
out4_O,
out5_O,
out6_O,
out7_O,
out0_T,
out1_T,
out2_T,
out3_T,
out4_T,
out5_T,
out6_T,
out7_T
);
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_Bottom_Row TRI_I" *)
output wire [3 : 0] in_bottom_bus_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_Bottom_Row TRI_O" *)
input wire [3 : 0] in_bottom_bus_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_Bottom_Row TRI_T" *)
input wire [3 : 0] in_bottom_bus_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_I" *)
output wire in0_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_I" *)
output wire in1_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_I" *)
output wire in2_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_I" *)
output wire in3_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_O" *)
input wire in0_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_O" *)
input wire in1_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_O" *)
input wire in2_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_O" *)
input wire in3_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_T" *)
input wire in0_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_T" *)
input wire in1_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_T" *)
input wire in2_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_T" *)
input wire in3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_I" *)
input wire out0_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_I" *)
input wire out1_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_I" *)
input wire out2_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_I" *)
input wire out3_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_I" *)
input wire out4_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_I" *)
input wire out5_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_I" *)
input wire out6_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_I" *)
input wire out7_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_O" *)
output wire out0_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_O" *)
output wire out1_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_O" *)
output wire out2_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_O" *)
output wire out3_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_O" *)
output wire out4_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_O" *)
output wire out5_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_O" *)
output wire out6_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_O" *)
output wire out7_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_T" *)
output wire out0_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_T" *)
output wire out1_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_T" *)
output wire out2_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_T" *)
output wire out3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_T" *)
output wire out4_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_T" *)
output wire out5_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_T" *)
output wire out6_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_T" *)
output wire out7_T;
pmod_concat #(
.Top_Row_Interface("SPI"),
.Bottom_Row_Interface("GPIO")
) inst (
.in_top_bus_I(),
.in_top_bus_O(4'B0),
.in_top_bus_T(4'B0),
.in_top_uart_gpio_bus_I(),
.in_top_uart_gpio_bus_O(2'B1),
.in_top_uart_gpio_bus_T(2'B1),
.in_top_i2c_gpio_bus_I(),
.in_top_i2c_gpio_bus_O(2'B1),
.in_top_i2c_gpio_bus_T(2'B1),
.in_bottom_bus_I(in_bottom_bus_I),
.in_bottom_bus_O(in_bottom_bus_O),
.in_bottom_bus_T(in_bottom_bus_T),
.in_bottom_uart_gpio_bus_I(),
.in_bottom_uart_gpio_bus_O(2'B1),
.in_bottom_uart_gpio_bus_T(2'B1),
.in_bottom_i2c_gpio_bus_I(),
.in_bottom_i2c_gpio_bus_O(2'B1),
.in_bottom_i2c_gpio_bus_T(2'B1),
.in0_I(in0_I),
.in1_I(in1_I),
.in2_I(in2_I),
.in3_I(in3_I),
.in4_I(),
.in5_I(),
.in6_I(),
.in7_I(),
.in0_O(in0_O),
.in1_O(in1_O),
.in2_O(in2_O),
.in3_O(in3_O),
.in4_O(1'B1),
.in5_O(1'B1),
.in6_O(1'B1),
.in7_O(1'B1),
.in0_T(in0_T),
.in1_T(in1_T),
.in2_T(in2_T),
.in3_T(in3_T),
.in4_T(1'B1),
.in5_T(1'B1),
.in6_T(1'B1),
.in7_T(1'B1),
.out0_I(out0_I),
.out1_I(out1_I),
.out2_I(out2_I),
.out3_I(out3_I),
.out4_I(out4_I),
.out5_I(out5_I),
.out6_I(out6_I),
.out7_I(out7_I),
.out0_O(out0_O),
.out1_O(out1_O),
.out2_O(out2_O),
.out3_O(out3_O),
.out4_O(out4_O),
.out5_O(out5_O),
.out6_O(out6_O),
.out7_O(out7_O),
.out0_T(out0_T),
.out1_T(out1_T),
.out2_T(out2_T),
.out3_T(out3_T),
.out4_T(out4_T),
.out5_T(out5_T),
.out6_T(out6_T),
.out7_T(out7_T)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, v; map<int, int> mp; vector<int> a; bool can(int mid) { int rem = 0; for (int i = 0; i < a.size(); i++) { if (mp[a[i]] >= mid) { rem += mp[a[i]] / mid; } } return rem >= k; } bool cmp(int s, int f) { return mp[s] > mp[f]; } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) { cin >> v; mp[v]++; } for (auto i : mp) { a.push_back(i.first); } sort(a.begin(), a.end(), cmp); int l, r, ans = 1; l = 1, r = n; while (l < r) { int mid = (l + r) / 2; if (can(mid)) { l = mid + 1; ans = mid; } else { r = mid; } } n = a.size(); for (int i = 0; i < n; i++) { if (k - mp[a[i]] / ans >= 0) { for (int j = 0; j < mp[a[i]] / ans; j++) cout << a[i] << ; k -= mp[a[i]] / ans; } else { for (int j = 0; j < k; j++) cout << a[i] << ; break; } } }
|
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