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#include <bits/stdc++.h> using namespace std; const int MX = 200100; int N, M; char S[MX]; int A[MX]; struct Segment { int a, b, c, d, e; int z, l, r; void add(int x) { a += x, b += x, c -= x, d -= x, z += x; } } T[MX << 2]; inline void PushUp(int i) { Segment &t = T[i], &x = T[(i << 1)], &y = T[(i << 1 | 1)]; t.a = max(x.a, y.a); t.b = min(x.b, y.b); t.c = max(max(x.c, y.c), x.a - 2 * y.b); t.d = max(max(x.d, y.d), y.a - 2 * x.b); t.e = max(max(x.e, y.e), max(x.c + y.a, x.a + y.d)); } inline void PushDown(int i) { if (T[i].z) T[(i << 1)].add(T[i].z), T[(i << 1 | 1)].add(T[i].z), T[i].z = 0; } void Build(int i, int l, int r) { T[i].l = l, T[i].r = r; if (l == r) { T[i].a = T[i].b = A[l], T[i].c = T[i].d = -A[l]; return; } int m = (l + r) >> 1; Build((i << 1), l, m), Build((i << 1 | 1), m + 1, r); PushUp(i); } void Add(int i, int a, int b, int x) { if (a <= T[i].l && T[i].r <= b) { T[i].add(x); return; } PushDown(i); if (a <= T[(i << 1)].r) Add((i << 1), a, b, x); if (b >= T[(i << 1 | 1)].l) Add((i << 1 | 1), a, b, x); PushUp(i); } int main() { int n; scanf( %d%d%s , &n, &M, S + 1), N = strlen(S + 1); for (int i = (1); i <= (N); ++i) A[i] = A[i - 1] + (S[i] == ( ? 1 : -1); Build(1, 0, N); printf( %d n , T[1].e); for (int i = (1); i <= (M); ++i) { int l, r; scanf( %d%d , &l, &r); if (l > r) swap(l, r); if (S[l] != S[r]) Add(1, l, r - 1, S[l] == ( ? -2 : 2), swap(S[l], S[r]); printf( %d n , T[1].e); } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_vref_logic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_vref_logic(a ,vrefcode ,c ,b ,vdd18 );
output [7:0] vrefcode ;
input a ;
input c ;
input b ;
input vdd18 ;
wire net202 ;
wire net185 ;
wire net190 ;
wire net193 ;
wire net0106 ;
wire net196 ;
wire net0107 ;
wire net198 ;
wire net0109 ;
wire net0120 ;
wire net181 ;
bw_u1_nand3_1x I1 (
.z (net202 ),
.a (a ),
.b (b ),
.c (c ) );
bw_u1_nand2_1x I2 (
.z (net196 ),
.a (a ),
.b (b ) );
bw_u1_nand2_1x I3 (
.z (net193 ),
.a (net0107 ),
.b (a ) );
bw_u1_nor2_2x I4 (
.z (net190 ),
.a (c ),
.b (b ) );
bw_u1_nand2_1x I9 (
.z (net198 ),
.a (b ),
.b (c ) );
bw_u1_nor2_1x I12 (
.z (net185 ),
.a (b ),
.b (a ) );
bw_u1_nor3_1x I13 (
.z (net181 ),
.a (c ),
.b (b ),
.c (a ) );
bw_u1_inv_1x I47 (
.z (net0106 ),
.a (a ) );
bw_u1_inv_1x I52 (
.z (net0109 ),
.a (net0120 ) );
bw_u1_nand2_1x I53 (
.z (net0120 ),
.a (net0106 ),
.b (net198 ) );
bw_u1_inv_1x I54 (
.z (net0107 ),
.a (net190 ) );
bw_io_ddr_vref_logic_high x0 (
.in ({net202 ,net196 ,net193 ,net0106 ,net0109 ,net185
,net181 } ),
.vrefcode ({vrefcode } ),
.vdd18 (vdd18 ) );
endmodule
|
#include <bits/stdc++.h> int main() { int i, j, k, l; long long n, m, sum; while (scanf( %lld%lld , &n, &m) != EOF) { sum = 0; for (int i = 1; i <= n; i++) { if (m % i == 0 && m / i <= n) { ++sum; } } printf( %d n , sum); } return 0; }
|
#include <bits/stdc++.h> const int a[250] = {0, 1, 1, 1, 2, 1, 2, 1, 5, 2, 2, 1, 5, 1, 2, 1, 14, 1, 5, 1, 5, 2, 2, 1, 15, 2, 2, 5, 4, 1, 4, 1, 51, 1, 2, 1, 14, 1, 2, 2, 14, 1, 6, 1, 4, 2, 2, 1, 52, 2, 5, 1, 5, 1, 15, 2, 13, 2, 2, 1, 13, 1, 2, 4, 267, 1, 4, 1, 5, 1, 4, 1, 50, 1, 2, 3, 4, 1, 6, 1, 52, 15, 2, 1, 15, 1, 2, 1, 12, 1, 10, 1, 4, 2}; int main() { int n; scanf( %d , &n); printf( %d , a[n]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int len, pos; void insert(int x) { len++; if (x <= pos) pos++; } void erase(int x) { if (x >= pos) len = x; else len -= x, pos -= x; } int main() { int m, t; scanf( %d%d%d%d , &len, &pos, &m, &t); while (t--) { int type, x; scanf( %d%d , &type, &x); if (type == 1) insert(x); else erase(x); printf( %d %d n , len, pos); } }
|
#include <bits/stdc++.h> using namespace std; int n, ans; int f[1000]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { if (i + j - 1 <= n) { for (int k = j; k <= i + j - 1; k++) f[k]++; } } for (int i = 1; i <= n; i++) ans = max(ans, f[i]); printf( %d , ans); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// this is a sine function (approximate), the basic idea is to approximate sine as a
// polynomial function (there are a lot of stuff about this on the web)
`timescale 1ns/100ps
module ad_dds_sine #(
parameter DELAY_DATA_WIDTH = 16) (
// sine = sin(angle)
input clk,
input [15:0] angle,
output [15:0] sine,
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [33:0] s1_data_p = 'd0;
reg [33:0] s1_data_n = 'd0;
reg [15:0] s1_angle = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s1_ddata = 'd0;
reg [18:0] s2_data_0 = 'd0;
reg [18:0] s2_data_1 = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s2_ddata = 'd0;
reg [18:0] s3_data = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s3_ddata = 'd0;
reg [33:0] s4_data2_p = 'd0;
reg [33:0] s4_data2_n = 'd0;
reg [16:0] s4_data1_p = 'd0;
reg [16:0] s4_data1_n = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s4_ddata = 'd0;
reg [16:0] s5_data2_0 = 'd0;
reg [16:0] s5_data2_1 = 'd0;
reg [16:0] s5_data1 = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s5_ddata = 'd0;
reg [16:0] s6_data2 = 'd0;
reg [16:0] s6_data1 = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s6_ddata = 'd0;
reg [33:0] s7_data = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] s7_ddata = 'd0;
reg [15:0] sine_int = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] ddata_out_int = 'd0;
// internal signals
wire [15:0] angle_s;
wire [33:0] s1_data_s;
wire [(DELAY_DATA_WIDTH-1):0] s1_ddata_s;
wire [15:0] s1_angle_s;
wire [33:0] s4_data2_s;
wire [(DELAY_DATA_WIDTH-1):0] s4_ddata_s;
wire [16:0] s4_data1_s;
wire [33:0] s7_data2_s;
wire [33:0] s7_data1_s;
wire [(DELAY_DATA_WIDTH-1):0] s7_ddata_s;
// make angle 2's complement
assign angle_s = {~angle[15], angle[14:0]};
// level 1 - intermediate
ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16)) i_mul_s1 (
.clk (clk),
.data_a ({angle_s[15], angle_s}),
.data_b ({angle_s[15], angle_s}),
.data_p (s1_data_s),
.ddata_in ({ddata_in, angle_s}),
.ddata_out ({s1_ddata_s, s1_angle_s}));
// 2's complement versions
always @(posedge clk) begin
s1_data_p <= s1_data_s;
s1_data_n <= ~s1_data_s + 1'b1;
s1_angle <= s1_angle_s;
s1_ddata <= s1_ddata_s;
end
// select partial products
always @(posedge clk) begin
s2_data_0 <= (s1_angle[15] == 1'b0) ? s1_data_n[31:13] : s1_data_p[31:13];
s2_data_1 <= {s1_angle[15], s1_angle[15:0], 2'b00};
s2_ddata <= s1_ddata;
end
// unit-sine
always @(posedge clk) begin
s3_data <= s2_data_0 + s2_data_1;
s3_ddata <= s2_ddata;
end
// level 2 - final
ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2 (
.clk (clk),
.data_a (s3_data[16:0]),
.data_b (s3_data[16:0]),
.data_p (s4_data2_s),
.ddata_in ({s3_ddata, s3_data[16:0]}),
.ddata_out ({s4_ddata_s, s4_data1_s}));
// 2's complement versions
always @(posedge clk) begin
s4_data2_p <= s4_data2_s;
s4_data2_n <= ~s4_data2_s + 1'b1;
s4_data1_p <= s4_data1_s;
s4_data1_n <= ~s4_data1_s + 1'b1;
s4_ddata <= s4_ddata_s;
end
// select partial products
always @(posedge clk) begin
s5_data2_0 <= (s4_data1_p[16] == 1'b1) ? s4_data2_n[31:15] : s4_data2_p[31:15];
s5_data2_1 <= s4_data1_n;
s5_data1 <= s4_data1_p;
s5_ddata <= s4_ddata;
end
// corrected-sine
always @(posedge clk) begin
s6_data2 <= s5_data2_0 + s5_data2_1;
s6_data1 <= s5_data1;
s6_ddata <= s5_ddata;
end
// full-scale
ad_mul #(.DELAY_DATA_WIDTH(1)) i_mul_s3_2 (
.clk (clk),
.data_a (s6_data2),
.data_b (17'h1d08),
.data_p (s7_data2_s),
.ddata_in (1'b0),
.ddata_out ());
ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_s3_1 (
.clk (clk),
.data_a (s6_data1),
.data_b (17'h7fff),
.data_p (s7_data1_s),
.ddata_in (s6_ddata),
.ddata_out (s7_ddata_s));
// corrected sum
always @(posedge clk) begin
s7_data <= s7_data2_s + s7_data1_s;
s7_ddata <= s7_ddata_s;
end
// output registers
assign sine = sine_int;
assign ddata_out = ddata_out_int;
always @(posedge clk) begin
sine_int <= s7_data[30:15];
ddata_out_int <= s7_ddata;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: terminator.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module terminator (/*AUTOARG*/
// Inputs
TERM
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
inout TERM; // From cluster_header0 of cluster_header.v
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_9_1,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_9_1,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=16,DIN_FROM=15,DIN_TO=15}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_9_1 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_SYMBOL_V
`define SKY130_FD_SC_HS__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_SYMBOL_V
|
//****************************************************************************/
//
// Copyright (C) yyyy Ronan Barzic -
// Date : Fri Apr 22 13:25:26 2016
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : two_phase_slave.v
//
// Description :
// A simple module that handles request and provides an acknowledge
// after some time
//
//
//
//
//****************************************************************************/
`timescale 1ns/1ps
module two_phase_slave (/*AUTOARG*/
// Outputs
ack,
// Inputs
req
);
input req;
output ack;
parameter spread=200;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
reg ack;
event evt_dbg_1;
event evt_dbg_2;
always @(posedge req) begin
if(ack == 1'b1) begin
$display("-E- Protocol violation (posedge req while ack == 1)");
$finish(1);
end
else begin
#($unsigned($random) % 200);
ack <= 1'b1;
end
end
always @(negedge req) begin
if(ack == 1'b0) begin
$display("-E- Protocol violation (negedge req while ack == 0)");
$finish(1);
end
else begin
#($unsigned($random) % 200);
ack <= 1'b0;
end
end
endmodule // two_phase_slave
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; long long int binarySearch(long long int* arr, long long int l, long long int r, long long int x) { if (r >= l) { long long int mid = l + (r - l) / 2; if (arr[mid] == x) return mid; if (arr[mid] > x) return binarySearch(arr, l, mid - 1, x); return binarySearch(arr, mid + 1, r, x); } return -1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t, n1, n2, n3, i, j, l, x; cin >> t; for (l = 0; l < t; l++) { string s = ; cin >> n1 >> n2 >> n3; if (n1 > 0) { for (i = 0; i <= n1; i++) s += 0 ; } if (n3 > 0 && n1 > 0) n2 -= 1; if (n3 > 0) { for (i = 0; i <= n3; i++) s += 1 ; } if (n2 > 0 && n3 > 0) { x = 0; for (i = 0; i < n2; i++) { s += (x + 0 ); x = (x + 1) % 2; } } else if (n2 > 0 && n1 > 0) { x = 1; for (i = 0; i < n2; i++) { s += (x + 0 ); x = (x + 1) % 2; } } else if (n2 > 0) { s += 1 ; x = 0; for (i = 0; i < n2; i++) { s += (x + 0 ); x = (x + 1) % 2; } } cout << s << n ; } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char str[999]; cin >> str; str[0] = toupper(str[0]); cout << str << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// The DLP makes one page read requests from host clock domain. This block has
// to synchronize the requests, pass them on to the arbiter, and mask the
// push enables that come back.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_dlp
#(parameter BYTES = 16)
(
input reset_n,
input mclock,
input hst_clock,
input dlp_req,
input [4:0] dlp_wcnt,
input [27:0] dlp_org,
input dlp_gnt,
input dlp_push,
output reg dlp_mc_done,
output reg dlp_arb_req,
output reg [4:0] dlp_arb_wcnt,
output reg [27:0] dlp_arb_addr,
output reg dlp_ready
);
reg [27:0] capt_org;
reg [4:0] capt_wcnt;
reg dlp_req_toggle;
reg req_sync_1, req_sync_2, req_sync_3;
reg dlp_gnt_toggle;
reg gnt_sync_1, gnt_sync_2, gnt_sync_3;
reg [1:0] request_count;
reg [4:0] dlp_count;
localparam DLP = 3'h1;
// Capture request and control the ready signal
always @ (posedge hst_clock or negedge reset_n) begin
if(!reset_n) begin
dlp_ready <= 1'b1;
dlp_req_toggle <= 1'b0;
gnt_sync_1 <= 1'b0;
gnt_sync_2 <= 1'b0;
gnt_sync_3 <= 1'b0;
end else begin
if(dlp_req==1'b1) begin
dlp_req_toggle <= ~dlp_req_toggle;
capt_org <= dlp_org;
capt_wcnt <= dlp_wcnt;
dlp_ready <= 1'b0;
end // if (dlp_req==1'b1)
// synchronize the gnt toggle from mclock domain
gnt_sync_1 <= dlp_gnt_toggle;
gnt_sync_2 <= gnt_sync_1;
gnt_sync_3 <= gnt_sync_2;
if(gnt_sync_2 ^ gnt_sync_3) dlp_ready <= 1'b1;
end // else: !if(!reset_n)
end // always @ (posedge hst_clock or negedge reset_n)
// Issue requests to the arbiter
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
dlp_arb_req <= 1'b0;
dlp_gnt_toggle <= 1'b0;
req_sync_1 <= 1'b0;
req_sync_2 <= 1'b0;
req_sync_3 <= 1'b0;
dlp_mc_done <= 1'b0;
dlp_arb_addr <= 28'b0;
dlp_arb_req <= 1'b0;
dlp_count <= 5'b0;
end else begin
req_sync_1 <= dlp_req_toggle;
req_sync_2 <= req_sync_1;
req_sync_3 <= req_sync_2;
if(req_sync_2 ^ req_sync_3) begin
dlp_arb_addr <= capt_org;
dlp_arb_req <= 1'b1;
dlp_arb_wcnt <= capt_wcnt;
end // if (req_sync_2==1'b1 && req_sync_3==1'b0)
if(dlp_gnt==1'b1) begin
dlp_arb_req <= 1'b0;
dlp_gnt_toggle <= ~dlp_gnt_toggle;
end // if (dlp_gnt==1'b1)
if (dlp_push && ~dlp_mc_done)
dlp_count <= dlp_count + 5'h1;
else if(dlp_mc_done)
dlp_count <= 5'h0;
if (dlp_push && ~dlp_mc_done) begin
if (BYTES == 4) dlp_mc_done <= &dlp_count; // FIXME.
else if (BYTES == 8) dlp_mc_done <= dlp_count[0]; // FIXME.
else dlp_mc_done <= (dlp_count == dlp_arb_wcnt);
end
else dlp_mc_done <= 1'b0;
end // else: !if(!reset_n)
end // always @ (posedge mclock or negedge reset_n)
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 7; int n; int v[N], f[N]; bool e[N]; int st, dr; bool ok(int l, int r) { for (int i = 1; i <= n; i++) { e[i] = 0; f[i] = 0; } for (int i = l; i <= r; i++) { e[i] = 1; f[v[i]]++; } for (int i = 1; i < n + 1 - i; i++) { if (e[i] == 1 && e[n + 1 - i] == 0) { if (f[v[n + 1 - i]] > 0) { f[v[n + 1 - i]]--; } else { return 0; } } if (e[i] == 0 && e[n + 1 - i] == 1) { if (f[v[i]] > 0) { f[v[i]]--; } else { return 0; } } if (e[i] == 0 && e[n + 1 - i] == 0 && v[i] != v[n + 1 - i]) { return 0; } } int cntimp = 0; for (int i = 1; i <= n; i++) { if (f[i] % 2 == 1) { cntimp++; } } return (cntimp <= 1); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> v[i]; f[v[i]]++; } int imp = 0; for (int i = 1; i <= n; i++) { if (f[i] % 2 == 1) { imp++; } } if (imp >= 2) { cout << 0 n ; return 0; } bool pali = 1; for (int i = 1; i < n + 1 - i; i++) { if (v[i] != v[n + 1 - i]) { pali = 0; } } if (pali) { long long res = n * (long long)(n + 1) >> 1; cout << res << n ; return 0; } st = 1; dr = n; while (v[st] == v[dr]) { st++; dr--; } int lo = st; int hi = dr; int prf = -1, suf = -1; while (lo <= hi) { int mid = (lo + hi) >> 1; if (ok(st, mid)) { prf = mid; hi = mid - 1; } else { lo = mid + 1; } } lo = 1; hi = n; while (lo <= hi) { int mid = (lo + hi) >> 1; if (ok(mid, dr)) { suf = mid; lo = mid + 1; } else { hi = mid - 1; } } int cntgood = 0; if (prf != -1) { cntgood += (dr - prf + 1); } if (suf != -1) { cntgood += (suf - st + 1); } long long res = cntgood * (long long)st - 1 + (st - 1LL) * (long long)(st - 1LL); cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INT_INF = 1e9; const long long LL_INF = 1e18; const int MAXN = 200003; int n, m; int A[MAXN]; long long calc(int m) { long long ret = 0; map<int, int> dp; int sum = 0; dp[sum] = 1; long long add = 0; for (int i = 1; i <= n; i++) { if (A[i] < m) { sum--; add -= dp[sum]; } else if (A[i] >= m) { add += dp[sum]; sum++; } ret += add; dp[sum]++; } return ret; } int main() { scanf( %d %d , &n, &m); for (int i = 1, x; i <= n; i++) { scanf( %d , &x); A[i] = x; } long long ret1 = calc(m); long long ret2 = calc(m + 1); printf( %lld , ret1 - ret2); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 100 * 30; int main() { string A, B; cin >> A >> B; vector<vector<int> > v(26, vector<int>(26, INF)); for (int i = 0; i < 26; ++i) v[i][i] = 0; int N; cin >> N; while (N--) { char a, b; int cost; cin >> a >> b >> cost; int ia = a - a , ib = b - a ; v[ia][ib] = min(v[ia][ib], cost); } for (int k = 0; k < 26; ++k) for (int i = 0; i < 26; ++i) for (int j = 0; j < 26; ++j) v[i][j] = min(v[i][j], v[i][k] + v[k][j]); if (A.size() != B.size()) { cout << -1 << endl; } else { unsigned ans = 0; bool fail = false; string res = ; for (int i = 0; i < A.size(); ++i) { if (A[i] == B[i]) { res += A[i]; continue; } int ia = A[i] - a , ib = B[i] - a ; char to_ch = 0; int cost = INF * 10; for (int j = 0; j < 26; ++j) { if (v[ia][j] < INF && v[ib][j] < INF) { if (v[ia][j] + v[ib][j] < cost) { cost = v[ia][j] + v[ib][j]; to_ch = j + a ; } } } if (to_ch == 0) { fail = true; break; } ans += cost; res += to_ch; } if (fail) cout << -1 << endl; else { cout << ans << endl; cout << res << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; vector<long long> p; vector<long long> pre; for (long long i = 0; i < n; i++) { p.push_back(i + 1); } long long sum = 0; for (long long i = 0; i < n; i++) { sum += p[i]; pre.push_back(sum); } long long ind = lower_bound(pre.begin(), pre.end(), k) - pre.begin(); long long x = p[ind]; long long y = n - x - 1; long long bb; bb = y + (pre[ind] - k) + 1; vector<char> ans; for (long long i = 0; i < n; i++) { if (i == y || i == bb) ans.push_back( b ); else ans.push_back( a ); } for (int i = 0; i < n; i++) { cout << ans[i]; } cout << endl; } return 0; }
|
//`define ICDEBUG 1
`ifdef FPGA
// `define DUMMY_CACHE
`endif
// Number of cache lines
`define IC_WIDTH_BITS 4
`define IC_LINES_BITS 6
`define IC_WIDTH_ZERO 4'b0000
`define IC_WIDTH_ONES 4'b1111
`define IC_WIDTH (1<<`IC_WIDTH_BITS)
`define IC_LINES (1<<`IC_LINES_BITS)
`ifdef DUMMY_CACHE
module toy_icache(input clk,
input reset,
input [31:0] ic_addr,
input ic_rq,
output reg ic_data_out_valid,
output reg [31:0] ic_data_out,
// memory bus interface
input [31:0] data_in, // bus data in
input data_in_ready, // bus data ready
output reg data_rd, // request data read
output reg [31:0] data_address // output data address
);
always @(posedge clk)
begin
data_address <= ic_addr;
data_rd <= ic_rq;
ic_data_out <= data_in;
ic_data_out_valid <= data_in_ready;
end
endmodule
`endif
`ifndef DUMMY_CACHE
module toy_icache(input clk,
input reset,
input [31:0] ic_addr,
input ic_rq,
output reg ic_data_out_valid,
output reg [31:0] ic_data_out,
// memory bus interface
input [31:0] data_in, // bus data in
input data_in_ready, // bus data ready
output reg data_rd, // request data read
output reg [31:0] data_address // output data address
);
// bits 2-0 are cache line address
// bits 31-3 are a tag
// bits 7-3 are a line address
// bits 7-0 are
reg [31-`IC_WIDTH_BITS+1:0] ictags[0:`IC_LINES-1];
reg [31:0] cacheram[0:`IC_LINES*`IC_WIDTH-1];
wire [31-`IC_WIDTH_BITS:0] addrtag;
assign addrtag = ic_addr[31:`IC_WIDTH_BITS];
reg [31-`IC_WIDTH_BITS+1:0] icnewtag;
parameter S_IDLE = 0;
parameter S_FILL = 1;
parameter S_FILL_STEP = 2;
reg [1:0] ic_state;
reg [31:0] ictagsout;
reg [1:0] ic_rq_shift;
always @(posedge clk)
if (!reset) begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
icnewtag <= 0;
data_rd <= 0;
ic_state <= S_IDLE;
ictagsout <= 0;
ic_rq_shift <= 0;
end else begin
ic_rq_shift <= {ic_rq_shift[0],ic_rq};
ictagsout <= ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]];
case (ic_state)
S_IDLE:
if (ic_rq_shift[1]) begin
if(ictagsout == {1'b1,addrtag}) // hit
begin
`ifdef ICDEBUG
$display("ICACHE HIT: %X -> %X", ic_addr, cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]]);
`endif
ic_data_out <= cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]];
ic_data_out_valid <= 1;
end else begin // sorry, miss
`ifdef ICDEBUG
$display("ICACHE SHIT: %X [%X vs. %X] at %X", ic_addr, ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]], {1'b1,addrtag}, ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]);
`endif
ic_data_out_valid <= 0;
ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]] <= 0; // evict
ic_state <= S_FILL;
data_address <= {ic_addr[31:`IC_WIDTH_BITS],`IC_WIDTH_ZERO}; // start of the line
data_rd <= 1;
icnewtag <= {1'b1, addrtag};
end
end else begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
S_FILL: begin
if (data_in_ready) begin
`ifdef ICDEBUG
$display("ICACHE FILL %X <- %X", data_address, data_in);
`endif
if (ic_rq && data_address == ic_addr) begin // a possibly premature hit, report it
`ifdef ICDEBUG
$display("ICACHE FHIT: %X -> %X", ic_addr, data_in);
`endif
ic_data_out <= data_in;
ic_data_out_valid <= 1;
end else begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
cacheram[data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:0]] <= data_in;
data_rd <= 0;
if (data_address[`IC_WIDTH_BITS-1:0] == `IC_WIDTH_ONES) begin
`ifdef ICDEBUG
$display("ICACHE FILLING DONE %X at %X", icnewtag, data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]);
`endif
ictags[data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]] <= icnewtag; // reclaim a line
ic_state <= S_IDLE;
end else begin
ic_state <= S_FILL_STEP;
data_address <= data_address + 1;
end
end else begin // if (data_in_ready && ~stall)
if (ic_rq &&
data_address[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]
==
ic_addr[`IC_LINES_BITS+`IC_WIDTH_BITS-1:`IC_WIDTH_BITS]
&& !(data_address[31:`IC_WIDTH_BITS] == ic_addr[31:`IC_WIDTH_BITS])) begin
// have to evict before completion
ictags[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:`IC_WIDTH_BITS]] <= 0;
ic_state <= S_IDLE;
ic_data_out_valid <= 0;
end
if (ic_rq && data_address[31:`IC_WIDTH_BITS] == ic_addr[31:`IC_WIDTH_BITS]
&& ic_addr[`IC_WIDTH_BITS-1:0] < data_address[`IC_WIDTH_BITS-1:0]) begin
`ifdef ICDEBUG
$display("ICACHE FFHIT: %X -> %X [%X vs %X]", ic_addr, cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]],
ic_addr[`IC_WIDTH_BITS-1:0], data_address[`IC_WIDTH_BITS-1:0]);
`endif
ic_data_out <= cacheram[ic_addr[`IC_WIDTH_BITS+`IC_LINES_BITS-1:0]];
ic_data_out_valid <= 1;
end else begin
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
end
end // case: S_FILL
S_FILL_STEP: begin
data_rd <= 1;
ic_state <= S_FILL;
ic_data_out_valid <= 0;
ic_data_out <= 0;
end
endcase // case (ic_state)
end
endmodule
`endif // `ifndef DUMMY_CACHE
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY
*/
module eth_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
*/
output wire tx_bad_block,
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_sequence_error,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_bad_block(tx_bad_block),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while ( 0 <= c && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } int n, m, cnt, h[200005], X[200005], Y[200005], dep[200005], du[200005], Tot, col[200005], ans[200005]; struct Edge { int to, next; } a[200005 * 2]; inline void Add(int x, int y) { cnt++; a[cnt].to = y; a[cnt].next = h[x]; h[x] = cnt; } void dfs(int x, int fa, int ban) { dep[x] = dep[fa] + 1; int now = 1; if (ban == Tot) for (int i = h[x]; i; i = a[i].next) { int y = a[i].to; if (y != fa) { ans[y] = now; dfs(y, x, now); now = min(now + 1, Tot - 1); if (!now) now = 1; } } else for (int i = h[x]; i; i = a[i].next) { int y = a[i].to; if (y != fa) { if (now == ban) now++; ans[y] = now; dfs(y, x, now); now = min(now + 1, Tot); } } } bool check(int lim) { int sum = 0; for (int i = 1; i <= n; ++i) sum += (du[i] > lim); return sum <= m; } int main() { n = read(); m = read(); for (int i = 1; i < n; ++i) { int x = read(), y = read(); X[i] = x; Y[i] = y; Add(x, y); Add(y, x); du[x]++; du[y]++; } int l = 1, r = n, mid; while (l <= r) { mid = l + r >> 1; if (check(mid)) r = mid - 1, Tot = mid; else l = mid + 1; } dfs(1, 0, 0); cout << Tot << n ; for (int i = 1; i < n; ++i) { if (dep[X[i]] > dep[Y[i]]) cout << ans[X[i]] << ; else cout << ans[Y[i]] << ; } }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_decoder(
ck,
reset_n,
code,
pattern
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [3:0] code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] pattern;
reg [3:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 4'b0000;
end
else begin
code_R <= code;
end
end
genvar j;
generate
for(j = 0; j < DATA_WIDTH; j = j + 1)
begin : bit_pattern
if(j % 2 == 0) begin
assign pattern[j] = code_R[3];
assign pattern[j + DATA_WIDTH] = code_R[2];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end
end
else begin
assign pattern[j] = code_R[3] ^ code_R[0];
assign pattern[j + DATA_WIDTH] = code_R[2] ^ code_R[0];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3] ^ code_R[0];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2] ^ code_R[0];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end
end
end
endgenerate
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_SHARED_CODE
parameter NUM_CKS_1 = (num_cks-1);
parameter NUM_CKS_2 = (NUM_CKS_1 > 0) ? (NUM_CKS_1 - 1) : 0;
reg [NUM_CKS_1:0] seq_queue;
`ifdef OVL_SYNTHESIS
`else
initial begin
seq_queue = {num_cks{1'b0}};
end
`endif
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b1) begin
seq_queue <= {num_cks{1'b0}};
end
else begin
seq_queue[NUM_CKS_1] <= (necessary_condition == `OVL_TRIGGER_ON_FIRST_NOPIPE) ?
(~(|seq_queue[NUM_CKS_1:1])) && event_sequence[NUM_CKS_1] : event_sequence[NUM_CKS_1];
seq_queue[NUM_CKS_2:0] <= (seq_queue >> 1) & event_sequence[NUM_CKS_2:0];
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_cycle_sequence_assert #(
.num_cks(num_cks),
.necessary_condition(necessary_condition))
assert_cycle_sequence_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.event_sequence(event_sequence),
.seq_queue(seq_queue),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_cycle_sequence_assume #(
.num_cks(num_cks),
.necessary_condition(necessary_condition))
assert_cycle_sequence_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.event_sequence(event_sequence),
.seq_queue(seq_queue),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_cycle_sequence_cover #(
.num_cks(num_cks),
.necessary_condition(necessary_condition),
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_cycle_sequence_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.event_sequence(event_sequence),
.seq_queue(seq_queue));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_cycle_sequence.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_cycle_sequence_assert (clk, reset_n, event_sequence, seq_queue, xzcheck_enable);
parameter num_cks = 2;
parameter necessary_condition = 0;
input clk, reset_n;
input [num_cks-1:0] event_sequence, seq_queue;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_cycle_sequence_assume (clk, reset_n, event_sequence, seq_queue, xzcheck_enable);
parameter num_cks = 2;
parameter necessary_condition = 0;
input clk, reset_n;
input [num_cks-1:0] event_sequence, seq_queue;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_cycle_sequence_cover (clk, reset_n, event_sequence, seq_queue);
parameter num_cks = 4;
parameter necessary_condition = 0;
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n;
input [num_cks-1:0] event_sequence, seq_queue;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long n; while (cin >> n) { long flag = 0, count = 0, a[100005] = {0}, i; for (i = 0; i < n; i++) cin >> a[i]; for (i = n - 1; i > 0; i--) { if (a[i - 1] > a[i]) break; else count++; } cout << n - count - 1 << endl; } return 0; }
|
`timescale 1ns / 1ns
module meganode_tb();
wire clk_20;
sim_clk #(20) sim_clk_20_inst(.clk(clk_20));
wire clk_25;
sim_clk #(25) sim_clk_25_inst(.clk(clk_25));
wire clk_50;
sim_clk #(50) sim_clk_50_inst(.clk(clk_50));
wire clk_48;
sim_clk #(48) sim_clk_48_inst(.clk(clk_48));
wire clk_100;
sim_clk #(100) sim_clk_100_inst(.clk(clk_100));
wire enet_rst, enet_mdc, enet_mdio;
wire [3:0] enet_leds;
wire [1:0] enet_txclk, enet_txen, enet_rxclk, enet_rxdv;
wire [3:0] enet_txd, enet_rxd;
wire [4:0] usb_oe, usb_rcv, usb_pwr, usb_vp, usb_vm;
wire [15:0] outb;
wire [2:0] mosfet_hi, mosfet_lo, mclk;
reg [2:0] mdata;
wire mosfet_en;
wire mcu_io;
wire mcu_spim_cs, mcu_spim_sclk, mcu_spim_mosi, mcu_spim_miso;
wire mcu_spis_cs, mcu_spis_sclk, mcu_spis_mosi, mcu_spis_miso;
wire led;
localparam W = 8;
reg [W-1:0] master_txd;
wire [W-1:0] master_rxd;
reg master_txdv;
wire master_rxdv;
wire master_done, master_busy;
spi_master #(.SCLK_DIV(50), .W(8)) spi_master_inst
(.c(clk_100), .busy(master_busy), .done(master_done),
.txd(master_txd), .txdv(master_txdv),
.rxd(master_rxd), .rxdv(master_rxdv),
.cs(mcu_spis_cs), .sclk(mcu_spis_sclk),
.mosi(mcu_spis_mosi), .miso(mcu_spis_miso));
initial begin
master_txd = 8'ha5;
master_txdv = 0;
#100
@(posedge clk_100);
#1 master_txdv = 1;
@(posedge clk_100);
#1 master_txd = 8'h7;
@(posedge clk_100);
#1 master_txd = 8'h51;
@(posedge clk_100);
#1 master_txdv = 0;
#50000
@(posedge clk_100);
#1 master_txdv = 1;
@(posedge clk_100);
#1 master_txd = 8'h8;
@(posedge clk_100);
#1 master_txd = 8'h52;
@(posedge clk_100);
#1 master_txdv = 0;
end
meganode meganode_inst(.*);
initial begin
$dumpfile("meganode.lxt");
$dumpvars();
#1_000_000 $finish();
//#150000 $finish();
end
fake_rmii_phy #(.INPUT_FILE_NAME("tb_packets.dat")) sim_rmii_phy_0
(.refclk(clk_50), .mdc(enet_mdc), .mdio(enet_mdio),
.txd(enet_txd[1:0]), .txen(enet_txen[0]),
.rxd(enet_rxd[1:0]), .rxdv(enet_rxdv[0]),
.rst(1'b1));
fake_rmii_phy #(.INPUT_FILE_NAME("tb_packets.dat")) sim_rmii_phy_1
(.refclk(clk_50), .mdc(enet_mdc), .mdio(enet_mdio),
.txd(enet_txd[3:2]), .txen(enet_txen[1]),
.rxd(enet_rxd[3:2]), .rxdv(enet_rxdv[1]),
.rst(1'b1));
wire [4:0] usb_dp, usb_dm;
sim_fsusb_phy sim_usb_phy[4:0]
(.vp(usb_vp), .vm(usb_vm), .oe_n(usb_oe), .pwr(usb_pwr),
.dp(usb_dp), .dm(usb_dm));
sim_fsusb_encoder sim_enc[2:0]
(.dp(usb_dp[2:0]), .dm(usb_dm[2:0]));
sim_fsusb_foot sim_foot
(.dp(usb_dp[3]), .dm(usb_dm[3]));
integer i;
reg [2:0] all_bits [999:0];
initial begin
$readmemh("sigma_delta_test_data.txt", all_bits, 0, 999);
mdata = 3'b0;
for (i = 0; i < 1000; i = i + 1) begin
wait(mclk[0]);
wait(~mclk[0]);
mdata = all_bits[i]; //{3{all_bits[i][0]}};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long min(long long a, long long b) { return (a < b) ? a : b; } int main() { long long n, m, b_max_1 = 0, b_max_2 = 0, g_min = 1e9; long long sum_b = 0, sum_g = 0; cin >> n >> m; long long b[n], g[m]; for (int i = 0; i < n; ++i) { cin >> b[i]; sum_b += b[i]; if (b[i] > b_max_1) { b_max_2 = b_max_1; b_max_1 = b[i]; } else if (b[i] > b_max_2) { b_max_2 = b[i]; } } sum_b = sum_b * m; for (int i = 0; i < m; ++i) { cin >> g[i]; sum_g += g[i]; g_min = min(g_min, g[i]); } if (b_max_1 > g_min) { cout << -1 << n ; return 0; } if (g_min > b_max_1) sum_b = sum_b + sum_g - (m - 1) * b_max_1 - b_max_2; else sum_b = sum_b - m * b_max_1 + sum_g; cout << sum_b << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; string s; cin >> s; set<char> S; int ans = 0; for (int i = 0; i <= s.size(); ++i) { if (i == s.size() || isupper(s[i])) { ans = max(ans, (int)S.size()); S.clear(); } else { S.insert(s[i]); } } cout << ans << endl; return 0; }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
strobe_ena_hr_clock_in,
strobe_ena_clock_in,
capture_strobe_ena,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
dll_delayctrl_in
);
input [6-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input strobe_ena_hr_clock_in;
input strobe_ena_clock_in;
input [2-1:0] capture_strobe_ena;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 1 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [14-1:0] parallelterminationcontrol_in;
input [14-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_ddio_3reg_stratixiv altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.strobe_ena_clock_in( strobe_ena_clock_in),
.capture_strobe_ena( capture_strobe_ena),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "true";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 533;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "1876 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "HIGH";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 2;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 9000;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.DLL_WIDTH = 6;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 2;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "true";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
endmodule
|
`ifndef MEMORY_V
`define MEMORY_V
`define MEM_CMD_WIDTH 1
`define MEM_CMD_READ 1'b0
`define MEM_CMD_WRITE 1'b1
module memory#(
parameter ADDRESS_WIDTH=32,
parameter DATA_WIDTH=32,
parameter SIZE = 1024*1024,
parameter READ_DELAY = 22,
parameter WRITE_DELAY = 15
)(
input clk,
input reset,
input [ADDRESS_WIDTH-1:0]i_address,
input [DATA_WIDTH-1:0]i_data,
input i_valid,
input i_res_ready,
input i_cmd,
output [DATA_WIDTH-1:0]o_data,
output o_res_valid,
output o_ready
);
`define CELLS (SIZE / (DATA_WIDTH / 8))
reg [DATA_WIDTH-1:0]memory_cells [0:`CELLS];
wire [ADDRESS_WIDTH-1:0]cell_address = i_address >> $clog2(DATA_WIDTH/8);
reg ready;
reg res_valid;
reg [DATA_WIDTH-1:0]data;
assign o_data = data;
assign o_res_valid = res_valid;
assign o_ready = ready;
//load data
initial begin
string file;
integer fd, size, result;
if ($value$plusargs("img=%s", file)) begin
// get file size
fd = $fopen(file, "r");
result = $fseek(fd, 0, 2);
result = $ftell(fd);
$fclose(fd);
size = (result / 11); // '0' + 'x' + 8chars + lf,
//one cell -- one line no matter the cell size
$display("Loading img file: %s, file size: %d, cells: %d", file, result, size);
$readmemh(file, memory_cells, 0, size - 1); // '0' + 'x' + 8chars + lf
$display("The first word is: %x", memory_cells[0]);
$display("The second word is: %x", memory_cells[1]);
end else begin
$display("Please specify input image file '+img'");
end
end
// reset
always @(posedge clk) begin
if (reset) begin
ready = 1'b1;
res_valid = 1'b0;
data = 1'bx;
end
if (!reset && i_valid && o_ready) begin
case (i_cmd)
//read takes
`MEM_CMD_READ: begin
#READ_DELAY data <= memory_cells[cell_address];
#READ_DELAY res_valid <= 1'b1;
ready <= 1'b0;
end
`MEM_CMD_WRITE: begin
//TODO
$display("Mem Write not implemented");
$finish();
end
endcase
end
if (!reset && res_valid && i_res_ready) begin
ready <= 1'b1;
res_valid <= 1'b0;
data <= 1'bx;
end
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int ispalin(string a) { string b = a; reverse(b.begin(), b.end()); return a == b; } int main() { string str; cin >> str; int N = str.size(); for (int i = 0; i <= N; i++) { for (char xc = a ; xc <= z ; xc++) { string str1; for (int j = 0; j < i; j++) str1 += str[j]; str1 += xc; for (int j = i; j < N; j++) str1 += str[j]; if (ispalin(str1)) { cout << str1; return 0; } } } cout << NA ; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:21:12 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_1/RAT_xlslice_0_1_stub.v
// Design : RAT_xlslice_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_xlslice_0_1(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[9:0],Dout[7:0]" */;
input [9:0]Din;
output [7:0]Dout;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_PP_V
|
// --------------------------------------------------------------------
// ng_ADR.v - Address decoding and Bank Register selection logic
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_ADR(
input CLK2, // Clock Pulse 2
input [ 15:0] WRITE_BUS, // Control Pulse
input [100:0] CP, // Control Pulse
output [ 5:0] SELECT, // Select Input
output [ 13:0] ADDRESS, // Address Input
output [ 15:0] ADR_BUS // ADR Module Bank reg output
);
// --------------------------------------------------------------------
// JTAG Debugging Probes
// --------------------------------------------------------------------
//JTAG_Probe1 Probe1_EQU_17(.probe( EQU_17 ));
//JTAG_Probe14 Probe1_ADDR (.probe( ADDRESS ));
// --------------------------------------------------------------------
// Control pulse definitions
// --------------------------------------------------------------------
wire GENRST = CP[`CPX(`GENRST)]; // General reset signal
wire WBK = CP[`CPX(`WBK)]; // Write BANK
wire WS = CP[`CPX(`WS)]; // Write S
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg [ 3:0] BNK; // BANK Register
reg [11:0] S; // S Register
// --------------------------------------------------------------------
// Instantiate Register S Latch
// --------------------------------------------------------------------
always @(posedge CLK2) begin // on positive edge
if(!GENRST) S <= 12'h000; // Clear to 0
else if(!WS) S <= WRITE_BUS[11:0]; // Load with bottom 12 bits
end
// --------------------------------------------------------------------
// Instantiate Register BNK Latch
// --------------------------------------------------------------------
always @(posedge CLK2) begin // on positive edge
if(!GENRST) BNK <= 4'h0; // Clear to 0
else if(!WBK) BNK <= WRITE_BUS[13:10]; // Load with top 4 bits
end
assign ADR_BUS = {2'b00, BNK, 10'h00}; // Place Bank reg on output bus
// --------------------------------------------------------------------
// Form up Address output
// --------------------------------------------------------------------
wire Bnk_sel = !(!(BNK[3] | BNK[2]) | !(S[11] & S[10])); // 1=use BNK
wire [3:0] BANK = Bnk_sel ? BNK : {2'b00, S[11:10]}; // Mux
assign ADDRESS = {BANK, S[9:0]};
// --------------------------------------------------------------------
// Selection Logic
// --------------------------------------------------------------------
wire GTR_1777 = !(ADDRESS > 14'o1777); // Greater than Octal 1777
wire GTR_17 = !(ADDRESS > 14'o0017); // Greater than Octal 17
wire GTR_27 = !(ADDRESS > 14'o0027); // Greater than Octal 27
wire EQU_25 = !(ADDRESS == 14'o0025); // Equal to Octal 25
wire EQU_17 = !(ADDRESS == 14'o0017); // Equal to Octal 17
wire EQU_16 = !(ADDRESS == 14'o0016); // Equal to Octal 16
// --------------------------------------------------------------------
// Selection definitions
// --------------------------------------------------------------------
assign SELECT[`SLX(`GTR_1777)] = GTR_1777; // Greater than Octal 1777
assign SELECT[`SLX(`GTR_17) ] = GTR_17; // Greater than Octal 17
assign SELECT[`SLX(`GTR_27) ] = GTR_27; // Greater than Octal 27
assign SELECT[`SLX(`EQU_25) ] = EQU_25; // Equal to Octal 25
assign SELECT[`SLX(`EQU_17) ] = EQU_17; // Equal to Octal 17
assign SELECT[`SLX(`EQU_16) ] = EQU_16; // Equal to Octal 16
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; template <class T> void chmin(T &a, const T &b) { if (a > b) a = b; } template <class T> void chmax(T &a, const T &b) { if (a < b) a = b; } long long dp[200020]; const long long INF = 1e18; int main() { cin.tie(0); ios::sync_with_stdio(false); int N; cin >> N; vector<long long> A(N); for (int i = 0; i < (N); ++i) cin >> A[i]; vector<pair<long long, int>> v; for (int i = 0; i < (N); ++i) v.push_back(make_pair(A[i], i)); sort(v.begin(), v.end()); for (int i = 0; i <= N; i++) dp[i] = INF; dp[0] = 0; for (int i = 0; i < N; i++) { int idx = v[i].second; long long mi = A[idx], ma = A[idx]; for (int j = 0; j < 5; j++) { if (i + j >= N) break; int nex = v[i + j].second; chmin(mi, A[nex]); chmax(ma, A[nex]); if (j >= 2) chmin(dp[i + 1 + j], dp[i] + ma - mi); } } long long K = dp[N]; vector<int> ans(N, 0); int tar = N; int col = 1; for (int i = N - 1; i >= 0; i--) { int idx = v[i].second; long long mi = A[idx], ma = A[idx]; for (int j = 0; j < 5; j++) { if (i + j >= N) break; if (i + j >= tar) break; int nex = v[i + j].second; chmin(mi, A[nex]); chmax(ma, A[nex]); if (j >= 2 && i + j == tar - 1) { long long res = dp[i] + ma - mi; if (res == dp[tar]) { for (int k = 0; k <= j; k++) ans[i + k] = col; col++; tar = i; break; } } } } cout << K << << col - 1 << endl; vector<int> res(N, 0); for (int i = 0; i < (N); ++i) res[v[i].second] = ans[i]; for (int i = 0; i < N; i++) cout << res[i] << ; cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long t, d, ct, q, ans, l, m, r, n, mx, mn, i, j, k, x, y, z, s; char ch; string ss = , str = ; long long a[200003], b[200003]; long long pref[200003]; int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); s = k = d = l = mx = m = mn = r = q = i = j = z = x = y = ct = ans = 0; for (i = 0; i < 26; i++) cin >> a[i]; cin >> ss; n = ss.length(); pref[1] = a[ss[0] - a ]; for (i = 1; i < n; i++) pref[i + 1] = pref[i] + a[ss[i] - a ]; vector<long long> v[26]; for (i = 0; i < n; i++) v[ss[i] - a ].push_back(i + 1); for (i = 0; i < 26; i++) { m = v[i].size(); if (m <= 1) continue; y = 0; vector<long long> diff; for (auto h : v[i]) diff.push_back(pref[h - 1]); map<long long, long long> mp; for (j = 0; j < diff.size(); j++) { ans += mp[diff[j] - a[i]]; mp[diff[j]]++; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; char t[200002]; struct node { int nt[5][5]; }; node st[4 * 200000 + 2]; node merge(node a, node b) { if (a.nt[0][0] == -1) return b; if (b.nt[0][0] == -1) return a; node ans; for (int i = 0; i <= 4; i++) for (int j = 0; j <= 4; j++) ans.nt[i][j] = -1e9; for (int i = 0; i <= 4; i++) { for (int j = i; j <= 4; j++) { ans.nt[i][j] = max(ans.nt[i][j], a.nt[i][j]); ans.nt[i][j] = max(ans.nt[i][j], b.nt[i][j]); for (int k = i; k <= j; k++) { ans.nt[i][j] = max(ans.nt[i][j], a.nt[i][k] + b.nt[k][j]); } } } return ans; } void build(int n, int s, int e) { if (s == e) { for (int i = 0; i <= 4; i++) for (int j = 0; j <= 4; j++) st[n].nt[i][j] = -1e9; for (int i = 0; i <= 4; i++) st[n].nt[i][i] = 1; if (t[s] == 2 ) { st[n].nt[0][1] = 1; st[n].nt[0][0] = -1e9; } else if (t[s] == 0 ) { st[n].nt[1][2] = 1; st[n].nt[1][1] = -1e9; } else if (t[s] == 1 ) { st[n].nt[2][3] = 1; st[n].nt[2][2] = -1e9; } else if (t[s] == 7 ) { st[n].nt[3][4] = 1; st[n].nt[3][3] = -1e9; } else if (t[s] == 6 ) { st[n].nt[3][3] = -1e9; st[n].nt[4][4] = -1e9; } } else { int mid = (s + e) / 2; build(n + n, s, mid); build(n + n + 1, mid + 1, e); st[n] = merge(st[n + n], st[n + n + 1]); } } node query(int n, int s, int e, int l, int r) { if (s > r || l > e) { node ans; ans.nt[0][0] = -1; return ans; } if (l <= s && e <= r) return st[n]; int mid = (s + e) / 2; return merge(query(n + n, s, mid, l, r), query(n + n + 1, mid + 1, e, l, r)); } int main() { int n, q; scanf( %d%d , &n, &q); scanf( %s , t + 1); build(1, 1, n); for (int i = 1; i <= q; i++) { int l, r; scanf( %d%d , &l, &r); node ans = query(1, 1, n, l, r); if (ans.nt[0][4] < 0) printf( -1 n ); else printf( %d n , r - l + 1 - ans.nt[0][4]); } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; unordered_map<long long, long long> mymap; long long maxval = INT_MIN, minval = INT_MAX; for (int i = 0; i < n; i++) { long long temp; cin >> temp; mymap[temp]++; if (temp > maxval) maxval = temp; if (temp < minval) minval = temp; } cout << maxval - minval << ; if (maxval == minval) cout << (mymap[maxval] * (mymap[maxval] - 1)) / 2 << endl; else cout << mymap[maxval] * mymap[minval] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> vector<T> uniq(vector<T> v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); return v; } template <typename T> struct RMQ { using F = function<T(const T &, const T &)>; int n; vector<T> t; F f; RMQ(int n, F f, T df = 0) : n(n), f(f), t(vector<T>(n << 1, df)) {} void modify(int p, T v) { for (t[p += n] = v; p > 1; p >>= 1) t[p >> 1] = f(t[p], t[p ^ 1]); } T query(int l, int r, T res = 0) { for (l += n, r += n + 1; l < r; l >>= 1, r >>= 1) { if (l & 1) res = f(res, t[l++]); if (r & 1) res = f(res, t[--r]); } return res; } }; int32_t main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> l(n + 1, 0), r(n + 1, 0); vector<int> a(n); for (int &x : a) cin >> x; vector<int> b; for (int i = 0; i < n; i++) { b.push_back(a[i] - i); b.push_back(a[i] - i + 1); } b = uniq(b); int ptr = 0; map<int, int> mp; for (int x : b) mp[x] = ++ptr; RMQ<int> ST(b.size() + 10, [&](int p, int q) { return max(p, q); }); for (int i = 0; i < n; i++) { l[i] = 1 + ST.query(1, mp[a[i] - i]); ST.modify(mp[a[i] - i], l[i]); } ST = RMQ<int>(b.size() + 10, [&](int p, int q) { return max(p, q); }); for (int i = n - 1; i >= 0; i--) { r[i] = 1 + ST.query(mp[a[i] - i], b.size() + 9); if (i + 1 < n) { int x = 1 + ST.query(mp[a[i + 1] - (i + 1) + 1], b.size() + 9); ST.modify(mp[a[i + 1] - (i + 1) + 1], x); } } int ans = 0; for (int i = 0; i < n; i++) ans = max(ans, l[i] + r[i] - 1); cout << n - 1 - min(n - 1, ans) << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfstp (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_PP_BLACKBOX_V
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Simulated Memory */
`include "consts.vh"
module mem (
input clk,
input reset,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
);
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory [MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
initial begin
/* Loads by word addresses. Address 0x302c corresponds to 0x0c0b. */
$readmemh("mem.hex", memory);
end
always @ (*) begin
if (enable && cmd == `MEM_CMD_READ) begin
load_data = memory[word_addr];
valid = 1;
end else begin
load_data = 32'b0;
valid = 0;
end
end
wire [31:0] expanded_mask = {mask[3] ? 8'hFF : 8'h00,
mask[2] ? 8'hFF : 8'h00,
mask[1] ? 8'hFF : 8'h00,
mask[0] ? 8'hFF : 8'h00};
wire [31:0] to_be_written = (memory[word_addr] & ~expanded_mask) | (write_data & expanded_mask);
always @ (*) begin
if (enable && cmd == `MEM_CMD_WRITE) begin
memory[word_addr] = to_be_written;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_8_V
`define SKY130_FD_SC_LP__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_8_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sun.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sun (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/sun.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/sun.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 23:35:07 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_stub.v
// Design : system_vga_sync_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync,Vivado 2016.4" *)
module system_vga_sync_0_0(clk, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
#include <bits/stdc++.h> int main() { long long int n; scanf( %lld , &n); printf( %lld n , n / 2 + 1); long long int count1 = 0; long long int count2 = 1; for (int i = 1; i <= n; i++) { if (i % 2 == 0) { count2++; } else { count1++; } printf( %lld %lld n , count1, count2); } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage3.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module stage3 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/phd.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/phd.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_SYMBOL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_SYMBOL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_267x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_267x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [266:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [266:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [266:0] sub_wire4;
wire rdempty = sub_wire0;
wire [6:0] wrusedw = sub_wire1[6:0];
wire wrfull = sub_wire2;
wire wrempty = sub_wire3;
wire [266:0] q = sub_wire4[266:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.wrempty (sub_wire3),
.q (sub_wire4)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 267,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "267"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "267"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "267"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 267 0 INPUT NODEFVAL data[266..0]
// Retrieval info: USED_PORT: q 0 0 267 0 OUTPUT NODEFVAL q[266..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 267 0 data 0 0 267 0
// Retrieval info: CONNECT: q 0 0 267 0 @q 0 0 267 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//#############################################################################
//# Function: Generic RAM memory #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_ram # (parameter DW = 104, //memory width
parameter DEPTH = 32, //memory depth
parameter AW = $clog2(DEPTH) // address width
)
(// read-port
input rd_clk,// rd clock
input rd_en, // memory access
input [AW-1:0] rd_addr, // address
output reg [DW-1:0] rd_dout, // data output
// write-port
input wr_clk,// wr clock
input wr_en, // memory access
input [AW-1:0] wr_addr, // address
input [DW-1:0] wr_wem, // write enable vector
input [DW-1:0] wr_din // data input
);
reg [DW-1:0] ram [DEPTH-1:0];
integer i;
//registered read port
always @ (posedge rd_clk)
if(rd_en)
rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
//write port with vector enable
always @(posedge wr_clk)
for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i];
endmodule // oh_memory_ram
|
#include <bits/stdc++.h> using namespace std; long long int INF = 1000000000; vector<vector<int> > v; int* dist; void bfs(int ver, int n) { bool vis[n]; for (int i = 0; i < n; i++) vis[i] = false; vis[ver] = true; queue<pair<int, int> > q; q.push(make_pair(ver, 0)); while (!q.empty()) { pair<int, int> p = q.front(); q.pop(); int a = p.first, b = p.second; dist[a] = b; for (int i = 0; i < v[a].size(); i++) { if (vis[v[a][i]] == false) { vis[v[a][i]] = true; q.push(make_pair(v[a][i], b + 1)); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n, m; cin >> n >> m; vector<vector<int> > vt(n); v = vt; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x -= 1; y -= 1; v[y].push_back(x); vt[x].push_back(y); } int k; cin >> k; vector<int> path(k); for (int i = 0; i < k; i++) { int x; cin >> x; x -= 1; path[i] = x; } dist = new int[n]; bfs(path[k - 1], n); vector<pair<int, int> > pos(k, make_pair(0, 0)); for (int i = 1; i < k; i++) { int ver = path[i - 1], pver = path[i]; vector<pair<int, int> > t; for (int j = 0; j < vt[ver].size(); j++) t.push_back(make_pair(dist[vt[ver][j]], vt[ver][j])); int md = t[0].first; for (int j = 1; j < t.size(); j++) md = min(md, t[j].first); for (int j = 0; j < t.size(); j++) { if (t[j].first == md and t[j].second == pver) pos[i].first = 1; if (t[j].first == md and t[j].second != pver) pos[i].second = 1; } } int mans = 0, Mans = 0; for (int i = 1; i < k; i++) { if (pos[i].first != 1) mans += 1; if (pos[i].second == 1) Mans += 1; } cout << mans << << Mans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 100005; const long long LL_INF = (long long)2e18 + 5; inline int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } const long long mod = 1000000007; bool isprime(long long n) { for (long long i = 2; i * i <= n; ++i) { if (n % i == 0) { return false; } } return true; } long long factorial(long long n) { return (n == 1 || n == 0) ? 1 : n * factorial(n - 1); } long long power(long long x, long long y) { long long res = 1; x = x % mod; while (y > 0) { if (y & 1) res = ((res % mod) * (x % mod)) % mod; y = y >> 1; x = ((x % mod) * (x % mod)) % mod; } return res; } long long ncr(long long n, long long r) { long long res = 1; if (r > n) return 0; if (r > n - r) r = n - r; for (long long i = 0; i < r; i++) { res = ((res % mod) * ((n - i) % mod)) % mod; res = ((res % mod) * (power(i + 1, mod - 2)) % mod) % mod; } return res; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long lcm(long long a, long long b) { return (a / gcd(a, b) * b); } long long max(long long a, long long b) { long long sol = a > b ? a : b; return sol; } long long min(long long a, long long b) { long long sol = a < b ? a : b; return sol; } map<long long, long long> mp; inline void solve() { long long n, k; long long a[26] = {0}; cin >> n >> k; string s; cin >> s; char ch; while (k--) { cin >> ch; a[ch - a ]++; } long long prev = -1, r; long long ans = 0; for (int i = 0; i < n; i++) { if (a[s[i] - a ] == 0) { r = i - prev - 1; ans += ((r * (r + 1)) / 2); prev = i; } } r = n - prev - 1; ans += ((r * (r + 1)) / 2); cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; solve(); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:40:26 10/09/2014
// Design Name: mojo_top
// Module Name: /home/bjones/src/fpga-tunes/test/mojo_top_tb.v
// Project Name: fpga-tunes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mojo_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mojo_top_tb;
// Inputs
reg clk;
reg rst_n;
reg cclk;
reg spi_ss;
reg spi_mosi;
reg spi_sck;
reg avr_tx;
reg avr_rx_busy;
reg [4:0] button;
// Outputs
wire [7:0] led;
wire spi_miso;
wire [3:0] spi_channel;
wire avr_rx;
wire [7:0] dac;
// Instantiate the Unit Under Test (UUT)
mojo_top uut (
.clk(clk),
.rst_n(rst_n),
.cclk(cclk),
.led(led),
.spi_miso(spi_miso),
.spi_ss(spi_ss),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_channel(spi_channel),
.avr_tx(avr_tx),
.avr_rx(avr_rx),
.avr_rx_busy(avr_rx_busy),
.dac(dac),
.button(button)
);
assign led[4:0] = button;
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
cclk = 0;
spi_ss = 0;
spi_mosi = 0;
spi_sck = 0;
avr_tx = 0;
avr_rx_busy = 0;
button = 0;
// 10 ns without clock
#10
// 10 ns with clock
repeat(10) #1 clk = ~clk;
// bring rst low
rst_n = ~rst_n;
// Press buttons 0 - 3 at increasing intervals
button[0] = 1;
repeat(20000) #1 clk = ~clk;
button[1] = 1;
repeat(40000) #1 clk = ~clk;
button[2] = 1;
repeat(160000) #1 clk = ~clk;
button[3] = 1;
repeat(320000) #1 clk = ~clk;
$finish;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Resize the data width between the source interface and the burst memory
* if necessary.
*/
`timescale 1ns/100ps
module axi_dmac_resize_src #(
parameter DATA_WIDTH_SRC = 64,
parameter DATA_WIDTH_MEM = 64
) (
input clk,
input reset,
input src_data_valid,
input [DATA_WIDTH_SRC-1:0] src_data,
input src_data_last,
output mem_data_valid,
output [DATA_WIDTH_MEM-1:0] mem_data,
output mem_data_last
);
generate if (DATA_WIDTH_SRC == DATA_WIDTH_MEM) begin
assign mem_data_valid = src_data_valid;
assign mem_data = src_data;
assign mem_data_last = src_data_last;
end else begin
localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_SRC;
reg [RATIO-1:0] mask = 'h1;
reg valid = 1'b0;
reg last = 1'b0;
reg [DATA_WIDTH_MEM-1:0] data = 'h0;
always @(posedge clk) begin
if (reset == 1'b1) begin
valid <= 1'b0;
mask <= 'h1;
end else if (src_data_valid == 1'b1) begin
valid <= mask[RATIO-1] || src_data_last;
if (src_data_last) begin
mask <= 'h1;
end else begin
mask <= {mask[RATIO-2:0],mask[RATIO-1]};
end
end else begin
valid <= 1'b0;
end
end
integer i;
always @(posedge clk) begin
for (i = 0; i < RATIO; i = i+1) begin
if (mask[i] == 1'b1) begin
data[i*DATA_WIDTH_SRC+:DATA_WIDTH_SRC] <= src_data;
end
end
last <= src_data_last;
end
assign mem_data_valid = valid;
assign mem_data = data;
assign mem_data_last = last;
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; char a[1 << 9][1 << 9]; void solve(int n) { if (n == 0) { a[0][0] = + ; return; } solve(n - 1); int mid = 1 << (n - 1); for (int i = (mid), _b = ((1 << n) - 1); i <= _b; ++i) for (int j = 0, _a = (mid); j < _a; ++j) a[i][j] = a[i - mid][j]; for (int i = 0, _a = (mid); i < _a; ++i) for (int j = (mid), _b = ((1 << n) - 1); j <= _b; ++j) a[i][j] = a[i][j - mid]; for (int i = (mid), _b = ((1 << n) - 1); i <= _b; ++i) for (int j = (mid), _b = ((1 << n) - 1); j <= _b; ++j) a[i][j] = + + * - a[i - mid][j - mid]; } int main() { ios ::sync_with_stdio(0); cin.tie(0); while (cin >> n) { solve(n); for (int i = 0, _a = (1 << n); i < _a; ++i) { for (int j = 0, _a = (1 << n); j < _a; ++j) putchar(a[i][j]); puts( ); } } }
|
#include <bits/stdc++.h> using namespace std; int n, x, l, r, m; int main() { cin >> n; int endtime = 0; while (n--) { cin >> x; endtime += x; } cin >> m; while (m--) { cin >> l >> r; if (endtime <= l) { cout << l << endl; return 0; } else if (endtime > r) { continue; } else { cout << endtime << endl; return 0; } } cout << -1 << endl; return 0; }
|
// DESCRIPTION: Verilator: Test symbol table scope map and general public
// signal reflection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module t
(
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo #(.WIDTH (65)) foo65 (.*);
foo #(.WIDTH (96)) foo96 (.*);
foo #(.WIDTH (97)) foo97 (.*);
foo #(.WIDTH (128)) foo128 (.*);
foo #(.WIDTH (256)) foo256 (.*);
foo #(.WIDTH (1024)) foo1024 (.*);
bar #(.WIDTH (1024)) bar1024 (.*);
endmodule
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ];
value_q = initial_value[ WIDTH - 1 : 0 ];
end
always @(posedge CLK)
value_q <= ~value_q;
endmodule
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e6 + 5; int arr[MAX_N]; int vis[MAX_N]; void solve() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); vis[i] = 0; } vector<int> stk; for (int i = 1; true; i = i - arr[i]) { if (vis[i]) { vector<int> ans; for (int j = stk.size() - 1; j >= 0; j--) { ans.push_back(stk[j]); if (stk[j] == i) break; } printf( %d n , (int)ans.size()); for (int u : ans) { printf( %d , u); } printf( n ); return; } else { vis[i] = 1; stk.push_back(i); } } } int main() { int testc; scanf( %d , &testc); for (int i = 0; i < testc; i++) { solve(); } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:38:15 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.v
// Design : system_zed_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_vga,Vivado 2016.4" *)
module system_zed_vga_0_0(rgb565, vga_r, vga_g, vga_b)
/* synthesis syn_black_box black_box_pad_pin="rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]" */;
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
//`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Set the clock signal, and its frequency
*
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/*
* Clock frequency is arbitrarily chosen
* Period = 10 ns, frequency = 100MHz
*/
#5 ck = 0;
#5 ck = 1;
end
/**
* Instantiate an instance of a convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
bin = 1'b0;
rset=0;
// @ t=3,
#3;
bin = 1'b1;
rset=0;
// @ t=10,
#7;
bin = 1'b0;
rset=0;
// @ t=19,
#9;
bin = 1'b1;
rset=0;
// @ t=29,
#10;
bin = 1'b0;
rset=0;
// @ t=39,
#10;
bin = 1'b1;
rset=0;
// @ t=50-1,
#10;
bin = 1'b0;
rset=0;
// @ t=60-1,
#10;
bin = 1'b1;
rset=0;
// @ t=70-1,
#10;
bin = 1'b0;
rset=0;
// @ t=80-1,
#10;
bin = 1'b0;
rset=0;
// @ t=90-1,
#10;
bin = 1'b1;
rset=0;
// @ t=100-1,
#10;
bin = 1'b1;
rset=1;
// @ t=110-1,
#9;
bin = 1'b0;
rset=0;
// @ t=120-1,
#10;
bin = 1'b1;
rset=0;
// @ t=130-1,
#10;
bin = 1'b0;
rset=0;
// @ t=140-1,
#10;
bin = 1'b1;
rset=1;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int res = 0, ans = 0; a[0] = -10; for (int i = 1; i <= n; i++) { if (a[i] == a[i - 1] + 1) res++; else res = 0; ans = max(res, ans); } ans = max(ans - 1, 0); int f1 = 0; for (int i = 1; i <= n + 1; i++) { if (a[i] == i) { f1++; } } int f2 = 0; for (int i = n; i >= 0; i--) { if (a[i] == (1000 - n + i)) { f2++; } } if (f1 >= n || f2 >= n) { f1 = n; f2 = n; } ans = max(ans, max(f1, f2) - 1); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int maxv = 2045; const long long mod = 1e9 + 7; const int maxn = 1e6 + 40; long long fac[maxn], inv[maxn]; long long qpow(long long a, long long p) { long long ans = 1; long long xx = a; while (p > 0) { if (p & 1) ans = (xx * ans) % mod; xx = (xx * xx) % mod; p >>= 1; } return ans; } void init() { fac[0] = 1; inv[0] = 1; for (long long i = 1; i < maxn; i++) { fac[i] = (fac[i - 1] * i) % mod; inv[i] = inv[i - 1] * qpow(i, mod - 2) % mod; } } int h, w, n; pair<long long, long long> a[maxv]; long long dp[maxv]; long long culC(long long a, long long b) { return fac[a] * inv[a - b] % mod * inv[b] % mod; } long long path(long long sx, long long sy, long long tx, long long ty) { return culC(ty - sy + tx - sx, tx - sx); } void solve() { for (int i = 0; i <= n; i++) { long long ans = 0; for (int j = 0; j < i; j++) { if (a[j].second <= a[i].second) ans += path(a[j].first, a[j].second, a[i].first, a[i].second) * dp[j] % mod, ans %= mod; } dp[i] = (path(1, 1, a[i].first, a[i].second) - ans) % mod + mod, dp[i] %= mod; } } int main() { init(); cin >> h >> w >> n; for (int i = 0; i < n; i++) { int c, r; scanf( %d%d , &r, &c); a[i].first = r; a[i].second = c; } sort(a, a + n); a[n] = pair<long long, long long>(h, w); solve(); cout << dp[n] << endl; return 0; }
|
#include <bits/stdc++.h> float a1(float x, float y, float z) { if (x >= 1.0) return z * log(y) + log(log(x)); else if (x < 1.0 && y < 1.0 && z < 1.0) return z * log(y) + log(log(1 / x)); else return 0.0 / 0.0; } float a2(float x, float y, float z) { if (x >= 1.0) return log(z) + log(y) + log(log(x)); else if (x < 1.0 && y < 1.0 && z < 1.0) return log(z) + log(y) + log(log(1 / x)); else return 0.0 / 0.0; } int main() { float x, y, z; scanf( %f %f %f , &x, &y, &z); float a[12]; char pat[12][10] = { x^y^z 0 , x^z^y 0 , (x^y)^z 0 , (x^z)^y 0 , y^x^z 0 , y^z^x 0 , (y^x)^z 0 , (y^z)^x 0 , z^x^y 0 , z^y^x 0 , (z^x)^y 0 , (z^y)^x 0 }; a[0] = a1(x, y, z); a[1] = a1(x, z, y); a[2] = a2(x, y, z); a[3] = a2(x, z, y); a[4] = a1(y, x, z); a[5] = a1(y, z, x); a[6] = a2(y, x, z); a[7] = a2(y, z, x); a[8] = a1(z, x, y); a[9] = a1(z, y, x); a[10] = a2(z, x, y); a[11] = a2(z, y, x); float ans; int pos, i; if (x >= 1.0) { ans = a[0]; pos = 0; } else if (y >= 1.0) { ans = a[4]; pos = 4; } else { ans = a[8]; pos = 8; } if (x < 1 && y < 1 && z < 1) { for (i = 11; i >= 0; --i) { if (a[i] <= ans) { ans = a[i]; pos = i; } } } else { for (i = 11; i >= 0; --i) { if (a[i] >= ans) { ans = a[i]; pos = i; } } } printf( %s , pat[pos]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); vector<string> s(n); for (string &e : s) cin >> e; vector<vector<int> > a(n, vector<int>(m, 0)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); vector<int> dp(1 << n, (1 << 30)); vector<vector<int> > cost(n, vector<int>(m, 0)), masks(n, vector<int>(m, 0)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int max_a = 0; for (int k = 0; k < n; k++) if (s[i][j] == s[k][j]) { max_a = max(max_a, a[k][j]); cost[i][j] += a[k][j]; masks[i][j] |= (1 << k); } cost[i][j] -= max_a; } dp[0] = 0; for (int mask = 1; mask < (1 << n); mask++) { int j = 0; for (; j < n; j++) if (mask & (1 << j)) break; for (int i = 0; i < m; i++) { dp[mask] = min(dp[mask], dp[mask & (mask ^ masks[j][i])] + cost[j][i]); dp[mask] = min(dp[mask], dp[mask ^ (1 << j)] + a[j][i]); } } printf( %d n , dp[(1 << n) - 1]); return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; ll min(ll a, ll b) { if (a < b) return a; return b; } void solve() { ll testCases; cin >> testCases; while (testCases--) { ll n; cin >> n; vector<ll> arr(n); vector<ll> res(n, 1); for (int i = 0; i < n; i++) cin >> arr[i]; int i = 0; for (i = 0; i < n; i++) { if (arr[i] != arr[(i + 1) % n]) break; } if (i == n) { cout << 1 n ; for (i = 0; i < n; i++) cout << 1 << ; cout << n ; continue; } if (n % 2 == 0) { cout << 2 n ; for (i = 0; i < n; i++) cout << (i % 2) + 1 << ; cout << n ; continue; } else { bool isTwo = 0; for (i = 0; i < n; i++) { if (arr[i] == arr[(i + 1) % n]) { for (int j = 0, k = i + 1; k < n; k++, j ^= 1) res[k] = j + 1; for (int j = 0, k = i; k >= 0; k--, j ^= 1) res[k] = j + 1; cout << 2 n ; for (auto e : res) cout << e << ; cout << n ; isTwo = 1; break; } } if (!isTwo) { cout << 3 n ; for (i = 0; i < n - 1; i++) cout << i % 2 + 1 << ; cout << 3 n ; } } } } int main() { { ios_base::sync_with_stdio(false); cin.tie(NULL); }; solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hdll__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_V
|
////////////////////////////////////////////////////////////////
// File: measure_position.v
// Author: T. Dotsikas, B. Brown
// About: Locate center (x,y) position of object
////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module measure_position #(
parameter INPUT_WIDTH = 11,
parameter COLOR_WIDTH = 10,
parameter FRAME_X_MAX = 640,
parameter FRAME_Y_MAX = 480,
parameter COUNT_THRESH = 40
)( //////////// CLOCK //////////
input clk,
//////////// DATA ///////////
input wire [(INPUT_WIDTH-1):0] vga_x,
input wire [(INPUT_WIDTH-1):0] vga_y,
input wire [(COLOR_WIDTH-1):0] delta_frame,
output wire [(INPUT_WIDTH-1):0] x_position,
output wire [(INPUT_WIDTH-1):0] y_position,
output wire xy_valid,
//////////// CONTROL ///////////
input wire aresetn,
input wire enable
);
// Internal Signals (widths determined based on max x and y values)
reg [18:0] total_count;
reg [26:0] x_coordinate_sum;
reg [26:0] y_coordinate_sum;
// Wrappers
reg [(INPUT_WIDTH-1):0] int_x_position;
reg [(INPUT_WIDTH-1):0] int_y_position;
reg int_xy_valid;
assign x_position = int_x_position;
assign y_position = int_y_position;
assign xy_valid = int_xy_valid;
// These are the three values used in the algorithm
always @(posedge clk or negedge aresetn) begin
// Reset
if (~aresetn)
begin
total_count <= 'd0;
x_coordinate_sum <= 'd0;
y_coordinate_sum <= 'd0;
end
// Enable
else if (~enable)
begin
total_count <= 'd0;
x_coordinate_sum <= 'd0;
y_coordinate_sum <= 'd0;
end
// Clear at end of frame
else if (vga_x == FRAME_X_MAX & vga_y == FRAME_Y_MAX)
begin
total_count <= 'd0;
x_coordinate_sum <= 'd0;
y_coordinate_sum <= 'd0;
end
// Check if all bits are 1, if so apply algorithm
else if (&delta_frame)
begin
total_count <= total_count + 1;
x_coordinate_sum <= x_coordinate_sum + vga_x;
y_coordinate_sum <= y_coordinate_sum + vga_y;
end
// Otherwise latch the values
else
begin
total_count <= total_count;
x_coordinate_sum <= x_coordinate_sum;
y_coordinate_sum <= y_coordinate_sum;
end
end
// Generate the algorithm result using the above values
always @(posedge clk or negedge aresetn) begin
// Reset
if (~aresetn)
begin
int_xy_valid <= 1'b0;
int_x_position <= 'd0;
int_y_position <= 'd0;
end
// Enable
else if (~enable)
begin
int_xy_valid <= 1'b0;
int_x_position <= 'd0;
int_y_position <= 'd0;
end
// Pulse result at end of frame
else if (vga_x == FRAME_X_MAX & vga_y == FRAME_Y_MAX)
begin
int_xy_valid <= 1'b1;
// Places a criteria on number of pixels that define an object
if (total_count < COUNT_THRESH)
begin
int_x_position <= {INPUT_WIDTH {1'b1}};
int_y_position <= {INPUT_WIDTH {1'b1}};
end
else
begin
int_x_position <= x_coordinate_sum / total_count;
int_y_position <= y_coordinate_sum / total_count;
end
end
else
begin
int_xy_valid <= 1'b0;
int_x_position <= int_x_position;
int_y_position <= int_y_position;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:44:08 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND4BB_FUNCTIONAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4bb (
VPWR,
VGND,
Y ,
A_N ,
B_N ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
// Local signals
wire D nand0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long n, s, h; string s2, s1; long long gw(long long n, long long x) { long long rs = 0; for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { for (__typeof(n) j = (0) - ((0) > (n)); j != (n) - ((0) > (n)); j += 1 - 2 * ((0) > (n))) { if ((i + j) % 2 == x) { rs++; } } } return rs; } int main() { ios_base::sync_with_stdio(false); cout.precision(30); cout.tie(0); cin.tie(0); cin >> n; for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { cin >> s1 >> s2; if (s2 == hard ) h++; else s++; } for (__typeof(1001) i = (1) - ((1) > (1001)); i != (1001) - ((1) > (1001)); i += 1 - 2 * ((1) > (1001))) { long long w = gw(i, 0), b = gw(i, 1); if (h <= b && s <= w || h <= w && s <= b) { cout << i << endl; return 0; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; char gride[5010]; vector<vector<char> > grid; vector<vector<int> > pesq, pesq2; vector<vector<int> > pdir, pdir2; vector<vector<int> > pcima, pcima2; vector<vector<int> > pbaxo, pbaxo2; void apaga(int i, int j) { if (pesq2[i][j] != -1) pdir2[i][pesq2[i][j]] = pdir2[i][j]; if (pdir2[i][j] != -1) pesq2[i][pdir2[i][j]] = pesq2[i][j]; if (pcima2[i][j] != -1) pbaxo2[pcima2[i][j]][j] = pbaxo2[i][j]; if (pbaxo2[i][j] != -1) pcima2[pbaxo2[i][j]][j] = pcima2[i][j]; } int simula(int i, int j) { if (grid[i][j] == U ) { int k = pcima2[i][j]; if (k == -1) return 1; apaga(i, j); return 1 + simula(k, j); } if (grid[i][j] == D ) { int k = pbaxo2[i][j]; if (k == -1) return 1; apaga(i, j); return 1 + simula(k, j); } if (grid[i][j] == L ) { int k = pesq2[i][j]; if (k == -1) return 1; apaga(i, j); return 1 + simula(i, k); } if (grid[i][j] == R ) { int k = pdir2[i][j]; if (k == -1) return 1; apaga(i, j); return 1 + simula(i, k); } return 0; } int main() { scanf( %d %d , &n, &m); grid.resize(n); for (int i = 0; i < n; i++) { scanf( %s , gride); grid[i].resize(m); for (int j = 0; j < m; j++) grid[i][j] = gride[j]; } pesq.resize(n); pdir.resize(n); pcima.resize(n); pbaxo.resize(n); for (int i = 0; i < n; i++) { pesq[i].resize(m); pdir[i].resize(m); pcima[i].resize(m); pbaxo[i].resize(m); int atu = -1; for (int j = 0; j < m; j++) if (grid[i][j] != . ) { pesq[i][j] = atu; atu = j; } atu = -1; for (int j = m - 1; j >= 0; j--) if (grid[i][j] != . ) { pdir[i][j] = atu; atu = j; } } for (int j = 0; j < m; j++) { int atu = -1; for (int i = 0; i < n; i++) if (grid[i][j] != . ) { pcima[i][j] = atu; atu = i; } atu = -1; for (int i = n - 1; i >= 0; i--) if (grid[i][j] != . ) { pbaxo[i][j] = atu; atu = i; } } int best = 0; int qts = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (grid[i][j] != . ) { pcima2 = pcima; pbaxo2 = pbaxo; pesq2 = pesq; pdir2 = pdir; int t = simula(i, j); if (t == best) qts++; else if (t > best) { best = t; qts = 1; } } printf( %d %d n , best, qts); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( -O2 ) const int LIM = 5e5 + 5, MOD = 1e9 + 7; int t, n, m, k, x, y; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tests; cin >> tests; cout << setprecision(10) << fixed; while (tests--) { long double d; cin >> d; long long v = d * d - 4 * d; if (v < -1e-9) { cout << N n ; } else { long double a, b, c; c = sqrt(v); a = (d + c) / 2; b = (d - c) / 2; cout << Y << a << << b << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t > 0) { int n; cin >> n; while (n > 0) { cout << 1 << ; n--; } cout << n ; t--; } return 0; }
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`timescale 1ps / 1ps
module SEGMENT_interface_AXI_test (
);
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
localparam tries = 4;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;
// Autogen localparams
reg CLK = 1'b0;
reg RST;
wire [7:0] SEGMENT_AN;
wire [7:0] SEGMENT_SEG;
// AXI4-lite master memory interfaces
reg axi_awvalid;
wire axi_awready;
reg [sword-1:0] axi_awaddr;
reg [3-1:0] axi_awprot;
reg axi_wvalid;
wire axi_wready;
reg [sword-1:0] axi_wdata;
reg [4-1:0] axi_wstrb;
wire axi_bvalid;
reg axi_bready;
reg axi_arvalid;
wire axi_arready;
reg [sword-1:0] axi_araddr;
reg [3-1:0] axi_arprot;
wire axi_rvalid;
reg axi_rready;
wire [sword-1:0] axi_rdata;
//integer fd1, tmp1, ifstop;
integer PERIOD = 5000 ;
integer i, error;
SEGMENT_interface_AXI
inst_SEGMENT_interface_AXI (
.CLK(CLK),
.RST(RST),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_awaddr(axi_awaddr),
.axi_awprot(axi_awprot),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_araddr(axi_araddr),
.axi_arprot(axi_arprot),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.axi_rdata(axi_rdata),
.SEGMENT_AN(SEGMENT_AN),
.SEGMENT_SEG(SEGMENT_SEG)
);
always
begin #(PERIOD/2) CLK = ~CLK; end
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else
begin
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
task axi_write;
input [sword-1:0] waddr, wdata;
begin
#(PERIOD*8);
// WRITTING TEST
axi_awvalid = 1'b1;
axi_awaddr = waddr;
#PERIOD;
while(!axi_awready) begin
#PERIOD;
end
axi_awvalid = 1'b0;
axi_wvalid = 1'b1;
axi_wdata = wdata;
#PERIOD;
while(!axi_wready) begin
#PERIOD;
end
axi_wvalid = 1'b0;
while(!axi_bvalid) begin
#PERIOD;
end
//axi_bready = 1'b1;
#PERIOD;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
//axi_bready = 1'b0;
end
endtask
task axi_read;
input [sword-1:0] raddr;
begin
// READING TEST
#(PERIOD*8);
axi_arvalid = 1'b1;
axi_araddr = raddr;
#PERIOD;
while(!axi_arready) begin
#PERIOD;
end
axi_arvalid = 1'b0;
while(!axi_rvalid) begin
#PERIOD;
end
//axi_rready = 1'b1;
#PERIOD;
axi_arvalid = 1'b0;
//axi_rready = 1'b0;
end
endtask
initial begin
//$sdf_annotate("AXI_SRAM.sdf",AXI_SRAM);
CLK = 1'b0;
RST = 1'b0;
error = 0;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b1;
axi_arvalid = 1'b0;
axi_rready = 1'b1;
axi_awaddr = {sword{1'b0}};
axi_awprot = {3{1'b0}};
axi_wdata = {sword{1'b0}};
axi_wstrb = 4'b1111;
axi_araddr = {sword{1'b0}};
axi_arprot = {3{1'b0}};
#101000;
RST = 1'b1;
//while(1) begin
axi_write(32'h00000000 << 2, {24'd0, "a"});
axi_write(32'h00000000 << 2, {24'd0, "b"});
axi_write(32'h00000000 << 2, {24'd0, "r"});
axi_write(32'h00000000 << 2, {24'd0, "a"});
axi_write(32'h00000000 << 2, {24'd0, "s"});
axi_write(32'h00000000 << 2, {24'd0, "e"});
axi_write(32'h00000000 << 2, {24'd0, "."});
axi_write(32'h00000000 << 2, {24'd0, " "});
//end
//$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; const int MAX = 1000100; const int off = 1 << 19; const int inf = 1e9; int a[MAX], s[MAX], c[MAX]; pair<int, int> T[2 * off]; int n, k; pair<int, int> getmax(int i, int lo, int hi, int a, int b) { if (lo >= b || hi <= a) return {-inf, -1}; if (lo >= a && hi <= b) return T[i]; return max(getmax(i * 2, lo, (lo + hi) / 2, a, b), getmax(i * 2 + 1, (lo + hi) / 2, hi, a, b)); } long long solve(int lo, int hi) { if (lo >= hi) { for (int i = lo; i <= hi; ++i) c[s[i]]--; return 0; } int m = getmax(1, 0, off, lo, hi).second; assert(m != -1); long long ans = 0; if (hi - m < m - lo) { for (int i = m + 1; i <= hi; ++i) c[s[i]]--; for (int i = m + 1; i <= hi; ++i) ans += c[(s[i] - (a[m] % k) + k) % k]; ans--; ans += solve(lo, m); for (int i = m + 1; i <= hi; ++i) c[s[i]]++; ans += solve(m + 1, hi); } else { for (int i = lo; i <= m; ++i) c[s[i]]--; for (int i = lo; i <= m; ++i) ans += c[(s[i] + a[m]) % k]; ans--; ans += solve(m + 1, hi); for (int i = lo; i <= m; ++i) c[s[i]]++; ans += solve(lo, m); } return ans; } int main(void) { scanf( %d %d , &n, &k); for (int i = (0); i < (n); ++i) scanf( %d , a + i); s[0] = 0; for (int i = (0); i < (n); ++i) s[i + 1] = (s[i] + a[i]) % k; for (int i = (0); i < (n + 1); ++i) c[s[i]]++; for (int i = (0); i < (n); ++i) T[off + i] = {a[i], i}; for (int i = off - 1; i > 0; --i) T[i] = max(T[i * 2], T[i * 2 + 1]); long long ans = solve(0, n); printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int n; vector<pair<int, int> > v; vector<int> tail; int getIdx(int l, int r, int key) { while (l < r) { int mid = (l + r) / 2; if (tail[mid] < key) r = mid; else l = mid + 1; } return r; } int LIS() { int length = 1; tail[0] = v[0].second; for (int i = 1; i < n; i++) { if (v[i].second > tail[0]) tail[0] = v[i].second; else if (v[i].second < tail[length - 1]) tail[length++] = v[i].second; else { tail[getIdx(0, length - 1, v[i].second)] = v[i].second; } } return length; } int main() { int x, y; scanf( %d , &n); v = vector<pair<int, int> >(n); for (int i = 0; i < n; i++) { scanf( %d , &x); x--; v[x].first = i; } for (int i = 0; i < n; i++) { scanf( %d , &y); y--; v[y].second = i; } sort(v.begin(), v.end()); tail = vector<int>(n, 0); cout << LIS(); return 0; }
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#include <bits/stdc++.h> using namespace std; int dp[(1 << 22)], a[1000000]; int main() { int N; while (scanf( %d , &N) != EOF) { memset(dp, -1, sizeof(dp)); for (int i = int(0); i < int(N); i++) { scanf( %d , a + i); dp[a[i]] = a[i]; } for (int i = int(0); i < int(22); i++) { for (int j = int(0); j < int((1 << 22)); j++) { if (~dp[j]) dp[j | 1 << i] = dp[j]; } } for (int i = int(0); i < int(N); i++) { printf( %d%c , dp[~a[i] & (1 << 22) - 1], n [i == N - 1]); } } return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long read() { register long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } const long long N = 1e5 + 10; const long long M = N; const long long INF = 1e16; struct edge { long long u, v, w, next; bool operator<(const edge &x) const { return w < x.w; } } e[M << 1]; long long head[N], cnt; void add(long long u, long long v, long long w = 0) { e[++cnt] = (edge){u, v, w, head[u]}; head[u] = cnt; } long long n, m, k, ans = INF; long long dis[N], s[N], from[N]; bool vis[N]; struct node { long long u, d; bool operator<(const node &x) const { return d > x.d; } }; priority_queue<node> q; void Dij() { for (long long i = 1; i <= n; i++) from[i] = vis[i] = 0, dis[i] = INF; for (long long i = 1; i <= k; i++) from[s[i]] = s[i], dis[s[i]] = 0, q.push((node){s[i], 0}); while (!q.empty()) { long long u = q.top().u; q.pop(); if (vis[u]) continue; vis[u] = 1; for (long long i = head[u]; i; i = e[i].next) { long long v = e[i].v; if (vis[v]) continue; if (dis[v] > dis[u] + e[i].w) { dis[v] = dis[u] + e[i].w; from[v] = from[u]; q.push((node){v, dis[v]}); } } } } long long fa[N]; long long find(long long x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } void krus() { for (long long i = 1; i <= cnt; i++) { e[i].w += dis[e[i].u] + dis[e[i].v]; e[i].u = from[e[i].u], e[i].v = from[e[i].v]; } sort(e + 1, e + cnt + 1); for (long long i = 1; i <= cnt; i++) { long long fx = find(e[i].u), fy = find(e[i].v); if (fx == fy) continue; ans += e[i].w; fa[fx] = fy; } } signed main() { n = read(), m = read(); for (long long i = 1; i <= n; i++) fa[i] = i; for (long long i = 1; i <= m; i++) { long long u = read(), v = read(), w = read(); add(u, v, w), add(v, u, w); } s[k = 1] = 1; Dij(); k = read(); for (long long i = 1; i <= k; i++) { s[i] = read(); ans = min(ans, dis[s[i]]); } Dij(); krus(); cout << ans; }
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#include <bits/stdc++.h> const long long mod = 1000000007; int n; long long x[1 << 20]; long long y[1 << 20]; long long d[1 << 20]; long long sx[1 << 20]; long long sy[1 << 20]; long long sd[1 << 20]; long long ssd[1 << 20]; long long cirsm(int s, int v, long long sa[] = sd) { long long ar = 0; if (s > 0 && v > s) { ar = sa[v - 1] - sa[s - 1]; } else if (s == 0) { ar = sa[v - 1]; } else { ar = sa[n + v - 1] - sa[s - 1]; } return ar; } long long area(int s, int v) { long long ar = cirsm(s, v); ar += (x[s] - x[v]) * (y[s] + y[v]); return ar; } long long sumsd2(int s, int v) { long long ar = 0; if (s == 0) { ar = ssd[v - 1]; } else if (s < v) { long long rm = (long long)(v - s) * (sd[s - 1] % mod); rm = rm % mod; if (rm < 0) { rm += mod; } ar = (mod + ssd[v - 1] - ssd[s - 1] + mod - rm) % mod; } else { v += n; long long rm = (long long)(v - s) * (sd[s - 1] % mod); rm = rm % mod; if (rm < 0) { rm += mod; } ar = (mod + ssd[v - 1] - ssd[s - 1] + mod - rm) % mod; } return ar; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { long long xx, yy; scanf( %lld %lld , &xx, &yy); x[i + n] = x[i] = xx; y[i + n] = y[i] = yy; } for (int i = 0; i < 2 * n; ++i) { if (i + 1 < 2 * n) { d[i] = (x[i + 1] - x[i]) * (y[i + 1] + y[i]); } else { d[i] = d[i - n]; } if (i == 0) { sx[i] = x[i]; sy[i] = y[i]; sd[i] = d[i]; ssd[i] = sd[i] % mod; if (ssd[i] < 0) { ssd[i] += mod; } } else { sx[i] = sx[i - 1] + x[i]; sy[i] = sy[i - 1] + y[i]; sd[i] = sd[i - 1] + d[i]; ssd[i] = ssd[i - 1] + sd[i]; ssd[i] %= mod; if (ssd[i] < 0) { ssd[i] += mod; } } } long long S = sd[n - 1]; long long ans = 0; int k = 1; int v = 0; long long dsm = 0; while (k < n && 2 * area(0, k + 1) < S) { ++k; dsm += (x[k] - x[0]) * (y[k] + y[0]); dsm %= mod; if (dsm < 0) { dsm += mod; } } for (int i = 0; i < n; ++i) { long long lt = cirsm(i, k) % mod; if (lt < 0) { lt += mod; } long long gt = cirsm(k, i) % mod; if (gt < 0) { gt += mod; } long long cnt = (k - 1 - i); if (cnt < 0) { cnt += n; } long long aa = 0; aa = cnt * (cirsm(i + 1, k) % mod) - sumsd2(i + 1, k); aa %= mod; if (aa < 0) { aa += mod; } if (cnt) { long long ch = cnt * (gt - lt + mod) + aa + aa + 2LL * dsm; ch %= mod; ans += ch; ans %= mod; if (ans < 0) { ans += mod; } } if (i + 1 >= n) { break; } if (k != (i + 1) % n) { int j = (i + 2) % n; dsm -= (x[j] - x[i]) * (y[j] + y[i]); dsm %= mod; if (dsm < 0) { dsm += mod; } } long long ndi = k - i - 2; if (ndi < 0) { ndi += n; } if (k != (i + 1) % n && k != (i + 2) % n) { long long c = (x[i + 1] * y[i + 1] - x[i] * y[i]) % mod; dsm = dsm - c * ndi; dsm %= mod; long long xsm = cirsm(i + 3, k + 1, sx) % mod; dsm += xsm * (y[i + 1] - y[i]); long long ysm = cirsm(i + 3, k + 1, sy) % mod; dsm -= ysm * (x[i + 1] - x[i]); dsm %= mod; if (dsm < 0) { dsm += mod; } } if ((i + 1) == k) { k = (i + 2) % n; } while ((unsigned long long)2LL * (unsigned long long)area(i + 1, (k + 1) % n) < S) { k = (k + 1) % n; dsm += (x[k] - x[i + 1]) * (y[k] + y[i + 1]); dsm %= mod; if (dsm < 0) { dsm += mod; } } } ans += mod; ans %= mod; printf( %lld n , (long long)ans); return 0; }
|
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = ~(a ^ b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
xnor104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
//`timescale 1 ms /1 us
`include "mux81a.v"
module chap4p32a_tb (S);
// module declaration
output [0:3] S;
reg [0:3] S;
//S[0]=A, S[1]=B, S[2]=C, S[3]=D
wire [0:7] I;
wire Y;
integer fp;
// program body
assign I[0]=~S[3];
assign I[1]=~S[3];
assign I[2]=S[3];
assign I[3]=S[3];
assign I[4]=1'b0;
assign I[5]=S[3];
assign I[6]=1'b0;
assign I[7]=~S[3];
mux81a I1 (I,S[0:2],Y);
initial
begin
fp=$fopen("./chap4p32a_tb.out");
$fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
#2000
$fclose(fp);
$finish;
end
initial
begin
S=4'b0000;
#100
S=4'b0001;
#100
S=4'b0010;
#100
S=4'b0011;
#100
S=4'b0100;
#100
S=4'b0101;
#100
S=4'b0110;
#100
S=4'b0111;
#100
S=4'b1000;
#100
S=4'b1001;
#100
S=4'b1010;
#100
S=4'b1011;
#100
S=4'b1100;
#100
S=4'b1101;
#100
S=4'b1110;
#100
S=4'b1111;
end
initial #4000 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int nex = 2e5 + 5; void solve() { int a, b; cin >> a >> b; string s; cin >> s; int cnt = 0; vector<int> v; for (int i = 0; i < ((int)s.size()); i++) { if (s[i] == X ) { if (cnt) v.push_back(cnt); cnt = 0; } else { cnt++; } } if (cnt) v.push_back(cnt); cnt = 0; int val = 0; for (int x : v) { if (x < a && x >= b) { cout << NO n ; return; } if (x >= a && x < 2 * b) cnt++; else if (x >= 2 * b) { if (val) { cout << NO n ; return; } val = x; } } cnt = cnt; for (int i = 0; i <= (val - a); i++) { int x = i, y = val - a - i, lcnt = cnt; if (x < 2 * b && y < 2 * b) { if (x < a && x >= b) continue; if (y < a && y >= b) continue; if (y >= a) lcnt++; if (x >= a) lcnt++; if (lcnt % 2 == 0) { cout << YES n ; return; } } } if (val == 0) { if (cnt % 2) cout << YES n ; else cout << NO n ; return; } cout << NO n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cout << fixed << setprecision(11); clock_t beg = clock(); int t = 1, n; cin >> t; while (t--) { solve(); } clock_t end = clock(); fprintf(stderr, %lf sec n , (double)(end - beg) / (CLOCKS_PER_SEC)); return 0; }
|
module signed_multiplier_test;
reg failed_flag = 0;
reg signed [5:0] s_prod;
wire [2:0] u_pos_two = 3'b010;
wire signed [2:0] s_pos_two = 3'sb010;
wire signed [2:0] s_neg_two = 3'sb110;
wire s = 1'b1; // flag to indicate signed
wire u = 1'b0; // flag to indicate unsigned
initial begin
// unsigned positive two as first argument of multiply
#1 s_prod = u_pos_two * u_pos_two;
check_mult(1,u,u_pos_two,u,u_pos_two,s_prod,6'sb000100);
#1 s_prod = u_pos_two * s_pos_two;
check_mult(2,u,u_pos_two,s,s_pos_two,s_prod,6'sb000100);
// This makes an unsigned result.
#1 s_prod = u_pos_two * s_neg_two;
check_mult(3,u,u_pos_two,s,s_neg_two,s_prod,6'sb001100);
// signed positive two as first argument of multiply
#1 s_prod = s_pos_two * u_pos_two;
check_mult(4,s,s_pos_two,u,u_pos_two,s_prod,6'sb000100);
#1 s_prod = s_pos_two * s_pos_two;
check_mult(5,s,s_pos_two,s,s_pos_two,s_prod,6'sb000100);
#1 s_prod = s_pos_two * s_neg_two;
check_mult(6,s,s_pos_two,s,s_neg_two,s_prod,6'sb111100);
// signed negative two as first argument of multiply
// This makes an unsigned result.
#1 s_prod = s_neg_two * u_pos_two;
check_mult(7,s,s_neg_two,u,u_pos_two,s_prod,6'sb001100);
#1 s_prod = s_neg_two * s_pos_two;
check_mult(8,s,s_neg_two,s,s_pos_two,s_prod,6'sb111100);
#1 s_prod = s_neg_two * s_neg_two;
check_mult(9,s,s_neg_two,s,s_neg_two,s_prod,6'sb000100);
if (failed_flag == 0)
$display("PASSED");
$finish;
end
task check_mult;
input [31:0] idx;
input signeda;
input [ 2:0] arga;
input signedb;
input [ 2:0] argb;
input [ 5:0] result,expected;
if (result !== expected) begin
failed_flag = 1;
$write("failed: test %0d, ",idx);
if (signeda)
$write("3'sb%b",arga);
else
$write("3 'b%b",arga);
$write(" * ");
if (signedb)
$write("3'sb%b",argb);
else
$write("3 'b%b",argb);
$write(" = 6'sb%b (expected 6'sb%b)\n",result,expected);
end
endtask
endmodule
|
module testbench_BoothPPG_32R4_MSB();
reg[31:0] mulcand;
reg msb;
reg sign;
wire[31:0] pp;
BoothPPG_32R4_MSB ppg(.mulcand(mulcand), .msb(msb), .sign(sign), .pp(pp));
task check(input[31:0] cand);
reg[31:0] expectPP;
reg errorFlag;
begin
errorFlag = 0;
mulcand = cand;
sign = 1;
msb = 1;
expectPP = 0;
#10;
if (pp !== expectPP) begin
$display("fail: mulcand = %x, msb = %1b, sign = %1b, expect pp = %x, but actual pp = %x", mulcand, msb, sign, expectPP, pp);
errorFlag = 1;
end
msb = 0;
expectPP = 0;
#10;
if (pp !== expectPP) begin
$display("fail: mulcand = %x, msb = %1b, sign = %1b, expect pp = %x, but actual pp = %x", mulcand, msb, sign, expectPP, pp);
errorFlag = 1;
end
sign = 0;
msb = 1;
expectPP = mulcand;
#10;
if (pp !== expectPP) begin
$display("fail: mulcand = %x, msb = %1b, sign = %1b, expect pp = %x, but actual pp = %x", mulcand, msb, sign, expectPP, pp);
errorFlag = 1;
end
msb = 0;
expectPP = 0;
#10;
if (pp !== expectPP) begin
$display("fail: mulcand = %x, msb = %1b, sign = %1b, expect pp = %x, but actual pp = %x", mulcand, msb, sign, expectPP, pp);
errorFlag = 1;
end
if(errorFlag === 0) begin
$display("mulcand = %x passed", cand);
end
else begin
$display("mulcand = %x failed", cand);
end
end
endtask
integer loopchk;
initial begin
for(loopchk = 0; loopchk < 100; loopchk = loopchk+1) begin
check($random());
end
check(32'h00000001);
check(32'h00000001);
check(32'h10000001);
check(32'hffffffff);
check(32'hdeadbeef);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long N = 200; long long c[N][N], dp[N][N * N + N], g[N][N]; long long modp(long long a, long long b) { if (b == 0) return 1; long long u = modp(a, b / 2); u = (u * u) % mod; if (b & 1) return (a * u) % mod; return u; } int32_t main() { long long n, m, o; cin >> n >> m >> o; for (long long i = 0; i < N; i++) c[i][0] = dp[i][0] = 1; for (long long i = 1; i < N; i++) for (long long j = 1; j <= i; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mod; for (long long i = 1; i <= n; i++) for (long long j = 0; j <= n; j++) g[i][j] = modp(c[n][j], (m + n - i) / n); for (long long i = 1; i <= n; i++) for (long long j = 1; j <= n * i; j++) for (long long k = max(j - n, 0LL); k <= j; k++) { dp[i][j] = (dp[i][j] + dp[i - 1][k] * g[i][j - k]) % mod; } cout << dp[n][o] << n ; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 2e2 + 10; vector<string> v[N]; int nex[N]; int flag[N]; int main() { int n; cin >> n; map<char, int> mc; memset((nex), (-1), sizeof(nex)); while (n--) { string str; cin >> str; int o = 0; for (auto &c : str) { mc[c] = 1; if (flag[c] == 0) flag[c] = 1; if (o >> (c - 0 ) & 1) { puts( NO ); return 0; } o |= 1 << (c - 0 ); } for (int i = 0; i + 1 < str.length(); i++) { if (nex[str[i]] == -1) { nex[str[i]] = str[i + 1]; flag[str[i + 1]] = 2; } if (nex[str[i]] != str[i + 1]) { puts( NO ); return 0; } } } string ans; for (int i = a ; i <= z ; i++) { if (flag[i] != 1) continue; int c = i; while (c != -1 && ans.length() <= mc.size()) { ans.push_back(c); c = nex[c]; } } if (ans.length() != mc.size()) { puts( NO ); } else puts(ans.c_str()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 5e5 + 5; bool vis[MAXN]; long long sp[MAXN]; long long f[MAXN]; bool is[MAXN]; long long ar[MAXN]; long long POWER[25]; long long F[25]; void sieve() { for (long long i = 0; i < MAXN; i++) vis[i] = false, sp[i] = 2; for (long long i = 3; i < MAXN; i += 2) { if (!vis[i]) { sp[i] = i; for (long long j = i * i; j < MAXN; j += 2 * i) { vis[j] = true; sp[j] = i; } } } } int main() { long long n, q; cin >> n >> q; for (long long i = 1; i <= n; i++) scanf( %lld , &ar[i]); sieve(); long long added = 0; POWER[0] = 1; for (long long i = 1; i < 15; i++) POWER[i] = POWER[i - 1] << 1; long long ans = 0; while (q--) { long long x; long long temp = 0; scanf( %lld , &x); long long cc = 0; long long val = ar[x]; while (val != 1) { long long div = sp[val]; F[cc++] = div; while (val % div == 0) val /= div; } for (long long i = 1; i < POWER[cc]; i++) { long long p = 1; long long counter = 0; for (long long j = 0; j < cc; j++) if (POWER[j] & i) counter++, p *= F[j]; if (counter & 1) temp += f[p]; else temp -= f[p]; } if (is[x]) { ans -= added - temp; if (ar[x] == 1) ans++; is[x] = false; for (long long i = 1; i < POWER[cc]; i++) { long long p = 1; for (long long j = 0; j < cc; j++) if (POWER[j] & i) p *= F[j]; f[p]--; } added--; } else { ans += added - temp; is[x] = true; for (long long i = 1; i < POWER[cc]; i++) { long long p = 1; for (long long j = 0; j < cc; j++) if (POWER[j] & i) p *= F[j]; f[p]++; } added++; } printf( %lld n , ans); } return 0; }
|
`timescale 1ns / 1ps
/*
-- Module Name: Outport Scheduler Control Unit
-- Description: Maquina de control para las unidades perteneceientes al
planificador de salida. En general, el modulo espera
a recibir una peticion desde cualquier puerto
(any_request_din).
Al recibir peticiones, el modulo da la señal
(arbiter_strobe_dout) de inicio de un proceso de
arbitraje por el uso del puerto de salida ligado a el.
Al obtener un resultado del arbitraje, el modulo deja
saber al la fuente de la peticion ganadora, por medio
de la señal 'transfer_strobe_dout', que puede empezar
el envio del paquete.
-- Dependencies: -- system.vh
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 06 de Junio 2015
*/
`include "system.vh"
module outport_scheduler_control_unit #(
parameter PORT_DIR = `X_POS
)
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire any_request_din,
input wire credit_in_din,
// -- outputs ------------------------------------------------ >>>>>
output wire zero_credits_dout,
output wire transfer_strobe_dout,
output wire arbiter_strobe_dout,
output wire clear_arbiter_dout
);
// -- Declaracion de parametros locales -------------------------- >>>>>
localparam CREDITS = (PORT_DIR == `PE) ? 1 : `BUFFER_DEPTH/5;
localparam CRT_WIDTH = clog2(CREDITS);
localparam FLIT_COUNTER_WITDH = clog2(`DATA_FLITS);
// -- FSM -------------------------------------------------------- >>>>>
localparam IDLE = 1'b0;
localparam ACTIVE = 1'b1;
// -- Declaracion Temprana de Señales ---------------------------- >>>>>
wire credit_sub;
/*
-- Contador de Creditos y de Flits faltantes
-- Descripcion: Contadores de apoyo para la operacion del puerto de
salida.
Contador de Flits: Lleva control de el numero de flits
que han sido transferidos desde el
puerto de entrada al puerto de
salida.
Contador de Creditos: Control de espacio disponible en
buffer en el router vecino.
Nucleo del mecanismo de control
de flujo de paquetes entre
routers (credit flow control).
*/
// -- Elemento de Memoria :: Contador de Flits --------------- >>>>>
reg [FLIT_COUNTER_WITDH:0] counter_reg;
wire counter_sub;
wire counter_clear;
wire couter_reset;
assign couter_reset = reset | counter_clear;
always @(posedge clk)
if(couter_reset)
counter_reg <= `DATA_FLITS;
else
if (counter_sub)
counter_reg <= counter_reg - 1'b1;
// -- Logica de Estado Siguiente :: Contador de Flits -------- >>>>>
assign counter_sub = (state_reg == ACTIVE) ? 1'b1 : 1'b0;
assign counter_clear = (state_reg == ACTIVE && state_next == IDLE) ? 1'b1 : 1'b0;
// -- Elemento de Memoria :: Contador de Creditos ------------ >>>>>
reg [CRT_WIDTH-1:0] credit_reg;
reg [CRT_WIDTH-1:0] credit_next;
always @(posedge clk)
if (reset)
credit_reg <= CREDITS;
else
credit_reg <= credit_next;
always @(*)
begin
credit_next = credit_reg;
case ({credit_in_din, credit_sub})
2'b01: credit_next = credit_reg - 1'b1;
2'b10: credit_next = credit_reg + 1'b1;
endcase //{credit_in_din, credit_sub}
end
// -- Logica de Estado Siguiente :: Contador de Creditos ----- >>>>>
assign credit_sub = (state_reg == IDLE && state_next == ACTIVE) ? 1'b1 : 1'b0;
// -- Logica de salida del contador de creditos -------------- >>>>>
assign zero_credits_dout = ~|credit_reg;
/*
-- Maquina de Estados Finito :: Tranferencia de Flits
-- Descripcion: La FSM tiene dos estados: IDLE Y ACTIVE.
En estado de reposo (IDLE) la maquina solo esta a la
espera de la llegada de una o mas peticiones desde
cualquier modulo 'link controller'.
Durante la transicion de estado de reposo a activo
(ACTIVE) se solicita el bloqueo de la peticion ganadora
en el arbitro (arbiter_strobe_dout). Ademas se envia una
señal (transfer_strobe_dout) a la peticion ganadora para
avisar que se puede iniciar la transferencia de flits.
El estado ACTIVE tiene una duracion igual al numero de
flits de un paquete.
El proceso de arbitraje no puede iniciar si no hay
creditos disponibles para el envio de paquetes al
siguiente router.
*/
// -- FSM :: Elementos de Memoria ---------------------------- >>>>>
reg state_reg;
reg state_next;
always @(posedge clk)
if (reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- FSM :: Logica de Estado Siguiente ---------------------- >>>>>
always @(*)
begin
state_next = state_reg;
case (state_reg)
IDLE:
if((|credit_reg) & any_request_din)
state_next = ACTIVE;
ACTIVE:
if (|counter_reg)
state_next = ACTIVE;
else
state_next = IDLE;
endcase //state_reg
end
/*
-- Logica de Salida
-- Descripcion: La logica de salida del modulo depende del estado
presente y estado siguiente de ambas maquinas de
estado finito.
clear_arbiter_dout: Da clear al resultado actual del
arbitro, eliminando la salida de datos provenientes
de cualquier puerto de entrada. Se considera como el
estado de reposo.
arbiter_strobe_dout: Señal de captura del resultado
del presente proceso de arbitraje.
*/
assign clear_arbiter_dout = (state_reg == ACTIVE && state_next == IDLE) ? 1'b1 : 1'b0;
assign arbiter_strobe_dout = (state_reg == IDLE && state_next == ACTIVE) ? 1'b1 : 1'b0;
reg transfer_strobe_reg = 1'b0;
always @(posedge clk)
if (state_reg == IDLE && state_next == ACTIVE)
transfer_strobe_reg <= 1'b1;
else
transfer_strobe_reg <= 1'b0;
assign transfer_strobe_dout = transfer_strobe_reg;
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
// -- Simbolos de Depuracion --------------------------------- >>>>>
reg [8*9:0] estado_presente;
reg [5*8:0] crd_count_reg_dbg;
always @(*)
case (state_reg)
IDLE: estado_presente = "IDLE";
ACTIVE: estado_presente = "ACTIVE";
endcase //state_reg
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
outport_scheduler_control_unit unidad_de_control_planificador_salida
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.any_request_din (port_request_din),
.credit_in_din (credit_in_din),
// -- outputs ------------------------------------------------ >>>>>
.zero_credits_dout (zero_credits_dout),
.transfer_strobe_dout (transfer_strobe_dout),
.arbiter_strobe_dout (arbiter_strobe_dout),
.clear_arbiter_dout (clear_arbiter_dout)
);
*/
|
/******************************************************************************
* File Name : ks58.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 1/Apr/2008
* Type of file : Verilog source code
* Synopsis : Automatically generated code for karatsuba 58 bit
******************************************************************************/
`ifndef __KS_58_V__
`define __KS_58_V__
//`include "ks29.v"
module ks58(a, b, d);
input wire [57:0] a;
input wire [57:0] b;
output wire [114:0] d;
wire [56:0] m1;
wire [56:0] m2;
wire [56:0] m3;
wire [28:0] ahl;
wire [28:0] bhl;
ks29 ksm1(a[28:0], b[28:0], m2);
ks29 ksm2(a[57:29], b[57:29], m1);
assign ahl[28:0] = a[57:29] ^ a[28:0];
assign bhl[28:0] = b[57:29] ^ b[28:0];
ks29 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08];
assign d[09] = m2[09];
assign d[10] = m2[10];
assign d[11] = m2[11];
assign d[12] = m2[12];
assign d[13] = m2[13];
assign d[14] = m2[14];
assign d[15] = m2[15];
assign d[16] = m2[16];
assign d[17] = m2[17];
assign d[18] = m2[18];
assign d[19] = m2[19];
assign d[20] = m2[20];
assign d[21] = m2[21];
assign d[22] = m2[22];
assign d[23] = m2[23];
assign d[24] = m2[24];
assign d[25] = m2[25];
assign d[26] = m2[26];
assign d[27] = m2[27];
assign d[28] = m2[28];
assign d[29] = m2[29] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[30] = m2[30] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[31] = m2[31] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[32] = m2[32] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[33] = m2[33] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[34] = m2[34] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[35] = m2[35] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[36] = m2[36] ^ m1[07] ^ m2[07] ^ m3[07];
assign d[37] = m2[37] ^ m1[08] ^ m2[08] ^ m3[08];
assign d[38] = m2[38] ^ m1[09] ^ m2[09] ^ m3[09];
assign d[39] = m2[39] ^ m1[10] ^ m2[10] ^ m3[10];
assign d[40] = m2[40] ^ m1[11] ^ m2[11] ^ m3[11];
assign d[41] = m2[41] ^ m1[12] ^ m2[12] ^ m3[12];
assign d[42] = m2[42] ^ m1[13] ^ m2[13] ^ m3[13];
assign d[43] = m2[43] ^ m1[14] ^ m2[14] ^ m3[14];
assign d[44] = m2[44] ^ m1[15] ^ m2[15] ^ m3[15];
assign d[45] = m2[45] ^ m1[16] ^ m2[16] ^ m3[16];
assign d[46] = m2[46] ^ m1[17] ^ m2[17] ^ m3[17];
assign d[47] = m2[47] ^ m1[18] ^ m2[18] ^ m3[18];
assign d[48] = m2[48] ^ m1[19] ^ m2[19] ^ m3[19];
assign d[49] = m2[49] ^ m1[20] ^ m2[20] ^ m3[20];
assign d[50] = m2[50] ^ m1[21] ^ m2[21] ^ m3[21];
assign d[51] = m2[51] ^ m1[22] ^ m2[22] ^ m3[22];
assign d[52] = m2[52] ^ m1[23] ^ m2[23] ^ m3[23];
assign d[53] = m2[53] ^ m1[24] ^ m2[24] ^ m3[24];
assign d[54] = m2[54] ^ m1[25] ^ m2[25] ^ m3[25];
assign d[55] = m2[55] ^ m1[26] ^ m2[26] ^ m3[26];
assign d[56] = m2[56] ^ m1[27] ^ m2[27] ^ m3[27];
assign d[57] = m1[28] ^ m2[28] ^ m3[28];
assign d[58] = m1[29] ^ m2[29] ^ m3[29] ^ m1[00];
assign d[59] = m1[30] ^ m2[30] ^ m3[30] ^ m1[01];
assign d[60] = m1[31] ^ m2[31] ^ m3[31] ^ m1[02];
assign d[61] = m1[32] ^ m2[32] ^ m3[32] ^ m1[03];
assign d[62] = m1[33] ^ m2[33] ^ m3[33] ^ m1[04];
assign d[63] = m1[34] ^ m2[34] ^ m3[34] ^ m1[05];
assign d[64] = m1[35] ^ m2[35] ^ m3[35] ^ m1[06];
assign d[65] = m1[36] ^ m2[36] ^ m3[36] ^ m1[07];
assign d[66] = m1[37] ^ m2[37] ^ m3[37] ^ m1[08];
assign d[67] = m1[38] ^ m2[38] ^ m3[38] ^ m1[09];
assign d[68] = m1[39] ^ m2[39] ^ m3[39] ^ m1[10];
assign d[69] = m1[40] ^ m2[40] ^ m3[40] ^ m1[11];
assign d[70] = m1[41] ^ m2[41] ^ m3[41] ^ m1[12];
assign d[71] = m1[42] ^ m2[42] ^ m3[42] ^ m1[13];
assign d[72] = m1[43] ^ m2[43] ^ m3[43] ^ m1[14];
assign d[73] = m1[44] ^ m2[44] ^ m3[44] ^ m1[15];
assign d[74] = m1[45] ^ m2[45] ^ m3[45] ^ m1[16];
assign d[75] = m1[46] ^ m2[46] ^ m3[46] ^ m1[17];
assign d[76] = m1[47] ^ m2[47] ^ m3[47] ^ m1[18];
assign d[77] = m1[48] ^ m2[48] ^ m3[48] ^ m1[19];
assign d[78] = m1[49] ^ m2[49] ^ m3[49] ^ m1[20];
assign d[79] = m1[50] ^ m2[50] ^ m3[50] ^ m1[21];
assign d[80] = m1[51] ^ m2[51] ^ m3[51] ^ m1[22];
assign d[81] = m1[52] ^ m2[52] ^ m3[52] ^ m1[23];
assign d[82] = m1[53] ^ m2[53] ^ m3[53] ^ m1[24];
assign d[83] = m1[54] ^ m2[54] ^ m3[54] ^ m1[25];
assign d[84] = m1[55] ^ m2[55] ^ m3[55] ^ m1[26];
assign d[85] = m1[56] ^ m2[56] ^ m3[56] ^ m1[27];
assign d[86] = m1[28];
assign d[87] = m1[29];
assign d[88] = m1[30];
assign d[89] = m1[31];
assign d[90] = m1[32];
assign d[91] = m1[33];
assign d[92] = m1[34];
assign d[93] = m1[35];
assign d[94] = m1[36];
assign d[95] = m1[37];
assign d[96] = m1[38];
assign d[97] = m1[39];
assign d[98] = m1[40];
assign d[99] = m1[41];
assign d[100] = m1[42];
assign d[101] = m1[43];
assign d[102] = m1[44];
assign d[103] = m1[45];
assign d[104] = m1[46];
assign d[105] = m1[47];
assign d[106] = m1[48];
assign d[107] = m1[49];
assign d[108] = m1[50];
assign d[109] = m1[51];
assign d[110] = m1[52];
assign d[111] = m1[53];
assign d[112] = m1[54];
assign d[113] = m1[55];
assign d[114] = m1[56];
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int a, b, t; cin >> t; int arr[t]; for (int i = 0; i < t; i++) { cin >> a >> b; arr[i] = a + b; } for (int i = 0; i < t; i++) { cout << arr[i] << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_4_V
`define SKY130_FD_SC_HD__O32A_4_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2111; const int mod = 1e9 + 7; int n; int pri[N], tot; long long a[N], b[N]; struct node { long long k, b; node(long long _k = 0, long long _b = 0) { k = _k; b = _b; } } f[N], g[N]; long long gcd(long long x, long long y) { return y == 0 ? x : gcd(y, x % y); } long long ksm(long long base, long long x) { long long ans = 1; while (x) { if (x & 1) ans = ans * base % mod; base = base * base % mod; x >>= 1; } return ans; } void get(int x) { for (int i = 2; i * i <= x; i++) { if (x % i == 0) { pri[++tot] = i; while (x % i == 0) x /= i; } } if (x > 1) pri[++tot] = x; } void get_g(int id) { for (int i = 1; i <= tot; i++) { g[i].b = g[i].k = 0; while (a[id] % pri[i] == 0) { g[i].b++; a[id] /= pri[i]; } while (b[id] % pri[i] == 0) { g[i].k++; b[id] /= pri[i]; } } } long long ex_gcd(long long A, long long B, long long &x, long long &y) { if (!B) { x = 1; y = 0; return A; } long long xx, yy; long long d = ex_gcd(B, A % B, xx, yy); x = yy; y = xx - A / B * yy; return d; } bool merge() { bool flag = 0; for (int t = 0; t < 3; t++) { for (int i = 1; i <= tot; i++) { long long fk = f[i].k, fb = f[i].b; long long gk = g[i].k, gb = g[i].b; bool fl = 0; if (!fk && !gk) { if (fb != gb) return 0; } else { if (!gk || !fk) { if (!fk) swap(fk, gk), swap(fb, gb), fl = 1; if (fb > gb || (gb - fb) % fk != 0) return 0; long long k = (gb - fb) / fk; if (fl) for (int j = 1; j <= tot; j++) g[j].b += g[j].k * k, g[j].k = 0; else for (int j = 1; j <= tot; j++) f[j].b += f[j].k * k, f[j].k = 0; flag = 1; } } } } if (flag) return 1; int fl = 0; long long A = 0, B = 0, C = 0; for (int i = 1; i <= tot; i++) { if (!f[i].k || !g[i].k) continue; if (!fl) A = f[i].k, B = -g[i].k, C = g[i].b - f[i].b, fl = 1; else if (fl == 1) { long long nA = f[i].k, nB = -g[i].k, nC = g[i].b - f[i].b; long long d = gcd(nA, A); A *= nA / d; B *= nA / d; C *= nA / d; nA *= A / d; nB *= A / d; nC *= A / d; if (B == nB) { if (C != nC) return 0; long long d = gcd(A, gcd(abs(B), abs(C))); A /= d; B /= d; C /= d; continue; } else { if ((C - nC) % (B - nB)) return 0; long long y = (C - nC) / (B - nB); if (y < 0) return 0; if ((C - B * y) % A) return 0; long long x = (C - B * y) / A; if (x < 0) return 0; for (int j = 1; j <= tot; j++) f[j].b += f[j].k * x, f[j].k = 0; for (int j = i + 1; j <= tot; j++) { nA = f[j].k, nB = -g[j].k, nC = g[j].b - f[j].b; if (nA * x + nB * y != nC) return 0; } return 1; } } } long long x = -1, y = -1; long long d = ex_gcd(A, -B, x, y); if (C % d) return 0; y *= -1; long long kx = (-B) / d; long long ky = A / d; x *= C / d, y *= C / d; long long tx = x < 0 ? -(-x + kx - 1) / kx : x / kx; long long ty = y < 0 ? -(-y + ky - 1) / ky : y / ky; x -= min(tx, ty) * kx; y -= min(tx, ty) * ky; for (int i = 1; i <= tot; i++) { f[i].b += f[i].k * x; f[i].k = f[i].k * kx; } return 1; } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i], &b[i]); get(a[i]); get(b[i]); } sort(pri + 1, pri + 1 + tot); tot = unique(pri + 1, pri + 1 + tot) - (pri + 1); for (int i = 1; i <= tot; i++) { while (a[1] % pri[i] == 0) { f[i].b++; a[1] /= pri[i]; } while (b[1] % pri[i] == 0) { f[i].k++; b[1] /= pri[i]; } } for (int i = 2; i <= n; i++) { get_g(i); if (!merge()) { puts( -1 ); return 0; } } int ans = 1; for (int i = 1; i <= tot; i++) { ans = 1LL * ans * ksm(pri[i], f[i].b) % mod; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1000 + 10; int n, flag, a[maxN], i, j, m; int main() { cin >> n; for (i = 2; i <= n; i++) { for (j = 2; j * j <= i; j++) { if (i != j && i % j == 0) flag = 1; } j = i; while (flag == 0 && j <= n) { a[m++] = j; j *= i; } flag = 0; } cout << m << endl; for (int k = 0; k < m; k++) cout << a[k] << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_2_V
`define SKY130_FD_SC_LP__SDFSTP_2_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler, Nick Desaulniers
//
// Create Date: 10:58:44 04/07/2011
// Design Name: data_path
// Module Name: data_path
// Project Name: Data Path for the Pipelined CPU
// Target Devices: Xilinx Spartan-3E
// Tool versions: Xilinx ISE Project Navigator
// Description: This is a pipelined data_path with five stages: IF, ID, EX, M, WB
//
// Dependencies: n/a
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Removed v, c from execute block
// Revision 2.00 - Added clk_n, rst_n to memory module
// Revision 3.00 - Fixed some inputs (clk_n, rst_n) to modules (CRC)
// Revision 4.00 - Temporarily wired stages together, no pipeline; addec cu_branch (CRC)
// Revision 5.00 - Added FFs between stages, untested (CRC)
// Revision 6.00 - Modified cu_branch width, cu_alu_opcode width
// Revision 7.00 - Changed width of cu_branch input, removed m_branch_en_ff (CRC)
// Revision 8.00 - Added assign for id_opcode_out, fixes to pipeline (CRC)
//
//////////////////////////////////////////////////////////////////////////////////
module data_path(
input wire clk,
input wire clk_n,
input wire rst_n,
input wire cu_reg_load,
input wire cu_alu_sel_b,
input wire [10:0] cu_alu_opcode,
input wire cu_dm_wea,
input wire cu_reg_data_loc,
input wire[1:0] cu_branch,
output wire [3:0] id_opcode_out,
output wire [7:0] leds
);
wire [6:0] if_next_addr;
wire [15:0] if_curr_inst;
reg [6:0] if_next_addr_ff;
reg [15:0] if_curr_inst_ff;
wire [3:0] id_opcode;
wire [6:0] id_next_addr;
wire [15:0] id_register1_data;
wire [15:0] id_register2_data;
wire [6:0] id_sign_ext_addr;
wire [2:0] id_dest_reg_addr;
reg [3:0] id_opcode_ff;
reg [6:0] id_next_addr_ff;
reg [15:0] id_register1_data_ff;
reg [15:0] id_register2_data_ff;
reg [6:0] id_sign_ext_addr_ff;
reg [2:0] id_dest_reg_addr_ff;
wire [6:0] ex_sign_ext_next_addr;
wire ex_alu_z;
wire [15:0] ex_alu_result;
wire [15:0] ex_register2_data;
wire [2:0] ex_reg_waddr;
reg [6:0] ex_sign_ext_next_addr_ff;
reg ex_alu_z_ff;
reg [15:0] ex_alu_result_ff;
reg [15:0] ex_register2_data_ff;
reg [2:0] ex_reg_waddr_ff;
wire [15:0] m_alu_result;
wire [15:0] m_dm_dout;
wire [2:0] m_reg_waddr;
wire m_branch_en;
reg [15:0] m_alu_result_ff;
reg [15:0] m_dm_dout_ff;
reg [2:0] m_reg_waddr_ff;
wire [15:0] wb_reg_wdata;
wire [2:0] wb_reg_waddr;
// Control signals through ffs
reg cu_reg_load_ff1;
reg cu_reg_data_loc_ff1;
reg [1:0] cu_branch_ff1;
reg cu_dm_wea_ff1;
reg [10:0] cu_alu_opcode_ff1;
reg cu_alu_sel_b_ff1;
reg cu_reg_load_ff2;
reg cu_reg_data_loc_ff2;
reg [1:0] cu_branch_ff2;
reg cu_dm_wea_ff2;
reg cu_reg_load_ff3;
reg cu_reg_data_loc_ff3;
assign id_opcode_out = id_opcode_ff;
assign leds = 8'hAA;
instruction_fetch i_instruction_fetch(
.clk_n(clk_n),
.rst_n(rst_n),
.m_branch_addr(ex_sign_ext_next_addr_ff),
.m_branch_en(m_branch_en),
.if_next_addr(if_next_addr),
.if_curr_inst(if_curr_inst)
);
instruction_decode i_instruction_decode(
.clk_n(clk_n),
.if_next_addr(if_next_addr_ff),
.if_curr_inst(if_curr_inst_ff),
.wb_reg_wea(wb_reg_wea),
.wb_reg_wdata(wb_reg_wdata),
.wb_reg_waddr(wb_reg_waddr),
.id_opcode(id_opcode),
.id_next_addr(id_next_addr),
.id_register1_data(id_register1_data),
.id_register2_data(id_register2_data),
.id_sign_ext_addr(id_sign_ext_addr),
.id_dest_reg_addr(id_dest_reg_addr)
);
execute i_execute(
.clk_n(clk_n),
.rst_n(rst_n),
.id_next_addr(id_next_addr_ff),
.id_register1_data(id_register1_data_ff),
.id_register2_data(id_register2_data_ff),
.id_sign_ext_addr(id_sign_ext_addr_ff),
.id_dest_reg_addr(id_dest_reg_addr_ff),
.cu_alu_opcode(cu_alu_opcode_ff1),
.cu_alu_sel_b(cu_alu_sel_b_ff1),
.ex_sign_ext_next_addr(ex_sign_ext_next_addr),
.ex_alu_z(ex_alu_z),
.ex_alu_result(ex_alu_result),
.ex_register2_data(ex_register2_data),
.ex_reg_waddr(ex_reg_waddr)
);
memory i_memory(
.clk_n(clk_n),
.rst_n(rst_n),
.ex_alu_result(ex_alu_result_ff),
.ex_register2_data(ex_register2_data_ff),
.ex_reg_waddr(ex_reg_waddr_ff),
.cu_dm_wea(cu_dm_wea_ff2),
.cu_branch(cu_branch_ff2),
.ex_alu_z(ex_alu_z_ff),
.m_alu_result(m_alu_result),
.m_dm_dout(m_dm_dout),
.m_reg_waddr(m_reg_waddr),
.m_branch_en(m_branch_en)
);
write_back i_write_back(
.m_alu_result(m_alu_result_ff),
.m_dm_dout(m_dm_dout_ff),
.m_reg_waddr(m_reg_waddr_ff),
.cu_reg_data_loc(cu_reg_data_loc_ff3),
.cu_reg_load(cu_reg_load_ff3),
.wb_reg_wdata(wb_reg_wdata),
.wb_reg_wea(wb_reg_wea),
.wb_reg_waddr(wb_reg_waddr)
);
// IF -> ID
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
if_next_addr_ff <= 7'b0;
if_curr_inst_ff <= 16'b0;
end else begin
if_next_addr_ff <= if_next_addr;
if_curr_inst_ff <= if_curr_inst;
end
end
// ID -> EX
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
id_opcode_ff <= 4'b0;
id_next_addr_ff <= 7'b0;
id_register1_data_ff <= 16'b0;
id_register2_data_ff <= 16'b0;
id_sign_ext_addr_ff <= 7'b0;
id_dest_reg_addr_ff <= 3'b0;
cu_reg_load_ff1 <= 1'b0;
cu_reg_data_loc_ff1 <= 1'b0;
cu_branch_ff1 <= 2'b0;
cu_dm_wea_ff1 <= 1'b0;
cu_alu_opcode_ff1 <= 11'b0;
cu_alu_sel_b_ff1 <= 1'b0;
end else begin
id_opcode_ff <= id_opcode;
id_next_addr_ff <= id_next_addr;
id_register1_data_ff <= id_register1_data;
id_register2_data_ff <= id_register2_data;
id_sign_ext_addr_ff <= id_sign_ext_addr;
id_dest_reg_addr_ff <= id_dest_reg_addr;
cu_reg_load_ff1 <= cu_reg_load;
cu_reg_data_loc_ff1 <= cu_reg_data_loc;
cu_branch_ff1 <= cu_branch;
cu_dm_wea_ff1 <= cu_dm_wea;
cu_alu_opcode_ff1 <= cu_alu_opcode;
cu_alu_sel_b_ff1 <= cu_alu_sel_b;
end
end
// EX -> M
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ex_sign_ext_next_addr_ff <= 7'b0;
ex_alu_z_ff <= 1'b0;
ex_alu_result_ff <= 16'b0;
ex_register2_data_ff <= 16'b0;
ex_reg_waddr_ff <= 3'b0;
cu_reg_load_ff2 <= 1'b0;
cu_reg_data_loc_ff2 <= 1'b0;
cu_branch_ff2 <= 2'b0;
cu_dm_wea_ff2 <= 1'b0;
end else begin
ex_sign_ext_next_addr_ff <= ex_sign_ext_next_addr;
ex_alu_z_ff <= ex_alu_z;
ex_alu_result_ff <= ex_alu_result;
ex_register2_data_ff <= ex_register2_data;
ex_reg_waddr_ff <= ex_reg_waddr;
cu_reg_load_ff2 <= cu_reg_load_ff1;
cu_reg_data_loc_ff2 <= cu_reg_data_loc_ff1;
cu_branch_ff2 <= cu_branch_ff1;
cu_dm_wea_ff2 <= cu_dm_wea_ff1;
end
end
// M -> WB
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
m_alu_result_ff <= 16'b0;
m_dm_dout_ff <= 16'b0;
m_reg_waddr_ff <= 16'b0;
cu_reg_load_ff3 <= 1'b0;
cu_reg_data_loc_ff3 <= 1'b0;
end else begin
m_alu_result_ff <= m_alu_result;
m_dm_dout_ff <= m_dm_dout;
m_reg_waddr_ff <= m_reg_waddr;
cu_reg_load_ff3 <= cu_reg_load_ff2;
cu_reg_data_loc_ff3 <= cu_reg_data_loc_ff2;
end
end
endmodule
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