text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> long long strange[100001]; int main() { for (int i = 1; i <= 100000; i++) { long long a = i, b = i; while (b) { a *= 10; a += b % 10; b /= 10; } strange[i] = a; } long long k, p; while (scanf( %lld%lld , &k, &p) != EOF) { long long sum = 0; for (int i = 1; i <= k; i++) sum += strange[i]; printf( %lld n , sum % p); } }
|
/*****************************************************************************
* *
* Module: Altera_UP_Clock_Edge *
* Description: *
* This module finds clock edges of one clock at the frquency of *
* another clock. *
* *
*****************************************************************************/
module Altera_UP_Clock_Edge (
// Inputs
clk,
reset,
test_clk,
// Bidirectionals
// Outputs
rising_edge,
falling_edge
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input test_clk;
// Bidirectionals
// Outputs
output rising_edge;
output falling_edge;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire found_edge;
// Internal Registers
reg cur_test_clk;
reg last_test_clk;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
cur_test_clk <= test_clk;
always @(posedge clk)
last_test_clk <= cur_test_clk;
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
assign rising_edge = found_edge & cur_test_clk;
assign falling_edge = found_edge & last_test_clk;
// Internal Assignments
assign found_edge = last_test_clk ^ cur_test_clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O211AI_FUNCTIONAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, w = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) w = -1; for (; isdigit(ch); ch = getchar()) s = (s << 1) + (s << 3) + (ch ^ 48); return s * w; } inline void print(long long x, int op = 10) { if (!x) { putchar( 0 ); if (op) putchar(op); return; } char F[40]; long long tmp = x > 0 ? x : -x; if (x < 0) putchar( - ); int cnt = 0; while (tmp > 0) { F[cnt++] = tmp % 10 + 0 ; tmp /= 10; } while (cnt > 0) putchar(F[--cnt]); if (op) putchar(op); } inline long long gcd(long long x, long long y) { return y ? gcd(y, x % y) : x; } long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans *= a; b >>= 1; a *= a; } return ans; } long long qpow(long long a, long long b, long long mod) { long long ans = 1; while (b) { if (b & 1) (ans *= a) %= mod; b >>= 1; (a *= a) %= mod; } return ans % mod; } const int dir[][2] = {{0, 1}, {1, 0}, {0, -1}, {-1, 0}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; const int MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; const long long INF64 = 0x3f3f3f3f3f3f3f3f; const int N = 1e6 + 7; struct Node { long long val; int id; bool operator<(const Node& opt) const { return val < opt.val; } }; long long n, m; set<int> st; int p[20]; int solve() { n = read(); int cnt = 0; for (int i = 1; i <= n; ++i) p[i] = read(), cnt += p[i] == 0; st.clear(); st.insert(0); for (int i = 1; i <= n; ++i) { set<int> tmp = st; for (auto& it : st) { int x1 = it - p[i]; int x2 = it + p[i]; cnt += x1 == 0; cnt += x2 == 0; tmp.insert(x1), tmp.insert(x2); } st = tmp; } return cnt; } int main() { int T = read(); for (int _ = 1; _ <= T; ++_) { cout << (solve() ? YES : NO ) << n ; } return 0; }
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (win64) Build Wed Nov 12 18:52:34 MST 2014
//Date : Tue Jun 23 14:17:06 2015
//Host : RRNTU-MV01 running 64-bit major release (build 9200)
//Command : generate_target system_wrapper.bd
//Design : system_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Data RAM for Tawas Core
//
module dram
(
input clk,
input [31:0] addr,
input cs,
input wr,
input [3:0] mask,
input [31:0] din,
output [31:0] dout
);
parameter DRAM_DATA_FILE = "dram.hex";
reg [7:0] data_array_w0[(1024 * 16)-1:0];
reg [7:0] data_array_w1[(1024 * 16)-1:0];
reg [7:0] data_array_w2[(1024 * 16)-1:0];
reg [7:0] data_array_w3[(1024 * 16)-1:0];
reg [31:0] data_out;
initial
begin
$readmemh({DRAM_DATA_FILE, ".0"}, data_array_w0);
$readmemh({DRAM_DATA_FILE, ".1"}, data_array_w1);
$readmemh({DRAM_DATA_FILE, ".2"}, data_array_w2);
$readmemh({DRAM_DATA_FILE, ".3"}, data_array_w3);
end
always @ (posedge clk)
if (cs && wr && mask[0])
data_array_w0[addr[15:2]] <= din[7:0];
always @ (posedge clk)
if (cs && wr && mask[1])
data_array_w1[addr[15:2]] <= din[15:8];
always @ (posedge clk)
if (cs && wr && mask[2])
data_array_w2[addr[15:2]] <= din[23:16];
always @ (posedge clk)
if (cs && wr && mask[3])
data_array_w3[addr[15:2]] <= din[31:24];
always @ (posedge clk)
if (cs)
begin
data_out[7:0] <= data_array_w0[addr[15:2]];
data_out[15:8] <= data_array_w1[addr[15:2]];
data_out[23:16] <= data_array_w2[addr[15:2]];
data_out[31:24] <= data_array_w3[addr[15:2]];
end
assign dout = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; char c[600][600]; int check(int x, int y) { if (c[x][y - 1] == * && c[x][y + 1] == * && c[x + 1][y] == * && c[x - 1][y] == * && c[x][y] == * ) return 1; return 0; } int main() { int m, n; cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> c[i][j]; int x = -1, y = -1; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (check(i, j) == 1) { x = i; y = j; } } if (x == -1 || y == -1) { cout << NO << endl; return 0; } for (int i = x - 1; i >= 0; i--) { if (c[i][y] == * ) { c[i][y] = . ; } else break; } for (int i = x + 1; i < n; i++) { if (c[i][y] == * ) { c[i][y] = . ; } else break; } for (int i = y - 1; i >= 0; i--) { if (c[x][i] == * ) { c[x][i] = . ; } else break; } for (int i = y + 1; i < m; i++) { if (c[x][i] == * ) { c[x][i] = . ; } else break; } c[x][y] = . ; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (c[i][j] == * ) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace std; const long long int mod = 1e9 + 7; const long long int MAX = LLONG_MAX; const long long int MIN = LLONG_MIN; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n, k; cin >> n >> k; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; map<long long int, long long int> mp; long long int c = 0; deque<long long int> d; for (long long int i = 0; i < n; i++) { if (c < k) { if (mp[a[i]] == 0) { d.push_front(a[i]); mp[a[i]]++; c++; } else { } } else { long long int x = d.back(); if (mp[a[i]] != 0) { } else { mp[x] = mp[x] - 1; d.pop_back(); d.push_front(a[i]); mp[a[i]]++; } } } cout << d.size() << n ; for (auto i = d.begin(); i != d.end(); i++) { cout << *i << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char d[8][8]; int i, j, sch, k, m; int main() { k = 0; m = 0; for (i = 0; i < 8; i++) { sch = 0; for (j = 0; j < 8; j++) { cin >> d[i][j]; if (d[i][j] == B ) sch++; } if (sch == 8) k++; else if (sch > m) m = sch; } cout << k + m; return 0; }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_trs.v: //
// Brute-force/Transposed-RAM Binary Content Addressasble Memory (BCAM) stage //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module bcam_trs
#( parameter CAMD = 128 , // CAM depth
parameter CAMW = 9 , // CAM/pattern width
parameter BYPS = 1 , // Bypassed? (binary; 0 or 1)
parameter PIPE = 0 , // Pipelined? (binary; 0 or 1)
parameter INOM = 1 , // binary / Initial CAM with no match
parameter BRAM = "M20K") // BRAM type- "M20K":Altera's M20K; "GEN":generic
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CAMD)-1:0] wAddr , // write address / [`log2(CAMD)-1:0]
input [ CAMW -1:0] wPatt , // write pattern / [ CAMW -1:0]
input [ CAMW -1:0] mPatt , // patern to match / [ CAMW -1:0]
output [ CAMD -1:0] match ); // match / one-hot / [ CAMD -1:0]
localparam ADDRW = `log2(CAMD);
///////////////////////////////////////////////////////////////////////////////
// Trace RAM - a single-ported RAM
reg addRmv; // add or remove (inverted) pattern from CAM / control for CAM
wire [CAMW-1:0] rDataRAM; // read data from RAM (should be erased from CAM)
spram #( .MEMD ( CAMD ), // memory depth
.DATAW( CAMW ), // data width
.IZERO( INOM ), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE( "" )) // initialization hex file (don't pass extension), optional
trram ( .clk ( clk ), // clock
.wEnb ( !addRmv ), // write enable for port B
.addr ( wAddr ), // write/read address / [`log2(MEMD)-1:0]
.wData( wPatt ), // write data / [DATAW -1:0]
.rData( rDataRAM )); // read data / [DATAW -1:0]
///////////////////////////////////////////////////////////////////////////////
// Transposed RAM as a CAM
wire [CAMD-1:0] match1Hot ; // pattern one-hot match from CAM
reg wEnbCAM ; // write enable for CAM / control for CAM
wire rmvSameAdd = !addRmv & (wPatt==rDataRAM); // trying to remove same just added pattern
trcam #( .CAMD ( CAMD ), // CAM depth (power of 2)
.CAMW ( CAMW ), // CAM/pattern width / for one stage (<=14)
.INOM ( INOM ), // binary / Initial CAM with no match
.BRAM ( BRAM )) // BRAM type- "M20K":Altera's M20K; "GEN":generic
trcam_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnbCAM & !(rmvSameAdd) ), // write enable
.wrEr ( addRmv ), // add or remove (inverted) pattern from CAM
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( addRmv ? wPatt : rDataRAM ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( match1Hot )); // match / one-hot / [ CAMD -1:0]
///////////////////////////////////////////////////////////////////////////////
// CAM bypassing
// register write address and pattern on wEnb
reg [ADDRW-1:0] wAddrR;
reg [CAMW -1:0] wPattR;
always @(posedge clk, posedge rst)
if (rst) {wAddrR,wPattR} <= {{(ADDRW+CAMW ){1'b0}}};
else if (wEnb) {wAddrR,wPattR} <= { wAddr,wPatt };
// bypass if registered write pattern equals to pattern to match
wire isByp = (wPattR==mPatt);
// second stage bypassing
reg isBypR;
reg [ADDRW-1:0] wAddrRR;
always @(posedge clk, posedge rst)
if (rst) {wAddrRR,isBypR} <= {{(ADDRW +1 ){1'b0}}};
else {wAddrRR,isBypR} <= { wAddrR,isByp };
/////////////// retiming //////////////
//// will increase registers count ////
// onehot registerd write address
reg [CAMD-1:0] wAddr1HotRR ;
//always @(*) begin
// wAddr1HotRR = 0 ;
// wAddr1HotRR[wAddrRR] = 1'b1;
//end
reg [CAMD-1:0] wAddr1HotR ;
always @(*) begin
wAddr1HotR = 0 ;
wAddr1HotR[wAddrR] = 1'b1;
end
always @(posedge clk, posedge rst)
if (rst) wAddr1HotRR <= {CAMD{1'b0}};
else wAddr1HotRR <= wAddr1HotR ;
/////////////// retiming //////////////
// masked onehot match to onehot output
assign match = BYPS ? ( isBypR ? ( wAddr1HotRR | match1Hot)
: (~wAddr1HotRR & match1Hot) )
: match1Hot;
///////////////////////////////////////////////////////////////////////////////
// controller / Mealy FSM
// Inputs : wEnb
// Outputs: addRmv wEnbCAM
reg curStt, nxtStt ;
localparam S0 = 1'b0;
localparam S1 = 1'b1;
// synchronous
always @(posedge clk, posedge rst)
if (rst) curStt <= S0 ;
else curStt <= nxtStt;
// combinatorial
always @(*)
case (curStt)
S0: if (wEnb) {nxtStt,wEnbCAM,addRmv}={S1,2'b11};
else {nxtStt,wEnbCAM,addRmv}={S0,2'b01};
S1: if (wEnb) {nxtStt,wEnbCAM,addRmv}={S0,2'b10};
else {nxtStt,wEnbCAM,addRmv}={S0,2'b10};
endcase
///////////////////////////////////////////////////////////////////////////////
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: mult16.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult16 (
clock,
dataa,
result);
input clock;
input [15:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altsquare altsquare_component (
.clock (clock),
.data (dataa),
.result (sub_wire0),
.aclr (1'b0),
.ena (1'b1));
defparam
altsquare_component.data_width = 16,
altsquare_component.lpm_type = "ALTSQUARE",
altsquare_component.pipeline = 1,
altsquare_component.representation = "SIGNED",
altsquare_component.result_width = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
// Retrieval info: CONNECT: @data 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; vector<int> o, p, e; int n, i, j, x; int a[200000], b[200000]; struct T { int i; } t; bool operator<(T t1, T t2) { if ((t2.i - x - a[b[t2.i]] + 2 * n) % n != (t1.i - x - a[b[t1.i]] + 2 * n) % n) return (t2.i - x - a[b[t2.i]] + 2 * n) % n < (t1.i - x - a[b[t1.i]] + 2 * n) % n; return t1.i < t2.i; } priority_queue<T> qp; set<T> qo; set<T>::iterator it; int main() { scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &x); a[x - 1] = i; } for (i = 0; i < n; i++) { scanf( %d , &b[i]); b[i]--; } x = 0; for (i = 0; i < n; i++) if (a[b[i]] < i) { t.i = i; qp.push(t); } else if (a[b[i]] > i) { t.i = i; qo.insert(t); } else e.push_back(i); for (i = 0; i < n; i++) { x = 1999999999; if (e.size()) printf( 0 n ); else { if (qp.size()) { t = qp.top(); x = min(x, (t.i - i + n) % n - a[b[t.i]]); } if (qo.size()) { it = qo.begin(); j = it->i; x = min(x, a[b[j]] - (j - i + n) % n); } printf( %d n , x); } x = i + 1; for (j = 0; j < e.size(); j++) { if (e[j] != i) { t.i = e[j]; qo.insert(t); } else { t.i = e[j]; qp.push(t); } } e.clear(); while (!qp.empty()) { t = qp.top(); if ((t.i - i - 1 + n) % n == a[b[t.i]]) { e.push_back(t.i); qp.pop(); } else break; } t.i = i; it = qo.find(t); if (it != qo.end()) { qo.erase(t); if (a[b[i]] == n - 1) e.push_back(i); else { t.i = i; qp.push(t); } } } return 0; }
|
#include <bits/stdc++.h> const long long int mod = 1000000007; const long long int AM = 2e6 + 5; using namespace std; long long int powm(long long int a, long long int b, long long int n) { long long int x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y) % n; } y = (y * y) % n; b /= 2; } return x % n; } long long int pow(long long int x, long long int y) { long long int res = 1; while (y > 0) { if (y & 1) res = ((res) * (x)); y = y >> 1; x = ((x) * (x)); } return res; } long long int fact(long long int n) { long long int ans = 1; for (long long int i = 1; i <= n; i++) ans *= i; return ans; } long long int nCr(long long int n, long long int r) { if (r > n - r) r = n - r; long long int ans = 1, i; for (i = 1; i <= r; i++) { ans *= n - r + i; ans /= i; } return ans; } bool isPrime(long long int n) { if (n <= 1) return false; for (long long int i = 2; i < n; i++) if (n % i == 0) return false; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int n; cin >> n; long long int s = sqrt(n), f1, f2; if (s * s >= n) { f1 = s; f2 = s; } else if (s * (s + 1) >= n) { f1 = s; f2 = s + 1; } else { f1 = s + 1; f2 = s + 1; } cout << f1 + f2; }
|
// DEFINES
`define BITS 4 // Bit width of the operands
module bm_stmt_all_mod(clock,
reset_n,
a_in,
b_in,
out1,
out0,
out3,
out4,
out5,
out6,
out7,
out8,
out10,
out9);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
output out1;
output out3;
output [`BITS-1:0] out4;
output out5;
output [`BITS-1:0] out6;
output out7;
output [`BITS-1:0] out8;
output out9;
output [`BITS-1:0] out10;
reg [`BITS-1:0] out0;
reg out1;
reg out3;
reg [`BITS-1:0] out4;
reg out5;
reg [`BITS-1:0] out6;
reg out7;
reg [`BITS-1:0] out8;
reg out9;
reg [`BITS-1:0] out10;
always @(posedge clock)
begin
case (a_in)
4'b0000: out0 <= 4'b1111 ;
4'b0001: out0 <= 4'b1110 ;
4'b0010: out0 <= 4'b1101 ;
4'b0011: out0 <= 4'b1100 ;
4'b0100: out0 <= 4'b1011 ;
4'b0101: out0 <= 4'b1010 ;
4'b0110: out0 <= 4'b1001 ;
4'b0111: out0 <= 4'b1000 ;
4'b1000: out0 <= 4'b0111 ;
4'b1001: out0 <= 4'b0110 ;
4'b1010: out0 <= 4'b0101 ;
4'b1011: out0 <= 4'b0100 ;
4'b1100: out0 <= 4'b0011 ;
4'b1101: out0 <= 4'b0010 ;
4'b1110: out0 <= 4'b0001 ;
4'b1111: out0 <= 4'b0000 ;
default: out0 <= 4'b0000 ;
endcase
end
always @(posedge clock)
begin
case (b_in)
1'b0: out1 <= 1'b1 ;
1'b1: out1 <= 1'b0 ;
default: out1 <= 1'b0 ;
endcase
end
always @(posedge clock)
begin
case (b_in)
1'b0:
begin
out3 <= 1'b1 ;
out4 <= 4'b0001 ;
end
1'b1:
begin
out3 <= 1'b0 ;
out4 <= 4'b0000 ;
end
default: out3 <= 1'b0 ;
endcase
end
always @(posedge clock)
begin
if (b_in == 1'b0)
begin
out5 <= 1'b1 ;
out6 <= 4'b0001 ;
end
else
begin
out5 <= 1'b0 ;
out6 <= 4'b0000 ;
end
end
always @(posedge clock)
begin
if (b_in == 1'b0)
begin
out7 <= 1'b1 ;
out8 <= 4'b0001 ;
end
else if (a_in == 4'b0000)
begin
out7 <= 1'b0 ;
out8 <= 4'b0100 ;
end
else
begin
out7 <= 1'b1 ;
out8 <= 4'b0000 ;
end
end
always @(posedge clock)
begin
out9 <= 1'b1;
out10 <= 4'b0000;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long neutral = 0; class SegmentTree { vector<long long> a; int n; public: SegmentTree(long long* st, long long* en) { int sz = int(en - st); for (n = 1; n < sz; n <<= 1) ; a.assign(n << 1, neutral); for (int i = 0; i < sz; i++) a[i + n] = st[i]; for (int i = n + sz - 1; i > 1; i--) a[i >> 1] = ((a[i >> 1]) | (a[i])); } void update(int i, long long x) { a[i += n] = x; for (i >>= 1; i; i >>= 1) a[i] = ((a[i << 1]) | (a[1 + (i << 1)])); } long long query(int l, int r) { long long ans = neutral; for (l += n, r += n + 1; l < r; l >>= 1, r >>= 1) { if (l & 1) ans = ((ans) | (a[l++])); if (r & 1) ans = ((ans) | (a[--r])); } return ans; } }; int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); int n, q, m; string s; cin >> s; n = (int)(s).size(); long long v[n]; for (int i = 0; i < (n); ++i) { v[i] = 1LL << (s[i] - a ); } cin >> q; SegmentTree st(v, v + n); while (q--) { int t; cin >> t; if (t == 2) { int a, b; cin >> a >> b; long long res = st.query(a - 1, b - 1), c = 0; while (res > 0) c++, res -= (res & -res); cout << c << endl; } else { int a; char c; cin >> a >> c; int b = c - a ; st.update(a - 1, 1LL << b); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFBBN_PP_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_PP_BLACKBOX_V
|
module daala_idct4_stream_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXIS
parameter integer C_S00_AXIS_TDATA_WIDTH = 64,
// Parameters of Axi Master Bus Interface M00_AXIS
parameter integer C_M00_AXIS_TDATA_WIDTH = 64,
parameter integer C_M00_AXIS_START_COUNT = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXIS
input wire axis_aclk,
input wire axis_aresetn,
output wire s00_axis_tready,
input wire [C_S00_AXIS_TDATA_WIDTH-1 : 0] s00_axis_tdata,
input wire s00_axis_tlast,
input wire s00_axis_tvalid,
// Ports of Axi Master Bus Interface M00_AXIS
output wire m00_axis_tvalid,
output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
output wire m00_axis_tlast,
input wire m00_axis_tready
);
reg signed [31:0] t0_0;
reg signed [31:0] t1_0;
reg signed [31:0] t2_0;
reg signed [31:0] t3_0;
always @(*)
begin
t0_0 = $signed(s00_axis_tdata[15:0]);
t1_0 = $signed(s00_axis_tdata[31:16]);
t2_0 = $signed(s00_axis_tdata[47:32]);
t3_0 = $signed(s00_axis_tdata[63:48]);
end
reg tlast_1;
reg tvalid_1;
reg signed [31:0] i1_1;
reg signed [31:0] t0_1;
reg signed [31:0] t1_1;
reg signed [31:0] t2_1;
reg signed [31:0] t3_1;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_1 <= 0;
tvalid_1 <= 0;
end
else if (m00_axis_tready)
begin
t0_1 <= t0_0;
t1_1 <= t1_0;
t2_1 <= t0_0 - t2_0;
t3_1 <= t3_0;
i1_1 <= t1_0*16'sd18293;
tvalid_1 <= s00_axis_tvalid;
tlast_1 <= s00_axis_tlast;
end
end
reg tlast_2;
reg tvalid_2;
reg signed [31:0] t0_2;
reg signed [31:0] t1_2;
reg signed [31:0] t2_2;
reg signed [31:0] t3_2;
reg signed [31:0] t2h_2;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_2 <= 0;
tvalid_2 <= 0;
end
else if (m00_axis_tready)
begin
t2h_2 <= t2_1 / 16'sd2;
t0_2 <= t0_1;
t1_2 <= t1_1;
t2_2 <= t2_1;
t3_2 <= t3_1 + ((i1_1+16'sd8192)>>>14);
tvalid_2 <= tvalid_1;
tlast_2 <= tlast_1;
end
end
reg tlast_3;
reg tvalid_3;
reg signed [31:0] t0_3;
reg signed [31:0] t1_3;
reg signed [31:0] t2_3;
reg signed [31:0] t3_3;
reg signed [31:0] t2h_3;
reg signed [31:0] i1_3;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_3 <= 0;
tvalid_3 <= 0;
end
else if (m00_axis_tready)
begin
t2h_3 <= t2h_2;
t0_3 <= t0_2;
t1_3 <= t1_2;
t2_3 <= t2_2;
t3_3 <= t3_2;
i1_3 <= t3_2*16'sd21407;
tvalid_3 <= tvalid_2;
tlast_3 <= tlast_2;
end
end
reg tlast_4;
reg tvalid_4;
reg signed [31:0] t0_4;
reg signed [31:0] t1_4;
reg signed [31:0] t2_4;
reg signed [31:0] t3_4;
reg signed [31:0] t2h_4;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_4 <= 0;
tvalid_4 <= 0;
end
else if (m00_axis_tready)
begin
t2h_4 <= t2h_3;
t0_4 <= t0_3;
t2_4 <= t2_3;
t3_4 <= t3_3;
t1_4 <= t1_3 - ((i1_3+16'sd16384)>>>15);
tvalid_4 <= tvalid_3;
tlast_4 <= tlast_3;
end
end
reg tlast_5;
reg tvalid_5;
reg signed [31:0] t0_5;
reg signed [31:0] t1_5;
reg signed [31:0] t2_5;
reg signed [31:0] t3_5;
reg signed [31:0] t2h_5;
reg signed [31:0] i1_5;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_5 <= 0;
tvalid_5 <= 0;
end
else if (m00_axis_tready)
begin
t2h_5 <= t2h_4;
t0_5 <= t0_4;
t1_5 <= t1_4;
t2_5 <= t2_4;
t3_5 <= t3_4;
i1_5 <= t1_4*16'sd23013;
tvalid_5 <= tvalid_4;
tlast_5 <= tlast_4;
end
end
reg tlast_6;
reg tvalid_6;
reg signed [31:0] t0_6;
reg signed [31:0] t1_6;
reg signed [31:0] t2_6;
reg signed [31:0] t3_6;
reg signed [31:0] t2h_6;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_6 <= 0;
tvalid_6 <= 0;
end
else if (m00_axis_tready)
begin
t2h_6 <= t2h_5;
t0_6 <= t0_5;
t1_6 <= t1_5;
t2_6 <= t2_5;
t3_6 <= t3_5 + ((i1_5+16'sd16384)>>>15);
tvalid_6 <= tvalid_5;
tlast_6 <= tlast_5;
end
end
reg tlast_7;
reg tvalid_7;
reg signed [31:0] t0_7; // intermediate
reg signed [15:0] x0_7;
reg signed [31:0] t1_7; // intermediate
reg signed [15:0] x1_7;
reg signed [15:0] x2_7;
reg signed [15:0] x3_7;
always @(posedge axis_aclk)
begin
if (axis_aresetn == 1'b0)
begin
tlast_7 <= 0;
tvalid_7 <= 0;
end
else if (m00_axis_tready)
begin
t0_7 = t0_6 - (t2h_6 - (t3_6 / 16'sd2));
x0_7 <= t0_7;
t1_7 = t2h_6 - t1_6;
x1_7 <= t2_6 - t1_7;
x2_7 <= t1_7;
x3_7 <= t0_7 - t3_6;
tvalid_7 <= tvalid_6;
tlast_7 <= tlast_6;
end
end
assign s00_axis_tready = m00_axis_tready;
assign m00_axis_tlast = tlast_7;
assign m00_axis_tvalid = tvalid_7;
assign m00_axis_tdata = {x3_7,x2_7,x1_7,x0_7};
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_find_segment_stn1 (
ph_seg_p_1_1_1_V_read,
th_seg_p_1_1_0_V_read,
th_seg_p_1_1_1_V_read,
cpat_seg_p_1_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_1_1_1_V_read;
input [6:0] th_seg_p_1_1_0_V_read;
input [6:0] th_seg_p_1_1_1_V_read;
input [3:0] cpat_seg_p_1_1_1_V_read;
output [11:0] ap_return_0;
output [3:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
assign ap_return_0 = ph_seg_p_1_1_1_V_read;
assign ap_return_1 = cpat_seg_p_1_1_1_V_read;
assign ap_return_2 = th_seg_p_1_1_0_V_read;
assign ap_return_3 = th_seg_p_1_1_1_V_read;
endmodule //sp_find_segment_stn1
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM_ram_bank.v when simulating
// the core, RAM_ram_bank. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM_ram_bank(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [3 : 0] addra;
input [3 : 0] dina;
output [3 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(4),
.C_ADDRB_WIDTH(4),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16),
.C_READ_DEPTH_B(16),
.C_READ_WIDTH_A(4),
.C_READ_WIDTH_B(4),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16),
.C_WRITE_DEPTH_B(16),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(4),
.C_WRITE_WIDTH_B(4),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int dp[2][4004]; struct node { int st; int cost; } save[4004]; int n, k; void checkmin(int &a, int b) { if (a == -1 || a > b) a = b; } int main() { int i, j; int ans; while (~scanf( %d%d , &n, &k)) { memset(dp, -1, sizeof(dp)); for (i = 1; i <= n; i++) { scanf( %d%d , &save[i].st, &save[i].cost); save[i].cost; } dp[0][0] = 1; save[i].st = 86400 + 1; ans = save[1].st - 1; for (i = 1; i <= n; i++) for (j = 0; j <= k && j <= i; j++) { if (j == 0) { if (dp[(i - 1) & 1][0] != -1) { if (save[i].st > dp[(i - 1) & 1][0]) dp[i & 1][0] = save[i].st + save[i].cost; else dp[i & 1][0] = dp[(i - 1) & 1][0] + save[i].cost; } if (dp[i & 1][0] != -1) ans = max(ans, save[i + 1].st - dp[i & 1][0]); } else { if (dp[(i - 1) & 1][j - 1] != -1) dp[i & 1][j] = dp[(i - 1) & 1][j - 1]; if (dp[(i - 1) & 1][j] != -1) { if (save[i].st > dp[(i - 1) & 1][j]) checkmin(dp[i & 1][j], save[i].st + save[i].cost); else checkmin(dp[i & 1][j], dp[(i - 1) & 1][j] + save[i].cost); } if (dp[i & 1][j] != -1) ans = max(ans, save[i + 1].st - dp[i & 1][j]); } } printf( %d n , ans); } }
|
//-- //////////////////////////////////////////////////////////////////////////////
//-- /// Copyright (c) 2013, Jahanzeb Ahmad
//-- /// All rights reserved.
//-- ///
//-- /// Redistribution and use in source and binary forms, with or without modification,
//-- /// are permitted provided that the following conditions are met:
//-- ///
//-- /// * Redistributions of source code must retain the above copyright notice,
//-- /// this list of conditions and the following disclaimer.
//-- /// * Redistributions in binary form must reproduce the above copyright notice,
//-- /// this list of conditions and the following disclaimer in the documentation and/or
//-- /// other materials provided with the distribution.
//-- ///
//-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
//-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
//-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
//-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
//-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
//-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
//-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
//-- /// POSSIBILITY OF SUCH DAMAGE.
//-- ///
//-- ///
//-- /// * http://opensource.org/licenses/MIT
//-- /// * http://copyfree.org/licenses/mit/license.txt
//-- ///
//-- //////////////////////////////////////////////////////////////////////////////
module HeaderRam(d, waddr, raddr, we, clk, q);
output [7:0] q;
input [7:0] d;
input[9:0] raddr;
input[9:0] waddr;
input clk, we;
reg [9:0] read_addr;
reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;
initial $readmemh("header.hex", mem);
assign q = mem[read_addr];
always @(posedge clk) begin
if (we)
mem[waddr] <= d;
read_addr <= raddr;
end
endmodule
|
//% @file data_sampler_fifo.v
//% @brief Take a snippet of data into fifo and interface to fifo readout.
//% @author Yuan Mei
//%
`timescale 1ns / 1ps
module data_sampler_fifo
#(
parameter DIN_WIDTH = 512,
parameter DOUT_WIDTH = 32
)
(
input RESET,
input CLK,
input TRIG,
input [DIN_WIDTH-1:0] DIN,
input DIN_VALID,
input DIN_CLK,
output [DOUT_WIDTH-1:0] DOUT,
output DOUT_EMPTY,
input DOUT_RDEN
);
localparam FIFO_REDUCTION_RATIO = DIN_WIDTH / DOUT_WIDTH;
reg trig_prev, trig_prev1, trig_prev2, trig_synced, busy;
reg [3:0] cnt, cnt1;
reg [27:0] cnt2;
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
trig_prev <= 1;
trig_prev1 <= 1;
trig_prev2 <= 1;
trig_synced <= 0;
busy <= 0;
cnt <= 0;
cnt1 <= 0;
cnt2 <= 0;
end
else begin
cnt2 <= cnt2 + 1; // a timer for self-trigger if external TRIG doesn't arrive.
trig_prev <= TRIG | cnt2[27];
trig_prev1 <= trig_prev;
trig_prev2 <= trig_prev1;
trig_synced <= 0;
if ((trig_prev2 == 0) && (trig_prev1 == 1)) begin // catch rising edge of TRIG
cnt1 <= 3;
end
if (cnt1 > 0) begin // make sure trig_synced is 3-CLK wide
trig_synced <= 1;
cnt1 <= cnt1 - 1;
end
if (!busy) begin
if (cnt < 15) begin // make sure reset and trig are separate
cnt <= cnt + 1;
trig_synced <= 0;
end
end
else begin
trig_synced <= 0;
end
if (trig_synced && cnt1 == 0) begin
busy <= 1; // hold busy when triggered, reset clears.
end
end
end
// write into fifo
wire [DIN_WIDTH-1:0] fifo_dout;
wire fifo_rden;
wire fifo_empty, fifo_full;
fifo512x fifo512x_inst // FWFT fifo
(
.rst(trig_synced | RESET),
.wr_clk(DIN_CLK),
.rd_clk(CLK),
.din(DIN),
.wr_en(DIN_VALID),
.rd_en(fifo_rden),
.dout(fifo_dout),
.full(fifo_full),
.empty(fifo_empty)
);
fifo_rdwidth_reducer
#(
.RDWIDTH(32),
.RDRATIO(FIFO_REDUCTION_RATIO),
.SHIFTORDER(1) // 1: MSB first, 0: LSB first
)
fifo_rdwidth_reducer_inst
(
.RESET(~busy | RESET),
.CLK(CLK),
// input data interface
.DIN(fifo_dout),
.VALID(~fifo_empty),
.RDREQ(fifo_rden),
// output
.DOUT(DOUT),
.EMPTY(DOUT_EMPTY),
.RD_EN(DOUT_RDEN)
);
endmodule // data_sampler_fifo
|
#include <bits/stdc++.h> using namespace std; const int dy[] = {-1, 0, 1, 0}, dx[] = {0, 1, 0, -1}; const double EPS = 1e-8; const double PI = acos(-1.0); int popcount(int n) { return __builtin_popcount(n); } int popcount(long long n) { return __builtin_popcountll(n); } template <class T> int SIZE(T a) { return a.size(); } template <class T> string IntToString(T num) { string res; stringstream ss; ss << num; return ss.str(); } template <class T> T StringToInt(string str) { T res = 0; for (int i = 0; i < SIZE(str); i++) res = (res * 10 + str[i] - 0 ); return res; } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> void PrintSeq(T &a, int sz) { for (int i = 0; i < sz; i++) { cout << a[i]; if (sz == i + 1) cout << endl; else cout << ; } } long long getTen(int a) { return (a <= 0) ? 1 : (getTen(a - 1) * 10); } bool EQ(double a, double b) { return abs(a - b) < EPS; } void fastStream() { cin.tie(0); std::ios_base::sync_with_stdio(0); } vector<string> split(string str, char del) { vector<string> res; for (int i = 0, s = 0; i < SIZE(str); i++) { if (str[i] == del) { if (i - s != 0) res.push_back(str.substr(s, i - s)); s = i + 1; } else if (i == SIZE(str) - 1) { res.push_back(str.substr(s)); } } return res; } int N; int as[500001]; int valToPos[500010]; int posToVal[500010]; const int MAX_N = 5000100; class BIT { private: long long bit[MAX_N]; int n; public: BIT(int sz) { n = sz; for (int i = 0; i <= n; i++) bit[i] = 0; } long long sum(int i) { long long s = 0; while (i > 0) { s += bit[i]; i -= i & -i; } return s; } long long rangeSum(int from, int to) { long long res = 0; res = sum(to) - sum(from - 1); return res; } void add(int i, long long x) { while (i <= n) { bit[i] += x; i += i & -i; } } void insert(int i, long long x) { add(i, -(sum(i) - sum(i - 1)) + x); } }; BIT bit(1000000); int main() { cin >> N; for (int i = 0; i < N; i++) { cin >> as[i]; posToVal[i] = as[i]; valToPos[as[i]] = i; } for (int i = 0; i < N; i++) { if (as[i] == 1) bit.add(1, 0); else { int pos1 = i; int pos2 = valToPos[as[i] - 1]; if (pos2 > pos1) { bit.add(as[i], 1); } } } int Q; cin >> Q; for (int i = 0; i < Q; i++) { int p, x, y; cin >> p >> x >> y; if (p == 1) { cout << bit.rangeSum(x, y) + 1 - bit.rangeSum(x, x) << endl; } else { int posx = x - 1; int posy = y - 1; x = posToVal[posx]; y = posToVal[posy]; valToPos[x] = posy; valToPos[y] = posx; posToVal[posx] = y; posToVal[posy] = x; int ary[6] = {x, x - 1, x + 1, y, y - 1, y + 1}; for (int j = 0; j < 6; j++) { int num = ary[j]; if (num == 0) continue; else if (num == 1) continue; else { int pos1 = valToPos[num]; int pos2 = valToPos[num - 1]; if (pos2 > pos1) bit.insert(num, 1); else bit.insert(num, 0); } } } } return 0; }
|
#include <bits/stdc++.h> int main() { char name[100], winner[100]; int sh, uh, a, b, v, c, d, e; int n, i; int sum; int total = sum; scanf( %d , &n); scanf( %s %d %d %d %d %d %d %d , name, &sh, &uh, &a, &b, &c, &d, &e); sum = sh * 100 - uh * 50 + a + b + c + d + e; total = sum; strcpy(winner, name); for (i = 0; i < n - 1; i++) { scanf( %s %d %d %d %d %d %d %d , name, &sh, &uh, &a, &b, &c, &d, &e); sum = sh * 100 - uh * 50 + a + b + c + d + e; if (sum > total) { total = sum; strcpy(winner, name); } } printf( %s , winner); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; const int INF = 0x3f3f3f3f, N = 2000005, M = 2000005, MOD = 1e9 + 7; int sgn(double x) { return x < -eps ? -1 : (x < eps ? 0 : 1); } int Rand(int x) { return rand() * rand() % x + 1; } vector<int> G[N]; int dep[N]; double ans = 0; void dfs(int x, int _fa, int _dep) { dep[x] = _dep; ans += 1. / dep[x]; for (auto v : G[x]) if (v != _fa) { dfs(v, x, _dep + 1); } } int Solve() { int n; cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; G[u].push_back(v), G[v].push_back(u); } dfs(1, 0, 1); cout << fixed << setprecision(12) << ans << endl; return 0; } void Pre() {} int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); Pre(); while (Solve()) ; return 0; }
|
//----------------------------------------------------------------------------
//-- Prueba de tranmision 2. Se transmite el caracter "A" cada 100ms
//------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//--
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 9600, 19200, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
`include "divider.vh"
//--- Modulo que envia un caracter cuando load esta a 1
//--- La salida tx ESTA REGISTRADA
module fsmtx2 (input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
output reg tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Caracter a enviar
parameter CAR = "A";
//- Tiempo de envio
parameter DELAY = `T_100ms;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
wire start;
//-- Señal de start registrada
reg start_r;
//-- Reloj para la transmision
wire clk_baud;
//-- Reset
reg rstn = 0;
//-- Bitcounter
reg [3:0] bitc;
//--------- Microordenes
wire load; //-- Carga del registro de desplazamiento. Puesta a 0 del
//-- contador de bits
wire baud_en; //-- Habilitar el generador de baudios para la transmision
//-------------------------------------
//-- RUTA DE DATOS
//-------------------------------------
//-- Registrar la entrada start
//-- (para cumplir con las reglas de diseño sincrono)
always @(posedge clk)
start_r <= start;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando load_r es 0, se carga la trama
//-- Cuando load_r es 1 y el reloj de baudios esta a 1 se desplaza hacia
//-- la derecha, enviando el siguiente bit
//-- Se introducen '1's por la izquierda
always @(posedge clk)
//-- Reset
if (rstn == 0)
shifter <= 10'b11_1111_1111;
//-- Modo carga
else if (load == 1)
shifter <= {CAR,2'b01};
//-- Modo desplazamiento
else if (load == 0 && clk_baud == 1)
shifter <= {1'b1, shifter[9:1]};
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (load_r == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
//-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono
//-- y hay que evitar que salgan pulsos espureos (glitches)
always @(posedge clk)
tx <= shifter[0];
//-- Divisor para obtener el reloj de transmision
baudgen #(BAUD)
BAUD0 (
.clk(clk),
.clk_ena(baud_en),
.clk_out(clk_baud)
);
//---------------------------
//-- Temporizador
//---------------------------
dividerp1 #(.M(DELAY))
DIV0 ( .clk(clk),
.clk_out(start)
);
//------------------------------
//-- CONTROLADOR
//------------------------------
//-- Estados del automata finito del controlador
localparam IDLE = 0;
localparam START = 1;
localparam TRANS = 2;
//-- Estados del autómata del controlador
reg [1:0] state;
//-- Transiciones entre los estados
always @(posedge clk)
//-- Reset del automata. Al estado inicial
if (rstn == 0)
state <= IDLE;
else
//-- Transiciones a los siguientes estados
case (state)
//-- Estado de reposo. Se sale cuando la señal
//-- de start se pone a 1
IDLE:
if (start_r == 1)
state <= START;
else
state <= IDLE;
//-- Estado de comienzo. Prepararse para empezar
//-- a transmitir. Duracion: 1 ciclo de reloj
START:
state <= TRANS;
//-- Transmitiendo. Se esta en este estado hasta
//-- que se hayan transmitido todos los bits pendientes
TRANS:
if (bitc == 11)
state <= IDLE;
else
state <= TRANS;
//-- Por defecto. NO USADO. Puesto para
//-- cubrir todos los casos y que no se generen latches
default:
state <= IDLE;
endcase
//-- Generacion de las microordenes
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
//-- Inicializador
always @(posedge clk)
rstn <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[100001]; vector<vector<pair<int, int>>> o[6], ans; void relax(vector<int>& m) { o[m.size()].push_back({}); for (size_t i = 0; i < m.size(); i++) o[m.size()].back().push_back({m[i], m[(i + 1) % m.size()]}); m.resize(1); } void gao(int x, int y) { if (!y) ans.insert(ans.end(), o[x].begin(), o[x].end()); while (o[x].size() > (x == y) && o[y].size()) { ans.push_back(o[x].back()); o[x].pop_back(); ans.back().insert(ans.back().end(), o[y].back().begin(), o[y].back().end()); o[y].pop_back(); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) if (a[i] != i) { vector<int> u = {i}, m = {i}; while (a[u.back()] != i) u.push_back(a[u.back()]); for (size_t c = 1; c < u.size(); c++) { if (m.size() == 5) relax(m); m.push_back(a[u[c]] = u[c]); } relax(m); } gao(5, 0); gao(4, 0); gao(2, 3); while (o[3].size() >= 2) { auto u = o[3].back(); o[3].pop_back(); o[2].push_back({{u[0].first, u[1].first}, {u[1].first, u[0].first}}); o[2].push_back({{u[1].first, u[2].first}, {u[2].first, u[1].first}}); gao(2, 3); } gao(2, 2); gao(3, 0); gao(2, 0); printf( %d n , ans.size()); for (auto& c : ans) { printf( %d n , c.size()); for (auto x : c) printf( %d , x.first); puts( ); for (auto x : c) printf( %d , x.second); puts( ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, k, p, s; cin >> n; int a[5][5]; for (i = 1; i <= 4; i++) { for (j = 1; j <= 4; j++) { cin >> a[i][j]; } } s = 0; for (i = 1; i <= 4; i++) { k = min(a[i][1], a[i][2]); p = min(a[i][3], a[i][4]); if (k + p <= n) { cout << i << << k << << n - k << endl; s++; i = n; } } if (s == 0) cout << -1 << endl; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM.v when simulating
// the core, BRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [6 : 0] addra;
input [31 : 0] dina;
input clkb;
input [6 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(7),
.C_ADDRB_WIDTH(7),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[3000], b[3000]; map<long long, pair<long long, long long> > mymap; pair<long long, long long> p1, p2; int main() { std::ios::sync_with_stdio(false); long long n, m, sa = 0, sb = 0; p1.first = p1.second = p2.first = p2.second = -1; mymap.clear(); cin >> n; for (long long i = (long long)(1); i <= (long long)(n); i++) { cin >> a[i]; sa += a[i]; } cin >> m; for (long long i = (long long)(1); i <= (long long)(m); i++) { cin >> b[i]; sb += b[i]; } long long curdiff = abs(sa - sb); for (long long i = (long long)(1); i <= (long long)(n); i++) { for (long long j = (long long)(1); j <= (long long)(m); j++) { long long tmpsa, tmpsb; tmpsa = sa - a[i] + b[j]; tmpsb = sb + a[i] - b[j]; if (abs(tmpsa - tmpsb) < curdiff) { curdiff = abs(tmpsa - tmpsb); p1.first = i; p1.second = j; } } } for (long long i = (long long)(1); i <= (long long)(n - 1); i++) { for (long long j = (long long)(i + 1); j <= (long long)(n); j++) { long long val = a[i] + a[j]; val = val * 2ll; mymap[val] = make_pair(i, j); } } map<long long, pair<long long, long long> >::iterator it; for (long long i = (long long)(1); i <= (long long)(m - 1); i++) { for (long long j = (long long)(i + 1); j <= (long long)(m); j++) { long long val = sa - sb + 2 * (b[i] + b[j]); it = mymap.lower_bound(val); if (it != mymap.begin()) it--; if (it == mymap.end()) continue; long long temp = val; temp = abs(val - it->first); if (temp < curdiff) { curdiff = temp; p1.first = (it->second).first; p1.second = i; p2.first = (it->second).second; p2.second = j; } it++; if (it != mymap.end()) { temp = abs(val - it->first); if (temp < curdiff) { curdiff = temp; p1.first = (it->second).first; p1.second = i; p2.first = (it->second).second; p2.second = j; } } } } cout << curdiff << endl; if (p2.first != -1) { cout << 2 << endl; cout << p1.first << << p1.second << endl; cout << p2.first << << p2.second << endl; } else if (p1.first != -1) { cout << 1 << endl; cout << p1.first << << p1.second << endl; } else { cout << 0 << endl; } return 0; }
|
//==================================================================================================
// Filename : tb_CORDIC_Arch3.v
// Created On : 2016-10-03 23:39:40
// Last Modified : 2016-10-28 20:53:04
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-03 23:33:09
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch3 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
//reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
wire zero_flag;
wire busy;
`ifdef SINGLE
CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 inst_CORDIC_Arch3 (
`endif
`ifdef DOUBLE
CORDIC_Arch3_W64_EW11_SW52_SWR55_EWR6 inst_CORDIC_Arch3 (
`endif
.clk (clk),
.rst (rst),
.beg_fsm_cordic (beg_fsm_cordic),
.ack_cordic (ack_cordic),
.operation (operation),
.data_in (data_in),
.shift_region_flag (shift_region_flag),
.ready_cordic (ready_cordic),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.busy (busy),
.data_output (data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 0;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
`ifdef SINGLE
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
`endif
`ifdef DOUBLE
$readmemh("CORDIC64_input_angles_hex.txt", Array_IN);
`endif
end
// clock
initial forever #5 clk = ~clk;
always @(negedge clk) begin
//#(PERIOD/3);
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(negedge clk) begin
// #(PERIOD/3);
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void init() { cin.tie(0); cin.sync_with_stdio(0); } int main() { init(); int n, z; cin >> n >> z; for (int i = 0; i < z; i++) { (n % 10 == 0) ? n /= 10 : n -= 1; } cout << n << endl; }
|
#include <bits/stdc++.h> using lli = long long int; using li = long int; using namespace std; const lli MOD{1000000007}; const lli INF{(false ? (INT_MAX - 1) / 2 : (lli)1e18 + 5)}; const lli N{200005}; int main() { cout << setprecision(15); cin.tie(nullptr)->sync_with_stdio(false); li T{1}; cin >> T; while (T--) { lli n{}, x{}, y{}; cin >> n >> x >> y; lli z{x + y - 1}; lli done{n - z}; if (done > 0) cout << 1 << ; else cout << min(2 - done, n) << ; done = max((lli)0, done); cout << n - done << n ; if (z <= n) done -= n - z + 1; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF64 = 1e18 + 1337; const int INF32 = 1e9 + 228; const int MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, s; cin >> n >> s; vector<long long> a(n); long long sum = 0; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } if (sum < s) { cout << -1; return 0; } sort(a.begin(), a.end(), greater<int>()); for (int i = 0; i < n - 1; i++) s -= (a[i] - a[n - 1]); while (s > 0 && a[n - 1] > 0) { s -= n; a[n - 1]--; } cout << a[n - 1]; return 0; }
|
#include <bits/stdc++.h> using std::max; const int N = 3e5 + 5; template <typename T> void read(T &x) { bool neg = false; unsigned char c = getchar(); for (; (c ^ 48) > 9; c = getchar()) if (c == - ) neg = true; for (x = 0; (c ^ 48) < 10; c = getchar()) x = (x << 3) + (x << 1) + (c ^ 48); if (neg) x = -x; } struct line { int next, to, w; } e[2 * N]; int n, q, hd[N], cnt, a[N], b[N], fa[N], dep[N], siz[N], hc[N], top[N]; long long s[N], f[N], g[N], h[N], c[N], ff[N]; void adline(int u, int v, int w) { e[cnt].to = v; e[cnt].w = w; e[cnt].next = hd[u]; hd[u] = cnt++; } void dfs1(int u) { hc[u] = -1; s[u] = s[fa[u]] + a[u] - b[u]; for (int i = hd[u]; ~i; i = e[i].next) { int v = e[i].to; if (v == fa[u]) continue; fa[v] = u; b[v] = e[i].w; dep[v] = dep[u] + 1; dfs1(v); siz[u] += siz[v]; if (!~hc[u] || siz[v] > siz[hc[u]]) hc[u] = v; f[u] += max(0ll, f[v] + a[v] - 2 * b[v]); } ++siz[u]; } void dfs2(int u) { long long sum = (ff[u] = f[u]) + g[u] + a[u]; h[u] = max(h[u], 0ll); if (~hc[u]) { int v = hc[u]; top[v] = top[u]; g[v] = max(0ll, sum - 2 * b[v] - max(0ll, h[v] = f[v] + a[v] - 2 * b[v])); dfs2(v); } for (int i = hd[u]; ~i; i = e[i].next) { int v = e[i].to; if (v == fa[u] || v == hc[u]) continue; g[v] = max(0ll, sum - 2 * b[v] - max(0ll, h[v] = f[v] + a[v] - 2 * b[v])); dfs2(top[v] = v); } } void dfs3(int u) { for (int i = hd[u]; ~i; i = e[i].next) { int v = e[i].to; if (v == fa[u]) continue; f[v] += f[u]; h[v] += h[u]; dfs3(v); } } int lca(int u, int v) { while (top[u] != top[v]) { if (dep[top[u]] > dep[top[v]]) u = fa[top[u]]; else v = fa[top[v]]; } return dep[u] < dep[v] ? u : v; } int main() { read(n); read(q); for (int i = 0, i_end = n; i < i_end; ++i) read(a[i]); for (int i = 0, i_end = n; i < i_end; ++i) hd[i] = -1; for (int i = 0, i_end = n - 1; i < i_end; ++i) { int u, v, w; read(u); read(v); read(w); adline(--u, --v, w); adline(v, u, w); } dfs1(0); dfs2(0); dfs3(0); while (q--) { int u, v, m; long long ans; read(u); read(v); --u, --v; m = lca(u, v); ans = s[u] + s[v] - 2 * s[m] + a[m]; ans += f[u] + f[v] - 2 * f[m] + g[m]; ans -= h[u] + h[v] - 2 * h[m] - ff[m]; printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int inp() { return 0; } inline int inp(bool& A) { if (cin >> A) return 1; return -1; } inline int inp(char& A) { return scanf( %c , &A); } inline int inp(int& A) { return scanf( %d , &A); } inline int inp(float& A) { if (cin >> A) return 1; return -1; } inline int inp(long long& A) { return scanf( %I64d , &A); } inline int inp(double& A) { return scanf( %lf , &A); } inline int inp(char* A) { return scanf( %s , A); } inline int inp(string& A) { if (cin >> A) return 1; return -1; } template <class Front, class... Queue> inline int inp(Front& A, Queue&... B) { return inp(A) + inp(B...); } inline int oup() { return 0; } inline int oup(bool A) { if (cout << A) return 1; return -1; } inline int oup(char A) { return printf( %c , A); } inline int oup(int A) { return printf( %d , A); } inline int oup(float A) { if (cout << A) return 1; return -1; } inline int oup(long long A) { return printf( %I64d , A); } inline int oup(double A) { return printf( %lf , A); } inline int oup(char* A) { return printf(A); } inline int oup(const char* A) { return printf( %s , A); } inline int oup(string& A) { if (cout << A) return 1; return -1; } template <class Front, class... Queue> inline int oup(Front A, Queue... B) { return oup(A) + oup(B...); } template <class T> inline void remax(T& A, T B) { if (A < B) A = B; } template <class T> inline void remin(T& A, T B) { if (A > B) A = B; } string ToString(long long num) { string ret; do { ret += ((num % 10) + 0 ); num /= 10; } while (num); reverse(ret.begin(), ret.end()); return ret; } long long ToNumber(string s) { long long r = 0, p = 1; for (int i = s.size() - 1; i >= 0; --i) r += (s[i] - 0 ) * p, p *= 10; return r; } long long Gcd(long long a, long long b) { while (a %= b ^= a ^= b ^= a) ; return b; } long long Power(long long base, long long power) { long long ret = 1; while (power) { if (power & 1) ret *= base; power >>= 1; base *= base; } return ret; } long long PowerMod(long long base, long long power, long long mod) { if (!power) return 1; if (power & 1) return (base * PowerMod(base, power - 1, mod)) % mod; return PowerMod((base * base) % mod, power >> 1, mod); } int Log(long long num, long long base) { int ret = 0; while (num) { ++ret; num /= base; } return ret; } int Count(long long mask) { int ret = 0; while (mask) { if (mask & 1) ++ret; mask >>= 1; } return ret; } inline void run() { in:; int n, m, k; if (inp(n, m, k) != 3) return; vector<int> a(m), b(m), c(m); long long ans = 0; for (int i = 0; i < m; ++i) inp(a[i], b[i], c[i]); while (k--) { int tmp; inp(tmp); for (int i = 0; i < m; ++i) if (tmp >= a[i] && tmp <= b[i]) ans += (long long)c[i] + tmp - a[i]; } oup(ans, n ); goto in; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); run(); return 0; }
|
//#############################################################################
//# Function: MIO Configuration Registers #
//# (See README.md for complete documentation) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) #
//#############################################################################
`include "mio_regmap.vh"
module mio_regs #(parameter N = 8, // number of I/O pins
parameter AW = 32, // address width
parameter PW = 104, // packet width
parameter DEF_CFG = 18'h1070, // default config
parameter DEF_CLK = 7 // clock divider
)
(
// clk,reset
input clk,
input nreset,
// register access interface
input access_in, // incoming access
input [PW-1:0] packet_in, // incoming packet
output wait_out,
output access_out, // outgoing read packet
output [PW-1:0] packet_out, // outgoing read packet
input wait_in,
// config outputs
output tx_en, // enable tx
output rx_en, // enable rx
output ddr_mode, // ddr mode for mio
output emode, // epiphany packet mode
output amode, // mio packet mode
output dmode, // mio packet mode
output [1:0] datamode, // mio datasize
output [1:0] iowidth, // mio io width
output lsbfirst, // lsb shift first
output framepol, // framepolarity (0=actrive high)
output [4:0] ctrlmode, // emode ctrlmode
output [AW-1:0] dstaddr, // destination address for RX dmode
output clkchange, // indicates a clock change
output [7:0] clkdiv, // mio clk clock setting
output [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
output [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
// status inputs
input tx_full, //tx fifo is full (should not happen!)
input tx_prog_full, //tx fifo is nearing full
input tx_empty, //tx fifo is empty
input rx_full, //rx fifo is full (should not happen!)
input rx_prog_full, //rx fifo is nearing full
input rx_empty //rx fifo is empty
);
localparam DEF_RISE0 = 0; // 0 degrees
localparam DEF_FALL0 = ((DEF_CLK+8'd1)>>8'd1); // 180 degrees
localparam DEF_RISE1 = ((DEF_CLK+8'd1)>>8'd2); // 90 degrees
localparam DEF_FALL1 = ((DEF_CLK+8'd1)>>8'd2)+
((DEF_CLK+8'd1)>>8'd1); // 270 degrees
//##############
//# LOCAL WIRES
//##############
reg [20:0] config_reg;
reg [15:0] status_reg;
reg [31:0] clkdiv_reg;
reg [63:0] addr_reg;
reg [31:0] clkphase_reg;
wire [7:0] status_in;
wire reg_write;
wire config_write;
wire status_write;
wire clkdiv_write;
wire clkphase_write;
wire idelay_write;
wire odelay_write;
wire addr0_write;
wire addr1_write;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//#####################################
//# DECODE
//#####################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign reg_write = write_in & access_in;
assign config_write = reg_write & (dstaddr_in[5:2]==`MIO_CONFIG);
assign status_write = reg_write & (dstaddr_in[5:2]==`MIO_STATUS);
assign clkdiv_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKDIV);
assign clkphase_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKPHASE);
assign idelay_write = reg_write & (dstaddr_in[5:2]==`MIO_IDELAY);
assign odelay_write = reg_write & (dstaddr_in[5:2]==`MIO_ODELAY);
assign addr0_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR0);
assign addr1_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR1);
assign clkchange = clkdiv_write | clkphase_write;
//################################
//# CONFIG
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
config_reg[20:0] <= DEF_CFG;
end
else if(config_write)
config_reg[20:0] <= data_in[20:0];
assign tx_en = ~config_reg[0]; // tx disable
assign rx_en = ~config_reg[1]; // rx disable
assign emode = config_reg[3:2]==2'b00; // emesh packets
assign dmode = config_reg[3:2]==2'b01; // data mode (streaming)
assign amode = config_reg[3:2]==2'b10; // auto address mode
assign iowidth[1:0] = config_reg[5:4]; // iowidth(or 8,16,32,64 pins)
assign datamode[1:0] = config_reg[7:6]; // rx datamode(8,16,32,64)
assign ddr_mode = config_reg[12]; // dual data rate mode
assign lsbfirst = config_reg[13]; // lsb-first transmit
assign framepol = config_reg[14]; // frame polarity
assign ctrlmode[4:0] = config_reg[20:16]; // ctrlmode
//###############################
//# STATUS
//################################
assign status_in[7:0] = {2'b0, //7:6
tx_full, //5
tx_prog_full,//4
tx_empty, //3
rx_full, //2
rx_prog_full,//1
rx_empty //0
};
always @ (posedge clk or negedge nreset)
if(!nreset)
status_reg[15:0] <= 'b0;
else if(status_write)
status_reg[15:0] <= data_in[7:0];
else
status_reg[15:0] <= {(status_reg[15:8] | status_in[7:0]), // sticky bits
status_in[7:0]}; // immediate bits
//###############################
//# CLKDIV
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkdiv_reg[7:0] <= DEF_CLK;
else if(clkdiv_write)
clkdiv_reg[7:0] <= data_in[7:0];
assign clkdiv[7:0] = clkdiv_reg[7:0];
//###############################
//# CLKPHASE
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
clkphase_reg[7:0] <= DEF_RISE0;
clkphase_reg[15:8] <= DEF_FALL0;
clkphase_reg[23:16] <= DEF_RISE1;
clkphase_reg[31:24] <= DEF_FALL1;
end
else if(clkphase_write)
clkphase_reg[31:0] <= data_in[31:0];
assign clkphase0[15:0] = clkphase_reg[15:0];
assign clkphase1[15:0] = clkphase_reg[31:16];
//###############################
//# RX DESTINATION ADDR ("AMODE")
//################################
always @ (posedge clk)
if(addr0_write)
addr_reg[31:0] <= data_in[31:0];
else if(addr1_write)
addr_reg[63:32] <= data_in[31:0];
assign dstaddr[AW-1:0] = addr_reg[AW-1:0];
//###############################
//# READBACK
//################################
assign access_out ='b0;
assign wait_out ='b0;
assign packet_out ='b0;
endmodule
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../../oh/common/hdl")
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:31:21 AM
// Design Name:
// Module Name: multiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multiplier
# (parameter W = 32/*,level=5*/) (//level=log2(W)
input wire clk,
input wire [W-1:0] Data_A_i,
input wire [W-1:0] Data_B_i,
output wire [2*W-1:0] Data_S_o
);
//reg [W-1:0] aint,bint;
reg [2*W-1:0] pdt_int;/*[level-1:0];*/
//integer i;
assign Data_S_o=pdt_int;//[level-1];
always@(posedge clk)
begin
//aint<=Data_A_i;
//bint<=Data_B_i;
pdt_int<= Data_A_i*Data_B_i;
//for (i=1;i<level;i=i+1)
//pdt_int[i]<=pdt_int[i-1];
end
endmodule
//module multiplier #(parameter W=32)(
// input wire clk,
// input wire [W-1:0] Data_A_i,
// input wire [W-1:0] Data_B_i,
// output reg [2*W-1:0] Data_S_o
// );
// //reg [W-1:0] a_in, b_in;
// //wire [2*W-1:0] multi_reg;
// reg [2*W-1:0] pipe1, pipe2, pipe3, pipe4, pipe5;
// //assign multi_reg = a_in * b_in;
// always @(posedge clk) begin
// //a_in <= Data_A_i; b_in <= Data_B_i;
// pipe1 <= Data_A_i*Data_B_i;
// pipe2 <= pipe1;
// pipe3 <= pipe2;
// pipe4 <= pipe3;
// pipe5 <= pipe4;
// Data_S_o <= pipe5;
// end
// endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n, k, i, j, t, x; int c[200]; cin >> n; int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; c[i] = a[i]; } cin >> m; int b[m]; for (j = 0; j < m; j++) { cin >> b[j]; c[i + j] = b[j]; } x = m + n; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { t = 0; for (k = 0; k < x; k++) { if (a[i] + b[j] == c[k]) { t = 1; break; } } if (t == 0) { cout << a[i] << << b[j] << endl; goto here; } } } here: return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; const int MOD = 1e9 + 7; int n, m; vector<int> tmp; vector<int> g[N]; int cnt1[N]; int marked[N]; int f[N]; map<vector<int>, int> cnt; int product(int a, int b) { return (1ll * a * b) % MOD; } void mult(int &a, int b) { a = (1ll * a * b) % MOD; } int main() { f[0] = 1; for (int i = 1; i < N; i++) f[i] = product(f[i - 1], i); scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { int k; scanf( %d , &k); for (int j = 0; j < k; j++) { int x; scanf( %d , &x); g[x].push_back(i); } } for (int i = 1; i <= m; i++) cnt[g[i]]++; int ans = 1; for (auto p : cnt) { mult(ans, f[p.second]); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long LINF = 1001002003004005006ll; int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (b < a) { a = b; return 1; } return 0; } signed main() { cin.tie(0); ios::sync_with_stdio(0); long long n; cin >> n; string s; cin >> s; if (n == 1) { cout << 0 << endl; return 0; } vector<long long> v; long long i = 0; while (i < n) { char tmp = s[i]; long long cnt = 0; while (i + cnt < n and s[i + cnt] == tmp) { cnt++; } v.push_back(cnt); i += cnt; } long long m = v.size(); if (m == 1) { long long ans = n * (n + 1) / 2 - n; cout << ans << endl; return 0; } long long diff = 0; for (long long i = 0; i < m; i++) { diff += 2 * v[i]; } diff -= v[0]; diff -= v[m - 1]; diff -= m - 1; long long ans = n * (n + 1) / 2 - diff - n; cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_TB_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
`define STRINGIFY(x) `"x`"
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
//======================================================================
module t;
integer file;
integer r_i;
byte r_upb[20:10];
byte r_dnb[20:10];
reg [13:0] r_ups[20:10];
reg [13:0] r_dns[10:20];
reg [30:0] r_upi[20:10];
reg [30:0] r_dni[10:20];
reg [61:0] r_upq[20:10];
reg [61:0] r_dnq[10:20];
reg [71:0] r_upw[20:10];
reg [71:0] r_dnw[10:20];
task clear;
// Initialize memories to zero,
// avoid differences between 2-state and 4-state.
r_i = ~0;
foreach (r_upb[i]) r_upb[i] = ~0;
foreach (r_dnb[i]) r_dnb[i] = ~0;
foreach (r_ups[i]) r_ups[i] = ~0;
foreach (r_dns[i]) r_dns[i] = ~0;
foreach (r_upi[i]) r_upi[i] = ~0;
foreach (r_dni[i]) r_dni[i] = ~0;
foreach (r_upq[i]) r_upq[i] = ~0;
foreach (r_dnq[i]) r_dnq[i] = ~0;
foreach (r_upw[i]) r_upw[i] = ~0;
foreach (r_dnw[i]) r_dnw[i] = ~0;
// Open file
$fclose(file);
file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r");
if ($feof(file)) $stop;
endtask
task dump;
$write("Dump:");
$write("\n r_i:"); $write(" %x",r_i);
$write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]);
$write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]);
$write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]);
$write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]);
$write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]);
$write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]);
$write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]);
$write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]);
$write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]);
$write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]);
$write("\n\n");
endtask
integer code;
initial begin
clear;
code = $fread(r_i, file); `checkd(code, 4);
code = $fread(r_upb, file); `checkd(code, 11);
code = $fread(r_dnb, file); `checkd(code, 11);
code = $fread(r_ups, file); `checkd(code, 22);
code = $fread(r_dns, file); `checkd(code, 22);
code = $fread(r_upi, file); `checkd(code, 44);
code = $fread(r_dni, file); `checkd(code, 44);
code = $fread(r_upq, file); `checkd(code, 88);
code = $fread(r_dnq, file); `checkd(code, 88);
code = $fread(r_upw, file); `checkd(code, 99);
code = $fread(r_dnw, file); `checkd(code, 99);
dump;
clear;
code = $fread(r_upb, file, 15); `checkd(code, 6);
code = $fread(r_ups, file, 15, 2); `checkd(code, 4);
dump;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int a[N]; struct Block { int len, st, ed, num; Block(const int len = 0, const int st = 0, const int ed = 0, const int num = 0) : len(len), st(st), ed(ed), num(num){}; }; vector<Block> v; bool islucky(int a) { bool ret = true; while (a && ret) { ret = a % 10 == 4 || a % 10 == 7; a /= 10; } return ret; } struct Node { int l, r; Node *left, *right; Node(const int l = 0, const int r = 0) : l(l), r(r), left(NULL), right(NULL) {} }; unsigned long long cal(const unsigned long long l, const unsigned long long r) { return (r - l) * (r - l + 1) / 2; } unsigned long long cal3(const unsigned long long n) { return n * (n + 1) / 2 * n * (n + 1) / 2; } unsigned long long cal3(const unsigned long long l, const unsigned long long r) { return (r * (r + 1) / 2 + (l - 1) * l / 2) * (r * (r + 1) / 2 - (l - 1) * l / 2); } unsigned long long cal2(const unsigned long long n) { return n * (2 * n + 1) * (n + 1) / 6; } unsigned long long cal2(const unsigned long long l, const unsigned long long r) { return cal2(r) - cal2(l - 1); } unsigned long long cal1(const unsigned long long l, const unsigned long long r) { return (r + l) * (r - l + 1) / 2; } unsigned long long cal0(const unsigned long long l, const unsigned long long r) { return r - l + 1; } int main() { unsigned long long n; cin >> n; int last = 0; for (int i = 0; i < n; ++i) { scanf( %d , a + i); if (islucky(a[i])) { v.push_back(Block(i - last + 1, last, i, a[i])); last = i + 1; } } a[n] = -1; if (last != n) { v.push_back(Block(n - last, last, n, -1)); } map<int, vector<int> > tr; for (int i = 0; i < (int)v.size(); ++i) { tr[v[i].num].push_back(v[i].ed); } unsigned long long ans = 0; for (int i = 0; i < v.size(); ++i) { unsigned long long bpSum = 0; set<int> bp; set<int> contain; unsigned long long tmp = 0; tmp = 1 * cal3(v[i].st, v[i].ed - 1); tmp += (n * (n - 1) + n * (v[i].st - 1) + (n - 1) * (v[i].st - 1)) * cal1(v[i].st, v[i].ed - 1); tmp -= (n + n - 1 + (v[i].st - 1)) * cal2(v[i].st, v[i].ed - 1); tmp -= (v[i].st - 1) * n * (n - 1) * cal0(v[i].st, v[i].ed - 1); ans += tmp / 2; bp.insert(n); bp.insert(v[i].ed - 1); bpSum = cal(v[i].ed, n); for (int j = i; j + 1 < (int)v.size(); ++j) { int bar = v[j + 1].ed; while (*bp.begin() < bar) { bpSum -= cal(*bp.begin() + 1, *(++bp.begin())); bp.erase(bp.begin()); } bp.insert(bar - 1); bpSum += cal(*bp.begin() + 1, *(++bp.begin())); if (!contain.count(v[j].num)) { contain.insert(v[j].num); vector<int> breaks = tr[v[j].num]; for (int k = 0; k < breaks.size(); ++k) { if (breaks[k] >= v[j + 1].ed) { int cut = breaks[k]; set<int>::iterator it = bp.upper_bound(cut); int right = *it, left = *(--it); bpSum -= cal(left + 1, right); bp.insert(cut); bpSum += cal(left + 1, cut) + cal(cut + 1, right); } } } unsigned long long k, tmp1, rem = bpSum; k = *(++bp.begin()); rem *= (v[j + 1].ed - v[j].ed); tmp1 = 1 * cal2(v[j].ed, v[j + 1].ed - 1) + (2 * k - v[j + 1].ed) * (v[j + 1].ed - 1) * cal0(v[j].ed, v[j + 1].ed - 1) - (2 * k - v[j + 1].ed + v[j + 1].ed - 1) * cal1(v[j].ed, v[j + 1].ed - 1); ans += v[i].len * (rem + tmp1 / 2); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int tree[27][2000000 + 5]; vector<int> data[244]; int del[2000000 + 6]; int read(int t, int idx) { int sum = 0; while (idx > 0) { sum += tree[t][idx]; idx -= (idx & -idx); } return sum; } void update(int t, int idx, int val) { while (idx <= 2000000) { tree[t][idx] += val; idx += (idx & -idx); } } int bin(int t, int tar) { int i = 1, j = 2000000; while (i < j) { int x = (i + j) / 2; if (tar <= read(t, x)) j = x; else i = x + 1; } return i; } void init() { for (int i = 1; i <= 26; ++i) { int siz = data[i].size(); for (int j = 1; j <= siz + 1; ++j) update(i, j, 1); } } int main() { int k, ll, n, p; char c; string ss; cin >> k >> ss; ll = ss.length(); ss = + ss; for (int i = 1; i <= k; ++i) { for (int p = 1; p <= ll; ++p) { data[ss[p] - a + 1].push_back(p + (i - 1) * ll); } } init(); cin >> n; for (int i = 1; i <= n; ++i) { cin >> p >> c; int num = bin(c - a + 1, p); del[data[c - a + 1][num - 1]] = 1; update(c - a + 1, num, -1); } for (int i = 1; i <= k; ++i) { for (int p = 1; p <= ll; ++p) { if (del[p + (i - 1) * ll] == 0) printf( %c , ss[p]); } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hd__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:54:12 08/27/2015
// Design Name: display
// Module Name: A:/Dropbox/University/Computing/COMP3601/AudioController/display_tbw.v
// Project Name: AudioController
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module display_tbw;
// Inputs
reg CLK;
reg [7:0] BPM;
// Outputs
wire [3:0] SEGA;
wire [7:0] SEGD;
// Instantiate the Unit Under Test (UUT)
display uut (
.CLK(CLK),
.BPM(BPM),
.SEGA(SEGA),
.SEGD(SEGD)
);
initial begin
// Initialize Inputs
CLK = 0;
BPM = 12'h123;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
CLK = ~CLK;
BPM = BPM + 1;
#1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t = 1; cin >> t; while (t--) { long long int n; cin >> n; cout << n << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int vis[51]; int main() { string s; int n, len; cin >> len >> n; cin >> s; while (n--) { for (int i = 0; i <= len; i++) { if (s[i] == B && s[i + 1] == G ) { swap(s[i], s[i + 1]); i++; } } } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 10010; const int M = 15; const double eps = 1e-7; const int INF = 1 << 30; int n; struct node { double x, y, z; node() { x = y = z = 0; } node(double xx, double yy, double zz) { x = xx; y = yy; z = zz; } } poy[N], ori; double vp, vs, prelen; int ln; double ABS(double x) { while (x < 0) x = -x; return x; } double dist(node a, node b) { double tmp = 0; tmp += (a.x - b.x) * (a.x - b.x); tmp += (a.y - b.y) * (a.y - b.y); tmp += (a.z - b.z) * (a.z - b.z); return sqrt(tmp); } void init() { double x, y, z; for (int i = 1; i <= n + 1; i++) { cin >> x >> y >> z; poy[i] = node(x, y, z); } cin >> vp >> vs; cin >> x >> y >> z; ori = node(x, y, z); } bool solve() { double t = 0; for (int i = 2; i <= n + 1; i++) { double len = dist(ori, poy[i]) / vp; double edge = dist(poy[i - 1], poy[i]) / vs; t += edge; if ((t - len) >= -eps) { ln = i; prelen = t - edge; return 1; } } return 0; } node getmid(node a, node b) { double xx, yy, zz; xx = (a.x + b.x) * 0.5; yy = (a.y + b.y) * 0.5; zz = (a.z + b.z) * 0.5; return node(xx, yy, zz); } void cal() { node pre = poy[ln - 1]; node l = poy[ln - 1], r = poy[ln]; double t; while (ABS(dist(l, r)) > eps) { node mid = getmid(l, r); double len1 = dist(ori, mid); double len2 = dist(mid, pre); double t1 = len1 / vp; double t2 = len2 / vs + prelen; t = t1; if ((t1 - t2) < 1e-15) r = mid; else l = mid; } printf( %.10lf n%.10lf %.10lf %.10lf n , t, l.x, l.y, l.z); } int main() { while (cin >> n) { init(); if (solve()) cout << YES << endl; else { cout << NO << endl; continue; } cal(); } }
|
// Author: Adam Nunez,
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module KeyPadDecoder(
input [3:0] In,
output reg [3:0] Out
);
// This module accepts as input a four bit value that describes
// the row col vector and decodes into the value at that location
// for a 4 by 4 matrix keypad with layout ...
// 1 2 3 A
// 4 5 6 B
// 7 8 9 C
// * 0 # D
always @(In) begin
case (In)
4'b0000: Out = 4'h1;
4'b0001: Out = 4'h2;
4'b0010: Out = 4'h3;
4'b0011: Out = 4'hA;
4'b0100: Out = 4'h4;
4'b0101: Out = 4'h5;
4'b0110: Out = 4'h6;
4'b0111: Out = 4'hB;
4'b1000: Out = 4'h7;
4'b1001: Out = 4'h8;
4'b1010: Out = 4'h9;
4'b1011: Out = 4'hC;
4'b1100: Out = 4'hF;
4'b1101: Out = 4'h0;
4'b1110: Out = 4'hE;
4'b1111: Out = 4'hD;
default: Out = 4'h1;
endcase
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1000000000 ) #pragma GCC optimize( Ofast,no-stack-protector ) using namespace std; const int maxn = (int)1e5 + 10; vector<int> ed[maxn]; int sz[maxn]; void dfs(int v, int p) { sz[v] = 1; for (int u : ed[v]) { if (u != p) { dfs(u, v); sz[v] += sz[u]; } } } int h[maxn]; vector<pair<pair<int, int>, int> > g[maxn]; long long sum = 0; set<int> vert[maxn]; int tt = -1; int tin[maxn], tout[maxn]; void build(int v, int p, int pr, int hh) { tt++; tin[v] = tt; vert[pr].insert(v); sum += hh; h[v] = hh; sz[v] = 1; vector<int> a; for (int u : ed[v]) { if (u == p) { continue; } build(u, v, pr, hh + 1); sz[v] += sz[u]; if (sz[u] & 1) { a.push_back(u); } } while ((int)a.size() >= 2) { int x = a.back(); a.pop_back(); int y = a.back(); a.pop_back(); g[pr].push_back(make_pair(make_pair(x, y), hh)); } if (!a.empty()) { g[pr].push_back(make_pair(make_pair(a.back(), v), hh)); } tout[v] = tt; } bool is_anc(int x, int y) { return tin[x] <= tin[y] && tout[y] <= tout[x]; } int main() { int n; long long k; cin >> n >> k; for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d %d , &x, &y); x--; y--; ed[x].push_back(y); ed[y].push_back(x); } dfs(0, -1); int v = 0; while (true) { bool ok = true; for (int u : ed[v]) { if (sz[u] < sz[v] && 2 * sz[u] > n) { v = u; ok = false; break; } } if (ok) { break; } } for (int u : ed[v]) { build(u, v, u, 1); reverse((g[u]).begin(), (g[u]).end()); } if (k > sum) { cout << NO n << n ; return 0; } set<pair<int, int> > s; for (int u : ed[v]) { s.insert(make_pair(sz[u], u)); } vector<pair<int, int> > res; if ((k - sum) & 1) { cout << NO n << n ; return 0; } while (!s.empty() && sum != k) { int u = s.rbegin()->second; s.erase(*s.rbegin()); if (sz[u] == 1) { cout << NO n << n ; return 0; } if (sum - 2 * g[u].back().second >= k) { sum -= 2 * g[u].back().second; sz[u] -= 2; s.insert(make_pair(sz[u], u)); res.push_back(g[u].back().first); vert[u].erase(g[u].back().first.first); vert[u].erase(g[u].back().first.second); g[u].pop_back(); continue; } int x = g[u].back().first.first; int y = -1; for (int z : vert[u]) { if (sum - 2 * h[z] == k && is_anc(z, x)) { y = z; break; } } assert(y != -1); res.push_back(make_pair(x, y)); vert[u].erase(x); vert[u].erase(y); break; } cout << YES n ; s.clear(); for (int u : ed[v]) { if (vert[u].size()) { s.insert(make_pair(vert[u].size(), u)); } } while ((int)s.size() > 1) { int x = s.rbegin()->second; s.erase(*s.rbegin()); int y = s.rbegin()->second; s.erase(*s.rbegin()); int a = *vert[x].begin(); vert[x].erase(a); int b = *vert[y].begin(); vert[y].erase(b); res.push_back(make_pair(a, b)); if (vert[x].size()) { s.insert(make_pair(vert[x].size(), x)); } if (vert[y].size()) { s.insert(make_pair(vert[y].size(), y)); } } int x = s.begin()->second; assert((int)vert[x].size() == 1); res.push_back(make_pair(v, *vert[x].begin())); for (pair<int, int> f : res) { printf( %d %d n , f.first + 1, f.second + 1); } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; int arr[m]; for (int i = 0; i < m; i++) cin >> arr[i]; long long res = arr[0]; for (int i = 1; i < m; i++) { if (arr[i] - arr[i - 1] < 0) { res += (n - arr[i - 1]) + arr[i]; } else res += (arr[i] - arr[i - 1]); } cout << res - 1 << n ; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9671_pnmon (
// adc interface
adc_clk,
adc_valid,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input adc_valid;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
// internal registers
reg adc_pn_valid = 'd0;
reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0;
// internal signals
wire adc_pn_valid_s;
wire [31:0] adc_pn_data_pn_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_valid_s = adc_valid & adc_pn_valid;
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_pn_valid <= ~adc_pn_valid;
adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]};
end
if (adc_pn_valid_s == 1'b1) begin
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_pn_valid_s),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, num, k; pair<int, int> a[200005]; bool comp(pair<int, int> a, pair<int, int> b) { return a.second < b.second; } int main() { ios::sync_with_stdio(0); cin.tie(NULL); int t = 1; cin >> t; while (t--) { cin >> n >> k; unordered_map<int, int> mp; int color = 1; for (int i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a, a + n); for (int i = 0; i < n; i++) { mp[a[i].first]++; if (mp[a[i].first] > k) a[i].first = 0; else { a[i].first = color; if (color == k) color = 1; else color++; } } color--; for (int i = n - 1; i >= 0; i--) { if (a[i].first == color) { a[i].first = 0; color--; } } sort(a, a + n, comp); for (int i = 0; i < n; i++) cout << a[i].first << ; cout << endl; } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
parameter string ES = "";
parameter EI = ""; // B is an integer of width 8
parameter string OS = "O";
parameter OI = "O"; // B is an integer of width 8
parameter bit [31:0] NEST = "NEST";
parameter bit [31:0] TEST = "TEST";
bit [31:0] rest;
string s;
initial begin
$display(">< == >%s<", "");
$display(">< == >%s<", ES);
$display("> < == >%s<", EI);
if ($bits("") != 0) $stop;
if ($bits("A") != 8) $stop;
if ($bits(ES) != 0) $stop;
if ($bits(EI) != 8) $stop;
if ($bits(OS) != 8) $stop;
if ($bits(OI) != 8) $stop;
if (ES == "TEST") $stop; // Illegal in some simulators as not both strings
if (EI == "TEST") $stop;
if (OS == "TEST") $stop; // Illegal in some simulators as not both strings
// verilator lint_off WIDTH
if (OI == "TEST") $stop;
if (rest == "TEST") $stop;
if (ES == TEST) $stop;
if (EI == TEST) $stop;
if (OS == TEST) $stop;
if (OI == TEST) $stop;
if (rest == TEST) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int d(int a, int b, int a1, int b1) { return abs(a - a1) + abs(b - b1); } int main() { int n; cin >> n; int x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; if (y1 == y2 && (y1 == 0 || y1 == n)) { cout << abs(x1 - x2) << endl; return 0; } if (x1 == x2 && (x1 == 0 || x1 == n)) { cout << abs(y1 - y2) << endl; return 0; } if (abs(y1 - y2) == n) { swap(x1, y1); swap(x2, y2); } if (abs(x1 - x2) == n) { cout << n + min(y1 + y2, 2 * n - y1 - y2) << endl; return 0; } int mi = 2 * n; for (int i = 0; i <= n; i += n) for (int j = 0; j <= n; j += n) { mi = min(mi, d(x1, y1, i, j) + d(x2, y2, i, j)); } cout << mi << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[100005], tmp[100005], b[100005]; bool die[100005]; int n, m; vector<long long> candidate; bool solve(int pos) { candidate.clear(); for (int i = 1; i <= n; i++) if ((!die[i]) && (a[i] & (1ll << pos))) { candidate.push_back(a[i]); die[i] = true; } for (int i = 1; i <= m; i++) tmp[i] = b[i]; int len_tmp = m; int cur = 1; m = 0; for (int i = 0; i < candidate.size(); i++) { b[++m] = candidate[i]; while (cur <= len_tmp && !(tmp[cur] & (1ll << pos))) { b[++m] = tmp[cur]; cur++; } if (cur > len_tmp && i != candidate.size() - 1) return false; b[++m] = tmp[cur]; cur++; } while (cur <= len_tmp) { b[++m] = tmp[cur]; cur++; } return true; } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 59; i >= 0; i--) if (!solve(i)) { printf( No ); return 0; } cout << Yes n ; for (int i = 1; i <= n; i++) cout << b[i] << ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100500; struct matrix { long double a[3][3]; void clear() { memset(a, 0, sizeof(a)); } matrix operator*(const matrix &y) { matrix ans; ans.clear(); for (int i = (0), iend = (2); i <= iend; i++) for (int j = (0), jend = (2); j <= jend; j++) for (int k = (0), kend = (2); k <= kend; k++) ans.a[i][j] += a[i][k] * y.a[k][j]; return ans; } } basis; struct segment_tree { matrix sum[maxn << 2]; void push_up(int rt) { sum[rt] = sum[(rt << 1)] * sum[(rt << 1 | 1)]; } void upd(int l, int r, int rt, int tar, long double val) { if (l == r) { sum[rt].clear(); sum[rt].a[1][0] = 1; sum[rt].a[2][1] = 1; sum[rt].a[1][2] = (val - 1) / val; sum[rt].a[2][2] = 1 / val; return; } int mid = (l + r) >> 1; if (tar <= mid) upd(l, mid, (rt << 1), tar, val); else upd(mid + 1, r, (rt << 1 | 1), tar, val); push_up(rt); } matrix query(int l, int r, int rt, int tl, int tr) { if (tl <= l && r <= tr) return sum[rt]; int mid = (l + r) >> 1; matrix ans = basis; if (tl <= mid) ans = ans * query(l, mid, (rt << 1), tl, tr); if (tr >= mid + 1) ans = ans * query(mid + 1, r, (rt << 1 | 1), tl, tr); return ans; } } t; int main() { basis.clear(); for (int i = (0), iend = (2); i <= iend; i++) basis.a[i][i] = 1; int n, q; scanf( %d%d , &n, &q); for (int i = (1), iend = (n); i <= iend; i++) { int a, b; scanf( %d%d , &a, &b); t.upd(1, n, 1, i, (long double)(a) / b); } for (int i = (1), iend = (q); i <= iend; i++) { int ty; scanf( %d , &ty); if (ty == 1) { int idx, a, b; scanf( %d%d%d , &idx, &a, &b); t.upd(1, n, 1, idx, (long double)(a) / b); } else { int l, r; scanf( %d%d , &l, &r); matrix ans; ans.clear(); ans.a[0][2] = 1; ans = ans * t.query(1, n, 1, l, r); long double out = (long double)(1) / ans.a[0][2]; if (isnan(out)) out = 0; printf( %.7lf n , (double)(out)); } } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 09:07:01
// Design Name:
// Module Name: counters_8bit_with_T_ff
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counters_8bit_with_T_ff(
input Clk,
input Enable,
input Clear,
output [7:0] Q
);
T_ff_with_synch_reset_behavior SR0 (.Clk(Clk), .T(Enable), .reset_n(Clear), .Q(Q[0]));
T_ff_with_synch_reset_behavior SR1 (.Clk(Clk), .T(Enable & Q[0]), .reset_n(Clear), .Q(Q[1]));
T_ff_with_synch_reset_behavior SR2 (.Clk(Clk), .T(Enable & Q[0] & Q[1]), .reset_n(Clear), .Q(Q[2]));
T_ff_with_synch_reset_behavior SR3 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2]), .reset_n(Clear), .Q(Q[3]));
T_ff_with_synch_reset_behavior SR4 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3]), .reset_n(Clear), .Q(Q[4]));
T_ff_with_synch_reset_behavior SR5 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4]), .reset_n(Clear), .Q(Q[5]));
T_ff_with_synch_reset_behavior SR6 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5]), .reset_n(Clear), .Q(Q[6]));
T_ff_with_synch_reset_behavior SR7 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6]), .reset_n(Clear), .Q(Q[7]));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; bool watched[1000001]; cin >> n; while (cin >> x) watched[x] = true; for (int i = 1; i <= n; i++) if (!watched[i]) cout << i; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxl = 60, w = 10000; struct Big { int s[maxl], l; Big() { memset(s, 0, sizeof(s)); l = 1; } inline void fix() { for (int i = 1; i < l; i++) { if (s[i] >= w) { s[i + 1] += s[i] / w; s[i] %= w; } } while (s[l] >= w) { s[l + 1] += s[l] / w; s[l] %= w; l++; } } void fuzhi(int x) { s[1] = x; l = 1; fix(); } inline void out() { if (s[l] >= 1000) cout << s[l] / 1000 % 10; if (s[l] >= 100) cout << s[l] / 100 % 10; if (s[l] >= 10) cout << s[l] / 10 % 10; cout << s[l] % 10; for (int i = l - 1; i >= 1; i--) { if (s[i] < 1000) cout << 0; if (s[i] < 100) cout << 0; if (s[i] < 10) cout << 0; cout << s[i]; } cout << endl; } }; inline Big operator*(const Big &x, const Big &y) { Big ans; ans.l = x.l + y.l - 1; for (int i = 1; i <= x.l; i++) { for (int j = 1; j <= y.l; j++) ans.s[i + j - 1] += x.s[i] * y.s[j]; } ans.fix(); return ans; } inline bool operator<(const Big &x, const Big &y) { if (x.l != y.l) return x.l < y.l; for (int i = x.l; i >= 1; i--) if (x.s[i] != y.s[i]) return x.s[i] < y.s[i]; return false; } inline Big tran(long long x) { Big ans; ans.fuzhi(x); return ans; } const int maxn = 770; struct E { int from, to, next; } e[maxn * 2]; int te = 1, n, point[maxn]; void add(int x, int y) { te++; e[te].from = x; e[te].to = y; e[te].next = point[x]; point[x] = te; } int size[maxn]; Big f[maxn][maxn]; void dfs(int p, int fa) { size[p] = 1; for (int i = 0; i <= n; i++) f[p][i].fuzhi(1); for (int i = point[p]; i; i = e[i].next) { int to = e[i].to; if (to == fa) continue; dfs(to, p); for (int j = size[p]; j >= 0; j--) for (int k = size[to]; k >= 0; k--) f[p][j + k] = max(f[p][j + k], f[p][j] * f[to][k]); size[p] += size[to]; } for (int i = 1; i <= size[p]; i++) f[p][0] = max(f[p][0], f[p][i] * tran(i)); } void ceshi() { Big a, b; int x, y; cin >> x >> y; a.fuzhi(x); b.fuzhi(y); a.out(); b.out(); a = a * b; a.out(); exit(0); } int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; add(x, y); add(y, x); } dfs(1, 0); f[1][0].out(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_PP_V
|
`default_nettype none
`define WIDTH 16
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [`WIDTH-1:0] dout,
input wire [`WIDTH-1:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn);
reg [4:0] dsp, dspN; // data stack pointer
reg [`WIDTH-1:0] st0, st0N; // top of data stack
reg dstkW; // data stack write
reg [12:0] pc, pcN; // program counter
wire [12:0] pc_plus_1 = pc + 13'd1;
reg rstkW; // return stack write
wire [`WIDTH-1:0] rstkD; // return stack write value
reg reboot = 1;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [`WIDTH-1:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(16)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2 #(.DEPTH(19)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
// stack2 #(.DEPTH(24)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
// stack2 #(.DEPTH(24)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
always @*
begin
// Compute the new value of st0
casez ({pc[12], insn[15:8]})
9'b1_???_?????: st0N = insn; // literal
9'b0_1??_?????: st0N = { {(`WIDTH - 15){1'b0}}, insn[14:0] }; // literal
9'b0_000_?????: st0N = st0; // jump
9'b0_010_?????: st0N = st0; // call
9'b0_001_?????: st0N = st1; // conditional jump
9'b0_011_?0000: st0N = st0; // ALU operations...
9'b0_011_?0001: st0N = st1;
9'b0_011_?0010: st0N = st0 + st1;
9'b0_011_?0011: st0N = st0 & st1;
9'b0_011_?0100: st0N = st0 | st1;
9'b0_011_?0101: st0N = st0 ^ st1;
9'b0_011_?0110: st0N = ~st0;
9'b0_011_?0111: st0N = {`WIDTH{(st1 == st0)}};
9'b0_011_?1000: st0N = {`WIDTH{($signed(st1) < $signed(st0))}};
9'b0_011_?1001: st0N = {st0[`WIDTH - 1], st0[`WIDTH - 1:1]};
9'b0_011_?1010: st0N = {st0[`WIDTH - 2:0], 1'b0};
9'b0_011_?1011: st0N = rst0;
9'b0_011_?1100: st0N = io_din;
9'b0_011_?1101: st0N = io_din;
9'b0_011_?1110: st0N = {{(`WIDTH - 5){1'b0}}, dsp};
9'b0_011_?1111: st0N = {`WIDTH{(st1 < st0)}};
default: st0N = {`WIDTH{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire is_alu = !pc[12] & (insn[15:13] == 3'b011);
assign mem_wr = !reboot & is_alu & func_write;
assign dout = st1;
assign io_wr = !reboot & is_alu & func_iow;
assign io_rd = !reboot & is_alu & func_ior;
assign rstkD = (insn[13] == 1'b0) ? {{(`WIDTH - 14){1'b0}}, pc_plus_1, 1'b0} : st0;
always @*
begin
casez ({pc[12], insn[15:13]})
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01};
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11};
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({pc[12], insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01};
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]};
default: {rstkW, rspI} = {1'b0, 2'b00};
endcase
casez ({reboot, pc[12], insn[15:13], insn[7], |st0})
7'b1_0_???_?_?: pcN = 0;
7'b0_0_000_?_?,
7'b0_0_010_?_?,
7'b0_0_001_?_0: pcN = insn[12:0];
7'b0_1_???_?_?,
7'b0_0_011_1_?: pcN = rst0[13:1];
default: pcN = pc_plus_1;
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
reboot <= 1'b1;
{ pc, dsp, st0} <= 0;
end else begin
reboot <= 0;
{ pc, dsp, st0} <= { pcN, dspN, st0N };
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[5]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); cout << a[n / 2]; }
|
#include <bits/stdc++.h> const long long MOD = 1e9 + 7; using namespace std; long long n, u, v, ans, dp[100005], cntt[100005]; vector<vector<long long> > g(100005); bool used[100005]; long long bpow(long long x, long long p) { if (p == 0) return 1; long long cur = bpow(x, p >> 1); cur = (cur * cur) % MOD; if (p & 1) cur = (cur * x) % MOD; return cur; } void countDp(long long x) { used[x] = true; long long cans = 1, cnt = 0; ; for (int i = 0; i < g[x].size(); i++) { if (!used[g[x][i]]) { countDp(g[x][i]); cnt++; cans = (cans * dp[g[x][i]]) % MOD; } } if (cnt != 0) cans = (2 * cans) % MOD; cntt[x] = cnt; dp[x] = cans; } void countAns(long long x, long long mlt, bool root) { used[x] = true; if (!root && cntt[x] == 0) { dp[x] = (dp[x] * 2) % MOD; } dp[x] = (dp[x] * mlt) % MOD; ans = (ans + dp[x]) % MOD; for (int i = 0; i < g[x].size(); i++) { if (!used[g[x][i]]) { if (root && cntt[x] == 1) countAns( g[x][i], (((dp[x] * bpow(dp[g[x][i]], MOD - 2)) % MOD) * bpow(2, MOD - 2)) % MOD, 0); else countAns(g[x][i], (dp[x] * bpow(dp[g[x][i]], MOD - 2)) % MOD, 0); } } } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n - 1; i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } countDp(1); for (int i = 1; i <= n; i++) { used[i] = false; } countAns(1, 1, 1); cout << ans; return 0; }
|
/*******************************************************************
*****串口接收模块
*****1：确认开始位（检测低电平）
*****2：采集8bit有效数据位
*******************************************************************/
module Uart_rx(
input clk, //系统50MHz时钟
input rst_n, //复位，低电平有效
input rs232_rx, //输入串行数据
input [3:0] num, //控制一帧数据有多少bit
input sel_data, //波特率计数的中心点（采集数据的使能信号）
output rx_en, //接收信号使能：启动接收波特率计数
output reg tx_en, //发送信号使能：接收数据完成后，开始启动发送数据
output reg [7:0] rx_data //将接收到的8bit的串行数据转换为并行数据
);
//检测低电平信号（开始位）
reg in_1,in_2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
in_1 <= 1'b1;
in_2 <= 1'b1;
end
else
begin
in_1 <= rs232_rx;
in_2 <= in_1;
end
assign rx_en = in_2 & (~in_1); //当检测到信号由高变低时，将使能信号拉高
//确保一帧数据的中间8bit进行数据的读取，读取完成后，使能信号tx_en控制串口发送模块
reg [7:0] rx_data_r; //锁存数据寄存器
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
rx_data_r <= 8'd0;
rx_data <= 8'd0;
end
else
if(sel_data)
case(num)
0: ; //忽略开始位
1: rx_data_r[0] <= rs232_rx; //采集中间八位有效数据
2: rx_data_r[1] <= rs232_rx;
3: rx_data_r[2] <= rs232_rx;
4: rx_data_r[3] <= rs232_rx;
5: rx_data_r[4] <= rs232_rx;
6: rx_data_r[5] <= rs232_rx;
7: rx_data_r[6] <= rs232_rx;
8: rx_data_r[7] <= rs232_rx;
9: rx_data <= rx_data_r; //锁存采集的8位有效数据（忽略停止位）
default: ; //默认状态下不采集
endcase
//发送使能模块，检测数据接收是否完成？完成后就将tx_en拉高（开始启动数据发送模块）
always @(posedge clk or negedge rst_n)
if(!rst_n)
tx_en <= 0;
else
if(num == 4'd9 && sel_data) //接收停止之后拉高一个时钟
tx_en <= 1;
else
tx_en <= 0;
endmodule
|
module adder_tb;
parameter N_BITS_A = 3;
parameter BIN_PT_A = 1;
parameter SIGNED_A = 1;
parameter N_BITS_B = 4;
parameter BIN_PT_B = 3;
parameter SIGNED_B = 0;
parameter N_BITS_OUT = 6;
parameter BIN_PT_OUT = 3;
reg [N_BITS_A-1:0] a;
reg [N_BITS_B-1:0] b;
wire [N_BITS_OUT-1:0] sum;
initial begin
a = 3'b0_0_0; // 0
b = 4'b0_001; // + 1/8
// 1/8
#10
a = 3'b1_1_1; // -1/2
b = 4'b0_001; // + 1/8
// -3/8
#5
a = 3'b1_1_0; // -1
b = 4'b0_100; // + 1/2
// -1/2
#5
a = 3'b0_0_1; // 1/2
b = 4'b1_000; // + 1
// 3/2
#10 ;
$finish;
end //initial
adder #(.N_BITS_A(N_BITS_A),
.BIN_PT_A(BIN_PT_A),
.SIGNED_A(SIGNED_A),
.N_BITS_B(N_BITS_B),
.BIN_PT_B(BIN_PT_B),
.SIGNED_B(SIGNED_B),
.N_BITS_OUT(N_BITS_OUT),
.BIN_PT_OUT(BIN_PT_OUT)) a0 (a, b, sum);
initial begin
$monitor("%t, a = \t(%d,%d)b'%b\t a_padded = \t(%d,%d)b'%b\n%t, b = \t(%d,%d)b'%b\t b_padded = \t(%d,%d)b'%b\n%t, sum = \t\t\t\t\t(%d,%d)b'%b", $time, N_BITS_A, BIN_PT_A, a, N_BITS_OUT, BIN_PT_OUT, a0.add0.a_padded, $time, N_BITS_B, BIN_PT_B, b, N_BITS_OUT, BIN_PT_OUT, a0.add0.b_padded, $time, N_BITS_OUT, BIN_PT_OUT, sum);
end
endmodule //add_tb
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 212345, OFFSET = 3; struct BITree { long long a[MAXN]; void clear() { memset(a, 0, sizeof(a)); } int lowbit(int i) { return (i & -i); } long long sum(int i) { long long ret = 0; for (i += OFFSET; i > 0; i -= lowbit(i)) ret += a[i]; return ret; } void add(int i, long long d) { for (i += OFFSET; i < MAXN; i += lowbit(i)) a[i] += d; } } cnt, sum; int h[MAXN]; vector<pair<int, long long> > qq; vector<int> H; int find(int h) { return lower_bound(H.begin(), H.end(), h) - H.begin(); } int main() { int n, q; scanf( %d%d , &n, &q); for (int i = 0; i < int(n); i++) scanf( %d , h + i); qq.resize(q); H = vector<int>(h, h + n); for (int i = 0; i < int(q); i++) { int t; scanf( %d , &t); if (t == 1) { int p, x; scanf( %d%d , &p, &x); qq[i].first = p - 1; qq[i].second = x; H.push_back(x); } else { long long v; scanf( %I64d , &v); qq[i].first = -1; qq[i].second = v; } } sort(H.begin(), H.end()); H.resize(unique(H.begin(), H.end()) - H.begin()); cnt.clear(); sum.clear(); for (int i = 0; i < int(n); i++) { h[i] = find(h[i]); cnt.add(h[i], 1); sum.add(h[i], H[h[i]]); } for (int i = 0; i < int(q); i++) { if (~qq[i].first) { int j = qq[i].first; cnt.add(h[j], -1); sum.add(h[j], -H[h[j]]); h[j] = find(qq[i].second); cnt.add(h[j], 1); sum.add(h[j], H[h[j]]); } else { long long v = qq[i].second; int l = 0, r = H.size() - 1; while (l < r) { int m = (l + r + 1) / 2; int tot = cnt.sum(m); long long vol = sum.sum(m); if (H[m] * (long long)tot - vol < v) l = m; else r = m - 1; } int tot = cnt.sum(l); long long vol = sum.sum(l); printf( %.10f n , H[l] + (v - (H[l] * (long long)tot - vol)) / (double)tot); } } }
|
#include <bits/stdc++.h> using namespace std; const int mx = 1e2 + 10; const long long mod = 1e9 + 31; mt19937 mtrand(time(0)); int n, m; char s[2][1 << 12]; int mp[2][1 << 14]; int f[1 << 15], ans, pr[1 << 15]; int unfd(int x) { int r = x; while (r != f[r]) r = f[r]; int t; while (f[x] != r) t = f[x], f[x] = r, x = t; return r; } void unjoin(int x, int y) { int fx = unfd(x), fy = unfd(y); if (fx != fy) { --ans; f[fx] = fy; } } int main() { int num; cin >> n >> m; for (int i = 0; i < n; ++i) { int id = i & 1, nid = id ^ 1; scanf( %s , s[id]); num = 0; for (int j = 0; j < m / 4; ++j) { if (s[id][j] >= 0 && s[id][j] <= 9 ) num = s[id][j] - 0 ; else num = s[id][j] - A + 10; for (int k = 0; k < 4; ++k) { mp[id][j * 4 + k] = (num >> (3 - k)) & 1; if (mp[id][j * 4 + k] == 1) ++ans; } } for (int j = m; j < m * 2; ++j) f[j] = j; if (i > 0) { for (int j = 0; j < m; ++j) { if (mp[nid][j] & mp[id][j]) unjoin(j, m + j); } } for (int j = 1; j < m; ++j) { if (mp[id][j - 1] & mp[id][j]) unjoin(m + j - 1, m + j); } for (int j = m; j < m * 2; ++j) { pr[unfd(j)] = j - m; } for (int j = 0; j < m; ++j) { f[j] = pr[unfd(j + m)]; } } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_TB_V
`define SKY130_FD_SC_LP__OR4BB_TB_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__or4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_TB_V
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_data_check(CLK,RST,RDEN_DATA,RDEN_MSG,DATA,MSG,ERR0,ERR1,ERR2,ERR3,ERR_MSG);
input CLK,RST,RDEN_DATA,RDEN_MSG;
input [31:0] DATA;
input [39:0] MSG;
output reg [3:0] ERR0,ERR1,ERR2,ERR3,ERR_MSG;
reg [31:0] DATA_TEMP;
reg [7:0] MSG_TEMP;
always @ (posedge CLK)
begin
if(RST)
begin
ERR0 <= 0;
ERR1 <= 0;
ERR2 <= 0;
ERR3 <= 0;
ERR_MSG <= 0;
DATA_TEMP <= 0;
MSG_TEMP <= 0;
end
else if(RDEN_DATA)
begin
DATA_TEMP <= DATA;
MSG_TEMP <= MSG;
if(DATA_TEMP[7:0] + 1 != DATA[7:0] && DATA[7:0] != 0)
ERR0 <= ERR0 + 1;
if(DATA_TEMP[15:8] + 1 != DATA[15:8] && DATA[15:8] != 0)
ERR1 <= ERR1 + 1;
if(DATA_TEMP[23:16] + 1 != DATA[23:16] && DATA[23:16] != 0)
ERR2 <= ERR2 + 1;
if(DATA_TEMP[31:24] + 1 != DATA[31:24] && DATA[31:24] != 0)
ERR3 <= ERR3 + 1;
if(MSG[39:32] + 1 != MSG[31:24] || MSG[31:24] + 1 != MSG[23:16] || MSG[23:16] + 1 != MSG[15:8] || MSG[15:8] + 1 != MSG[7:0])
ERR_MSG <= ERR_MSG + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, s, k; string u; long long r[60], dp[2501][60]; signed main() { cin >> n >> s >> k; for (long long i = 0; i < n; ++i) cin >> r[i]; cin >> u; for (long long i = 0; i < n; ++i) for (long long j = 0; j < n; ++j) dp[i][j] = -1e18; --s; dp[0][s] = r[s]; for (long long i = 0; i < s; ++i) dp[s - i][i] = r[i]; for (long long i = s + 1; i < n; ++i) dp[i - s][i] = r[i]; for (long long i = 1; i <= 2500; ++i) for (long long j = 0; j < n; ++j) for (long long t = 1; t <= i; ++t) { if (j - t >= 0 && u[j - t] != u[j] && r[j - t] < r[j]) dp[i][j] = max(dp[i][j], dp[i - t][j - t] + r[j]); if (j + t < n && u[j + t] != u[j] && r[j + t] < r[j]) dp[i][j] = max(dp[i][j], dp[i - t][j + t] + r[j]); } for (long long i = 0; i < 2501; ++i) for (long long j = 0; j < n; ++j) if (dp[i][j] >= k) return cout << i, 0; cout << -1; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<long long> num(1, 0); vector<long long> arr(1, 0); for (int i = 1; i <= 1e5; i++) { num.push_back(num.back() + 1 + floor(log10(i))); arr.push_back(arr.back() + num.back()); } int q; cin >> q; while (q--) { int x; cin >> x; x--; x -= *--upper_bound(arr.begin(), arr.end(), x); int p = upper_bound(num.begin(), num.end(), x) - num.begin(); x -= num[p - 1]; x = floor(log10(p)) - x; while (x--) p /= 10; cout << p % 10 << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { string a; string b; cin >> a >> b; long long int len1 = a.length(); long long int len2 = b.length(); if (a.compare(b) == 0) { cout << -1 n ; } else { if (len1 > len2) cout << len1 << n ; else cout << len2 << n ; } }
|
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 10; using ll = long long; ll const INF = 0x3f3f3f3f3f3f3f3fll; struct edge { ll to, cost, id; edge(ll to = 0, ll cost = 0, ll id = 0) : to(to), cost(cost), id(id) {} }; vector<edge> e[N]; ll d[N]; vector<ll> p[N]; ll n, m, k; queue<ll> q; bool inq[N]; bool v[N]; bool can_change[N]; int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> k; for (ll i = 0, u, v, w; i < m; ++i) { cin >> u >> v >> w; e[u].push_back(edge(v, w, i + 1)); e[v].push_back(edge(u, w, i + 1)); } for (ll i = 0, s, y; i < k; ++i) { cin >> s >> y; e[1].push_back(edge(s, y, m + i + 1)); e[s].push_back(edge(1, y, m + i + 1)); } memset(d, 0x3f, sizeof(d)); memset(can_change, true, sizeof(can_change)); d[1] = 0; q.push(1); inq[1] = true; while (!q.empty()) { ll x = q.front(); q.pop(); inq[x] = false; for (auto &ed : e[x]) { ll y = ed.to, w = ed.cost, id = ed.id; if (d[y] > d[x] + w) { d[y] = d[x] + w; p[y].clear(); if (id > m) { can_change[y] = true; p[y].push_back(id); } else { can_change[y] = false; } if (!inq[y]) { inq[y] = true; q.push(y); } } else if (d[y] == d[x] + w) { if (id > m) { if (can_change[y]) p[y].push_back(id); } else { can_change[y] = false; p[y].clear(); } } } } for (ll i = 1; i <= n; ++i) if (!p[i].empty()) { bool skip = false; for (auto id : p[i]) { if (v[id - m]) { skip = true; break; } } if (!skip) v[p[i].front() - m] = true; } ll cnt = 0; for (ll i = 1; i <= k; ++i) if (!v[i]) ++cnt; cout << cnt << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int F[1024]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int n; cin >> n; char a; int b; for (int mask = 0; mask < (1 << 10); mask++) { F[mask] = mask; } for (int i = 0; i < n; i++) { cin >> a >> b; for (int mask = 0; mask < (1 << 10); mask++) { if (a == | ) F[mask] = (F[mask] | b); else if (a == ^ ) F[mask] = (F[mask] ^ b); else F[mask] = (F[mask] & b); } } for (int i = 0; i < (1 << 10); i++) { for (int j = 0; j < (1 << 10); j++) { set<int> S; for (int mask = 0; mask < (1 << 10); mask++) { int val = mask; val = (val | i); val = (val & j); S.insert((val ^ F[mask])); } if (S.size() == 1) { cout << 3 << n ; cout << | << i << n ; cout << & << j << n ; cout << ^ << (*S.begin()) << n ; return 0; } } } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:03 03/11/2015
// Design Name: Arithmetic_Logic_Unit
// Module Name: F:/ISE/work/cpu/cpu/ALU_Test.v
// Project Name: cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Arithmetic_Logic_Unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_Test;
// Inputs
reg [4:0] ctrl;
reg [15:0] data_in_A;
reg [15:0] data_in_B;
// Outputs
wire [15:0] data_out;
// Instantiate the Unit Under Test (UUT)
Arithmetic_Logic_Unit uut (
.data_out(data_out),
.ctrl(ctrl),
.data_in_A(data_in_A),
.data_in_B(data_in_B)
);
initial begin
// Initialize Inputs
ctrl = 0;
data_in_A = 2;
data_in_B = 8;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
ctrl = 1;
#50;
ctrl = 2;
#50;
ctrl = 3;
#50;
ctrl = 4;
#50;
ctrl = 5;
#50;
ctrl = 6;
#50;
ctrl = 7;
#50;
ctrl = 8;
#50;
ctrl = 9;
#50;
ctrl = 10;
#50;
ctrl = 11;
#50;
ctrl = 12;
#50;
ctrl = 13;
#50;
ctrl = 14;
#50;
ctrl = 15;
#50;
ctrl = 16;
#50;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1050; pair<int, int> a[MAX_N]; int cnt[MAX_N]; int sub[MAX_N]; map<int, int> ids; int inds[MAX_N]; int id = 0; int countplz(int f0, int f1) { memset((sub), 0, sizeof(sub)); ++sub[a[f0].second]; ++sub[a[f1].second]; int ans = 2; while (true) { int fnval = a[f0].first + a[f1].first; auto it = ids.find(fnval); if (it == ids.end()) { return ans; } int fnid = it->second; int fn = inds[fnid]; int rest = cnt[fnid] - sub[fnid]; if (rest <= 0) { return ans; } ++ans; sub[fnid]++; f0 = f1; f1 = fn; } } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { int x; cin >> x; if (ids.count(x) == 0) { ids[x] = id; inds[id] = i; ++id; } a[i] = make_pair(x, ids[x]); cnt[ids[x]]++; } int maxs = 2; if (ids.count(0) > 0) { maxs = max(maxs, cnt[ids[0]]); } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (i == j || (a[i].first == a[j].first && a[i].first == 0)) { continue; } maxs = max(maxs, countplz(i, j)); } } cout << maxs << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3 (
VPWR,
VGND,
Y ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_FUNCTIONAL_PP_V
|
//-----------------------------------------------------------------------------
// Title :Block level wrapper
//-----------------------------------------------------------------------------
// File : xgbaser_gt_same_quad_wrapper.v
//-----------------------------------------------------------------------------
// Description: This file is a wrapper for the 10GBASE-R core. It contains the
// 10GBASE-R core, the transceivers and some transceiver logic.
//-----------------------------------------------------------------------------
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ps / 1ps
`define DLY #1
module xgbaser_gt_same_quad_wrapper #
(
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "FALSE"
)
(
input gt_txclk322,
output gt_txusrclk,
output gt_txusrclk2,
output qplllock,
output qpllrefclklost,
output qplloutclk,
output qplloutrefclk,
output reg qplllock_txusrclk2,
output reg gttxreset_txusrclk2,
output reg txuserrdy,
output reg areset_clk_156_25_bufh,
output reg areset_clk_156_25,
output reg mmcm_locked_clk156,
output reset_counter_done,
output reg core_reset,
input gt0_tx_resetdone,
input gt1_tx_resetdone,
input gt2_tx_resetdone,
input gt3_tx_resetdone,
input tx_fault,
output gttxreset,
output gtrxreset,
input gt_refclk,
output clk156,
output dclk,
input areset
);
wire clk_156_25_bufh;
wire clk156_buf;
wire dclk_buf;
wire clkfbout;
wire mmcm_locked;
wire qpllreset;
reg [7:0] reset_counter = 8'd0;
reg [3:0] reset_pulse;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [7:0] tied_to_vcc_vec_i;
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 8'hff;
reg core_reset_tmp;
//- Synchronize resets
reg areset_clk_156_25_bufh_tmp;
reg areset_clk156_25_tmp;
reg qplllock_txusrclk2_tmp;
reg mmcm_locked_clk156_tmp;
reg gttxreset_txusrclk2_tmp;
MMCME2_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.500),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE_F (6.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (13),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (6.4),
.REF_JITTER1 (0.010))
clkgen_i
(
.CLKFBIN(clkfbout),
.CLKIN1(clk_156_25_bufh),
.PWRDWN(1'b0),
.RST(!qplllock),
.CLKFBOUT(clkfbout),
.CLKOUT0(clk156_buf),
.CLKOUT1(dclk_buf),
.LOCKED(mmcm_locked)
);
BUFG clk156_bufg_inst
(
.I (clk156_buf),
.O (clk156)
);
BUFG dclk_bufg_inst
(
.I (dclk_buf),
.O (dclk)
);
//synthesis attribute async_reg of core_reset_tmp is "true";
//synthesis attribute async_reg of core_reset is "true";
always @(posedge areset or posedge clk156)
begin
if(areset)
begin
core_reset_tmp <= 1'b1;
core_reset <= 1'b1;
end
else
begin
// Hold core in reset until everything else is ready...
core_reset_tmp <= (!(gt0_tx_resetdone) || !(gt1_tx_resetdone) || !(gt2_tx_resetdone) || !(gt3_tx_resetdone) || areset || tx_fault );
core_reset <= core_reset_tmp;
end
end
//synthesis attribute async_reg of qplllock_txusrclk2_tmp is "true";
//synthesis attribute async_reg of qplllock_txusrclk2 is "true";
always @(negedge qplllock or posedge gt_txusrclk2)
begin
if(!qplllock)
begin
qplllock_txusrclk2_tmp <= 1'b0;
qplllock_txusrclk2 <= 1'b0;
end
else
begin
qplllock_txusrclk2_tmp <= 1'b1;
qplllock_txusrclk2 <= qplllock_txusrclk2_tmp;
end
end
//synthesis attribute async_reg of mmcm_locked_clk156_tmp is "true";
//synthesis attribute async_reg of mmcm_locked_clk156 is "true";
always @(negedge mmcm_locked or posedge clk156)
begin
if(!mmcm_locked)
begin
mmcm_locked_clk156_tmp <= 1'b0;
mmcm_locked_clk156 <= 1'b0;
end
else
begin
mmcm_locked_clk156_tmp <= 1'b1;
mmcm_locked_clk156 <= mmcm_locked_clk156_tmp;
end
end
//synthesis attribute async_reg of gttxreset_txusrclk2_tmp is "true";
//synthesis attribute async_reg of gttxreset_txusrclk2 is "true";
always @(posedge gttxreset or posedge gt_txusrclk2)
begin
if(gttxreset)
begin
gttxreset_txusrclk2_tmp <= 1'b1;
gttxreset_txusrclk2 <= 1'b1;
end
else
begin
gttxreset_txusrclk2_tmp <= 1'b0;
gttxreset_txusrclk2 <= gttxreset_txusrclk2_tmp;
end
end
always @(posedge gt_txusrclk2 or posedge gttxreset_txusrclk2)
begin
if(gttxreset_txusrclk2)
txuserrdy <= 1'b0;
else
txuserrdy <= qplllock_txusrclk2;
end
//synthesis attribute async_reg of areset_clk_156_25_bufh_tmp is "true";
//synthesis attribute async_reg of areset_clk_156_25_bufh is "true";
always @(posedge areset or posedge clk_156_25_bufh)
begin
if(areset)
begin
areset_clk_156_25_bufh_tmp <= 1'b1;
areset_clk_156_25_bufh <= 1'b1;
end
else
begin
areset_clk_156_25_bufh_tmp <= 1'b0;
areset_clk_156_25_bufh <= areset_clk_156_25_bufh_tmp;
end
end
//synthesis attribute async_reg of areset_clk156_25_tmp is "true";
//synthesis attribute async_reg of areset_clk_156_25 is "true";
always @(posedge areset or posedge clk156)
begin
if(areset)
begin
areset_clk156_25_tmp <= 1'b1;
areset_clk_156_25 <= 1'b1;
end
else
begin
areset_clk156_25_tmp <= 1'b0;
areset_clk_156_25 <= areset_clk156_25_tmp;
end
end
BUFHCE bufhce_156_25_inst(
.CE (tied_to_vcc_i),
.I (gt_refclk),
.O (clk_156_25_bufh)
);
BUFG tx322clk_bufg_i
(
.I (gt_txclk322),
.O (gt_txusrclk)
);
assign gt_txusrclk2 = gt_txusrclk;
//***********************************************************************//
// //
//--------------------- Reset Logic -----------------------------------//
// //
//***********************************************************************//
// Hold off release the GT resets until 500ns after configuration.
// 128 ticks at 6.4ns period will be >> 500 ns.
always @(posedge clk_156_25_bufh or posedge areset_clk_156_25_bufh)
begin
if (areset_clk_156_25_bufh == 1'b1)
reset_counter <= 8'd0;
else if (!reset_counter[7])
reset_counter <= reset_counter + 1'b1;
else
reset_counter <= reset_counter;
end
always @(posedge clk_156_25_bufh)
begin
if(!reset_counter[7])
reset_pulse <= 4'b1110;
else
reset_pulse <= {1'b0, reset_pulse[3:1]};
end
assign reset_counter_done = reset_counter[7];
assign gttxreset = reset_pulse[0];
assign gtrxreset = reset_pulse[0];
assign qpllreset = reset_pulse[0];
// Instantiate the 10GBASER/KR GT Common block
ten_gig_eth_pcs_pma_ip_GT_Common_wrapper # (
.WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware
ten_gig_eth_pcs_pma_gt_common_block
(
.refclk (gt_refclk),
.qplllockdetclk (dclk),
.qpllreset (qpllreset),
.qplllock (qplllock),
.qpllrefclklost (qpllrefclklost),
.qplloutclk (qplloutclk),
.qplloutrefclk (qplloutrefclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long par[200000]; long long ran[200000]; long long cnt[200000]; void init(long long n) { for (long long i = 0; i <= n; i++) { par[i] = i; ran[i] = 0; } } long long finds(long long x) { if (par[x] == x) return x; else return par[x] = finds(par[x]); } void unite(long long x, long long y) { x = finds(x); y = finds(y); if (x == y) return; if (ran[x] < ran[y]) { par[x] = y; } else { par[y] = x; if (ran[x] == ran[y]) ran[x]++; } } long long quick_mod(long long a, long long n) { long long tmp = a; long long ans = 1; while (n) { if (n % 2 == 1) ans = (tmp * ans) % 1000000007; n /= 2; tmp = (tmp * tmp) % 1000000007; } return ans; } int main() { long long n, k; scanf( %lld%lld , &n, &k); init(n); for (long long i = 0; i < n - 1; i++) { long long a, b, c; scanf( %lld%lld%lld , &a, &b, &c); if (c == 0) unite(a, b); } for (long long i = 1; i <= n; i++) { finds(i); cnt[par[i]]++; } long long ans = quick_mod(n, k); for (long long i = 1; i <= n; i++) { ans = (ans + 1000000007 - quick_mod(cnt[i], k)) % 1000000007; } printf( %lld n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_SYMBOL_V
`define SKY130_FD_SC_MS__A222O_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_SYMBOL_V
`define SKY130_FD_SC_MS__DFSBP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_SYMBOL_V
`define SKY130_FD_SC_HDLL__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for udp_mux
*/
module test_udp_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT-1:0] s_udp_hdr_valid = 0;
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
reg [S_COUNT*16-1:0] s_eth_type = 0;
reg [S_COUNT*4-1:0] s_ip_version = 0;
reg [S_COUNT*4-1:0] s_ip_ihl = 0;
reg [S_COUNT*6-1:0] s_ip_dscp = 0;
reg [S_COUNT*2-1:0] s_ip_ecn = 0;
reg [S_COUNT*16-1:0] s_ip_length = 0;
reg [S_COUNT*16-1:0] s_ip_identification = 0;
reg [S_COUNT*3-1:0] s_ip_flags = 0;
reg [S_COUNT*13-1:0] s_ip_fragment_offset = 0;
reg [S_COUNT*8-1:0] s_ip_ttl = 0;
reg [S_COUNT*8-1:0] s_ip_protocol = 0;
reg [S_COUNT*16-1:0] s_ip_header_checksum = 0;
reg [S_COUNT*32-1:0] s_ip_source_ip = 0;
reg [S_COUNT*32-1:0] s_ip_dest_ip = 0;
reg [S_COUNT*16-1:0] s_udp_source_port = 0;
reg [S_COUNT*16-1:0] s_udp_dest_port = 0;
reg [S_COUNT*16-1:0] s_udp_length = 0;
reg [S_COUNT*16-1:0] s_udp_checksum = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_udp_payload_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_udp_payload_axis_tkeep = 0;
reg [S_COUNT-1:0] s_udp_payload_axis_tvalid = 0;
reg [S_COUNT-1:0] s_udp_payload_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_udp_payload_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_udp_payload_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_udp_payload_axis_tuser = 0;
reg m_udp_hdr_ready = 0;
reg m_udp_payload_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire [S_COUNT-1:0] s_udp_hdr_ready;
wire [S_COUNT-1:0] s_udp_payload_axis_tready;
wire m_udp_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [15:0] m_udp_source_port;
wire [15:0] m_udp_dest_port;
wire [15:0] m_udp_length;
wire [15:0] m_udp_checksum;
wire [DATA_WIDTH-1:0] m_udp_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep;
wire m_udp_payload_axis_tvalid;
wire m_udp_payload_axis_tlast;
wire [ID_WIDTH-1:0] m_udp_payload_axis_tid;
wire [DEST_WIDTH-1:0] m_udp_payload_axis_tdest;
wire [USER_WIDTH-1:0] m_udp_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_udp_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_version,
s_ip_ihl,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_header_checksum,
s_ip_source_ip,
s_ip_dest_ip,
s_udp_source_port,
s_udp_dest_port,
s_udp_length,
s_udp_checksum,
s_udp_payload_axis_tdata,
s_udp_payload_axis_tkeep,
s_udp_payload_axis_tvalid,
s_udp_payload_axis_tlast,
s_udp_payload_axis_tid,
s_udp_payload_axis_tdest,
s_udp_payload_axis_tuser,
m_udp_hdr_ready,
m_udp_payload_axis_tready,
enable,
select
);
$to_myhdl(
s_udp_hdr_ready,
s_udp_payload_axis_tready,
m_udp_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_udp_source_port,
m_udp_dest_port,
m_udp_length,
m_udp_checksum,
m_udp_payload_axis_tdata,
m_udp_payload_axis_tkeep,
m_udp_payload_axis_tvalid,
m_udp_payload_axis_tlast,
m_udp_payload_axis_tid,
m_udp_payload_axis_tdest,
m_udp_payload_axis_tuser
);
// dump file
$dumpfile("test_udp_mux_4.lxt");
$dumpvars(0, test_udp_mux_4);
end
udp_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// UDP frame inputs
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tid(s_udp_payload_axis_tid),
.s_udp_payload_axis_tdest(s_udp_payload_axis_tdest),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tid(m_udp_payload_axis_tid),
.m_udp_payload_axis_tdest(m_udp_payload_axis_tdest),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
/// date:2016/3/5
/// engineer :ZhaiShaoMin 3/6 am: 10:57 done!
/// module function :because accesses come from three different sources:cpu,IN_req/rep(at one time ,only req or rep),mem
/// so here we need a arbiter to determine who can access data cache finally.
module arbiter_for_dcache(//input
clk,
rst,
dcache_done_access,
v_dc_download,
dc_download_flits,
v_cpu,
cpu_access_flits,
v_m_d_areg,
m_d_areg_flits,
//output
flits_dc,
v_flits_dc,
re_dc_download_flits,
re_cpu_access_flits,
re_m_d_areg_flits,
cpu_done_access,
dc_download_done_access,
m_d_areg_done_access
);
//input
input clk;
input rst;
input dcache_done_access;
input v_dc_download;
input [143:0] dc_download_flits;
input v_cpu;
input [67:0] cpu_access_flits;
input v_m_d_areg;
input [143:0] m_d_areg_flits;
//output
output [143:0] flits_dc;
output v_flits_dc;
output re_dc_download_flits;
output re_cpu_access_flits;
output re_m_d_areg_flits;
output cpu_done_access;
output dc_download_done_access;
output m_d_areg_done_access;
// parameter for fsm state
parameter idle=4'b0001;
parameter cpu_busy=4'b0010;
parameter dc_busy=4'b0100;
parameter mem_busy=4'b1000;
reg [2:0] select;
reg update_priority_3;
reg update_priority_2;
reg [3:0] nstate;
reg [3:0] state;
reg re_cpu_access_flits;
reg re_dc_download_flits;
reg re_m_d_areg_flits;
reg cpu_done_access;
reg dc_download_done_access;
reg m_d_areg_done_access;
reg [143:0] flits_dc;
reg v_flits_dc;
wire [2:0] v_vector;
reg [2:0] priority_3;
reg [1:0] priority_2;
assign v_vector={v_dc_download,v_cpu,v_m_d_areg};
always@(*)
begin
select=3'b000;
update_priority_3=1'b0;
update_priority_2=1'b0;
nstate=state;
re_cpu_access_flits=1'b0;
re_dc_download_flits=1'b0;
re_m_d_areg_flits=1'b0;
cpu_done_access=1'b0;
dc_download_done_access=1'b0;
m_d_areg_done_access=1'b0;
flits_dc=144'h0000;
v_flits_dc=1'b0;
case(state)
idle:
begin
if(v_vector==3'b111)
begin
select=priority_3;
update_priority_3=1'b1;
end
else if(v_vector==3'b011)
begin
select={1'b0,priority_2};
update_priority_2=1'b1;
end
else if(v_vector==3'b101)
begin
select={priority_2[0],1'b0,priority_2[1]};
update_priority_2=1'b1;
end
else if(v_vector==3'b110)
begin
select={priority_2,1'b0};
update_priority_2=1'b1;
end
else if(v_vector==3'b001||v_vector==3'b010||v_vector==3'b100)
begin
select=v_vector;
end
if(select==3'b001)
nstate=mem_busy;
else if(select==3'b010)
nstate=dc_busy;
else if(select==3'b100)
nstate=cpu_busy;
end
cpu_busy:
begin
re_cpu_access_flits=1'b1;
flits_dc={cpu_access_flits,76'h0000};
v_flits_dc=1'b1;
if(dcache_done_access)
begin
nstate=idle;
cpu_done_access=1'b1;
end
end
dc_busy:
begin
re_dc_download_flits=1'b1;
flits_dc=dc_download_flits;
v_flits_dc=1'b1;
if(dcache_done_access)
begin
nstate=idle;
dc_download_done_access=1'b1;
end
end
mem_busy:
begin
re_m_d_areg_flits=1'b1;
flits_dc=m_d_areg_flits;
v_flits_dc=1'b1;
if(dcache_done_access)
begin
nstate=idle;
m_d_areg_done_access=1'b1;
end
end
endcase
end
/// fsm state
always@(posedge clk)
begin
if(rst)
state<=4'b0001;
else
state<=nstate;
end
/// priority state
always@(posedge clk)
begin
if(rst)
priority_3<=3'b001;
else if(update_priority_3)
priority_3<={priority_3[1:0],priority_3[2]};
end
always@(posedge clk)
begin
if(rst)
priority_2<=2'b01;
else if(update_priority_2)
priority_2<={priority_2[0],priority_2[1]};
end
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 3;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_if.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_if_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 42);
`assert(result_empty, 0);
`assert(trap, `ENDED);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000030; int num[MAXN]; int a[MAXN], b[MAXN]; int dex[MAXN]; int res[MAXN]; int bsch(int le, int ri, int key) { int l = le, r = ri; while (l <= r) { int m = (l + r) / 2; if (res[m] == key) return m; else if (res[m] > key) r = m - 1; else l = m + 1; } return l; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); dex[b[i]] = i; } for (int i = 1; i <= n; i++) { num[i] = dex[a[i]]; } for (int i = 1; i <= n / 2; i++) { swap(num[i], num[n - i + 1]); } for (int i = 1; i <= n; i++) { res[i] = 1 << 30; } int maxv = 1; res[1] = num[1]; for (int i = 2; i <= n; i++) { int s = bsch(1, n, num[i]); res[s] = num[i]; if (maxv < s) maxv = s; } printf( %d n , maxv); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_1_V
`define SKY130_FD_SC_LS__NOR4B_1_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_1_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const int base = 31337; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const int logo = 20; const int off = 1 << logo; const int treesiz = off << 1; int n; int niz[maxn]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , niz + i); niz[i] *= 2; } int sum = 0; for (int i = 0; i < n; i++) sum += niz[i]; if (sum >= 9 * n) printf( 0 ); else { sort(niz, niz + n); for (int i = 0; i < n; i++) { sum += 10 - niz[i]; if (sum >= 9 * n) { printf( %d n , i + 1); break; } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave_b2b
* this module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b
#(parameter start_cnt = 1)
(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
reg [7:0] first_byte;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1] == 2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1] == 2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
* read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge) begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
if((bytecnt == 'h0 && byte_data_received == start_cnt + 1'b1) || first_byte == start_cnt + 1'b1)
received_memory <= (byte_data_received == bytecnt + start_cnt + 1'b1) ? (received_memory + 1'b1) : received_memory;
else
received_memory <= (byte_data_received == bytecnt + start_cnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
first_byte <= 'h0;
else if(bytecnt == 'h0 && byte_data_received == start_cnt + 1'b1)
first_byte <= byte_data_received;
else
first_byte <= first_byte;
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= start_cnt;
else begin
if((first_byte == start_cnt + 1'b1) && (!recived_status))
cnt<= start_cnt + 1'b1;
else if(byte_received && recived_status)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct creature { long long hp, dmg; long long div; bool operator<(const creature& rhs) const { return div > rhs.div; } }; int n, a, b; creature in[200050]; long long ans = 0; int it, use; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> a >> b; for (int i = 0; i < n; ++i) { cin >> in[i].hp >> in[i].dmg; in[i].div = in[i].hp - in[i].dmg; } sort(in, in + n); use = b; for (int i = 0; i < n; ++i) { if (use && in[i].hp > in[i].dmg) { in[i].dmg = in[i].hp; --use; } ans += in[i].dmg; } it = b - use; int icur = it - 1; in[n] = {0, 0, 0}; long long dx = 0; if (b && a) for (int i = 0; i < n; ++i) { long long tmp = (in[i].hp << a) - in[i].dmg; if (use) dx = dx > tmp ? dx : tmp; else if (i < it) dx = tmp > dx ? tmp : dx; else dx = (tmp - in[icur].div > dx) ? tmp - in[icur].div : dx; } cout << ans + dx; return 0; }
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
//
`define bsg_mem_1rw_sync_macro(words,bits,lgEls,newBits,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc180_1rw_lg``lgEls``_w``newBits``_m``mux``_all mem \
(.Q(data_o) \
,.CLK(clk_i) \
,.CEN(~v_i) \
,.WEN(~w_i) \
,.A(addr_i) \
,.D(data_i) \
// 1=tristate \
,.OEN(1'b0) \
); \
end
`define bsg_mem_1rw_sync_macro_rf(words,bits,lgEls,newBits,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
wire [newBits-1:0] tmp_lo,tmp_li; \
assign data_o = tmp_lo[bits-1:0]; \
assign tmp_li = newBits ' (data_i); \
\
tsmc180_1rf_lg``lgEls``_w``newBits``_m``mux``_all mem \
( \
.Q(tmp_lo) \
,.CLK(clk_i) \
,.CEN(~v_i) \
,.WEN(~w_i) \
,.A(addr_i) \
,.D(tmp_li) \
); \
end
module bsg_mem_1rw_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=$clog2(els_p)
// whether to substitute a 1r1w
, parameter substitute_1r1w_p=1)
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
`bsg_mem_1rw_sync_macro(2048,32,11,32,8) else
`bsg_mem_1rw_sync_macro(1024,32,10,32,8) else
`bsg_mem_1rw_sync_macro(256,128,8,128,4) else
`bsg_mem_1rw_sync_macro_rf(128,74,7,74,2) else
`bsg_mem_1rw_sync_macro_rf(128,73,7,74,2) else
`bsg_mem_1rw_sync_macro_rf(128,72,7,72,2) else
`bsg_mem_1rw_sync_macro_rf(128,71,7,72,2) else
`bsg_mem_1rw_sync_macro_rf(128,70,7,70,2) else
`bsg_mem_1rw_sync_macro_rf(128,69,7,70,2) else
`bsg_mem_1rw_sync_macro_rf(128,68,7,68,2) else
`bsg_mem_1rw_sync_macro_rf(128,67,7,68,2) else
`bsg_mem_1rw_sync_macro_rf(128,66,7,66,2) else
`bsg_mem_1rw_sync_macro_rf(128,65,7,66,2) else
`bsg_mem_1rw_sync_macro_rf(128,64,7,64,2) else
`bsg_mem_1rw_sync_macro_rf(128,63,7,64,2) else
`bsg_mem_1rw_sync_macro_rf(128,62,7,62,2) else
`bsg_mem_1rw_sync_macro_rf(128,61,7,62,2) else
begin : z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1rw synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(0)
) mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (v_i & w_i)
,.w_addr_i (addr_i)
,.w_data_i (data_i)
,.r_addr_i (addr_i)
,.r_v_i (v_i & ~w_i)
,.r_data_o (data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i)
data_o <= data_lo;
end // block: subst
else
begin: notmacro
bsg_mem_1rw_sync_synth
# (.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
end // block: notmacro
end // block: z
// synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync)
|
module peripheral_SD(clk , reset , d_in , cs , addr , rd , wr, d_out, sclk, mosi, miso, ss );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
input reset;
output sclk;
input miso;
output mosi;
output ss;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and write registers
reg [15:0] datain=0;//---mult_32 input registers
reg enable=0;
wire [15:0] dataout; //mult_32 output Regs
wire done;
//------------------------------------ regs and wires-------------------------------
spi driver ( .clk(clk), .reset(reset), .datain(datain), .en(enable), .dataout(dataout), .done(done), .sclk(sclk), .mosi(mosi), .miso(miso), .ss(ss) );
always @(*) begin//------address_decoder------------------------------
case (addr)
4'h0:begin s = (cs && wr) ? 4'b0001 : 6'b0000 ;end //datain
4'h2:begin s = (cs && wr) ? 4'b0010 : 6'b0000 ;end //en
4'h4:begin s = (cs && rd) ? 4'b0100 : 6'b0000 ;end //done
4'h6:begin s = (cs && rd) ? 4'b1000 : 6'b0000 ;end //dataout
default:begin s = 6'b000000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin//-------------------- escritura de registros
datain = (s[0]) ? d_in : datain; //Write Registers
enable = (s[1]) ? d_in[0] : enable; //Write Registers
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_2 : multiplexa salidas del periferico
case (s)
4'b0100: d_out[0] = done ;
3'b1000: d_out = dataout[15:0] ;
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_2
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; int n, m, k, second; int a[500005]; int b[500005]; int cnt[500005]; int rbd[500005]; int stat[500005]; int app[500005]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> m >> k >> n >> second; for (int i = (1); i <= (signed)(m); i++) { cin >> a[i]; } for (int i = (1); i <= (signed)(second); i++) { int x; cin >> x; b[x]++; } int rb = 0; int sat = 0; for (int i = (1); i <= (signed)(m); i++) { while (rb <= m && sat < second) { rb++; int c = a[rb]; if (b[c] > cnt[c]) { sat++; } cnt[c]++; } rbd[i] = max(rb, i + k - 1); int c = a[i]; if (b[c] >= cnt[c]) sat--; cnt[c]--; } int dc = 0; for (int i = (1); i <= (signed)(m); i++) { if (rbd[i] == m + 1) break; int bef = (i - 1) / k; int aft = (m - rbd[i]) / k; if (bef + aft + 1 >= n) { for (int j = (i); j <= (signed)(rbd[i]); j++) { int c = a[j]; if (b[c] > app[c]) { stat[j] = 1; } app[c]++; } int added = second; for (int j = (i); j <= (signed)(rbd[i]); j++) { if (added < k && stat[j] == 0) { added++; stat[j] = 1; } else if (added == k && stat[j] == 0) { stat[j] = -1; dc++; } } int td = (i - 1) % k; if (bef >= n) { td += (bef + 1 - n) * k; } for (int i = (1); i <= (signed)(td); i++) { stat[i] = -1; dc++; } cout << dc << n ; for (int i = (1); i <= (signed)(m); i++) { if (stat[i] == -1) cout << i << ; } return 0; } } cout << -1 n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, qc; int a[100005]; int freq[100005], ord[100005], inv[100005]; int cnt[100005] = {}, small[100005] = {}; int from[100005], to[100005]; const int ROOT = 320; const int BIG_COUNT = 100; const int SMALL = (100000 + BIG_COUNT - 1) / BIG_COUNT; inline bool cmp(const int &lhs, const int &rhs) { return freq[lhs] > freq[rhs]; } inline bool qcmp(const int &lhs, const int &rhs) { if (from[lhs] / ROOT != from[rhs] / ROOT) return from[lhs] < from[rhs]; return to[lhs] < to[rhs]; } int l = 0, r = -1; void extendRight() { ++r; if (a[r] >= BIG_COUNT) { --small[cnt[a[r]]]; ++small[cnt[a[r]] + 1]; } ++cnt[a[r]]; } void extendLeft() { --l; if (a[l] >= BIG_COUNT) { --small[cnt[a[l]]]; ++small[cnt[a[l]] + 1]; } ++cnt[a[l]]; } void shrinkRight() { if (a[r] >= BIG_COUNT) { --small[cnt[a[r]]]; ++small[cnt[a[r]] - 1]; } --cnt[a[r]]; --r; } void shrinkLeft() { if (a[l] >= BIG_COUNT) { --small[cnt[a[l]]]; ++small[cnt[a[l]] - 1]; } --cnt[a[l]]; ++l; } priority_queue<int, vector<int>, greater<int> > q; int c[SMALL + 1]; int res[100005]; int main() { scanf( %d , &n); for (int i = 0; i < (int)(n); ++i) scanf( %d , a + i), --a[i]; for (int i = 0; i < (int)(n); ++i) ++freq[a[i]]; for (int i = 0; i < (int)(100000); ++i) ord[i] = i; sort(ord, ord + 100000, cmp); for (int i = 0; i < (int)(100000); ++i) inv[ord[i]] = i; for (int i = 0; i < (int)(n); ++i) a[i] = inv[a[i]]; scanf( %d , &qc); for (int i = 0; i < (int)(qc); ++i) scanf( %d%d , from + i, to + i), --from[i], --to[i]; for (int i = 0; i < (int)(qc); ++i) ord[i] = i; sort(ord, ord + qc, qcmp); for (int ii = 0; ii < (int)(qc); ++ii) { int i = ord[ii]; while (r < to[i]) extendRight(); while (l > from[i]) extendLeft(); while (r > to[i]) shrinkRight(); while (l < from[i]) shrinkLeft(); for (int j = 1; j <= SMALL; ++j) { c[j] = small[j]; } int ans = 0; int rem = -1; for (int i = 0; i < (int)(BIG_COUNT); ++i) if (cnt[i] <= SMALL) { ++c[cnt[i]]; } else { q.push(cnt[i]); } for (int j = 1; j <= SMALL; ++j) if (c[j]) { if (rem != -1) { --c[j]; ans += j + rem; if (j + rem <= SMALL) { ++c[j + rem]; } else { q.push(j + rem); } } ans += j * (c[j] & ~1); int nj = j << 1; if (nj <= SMALL) { c[nj] += c[j] >> 1; } else { for (int times = 0; times < (int)(c[j] >> 1); ++times) { q.push(nj); } } if (c[j] & 1) { rem = j; } else { rem = -1; } } if (rem != -1) { q.push(rem); } while ((int)q.size() > 1) { int a = q.top(); q.pop(); int b = q.top(); q.pop(); ans += a + b; q.push(a + b); } assert(!q.empty()); q.pop(); res[i] = ans; } for (int i = 0; i < (int)(qc); ++i) { printf( %d n , res[i]); } return 0; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.